Patent GB-1363594-A (GB)
Title: Data transmission
IPC: H04J3/12
Filed: 1972-04-21
Abstract: 1363594 Digital transmission INTERNATIONAL BUSINESS MACHINES CORP 21 April 1972 [30 June 1971] 18556/72 Heading H4P  In a system whereby a stream of bits for example from a digitized analogue signal are transmitted continuously, selected information or control characters may substitute, when required, for a corresponding portion of the stream, which characters are recognized on reception.  In the embodiment described, 'an analogue signal is coded by a delta modulator into a series of +ve and - ve pulses, represented by l's and 0's, which series are reformed at the receiver into a multi-level signal and compensation is made for the numerical weight of the portion if different from the character replacing it. Where the stream produces patterns identical to that of characters, the patterns are altered to eliminate identity. Information bits are coded into 8-bit characters W1, W2 corresponding to 0's, l's, each of zero weight this is not essential but simplifies weight correction circuitry.  Fig. 2 (not shown), line (D), illustrates a reformed wave at a receiver with and without substitution of a character W1 and the correction necessary to bring receiver output to the same condition as if the character had not been substituted. This is performed by sensing the weight of bits removed and determining amplitude correction needed after termination of the substituted character. In the example given in Fig. 2 a weight correction of 4 units is effected by reversing the polarity of pulses (T9, T20) lines (B), (C). Where any 8-bit groups of the stream resembles a word W1, W2, one bit of the group is altered by inverting it and this is corrected by also inverting the next bit of the same polarity. Shift registers 70, 72 receive identical inputs from a delta modulator (20) (Fig. 4A, not shown) and contents are shifted by clock pulses S. Register 70 is normally operative through gate 74 to transmission line 42. At any determined time a W1 (W2) character may be inserted hence wire 80 (82) is pulsed, the former setting flip-flop 84 (144) and through AND 86 (146) the next R pulse sets flip-flop 88 (148). Gate 74 is disabled and the counter 96 controls entry of appropriate 8-bit word W1, W2 after which gate 74 is re-enabled. During the time that W1 (W2) is being transmitted, unused pulses from register 72 are fed to an adder 164 which provides a signal proportional to the algebraic sum which is passed over wire 46 to multiplier (26), Fig. 4A (not shown), thus causing succeeding bits to be inverted, if necessary, to restore the weight to zero relative to the original signal. Each stage of the register 70 has 0, 1 outputs to AND's 170, 172 which give an output if a series corresponding to W1, W2 respectively from the delta modulator are issued. If so, one of wires 178, 180 are energized to invert a bit in stage 1, but any other stage may be selected, e.g. stage 8. This causes a weight correction signal over line 64, 66 to the delta modulator. Should an inserted word W1, W2 occur when register 70 fortuitously contains an identical sequence the weight correcting circuitry is disabled. In such circumstance although the bit in stage 1 may be inverted this will have no effect due to the weight circuitry being disabled.