Patent GB-1440510-A (GB)
Title: Realtime control arrangement for simulation device
IPC: G06F15/16
Filed: 1973-11-22
Abstract: 1440510 Data processing systems INTERNATIONAL STANDARD ELECTRIC CORP 22 Nov 1973 [30 Nov 1972] 54133/73 Heading G4A The system, which includes two or more operational computers operating on a loadsharing basis, has a simulation computer designed to simulate the peripheral units with which the computers communicate. When a simulated event occurs which requires an operational computer to stop (e.g. an i/o event), timing circuitry is enabled to introduce delays in the simulation equivalent to the delays which would occur if the peripherals were not simulated but real. In Fig. 1b two operational computers 1A, 1B coupled by load-sharing unit 2 are coupled via a store assembly 13 to simulation computer 6 which has a peripheral unit 5c, e.g. a teleprinter. The arrangement is such that computer 6 cannot operate when either operational computer operates. When one computer stops the other also is stopped. However since the second computer can stop only at the end of a sequence the interval between the stopping of the computers varies from stop to stop. Control unit 11 takes account of such variation. The control unit 11 has various counters which are fed by a common clock (8, Fig. 3, not shown). One such is a real-time counter (9), and after each unit of real time the computers 1A, 1B are turned off, allowing computer 6 to communicate with its peripheral 5c. At the end of a real time unit a signal indicating that the resulting stop is a real time unit stop is stored at 13, and a stop signal is sent to 1A and 1B. The first computer to stop stops the real time counter (9) and starts a so called "shift" counter (10). When the other computer stops the shift counter (10) is stopped, its count representing the interval between the stopping of the two computers. Simulation computer 6 takes note of the nature of the stop signal stored at 13 and reads from the store the data that computers 1A, 1B wish to send to the simulated peripherals or performs an i/o operation with its peripheral 5c. Computer 6 then sends a start order which restarts the real-time counter (9) and the first computer that stopped, and which causes the shift counter (10) to be counted down. When the shift counter reaches zero the other computer is started, the interval between the starting of the computers thus being equal to the interval between the stopping of them. When a computer, e.g. 1A, issues an i/o command the real-time counter (9) is stopped and the nature of the stop, the address of the relevant peripheral, and the data, are stored at 13. As before, the shift counter (10) measures the interval until computer 1B stops. The simulation computer reads the store 13. After a certain time, corresponding to the peripheral response time and defined by decrementing a further counter (14A) which is loaded by computer 6, a response is sent to the relevant computer, here 1A. Computer 6 then sends a start order to unit 11 as before to start computers 1A and 1B in sequence with the correct interval between the starts. Should both computers 1A and 1B issue an i/o command approximately simultaneously the simulation computer 6 and control unit 11 operate to send responses to the computers and to restart them after periods which make due allowance for the response times of the relevant simulated peripherals and the interval between the i/o commands. The simulation computer and control unit also operate to provide responses and restart the computers 1A, 1B if either issues an i/o command when the other is awaiting a response.