Patent GB-858321-A (GB)
Title: Improvements in or relating to devices for multiplying numbers
IPC: G11C19/04
Filed: 1958-12-24
Abstract: 858,321. Electronic multiplying apparatus. BLIKMAN & SANTORIUS N.V. Dec. 24, 1958 [Dec. 31, 1957; April 3, 1958], No. 41675/58. Class 106 (1). An electronic decimal multiplier suitable for attachment to a typewriter comprises two matrices of magnetic cores for registering the multiplier and multiplicand, each matrix consisting of a column for each decimal denomination and rows corresponding to decimal digits, and multiplication is effected by reading out the multiplier digits one at a time in a way which produces for each digit a number of pulses equal to the digit registered, and each pulse reads out the multiplicand from its register into demoninations of an accumulator appropriate to the multiplier digit. Figs. 1 and 2 show a multiplicand register, and a multiplier register and accumulator, respectively, with associated write, read and gating means. The registers are similar, each having four windings per core connected in series row- and columnwise; a read-winding (row windings AL with associated flip-flops A1-A9) and three writewindings (rows CL, TL and columns DL) of which two windings must be energized to change the state of a core. Keys S2 and S3 (or S4 and S5) enter the multiplier (or multiplicand) digits one-by-one starting in the righthand column by setting one of the triggers C1-C9 (if a decimal digit 1-9 is to be registered) simultaneously with the appropriate column or decimal denomination trigger D1- D9. Each D trigger supplies a negative and then a positive pulse, the latter co-acting with a positive pulse from a C trigger to set a core where appropriate. The switches S2 and S4 may be operated by the typewriter carriage movement, and S3 and S5 by the decimal digit keys. Energization of any trigger D also operates a trigger T which provides a negative pulse coinciding with that of the D trigger, and operation of any trigger subsequently operates all triggers to the left, but this does not affect entry of subsequent digits since entry is from right to left. When multiplier and multiplicand have both been registered, switch S8 is closed and triggers D1-D9 of Fig. 2 operated in turn. Each D trigger in combination with the T trigger resets the core in that denomination (if a digit 1-9 has been registered) and the output pulse operates one of the A1-A9 triggers which successively operates the A triggers of lower order, each of which provides a pulse on line W so that a number of pulses equal to the digit registered is sent out, before the next D trigger is operated to read out the next higher denomination. Each pulse on line W reads out the multiplicand in like manner, except that diode connections between the A and C triggers re-enter the the multiplicand digits after read-out; the output pulses on line Z are supplied to the decimal denominations R1-R10 of an accumulator through gates P1-P10 controlled by signals from triggers D1-D9 of the multiplier matrix, which open the appropriate gate for entry of the first multiplicand digit, delay circuits then opening higher order gates in turn. A double-intensity re-setting pulse through S9 clears the multiplicand register after multiplication. Fig. 4 (not shown), illustrates a modified multiplicand register without the A and T triggers and their windings and in which each multiplier pulse received on line W generates ten pulses which shift the " 1 " condition in each denomination cyclically upwards through all " digit value " cores back to its original core, the switches of the 0 value core opening a gate to pass a number of pulses equal to the multiplicand digit to a commutator which directs them to appropriate denominations of an accumulator in accordance with the number of pulses that have been received from the multiplier T trigger (i.e. in accordance with the denomination of the multiplier digit pulses).