Patent GB-1121354-A (GB)
Title: Pulse generator
IPC: H03K3/33
Filed: 1966-03-15
Abstract: 1,121,354. Pulse generators. SCM CORP. 15 March, 1966 [15 March, 1965], No. 11243/66. Heading H3T. A circuit for generating a pulse having rise and fall times of less than Ins, followed by a similar pulse of adjustable spacing, uses chargestorage diodes for sharpening the edges and variable delay circuits for controlling the duration and spacing of the pulses. In Fig. 1 pulses are produced at 101-103 and applied to two separate channels which produce the two pulses of the pair respectively, the spacing being controlled by a variable delay circuit D2. In each channel the pulses are again split into two paths each comprising a delay circuit D3/D4, blocking oscillator 109/111, amplifier 115/119, and charge-storage diode 117/121. The first path produces the leading edge of the output pulse while the second path inverts the polarity at 119 and introduces a delay relative to the first, to provide the trailing edge of the output pulse. Adjustment of the delay circuit D4 thus controls the duration of the output pulse. The two step waveforms are combined in a diode gate 123 to form a complete pulse, and the second pulse of the pair is added in a further diode gate 105. Delay circuits (Fig. 5).-Initially transistors T1 and T2 are cut off as diodes 501 and 505 are both conducting. An input step voltage at 517 passes current through inductor 519 to diode 501 which is of the charge-storage type; when the stored carriers have been driven out the diode is cut off abruptly and the base voltage of T1 rises, turning it on and reversely biasing diode 505. Transistor T2 then conducts providing an output at 521. With variable resistor 511 at its maximum the delay time is a minimum and such a circuit is used for D1, D3 and D5 of Fig. 1. Reduction of 511 increases the delay time, and a circuit with variable 511 is used for D2, D4 and D6 of Fig. 1. Pulse shaping circuits (Fig. 6).-A pulse from D3 of Fig. 1 turns on blocking-oscillator transistor T3 and a pulse from D4 turns on another blocking oscillator T4 which is connected to T3 via auxiliary winding 613 and transistor T 5  to shut down T3 after a time of 0-100ns depending on the setting of D4. The output of T3 feeds parallel amplifiers T6, T7 emitter-coupled to normally conducting chargestorage diodes 617, 618. When the stored carriers in diode 617 are driven out this diode cuts off in 2ns and the potential at B rises. The amplifiers T6, T7 now pass current into the other charge-storage diode 618, which has a shorter storage time and cuts off in 0À4ns, raising the potential of C to a value where the diodes 627 and 629 in the gates 123 and 105 conduct, so that current from T6 and T7 flows into the load 107. The other blocking oscillator T4 feeds similar parallel amplifiers T8, T9 collector coupled to give a pulse of opposite polarity to further charge-storage diodes 634, 635 connected in opposite polarity to 617, 618. When the diode 635 is cut off the potential at G falls, turning on the gating diode 639 and diverting the current from T6, T7 away from the load. When the pulses at 125 and 127 cease, the charge-storage diodes conduct again and the circuit is ready to receive another pulse.