Patent GB-1394736-A (GB)
Title: Rectifier bridge circuits
IPC: G05F1/44
Filed: 1972-05-12
Abstract: 1394736 Converting HEWLETT-PACKARD CO 12 May 1972 [18 May 1971] 22384/72 Heading H2F [Also in Divisions G3 and H3] In a rectifying system comprising a bridge of two controlled rectifiers D1, D2 and two diodes D3, D4, the output of the bridge is shunted by a series circuit comprising at least one inductor L1 and at least one capacitor C3 and a ripple filter L3, C5 connected to a tap on inductor L1 in such a way that the main ripple component is preferably four times the supply frequency. This allows a smaller filter L3, C5 to be employed. The circuit as shown is suitable for operation on 115 V. A.C. input, the thyristors D1, D2 acting with capacitors C3, C4 as voltage doublers. If the jumpers are removed, the circuit acts as a conventional full-wave bridge and is suitable for 230 V. A.C. input. Trains of pulses are supplied to T1 So as to adjust the conduction angle of thyristors D1, D2 and so adjust or control the output voltage. Over-voltage protection.-The output voltage is monitored by Zener diodes D6, D7 and if excessive, turns on a crowbar thyristor D5. This thyristor is also turned on by a pulse fed via T2 in the event of excess output current. D.C.-D.C. converting.-The output from the rectifying system shown in Fig. 2 is fed to a pair of inverters (Fig. 3) each comprising a bridge of transistors with inverse diodes. The inverters are driven by 400 Hz clock pulses from a source 15 in quadrature and provides substantially square wave outputs so that a two-phase diode rectifying system (Fig. 6, not shown), with very little smoothing, can be connected to their output transformers T4, T4<SP>1</SP>. The transistors in each bridge inverter are driven by a further bridge of four transistors forming two "totem pole" arrangements. Controlling thyristor rectifiers.-The A.C. supply is fed via a transformer T5 (Figs. 2 and 8) to a full-wave rectifier 66, the unsmoothed output of which is arranged to charge capacitor C7 via transistor Q13 so as to produce a ramp waveform. The capacitor C7 is discharged by Q15 just after the end of each half cycle by means of a sloping pulse (Fig. 11, not shown) derived by transistors Q17 ... Q20. The slope of the ramp is a function of the A.C. input and also of the current in Q14 which is determined by an I L  input proportional to the flux in the  output transformers in a pair of inverters (Fig. 4, not shown) supplied by the rectifying system of Fig. 2. The ramp is D.C. restored by FET Q16 and fed to a differential amplifier Q21, Q22 where it is compared with a voltage from amplifier 68 derived in proportion to the flux in the inverter output transformers. A step is generated at the crossing point between ramp and control voltage and after amplification at Q23, Q24 triggers a blocking oscillator Q26 which provides a train of pulses per half cycle, each train commencing at a point in the A.C. input at which the thyristors D1, D2 of Fig. 2 are to be triggered. The I L  input is stated to correct variations in loop gain and thus improve regulation. Automatic voltage control of D.C.-D.C. converter.-Fig. 7 (not shown, see Division G3) relates to a Darlington pair of transistors used as a chopper regulator for one of the outputs of the rectifiers (Fig. 6, not shown) supplied from the two-phase inverters of Fig. 3.