Patent GB-1169441-A (GB)
Title: Radix Reconversion Apparatus.
IPC: H03M7/00
Filed: 1967-01-09
Abstract: 1,169,441. Radix conversions. BURROUGHS CORP. 9 Jan., 1967 [9 Feb., 1966], No. 1203/67. Heading G4A. A radix reconverter comprises two buffer memories interconnected for data transfer therebetween, and two accumulators, one of the buffer memories having an output connected to one of the accumulators. A 12-stage pence accumulator RA is provided to store a pence quantity of up to 12 decimal digits for reconversion to pounds, shillings and pence. To perform the reconversion, an addressing device AAR addresses the stages of RA in turn, most significant first. In a first phase, characterized by bi-stables SQ1, SQ2 both being off, a clock 15 increments a cyclic group counter GPC having a range 0 to 9, and increments the addressed stage of RA. When this stage goes to 0, producing a carry, bi-stable C is set to 1 (carry between decimal orders in RA is inhibited) thus preventing further incrementing of RA and passing subsequent pulses from the clock 15 to increment a cyclic count-up counter CUC having a range 0 to 23. When group counter GPC goes from 9 to 0, the clock 15 is turned off, flip-flop SQ1 is set to 1 and a second phase starts. In this the contents of count-up counter CUC and a bi-stable W which was set to 1 if the count CUC went from 23 to 0, are transferred in parallel to a cyclic count-down counter CDC with a range 0 to 23, and a bistable X respectively. Fig. 1 does not show the interconnections for phases 2 and 3 (Figs. 3, 5, not shown), but the same main units are used. Bi-stable Y is set to 1 if CUC does not hold 0 or if it does and W is at 1, i.e. Y being at 1 means that CUC stored a value other than 0 at some time during the first phase. CUC and W are reset to 0. Carry between decimal orders in RA is now enabled. The group counter GPC and (provided Y is at 1) count-up counter CUC are incremented by clock 15 and whenever GPC goes from 9 to 0, CDC is decremented. Whenever during this, CUC goes from 23 to 0, a carry is added in to the addressed stage of RA. When CDC reaches 0 then if X is at 0, Y is reset to 0. Whether X is at 0 or not, X is reset to 0 when CDC reaches 0 so Y will be reset to 0 at the first or second time CDC reaches 0. When Y is reset, the clock 15 is stopped, AAR is caused to address the next higher state of RA, and SQ2 is set to 1 to initiate phase 3. In this phase, clock 15 advances AAR and GPC until the latter goes to 0 when the clock 15 is turned off. The AAR has thus advanced to the next lower order decimal digit of the pence quantity, phases 1 to 3 for this now following. The above mode of operation is modified in dealing with the next-to-least-significant decimal order in RA if Y is at 1, as follows. In phase 2, the CUC is not incremented by each CLK pulse but only when GPC goes from 9 to 0. Thus CUC counts at the same rate as CDC. Also, any carries from CUC go to the third stage of RA, not the currently-addressed second stage. The above mode of operation is also modfied in dealing with the least significant (first) decimal order in RA, as follows. Following the setting of C in phase 1, subsequent pulses from clock 15 are applied to a cyclic pence accumulator D ACC with a range 0 to 11, instead of CUC, and in phase 2, counting down of CDC is accompanied by incrementing of D ACC not CUC. Any carry from D ACC in phase 2 goes to the addressed (lowest) stage of RA. Thus finally, D ACC holds the pence and RA holds pounds and shillings, the shillings being in the lowest order two stages. The counters with ranges 0 to 11, and 0 to 23 may consist of 4 and 5 serially-connected bi-stables respectively.