Patent GB-1278102-A (GB)
Title: Pipelined high speed arithmetic unit
Inventor: WATSON WILLIAM JOSEPH
IPC: G06F7/487
Filed: 1969-06-12
Abstract: 1278102 Digital computer TEXAS INSTRUMENTS Inc 12 June 1969 [9 July 1968] 29854/69 Heading G4A The invention relates to a computer performing arithmetic operations using vectors, using an arithmetic unit containing special purpose units each performing a different arithmetic operation and being connectible in different series configurations. A computer has a central processing unit, a peripheral processing unit containing a plurality of virtual processors coupled to a common arithmetic unit, several memory units including magnetic tape, disc and thin film, a card reader and punch, a line printer, cathode ray tubes and keyboards. The CPU 10 executes user programs which require input/output services from the PPU 11. Programs which can proceed without waiting for an I/O service to be provided request a system call and proceed SCP command on line 41 and the program continues. Programs which cannot proceed without the service wait and a new program is selected. The PPU constantly analyses the programs in CPU 10 not being executed and chooses which is to be executed next and sets a switch plug 44. When a SCW command appears from the CPU on line 42 the switch plug enables an AND gate 43 which resets the plug and causes an indication of the next program to be executed to be fed to the CPU. This enables the next program to be executed without delay caused by a dialogue between the CPU and the PPU. The computer operates on vectors (X 1 , X 2 , ..., X n ) and is arranged to multiply matrices where To produce the matrix C two program loops are followed, an inner loop to produce rows e.g. C 11 , C 12 , C 13  and an outer loop changing the indices to allow the inner loop to produce the next row. The computer communicates at high speed with the arithmetic unit and is capable of looking at four succeeding operations at the same time (Fig. 7) so that as the arithmetic unit is performing a calculation T 1  Store/Fetch and Control Units are preparing for the next operation T 2 , the index and instruction buffer units prepare for the following operation T 3  and the instruction Fetch Unit is obtaining the next instruction. Data to the AU is passed via buffers A<SP>1</SP>, A and B<SP>1</SP>, B and is returned via buffers C<SP>1</SP>, C a word being supplied per clock pulse and an arithmetical operation being performed in general during a clock pulse. A generic vector instruction acquired in Unit 128 transfers data from a vector parameter file 125 to file 132 so that complex vector operations are specified at the machine language level. The file 132, used for multiplying vectors A and B to produce C defines the starting addresses in store of the three vectors, the number of elements in the operation, the number of turns in each loop and the address increments for each loop and the file works in conjunction with file 133 holding the current address of the vectors and the vector and loop counts. The arithmetic unit is pipe-lined and has several units performing different jobs and capable of being cross coupled in different ways. The virtual processors are selected by means of a unit illustrated in Fig. 13 (not shown). As described 8 virtual processors are used and two registers between them holding as many four bit words as there are time sharing slots in a timing cycle are provided each four bit word feeding a set of four AND gates which sets are successively enabled by a counter fed with clock pulses. Each AND gate of a set feeds a separate OR gate which feeds a register coupled to a decoder. Each four bit word contains 3 bits identifying one of the eight processors and one bit enabling or inhibiting the decoder. The decoder supplies a signal coupling one of the processors and the arithmetic unit together. The registers allow any desired allocation of time to any processors and allows easy change of the allocation.