Patent GB-1087189-A (GB)
Title: Content addressable memory system
IPC: G06F17/30
Filed: 1965-10-20
Abstract: 1,087,189. Content addressable memory. INTERNATIONAL BUSINESS MACHINES CORPORATION. Oct. 20, 1965 [Dec. 23, 1964], No. 44417/65. Heading G4C. In a content addressable memory system in which the identifiers generate a plurality of addresses which are not unique for all identifiers and in which the relevant data is stored at one of these addresses during a data storage cycle, comparison means is used during a single access cycle for determining which of the addresses contains the relevant identifier. In the example of Fig. 1 having three magnetic core matrix banks 10-12 an input register 18 contains both the identifier NAME and the relevant data. The identifier portion is applied to address transform circuits 30, 31, 32 which generate three different addresses according to different sets of criteria whereby the memory address registers 40-42 are correspondingly set. Three memory buffer registers 55-57 are thereby set to indicate the identifier and data contents (if any) of the different addresses. The identifier contents of the register 18 are then compared at comparators 25-27 with the identifier contents of the buffer registers 55-57 whereby one of the alternative gates 70-72 is selected for passage of the data to the output register 90. Operation (1) add name to system.-The identifier with or without relevant data is applied to input, register 18 via input 20 whereby the contents (if any) at the three addresses in the banks 10-12 are read out into buffer registers. 55-57 which also contain a single " S " bit position. Figs. 2A-2C (not shown), which indicates, when zero, that the .register is empty and therefore that the addressed storage location is available for the data. Simultaneously, compare circuits; 25-27 indicate whether the identifier to be inserted is in fact already stored. In this case a signal is generated on an (M) line (362), Fig. 3 (not shown), which indicates to the input/output device that the data has not been entered. Where all three memory locations already contain data, a " bumping routine " is initiated by a signal on one of the (V) lines (261), (263), Fig. 3 (not shown) of a random number generator whereby the new identifier and data is stored at one of the three randomly selected addresses. "Bumping routine."-The old name and data previously in the address location is transferred by lines not shown to the input buffer register 18 and the identifier applied to the transform circuits 30-32. Since the contents of the address of one memory bank already contains, the new data only two new addresses (if empty) can be available for storing the bumped data. If no addresses are empty the bumped data is again randomly stored in one of the addresses and new bumped data inserted in register 18. The bumping operation continues until a vacant address is found. Name delete operation (2).-The name is set up in register 18 from input 20 and the data as identified by the comparators 25-27 is supplied to the output buffer register 90 for transfer to a utilizing device. The data in two of the registers 55-57 not containing the identified data is recirculated into the memory locations while movement of the identified data is inhibited so that the addressed location is filled with zeros. Data write operation (3).-New data supplied to input register 18 is applied through lines 16 to the identified address in place of recirculating the contents of the identified buffer register 55-57. Data read operation (4).-The operation is the same as for " name delete " but after transfer via the output register 90 the contents of all the registers 55-57 are recirculated into the memory locations. Magnetic drum memory.-In a modification (Fig. 4, not shown) the content addressing system is applied to a magnetic drum memory (550) having three drum address registers (555)-(557) which are compared with that of an actual address register (572). On matching, the contents of the matched address are read out to the buffer register (586) whereby as in the example of Fig. 1 it is ascertained whether the address is empty or contains the required matched identifier. Where neither condition occurs during a complete rotation of the drum a bumping routine is initiated at the first address coming under the head during the next complete rotation.  Modified bumping routine.-A scheme is referred to in which the names in the accessed addresses are applied sequentially to the address transform circuits 30-32 giving nine addresses from which to find an empty address. If none is found the operation is repeated to give twenty-seven addresses &c. until an empty address is located.