Patent GB-840598-A (GB)
Title: Improvements in or relating to pulse code modulation systems
IPC: H03M1/00
Filed: 1957-12-20
Abstract: 840,598. Pulse code modulation circuits. WESTERN ELECTRIC CO. Inc. Dec. 20, 1957 [Dec. 31, 1956], No. 39648/57 Class 40(5). Relates to a pulse code modulation system in which volume range compression is combined with the encoding operation and volume range expansion with the decoding operation, both the encoding and decoding apparatus inclu ding a feedback circuit com prising a phase-inverting amp lifier to produce the desirec non-linearity. The basic circui Fig. 1 includes resistors 1-5 to 1-1 having values of R, R, 2R 4R, 8R, respectively, which are connected in series betweer ground 2 and a reference poin 3, and through taps 4, switches S2 to S6, equal high resistances 6, and a common load resistor 7, may be connected to a source of potential B. The point 3 is connected to the input of a phase-inverting amplifier 8 whose output is connected to the point 9 which is common to all the resistors 6 The switches S2-S6 are closed (i.e. positioned to connect the source B to the corresponding resistor (1) in accordance with the binary code which is to be decoded, whereby, if the feedback amplifier is disregarded, a standard current flows through the resistance network and produces a potential at the point 3 corresponding to the code. The amplifier 8 receives at its input a signal proportional to the potential at 3, amplifies and inverts it, and applies the resulting signal to the terminal 9, thus reducing the potential at this point. Thus produces at the output 10 an amplitude compression of the output signal as compared with the input signal. In the code tabulated in Fig. 3, the presence of the first, or most significant digit denotes a negative signal, the remaining digits being the same for positive and negative values, and the code groups representing small amplitudes are characterized by a large proportion of 1's while the code groups representing large amplitudes are characterized by a large proportion of 0's. Fig. 6 shows an encoder in which code element-groups are applied to the switches S1 to S6 in systematic succession to generate corresponding decoded values which are matched in turn against the signal amplitude to be coded. When the best match has been obtained the pattern of switch closures which produces it represents the code counterpart of the signal amplitude thus matched. An adding network of resistors R to 8R is connected as before between ground and a test point 3, the point 3 being connected to the input of an inverting amplifier 8. The resistors are supplied with control current through respective changeover switches S2 to S6 and resistors r from a source B+, through a load resistor RL, and a supplementary source E, and a selected one of two bias sources +V and -V may be connected via a switch S1 to the test point 3. The arangement is such that the voltage drop across the adding resistor network may be either positive or negative, and the maximum value of this voltage when all the switches S2 to S6 are closed is balanced by the bias +V or -V according to whether the drop is negative or positive. The incoming signal at 16 is amplified at 17 sampled at 18, and compared at 15 with the potential at point 3, which initially with all the switches S1 52 to S6 closed, as shown is zero the unit 15, consisting of a trigger tripping one way or the other according to the potential difference, taking account of polarity between the input potentials to produce a corresponding output pulse on terminal 20 or 21. The output pulse from 15 is standardized as by a blocking oscillator 24 controlled by timing pulses at the code element rate from a source 25. A divider circuit 26 derives pulses at the signal sample or pulse group rate to control the sampler 18 which are also applied to terminals b of triggers FFMV2 to FFMV6 and terminal a of FFMV1 to reset them prior to each encoding operation to a position in which their outputs drive all the switches S2 to S6 to the positions shown. The group rate pulses are also passed through delay devices 28 each of which delays the pulse by one code element interval the outputs of the delay devices being connected to respective control terminals of auxiliary reset switches Fl to F5 to permit the application of a pulse from the output of the blocking oscillator 24 to switch a corresponding trigger 27 from its test or 'b' conduction condition to its reset or 'a' condition. Each time the trigger FFMV1 receives a group rate pulse at its input a it delivers an output pulse to reverse the switch S1 and place a negative bias on the test point 3, and to reverse the switch 22, thus applying pulses when they exist from the terminal 20 to the blocking oscillator 24. Each time one of the other triggers 27 delivers an output pulse as determined by application of a group rate pulse via a delay device 28. to its input a it opens the corresponding switch S2 &c. If, for example a positive signal sample of unknown amplitude be applied from the source 16 the comparator 15 delivers an output pulse at its terminal 20 but this terminal is open-circuited by the switch 22. Hence the blocking oscillator 24 is not tripped and the first digit of the code pulse group is an "OFF" or "O" pulse which appears at the output terminal 29, and the switches remain unchanged for the next comparison. After one code element interval the group rate reset pulse appears at the terminal a of the trigger FFMV2 thus opening the switch S2 and bringing the potential of the point 3 to a new value which is positive. If the signal sample is more positive than this new test value the blocking oscillator 24 receives no pulse from the unit 15 and delivers a "O" pulse to the output for the second digit and the switch S2 remain open. If the signal sample is less positive than the potential of point 3 the unit 15 delivers a pulse to the blocking oscillator 24 an "ON" pulse is delivered to the output terminal 29, and through the switch F2, now closed by the group rate pulse, to the terminal b of the trigger FFMV2 to restore the switch S2 to its closed position. The same group rate pulse is applied to the terminal a of trigger FFMV3, thus preparing the apparatus for a third comparison of the signal sample amplitude with the potential at the test point 3. This process is repeated until the coding of the sample is complete, and the group rate pulse resets all the switches to the rest condition and operates to take a new sample. The characteristic of the coder is shown in Fig. 8. The decoder, Fig. 7, comprises a similiar group of resistors R, R, 2R, 4R, 8R, and inverting amplifier 8 each resistor being supplied with control current through a respective switch S2 to S6 from a source +B via a load resistor R L , and a supplementary source E. The bias source +V or -V may be connected to the point 3 according to the position of the switch S1. Initially the switch Sl is in the position shown and the remaining switches S2 &c. are open, i.e. in the opposite position to that shown. Incoming pulses at the terminal 30 are reshaped at 31 and are brought into time coincidence by a distributor consisting of delay devices 32, the presence or absence of a pulse in a code group determining whether the corresponding switches S1 to S6 are changed over or not. For example, if the code pulse group is 011111, representing O, application of the first digit OFF pulse holds the switch S1 at its left-hand position and the remaining ON pulses close the switches S2 to S6 thus producing a negative voltage drop across the resistance network proportional to 16+8+4 +2+1=31 which is balanced by the positive bias from +V to produce a zero potential at point 3. Similarly with an input pulse group of 011001, representing +6, the voltage drop across the resistance network is -16-8-0-0-1= -25 and the net voltage at the output point 3 is 31-25=6. The output potential is modified by the degenerative feedback action of the valve 8 to produce a volume range expansion characteristic which is the inverse of that shown in Fig. 8, Fig. 9 (not shown) the output being taken from a sampler 37 which is controlled by timing pulses at the code group rate which are generated from a timing source 34 controlled by the input signals and applied via a divider 31 and adjustable delay device 36. In modifications of the embodiments shown in Figs. 6 and 7 diode gates replace the switches. Resistors R, 2R, 4R, &c. may be arranged in parallel to form a current addition network, Fig. 12 (not shown). The apparatus may be adapted for use with codes other than binary. For example in the case of the ternary code each digit position may contain a pulse having one of three values, 0, 1, 2, the elements of the adding network may be proportioned so that the various sums of any number of them, taken in succession from a reference point are proportional to the succesive integral powers of three, and the switches S may be three position-instead of two-position. Specification 697,880 is referred to.