baber/WOPTO huggingface dataset:
Patent JP-H11238153-A (JP)
Title: Charging processor to vehicle and card for charging processing
Inventor: YANAGISAWA TAKASHI
IPC: G01C21/26
Filed: 1998-02-19
Abstract: PROBLEM TO BE SOLVED: To perform a charging processing to the user of a vehicle by simple constitution. SOLUTION: An on-vehicle equipment 30 reads area information from an IC card 232 and stores it in a memory 230. The area information includes the data of a charging object area and the charging amount of the area, etc. When the vehicle travels, the position of the vehicle is specified by GPS signals and whether or not it is the charging object area is judged by using the area information (table) read from the IC card 232 and stored in the memory 230. When it is the charging object area, the charging amount is calculated by using the area information (table) and charging is performed. Thus, even in the case of not loading a communication equipment, the charging object area is easily specified and the charging processing is appropriately performed.
Patent JP-2000236430-A (JP)
Title: Facsimile equipment
Inventor: YASUDA HISAHIRO
IPC: H04M15/28
Filed: 1999-02-16
Abstract: PROBLEM TO BE SOLVED: To provide a facsimile equipment that calculates a communication charge required for facsimile communication with high accuracy before completing the facsimile communication. SOLUTION: This facsimile equipment, that receives a destination telephone number and instruction of transmission, reads a transmission original to store coded image data to a memory temporarily, recognizes a file capacity F of image data and stores the destination telephone number and a transmission designation time T in cross reference with the image data to the memory. When the facsimile equipment dials the destination telephone number and is connected to a line with the destination, the facsimile equipment executes a usual facsimile communication procedure to confirm a real transmission rate K' and to calculate a transmission time(t) required for transmitting the image data of a transmission original on the basis of the real transmission rate K' and the file capacity F.  Then the facsimile equipment calculates an estimate speech charge S in the case of a speech to an area of the transmission destination for a transmission time(t) from a charge table, and transmits the estimate speech charge S to the destination by a prescribed unique communication control procedure without opening the line when the transmission of the image data is finished (steps S101-S110).
Patent JP-S55130282-A (JP)
Title: Picture tracking device
Inventor: HIGUCHI HIROSHI
IPC: H04N5/228
Filed: 1979-03-30
Abstract: PURPOSE:To ensure the effective elimination of the after-image by repeating alternately the field for reading the video signal and the field for erasion of the after- image. CONSTITUTION:In the field for reading of the image, constant circuits 14 and 17 are connected to electron beam focusing circuit 13 and bias circuit 16 via the function of selectors 15 and 18 so that the diameter of the electron beam may be stopped down into the small value on photoelectric screen 8. In the next field, constant circuit 19 is connected in switching to circuit 13 so that a necessary size may be secured for the electron beam diameter on screen 8. At the same time, constant circuit 20 is connected to circuit 16 selectively so as to obtain a sufficient amount of electron beam for discharge of the residual charge. The selective switching is carried out in the electronic way for the constant circuits with every field.
Patent JP-H02215845-A (JP)
Title: Preparation of hard foam with improved physical property
Inventor: IMAI YOSHIO
IPC: C08L75/04
Filed: 1989-02-17
Abstract: PURPOSE:To improve physical properties without occurrence of cell disorder and shrinkage by reacting a polyol and a polyisocyanate compd. in the presence of a specified foaming agent, a catalyst, a foam stabilizer, etc. CONSTITUTION:A foaming agent is obtd. by compounding 80mol% or less tetramethylsilane and trichloromonofluoromethane. A polyol and a polyisocyanate compd. (B) are reacted in the presence of above agent, a catalyst, a foam stabilizer, etc.
Patent JP-S56133882-A (JP)
Title: Semiconductor optical detector
Inventor: YAMAMOTO YOSHIMICHI
IPC: H01L31/0352
Filed: 1980-03-24
Abstract: PURPOSE:To reduce crosstalk by providing in a multilayer semiconductor substrate with the first conductivity type, a plurality of semiconductor regions with the second conductivity type piled one upon another being connected to each other through only a portion thereof. CONSTITUTION:P type impurity is diffused into a silicon substrate 1 to form a diffused layer 8 with the opposite conductivity type. Then, an epitaxial layer 9 is formed, and therein, a diffused layer 10 is formed so as to overlap with the regions 8 through only a portion thereof. Similarly, an epitaxial layer 11 is formed, and therein, a diffused layer 12 is formed. Then, epitaxial layers and diffused layers are successively formed, and only the portions where the layers 8, 10, 12... overlap with each other are allowed to conduct.
Patent JP-S56133666-A (JP)
Title: Testing method of dielectric strength
Inventor: TANI ISAO
IPC: G01R31/12
Filed: 1980-03-24
Abstract: PURPOSE:To take a test of dielectric strength to a DC voltage as to a stator coil, cable etc., in rated voltage, by providing voltage-dividing electrodes at the coil end part of an electric-field reduction layer and by applying the voltage obtained by dividing a voltage applied to a conductor. CONSTITUTION:At the outer circumference of main insulating layer 5 of the coil end side part of electric field reduction layer 7, voltage-dividing electrodes 9a and 9b are provided and the 20% and 60% voltage taps of power source 8 are connected respectively. As the voltage-dividing electrodes, electrodes wound with usual conductive metallic foil of about 10mm. in width may be used. Consequently, the potential distribution of voltage reducing layer 7 is shown by (b) and the potentials of  the voltage- dividing electrodes are forcibly held at the same potentials with the tap  voltages of the DC high-voltage source. As a result, gradients of rises in potential from one terminal of the electric-field reduction layer to electrode 9a, electrode 9a to  electrode 9b, and electrode 9b to the 100% potential are more gentle than usual,  and no creeping discharge occurs on the surface of main insulating layer 5.
Patent JP-H08234516-A (JP)
Title: Electrophotographic device
Inventor: NAKAMICHI KIYOSHI
IPC: G03G15/00
Filed: 1995-02-27
Abstract: PURPOSE: To provide an electrophotographic device capable of rapidly driving a stand-by roller and capable of performing a high-speed printing without colliding a previously printed paper with a succeedingly printed paper on a path from an inverting roller to an inversion carrying path without enhancing the performance of a driving motor in an electrophotographic device of an electrophotographic printing system capable of performing printing on both sides of a paper. CONSTITUTION: In a paper carrying means provided with a stand-by roller 102 making the paper fed from a paper feeding cassette 2 pass through between a printing means constituted of a photoreceptor 17 and a transferring device 18, an inverting roller 106 carrying the paper passing through the printing means, fixed by a fixing roller 103 so as to be printed to a paper carrying path 101 in an ejection direction or to the inversion carrying path 107 while inverting the carrying direction, and a flipper 105 facing the trailing end of the paper reaching the roller 106 on an inversion carrying path 107 side, the roller 102 is driven by a stepping motor which is independent of the driving system of the photoreceptor 17 and whose responsiveness is good.
Patent JP-S51113110-A (JP)
Title: Drive system for inductor type synchronous motor
Inventor: AKAMATSU MASAHIKO
IPC: H02P8/18
Filed: 1975-03-28
Abstract: PURPOSE:To enhance the precision in finely disassembled control of an inductor type synchronous motor system for highly disassembled control.
Patent JP-H04276953-A (JP)
Title: Communication controller
Inventor: SHINOHARA SATOSHI
IPC: H04L29/08
Filed: 1991-03-05
Abstract: PURPOSE:To improve the communication efficiency by stopping tentatively a transmission clock depending on the congestion state of a host device in the communication controller of a high level data link so as to avoid the occurrence of abort due to under-run. CONSTITUTION:A congestion deciding circuit 4 detects the congestion state of a host processing unit 1 and sends a stop command of a transmission clock to a transmission clock stop circuit 6. Upon the receipt of the stop command, the stop circuit 6 stops tentatively the transmission of the transmission clock of a transmission data to a line. Thus, the data transmission speed to the line is tentatively decreased till the congestion state of the host processing unit is released thereby avoiding the occurrence of abort.
Patent JP-H05206040-A (JP)
Title: Silicon selective growth method
Inventor: OSHITA YOSHIO
IPC: H01L21/205
Filed: 1992-01-29
Abstract: PURPOSE:To selectively deposit a film on a plurality of substrates at a low temperature by holding a plurality of substrates, the surface of which is partly covered by a dielectric insulating film, and on the reverse side of which silicon is exposed, at intervals less than the mean free pass of the gas molecule under the deposition pressure conditions, and by carrying the material gas to each of the substrates by diffusion. CONSTITUTION:An arrangement is made to introduce a material gas and a carrier gas from the lower part of a reaction tube 11 and exhausted from the upper part of it. By making the gas flow from the bottom to the top, a stabilized flow is formed, and the material is carried by diffusion to the intervals of each surface of the substrates. The substrates 18 are installed in the reaction tube 11. The number of the substrates 18 is 26. The interval between them is 500mum. Each surface of the substrates 18 is oxidized by the thermal oxidation method to form an oxide film 32. Then by removing them partly to form apertures 33. The oxide film on the reverse side is removed in advance. Then, silicon is deposited. As a result, the deposition is executed on the apertures 33 on all the substrates with the exception of the one mounted on the uppermost part.
Patent JP-S62196859-A (JP)
Title: Soldering method for semiconductor device
Inventor: TAKAHASHI HIDEYUKI
IPC: H01L23/31
Filed: 1986-02-24
Abstract: PURPOSE:To prevent the resin of a package from cracking by performing a waterproof process on the contacting portion of at least external leads of a resin-sealed semiconductor device with a sealing resin, and soldering the device. CONSTITUTION:The resin 12 of a package 14 is covered with a film 22 of waterproof agent 21 together with the contacting portion 19 of external leads 11 and the resin 12. The package 14 formed with the film 22 is dipped in a soldering bath 16. Then, in the steps of covering only the leads 11 with a solder 15 and soldering to mount the leads on a substrate, moisture invaded into a package 14 is not evaporated by heat. Thus, it can prevent the resin of the package 14 from cracking.
Patent JP-H10239940-A (JP)
Title: Image forming device
Inventor: URAKAWA TOSHIO
IPC: G03G15/01
Filed: 1997-02-24
Abstract: PROBLEM TO BE SOLVED: To reduce the number of parts and further the size of an image forming device main body by providing a scanning mirror for scanning with plural light beams and a reflection mirror for irradiating plural image carriers. SOLUTION: This image forming device is provided with a polygon mirror 13 which is a scanning mirror for scanning with laser beams from respective laser diodes 11, a scanning motor 14 which rotationally drives the polygon mirror 13 and the reflection mirror 15 which makes the laser beams cross once corresponding to respective colors, after being used for scanning, at the same intersection B and then, reflecting the laser beams to photoreceptor drums 7, so as to expose their surfaces corresponding to the respective colors. Then, the laser beams for the respective colors, from the laser diodes 11 are emitted toward the polygon mirror 13 in parallel, to be made incident on the same reflecting surface of the polygon mirror 13 and used for scanning and then, reflected by the reflecting surfaces of plane mirrors corresponding to the respective color of the reflection mirror 15.  Then, all laser beams cross at the intersection B and pass through and then, the surface of the drums 7 of the respective colors are exposed. Therefore, the laser beams for the respective colors can be reflected by one reflection mirror 15.
Patent JP-H0373922-A (JP)
Title: Liquid crystal display device
Inventor: IIJIMA CHIYOAKI
IPC: G02F1/133
Filed: 1990-02-20
Abstract: PURPOSE:To obtain the easily visible display device which has less unequalness (cobwebbing), makes high-speed response and is free from the jitters of a screen by constituting a nematic liquid crystal of a compsn. which contains a compd. having a -CN group or -F group at the terminal and in which the total compsn. ratio of this compd. ranges from 5wt.% to 40wt.%. CONSTITUTION:This liquid crystal display device is provided with a liquid crystal cell 2 constituted by inserting the nematic liquid crystal 6 twist oriented in a 180 to 360 deg. range between a pair of electrode substrates 3 and 4 disposed to face each other and a pair of polarizing plates 8 and 9 disposed on both sides of the liquid crystal cell 2. The layer thickness (d) of the nematic liquid crystal 6 is 2 to 5.5 mum. This nematic liquid crystal 6 is the compsn. which contains the compd. having the -CN group or -F group at the terminal and in which the total compsn. ratio of this compd. ranges from 5wt.% to 40wt.%. The volume of the liquid crystal layer can be lessened and the jitters of the display screen can be decreased. The liquid crystal display device which is short in response time, has the less cobwebbing and further has the decreased jitters of the screen is obtd. in this way.
Patent JP-S61209129-A (JP)
Title: Manufacture of partially microporous sheet
Inventor: NAKAMURA SHUNICHI
IPC: B29K105/04
Filed: 1985-03-01
Abstract: PURPOSE:To form a patterned and partially microporous sheet excellent in permeability to air and moisture, water repellency and tearing strength by a method wherein a sheet, which is made of composition consisting of thermoplastic resin and filler and in which portions different in thickness are distributed both in longitudinal and width directions, is stretched. CONSTITUTION:A thermoplastic resin composition, the thicker portions of which are set to run in the direction normal to the longitudinal direction (extrusion direction) of the sheet of the composition and the thinner portions of which takes 50% or more than the whole area of the sheet, is stretched. The rolling of the sheet is generally done at a temperature, which is lower than the melting point and higher than the secondary transition point of the thermoplastic resin with rolls, preferably with embossing rolls. The shapes of concavities and convexities 1 and 2 engraved on the embossing roll are preferably the pattern, which locates non-rolled portions perpendicular to the weak direction for preventing the propagation of tearing. Next, the rolled sheet is stretched so as to mainly stretch its thinner portion (rolled portion). Further, the resultant sheet is heat-treated under tension and cooled from the drawing temperature down to room temperature in order to be taken off.
Patent JP-H02216860-A (JP)
Title: Semiconductor device
Inventor: URABE TAKASHI
IPC: H01L21/822
Filed: 1989-02-16
Abstract: PURPOSE:To form a resistor element with a desired resistance value by forming trenches, bending in the depth direction thereof, and adjusting the number of the trenches and the depth of the trenches within a limited surface area. CONSTITUTION:Trenches 3 are formed in a P-type silicon substrate 1. Then, a resist 7 is applied and patterned by photolithographic technique. Next, an impurity is injected by using the resist as a mask (an N-type impurity such as P, As for a P-type silicon substrate, and a P-type impurity such as B for an N-type silicon substrate). Then, the resist is removed annealed to obtain a resistor element.
Patent JP-H10242349-A (JP)
Title: Semiconductor package connector and its manufacture
Inventor: KONO FUMIO
IPC: H01L23/32
Filed: 1997-02-24
Abstract: PROBLEM TO BE SOLVED: To enable an easy mounting or demounting of a package having extremely many electrodes to or from a circuit board, etc., by burying connection bumps at predetermined intervals in a bottom face of an insulating material and fusing one end of each contact lead to each connection bump and allowing the other end to project and bend from an upper face of the insulating material. SOLUTION: A package connector 1 has such a structure that a fixation frame 2 may be formed around an insulating material 3 and connection bumps 4 may be buried in a bottom face of the insulating material 3 and one end of a contact lead 5 may be fused to each of the connection bumps 4 with the other end being projecting and bending from an upper face of the insulating material 3. With such a package connector 1, high-level soldering technique is not required when connecting a package to a circuit board and all that is needed is to apply a little load. Therefore, the deformation and destruction of the package or the circuit board can be prevented and a stable conduction can be obtained. Furthermore, the package can be mounted and demented easily and surely without using special jigs.
Patent JP-H08280729-A (JP)
Title: Contraception adhesive film wherein function which is constituted by making holes on polyethylene adhesive film, and joining dome-form film is made contraception device
Inventor: KIN SATORU
IPC: A61F6/04
Filed: 1992-01-07
Abstract: PURPOSE: To avoid covering of a tactile skin and diminishing of a sympathy due to attaching a contraception appliance by constructing to adhere a same shaped polyethylene film with a predetermined thickness to a concave-convex adhesive film with a predetermined diameter, length and thickness. CONSTITUTION: Hemispherical crown paper 1, comprising an exfoliation covering 2 formed by coating an exfoliation solvent, is formed in hemispherical crown- shaped liner 3. An adhesive solvent is coated to the liner 3, and a both-sided adhesive film having a diameter of 25 mm, a length of 10 mm, and a thickness of 20 μm is formed. A four-structure copolymerized film 6 is formed by covering and bonding the convex of the adhesive film 4 with a concave side of the same shaped polyethylene film 5 having the thickness of 5 μm. In a surface area of about 80 mm<2> of the copolymerized film 6, oval holes having a length of about 2 mm, and a width of about 0.6 mm are perforated at about 70 mm<2> to form vent holes 7, and an adhesive vent film 8 is formed. A latex film 9 with a thickness of 10 μm is bonded to the convex of the adhesive vent film 8 at a bonding section 10.
Patent JP-S60184129-A (JP)
Title: Method of driving foundation pile for latticed wall
Inventor: TAKESHITA TAKASHI
IPC: E02D27/30
Filed: 1984-02-29
Abstract: PURPOSE:To construct the foundation which is excellent in a support force and an earthquake resistant force, by a method wherein foundation piles, which are continuously connected with each other, are simultaneously driven by means of a 3-shaft agitating rod by the use of an improved hardener, the foundation piles are continuously connected in a lattice shape, and intersection parts and corner parts are filled with a core body. CONSTITUTION:By means of a 3-shaft rod 9 having agitating vanes 12 and injection holes 13, which is located at the lower end of a driving machine 7 having a 3-shaft swivel 8, triplex foundation piles 2 are simultaneously driven in a ground, where foundation is intended to be constructed, by the use of an improved hardener. The foundation piles 2 are continuously driven, in order, to construct a latticed wall 6, and the intersection parts and corner parts of the foundation piles 2 are filled with a core body 3, such as steel pipes, and are cured to construct a foundation. This enables a total foundation to be integrally constructed, and enables provision of the foundation which is high in a supporting strength, earthquake resistant force, and horizontality.
Patent JP-S51114829-A (JP)
Title: Picture split indication control system
Inventor: HARA TOSHITAKA
IPC: G06F3/14
Filed: 1975-04-02
Abstract: PURPOSE: A system to display more than two split but independent pictures on one CRT Ddisplay screen. 
     COPYRIGHT: (C)1976,JPO&Japio
Patent JP-S56136094-A (JP)
Title: Chrominance signal generator of color telecamera
Inventor: KATOU TOKUZOU
IPC: H04N9/07
Filed: 1980-03-27
Abstract: PURPOSE:To improve the separation of a chrominance signal by obtaining a frequency-separated chrominance signal by temporarily converting a video signal into a signal with a frequency at which a filter having excellent characteristics can be obtained. CONSTITUTION:Frequency f0 obtained by crystal oscillator 12 which generates a reference signal for synchronizing signal generator 13 is multiplied and then heterodyned mixer 9 with a video signal from preamplifier 2 to perform frequency conversion once, and a chrominance signal is separated through filters 10 and 11 having excellent skirt characteristics like a surface elastic wave filter. Then, red and blue signals are obtained and detected by detectors 6 and 7, and a color difference signal is obtained by color encoder 8.
Patent JP-S59165152-A (JP)
Title: Error correction system
Inventor: KAZAMI HARUO
IPC: G06F11/10
Filed: 1983-03-11
Abstract: PURPOSE:To reduce the number of pins in case of closing to one LSI, etc., by allowing file counting for data transfer to substitute for shift counting for syndrome calculation and performing processing similar to data transfer. CONSTITUTION:An SQ update control circuit 4 operates by an external signal READ.TAG to update the contents of an SQ register 5. Serial data SRDATA from a disk device is inputted to an error correction control circuit ECC1 and a serial-parallel converting circuit 2. The circuit ECC1 selects the input data and supplies its output to an ECC buffer 3. The ECC buffer 3 codes a polynomial based upon correction codes in READ operation and performs error detection when a read of the correction codes is completed. Parallel data converted by the serial-parallel converting circuit 2 is ANDed by an AND circuit 7 by SQ condition and the output of a bit string register 6, and a strobe signal of read data is sent to a processor.
Patent JP-S59165299-A (JP)
Title: Memory parity error display system
Inventor: HONMA HIROSHI
IPC: G06F11/10
Filed: 1983-03-11
Abstract: PURPOSE:To obtain an inexpensive display system by making the 1st processor constituting a multi-processor system read the entire area of each of plural memories constituting the system so as to generate a parity error and displaying the error to a display means of the 1st processor. CONSTITUTION:A control program of a memory 3 sets ''during operation'' to an LP(local program) supervising area in a prescribed period. The local supervising program discriminates the LP system normal when ''during operation'' is set and sets ''during supervision by LP'' to said area. If ''during operation'' is not set in said area even when said prescribed period is elapsed, it is discriminated as the failure of the LP system, the control program of the memory 3 reads the entire area of a local memory 41, and when the parity error occurs, an interruption signal 10 is inputted to a processor 1 and an error processing routine is started. The processing routine saves the register having an error to a register saving area, starts a display circuit driver 6A through a signal line 11 and displays the information on a display device 6B.