Patent GB-823374-A (GB)
Title: Improvements in or relating to electronic calculating apparatus
Inventor: KNIGHT LORIN
IPC: G06F7/50
Filed: 1955-06-23
Abstract: 823,374. Digital-electric-calculating apparatus. INTERNATIONAL COMPUTERS & TABULATORS Ltd. June 22, 1956 [June 23, 1955], No. 18182/55. Class 106 (1). Specification 767,692 describes a calculator for performing arithmetic operations on numbers expressed in non-uniform notation, e.g. pounds, shillings and pence, in which the denominations of the number are operated upon serially, each digit being expressed as four binary components which are operated upon in parallel. This binary notation has a scale of sixteen so that amounts in a scale of more than ten such as pence can be dealt with as a single denomination. According to the present invention, which modifies a calculator of this kind to enable it to deal with Indian currency, in order to facilitate arithmetic operations provision is made for generating from a pair of denominational groups of signals, which together represent a digit in a single denomination of a number, equivalent value-representing signals in the lower denominational group. The pair of denominational groups may be annas and tens of annas (in Indian currency), these values being read from separate columns of punched cards, so that 15 annas is represented by a " one " in the tens denomination and a " five " in the units denomination. This value is converted to a single binary representation of 15 in the units denomination. There are twelve pies to one anna and sixteen annas to one rupee so that amounts in this currency can be handled in a calculator designed to deal in sterling with a modification to compensate for the difference that there are sixteen annas to the rupee whereas there are twenty shillings to the pound. The modifications are described with reference to the above-mentioned Specification, in which the amount is read from a card into a register and where it is to be multiplied, the multiplier is likewise read from a card into a register. Multiplication is effected by repeatedly halving the multiplier and doubling the amount, until the multiplier vanishes, the amount being entered into an adder each time the multiplier becomes odd. For subtraction the amount to be subtracted is passed through a complementing unit before being entered into the adder. Adding circuit.-In the modification, before entering the adder or the complementing unit, the two denominational groups representing annas and tens of annas are converted into one denominational group based on a scale of sixteen. This is done by adding ten to the lower denominational group if there is a " one " in the higher denomination and suppressing read-out of this latter denomination. The adding unit described in Specification 767,692 is modified as shown in Fig. 1. The inputs to the adder from the registers are through inverters 39 which enter the signals into two sets of triggers 600, 601. These form a two-stage shifting register holding two adjacent denominations of one of the numbers to be entered into the adder. The second trigger 601(1) controls a gate 44(1) through gate 602 and a gate 43(1) through gate 621. One output of trigger 601(2) is connected to one input of a two-input adder 603, the other input coming from gate 604. The sum output of the adder controls gate 44(2) and the carry output controls gate 44(4) (also controlled by trigger 601 (4)). Gate 44 (8) is controlled by the gate 604 and also by trigger 601(8). These gates 44, when open, pass the outputs from the triggers 601 to the binary adders 330, 331, 332, 333 which are three-input adders. Another input to the adder 330 is through inverters 36 through a similar two-stage shifting register comprising triggers 605(1), 606(1) controlling gates 607, 609. A two-input adder 608 is connected in a way similar to adder 603. When the triggers 601, 605 are registering annas, the tens of annas, fed from the next stages of the registers, are registered on triggers 600(1) and 606(1). The tens of annas can only have values " 0 " or " 1." Gates 604, 609 are controlled by these triggers and if trigger 600(1) is on, a " 2 " input is passed to adder 603 and an " 8 " input is passed to the gate 44(8) thereby adding ten to the annas and converting it to a scale of sixteen. If trigger 606(1) is on, the gate 609 likewise adds ten to the second input of adders 330, 331, 332, 333. A carry from the adder 333 represents 16 annas and is added as a " 1 " to the units of the rupees. This is effected by a carry trigger 613. Filler digits are added to convert the sum output from the adders 330-333 to decimal form. On the next step when the tens of annas have moved into triggers 601(1) and 605(1) the line R1 is made positive closing the gates 602 and 607 to prevent a " 1 " being passed to the adder 330. The value represented in triggers 601 is complemented by closing gates 44 and opening gates 43. The sum output from the adder 603 is inverted and fed to two-input adder 618, the other input being derived from line 322 via gate 619 which is controlled by line R2. Adder 618 controls gate 43(2), the output therefore representing the inverted output of adder 603 plus a " 2 " filler digit. The inverted output from trigger 601(4) is passed to a three-input adder 620, the other inputs being the carry output from adder 618 and the line R2. A " 4 " is inserted when line R2 is negative. The sum output of adder 620 operates gate 43(4) and the carry output operates gate 43(8), which is also operable by the inverted output of trigger 601(8). An impulse on line 328 also operates gate 43(8) to enter an " 8 " filler digit. The inputs to the gates 43 therefore represent the inverted settings of triggers 601 plus the necessary filler digits. Complementing a value in annas requires no filler digits since they are already in a scale of 16. Doubling circuit (Fig. 2, not shown).-Before the annas and tens of annas values are entered into the doubling unit they are combined into one denomination as described but separate triggers for the two consecutive denominations are not used. Instead the last two stages of the store holding the number to be doubled are used. The output from the doubling circuit is passed to the adding unit by lines 645. Division by ten.-This is effected in two stages. In the first stage the number is divided by ten as if it were sterling but with the doubling and adding circuits operating. in rupees, annas and pies. This gives a division by ten which obeys the rules for sterling and in particular it gives this incorrect result: 1 rupee divided by ten = 2 annas. The correct value is 1 anna, 7.2 pies, and a correction value of 4.8 pies per rupee has to be subtracted from the result. This correction is made in stage two, by means of a coding matrix which operates under the control of four triggers set to represent the number of rupees. The matrix then produces the necessary correction value which is subtracted from the result obtained in stage one to give the correct answer.