baber/WOPTO huggingface dataset:
Patent TW-266242-B (TW)
IPC: F16L55/179
Filed: 1995-03-20
Granted: 1995-12-21
Abstract: The novel method is used to renovate or close connections in a pipeline (12), in particular in drains, especially after the main and/or connecting pipe (16) has been relined. The method comprises the following steps: introducing and positioning a shuttering sleeve (22) with a recess and bores (28) corresponding to the connection aperture for pressing in a hardenable, and possibly resilient, mortar, preferably epoxy mortar, in the main pipe; introducing the expandable rubber balloon (34) so that its outer part lies in the still-intact part of the connection pipe (16), its central part lies between the connection pipe and the recess in the shuttering sleeve, and its part containing the fluid delivery point lies in said recess and in the main pipe; expanding and positioning said expandable rubber balloon so that it delimits a space either between the bored-out end of the connection pipe, the recess in the shuttering sleeve and the surrounding soil, or simply between the bored-out end of the connection pipe and said recess if the previously projecting connections have been milled off, said space then being filled with a hardenable, and possibly resilient, mortar, preferably epoxy mortar; and, when the mortar has set, optionally removing and extending both the shuttering sleeve and the expandable rubber balloon which has been rendered pressure-free.
Patent TW-350141-B (TW)
Title: BICMOS cache tag comparator having redundancy and separate read and compare paths
Inventor: FENG TAISHENG
IPC: G06F12/08
Filed: 1995-05-11
Granted: 1999-01-11
Abstract: A sort of fast access label comparator, having a memory unit label line; a memory unit extra line for replacing the memory units with flaws in said label line; a plurality of data multiplexers coupled to the label line and the extra lines, and one of the data multiplexers providing a label address byte having a selected memory unit corresponding to either the label line or the extra line, with logic status; a plurality of comparators, coupled to a plurality of data multiplexers, of which one is coupled to one of the plurality of data multiplexers, and the comparator for receiving an input data and the label address byte, in case of identical the logic status of the address byte and that of the input data, provision of a comparison signal on a logic status output and in case of different the label address byte of the logic status and the logic status of the input data, provision of a comparison signal of the second logic status; and BICMOS logic circuit, coupled to the plurality of multiplexers, when all the comparator signals in identical logic status, the BICMOS logic circuit providing a matching signal having the first logic status and in case of different, BICMOS matching logic circuit providing the second logic status.
Patent TW-263600-B (TW)
Title: Process for implementing etching
Inventor: LIOU MING-TZONG
IPC: H01L21/311
Filed: 1995-06-06
Granted: 1995-11-21
Abstract: A process of implementing etching with photoresist as mask, that is applicable to form semiconductor material with at least one etched layer, comprises the steps of: covering photoresist layer on the above etched layer; aligning mask with predetermined pattern, and implementing exposure to the above photoresist layer; implementing developing the above photoresist layer; implementing baking to the above photoresist layer; and with the above photoresist layer as mask, implementing etching to the above etched layer; It features that implementing ion implantation to the above photoresist layer is done before implementing etching to the above etched layer.
Patent TW-332197-B (TW)
Title: A process for recovering 2-hydroxy-4-methylthiobutyric acid (MHA), MHA and its use
Inventor: HASSEDRG HANS-AKBRECHT
IPC: C07C323/60
Filed: 1995-07-07
Granted: 1998-05-21
Abstract: A process for recovering 2-hydroxy-4-methylthiobutyric acid (MHA) from a reaction mixture which is obtained by adding hydrocyanic acid (HCN) to methylmercaptopropionaldehyde (MMP) and hydrolysis of the thereby obtained methylmercaptopropionaldehyde cyanohydrin (MMP-CH) with sulphuric acid, in which the reaction mixture is placed in contact with an organic solvent which is essentially immiscible with water in a liquid / liquid extraction system in order to form an extraction solution which contains the solvent and MHA transferred from the reaction mixture ; the MHA is recovered as an extract from this extraction solution by evaporation, which is characterized in that the evaporation is carried out such that the remaining extract contains less than 4 wt% of water.
Patent TW-368745-B (TW)
Title: Semiconductor device with IC chip highly secured
Inventor: ISHIDA YOSHIHIRO
IPC: H01L23/31
Filed: 1995-08-09
Granted: 1999-09-01
Abstract: In the semiconductor device that after the IC chip being loaded on the circuit substrate, employing the packaging resin as the packaging, and the curved resist film is formed on the substrate and at the opposite to the curved portion of IC chip. Employing the die bond to attach the curved portion on the curved resist film. Furthermore, the die pattern is protruded to the outside of the said curved photoresist film, and surrounded the proximity to form the power pattern. The power terminal of IC chip and the said die pattern and the power pattern are connected by the bonding wires. Through these steps, the bonding force of the curved portion of IC chip can be enhanced and the peeling effect can be prevented; and, the bonding can be freely configured for a plurality of power supply wiring at the same time.
Patent TW-396145-B (TW)
Title: A process for producing cobalt (II) oxide containing cobalt metal
Inventor: GOGRE ASTRID
IPC: H01M4/52
Filed: 1996-01-26
Granted: 2000-07-01
Abstract: The present invention relates to cobalt (II) oxide containing metallic cobalt and to a process for producing, characterised in that crstallised basic cobalt compounds of general formula. Co[(OH)2]a[O]b[CO3]c where 1.5>(a+b+c)>1.0 are reacted with aqueous and/or alcoholic solutions of a carboxylic acid selected from the group consisting of linear or branched, saturated or unsaturated polycarboxylic acids having a number of C atoms from 2 to 10 and linear or branched, saturated or unsaturated mono-and polyhydroxy-carboxylic acids having a number of C atoms from 2 to 7 and the solids thus obtained are separated from the suspension and calcined; wherein calcination is effected in an inert gas atmosphere at temperatures between 200 and 1000 DEG C, and the reaction is first conducted for 0.1 to 3 hours at room temperature, and  subsequently for 0.1 to 3 hours at 50 to 100 DEG C. wherein after the completion of calcination, both the internal and external surface of the Co(II) oxide is covered with the metallic cobalt.
Patent TW-360624-B (TW)
Title: Improved corrosion inhibiting formulations with calcium nitrite
Inventor: BERKE NEAL STEVEN
IPC: C04B28/02
Filed: 1996-01-27
Granted: 1999-06-11
Abstract: An admixture for cement compositions is provided which contributes both anodic and cathodic corrosion inhibition, and the cement compositions containing such additives. The cement additive is a combination of an anodic corrosion inhibitor such as calcium nitrite, and a cathodic corrosion inhibitor such as calcium stearate or other fatty acid. The mixed inhibitors in accordance with the invention provide as good or better corrosion inhibition than does calcium nitrite when used alone.
Patent TW-322465-B (TW)
Title: Technique for the removal of residual spin-on-glass (SOG) after full SOG etchback
Inventor: WU LIN-JUNE
IPC: H01L21/768
Filed: 1996-09-20
Granted: 1997-12-11
Abstract: This invention relates to a method for removing residual spin-on-glass (SOG) during a planarization processing step wherein the SOG is used as a sacrificial planarization medium and subjected to a full etchback to an underlying interlevel dielectric (ILD) layer. The SOG is applied over the ILD layer, and etched back into the ILD layer by reactive-ion-etching under conditions of comparable etch rates for both SOG and ILD. At endpoint there some residual pockets of SOG can be present as well as a region of SOG along the edges of the wafer where it is clamped in the etchback tool. The residual SOG must be removed completely to avoid SOG cracking after thermal processing and SOG outgassing during subsequent metal deposition. For this purpose an aqueous etch consisting of hydrofluoric acid buffered with ammonium fluoride is used. The etchant composition chosen exhibits a selectivity for SOG over the ILD glass of greater than 40 making it suitable for removing considerable SOG residues with minimal attack of the ILD.
Patent TW-306005-B (TW)
Title: Decoding method of diode-type read only memory array
Inventor: JANG GUANG-YEH
IPC: G11C17/06
Filed: 1996-11-22
Granted: 1997-05-21
Abstract: A decoding method of diode-type read only memory array, in which the diode-type read only memory array includes at least one row of memory cell and at least one column of memory cell, and the row memory cell and column memory cell independently contain multiple memory cells, and those memory cells contains multiple first memory cells with logic "1" and multiple second memory cells with logic "0", and each memory cell independently is coupled to one word line and one bit line, and the same row memory cell is coupled to same word line, different row memory cell is coupled to different word line, and the same column memory cell is coupled to same bit line, different column memory cell is coupled to different bit line, comprises of:(1) selected one memory cell to be read, inputting one low voltage to all bit lines coupled to the memory cell, and inputting one high voltage to the other bit line; and (2) inputting the high voltage to word line coupled to selected memory cell, and inputting the low voltage to the rest word line.
Patent TW-402483-B (TW)
Title: Pesticidal composition and method for controlling pests using the same
Inventor: MURAKAMI YOSHIKAZU
IPC: A01N57/02
Filed: 1996-12-13
Granted: 2000-08-21
Abstract: A pesticidal composition comprising micro-capsules, each microencapsulating an organophosphorus compound having a melting point of at least 15 DEG C, a proportion (A) of aromatic ring structure in microcapsule wall material being not more than 40% by weight, and a ratio of (A) to (average diameter/wall thickness) of the microcapsules being not less than 0, but not more than 0.8, causes less color change to applied area even if applied outdoors.
Patent TW-363249-B (TW)
Title: Manufacturing method for reducing the contact deformation
Inventor: CHENG CHIH-HSIANG
IPC: H01L21/768
Filed: 1997-01-13
Granted: 1999-07-01
Abstract: A kind of manufacturing method on which there is a metal silicide layer on the surface of silicon contact region with cruds and to form a conductive layer on it. The selected thickness and material must make the conductive layer be a reflection resistant layer during the process of contact photolithography. The formed reflection resistant layer is to depose a metal layer on the doped contact region and convert part of metal layer into metal silicide by the annealing process. The second annealing converts the metal silicide to a low resistance phase. The third annealing employs the rapid thermal anneal, better within the nitride or ammonia, to convert part of surface of metal silicide into the titanium nitride whose thickness must be able to be the reflection resistant layer that the thickness equals to a quarter of wave length used by the photo phase corresponding to the reflection rate of titanium nitride in the process of forming the dielectric contact.
Patent TW-439005-B (TW)
Title: Thin film forming apparatus
Inventor: MASAKI KENICHI
IPC: B41F17/14
Filed: 1997-03-14
Granted: 2001-06-07
Abstract: In a thin film forming apparatus including a printing roll 3 having a rubber or resin elastic projection 31 mounted on its surface, and an anilox roll 4 rotating with faced to the printing roll 3 which transfer ink to the surface of the elastic projection 31 with the contact with the printing roll 3, a pair of printing roll-side contact members 300 is provided on a body of the printing roll or its rotary shaft, a pair of anilox roll-side contact members 400 is provided on a body of the anilox roll or its rotary shaft, and the printing roll-side contact members 300 continuously contact the anilox roll-side contact members 400 at least from before the elastic projection 31 contacts the anilox roll 4 to when the elastic projection 31 contacts the anilox roll 4, thus forming a thin film with a uniform thickness.
Patent TW-353725-B (TW)
Title: Color filter and method for manufacturing the same
Inventor: YAMADA NOBUAKI
IPC: G02F1/1333
Filed: 1997-03-25
Granted: 1999-03-01
Abstract: A color filter comprising: a conductive layer having low conductivity regions; and a plurality of colored regions included in a colored layer on the conductive layer, in which each of the colored regions has a concave portion at a position corresponding to each of the low conductivity regions.
Patent TW-322624-B (TW)
Title: Process of raising polysilicon load effective length in static random memory cell
Inventor: PERNG JIUNN-HORNG
IPC: H01L21/8244
Filed: 1997-07-10
Granted: 1997-12-11
Abstract: A manufacturing method of forming resistive load static random access memory cell comprises of the following steps: (1) depositing one SiN layer on one transistor cell surface, in which the transistor cell includes one doped source and drain located on substrate, source and drain of the transistor cell independently are located two sides of undoped channel in substrate, the transistor cell has one gate oxide located above and contacting with the channel region, one first polysilicon located above and contacting with the gate oxide, one salicide layer located above and contacting with the first polysilicon, the transistor cell has one space located on the above first polysilicon, salicide layer, and gate oxide sidewall, the first polysilicon and the salicide layer constitute one gate of the transistor cell, one N lightly doped drain is formed in substrate of the transistor cell; (2) on the SiN layer surface depositing one first tetra-ethyl-ortho-silicate(TEOS); (3) on the source and drain surface forming one first polysilicon via; (4) on the above TEOS surface covering one first photoresist; (5) by masking and patterning, removing the above TEOS which is not covered by the first photoresist by etching; (6) on the above first TEOS surface depositing one second polysilicon with low density; (7) on the above first TEOS covering one second photoresist; (8) by masking and patterning, removing the above TEOS which is not covered by the second photoresist by etching; (9) on the above first TEOS surface depositing one second polysilicon with high density.
Patent TW-347313-B (TW)
Title: Shoe sole and shoe and sandal including the sole
Inventor: TUJI HIROAKI
IPC: A43B13/00
Filed: 1997-11-26
Granted: 1998-12-11
Abstract: A shoe sole, comprising: a toe portion (10) having a first upper surface (F) mainly supporting toes in a forepart of a foot, and a first bottom surface portion (A) in contact with a plane of walking; and a main portion (20) formed continuously with the toe portion having a second upper surface (E) mainly supporting the metatarsal bones of the forepart, a middle part and a back part of the foot, and second, third and fourth bottom surface portions (B, C, D), in which the second bottom surface portion (B) is connected almost in parallel with the first bottom surface portion and connected in a flexible manner to the first bottom surface portion; the third bottom surface portion (C) is provided continuously with the second bottom surface portion and in an inclination at a prescribed angle upwardly relative to the second bottom surface portion, and has a smaller thickness at a portion on a lateral side of the foot than the thickness of a portion on a medial side of the foot; and the fourth bottom surface portion (D) is formed virtually flat, continuously with the third bottom surface portion and in an inclination at a prescribed angle upwardly relative to the third bottom surface.
Patent TW-379413-B (TW)
Title: Method of forming buried via in integrated circuits
Inventor: HUANG GUO-CHIN
IPC: H01L21/768
Filed: 1997-12-27
Granted: 2000-01-11
Abstract: A method of forming buried via in integrated circuits by first forming regional isolation on a semiconductor substrate, followed by forming the gate oxide layer, a thin silicon layer and a hard protection mask. By using microfilm, etching and ion planting to form the light doped drain of a transistor. Then comes the forming of silicon oxide plug, and the removal of the hard protective mask by using microfilm, etching and ion planting to form the buried via. Depositing the low isolation conductive layer and then forming the sidewall, finally the source/drain of the transistor by using ion distribution.
Patent TW-409126-B (TW)
Title: Method of making (1S, 4R)-1-azabicyclo[2.2.1]heptan-3-one and (1R, 4S), 1-azabicyclo[2.2.1]heptan-3-one
Inventor: SOBIERAY DENIS M
IPC: A61K31/4015
Filed: 1998-01-22
Granted: 2000-10-21
Abstract: Racemic (+/-) -1-azabicyclo[2.2.1] heptan-3-one may be efficiently resolved into its (1S, 4R) -and (1R, 4S) -1-azabicyclo[2.2.1]heptan-3-one isomers by formation of di-p-toluoyl hemitartrate salts by combination with di-p-toluoyl-L-tartaric acid and di-p-toluoyl-D-tartaric acid, respectively./ Selective crystallization using one of the di-p-toluoyltartaric acids in less than stoichiometric amount in a suitable solvent mixture allows isolation of the desired isomer as its respective di-p-toluoyl hemitartrate in high isomeric purity. The isolated hemitartrates are storage stable and may be used as such in the preparation of pharmaceuticals and other biologically active compounds, or may be used to provide the free base of the respective 1-azabicyclo[2.2.1]heptan-3-one isomer.
Patent TW-358998-B (TW)
Title: Self-alignment for contact probe
Inventor: YANG JR-REN
IPC: H01L21/66
Filed: 1998-02-17
Granted: 1999-05-21
Abstract: A self-alignment for contact probe, for alignment of a probe having a pair of alignment wafers for alignment of patterns onto a wafer having a pair of probes, including the self-alignment of the contact probe the following steps: defining on the wafer alignment pattern a first coordinate system, which has a center O1 and a right crossed X1 and Y1 axes, and the wafer alignment pattern including a circular sector having O1 as the center, and defining in the sector a supposed concentric circle; defining a second coordinate system having O2 as the center, and the right crossed X2 and Y2 axes on the probe alignment pattern, including the first supposed pattern having O2 as the center, and with Y2 axis and Y1 axis for forming the probe angle; pre-alignment, with the probe aligning pattern aligning the wafer alignment pattern and the center O2 defined in a specific quadrant on the first coordinate system and in the concentric circle, and the first supposed circle having a first arc, defined outside the circle and the center point of the first arc and the center O2 forming a first arc axis; obtaining a first measurement data, for determination of the first distance between the center O2 and O2, and the first angle between the first arc axis and the Yx axis; by means of an offset distance, in parallel to the X1 or Y1 axis to move the probe alignment pattern and maintaining the center O2 in the quadrant and the supposed concentric circle, being the Y2 axis and Y1 axis maintaining the probe angle, having a second arc as the first supposed circle, for defining outside the circle; the center point and O2 of the second arc forming a second arc axis; obtaining a second measurement data, for determination of the second distance between the center O1 and O2, and the second angle between the second arc axis and the Y2 axis; and by using the first and the second distance and the first and second angle, for determination of the probe angle between the Y1 and Y2 axes and the position of O2 in the first coordinate system.
Patent TW-394961-B (TW)
Title: Low capacitance chip varistor and fabrication method thereof
Inventor: AHN BYEUNG-JOON
IPC: H01C10/00
Filed: 1998-03-17
Granted: 2000-06-21
Abstract: A low capacitance chip varistor and a fabrication method thereof are disclosed, which are capable of protecting the electronic elements of an electronic instrument from an external and internal surge and being well applicable to an electronic element which requires a low capacitance, and the low capacitance chip varistor includes at least one sheet support layer formed of a member having a low dielectric constant, a varistor layer including at least more than one varistor coating layer formed on the support layer, at least more than two internal electrode folded with a predetermined portion of the varistor layer to be connected with the varistor layer, one end of each of which is extended from a lateral surface of the support layer, and a pair of integrally formed external electrodes formed on a lateral surface of a varistor stack member integrally formed of the support layer, the varistor layer and the internal electrodes to be connected with one end portion of each internal electrode.
Patent TW-410152-B (TW)
Title: Pulse wave detection apparatus, pulse motion detection apparatus and pressure detection apparatus
Inventor: AMANO KAZUHIKO
IPC: A61B5/024
Filed: 1998-03-25
Granted: 2000-11-01
Abstract: This invention is a kind of pulse wave detection apparatus, pulse motion detection apparatus and pressure detection apparatus wherein the pulse wave detection apparatus comprises a plural pulse wave detection units and the supporting body in said pulse wave detection unit is the beam body installed the pressure detection apparatus, the contact portion in the front terminal of the beam body contacts the wrist in accompanying with the pulse pressure change of the radial artery is the detection of the circuit device on the beam body. And the supporting body in the supporting beam body is settled the contact portion having the clamping beam body on its two lateral there are two press leg portion, and on the front end of the press leg portion is pressed the wrist of the measured one, the press leg portion has higher hardness than the radial artery, and the spacing between two is from the operation of the micro-measuring head which could proceed change, besides the front terminal of the beam body is installed on the above portion of the opposite lateral toward the direction of front end which is more front than the press leg.
Patent TW-414758-B (TW)
Title: Mask for use in screen printing
Inventor: MANO TAKUMI
IPC: B41N1/24
Filed: 1998-05-28
Granted: 2000-12-11
Abstract: A mask for use in screen printing is provided which can increase the product yield as a result of the fact that oozing of ink is suppressed, can decrease the operating time period as a result of the fact that the frequency at which the mask is cleaned is suppressed, further can also lessen the wear of the opening portion edge of the mask as a result of the fact that the cleaning frequency of the mask has been decreased and hence can also extend the use life of the mask, and therefore can reduce the printing cost compared to a conventional mask. To this end, in the printing mask for use in screen printing, there are provided ink dams each of which consists of a U-groove and is provided in the ambient area in the vicinity of an opening portion, constituting an ink discharge portion on a printing surface side in opposition to a member to be printed, of the screen printing mask. Further, the distance from an end portion of the opening portion of the screen printing mask to the ink dam is in a range of from 20 mu m inclusive to 100 mu m inclusive, the width of the ink dam is in a range of from 30 mu m inclusive to 100 mu m inclusive, and the depth of the ink dam is in a range of from 1/2 inclusive of the thickness of the mask to 30 mu m inclusive.