Patent GB-717114-A (GB)
Title: Improvements in or relating to digital computers
Inventor: WILKINSON JAMES HARDY
IPC: G06F7/52
Filed: 1950-01-04
Abstract: 717,114. Digital electric calculating-apparatus. NATIONAL RESEARCH DEVELOPMENT CORPORATION. Dee. 20, 1950 [Jan. 4, 1950], No. 240/50. Class 106 (1) Electrical apparatus for multiplying two ndigit binary numbers represented by series-mode pulse trains has a first serial store for storing 2n digits arranged to be fed with the multiplier, means for producing an additional unit delay connected during multiplication in the circulation circuit of thestore, a second serial store for storing n digits arranged to be fed with the multiplicand, means for periodically extracting the output from the delaying means during each first digit period of the multiplicand, an adder, means operated by the said extracted output for feeding the output from the second store to one input of the adder when the extracted output is one, and a serial store for storing 2n digits and connected to include the adder and a unit delay in its circulation circuit whereby at the conclusion of the operation, the output of the adder represents the product. The unit delays may be incorporated in the associated serial stores, and the last mentioned store may in fact be the first store. In one arrangement, Fig. 19, the output of an acoustic delay line of 65-digit length, through which the 32-digit multiplier is circulated, is applied to a trigger L of threshold 2. P1 pulses are also applied to this trigger so that the trigger is switched on during the first digit period of each minor cycle if the output of the delay line at. the moment is a one. When the trigger is on, a gate N is opened to pass the output from a 32-digit delay line, through which the 32-digit multiplicand is circulated. to one input of an adder Ad. The other input to the adder is supplied by a second 65-digit delay line which is initially empty. Thus during the first effective minor cycle, the partial product formed by multiplying the multiplicand by the highest-order digit of the multiplier is represented by the output of the adder. This is fed into the second . 65-digit delay line. During the first period of the next minor cycle, the output digit of the first delay line is, in any case, a zero and so the trigger L, which is restored if it has been switched on during the last digit period of each minor cycle by a P32¢ pulse, is not switched on. During each successive pair of minor cycles, a further partial product is added to the sum of those already formed, the different digits of the multiplier becoming available and the sum of the partial products being column-shifted by virtue of the fact that the relevant delay lines accommodate 65 digits each, so that eventually the product appears at the output of the adder. In a preferred arrangement, Fig 21, the first 65-digit delay line is replaced by a 64-digit delay line and a unit delay 5, and the output of the adder is fed into the delay line r. Normally the pulses stored in this delay line do not circulate through the unit delay but during a multiplication operation, a potential M closes a gate in the normal circulation path and opens a gate to the unit delay, the output of which is applied to the trigger L. In order that this trigger be controlled only by multiplier digits, it is pulsed with alternate P1 pulses only which are applied also to close a gate 6 in the circulation path effective during multiplication which passes through the adder Ad. Thus, each multiplier digit is erased when it has controlled the trigger L to effect or inhibit the entry of the multiplicand from the 32-digit store d into the adder, to make room for the increasing number of digits in the running total of the partial products. The various control pulses necessary for amultiplication operation may be produced by a circuit. Fig. 24, on receipt of an initiating pulse which opens a gate 14 to a P32 pnlse. The latter switches on a trigger Mu, which supplies the control potential M, Fig. 21. This trigger also switches on a trigger 15 which switches itself off after just over one minor cycle. A trigger 10 is switched by successive P16 pulses so that a gate 11 is opened during alternate minor cycles to P32 pulses. The first of these pulses passes through a gate 17 temporarily opened by the trigger 15 and initiates operation of a counter comprising five triggers 18, all of which are initially on. This first pulse switches the triggers off so that a gate 28 of threshold 5 is closed and a gate 27 is opened for the counter-operating pulses. After the thirty-second alternate P32 pulse, the triggers 18 are again all on and the gate 28 is opened to close the gate 27, and to apply a potential through a unit delay to open a gate 29 to P32 pulses delayed by a half-unit delay 13 to provide P32¢ pulses one of which is consequently passed through the gate 29 to the trigger Mu to restore it at the end of the operation. The alternate PI pulses are obtained by delaying the alternate P32 pulses by one unit. The acoustic delay lines maty be replaced by magnetic storage devices as described, for example, in Specifications 707,634, 707,635, 707,637 and 717,113. Diagrams are given for a 32-digit (one minor cycle) ring counter, a staticizer, a dynamicizer and an adder. Specification 700,007 also is referred to.