Patent GB-1410631-A (GB)
Title: Data processing system interrupt arrangements
IPC: G06F12/10
Filed: 1972-01-26
Abstract: 1410631 Program interrupt systems PLESSEY CO Ltd 15 Jan 1973 [26 Jan 1972] 3601/72 Heading G4A In a system in which a processor has at least one capability register storing a segment descriptor defining a memory segment to which the processor may have access while executing a particular process, a characteristic code may be loaded into the capability register whereby, if an attempt is made by the processor to access the corresponding memory segment, the presence of the code causes suspension of the current process and entry into an interrupt handling program. Loading of capbility register.-In response to a load capability register instruction, a reserved capability pointer, comprising an access type code and reserved capability pointer address offset, is read from memory. If the two most significant bits of the access code are 11 signifying a memory segment capability, the capability register is loaded with the base and limit addresses of a particular segment obtained from a master capability table after performing a sum check on that data. If the required segment is undergoing relocation, the associated sum check word in the master capability table is reset to zero and on detection of this condition during a load capability register operation, the capability register concerned is set to all zeros. Similarly, if the access code most significant bits are other than 11, the capability register is again set to all zeros instead of being loaded with the segment base and limit addresses. Normal operation.-An external address is obtained from an instruction by adding an offset address in an operand register to the base address in a selected capability register and with modification if this is called for. The two highest bits of the access code in the selected capability register are tested, and if found to be 11, the access type, address limits, and function code are checked before performing the function specified by the instruction. Violation of any of these conditions results in setting of a fault indicator and entry into a fault handling process. If the two highest access code bits are not 11 a trap microsequence is initiated. Trap microsequence.-The identity of the capability register in use at the time is recorded in registers in the processor and a trap accept bit is set in an interrupt accept word register to indicate the reason for entry into an interrupt handling process. The current process parameters (contents of accumulator registers, scheduler timer register and a primary indicator register) are transferred to a dump stack assigned to the current process and defined by a segment descriptor stored in a particular capability register. The interrupt handling process proper is then entered by reference to the master capability table. The interrupt handling process can, from the stored identity of the capability register in use when the process was suspended, compute the dump stack address of the corresponding reserved capability pointer. The access code of that pointer enables the reason for the process being trapped to be ascertained so that a disc handling or I/O handling process may be initiated or, if the two highest access code bits are 00, for the process to be suspended until the segment in question is free. In this way all processes requiring reference to a segment which is undergoing relocation can be trapped, or a particular process can be trapped selectively (code 00), or trapped for entry into a page changing or I/O handling process (codes 10, 01). Specifications 1,329,721 and 1,332,797 are referred to.