Patent GB-807700-A (GB)
Title: Magnetic core memory system
IPC: G11C7/02
Filed: 1957-09-02
Abstract: 807,700. Electric digital-data-storage apparatus. NATIONAL CASH REGISTER CO. Sept. 2, 1957 [Oct. 17, 1956], No. 27553/57. Class 106 (1). [Also in Group XL (c)] A computer magnetic core matrix storage system has the row (and column) drive lines at one end connected in groups selectable by a group address matrix comprising transistors and at the other end connected to a line address matrix common to all of the groups also comprising transistors. As shown, Fig. 1, to select a core of the array 21, one X and one Y drive line are selected. The drive lines are connected in groups 1x, 2x, 3x selected by the X drivers 24 under control of the X address matrix 23, and the X " symmetrical drivers " 25 select under the control of the X " common address matrix " 26 a single X drive line. Selection of the Y drive lines is accomplished in a similar manner. The timing pulse generator 37 in response to signals from a clock pulse source 38, delivers logical read and write pulses on the lines Rx, W x , Ry, &c., and the flip-flops L1-L12 in response to signals from the computer determine selected row and column lines. During the computer read cycle, if a selected core is storing a binary one, an output is induced over the sense line 45 to a gate 41 which is opened by a pulse from the strobe generator 40 when a read pulse on the line R x  coincides with a clock pulse on the line 43. The pulse then triggers a flip-flop FFM1 whose output appears as a " true " output (0 volts) on the line M 1  and a " false " output (- 8 volts) on the line M<SP>1</SP> 1 . During the subsequent computer write cycle, if M<SP>1</SP> 1  is false from reading a one, gate 56 is closed to prevent the write pulse W<SP>1</SP> x  from actuating the inhibit driver 57 which thus does not send an inhibit pulse over the line 58 passing through all the cores of the array 21. Thus the X and Y drivers will write a one in the selected core. If M<SP>1</SP> 1  is true from reading a zero, an inhibit pulse on the line 58 prevents writing. New information to be written in can be inserted into the flip-flop FFMI over the lines 53, 54. The X address matrix 23, Fig. 3, selects a transistor 93-95, 112-114 for reading or writing to supply a half-current pulse to the selected group of rows in the array. Selection of the drivers 93-95 is by n-p-n transistors 86-91. Thus the driver 93 conducts only when the combination of transistors 86, 88, 89 conduct from the terminal 102 to the base of the driver 93 due to the lines Rx, L<SP>1</SP> 12 , L<SP>1</SP> 11  going true. Each transistor has a voltage dividing arrangement such as resistors 125, 127 so that current flows only through selected transistors. When none of the read drivers 93-95 is selected, current flows from terminal 100 through a " dummy driver " transistor 92 via a resistor 99 and inductance 98 to a terminal 101. When reading takes place, the line R x  goes true and R<SP>1</SP> x  false so the transistor 92 is cut off and the selected driver 93-95 conducts. During this changeover the inductance 98 acts to give the driving half-current pulse a fast rise time. The resistance 96 is of a value such that the current through the inductance 98 remains approximately constant. The resistance 99 reduces the amplitude of current variations to a range which can be controlled by the inductance 98. Thus the slow response time of the transistors is overcome and a halfcurrent pulse with a fast rise time and constant amplitude is provided. A " dummy driver " 115 acts in a similar manner to the dummy driver 92 for the write drivers. A second cause of poor rise time and variation in amplitude, current leakage through unselected driver transistors, is reduced by the connection of the base of the drive transistors to the collectors of transistors 89-91 since a change in voltage on the collector of a transistor in the arrangement shown will not cause a base current and thus will not allow a collector to emitter current. Individual x row selection, Fig. 4.-The " X common address matrix " 26 selects a symmetrical driver transistor 180-189 which connect to the rows 1-10 of each of the three groups of rows selected as described above. The matrix 26 comprises transistors connected (as shown) to select one of the symmetrical n-p-n transistors which conduct when current passes to their bases from earth 141. Thus the transistor 180 conducts only when the transistors 192, 131, 132, 133 have a false signal applied to their bases from the lines L 5 , L 6 , L 7 , L 8 , respectively. During reading, the line R x  goes true and a current pulse is passed from the +12V terminal 100 through the driver transistor, 93 for example, selected by the matrix 23 to the Group 1 line, and then through the particular line of the group selected by the matrix 26, such as by the line 1 connected to the transistor 180. Diodes are provided in lines of the array 21 to prevent sneak pulses passing through unselected lines. The arrangements for driving the Y lines are similar to those described.