Patent GB-1518731-A (GB)
Title: Methods of recording digital data signals
IPC: G11B20/14
Filed: 1976-01-08
Abstract: 1518731 Digital data recording and playback INTERNATIONAL BUSINESS MACHINES CORP 8 Jan 1976 [6 Feb 1975] 00685/76 Heading G4C For each serially-received data bit signal from a source 13, a sequence of discrete signal levels is generated by an arrangement 14 in accordance with a predetermined sequence extending over a predetermined number of data bit periods, the amplitudes of all the discrete signal levels occurring in each and every data bit period being summed prior to recording the summed amplitudes on a recording medium 10. The recording medium 10 may be a single or a multiple track magnetic tape or a magnetic disc. In the preferred embodiment the predetermined sequence is a Huffman sequence, although other sequences such as linear FM, pseudorandom sequences, Barker sequences and Frank sequences may be used. As described a Huffman sequence of MN terms is produced by interleaving an M-term Huffman sequence produced by a tapped delay line 25 (M taps) with an N- term Huffman sequence produced by a tapped delay line 26 (N taps), the spacing of the taps of delay lines 25, 26 being respectively 1 and M nominal data bit periods. A table of values is given for a 400-term Huffman sequence formed from choosing M=N=20. The outputs from the taps of the delay lines 25, 26 are combined in respective resistive analogue summing circuits 28, 30 (shown in detail in Fig. 3, not shown) to provide, respectively, the input to the delay line 26 and that to write circuits 11. Each summing circuit 28, 30 is identical, the values of the incorporated summing resistors (which are connected to the taps of the delay lines 25, 26) being inversely proportional to the values of the terms of the M-term and N-term Huffman sequences. For playback, an arrangement 40 of cascaded tapped delay lines similar to the arrangement 14 employed for recording is employed, the values of the incorporated summing resistors of the associated summing circuits 44, 46 being arranged in inverse order to those of the summing circuits 28, 30. A playback clock 42 may be synchronized with the output of a playback amplifier and filter 41, or with the output of either summing circuit 44 or 46. In another embodiment, Fig. 4 (not shown), the tapped delay lines of the playback circuits are replaced by a CCD analogue shift register clocked by a two-phase clock locked to the filtered played-back data signals to accommodate speed variations of the recording medium. A similar CCD analogue shift register may be used for recording, its clock being locked to the output signal of a tachometer driven by the recording medium. Sinusoidal synchronous biasing may be employed during magnetic recording by use of a circuit 100. It is stated that by distributing the information of a single data bit period over the predetermined number of data bit periods, immunity to noise and dropouts is obtained up to about 10% of the predetermined number of data bit periods. Crosstalk between adjacent tracks of a magnetic disc may be reduced by employing a Huffman sequence and its inverse for recording on these tracks.