Patent GB-1517661-A (GB)
Title: Method and apparatus for synchronizing master and local time base systems
IPC: H03L7/06
Filed: 1976-03-31
Abstract: 1517661 Master and secondary clock systems SINGER CO 31 March 1976 [14 July 1975] 13049/76 Heading G3T To effect the synchronization, with a master clock time-base of a plurality of local clock systems, e.g. on aircraft, ships and other vehicles and fixed stations, the synchronization errors of a local clock system are automatically corrected during a time slot unique to that local system. In the embodiment described, each system cycle or 'epoch' consists of a series of 1024 time slots in which time slot "O" (Fig. 1) is assigned to the master and 1023 are respectively assigned to each of the 1023 local systems in the operative community. The time duration of a single cycle is 2À68 secs so that each slot is 2À62 m. secs. The time base 21 generated by each local system is the same as the time base 21 generated by the master clock or controller. In Fig. 1, a local station or "user" N is out of synchronization with the controller time base 20. At the beginning of each controller slot O, the controller generates a coarse synchronization signal 22 which is received by all users. When a local station first joins the network this signal is used to set its time base to the start of a system cycle. Due to radio propagation time delay tp, the user's time base will have a relative error E=tp with respect to the controller. When the user's slot N is reached, the station N transmits a fine synchronization request signal 23 which is received by the controller at time T. The controller measures the elapsed time between the start of its timebase slot N to the time T and transmits a fine synchronization reply signal 24 at a time (10-T) which is the same distance from the end of slot N as T is from the beginning. When the reply is received the user N measures the elapsed time between the reply and the end of its slot N; the magnitude so measured is 2E. The local time base 21 is therefore automatically adjusted to eliminate the measured error E and bring it into synchronism with controller time base 20. Thereafter fine synchronization is effected every cycle. Fig. 2 illustrates a local station time base arrangement. The master time base arrangement is similar except that the correction circuits therein are inhibited. Coarse and fine synchronization signals from the master are decoded to produce pulses 50, 51 which are applied to a control logic circuit 52. The local timing signal 34 is produced by a relaxation oscillator 31 and a main counter divider 30. The oscillator frequency and phase controlled by a D/A converter 32 driven by an up-down counter 33. The counter 33 is normally set at mid-range and is incremented or decremented by a series of pulses proportional to the measured error. A counter 35 is stopped upon receipt of a reply signal and makes the synchronization error measurements by measuring the elapsed time between the fine synchronization reply and the end of the local station slot. The main counter 30 also gauges the period of each system cycle, of each slot and of each slot division. The measured error is fed to an arithmetic section 55 which is controlled by sequencing logic 53 and chooses one of a number of control states according to the magnitude of the error and the number of system cycles between updates. Outputs from section 55 representing the magnitude and sign of the required correction are fed to an increment control 58. The latter adjusts the up-down counter 33 and the main counter 30 to correct the oscillator and the clock signals from the main counter 30 respectively. The corrections are in effect based on the mean value of errors over a number of cycles rather than the instantaneous error at a given sampling time. The correction circuitry functions generally as a digital filter. The arithmetic processor section thereof is described with reference to Fig. 7 (not shown). A correction state control algorithm is given in Fig. 3 (not shown).