Patent SG-11201906749U-A (SG)
Title: Synchronous hardware event collection
Inventor: Norrie Thomas
IPC: G06F11/34
Filed: 2017-10-20
Abstract: INTERNATIONAL APPLICATION PUBLISHED UNDER THE PATENT COOPERATION TREATY (PCT) (19) World Intellectual Property Organization International Bureau (43) International Publication Date 04 October 2018 (04.10.2018) W I PO I PCT omit VIII °nolo OH 1101 SID mil ono oimIE (10) International Publication Number WO 2018/182783 Al (51) International Patent Classification: GOOF 11/30 (2006.01) GOOF 11/34 (2006.01) (21) International Application Number: PCT/US2017/057638 (22) International Filing Date: 20 October 2017 (20.10.2017) (25) Filing Language: English (26) Publication Language: English (30) Priority Data: 15/472,932 29 March 2017 (29.03.2017) US (71) Applicant: GOOGLE LLC [US/US]; 1600 Amphitheatre Parkway, Mountain View, California 94043 (US). (72) Inventors: NORRIE, Thomas; 1600 Amphitheatre Park- way, Mountain View, California 94043 (US). KUMAR, Naveen; 1600 Amphitheatre Parkway, Mountain View, California 94043 (US). (74) Agent: HENRY, Joel et al.; Fish & Richardson P.C., P.O. Box 1022, Minneapolis, Minnesota 55440-1022 (US). (81) Designated States (unless otherwise indicated, for every kind of national protection available): AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DJ, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JO, JP, KE, KG, KH, KN, KP, KR, KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW. (54) Title: SYNCHRONOUS HARDWARE EVENT COLLECTION 100 Host System Monitoring Engine 126 co N co 00 O C 102---„ \ Controller To Host 114 ( -116 Node Manager Host Interface Blk(HIB) 4J-0. First Processor Core (FPC) 104 A ( 120 106--„ \ / Matrix Unit Second Processor Core (SPC) Vector Programmable Unit (MXU) 4— Transpose ► (VPU) 122 Node Unit 110 Fabric (XU) (NF) To HBM ► 124 HBM Mux Reduction and Permutation Unit (RPU) -118 112 ICI Router (ICI) Tenso (Data Arrary) Core FIG. 1 (57) : A computer-implemented method that includes monitoring execution of program code by first and second processor components. A computing system detects that a trigger condition is satisfied by: i) identifying an operand in a portion of the program code; or ii) determining that a current time of a clock of the computing system indicates a predefined time value. The operand and the predefined time value are used to initiate trace events. When the trigger condition is satisfied the system initiates trace events that generate trace data identifying respective hardware events occurring across the computing system. The system uses the trace data to generate a correlated set of trace data. The correlated trace data indicates a time ordered sequence of the respective hardware events. The system uses the correlated set of trace data to analyze performance of the executing program code. [Continued on next page] WO 2018/182783 Al MIDEDIMOMMIONER1311101010MMODEVOIMIE (84) Designated States (unless otherwise indicated, for every kind of regional protection available): ARIPO (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW), Eurasian (AM, AZ, BY, KG, KZ, RU, TJ, TM), European (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR), OAPI (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG). Published: — with international search report (Art. 21(3))