Patent GB-1137907-A (GB)
Title: Improvements in or relating to multiple-chip integrated circuit assembly with interconnection structure
IPC: H01L21/60
Filed: 1965-12-08
Abstract: 1,137,907. Semi-conductor devices; circuit assemblies. SIGNETICS CORP. 8 Dec., 1965 [9 Dec., 1964], No. 52024/65. Headings H1K and H1R. A circuit assembly, Fig. 5, comprises an insulating wafer 13 bearing on its under surface a plurality of thin film resistors (Fig. 2, not shown) and a semi-conductor wafer 23 bearing on its under surface the electrodes of junction devices, e.g. diodes, transistors, formed in the wafer, and capacitors (Fig. 4, not shown), the said under surfaces of both wafers also bearing conductive terminal areas to which the components of the respective wafers are connected by deposited wiring, the said terminal areas being bonded to the ends of deposited conductors 33 on an insulating substrate 32. Wafer 13 is produced by the division of a slice of glass or Si having a plurality of resistor arrays formed thereon; similarly, wafer 23 is cut from a semiconductor slice, e.g. of Si, having a plurality of arrays of junction devices and capacitors formed thereon. Conductors 33, which may be formed by evaporating A1 on to substrate 32, either through a mask or with subsequent etching, are connected to leads 31, ends of which are flush-bonded in the substrate. Wafers 13, 23 may be spaced from substrate 32 by beads formed on the terminal areas or on the corresponding ends of conductors 33. A cross-over wafer 38 may also be bonded to selected conductors 33, and the assembly may be encapsulated by a cover adhered over the wafers and conductors by a suitable glaze. The cross-over wafer 38, Fig. 7, comprises semi-conductor material of one conductivity type having highly doped conductive regions 39, 40 of the opposite conductivity type in its lower surface. An insulating layer 41, e.g. of SiO 2 , is formed over the said surface, openings 42 being etched in the insulating layer 41 to give access to the highly doped regions 39, 40. A conductive layer is deposited by evaporation over the insulating layer 41 and into the opening 42 therein and is etched to form plugleads 43, 44 in the openings 42 and a further conductor 46. Raised portions, e.g. of Al or Au, are provided at the ends of the leads 43, 44 and the conductor 46 or on corresponding ends of the substrate conductors 31. Figs. 9, 10 (not shown), depict a simpler cross-over device comprising a glass or ceramic wafer (51) having a plurality of spaced parallel conductors (52) evaporated thereon. Modification.-In Fig. 11 (not shown), thin film elements are formed on an insulating wafer (73), and a smaller semi-conductor wafer (74) comprising the junction devices is bonded thereto, the insulating wafer (73) being subsequently bonded to conductors (81) on an insulating substrate (71) which comprises a recess (78) to accommodate the semi-conductor wafer (74). External leads (72) are moulded into the substrate (71), entering at an edge surface thereof and being bent through 90 degrees so that their inner ends lie flush with the major surface of the substrate (71) on which the conductors (81) are deposited, to make contact therewith. The assembly is hermetically sealed by a cover (84) attached to the substrate (71) by a glaze (87). Reference has been directed by the Comptroller to Specification 1,037,063.