Patent GB-1009412-A (GB)
Title: Parallel adders
IPC: G06F7/506
Filed: 1964-08-04
Abstract: 1,009,412. Parallel adders. NATIONAL CASH REGISTER CO. Aug. 4, 1964 [Aug. 6, 1963], No. 30546/64. Heading G4A. A radix-n parallel adder employs carry propagation circuits using majority logic elements. As described, a parallel adder, Fig. 4, adds two 12-decimal-digit numbers, each decimal digit being in binary coded 1-2-4-8 form, and parametron majority logic circuits are employed. The four binary signals representing the two decimal digits to be added in each decimal order are applied to a unit 21 comprising a partial adder circuit 22 for forming the sum mod 10 (Psm1-Psm12) of the applied decimal digits and a carry detector 38 producing an absolute carry such as Dmk, which is " 1 " whenever the partial sum of the decimal input digits is ten or greater and a conditional carry such as Rmk, which is " 1 " whenever the partial sum is nine or greater. The absolute and conditional carry signals are fed to a carry propagation network 24, together with a " zero order carry " from a circuit 23, which carry may be end-around array or an input from a lower rank register in the case of a double length operation, the network 24 producing correct carry signals Cm1-Cm12, signals Cm1-Cm11 being incorporated in circuits 26 with the partial sum signals Psm1-Psm12 to produce final sum output digits Sm1-Sm12, the signal Cm12 being an " overflow " digit. All the circuits employ parametrons each of which is supplied with signals belonging to one of three overlapped subclock phases (Fig. 2, not shown), the phases being labelled I, II, III in Fig. 4 and the complete addition being effected in two cycles each of three subclock phases. Each partial adder circuit 22 comprises four sub-circuits, each producing one of the four binary coded decimal digits of the partial sum; the circuit for producing the " 2 " bit in the 8-4-2-1 code being shown in Fig. 6. The connections in the sub-circuits are such that if the sum of the two input digits is ten or more, ten is subtracted to produce the correct output partial sum digit. Each carry detection circuit 38 (Fig. 9, not shown) comprises two levels of parametron circuits coupled to produce the required absolute and conditional carry signals. The carry propagation circuit 24 (Figs. 10A, 10B, Fig. 10A only shown) comprises an array of parametrons fed by the parametrons RM1, DM1 which provide the conditional and absolute carry signals. The zero order carry Cm0 is produced by the " carry in " parametron Pcin after delays at parametrons XMO, CMO. The first order carry Cm1 is formed from the equation by means of parametron Xm1, the output of which is delayed at parametron CM1 to produce the required carry signal. The second order carry Cm2 is formed from the equation the interdependence of the D and R signals of the same order enabling the inputs to the parametron XM2 to be reduced to those shown. The various higher order carries are produced by the illustrated network of parametrons, the " X " and " Y " parametrons (and " W " and " Z " parametrons in Fig. 10B, not shown) being effective in grouping the carries from various lower orders. The carry incorporation circuits 26 for each of the orders 1-9 are as shown in Fig. 11 and comprise parametrons arranged to combine, for each order the partial sum signal with the carry signal for that order. The carry incorporation circuits 26 for orders 10-12 are described with reference to Fig. 12 (not shown).