Patent GB-1221802-A (GB)
Title: Means and techniques useful in blanking interference
IPC: G01S13/78
Filed: 1968-02-08
Abstract: 1,221,802. Pulse radar. WHITTAKER CORP. 8 Feb., 1968 [25 April, 1967], No. 6396/68. Heading H4D. In an interference blanking system wherein received successive pulse trains contain synchronous pulses and unwanted asynchronous pulses, said trains are applied to the input of a digital memory system controlled by clock means, where the pulses are stored in accordance with the timings of their leading edges, and are delayed for a time commensurate with the repetition period of the trains. Input pulses are compared with output pulses from said memory system on a pulse-to-pulse basis by means which gives an output when there is a true co-incident condition. As described with reference to a secondary radar system for recognizing responding targets (I.F.F.), video or reply pulses applied to a terminal 100 are processed in a pulse processor 106 comprising a quantizer 108, an 0À2 microsecond delay circuit 110, an AND gate 112, a differentiator 114, an 0À6 micro-second delay circuit 116, an AND gate 118, and an OR gate 120. The delay line 110 in combination with the gate 112 eliminates impulsive noise signals, and the differentiator 114 produces an output of sharp pulses or spikes from the leading edges of the reply pulses. The delay circuit 116 in combination with the gate 118 ensures that two separate spikes are produced from two nearly overlapping pulses. The output of the processor 106 is connected to the set input terminal of a flip-flop circuit 130 having its output terminal connected to the input terminal of a shift register memory system 126. The flip-flop 130 is reset by a signal from the first cell of the shift register 126 as it assumes a binary "one" condition, said signal being differentiated by a differentiator 132. The shift register has a number of storage cells determined by the operating range of the radar, and it is stepped by pulses from a 1 Mc/s. clock. The video reply pulses at the terminal 100 are also applied to a tapped 22À0 microsecond delay circuit 160, and to a mode tag decoder 161 which is operated by the interrogation pulses to start the clock and select a particular shift register memory system 126 for use, there being one of the latter for each mode, said modes being distinguished by the time spacing between the two interrogation pulses. Signals read out from the shift register 126 on lead 136 are fed through a pulse stretcher 140 to one input of an AND gate 142 and to the input of an inverting amplifier 146. The other input of the AND gate 142 is connected to the output of the pulse processor 106, and co-incidence of pulses therefrom, and from the shift register memory system 126, produces output from the said gate 142, which sets a flip-flop 150 so that it sends a pulse to one input of an AND gate 102. The other input of the gate 102 is connected to the input terminal 100 via a delay circuit 154 (to compensate for delays in the circuit 110 and elsewhere) and co-incidence of pulses at the two inputs provides output at a terminal 104. The re-set terminal of the flip-flop 150 is connected to the output of an OR gate 158, one input of which is connected through a delay circuit 168 to the output of the inverting amplifier 146, and the other output of which is connected to one input of an AND gate 162. The other input of the AND gate 162 is connected through an inverter to the output of the AND gate 102. The above embodiment is a single defruiting system, and a second embodiment is also described which is a double defruiting system featuring a comparison between an incoming pulse train and the two corresponding pulse trains immediately preceding it (Fig. 4, not shown). In this, a single shift register memory system only is provided for each mode as in the first embodiment, and additional equipment generates a tag signal if a first and a second pulse train correspond. The AND gate providing the final output has three inputs, one of which is connected to the tag signal means, the other two being connected to the incoming signals and to the output of the shift register memory system. Thus, if there is correspondence between an incoming third pulse train, a second pulse train read out from the shift register memory system, and a first pulse train (i.e., a tag signal present) all inputs of the final AND gate are activated, and it provides an output which is doubly defruited.