Patent GB-1136314-A (GB)
Title: Data processing systems
Inventor: DAVIDSON EVAN EZRA
IPC: H03K17/64
Filed: 1966-03-29
Abstract: 1,136,314. Magnetic matrix memory. WESTERN ELECTRIC CO. Inc. 29 March, 1966 [31 March, 1965(2)], No. 13744/66. Heading G4C. [Also in Division H3] A selection circuit for a memory comprises two selection matrices each having a plurality of individually actuable circuit paths including two state switchable means for actuating one of the paths, means for supplying drive current pulses to the actuated path and means in one of the paths for indicating that the drive current supplied to the path is less than the full drive current pulse supplied by the means for supplying. In one embodiment (Fig. 3) a matrix driver supplies current pulses to row elements 39, 40 on line 53 and to column elements 41, 42 on line 56 of a memory row selector. A particular transistor 49, 50 is enabled in the row elements and a particular transistor 51, 52 is enabled in the column elements to allow a read or write pulse to pass through load 33, 36, 37 or 38 and operate the required row of the memory. A similar unit (18, Fig. 1, not shown) operates the columns. A read drive pulse thus passes along line 53, operates cores 58, 57 and then passes along line 39 for instance. To do this the pulse passes through core 57 again in such a manner as to reset it. The pulse, via diode 43, the transistor switch and diode 33R, for instance, passes load 33, enters column, 41, passes through the switch 51, through core 59, core 60, core 59 again and returns to the matrix driver. Thus at the end of a correct operation two cores 58, 60 are set and two are reset. Each read or write pulse is followed by an interrogate pulse (Fig. 2), formed by applying the read and write pulse to monostable flip-flops (23, 26 Fig. 1, not shown). The interrogating pulses are of the same polarity but of smaller magnitude than the read or write pulse and have sufficient current only to switch the cores 57, 58, 59, 60. The interrogation pulses are fed to a loop 61 which traverses all the cores. The pulses thus set any row or column check cores that have not already been set. The switching of the row cores is picked up on loop 62 and fed to a detection circuit 27, with a similar operation occuring to the column check cores. The pulse picked up is rectified, amplified and supplied to transistor 69, which is only allowed to conduct during the interrogate period by means of transistors 76, 77, 78 and lines 70, 71. For normal operation a pulse is supplied via amplifier 67 to transistor 69 which conducts and indicates correct operation. Certain faults which may occur in the translator or in the selection matrix cause the drive current pulses to be supplied to two rows or two columns. In which case, for instance on a read pulse the full current passes first through cores 57, 58 then the current divides and only half the full value passes through the cores the second time. This is less than the current required to reset the cores. The current passes through the matrix, is recombined in one column, sets one core 60 and sets and resets the other core 59. Thus on interrogation the column check circuit 32 is correct but since cores 57, 58 are both set there is no output on line 62 and the detector shows a fault condition. In a second embodiment (Figs. 4, not shown, and 5), varistors are used in place of the check cores. Each varistor is coupled to the primary winding of a transformer, the secondary windings being coupled in series to the detection circuit, such that the voltages developed across the secondaries of the column transformers 156, 157 oppose the voltages developed across the secondaries of the row transformers 156, 157. Under normal circumstances only one row varistor and one column varistor are raised to their high impedance state by the drive current and their voltages received in the detection loop 55 oppose each other. If a fault causes two columns and one row or two rows and one column to conduct then the voltages produced in the loop unbalance and the detection circuit 122 shows a fault condition. The detection circuit is illustrated in detail, Fig. 7, not shown, and includes a source of pulses for checking amplifier operation. The secondaries of the rows of the vertical and horizontal selection matrices may be connected in series and in opposition to all the column secondaries of the selection matrices as illustrated in Fig. 6 (not shown) to check against an open circuit fault as well as the faults previously discussed.