Patent GB-1187242-A (GB)
Title: Improvements in or relating to Electronic Computers
IPC: G06F7/38
Filed: 1967-03-22
Abstract: 1,187,242. Multiplication; ring counters. ANKER-WERKE A.G. 22 March, 1967 [29 Sept, 1966], No. 13360/67. Heading G4A. An electronic computer performs multiplication by repetitive addition, utilizing a columnselectable core-matrix " accumulator " for multiplier, intermediate results and product, decrementing of multiplier digits being associated with a column jump in the column selection in the opposite direction to the selection of successive columns otherwise used, under control of a step counter. 2-out-of-6-coded decimal digits can be supplied serially by decimal digit, parallel by bit, from one of two factor stores (FD, FE) or a mechanical accounting machine, via a decoder CE, to one input of an adder matrix DA, and from a so-called accumulator AK, via a further decoder KE (capable of complementing its input) to a second input of the adder DA, the adder output being recoded at CW before storage in the accumulator column (see below) from which the corresponding adder input came. The accumulator AK is simply a core matrix store having 30 six-bit columns S1 to S30 for holding respective decimal digits in 2-out-of-6 form. Two ring counters RZ5, RZ6 address any one of the columns via a 5X6 driver core matrix 13, the order of addressing corresponding to the order of numbering S1 to S30, the columns being positioned in the order S1, S16, S2, S17, S3, S18... S15, S30 as shown. Each pair of adjacently positioned columns has a respective marker core M1 to M15, addressed with each column of the pair, e.g. marker core M1 corresponds to columns S1 and S16. Initially columns S17 to S1 store the multiplier, lowest order in S17, columns S2 to S16 being empty since they are to be used for the successive partial products (though these assignments could be displaced cyclically). Columns S2 to S16 are addressed in turn, in synchronism with advance of a ring counter ZZ from 1 to 15. When ZZ equals 15, the addressed marker core M1 is set to signal the end of the multiplication process later. When ZZ equals 16, the currentlyaddressed column S17, holding the lowest order digit of the multiplier, is tested at gates 36, 59, 35, 34 to see if it is zero or non-zero. If it is non-zero, OR gate 36 and AND gate 35 give outputs, causing: (a) 9 to be added to the digit (with suppression of carry) by pulsing line 38, this being equivalent to subtracting one, (b) the multiplicand to be supplied, after a delay, via decoder CE, (c) the states of the rings RZ5, RZ6 to be stored in respective stores and then returned but with the state of RZ6 incremented by 3 so that the rings RZ5, RZ6 now address the column 15 columns before, i.e. in this case S2, (d) ZZ to be set to position 1. The multiplicand is now added serially by decimal digit to the contents of columns S2 to S16, the result digits being restored in the same columns, in synchronism with states 1 to 15 of ZZ. At ZZ equals 16, the lowest order digit of the multiplier is tested again and if non-zero the above operation repeats. When the digit is zero, AND gates 59, 34 are enabled but have no effect since the marker core M2 for the addressed column S17 is not set. The rings RZ5, RZ6 continue to cycle, next addressing column S18 which holds the next to least significant digit of the multiplier. If this is zero, the rings RZ5, RZ6 select the next multiplier digit and so on until a non-zero multiplier digit is reached. When this happens, gates 36, 35 are enabled causing steps (a) to (d) above to take place. Thus the multiplicand is added in again, with successive decrementing of the multiplier digit, but since step (c) caused the rings RZ5, RZ6 to address the column 15 columns before the multiplier digit considered, as the location to be incremented by the first digit of the multiplicand, the appropriate shift to high order is achieved. When a zero multiplier digit is reached whose marker core is set, i.e. the digit in column S1 with marker core M1, enablement of gates 59, 34 causes AND gate 60 to stop the multiplication. Ring counters RZ5, RZ6.-Fig. 4 shows ring counter RZ5 comprising magnetic cores K1 to K5, and its associated store comprising cores KI to KV. The counter is preset by a pulse on one of lines L1 to L5 which sets the next core K2 to K1 respectively. The counter is incremented by pulses applied via differentiator DS to reset the set core thus rendering conducting the corresponding transistors 43, 44, the former sustaining the pulse produced by the core and used to set the next core, and the latter pulsing the corresponding output line 27. The count can be transferred to the associated store KI to KV and the counter cleared by pulsing lines 52, 53 simultaneously with the pulse from differentiator DS, thus setting that one of the cores KI to KV corresponding to the core KI to K5 which would have been set by the pulse from DS if line 52 had not been pulsed. By then pulsing line 54, the set core KI to KV is reset and via an associated transistor 45 and connections such as 56 sets one of the counter cores K1 to K5 so that the count is at the value it had before the transfer. The six-stage ring counter RZ6 is similar except that the count is reset to its previous value plus 3 on resetting of the counter from its store.