Patent GB-769726-A (GB)
Title: Improvements relating to digital calculating apparatus
IPC: H03M7/12
Filed: 1954-12-21
Abstract: 769,726. Digital electric calculating-apparatus. GENERAL ELECTRIC CO. Dec. 21, 1954 [Dec. 21, 1953], No. 36936/54. Class 106 (1). In electronic digital calculating apparatus for converting a munber from a first to a second radix, the number is divided by a first radix number equivalent to the highest power of the base of the second radix which will give a whole number quotient, the remainder is divided by a number equivalent to the next lower power and so on, the successive quotients corresponding to the digits of the number in the second radix. As described, the divisions are performed by repeated subtraction. In the binaryto-decimal converter shown, the binary number to be converted is entered on parallel lines 11 into an accumulator 10 comprising stages 25a-25q and a " sign " stage 26 each comprising an Eccles-Jordan type bi-stable counting trigger circuit and associated carry trigger circuit and gates. The conversion is started by a pulse on line 34 which is applied over " complement " line 28 to the accumulator to switch over all the stages to their opposite state, and over line 35 to switch over bi-stable trigger circuit 37 so that it opens gates G1 and G2. Gate G1 allows regular pulses on line 43 to pass to one of lines 30-33 selected by resistor matrix 45 controlled by bi-stable cascade-connected trigger circuits 49, 48. Initially, line 30 is selected whereby each pulse is passed via cathode follower 12 to a binary counter 17 comprising four cascadeconnected trigger circuits, and to lines 16 connected to such stages of the accumulator 10 as to cause the binary equivalent of 104 to be entered therein. Since the number in the accumulator was complemented, this entry is effectively subtracted and such subtractions continue until an " overdraft " pulse is transmitted from stage 26 over line 27. This pulse, after delay in circuit 55 is passed through gate G2 to line 28 to complement the number remaining in the accumulator, and over line 47 to the input of trigger 49 to cause the matrix to select line 31. The pulses from 43 are then passed through cathode follower 13 to a counter 18 and to further lines 16 to cause 10<SP>3</SP> to be entered in the accumulator. Similarly each subsequent pulse on line 27 causes a re-complementing of the remainder in the accumulator, and switching of circuit 49, 48 to cause the next lower power of 10 to be entered over lines 16. When matrix 45 is switched to the last line 33 (corresponding to entry of 10<SP>1</SP>) it allows the next pulse on 27 to pass also via resistor 58 and line 59 to reset trigger 37 which then re-closes G1 and G2 and opens gate G3 so that the output from delay 55, as well as being to triggers 49, 48 to reset them to the initial state, is passed to line 29 to clear the accumulator. The counters 17, 18, 19, 20 corresponding to the successively decreasing powers of 10, and accumulator stages 25a-25d, which will hold the remainder corresponding to the unit's decimal digit, are connected to receding matrices 34-38 respectively, each of which marks one of ten output lines corresponding to a digit of the converted number. Owing to the method of calculation employed and the repeated complementing of the accumulator amount, alternate counters, starting with 17, are assumed to count forwards beginning at " 0 " and to count backwards beginning at " 9 " respectively. The matrix output lines may be connected to neon indicating tubes or printing mechanisms. In the latter case, the output from trigger 37 when reset is applied over line 64 to a trigger 65 to cause actuation of the printer. The counters 17-20 are subsequently cleared by an output on lines 61, 62 from trigger 48 when the latter is reset. A more detailed diagram including circuit details of the counter and accumulator stages is given.