Patent GB-1193198-A (GB)
Title: Bistable Trigger-Circuit
IPC: H03K3/037
Filed: 1967-11-27
Abstract: 1,193,198. Transistor pulse circuits. PHILIPS ELECTRONIC & ASSOCIATED INDUSTRIES Ltd. 27 Nov., 1967 [29 Nov., 1966], No. 53822/67. Heading H3T. A bi-stable trigger circuit having complementary outputs Q, Q and receiving an input D and clock pulses CP and having a plurality of directcoupled logic elements such as NOR gates N1 to N6, some of which N1-N4 are reciprocally coupled to form a switchable storage network, also has further logic elements such as AND gates U 7 , U 8  and a NOR gate N 9  arranged between an output stage N 5 , N 6  and an input stage, which may be the storage network N1-N4; the threshold voltages of at least some of the elements N1-N6, and of the further gate element 9, being selected to prevent, in conjunction with blocking action of the further elements (AND gates) U 7 , U 8 , generation of unwanted pulses by the clock pulse triggering edge, and to prevent any unwanted pulses generated during the non-triggering edge from reaching the output Q, Q. The circuit is designed to respond to slow edged clock pulses, the selected thresholds avoiding erroneous triggering therefrom. The circuit of six NOR gates N1-N6 without the further gates U 7 , U 8 , N 9  is said to constitute a known flip-flop (Fig. 9, not shown). Considering a slow edged clock pulse CP, Fig. 16, whose falling edge is assumed to be the triggering edge, the NOR gate N9 responds during the thresholds A1, A2, and the NOR gates N3, N4 during the thresholds B1, B2. Supporting a "1" to exist at the outputs of N3, N6, N9 and U7, and the complementary output Q to be connected to the input D, the changes shown in Fig. 16 happen during the rising and falling clock pulse edges. During the A1 period, N9 output becomes "0" and consequently AND gate U7 output falls to "0". During the B1 period N3 output falls as CP rises, so that of the inputs to N4, the right hand one is unchanged at "0" but the other two change in opposite directions and will pass through a common intermediate level which might appear to the gate N4 to be "0". Consequently N4 output goes to "1"; as soon as CP rises sufficiently further to be an unambiguous "1" the gate N4 reverts to "0", and thus a short pulse is produced. This pulse, which would in the arrangement of Fig. 9 (not shown), have changed the states of the cross-coupled output gates N5, N6 (Q, Q, Fig. 11, not shown), is prevented from so doing according to the invention by the AND gate U8 which was disabled during the A1 period. Considering the falling edge of the clock pulse CP, with a "1" at N1, N6 and "0" elsewhere, N4 output becomes "1" during the B2 period, and during the A2 period N9 output becomes "1". Now U8 has two "1" inputs and its output therefore becomes "1" to change the state of the output gates N5, N6. Without the AND gate U8, however (Fig. 9, not shown) the rising N4 output produced by the falling CP, the other two inputs to N4 being "0", might at some intermediate voltage become sufficient to trigger N5, N6 so that a "0" appears at the input D of N2 before the output of N4 has become an unambiguous "1". As this N4 output is fed back to the second N2 input, its level might appear to N2 to be a "0" and consequently N2 output becomes "1". This causes N4 output to revert to "0" and the chains of gate responses is reversed. Consequently a short pulse at N2 appears, (Fig. 12, not shown) and instability and possibly oscillation in the outputs Q, Q may occur. By making the circuit responsive to input D variations only during the short period B2 (B, Fig. 17, not shown) of the clock pulse cycle, the advantages of A.C. coupled logic is achieved, namely that the sequence of input signals and clock pulses is relatively uncritical, together with the advantages of D.C. coupled logic that slow edges can be used, permitting resistive coupling and integrated circuits to be employed. The rising edge of the clock pulse may be used, alternatively, for triggering. Avoidance of spurious pulses due to erroneous response to slow edges, in arrangements not using the invention, is described with reference to a J-K flip-flop (Fig. 4, not shown) and this is said to be known. Some of NOR gates (N3, N4, N9) of this circuit are said to have thresholds. The clock pulses are applied to AND gates (U1, U2) and not to a cross coupled storage network as such, and the circuit has the disadvantage of a relatively short period (t u , Fig. 5, not shown) of insensitivity to input signal variations, and therefore the input signal (J, K) and clock pulse (CP) sequence is more critical.