baber/WOPTO huggingface dataset:
Patent TW-428232-B (TW)
Title: Electrode structure of semiconductor capacitor
Inventor: CHEN HUNG-NAN
IPC: H01L21/28
Filed: 1999-03-01
Granted: 2001-04-01
Abstract: A dielectric layer is formed on the substrate, which includes a contact channel for communicating the upper surface of the dielectric layer down to the upper surface of the substrate, and a first conductor filled in the contact channel and connected to the substrate. A 3-dimensional second conductor is formed on the dielectric layer. The bottom side of the second conductor is connected to the first conductor, The second conductor has at least an inner surface and an outer surface. The outer surface has a hemi-spherical grained (HSG) silicon structure, and the inner surface is substantially of a smooth structure. Because the HSG silicon is only formed on the outer surface of the 3-dimensional electrode and the inner surface has a smooth simple structure without HSG silicon, the inner portion of the electrode will not be filled due to the growth of the HSG silicon. Therefore, it is applicable to be applied to manufacture smaller electrodes while maintaining the feature of high capacitance, so as to satisfy the requirement for miniaturizing the semiconductor device.
Patent TW-452876-B (TW)
Title: Method and apparatus for drying washed objects
Inventor: TANAKA AKINORI
IPC: H01L21/00
Filed: 1999-04-14
Granted: 2001-09-01
Abstract: A drying apparatus (10) for washed objects (50) capable of drying the objects (50) in a reduced period of time, thus effectively preventing contamination of the objects (50) during drying thereof, and attaining energy saving and a reduction in consumption of chemicals used. Mist of an organic solvent (34) is generated by means of an ultrasonic wave in an organic solvent mist generating tank (30) and the objects (50) are immersed in a pure water tank (20), the pure water tank (20) and organic solvent mist generating tank (30) are then operated to communicate with each other to discharge pure water and place the objects (50) in an atmosphere of the organic solvent mist, and then nitrogen gas is fed to the pure water tank (20) to purge the organic solvent mist with the nitrogen gas.
Patent TW-436370-B (TW)
Title: A carrier head for chemical mechanical polishing a substrate
Inventor: ZUNIGA STEVEN
IPC: B24B37/30
Filed: 1999-05-12
Granted: 2001-05-28
Abstract: A carrier head for a chemical mechanical polishing of a substrate, comprising: a base; and a flexible membrane extending beneath the base to define a pressurizable chamber, a lower surface of the flexible membrane providing a mounting surface for applying a load to a substrate, the flexible membrane including an inner portion and a lip portion surrounding the inner portion, the lip portion positioned and arranged such that, when a substrate is positioned against the mounting surface and the chamber is evacuated to pull the inner portion of the flexible membrane away from the substrate, the lip portion will be pulled against the substrate to form a seal therebetween.
Patent TW-425573-B (TW)
Title: Arrangement to attenuate the cross-talk in the word-lines of dram-circuits
Inventor: BROX MARTIN
IPC: G11C11/408
Filed: 1999-05-18
Granted: 2001-03-11
Abstract: This invention relates to an arrangement to attenuate the cross-talk in the word-lines (WL), which basically extend parallel to one another, of DRAM-circuits (2), it includes a decoder (1), which is provided on a 1st end of the word-line (WL), and a holding-transistor (WNRST). On the second end, which faces the first end, of the word-lines (WL) is provided a pull-down element (3) acted as a noise killer, which reduces the potential of the word-line (WL) in stand-by-and hold-operation in an active adjacent word-line (WL).
Patent TW-413876-B (TW)
Title: Wire bonding method
Inventor: NISHIURA SHINICHI
IPC: H01L21/60
Filed: 1999-05-20
Granted: 2000-12-01
Abstract: The present invention is able to form a stable wire loop shape and a loop shape having high shape holding force. In this wire bonding method, after reverse operation, as shown in Fig. 1(b), a capillary 4 is made to ascend in a direction of a second bonding point G up to a D1 point of a slant upper part, as shown in Fig. 1(c). The capillary 4 is made to ascend up to a D point, as shown in Fig. 1(d), and reverse operation which moves the capillary 4 in the opposite direction to the second bonding point G is performed, as shown in Fig. 1(e). Then the capillary 4 is made to ascend up to an F point, as shown in Fig. 1(f).
Patent TW-410454-B (TW)
Title: Laminated semiconductor device
Inventor: YOSHIDA YUICHI
IPC: H01L25/10
Filed: 1999-05-24
Granted: 2000-11-01
Abstract: The object of the present invention is to provide a laminated semiconductor device that can dissipate the heat generated from the semiconductor chips on the module substrate, other semiconductor chips, mother board and heat sink fins; and, when the semiconductor chip is during operation, it can prevent unnecessary temperature rising of semiconductor chip. In order to achieve the purpose, the laminated semiconductor device of the invention comprises a mother board and a laminated module configured on the mother board. The laminated module comprises two or more modules that each module comprises a module board and a semiconductor chip configured on the module board; in which, forming at least one radiator hole or more on each module board and mother board that the radiator holes are made to face the semiconductor chip.
Patent TW-499512-B (TW)
Title: Method for heat treatment of silicon substrate, substrate treated by the method, and epitaxial wafer utilizing the substrate
Inventor: AIHARA KEN
IPC: H01L21/322
Filed: 1999-06-23
Granted: 2002-08-21
Abstract: There is disclosed a method for heat treatment of a silicon substrate produced by the CZ method by utilizing a rapid thermal annealer, wherein the heat treatment is performed under an atmosphere composed of 100% nitrogen, or 100% oxygen, or a mixed atmosphere of oxygen and nitrogen by heating the silicon substrate to a maximum holding temperature within a range of from 1125 DEG C to the melting point of silicon, and holding the substrate at that maximum holding temperature for a holding time of 5 seconds or more, and then the substrate is rapidly cooled at a cooling rate of 8 DEG C/second or more from the maximum holding temperature. In the method, the amount of oxygen precipitation nuclei in the substrate can be controlled by changing the maximum holding temperature and the holding time. The present invention provide a method for heat treatment of a silicon substrate produced by the CZ method by utilizing an RTA apparatus, which can provide a silicon substrate having a desired oxygen precipitation characteristic without controlling oxygen concentration in the silicon substrate, and an epitaxial wafer utilizing a substrate heat-treated by the method.
Patent TW-436787-B (TW)
Title: Semiconductor device
Inventor: TAIRA TAKASHI
IPC: G11C11/407
Filed: 1999-07-16
Granted: 2001-05-28
Abstract: This invention relates to a semiconductor apparatus and the subject is that synchronous type DRAM with multi-database structure controls the conducting current when the pre-charging current is supplied for the database bit line circuit to generate the conduction. The solving means includes the followings: multiple database circuits Bki, which is commonly connected with the individually possessed pre-charging power source line and individually has the same structure; the first pre-charging power source supplying circuit 211, in which the output node is connected with the pre-charging power source line and the work of supplying the pre-charging current starts when DRAM chip is conducted with power source; and the second pre-charging power source supplying circuit 212, in which the output node is connected with the pre-charging power source line and the work of supplying the pre-charging current starts when the pre-charging current of the first pre-charging power source supplying circuit is used to make the bit line raise to a constant voltage.
Patent TW-570959-B (TW)
Title: Fire-retardant resin composition and molded part using the same
Inventor: KOBAYASHI KAZUHIKO
IPC: C08L23/12
Filed: 1999-08-30
Granted: 2004-01-11
Abstract: There is disclosed a fire-retardant resin composition, which comprises: a thermoplastic resin component (A) of (a) a (hydrogenated) block copolymer mainly made of a vinyl aromatic compound and a conjugated diene compound as its components, (b) a nonaromatic-series softener for rubber, (c) an ethylene/alpha-olefin copolymer, (d1) an ethylene/vinyl acetate copolymer, an ethylene/(meth)acrylic acid copolymer or an ethylene/(meth)acrylate copolymer, (e) a polypropylene resin, and (f) a polythylene resin modified with an unsaturated carboxylic acid or its derivative; and (g) an organic peroxide, (h) a (meth)acrylate-series and/or allyl-series crosslinking aid, and a metal hydrate (B), wherein a specific amount of the metal hydrate (B) is one being pretreated with a silane coupling agent, and the resin composition is a mixture of the above formulation that is heated and kneaded at the melting temperature of the (A) or higher. There is also disclosed a wiring material and other molded parts, in which the resin composition is utilized.
Patent TW-426978-B (TW)
Title: Method of fabricating narrow bit line structure
Inventor: WU JIN-LUNG
IPC: H01L23/50
Filed: 1999-08-30
Granted: 2001-03-21
Abstract: This invention is about the method of fabricating narrow bit line structure and includes the following procedures. At first, an interpoly dielectric layer is formed on a metal oxide semiconductor field effect transistor (MOSFET). Then, a landing pad is formed in the interpoly dielectric layer. The first polysilicon layer, a tungsten silicide layer, a silicon-oxy-nitride layer and the second polysilicon layer are sequentially formed on the interpoly dielectric layer. The defined photoresist layer is formed on the second polysilicon layer. The defined photoresist layer is used as a mask to etch one part of the second polysilicon layer. After that, the defined photoresist layer is stripped off and a polysilicon spacer is formed in the sidewall of the second polysilicon layer. A silicon oxide layer is deposited on the second polysilicon layer and is followed by the etch-back of the silicon oxide layer to expose the second polysilicon layer. The silicon oxide layer is used as a hard mask to etch the second polysilicon layer, the polysilicon spacer, one part of the silicon-oxy-nitride layer, one part of the tungsten silicide layer, and one part of the first polysilicon layer to expose the interpoly dielectric layer. The silicon oxide layer on the silicon-oxy-nitride layer is stripped off. At last, the narrow bit line structure is formed on the landing pad.
Patent TW-456128-B (TW)
Title: A method of frequency domain filtering employing a real to analytic transform
Inventor: TAL NIR
IPC: G06F17/10
Filed: 1999-11-04
Granted: 2001-09-21
Abstract: The present invention discloses a novel scheme of performing frequency domain filtering that does not require a Hilbert transform and which is faster than equivalent FIR filtering schemes. Such a scheme has applications in implementing filters in voice band modems on OSP platforms and in numerous other applications as well. The scheme of the present invention is shown to be superior in term of CPU resource consumption and memory storage space when compared with an equivalent implementation using prior art time domain convolution techniques. The scheme of the present invention permits the delay buffer in the far end echo canceler to store the signal in real format rather than complex format, thus reducing memory requirements by half. The present invention implements a real to analytic fast convolution in the frequency domain which uses zero CPU resources.
Patent TW-432831-B (TW)
Title: Radio communication system
Inventor: HUNT BERNARD
IPC: H04J3/16
Filed: 1999-09-23
Granted: 2001-05-01
Abstract: A method of operating a radio communication system in which secondary stations use dedicated time slots to request services from a primary station. A secondary station wishing to request a service sends a request in every time slot allocated to it until it receives an acknowledgement from the primary station. The primary station can use combining techniques on multiple time slots to identify the presence or absence of a request from a secondary station with improved accuracy.
Patent TW-452831-B (TW)
Title: DRAM-cells arrangement and its production method
Inventor: WILLER JOSEF
IPC: H01L21/8242
Filed: 1999-09-27
Granted: 2001-09-01
Abstract: The DRAM-cells arrangement has folded bit-lines. Memory-cells can be produced with an area of 4F<SP>2</SP> and are arranged in columns and rows, wherein the bit-lines extend parallel to the columns. The 1st word-lines contact each second memory-cell which is adjacent along one row. The 2nd word-lines contact the other memory-cells. Both word-lines extend parallel to the rows. One of the 1st word-lines and one of the 2nd word-lines overlap one of the rows. The word-lines and the bit-lines are mutually separated through the isolation layers (6, 11), isolation-regions (I1, I2) and isolation-spacer (Sp1, Sp2). The generation of the contact-area of the word-lines and the bit-lines is partly carried out self-adjustedly.
Patent TW-430974-B (TW)
Title: Manufacturing method for dual damascene structure of semiconductor chip
Inventor: CHEN KUEI-SHUN
IPC: H01L23/522
Filed: 1999-10-08
Granted: 2001-04-21
Abstract: The present invention is a manufacturing method for dual damascene structure on semiconductor chip surface. The semiconductor chip comprises a substrate, a conductive layer, a passivation, a first dielectric and a second dielectric that are sequentially formed on the substrate. The method comprises: firstly using a dry etching process to remove the second dielectric on the conductive layer to form a hole reaching the surface of the passivation; next, forming a negative photoresist on the semiconductor chip surface and filling up the hole; then, using the lithography process to remove the negative photoresist in a predetermined area above the hole and within the hole to form a linear opening; then, etching the second dielectric under the linear opening to reach the surface of the first dielectric to form a linear shallow trench; and, removing the photoresist and the passivation at the bottom of the hole until reaching the surface of the conductive layer; finally, depositing a metal layer and performing a CMP process so as to simultaneously form the dual damascene structure having metal wire and plug on the surface of the semiconductor chip.
Patent TW-421622-B (TW)
Title: Polishing method for wafer and holding plate
Inventor: KOBAYASHI DAISUKE
IPC: B24B37/30
Filed: 1999-12-31
Granted: 2001-02-11
Abstract: A polishing method for wafer, comprises the steps of: adhering a wafer to a wafer adhesion part of a holding plate through a wax, and rubbing the wafer with a polishing pad, wherein grooves are formed on the wafer adhesion part and extend to the outside of the wafer adhesion part.
Patent TW-409062-B (TW)
Title: The structure of golf ball club head and its manufacturing method
Inventor: LIN JUNG-CHIAN
IPC: A63B53/00
Filed: 2000-01-07
Granted: 2000-10-21
Abstract: The purpose of this invention is to provide a golf ball club head structure and its manufacturing method, which can adjust the weight distribution of the rod head by utilizing the balance weight value with nimble on the complex curve plane of the golf club head or in corresponding to the consumers' demand, which can be easily fabricated and could reduce its cost. Thereby, this invention has: the plate processing process; the process of preparing the balance weight material and the sinister agent and the mother material completed by plate processing; the process of combining the mother material, the sintering agent, and the balance weight material; the sinter process of sintering and melting the assembled and completed work; and the formation process for applying the bending formation which is applied in the structure balance weight and the ornament design of golf ball club head.
Patent TW-I228241-B (TW)
Title: Opaque rib structures for display panel
Inventor: LABORDE PASCALE
IPC: C03B19/09
Filed: 2000-02-15
Granted: 2005-02-21
Abstract: Methods of forming plasma addressed liquid crystal display ribs are disclosed. An exemplary method includes introducing a glass paste which includes a curable medium into cavities formed in an intaglio collector to define rib structures, which are from the collector to a surface of the substrate, and removing the curable medium from the rib structures on the substrate surface to generate pores in the rib structures. The substrate having rib structures is then dipped into a solution containing an opaque pigment which is absorbed into the rib structure. Another method includes forming a temporary mask on portions of a surface of a substrate, depositing a layer of a glass paste having a curable medium and at least one pigment blended therein over the substrate and temporary mask, micro-molding rib structures from the glass paste on the substrate surface in areas between the masked sections, removing any residual layer of paste material present on the temporary mask, removing the temporary mask from the substrate, and firing the substrate with micro-molded rib structures thereon.
Patent TW-527230-B (TW)
Title: Fluorine-resin coating and the preparation thereof
Inventor: YAMADA KATSUYA
IPC: B32B15/08
Filed: 2000-02-19
Granted: 2003-04-11
Abstract: The invention provides a fluorine-resin coating having the good properties of all wear-resistance, damage-resistance, corrosion-resistance and blister-resistance and the preparation thereof. A fluorine-resin coating and the preparation thereof, characterized in that a fluorine-resin coating comprising of coating one or two fluorine-resin layer on substrate, the most outer layer consisting of tetrafluoroethylene/perfluoroalkylvinylether (PFA) copolymer having melt flow-rate of 0.2 to 10 g/10 min regulated in accordance with ASTM-D-3307, said PFA is in the amount of 20 to 100 weight % by the weight of total PFA layer, and having the thickness of 10 to 90 mum.
Patent TW-476722-B (TW)
Title: Switch for a bicycle transmission device
Inventor: ASSEL MARTIN
IPC: B62K23/06
Filed: 2000-03-29
Granted: 2002-02-21
Abstract: This invention relates to a trigger switch used for a bicycle transmission device, it includes an operation lever which is rotatably arranged around a middle axis fixed to the housing, to control several operation parts likewise rotatable in the housing and arranged around the middle axis, and it contains the roll-up nut used for a cabling rope. In addition, a release and support mechanism consisting of a first tooth-segment and a second tooth-segment, which is connected to the operation parts, and the release and support mechanic also consists of a release lever, which jointly functions alternately with the first tooth-segment and the second tooth-segment. Wherein, in the housing a from the release lever movable slot element is rotatable arranged, it jointly functions exchangeably with the first and the second tooth-segment. The advantages of the switch arranged according to the present invention lies in a greatly enhanced connectionability of the bicycle transmission device gear shift steps, not only with the operation lever but also with the release lever. Wherein the slot element is so connected with both the two levers, that the movement of a lever itself is not transmitted to another lever.
Patent TW-514719-B (TW)
Title: Flowmeter
Inventor: SHIBA FUMIKAZU
IPC: G01F1/00
Filed: 2000-05-10
Granted: 2002-12-21
Abstract: A flowmeter comprises a plurality of channels (13) between an input port (11) and an output port (12), switch means (14) for opening and closing the channels (13), measuring means (15) for measuring the flow rate of a fluid flowing through at least one of the channels (13), and control means (17) for controlling the switch means (14) and measuring means (15). The control means (17) includes gain control means (16) for correcting the gain of the measuring means (15) associated with a channel (13) stopped by the switch means (14).
Patent TW-493115-B (TW)
Title: Data exchange method for the message bus between TIB/RV and DMBX
Inventor: TZENG MING-DE
IPC: G06F15/00
Filed: 2000-05-18
Granted: 2002-07-01
Abstract: A method for connecting the DMBX message bus and the TIB/RV message bus in a semiconductor foundry. The DMBX message bus is used to connect the semiconductor processing equipment and the server, and the TIB/RV message bus is used to connect the process database PROMIS/TP. The DMBX-TIB gateway communicates the DMBX message with the TIB/RV message and dynamically combine the messages, and the operations for transmitting the commands and tracking the commands by the message content. The method is to use the SDT control panel to establish the procedure file in the configuration phase, and the procedures are conducted with the main procedures and the sub-procedures in the activation phase. The loop of the main procedure is receiving the DMBX message and the command from the SDT control panel, and converted into the TIB/RV object; the sub-procedure is receiving the TIB/RV message and converted to the corresponding mailbox. The DMBX-TIB gateway cannot only communicate different message buses, and also record the delivery content in the message for the following tracking and debugging.
Patent TW-498527-B (TW)
Title: Surface mount millimeter wave IC package
Inventor: ZIEGNER BERNHARD ALPHONSO
IPC: H05K1/02
Filed: 2000-07-13
Granted: 2002-08-11
Abstract: A packaged integrated circuit (10, 10a) which includes a multiple-layer interconnect (16, 16a) including a dielectric layer (32, 32a) disposed between a base layer (34, 34a) and a conductive transmission layer (36, 36a). The conductive layer (36, 36a) is electrically connectable to a substrate (11) and is electrically connected to an integrated circuit (18, 18a). The packaged integrated circuit (10, 10a) includes a base member (12, 12a) which engaged the base layer (34, 34a) of the multiple-layer interconnect (16, 16a).
Patent TW-474883-B (TW)
Title: Closable opening device for sealed packages of pourable food products
Inventor: LA CIACERA MAURO
IPC: B65D51/18
Filed: 2000-06-09
Granted: 2002-02-01
Abstract: A closable opening device (2) having a frame (15) defining a through hole (16) and fitted about a pierceable portion (4) of a sealed package (1) for pourable food products; a removable cap (17) cooperating with the frame (15) to close the hole (16); and a substantially tubular cutting member (18) engaging, in use, the hose (16) in angularly and axially movable manner, and having an end edge (40) in turn having, on the face, cutting means (41) cooperating with the pierceable portion (4) to open the package (1); the frame (15) and the cutting member (18) are molded in one piece in a preassembly configuration, wherein they are secured coaxially to each other by breakable connecting means (62).
Patent TW-474072-B (TW)
Title: Method and arrangements in a telecommunications system
Inventor: ANDERSSON SOEREN
IPC: H01Q3/26
Filed: 2000-07-28
Granted: 2002-01-21
Abstract: The invention provides an arrangement and a method, which facilitate the communication of radio communication signals generated during operation of a radio communication system. The invention utilizes lobe forming to reduce both transmitted and received interference. The invention relates to an antenna assembly, and an associated method, which facilitates the communication of radio communication signals generated during operation of the radio communication system, and which uses location technology to establish the direction of arrival (DOA) in order to continuously calibrate the phases of an antenna array, which allows the use of base band beamforming without a costly calibration scheme. Information concerning the position of a mobile station in relation to a base station is sent, spontaneously, periodically or on request, from a central station in the network to a base station.