Patent GB-1323231-A (GB)
Title: Time division switching systems
IPC: H04J3/20
Filed: 1971-04-19
Abstract: 1323231 Automatic exchange systems WESTERN ELECTRIC CO Inc 19 April 1971 [13 April 1970] 26733/71 Heading H4K In a TDM system wherein each line is provided with a storage device which is chargeable by speech signals and which is periodically connected to a bus common to a group of lines, two-way communication between two storage devices pertaining to different groups is effected by comparing their charges during a time interval when both are connected to their respective buses and then charging one while discharging the other one for a time dependent on the difference in their original charges. The length of a time slot is thus dependent only on the amount by which one speech sample level exceeds another so that more rapid scanning or, preferably, more channels per frame are possible. The system is maintained quasisynchronous by restricting the frame length within certain limits so as to reduce random noise that is introduced by asynchronous sampling.  In Fig. 1 subscribers 101 are grouped on a common bus 124 while trunks 103 are grouped on common bus 126. Details of active subscribers and trunks are maintained in a central control 140 and their line gates 110 and 111 are periodically opened by address signals transmitted on buses 144 and 146. Assume that gates 110-1 and 111-n have been opened at a time t 0  representing the start of a time slot. For a fixed period ending at t 1 , the charges on storage capacitors 107-1 and 108-n flow via buses 124, 126 into a differential amplifier in Timer circuit 133 (Fig. 3, not shown) so as to charge an output capacitor thereof to a level dependent on the difference in charge levels existing at t 0 . The output capacitor is gated to the amplifier by a brief pulse of duration t 1 -t 2  transmitted by central control over lead 170. At time t 2  the capacitor is gated to a pair of flip-flops one of which sets in dependence on the polarity of the charge thereon, i.e. on which capacitor 107, 108 initially had the larger charge. Consequently either constant current sources 120, 121 or 122, 123 are enabled over lead 137 so as to charge, discharge or discharge, charge respectively capacitors 107, 108. At the same time the output capacitor is charged or discharged by not shown constant current sources towards a reference level, which on being reached, causes the set flip-flop to reset and thus terminate at t 3  the enabling signal on lead 137 so as to stop the charging/discharging of the line and trunk capacitors. A brief pulse of duration t 3 -t 4  on leads 150, 151 opens gates 113, 114 so as to discharge any residual charge on the common buses 124, 126 prior to the commencement of the next time slot after a brief guard interval. As will be appreciated from the above the interval t 2 -t 3  is of variable extent depending on the intial charge difference on the line and trunk capacitors. In order to maintain some degree of synchronousness two embodiments are put forth. In one (Fig. 4, not shown), two ring counters are provided one of which is stepped by clock pulses and the other by time slot terminating pulses t 3 . A system of gates between the counters ensures that a time slot initiating pulse t 0  can only be provided if the clock pulse ring counter is ahead of or at worst is only one step behind the slot terminating pulse ring counter. In the other embodiment (Fig. 8, not shown) the number of time slot terminating pulses occurring during a timed interval is compared with a predetermined number of time slots, i.e. the maximum permitted number of channels in a frame, and a new frame is not permitted to commence even if equality is reached until the end of the timed interval. Of course the latter may be insufficient to achieve equality in which case a new timing interval is not started until all the channels of the frame have been sampled. Obviously all the timing requirements of this paragraph are based on the observation that all conversations mostly comprise silences so 'that many "active" channels are in fact devoid of information whereby many more can be fitted into a frame if the dwell time of the control circuitry on each channel is made dependent on the contents thereof. In another arrangement (Fig. 2) the stations and trunks are arranged in sub-groups having access to one common sub-bus which is connected to a negative constant current source and also via a sub-group gate to a group bus akin to bus 124 or 126. Each station and trunk also has access via another common sub-bus to a positive constant current source. Apart from consequential increases in the control address logic due to the need to simultaneously operate a larger number of gates the operation is similar to that already described.  The constant current sources (Fig. 7, not shown) each comprise a first conductive transistor having its collector-base diode reverse biased so that it supplies a constant current either to a normally-on saturated second transistor acting as a sink or to a normally-off third transistor acting as a gate. The source has a high output impedance.