Patent GB-1247800-A (GB)
Title: Method and apparatus for driving memory core selection lines
IPC: G11C11/06
Filed: 1969-03-13
Abstract: 1,247,800. Magnetic storage matrices; transistor circuit for switching inductive loads. GENERAL MOTORS CORP. 13 March, 1969 [18 March, 1968], No. 13184/69. Headings H3B and H3T. A drive circuit for a magnetic memory matrix comprises a gated pair of transistor switches, each including two opposite conductivity type transistors, connected at the opposite ends of a drive line to connect the drive line to receive current from a regulated source of current, the voltage across the drive line being initially clamped to enable the current in the line to rise rapidly and linearly to a predetermined level after which the clamp is removed and the current through the line is held at the predetermined level by the current regulator. The X- co-ordinate drive lines Xo to X 47  are arranged as shown in Fig. 2, two sets of switches one for reading RS1, RSO and one for writing WS1, WSO, being provided with the switches of each set arranged in an 8 x 6 matrix. Any one of the drive lines may be selected by addressing a pair of switches RS1, RS0 or WS1, WSO from an address register and the application of a read or write timing pulse RT or WT thereto. One drive line 11 and associated pair of switches RS1, RS0, i.e. 13, 14 are shown in Fig. 3. When address and timing control signals are applied to the T<SP>2</SP>L NAND gates 34, 36 transistors 50, 52 acting as constant current sources are switched on to drive transistors 42, 44 into saturation, and reverse bias diode 26 to remove the negative voltage applied to the upper end of the line 11 from regulator supply 16. A clamp diode 28 is still forward biased and holds the point A of current regulator 18, comprising a high gain differential operational amplifier connected in a closed feedback loop and a current sensing resistor, and the emitter of transistor 44 at a negative potential. The line is driven from the constant voltage produced by regulator 18 until the current supplied thereto from the stack supply 17 and the upper current switches attains the level of drive current required. As the line current increases the current from the regulator power supply 16 decreases proportionally to maintain the total current through regulator 18 at the regulator level. When the drive current has attained its final valve no more current is furnished through diode 28 from the regulator supply the current then flowing being that from stack supply 17 and switches 13, 14. At this point diode 28 is rapidly reverse biased and the emitter of transistor 44 rises rapidly in potential accompanied by an induced voltage spike at the lower end of line 11. Shunt termination circuit 22.-All the lines 11 of a co-ordinate axis are connected at point K to a shunt termination circuit 22 comprising a resistor 80 and switch 78 controlled by constant current source 72 and input gate 70, resistor 80 being connected to point A to which all of the lower line selection switches of the co-ordinate axis are connected. When the current in the drive line 11 has attained its required value circuit 22 is activated by applying an input signal representing a read or write time control signal to gate 70 resulting in transistor 78 being switched on so that resistor 80 is placed in shunt with line 11 and serves to damp overshoot and consequent ringing and voltages reflection on the lines resulting from a sudden change in potential thereon. Inactive line termination circuit 24.-All the lines 11 of a co-ordinate axis are connected at their lower ends L via a common inactive line termination circuit 24 to the current regulator 18 of that axis, circuit 24 comprising a T<SP>2</SP>L gate 82, a constant current generator 100, switch transistor 96 and resistors 92, 102. When the reacting or writing timing pulse terminates switches 13, 14 and shunt termination circuit 22 are disabled. At the same time T<SP>2</SP>L gate 82 is enabled causing transistor 96 to be activated and connect resistor 92 to point A and clamp diodes 26, 28 become forward biased to place the upper end of line 11 and the emitter of transistor 96 at the same potential. Resistor 92 is thus effectively placed in a closed decay loop for discharging the memory stack capacitance and preventing large induced voltage rings and consequent ringing upon turn off of the line. The diode 28 and circuit 24 maintain both ends of the line at the same potential to prevent the lines from leaking or recharging the line capacitance during memory idle periods.