Patent GB-910414-A (GB)
Title: Improvements in or relating to data processing machines
IPC: G06F3/08
Filed: 1959-05-25
Abstract: 910,414. Binary-decimal conversion. INTERNATIONAL BUSINESS MACHINES CORPORATION. May 25, 1959 [May 27, 1958], No. 17733/59. Class 106 (1). The binary equivalents of powers of ten are represented by magnetic cores connecting row and column lines in an array of conductor. The columns of the upper array (encoder) of Fig. 2 represent powers of two, the rows, powers of ten. In the second row of the encoder, for example, magnetic cores connect the second and fourth column conductor to the row conductor since 10 decimal = 1010 binary. The cores are threaded by a single sense line S and are switched by simultaneous energization of row and column conductors. A serial representation of the binary equivalent of a selected power of ten appears on sense line S through the action of a distributer 13 and pulse generators as described below. The binary equivalent of a decimal digit is obtained by accumulating in a word position of the lower array (memory) of Fig. 2 the binary equivalent of the order to which the digit belongs. The machine in which the encoder is incorporated is plugboard controlled with punched card data input and a data punch output and operates internally with signplus 30-bit words. The basic machine cycle is a scanning cycle divided into sixteen T-times during which the following operations are performed on two successive binary orders of two operands: read a binary order (X) of a first operand to an arithmetic unit (read X); regenerate X in the position from which it was read (write X); read the corresponding binary order (Y) of a second operand to the arithmetic unit where the operation required is performed (read Y); and write in the storage position previously occupied by Y the result of the operation (write Y). Both the encoder and memory are wired as shown in Fig. 4 to achieve this result. A and C are cores storing successive orders of the first operand, B and D, cores storing corresponding orders for the second operand. When the appropriate T-time is reached distributer 13 closes switches S1, S2; S4 and S5 are closed during read/write X; S4<SP>1</SP> and S5<SP>1</SP> are closed during read/write Y. The sense line is not shown. Assuming that each core stores a binary one, the pulse generators operate in pairs in the following order: G1, G3; G2, G4; G1, G3; G2, G4; G1, G4; G2, G3;. G1, G4; G2, G3; resulting in additive combinations of switching currents at cores A, A ; B, B; C, C; and D, D ; respectively. When it is not required write a binary one into a core, generator G2 does not operate, being controlled by the setting of an accumulator trigger in the arithmetic unit. In an encoding operation a row of the encoder is the first operand and the cores of the encoder are always regenerated. Decimal to binary conversion.-The decimal number is represented by single punches in columns of a card. Appropriate outputs of a column emitter are plugged to the rows of the encoder-the output energized when the units column of the card is passing the read brushes is plugged to the first row of the array, and so on. The same plugging selects a storage position of memory for the equivalent binary word. A counter is set to the complement on twelve of the value punched in the column passing the read brushes. The counter comprises four triggers operating in cascade and having the weighted values 1-2-4-4. A number of scanning cycles are now performed during each of which the contents of the row of the encoder corresponding to the column being read are added into the selected storage position. At the end of each cycle the counter is advanced by one until a count of twelve is reached whereupon the operation stops and the next column read. Binary to decimal conversion: data output.- When it is required to punch the contents of a storage location of memory, the binary data word is first converted to a decimal representation from which the punch relays are operated. The column of the card to be punched currently being operated on causes the corresponding row of the encoder to be subtracted a number of times from the contents of the storage location being read out. At each subtraction which is by complement addition, unless there is no end carry from the highest binary order the counter is advanced by one. When no end carry occurs the row of the encoder is added once into the storage location and the setting of the counter used to select one out of ten punch relays. Arithmetic unit.-This is not described in detail but the adder consists of two triggers, accumulator and carry. In addition, the binary digit of the first operand is entered in the accumulator trigger. The binary digit of the second operand is compared with the carry from the previous order and if these differ the accumulater trigger is complemented. Detailed control circuits are described with reference to Figs. 6a to 6j (not shown).