Patent GB-1498016-A (GB)
Title: Content addressable memory
IPC: G11C15/04
Filed: 1975-03-25
Abstract: 1498016 Content addressable memory NATIONAL RESEARCH DEVELOPMENT CORP 25 March 1975 [2 April 1974] 14531/74 Heading H3T A content-addressable memory comprises an array of binary memory cells arranged in rows and columns with an input conductor for each column and first and second control conductors for each row and each memory cell comprises a first MOS transistor 14 with its channel connected between the input conductor 18 and the second control conductor 20 and a second MOS transistor 16 with its channel connected between the input conductor 18 and the gate of the first transistor 14, the gate of the second being connected to the first control conductor 22, whereby in use the two states of each memory cell comprise the presence or absence of charge on the gate of the first MOS transistor 14. The substrate, not shown, is connected to a positive reference potential +V. If "match 0" is to be possible two such arrangements are used with separate input conductors (42, 44, Fig. 3, not shown), but with common first and second control conductors (20,22). As shown, the transistors are of the P channel enhancement type. As shown, the memory cell may be driven by a control cell 12. When an array of cells is used (Fig. 1, not shown) the control cell is shared in common by all the memory cells in a row. The main and second main control conductors 30, 32 are driven out of phase one always being at the positive reference voltage + V and the other at a negative voltage -V. The voltage on the first control conductor 22 depends both on the state of the main control conductors 30, 32 and on the voltage applied to the second control conductor 20, being either at +V or a value between + V and - V according to Table 1. The signals applied to the lines 18, 20, 30 and 32 in order to address the cell 10, the resulting signals on line 22 and, in the case of read and match operations, the output, are listed in Table I where X indicates "don't care". To write into a cell the main control conductor 30 must be negative and a 0 or 1 written by applying zero voltage at +V respectively to the desired column input conductor 18 while the first control conductor 20 of the desired row is also at zero voltage. To read from the cell the column input conductor 18 is at zero voltage and the first control conductor at + V and if a "0" is stored a current will flow in 18 from 20 while an absence of current shows a "1" is stored. Other functions are indicated in the table. The memory cell requires refreshing from time to time. The doubled cell (Fig. 3, not shown) has extra functions in addition to its ability to "match 0". In normal use the gate of one MOS transistor only would be charged at a time, thereby storing a logic 1 with one transistor (50) charged or a logic 0 with the other (46) charged. In addition both transistors can be uncharged to indicate "dont care", or both charged to indicate "match row inhibit" and this will prevent a match being achieved with any other cell in the same row. The voltage conditions necessary to provide these and other functions are presented in Table II (not shown).