baber/WOPTO huggingface dataset:
Patent TW-I224971-B (TW)
Title: Hydrophilic/lipophilic polymeric matrix dosage formulation
Inventor: VERGNAULT GUY
IPC: A61K9/24
Filed: 2001-04-30
Granted: 2004-12-11
Abstract: An oral dosage form comprising a pharmaceutical tablet of one or more layers, one of which carries a biologically active substance; the formulation of said tablet includes different percentages of hydrophilic and lipophilic polymeric materials, and adjuvant substances. The tablets of the present invention show a release rate which is independent from the amounts of active substance present in the tablet.
Patent TW-512290-B (TW)
Title: Dial navigation picture indication method
Inventor: CHEN SHI-TSANG
IPC: G08G1/0968
Filed: 2001-06-22
Granted: 2002-12-01
Abstract: The present invention relates to a dial navigation picture indication method, which uses the carrier with display screen in association with a navigation device to convert the driving navigation messages into an indication guiding the driving route data with a clock-like dial picture. The present invention uses the connection linkage with the navigation device, the wireless communication device, the navigation service center, or other information device providing the computed driving route information, and employs the driving route data transmitted from the navigation service center, or the driving route data computed by the active navigation program in the navigation device, or uses the connection between the information device and the navigation device to provide the computed driving route information. With the screen of the navigation device, the picture can exhibit an clock-like dial indication, so that each indicator represents each item of navigation information (such as the next turning intersection, the turning direction, the destination direction, and the distance and the orientation), and the limited screen space can be used to provide an easy-to-read navigation guidance.
Patent TW-517242-B (TW)
Title: Semiconductor circuit in which power consumption is reduced and semiconductor circuit system using the same
Inventor: UCHIYAMA YOSHINORI
IPC: G02F1/133
Filed: 2001-07-03
Granted: 2003-01-11
Abstract: A semiconductor circuit system includes a first signal line and n circuit sections (n is an integer equal to or more than 2), each of which has an input terminal and an output terminal. The input terminals of predetermined k ones (k is an integer satisfying 2 ≤ k < n) of the n circuit sections are connected to the first signal line, and the output terminal of a m-th one (1 ≤ m ≤ n-k) of the n circuit sections is connected to the input terminal of a (m+k)-th one of the n circuit sections.
Patent TW-I237808-B (TW)
Title: Method for calibrating tracking position of CD drive
Inventor: LI SUNG-HUNG
IPC: G11B7/09
Filed: 2001-08-16
Granted: 2005-08-11
Abstract: A method for calibrating tracking position of CD drive is provided to lock an optical pick-up head of a CD drive at a calibrated tracking position. The method comprises the steps of first performing an initial tracking procedure in accordance with a tracking error (TE) to lock the optical pick-up head at the initial tracking position; and then carrying out the tracking position calibration procedure to fine-tune the optical pick-up head to a calibrated tracking position approximating to the maximum value of the amplitude of radio frequency ripple (RFRP). The method can avoid the incorrect tracking position resulting from the error of TE signal to lock the optical pick-up head at the center of a correct track so as to improve the data read quality.
Patent TW-511164-B (TW)
Title: Method of improving gate oxide reliability
Inventor: SHIH WONG-CHENG
IPC: H01L21/28
Filed: 2001-08-17
Granted: 2002-11-21
Abstract: A kind of method for improving gate oxide reliability, which is suitable for use in a semiconductor apparatus, is disclosed in the present invention. At first, after cleaned by a diluted hydrogen fluoride (HF), a silicon substrate is undergone with a vacuum thermal annealing process; then, the second annealing process is conducted onto the silicon substrate in a deuteron gas (D2) environment. After that, a gate oxide layer is formed on the substrate and is followed by the third annealing process in the environment containing nitrogen gas and deuteron gas (D2) so as to increase the deuteron concentration at the interface between the gate oxide layer and the silicon substrate. At last, the gate electrode is formed on the gate oxide layer to complete the manufacture of semiconductor device. In the invention, the gate oxide layer reliability of the semiconductor device, which has been undergone with three times of annealing process, can be effectively improved.
Patent TW-576856-B (TW)
Title: Water-soluble monoazo dyes, their preparation and use
Inventor: ENGEL ALOYS
IPC: C09B29/30
Filed: 2001-09-20
Granted: 2004-02-21
Abstract: Dyes of the formula (1), in which M is hydrogen, ammonium, an alkali metal or the equivalent of an alkaline earth metal; X is sulfonyl or -COCH2O-; R1, R2 and R3 independently of one another are hydrogen, halogen, for example fluorine, chlorine or bromine, unsubstituted or chloro- or hydroxy-substituted C1 to C4 alkoxy, for example 2-chloroethoxy or 2-hydroxyethoxy, and the sulfo group is in position 3 or 4 to the NH group, their preparation, and their use for dyeing or printing carboxamido-containing materials.
Patent TW-554622-B (TW)
Title: Automatic phone receiving system
Inventor: LIAU YIN-LING
IPC: H04M1/64
Filed: 2001-10-19
Granted: 2003-09-21
Abstract: The invention relates to an automatic phone receiving system including a CPU, an external detection unit, an internal operation unit, an amplifier and an automatic receiving unit. The internal operation unit is used to switch to automatic answering switch, so that the system allows a caller to directly forward message to CPU for processing via the external detection unit. Further, an automatic receiving system is used to record the caller's voice tone. In addition to making use of the amplifier for directly broadcasting to the listener the automatic receiving unit will repeatedly play the incoming call if no one answers the call, such that the listener can call back.
Patent TW-515763-B (TW)
Title: Enhanced structure for guarding tires against punctures and bursting
Inventor: SHIU SHUEI-JEN
IPC: B60C17/04
Filed: 2001-11-06
Granted: 2003-01-01
Abstract: This invention relates to an enhanced structure for guarding tires against punctures and bursting, particularly a tire that although leaking or bursting due to damages resulted from punctures by sharp objects or knife edges, may continue operation safely so as to reach garages for services and maintenance, thereby eliminating the hardship and life risks of pushing cars so as to provide beneficial effects to the traffic safety of the general public.
Patent TW-535140-B (TW)
Title: Phoneme decoder
Inventor: YANG HUANG-LIN
IPC: G10L19/00
Filed: 2001-12-07
Granted: 2003-06-01
Abstract: The present invention provides a phoneme decoder, which uses the voice data encoded with three parameters in the voice data, such as pitch, root of mean square, and reflection of coefficients, for being composed as a voice signal. The phoneme decoder comprises: an initialization unit, a parameter loading unit, a smoothing unit, a composition unit, and a voice output unit. The initialization unit generates the initialization signal, and loads the three voice parameters, such as pitch, root of mean square, and reflection coefficients, into the smoothing unit. The smoothing unit receives the voice parameter data, and uses the interpolation method for smoothing, and transmits the processed voice parameter data to the composition unit. The composition unit composes the voice data according to the parametric sequence of pitch, reflection coefficients and root of mean square, and outputs the same to the voice output unit.
Patent TW-527293-B (TW)
Title: Occupant protective device of vehicle
Inventor: NAMIKI HIDEO
IPC: B60R21/261
Filed: 2002-03-13
Granted: 2003-04-11
Abstract: The object of this invention is to effectively restrict the bust, head and neck of an occupant in an occupant protective device of a vehicle in which the occupant is restricted by inflating a webbing. An upper part of an inflation part 43 of the webbing 30 of an air-belt device 25 is located and has a shape so as to protect the sides of the head H and the neck N, the bust B of the occupant can be restricted flexibly by the inflation part 43 in the head-on collision, the head H and the neck N of the occupant can be flexibly restricted in the side impact, and thus, the functions of a side airbag device and the air curtain device can be given to the air-belt device 25. In addition, the size of the inflation part 43 in the inflation is reduced from the upper part to the lower part, and the required capacity of an inflator 28 can be reduced by reducing the volume of the lower part of the inflation part 43 in which the required restrictive force can be obtained even when the size is reduced.
Patent TW-579434-B (TW)
Title: Inspection-microscope for several wavelength-ranges and reflection-reduction-layer for an inspection-microscope for several wavelength-ranges
Inventor: EISENKRAEMER FRANK
IPC: G02B1/115
Filed: 2002-03-28
Granted: 2004-03-11
Abstract: An inspection-microscope for several wavelength-ranges with at least one lighting-beam-path and at least one image-beam-path is given. The optical components, which are radiated through by the beams of all wavelength-ranges, in the lighting-beam-path and in the image-beam-path are provided with a reflection-reduction-layer, in which the reflection-reduced wavelength-regions of the visible VIS-wavelength-range is until 650 nm, the i-line is in lambda=365 nm and the ultra-violet DUV-wavelength-range is from 240 nm to 270 nm. The reflection-reduction-layer has a sandwich structure, which is composed of various material-combinations, such as M2/MgF2 or M2/MgF2/SiO2 or M2/MgF2/Al2O3.M2 is a mixture-substance of Fa.Merck, which is composed of La2O3.3.3Al2O3. The reflection-reduced optical components are composed preferably of Quarz-glass or CaF2.
Patent TW-536835-B (TW)
Title: Phosphor converted light emitting diode
Inventor: MUELLER GERD O
IPC: C09K11/77
Filed: 2002-04-01
Granted: 2003-06-11
Abstract: A method of fabricating a light emitting device includes providing a light emitting diode that emits primary light, and locating proximate to the light emitting diode a (Sr1-u-v-xMguCavBax)(Ga2-y-zAlyInzS4):Eu<2+> phosphor material capable of absorbing at least a portion of the primary light and emitting secondary light having a wavelength longer than a wavelength of the primary light. The composition of the phosphor material can be selected to determine the wavelengths of the secondary light. In one embodiment, the light emitting device includes the phosphor material dispersed as phosphor particles in another material disposed around the light emitting diode. In another embodiment, the light emitting device includes the phosphor material deposited as a phosphor film on at least one surface of the light emitting diode.
Patent TW-I230517-B (TW)
Title: System and method for acquiring a received signal in a spread spectrum device
Inventor: CHALLA RAGHU
IPC: H04B7/26
Filed: 2002-04-09
Granted: 2005-04-01
Abstract: A spread spectrum wireless device (100) may include a receiver (110), a searcher (128) a search controller (130) and other features, The search controller (130) selectively genres control signals to control the searcher (128), which searches for a spread-spectrum signal In one embodiment, the architecture of the searcher (128) is dynamically configurable by the search controller (130) to selectively search multiple channels using multiple frequency bins for the signal.
Patent TW-536789-B (TW)
Title: Mask ROM
Inventor: JONG FUH-CHENG
IPC: G11C7/18
Filed: 2002-04-18
Granted: 2003-06-11
Abstract: The present invention provides a mask ROM, which consists of: (1) a memory cell array having plural word lines and plural memory cells, wherein the word lines are arranged with checkerboard type and each memory cell has its corresponding drain; (2) plural first bit lines parallel to the diagonal line of the memory array above the drains, wherein drains on the two sides of each word line connect and disconnect the corresponding bit lines respectively; (3) plural second bit lines parallel to the diagonal line of the memory array above the drains, wherein drains on the two sides of each word line connect and disconnect the corresponding bit lines respectively; (4) plural third bit lines connected to the first bit lines; and (5) plural forth bit lines connected to the second bit lines.
Patent TW-538538-B (TW)
Title: Ordered two-phase dielectric film, and semiconductor device containing the same
Inventor: GATES STEPHEN MCCONNELL
IPC: H01L21/312
Filed: 2002-04-29
Granted: 2003-06-21
Abstract: A porous, low-k dielectric film that has good mechanical properties as well as a method of fabricating the film and the use of the film as a dielectric layer between metal wiring features are provided. The porous, low-k dielectric film includes a first phase of monodispersed pores having a diameter of from about 1 to about 10 nm that are substantially uniformly spaced apart and are essentially located on sites of a three-dimensional periodic lattice; and a second phase which is solid surrounding the first phase. Specifically, the second phase of the film includes (i) an ordered element that is composed of nanoparticles having a diameter of from about 1 to about 10 nm that are substantially uniformly spaced apart and are essentially arranged on sites of a three-dimensional periodic lattice, and (ii) a disordered element comprised of a dielectric material having a dielectric constant of about 2.8 or less.
Patent TW-556061-B (TW)
Title: Non-equal period timing method and device of timer
Inventor: CHEN JIUN-RU
IPC: G04F1/00
Filed: 2002-04-30
Granted: 2003-10-01
Abstract: The present invention discloses a non-equal period timing method and device of timer, which are applied in the timer circuit for counting the information preservation time in the network. The main purpose is to provide a unit timing scale with non-equal period and flexible counting time to count the preservation time of the information to be counted effectively. Some timing blocks and some unit timing scales can be set for the timing unit, and some sets of timers are designed relatively. The non-equal period timing device disclosed by the present invention comprises a non-equal period timing unit, a comparison unit and an adder, etc., so as to realize counting the information preservation time in the network through the design of each device by the method of the present invention.
Patent TW-I220024-B (TW)
Title: Hierarchical built-in self-test for system-on-chip design
Inventor: CHEN HOWARD H
IPC: H01L21/822
Filed: 2002-05-22
Granted: 2004-08-01
Abstract: Hierarchical built-in self-test methods and arrangement for verifying system functionality. As a result, an effective built-in self-test methodology is provided for conducting complete system-on-chip testing, to ensure both the circuit reliability and performance of system-on-chip design. As an added advantage, development costs are reduced for system-on-chip applications.
Patent TW-548696-B (TW)
Title: Method of manufacturing group III nitride compound semiconductor
Inventor: ASAI MAKOTO
IPC: H01L21/00
Filed: 2002-06-04
Granted: 2003-08-21
Abstract: This invention provides a method of manufacturing a group III nitride compound semiconductor where pit is reduced. It is assumed that a group III nitride compound semiconductor layer 31(a) having pit P is formed due to the presence of a certain small area S. When the epitaxial growth is once stopped and the substrate temperature is raised to the constant temperature, the surface of the group III nitride compound semiconductor after the epitaxial growth is activated to exhibit the so-called mass-transport. The assumed reason is that the group III nitride compound semiconductor moves to the area near the peak point S (the lowest part) of the inverted hexagonal pyramid having impeded the epitaxial growth (b). When the bottom S of pit (the peak point of the inverted hexagonal pyramid) is once covered in the profile of lateral growth with the group III nitride compound semiconductor (c), the group III nitride compound semiconductor 32(d) is quickly formed in the recessed area through the epitaxial growth by starting again the supply of the group III source and nitrogen source. As a result, extremely flat surface (c) can be formed.
Patent TW-564626-B (TW)
Title: Preventing the unwanted external detection of operations in digital integrated circuits
Inventor: ECKSTEIN GERNOT
IPC: G06F1/00
Filed: 2002-06-06
Granted: 2003-12-01
Abstract: In a digital circuit (1) comprising an asynchronous circuit (2), the supply voltage of the asynchronous circuit (2) is varied by means of a random voltage jitter. The random variation of the supply voltage causes a time jitter in the processing of the individual operations within the asynchronous circuit, whereby an artificial synchronizing of individual measurements in side channel attacks is prevented.
Patent TW-578080-B (TW)
Title: Image processing method
Inventor: NAOI JUNICHI
IPC: G06T13/20
Filed: 2002-06-06
Granted: 2004-03-01
Abstract: Size of polygons for composing an object in computer graphics, contained in the polygon data is compared with a predetermined threshold value. Each polygon not exceeding the threshold value is directly converted into pixels. On the other hand, each polygon having a size which exceeds the threshold value is divided, and the resultant polygons are compared again. This ensures efficient processing of the polygons without causing expansion of the circuit constitution or significant increase in the cost. The processing of the polygon will never be affected by the size of polygons.
Patent TW-563245-B (TW)
Title: Semiconductor memory having a plurality of memory-cell arrays
Inventor: SCHNEIDER HELMUT
IPC: H01L27/105
Filed: 2002-06-17
Granted: 2003-11-21
Abstract: The invention relates to a semiconductor memory (1) having a plurality of memory-cell arrays (2), a plurality of sense-amplifier areas (3) and a plurality of driver areas (4) on a semiconductor substrate (7) of a first conductivity type, each of the multiple sense-amplifier areas (3) and multiple driver areas (4) containing at least one first well (9) of the first conductivity type and/or at least one second well (10) of a second conductivity type, and each first well (9) of the driver areas (4) being isolated from the semiconductor substrate (7) by a buried horizontal layer (8) of the second conductivity type. In order to ensure less space is required, the semiconductor memory according to the invention exhibits the features that the buried horizontal layer (8) extends continuously beneath at least all the memory-cell arrays (2) and the multiple driver areas (4) of the semiconductor memory (1), and that a separation (delta) is provided between the second well (10) and the buried horizontal layer (8) so that the second well (10) is electrically isolated from the buried horizontal layer (8).
Patent TW-539828-B (TW)
Title: Cooling method and apparatus of emission gas with high temperature, and burning handling apparatus
Inventor: SUGIMORI YOSHIAKI
IPC: B01D47/06
Filed: 2002-06-19
Granted: 2003-07-01
Abstract: A cooling method and apparatus of an emission gas with high temperature, and a burning handling apparatus are that using a little water effectively cools the emission gas with high temperature. The cooling method is that a water film forms in the flowing way of the emission gas with high temperature. The water film is vertical with the flowing direction of the emission gas, and the emission gas with high temperature passes the water film. The cooling apparatus is including a cylindraceous cooling room (53) and a plurality of water spray pipe (54). The cylindraceous cooling room (53) is including a guiding part of the emission gas with high temperature (51) on the above, and a emission part of the emission gas with cool temperature (52) on the below. The water spray pipe (54) set vicinity of the guiding part of the emission gas with high temperature. The ejecting axis of the spray nozzle (58) of the water spray pipe (54) dispose on the same plane. The ejecting axis faces the center direction of the cooling room (53). The water drops from each spray nozzle (58) collide with each other.
Patent TW-561232-B (TW)
Title: Apparatus for continuously monitoring liquid level conditions in a liquid-vapor separating device
Inventor: OLLAT XAVIER R
IPC: F22B37/26
Filed: 2002-07-02
Granted: 2003-11-11
Abstract: An apparatus 100 for providing information concerning a condition of a vessel such as a steam drum 12 which segregates steam and liquid from one another includes a liquid contact assembly 102, a signal generator element 130, and a housing 112 and a conduit 114 for enclosing the signal generator element 130 in a substantially leak proof manner within the vessel space. The liquid contact assembly 102 is disposable at a first vessel location in the steam drum 12 and has a vibration component 108 operable to vibrate at natural frequencies which vary as a function of a predetermined characteristic of the liquid at the first vessel location and a support component 110 for supporting the water contact assembly 102 in contact with the liquid at the first vessel location. The signal generator element 130 generates a signal indicative of a natural frequency of the vibration component 108.
Patent TW-I231896-B (TW)
Title: Security system and method for computers
Inventor: HEARN MICHAEL ALFRED
IPC: G06F21/00
Filed: 2002-06-28
Granted: 2005-05-01
Abstract: The present invention relates to a computer security system and device. The system comprises a host CPU, a memory, a storage device, and a processing means which is independent of the host CPU for controlling access between the host CPU and the storage device. A program memory that is independent of the computer memory and the storage device unalterably stores and provides computer programs for operating the processor in a manner so as to control access to the storage device. The security device is connected only with the data access channel between the host CPU and the storage device, and is not connected with the main data and control bus of the host CPU. All data access by the host CPU to the data storage device is blocked before initialization of the security device and is intercepted immediately after the initialization under the control of the processor. The processor effects independent access control of the host CPU and configuration of the computer with a verification mechanism, an interception device, and other means to prevent unauthorized access to the system.
Patent TW-550896-B (TW)
Title: Dynamic link adaption for time division duplex (TDD)
Inventor: ZEIRA ELDAD
IPC: H04J13/16
Filed: 2002-08-05
Granted: 2003-09-01
Abstract: A UE system implements dynamic link adaptation by adding or changing control information to notify a receiver which timeslots and codes are currently active and which timeslots should be avoided. The UE provides synchronization such that the receiver knows which timeslots and codes the UE has used to map the coded composite transport channel onto physical channels. The UE attempts to avoid the timeslots which are experiencing transmission difficulties, while attempting to utilize the timeslots which are not experiencing transmission problems.