Patent GB-705487-A (GB)
Title: Improvements in electrical signal detecting and amplifying systems
Inventor: WILLIAMS FREDERIC CALLAND
IPC: H03F1/50
Filed: 1949-08-08
Abstract: 705,487. Digital electric calculating-apparatus. NATIONAL RESEARCH DEVELOPMENT CORPORATION. July 13, 1950 [Aug. 8, 1949], No. 20625/49. Class 106 (1). [Also in Group XL(c)] A circuit for developing electrical signals which are dependent upon the sense of pulses comprises an integrating circuit to which the pulses are applied and the time constant of which is longer than the duration of any of the pulses, portions of the output from the integrating circuit being selected which have a shorter duration than any of the pulses and which occur when the output has reached its peak amplitude. The application of the circuit to the signal detecting and amplifying systems of an electrostatic digital storage system as disclosed in Specifications 645,691, 657,591 and 705,474 is described. Fig. 4 shows the general arrangement of an electrostatic storage system in which different items of digital data, are recorded upon the screen 15 of a C.R. tube 14 as different conditions of charge of elemental areas of the screen. When the screen is irradiated by an electron beam the current flowing to a signal plate 16 is indicative of the state of charge of the storage screen and thus the stored data may be generated, erased or replaced by new data. A pulse generator 10 generates dash pulses, Fig. 3 (b), which are divided down in repetition frequency in divider 11 the output pulses from which synchronize the X and Y time bases of C.R. tube 14. Signals from pick-up plate 16 produced by the beam scanning a charge pattern on screen 15 are applied to an integrating circuit Cl, R1 of a valve VI which represents schematically with unit A, a multi-stage amplifier, an output T1 of which is applied to diode D1 via network C2, R4. The number of stages in the amplifier is such that a dash on screen 15 produces a negativegoing pulse at output T1. Valve V7 is normally held conducting by diodes D1, D2, D3 which are themselves held conducting by the positivegoing portion of a strobe waveform which is generated by strobe generator 18 under the control of the dash generator 10. When a dash is thus present on the area of screen 15 under examination the negative pulse at terminal TI cuts off valve V7 and capacitor C3 charges from the H.T. supply and is subsequently discharged through valve V7 when this valve is rendered conducting by the short negative-going strobe pulses. A positive-going sawtooth waveform is thus produced at the junction of resistors R5, R6, by each dash on screen 15 and this waveform is applied to open gate circuit 19 to pass dash pulses from generator 10 to the control electrode 20 of the C.R. tube 14. Normally dot pulses, Fig. 3 (a), from generator 21 under the control of dash generator 10 are applied through diode 22 to control electrodes 20 and are thus recorded upon screen 15 in the absence of gating pulses applied to gate 19. Thus whenever a gating pulse is applied to gate 19 the dots upon screen 15 are extended to dashes and the charge pattern upon screen 15 is regenerated. Information can be read-off from terminal 23 and new information can be written-in by applying an erasing voltage to terminal 24 to cut-off valve V1 and applying a suitable positive-going dash voltage to terminal 25 to convert dots to dashes where appropriate. The strobe pulses which should be of the order of 0.1 micro-seconds duration are timed to occur near the end of the initial period of each digit interval during which the intergated signal is built up so that the strobed portion of the waveform has an amplitude which is substantially equal to the maximum amplitude of the integrated signal, thus the integration process enables a very narrow strobe pulse to be used which improves the signal/noise ratio of the system. The clamping circuit comprising diodes D1, D2, D3 and valve V7 may be replaced by a conventional clamp or the signals may be held at a constant D.C. level by replacing amplifier Vl, A by an amplifier delay network DN in the internal coupling beas shown in Fig. 2 in which the short-circuited tween valves V4 and V5 of the amplifier shown in Fig. 2 has an overall delay of 1 micro-second which is equal to the interval during which each item of stored data is derived so that an input signal to the amplifier as shown, for example in Fig. 3 (e), appears at the amplifier output as a balanced signal as shown in Fig. 3 (f). In this way the initial portion of the output wave contains a true indication of the state of the corresponding portion of the C.R. tube storage screen 15 and the D.C. level of the signal is maintained constant. Specification 705,482 also is referred to.