Patent GB-1258972-A (GB)
IPC: G06F13/00
Filed: 1969-06-20
Abstract: 1,258,972. Data processing. INTERNATIONAL BUSINESS MACHINES CORP. 20 June, 1969 [9 July, 1968], No. 31204/69. Heading G4A. A data processing system comprises storage and data processing and control circuitry for execution of a programme, and having connected thereto but under control independent thereof a maintenance adapter including input means for receiving external signals, means for differentiating adapter commands from other information, and control means responsive to the adapter commands for causing to operate selected sections of the data processing circuitry whereby remote testing of idle sections of the data processing circuitry is possible. A stored-programme computer is tested using an adapter and console unit, the adapter receiving test information serial-by-bit selectively from a remote computer or a local readonly magnetic disc file, into an input shift register where start, stop and parity bits accompanying each byte are checked and if they are satisfactory, the byte, if a control command, is decoded to control the system, and if not, is inserted into a diagnostic register from which it can load selected sections of a microinstruction register in the computer, go to the pushbuttons and rotary switches on the console to simulate manual control, or be compared with system signals. In the console unit, a console register receives the output of the manual controls, or the signals simulating them, in part encoded according to the previous contents of the register, and can also be fed from an adder output bus in the computer. When enabled by a log transmit control command decoded in the adapter, address gates respond to the console register, and counters driven by a clock synchronized with the computer clock, to select status points in the computer to supply their statuses serial-by-bit into a byte register in the console unit. The byte register, which can also be fed from the console register, feeds a console store addressed by the address gates. The console store can feed the console register or console lights or the adapter. The byte register can also by-pass the console store to feed bytes to the lights or adapter. The console register can feed registers in the computer (communicating with its arithmetic and logic circuitry) or provide microinstruction address information to the computer (see below). The log (status) bytes received by the adapter from the console unit are inserted into an output shift register except for parity and parity check status bits from the bytes which are held in a buffer. The shift register is shifted out after each byte, to transmit to the remote computer serial-by-bit, start, stop and calculated parity bits being appended. The buffer contents are inserted into the output shift register after every four bytes (when the buffer is full) for similar transmission. The input shift register in the adapter can feed the computer registers under computer control. Testing can be done with the computer operating essentially normally, or operating under direct control of the adapter with the computer clocks advanced continuously or step-wise. When the microinstruction register in the computer is not being fed from the adapter, it receives the output of a selected one of two or three microprogramme read-only stores read out simultaneously. The microinstruction register, besides providing gate control throughout the computer, can also be used to emit (insert) data representations directly into the computer data paths and registers. The next microinstruction address is derived from fields of the microinstruction register and computer conditions, the address including two branch bits which are also supplied to the adapter for comparison with test information. The computer operates in CPU or I/O mode and interrupt (break-in) can cause the mode to be switched. The console register, and seven registers relating to the CPU mode and six I/O channels respectively, are used to provide the next microinstruction address at break-in and to save addresses at break-in to permit return when the purpose of the break-in is accomplished and break-in back occurs. The current and the previous three microinstruction addresses are kept in further registers, for diagnosis purposes. A signal is given on equality between the current address and an address set up on the console. Termination of the current microinstruction sequence without the possibility of return can occur (trap) in response to particular reset and other requirements, with insertion of respective pre-wired microinstruction addresses. A second microinstruction register allows microinstruction pre-fetch. The computer contains various back-up registers for retry of microprogrammes on error. Main storage has two address registers for CPU and I/O operations respectively. A chain of instruction buffers permits instruction pre-fetch, and a chain of instruction counters permits buffering of next instruction addresses. The main store is provided with a faster subsidiary store, and when a CPU fetch operation is required, an index array is consulted to determine if the word or byte required is in the subsidiary store, it being obtained from the latter if it is and if it is not a 4-word block being transferred to the subsidiary store from the main store including the required information which is also gated out. A CPU store operation involves insertion into both main and subsidiary stores. I/O communications are with the main store only, via local stores. The computer may be as in Specification 1,108,800 (referred to).