baber/WOPTO huggingface dataset:
Patent JP-2015173211-A (JP)
Title: Method of manufacturing semiconductor device
Inventor: ISHIBASHI YUTARO
IPC: H01S5/02
Filed: 2014-03-12
Abstract: PROBLEM TO BE SOLVED: To provide a method of manufacturing a semiconductor device that can correct the cleaving position and direction of a semiconductor wafer 11 so that the cleavage progresses at a nearer position and in a nearer direction to a cleavage line along which the cleavage should be originally performed when a starting point of the cleavage of the semiconductor wafer 11 is displaced.SOLUTION: A concave portion 22 is formed on at least one of first and second principal surfaces 11A, 11B in a dummy forming area of a semiconductor wafer 11 so as to be overlapped with a cleavable cleavage line 15 of the semiconductor wafer 11, the dummy forming area being, in plan view, away from an element forming area of a semiconductor wafer 11 on which a semiconductor element pattern 12 is formed. A scratch 17 is formed on the first principal surface 11A, and the semiconductor wafer 11 is cleaved along the cleavage line 15 with the scratch 17 set as a starting point. The scratch 17 is formed along the cleavage line 15 on a part of the cleavage line 15 on which the concave portion 22 is formed.
Patent JP-2014142992-A (JP)
Title: Semiconductor nonvolatile storage circuit and method of testing the same
Inventor: TENO YOSHIHIRO
IPC: G11C16/04
Filed: 2014-03-14
Abstract: PROBLEM TO BE SOLVED: To provide a semiconductor nonvolatile storage circuit that can be shipped after confirming the on-current difference (margin) itself of a transistor pair forming a memory, and that can increase the reliability of a product by more strictly performing a test of the product during manufacture and at pre-shipment.SOLUTION: A semiconductor nonvolatile storage circuit includes: a pair of a first transistor N11 and a second transistor N22 that forms a memory cell CEL <1>; a sense amplifier SA that generates an output signal of a logic level according to the high and low relation between a first on-current I1, 20 μA, flowing through the first transistor and a second on-current I2, 50 μA, flowing through the second transistor; and a test circuit TEST that controls whether or not to apply an offset 20-40 μA to the first on-current I1 and whether or not to apply the offset 20-40 μA to the second on-current I2, individually.
Patent JP-2015175438-A (JP)
Title: Vibration isolator
Inventor: KOJIMA HIROSHI
IPC: F16F13/14
Filed: 2014-03-14
Abstract: PROBLEM TO BE SOLVED: To improve attenuation performance.SOLUTION: There are provided a pair of first pressure receiving liquid chambers 35 each of which is communicated with an auxiliary liquid chamber 28 through a first limiting passage 37, and a second pressure receiving liquid chamber 36 communicated with the auxiliary liquid chamber 28 through a second limiting passage. A pair of first pressure receiving liquid chambers 35 are arranged to hold an inner cylinder 11 therebetween. The second pressure receiving liquid chamber 36 is arranged by an inner cylinder 11 at a crossing direction C crossing with both directions, i.e. an axial direction of the inner cylinder 11 and a holding direction B where a pair of first pressure receiving liquid chambers 35 hold the inner cylinder 11. The auxiliary liquid chamber 28 is arranged by the crossing direction C of the second pressure receiving chamber 36. The inner cylinder 11 is extended over an axial entire length of each of the pair of first pressure receiving liquid chambers 35 and the second pressure receiving liquid chamber 36. The first limiting passage 37 is extended at an outer cylinder 12 in a circumferential direction of the outer cylinder 12 and causes the first pressure receiving liquid chambers 35 and the auxiliary liquid chamber 28 to be communicated to each other at the outer cylinder 12 through a part positioned at an opposite side of the auxiliary liquid chamber 28 holding the inner cylinder 11 in the crossing direction C.
Patent JP-2015177041-A (JP)
Title: semiconductor device
Inventor: SEKIGUCHI HIDEKI
IPC: H01L21/336
Filed: 2014-03-14
Abstract: PROBLEM TO BE SOLVED: To provide a semiconductor device having improved withstand voltage.SOLUTION: A semiconductor device 100 includes a substrate 10, a first conductive layer 20, a diffusion layer 30, a first insulation layer 40, a second conductive layer 50, a second insulation layer 60 and a third insulation layer 70. The substrate has a principal surface 10p and includes an inside region 11 including a semiconductor element and an outside region 12 around the inside region. The first conductive layer is provided above the outside region and includes a first outside conductive part 21 and a first inside conductive part 22. The diffusion layer is provided in the outside region and includes an outside diffusion part 31 and an inside diffusion part 32 which lie between the inside region and the first outside conductive part when projected on the principal surface. The first insulation layer is provided between the first outside conductive part and the outside region and includes an outside insulation part 41 and an inside insulation part 42 which lies between the outside insulation part and the outside diffusion part when projected on the principal surface. The second conductive layer is provided between the outside region and the first outside conductive part and includes a second outside conductive part 51 between the inside insulation part and the first outside conductive part, a second inside conductive part 52 between the outside diffusion part and the first inside conductive part, and an intermediate conductive part 53.
Patent JP-2015177113-A (JP)
Title: Semiconductor device and manufacturing method therefor
Inventor: SHIBATA HIRONOBU
IPC: H01L21/28
Filed: 2014-03-17
Abstract: PROBLEM TO BE SOLVED: To provide a semiconductor device in which appropriate bonding of an electrode and a solder can be achieved, and to provide a manufacturing method therefor.SOLUTION: A semiconductor device includes an electrode layer containing a first metal element. Furthermore, the device includes a metal layer provided on the electrode layer, and containing a first metal element and a second metal element different from the first metal element. Furthermore, the device includes a solder layer provided on the metal layer separately therefrom, and containing the second metal element.
Patent JP-2015008272-A (JP)
Title: Electronic part, electronic apparatus, and moving object
Inventor: KOYAMA YUGO
IPC: H01L21/60
Filed: 2014-03-18
Abstract: PROBLEM TO BE SOLVED: To provide an electronic part that is capable of preventing a surface protection film provided on a circuit board from being broken when being bonded to a mount board, thereby having high reliability.SOLUTION: An electronic part 1 includes: a mount board 30; a circuit board 10; a pad 12 disposed on the circuit board 10; a bump 20 that connects the mount board 30 and the pad 12 to each other; and a surface protection film 16 that extends from a surface of the pad 12 via an outer circumferential edge of the pad 12 to a surface of the circuit board 10 and has at least two openings 18 adjacent to each other on the pad 12. The length equal to one-half the shortest distance from an end of one of the adjacent openings 18 to an end of the other opening 18 is smaller than the length of the shortest distance from the outer circumferential edge of the pad 12 to the end of each of the openings 18. The bump 20 is provided in each of the two openings 18 and overlaps the surface protection film 16.
Patent JP-2015180144-A (JP)
Title: Battery voltage control unit and battery voltage control method
Inventor: MORITA TOMOHIRO
IPC: B60L15/20
Filed: 2014-03-19
Abstract: PROBLEM TO BE SOLVED: To minimize a loss derived from boost and improve drivability by optimally controlling boost of a battery voltage according to a driving mode relevant to an output characteristic of a drive motor.SOLUTION: A battery control unit of the present invention includes a boost converter 600 that boosts a high-voltage battery 500 and applies the battery voltage to a drive motor 800, a driving mode acquisition unit 302 that acquires a driving mode relevant to an output characteristic of the drive motor 800, an accelerator pedal effort acquisition unit 304 that acquires an accelerator pedal effort, and a boost control unit 306 that controls a target boost voltage for boost, which is performed by the boost converter 600, on the basis of the driving mode and accelerator pedal effort.
Patent JP-2015178887-A (JP)
Title: Baffle plate for differential mechanism
Inventor: KOGA TORU
IPC: F16J15/10
Filed: 2014-03-20
Abstract: PROBLEM TO BE SOLVED: To provide a baffle plate for a differential mechanism low in cost, high in the degree of freedom for shape, and excellent in sealability.SOLUTION: A ring gear 12 serving as an input gear and a baffle plate 30 are provided in a differential case 2. The baffle plate 30 includes a synthetic resin body 31 provided on one side of the ring gear 12; and a seal member 32 attached to an outer peripheral edge of the body 31, fixedly attached to a bottom wall of the differential case 2, and elastically deformable. A lower portion in the differential case 2 is partitioned into a first chamber C1 in which the ring gear 12 is located and a second chamber C2 by the baffle plate 30, and an upper space of the first chamber C1 communicates with an upper space of the second chamber C2. Lubricating oil F scraped up by the ring gear 12 is supplied to the second chamber C2 through the upper spaces, thereby lowering an oil level of the first chamber C1. The seal member 32 is attached to the body 31 by fitting (engaging) a locking claw into (with) a fitting hole, with the fitting hole provided in one of the body 31 and the seal member 32 and the locking claw provided in the other.
Patent JP-2014195249-A (JP)
Title: Operation method, radio communication system, base station and terminal
Inventor: MILOS TESANOVIC
IPC: H04W16/08
Filed: 2014-03-20
Abstract: PROBLEM TO BE SOLVED: To improve a management technique to manage coverage provided by an existing base station in a radio communication system.SOLUTION: In a method of the invention is a method for operating a radio communication system that includes one or more base stations, each of which is configured to provide corresponding coverage at the time of use, a particular base station of the base stations provides coverage for one or more terminals inside its coverage, and outside the coverage provided by the particular base station, and there are one or more terminals outside the coverage. The method includes: determining whether a condition related to direct inter-device radio communication between the terminals inside the coverage and the terminal outside the coverage is satisfied; and if the condition is satisfied, changing at least one of the coverage of the particular base station and the coverage of another base station of the base stations, providing coverage for one or more terminals of the terminals outside the coverage.
Patent JP-2015184726-A (JP)
Title: Voting system, voting processor, voting processing method, and program for voting processing
Inventor: ISHIZUKA YOSHIRO
IPC: G06Q50/34
Filed: 2014-03-20
Abstract: PROBLEM TO BE SOLVED: To provide a voting system for enabling a user to easily vote for a candidate whom the user is actually referring to.SOLUTION: The voting system includes: a user terminal 80; and a voting processor 90. The user terminal 80 includes: photographing means 81 for photographing a voting candidate; image transmission means 82 for transmitting the photographed voting candidate image to a voting processor 90; and instruction means 83 for performing a voting instruction to the voting processor 90 in accordance with the operation of a user. The voting processor 90 include: identification means 91 for identifying the voting candidate on the basis of identification information extracted from a received voting candidate image; specification means 92 for specifying voting instruction information to be used for performing the voting instruction to the identified voting candidate; information transmission means 93 for transmitting the specified voting instruction information to the user terminal 80; and voting means 94 for performing voting processing in accordance with the voting instruction from the user terminal 80. The instruction means 83 of the user terminal 80 performs the voting instruction by using the voting instruction information received from the voting processor 90.
Patent JP-2015185938-A (JP)
Title: Base station device, architecture information acquisition method, and computer program
Inventor: OZEKI TAKEO
IPC: H04W92/20
Filed: 2014-03-20
Abstract: PROBLEM TO BE SOLVED: To contribute to performing dual connectivity by using a plurality of base station devices each supporting a different architecture.SOLUTION: The base station device for relaying a communication link established between a communication device and a terminal device includes a communication section 12 that transmits support architecture information representing an architecture supported by own base station device to another base station device among a plurality of architectures that establishes other communication link with the terminal device through the other base station device while leaving part of communication link at a certain base station device when establishing the communication link.
Patent JP-2015184105-A (JP)
Title: pointer type display device
Inventor: HASEGAWA KOSUKE
IPC: G04C3/00
Filed: 2014-03-24
Abstract: PROBLEM TO BE SOLVED: To provide a pointer type display device capable of easily performing the comparison display between the present position and the past position.SOLUTION: A pointer type display device includes: position acquisition means for acquiring the present position; storage means for storing the position acquired by the position acquisition means; a pointer which is rotatably arranged; and position display control means in which operation indicating the latest position acquired very recently by the position acquisition means and operation indicating the previous position which is acquired earlier than this latest position and stored in the storage means are alternately performed by respective time periods preset by the pointer.
Patent JP-2015186892-A (JP)
Title: Method for manufacturing three-dimensional molded article, and three-dimensional molded article
Inventor: OKAMOTO EIJI
IPC: B29C67/00
Filed: 2014-03-27
Abstract: PROBLEM TO BE SOLVED: To provide a method for manufacturing a three-dimensional molded article, by which a high-quality three-dimensional molded article with mitigated step-like profiles among dots can be manufactured.SOLUTION: The method for manufacturing a three-dimensional molded article comprises stacking layers, and the method includes: a step of obtaining a smoothed data of a layer from a three-dimensional data of the layer; a step of obtaining a gradation reversed data by reversing gradations of the smoothed data; a step of exchanging a first gradation dot for a first adjacent dot in the smoothed data, removing the first adjacent dot from the exchanged data, and storing the remaining data as a body main data; a step of storing a data composed of the removed dots as a body sub data; a step of exchanging a second gradation dot for a second adjacent dot in the gradation reversed data, removing the second adjacent dot from the exchanged data, and storing the remaining data as a sacrificial part main data; a step of storing a data composed of the removed dots as a sacrificial part sub data; and a step of ejecting an ink for forming the body part and an ink for forming the sacrificial part based on the respective data.
Patent JP-2015195665-A (JP)
Title: Torque return control method and motor control device
Inventor: YAMASHITA MICHIHIRO
IPC: B60L15/20
Filed: 2014-03-31
Abstract: PROBLEM TO BE SOLVED: To suppress a chain of induction of idling slide.SOLUTION: When application conditions of slowing treatment are satisfied, the slowing treatment is applied. The slowing treatment is for temporarily stopping a return operation or for reducing a return pace (it can be also said as a return speed) so that a torque command value approaches a target torque value. In (1), the application conditions are satisfied at a time t35, and therefore, a return operation is temporarily stopped during times t35 to t36. In (2), the application conditions are satisfied at a time t29 when a second holding period is ended and a second return operation is started, and therefore, it is shown that start of the return operation is temporarily stopped until a time t30.
Patent JP-2015192611-A (JP)
Title: Novel microorganisms which decompose oil and fats and fatty acid
Inventor: INAGAWA AKITSUGU
IPC: C12N1/16
Filed: 2014-03-31
Abstract: PROBLEM TO BE SOLVED: To provide Yarrowia lipolytica microorganism which is excellent in reduction effect of the oil content in a grease trap, particularly has properties capable of purifying a drainage even in an environment of water quality such as wide-ranging pH, or the like.SOLUTION: The invention relates to yeast strain 02-LM011 belonging to Yarrowia lipolytica which reduce 1% (w/v) of oil content by 50% by weight or more in 20 hours under conditions of pH 3.5-10.5 (it has been deposited with the National Institute of Technology and Evaluation Patent Microorganisms Depositary under Accession number NITE P-01813).
Patent JP-2015196058-A (JP)
Title: Operation support device for bed
Inventor: MICHIKI SHINJI
IPC: A61G7/05
Filed: 2014-04-03
Abstract: PROBLEM TO BE SOLVED: To provide a technique capable of accurately operating a bed by using brain waves.SOLUTION: The technique includes: a brain wave detection device 50 that detects brain waves of a person lying on a bed and outputs a brain wave signal; a storage device 70 that stores reference brain wave signals by associating with instruction signals; comparison means 60a that when the brain wave signal detected by the brain wave detection device 50 coincides with the reference brain wave signal stored in the storage device 70, outputs the instruction signal corresponding to the coincided reference brain wave signal; and processing means 60b that controls, on the basis of the instruction signal outputted by the comparison means 60a, a nurse call device 40 and drive devices 31-33 for adjusting a state of the bed, the processing means 60b storing, when the same instruction signal is outputted from the comparison means 60a for n times (n is a positive integer including "1"), the average value of the latest m numbers (m is a positive integer equal to or smaller than n, including "1") of the brain wave signals that are the causes of the n-times of output of the instruction signals, in the storage device 70 as the reference brain wave signal corresponding to the instruction signals.
Patent JP-2014144914-A (JP)
Title: Method for filling mold and system for filling mold
Inventor: JOOP DALSTRA
IPC: C03B7/16
Filed: 2014-04-09
Abstract: PROBLEM TO BE SOLVED: To provide a method capable of improving process control, in a delivery system for filling a mold with a glass gob.SOLUTION: A mold 8 is filled with a glass gob 10 through an opening part 12 of the mold 8 by using a delivery system 14. The delivery system 14 has an inlet 16, an outlet 18, and guide means 20 for guiding the glass gob through the delivery system 14. After the glass gob passes the inlet 16 of the delivery system 14, the glass gob is observed at at least one point of time and/or during at least one period by using an optical imaging device 4, and a glass gob observation result including glass gob speed is determined, and glass distribution of a glass product molded by the mold 8 is predicted and/or next glass gob is controlled.
Patent JP-2015211109-A (JP)
Title: Electronic circuit board
Inventor: SAWAKI TAKANORI
IPC: H05K3/34
Filed: 2014-04-25
Abstract: PROBLEM TO BE SOLVED: To provide an electronic circuit board in which generation of unnecessary stress in the soldering portion of an electronic component subjected to flow soldering can be suppressed, even if warpage or deflection occurs in the electronic circuit board due to temperature change.SOLUTION: In an electronic circuit board on which an electronic component is mounted by flow soldering, the electronic component includes a first connector 30 having a plurality of first terminals 34, and a through hole bored portion, where a plurality of through holes 16 are bored and arranged, is provided in first regions A1, A2 and A3 along the end of a flow solder portion W where the plurality of first terminals 34 are mounted on the electronic circuit board 10 by flow soldering.
Patent JP-2015215984-A (JP)
Title: Light emitting device, surface light source device and display device
Inventor: TAKATORI HIROSHI
IPC: F21S2/00
Filed: 2014-05-08
Abstract: PROBLEM TO BE SOLVED: To provide a light emitting device having at least a light-emitting element for injecting light from a side surface and capable of controlling the light emitted from the light emitting element to a desired light distribution.SOLUTION: A light-emitting device of this invention comprises: a circuit board where a regular reflection area for regular reflecting a reached light is arranged at one surface; a light-emitting element arranged on the circuit board to emit light from at least a side surface; and a light flux control member arranged on the light-emitting element to control distributed light emitted from the light-emitting element. The light flux control member comprises: a rear surface arranged at the circuit board; an inner surface of a recess opened at the rear surface, i.e an incident plane for incident light emitted from the light-emitting element; and an outgoing radiation plane for radiating at least a part of the incident light at the incident plane to outside. The outer edge of the regular reflection area is positioned at more outside part than the opening edge of the recess.
Patent JP-2015216742-A (JP)
Title: Voltage smoothing circuit, voltage conversion circuit, and method for controlling voltage applied to multilayer capacitor
Inventor: FUJII HIROO
IPC: H02M1/00
Filed: 2014-05-09
Abstract: PROBLEM TO BE SOLVED: To provide a voltage smoothing circuit having a multilayer capacitor, and capable of feeding a smooth voltage and reducing noise in a circuit board.SOLUTION: A voltage smoothing circuit 11 includes: a first multilayer capacitor C1 and a second multilayer capacitor C2; and a regulator 13 having an input terminal 13a electrically connected to the second multilayer capacitor C2 and an output terminal 13b electrically connected to the first multilayer capacitor C1. When an electric potential difference applied to the second multilayer capacitor C2 increases or decreases, so as to reduce or increase an electric potential difference applied to the first multilayer capacitor C1, the regulator 13 calculates a first voltage applied to the first multilayer capacitor C1 based on a second voltage applied to the second multilayer capacitor C2 from the input terminal 13a and outputs the first voltage from the output terminal 13b.