Patent GB-800273-A (GB)
Title: Data storage and processing machine
IPC: G06F15/78
Filed: 1954-12-14
Abstract: 800,273. Digital electric calculating-apparatus. INTERNATIONAL BUSINESS MACHINES CORPORATION. Dec. 14, 1954 [Dec. 18, 1953], No. 36136/54. Class 106 (1). A data processing machine comprises first and second data storage means, selection means operable under control of said first data storage means to cause said second data storage means to deliver a sequence of items of data commencing with an item selected in accordance with data stored in said first data storage means, means for comparing successive items with data stored in a third data storage means and means operable upon the detection of correspondence between data so compared to modify the contents of the first data storage means in accordance with the number of items compared before detection of correspondence. A general purpose computer using two-address instructions, Fig. 1, is described having a table look-up instruction, to which feature the claims are directed. The normal operating sequence is as follows: First an instruction is read from the main (drum) store into a programme storage staticisor 19, from where the first address and the function or operation part of the instruction are immediately copied into registers 21 and 22. The computer then performs the operation specified by the number registered in the operation register 22 which operation will normally involve the data located in general storage at the address contained in the address register 21 (that is the first address in the instruction). When this operation is completed the second programme storage register 19 is copied into the address register 21 and the word at this address in the main store is read into the programme storage register 19 and used as the next instruction. In the case of " jump " instructions the next instruction is selected from either of the two addresses contained therein in dependance upon the result of the test specified therein. Before a table look-up instruction can be obeyed a table must be entered into the main store in the form of a set of arguments x r , 1#r#n, stored at addresses Ar and sets of values of the functions f s (x r ) 1#s#m stored at addresses (A r +ks), (where k s+1 -k s #n, 1#s#m), and the argument X of which some function is required must be entered into the distributer. The operation performed by a table look-up instruction is, given the address A (which will occupy the first address position of the instruction) to find the address of the x r  next lower than X. This is done by reading the arguments x r  from the store in succession, starting with x 1 , and subtracting each from the argument X until an x r  is read which is larger than X, whereupon one less than the number of arguments x r  read out is added to the address A 1  and the result left in the accumulator. The machine then proceeds to the next instruction, which it takes from the address contained in the second address portion of the table look-up instruction, and the next instruction will normally cause the number in the accumulator to be transferred to a specified position in the main store where it will remain until it is desired to introduce a function f s (X) into the calculation when the value k s  will be added to it to give the address of f( s X). The accumulator, Figs. 13d, 13e, consists of a 5 x 22 matrix of condensers, and can store 22 decimal digits-one per column of which only five are shown in Figs. 13don a biquinary code. The columns of the matrix are continually being successively read and the contents thereof normally regenerated and re-entered one digit later. Data stored in the matrix can be shifted leftwards in one digit position steps. Each column of condensers, for example column D8U, has associated with it two leads, the lefthand one of which coming from a cathode follower 178 is normally at a negative potential and is raised to zero potential from DG7UB time to DG8UA time, and the right-hand one of which coming from an inverter 181 is normally at a positive potential and is lowered to zero potential from DG8UB time to DG9UA time. The purpose of the positive pulse on the lefthand lead is to read the data in the column one digit time before the number of the column; consider for example condenser 173; if this is uncharged (points B and D both at a negative potential) signifying the presence of a bit, the positive pulse at point A passes through the condenser and raises the potential of point D to zero-indicating the presence of a bitwhereas if the condenser is charged (point B at zero potential and point D at a negative potential) signifying the absence of a bit, the positive pulse at point A merely ensures that any charge lost by the condenser is replaced and the potential at point D remains substantially the same, indicating the absence of a bit. Thus as a result of the positive pulse the column is read and each condenser thereof left in a charged state. The purpose of the negative pulse on the right-hand lead is to control read-in of fresh data: consider condenser 173 again; during the duration of the DG7U pulse this condenser is read and is left in a charged state, as described above. If no bit is to be entered into the condenser the potential of point D is kept at its normal negative level and the negative pulse on the right-hand lead has no effect since it merely lowers point C to zero potential while point B is already at zero potential, and thus the condenser remains charged, but if a bit is to be entered into the condenser the potential of point D is caused to rise to zero at the same time as the negative pulse appears on the righthand lead which causes electrons to be attracted to the upper plate of the condenser (both points B and C being at zero potential) which electrons are trapped on the condenser by diode 177 when the potential of C rises, and hence the condenser is uncharged. Thus the negative pulse on the right-hand lead causes data applied to the lower plates of the condensers to be entered into the column. During normal regeneration the data read-out, for example from condenser 173, is delayed by one digit by an arrangement of gates and latches, Fig. 13e, which functions as follows and re-applied to the lower plate, point D, of the condenser simultaneously with the negative read-in control pulse on the right-hand lead. If a bit is read out of condenser 173, point D and lead 193 rise in potential at time DG7UA. This rise in potential is transmitted via a double inverter 194 and a cathode follower 195 to turn on an " early " latch (so called because it goes on one digit before the number of the column being read) comprising double inverter 198 and cathode follower 199. At DG8UA time the early latch is turned off by an A pulse applied to it via an inverter 204, and in going off it turns on an " on-time " latch comprising double inverter 202 and cathode follower 203. This latch remains on for one digit and is then turned off by an A pulse applied to it via an inverter 205. If normal regeneration is to occur a gate 215 is held open and then during the time that the " on-time " latch is on cathode follower 208 is rendered conductive (via cathode follower 213 and gate 212) thus raising the potential of lead 193 and point D and causing the re-entry into condenser 173 of the bit read out. If when the next column D9U a bit is read out of condenser 174, the early latch is set on as before, but via double inverter 185 and cathode follower 186, cathode followers 186 and 195 being alternatively clamped non-conducting by inverters 196 and 197 and odd and even pulses. If data is to be shifted leftwards a gate 216 is held open, instead of gate 215, in which case cathode follower 213 is controlled by the early latch, and thus the data entered into condenser 173 is that which was read from condenser 174. Fresh data may be entered into the matrix via either of gates 214 and 217, and the data read out of the matrix is available either on time on lead 986 or early on lead 969. The adder, Figs. 13l, 13m, comprises an array of gates and latches and adds two numbers B and A presented serially in bi-quinary code on two groups of seven leads at the upper lefthand and right-hand corners of Figs. 13l and 13m respectively, and produces a serial biquinary output on seven leads from latches B0, B5, Fig. 131, and Q0, Q1, Q2, Q3, Q4, Fig. 13m, delayed by one digit. The quinary parts of the two numbers are added by the pyramid array of gates in Fig. 13m. As a result of energizing one of each of the A quinary group and B quinary group of leads (for an example Q2 and Q4) one of the nine sum output leads of the array coming from gate 492, mixers 505, 504, 503, 502, 499, 498 and gate 474 which represent respectively 0 to 8, is energized (in the example, the lead coming from mixer 499 representing 6 will be energized). Each of these leads is either via one of a row of gates 539, 542, 544, 546, 548 if a carry zero from previous denomination latch 509 is on to a similar numbered (mod. 5), quinary output latch or, via one of a row of gates 541, 543, 545, 549, if a carry one latch is " on," to the next higher quinary output latch. (In the example, the output latch in question is either Q1 or Q2 depending upon whether or not there is a carry from the previous denomination). The setting on of the output latches in accordance with the sum digit is done by a D pulse, which occurs at the end of each digit period and which accounts for the digit delay introduced by the adder. The binary section of the adder, Fig. 131, functions in a similar manner, the lead from mixer 511 being energized when there is no carry from the quinary section to the binary section, and the lead from mixer 512 being energized when there is a carry from the quinary section to the binary section. Specification 710,554, [Group XL (c)], is referred to.