Patent GB-1125957-A (GB)
Title: Synchronizing system
IPC: H04J3/06
Filed: 1965-10-19
Abstract: 1,125,957. Automatic phase control; transistor pulse circuits. XEROX CORP. 19 Oct., 1965 [26 Oct., 1964], No. 44233/65. Headings H3A and H3T. A receiver for receiving signals including synchronizing signals, e.g. facsimile signals, comprises a synchronizing signal separator 22 which feeds received synchronizing signals to a phase oomparator 23 where they are compared with signals generated by a local synchronization generator 25 to produce an error correction signal which is fed via control unit 24 to phase lock the oscillator 25 to the incoming signal. The two synchronizing signals are also fed to a coincidence detector 27 which generates an in-synchronization signal on line 29 when the two signals are in synchronization for a predetermined number of synchronization periods. This signal is applied to close an input gate 21 to disconnect the received signal from the separator 22 except during the time intervals when the synchronizing signals appear. During times when the two synchronizing signals go out of synchronization for more than a predetermined number of synchronization periods the gate 21 remains permanently open. Synchronization separator.-Under out-ofsynchronization conditions, diodes SR2, SR4, Fig. 3a, are reversely biased and diode SR3 is forward biased so that signals received as input 20 are fed to separator Q4. The separator output is integrated by C9, C10, and fed to a trigger circuit Q10, Q12 which is adjusted by R38 to be switched only when the predetermined number of pulses have been integrated. The output from the trigger circuit is differentiated by C13, R45, Fig. 3b, and used to trigger a mono-stable circuit Q15, Q17 which produces 1 ms. " raw " synchronizing pulses at the collectors of Q17 and Q20. Local synchronization generator comprises a multivibrator Q25, Q26 from which an output K is fed via a transistor Q27, Fig. 3c, to transistors Q28, Q29. Each positive pulse from Q27 switches Q28 off for a short time until capacitor C25 charges after which Q28 again becomes conductive. The output from Q28 is also fed to Q29, which becomes conductive only during the time that Q27 and Q28 are both cut off. The output A from Q29 is fed as one input to the phase comparator. Phase comparator comprises a capacitor C16, Fig. 3b, which is alternately charged and discharged from constant current sources comprising transistors Q13, Q14, depending on the polarity of the pulse A. During the charging period the " raw " synchronizing pulse switches transistors Q16, Q18, Q19 to isolate the capacitor C16 from the charging circuit and connect it to the local oscillator Q25, Q26. The voltage to which capacitor C16 is charged before the arrival of a raw synchronizing pulse is proportional to the phase difference between the " raw " and local synchronizing signals and is fed via transistors Q23, Q24 to adjust the oscillator frequency. In- and out-of-synchronization circuits.- During the time that the two signals are out of synchronization transistor Q2, Fig. 3a, remains conducting, and trigger Q8, Q11 remains in a state to hold the diodes SR2, SR4 cut off at all times as stated above. When the two signals come into synchronization coincident application of pulses at J and N trigger Q2, Q3 and hence Q8, Q11 to switch diode SR4 on. Input signals are then blocked from Q4 except when a local oscillator pulse on J cuts SR4 off. Pulse shaping.-Pulses with various delays and widths synchronized with the local signal are obtainable from D, E, Fig. 3c, for synchronizing the image reproducer.