baber/WOPTO huggingface dataset:
Patent TW-432712-B (TW)
Title: Semiconductor crystal, fabrication method thereof and semiconductor device
Inventor: SAITOH TOHRU
IPC: H01L21/20
Filed: 2000-01-14
Granted: 2001-05-01
Abstract: The present invention provides a crystal structure for a SiGeC layer which is resistant to degradation during the heat treatment process. A Si1-xGex/Si1-yCy short-period superlattice which functions as a single SiGeC layer is formed by alternately growing Si1-xGex layers (0 < x < 1) and Si1-yCy layers (0 < y < 1) each having a thickness corresponding to several atomic layers which is small enough to prevent discrete quantization levels from being generated. This provides a SiGeC mixed crystal which is free from Ge-C bonds and has good crystalline quality and thermal stability. The Si1-xGex/Si1-yCy short-period superlattice is fabricated by a method in which Si1-xGex layers and Si1-yCy layers are epitaxially grown alternately, or a method in which a Si/Si1-xGex short-period superlattice is first formed and then C ions are implanted into the superlattice followed by annealing for allowing implanted C ions to migrate to Si layers.
Patent TW-469364-B (TW)
Title: Current source
Inventor: HOUGHTON RUSSELL J
IPC: G05F3/24
Filed: 2000-03-06
Granted: 2001-12-21
Abstract: A method and circuit for producing an output current is provided. The method and circuit adds two currents with opposing temperature coefficients to produce such output current. A first one of the two currents, I1, is a scaled copy of current produced in a temperature compensated bandgap reference circuit. A second one of the two currents, I2, is derived from a temperature stable voltage produced by the bandgap circuit divided by a positive temperature coefficient resistance. The added currents, I1+I2, provide the output current. The circuit includes a first circuit for producing: (i) a reference current having a positive temperature coefficient; and (ii) an output voltage at an output node substantially insensitive to variations in supply voltage and temperature over a predetermined range. The current source includes a second circuit connected to the output node for producing a first current derived from the bandgap reference current. The first current has a positive temperature coefficient. Also provided is a third circuit connected to the output node for producing a second current derived from the output voltage, such second current having a negative temperature coefficient. The first and second currents are summed at the output node to produce, at the output node, an output current related to the sum of the first and second currents, such output current being substantially insensitive to variations in temperature and supply voltage over the predetermined range.
Patent TW-451517-B (TW)
Title: A method for treating contact leads on electrochemical cells so as to achieve improved hermeticity and hermetically sealed electrochemical cells derived therefrom
Inventor: XIE LIKE
IPC: H01M50/562
Filed: 2000-06-21
Granted: 2001-08-21
Abstract: The present invention provides a method of hermetically sealing an electrochemical cell. In the disclosed method, a coating of an adhesive composition is applied to an external metal tab that serves as a contact lead from the cell to a device within which the cell is employed. The adhesive coats and hermetically seals the tab surface thereby. The coating process can be executed by directly heat-sealing an adhesive film onto the tab surface. Alternatively, an aqueous suspension of the adhesive composition can be sprayed onto the tab surface, or the tab may be roll coated in the composition and thereafter subjected to heat treatment, causing the adhesive to melt and flow. The coated tab is thereafter welded to a corresponding current collector in the form of a metal foil. The complete cell assembly is heat-sealed in a final closure sealing member such that the sealed tabs extend therethrough.
Patent TW-478178-B (TW)
Title: Nitride semiconductor device
Inventor: TANIZAWA KOJI
IPC: H01S5/323
Filed: 2000-03-27
Granted: 2002-03-01
Abstract: The present invention provides a nitride semiconductor light emitting device with an active layer of the multiple quantum well structure, in which the device has an improved luminous intensity and a good electrostatic withstanding voltage, thereby allowing the expanded application to various products. The active layer 7 is formed of a multiple quantum well structure containing InaGa1-aN (0 ≤ a < 1). The p-cladding layer 8 is formed on said active layer containing the p-type impurity. The p-cladding layer 8 is made of a multi-film layer including a first nitride semiconductor film containing A1 and a second nitride semiconductor film having a composition different from that of said first nitride semiconductor film. Alternatively, the p-cladding layer 8 is made of single-layered layer made of AlbGa1-bN (0 ≤ b < 1). A low-doped layer 9 is grown on the p-cladding layer 8 having a p-type impurity concentration lower than that of the p-cladding layer 8. A p-contact layer is grown on the low-doped layer 9 having a p-type impurity concentration higher than those of the p-cladding layer 8 and the low-doped layer 9.
Patent TW-495379-B (TW)
Title: Processes and apparatus for recovery and removal of copper from fluids
Inventor: GOOSEY MARTIN T
IPC: C22B3/22
Filed: 2000-04-08
Granted: 2002-07-21
Abstract: The invention provides novel processes and apparatus for removal of copper from a solution or fluid, particularly spent etchant solutions that contain copper produced through printed circuit board manufacture. The invention is particularly useful for recovery/removal of copper from aqueous admixtures that contain a copper complexing agent.
Patent TW-434056-B (TW)
Title: Vibration diagnostic method for deterioration and malfunction of clamping rollers of coiling machine for heat rolling steel belts
Inventor: JENG JI-JAU
IPC: B21B38/00
Filed: 2000-04-10
Granted: 2001-05-16
Abstract: Disclosed is a vibration diagnostic method for deterioration and malfunction of clamping rollers of coiling machine for heat rolling steel belts, primarily comprising the steps of: measuring vibration signals, computing signals, determining true value of the amplitude and the peak-to-peak value of the vibration, determining frequency modulation, determining concentration degree of frequency, determining center of a first equivalent frequency, determining rate of wave amplitude, determining center a second equivalent frequency, determining variation of frequency modulation, determining center a third equivalent frequency, and determining center a fourth equivalent frequency, so as to diagnostic the characteristic parameters, such as the time domain, the frequency domain, and the frequency modulation of each vibration signal, which parameters are then implemented to plural formulas to determine whether the clamping rollers are under such abnormal states as, ""loose bearing seats"", ""loose bolts of coupler"", ""damages in bearings"", ""oil leakage in bearings"", ""water found in bearings"", ""inappropriate levelness adjustment of clamping rollers"", and ""trembling"".
Patent TW-552479-B (TW)
Title: Silicon-containing polymer, process for its production, resist composition employing it, pattern-forming method and electronic device fabrication method
Inventor: KOZAWA MIWA
IPC: H01L21/027
Filed: 2000-04-21
Granted: 2003-09-11
Abstract: A silicon-containing polymer having a tetrafunctional siloxane portion as the basic skeleton, and containing a carboxylic acid group-containing triorganosiloxane portion and a carboxylic acid derivative group-containing triorganosiloxane portion in a specific proportion. It may be advantageously used as a negative non-chemical amplification resist polymer or a positive chemical amplification resist polymer.
Patent TW-472427-B (TW)
Title: Programmable electric motor and method of assembly
Inventor: HOLLENBECK ROBERT KEITH
IPC: H02K11/00
Filed: 2000-05-03
Granted: 2002-01-11
Abstract: An electric motor having a snap-together construction without the use of separate fasteners. The construction of the motor removes additive tolerances for a more accurate assembly. The motor is capable of programming and testing after final assembly and can be non-destructively disassembled for repair for modification. The motor is constructed to inhibit the ready entry of water into the motor housing and to limit the effect of any water which manages to enter the housing.
Patent TW-462021-B (TW)
Title: Mouse device
Inventor: SUNG CHUNG-REN
IPC: G06F3/033
Filed: 2000-05-17
Granted: 2001-11-01
Abstract: The present invention provides a mouse device, which uses four pins to detect the displacement and button press, wherein two pins are provided to drive two LEDs from positive and negative directions and in time sharing manner, and the other two pins are provided to detect the potential of a photo-coupling transistor. The potential can detect the displacement of X and Y axes by hardware or software anti-jittering Schmitt circuit. The three buttons are connected in series to the two pins for detecting potential and one of the pins for controlling LED, so as to read the status of the button in a short time by abruptly outputting high voltage and then transiting to the input state.
Patent TW-I226908-B (TW)
Title: Method of forming copper seed layer by utilizing electroless process
Inventor: YOU JR-JOU
IPC: C23C18/40
Filed: 2000-05-29
Granted: 2005-01-21
Abstract: The present invention provides a method of forming copper seed layer by utilizing electroless process, and the method is to form an interface of a copper activation layer by contact displacement technique with amorphous silicon layer or alloy layer thereof at room temperature. The formed activation layer has a planar activation surface to allow the improvement of conventional island structure. Thereafter, a nontoxic glyoxylic acid is used as a reductant in copperplate solution of the present invention. And, a copper electroless process is performed by an electroplating solution, which includes copper ion source, complexing agent, stabilizer, and surfactant, at a temperature of 55 to 65 DEG C in order to form the copper seed layer on the activation surface.
Patent TW-498624-B (TW)
Title: δ-Σ type digital/analog converter
Inventor: TAKEDA MINORU
IPC: H03M1/74
Filed: 2000-06-05
Granted: 2002-08-11
Abstract: A thermometer code outputted from a thermometer code converter 2 is divided into P blocks for every Q bits. An arrangement of the blocks is shifted in rotation by a barrel shifter 5 at a frequency fs. Along with this, an arrangement of bits in the block is shifted in rotation by a shift register 7 at a frequency (Q*fs), the frequency fs multiplied by Q. The bits of thus obtained code is given to local DACs (LDAC 1 to LDAC 12) each specified to correspond to each of the given bits. This allows to keep an operating frequency lower and to reduce distortion in the output which is due to change in shifting the data in rotation in the local DACs, which change occurs depending on bit levels of the data in a form of the thermometer code.
Patent TW-463384-B (TW)
Title: Thin film transistor having subgate and Schottky source/drain and the manufacturing method thereof
Inventor: LIN HUNG-JR
IPC: H01L29/47
Filed: 2000-06-15
Granted: 2001-11-11
Abstract: A thin film transistor having subgate and Schottky source/drain and the manufacturing method thereof are disclosed, which eliminates the traditional source/drain implantation doping, and the following annealing steps to reduce the complication and cost, and which is advantageous for the low-temperature process. For the thin film transistor having subgate and Schottky source/drain of the present invention, both of the n-type and p-type channel operation modes can be demonstrated on the same transistor device only by adjusting the bias voltage of the subgate; in addition, the bias voltage of the subgate is applied to sense and form the electrical junction for equivalently replacing the traditional source/drain extension region, so the cut-off leakage current can be reduced.
Patent TW-473445-B (TW)
Title: Ephemeris/attitude reference determination using on-board optics and other satellite ephemeris
Inventor: WEHNER JAMES W
IPC: H04B10/118
Filed: 2000-06-20
Granted: 2002-01-21
Abstract: The present invention provides a system (200) for determining the ephemeris and attitude for a spacecraft based on optical payload pointing directions and the ephemeris of other spacecraft. An ephemeris determining subsystem (300) obtains ephemeris data (308) for one or more reference spacecraft. Optical payload pointing information (306) is obtained for the optical payload pointed to the reference spacecraft. The spacecraft ephemeris (312) is then calculated with ephemeris determination algorithms (302) based on the ephemeris data (308) and optical payload pointing information (306). Other available information, such as stored results of previous measurements and calculations, time (310), spacecraft attitude (304), information from non-payload sensors and ranging information may be used to enhance the accuracy or decrease the complexity of the ephemeris calculations. In addition to ephemeris determination, the present invention also provides an attitude determining subsystem (800) for the determination of spacecraft attitude (810). Ephemeris data for reference spacecraft (806) and optical payload pointing information (802) is obtained. The spacecraft attitude is then calculated by attitude determination algorithms (804) based on the ephemeris of reference spacecraft (806) pointed to by the optical payload and the optical payload pointing information (802). Other available information, such as stored results of previous measurements and calculations, time (808), information from non-payload sensors, and ranging information may be used to enhance the accuracy or decrease the complexity of the attitude calculations.
Patent TW-466657-B (TW)
Title: Method for calculating the yield loss
Inventor: RETTELBACH MICHAEL
IPC: H01L21/66
Filed: 2000-06-23
Granted: 2001-12-01
Abstract: The present invention provides a method for calculating the total yield loss caused by a signature, which includes the following steps: first, dividing the chip array on a produced wafer surface to define a plurality of neighbored regions; next, providing a plurality of yield lists for a plurality of wafer pieces, wherein each yield list comprises a plurality of regional signature yields and a signature field, each regional signature yield is corresponding to a yield at a related test condition for a corresponding region of a related wafer, and the signature field is used to indicate if the related wafer is effected by the signature; then, defining at least one region which will be effected by the signature and the test conditions; using a linear regression method based on the plurality of yield lists to calculate the regional signature yield loss caused by corresponding to the effected test conditions when the signature is appeared once in the effected region; finally, processing the regional signature yield loss based on the ratio of the effected area to the chip array area and the ratio of the wafers effected by the signature to the plurality of the wafers, so as to estimate the total yield loss.
Patent TW-447124-B (TW)
Title: Split-gate flash memory unit
Inventor: CHEN JR-MIN
IPC: H01L27/115
Filed: 2000-07-04
Granted: 2001-07-21
Abstract: The present invention discloses a split-gate flash memory unit formed on a semiconductor substrate. Said memory unit includes: a deep n-well region formed on said substrate; a p-well region formed on said deep n-well region; a selective gate structure formed on said p-well region, the selective gate structure comprises: a stacked gate layer, a poly-silicon layer and a top oxide layer, a tunnel oxide layer formed on the p-well region, and is adjacent to the selective gate structure; a floating gate formed on the selective gate structure, and extends to at least portion of the tunnel oxide layer, a source formed on said p-well region, and is adjacent to said floating gate; and a drain formed on said p-well region, and is adjacent to said selective gate structure. The memory unit of the present invention is programmable by using the hot electrons in the drain-side of channel, and the erase operation is performed by using the channel erasing to improve the periodic endurance performance.
Patent TW-552152-B (TW)
Title: Song accompaniment system
Inventor: TOYAMA MOTOKI
IPC: A63F13/5375
Filed: 2000-08-30
Granted: 2003-09-11
Abstract: A song accompaniment system includes a karaoke machine and a simulated guitar machine, and the karaoke machine downloads accompanying music in the form of MIDI data from a source data storage. Of the MIDI data downloaded from the source data storage, a simulative instrument part of the accompanying music is transferred to the simulated guitar machine. In the simulated guitar machine, an allocation processor allocates individual sounds of the simulative instrument part to three scroll bars in a guidance picture which is presented on a monitor of the simulated guitar machine, and operating timing for producing the individual sounds is indicated by note marks which are scrolled along the scroll bars. When a player plays a simulated guitar, tone waveforms contained in the MIDI data received from the source data storage are modulated and an audio signal thus generated is output from speakers. If the simulated guitar is correctly operated, the accompanying music is reproduced in proper fashion.
Patent TW-465058-B (TW)
Title: Quad flat non-leaded package and method for manufacturing the same
Inventor: LIN CHIEN-TSUN
IPC: H01L23/28
Filed: 2000-09-02
Granted: 2001-11-21
Abstract: A quad flat non-leaded (QFN) package mainly comprises the following. A chip with the front side facing up, wherein a plurality of pads are set on the periphery of the front side of the chip. A lead frame on which the inner leads on the periphery of the chip is formed and the inner leads surround a chip zone without die pads. Electrically connecting device in which the circuit connects the pad of the chip and the inner leads of the lead frame. A molding compound which at least encapsulates the electrically connecting device and exposes the back side of the chip. The thickness of the package thereby may be effectively reduced.
Patent TW-530360-B (TW)
Title: Testing system and manufacturing method of semiconductor integrated circuit device
Inventor: SHIMIZU ISAO
IPC: H01L21/68
Filed: 2000-11-02
Granted: 2003-05-01
Abstract: For the testing circuit constructed on the wafer formed by the probing test card or the tested semiconductor chip in the invention, a test is performed by electrically connecting the testing circuit with the tested semiconductor chip such that it is capable of executing the test without using a tester. In addition, by executing the test of mounting wafer stage inside the aging apparatus, the test after the packaging stage can be simplified or omitted.
Patent TW-I272270-B (TW)
Title: Adenosine A1 receptor antagonists and methods of making and using the same
Inventor: KIESMAN WILLIAM F
IPC: A61P17/02
Filed: 2000-12-15
Granted: 2007-02-01
Abstract: The invention is based on the discovery that compounds of Formula I are unexpectedly highly potent and selective inhibitors of the adenosine A1 receptor. Adenosine A1 antagonists can be useful in the prevention and/or treatment of numerous diseases, including cardiac and circulatory disorders, degenerative disorders of the central nervous system, respiratory disorders, and many diseases for which diuretic treatment is suitable. In one embodiment, the invention features a compound of formula I.
Patent TW-528780-B (TW)
Title: Epoxy resin composition, prepreg and multilayer printed-wiring board
Inventor: NAKAMURA YOSHIHIKO
IPC: C08G59/30
Filed: 2000-11-16
Granted: 2003-04-21
Abstract: An epoxy resin composition, which comprises, as an essential component, a phosphorus compound having an average of not less than 1.8 and less than 3 of phenolic hydroxy groups reactive with an epoxy resin and an average of not less than 0.8 of a phosphorus element in the molecule, an inorganic filler having an average particle diameter of not greater than 30 μm, a bifunctional epoxy resin having an average of not less than 1.8 and less than 2.6 of epoxy groups in the molecule and a hardener, wherein the bifunctional epoxy resin is contained at an amount of not less than 51% by mass relative to the whole epoxy resin, at least one of dicyandiamide and a polyfunctional phenol system compound having an average of not less than 3 of phenolic hydroxy groups in the molecule is used as the hardener and a ration (a/c) of equivalent (a) of a phenolic hydroxy group of the phosphorus compound and equivalent (c) of an epoxy group of the bifunctional epoxy resin is not less than 0.3 and less than 0.75, and wherein aluminium hydroxide is used as the inorganic filler, an amount of the inorganic filler to be added is not less than 15 parts by mass and less than 100 parts by mass relative to 100 parts by mass of the resin solids constituent, and the content of a phosphorus element is not less than 0.8% by mass and less than 3.5% by mass relative to the whole resin solids constituent.
Patent TW-I251686-B (TW)
Title: Color filter substrate, method of fabricating color filter substrate and liquid crystal device
Inventor: TAKIZAWA KEIJI
IPC: G02F1/1335
Filed: 2000-12-28
Granted: 2006-03-21
Abstract: A color filter substrate 8 having a plurality of pixels D1 includes a reflecting layer 4 composed of a metal film formed on a substrate 2, and any one of blue, green, and red color filter layers 10, 12, and 14 formed on the reflecting layer 4 at a position corresponding to each pixel D1. A metal complex of phthalocyanine is applied to the surface of the reflecting layer 4 at the interface with each color filter layer.
Patent TW-490717-B (TW)
Title: Display device and method of manufacturing the same
Inventor: YAMAZAKI SHUNPEI
IPC: H01L21/84
Filed: 2001-01-16
Granted: 2002-06-11
Abstract: To provide a technique for manufacturing a high-performance display device by employing a plastic substrate. A peeling layer is formed on an element-forming substrate, and a semiconductor element and a luminous element are further formed thereon. Then, a fixed substrate (130) is bonded on the luminous element by using a first adhesive (129). The entire substrate in this state is exposed in a gas containing halogen fluoride to thereby remove the peeling layer and separate the element-forming substrate. Thereafter, a bonding substrate (132) that comprises a plastic substrate is bonded in place of the separated element-forming substrate.
Patent TW-558898-B (TW)
Title: Image sensor and light detecting element with an interlaced alternating pixel scheme, and a method therefor
Inventor: LEE SYWE N
IPC: H04N5/335
Filed: 2001-02-05
Granted: 2003-10-21
Abstract: A structure of an image sensor for sensing the light of an image impinging thereupon and for translating the image into a standard television format is disclosed. The structure comprises a plurality of first and second light detecting elements (22, 23) arranged in rows and columns and half as many rows and columns as scan lines of a television format for generating respective analog signals in proportion to the intensity of the light impinging respectively on each of the first and second light detecting elements (22, 23), wherein the first and second light detecting elements in each row are alternately disposed and activated by first read lines RDOn (n=1 ... 256) to generate odd field signals, and wherein the first and second light detecting elements (22, 23) of two adjacent rows disposed in a zigzag or serrated manner are activated by second read lines RDEn (n=1 ... 256) to generate even field signals.