Patent GB-1014825-A (GB)
Title: Computer with error recovery
IPC: G06F11/32
Filed: 1962-08-02
Abstract: 1,014,825. Digital computers. SPERRY RAND CORPORATION. Aug. 2, 1962 [Sept. 13, 1961], No. 29672/62. Heading G4A. A computing system includes a programme-controlled digital computer comprising a counter, means for adding a value to the counter whenever an error occurs in the computer, and means responsive to a predetermined count in the counter for indicating that the computer is incapable of functioning properly as a part of the system. General arrangement.-The computer described is basically identical with that described in Specification 1,014,824, but the various parity check circuits, parity generator circuits, and the error registers and counter are described in detail. The computer is constructed in modular units called D units which are pluggable and easily replaceable. Each D unit may include a number of " C planes " which are also removable. Each D unit has an indicator light and each C plane a mechanical flag, the lights and flags being actuated to indicate faults. The arrangement of the computer circuits is as shown in Figs. 1a, 1b, and the various components are described in detail in the Specification, which also contains details of the operations shift, round-off, divide and square root controlled by the arithmetic sequence control circuits ASC. Error checking.-There are provided various error checking circuits responsive to errors in their associated computer components and arranged to set a distinguishing code into an error register E thereby initiating an " error interrupt " sub-routine to store the error code and a representation of the location of the error. When one or a plurality of errors have occurred an " error " sub-routine is initiated to cause indications of the locations of the errors. The principal error checking features described are the following. (1) Error counter, Fig. 72. The computer can operate as part of a real-time system in which data and control signals are fed to the computer from an external unit, the computed results being fed back to the external unit, and in such a system, there is no objection to occasional computer errors. There is therefore provided an error counter in which the count is increased by one each time a computer error occurs and decreased by one each time the external device initiates a fresh computer programme. If the counter reaches a certain predetermined count a signal is emitted to indicate that errors are being produced at a rate greater than the permissible rate. When the computer is operating otherwise than as part of a real-time system, the error counter produces an output when a predetermined number of errors has occurred. (2) Extended sequence check, Fig. 57. The basic computer cycle is 5 microseconds, but the multiply, divide, square root and shift instructions, called " extended sequence " instructions, require a plurality of machine cycles. A counter is provided as an extended sequence check, this counter being preset on the initiation of an extended sequence instruction to a predetermined value dependent on the particular instruction. One is then added for each machine cycle completed and an output is produced to set an error code in the error register if a predetermined count is reached before the instruction has been completed. (3) Main pulse distributer check, (Fig. 59, not shown). This is accomplished by delaying the pulses produced at one output of the distributer and comparing them with the succeeding pulses produced at that output. (4) Command generation checks, (Figs. 63a, 63b, not shown).-This circuit compare stages 0-5 of the two instruction registers U, U*, to check that the transfer from U to U* has been performed correctly, the circuit also checking that certain commands are correctly produced during the instruction for which they are initiated. (5) Invalid operation code.-Means are provided for detecting the presence of an invalid operation code in an instruction register and re-addressing a memory to read out the instruction from the same address. (6) Memory checks.-As described in Specification 1,014,824, the computer includes two separate memories. When operating in the realtime mode, only one of these memories should be addressed, and an error is indicated if the wrong memory is addressed. (7) Checking address transfers, (Figs. 67a, 67b, not shown). A bi-stable element is provided for each possible address transfer path, an element being set when a corresponding transfer is made. The address parity is checked before and after transfer, the two parities are compared, and if they are equal, the bi-stable element is reset. If they are not equal, the bistable element is not reset and an error signal is produced. (8) Permanent memory addressing check.- If an instruction calls for reading in an oper- and to an address in the permanent memory, an error condition is signalled. (9) Parity checking data transferred to or from memory, (Figs. 60a, 60b, not shown). Each memory input-output register Z, O has an associated parity generation circuit which generates a parity bit for each word entered into the memory, this bit being stored with the word. When the word is read out, a parity bit is again generated and compared with the stored parity, an error signal being produced if the parities are unequal. (10) Tape unit parity checks, (Fig. 58, not shown). The parities of characters read from the input-output tapes are checked for correctness and summed to produce the parity digit of a multi-character computer word assembled from the tape characters. Operation of error circuits.-The E register (Fig. 68, not shown), comprises 24 binary stages and on occurrence of an error as described above stores a code indicative of the error, a 14-bit register E* registering the address of the word being referenced when the error occurred. When the E register contains data it requests an " error interrupt " routine which stores the contents of the registers E, E* in the variable memory. When a predetermined number of errors have occurred a diagnostic programme is carried out which causes the appropriate D error indicators and C indicator flags (Fig. 69, not shown), to be actuated. The final step of the diagnostic programme stops the computer so that the faulty unit can be replaced.