Patent GB-825949-A (GB)
Title: Means for the transfer of information in circuits incorporating magnetic cores
IPC: G11C19/04
Filed: 1956-06-21
Abstract: 825,949. Circuits employing bi-stable magnetic elements. SOC. D'ELECTRONIQUE ET D'AUTOMATISME. June 21, 1956 [June 21, 1955; Feb. 14, 1956], No. 19316/56. Class 40 (9). [Also in Group XIX] Magnetic cores of a shift register are linked in pairs by windings in series with condensers. When an N shift pulse in winding 3, Fig. 6, reverses the magnetization of a core 1 from P to N, the condenser 4 is charged. When core 1 reaches saturation and the shift pulse terminates, the condenser discharges through winding 2 which then offers a low impedance as the magnetic flux due to the discharge is in the same direction as the shift pulse flux and tends to increase the saturation. In core 5, the discharge tends to drive the core into the P state. If core 5 is already in the P state, winding 6 offers a low impedance; the discharge is abrupt and without effect. If the core 5 is in the N state it is driven to the P state and the discharge is completed abruptly as saturation is reached. The change of core 5 from N to P can be inhibited by a N pulse in winding 7. Information can be transferred from core 5 to core 1 by a shift pulse in winding 7. Resistor 9 damps the oscillations when the condenser discharges. Shift register, Fig. 8.-Cores 0 to 7 &c. are arranged in three groups 1, 4, 7 &c., 2, 5 &c., 0, 3, 6 &c., controlled respectively by shift pulse conductors Ia1, Ia2, Ia3. Shift pulses, Fig. 9, which recur in cycles of six time intervals t1 to t6, and are applied to windings 3, 7, 10, step a pattern of information stored in the first group of cores 1, 4, 7 &c. from left to right, the pattern being transferred from the first group to the second, from the second to the third and from the third back to the first twice in a complete cycle of six time intervals. If the pattern includes an even number of digits, a recirculating loop is formed by linking the last core (10), Fig. 10, to the first core (0). An additional core (11), enables information to be fed into the loop, the output windings 2 of cores 10 and 11 being connected in series with a common condenser 4. Alternatively, the output circuits 2, Fig. 11, with individual condensers 4 may be connected in parallel to the core (0). If the pattern includes an odd number of digits, a complementing stage is necessary. An output may be derived from the register by connecting the winding 2 of the last stage (k), Fig. 12, of the register to input windings 6 on two cores (12), (13), the windings 2, 6 being in series with a common condenser 4. In an alternative arrangement, the windings 6, Fig. 13, have individual condensers 4 and are connected in parallel with the output winding 2 of core (1k). With the control current shown in Fig. 18, the register in the normal state has all cores in the state P or all in the state N. A pattern stored on group 1 of the cores is shifted as before. With the control currents shown in Fig. 19 the cores are again normally in the state P but the control current of two successive time intervals are required to shift the pattern one step. Logical devices.-Cores may be arranged to perform AND, OR and other logical operations. In Fig. 20, the output windings 2 of cores (10) and (11) are connected to input windings 6 on core (12). When a " 1 " signal is written in either core (10) or core (11), " 1 " is written in cores (12) and (0). In Fig. 22, a " 1 " is written into core (14) in phase with each signal a written in core (16). The output windings 2 of cores (14), (16) are connected in opposition to input windings 6 on core (15). The complement of a (i.e. a) is written into cores (15) and (0). The same circuit may be used as an inhibiting circuit. If signals a are written in core (16) and signals (b) in core (14) either #a b or a #b is written into cores (15) and (0) depending upon the normal setting of (15) by winding 7. Two inhibiting circuits may be combined with an OR circuit to give a #b + #a b which is " Exclusive OR." An AND operation may be carried out by using a complementing circuit to obtain b. An inhibiting network in which a signal a is inhibited by #b gives a.b. In an alternative arrangement two inhibiting operations produce a.(a.#b) which is a.b.