Patent GB-1059467-A (GB)
Title: Memories
IPC: G11C17/04
Filed: 1964-06-17
Abstract: 1,059,467. Permanent data stores. RADIO CORPORATION OF AMERICA. June 17, 1964 [July 11, 1963], No. 25143/64. Heading G4A. [Also in Division H3] In a permanent memory circuit in which rows store data words, each row is connected to a read-out pulse source through positive resistance diodes or transistors which are caused to block the read-out pulses in all but the selected row by applying driver pulses in the column address conductors. In some examples the rows may be " content addressed" for detecting the presence of a desired word. As shown in Fig. 5, a memory comprises a two-column address section (each column comprising two separate column wires a and b) and a three-column data section. In the address section, a " 0 " is represented by the capacitor connection of a column wire a to a row wire and a " 1 " by the connection of a column wire b to the row wires. In the data section, the presence of a capacitor at a cross-point represents a " 1 " and its absence represents a " 0." Each row wire is connected to a transistor 134-140, normally in its low voltage state. In operation, drivers apply address signals to the address section, a positive pulse on a column wire a together with zero potential on the associated column wire b representing an address digit " 1," and vice versa for an address digit " 0." Consequently, the transistors of all rows except the desired row are switched from the low to the high voltage state. A positive read-out pulse 146 is now applied from source 142 thereby switching the transistor in the addressed row to the high state to apply a signal to the corresponding row wire to read out the data stored therein, signals on column wires connected via a capacitor to the selected row wire being detected via amplifiers 144 which are strobed by the source 142 during the interval of the driver pulse. After read-out, all the transistors are reset by a negative pulse. In a modification (Fig. 6, not shown), the whole of the memory is content-addressable and all the columns contain two individual column wires as in the address section of Fig. 5. If it is desired to be able to read out more than one word from the memory as a result of a single addressing operation, an interrogation routine as described in Specification 954,756 may be employed. In the embodiment (Fig. 6, not shown), the charge storage effect of the capacitors in the memory is employed to back bias ordinary diodes (connected one to each row) so that only the diode in the selected row can pass the readout pulse. In another embodiment, Fig. 7, a transformer is located at each matrix crosspoint, the primaries being connected to an a column wire or a b column wire according as a " 0" " or " 1 " is to be stored. The transformer secondaries of each row are connected in series to a row wire such as 454, this row wire being connected in shunt with an alternative path containing an ordinary diode such as 420. All the rows of the memory are connected in series by connections such as 426. In operation, one or more of the column drivers 432-436 is operated to apply a tag word to the memory thereby inducing at least one secondary current in non-selected rows to render the associated diodes conductive to the read-out pulse 450. If there is at least one row containing the tag, a high impedance is presented by the matrix to the read-out pulse which is therefore effective to cause a sense amplifier 458 to produce an output. The desired word or words can be read out by an interrogation routine as described below. In a further embodiment (Fig. 8, not shown), the matrix elements comprise resistors connected to respective " 0 " or " 1 " column wires at each cross-point, the drive pulses applied are of relatively long duration and are effective to back bias diodes in non-selected rows. The read-out pulse is effective in the selected row to read out the data stored therein, amplifier means (Fig. 9a, not shown) (see Division H3) being provided to detect the presence of the relatively short read-out pulse when present simultaneously with a drive pulse. The memory of Fig. 10 also employs resistors but has only a single sense amplifier 250 for the whole matrix. By applying a sequence of 15 tag words to the memory, the words stored therein can be ascertained by noting the binary states of the driver circuits when all driver circuits are applying " 0 " or " 1 " and the sense amplifier 250 produces an output. The matrix may be realised physically by printed circuit techniques, each row of the matrix being formed by an individual printed circuit card, the cards being stacked to constitute the matrix.