Patent SG-11201811488V-A (SG)
Title: A semiconductor logic element and logic circuitries
Inventor: AUROLA ARTTO;
IPC: H01L27/085
Filed: 2017-07-13
Abstract: INTERNATIONAL APPLICATION PUBLISHED UNDER THE PATENT COOPERATION TREATY (PCT) (19) World Intellectual Property 111111110111101110101011111011111011111111011101011101111101111111011110111111 Organization International Bureau (10) International Publication Number (43) International Publication Date ......0\"\" WO 2018/011472 Al 18 January 2018 (18.01.2018) WIP0 I PCT (51) International Patent Classification: (74) Agent: BERGGREN OY; P.O. Box 16, (Etelainen H03K 19/094 (2006.01) H03K 19/20 (2006.01) Rautatiekatu 10 A), 00101 HELSINKI (FI). H01L 27/085 (2006.01) H03K 19/0952 (2006.01) H03K 19/003 (2006.01) (81) Designated States (unless otherwise indicated, for every kind of national protection available): AE, AG, AL, AM, (21) International Application Number: AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, PCT/FI2017/050537 CA, CH, CL, CN, CO, CR, CU, CZ, DE, DJ, DK, DM, DO, (22) International Filing Date: DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, 13 July 2017 (13.07.2017) HR, HU, ID, IL, IN, IR, IS, JO, JP, KE, KG, KH, KN, KP, KR, KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, (25) Filing Language: English MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, (26) Publication Language: English OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, (30) Priority Data: TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW. 20160183 14 July 2016 (14.07.2016) FI (84) Designated States (unless otherwise indicated, for every (71) Applicant: HYPERION SEMICONDUCTORS OY kind of regional protection available): ARIPO (BW, GH, [FIIFI]; Otakallio 1 A 7, 02150 Espoo (FI). GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW), Eurasian (AM, AZ, BY, KG, KZ, RU, TJ, (72) Inventor: AUROLA, Artto; Otakallio 1 A 7, 02150 ESPOO (FI). TM), European (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, = (54) Title: A SEMICONDUCTOR LOGIC ELEMENT AND LOGIC CIRCUITRIES = 415 0490 325 483 () 326 416 362 485 7 N '-. N ./A7 A& V -' 481 4& v /7/ .d 7/ Ne/v/ N N . ' 484 471 311 331 313 312 332 314 482 1-1 FIG 4 direction >x direction ei I r ----- (57) : The invention relates to a semiconductor logic element comprising a field effect transistor of the first conductivity type 71' ,1 and a field effect transistor of the second conductivity type. A gate of the first FET is an input of the semiconductor logic element, a - drain of the second FET is referred to as the output of the semiconductor logic element and a source of the second FET is the source 0 • -.... of the semiconductor logic element. By applying applicable potentials to the terminals of the field effect transistors it is possible to GC influence the state of the output of the logic element. The invention relates also to different kinds of logic circuitries comprising the C 1-1 described logic element. ei O [Continued on next page] WO 2018/011472 Al MIDEDIMOMOIDEIROHOINIIMOHOEHOMOMMOVOIMIE MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR), OAPI (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG). Published: — with international search report (Art. 21(3)) — before the expiration of the time limit for amending the claims and to be republished in the event amendments (Rule 48.2(h)) of receipt of