Patent GB-1353770-A (GB)
Title: Data processing apparatus
IPC: G06F13/12
Filed: 1971-09-27
Abstract: 1353770 I/O controller INTERNATIONAL BUSINESS MACHINES CORP 27 Sept 1971 [1 Oct 1970] 44829/71 Heading G4A An input/output controller includes two interfaces each arranged to handle data having a respective format, circuits connected between the interfaces and arranged to process data signals in accordance with the respective interface formats whereby data signals may be passed between the interfaces, and two microprogrammed units each associated with a respective interface and arranged to exchange control and data signals therewith, there being two sets of registers connected to respective ones of the microprogrammed units and arranged to pass control signals to the processing circuits, and two sets of gates controlled by respective microprogrammed units to gate signals from the registers to the non-corresponding microprogrammed units. General.-As described a CPU communicates with an I/O controller 11 via an interface and several I/O peripherals, e.g. magnetic tape units communicate with the controller via a second interface. The interfaces are of the kind usable with multiplex channels (see U.S.A. Specification 3,303,476) and have different signal formats corresponding to the CPU and the peripherals respectively. Each interface is connected to a respective microprogrammed unit MPUX and MPUY which are themselves interconnected via resistors 14 and 15. Data to be transferred between the CPU and a peripheral selected by signals passed by MPUX is passed through the data flow processor 13 via buses 23 and 24, the flow processor being controlled in accordance with signals fed from the output registers 14 and 15. The flow processor includes a third microprogramme controlled unit MPUD substantially identical with the interface microprogramme units MPUX and MPUY. The flow processor is operative to process data from one interface so as to provide data in the correct format for the other in response to control signals from the interface microprogramme units. The CPU interface interrupts its unit MPUX via line 17 when data transfer is required and MPUX in turn interrupts MPUY via line 18. The system is described in terms of communication between a magnetic tape and the CPU, tape control signals, e.g. speed indication, being supplied via line 36.  Microprogramme unit.-Microprogrammes are contained in a store 65 which is preferably a read only store. The microinstruction are accessed by an instruction counter which is normally incremented or decremented once per cycle but which may cause a branch or jump to occur when loaded via cable 68 from the output staticizer 67 of the store. Index addressing is performed using the arithmetic unit 72. The unit has a local store 75 accessible by means of addresses supplied by cable 68. The addresses are parity checked (one parity bit per byte) in check circuit 76 and may, under the control of signals applied to AND gates 77 from control circuit 70, be passed via AND gates 77 to instruction counter 66 to cause a branch. The branch may be conditional under the control of circuit 79. The arithmetic unit 72 has a limited repertoire of instructions which include addition, AND, OR and exclusive-OR operations. Each individual unit has a computing capability less than that required for all possible I/O operations. Data flow microprogramme unit.-Data signals from the tape are received over cable 32 and are passed to an envelope detector and thence to either a phase encoded or an NRZI signal decoder, the selection being in accordance with the format of the preamble on the tape. The unit provides timing and control function, deskewing, signal threshold variation for error purposes and passes the decoded signals to a buffer from where they are accepted by the CPU interface microprogramme unit. Microprogrammes.-The microprogramme required by each unit in respect of communication between an I/O peripherals and the CPU are described in some detail with reference to flow drawings. The Specification states that different programmes will be required for different peripherals.