Patent GB-1526005-A (GB)
Title: Multiplexing communication system
IPC: H04J3/00
Filed: 1976-03-10
Abstract: 1526005 Frequency-time division multiplex; phase shift systems N S ELECTRONICS 10 March 1976 [17 March 1975] 09619/76 Headings H4M and H4P For a frequency-time division multiplexing system, each of a plurality of distinct carrier frequencies being phase modulated to one of "m" possible discrete absolute phase values throughout the duration of a time-slot in a t.d.m. frame of p slots, the value of m being in correspondence with a particular q-bit binary data word {m#2<SP>q</SP>} the receiver operates to detect the absolute phase value appertaining to any one of the slots a plurality of times within the duration of the time slot, the resultant, in the form of a one-out-of-m binary number being decoded in accordance with the correspondence between the detected m value and the q-bit data word to reconstruct the latter. The transmitter receives an input for each transmitted frequency, during each time slot, a corresponding one-out-of-m binary number which is sensed a plurality of times within the time slot to control the "ringing" phase of tank circuits providing the transmitted signal of that frequency. Receiver, Fig. 5. The phase modulated carrier, received at 201, 202 passes to phase comparator 217, providing as output a pulse at 222, whose duration is proportional to the phase deviation from a reference phase provided by the controlled oscillator 219 {whose output represents the carrier phase averaged over a plurality of t.d.m. frames}, and a polarity dependent on the sense of the deviation {lagging or leading}, the phase range - 180 degrees ### + 180 degrees being divided into m + 2 discrete values of which the intermediate m are used for information carrying. For each alternate carrier half-cycle, leading, or lagging phase detector counter {e.g. 247} is counted at a high frequency rate for the duration of the pulse at 222, the count reached during the half-cycle being passed to counter 259, the phase detector counter being reset in the succeeding half-cycle. Only when the same count is reached a plurality of times successively is the resultant m value provided at outputs 246 {for further transmission} or 262 {for local decoding and use}. Transmitter, Figs. 7, 8A, 8 (not shown). Tank circuits (318, 319) are "spiked" at epochs defining the phase shift required in each time slot, the "spiking" taking place a plurality of times in each slot, under control of flip flops (321, 337) and gates (322), the former receiving the one-out-of-m data format signals. The q-bit words may be derived from telephone analogue signals, #-modulation being used, or data signals in serial or parallel format, Fig. 9A, 9B (not shown) may be handled. To increase system capacity, one-out-of-m format words may be transformed to one-out-of-R format, with R>m, the carrier phase having one of R possible values, using disclosed numerical methods, Fig. 10 (not shown). Code conversion (i) To one-out-of-m, Figs. 3, 3A, 4, 4A (not shown). During each frame duration, the bits comprising the word are stored in flip-flops (81, 83, 85, 87, 89) or (82, 84, 86, 88, 90), the respective groups being in use in alternate frames. During the succeeding frame, the stored word is passed to the rows of a cross bar matrix (Fig. 4), cross connections to whose columns are so arranged that one out of m output lines receives a signal for each used combination of bits in a word {m#2<SP>q</SP>}. There are provided as many matrices as there are words in a frame. (ii) From one-out-of-m, Fig. 6 (not shown). OR gates, for example 269, receive as inputs a sequence of pulses, and provide as outputs, each used q-bit word. An AND gate, for example (268) is enabled only if it appertains to the momentarily received signal bit of the m, the corresponding q-bit word appearing serially at output (271). A receiver and transmitter coupled together without facility for passage of information to and from local users, may function as a regenerative repeater.