Patent GB-762221-A (GB)
Title: Improvements in or relating to electronic integration systems
IPC: G05B11/42
Filed: 1954-04-13
Abstract: 762,221. Electric analogue calculating apparatus. SOC. D'ELECTRONIQUE ET D'AUTOMATISME. April 13, 1954 [April 15, 1953], No. 10858/54. Class 37. An electronic integration system comprises an integrating circuit of the resistance-capacitance retroactive amplifier type having positive and negative limiting values of output signal, supplying an amplitude discriminator circuit, arranged to operate relay circuits, on the integrated signal exceeding the limiting values in either sense, to restore the integrating circuit to its initial condition and to algebraically register each such restoration operation on an electronic counter circuit provided with a decoder circuit supplying an electric analogue signal representing the algebraic sum registered on the counter to a summation amplifier, where it is combined with the current output signal of the integrator circuit to develop a total output signal representing the continuous integrated value of the input signal. Two identical in. tegrating circuits may be provided receiving the input signal in common and supplying integrated output signals to the summation amplifier, over reciprocally operated gating circuits responsive to successive integrator restoration and counter registration operations so that one integrator is operative while the other is being restored to its initial condition and integration proceeds without interruption. Fig. 1 shows an electrical integration system wherein an input signal x at 11 is resistance fed to a high gain amplifier having retroactive feedback over capacitor 15; the integrated output signal y, within determining values set by the time constant of the integrating circuit, appearing at terminal 16, which is connected over normally closed contact 9 to the series resistance input of a high gain summation amplifier 19 having retroactive feedback over resistance 20: An amplitude discriminator 2 comprising equal resistance branches 36, 37 and 38, 39; whose junctions are connected to sources of voltage # #/2, where # represents the determining value of the integrator output, over oppositely poled rectifiers 40, 41 is interposed between the output terminal 16 and amplifier 35 which energizes a polarized relay winding 3, having changeover contacts 7, 8 normally centralised and normally closed contact 9, of which 7, 8 are operable in either direction according to the relay sense of energization and contact 9 is opened. Contacts 8 control in either sense a step-by-step counter circuit 4 operating a decoder 5 to supply a unidirectional analogue voltage representing the total algebraic count to summation amplifier 19 over series resistance 22, which counterdecoder may utilize a step-by-step reversible counting relay chain selecting resistance networks controlling the deconded voltages, but which as shown comprises a chain of symmetrically actuated bi-stable trigger stages 45a to 45n in cascade, each having symmetrical outputs gated to operate the succeeding circuit, the final trigger stage outputs being back con. nected to the actuation input of the first stage over reciprocally operative gate circuits 43, 44 opened alternatively by univibrators 29 or 30 to determine the sign allocated to each counting pulse. The decoder 5 comprises a range of gate circuits corresponding to the successive counter stages, operative to connect calibrated voltages, corresponding in sign and magnitude to the total acrued count, to the summation amplifier. When the integrated output voltage at output terminal 16 lies within the determining values Œ # relay 3 is inoperative, contact 7. is open and contact 9 is closed so that the output signal at terminal 12 represents the integrated value of the input signal x, and contact 8 lies in its central position, so that a positive bias 24 balances a negative bias over resistance 28 and the counter is inoperative so that the decoder output signal is zero. When the integrated output signal y reaches the determining values Œ # of the integrater output, the amplified output of the amplitude discriminator momentarily operates relay 3 according to the polarity of the signal y to shortcircuit capacitor 15 over contact 7, open contact 9 to disconnect the signal y from amplifier 19 and to deflect contact 8 in sense appropriate to the sign of the signal y to trip either univibrator 29 or 30, and to remove the positive bias source 24 whereby the counter is pulsed over capacitor 25 and delay circuit 27 to register a unit count of sign determined by the gate circuits operated in response to the setting of the univibrators 29, 30 in accordance with the deflection of contact 8. On capacitor 15 being short circuited, relay 3 is released, and integration of signal x continues, each individual attainment by the value of integrated signal y of the determining voltage Œ # being algebraically counted, so that at any instant the integrated value of the input signal x at terminal 12 comprises the analogue voltage representing the decoded algebraic sum of the preceding integration cycles terminating in the voltage Œ #, combined with the integrator output-voltage y of the present integration cycle (Fig. 2, not shown). In a modification (Figs. 3, 4, 5, 6, not shown) introducing a correction for changes in the integrated signal at 16 over the time delay between operation of relay 3 and operation of the counter introducing a cumulative error into the output signal, there is provided an additional capacitor, one side of which is connected to the input of integrating amplifier 14 and which is normally shortcircuited while capacitor 15 is open-circuited for integration. On operation of relay 3, the latter is not short-circuited, but the time constant of the integrating circuit is lengthened, and a voltage Œ α, where α## is connected to the integrating amplifier input over the additional capacitor in such sign as to be in opposite polarity to the feedback voltage over integrating capacitor 15 so long as the relay 3 is operative, and this arrangement is shown to effectively compensate for the delay time error. In a further modification (Fig. 7) the input signal x is applied over series resistors 13, 53 to integrating amplifiers 14, 54 having feedback capacitors 15, 55, the component values being identical in each circuit. Additional capacitors 42, 52 are connected to the amplifier inputs and are normally short-circuited in the central or in. operative positions of changeover contacts 47, 57, the remaining terminals of the additional capacitors being alternatively connectible in the opposed operative conditions of the contacts to respective sources of voltage Œ α, Œ # (α = #<#) in dependence on the sense. The integrated output signal of amplifier 14 is applied as in Fig. 1 to an amplitude discriminator circuit 2 controlling relay 3 direct to operate contact 47, and relay 63 through delay circuit 62 to operate contact 57 in appropriate senses to deviations of the integrated signal outside the determining limit values of Œ #, while relay 63 also operates contact 68 in similar manner to contact 8 in Fig. 1 to control univibrators 10, counter 4 and decoder 23 as described to apply an analogue output voltage as before to summation amplifier 19. The outputs of integrating circuits 1, 51 are respectively connected to the input of the summation amplifier gating through reciprocally operative circuits 64, 65 controlled by a bi-stable trigger circuit 66 changing over in response to alternative unidirectional impulses respectively derived from changeover contacts 69 operated by relay 63 and 59 operated by relay 3, which are normally disconnected in their undeviated positions as shown. When the output of integrator 1 attains either determining value Œ #, relay 3 is energized to operate contact 47 in appropriate sense to apply a voltage Œ α to the integrator input and increase the integration time constant by interposition of capacitor 42. At the same time contact 59 operates to turn over the trigger stage 66, open gate 65, and close gate 64. The integrator stage 51 is immediately substituted for stage 1 in supplying the summation amplifier 19 so that the integration process continues. After the delay imposed by circuit 62, relay 63 is energized and relay 3 has been meanwhile deenergized to restore contacts 47, 59 while contacts 57, 69 are operated by relay 63. Trigger circuit 66 is restored to its former condition and gate 64 opens while gate 65 closes. Integrator 1 is now re-connected to the summation amplifier and integration thereafter proceeds indefinitely in the same manner; every excursion of the integrated signal beyond the determining values Œ # being operative to register one step in the algebraic summing counter and restore the integrating circuit to its starting point while the second integrating circuit 51 replaces the first integrating circuit 1 to bridge (Fig. 8, not shown), the discontinuity occurring in the integration characteristic at the changeover and count, and both integrators are corrected as described above for the cumulative error due to integration proceeding during time delay between the operation of the changeover relay and registration of the count.