Patent GB-1029571-A (GB)
Title: Computing device incorporating interruptible repeat instruction
IPC: G06F9/48
Filed: 1963-01-09
Abstract: 1,029,571. Digital computers. SPERRY RAND CORPORATION. Jan. 9, 1963 [Jan. 22, 1962], No. 943/63. Heading G4A. A digital computer comprises a main memory and a relatively small high-speed " control " memory, both memories storing instructions and operands, the computer being responsive to a " repeat " instruction for performing repetitive operations, and having means for temporarily interrupting the repetitive operations in response to an interrupt condition. The memories have separate access equipment and can be referenced simultaneously, a plurality of references of the high-speed memory being possible during the course of the execution of an instruction read from the main memory. In addition, when such an instruction is being extracted from the main memory, the highspeed control memory can be referenced under the control of the previous instruction, so that an effective " instruction overlap " is obtained. Instruction format.-Each 36-bit instruction word takes the form where f is the operation code, j has various uses, a and b are addresses in the control memory, h is an incrementation designator, i is an indirect address designator, and u is an operand or the address in the main memory of an operand. General arrangement.-The computer described, Fig. 1, comprises a main magnetic core memory (memory 1) capable of storing 65,536 36-bit words and having an access time of 4 Ás.; a relatively small magnetic thin film " control " memory (memory 0) having an access time of 2/3 Ás.; data transfer registers (Z1 and Z0 registers) 22 and 20 for the respective memories; a first instruction register (F0 register) 28 for storing a 36-bit instruction word; a second instruction register (F1 register) 30 for storing the f, j and a designators of an instruction originally contained in the F0 register; an index adder 32 for modifying information and having three associated 18-bit registers (W1, W2, W3) 34, 36, 38, the register W1 being capable of being set to - 1 and the register W3 being capable of being set to + 1 or to - 1; address registers (S1 and So registers) 26 and 24 for the respective memories; further auxiliary registers (P and R registers) 40, 42; and a conventional input-output section 12, and arithmetic section 10. Modification arrangements.-As examples of modifications, (1) the lower part of the Z0 register 20 is transmitted to the W1 register while the lower portion of the F0 register 28 is transmitted to the W3 register 38, the contents of the registers W1, W3 being added at 32 and the result transmitted via the R and P registers 42, 40 to the S1 register 26; (2) the upper half of the Z register 20 is transmitted via the W2 register 36 to the W3 register 38, the lower half of the Z0 register 20 being transmitted to the W1 register 34, the result of the addition at 32 being transmitted back to the Z0 register. This is called " self-modification "; (3) the contents of the programme address register (P register) 40 may be incremented by transmission to the W1 register 34, the W3 register being set to + 1. Repeat instruction.-An example of an instruction requiring repetitive operations is the " repeated equality test " instruction which takes the octal-code form The function performed is to test whether the contents of the control memory address designated by a is equal to the contents of the main memory address designated by u as modified by the contents of the control memory address b. If there is equality, the next instruction is skipped. If there is inequality, the test is repeated until the repeat count becomes zero. The designator h = 1 indicates that the address modifier word is to be " self-modified " (as described above) to provide the value actually required for modification. The steps required for executing this instruction are arranged in two groups: (1) Repeat Set-up: The operation code f is translated, the address in the P register, which is the address of the instruction to be performed when the repeat instruction has been executed, is stored in a specified location in the control memory; the " repeat count " i.e. the number of times the repeat instruction is to be repeated is extracted from a specified location in the control memory and placed in the P register 40; the " comparator word " from the address location a in the control memory is extracted and placed in the arithmetic section 10. (2) Repeat operation: The operand from the main memory location u is obtained and placed in the arithmetic section and compared therein with the " comparator word." The operand address is then modified by the address-modifier word which has itself been " self-modified " by addition of its upper half, which is unity, to its lower half, which is initially zero. Thus successive operand addresses in the main memory are selected. After each unsuccessful comparison, the repeat count in the P register is reduced by unity, until it reaches zero. Instruction overlap.-Due to the provision of the additional instruction register (F register) 30, during the time that a prior instruction is being executed, a new instruction can be retrieved and set up in the F0 instruction register 28. Control sequences.-The described operations are controlled by timing sequence control circuits (Figs. 9-11, not shown) comprising chains of flip-flops to produce the required control signals. Three " sequences " of signals called the T0, T2 and T3 sequence respectively are required, the T0 sequence being the primary control sequence, the T2 sequence being for setting up a repeat instruction and the T3 sequence for controlling the programme address register (P register) 40. Interrupt operation.-The execution of a repeat instruction may be interrupted by the occurrence of interrupt conditions such as requests from peripheral units associated with the computer, the repeat instruction being temporarily stored and extracted when the execution of the instruction is to be continued after termination of the repeat operation. The communication with the peripheral equipment required during an interrupt operation is controlled by a stored subroutine.