Patent GB-868238-A (GB)
Title: Improvements in signal translating device
Inventor: BONN THEODORE HERTZ
IPC: G11C19/04
Filed: 1957-07-05
Abstract: 868,238. Controlled non-linear inductors. SPERRY RAND CORPORATION. July 5, 1957, No. 21397/57. Class 40 (9). [Also in Group XIX] The Specification describes several arrangements of resetting magnetic amplifiers of both the complementing and non-complementing types in which a two-winding core is acted upon in opposite senses by alternately applied power and reverting pulses, signal pulses being applied at the same time and in the opposite sense to the reverting pulses, and blocking pulses being applied to the windings in the intervals between the respective pulses to prevent the spurious induction of pulses from one winding to the other. Basic devices utilizing two windings. As shown in Fig. 2, a core C of rectangular hysteresis material such as Orthonik or Moly-Permalloy carries signal and output windings 1, 2 each respectively in series with a diode H and D. Blocking pulses, Fig. 2a, are applied to terminal B1, the signal to terminal A, and power pulses to terminal B; the core normally permitting output pulses to pass to a load RL except when its flux is reversed by a signal pulse. In a complementing arrangement, Figs. 3 and 3a, the core is driven between its two saturation states by alternately applying power and reverting pulses to respective terminals B and B1. Consequently the output winding presents a high impedance to the power pulses and little current passes to the load RL. When a signal pulse is applied to a gate G in the circuit of winding 1, the gate is closed and reversion inhibited. The next power pulse is then effective in the load as the output winding presents a low impedance. Alternatively the signal impulse may be applied directly to winding 1 in opposition to the reversion current, Figs. 6 and 6a (not shown), or the winding may be short-circuited by applying a negative signal pulse to a shunting diode H2, Fig. 7. In a modification of the latter embodiment, Figs. 8 and 8a (not shown), the diodes and the direction of winding 1 are reversed so that control is exercised by a positive signal pulse. A further device is shown in Figs. 18 and 18a in which core flux reversion is effected by a constant negative potential applied to winding 2 over a resistor R. Spurious output suppression. The output from winding 2 is not zero when the core flux establishes a high impedance condition, due to the magnetizing current which must flow to reset the core. This output pulse may be completely eliminated from the load RL by applying a negative pulse to a terminal L, Fig. 9, in the same time position as the power pulse. Alternatively a positive pulse may be applied to terminal T in the circuit of load RL as shown in the same Figure, or the output circuit may include a series-connected thyrite resistor, Fig. 10 (not shown). A further arrangement, Fig. 11, comprises a resistor R and diode M which are connected to a negative potential - E. Continuous output circuits. The output pulses may be integrated by a capacitor circuit F, Fig. 12, or use may be made of a delay line entered at various points over diodes D1-D3, as shown in Fig. 13. Doubling rate of output pulse transmission over a single line by interlacing. As shown in Figs. 14a and 14b, devices A1, A2 are subjected to respective power pulses PP1, PP2 and timing pulses TP1, TP2 which establish an alternating flux in each core. In consequence no effective output is obtained except when the reverting effect of the TP pulses is inhibited by an incoming signal. As the power and timing pulses PP1, TP1 and PP2, TP2 applied to each amplifier are in phase opposition, an incoming signal produces interlaced output pulses across a common load RL. Frequency division. The device shown in Figs. 15 and 15a has no input signal circuit, and a blocking pulse is applied to terminal B1 of winding 1. The output to RL from winding 2 is also supplied to winding 1 over a delay line D. In operation, the first power pulse produces an output which passes over the delay line and reverts the core in the next pulse period. The second power pulse resets the core and thus produces no output. As the core flux is unaffected by the third power pulse, the output winding impedance is low and an effective output pulse is obtained; this operating cycle being repeated for each subsequent pair of power pulses. Trigger unit. As shown in Figs. 16a and 16b, a device C is subjected to power and reverting pulses at terminals B and A1, respectively, so that normally no output is developed across RL. When an input pulse is applied to winding 1 over diode D1, core flux reversion is inhibited and an effective output is obtained which is fed back to winding 1 over a delay unit D and diode D2. This feedback disables the reverting pulses so that a train of output pulses is produced. The output train is terminated by applying a negative pulse over diode D6 which renders the fed-back pulses ineffective. The trigger circuit may alternatively comprise the device in Figs. 18 and 19 (not shown).. Shifting register. Magnetic devices A-D, Figs. 17 and 17a, each of the complementing type, are interconnected by diodes. The devices in the two groups A, C and B, D are alternately energized by power pulses on leads 1 and 3, respectively and are also subjected to blocking and spurious-output-suppression pulses on leads 2 and 4. Lead 5 is maintained at zero potential. In operation, a device produces an output during each power pulse period except when the core flux is reversed by input information. Consequently alternate devices respectively store the information entry and its complement as progressive stepping proceeds. In a modification the controlling pulse pattern shown in Fig. 17b may be used, in which case spurious output suppression is effected by a constant bias on lead 5, while leads 2 and 4 are at constant potential and both power and blocking pulses are supplied by alternating pulses in leads 1 and 3. The devices may all be operated by the same power pulses by including a delay line, capacitor, or inductor in the transfer circuits, Figs. 20a and 20b. As shown, two complementing devices C, Cl are connected in cascade by a circuit comprising a diode D4 and a condenser F. Power pulses are applied to terminal B and act on the cores by way of diodes D1 and D3. Blocking pulses at terminal A1 determine the time position when the condenser (previously charged by a power pulse), is able to discharge through diode D4 and winding 1 of device C1 The output of the capacitor thus constitues a delayed reverting pulse. A similar arrangement is described with reference to Figs. 20c and 20d (not shown); in which reversion is effected by a D.C. bias.