Patent GB-1127271-A (GB)
Title: Memory with delay devices
IPC: G06F13/22
Filed: 1966-02-11
Abstract: 1,127,271. Delay line stores; computers; seat reservations. INTERNATIONAL BUSINESS MACHINES CORP. 11 Feb., 1966 [15 Feb., 1965 (2)], No. 6019/66. Headings G4A, G4C and G4T. The invention is a multi-delay-loop memory. Referring to Fig. 1 (not shown), ticket reservation requests from terminal units (2) are communicated on low speed lines to buffered line selectors (4) communicating on high speed lines with a central computer (1) which returns availability data via the line selectors (4) to the terminal units (2) where it is printed out. In each buffered line selector (Fig. 2), data may pass in both directions concurrently through the following portions in order: the low speed lines 3, 8, a recirculating delay loop called C-line 14, a multi-loop delay line memory 9, a recirculating delay loop called D-line 15, the high speed lines 5, 7. A register 17 is provided between C-line and the outgoing low speed lines 8 with one bit position for each outgoing line. A two-position shift register is provided between the D-line and the high speed line to the computer. The ingoing and outgoing low speed lines 3, 8 are scanned concurrently. The C-line assembles bits from the low speed lines into 3-character blocks (8 bits per character) and disassembles such blocks for transmission to the low speed lines. Each low speed channel has a respective slot in the C-line, divided into two semi-slots for input and output respectively. Each semi-slot holds three 8-bit characters and the following control bits used where appropriate: (a) three bits called scan counter indicating the number of times the current incoming bit on the low speed channel has been sampled, only one sample of a given bit being retained in the slot, (b) a bit giving the previous such sample value, (c) three bits indicating the number of bits of the current character so far read into the C-line, (d)-(f) three bits for indicating start of character received, message completed and semislot filled respectively. The last bit becomes 1 when a 1 preceding the first character moves into its position since the message bits are inserted into the slot and then shifted along. The scan counter is reset to zero when an incoming bit sample differs from the previous sample value stored (b). The multi-loop delay line memory 9 comprises say 4 delay loops (Fig. 12 shows part of each loop) each having a 6-block slot for each low speed channel, each block having space for three 8-bit characters and two control bits. One control bit indicates if there is any data in the block and the other if the slot is becoming full and so requires service. Referring to Fig 12 and letting x/y mean the yth block of the xth loop (in a given slot), then as the recirculating data passes a regeneration and transfer section (Fig. 13, not shown), (a) 3-character blocks can be transferred from C-line to 1/3, even-numbered and odd-numbered blocks being transferrable on alternate revolutions, and then be propagated along the following sequence until a non- empty block is encountered-2/3, 3/3, 4/3, 1/4, 2/4, 3/4, 4/4, 1/5, 2/5, 3/5, 4/5, 1/6, 2/6, 3/6, 4/6, (b) blocks can be transferred from 4/6 to the D-line, (c) blocks from the D-line can be inserted in 1/1 and propagated as follows until reaching a non-empty block-2/1, 3/1, 4/1, 1/2, 2/2, 3/2, 4/2, (d) blocks from 4/2 can be transferred to the C-line. The D-line is synchronized with the C-line and has four slots of a similar slot format (but not assigned to any particular low speed channels). Two semi-slots are used alternately for data transfer to the computer and another two alternately for transfer from the computer. The buffered line selectors (4) transmit to the computer in turn, each on receiving a " go ahead" " character and its own address. These come from the computer in the case of the first line selector and from the respective preceding line selector in the case of each of the others. This sequence can be altered by the computer sending the next address with a special character &c. Synchronizing, end of message and low-speed-channel-address characters are also used generally. In each buffered line selector (4), counters control delay line timing and scanning of low speed channels. The delay lines may be magnetostrictive sonic or ultrasonic lines or radiofrequency lines. Checking.-A vertical check is provided in each 8-bit character by using a fixed count 4 out of 8 code or a BCD code with double interleaved parity check, to provide adjacent double error detection. A longitudinal check character accompanies each message transmitted between the computer and a buffered line selector, the computer programme determining action to be taken on detection of an error at the computer, whereas on detection of an error at a line selector a special character is sent to the destination terminal unit (2) with the message to warn the operator. A semislot in the D-line is used for constructing the longitudinal check character prior to transmission of a message to the computer.