Patent GB-891935-A (GB)
Title: Improvements in or relating to devices for controlling transfers of programme instructions in data processing machines
IPC: G06F9/46
Filed: 1958-09-24
Abstract: 891,935. Digital electric calculating apparatus. COMPAGNIE DES MACHINES BULL. Sept. 24, 1958 [Oct. 8, 1957], No. 30565/58. Drawings to Specification. Class 106 (1). An electronic computer for performing several independent programmes simultaneously includes a device for controlling the transfer of instructions, which are grouped in routines, from a general memory to the functional elements of the computer, the device comprising coding means for generating and storing a reserve instruction in the general memory each time a routine demands a functional element which is occupied, a decoding circuit recalling the reserve instruction when the functional element becomes available. The system described employs routines of sequentially stored instructions, the instructions in a routine all relating to the same functional, e.g. storage element (EF), and permits routines relating to different functional elements to be carried out concurrently. The instructions may be stored initially in a magnetic drum storage element from which they are passed to a high speed main store. Associated with each functional element are three storage devices A, B, C which contain the main address numbers respectively of the instruction to be performed, and of instructions in the first and last of any waiting routines. Each routine, Si say, comprises a first element-selecting instruction with address number Pi, followed by a " blank " instruction pi + 1 and further instructions pi + 2 . . . qi. Suppose e.g. that while a particular element EFk is performing a routine S1, a second routine S2 appears which also involves this element; then the address number P2 + 1 is stored in devices Bk and Ck. If a further routine S3 appears, a " reserve " instruction comprising the address p3 + 1 plus an identifying portion (common to all such instructions) is stored at the address p2 + 1 in the main store and the address number P3 + 1 is stored in Ck. Similarly, for any additional waiting routine Si, a reserve instruction is stored at the address Pi-1 + 1 given by Ck which thereafter receives the new address number P2 + 1. When the routine S1 has been completed, the contents of Bk (p2 + 1) are transferred to Ak and applied to the address-selecting circuits of the main store, the address portion (p3 + 1) of the reserve instruction thus selected being read out to Bk. The contents of Ak are then repeatedly increased by " 1 " whereby the routine S2 is performed. Similar operations occur at the end of routine S2 and of all subsequent waiting routines until an address Pi + 1 is found not to contain a reserve instruction when zero is stored in Bk and subsequently transferred to Ak, whereupon operation of EFk ceases. In the system illustrated (Figs. 1 and 2, not shown) instructions relating to different functional elements are dealt with according to a predetermined priority by employing circuits similar to those described in Specification 883,655. The storage devices A, which may comprise static magnetic elements, are combined into a general store (59) with common address-selecting and read/write circuits; the storage devices B and C similarly form general stores (63 and 66). The conditions of a functional element (viz., whether or not it is free to perform a routine) and of the associated storage device B are indicated by bi-stable flip-flops (102 and 103), and the flow of instruction information is determined by gates controlled by these flip-flops and by various sequences of timing pulses.