Patent GB-1522698-A (GB)
Title: Digital signal processing device
IPC: H03H17/04
Filed: 1975-10-29
Abstract: 1522698 Active filters; digital oscillators PHILIPS ELECTRONIC & ASSOCIATED INDUSTRIES Ltd 29 Oct 1975 [14 Nov 1974] 44624/75 Headings H3U and H3H A digital processing arrangement comprises a device for storing and retrieval of at least one code word, e.g. a binary number which is related to an output word, a serial multiplying and combination device to which first and second code words both related to output words are applied together with weighting factors, the output of the combination device(s) being supplied to a feedback circuit including a "quantiser" whose output is coupled to the input of the store, the quantiser being controlled by words related to those applied to the multiplier through a second combination device, the "quantiser" operating on sum signal code words produced by the first device in dependence on the control signal words produced by the second device, a quantised signal code word having a number of bits which is less than the number of bits in the sum signal code word, and having a magnitude which in dependence upon the control signal is greater or smaller than the magnitude of said sum signal code word. In the embodiments described the quantiser performs multiplication also reduction of the number of bits so that the output number does not exceed the greater of either input number of bits. When arranged as a second order recursive digital filter a first adder I receives input binary numbers representing magnitude and polarity of an analogue signal at instants t = nT and frequency i/T and feeds delay and storage sections 2(0), 2(1) each having a delay time T and output from which is respectively multiplied at 3(0), 3(1) by factors a, b derived from source 7. This results in 10 bit numbers (plus sign bit) which are added at 4 resulting in a 20 bit number (plus polarity bit) which is reduced to 10 bits in quantiser 6 and added to input bits, then stored at 2(0), 2(1). Quantiser 6 is controlled by a circuit including a further adder 9 receiving output from 2(1), also from 4 multiplied by - I in 10. This may be alternatively achieved by inversion. If adder 9 output is positive, the quantiser content is rounded up and conversely. Rounding may also be determined by comparison with a reference number. Modified arrangements are given in Figs. 2 and 3 (not shown). A d/a converter and serial L.P filter may be connected to the output y(n). In a further arrangement Fig. 4 (not shown) a modification forms a digital oscillator giving a sinusoidal output y(n) to generate coded samples of a sinusoidal signal. Multiplying factor a determines the period and b = - which causes undamped oscillation. To avoid saturation a non- linear device 11 provides limitation to a maximum value hence magnitude truncation is not performed in quantiser 6. A type of quantiser is illustrated in Fig. 5 (not shown) is which positive numbers are rounded down and negative numbers rounded up. A read-only memory may be used in place of multiplier devices 3 in which case numbers stored in sections 2(0), 2(1) are used as address codes. The word i.e. numbers may be replaced by other representations, e.g. 2's complement. The filter may be combined with other recursive and non- recursive filters in order to realise higher orders of filters.