Patent AT-E48195-T1 (AT)
Inventor: NUSSBAECHER HANS KLAUS DIPL-IN
IPC: G06F12/12
Filed: 1985-08-09
Granted: 1989-12-15
Abstract: 1. Circuit arrangement for classifying in order of priority and for recording individual memory sections or banks of a memory arrangement, using priority data which are provided in a priority memory and are associated with the individual memory sections or banks, having hit and miss logic circuits for evaluating or generating hit and/or miss signals, as well as using an LRU replacement algorithm in such a manner that in the case of successful access to a bank, its priority moves up to first place, and other banks previously with their priority in front of this bank each move downwards one place, and that in the case of a full memory and unsuccessful access, further data are in each case stored in that memory section whose data have not been accessed for the longest period of time, whereupon the priority of this memory section then moves up to the first place from the last place, characterized in that on the output side the priority memories (PS-A, ..., PS-D) associated in each case with one of four memory banks, or the priority registers (LRU-AX, LRU-AY, ..., LRU-DX, LRU-DY) downstream in each case are connected to the inputs of an in each case bank-related miss logic circuit (ML-A, ..., ML-D), the further inputs of which receive the miss signal (MISS) and the lowest-order (MB00, MC00, MD00, ...), second-lowest (MB01, MC01, MD01 ...) and second-highest intermediate priority signals (MB10, MC10, MD10 ...) of these three memory banks which occur in the miss logic circuits of the respective other three memory banks, in that the intermediate priority signals of all four miss logic circuits are logically combined by in each case one OR element (OGA) to form in each case one miss signal (MISS-A, ..., MISS-D), in that each of the four miss signals (MISS-A, ..., MISS-D) is fed in each case to a first input of in each case one multiplexer (MUX-A, ..., MUX-D), the second input of which in each case receives a bank-specific, processor-side hit signal (MTCH-A, ..., MTCH-D), and the output of which is connected in one case directly (HIT-A, ..., HIT-D) and in one case inverted (~H~I~T~-~A~, ..., ~H~I~T~-~D) to in each case one input of the respective bank-related hit logic circuit (HL-A, ..., HL-D), in that the outputs of the priority registers (LRU-AX, LRU-AY, ..., LRU-DX, LRU-DY) containing in each case two priority bits are connected to the inputs of in each case one bank-related decoding stage (DEK-A, ..., DEK-D), the four outputs (A00, A01, A10, A11, ..., D00, D01, D10, D11) of which associated in each case with different priority values are connected to further inputs of the respective bank-related hit logic circuit (HL-A, ..., HL-D), in that further inputs of these hit logic circuits (HL-A, ..., HL-D) are connected to the outputs (B00, C00, D00, B11, C11, D11, ..., A00, B00, C00, A11, B11, C11), associated with the respective lowest-order and highest-order priority values, of the decoding stages (DEK-B, C, D, ..., DEK-A, B, C) of the respective three other memory banks and to the outputs (HIT-B, HIT-C, HIT-D, ..., HIT-A, HIT-B, HIT-C) of the multiplexers (MUX-A, ..., MUX-D) in each case downstream of the miss logic circuits (ML-B, ML-C, ML-D, ..., ML-A, ML-B, ML-C) of the three other memory banks, and in that the two priority bit outputs (L-AX, L-AY, ..., L-DX, L-DY) of each hit logic circuit (HL-A, ..., HL-D) are connected to the inputs of the associated priority memories (PS-A, ..., PS-D).