Patent GB-1136523-A (GB)
Title: Division apparatus
IPC: G06F7/52
Filed: 1967-07-31
Abstract: 1,136,523. Division apparatus. INTERNATIONAL BUSINESS MACHINES CORP. 31 July, 1967 [30 Aug., 1966], No. 35056/67. Heading G4A. In division apparatus, an approximate reciprocal of the divisor is generated and multiplied by both the dividend and divisor to produce a new dividend and divisor which are used in place of the original dividend and divisor for the same purposes, this being repeated until a new divisor equal to unity to within the tolerance of the apparatus is produced. In Fig. 2, floating-point divisor and dividend of up to 64 bits each are supplied via registers 60, 61 to one of two registers 30 and one of two registers 31. Regarding the fraction portions of the divisor and dividend as composed of 4-bit base-16 digits, the fractions are initially normalized, so that the highest order base-16 digit contains a 1 bit, by a digit shifter 68. The divisor fraction is then further normalized by a bit shifter 79 so that the highest order bit is a 1, the dividend fraction being shifted an equal number of bit positions. If in this latter dividend shifting, a 1 bit is shifted out, the dividend fraction is shifted back 4 bits. Exponent subtraction occurs in exponent "adder" 67, being modified if necessary on account of the fraction normalization. The multiplication, described in more detail in the abridgment of referred-to Specification 1,136,522, is done by taking the bits of the multiplier in one or more successive overlapping groups and decoding each group in decoder 32 (having latching), 6 overlapping sub-groups of the decoded group obtaining respective multiplies of the multiplicand by shift and/or complementing and entering them into 6 sets of latches 24-29. The multiplicand comes from OR gates 78 fed from any of the units shown. A tree 21 of carry-save adders (including latching) receives the outputs of latches 24-29 and feeds a loop 22 of carry-save adders (including latching) which feeds its own input with shift and a carry propagate adder 23. If the multiplier is short enough to form only one group of bits (see above), the adder loop 22 is by-passed. A spill adder 71 is provided to apply an extra carry to adder 23 if necessary in response to low-order bits lost at the input to adder loop 22. In a first division iteration DIV 1, 6 high-order bits of the normalized divisor fraction are used toobtain an approximate divisor fraction reciprocal by table look-up at 80, this reciprocal then being used as the multipler while the multiplicand is in turn the normalized divisor fraction and the normalized dividend fraction. These multiplications are done as above with the adder loop being by-passed. Due to latching in the adder tree 21, the two multiplications overlap in time. The multiplications using divisor and dividend provide a new divisor and a new dividend respectively. In each of three more iterations DIV 2, 3, 4 a high-order portion of the new divisor produced by the preceding iteration is complemented, a low-order portion of the result constituting a new approximate reciprocal which is used as a multiplier for two multiplications which are as before except that the multiplicands used are the new divisor and dividend produced by the preceding iteration, both shifted at 77 for application to OR gates 78 and applied direct to adder tree 21 without shift also. The new dividend produced by the fourth iteration is the final quotient if short precision floating-point fractions (24 bits) are used. If a long precision fraction (56 bits) is to be divided, a fifth iteration DIV 5 follows in which a reciprocal derived from the new divisor produced by the fourth iteration is used as the multiplier and the new dividend produced by the fourth iteration is used in the same way as before (see above) as multiplicand in a multiplication to produce the final quotient. In this multiplication, the multiplier bits are taken in three groups, and so the adder loop 22 is used.