Patent UA-103540-U (UA)
Title: Shaper single series with two packs of pulses
Inventor: KOROBKOV MYKOLA HRYHOROVYCH
IPC: H03K3/78
Filed: 2015-05-22
Abstract: Shaper single series with two packs of pulses comprising: two reversible binary counters, each of which has an input supply pulse synchronization input adjustment on mode summation / subtraction, entry permit regime counting, entry permit simultaneous parallel downloads and inputs supply data input asynchronous installation in zero state, the output overflow; inverter; the first and second elements OR; chain consisting of series connected resistor and capacitor; synchronous D-flip-flop with asynchronous input settings in the zero state, the first and second elements and two inputs, and the common point of series connected resistor and capacitor connected to the information input of D-flip-flop, with one input of the first and second post of the door element and two; And out of the first element is connected to the input of asynchronous installation D-flip-flop in the zero state; a second input of the second element is connected to the output of the first OR element, one of the inputs is connected to the output of D-flip-flop; second counter overflow output connected to its input permission boot mode; inputs parallel data loading meters form the inputs to programming generator set timing pulses on the output of the shaper; the output of the second element is connected to the meters are interconnected, creating shaper input - input supply continuous periodic sequence of pulses output from the external oscillator; clock input of D-trigger input generates pulses start filing also introduced: the third element OR; two-way NAND element; first and second JK-flip-flops with asynchronous input settings in the zero state; first JK-flip-flop has direct inputs J and K creating entry permit regime transition (counting) which is connected to the output of the second OR element, one input is connected to the output of the third OR element and the second exit inverter input is from 'disconnected from the output of the second counter overflows, entrance permit simultaneous parallel loading the first and second counters inverse inputs J and K of the second JK-flip-flop and a second input of the first OR element; overflow output of the first counter is connected to the first input NAND element and the third element OR; second input NAND element is connected to an inverted output of the first JK-flip-flop and a second input of the first element I; output of NAND element is connected to the input mode permits counting of the first counter; the second input of the third OR element connected to direct the first JK-flip-flop; the output of the third OR element connected to the input of the second input element OR and authorization regime counting of the second counter; inputs parallel data loading first counter inputs form programming shaper for the specified number of pulses per pack; inputs parallel data loading form a second counter inputs shaper programming on a given length of the pause between pulses packs; JK-clock inputs of flip-flops is connected to the input shaper; asynchronous inputs in a zero installation JK-flipflops connected to the output of the second element I.