Patent GB-1275295-A (GB)
Title: An integrated flip-flop circuit
Inventor: ENG HUNG LUEN DOMINIC
IPC: H03K3/3562
Filed: 1969-08-13
Abstract: 1275295 Transistor bi-stable circuits NORTHERN ELECTRIC CO Ltd 13 Aug 1969 [11 Sept 1968 8 Nov 1968] 40553/69 Heading H3T First and second bi-stable stages 20, 21 each consist of two series circuits, each circuit having an inverting MOST Q40 and a load MOST QR40 (and Q41, QR41, Q45 QR45, Q46 QR46), a feed forward connection in each bi-stable from QR40 to Q41 gate and from QR45 to Q46 gate, and a feedback connection in each bi-stable through a further MOST QT5, QT6; and a clock pulse source C is connected to the gates of QT5, QT6. The clock pulse source C is connected directly to QT6 and through an inverter Q13 to Q75, so that QT5 QT6 operate alternately. The output B41 of bi-stable 20 is connected through a MOST QT7 to the gate of Q45 in bi-stable 21, and the output B45 of bi-stable 21 is connected through a MOST QT8 to the gate of QT40 in bistable 20, both QT7, QT8 being clocked as shown. One embodiment (Fig. 3, not shown) contains only the above features of Fig. 6 and operates as follows: the start of a negative going clock pulse turns on QT6, and after inversion in Q13 turns off QT5 so that the feedback path of bi-stable 20 is opened while bi-stable 21 is now fully crosscoupled and stores whatever conditions existed at the time of the clock pulse arrival. Also, QT7 is opened and QT8 closed so that bi-stable 20 is reset by bi-stable 21. At the end of the clock pulse the connecting transistors QT5, QT6, QT7, QT8 reverse their conditions, and now bi-stable 20 becomes stable and bi-stable 21 is reset thereby, so that the entire circuit has changed state at the end of one clock pulse. In a second embodiment incorporating all the features shown in Fig. 6, J-K operation is achieved by applying the J, K signals to MOST's Q42, Q43 in series with Q40, Q41; Q43 has a further Q44 in parallel receiving a feedback from B45. A third bi-stable 22 is controlled by QT10 and has a feedback MOST QT9 these receiving opposite clock pulse signals, so that with J=K= 1 to make bistables 20, 21 operate as in Fig. 3, the third bi-stable changes over only at the end of the clock pulse. Set and reset inputs 30, 31 are provided. The integrated circuit layout is said to require a smaller total gate area than prior art circuits due to the reduction in the number of invertor MOST's in series with any one load MOST; since an inverter requires a larger gate area than its load MOST to ensure a lower impedance, any other MOST's in series therewith must also have the larger gate area. One J-K flip-flop, said to be known, has two MOST bi-stables (M, S, Fig. 1, not shown) each having series connected MOST)s for interconnecting the bi-stables (Q3, Q4; Q8, Q5) and for receiving J-K signals (Q11, Q12), and for receiving clock pulses (Q 5 , Q10). In another J-K flip-flop said to be known (Fig. 2, not shown), one bi-stable (Q1, Q2) has its state stored on the gate capacitances (C26, C29) of MOST's (Q26, Q27), and clock pulses (C) cause the capacitances to be disconnected (by Q31, Q32) from the bi-stable output (B1, B2) and to control MOST's (Q26, Q29) which are in series with J, K-receiving MOST's (Q27, Q30) and with further clock-controlled MOST's (Q25, Q28) which reset the bi-stable.