Patent GB-763143-A (GB)
Title: Improvements in or relating to analog-to-digital converters
IPC: H03M1/00
Filed: 1954-02-18
Abstract: 763,143. Analogue to digital converter. SOC. D'ELECTRONIQUE ET D'AUTOMATISME. Feb. 18, 1954 [Feb. 19, 1953], No. 4848/54. Class 40 (1). In an electric analogue to digital-binaryvoltage converter, periodically sampled values U of the analogue voltage are each compared with the reading of a static accumulator set by the preceding sampled value. The accumulator reading is translated into analogue form Z for the comparison and the difference-analogue voltage U-Z is translated in a static register into binary-digital form and added algebraically to the accumulator setting prior to the next comparison. In the embodiment described, the sampling time interval, and the conversion time period within the sampling time interval, are so chosen that the analogue value U does not change more than one binary unit between two successive samplings. When the difference voltage may exceed unity it may be converted into binary form as disclosed in Specification 761,884 and the circuitry modified accordingly. General operation. As shown, the input analogue voltage U and the analogue voltage Z derived in a decoder 30 from the setting of the static accumulator 7 are applied to a comparison resistor network 31, 32 the algebraic difference voltage U-Z being amplified at 34 and fed over an input circuit 23 and gating valves 18, 19, 13, 14 to set successively the stages S, N of a static digital-binary register 10 according to the difference. The stage N represents the value, one or zero, of the comparison voltage and the stage S its sign, plus or minus. The setting of the register 10 is decoded at 27, the corresponding analogue voltage V, derived at point 45 being fed back to the summing network 31-33 and added algebraically to U-Z. The register 10 is zeroized at the end of each conversion period. V is thus zero at the start of each conversion period and is varied according to the sign setting of the first stage S of the register to adjust the input voltage to the amplifier 34 to control the setting of the register stage N automatically. Finally, when both stages in the register 10 are set, and U - Z + V = 0, the setting of the register is read in a stage 6 and fed to the input 8 to be added algebraically to the accumulator setting. The setting of the accumulator is read out by applying a reading pulse at 51 to unblock pentodes 50, a combination of which thereupon conduct according to the setting of the associated digital stages of the accumulator 7 and apply pulses to a delay line 52 which delivers at 53 a pulse train corresponding to the accumulator setting. Accumulator. This may comprise an algebraic binary counter, Fig. 3 (not shown). It may, alternatively, comprise a register 70, Fig. 5 (not shown), consisting of a set of independent digital flip-flop stages I, II, III ... A reading- out device additional to that shown in Fig. 2 is then provided consisting of gating valves 71, which in a manner similar to the reading device of Fig. 2, produces a digital-binary pulse train at the output end of a delay line 72 when a reading pulse is applied at 73. This pulse train is fed to an adder 76 where the input from the reading out device 6 of the static register 10 is algebraically added thereto, the resultant binary number being fed, after zeroizing of the register 70, over the delay line to set the various register stages I, II, III ... over valves 80 when a gating pulse is applied at 81. The static accumulator may, alternatively, comprise a register capable of shifting step-by-step, its reading-out pulse train being obtained by such a progressive shifting and fed to an adder as above mentioned, the resetting of the register being effected automatically during the reading out, Fig. 4 (not shown).