Patent GB-1415199-A (GB)
Title: Electronic selector apparatus
IPC: H04N5/00
Filed: 1972-10-26
Abstract: 1415199 Electronic gating; TV channel selector apparatus SANYO ELECTRIC CO Ltd and TOKYO SANYO ELECTRIC CO Ltd 26 Oct 1972 [28 Oct 1971 (3) 15 Dec 1971] 49448/72 Headings H3T and H3Q [Also in Division G1] An electronic selector apparatus comprises a plurality of store devices F1-Fn, Fig. 1 having respective inputs P1-P2 and each capable of storing in response to an enabling signal #1 a first input signal representative of selection of the store device or a second input signal representative of non-selection of the store device and an enabling signal generator CL for generating an enabling signal #1 in response to appearance of a first signal on the input of any of the store devices and supplying the enabling signal so generated to each of the store devices F1-Fn so that the selected device stores the first signal and the remaining devices each store the second signal.  To select a channel such as channel CH1 plate P1, Fig. 1, is touched to cause an A.C. signal to be applied to the plate P1. This changes the input to the flip-flop F1 from a high to a low level and causes the output of an AND gate A to change so as to cause the clock generator CL to generate the first clock pulse #1. In response to this first clock pulse #1 the first stage of the flip-flop F1 stores and inverts the low level at its input and the first stages of the flipflops F2-Fn store and invert the high level at their inputs. Next the second clock pulse #2 is generated until the next selection is made. The signals stored in the first stages are shifted to the second stages of the flip-flop under control of the second clock #2 and are stored and in verted again. The output 01 from an inverter I1 is high for the selected channel CH1 and outputs O2-On from inverters I2-In remain at low. The input of the apparatus may bemodified (Fig. 3, not shown) where the resistance of a finger bridging two contracts PL1 and PL2 in place of the plate P1 is used to select the flip-flop F1. Each flip-flop F1-Fn may be as shown in Fig. 2, having a first stage ST1 and a similar second stage ST2. A low input together with a first clock #1 cause T10 and T17 to turn on so as to store the input signal. The cross coupling between T12 and T14 holds the state of the first stage. Now when the second clock #2 occurs T20 and T27 turn on and the output from the first stage ST1 is written into the second stage ST2 and is held by the cross coupling of T22 and T24. The clock pulse generator CL may include a monostable circuit M1 comprising a differentiation circuit (DF1, Fig. 4, not shown) and a P channel FET inverter (I11), the output of which provides the second clock pulse #2 (C, Fig. 5, not shown). Also the output of this inverter (I11) feeds a second monostable circuit (M2) comprising a second differentiation circuit (DF2) and a second inverter (I12) the output of which provides the first clock pulse #1 (e). Instead of the two stage static flip-flop described in Fig. 2 other types of flip-flop may be used such as two-phase quasi static delay flip-flop or edge trigger delay flip-flop. The flip-flop may be made with bipolar devices and J-K and R-S types may also be used. In a modification Fig. 6 using AND gates AG1-AGn and OR gates OG1-OGn any one of the channels CH1-CHn, is selectively brought in an active state on application of either an individual selection signal to the input P1-Pn of the selected channel or a remote control signal RT which provides a common control signal from CS providing control of the first and second clocks #1, #2. The common control signal CS shifts the signal written and stored in e.g. the flip-flop F1 to the adjacent flip-flop F2 so that the channels are sequentially selected by successive common selection signals. When the power source of the system is turned on a pulse from a return control signal source RC, disclosed in detail in (Fig. 7, not shown) controls AND gate AG11 to select channel CH1. The pulse output from RC may be (c, Fig. 8, not shown) from the output of a FET inverter (IV1) controlled by a delay circuit (DL) or preferably (e) from the output of a monostable circuit (MS) including a differentiation circuit (DIF) and an inverter (IV2) fed with the output from the FET. In a modification of Fig. 6 (Fig. 9, not shown) a pulse separation circuit (PS) operates in response to a chain of pulses to the remote control terminal RT to return the system to an initial condition by activating channel CH1 and then sequentially shift the active flip-flop to select the required channel. The pulse separation circuit (PS) is described (Figs. 10-11, not shown) which includes a pulse chain detection circuit (PCD) comprising a diode (D20) a storage circuit (DL21) and a MOST inverter (IV22) generating a pulse having a width equal to the period of the chain of pulses. The output of the MOST is applied to a monostable circuit (MS) including a differentiating circuit (DF33) and a MOST inverter (IV24) providing an output pulse having a width which covers the first two pulses of the pulse chain so as to allow the first two pulses of the pulse chain to pass via a logic circuit (LG, OG26) to the AND gate AG11 to reset the system to the initial condition while the logic gate (LG, OG27) allows the remaining pulses to pass to the OR gates OG1-OGn to provide the shifting operation. Remote control may be by an ultrasonic, optic or electromagnetic path (TP, Fig. 13, not shown) from a transmitter (TR) including the pulse chain generator (PCG) to a receiver (RV) including the switch control system of (Fig. 9, not shown)-described above. The pulse chain generator is described (Fig. 14, not shown) which includes input terminals (1-10) which may be the same as the touch operated terminals disclosed in (Fig. 3, not shown) feeding via an encoder (EC) the selected channel into a store formed by flip-flops (FF1- FF4). The output from the encoder triggers a single shot circuit (SS31) which operates a flip-flop (FF21) and this causes flip-flops (FF31-FF34) of a binary counter to be reset and a pulse generator (PG) to start. The pulse generator (PG) feeds its output pulses via an AND gate (AG31) to the output of the pulse chain generator and to the counter (FF31-FF34) and when the output from counter corresponds that stored in the flip-flops (FF1-FF4) coincidence gates (CO1-CO4) provide outputs to operate a single shot circuit (XS32) to stop the pulse generator (PG).