baber/WOPTO huggingface dataset:
Patent TW-472442-B (TW)
Title: Break-before-make distortion compensation for a digital amplifier
Inventor: MIAO GUOQING
IPC: H03M3/02
Filed: 2000-07-29
Granted: 2002-01-11
Abstract: Methods and apparatus are described for reducing or eliminating break-before-make distortion in switching amplifiers. A switching amplifier has an input stage for generating a switching signal. Break-before-make distortion compensation circuitry alters the switching signal. Break-before-make generator circuitry generates two drive signals from the altered switching signal. A power stage includes two switches which are alternately driven by the two drive signals. Break-before-make distortion detection circuitry detects a distortion pattern at the power stage output node and controls the break-before-make distortion compensation circuitry to alter the switching signal in response to the distortion pattern detected to thereby eliminate at least some break-before-make distortion.
Patent TW-558701-B (TW)
Title: Active matrix electroluminescent display device
Inventor: BATTERSBY STEPHEN JOHN
IPC: G09G3/30
Filed: 2000-10-04
Granted: 2003-10-21
Abstract: An active matrix electroluminescent (EL) display device has an array of pixels (10) on a substrate (25) each comprising an EL display element (20) and a driving device (22) controlling drive current therethrough in a drive period based on a data signal applied in a preceding address period, and a drive circuit (16, 18) connected to the pixels via sets of address conductors (12, 14) for selecting the rows of pixels and supplying data signals to each selected row of pixels in a respective row address period. The data signals are provided by drive ICs (40). To reduce the number of ICs required, a multiplexing circuit (45) is integrated with the pixel array on the substrate (25) and connected between the drive IC outputs (41) and one set of address conductors (14) and is operable to apply data signals from an individual drive IC output to a respective associated plurality of address conductors in sequence in a row address period. The display elements of a selected row of pixels are prevented from operating in the row address period to avoid unwanted cross-talk effects. Row selection signals may similarly be supplied by a multiplexing circuit (16) integrated on the substrate.
Patent TW-451023-B (TW)
Title: Installation device for skirt board
Inventor: HOU SHENG-JU
IPC: F16B2/24
Filed: 2000-12-01
Granted: 2001-08-21
Abstract: An installation device for skirt board includes pole 2 which struts engaged board 1, the convex plate with downward free ends set upon pole 2 for braking function, and strut frame 6 with round-stick-shaped supporting axis 4 put on it to support the fitting part set on the bottom rim of skirt board 3. Skirt board 3 includes top rim of elastic force to fit into the convex plate set upon the pole 2 mentioned above, and reverse-U-shaped fitting plate 5 set at the under part to fit into axis 4 of pole 2. Then to fit skirt board 3 into pole 2 to complete the installation. The installation mechanism allows un-installation of the skirt board for necessary circuit arrangement or socket installation after usage.
Patent TW-460969-B (TW)
Title: A method for reducing the cracks resulted from CMP of low-K material
Inventor: JANG WEN
IPC: H01L21/304
Filed: 2000-12-08
Granted: 2001-10-21
Abstract: The present invention provides a method for reducing the cracks resulted from CMP of low-K material comprising the following steps: forming a low-K material layer on the rough surface on the semiconductor substrate; remove part of the low-K dielectric layer to form an opening in the low-K dielectric layer; forming a metal film on the low-K dielectric layer, and fill into the opening; polishing the metal film by CMP to form metal lines; and etching back the low-K dielectric layer by plasma etching back technique without O2 to remove the micro-scratch and reduce dishing and erosion structures on the surface of the low-k dielectric layer and metal lines.
Patent TW-478049-B (TW)
Title: Forming method of salicide
Inventor: LUO JI-JIN
IPC: H01L21/28
Filed: 2000-12-19
Granted: 2002-03-01
Abstract: The present invention proposes a forming method of salicide, which comprises the following steps: (1) form a first insulating layer on the semiconductor substrate, whose surface has a transistor gate structure; (2) form the second insulating layer on the surface of the first insulating layer; (3) form the first dielectric layer on the surface of the second insulating layer; (4) remove part of the first dielectric layer by using the second insulating layer as the etch stop layer to form a spacer formed by the first dielectric layer on the sidewall of the second insulating layer; (5) remove part of the second insulating layer by using the first insulating layer as the etch stop layer; (6) remove part of the first insulating layer by using the gate structure as the etch stop layer; (7) proceed ion implantation to the semiconductor substrate using the transistor gate structure, the first insulating layer, the second insulating layer and the first dielectric layer as the mask to form the source/drain in the semiconductor substrate; (8) remove the first dielectric layer and part of the first insulating layer under the second insulating layer; (9) deposit metal layer on the semiconductor substrate, gate electrode, the first insulating layer and the second insulating layer; (10) proceed ion implantation of Nitrogen ions to the metal layer, so that part of the metal layer can be converted to metal nitride layer; (11) thermally anneal the metal layer to convert part of the metal layer contacting the gate electrode and source/drain into silicide; (12) remove the metal nitride layer and part of the metal layer unreacted into silicide layer; (13) thermally anneal the silicide layer to reduce the resistance of the silicide layer.
Patent TW-544711-B (TW)
Title: Ion-implanting method and ion-implanting apparatus
Inventor: HAMAMOTO NARIAKI
IPC: H01J37/147
Filed: 2000-12-28
Granted: 2003-08-01
Abstract: The ion-implanting apparatus includes an implanting control device 26a having the functions of sweeping an ion beam by a sweeping magnet 12 and scanning a target by a scan mechanism. The implanting control device 26a has the functions of changing a sweep frequency of the ion beam to be swept by said sweeping magnet according to at least one of the species and energy of the ion beam and changing the minimum number of times of scanning of the target to be scanned by said scan mechanism according to the changing of the sweep frequency.
Patent TW-487986-B (TW)
Title: Planarization method of inter-layer dielectric layer and inter-metal dielectric layer
Inventor: JENG PEI-REN
IPC: H01L21/304
Filed: 2001-02-02
Granted: 2002-05-21
Abstract: This invention provides a planarization method of inter-layer dielectric layer and inter-metal dielectric layer, which forms a cap layer after the inter-layer dielectric layer and the inter-metal dielectric layer are planarized by chemical mechanical polishing. The cap layer can be selected from UV-silicon nitride, silicon oxynitride or silicon-rich oxide with a higher refractive index. The function of the cap layer is provided to fill the micro-scratch incurred by polishing, to block diffusion of hydrogen atoms and exhibit anti-reflection capability, which leads to improved process window of subsequent exposure step, enhanced data retention capability of device and improved device protection.
Patent TW-527765-B (TW)
Title: An ultra linear high frequency transconductor structure
Inventor: MYERS BRENT
IPC: H03F3/45
Filed: 2001-07-17
Granted: 2003-04-11
Abstract: A transconductor block including a Czarnul tuning network, transconductance resistors, an input voltage follower amplifier, a common mode circuit, PMOS transistors coupled in cascode configuration, an input current source, and high gain amplifiers that drive NMOS transistors at the output. The input voltage follower amplifier receives a differential input signal including a common mode voltage and applies the differential input signal to the Czarnul tuning network. The Czarnul tuning network includes series resistors and is coupled in parallel with the transconductance resistors. The common mode circuit receives the differential input signal and a reference common mode voltage and provides a bias voltage and a common mode feedback voltage. The common mode circuit asserts the common mode feedback voltage to the output PMOS transistors to establish a DC output current and to minimize drift of the common mode voltage of the transconductance block. Also, the bias voltage is level shifted from the common mode signal. The high gain amplifiers maintain the output of the Czarnul tuning network and transconductance resistors at the bias voltage.
Patent TW-509758-B (TW)
Title: Deformed conveyor belt
Inventor: YAMAZAKI TAKAYA
IPC: B65G15/46
Filed: 2001-05-09
Granted: 2002-11-11
Abstract: The technical problem of this invention is to prevent breakage due to bending strength, etc., by improving flexibility of a resin molded product fixed on a conveyor belt and to prevent breakage due to abrasion by improving abrasion resistance.The solution adopted by this invention is that the deformed conveyor belt is constituted by fixing the resin molded product 22 on the carrying belt 21, and the resin molded product is furnished with a main body part 22a welded on the conveyor belt, etc., and a contact part 22b laminated on a surface of the main body part with resin having higher hardness than the main body part and to make contact with a product. The conveyor belt is formed in a mushroom shape, and the resin molded product is furnished with the main body part a cross-section of which is formed angular, extends in the cross direction of the conveyor belt and is welded on the conveyor belt, etc., and the contact part laminated on one slant face of the main body part with resin higher in hardness than the main body part and to make contact with a work.
Patent TW-503363-B (TW)
Title: Device and method for automatically optimizing truck dispatching
Inventor: SONG JEFF
Filed: 2001-05-10
Granted: 2002-09-21
Abstract: The present invention provides a device and method for automatically dispatching a distribution route, which includes the following steps: first, providing several distribution point data and at least one distribution tool data; generating a first distribution point list by executing the sorting of the distribution point data based on the distribution point data and the distribution tool data, and the sorting procedure is executed corresponding to several distribution location density of the distribution location data; next, selecting a first distribution location suitable for the distribution tool data based on the first distribution point list; then, executing the sorting on the distribution location data according to the distance from other distribution locations in the first distribution location list to the first distribution location to generate a second distribution location list; selecting a second distribution location compliant for the distribution tool from the second distribution location list.
Patent TW-494525-B (TW)
Title: Chip mounting device and the alignment method for the device
Inventor: ARAI YOSHIYUKI
IPC: H05K13/04
Filed: 2001-05-22
Granted: 2002-07-11
Abstract: A chip mounting device and the alignment method for the device, which is provided with a chip holding tool and a substrate holding table, wherein the wafer holding tool and at least one side of the substrate holding table on the coarse moving table for coarsely adjusting the position for the chip or substrate; and, configuring the braking device on the coarse moving table for fixing the position of the coarse moving table after the coarse adjustment; and, configuring the fine moving device on the rough moving table for fine tuning the position of the chip or substrate. The present invention can be applied for high precision alignment in sub-micron level, and rapidly proceed with high precision alignment, and greatly reduce the intermission period for the chip mounting.
Patent TW-554199-B (TW)
Title: Reflective thin-film transistor liquid crystal display with rough diffuser
Inventor: LAI HAN-JUNG
IPC: G02F1/1335
Filed: 2001-08-29
Granted: 2003-09-21
Abstract: The present invention discloses a method for forming a thin-film transistor liquid crystal display having rough diffuser pixel electrode, which includes the following steps: first, defining a gate structure on the transparent insulative substrate and the insulative layer covered thereon; defining the drain structure and the source structure to compose the transistor devices; next, forming a first passivation layer on the transparent insulative substrate to cover the source structure, the drain structure and the insulative layer; etching the first passivation layer to form the contact holes for exposing part of the source structure and the drain structure; then, forming the pixel electrodes on the surface of the first passivation layer, and electrically connecting to the drain structure; then, depositing a second passivation layer on the first passivation layer and the pixel electrodes to fully cover the transistor devices and provide the planarization effect; and, conducting the lithography etching process on the upper surface of the second passivation layer to form the wavy and rough scattering surface, so as to utilize the incident light from the outside through the second passivation layer to generate the scattering effect.
Patent TW-I237667-B (TW)
Title: Target formed of sintered zinc sulfide-silicon dioxide and method of producing the same
Inventor: SETO YASUHIRO
IPC: C23C14/34
Filed: 2001-09-26
Granted: 2005-08-11
Abstract: The invention provides a sputtering target formed of sintered zinc sulfide-silicon dioxide, which target attains a high deposition rate without excessive elevation of the input power; prevents breakage and like accidents; and contains, inside the target, residual impurities in reduced amounts, and also provides a method of producing the sputtering target. The sputtering target contains ZnS in an amount of 70-90 mol%, the balance being SiO2 and unavoidable impurities, wherein ZnS constituting the sputtering target exhibits, in an X-ray diffraction chart showing the crystal structure of ZnS, peak intensities satisfying the following expression: 0 <= I(w100)/(I(zb111)+I(w002)) <= 0.2, wherein I(w100) represents the intensity of the (100) diffraction peak attributed to wurtzite structure; I(w002) represents the intensity of the (002) diffraction peak attributed to wurtzite structure; I(zb111) represents the intensity of the (111) diffraction peak attributed to zinc blende structure; and (I(zb111)+I(w002)) represents the intensity of the diffraction peak observed as overlapped diffraction peaks.
Patent TW-552168-B (TW)
Title: Environmental disk recycling method with overall benefit and its device
Inventor: JANGHUANG SHIUE-FANG
IPC: B09B3/00
Filed: 2001-10-19
Granted: 2003-09-11
Abstract: The present invention provides an environmental disk recycling method with overall benefit and its device. The method comprises the steps of: placing all the recycled disks on the disk organizing part of a device body, and using a first transfer structure to rapidly draw and send the disks one by one from the bottom of the stacked disks to a first organizing part to perform a first metal grinding process; then transferring the disks to a first cleaning part to perform a high-pressure cleaning; next, transferring the disks from the second transfer structure to a fine recycling part to perform a fine grinding; then transferring the disks to a second cleaning part to perform a high-pressure cleaning part; and finally performing a high-pressure drying, so as to provide the manufacturer with a fast, sure, labor-less, environmental, automated, low-cost, and high-quality disk recycling method and device.
Patent TW-I252876-B (TW)
Title: Verge-hoop device of edge bevel remover
Inventor: CHENG HSI-KUEI
IPC: C25D17/00
Filed: 2001-11-22
Granted: 2006-04-11
Abstract: The present invention relates to a verge-hoop device of an edge bevel remover suitable for being applied to an electroplating machine so as to support wafer chips. The device of the invention comprises at least a base and three triangular pose supports disposed on the base. The triangular pose supports connect to the base by a rectangular bottom and is located at the circumference of a concentric circle whose center is at the middle of the base; moreover, the triangular pose supports divide the circumference into equal parts. The direction of the triangular pose supports is perpendicular to the direction of the tangent line of the concentric circle.
Patent TW-I237234-B (TW)
Title: Optical disc recording apparatus and medium
Inventor: MASHIMO AKIRA
IPC: G11B7/126
Filed: 2001-11-23
Granted: 2005-08-01
Abstract: An optical recording apparatus comprises an optimum recording power calculating device capable of varying a recording power to perform a recording process on a test recording area of the erasable optical disc, and calculating an optimum recording power according to signals that reproduce the test recording area; and an optimum erasing power calculating device, for calculating an optimum erasing power from the optimum recording power and a coefficient corresponding to the optimum recording power. The optimum recording power and the optimum erasing power are used for recording the erasable optical disc. Thereby, even though the dispersion of the recording power becomes large, the erasing power is not greater than a certain range; therefore, the total of the recording power and the erasing power can be restrained while the degradation of the durability that the optical disc can be repeatedly recorded can be suppressed.
Patent TW-I257224-B (TW)
Title: System and method for automatically preserving space for packet in tunnel
Inventor: LIN JYUN-NAIH
IPC: H04L29/02
Filed: 2001-12-03
Granted: 2006-06-21
Abstract: The present invention relates to a system and a method for automatically preserving a space for packet in a tunnel, wherein a first gateway transmits an ICMP (Internet control message protocol) control message back to at least one source side host device and modifies the maximum segment size of TCP sync packet issued from the source-side host device. The modified sync packet is then transmitted through a second gateway to a destination-side host device. The destination-side host device, upon receiving the modified sync packet, transmits a confirmed sync packet back to the at least one source-side host device to complete the connection. Thereafter, at least one source-side host device, when attempting to transmit a packet to the destination-side host device, divides the packet for transmission on the basis of the maximum transmission unit indicated by the control message provided by the first gateway or the maximum segment size defined in the establishment of connection between the source-side host device and the destination-side host device. Thus, the size of packets transmitted from the source side can be controlled for preservation of space.
Patent TW-530373-B (TW)
Title: Semiconductor device having shallow trench isolation structure and method for manufacturing the same
Inventor: OH YONG-CHUL
IPC: H01L27/10
Filed: 2001-12-04
Granted: 2003-05-01
Abstract: A semiconductor device having a shallow trench isolation (STI) structure, which reduces leakage current between adjacent P-FETs, and a manufacturing method thereof. The device comprises a semiconductor substrate having first and second trenches, the first trench being formed in a cell area; a first sidewall oxide layer formed on inner surfaces of the first and second trenches; a second sidewall oxide layer formed on a surface of the first sidewall oxide layer in the second trench; a first relief liner formed on the first sidewall oxide layer in the first trench; a second relief liner formed on the first relief liner in the first trench, and also formed on the second sidewall oxide layer in the second trench; and a dielectric material formed within the first and second trenches.
Patent TW-593595-B (TW)
Title: Binder for powdered thermosetting composition, powdered thermosetting composition for coatings and method of preparing it
Inventor: MOENS LUC
IPC: C09D167/02
Filed: 2001-12-21
Granted: 2004-06-21
Abstract: The present invention relates to powdered thermosetting compositions including a binder which comprises a carboxyl group containing amorphous isophthalic acid containing polyester, a carboxyl group containing aliphatic semi-crystalline polyester, an optional and different carboxyl group containing semi-crystalline polyester, at least 5 parts by weight, based on the total weight of the binder, of a specific glycidyl group containing acrylic copolymer and a curing agent having functional groups reactive with the polyesters carboxyl groups. The powdered thermosetting compositions are useful for the preparation of powdered paints and varnishes which give semi-matt coatings having an outstanding flow, a remarkable weatherability and excellent mechanical properties.
Patent TW-594992-B (TW)
Title: Aluminum nitride and aluminum oxide/aluminum nitride heterostructure gate dielectric stack based field effect transistors and method for forming same
Inventor: BOJARCZUK NESTOR A JR
IPC: H01L29/78
Filed: 2001-12-28
Granted: 2004-06-21
Abstract: A structure (e.g., field effect transistor) and a method for making the structure, include a substrate having a source region, a drain region, and a channel region therebetween, an insulating layer disposed over the channel region, the insulating layer including a layer including aluminum nitride disposed over the channel region, and a gate electrode disposed over the insulating layer.
Patent TW-544783-B (TW)
Title: Intrinsic dual gate oxide mosfet using a damascene gate process
Inventor: BERTIN CLAUDE LOUIS
IPC: H01L29/423
Filed: 2002-02-19
Granted: 2003-08-01
Abstract: Damascene or non-damascene processing when used with a method that includes (a) forming a mask having an opening therethrough on a structure, said opening having sidewalls; (b) implanting an inhibiting species into said structure through the opening so as to form an inhibiting region in said structure; and (c) growing a dielectric layer on the structure in said opening, wherein the inhibiting region partially inhibits growth of the dielectric layer is capable of forming a semiconductor structure, e.g., MOSFET or anti-fuse, including a dual thickness dielectric layer. Alternatively, the dual thickness dielectric can be formed by replacing the inhibiting species mentioned above with a dielectric growth enhancement species which forms an enhancing region in the structure which aids in the growth of the dielectric layer.