Patent GB-1144778-A (GB)
Title: Automatic target detection radar system
Inventor: WILMOT RICHARD DEAN
IPC: G01S7/36
Filed: 1966-04-29
Abstract: 1,144,778. Pulse radar; transistor gating circuits. HUGHES AIRCRAFT CO. 29 April, 1966, No. 18994/66. Headings H3T and H4D. An automatic target detection apparatus responsive to amplitude-quantized radar video echo signals has a first circuit for determining whether the signals meet a statistical target criterion, a second circuit for determining whether the signals meet a statistical clear region criterion, and a third circuit responsive to outputs from the first and second circuits for indicating that a target encompassed by clear regions has been statistically detected. In the rotating-aerial pulse radar described, the quantized echo signals (" hits " and " misses," corresponding to a video signal level respectively above or below a threshold value) are fed to a toggle OTlFF, Fig. 1, which is also supplied with clock pulses C (representing range " bin " intervals) and which is connected to a writing circuit 24 associated with an X-Y storage array of ferrite cores 34. The clock pulses are fed also to writing and reading address registers 48, 46 which control respective switching units 44, 42 associated with memory 34, (ii) a range counter 50 from which the radar trigger pulse is derived, (iii) a register 26, and (iv) a timing circuit 60. One bit of information to be written into memory 34 comes from circuit 60 and another nineteen bits from register 36 comprising toggles P1 to P20. During each writing operation the bit from the oldest range sweep interval (toggle P20) is not shifted into register 26 and the new bit from toggle OT1 is written into memory 34. Also during writing the bits from toggles P1 to P19 are transferred to toggles PW2 to PW20 in register 26. The addressing of word positions is controlled from counter 50. To determine that clear areas occur in azimuth on both sides of a target area which may be eleven range sweeps, toggles 84, 86 develop " true " signals X A , X B  when those areas have, e.g., less than three hits in the same range bin in the five sweeps of each area (statistical zero criterion). For detecting target presence, outputs from toggles P5 to P15 are applied to an " E 0  " logic circuit 90 which passes a signal to toggle 94 when a selected bit density criterion is met. For detecting whether a selected miss density is met a " K 0  " logic circuit 98 is fed from toggles P 5  to P 15  and feeds into a counter 102 for determining whether there are e.g. six misses in eleven range bin intervals (statistical clear region in range). The Specification includes a graphical illustration (a part of the storage in memory 34) of a clear region on all sides of the target, Fig. 10 (not shown). " Valid " targets are displayed on P.P.I. 118; binary range and azimuth signals are provided. Transistor gating circuits, Fig. 2.-A toggle including transistors 122, 124 has input gates 130, 132; in e.g. the gate 130 two " true " i.e. ground potentials on terminals 148, 150 maintain transistor 140 non-conductive so that a negative clock pulse C causes transistor 122 to conduct to apply a " true " signal to terminal 136. If a " false " signal of - 8 volts is applied to either or both of terminals 148, 150 transistor 140 conducts and a " true " signal maintains transistor 122 non-conductive; a clock pulse C is passed to ground and the toggle is not set to its " true " state. An inductor 146 inhibits " racing " in a counter utilizing the toggle.