Patent GB-1390384-A (GB)
Title: Microprogramme computer
IPC: G06F9/26
Filed: 1972-06-14
Abstract: 1390384 Variable word length processors BURROUGHS CORP 14 June 1972 [28 June 1971] 27841/72 Heading G4A A microprogrammed computer for processing operands and data of variable length includes a main addressable memory 10, an arithemtic unit 12, registers 14, 16, 18, 20 for use in arithmetic and logic operations, registers 24, 25 used for addressing the main memory and a register 22 for storing the length of the data being processed. As described, programme instructions are stored in memory 10, each instruction being executed by a string of micro-operations stored in a memory 28, this memory also storing micro-operators for addressing the memory using register 26 to read out a new programme instruction. A memory 34 is provided for storing return addresses following a subroutine. Micro-operators.-Various micro-operators are described, each of 16 bits, having a variable number of bits representing the function to be performed, e.g. transfer of data, read/write, branching and a number of bits representing, e.g. stores to be accessed, the width of data to be transferred and branching addresses. Addition.-Prior to executing an "add" instruction, the starting address and the field length of the operands A, B are stored in register 24 and the zero location of register 26 respectively. The first micro-operaror is a bias operator which results in the lesser of the field length of the operand A stored in section FL of the register 24 and a constant K (fixed by the maximum length of data which the processor can handle), being entered into section CPL of register 22. The next micro-operator performs a read/write function transferring a number of bits of operand A into register 14, using the address section FA of register 24 to access the memory 10 and using the contents of section CPL to determine the number of bits to be transferred, with sections FA and FL being incremented and dercemented respectively by the number of bits transferred. Under the control of the next micro-operator the contents of register 24 and location zero of register 26 are exchanged to enter the operand B into register 24, the read process then being repeated, with no incrementing and decrementing of the stored addresses and field lengths, so that the operand B is entered into register 16. Arithmetic units 12 then adds the contents of registers 14 and 16 and enters the sum in register 20, the number of outputs transferred to the register being controlled by the length stored in section CPL. Any carry results in a flip-flop in register 22 being set. A "write" operation is then effected using the contents of section FA of register F as the address so that the sum replaces the operand B in memory 10. The address FA and word length FL are then incremented and decremented and an exchange operator causes the contents of register 24 to be exchanged with the contents of address zero in register 26 and address register 32 for the micro-operator store 28 is reset to the starting address to repeat the process until section FL is at zero when the next instruction is fetched from memory 10. Specifications 1,360,930, 1,390,385, 1,390,386, 1,390,387, 1,390,388, 1,390,389, 1,390,390 are referred to in the description.