Patent GB-1117905-A (GB)
Title: Data storage systems
IPC: G11C29/00
Filed: 1967-05-05
Abstract: 1,117,905. Faulty storage locations. INTERNATIONAL BUSINESS MACHINES CORPORATION. 5 May, 1967 [8 June, 1966], No. 20901/67. Heading G4C. In a data storage system, a word counter is updated as successive word locations in a main storage block are accessed and can be inhibited by means responsive to detection of a faulty location, an overflow block associated with the main block being accessed if necessary to exhaust the word counter. A store consists of 2<SP>x</SP> main blocks, each of 2<SP>n</SP> words, and 2<SP>x</SP> respective overflow blocks, each of 2<SP>y</SP> words. An address register for the store has an overflow bit position, set to 1 when an overflow block rather than a main block is to be addressed, and (x+n) bit positions to select a block and a word within the block. The n bit positions are set from a word address counter. A block address counter sets the x positions, except when an overflow rather than main block is to be addressed in which case the bits from the block address counter are shifted (n - y) bit positions into the n bit section of the address register (this will not interfere with the word selection since the remaining y bit positions are sufficient for word selection in an overflow block). A faulty word location includes a tag bit set to indicate this. Alternatively, where parity checking is provided, faulty words could be all set to 0 (or all to 1) to indicate their faulty state. When a word is addressed it is read out, and if its location is not faulty, it is gated to user equipment and also rewritten (in the case of a read operation) or replaced by a word gated from the user equipment and the replacement rewritten (in the case of a write operation). A word is neither sent to nor accepted from the user equipment in the case of a faulty location. A data transfer instruction can cause the accessing of one or more consecutive blocks, word by word, the instruction presetting (a) the block address counter to specify the first of the blocks, (b) a block counter to specify the number of blocks, and (c) a word count register to specify the number of words required in the last of the blocks (being 0 if all 2<SP>n</SP> are required). The word address counter is set to 0 to address the first word of the first block required. Each of the required blocks is addressed in turn, word by word, with incrementing of the word address counter by 1 after each word, incrementing by 1 of the block address counter after each block, and decrementing of the block counter by 1 after each block. At the start of each block, except in the case of the last block required if the whole of this block is not wanted, the word counter is preset to all 1's, and is thereafter decremented by 1 for each non-faulty word. In the case of the last block required, if the whole of it is not wanted, the word counter is preset from the word count register rather than with all 1's. In the absence of faulty locations, consecutive main blocks would be accessed in turn and the overflow blocks ignored. If the required number of non-faulty words is not present in a given main block, as indicated by the relative states of the word counter and word address counter, words in the associated overflow block are accessed after all the words in the main block until the word counter (decremented by 1 for each non-faulty word) reaches zero. The flow of words to or from the user equipment can be made uniform if the first word in each block is non-faulty and no two adjacent words are faulty, by using the tag bit to indicate whether the next word is faulty and incrementing the word address counter by 2 if so, to skip the faulty word. Uniform flow can also be achieved if two tag bits are used and there are never four adjacent bad locations, the word address counter being incrementable by 1, 2, 3 or 4.