Patent GB-1252217-A (GB)
IPC: G09G1/18
Filed: 1969-12-24
Abstract: 1,252,217. Cathode-ray tube displays; transistor waveform generators and pulse discriminator circuits. PHILIPS ELECTRONIC & ASSOCIATED INDUSTRIES Ltd. 24 Dec., 1969 [27 Dec., 1968], No. 62798/69. Headings H3T and H4T. [Also in Division H3] In an arrangement for displaying Alpha- Numeric &c. characters in dot matrix form on the screen of a cathode-ray tube the beam bright-up requirements in the production of each character and the horizontal and vertical beam deflection requirements for producing and positioning each character matrix are specified by respective elements of a sequential three element composite signal. Fig. 1 shows the general scheme in which clock pulses from generator 3 are fed to a modulator 9 supplied with data information from a source 2 (e.g. a computer) and operating to pass or not to pass the clock pulses to a summation device 10 depending, respectively, on whether a brightened dot is, or is not, required.. The clock pulses are also fed to a ¸9 divider 5 producing pulses for controlling the scanning of the (vertical) columns of the matrix and then via ¸ 6, ¸ 7, ¸ 11 dividers 6, 7, 8 producing pulses controlling the positioning of successive matrices in the horizontal direction, both sets of pulses being fed to the summation device 10. Fig. 2 shows the pulse train produced by the modulator 9 in respect of the character A formed, as shown in Fig. 3, by bright-up of selected dots in the matrix, the brightened dots, shown in full lines, corresponding to the similarly numbered full line pulses shown in Fig. 2. A maximum of seven clock pulse positions t 3  is provided for in each (vertical) column and five columns C 1 -C 5  are provided, two clock pulses periods (t 2 ) serving for beam fly-back between successive columns and eleven clock pulse periods t 5  serving for spacing (C 6 ) between successive matrices. Each matrix together with its spacing columns C 6  thus occupies a period t 6 , 64 matrices are produced on each line (Fig. 4) and a period of 13xt 6  is allowed for fly-back between adjacent lines. The dividers of Fig. 1, comprise transistor blocking oscillators (Fig. 5, not shown) and the summation device 10 (also Fig. 5, not shown) comprises transistors operating with different bias levels so that each element of the composite (sequential), three element signal is produced at a different amplitude level. Fig. 11 shows this signal in which the beam bright-up pulses (i.e. those occurring during successive t 3  periods) are produced with an amplitude of + 1, the matrix column synchronizing pulses (during period t 2 ) with an-amplitude of -1 and the line synchronizing pulses (13xt 6 ) with an amplitude of -2. This signal is sent over a transmission line 11 to a display unit 12 including a separation circuit 13 which, as shown in Fig. 6, comprises an impedance matching transistor stage 105 the output of which (the waveform of Fig. 11) is supplied directly to amplifier 14 controlling the beam bright-up of tube 26 and is also supplied to separation networks including transistors 117, 128 and 120, 129. The base bias of transistor 117 is adjusted to cut-off at the level (-1) so that it passes the column synchronizing pulses (t 2 ) via a differentiating capacitor 122 to transistor 128 and thence via a second differentiating capacitor 130 to the column deflection generator 15 comprising a mono-stable circuit (transistors 139, 150) the pulse output of which is integrated by capacitor 157 to provide via amplifier 18 the (vertical) column deflection waveform for deflection coil 23. The line synchronizing pulses (13xt 6 ) are separated by adjusting the base bias of transistor 120 such that the level (-2) is transferred via differentiating capacitor 123 to the base of transistor 129 which is biased to cut-off for level (-) but is conducting for the level (-2). The output is then fed via differentiating capacitor 131 to the line deflection generator 16 (similar to column deflection generator 15 except for parameter values) which produces via integrating capacitor 154 and amplifier 19 the (horizontal) line deflection waveform for deflection coil 24. Frame (vertical) deflection is effected by a step waveform (Fig. 14) produced by supplying the pulse output at the collector of transistor 140 (in the line deflection generator 16) to charge a capacitor 158 which is discharged by a thyristor 161 when the voltage across the capacitor exceeds the voltage at the ignition electrode of the anode. This voltage is set by the divider formed by resistors 159, 160 and, in the case of the eight line display of Fig. 4, the generated step waveform has an overall trace time of (8x64xt 6 ) + (8x13xt 6 ) and a fly-back time of 13xt 6 . After shaping in circuit 20 the step waveform is supplied to a further (vertical) deflection coil 25 via amplifier 21. If a monitor with a special frame (vertical) deflection coil of low stray-capacitance is employed such coil may replace the two deflection coils 23, 25. Alternatively, electrostatic deflection may be used.