Patent GB-1322386-A (GB)
Title: Integrated phase-shifting microcircuit
IPC: H01L27/00
Filed: 1970-12-11
Abstract: 1322386 Semi-conductors THOMSON-CSF 11 Dec 1970 [16 Dec 1969] 59159/70 Heading H1K A switchable phase shifter (Fig. 1) comprising grounded and ungrounded transmission lines L, M excited with HF oscillations is sequentially subdivided by junctions P, Q, R etc. of the transverse branches T 1 , T 2 , T 11 , T 12  etc. lying in pairs in opposite sides of line L and connected to ground over series diode capacitance inductance loops D 1 , C 1 , D 2 , C 2 ; D 11 , C 11 ; D 12 , C 12  etc. Bias voltages are applicable to D 1 , D 2  and to D 11 , D 12  etc. over respective common leads to their capacitance junctions for segments PQ, QR etc. Blocking positive bias disconnects and negative bias connects a loop in shunt across the conductors so as to selectively vary the phase delay of the line in steps dependent on the number of segments; the shunt impedance being capacitive or inductive according to the diode state. Structurally (Figs, 2, 3) lines L, M and branches T 1 , T 2  etc., are formed on a silicon wafer 1 oxide coated at 2, 3 on its major surfaces with continuous metallic layer M on its lower surface, and discontinuous layer L on its upper surface. The layer is diffusion doped at P + and N+ to form diode anode and cathode regions separated by intrinsic regions I, and the P+ regions contact extremities of branches T 1 , etc. through apertures of the oxide layer, and wider regions N+ are common to diode pairs D 1 , D 2 ; D 11 , D 12 ; etc. Bias is fed to the latter layers over incisions 4 extending into N + regions and metallically lined. In a modification (Fig. 4 not shown), zones N+ are extended to the upper oxide layer to contact a metallic terminal and the thickness of the wafer underlying the extension is reduced by a recess in the lower surface, to minimize the necessary diffusion depth. In a further modification (Fig. 5 not shown) the recess is widened to underly the corresponding diodes. The P and N regions are interchangeable, with corresponding bias polarity reversal. The completed device is enclosable in a housing with coaxial or 2 or 3 wire microstrip connections, and the incisions and recesses are formed by selective etching over a mask and the electrodes are vapour deposited. Capacitance values and loop dimensions are variably designed to establish desired response characteristics, and branch points P, Q, R are displaced #/4 while the branch lengths are #/8 and the line impedance <-< the shunt path impedance. In further modifications (Figs 6 to 8 not. shown) the reactive series diode capacitance inductance loops are separated from the line L and connected thereto by series diodes and capacitances; the branches being interconnected by conductor sections each forming one plate of a coupling capacitor whose opposite plate is the grounded layer M; the intervening semiconductor regions being N or P doped to reduce their resistance values. A reflex phase shifted may be connected across the transmission line output and is switchable by a similar biased diode between O and # to double the phase shift selectively introduced by the line segments; the connection being over a ribbon in series with L of length equal to a small fraction of # to form an induedance with an intermediate point grounded through a capacitor comparable with the terminal diode capacitance.  The device is applicable to a radar antenna array sweep circuit.