Patent GB-1267607-A (GB)
Title: Time division multiplex communication systems
IPC: H04B7/212
Filed: 1969-08-15
Abstract: 1,267,607. Communication system. FUJITSU Ltd. 15 Aug., 1969 [15 Aug., 1968 (2)], No. 40994/69. Heading H4L. General.-Specification describes a P.C.M., T.D.M. satellite communication system, of the type wherein N ground stations, Fig. 1 each transmit a P.C.M. burst B1-BN to the other ground stations via a satellite S, the bursts being positioned in respective allotted time slots, whereby they form a non-overlapping train at the satellite and said train is received at each ground station. In the case of a non-stationary satellite, ground station/satellite distance variation shifts the relative time positions of the burst of the satellite whereby interfering overlapping can occur. Said shifting is reflected in the ground station reception whereby synchronous demodulation of the P.C.M. is made impossible. In a ground station, a memory Ml, Fig. 4 is provided in a receiver synchronizing circuit (RSYC), Fig. 3, having N addresses, the nth of which stores the time interval between consecutive burst Bn-1 and Bn in the preceding frame. The stored intervals are used to generate gates whereby the arrival times of the corresponding real time burst are tracked and the stored intervals updated by any tracking error detected. Assuming little time change from frame to frame, the stored intervals are used for the synchronous demodulation of the P.C.M. signal and other timing functions. The transmitter synchronizing circuit TSYC detects from the contents of said memory any out of time positioning of its burst at the satellite and accordingly varies the transmission time of the next burst. In the ground station, Fig. 3, the voice information from control CT is sampled in device PAM, MOD and pulse code modulated in device COD. Considering station 1 the transmitter channel control circuits (TCHC) and the transmitter synchronizing circuits (TSYC) cause the modulated voice information to occupy channel CH1 in burst B1, the burst also containing synchronizing portions CR, BR, a station identifying portion UW and a control information portion OCH all added in circuit (TCNC). The burst B1 is then modulated on to a carrier in circuit (MOD) and transmitted by radio transmitter (RFT). The received train of bursts B1 ... BN is received from the satellite and the carrier demodulated in circuit (DEM). The train of bursts passes to pulse code demodulating circuit (DEC) for synchronous demodulation under the control of receiver channel control circuit (RCHC) and receiver synchronizing circuit (RSYC) and the various voice information channels CHI, CH2 ... CNN, are distributed by a system of gates (PAM.DEM). The system is monitored and the initial timing relations set by a control processing unit (CPU) and memory (MEM). Information from (CPU) is transmitted on information channel OCH. Receiver synchronizing circuit, Figs. 4, 5.-In addition to memory M1, circuit (RSYC) comprises a memory M2 having N addresses, and five store areas, respectively storing:- (1) Is burst interval in use? (WORK) (2) Has synchronization been obtained for burst? (SYNC) (3) Ground station identification pattern UW. (U.W.) (4) How many times has identification pattern UW not been detected (ERROR) (5) Number of next burst (NEXT BURST) The output of area (5) enables a series of flip/ flops BF1/BFN to produce a sequence of address pulses b1/bN. Assuming an address pulse b1 at address input AD2, the B 1 identification pattern UW1 is fed to coincidence detector (MATCH). The pulse code burst B1 is fed from carrier demodulators DEM 0 , DEM 1 , to a shift register SR, during time T(P 2  to P 6 )-see later-for comparison of the UW portion with UW1. At the instant of established match, i.e. at the end of the UW portion, a pulse UWP is produced. The address pulse b N  (i.e. that before b 1 ) has been applied to address input AD 1  of memory M1 which has read out to backward counter CCO at time P2 a count indicating the predicted (i.e. that found in the previous frame) interval between pulses P2 for the burst B N  and pulse SB indicating the start of burst B 1 . A clock pulse CL<SP>1</SP> counts down CCO which produces a SB pulse when its count reaches zero. Pulse SB starts a timer (TIMER) which produces time pulses. P 1  ... P 4 , P-#, P+#, P 6 , P 7 , P 8 . An early gate T[SB - (P - #)], ((f), Fig. 5) and a late gate T[(P + #) - P6], (e), are also produced and are fed, with pulse UWP to early and late gates and flip/flops FFE and FFL respectively. If the pulse UWP occurs before its anticipated time [(P - #) # (P + #)], FFE is set and circuit A4 subtracts a 1 from the interval (P 2 -SB) stored in memory M1, or if the pulse occurs after said time, FFL is set and A3 adds a 1 to said interval. A pair of flip/flops FF0, FF1 produce a pulse UW, if the signal UWP is not detected in the interval (SB-P6), which is added to the count in area (4) of memory M2. When this count has reached a particular level a signal (OF) is produced which is carried to area (2) to indicate loss of synchronism, which area produces a signal (SYC) which rapidly adjusts the count in counter CCO until synchronism is recovered. Pulses UWP and SB are therefore phase locked to the bursts. Receiver channel control (RCHC), Figs. 6, 7.- Clock pulses CL and pulse UWP are fed to digital counters and decoders DC, CHC, DEC 1 , DEC 2  to produce a series of bit pulses d1/d8 defining the times of the eight bits in the code of the P.C.M., which pulses are fed to the PCM decoder (DEC), and a series of channel defining pulses Ch1/Chn and OCh. The data and information channel OCH is separated out by pulse OCh, verified by check circuit CK and passed to area (2) of memory M3, for possible use by the control processing unit. Assuming that the satellite has capacity for 14 information channels, and that burst B1 uses 4 channels, burst B2 uses 4 channels and that burst B3 uses 6 channels; memory M4 is provided with 14 addresses AD 4  in each of which is stored the number of the voice channel TRK(i) to which the information in the designated channel is to be fed. Area (1) of memory M3 stores in its three addresses (there are three bursts), the total number of channels used in the previous bursts. Thus if the 4th channel of burst B3 is to be fed to voice channel TRK(i), then address AD3 is fed with b3 so that number 8 is read out, and channel pulse Ch 4  (4) is added to said number in ADD means, to produce an AD 4  address of 12, whereby the voice channel number TRK(i) is read out to enable gating means DEM-G in said channel to pass the output of decoder DEC. Transmitter synchronizing circuit (TSYC), Fig. 8.-Fig. 9 shows at (a) burst B1 as transmitted from ground station 1. At (b) is shown, burst B1 as received, together with the other bursts B2/BN, at the satellite, and at (c) the train of bursts as received back at the ground station 1. The (TSYC) circuit of ground station 1 operates to control the interval between the time SB1 of receiving back the start of burst B1 and the start ST1 of the next burst B1 transmission, so that the interval between the end of burst BN and the start of burst B1 at the satellite shall be a required amount. An initial value for the interval (SB 1 -ST 1 ) or (SB 1 -TR) is thus set in register (SB1-TR) by the control processing unit (CPU). The end of the received burst BN is detected by means (GTR) and (MATCH 1 ) using timing signals from the (RSYC) circuit, to produce a signal STO, (b) Fig. 10. This signal starts a timer (TIM) which generates P<SP>1</SP>o and P<SP>1</SP>1. These cause flip-flops FFE and FFL to generate early and late gating pulses (e) and (f), Fig. 10 for tracking the time of pulse SB1. The value stored in register (SB1 -TR) is accordingly added to or subtracted from, according to whether pulse SB1 is early or late. The corrected stored value is fed to comparator (MATCH 2 ), the other input of which receives a counter (c) output, counting clock pulses CL<SP>1</SP> and started by pulse SB1. Comparator (MATCH 2 ) produces the starting pulse ST1. Transmitter channel control (TCHC).-Register (PAWR) holds the synchronizing signals CR, BR and the identity signal pattern UW and is read out to the P.C.M. transmitter by a pulse started by pulse ST1 and ended by a " beginning of channel CH1 " pulse. Channel pulse generators and bit pulse generators CHC<SP>1</SP> and DC<SP>1</SP> are also started and controlled by pulse ST1. The voice information TRK is modulated on to the correct channel CH by use of the correct channel pulse Ch<SP>1</SP> n  on gate MOD-G.