Patent GB-1347438-A (GB)
Title: Memory syxtem
IPC: G05F3/22
Filed: 1972-10-27
Abstract: 1347438 Transistor switching circuits INTERNATIONAL BUSINESS MACHINES CORP 27 Oct 1972 [30 Dec 1971] 45941/72 Heading H3T [Also in Division G4] In a memory addressing circuit, the individual cells of the memory and switching circuits for addressing the selected cell are transistorized. The memory comprises 72 cards each having a 16 x 4 array of chips, each chip comprising a monolithic array of 32 x 16 cells. Address bits are applied to an emitter decoder 4 (Fig. 1), base decoder 9, emitter switch 7 and column select drivers 14 to select a chip, further address bits being fed to emitter and base decoders 43, 43<SP>1</SP> (Fig. 2), emitter switch 46 and bit decoders 51, 56 to select a cell on the selected chip. Emitter switch 7 (Fig. 4, not shown) couples decoder 4 to power gate drivers 12. Transistors (170, 180) provide a voltage regulated supply to the base of transistors (167-169) the collectors of which are connected to the emitters of transistors (154, 157). The signal from decoder 4 is fed to the base of one of the transistors to activate one of four output lines 8. Power gate driver (Fig. 6).-Each of the output lines of address decoder 9 and switch 7 are connected to the base of a column of transistors and to the emitter of a row of transistors respectively so that one transistor 270 is rendered conductive. This results in transistor 274 cutting off and transistor 279 turning on and acting as an emitter follower to cause a rise in potential at the base of transistor 284 which also acts as an emitter follower to cause a rise in potential at output line 13. Transistors 293 and 294 provide feedback to limit the upward swing of line 13. Data input/output circuit (Fig. 13, not shown). -The data input/output circuit transmits data at a pair of terminals (528, 529) to terminals (68) and from a terminal (66) to terminals (528, 529) under the control of a read/write signal at terminal (65). For a read operation, i.e. with a low signal at terminal (65), a transistor (538) is activated to activate transistors (534, 535) which act as differential amplifier to provide output signals on the data output line (68). For a write operation transistors (547, 552) are activated by the conduction of a transistor (567) so that the signal on data-in line (66) turns on either transistor (547) or transistor (552), the potentials of the connectors of these transistors being transmitted to the terminals (528, 529) and hence to the memory cell. Memory cell (Fig. 14).-Each cell comprises a pair of transistors 588, 589. If during a read operation, in the selected cell transistor 589 is conducting and transistor 588 is not, when the potential of the pair of lines 62 is raised current will flow first in diode 593 and then in diode 592 to power up the cell. The resulting offset voltage across the collectors of transistors 588, 589 is transmitted via diodes 526, 527 to the line 69 of the input-output circuit. If during a write operation it is required to change the conductive states of the transistors to, for example, render transistor 388 conductive, the potential on the right-hand line 62 raises so that current flows through diode 593 to turn on transistor 588. Transistor 589 is subsequently cut off by lowering of its base potential. The transistors of all the cells in a row are connected by a diode 602 to current sink 603.