Patent GB-714094-A (GB)
Title: Improvements in or relating to electric pulse code modulation signalling systems
IPC: H03M1/00
Filed: 1952-01-18
Abstract: 714,094. Electric selective' systems. GENERAL ELECTRIC CO., Ltd., BAYLIS, A. J., and STENNING, L. C. Jan. 2, 1953 [Jan. 18,1952], No. 1520/52. Class 40 (1). In a pulse-code-modulation signalling system, the number of signal pulses transmitted in each of a series of intervals are counted at the transmitter and at the receiver, and compared at the receiver, where a warning device is actuated if the counts do not agree. In a multichannel system a separate channel may be used for transmitting the transmitter counts to the receiver. In a single channel system the normal signal transmission may be interrupted in order to transmit the count. As described, however, applied to the ten channel telemetering system disclosed in Specification 713,476, the number of digit pulses transmitted during each ten successive signal channel intervals, is counted, and transmitted during the synchronising channel interval which follows the ten interlaced signal channels. The channel intervals each have eight digit positions so that a maximum of eighty digit signal pulses may be transmitted in ten signal channels, which would require a seven digit binary counter for complete registration. Since the first and the last two digit pulse positions in the synchronising channel interval are used for synchronising purposes only five pulse positions, the second-sixth, are available therein for transmission of the count. Only the last five digits of the count are therefore transmitted so that the comparison check is only partial. Alternatively, single digit counters could be used in which case only discrepancies of an odd number of pulses would actuate the warning device. Transmitter, Fig. 1.-The line pulses from the output unit 4 of the transmitter 1, as disclosed in Specification 713,476, are fed to line 3, and also, through a gating circuit 5 controlled by the channel distributer 6, to a five digit binary counter 7 which registers pulses transmitted during the signal channel intervals only. Gating circuits 9-13 are connected to the outputs of the individual digit elements of the counter 7 and are pulsed respectively from the outputs D1-D5 of the digit distributer at the second-sixth time positions of each channel interval. The outputs of these gates are controlled by a further gate 14, opened during the synchronising interval only, by a pulse from the channel distributer output CS. Thus during the second-sixth time positions in the synchronising channel interval, digit pulses are passed by the gates, from those of the respective counter digit elements in which a digit is registered, to the output unit 4, and transmitted over line 3 to the receiver 2. A reset circuit 15, operated by the digit distributer output D6, D7 during the synchronising channel interval, zeroises the counter 7 ready for the following line signal pulses. Transmitter elements; circuits, Fig. 2.-The gate circuit 5 comprises a cold cathode triode 50 to the anode of which output pulses from the unit 4, Fig. 1, are fed over point 52. These pulses are also fed over a potentiometer 54, 55 to a cold cathode diode 51. During the synchronising channel interval the positive channel output pulse CS is fed over point 58 and prevents the tubes 50, 51 from firing. During the signal channel intervals, however, each input pulse fires the diode 51 and triode 50 in turn to pass a positive pulse from the triode cathode to the counter 7. Counter.-Each stage of the five-digit-binarycounter consists of a cold cathode triode pair 60A-61A, 60B-61B, ... 60E-61E, connected in a bi-stable trigger circuit. In the zero position of the counter the right hand tubes 61A-61E are fired, each input pulse to a stage reversing the 'condition of that stage in the usual way and passing a pulse to the next higher stage as its zero tube 61A-E is fired. Gating circuits 9-14.-The digital gating circuits 9-13 each consist of a cold cathode diode 80A-E, the anodes of which are pulsed, respectively, from the digit distributer outputs D1-D5 in the second-sixth time positions in each channel interval over points 85A-15. In addition, a positive potential is fed to each diode anode from the midpoint of the load resistors of the associated: stage counter tube 60A-E if the latter is fired. Each diode 80AE, will fire only if pulsed when this potential exists; i.e., if a 'digit is registered in the associated counter stage. Positive digit pulses corresponding to the setting of the individual stages of counter 7 are thus produced in the second-sixth time positions of each channel across load resistor 81 and fed to the gate 14. This consists of a cold cathode triode 90 which fires only when pulsed concurrently from a digit gate, 80A-E, and from the channel distributer output CS applied to point 97. The counter setting is thus only passed by the gate 14 during the synchronising channel interval, the gate output pulses being fed from point 93 to the receiver output unit 4 as above described. Counter reset circuit 15.-This comprises cold cathode triodes 100, 101 connected in a bi-stable circuit, and operable only during the synchronising channel interval when the channel distributer output CS biases both trigger circuits over point 58. In the seventh time position of this interval, the digit distributer output D6 is fed over point 102 to fire the triode 100 and extinguish 101. A relay 103, operates in series with the triode 100, and at its contact 79 connects H.T. positive to line 78, thereby firing cold cathode diodes, 77A-E, which in turn fire their associated counter tubes 61A-E (if not already fired) to zeroise the counter. At the eighth time position, the digit distributer output D7, applied at 105, fires the triode 101 which extinguishes 100, whereupon relay 103 relapses and extinguishes the diodes 77A-E leaving the counter 7 at zero ready to count the signal pulses in the succeeding signal channels. Receiver, Fig. 1.-The line pulses are fed to the receiver 2 as described in Specification 713,476, and also through a gating circuit 20, controlled by the channel distributer 22, to a five digit binary counter 21 which counts only those pulses transmitted during the signalling channels. The five digital stages of the counter are each connected to the corresponding digital comparison circuit 23-27 to which are also connected the corresponding second-sixth digit present circuits 28-32 of the receiver 2. The digit present circuits are set during each channel interval according to the binary value transmitted during the corresponding interval and reset at the end of each interval. After the transmitter count, transmitted as above described iri the second-sixth time positions of the synchronising channel interval, has been set on the digit present circuits, a gate circuit 34 actuated by concurrent pulses from the channel distributer , output CS and the digit distributer output D6, i.e., in the seventh time position, energises the camparison device which operates a warning/device 35 if there is a discrepancy in any of the five digits registered on the counter and digit present circuits. The synchronising relay unit 36 in the receiver 2 which responds to the long pulse covering the last two time intervals in the synchronising channel interval resets the counter 21 and the comparison circuits. Receiver elements; circuits.-The gating circuit 20 and the digit stages 21A-E, of counter 21 are similar, and operate in the same manner as the gate 5 and counter 7 at the transmitter, to count the line pulses transmitted during each ten successive signal channel intervals. Zeroising of the counter 21 is effected, however, by the synchronising relay circuit 36 which connects H.T. positive to point 113 after comparison has been effected. The digit present circuits 28-32, Fig. 1, as described in Specification 713,476, each include a cold cathode triode which is fired if the corresponding digit pulse is present in the pulse code group received, to apply a positive potential to the point 115A-E in the corresponding digital stage 23-27 of the comparison device. Gating circuit 34.-This comprises cold cathode triodes 116, 117 to the trigger electrodes of which a positive bias is applied from CS only during the synchronising channel interval over point 111. Both tubes 116, 117 thus fire at the seventh time position in the synchronising channel interval when the digit distributer output D7 is applied to points 118. A positive pulse is fed from the cathode of triode 116 and a negative pulse from the anode of triode 117 to the comparison circuits until the tubes 116, 117 are extinguished by the synchronising relay circuits 36 somewhat after the seventh time position, by removing the H.T. supply from point 119. Comparison and alarm circuits.-Each comparison circuit 23-27 compares the state of the "o" i.e., the right hand triode in the corresponding counter stage 20A-E with that of the triode in the corresponding digit present circuit. Normally the "o" valves should all be in the opposite state to the digit present valves. Each comparison circuit is therefore in two parts, one for checking whether the "o" counter valves and the corresponding digit present valves are both fired, and the other part to check whether they are both' extinguished. All the comparison circuits are identical. Consider circuit 23, for example. When the positive pulses from triode 116 in gate 34 is applied to the anode of a cold cathode diode 120A, it fires only if the associated digit present valve is fired and therefore feeds - a positive potential to point 115A. The diode 120A then applies a positive pulse to the anode of a further cold cathode diode 121A which fires only if the associated counter "o " valve is fired to apply concurrently a positive potential to the anode of diode 121A. When the diode 121AE in any of the comparison circuits fires, it applies a positive pulse to trigg