Patent GB-1489191-A (GB)
Title: Radiation pick-up arrangement comprising a series of radiation-responsive charge storage elements intercoupled to form an information shift register
IPC: H04N5/372
Filed: 1974-08-16
Abstract: 1489191 Television PHILIPS ELECTRONIC & ASSOCIATED INDUSTRIES Ltd 16 Aug 1974 [20 Aug 1973] 36188/74 Heading H4F An analogue information pick-up arrangement comprises a series of pick-up elements D each associated with a respective stage P of a charge-transfer shift-register PP1 from which information may be shifted into a further (reversible) shift-register SS1 where it is shifted in one direction during an input period and in the opposite direction during an output period, the two shift-registers being designed such that the information undergoes degradation which is uniform and independent of place of origin. Thus, if the register PP1 operates with a total number n of different switching operations (two per stage), the information (Px) originating in the stage Px undergoes 2(n + 1 - x) switching operations before application to the terminal K1 The information is applied to register SS1 and is shifted therein to the stage Sx and then back to the terminal K1, thus undergoing (2x-1) switching operations. If the degradation factor in register PP1 is a, and that in register SS1 is b, the total degradation of information (Px) is: and this can be made independent of x by arranging that b = a/2. This is possible to arrange in practice, since the register SS1 is without the pick-up elements which constrain the design of register PP1. The register PP1 shown comprises five stages P1... P5, containing odd and even series of capacitors C1... C9; C2 ... C10, odd and even series of transistors T1 ... T9; T0 ... T10, and odd and even series of photo-diodes (pick-up elements) D1... D9; D2...D10. The transistors are of the isolated-gate type. The register SS1 has similar odd and even series of elements, but the mode of interconnection of the elements (evident from the Figure) differs in the two registers such that the register SS1 may be reversed under control of a clock-pulse source G1 common to both registers. Information is read out under control of clock pulses during successive periods w, z, Fig. 2, which recur periodically and are spaced by much longer periods w<SP>1</SP> during which the diodes D acquire information in the form of negative changes. At the end of each period w<SP>1</SP>, signal F triggers a counter G1 which delivers two series A, B of 2n pulses to terminals w, z of switches Q1, Q2, Q3 (the last receiver only pulses A). The switches are actuated by pulses H (from counter G2) which changes the movable contacts between terminals w and terminals z at the ends of periods w<SP>1</SP>, w and z. The circuits T1, C2, &c. of register PP1 receive the signal A, O and the circuits T0, C1, T2, C3, &c. the signal B, O, through switch Q1, both these signals being zero during periods z and w<SP>1</SP>. Thus, the information is shifted through successive stages P to the terminal K1 during periods w as is indicated by the voltages U1, U2, U9, U10, Fig. 2. Control signals A, A and B, B are fed to the register SS1 directly from the counter G1 and control signals A, B and B, A through the switch Q2. These cause the register to shift the information originating at terminal K1 forward during periods w and backwards during periods z whereby the signal U11, Fig. 2, appears at terminal K1. Switch Q3 is actuated at the end of periods w and causes transistors T21 and T22 to conduct during the periods z wherein the output signal UK10 of the device appears at terminal K10. During periods w, the transistors T21, T22 are cut off by virtue of the earth connections made by the switch Q3. The invention may be applied to a bank of shift registers PP1, PP2, ... PPm (see Fig. 4, not shown) which are read out in turn. Two reversible registers SS1, SS2 are employed and are connected to the outputs of the bank PP1 ... PPm by a commutator switch actuated in such a manner that reversible register SS2 is being fed with information from an even numbered member of the bank PP whilst information previously derived from an oddnumbered member of bank PP is being read out of register SS1, and vice versa, the registers SS1, SS2 operating in opposite directions at any one moment. Fig. 5 shows an arrangement in which three shift registers PR1, PR2, PR3 associated respectively with pairs of reversible registers SS1, SS1<SP>1</SP>; SS2, SS2<SP>1</SP>; SS3, SS3<SP>1</SP>. In the shift registers PR the diodes are separated from the shift elements when the information is being fed out. Each register is read out without information being transferred from pick-up to shift elements and subsequently with such information being thus transferred. Each pair of reversible registers SS is connected to a respective subtraction circuit L which produces the difference of the two read-out signals whereby correction of the registers PR is achieved. A commutator switch Q4<SP>1</SP> is so actuated that information is being fed into one reversible register as it is being fed out of the next one.