Patent GB-1417170-A (GB)
Title: Methods of manufacturing semiconductor devices
IPC: H01L23/522
Filed: 1972-12-22
Abstract: 1417170 Semi-conductor devices MULLARD Ltd 22 Dec 1972 59337/72 Heading H1K A silicon integrated circuit comprises a 1024 bit random occurs memory wherein each cell comprises P-channel polycryatalline Si insulated gate field effect transistors. In such a transistor, a N-type slice with (111) face orientation is coated with SiO 2  at 2 by thermal treatment in wet oxygen, an opening is etched over photo-resist to expose the semi-conductor surface, and a further oxide layer 4 is formed by thermal treatment in dry O 2 . A layer 5 of un-doped polycrystalline Si is deposited by thermal decomposition of silane in N 2  and a masking SiO 2  layer 6 is formed therein by thermal oxidation in O 2 . An opening 7 partly overlying the thinner oxide layer 4 is etched in layer 6 over photo-resist so that a first part of layer 5 remains masked by SiO 2  layer 6. Boron is thermally deposited from oxidized boron nitride in N 2  and thermally driven into the unmasked part of the polycrystalline Si (Fig. 1e, Fig. 2e). The remaining mask layer 6 is etched off in buffered HF, and layer 5 is etched in hot ethylene diamine, pyro catechol and H 2 O to preferentially remove the less conductive Si layer and leave a pattern of the boron doped conductive Si layer having a portion 8 centrally disposed of the thinner oxide layer 4 to form the gate electrode and other portions 9 disposed on the thicker oxide layer 5. Source and drain electrodes 10, 11 are formed by removal of the thinner oxide layer 4 and in diffusing B to the exposed substrate surfaces; the gate electrode 8 and its underlying oxide 4 and the thicker oxide layer 2 masking. Alternatively the exposed parts of the oxide layer 4 remain in situ and Bo is ionically implanted; the gate electrode and thicker oxide layers masking; after which the implant is thermally annealed (Figs. lg, 2g).  The upper surface is covered with SiO 2  layer 12 by thermal decomposition of silane + N 2  in presence of O 2 , and openings 13, 14 are photolithographically etched therein to expose portions of regions 10, 11 and opening 15 is etched in layer 12 to expose portion 9 of the doped polycrystalline Si layer 9 (Figs. 1i, 2i) after which an Al layer is deposited over the entire upper surface including the exposed surface regions. This is photolithographically etched into a pattern defining portions 17, 18 (Figs. 1k, 2k) conductively connecting to source and drain electrodes 10, 11 and portion 19 connecting to the polycrystalline gate electrode 8 over portion 9 of the doped polycrystal layer; these portions connecting to other circuit elements. Other IGFETs and integrated circuit elements are simultaneously formed with their appropriate interconnections. A further opening 23 is made in SiO 2  layer 2 as a continuation of opening 3 (Figs. 3b, 4b) and covered with a further rectangular oxide layer 4, after which a polycrystal Si layer 5 and SiO 2  mask 6 are deposited as before; the former contacting the substrate at 25 through opening 24 in layer 4 (Figs. 3, 4). Subsequently a further opening 27 is photolithographically etched in layer 6 as a continuation of layer 7 to expose part of layer 5. Bo indiffusion renders the latter highly conductive and forms P-regions in the substrate underlying the same (Figs. 3e, 4e). Layer 6 is etched off and the layer 5 is preferentially etched leaving the B doped portion contacting the substrate surface and overlying SiO 2  layer 2 to form a conductive gate connection. The exposed substrate portion and the thinner SiO 2  layer 4 are B ion implanted to form a P<SP>+</SP> region 30 partly forming a transistor drain and partly a low resistance connection between part 9 of the Si layer and region 30. The surface is covered with a SiO 2  layer 12 (Figs. 3h, 4h). A resistor element may be formed (Figs. 5a to 5k; Figs. 6a to 6k, not shown) by depositing an A1 mask, photo-masking and etching to define a pattern; boron implanting to form source and drain electrode regions and simultaneously resistor P<SP>+</SP> contact regions; after which the aluminium is removed and Bo + Ne ions implanted in the area previously overlaid by A1 to form P resistor contact regions. Thereafter a composite SiO 2  layer is deposited, and photo-masked and etched to apertures exposing the resistor contact regions, and Al is deposited, photo-masked, and etched to form resistor contact tracks connecting to other circuit elements.  Modified methods of forming resistor elements are described (Figs. 1f, 2f; Figs. 5g to 5k; 6j to 6k, not shown); (Figs. 7, 8; 7e to 7h; 8e to 8h, not shown).  Specification 1,371,496 is referred to.