Patent FR-2805653-A1 (FR)
Title: Serial memory of electrically erasable and programmable read-only type with advanced data reading, for use in computing
Inventor: CAVALERI PAOLA
IPC: G11C16/26
Filed: 2000-02-28
Abstract: The memory in the form of an integrated circuit (MEM1) has an input (DIN) and an output (DOUT) in series and comprises means including a multiplexer (MEX1) for data reading on the reception of a partial address (ADR1) wherein N low-value bits are missing with respect to a complete address. The advanced reading operation comprises the following steps: the simultaneous reading of P first bits, that is P1(W0), P1(W1), ..., P1(WM), of M binary words (W0,W1,...WM) of the memory with the same partial address, when the received address is complete, that is comprising (ADR1,ADR2), the selection of P first bits of word indicated by the complete address and the delivery of these bits to the output, and the reading of subsequent P bits of word indicated by the complete address during the delivery of P preceding bits, and the delivery of the subsequent bits to the output when the preceding bits are delivered. The reading of P subsequent bits is effected like the reading of first P bits, that is by simultaneous reading of subsequent bits of words having the same partial address, and the selection of subsequent bits of word indicated by the complete address.  The reading operation is effected by applying the partial address to a decoder and by scanning the low-value address inputs allowing for 2N possible combinations of N low-value bits (A0,A1,...AN-1). A memory unit comprising cells laid out according to word lines and bit lines, where the bit lines are laid out in columns, also comprises an address decoder for the simultaneous selection of P bit lines of M columns, and an interconnection bus for connecting the selected bit lines to the reading circuits, that is sense amplifiers. A memory unit comprises cells laid out according to word lines and bit lines, where a word line forms a page memory, and the reading operation comprises a preliminary step which includes the registering of M words of the same partial address in M adjacent sub-pages, of each word in P adjacent sets of cells, each comprising K/P adjacent subsets of cells, where K is the number of bits of each word, and of bits of rank j and j+1 of word in sets of adjacent cells, and of rank j and j+P of word in subsets of adjacent cells, so that the words are folded in the sub-pages. The number P is equal to K/M where M is equal to 2N; in particular, N = 1, and M = 2. The P first bits of each word are high-value bits. The address decoder comprises transistors for the selection of bit lines, a programming circuit comprising M times K latches connected to the input of data bus having K leads, and also the means for the inhibition of N low-value address inputs in reading mode. A multiplexer in memory unit with subsets of cells is controlled by a scanning circuit. A memory unit comprising a block memory and peripheral elements, also comprises the means for interlacing bits in the form of random-access memory positioned between the data input and the block input, to form composite words comprising M sets of P bits of M different binary words. The memory also comprises means for registering composite words in a buffer memory.