Patent GB-741132-A (GB)
Title: Improvements in or relating to an electronic device for translating a binary number into decimal form
IPC: H03M7/08
Filed: 1952-07-21
Abstract: 741,132. Digital electric calculating-apparatus. SOC. D'ELECTRONIQUE ET D'AUTOMATISME. July 21, 1952 [July 23, 1951], No. 18370/52. Class 106 (1). In an electronic device for converting a binary number, represented by a series-mode pulse train of not more than N digit periods, into decimal form, the train at 1, Fig. 1, is applied via an input channel and multiple point 11 to line comparators 13<SP>9</SP> to 134 where it is compared respectively with values proportional to 9 Î 10<SP>n-1</SP>, 8 Î 10<SP>n-1</SP> ... 1 Î 10<SP>n-1</SP> represented by pulse trains applied to channels 14<SP>9</SP> to 141, n being the lowest value for which (9 x 10<SP>n-1</SP>) exceeds (2<SP>N-</SP>1), each comparator including a trigger or " flip-flop " stage 17 which is set to one condition or the other, according to whether the value represented by the train at 11 is less or not less than the comparison value; the stages 17 control discriminators 31<SP>9</SP> to 31<SP>1</SP> associated with indicating trigger stages 37 which are connected to corresponding input channels of a decimal-digit-indicating device and control associated gates or " conditional transfer stages " 39 to which are applied by means 44<SP>9</SP> to 441 pulse trains representing the complement of the comparison values with respect to 2<SP>N</SP>; one of the gates is opened, corresponding to the first decimal digit of the converted number, to pass the corresponding train to a common output channel 47 and an adding circuit to which is also applied, through a delayed-transmission channel, the train at 11; and the output of the adding circuit is multiplied by ten and re-injected at 11. As shown, an additional discriminator 31<SP>0</SP> and zero-indicating trigger stage 37 are provided. A series-mode binary pulse train of 16 terms, the first of which represents the sign, is applied at 1 to a network 2 which effects division by two by delaying the train by T - #, where T is a minor cycle period (166) and # a digit period. The sign pulse is diverted to sign-registering means comprising a bi-stable trigger stage 7 with an output line 9, and the halved number is passed to point 11, by gates 3, 4, respectively, e.g. pentodes, having control pulses applied to their terminals 5, 6. In the comparators 13<SP>9</SP> to 13<SP>1</SP>, the halved number is compared with <SP>9</SP>/ 2  Î 10<SP>4</SP>... 1/ 2  Î 10<SP>4</SP> produced in binary series-mode form by tapped delay lines 15<SP>9</SP>-15<SP>1</SP> and mixing resistors. These delay lines may be incorporated in a single " primary distribution " line producing all the required control pulses. Each comparator includes a pentode 19, Fig. 2, for reshaping the comparison train from the line 15, and the outputs of gate 4 and pentode 19 are applied through the connections 121, 122, 141, 142 to tubes 24, 25 of an anti-coincidence circuit 16. Lines 12<SP>1</SP>, 14<SP>1</SP> are connected to earthed inductances 22, 26 which convert a negative pulse I, Fig. 3 (representing " 1 ") at the anode of 4 or 19, into signal II. The positive portion of II applied to the control grid of the tube 24 or 25 causes the application of an effective negative output pulse to one side or the other of a bistable trigger stage 17 only if the tube does not receive simultaneously a negative signal II on its suppressor grid. Thus, at the end of a minor cycle, trigger 17 has its upper or lower tube (Fig. 2) conducting, corresponding to the operative and rest condition respectively, according to whether the comparison value is greater than, or less than or equal to, the input number. The trigger output lines 29, 30 are connected to discriminating gates 31<SP>9</SP>-31<SP>0</SP>, Fig. 1, one of which is opened corresponding to two consecutive triggers 17 in opposite condition, and at the end of a minor cycle, before the triggers are reset by pulses applied to terminals 18, a pulse is sent from terminal 36 through the open gate to operate the associated trigger stage 37 to indicate by a negative potential on a line 42 the first (highest) decimal digit. The operated trigger 37 opens the associated gate 39 so as to feed back a pulse train representing the complement to 2<SP>16</SP> of the comparison value corresponding to the decimal digit obtained, so that this value is subtracted from the input number by means of the adding circuit comprising two half-adders 70<SP>1</SP>, 70<SP>2</SP>. The input number is fed to the adder through an inverting tube 50, gate 51 and delay network 53 which divides by 8, the complementary values being similarly divided by 8 since no pulses occur in the first three digit positions. Each half-adder includes gating pentodes (Fig. 7, not shown) and delay networks which introduce a delay #, so that the adder effects multiplication by 4. The adder output is passed through a carry-suppressing gate 75 to two channels, one of which includes a delay 78 of 26, and the two trains thus produced are combined in a further adder 81, thus multiplying by 5 Î 4. Thus ten times the input number minus the comparison value is fed back to point 11 for obtaining the next decimal digit, this process being repeated each minor cycle and the triggers 37 being reset at the end of the cycle by pulses applied to terminals 40 (before those applied to 36). The output lines 42 (9-0) and 9 (-) are connected, through polarity inverters, to the suppressor grids of pentodes 839, 83<SP>8</SP>  ... , Fig. 8, to gate signals applied to the control grids from tapped delay lines 84<SP>9</SP>, 84<SP>8</SP>.... Each such delay line generates a signal such that when it is applied via the pentode to the control grid 87 of a C.R.T. 88 it will produce on the screen a dotted visual representation or outline of the corresponding digit or sign. The decimal number thus appearing on the screen may be photographed. The scanning of the screen is controlled by stepped waveforms applied to the top vertical deflection plate 90 and the two horizontal deflection plates 93, 94. These waveforms cause the seven lines of one decimal-digit area 89 to be scanned during one period T, the areas being scanned sequentially. Only the waveform generator for plate 94, which causes the stepping from one area to the next, is shown in detail; positive pulses of periodicity T applied from control terminal 104 to the grid of tube 103 cause progressive discharge of a condenser 98 in the grid circuit of output tube 97, the condenser being re-charged to cause a return to the first digit area by positive pulses of periodicity 6T applied from terminal 102 to tube 101. The other waveform generators 91, 95 are similar except for the times at which pulses are applied to their control terminals.