Patent GB-1410363-A (GB)
Title: Broadcast receivers
IPC: H03J7/18
Filed: 1972-11-27
Abstract: 1410363 Automatic control SONY CORP 27 Nov 1972 [29 Nov 1971] 54796/72 Heading G3N [Also in Divisions H1 and H3] In a broadcast receiver comprising an input circuit 1-3 Fig. 1 for receiving radio signals, a local oscillator 1, a divider 9 and a counter 14, the preselected contents of the counter 14 is varied in accordance with the number of pulses received from a pulse generator 92a, Fig. 16 for varying the dividing ratio of the divider 9 in dependence on the contents of 14, a frequency and phase comparator 10 compares the output from the divider 9 with a reference signal 11 and a control circuit varies the local oscillator frequency in dependence on the output signal from the comparator 10. A circuit CTL connected between the input circuit and a memory 59 provides a pulse in response to the output signal from the input circuit and applies the pulse to the memory whereby the existence of received radio signals is memorized by the memory 59. The radio or TV receiver has RF amplifier, mixer and a local oscillator 1 having a variable capacity diode; an IF amplifier 2, an FM discriminator 3 a muting circuit 4 and a stereo multiplexer 5. The output frequency of the local oscillator 1 is fed via a mixer having a crystal oscillator 7, a  divider 8 and a <SP>1</SP>/ N  divider 9 to a frequency and phase comparator 10 which is also fed by a reference signal generator 11 via a  divider 12. From the comparator 10 is obtained a direct voltage which is supplied as an oscillating frequency control voltage to the local oscillator 1. By changing the divide ratio N of the divider 9 FM waves with a frequency band are selectable. The divider 9 includes binary counters (11a, 11b, 11c,) Fig. 2, (not shown), a discriminator (15) and a gate (13) and the division ratio N is selected by a station select counter 14 including counters (14a, 14b, 14c). The contents of the station select counter 14 at (19a, 19b, 19c) are fed to a binary decimal decoder 20 the output of which feeds an RF indicator device 23 including indication tubes and feeds a matrix decoder 24. The binarydecimal decoder 20 and the matrix decoder 24 are described in detail Figs. 4A and 4B, (not shown). The matrix decoder 24 includes OR gate transistors (25) further described in Fig. 5 (not shown) and AND gate transistors (38) further described in Fig. 6 (not shown). The outputs from the matrix decoder 14 feed a lamp panel display 47 and a memory 59N. The lamp panel display 47 includes channel indicating elements such as neon lamps (L1-L70), Figs. 7 and 8 (not shown) and associated lamp push switches SW1...SW70. The neon lamps L1...L70 become ignited when the case made of glass and concerning each lamp is pushed. The state at which the switches SW1...SW70 are in the on condition is detected by a station select circuit (48) Fig. 9 (not shown). The memory 59N includes a 70 bit memory matrix having variable threshold MAOS FET (Q1...Q70) Fig. 12 (not shown) and is controlled by a memory control circuit (63) Fig. 13 (not shown) which has write, read and memory select switches (67a, 67b, and 67m). A control circuit CTL has self-light emitting buttons (87a-87e) Figs. 14 and 15 (not shown) for controlling the tuning and (88a-88e) for controlling the memory 59N. A control circuit for station search mode Fig. 16 includes a control button 88e, a monostable delay circuit 90, a flipflop 91, a station pulse generator 92a, a station search circuit 93 and a monostable write signal generator 101. The station search circuit 93 includes a D.C. level detector (95) Fig. 18 (not shown) fed from the output of the FM discriminator 3 and AND gate 96 fed from a muting control signal obtained by rectified output of the IF amplifier 2. The output from the level detector (95) feeds the AND gate (96) the output from which feeds an integration circuit (98). Operation of station search button 88e causes pulses to be generated by station pulse generator 92a which operates the station select counter 14 to scan through the RF range whereon the circuit is reset. If the receiver is in the tuned condition the pulse generator 92a is momentarily stopped so that the neon lamp in the panel display 47 corresponding to the tuned frequency is ignited for a longer period. When a station is present the memory 59N is written in succession. A scan mode circuit indicating all of the stations received in the FM band with the aid of the panel display 47 which only ignites the lamps corresponding to these stations is disclosed Fig. 21 (not shown). This scan mode circuit includes a station pulse generator (92b) a memory output discriminator (103) and a memory output delay circuit (104). A station may be selected by pushing the neon lamp corresponding to that station so that the scanning is stopped when this neon lamp is ignited. A control circuit relating to shift and step modes is disclosed Fig. 23 (not shown) which includes station pulse generators (92c, 92d, 92e) and a repeat monostable signal generator (92f). When a button (87b) is pushed the frequency changes to the next station. When a button (87c) is pushed the next tuning scan is affected at a given time without pushing the other buttons. When a button (87d) is pushed the frequency is shifted at a constant speed. When a button (87e) is pushed the frequency changes in a step manner. Another memory 59P similar to the memory 59N may be used for storing the desired stations beforehand.