Patent GB-989643-A (GB)
Title: Pulse forming network for a magnetic recording system
IPC: H03K3/26
Filed: 1962-04-04
Abstract: 989, 643. Recording digital data; magnetic recording head, local circuits for. MONROE CALCULATING MACHINE CO. April 4, 1962 [May 1, 1961], No. 12928/62. Headings G4C and G4R. [Also in Division H3] Maximum switching speed of a transistor driven inductive head of a magnetic drum recorder is achieved by shunting the head winding by a variator and by charging a capacitor from the head during switching off to provide a source of current for the transistor during the next switching on period. Fig. 3 shows a circuit for supplying writing pulses of one polarity to the winding 13 of a magnetic drum recording head, the pulses of the opposite polarity being supplied from a similar circuit connected to the lower half of the head winding and not shown. The pulses are fed to the coil from a negative 24 volt supply terminal and through two transistors 42, 44 connected in parallel. When input pulses render these transistors conducting current builds up in the coil until the core is saturated whereupon the maximum current is determined by the values of resistors 99 and the resistors 96, and 98, the latter also serving to equalise the currents in the two parallel transistors. A capacitor 100 connected in parallel with resistor 99 charges during the pulse and also prevents the resistor from limiting the initial rate of rise of current in the coil. When the transistors are rendered non-conductive a back emf is generated in the winding and this is prevented from damaging the transistors in three ways. Firstly the capacitor 100 provides a positive voltage in the collector circuit which offsets part of the back emf. Secondly the magnitude of the back emf is limited by a shunt circuit comprising a diode 102 and a variator. Thirdly, the inductor current is diverted from the transistor to a capacitor 121 through rectifier 125. When the transistors are rendered conducting again by the next input pulse capacitor 121 discharges through resistor 123 and the transistor so as to provide sufficient current to saturate the transistor in the initial period before current has built up in the head winding. The control circuit for the output transistors 42, 44 comprises an AND circuit 10 an amplifier 70, 76 a further AND circuit 46, 48 and a monostable circuit 4. When a 1 signal is present at a rectifier 38 and an ENABLE signal is applied to 40, a clock pulse applied to the "trigger" input to operate the monostable circuit 4 will apply a signal to diode 36 from transistor 28 to cause transistor 70 to conduct and thus 76 to conduct. The input signal applied from the monostable circuit 4 to rectifiers 46 and 48 is such that the output from 76 will cause the output transistors 42 and 44 to conduct. When the monostable circuit returns to its initial condition the AND gates 10 and 46, 48 close so that the output transistors are cut off. The monostable circuit 4 comprises two transistors cross coupled through capacitors 62 and 64 the timing being controlled by the circuit 64, 66, 68 of which 68 is variable to adjust the output pulse width. Resistor 66 is chosen so as to prevent the saturation of the input triggering diode 56 and a Zener diode 92 prevents transistor 28 saturating. In an alternative circuit (Fig. 4, not shown) a monostable circuit similar to 4 in Fig. 3 is used in place of transistors 70 and 76, the input signal the ENABLE signal and the clock pulse being applied to the input of the monostable circuit. The output pulse from the monostable circuit is applied to the output transistors 42 and 44 via a complementary pair type amplifier.