Patent GB-1523151-A (GB)
Title: Circuit arrangement
IPC: H04Q1/457
Filed: 1976-03-24
Abstract: 1523151 V.F. signalling POST OFFICE 24 March 1976 [24 Jan 1975] 3305/75 Heading H4R In a circuit arrangement for validating logical signals, particularly those derived from one out of four plus one out of four multifrequency signalling systems in which the signals have a pre-determined minimum duration and a pre-determined minimum inter signal pause, a first logic system detects the presence of a signal on only one line of a first set of input lines, and a second logic system detects the presence of a signal on only one of a second set of input lines and a coincidence verifying circuit provides an output only when the detected signals occur simultaneously. The verifying circuit output controls the initiating and terminating of the running of a timing clock counter and a timing verifying means produces a gating pulse when the period between initiation and termination exceeds a pre-determined minimum, the gating pulse being applied to a transmitting system which forwards the signals on the two sets of input lines to corresponding sets of output lines. An input signal change after the verifying pulse has been produced but before the output gates, which are clocked, have been enabled results in a further logic circuit disabling the gated output of the transmitting system. As described the arrangement includes logic circuitry and timing circuits to check that inter signal pauses exceed 39 mS and to enable the transmitter for a period of 32 mS for onward transmission of a valid signal. As shown in Fig. 2A presence of a correct frequency from a first group of four frequencies provides a "0" on a respective one of the four lines 100 to 103 and "1"s on the other lines. The inverters 1 to 4 and the NAND gates 9 to 12 and 20 ensure that NAND gate 20 only produces a "1" when one of the four input lines carries a "0" and the rest a "1". A similar arrangement responsive to a second group of four frequencies in a different band provides a similar output in respect of four further input lines and the outputs from the two arrangements provide inputs to a coincidence verifier 23 which provides a "0" to indicate coincidence of outputs. The output of the coincidence verifier is applied via a bi-stable, which changes the continuous output to pulse form, to logic circuitry Fig. 2C (not shown) which starts a clock counter Fig. 2E (not shown) which runs for 23 mS before providing an enabling signal to the logic circuit to enable a number of output gates Fig. 2F (not shown) which connect the signals on the input lines (100 to 107) to respective output lines (125 to 132). A further clock counter (156, Fig. 2F, not shown) maintains the gates enabled for 32 mS unless during this period the input signal changes, in which case the gates are disabled and the counters (156 and 158) are reset. When the coincidence verifying circuit indicates termination of signal coincidence counter 158 is reset and restarted and counts for 39 mS. If at the end of that period coincidence circuit indicates presence of valid input signals the counters are held set, but if the coincidence circuit indicates that there is no valid signal at that time then the counters are reset to their initial condition ready for a subsequent signal. Monitor points (202 and 203) are provided to indicate reception of a correct format signal and the onward transmission of a signal while control inputs (200 and 201) enable suppression of onward transmission, as may be required for scanning of a number of circuits, or disabling the operation of the entire circuit.