Patent GB-1161562-A (GB)
Title: Improvements in or relating to Apparatus Arrangements for Subtracting or Comparing Digital Numbers Represented by Electric Signals
Inventor: RUSSELL ALEXANDER
IPC: G06F7/494
Filed: 1966-04-05
Abstract: 1,161,562. Binary coded decimal subtractor. NATIONAL RESEARCH DEVELOPMENT CORP. 5 July, 1967 [5 April, 1966], No. 15124/66. Heading G4A. Apparatus for subtracting two binary coded decimal numbers each digit of which comprises four bits plus a sign bit in the parallel mode comprises means for adding the ones complement of each subtrahend digit group (row b) to the corresponding digit group, means for adding 0001 (row d) to the least significant sum digit (row c, D1) to produce an amended sum digit (row e), means for sensing the value of the sign digit of the amended sum digit and in accordance with a sensed positive or negative value adding 0001 or 0000 (row d) to the digit group of next higher significance (D2) and also adding the first or second compensatory digit group (row f) to the amended least significant digit sum (row c) to produce an answer digit group (row g) and, of each digit of greater significance, further means for sensing the value of the sign digit of the related digit group and in accordance with the positive or negative value adding the group 0001 or 0000 to the decimal digit of next greater significance (D3) and also adding a third or fourth compensatory digit group to the resultant sum digit of the related digit group to produce the answer digit group for such decimal digit. In one embodiment (Fig. 2) the first and second compensatory digit groups are 0000 and 1010 and the third and fourth digit groups are 0000 and 1010 respectively so that for the least significant digit 0001 (row d) is added to the sum (row c) of the minuend (row a) and the complemented subtrahend (row b). The result is positive in sign so 0001 is added (row d) to the sum of the next significant digits (D2) and 0000 (f ) is added to the amended sum (e) of the least significant digit. The amended sum (c) of the next significant digit D2 is negative so 0000 (d) is added to D3 and 1010 to D2. The sum (e) of D3 is negative so 1010 (f) is added to D3 and the negative sign (c) indicates that the result is negative. If this sign had been positive (Fig. 1, not shown), the resultant sum (g) would have been correct (e.g. +675). To correct the result as shown in Fig. 2, 1000 is subtracted from the result for a three-digit number or 10<SP>n</SP> is subtracted for an n digit number. This correction may be required for servo system requirements in order to drive a controlled device to any chosen position but may require inordinate accuracy, e.g. if there is a 1 difference between five digit minuend and subtrahend so that a control signal is formed from currents or voltages whose amplitudes are + 99999 and- 100000 units then the supply voltage must be held constant with an accuracy better than 1 part in 100,000. A second embodiment (Fig. 5) is used to avoid this. The procedure is as before with the first and second compensatory digit groups being 0101, 1111 and the third and fourth 0110, 0000. The final result in these cases is correct. An arithmetic unit comprising half adders formed of NOR gates (Fig. 4, not shown) is described.