Patent GB-1117099-A (GB)
Title: Combinational computer system
Inventor: HUNTER DAVID RHODES
IPC: G06F7/64
Filed: 1965-07-06
Abstract: 1,117,099. Digital computer. LITTON INDUSTRIES Inc. 6 July, 1965 [7 Oct., 1964], No. 28685/65. Heading G4A. A combinational computer includes a general purpose (GP) computer and a digital differential analyser (DDA), the GP computer performing most arithmetic operations and the DDA performing its more restricted operations. GP10 shown basically in Fig. 6 includes 32 memory tracks, 4 recirculating registers, A, M, B, U, the A register is the accumulator, M register holds multiplier or quotient, B holds multiplicand or divisor, U holds and recirculates any instructive read from memory. A register is connected to 3 flip-flops which may be included or by-passed to provide left and right shifts. The Y track functions as timing and sequencing control. Four phases are (1) search for next instruction, (2) read next instruction, (3) search for operand specified, (4) read operand and perform operation. Instruction register is capable of storing 32 individual instructions. Words comprise 25 bits, the first of which is a spacer to allow a period for dissipation of fring- ing flux generated when the write amplifiers are switched off. A 5 flip-flop D register is used to store the track address of the last instruction because in searching for a normal instruction the search is accomplished on the same track as the previous instruction. Sequence control register U controls 4 phases of operation. The sector address of the next instruction is in bit position t 13 -t 19  of the word in the U register, for unconditional transfer and idle in t 1 -t 7 . The sector search is made by sequentially matching bits in the U register against bits of the sector address track. Successful search causes the U register to advance. The words are then read into the U register and also into the appropriate flip-flop register, e.g. operation bits are fed into Instruction register. During phase 2 the sector search for the operand proceeds. A new operand address is shifted into the D register and the old track address shifted to the U register except when an unconditional transfer or idle instruction is read. These specify new track address so the old one is not saved. In phase 3 the instruction is executed. For ADD, SUBT. the operation is performed as the word is read from memory, MULT, DIV take 25 word times determined by counting down the contents of interval 2 of the U register instruction word. All negative numbers are held in 2's complement form. Logical equations defining the operations are given and described. Descriptions of arithmetical operations with reference to the logical equations are given. DDA section.-A single track is used for all Y numbers and a single track for all R numbers. Initial values of various Y numbers are filled into appropriate places on the Y register memory track. A programme placed on the programme memory track of the DDA provides integrator interconnections and all necessary commands. The DDA has an initial conditions track, a Y register track, R register track, a pair of magnitude and sign Z-line tracks and 5 programme tracks. Initial conditions are read in from external circuitry under the control of GP10. Initial Y numbers are then read from initial conditions track to the Y register track. A start command is produced by GP10. Each register utilizes a single pair of read and write heads spaced by 1600 bits. This allows numbers of variable lengths separated only by a single spacing bit to be stored on the register tracks and so save space generally lost on fixed-wordlength integrators. Y and R registers are recirculating registers. A full adder circuit is included in the DDA logic circuitry. A list of operations performed is given. The GP10 controls the operation of DDA in initializing the DDA clearing and initializing DDA, clearing R and Z registers, recirculating DDA, starting DDA, and transferring contents of the initial conditions track to the Y register. Words may be written from GP10 directly into the Y register of the DDA. The two Z lines represent the ternary values of the delta Z overflow. GP10 may call numbers from either the initial conditions track or the Y register track of the DDA.