Patent GB-1158010-A (GB)
Title: Data Storage Apparatus
Inventor: GILLET JOHN BRIAN
IPC: G11C29/00
Filed: 1966-12-21
Abstract: 1,158,010. Faulty storage locations. INTERNATIONAL BUSINESS MACHINES CORP. 21 Dec., 1966, No. 57200/66. Heading G4C. In data storage apparatus, when a main memory word location containing one or more faulty bit positions is addressed, one or more word locations in a supplementary store are addressed, only bit positions therein corresponding to the faulty bit positions being accessed. In Fig. 1, if one quarter 1a, 1b, 1c or 1d of a word location in a main memory 1 has faulty bit positions, the faulty bit positions are replaced for read-in and read-out purposes by correspondingly-positioned bit positions in a quarterlength word in one of four segments 5a, 5b, 5c, 5d of a supplementary store 5, the segment being that corresponding in position to the faulty quarter of the main memory word, viz. 5a for 1a, 5b for 1b &c. This replacement is achieved by storing, for each faulty main memory word, a word in an associative store 8. This latter word has a tag portion equal to the main memory word address, a flag portion specifying the bit positions in the word quarter (whichever this is) which are faulty, and an address portion which identifies the relevant segment 5a, 5b, 5c or 5d of the supplementary store 5 and the relevant quarter-length word therein. During main memory read-in and read-out, the main memory address at 2, besides addressing the main memory 1, is matched associatively on the tag portions in the associative memory 8, the address portion of the matching word accessing the appropriate quarter-length word from the appropriate segment of supplementary store 5 and the flag portion placing (by means of gates 6) the appropriate bit positions of this quarterlength word in communication with a register 4 which also communicates with main memory 1. Register 4 supplies or receives the data word to be read-in or read-out respectively. On read-out, any bits from the supplementary store 5 override corresponding bits from the main memory 1, by differential timing (or extra gates 6 may be provided between memory 1 and register 4). A given quarter-length word in supplementary store 5 will in general cater for more than one main memory word. Other fractions than a quarter are mentioned as alternatives. Fig. 2 (not shown) differs from Fig. 1 in that the supplementary store (15) has eight segments corresponding to respective overlapping quarters of the main memory word. Fig. 3 (not shown) allows faulty bit positions in up to two quarters of a main memory word to be replaced, each quarter being associated with a respective segment in each of two supplementary stores (35, 36), each word in the associative store (41) having two address portions and two flag portions. More supplementary stores may be provided in a similar fashion. In Fig. 4 (not shown), no flag portions are used but on read-out of a given word from the associative store (56), one of a plurality of control lines (60) is selected to control a matrix of transistor gates to put the appropriate bit positions in the accessed supplementary store (55) word in communication with the appropriate bit positions in the register (54) corresponding to register 4 of Fig. 1. In Fig. 6 (not shown), the associative store is dispensed with and each word in main memory (81) has, besides data, a flag and an address portion. On accessing of the word, the address and flag portions are read-out and used for selecting a word in a supplementary store (85) and bit positions in it, respectively, to replace the faulty main memory bit positions. Second flag and address portions may be provided and used similarly. The flag portions could be dispensed with as in Fig. 4 (not shown)-see above.