Patent GB-1207615-A (GB)
Title: Improvements in or relating to data processing systems
IPC: G06F9/22
Filed: 1968-04-24
Abstract: 1,207,615. Data processors. NATIONAL CASH REGISTER CO. 24 April, 1968 [4 May, 1967], No. 19361/68. Heading G4A. In a data processing system operable in either a user state or a supervisor state, either of two address registers can be rendered effective for addressing a random-access memory, the first register being able to address operand and command storage sections of the memory and the second being able to address a section which includes registers continuously storing control information for the user and supervisor states. A character-addressable random-access thin film magnetic rod memory 12 can be addressed from either a 2-character address register LA-1, LA-2 used for addressing operand and command sections and index registers therein or from a 1-character address register LB used for addressing the following registers provided therein: (a) supervisor control registers for storing supervisor flags, the starting address of the next supervisor command, and the fields of the latest supervisor command including the operand address(es) both before and after any indexing, (b) user control registers for storing corresponding quantities in connection with user commands &c. each user register differing in address from the corresponding supervisor register by the same amount, so that, when in the supervisor state, control register addresses are incremented by this amount as they go to the address register LB to obtain the appropriate set of registers (or decrementing could be used), (c) input/output registers storing command and status information for each peripheral and the next and final memory addresses to deliver/receive characters to/from each peripheral, (d) a repeat count register to hold the number of times the command following a REPEAT command is to be repeated, the register contents being successively decremented. A two-address command has the format and a one-address command has the format where Q is the command code, A 2 A 1  is the address of a first operand, B 2 B 1  is the address of a second operand, R A  specifies whether the first operand address is to be indexed, and if so the address of the appropriate index register and whether the indexed address is to replace the previous contents of the index register, R B  performs the same function for the second operand, and T specifies the number of characters per operand. If a command does not include the field T, the last previous value is used, as saved in one of the control registers. Each command is executed by a series of microcommands, the number of miorocommands varying with the command. The microcommands are loaded in turn into a register NB from a register NA and decoded at 16, except that on interrupt due to a peripheral being ready for transfer of a character to/from the memory 12, a particular microcommand to deal with this is inserted direct into NB at the end of the current microcommand without disturbing NA so that the interrupted command can proceed after the transfer has taken place. Each microcommand is executed in a series of machine cycles counted by a counter P, the count being decoded at 18. The number of cycles varies with the microcommand, the counter P being reset to zero at the end of each microcommand. The outputs of decoders 16, 18 feed control logic K consisting of logic feeding latches, the logic and the latches feeding further logic which controls the machine. An oscillator-driven delay line produces, in each machine cycle, a series of pulses t m  to control the memory 12 in a read-restore or clear-write cycle, and pulses t 0 , t 1 , t 2  to control the rest of the machine. Fig. 4 also shows a register M, data registers MA, MB, an adder J, console 20 (middle right of Fig.), input/output logic 201 and peripherals X 1  . . . X n , Y 1  . . . Y n . The supervisor state is used on detection of error, or for the performance of error checking or testing (e.g. of a just completed input/output transfer) during or between user commands. NAND circuits are used throughout. Execution of WAIT, PACK, UNPACK, MOVE, COMPARE, ARITHMETIC, REPEAT and IN-OUT commands is described.