baber/WOPTO huggingface dataset:
Patent JP-S60241255-A (JP)
Title: Manufacture of semiconductor device
Inventor: OGISHIMA JIYUNJI
IPC: H01L29/78
Filed: 1984-05-16
Abstract: PURPOSE:To obtain further improvement in operating speed of the titled device by a method wherein miniaturization is enabled by reducing the resistance of a diffused layer by silicifying the diffused layers of source and drain regions. CONSTITUTION:A P-well 12 is formed on an N type Si substrate 11, and element isolating SiO2 films 13; thereafter, polycrystalline Si gate electrodes 15a and 15b are formed on gate oxide films 14 by patterning. Afterwards, side walls 16a and 16b of insulation film are formed on the side surfaces of respective gate electrodes. Next, an Mo film 17 is evaporated, and then silicified only on the substrate 11 and the gates 15a and 15b. Further, the region of forming N-MOS transistor is masked with a resist 19, and boron is ion-implanted to the region of forming a P-MOS transistor. The P-region is masked with a resist 20, and arsenic is ion-implanted to the N-region. Thereafter, P<+> and N<+> diffused layers 21 and 22 constituting the source and drain regions are formed in the forming regions, respectively.
Patent JP-S61255118-A (JP)
Title: Semiconductor integrated circuit
Inventor: MARUO YUTAKA
IPC: H03F3/34
Filed: 1985-05-07
Abstract: PURPOSE:To obtain a stable circuit with small circuit scale without effect by a parasitic capacitance by applying an input signal of an analog arithmetic circuit and an output signal of an output signal of an integration circuit being an estimated value of an offset signal to an independent input circuit of the analog arithmetic circuit while eliminating the offset signal superimposed on the output of the analog arithmetic circuit. CONSTITUTION:The titled circuit consists of, e.g., the 1st input circuit consisting of a capacitor B1 and switches S1-S4 and connected to n input terminal IN, the 2nd input circuit consisting of a capacitor B2 and switches S5-S8 and connected to an output terminal of an operational amplifier A2 at the output of a switched capacitor integration circuit consisting of the operational amplifier A2, capacitors B4,B5 and switches S9-S12 and an analog arithmetic circuit consisting of an operational amplifier A1, capacitor B3 and a switch S13, and its output terminal OUT is connected to the input switch S11 of the said integration circuit. The time constant of an offset eliminating circuit by the said integrated circuit depends only on the product between the capacitance ratio of the input sampling capacitors B1,B2 of the analog operation circuit and the capacitance ratio of capacitors B4,B5 of the integration circuit and is independent of the parasitic capacitor.
Patent JP-S58214269-A (JP)
Inventor: KAMIYA SHIGERU
IPC: H01K1/40
Filed: 1982-06-04
Abstract: (57)【要約】本公報は電子出願前の出願データであるた め要約のデータは記録されません。
Patent JP-H11322893-A (JP)
Title: Polyurethane prepolymer having latent amino group and isocyanate group, its production and its use
Inventor: PFENNINGER UELI
IPC: C08G18/80
Filed: 1999-04-02
Abstract: PROBLEM TO BE SOLVED: To obtain a polyurethane material capable of being rapidly cured even when used in a thick layer, scarcely generating bubbles, having good storage stability and capable of providing cured products having excellent aging resistance, etc., by compounding a prepolymer having latent amino groups. SOLUTION: This moisture-curable one pack type polyurethane material contains a prepolymer of the formula: (NCO)m A(B)n  A is a [(m)+(n)]-valent group produced by removing [(m)+(n)] isocyanate groups from a [(m)+(n)]- valent polyurethane prepolymer; (m) is 1 or 2; (n) is 1 or 2; B is a latent amino group of formula I or II (R is a 1-8C aliphatic hydrocarbon group or the like; D is a 1-8C divalent aliphatic hydrocarbon group or the like; E is phenyl, an alkylphenyl or the like) capable of being bound to A through a urethane bond}. The prepolymer preferably has an average mol.wt. of 500-20,000 g/mol, and can be used for materials such as elastic sealing materials.
Patent JP-S62256202-A (JP)
Title: Readout circuit for magnetic disk device
Inventor: KUNO SHINICHIRO
IPC: G11B5/09
Filed: 1986-04-28
Abstract: PURPOSE:To secure the right-left symmetry of waveforms so as to reduce occurrence of peak shifts and the error rate of data, by changing readout signals passed through an LPF to pulses after passing through an all-band-pass filter. CONSTITUTION:Waveforms of signals read out from a medium by means of a magnetic head 1 are made narrow and sharp with a cosine equalizer 3 after amplification 2 and noises of the signals are reduced by controlling the band of the signals with an LPF 4. The readout signals are sent to a discrimination circuit after their group delay frequency characteristics are flattened by means of an all-band-pass filter 5 and they are changed to pulses by a pulse circuit 6. When the group delay frequency characteristics are flattened in such a way, the right-left symmetry of waveforms can be secured and, as a result, occurrence of peak shifts and error rates of data can be reduced.
Patent JP-S58213369-A (JP)
Title: Small sized electronic calculator having check function
Inventor: YANAGAWA MIKIO
IPC: G06F3/147
Filed: 1982-06-05
Abstract: PURPOSE:To attain to recognize how the final resulting data changes depending on correction, by displaying the final resulting data changed on a display section, in correcting a part of data of a formula during the display reproduction of the formula. CONSTITUTION:A control section 11 discriminates a key data outputted from a key input section 2 whether it is a reproducing key, an entry key, a function key or a clear key. Further, the resulting data on the way of each operation is inputted to an X register and displayed on a display section 3. In inputting the final data ''='', the formula is stored in a key memory 14, the final resulting data is inputted to the X register, the final result is displayed on a display section 3A and the formula is displayed on a display section 3B. For the purpose of check, the reproducing key 4A is operated to reproduce the formula on the display section 3B for the insertion of a desired equation or the correction of the data. In the display section 3, the formula changed by correction is displayed on the display 3B and the result of on the way or the final result is displayed on the display 3A.
Patent JP-H02274118-A (JP)
Title: Resistance capacitance type oscillating circuit
Inventor: OSAWA MASANORI
IPC: H03K3/354
Filed: 1989-04-17
Abstract: PURPOSE:To reduce the power consumption by making the size of a field effect transistor(TR) being a component of an initial inverter smaller than the size of a field effect TR being a component of other inverter. CONSTITUTION:A size W/L of a TR of an inverter IV 1 is selected to be 1/5 of the size W/L of inverters IV2, IV3. Since a P-channel FETP 1 and an N- channel FETN 1 have only to have a capability to charge/discharge the parasitic capacitance caused in the gate of the inverter IV 2, the size W/L of the TR is decreased. Thus, a through current of a current I1 flowing to the inverter IV 1 is reduced considerably and the resistance capacitance oscillation circuit whose power consumption is reduced is obtained.
Patent JP-S62254301-A (JP)
Inventor: NAITO KAZUMI
IPC: C01B15/08
Filed: 1986-04-28
Abstract: (57)【要約】本公報は電子出願前の出願データであるた め要約のデータは記録されません。
Patent JP-H05299203-A (JP)
Title: Manufacture of ptc resistor
Inventor: OGITA KIYOBUMI
IPC: H01C7/02
Filed: 1992-04-17
Abstract: PURPOSE:To provide a PTC resistor manufacturing method with which a PTC resistor, having excellent PTC characteristics, can be safely and stably obtained at low cost. CONSTITUTION:A subsidiary ingredient, which induces PTC characteristics is mixed with the VO2 of the main material then the mixture is granulated, and after the granulated powder has been molded, it is calcined in a reducing atmosphere, and a PTC resistor is manufactured. In the manufacture of the PTC resistor, it is desirable that one or two or more metal oxides, selected as a subsidiary ingredient from the group consisting of Cr2O2, Al2O3, and Sc2O3, are used and after the mixture has been precalcined in a reducing atmosphere, a PTC resistor is manufactured by adding one or two or more metals selected from the group of Fe, Co, Ni and Cu as a calcination assistant or the compound of these metals.
Patent JP-H03294021-A (JP)
Title: Method for bending metallic tube
Inventor: NISHIKAWA MASAYUKI
IPC: B21D7/024
Filed: 1990-04-12
Abstract: PURPOSE:To bend a tube at a stable bent angle by holding a bent part between 1st and 2nd groove parts through the use of bending rolls and a clamp, pressing a part adjacent the bent part to the bending roll and bending it. CONSTITUTION:The groove parts 25, 26 of the bending roll 22 and the clamp 23 show curved surfaces having an elliptical cross section each corresponding to the surface shape of the bent part 10. Therefore, when the bent part 10 is held by the bending roll 22 and the clamp 23, the surface of the bent part 10 contact tightly on the surfaces of the 1st groove part 25 and the 2nd groove part 26 and a high clamping force can be obtained. As a result, at the 2nd bending stage, a primary bent tube 1 is prevented from relative movement to the bending roll 22 and the clamp 23. When the bending roll 22 and the clamp 23 are turned to one direction as the bent part 10 is clamped, a part adjacent to the bent part 10 of the primary bent tube 1 is pressed by the bending roll 22 to obtain a secondary bent tube.
Patent JP-2000294649-A (JP)
Title: Automatic wiring method, automatic wiring device, and storage medium having stored automatic wiring program
Inventor: MURATA HISASHI
IPC: H01L21/82
Filed: 1999-04-02
Abstract: PROBLEM TO BE SOLVED: To prevent the occurrence of contravention of the design rules such as a short clearance between fellow wirings, the crossing, the contact, the overlapping, etc., by wiring a shield net, removing the attribute of inhibition of adjacent wiring and securing the specified clearance on both sides of the wiring course of a signal net. SOLUTION: The through wiring via 1E between the first layer and the second layer of a net and the first layer wiring segment 1B of the net are torn off, and a vial 1F is provided anew right above from a terminal 1T, and the second layer wiring segment 1A of the net is connected, without causing an error in crossing, to the terminal IT through the via 1F. This way, the attribute of the inhibition of the adjacent wiring of a clock net 3A is removed after rewiring, and then, the wiring of a shield net 4A is performed adjacently to the clock net 3A. Hereby, this method ceases to cause contravention of the design rule such as the short clearance between the fellow wirings, the crossing, the contact, the overlapping, etc.
Patent JP-S61255184-A (JP)
Title: Magnetic recording and reproducing device
Inventor: SHIOIRI TAKESHI
IPC: H04N5/783
Filed: 1985-05-08
Abstract: PURPOSE:To prevent the generation of noise bar and to improve S/N by selecting a lead angle, a diameter and the number of rotation of a rotating body, the number of rotating heads and a winding angle of a magnetic tape to the rotating body, respectively in such a manner that a scanning trace of the rotating head when the magnetic tape runs at high speed draws the same scanning trace during a normal recording reproduction. CONSTITUTION:Scanning traces of rotating heads 3-6 are drawn on a magnetic tape 7 running at a speed three time the speed during a normal reproduction as shown by center lines of tracks on A1, B1, A2, B2 ... of the figure and an information signal of a 1 field id recorded and reproduced in 1/3 field time. Accordingly, when the normally recorded magnetic tape is reproduced at a triple speed, a drum pulse has a polarity reversed every 1 field as shown by A of the figure and wave forms of respective reproduced frequency modulating information signals of the rotating heads 3, 4, 5 and 6 are successively obtained with a time difference of 1/3 field as shown in the figures B-E and from the respective rotating heads, the reproduced frequency modulating signal information signals of the 1 field are obtained.
Patent JP-H04326709-A (JP)
Title: Rotary transformer
Inventor: JINNO MEIJI
IPC: G11B5/53
Filed: 1991-04-26
Abstract: PURPOSE:To provide a rotary transformer which has cross talk reduction and many accompanying effects. CONSTITUTION:Cores 1, 2 which form a magnetic circuit are divided in a plane perpendicular to the axis of rotation together with a pair of coils 3, 4 arranged at faced parts. The divided cores are arranged so as to form gap parts; cylinders 5, 6 are bonded to sides which are not faced at the cores 1, 2. Through holes 7 which extract coil wires are made in the gap parts of the cylinders 5, 6. Since the cores 1, 2 are divided in the plane perpendicular to the axis of rotation, the magnetic circuit is closed at each core, and a cross talk can be reduced. Since the coil wires are extracted independently through the respective through holes, the cross talk can be reduced further.
Patent JP-H05265311-A (JP)
Title: Conductive roll
IPC: G03G15/08
Filed: 1992-03-23
Abstract: PURPOSE:To obtain an image density which is uniform and sufficient and has excellent fogging resistance by setting the volumetric resistance and surface resistance of the conductive roll itself so as to satisfy a specific relation, thereby facilitating the escape of the residual charges of a toner from the roll surface into the air. CONSTITUTION:This conductive roll is produced by using a conductive coating material compsn. Namely, the conductive coating material compsn. is applied by dipping, etc., on the outer peripheral surface of a metallic sleeve 12 and is dried, by which conductive layers 13a, 13b, 13c are formed. The conductive layers 13a, 13b, 13c formed on the outer periphery of this shaft body are formed by using a binder resin and the conductive coating material compsn. formed by dispersing the conductive powder in this resin. The conductive layers 13a, 13b, 13c are formed into multilayered structures of at least two layers rather than a single layer system. The volumetric resistance(Rv) and surface resistance(Rs) of the roll itself are so set as to satisfy the relation (Rv/5)>Rs.
Patent JP-H1058710-A (JP)
Title: Ink barrier for vacuum line or pressure line of fluid reservoir
Inventor: BROOKS JEFFREY B
IPC: B41J2/19
Filed: 1997-04-15
Abstract: PROBLEM TO BE SOLVED: To position a print head in any direction in three directions perpendicular to each other without escaping of ink through a line in an ink barrier for a vacuum line or pressure line of a reservoir. SOLUTION: A vent 82 of a reservoir 60 is positioned at a portion higher than a level of ink in each direction of the reservoir 60. A U-shaped tube 86 in the reservoir 60 has one end coupled to the bent 82 and the other end which is opened to the inner section of the reservoir 60 at a portion higher than the level of the ink in each direction of the reservoir 60. The U-shaped tube 86 is extended downward along one wall of the reservoir 60 and extended along the bottom of the reservoir 60 such that at least one part of the U-shaped tube 86 is positioned at a portion lower than a lowest level of the ink in the reservoir 60 in each direction thereof.
Patent JP-S61258047-A (JP)
Inventor: SHICHI TOSHIHARU
IPC: D03D23/00
Filed: 1985-05-08
Abstract: (57)【要約】本公報は電子出願前の出願データであるた め要約のデータは記録されません。
Patent JP-2000291463-A (JP)
Title: Engine controller
Inventor: FUSE TORU
IPC: F02D45/00
Filed: 1999-04-05
Abstract: PROBLEM TO BE SOLVED: To prevent the actual EGR ratio from temporarily increasing in a case where a throttle valve fixed in the full opened state. SOLUTION: In accelerating in the drive range of the lean air-fuel ratio, a calculating means 47 calculates a value obtained by increasing and correcting the target intake air amount by a correction value corresponding the deviation between target supercharged pressure and actual supercharged pressure as the second target intake air amount, and a drive means 48 drives a throttle valve controller 41 so that, the second target intake air amount may be introduced into an engine.  While, when the second target intake air amount exceeds the maximum intake air amount realizable in the drive range of the theoretical air-fuel ratio and in a natural aspiration state, a calculating means 53 calculates a value obtained by correcting the target EGR amount to the decreasing amount side as the second target EGR amount, and a driving means 54 drives an EGR valve controller 49 so that the second target EGR amount may be allowed to flow.
Patent JP-S5524257-A (JP)
Title: Valve
Inventor: OOBA KANJI
IPC: F16K1/34
Filed: 1978-08-09
Abstract: PURPOSE: To remove solidified film attached to the valve body by providing a smooth sealing end face to the valve body and a sharp-edged sealing end to the valve seat, and by pressing the turning sharp-edged end against the sealing end face in closing the valve.  
     CONSTITUTION: The valve seat 3 and valve body 9 are made of hard material, a smooth sealing end face 9a is provided to the valve body, and a sharp-edged sealing end which contacts with the sealing end face is formed on the valve seat. Even though a solidified film produced by the contracted vein of fluid in the passage 2 is attached to the sealing end face of the valve body, the film can be removed by pressing the turning sharp edge against the sealing end face with the handle 8. 
     COPYRIGHT: (C)1980,JPO&Japio
Patent JP-S59223080-A (JP)
Title: Control device of solid-state image pickup element
Inventor: HOSHINO KUNIHISA
IPC: H04N5/335
Filed: 1983-06-01
Abstract: PURPOSE:To obtain a fixed photoelectrically converted output irrespectively of the intensity of incident lights by obtaining a fixed photoelectrical transducing output by controlling the electric charge accumulating time when the intensity of incident light is within a prescribed range and by approaching the output to a fixed level by bringing up or bringing down the gain of the photoelectrical transducing output when the intensity of the incident light is out of the prescribed range. CONSTITUTION:In case the intensity of the incident light to a photoelectrical transducing surfaces 2-1-2-n is within a prescribed range and an electric charge accumulating time Ts is controlled so as to obtain a photoelectrical transducing output at a fixed level, an photoelectrical transducing output at a desired output level can be obtained by stopping the accumulation of an electric charge when it is detected that an output V13 reaches a prescribed value. When the intensity of incident light is too high, the output of an OR gate 21 remains at a low level, because the Q-output V18 of a D-FF 18 is low level as it is even when the output V14 of a comparator 14 becomes a high level before a lower limit time T1 passes. When the intensity is too low and the output V14 of the comparator 14 does not become a high level even when an upper limit time T2 passes and the output of an AND gate 20 is at a low level, the output of the OR gate 21 becomes a high level by the Q-output V19 at the high level generated by a D- FF19.
Patent JP-2000294929-A (JP)
Title: Manufacture of multilayer printed wiring board and the multilayer printed wiring board
Inventor: EN HONCHIN
IPC: H05K3/38
Filed: 1999-04-05
Abstract: PROBLEM TO BE SOLVED: To provide a manufacturing method for a multilayer printed wiring board, in which connection reliability of a conductor circuit to a via hole formed on a roughened face can be ensured sufficiently, even when the roughened face is formed on the conductor circuit through etching operation. SOLUTION: In this manufacturing method of a multilayer printed wiring board, conductor circuits 4 which are composed of a plurality of layers by sandwiching interlayer resin-insulating layers are formed on an insulating board by repeating a process, wherein the conductor circuits 4 are formed, a roughening treatment is executed, the conductor circuits 4 to which the roughening treatment is executed are covered with an interlayer resin-insulating layers 2 and opening for via holes are formed. Than the manufacturing method for the multilayer printed wiring board includes after the formation of the openings for the via holes, an etching treatment executed to the roughened faces 4a on the conductor circuits 4, which are exposed from the openings for the via holes.
Patent JP-H08268552-A (JP)
Title: Control method of each layer picking device
Inventor: YOSHINAGA YOICHI
IPC: B65G59/02
Filed: 1995-03-31
Abstract: PURPOSE: To prevent overturning and crushing of picking object goods by controlling advancing speed of a carriage by a picking condition of the picking object goods. CONSTITUTION: When the fact that a pickup roller 8 installed on the tip of a carriage 6 advances up to a specific distance position from picking object goods is detected, advancing speed of the pickup roller 8 is reduced, and the picking object goods can be prevented from being damaged by collision. When the fact that one end of the picking object goods is raised by the pickup roller 8 is detected, the advancing speed of the pickup roller 8 is increased up to predetermined speed according to rotating speed of the pickup roller, and a movement of the center of gravity of the picking object goods in the pickup roller 8 direction is facilitated, and overturning of the picking object goods is prevented.
Patent JP-H02275499-A (JP)
Title: Pronunciation evaluating method
Inventor: MIKI SATOSHI
IPC: G10L21/02
Filed: 1989-04-17
Abstract: PURPOSE:To improve the correspondence accuracy of phonemes by generating frame correspondence between the voice of a speaker to be evaluated after speaker adaption, i.e. after spectral individualities are absorbed and the voice of a standard speaker. CONSTITUTION:A voice analysis part 3 analyzes the voice 2 of the standard speaker, frame by frame, and a clustering arithmetic part 4 clusters the voice after the analysis to generate the code book 5 of the standard speaker. A voice analysis part 7 analyzes the voice 6 of the speaker to be evaluated and a clustering arithmetic part 8 clusters the voice to generate a code book 9. Then the frame correspondence between the voice of the speaker to be evaluated and the voice of the standard speaker is generated based upon spectrum similarity and then the phoneme features of the speaker to be evaluated and standard speaker which are normalized by the mean value and variance value of parameters are compared with each other in corresponding frame units. Consequently, the accuracy of the phoneme correspondence by the frame correspondence between the speaker to be evaluated and the standard speaker can be improved.
Patent JP-S5722219-A (JP)
Title: Stereoscopic viewing lens plate of plane image
Inventor: KIMURA SEIZABUROU
IPC: G02B30/27
Filed: 1980-07-16
Abstract: PURPOSE:To permit simple and marked stereoscopic visual observation of plane images on account of the effect of the parallax of both eyes by forming a lens plate by aligned disposition of concave lenses. CONSTITUTION:Two sheets of transparent plates of parallel planes which are arranged and formed uniformly with slender planoconcave lenses on their surfaces and are superposed in a biconcave lens form are used for a lens plate 2. Next, the lens part of the lens plate facing the plane image side is used as an objective lens part 3, and the lens part facing the eye A side as an eyepiece lens part 4. First, a plane image 1 is placed within the virtual focus F of the lens L1 of the part 3 forming the lens plate 2, and when the eye A views a picture element (p) at a line of vision a1 at an arbitrary angle through the lens plate 2, the converging ray a1p from the picture element p is is refracted by the lens L1 and is then diffused slightly and this results in that the virtual image point of this diffused ray a1p' formed at the point p1 on its extension line is viewed.