Patent GB-767709-A (GB)
Title: Improvements in electronic multiplying machines
IPC: G06F7/52
Filed: 1955-02-25
Abstract: 767,709. Digital electric calculating-apparatus. INTERNATIONAL BUSINESS MACHINES CORPORATION. Feb. 25, 1955 [March 1, 1954], No. 5705/55. Addition to 767,708. Class 106 (1). In the parent Specification a modification of an electronic digital multiplying machine is described in which a multiplier is registered in a register MP, each decimal denomination of which consists of ten hard-valve triggers, only one of which is on at any one time, and a multiplicand is registered in a register MC, each decimal denomination of which consists of only four hard-valve triggers S1, S2, S4, S8 which by particular arrangements of their " on " and "off" conditions together register decimal digits on the binary scale. In this modification multiplication is effected by successively using each digit of the multiplier to multiply in parallel first all the " 1 " bits or components of the multiplicand then all the " 2 " bits, then the " 4 " bits and finally the " 8 " bits. In the actual multiplication, as described in the parent Specification, a current multiplier digit selects a corresponding gating circuit, called an " X plate ", which issues pairs of groups of pulses representative of the product of the multiplier with each of the digits 1, 2, 4 and S respectively. The two groups of pulses associated with the digit r (r = 1, 2, 4 or 8), which represent respectively the left-hand and right-hand decimal digits of the product of the current multiplier with the digit r, are applied to a set of pairs of gates, each pair being associated with, and in part controlled by an " r " bit stage of the multiplicand register, the other control being by a secondary commutator which ensures that only the gates associated with the current " r " bit stage are operative, and depending upon the condition of the "r" bit stage these pulses either pass or do not pass to be routed to the appropriate denominations of the accumulator. When the secondary commutator has advanced through the four bits, the process is repeated using the next lower order multiplier digit. This process of using a secondary commutator to step through each of the four bits 1, 2, 4 and 8 is necessary to avoid the possibility (which does not exist in the main embodiment of the parent Specification since that embodiment uses ten triggers for each denomination of the multiplicand register) of two or more pulses, which should be counted separately, arriving at an accumulator simultaneously and being counted only once. The present Specification describes how, by the addition of only one extra accumulator, it is possible to multiply first all the " 1 ", " 4 " and " 8 " bits simultaneously and then all the " 2 " bits, thus reducing the secondary commutator cycle to only two points. That this is possible, without the risk of losing pulses, is due to the fact that each denomination has only to register from 0 to 9, and thus the " 8 " and " 2 " and " 8 " and " 4 " stages of any one denomination are never simultaneously " on ", and to the fact that all the left-hand digits for the " 1 " bits are zero. The operation of the present machine is as follows: (a) a record card 1, Fig. 1, is read and the digits of the multiplier and multiplicand registered in the MP and MC registers 2, 3 respectively. (b) A column shift commutator 7 causes the highest denominational digit of the multiplier to be used to select one X plate each of which is divided into a lefthand portion LH and a right-hand portion RH, 5, 6. Each X plate receives pulses from a compute commutator to produce the output pulses. (c) Under control of the secondary commutator the pulses supplied by the selected X plate are filtered through the output gates of the "1", "4" " and "8" bits of the MC register. (d) The pulses that pass the MC register are distributed by a column shift switch 8 and a distributer to the appropriate denommations of three accumulators, A, B and C, all the left-hand digits going to A, the right-hand digits for the " 1 " bits going to B and the righthand digits for the " 4 " and " 8 " bits going to C. (e) The secondary commutator is advanced one stage to cause the pulses from the selected X plate to be filtered through all the " 2 " bit stages of the MC register. (f) The pulses passing the " 2 " bit stages are distributed, the lefthand digits to accumulator A and the right-hand digits to the accumulator B. (g) The column shift commutator then causes the second digit of the multiplier to be used and operations (c) to (f) above are repeated using this'digit. (h) Finally the column shift commutator is advanced to control the transfer of the contents of the accumulator C to accumulator B and then accumulator A to accumulator B, and the product, which is then in accumulator B, is read out and punched in the record card. Specification 598,565 is referred to.