Patent GB-1089307-A (GB)
Title: Data processing apparatus
IPC: G06F7/52
Filed: 1966-04-04
Abstract: 1,089,307. Data processors. INTERNATIONAL BUSINESS MACHINES CORPORATION. April 4, 1966 [April 5, 1965], No. 14752/66. Heading G4A. Data processing apparatus comprises first means for accessing source information from selected positions of a buffer register, second means for maintaining the contents of the first means for storing result information into the register and third means for incrementing said contents and placing them in said first means for accessing the next item of source information. In performing operations with variable-fieldlength operands, a K-register and an L-register each receive a respective 8-byte data word from memory. A so-called T-pointer has a 3-bit register which through a decoder (T out) selects one byte from the K-register for passage to one input of an adder (or logical unit). A 3-bit latch block fed from the 3-bit register selects, through a decoder (T in), the same byte position in the K-register to receive the adder output (prior to storing this in memory). The latch contents are incremented or decremented and then inserted in the 3-bit register to select the next byte, which selection can thus take place concurrently with insertion of the previous adder output into the K-register. A socalled S-pointer has a similar structure but only one decoder (S out) which selects one byte from either the K-register or L-register to feed the second input of the adder, the " K-or-L " feature allowing corresponding bytes of the two operands to be in the same word, e.g. the operands may overlap. In this case, provision is made for transferring the contents of the K-register to the L-register via an M-register when they are still required for one operand but not the other. Otherwise the M-register is used to store subsequent words of the second operand prefetched from memory. Each byte contains two binary-coded-decimal digits, or one such digit plus zone bits and each adder input actually receives only half each presented byte at a time, the order in which the two halves applied to the second adder input are taken being reversible. The second adder input also includes a " true-complement and plus six " circuit. Instructions.-Each instruction word specifies the operation, and also for each of the two operands: (a) a register containing a base address, (b) a displacement to be added to the base address to get the address of the first byte, (c) the number of bytes. Accessing successive words in the memory.- Successive words of the two. operands are in general accessed alternately under the control of a so-called exponent register and a so-called shift counter. The exponent register stores a count of the words processed and gives the increment to be added to the starting address of the first operand to get the next word of that operand. The shift counter gives the increment to be added to the starting address of the first or second operand for the next fetch of either (whichever is next). When a word boundary of the second operand is crossed before one of the first operand during instruction execution, the shift counter is set to the value in the exponent register plus one and two before each subsequent word of the first and second operands respectively are fetched. Otherwise the shift counter is set to the value in the exponent register plus one before each fetch. Storing of result words is under control of the starting address incremented by the contents of the exponent register.