baber/WOPTO huggingface dataset:
Patent JP-H01151826-A (JP)
Title: Sub-range analog-digital converter with multplex input amplifier separating circuit between reduction junction point and lsb encoder
Inventor: MAIRON JIEI KOOEN
IPC: G11C27/02
Filed: 1988-06-29
Abstract: PURPOSE: To reduce the cost and complication of a remainder amplifier circuit part by evading the overdrive of the remainder amplifier of the analog/digital converter for a sub range of a high speed and high accuracy. CONSTITUTION: An MSB flash encoder 17 and an LSB flash encoder 48 respectively generate 7-bit output and it is latched to a digital error correction circuit 61. Least significant 7 bits and most significant 7 bits respectively generated by the LSB flash encoder 48 and the MSB flash encoder 11 are added together and a 12-bit output word for indicating input to this analog/digital converter 1 for the sub range is generated. Multiplexed differential input stages 351 and 352 prevent the overdrive of the remainder amplifier 43 and enable the direct feed-forward of an analog input voltage. Thus, inaccuracy relating to a feed- forward delay circuit is evaded and realization is easily performed on a monolithic circuit chip.
Patent JP-H0824256-A (JP)
Title: Ultrasonic diagnostic apparatus
Inventor: TAKAMIZAWA KINYA
IPC: A61B8/00
Filed: 1994-07-15
Abstract: PURPOSE:To observe a three-dimensional information in the bloodstream by means of a TV monitor by obtaining simultaneously signals within a range of a specified thickness in relation to the slice direction and displaying them transmittently. CONSTITUTION:The output of a driving circuit 3 is fed to continuously adjoining m pieces among m pieces of ultrasonic oscillators 5 being arranged in the scanning direction by means of an electronic switch 4 to generate an ultrasonic wave. Scanning is performed while a transmitting and receiving oscillator is successively shifted by the space of one piece and a Doppler component is extracted from the obtd. signal and it is successively stored in the memory in an operator 18 until data for one frame are formed. When the Doppler image informations for one frame are formed, the image informations are accumulated in the memory 1 in the memory 19 and in the same way, the ultrasonic probe is set approximately at the same site and continuous images approximayely at the same position are obtd. at a microtime interval and they are accumulated in memories 2,...n in the memory 19. Then, two or more image informations are output from the memory 19 and they are synthesized by means of synthesizer and after they are once stored in a memory 13, the are displayed on a monitor 1.
Patent JP-S5863334-A (JP)
Inventor: OOE TATSUYA
IPC: F16L11/12
Filed: 1981-10-14
Abstract: (57)【要約】本公報は電子出願前の出願データであるた め要約のデータは記録されません。
Patent JP-H11336146-A (JP)
Title: Water discharging device
Inventor: TAKAGI TAKESHI
IPC: E03D9/08
Filed: 1998-05-26
Abstract: PROBLEM TO BE SOLVED: To prevent generation of feeling of intermittence in discharged water, or generation of uncomfortable sound by preventing discharge of water in the condition where air bubbles are included in piping. SOLUTION: A controller 16 is interlocked with an input of a discharge water stopping signal from a user to firstly stop a pump motor 14 to drive an air pump 15. After that, a water stopping solenoid valve 12 is closed after passage of a time for all the mixed air bubbles to move to the downstream of the water stopping solenoid valve 12. A delay time (t) after stopping feeding to the pump motor 14 and before closing the water stopping solenoid valve 12 is computed based on a flow (q) equivalent to an output from a flow sensor 11 disposed in a supply passage 1, a piping inner diameter (d) in the supply passage 1, and a supply length (1) in the supply passage 1 from a position where the air bubbles are mixed to the water stopping solenoid valve 12. It is determined by satisfying t>=1/(q/(πd2/4)).
Patent JP-S6320343-A (JP)
Title: Stabilize for chlorine-containing resin
Inventor: FUJITA MITSUO
IPC: C08K9/04
Filed: 1986-07-11
Abstract: PURPOSE:To make it possible to improve the plate out phenomenon during extrusion molding, by adding a basic lead salt surface-treated with a coupling agent to a chlorine-containing resin. CONSTITUTION:This stabilizer for a chlorine-containing resin is one surface- treated with at least 0.2wt% coupling agent by a wet or dry process. Examples of the basic lead salts include tribasic lead sulfate, dibasic lead phosphite and basic lead sulfite. Examples of effective coupling agents include those based on titanium, silane and aluminum.
Patent JP-H0512163-A (JP)
Title: Address modification system
Inventor: IMOTO AKIO
IPC: G06F12/10
Filed: 1991-07-04
Abstract: PURPOSE:To prevent an irrational address setting and to shorten the down time of the network operation by modifying the addresses of machines in a network at one time and under the unitary control. CONSTITUTION:A network manager decides an address modification and gives an address modifying instruction to a controlled machine 3 via a network. The address modifying instruction includes the address decided by the manager, the time when the address is modified, and a prompt which urges the approval of the manager of each machine. The machine 3 modifies the address according to the address modifying instruction when the approval of the machine manager is obtained.
Patent JP-S5866526-A (JP)
Inventor: FUJIWARA KENJI
IPC: H02J7/00
Filed: 1981-10-13
Abstract: (57)【要約】本公報は電子出願前の出願データであるた め要約のデータは記録されません。
Patent JP-S6320188-A (JP)
Title: Method for press welding metallic foil on metallic surface
Inventor: SEGUCHI MANABU
IPC: B23K20/00
Filed: 1986-07-11
Abstract: PURPOSE:To easily obtain a surface-treated member having excellent corrosion resistance at a low cost by subjecting a metallic base material to a blasting treatment to form a rugged surface, imposing metallic foil thereon and subjecting the metallic foil again to the blasting treatment. CONSTITUTION:The surface of the metallic base material requiring cladding is subjected to the blasting treatment with a grit material for blasting and thereafter, the metallic foil is imposed on the blasted surface and is subjected to the blasting treatment from above again by using the same blast material, then the base material and the foil are press welded. The metallic foil is preferably subjected to >=3 times of repetitive treatments rather than one time of the blasting treatment in order to have the higher joint strength of the press welding.
Patent JP-H0917044-A (JP)
Title: Method for mounting stamper and mold for disk substrate
Inventor: ASAI IKUO
IPC: G11B7/26
Filed: 1995-06-29
Abstract: PURPOSE: To obtain a method for mounting a stamper capable of easily and surely fitting and mounting a stamper to positioning projecting part formed with a projecting front end as a flat surface approximately flush with the surface of the stamper. CONSTITUTION: A stamper holder 32 constituting the positioning projecting part 33 is made removable from a metal mold 10 and the stamper 14 is fitted to the stamper holder 32 removed from the metal mold 10. The stamper holder 32 is thereafter attracted and held by a holder and is introduced to the cavity forming surface 15 of the metal mold 10 and is attracted and fixed to the metal mold 10, by which the stamper 14 is superposed and mounted onto the cavity forming surface 15.
Patent JP-S6141217-A (JP)
Title: Delay circuit
Inventor: ASO MAKOTO
IPC: H03H11/26
Filed: 1984-08-01
Abstract: PURPOSE:To decrease the number of component parts and to improve the rise or fall performance of a delay circuit by feeding positively a signal produced from the output signal of an FET back to the gate of the FET. CONSTITUTION:The drain potential of an FET1 is set approximately at 0V in an application mode of power supply. Therefore a Tr5 is kept OFF with the FET1 kept ON respectively. A capacitor 2 is charged continuously after application of the power supply. Then the Tr5 is turned ON when the drain potential of the FET1 gives the breakdown to a Zener diode 4. Thus the gate potential of the FET1 is also reduced. As a result, an electric field is applied to the FET1 to increase the internal impedance. Then the drain impedance of the FET1 rises up further. Thus the base current of the Tr5 flowing through the diode 4 is increased more. The Tr5 is turned ON suddenly owing to such a reproducing action. While the FET1 is suddenly turned OFF.
Patent JP-S5588910-A (JP)
Title: Controlling method for rolling work for pipe
Inventor: YAMADA TAKEO
IPC: B21B37/78
Filed: 1978-12-27
Abstract: PURPOSE:To roll the pipe blank while setting and controlling the peripheral speed of reducing rolls in order to manufacture the finished pipe with wall thickness, etc., uniform over the entire length, according to the complementary variation pattern determined depending on the variation pattern obtained from the actual measurements of wall thickness, etc., over the entire length of the finished pipe being subjected to the previous rolling. CONSTITUTION:The mandrel 2 with the same specification as that of the actually used mandrel is inserted into the pipe blank with the same specification as that of the pipe blank 1 to be rolled; and the test rolling is worked on the pipe blank 1 by each reducing roll 31a-38a; after that, the wall thickness of the pipe blank 1 is actually measured over the entire length of the pipe blank 1; hereby, the variation pattern X of the wall thickness is obtained. Next, the aim wall thickness pattern Y being under the comlmentary relation with above variation pattern X is determined. Besides, Z is for the aim value. Then, the peripheral speed of rolls 31a-38a, necessary for rolling the pipe blank 1 into the finished pipe possessing the pattern Y, is determined and is previously memorized in the controller 4; and the pipe blank 1 is rolled while controlling the peripheral speed of each roll 31a-38a. As a result, the rolling work is carried out so as to eventually cancel the thick walled parts A, B, or thin walled parts C, D; hereby, the rolling accuracy for the wall thickness, outer diameter, etc., of the finished pipe is remarkably improved.
Patent JP-S648198-A (JP)
Title: Safety device for balancing cargo gear
Inventor: OTSUBO KAZUHIKO
IPC: B66D3/18
Filed: 1987-06-30
Abstract: PURPOSE: To prevent the jumping of a rope and an arm by detecting a quick unloading or quick loading by the comparison of a calculation means for finding out the load weight from the acceleration and weight of a hang load with the output of this calculation means and the memory weight of the memory means and stopping a motor emergently when it is detected. CONSTITUTION: A load weight is always calculated by the output of an acceleration sensor 23 and the output of a weight sensor 12 in a quick unload judging circuit 20, The calculated load weight Wx is compared with the memory weight W of a weight memory part 11. When the hang load 1 is hung normally, above comparison result is matched and when the hang load 1 is quickly unloaded or loaded by any reasons, the comparison result is not matched. When this comparison result is unmatched, in a circuit 20, a brake indication is inputted in a brake drive circuit 21 and thereby, the drive circuit 21 drives the brake 22 of a motor 8 and stops the motor 8. Consequently, the jumping of a cargo- handling device is prevented advancely.
Patent JP-S6319348-A (JP)
Inventor: USUI TADASHI
IPC: E04B1/22
Filed: 1986-07-14
Abstract: (57)【要約】本公報は電子出願前の出願データであるた め要約のデータは記録されません。
Patent JP-H1117173-A (JP)
Title: Manufacturing for semiconductor device
Inventor: GOCHO TETSUO
IPC: H01L21/28
Filed: 1997-06-20
Abstract: PROBLEM TO BE SOLVED: To provide a dual gate CNOS with low connection resistance of a gate electrode in a silicide technique, in which an short circuit between source and rain o the gate electrode can be prevented. SOLUTION: Each polysilicon gate electrode 16a or 16b is formed on a silicon substrate 11. An insulating side wall is formed at the sides of the gate electrodes 16a and 16b. An N-type impurity is implanted in the gate electrode 16a in an NMOS region 11a. A P-type impurity is implanted to the gate electrode 16b in an PMOS region in an ion implantation step. After a coating film 41 is formed all over the semiconductor substrate 11, the surface of the gate electrodes 16a and 16b is chemically lapped form the surface side of the coating film 41 to expose the polysilicon. A silicide layer 43 as a surface layer of the gate electrodes 16a and 16b and the semiconductor substrate 11 is formed in a silicide technique.
Patent JP-H0330338-A (JP)
Title: Electric charge transferring device
Inventor: TSUKIKI KAZUNORI
IPC: H01L21/339
Filed: 1989-06-28
Abstract: PURPOSE:To fetch only output signals corresponding to true signal electric charges by alternately transferring electric charges corresponding to smear components and signal electric charges containing smear components to a common electric charge transferring section after accumulation and finally performing a subtracting process. CONSTITUTION:Areas to which signal electric charges Qsig produced at a light receiving section 2 are transferred and another areas to which null transfer is made are alternately provided in an electric charge transferring section 3. To the areas, to which the signal electric charges Qsig are transferred, the true signal electric charges Qsig and smear electric charges Qsme regarding smear components are transferred, whereas only smear electric charges Qsme are transferred to the areas to which the null transfer is made. The electric charges of each adjacent pair of the alternately provided areas are locationally equivalent to each other in quantity of smear electric charges Qsme. Therefore, when a subtracting process is performed by simultaneously transferring these electric charges, only the true signal electric charges Qsig can be extracted.
Patent JP-H1185379-A (JP)
Title: Coordinate input device and recording medium in which program to be used for coordinate input device is recorded
Inventor: YANO TAKASHI
IPC: G06F3/043
Filed: 1998-06-11
Abstract: PROBLEM TO BE SOLVED: To improve the availability by allowing writing by plural users by enabling specification of a writing point from plural detecting positions, regarding a coordinate input device able to be combined with an image display. SOLUTION: Surface acoustic waves transmitted by transducers 2, 4 for transmission are reflected a part by a part by reflection arrays 6a, 6b, 7a, 7b, received by transducers 3, 5 for reception and the detecting position formed by synthesizing the detecting positions in directions of X and Y axes based on a reception signal is specified as the writing point on a substrate 1 by a control part 16 in the coordinate input device.  In this case, when the plural detecting positions are detected for each of the X axis and the Y axis, a coordinate of the writing point is specified by the detecting position of the X axis and the Y axis with the closest detection timing or which is arranged closely to the writing point immediately before the detection point most and in addition, when the last writing point is one, the coordinate of the writing point is specified by the detecting position of the X axis and the Y axis arranged closely to the writing point most and to simultaneously become a diagonal of the writing point by the control part.
Patent JP-S62103194-A (JP)
Title: Image-receiving material for transfer-type thermal recording
Inventor: YUBAGAMI KEIICHI
IPC: B41M5/50
Filed: 1986-07-11
Abstract: PURPOSE:To provide an image-receiving body capable of being subjected to an n-fold mode and giving a high recorded density, by providing a dyeing layer comprising a hardened product of a specified polyester urethane acrylate resin, on a base. CONSTITUTION:A dyeing layer comprising a hardened product of a polyester urethane acrylate resin of the formula, wherein a is a natural number, R is an alkylene and Z is phenylene, a subst. phenylene or an alkylene is provided on a base. By this, sufficient heat resistance can be obtained, and a binder of a color sheet and the dyeing layer are prevented from being fused to each other. Since the polyester urethane acrylate resin is highly dyeable, a high recorded density can be obtained.
Patent JP-H11323565-A (JP)
Title: Pretreatment of electroless nickel plating
Inventor: OKUMURA TATSUSABURO
IPC: C23C18/28
Filed: 1998-05-08
Abstract: PROBLEM TO BE SOLVED: To obtain a plating film having excellent adhesion property without influencing the dimensional accuracy of parts by subjecting a metal plate to be treated by electroless nickel plating to electrolysis pretreatment using it a cathode in an electrolytic cell. SOLUTION: A metal part such as a stainless steel plate having poor adhesion property of nickel plating is used as a cathode and electrolyzed in an electrolytic cell to activate the metal surface. Then the metal part is subjected to electroless nickel plating. Or, the metal part is subjected to PR electrolysis and then to cathode electrolysis for the equivalent time to activate the metal surface. The concn. of the iron metal salt used for the electrolytic soln. is preferably adjusted to 0.02 to 0.2 mol. concn. range which does not cause precipitation of the metal on the cathode. The acid used for the electrolytic soln. consists of one or more kinds of inorg. acids or org. acids. A metal corrosion preventing agent, a metal ion sealing agent, a dispersant and a surfactant may be added to the electrolytic soln.  A minute amt. of metal precipitated by the cathode electrolysis improves the adhesion property of the electroless nickel plating film in the succeeding process.
Patent JP-S6426310-A (JP)
Title: Enclosed switchboard
Inventor: ANTON ROODEII
IPC: H02B1/18
Filed: 1988-07-02
Abstract: PURPOSE: To obtain a highly reliable inexpensive switchboard by partitioning the inside of the housing of a switchboard into two regions and enclosing heat radiating components in one region along with a cooling means and enclosing drip-proof and dust-proof components in the other region. CONSTITUTION: Two regions 1, 2 are formed in the inside of the housing of a switchboard by means of a partitioning wall 3. Vents 5, 8 opened to the outside and a cooling fan 4 are provided in the region 1 and radiators 6, 7 for heat generating components, e.g. a transformer, is housed therein. Drip-proof and dust-proof components, e.g. an electronic switching circuit, are housed in the region 2 while being enclosed against the outer air. According to the structure, outer air can be prevented from having effect on a drip-proof component while utilizing the space in the housing optimally.
Patent JP-H1010600-A (JP)
Title: Camera
Inventor: MIYAMOTO HIDENORI
IPC: G03B7/24
Filed: 1996-06-25
Abstract: PROBLEM TO BE SOLVED: To easily perform the positioning operation of a photoreflector in a camera in which a film cartridge equipped with a bar code pattern rotating integrally with a spool shaft is loaded and where the bar code pattern is read by the photoreflector. SOLUTION: The photoreflectors 7A and 7B are fit in the mount holes 8B and 8C of an FPC 8 and soldered on the FPC 8, so that the FPC 8 and the photoreflectors 7A and 7B are electrically connected. Then, the FPC 8 on which the photoreflectors 7A and 7B are mounted is mounted in the camera body 10. In such a case, it is mounted in the body 10 so that the fitting hole 8A of the FPC 8 is fit to the wall part 6A of the body 10 and the photoreflectors 7A and 7B are fit in mount grooves 10A and 10B.
Patent JP-S6055785-A (JP)
Title: V-size control method of single-tube color camera
Inventor: MATSUOKA TAKAMI
IPC: H04N9/04
Filed: 1983-09-06
Abstract: PURPOSE:To make clear the best control point of V-shape by processing the output signal of a preamplifier of an image pickup tube to display quantitatively the state of the V-size. CONSTITUTION:The output signal of a preamplifier of an image pickup tube 11 is applied to a sampling circuit 12 and sampled to extract only the beat component. This beat component is detected by a wave detector 13 and held by a sample/hold circuit 14. Then the signal of one side is compounded in the same phase with the signal of the other side by a compounder 16 and through a phase inverter 15. This compounded signal is converted into a pulse by a pulse converter 17 and then applied to a digital display meter 18 to display the state of V-shape. Thus it is possible to display quantitatively the state of V-shape and then to make clear the best control point of the V-size.
Patent JP-S5952873-A (JP)
Title: Solid state image pickup device
Inventor: MIYATAKE SHIGEHIRO
IPC: H04N5/335
Filed: 1982-09-20
Abstract: PURPOSE:To increase the maximun quantity of signal charge of a vertical shift register as well as to expand the dynamic range of the titled device by a method wherein the transfer of charge is controlled by the extended part of one of the two layer shift register transistors and a photo diode and the shift register of the extended part of the other electrode are separated by forming a channel stop on the substrate region located directly below said extended part. CONSTITUTION:A channel stop region 14, which is located between the n type layer 3 of a photo diode and the n type layer 2 of a vertical shift register, is widely formed, and a transfer gate region 15 is provided in such a shape that it is formed in the region located directly below electrodes 7 and 9. Clock pulses phi'1, phi2, phi'3 and phi4 are applied to electrodes, 7, 8, 9 and 10. The clock pulses phi'1 and phi'3 are binary pulses of VL and VH. When the clock pulse phi2 or phi4 is VH, the signal charge accumulated on a photo diode 3 passes the transfer gate region 15 and transfered to a vertical shift register 2. On the other hand, when phi2 and phi4 are VL or VI, the signal charge in the shift register is transferred from the lower part to the upper part.
Patent JP-S6143003-A (JP)
Title: Mixer
Inventor: TANAAMI SHIGEYUKI
IPC: H03D9/06
Filed: 1984-08-06
Abstract: PURPOSE:To attain the operation with a small local oscillating power by flowing a bias current to a diode in a balanced type mixer comprising a both side plane circuit and the diode. CONSTITUTION:The right/left side of a slot line 3 orthogonal to a strip line 2 is bent and the right/left slot lones are connected so as to disconnect a part of the conductor connected tothe diode D1 from a grounding face 6. The grounding face 6 and a conductor part 6' disconnected from the grounding face 6 are connected by a capacitor 5 at a point where right/left slot lines are connected. Thus, the part between the conductor part 6' and the grounding face 6 are opened in terms of DC and short-circuited in terms of high frequencies. Thus, a bias current flows to diodes D1, D2 by connecting a bias terminal to the conductor part 6'. As a result the circuit is operated with a small local oscillating power.
Patent JP-S5789375-A (JP)
Title: Synchronization separating circuit
Inventor: OGINO MASANORI
IPC: H04N5/10
Filed: 1980-11-25
Abstract: PURPOSE:To reproduce stable pictures, by feeding back feedback pulse from a vertical deflectng circuit to the input side of a synchronizing separating circuit to stop the operation of the synchronization separating circuit for a short time. CONSTITUTION:Feedback pulses from a vertical deflecting circuit 2 are fed back to the input side of a synchronizing separating circuit through a feedback circuit 3, where a diode D11, a resistance R11, and a parallel circuit consisting  of a resistance R12 and a capacitor C12 are counted in series, to stop the operation of the synchronizing separating circuit for a short time. The parallel circuit  consisting of the resistance R12 and the capacitor C12 is a bias generating circuit for taking out only vertical feedback pulses, and the resistance R11 is provided to set the magnitude of the pulse current to be fed back.