baber/WOPTO huggingface dataset:
Patent TW-312832-B (TW)
Title: Semiconductor memory device and manufacturing method thereof
Inventor: KUMIHASHI TAKAO
IPC: H01L21/02
Filed: 1996-12-05
Granted: 1997-08-11
Abstract: A semiconductor memory device, which mainly has bottom electrode formed by stacking on semiconductor substrate in sequence, and stacked capacitorconstituted by capacitor insulating film and top electrode, and has the functions of storing charge on the capacitor or inverting memory electric signal according to the insulating film branch electrode, comprises of the feature: on the capacitor side forming sidewall spacer, with the top electrode located inner side of the sidewall spacer.
Patent TW-422835-B (TW)
Title: Process for preparing caprolactam
Inventor: JU SHIAU-RUNG
IPC: C07D201/18
Filed: 1997-05-03
Granted: 2001-02-21
Abstract: A simple and single step process for producing caprolactam comprising reacting 5-formylvaleric acid or an ester thereof in a solvent of water and/or an alcohol with hydrogen and ammonia in the presence a noble metal catalyst supported by a carrier of at 80 DEG C to 300 DEG C. under a pressure of 10 to 120 atm. whereby  amination, acidification, dehydration and cyclization occur to obtain caprolactam.
Patent TW-396325-B (TW)
Title: Automatic ticket examining system
Inventor: TSUJI SEIICHIRO
IPC: G06Q50/00
Filed: 1997-07-17
Granted: 2000-07-01
Abstract: This system is an automatic ticket examination device 100 for reading ticket examination information from a passenger ticket. It will automatically execute ticket examination work. A monitoring device sets up or simulates optimal conditions of the device 100. The monitoring device is provided with a reset validity/ invalidity setting switch for setting up a reset switch 16. Reset switch 16 is arranged on the device 100 to reset the abnormal state of the device 100 to a 1st mode in order to validate the switch 16 function or a 2nd mode to invalidate the function. The device 100 has a reset validating switch 17 to forcedly alter switch 16 to the 1st mode when the switch 16 is set at 2nd mode.
Patent TW-382168-B (TW)
Title: Data processing and communicating system with high throughput peripheral component interconnect bus
Inventor: MANABE MASAO
IPC: G06F13/40
Filed: 1997-07-18
Granted: 2000-02-11
Abstract: A data communication system has a host bus connected to a central processing unit and a system memory, a peripheral component interconnect bus connected to a communication device equipped with a first status machine and a second status machine independently requesting a right to use the peripheral component interconnect bus and a bus bridge circuit connected between the host bus and the peripheral component interconnect bus and having a first-in-first-out memory for data write-in and another first-in-first-out memory for data read-out, and the bus bridge circuit assigns the right to use the peripheral component interconnect bus to the second status machine so as to transfer write-in data codes through the peripheral component interconnect bus to said first-in-first-out memory until completion of a data transfer from the memory through the host bus to the first-in-first-out memory, thereby improving the throughput of the peripheral component interconnect bus.
Patent TW-355762-B (TW)
Title: Checkpoint rollback I/O control device and I/O control method
Inventor: YAMADA KUNIO
IPC: G06F11/14
Filed: 1997-07-25
Granted: 1999-04-11
Abstract: An I/O control device with checkpoint rollback function, arranged to work with computer systems with multi-stage data I/O modules, comprising: the first output control device that is interfacing the said I/O modules and submodules thereof, and the second output control device that is interfacing the said I/O modules and submodules thereof, and device for computing managed fault generation for each checkpoint rollback, and device for pausing direct memory access prior to checkpoint rollback, and device for calling reset handler for said hardware while performing checkpoint rollback; the said first I/O control device comprises: a device for storing I/O request and fault management generation from calling module, and the request for reissuing I/O when returning to the calling module; by comparing the results and issuing request for inconsistency so the reset handler will be able to return control to the calling module.
Patent TW-390816-B (TW)
Title: A needle assembly for electrostimulation of a nerve
Inventor: STROWE ROBERT J
IPC: A61N1/05
Filed: 1997-08-12
Granted: 2000-05-21
Abstract: An electrolocation apparatus is provided for locating a nerve to which anesthesia may be delivered. The apparatus includes a needle assembly having an electrically conductive needle cannula non-conductive tube secured over the needle cannula, and a conductive plating on the tube. The conductors are connected to a stimulator that generates alternating high and low charge pulses with a constant low current level. The high charge pulses generate noticeable muscle twitches immediately after insertion of the needle into the patient. Muscle twitches responsive to the low charge pulses will peak in magnitude, and muscle twitches responsive to the low charge pulses will become observable as the needle approaches the targeted nerve, and will be indistinguishable from the muscle twitches responsive to the high charge pulses when the needle is in a position for administration of anesthetic.
Patent TW-455800-B (TW)
Title: Device, system, and method for modem communication utilizing two-step mapping
Inventor: LONG GUOZHU
IPC: G06F19/00
Filed: 1997-10-16
Granted: 2001-09-21
Abstract: Modem technology is implemented in a system including a personal computer (PC) to enable communication over a PSTN using communication software which includes a mapping algorithm for mapping data into u-law signal points, which are divided into segments with different distances.
Patent TW-364065-B (TW)
Title: Low chromatic aberration rod type lens array and device, and an image scanner using such device
Inventor: TAHARA YASUTERU
IPC: H04N1/48
Filed: 1997-10-30
Granted: 1999-07-11
Abstract: The present invention relates a low chromatic aberration rod type lens array and device, and an image scanner using such device. The present invention consists of, generally, primary color LED array 4 for radiating light to read master copies 2, monochromic image sensor array 3, and rod type lens array 1 arranged between read master copies 2 and image sensor array 3 to construct color image scanner. Three refractive index distribution type rod lens 11, 12, 13 constructing rod type lens array 1 each has different action wavelength range and predetermined wavelength, while all types of lens length Z0 are the same, focusing parameter of each type of the rod lens is set such that all types are substantially the same in respect of conjugate length TC in the different type of predetermined wavelengths. Therefore, using rod type lens array with the advantages of compactness and brightness to read color image can sufficiently reduce the chromatic aberration of rod type lens array, thus achieving high image distinctness at low cost.
Patent TW-381318-B (TW)
Title: Method of manufacturing analog semiconductor device
Inventor: KIM JAE-KAP
IPC: H01L21/02
Filed: 1997-11-19
Granted: 2000-02-01
Abstract: The present invention to provide a method of manufacturing an analog semiconductor device capable of minimizing the CD variation of the gate and improving the integration  of a semiconductor device. The analog semiconductor device according to the present invention is manufactured by the following processes. First, a semiconductor substrate in which isolation films are formed is provided. A gate insulating layer, a first conductive layer, a dielectric layer and a second conductive layer are then formed on the substrate in sequence. Next, a first photoresist pattern is formed on the predetermined portion of the second conductive layer. The second conductive layer and the dielectric layer are then patterned using the first pattern as an etch mask, to form a first pattern for gate electrode on the substrate between the isolation films and form a second pattern for lower capacitor electrode on the predetermined portion for the isolation film. Next, the first photoresist pattern is removed and a second photoresist pattern for an upper capacitor electrode is then formed on the second pattern. The second conductive layer of the first and second patterns and the exposed first conductive layer at both sides of the first and second patterns are etched using the dielectric layer, the gate insulating layer and the isolation films as an etch stopper and then the second photoresist is removed.
Patent TW-366545-B (TW)
Title: Lead frame structure and semiconductor package using same and fabrication method thereof
Inventor: KWON OH-KYONG
IPC: H01L21/60
Filed: 1997-11-24
Granted: 1999-08-11
Abstract: A lead frame structure and semiconductor package using same and fabrication method thereof. The lead frame structure for a semiconductor package provided with a paddle, and a plurality of leads regularly aligned outside the paddle, includes an upper and lower dielectric adhesive layers sandwiching the plurality of leads therebetween, an upper and lower dielectric layers attached on an upper surface of the upper dielectric adhesive layer and a lower surface of the lower dielectric adhesive layer, and an upper and lower metallic polar plates formed on an upper surface of the upper dielectric layer and a lower surface of the lower dielectric layer. The semiconductor package decreases noises such as Electro-magnetic noise, reflection noise and delta-I noise by appropriately providing characteristic impedances for selected leads applicable to signal lines and at the same time decreasing characteristic impedances for the selected leads applicable to power lines or ground lines.
Patent TW-393719-B (TW)
Title: Localized oxidation without silicon residue
Inventor: JIN WEI-SHANG
IPC: H01L21/76
Filed: 1997-12-08
Granted: 2000-06-11
Abstract: A LOCOS method can avoid silicon residue that may contaminate the acid tank and process. This discovery comprises a pad oxide formed on the semiconductor substrate first, and then a silicon nitride layer. After etching a part of silicon nitride layer, it then generates an semiconductor substrate active area, then removes a part of the pad oxide layer to form a subsidence between the silicon nitride layer and the semiconductor substrate. Secondly, amorphous spacer is formed on the side wall silicon nitride layer and the pad oxide layer. Finally, the oxidize substrate to make a field isolation area on the substrate.
Patent TW-364189-B (TW)
Title: Method for forming a nonvolatile memory cell and memory cell resulting therefrom
Inventor: MCELROY DAVID J
IPC: H01L29/792
Filed: 1998-04-08
Granted: 1999-07-11
Abstract: A method for forming a nonvolatile memory cell (l0) includes the steps of forming an array area (12), an N-channel periphery (20), a P-channel periphery (24) and a polysilicon 1 layer slot area pattern (18). Patterning a stack transistor (40) array area (12) without removing photoresist (52) from N-channel periphery (20) and P-channel periphery (24) is another step of the present method. The method then includes patterning N-channel region (60) without removing photoresist (52) from P-channel periphery (24). Applying photoresist (74) to the stack transistor (40) and N-channel region (60), as well as over a predetermined portion of P-channel periphery (24) for forming P-channel region (70) then occurs. The P-channel region (70) may be formed in the P-channel periphery (24). Contacts and protective oxide (90, 92) may then cover stack transistor (40), N-channel region (60), and P-channel region (70).
Patent TW-356607-B (TW)
Title: Noise-isolated buried resistor
Inventor: NOWAK EDWARD J
IPC: H01L21/822
Filed: 1997-12-18
Granted: 1999-04-21
Abstract: A kind of buried resistor, comprising a region of first conductor inside first electrical slot of second inductor formed from the isolation of shallow trench insulator (STI), forming the first electrical slot inside the second electrical slot of the first conductor, and forming the second electrical slot inside a second conducting multi-cell layer on substrate, for using as electric field shield of the buried resistor.
Patent TW-369700-B (TW)
Title: Intrachip power distribution package and method for semiconductors
Inventor: MURRAY MICHAEL
IPC: H01L21/768
Filed: 1998-02-24
Granted: 1999-09-11
Abstract: An integrated circuit has a supply node for supplying power to at least one intermediate node coupled to circuitry for receiving power. Rather than transmit power from the supply node to the intermediate node by means of a power bus formed as part of the chip interconnect structure, power us supplied to an external wire which is coupled from the supply to the intermediate node. Other than as connected to the supply node and intermediate node, the wire is electrically isolated from the die. This structure and method for making the semiconductor package allow power to be distributed within a semiconductor chip without sacrificing valuable chip space and without requiring a special lead frame for distributing the power within the semiconductor chip.
Patent TW-565695-B (TW)
Title: Method and apparatus for correcting ambient temperature effect in biosensors
Inventor: HUANG DIJIA
IPC: G01N27/26
Filed: 1998-02-26
Granted: 2003-12-11
Abstract: A method and apparatus are provided for correcting ambient temperature effect in biosensors. An ambient temperature value is measured. A sample is applied to the biosensors, then a current generated in the test sample is measured. An observed analyte concentration value is calculated from the current through a standard response curve. The observed analyte concentration is then modified utilizing the measured ambient temperature value to thereby increase the accuracy of the analyte determination. The analyte concentration value can be calculated by solving the following equation, where G1 is said observed analyte concentration value, T2 is said measured ambient temperature value and I1, I2, S1, and S2 are predetermined parameters.
Patent TW-347453-B (TW)
Title: Energy guiding chain
Inventor: BLASE GUNTER
IPC: F16G13/16
Filed: 1998-04-14
Granted: 1998-12-11
Abstract: An energy guiding chain (1) for guiding cables, hoses and the like between two connection points, comprising several chain straps which are connected to one another via upper and lower cross-members in detachable fashion and assembled in two parallel strands, and which overlap one another and can be angled, there are alternating chain straps (2) designed as inner straps (3) with inner overlap areas (5) and as outer straps (4) with outer overlap areas (5) in each chain strap, the angling of the chain straps (2) relative to one another being restricted by stops (8,9,12,13) located in the overlap areas (5), the curvature of the chain (1) being defined by the position of the stops (8,9,12,13), which is characterized in that: if the stops (8,9,12,13) in the inner and outer straps (3,4) are positioned asymmetrically with respect to the center axis running in the longitudinal direction of the chain (S2) as the axis of symmetry, it is possible to produce two different bending behaviors in the energy guiding chain (1) using the same inner and outer straps (3,4), depending on the orientation of the straps (3,4) with respect to the longitudinal direction of the chain.
Patent TW-475210-B (TW)
Title: Structure and formation method of metal oxide semiconductor transistor
Inventor: YE WEN-GUAN
IPC: H01L21/336
Filed: 1998-06-15
Granted: 2002-02-01
Abstract: This invention provides structure and formation method of metal oxide semiconductor transistor. A first spacer is formed on the peripheral of a gate electrode on a semiconductor substrate. Source/drain area is formed using deep ion implantation, which is followed by an annealing treatment and removal of the spacer. A thin liner is deposited and lightly doped ion implantation is performed to create a ring structure in the source/drain area. The method of the present invention can avoid damage to the profile of the lightly-doped drain area by the annealing treatment, protect the surface of the substrate from the damage of ion bombardment by the formation of the dielectric layer, obtain shallower light-dopant profile and thinner spacer and reduce sheet resistance of the source/drain.
Patent TW-410246-B (TW)
Title: Roadside energy absorbing barrier with improved fender panel fastener
Inventor: MACHADO JOHN V
IPC: E01F15/14
Filed: 1998-06-15
Granted: 2000-11-01
Abstract: A roadside energy absorbing barrier includes energy absorbing elements interposed between diaphragms, with fender panels mounted by hinges to the diaphragms. The fender panels define longitudinally extending slots, and a fastener is mounted between adjacent fender panels. This fastener includes a bolt passing through an enlarged washer, a slot in one fender panel and an adjacent fender panel. A nut is positioned on the bolt inwardly of the fender panels, and a coil spring is mounted on the bolt and reacts against the nut and the fender panels to bias the first fender panel toward the second fender panel while permitting a selected separation therebetween.
Patent TW-467921-B (TW)
Title: Metal complex and its use in olefin polymerization
Inventor: MURRAY REX EUGENE
IPC: C08F4/60
Filed: 1998-07-16
Granted: 2001-12-11
Abstract: A catalyst precursor having the formula: AqMLn, wherein each A has the formula: M is a metal selected from the group consisting of group 3 to 13 elements and Lanthanide series elements; each L is a monovalent, bivalent, or trivalent anion; X and Y are each heteroatoms; cyclo is a cyclic moiety; each R1 is independently a group containing 1 to 50 atoms selected from the group consisting of hydrogen and group 13 to 17 elements, and two or more adjacent R1 groups may be joined to form a cyclic moiety; each R2 is independently a group containing 1 to 50 atoms selected from the group consisting of hydrogen and group 13 to 17 elements, and two or more adjacent R2 groups may be joined to form a cyclic moiety; Q is a bridging group; each m is independently an integer from 0 to 5; n is an integer from 1 to 4; q is 1 or 2; and when q is 2, the A groups are optionally connected by a bridging group Z is provided. The catalyst precursor may be made by reacting an organometal compound with a heteroatom-containing ligand. The catalyst precursor, when combined with an activating cocatalyst, is useful for the polymerization of olefins.
Patent TW-396306-B (TW)
Title: A method of executing perform locked operation instructions for supporting recovery of data consistency if lost due to processor failure, and a method of recovering the data consistency after processor failure
Inventor: SCALZI CASPER A
IPC: G06F11/22
Filed: 1998-09-03
Granted: 2000-07-01
Abstract: Provides a processor method of executing instances of a Perform Locked Operation (PLO) instruction for enabling a recovery of the consistency of a resource unit being changed by a PLO instance when processor failure occurs anywhere during execution of the PLO instance. The method uses a PLO save area for each processor in a computer system capable of executing PLO instructions. Each PLO save area has a resource-inconsistency (RI) indicator having an RI state and a non-RI state, and stores the function code (FC) of the PLO instance. The RI stste indicates that the resource is in a non-usable potentially inconsistent state, and the non-RI state indicates the resource is in the consistent state and my be used. A processor executing a PLO instance writes into its PLO save area all resource addresses where a charge is to be made in the resource unit, and also writes in its PLO save area all operand values which will be used to change the resource at the associated addresses. After the processor has sucessfully written all of these addresses and associated operand data values into its PLO save area, the processor sets its RI indicator to the RI state, and then stores into the resource unit the data values stored in its PLO save area at the resource addresses also stored in its PLO save area, according to the FC also stored therein. After completing all charges in the resource, the processor sets its RI indicator to the non-RI (resource consistent) state. If the processor should ever fail while executing a PLO instance, it signals its failing conditiion to the system. Then, a RCR method is executed by any operational processor (acting as a RCR processor) to recover the consistency of the resource unit. The RCR method uses the state of the RI indicator with the failed processor's PLO save area, the FC stored therewith, and the content of the failed processor's PLO save area to restore the consistency of the resource unit.
Patent TW-455636-B (TW)
Title: Device for forming chenilles on a crochet textile machine for warp weaving
Inventor: ZORINI LUIGI OMODEO
IPC: D04B25/14
Filed: 1998-09-17
Granted: 2001-09-21
Abstract: A device is provided for the formation of chenilles for crochet textile machines for warp weaving comprising a plurality of cutting elements (12) able to cut the woof threads (8) and positioned immediately below the area occupied by the needles (2) wherein the woven stitches (9a) are formed and means for controlling the cutting elements (12) defined by the same means for longitudinally driving the needles (2).
Patent TW-407380-B (TW)
Title: A new split gate flash memory and process for forming same
Inventor: YANG YU-HAU
IPC: H01L29/423
Filed: 1998-09-24
Granted: 2000-10-01
Abstract: A split-gate semiconductor flash memory contains an outwardly-diverging control gate stacked on but separated from a pair of opposing floating gates via an inter-poly dielectric layer. The split-gate flash memory is formed by (a) forming a first dielectric layer having a trench region on a substrate; (b) forming a tunnel oxide layer in the trench region; (c) forming a first polysilicon layer covering the first dielectric layer and the tunnel oxide layer; (d) applying an anisotropic etching technique on the first polysilicon layer to form a pair of opposing polysilicon sidewall spacers on the sidewalls which will eventually become floating gates; (e) depositing an inter-poly dielectric layer on the polysilicon sidewall spacers and the tunnel oxide layer; (f) filling the channel area between the pair of polysilicon sidewall spacers with a second polysilicon layer; (g) planarizing the second polysilicon layer so that relative to the first dielectric layer to form a control gate; (h) removing the first dielectric layer, capping the control gate and the floating gate with a final oxide layer, and forming source and drain regions in the substrate using ion implantation. The split-gate flash memory eliminates the over-erase problem experienced with the self-aligned ETOX flash memory cells, while allowing its cell dimension to maintain at least the same using the conventional photolithography technique.
Patent TW-396229-B (TW)
Title: Tissue paper having a substantive anhydrous softening mixture deposited thereon
Inventor: FICKE JONATHAN ANDREW
IPC: D21H17/59
Filed: 1998-10-01
Granted: 2000-07-01
Abstract: Strong, soft, and low dusting tissue paper webs useful in the manufacture of soft, absorbent sanitary products such as bath tissue, facial tissue, and absorbent towels are disclosed. At least one surface of the tissue paper has uniform discrete surface deposits of a substantively affixed chemical softening mixture comprising a mixture of a quartenary ammonium compound, an emollient, and a sorbitan ester.
Patent TW-389986-B (TW)
Title: Method for producing shallow trench isolation (STI)
Inventor: SHR SHIUE-HAU
IPC: H01L21/76
Filed: 1998-12-15
Granted: 2000-05-11
Abstract: A method for producing a shallow trench isolation (STI) comprises forming a pad oxide layer on a substrate; forming a hard mask layer on the pad oxide layer; defining the oxide layer and the pad oxide layer by a photolithography etching to expose a portion of the substrate; etching the exposed substrate to form a trench; planarizing the surface of the trench by a hydrogen treatment; forming a STI structure with a conventional process.