Patent GB-802745-A (GB)
Title: Improvements in or relating to electrical digital computers
Inventor: POEL WILLEM LOUIS VAN DER
IPC: G06F9/30
Filed: 1955-12-23
Abstract: 802,745. Digital electric calculating-apparatus. STAATSBEDRIJF DER POSTERIJEN TELEGRAFIE EN TELEFONIE, and STANDARD TELEPHONES & CABLES, Ltd. Dec. 23, 1955, No. 36986/55. Class 106 (1). In an electric digital computer in which operations are performed under control of instruction words each including a function portion consisting of a fixed number x of binary digits, each digit individually indicating one of a number of basic computer operations including arithmetic operations, the x digits are registered respectively on x individual elements of a binary register, and x control units each individual to a corresponding register element are arranged to be set to corresponding conditions, the operation of the computer for the performance of each basic operation occurring solely as a result of the condition of the appropriate control unit. The computer described comprises a magnetic drum having main storage tracks each holding 32 words of 33 binary digits plus a 7-digit gap, and three timing pulse tracks as in the drum described in Specification 799,793, and short single-word dynamic registers each comprising a section of magnetic track and a recirculation path between reading and writing heads. Two of these registers 2, 3, comprise accumulator sections ACC1, ACC2 of the arithmetic unit. The control unit comprises static registers CON1 for registering the current instruction and a further dynamic register CON2. Each instruction comprises function digits A, K, Q, L, R, I, B, C, D, E, test digits V, V4, V2, V1, digit W controlling the time selection of words in the main store, a short register address (5 binary digits - 1 or 2 decimal digits) and a drum store address (13 binary, 3 or 4 decimal). In operation, an instruction is fed serially into a pattern movement register (top register of CON1) comprising 33 bi-stable flipflops, and at the end of the word period, the digits (except V4, V2, V1) are normally transferred to corresponding flip-flops in a staticizer (lower register of CON1) whose outputs control coincidence gates to carry out the instruction. As shown, gating connections controlled by the function digits are diagrammatically represented by relay contacts which are shown in the " 0 " position, each digit individually indicating a separate computer operation. Instructions normally occupy alternate word positions on a drum and are selected sequentially by adding " 2 " to the drum address as it is passed from CON1 to CON2, the new address being fed back to CON1 provided A = 1 in the previously selected instruction. If A = 0, a new instruction is entered via an adder which may receive one input from the main store and, if K = 1, a second input from a short register. When A = 1 and K = 0 respectively data from the main store and short registers is passed to ACC1 or ACC2 (B = 0 or 1), and if C = 1 the selected accumulator section is cleared as the new data is entered. If R = 1, L = 1, a right or left shift respectively occurs in the accumulator in a similar manner to that described in Specification 799,793, with digit transfer between ACC1 and ACC2. If Q = 1, ACC2 acts as a counter to which " 1 " is added during every word cycle. An adder/subtractor is included in the recirculation path of both ACC1 and ACC2, subtraction being effected when I = 1. The adders and adders/subtractors shown may be similar to those described in Specifications 749,440 and 783,229 respectively, and each comprise an arrangement of coincidence gates and a carrystoring flip-flop (Fig. 7, not shown). If D = 1, E = 1 information is written, instead of being read, in the main store and short registers respectively. If A = 0 (" X " = 1) and D = 1, or if L, R and b32 (the lowest significant digit in ACC2) are " 1," the contents of short register 15 are passed to the accumulator. The combination LR occurs during multiplication and causes a right shift (R having precedence over L), the multiplicand in 15 being added in ACC1 whenever the multiplier digit b32 in ACC2 is " 1." Programmes are given in the Specification for multiplication and for other operations, e.g. checking the contents of part of the main store, and transfer of data between the main store and short registers. If digit V = 1, a test is made of the sign digit ao in ACC1 if V1 = 1, the sign digit bo in ACC2 if V2 = 1, or the lowest significant digit b32 in ACC2 if V4 = 1 respectively. If the tested digit is " 0," a flip-flop 264F inhibits the normal gating connections between the pattern movement register and the staticizer, and causes a " pseudo-instruction " A.W to be set up. The digit W is normally made " 1 " or " 0 " by the computer (by interpretive means, not described) according to whether the short register address or drum address occurs first in the input programme. If W = 0, the drum time selection circuits operate, the execution of an instruction being delayed, if necessary, until the required drum location is reached. If W = 1, the drum address p does not cause a selection from the main store, but is replaced by 213-2p and used to cause p repetitions of an instruction; the repetitions occur until, owing to the additions of " 2 " as the instruction passes to CON2, a carry occurs into the short register address positions, the new short register then addressed containing a " return " instruction. The address numbers control main storage track and short register selection through tree circuits, the main store having a single input/output tree including twoway gate devices, e.g. junction transistors.