Patent SG-11201908404U-A (SG)
Title: Energy-efficient variable power adder and methods of use thereof
Inventor: RAO HARI
IPC: G06F7/506
Filed: 2018-03-28
Abstract: 202 202 200 Coot FIG. 2 O O\ 00 O C (12) INTERNATIONAL APPLICATION PUBLISHED UNDER THE PATENT COOPERATION TREATY (PCT) (19) World Intellectual Property Organization International Bureau (43) International Publication Date 18 October 2018 (18.10.2018) WIP0 I PCT omit VIII °nolo VIII H 010 VIII OH oimIE (10) International Publication Number WO 2018/191015 Al (51) International Patent Classification: GOOF 7/506 (2006.01) (21) International Application Number: PCT/US2018/024785 (22) International Filing Date: 28 March 2018 (28.03.2018) (25) Filing Language: English (26) Publication Language: English (30) Priority Data: 15/488,019 14 April 2017 (14.04.2017) US (71) Applicant: QUALCOMM INCORPORATED [US/US]; ATTN: International IP Administration, 5775 Morehouse Drive, San Diego, California 92121-1714 (US). (72) Inventor: RAO, Hari; 5775 Morehouse Drive, San Diego, California 92121-1714 (US). (74) Agent: KELTON, Thomas W. et al.; Haynes and Boone, LLP, 2323 Victory Avenue, Suite 700, Dallas, Texas 75219 (US). (81) Designated States (unless otherwise indicated, for every kind of national protection available): AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DJ, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JO, JP, KE, KG, KH, KN, KP, KR, KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW. (54) Title: ENERGY-EFFICIENT VARIABLE POWER ADDER AND METHODS OF USE THEREOF (57) : A multi-bit adder apparatus comprising: a full adder stage configured to receive at least some of a plurality of least significant bits (LSBs) of first data and second data; and a half adder stage configured to receive at least some of a plurality of most significant bits (MSBs) of the first data and the second data; a carry generation stage coupled to the full adder stage and the half adder stage, wherein the carry generation stage includes at least one serial propagate-generate(PG) component; and a post summing stage coupled to the carry generation stage and the half adder stage and configured to generate a partial sum output of the first data and the second data, wherein a number of the at least some of the plurality of LSBs is different from a number of the at least some of the plurality of MSBs. [Continued on next page] WO 2018/191015 Al MIDEDIMOMOIDEIREEMOMOHHOEIROHOMEEN (84) Designated States (unless otherwise indicated, for every kind of regional protection available): ARIPO (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW), Eurasian (AM, AZ, BY, KG, KZ, RU, TJ, TM), European (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR), OAPI (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG). Declarations under Rule 4.17: as to applicant's entitlement to apply for and be granted a patent (Rule 4.17(ii)) as to the applicant's entitlement to claim the priority of the earlier application (Rule 4.17(iii)) Published: — with international search report (Art. 21(3))