Patent GB-1461087-A (GB)
Title: Automatic tuning apparatus
IPC: H03L7/14
Filed: 1973-12-28
Abstract: 1461087 Stop on signal receivers; AFC circuits SANYO ELECTRIC CO Ltd 28 Dec 1973 [8 June 1973 (3) 31 Aug 1973] 60022/73 Headings H3Q and H3A An automatic tuning apparatus comprises a solid state electro-chemical potential memory device 13 (1, Fig. 1, not shown) having a solid state electrolyte (4) between a cathode (2) including an active metal and an anode (3) comprising a compound including the metal, a tuning circuit 21 comprising a voltage controlled variable reactance device connected to be supplied with a voltage associated with the terminal voltage of the memory device, a circuit 12 for selectively charging or discharging the memory device and a circuit 40-42 and 47-49 responsive to a signal indicative that the tuning circuit 21 is tuned to a desired frequency for disabling the circuit 12 for discontinuing the charging or discharging of the memory device. In the TV receiver shown in Fig. 6 the scanning of TV channels up or down is started by manually operable up switch 11U or down switch 11D which operate a control circuit 12, shown in detail in Fig. 7, to charge the memory device 13 via R72, FET TR73 or discharge the memory device 13 via R71, FET TR73 and TR71 so as to tune a channel selector or tuner 21 to higher or lower channels. Lower and upper threshold detectors 15, 16 such as transistor Schmitt circuits (Fig. 8, not shown) are alternately operated in response to the charge and discharge of the memory device 13 reaching the thresholds of these circuits to change the control circuit 12 to discharge and charge states respectively. The operation of the threshold 15, 16 prevents the device 13 from being damaged by overcharging. The outputs from these threshold circuits 15, 16 set and reset a flip flop 17 so as to first enable a gate 20 to pass an output ramp voltage from a DC amplifier 14 via an inverter 19 to the tuning input of the channel selector 21 and then second to enable a second gate 18 to pass the output ramp voltage of the DC amplifier 14 to the tuning input of the channel selector 21. The ramp voltages are supplied to variable capacitance diodes (VC1, VC2, Fig. 9, not shown) of the hf amplifier and local oscillator of the tuner 21. An output from the flip flop 17 is fed via an inverter 29 to waveband switching diodes (D91 and D92) in the tuner 21 so that these diodes are off for low frequency channels and on for higher frequency channels. The output from the IF amplifier 23 is fed to a tuning detector circuit 40-41 and 47-49 shown in detail in Fig. 10. When the sound and video components of the IF passed by BPF's 47 and 48 reaches a level determined by level detectors 49 corresponding to a received signal an output signal sets a flipflop 134 which was reset from 135, Fig. 7 on operation of a switch 11 for channel selection. Also a frequency detector 42 such as a ratio detector operates via a charging/discharging control signal generating circuit 40 to provide an AFC. When exact tuning is detected the outputs 122, 123 from the circuit 40 together with the output from the flipflop 134 operate via an AND gate 41 to disable the control circuit 12 to stop the charging or discharging of the potential memory device 13. Simultaneous detection of the sound or video component and a synchronising pulse output can be used instead of control by the sound and video components. Any drift in tuning detected causes charging or discharging control signals from 120, 121 to control the charging or discharging of the potential memory device 13 so as to retain the tuning on the received signal. A simplified embodiment is disclosed (Fig. 4, not shown) which excludes the AFC. The memory device 13 includes a main cathode 32 of Ag for charging and discharging and an auxiliary cathode 34 of Ag for providing the ramp voltage output, a solid state electrolyte Ag 3 SI (31, Fig. 3, not shown) and an anode 33 of Ag-Te. The apparatus may be applied to AM and FM radio receivers. Specification 1461086 is referred to.