Patent DE-102005012356-A1 (DE)
Title: Wet-etch composition for manufacturing e.g. electrode of a capacitor for semiconductor device comprises peracetic acid and fluorinated acid
Inventor: LEE HYO-SAN
IPC: G11C8/02
Filed: 2005-03-17
Abstract: Wet-etch composition comprises an oxidant exhibiting a significantly greater etching rate for silicon-germanium relative to silicon and a fluorinated acid. The relative amount of the oxidant in the composition being sufficient to ensure an etch rate ratio of silicon-germanium (SiGe):silicon (Si) for PMOS transistors of the CMOS device. Independent claims are included for: (a) manufacturing semiconductor device having a multi-bridge-channel field effect transistor (MBCFET) structure involving providing a structure having stacked Si bridge layers and SiGe interbridge layers, respectively and supported by at least one bridge-support structure; applying an etchant composition to side surfaces of the SiGe bridge layers, the etchant including peracetic acid (PAA) and a fluorinated acid. The relative amount of the PAA in the composition being sufficient to yield an etch rate ratio of SiGe:Si for NMOS transistors of the MBCFET device that is substantially the same as an etch rate ratio of SiGe:Si for PMOS transistors of the MBCFET device; (b) selectively removing SiGe from between layers of silicon involving providing a substrate, forming a stack of alternating layers of SiGe and Si on the substrate, exposing side surfaces of the stack, applying an etchant composition to side surfaces of the SiGe bridge layer, the etchant including PAA and a fluorinated acid. The relative amount of the PAA in the composition being sufficient to yield an etch rate ratio of SiGe:Si for NMOS transistors that is substantially the same as an etch rate ratio of SiGe:Si for PMOS transistors; (c) manufacturing a semiconductor capacitor involving providing a substrate that includes a conductive region, forming a SiGe layer on the substrate, forming a storage node hole in the SiGe layer to expose the conductive region in the substrate, forming a silicon layer on the SiGe layer and on the exposed conductive region of the substrate, forming an insulating layer on the silicon layer, selectively removing portions of silicon layer and insulating layer to define a storage electrode, applying an etchant composition to side surfaces of the SiGe layer, the etchant including PAA and fluorinated acid; (d) manufacturing (M1) an integrated circuit CMOS field effect transistor involving forming a pre-active pattern on a surface of a substrate, the pre-active pattern including a series of SiGe inter-bridge layers and Si bridge layers stacked alternately upon each other; forming source/drain regions on the substrate, at opposite ends of the pre-active pattern; selectively removing, using an etchant, the number of interbridge layers, to form a number of tunnels passing through the pre-active pattern to define an active channel pattern including the tunnels and a number of bridges including the bridge layers, the etchant exhibiting an etch rate ratio of SiGe:Si for NMOS transistors of a CMOS device that is substantially the same as an etch rate ratio of SiGe:Si for PMOS transistors of the CMOS device and forming a gate electrode in the tunnels and surrounding the bridges; and (e) forming (F1) an electrode of a capacitor for a semiconductor device involving forming an interlayer insulating layer on a semiconductor substrate, the interlayer insulating layer having a conductive pad; forming an etch stop layer on the interlayer insulating layer, forming a first moulding layer of SiGe on the etch stop layer, forming a storage node opening in the first moulding layer, depositing conductive layer of Si on the first moulding layer and on the sidewalls and the bottom of the opening, forming a second molding layer of SiGe on the conductive layer, planarizing the resulting structure until the top surface of the first molding layer is exposed, partially removing an upper portion of the first and second molding layers using a PAA-based etchant to expose a sidewall portion of the conductive layer, thinning the exposed sidewall portion and removing the remaining portion of the first and the second molding layers .