Patent GB-1105245-A (GB)
Title: Improvements in stored programme data processing devices
Inventor: THREADGOLD RONALD
IPC: G06F9/28
Filed: 1964-08-28
Abstract: 1,105,245. Electric digital computers: micro-programmes. AUTOMATIC TELEPHONE & ELECTRIC CO. Ltd. 3 Sept., 1965 [28 Aug., 1964], No. 35430/64. Heading G4A. Main programme orders include a code for addressing a sequence of micro-orders in a pre-programmed micro-programme store. Each micro-order generates control signals according to the plugging of a plug board translation field for defining micro-instructions which are each performed in three phases viz: 1, control of addressing unit (indexing phase), 2, control of arithmetic unit (processing phase) and 3, selecting the next micro or main programme order. The phases may overlap. Only one function is performed by the indexing and arithmetic units respectively for any one microorder. The main programme order words (Fig. 2, not shown) comprise 48 bits of which the first 8 in all cases define an address in the microprogramme store shown in Fig. 3. Of these eight bits, 1-4 select one of 16 order selection units osu 0-15 and 5-8 select one of 16 micro-programme units MP 0-15. Each of the 256 order selection units has 12 output leads which may be connected by means of a plugboard translation field SF and R to 96 elementary instruction leads IL 1-96. These leads are arranged in twelve groups of 8 and each of the 12 leads for any one order selection unit must be connected to one or other of the 8 leads in the corresponding group of leads IL 1-96. Idle leads in each group are provided. This arrangement facilitates error detection using a detector as disclosed in Specification 1,033,103. Groups 1-4 of the leads IL 1-96 control operations in phase 1, groups 5-9 plus two leads in each of groups 10 and 11 control phase 2 operations and group 12 with the remaining leads in groups 10 and 11 control phase 3 operations. The general arrangement of the digital computer is illustrated in Fig. 1 (not shown) in which the main units comprise a two part store ST1 and ST2, arithmetic unit AU, indexing unit IU, control unit CU and peripheral equipment PE. Orders in a programme store (not shown) are obeyed sequentially according to the setting of a programme counter register PCR. Main programme orders are received in order register OR from where bits 1-8 pass to micro-programme store M-PS for initiating a sequence of micro-instructions as outlined above. Bits 9-48 of the order register contain store addresses (one, two or three) and other data (e.g. iteration counts) in a variety of configurations as detailed in Fig. 2 (not shown), for controlling the functioning of index processor I.P. The micro-programme store is disclosed in Specification 1,105,242 and the main store in Specification 1,063,296. A random data highway system as disclosed in Specification 1,063,296. is used. Details are given of micro programmes for fixed point addition, multiplication, division, and square root determination, and for floating point standardization, addition, subtraction, multiplication and division, together with intructions for controlling the exchange of data over the random data highway and interrupt procedures for testing if peripheral equipment such as tape readers and card punches is busy or calling the computer.