baber/WOPTO huggingface dataset:
Patent JP-H0697369-A (JP)
Title: Layout of power supply wiring
Inventor: YOSHIDA KOICHI
IPC: H01L27/04
Filed: 1992-09-16
Abstract: PURPOSE:To reduce the area for storing layout data by storing power supply wiring layout data in an area for storing master data while splitting into high potential side power supply wiring data and low potential side power supply wiring data. CONSTITUTION:A CAD computor 1 reads out circuit layout data from an area 3 for storing layout data. Upon provision of a data for designating any one of high potential side or low potential side power supply wirings, a common fixed power supply wiring layout data 8 is read out from the circuit layout data. It is then split into independent wiring data for high potential side and low potential side power supply wirings 6, 7. A mask data is then operated based on the circuit layout data at the part of module circuit 5 and the wiring data for the high and low potential side power supply wirings 6, 7, and the mask data thus operated is stored in an area 4 for storing mask data. When the power supply layout data 8 is employed commonly for the power supply wirings 6, 7, data can be stored in the area 3 for storing layout data while being compressed.
Patent JP-S62142195-A (JP)
Inventor: KIYOUICHI EI WATANABE
IPC: A61K31/7052
Filed: 1986-10-16
Abstract: (57)【要約】本公報は電子出願前の出願データであるた め要約のデータは記録されません。
Patent JP-H0297296-A (JP)
Title: Motor controller
Inventor: UEHARA SOKICHI
IPC: H02P27/06
Filed: 1988-09-30
Abstract: PURPOSE:To transmit and receive the data of low-speed and high-speed processing easily by installing a buffer between both principal arithmetic operation by a host microprocessor and high-speed processing arithmetic operation by a high-speed clock and synchronizing data access from the host microprocessor by the high-speed clock. CONSTITUTION:Buffers 4, 5 for data interfaces are mounted between both principal arithmetic operation by a host microprocessor 1 and high-speed processing arithmetic operation operated by a high-speed clock 10. A signal is acquired by synchronizing data access from the processor 1 by the clock 10, thus easily transmitting and receiving data over and from the digital processing system of low-speed and high-speed processing.
Patent JP-S60146809-A (JP)
Title: Alum composition
Inventor: OOHAMA CHIAKI
IPC: A23L3/34
Filed: 1983-12-30
Abstract: PURPOSE:A composition that is obtained by adding copper sulfate to alum, thus showing preserving and deodorizing actions. CONSTITUTION:Alum, preferably potassium alum, ammonia alum or sodium alum, especially burnt alum, is combined with copper sulfate in an amount less than 20wt%. Both components are dissolved in water at a certain ratio to prepare an aqueous solution or the solution is evaporated to dryness into a powder or granules. The resultant composition is used to remove bad smells such as ammonia and is suitably used to treat paper, woven clothes and timbers, because it has flameretarding action.
Patent JP-2000074457-A (JP)
Title: Air conditioner with service power supply
Inventor: WADA MITSUFUMI
IPC: F24F11/02
Filed: 1998-09-01
Abstract: PROBLEM TO BE SOLVED: To enhance incidental functions of an air conditioner. SOLUTION: Indoor unit 10 of an air conditioner is provided with a power supply receptacle 11 and a switch 12 for switching the power supply receptacle 11 between synchronous operation mode being turned on at the time of operating the air conditioner, and a switching operation mode being turned on at the time of stopping the operation. A fan 20 can be operated after expiration of a timer for cooling operation by using the switching operation mode. Furthermore, the power supply receptacle 11 can be used as illumination power supply at the time of repairing the indoor unit 10.
Patent JP-S61125651-A (JP)
Title: Error report processing system
Inventor: SEKI KAZUHISA
IPC: G06F12/16
Filed: 1984-11-21
Abstract: PURPOSE:To reduce the possibility of developing to an error of plural bits by preparing a status where the report about the error is submitted positively in case of a fault related to a hard error, i.e., a fixed fault of an element among the faults of a memory. CONSTITUTION:A transfer circuit 1 receives a report on the generation of a 1-bit error when the transfer is over with the final data. Thus an MPU7 sets the contents of a register 5 to an address register in the circuit 1. The value of the register 5 is equal to the address where the 1-bit error is produced and therefore the MPU7 uses said address to read a memory 3. Then the MPU7 writes the read data (normal data containing no error) to the same address, then reads it again in the same address. When an error occurs at this time, it is decided as a hard error. When the contents of the register 5 are not included in a register file 6, the MPU7 decides said error as the first one and sets a fault end status to the circuit 1 to indicate the end of the data transfer.
Patent JP-H04126407-A (JP)
Title: Automatic control circuit for threshold level
Inventor: FUJITA TAKASHI
IPC: H03K5/08
Filed: 1990-09-17
Abstract: PURPOSE:To regenerate a signal with an accurate duty ratio at all times even when an amplitude of an input signal is changed by generating a threshold level used for the comparison with the input signal from the said input signal. CONSTITUTION:An input signal enters an A/D converter 11, in which the signal is sampled at a prescribed period and converted into an n-bit digital data. The digital data as the n-bit digital data is fed to a maximum value detection section 12A and a minimum value detection section 12B. The maximum value detection section 12A and the minimum value detection section 12B detect respectively a maximum value and a minimum value of the input signal for one period and hold the detected values. The outputs from the maximum value detection section 12A and the minimum value detection section 12B are fed to an adder circuit 12C, its output is fed to a D/A converter 13, in which the output signal is converted into an analog signal. Then an output of the D/A converter 13 is used as a threshold level Vs.
Patent JP-H1178888-A (JP)
Title: Information providing system for transport facility utilization
Inventor: SOTAKE KAZUO
IPC: G06Q50/10
Filed: 1997-09-11
Abstract: PROBLEM TO BE SOLVED: To confirm newest information regarding each transport facility by one information terminal by controlling information for each transport facility by a host control device and storing the newest information in each local information control device. SOLUTION: In each of railway companies 1a and 1b, bits of newest information from a train schedule making system 11, a train running control system 12, a train seat reservation system 13 and a bus schedule system 14 are managed by a host control device 2. The newest information from this host control device 2 is transmitted, by a relay device 4, to the information file 10 of each local information control device 6 installed in a public place such as a station 19 or the like in each of the railway companies 1a and 1b. Thus, by operating an information providing terminal 8 installed in the public place such as the station 19, necessary newest information is retrieved from the information file 10 of each local information control device 6.
Patent JP-2000141517-A (JP)
Title: Laminate, its manufacture and package
Inventor: OGIWARA YOICHI
IPC: B65D30/16
Filed: 1999-09-01
Abstract: PROBLEM TO BE SOLVED: To provide a laminate adapted to a package having sufficient self- support, a self-supporting package and a method for manufacturing such a laminate. SOLUTION: The laminate 10 obtained by laminating polymer films 1, 3 and a reinforcing layer 2 for reinforcing the films 1, 3 comprises a reinforcing area obtained by adhering the layer 2 to the films 1, 3 and a non-reinforced area obtained without adhering the layer 2 to the films 1, 3. It is preferable to use a sheet or a nonwoven fabric having a basis weight of 60 to 200 g/m2 as the layer 2.
Patent JP-H1187745-A (JP)
Title: Insulating substrate for amorphous silicon thin-film solar battery and its manufacture
Inventor: MORI KOJI
IPC: H01L31/04
Filed: 1997-09-11
Abstract: PROBLEM TO BE SOLVED: To manufacture an insulating substrate for amorphous silicon thin-film solar battery having superior flexibility, heat resistance, and electrical insulating property by using an ordinary precoated steel sheet continuously coating facility. SOLUTION: An insulating substrate for amorphous silicon thin-film solar battery is manufactured by forming an electric insulating coating film, composed of a polyether sulfone resin and having a film thickness of 2-40 μm on a base material composed of a metallic sheet or a metallic foil. The electric insulating coating film is formed by applying the polyether sulfone resin to the surface of the base material, composed of the metallic sheet or metal foil and putting the resin together with the surface of the base material, by baking through a heat treatment at a temperature of 250-400 deg.C for 20-120 seconds in duration.
Patent JP-S61126632-A (JP)
Title: Production of magnetic recording medium
Inventor: SAKAI IKUO
IPC: C23C14/56
Filed: 1984-11-22
Abstract: PURPOSE:To obtain an excellent high-density magnetic recording medium a harring good surface characteristic and is not curved by forming an underlying layer haging a specific value or above of magnetic permeability on a supporting substrate and forming a vertical magnetic recording layer on the underlying layer at a specific temp. or above while a specific value or above of tension is kept exerted to the underlying layer. CONSTITUTION:The supporting substrate 2 such as polyester film is fed from an unwind ing roll 1 along a cooling can 3, and while the substrate is taken up on a take-up roll 4, a vertical magnetic recording film is formed by depositing a ferromagnetic metallic alloy such as CoCr alloy on the surface of the substrate 2 on which the under lying layer consisting of 78% Ni 'Permalloy(R)', etc. having >=1,000 magnetic permeabil ity is formed. The vertical magnetic recording layer is formed on the underlying layer at >=90 deg.C temp. under the conduction under which the tension of >=30g/mm<2> effective tension determined by the ratio between the product of the film thickness tp and Young' modulus Ep of the underlying layer and the film thickness ts and Young's modulus Es of the substrate is kept exerted to the underlying layer. The coercive force of the underlying layer is thus maintained at an optimum value and the excellent magnetic recording medium which has the good surface characteristic and small ther mal shrinkage and is not curved is stably manufactured.
Patent JP-H1092974-A (JP)
Title: Enclosure and semiconductor device employing it
Inventor: NEKOTSUKA KATSUYUKI
IPC: H01L25/00
Filed: 1996-09-19
Abstract: PROBLEM TO BE SOLVED: To prevent oscillation by forming a mount pattern in the center of a dielectric substrate and forming a plurality of quadrangular source region ground patterns on the underside and the upper right part of the mount pattern while spacing apart from each other thereby suppressing feedback between the source of FET at respective stages. SOLUTION: A mount pattern 14M for mounting a microwave monolithic IC is formed in the center of a dielectric substrate 12 and quadrangular source region ground patterns 14S are formed on the underside and the upper right part thereof while spacing apart from each other. The source region ground patterns 14S are connected through through holes 17 with the intrinsic ground plane 16 on the rear side in order to impart a ground potential to each source region ground patterns 14S. The mount pattern 14M is also connected through the through holes 17 with the intrinsic ground plane 16 thus bringing about a potentially stabilized state. This structure suppress feedback between the source of FET at respective stages thus preventing oscillation.
Patent JP-H03109323-A (JP)
Title: Anticancer agent
Inventor: TAKEUCHI TOMIO
IPC: A61K31/215
Filed: 1989-09-22
Abstract: PURPOSE:To obtain an anticancer agent, containing methyl 2,5- dihydroxycinnamate or a salt thereof and having high anticancer activity. CONSTITUTION:An anticancer agent, containing a compound expressed by the formula as an active ingredient and having anticancer activity, powerful tyrosine specific protein kinase inhibitory activity and stability in blood serum together. The aforementioned anticancer agent is normally preferably orally or parenterally administered in a dose so as to provide 50-500mg/kg expressed in terms of the compound which is the active ingredient for an adult per day. Furthermore, the compound expressed by the formula is obtained by reacting 2,5-dihydroxybenzaldehyde with methyl(triphenylphosphoranylidene)acetate in an aprotic solvent.
Patent JP-S62108063-A (JP)
Title: Printing control system
Inventor: MAKIGUCHI ATSUSHI
IPC: B41J2/485
Filed: 1985-11-05
Abstract: PURPOSE:To make the column and row conversion printing in a unit of line of the document having different spaces between letters including the underline and the ruled line possible, by possessing a means of drawing a underline under the letter space part and a means of drawing a ruled line to the letter space part. CONSTITUTION:Whether line feed code or not is judged. If no line feed code, whether the ruled line connection bit is on or not, is determined. If the ruled line connection bit of LIB is on, a horizontal ruled line code is set to a letter code. If the ruled line connection bit of LIB is not on, a letter pattern is immediately loaded from ROM and the LIB zone sequence number is loaded. Then, the letter is enlarged to be processed from line modification information such as letter size, rotation, inclined type, letter void, etc. and the zone sequence number. Thereafter, whether vertical ruled line code or not is judged, if no vertical ruled line code, the process is ended. Further, if vertical ruled line code, a vertical ruled line pattern is developed between lines and the process is ended. Furthermore, if it is judged to be a line feed code, a specific value indicating the printable maximum dot number is set at the line feed position of LIB and process of letter development is ended.
Patent JP-H0697043-A (JP)
Title: Reduction projecting aligner
Inventor: OUCHI YASUO
IPC: G03F7/207
Filed: 1992-09-17
Abstract: PURPOSE:To detect and compensate for the error of a reduction ratio without any damage caused to a wafer in a reduction projection aligner. CONSTITUTION:A photoelectric sensor 5 is provided in a position other than a wafer 6 on a wafer stage 3, and length measuring machines 13X, 13Y, 13Z are provided in the position of a stage to determine the error of the reduction ratio. Next, the error is compensated for by moving a drive system 19 in the direction of the optical axis of the wafer stage 3 and a reticle stage 17. Thereby, the reduction ratio of an image may be compensated for without any damage caused to a wafer.
Patent JP-2001076196-A (JP)
Title: Toll collection system, unit for maintenance, on-vehicle unit, and method for maintaining toll collection system
Inventor: NAMIKI MASAHITO
IPC: G07B15/00
Filed: 1999-09-01
Abstract: PROBLEM TO BE SOLVED: To provide a toll collection system, a unit for maintenance, an on- vehicle unit, and a method for maintaining the toll collection system which can reduce the staff for a maintenance test and improve the maintenance test efficiency. SOLUTION: The IC card part 40 of the unit 100 for ETC maintenance is loaded in the card slot part 1A of the on-vehicle unit 1 and an indication for starting a maintenance test of roadside equipment is sent from the unit 100 for ETC maintenance to a lane server 10 by using a function of radio communication with the roadside unit that the on-vehicle unit 1 has. Thus, the maintenance test of the roadside equipment can be started by operating the unit for maintenance connected to the on-vehicle unit, then a service engineer can indicate the start of the maintenance test where the behavior of object equipment to be tested can directly be monitored and then do operation for the maintenance test and monitor the behavior of the equipment alone.
Patent JP-2000082376-A (JP)
Title: Voltage tripping device for circuit breaker
Inventor: KOBAYASHI YOSHIAKI
IPC: H01H73/36
Filed: 1998-09-02
Abstract: PROBLEM TO BE SOLVED: To provide a voltage tripping device which is embodied in a small size and at a low cost and can be assembled easily. SOLUTION: An electromagnet is actuated with a signal voltage to cause a plunger 22 protruding to press a trip bar 16, and after tripping, the current feed to the electromagnet is stopped by a burnout preventive switch 24, and thus a voltage tripping device is constructed, wherein the middle part is borne so that rotatability is secured and there an operating lever 26 is provided, whereby an engage/disengage part 26b at one end is engaged with or disengaged from a movable contacting piece in accordance with the opening/closing motions of an opening/closing mechanism while an engaging finger part 26a at the other end is engaged with the plunger 22 and also a push grip 26c is engaged with an operation button 24a on the switch 24, and further a reset spring 28 is installed to cause the finger part 26a to energize and rotate the plunger 22 in the resetting direction.
Patent JP-H03120054-A (JP)
Title: Charge transfer image forming print cartridge
Inventor: ROBAATO ESU MATSUKARAMU
IPC: B41J2/39
Filed: 1989-09-26
Abstract: PURPOSE: To obtain a cartridge having a flexible basic body for carrying an electrode such that contacts of the cartridge are formed around a rigid unflat spine by inclining the contacts with respect to the discharging part of the cartridge. CONSTITUTION: The part of a board carrying parallel conductors 72 and the first part 80 of a finger electrode is fixed to the inner wall 54 of a spine 52 and the board is positioned correctly to the spine using matching pins. The parallel conductors 72 are then separated from the contact 74 of a drive electrode and the board 68 is bent along two imaginary longitudinal lines 150, 152 separating the first part 80 from the contact 61 of the finger electrode 70 to form three parts inclining each other. The side part of the board carrying the contacts is fixed to the side walls 58, 60 of the spine 52 thus obtaining a cartridge having a flexible basic body carrying the electrode.
Patent JP-S6399376-A (JP)
Inventor: KURUTO DAAMEN
IPC: D06N3/14
Filed: 1987-10-02
Abstract: (57)【要約】本公報は電子出願前の出願データであるた め要約のデータは記録されません。
Patent JP-H07107141-A (JP)
Title: Allowance error number judging circuit
Inventor: TAKADA MASATOSHI
IPC: H04L69/40
Filed: 1993-10-04
Abstract: PURPOSE:To provide a allowance error number judging circuit which can deal easily with input data at a high speed and is easy in a circuit configuration. CONSTITUTION:This circuit is provided with input terminals of error information CP1-CPn having bit information of an error, a cascade structure of allowable error number judging cells of the number (n) of steps corresponding to the number of bits of its error information, and output terminals for designating the number of errors extending from the number of errors 0 to the allowable number of errors in an output in its final stage, for instance, ERR0-ERR2, and the allowable error number judging cell is provided with plural pieces of input/ output terminals for designating the number of errors, bit information of error information of the cell, and logical level information related to the number of errors form the terminal corresponding to the output terminal of the prestage are inputted, and this circuit is provided with a logical gate circuit for outputting the logical level information of a result of decision from the output terminal corresponding to a new number of errors obtained by adding '0' or '1' of the number of errors of an error information input to its stage to the number of errors of the prestage.
Patent JP-H04126941-A (JP)
Title: Air conditioner
Inventor: MAEDA YUKA
IPC: F24F11/02
Filed: 1990-09-18
Abstract: PURPOSE:To get a comfortable sleeping by a method wherein a set temperature is varied in a period after elapsing of a specified time at a going-to-bed to a getting-up time in such a way as a room temperature becomes a set temperature of getting-up time when a getting-up time occurs. CONSTITUTION:A micro-computer 5 acting as a cooling or heating capability calculating means having means for setting or varying a cooling or heating capability is comprised of a timer 6 for calculating a time from a mode changing-over operation, an input circuit 7, a CPU 8, a memory 9 and an output circuit 10. A cooling or heating capability variable device 11 changes the number of revolutions of a compressor 12 in response to an output from the output circuit 10 and then a cooling capability is controlled When a well-sleeping mode is turned on at the time t1, a flow chart stored in the micro-computer 5 starts to operate, the set temperature is changed to a temperature of the going-to-bed time and then a room temperature is controlled to a temperature at the time of going-to-bed by the time t2. As the time t2 comes, a temperature converting range from t2 to t3 is calculated in reference to a time up to the getting-up time t3 and to a temperature difference between the temperature at the time of going-to-bed and the temperature at the getting-up time. Then, the set temperature is gradually varied for every certain time interval in such a way as the temperature becomes the temperature at the getting-up time at the time t3. As the getting-up times t3 comes, the temperature becomes the getting-up time temperature and then a room temperature is controlled at the temperature of the getting-up time until a well-sleeping mode is turned off at the time t4.
Patent JP-H09203303-A (JP)
Title: Facilities built on bedrock covered with soil sediment
Inventor: ENRIKU RAFUAERU SOROOZAANO
IPC: F01K13/00
Filed: 1996-09-20
Abstract: PROBLEM TO BE SOLVED: To provide standard-designed facilities built on a bedrock covered with soil sediment. SOLUTION: All of the main structures of a power generation complex such as nuculear reactor buildings 22, 24, a turbine building, a radioactive waste building, and a control building are arranged on a common mat foundation having elastic bearings or earthquake isolators 18. The mat foundation includes a concrete plate 10a supported on a plurality of pedestals 12. Each pedestal 12 is a cylindrical metallic shell 14 filled up with underwater concrete 16 and is buried into a bedrock. The concrete plate 10a is reinforced by steel bars. The nuclear reactor buildings 22, 24 are supported on a pair of earthquake isolators 18 mounted on the concrete plate 10a. The turbine building is also supported on another pair of earthquake isolators 18 mounted on the concrete plate 10a.
Patent JP-2000076806-A (JP)
Title: Servo circuit
Inventor: WACHI SHIGEAKI
IPC: G11B21/10
Filed: 1998-09-02
Abstract: PROBLEM TO BE SOLVED: To realize a servo operation exhibiting high anti-vibration characteristics against not only for external disturbance having a previously known period but also for external disturbance with a varied frequency or external disturbance having an unknown frequency without involving an increase in size due to a large-size anti-vibration mechanism or an increase in cost due to the use of a complicated actuator. SOLUTION: A servo circuit includes an external disturbance frequency detecting section 5 for detecting an frequency of periodic external disturbance included in a servo error signal SE, one or more selective servo signal generating circuits 4 each having a sift register (S, R) with a length corresponding to a period of the periodic external disturbance and extracting period components of the periodic external disturbance from the servo error signal SE, a phase compensation circuit 6 for suppressing any external disturbance components other than the periodic external disturbance included in the servo error signal SE, and an adder 11 for adding outputs of the selective servo signal generating circuits 4 and an output of the phase compensation circuit 6. An output of this adder 11 is used as a servo control signal to an actuator 13.