Patent GB-1454827-A (GB)
Title: Fault detection process and system for time-division switching network
IPC: H04Q11/04
Filed: 1974-11-19
Abstract: 1454827 Automatic exchange systems INTERNATIONAL STANDARD ELECTRIC CORP 19 Nov 1974 [27 Nov 1973] 50097/74 Heading H4K In a method of testing a time division switching network, partial origin data characteristic of the incoming TDM channel address is inserted into the network together with samples from that channel, and on the output side of the network the incoming TDM channel address is determined from the partial origin data received from the network and compared with a stored incoming TDM channel address, the latter being stored throughout the connection, any difference indicating a fault. As shown the invention is applied to a P.C.M. time space time system including one or more space switching stages 4. Serial P.C.M. samples on highways incoming to 8 are converted to parallel form and entered into a speech store 6 under the control of a clock driven updating device 9 which also supplies the channel address to an addressing device 19. The latter also receives the address of the particular input time switching section 3 involved from a wired logic circuit 28. Speech samples in store 6 read out under control of an address memory 7 (set by the exchange control processor and read out by the exchange clock) are transmitted parallel by bit through the space switch 4, each crosspoint of which has one more contact than the number of bits in a P.C.M. sample. In each time channel one bit of a serial stream comprising a 1, 0 start code and the address of the incoming speech channel is transmitted through its path through the switch via the additional contacts, the bits being modulated at 21 with the parity of the associated speech sample as determined at 20 to produce said origin data characteristic which is transmitted one bit per frame within a superframe. The speech samples and origin data characteristic are received by an output time switch, section 5 operating in similar manner to an input section 3. The parity of each speech code sample is determined at 22 and used assuming that the parity is correct to demodulate the associated origin data bit to recover the start code and incoming address one bit per frame. The bits are compared at 40 with corresponding bits read from a store 24 into which the correct incoming channel addresses have been entered by the exchange control, any difference whether caused by a parity change due to defective transmission through the network or an actual address difference due to defective operation of the switch enters corresponding error bits in a store 44 having one bit per channel and being prevented from being reset until the end of a superframe. The exchange control can determine whether or not for each channel the intermediate storage introduces a one frame delay and enters the incoming channel into the store 24 in the first or second location to compensate. Due to synchronization differences between the exchange and the incoming channels, the updating device 9 introduces irregular one frame delays to compensate. The 1, 0 start code in each superframe allows logic 32 to 35 to determine at the output side of the switch whether such a delay has been introduced. The results for each channel are stored at 31 and used to select at 37 or 38 an appropriate one of two addresses in store 24 for use in the above referred to comparison, these addresses being simultaneously read out and converted to serial form at 26 and 27.