baber/WOPTO huggingface dataset:
Patent JP-S60117371-A (JP)
Title: Automatic cash transaction device
Inventor: KONISHI YOSHIHARU
IPC: G06Q20/18
Filed: 1983-11-30
Abstract: PURPOSE:To realize a device which can answer the request of users to make interest calculation, by designating the interest calculation and calculating period to an automatic cash transaction device and displaying the calculated result by calculating the interest based on the balance and kind of the deposit. CONSTITUTION:When a user desires display of the interest of his deposit and depresses a corresponding ten-key of a key operating section 1, display requesting the user to input a future date until which the interest calculation must be made appears in a guidance display section 2. When the user inputs last two figures of the dominical year and two figures of the month of the date through the ten-key of the key operating section 1, the inputted four figures are displayed and user's confirmation is requested. If the user depresses a ''Confirmation Button'' under this condition, the future date and interest and amount with interest added at the date are displayed in the guidance display section 2. Therefore, an automatic cash transaction device which can calculate and display interests at indicated dates can be realized.
Patent JP-S61102225-A (JP)
Title: Air ejector device
Inventor: OOTAKE HIROSANE
IPC: B29C45/17
Filed: 1984-10-26
Abstract: PURPOSE:To facilitate the controlling of a moving platen by a method wherein the ejection of a molded part is done by the compressed air developed by the mold opening force of a molder. CONSTITUTION:When a mold starts to be open through the leftward shifting of a moving platen 1 after the completion of the injection and cooling processes, air cylinders 2 and 2' are also shifted leftwards, resulting in compressing the airs in the air cylinders 2 and 2'. The compressed airs pass through suction passages 9 and 9' and reach the suction port 13 of an air pressure chamber 8. When the pressure of the airs is raised by the retreatment of the moving platen 1 with the further opening of the mold, a position 11' is pressed against the force of a spring 12, resulting in communicating the suction passages 9 and 9' with an delivery passage in order for the airs compressed by pistons 5 and 5' to pass through exhaust passages 10 and 10' and jet from the front surface of the moving platen so as to remove a molding from the mold.
Patent JP-H0388119-A (JP)
Title: Magnetic recording medium
Inventor: GOTO SHIGETO
IPC: G11B5/66
Filed: 1989-08-30
Abstract: PURPOSE:To prevent sliding noise and head clouding without deteriorating electromagnetic conversion characteristics and still durability by constituting magnetic layers of two layers and incorporating specific binder into the respective magnetic layers. CONSTITUTION:The 1st magnetic layer and 2nd magnetic layer respectively contg. ferromagnetic powders and the binders are provided in this order on a nonmagnetic base. The 1st magnetic layer contains aliphat. polyurethane in the binder. The 2nd magnetic layer contains the arom. polyurethane in the binder. The polyurethane to be incorporated into the 1st magnetic layer and/or the 2nd magnetic layer has preferably a negative functional group. The sliding noise and head clouding are prevented in this way without deteriorating electro magnetic conversion characteristics and the still durability. The excellent electro magnetic conversion characteristics in a high-frequency region are obtd. and the reproduced output is improved.
Patent JP-H0785113-A (JP)
Title: Logic verification method for sequencing circuit
Inventor: EMURA HIDEYUKI
IPC: G06F17/50
Filed: 1993-09-09
Abstract: PURPOSE:To easily execute logic verification accurately. CONSTITUTION:A D flip-flop FF1 is replaced with a combination circuit executing equivalent logic processing to logic processing of an input signal (DT) when a logic level of output signals (OUT1, OUT2) is confirmed by a logic level of the input signal to the D flip-flop FF1 included in a circuit being a logic verification object. In this combination circuit, the data input DT is outputted directly as the 1st output OUT1 and a level of the data input DT is inverted by an inverter IV1 and the inverted level is used for the 2nd output signal OUT2. The logic is verified similarly to that of the combination circuit as to the circuit being the logic verification object after the replacement.
Patent JP-H0665844-A (JP)
Title: Apparatus for inspecting fabric
Inventor: ANDOU ATSUHISA
IPC: D06H3/08
Filed: 1992-08-24
Abstract: PURPOSE:To detect the presence of both a defect and its position in sensing the defect of a woven fabric. CONSTITUTION:A defect of a woven fabric is scanned by reciprocating sensor heads 12 and 13 in the width direction of the woven fabric (W) along a running rail 11 in a housing box 8. Proximity sensors 20 and 21 are arranged near both ends of the running rail 11. An origin signal (G) is outputted to a timer control circuit 40 each time the sensor heads 12 and 13 change the directions. A timer 41 is made to count the elapsed time (DELTAt) from the origin signal (G) to the appearance of a defect signal in the output signal (SG4) of the sensor heads 12 and 13 by the timer control circuit 40. The resultant count value (DELTAt) is then outputted to a positional arithmetic circuit 42. The coordinate values (x) are calculated on the basis of the count value (DELTAt) by the positional arithmetic circuit 42 and a light-emitting diode(LED) corresponding to the defect position on a display panel is lit based on the coordinate values (x) by a display control circuit 43.
Patent JP-H0388754-A (JP)
Title: Cast-in-place lining concrete composition and executing method therefor
Inventor: IWASAKI MASAHIRO
IPC: C04B7/19
Filed: 1989-09-01
Abstract: PURPOSE:To obtain the lining concrete composition which is inexpensive in execution cost and free from separation of material and executes a tunnel excellent in durability by constituting this lining concrete composition which incorporates cement and fine inorganic powder and does not incorporate ballast. CONSTITUTION:Cast-in-place lining concrete composition free from ballast is produced by incorporating cement and inorganic powder (e.g. fly ash, pulverized article of blast-furnace slag) having <=0.15mm particle diameter as a main component and blending an expanding admixture in accordance with necessity. A tunnel is constructed by the cast-in-place lining technique wherein this composition is utilized and mudcup concrete is placed at the same time as drilling of base rock. Thereby ballast is not utilized and therefore separation of material is not caused. Further a miniature force-feed pump can be utilized and miniaturization in an aspect of installation is enabled. Furthermore, release of a frame mold is realized in an early stage by admixing a quick hardening material (e.g. the mixture of calcium aluminate and gypsum).
Patent JP-H1042949-A (JP)
Title: Eyebrow drawing set utilizing eyebrow die
Inventor: KIMURA HIDESHI
IPC: A45D40/30
Filed: 1996-08-08
Abstract: PROBLEM TO BE SOLVED: To allow a beginner to simply and quickly draw beautiful eyebrows uniformly on the right and left regardless of sex and age by setting the eyebrow shapes in vogue on the eyebrows of one's own, and fringing them. SOLUTION: Favorite eyebrow dies 4 are set on inner frames 3, and a main body 1 is hooked and matched to the size of the face of one's own by a screw 10. The portions of eyebrow heads 15 are matched to the same positions of the eyebrow heads of one's own by screws 11, 12. When outer covers 5 are covered on the main body 1, the eyebrow dies 4 pushed by springs 6, 7, 8, 9 are brought into close contact with eyebrows, and the outer peripheries of eyebrow shapes 14 are fringed by a color pen. The main body 1 is removed, and all the eyebrows of one's own protruded from the fringed portions are extracted. A stuck paint is wiped off, the main body 1 is again hooked, the eyebrow shapes 14 are fringed by an eyebrow drawing pen, and the portions are merely traced to complete eyebrow drawing. Eyebrows can be simply drawn when the main body 1 is merely hooked in the next time and thereafter.
Patent JP-S6379097-A (JP)
Inventor: KASAHARA YOSHIYUKI
IPC: G21C19/19
Filed: 1986-09-22
Abstract: (57)【要約】本公報は電子出願前の出願データであるた め要約のデータは記録されません。
Patent JP-S6466903-A (JP)
Title: Semiconductor ceramic having positive resistance temperature characteristic
Inventor: SHIMABARA YUTAKA
IPC: H01C7/02
Filed: 1987-09-07
Abstract: PURPOSE:To increase deflective strength, and to improve breakdown strength by alternately laminating internal electrodes of a first kind, only an electrode for external connection of which is exposed to the outside, and internal electrodes of a second kind having no electrode for external connection and parting the internal electrodes of the first kind on their midways. CONSTITUTION:A positive temperature coefficient thermistor 10 is composed of the laminate 12 of PTC elements 11a-11g having positive resistance temperature characteristics, internal electrodes 13 formed onto the surfaces of the PTC elements 11b-11e on the inside and external electrodes 14 shaped at both ends of the laminate 12. The internal electrodes 13 have internal electrodes 15 of a first kind having electrode sections 15a for external connection connected to the external electrodes 14 and internal electrode sections 16 of a second kind having no electrode section for external connection, and are laminated alternately. Only the electrodes 15a for external connection are exposed to both ends of the laminate 12 in the internal electrodes 15 of the first kind, and residual electrode sections 15b are surrounded by the PTC elements 11, and parted at central sections. The PTC elements are joined mutually not only in the peripheral sections of the internal electrodes 13 but also in parting sections 15c by shaping the parting sections 15c, thus increasing deflective strength.
Patent JP-S59114858-A (JP)
Title: Manufacture of insulated gate type field effect semiconductor integrated circuit device
Inventor: YUASA HIROKAZU
IPC: H01L21/8234
Filed: 1982-12-21
Abstract: PURPOSE:To obtain an integrated circuit element which has no defects and has a large junction capacitance and a small depletion layer width by a method wherein a source and a drain diffused layer are so formed as to contact a buried diffused layer after burying a P type diffused layer and epitaxially growing it. CONSTITUTION:The buried diffused layer 7 is formed on a substrate 1, and then the epitaxial grown layer 8 is formed. Next, insulation oxide films 3 are selectively formed so as to contact the buried diffused layer 7. Further, after forming a gate oxide film 10 and a gate electrode 2, diffused layers 6 are so formed as to contact the buried diffused layer 7. The junction capacitance in the periphery of the source and drain diffused layers 6 can be increased, the volume of the depletion layer region of the junction of the periphery of the source and drain regions 6 can be reduced, and at the same time a channel stopper region can be formed by a method wherein the buried diffused layer 7 of higher impurity concentration than those of the substrate 1 and the epitaxial layer 8 contacts the source and drain regions 6 and the insulation oxide film 3.
Patent JP-H0969459-A (JP)
Title: Manufacture of magnetic recording medium
Inventor: KOBAYASHI ISAO
IPC: G11B5/852
Filed: 1995-09-01
Abstract: PROBLEM TO BE SOLVED: To manufacture a disc-shaped magnetic recording medium having even static magnetism characteristics in the circumferential direction. SOLUTION: Magnets 6a to 6h provided for confining a plasma are arranged in a cathode 3 of a magnetron sputtering device in such a way that the polarities of the magnets are alternately made to differ from each other in the circumferential direction of the cathode 3 and by rotating the magnets with the center part of the cathode 3 as the center of rotation, a magnetic field is generated in the circumferential direction of a target, which is fixed on the cathode 3. When a Co-Sm alloy magnetic layer is formed, a leakage magnetic field due to the magnets 6a to 6h, which are rotated, exerts an effect in the circumferential direction of the surface of a substrate and the axis of easy magnetization (a C-axis) of the magnetic layer subsequent to the formation is directed in the circumferential direction of the substrate.  Thereby, a magnetic recording medium, which has the magnetic layer of even static magnetism characteristics in the circumferential direction, is manufactured.
Patent JP-H0689532-A (JP)
Title: Tape cartridge
Inventor: MIZUTANI HIKARI
IPC: G11B23/087
Filed: 1992-07-30
Abstract: PURPOSE:To provide a tape cartrige advantageous for miniaturizing a tape deck at the tape cartridge provided with a slide frame and a front lid for opening/closing a pocket used for tape loading. CONSTITUTION:A slide frame 10 slided back and forth is provided on the lower surface of a pocket 6. A front lid 11 opened upward and rocked is arranged on the front surface of the slide frame 10. An upper lid 12 is placed on the rear of the upper part of the front lid 11. The upper lid 12 is opened and closed interlockingly with the slide frame 10 and the upper surface of the pocket 6 is opened in an open lid condition. Thus, the upper surface of the pocket is opened at the time of opening the lid and a space is provided on the front part of the pocket so that a rotary magnetic head enters it.
Patent JP-H0273649-A (JP)
Title: Wafer carrier
Inventor: NAKAJIMA NORIHIRO
IPC: H01L21/68
Filed: 1988-09-08
Abstract: PURPOSE:To prevent rust generated by corrosion with metal powder, used acid and alkali by forming a part of a wafer carrier used to manufacture semiconductor in contact with a semiconductor manufacturing apparatus of a plastic material, and composing the other parts of a metal material. CONSTITUTION:A plurality of grooves M for receiving the outer peripheral edge of a wafer are formed in parallel at the inside of the opposite sidewalls of a wafer carrier body 1 of bottomless gate shape, and the ceiling 1 of the body is composed of a metal material such as stainless steel or aluminum. The outer edge of the body to be easily worn in contact when it is charged in a semiconductor device is formed of a plastic material having excellent heat resistance, wear resistance, impact resistance, chemical resistance such as Teflon, and similar plastic material 2' is provided also in the bottom of the gate shape. Thus, the yield of manufacturing a semiconductor element can be improved.
Patent JP-H0653801-A (JP)
Title: Multiplex connection sensor circuit
Inventor: YAMAMOTO TAKESHI
IPC: H03K17/78
Filed: 1992-07-31
Abstract: PURPOSE:To collectively supply power supply voltage from a demodulator side and to receive a detection signal in an easily identifiable state by modulating the pulse time width of a transmission line in each period in accordance with the detection state of each sensor. CONSTITUTION:Gate voltage is outputted from a drive control circuit alternately at the timing of A and B, a P-MOSFET 11 is turned on when the gate voltage is low and power supply voltage is impressed to respective sensors through a transmission line 2. On the other hand, N-MOSFET 12 is turned on when the gate voltage is high to execute a reset function for returning the voltage of the line 2 to 0V by discharging electric charge stored in a transmission line. Only sensors whose addresses coincide with each other out of plural sensors 1a to 1c are alternately driven and the potential of the line 2 is turned to low. When a signal inverted by an inverter circuit 9 is received, the receiving time is judged by identify the detection state of each sensor.
Patent JP-H0273229-A (JP)
Title: Structure of liquid crystal display panel
Inventor: KATAUE SATORU
IPC: G02F1/1339
Filed: 1988-09-08
Abstract: PURPOSE:To surely control thickness and to facilitate a heating and curing operation by using a thermosetting sealing material on an inner side and a UV curable sealing material on an outer side. CONSTITUTION:The thermosetting sealing material 1 and the UV curable sealing material 2 are respectively printed on glass substrates 3, 4. The sealing material 1 is positioned on the inner side of the panel and the sealing material 2 is positioned on the outer side of the panel. Substrates 3, 4 are thereafter pressed to stick welded to each other. This liquid crystal display panel is formed by irradiating the press-welded single bodies with UV rays in the state of maintaining the specified thickness of the liquid crystal display panel. The liquid crystal display panel taken out of a press welding jig is thereafter is stuck by the sealing material 2 while the thickness and position thereof are exactly maintained. The sealing material 1 is cured by heating in the final. Since the heating is executed simply by putting the panel into a heating furnace, the heat is transferred over the entire surface and the sure adhesion is executed.
Patent JP-S6283731-A (JP)
Title: Optical switch
Inventor: KONDO MITSUKAZU
IPC: G02F1/313
Filed: 1985-10-08
Abstract: PURPOSE:To eliminate the dependency on the polarization state of incident light by installing a crystal substrate by placing the optical axis thereof within the plane approximately perpendicular to the light transmission direction of optical waveguides and inclining the same with respect to the direction perpendicular to the surface of the crystal substrate. CONSTITUTION:The optical waveguides 12, 13 formed by thermally diffusing a Ti film pattern to several hundreds - thousands Angstrom thickness and several - several tens mum width on the LiNbO3 substrate 11 to constitute an optical directional coupler 14. The LiNbO3 substrate 11 is so cut out and shaped that the optical axis (z) of the crystal is approximately perpendicular to the light transmission direction (y) of the waveguides 12, 13 and is inclined by theta deg. with respect to the normal z' of the substrate surface. The inclination is enough with 5 deg.<=theta<=85 deg.. A buffer layer consisting of an SiO2 having 1000-3000Angstrom  thickness is coated on the waveguides 12, 13. Control electrodes 15 consisting of Au, Al, etc., are installed thereon. The dependency on the polarization state of the incident light is thereby eliminated and the optical switch which has a low switching voltage and permits easy formation is obtd.
Patent JP-S6469780-A (JP)
Title: Piezoelectric pump
Inventor: KONDO TAKESHI
IPC: F04B9/00
Filed: 1987-09-10
Abstract: PURPOSE:To aim at miniaturization, weight reduction, saving power consumption and dissolution of a radio wave fault by arranging a laminated type piezoelectric element inside a casing, forming two chambers which are vertical to and parallel to the laminated type piezoelectric element respectively and also providing sluice valves among respective chambers. CONSTITUTION:The first chamber 1 parallel to the lamination axis of a rectangular parallelopiped laminated type piezoelectric element 3 and the secondary chamber 2 vertical to the element 3 are respectively formed in a inner space surrounded by an outer wall 5. And respective chambers 1, 2, and the outside space are separated by a plurality of valves 4-1-4-3. For example, when voltage increases, the laminated type piezoelectric element 3 elongates in the direction of the lamination axis so that the volume of the first chamber 1 expands to lower its pressure and the valve 4-1 is opened to allow fluid to flow in from the outside. Meantime, the volume of the secondary chamber 2 reduces to increase its pressure and the valve 4-3 opens to allow the fluid, to flow outside. Thus, the rise and fall of voltage repeats so that the fluid is supplied under pressure form an intake 6 to a discharge port 7.
Patent JP-S6469213-A (JP)
Title: System protective device
Inventor: KOYANAGI KAORU
IPC: H02H3/00
Filed: 1987-09-10
Abstract: PURPOSE:To permit stabilized power supply even upon a peak time in summer, by a method wherein loads are intercepted when a condition that a voltage is reduced to a value lower than a set value and a rate of the voltage reduction to the increase of an ineffective power is higher than a set value is continued for a time longer than a predetermined time. CONSTITUTION:A first condition 1, established when the value of a system voltage V has become lower than a preset value K1, and a second condition 2, established when the rate of increase of the delay ineffective power A of a system load to the reduction of the system voltage V ( Q/ V) has become higher than a preset value K2, are provided. These two conditions are connected to an AND circuit 3 and a load intercepting command is generated when these AND conditions are continued for a time longer than a set time T1 in a timer circuit 4. According to this method, even when a characteristic, in which an ineffective power Q is increased in accordance with the reduction of the voltage, such as upon the peak of demand in summer, is generated, power supply may be effected stably.
Patent JP-S61103899-A (JP)
Title: Peptide for determination of interferon-gamma
Inventor: INOUE TAKESHI
IPC: A61K39/00
Filed: 1984-10-25
Abstract: NEW MATERIAL:The compound of formula (R is H of Tyr-Gly; Thr may be labeled with radioactive iodine). USE:Determination of interferon-gamma free from sugar chain and prepared by a genetic engineering method. PREPARATION:For example, a copolymer of chloromethylated styrene and divinylbenzene is made to react with the cesium salt of a C-terminated amino acid having t-butoxycarbonylated amino group to effect the bonding of the salt to a solid carrier, and the amino-protecting group is removed. The product is made to react with an amino-protected amino acid according to the amino acid sequence of the peptide in the presence of a condensation agent, and the amino-protecting group is removed. The above operation is repeated to synthesize the objective peptide. The compound of formula can be obtained by removing all the protecting groups from the peptide and separating the peptide from the solid carrier.
Patent JP-S6380572-A (JP)
Title: Conductivity modulation vertical mos-fet
Inventor: SEKI YASUKAZU
IPC: H01L27/04
Filed: 1986-09-24
Abstract: PURPOSE:To suppress a latchup phenomenon due to a parasitic thyristor by providing a series resistor through a polysilicon layer and an insulating oxide film over both a source layer and a first conductivity type base layer. CONSTITUTION:A P<+> type layer 5 and a P-type base layer 6 are formed in an N<-> base layer 4, a gate polysilicon layer 9 is formed on an N<-> type gate layer, a resist mask 20 for metal-contacting with the layer 5 is attached to the hole, and As ions are implanted in a self-aligning manner by the mask 20 and the layer 9. Then, when the mask 20 is removed, an N<+> type source layer 8 is formed. Then, a PSG film 10 is formed on the surface, only a part metal-contacted with the layer 5 remains by a photoetching process, a resistor 15 of polysilicon to which an impurity dopant undoped or is suitably added to exhibit an N-type conductivity is added to the surface is formed, and a source electrode 1 is then formed.