Patent GB-1419292-A (GB)
Title: Programmatically onctrolled interrupt system for controlling inputoutput operations in a digital computer
IPC: G06F13/12
Filed: 1973-04-12
Abstract: 1419292 I/O control BURROUGHS CORP 12 April 1973 [28 April 1972] 17939/73 Heading G4A An I/O initiating signal causes at least part of an I/O descriptor to be fetched from memory, and, depending on the value of a bit in the fetched descriptor (part), the same descriptor (part) is repeatedly fetched at predetermined intervals or the transfer of information between an I/O unit and a buffer area in memory specified by the descriptor is initiated. Operation Fig. 1.-When a program requires an I/O operation to be performed, the processor, 10, 12 loads an appropriate descriptor into memory 18 and executes a Write Dispatch operation to load the address of the descriptor into a reserved memory location (00) and to load control and routing information into a Dispatch register of a port interchange unit 16. A dispatch interrupt signal DIL is then sent from unit 16 to the destination I/O control unit to initiate a Dispatch Read and Clear operation in which the IIO address, pointing to the Result Status field of the descriptor, is read from the reserved memory location and the Dispatch register in unit 16 is cleared to allow other Dispatch operations to be initiated. The destination I/O control unit 28, 34, 36 concerned then reads the Result Status field of the descriptor and tests the state of the operation complete bit OC. If the OC bit is 0, the OP code and Begin and End buffer address fields of the descriptor are transferred to the I/O control unit and the specified I/O operation is executed. On completion of the I/O operation, the last address used is entered into the descriptor, a new Result Status field is substituted for the old one in memory and the interrupt bit IR of the old field is tested, if 0, the link address field of the descriptor is read from memory preparatory to accessing the next descriptor in a linked chain, and if 1 (set previously by a processor) the I/O control unit executes a Write Dispatch operation which stores the Result Status at the reserved memory location and causes the interchange unit 16 to send a Dispatch Interrupt DIL to the appropriate processor to initiate entry into an interrupt handler. If, on testing, the OC bit is. found to be 1, the same Result Status field is repeatedly read until the buffer area has become available and the OC bit has been reset. Any I/O control unit 34, 36 may service any peripheral device 38, 40, e.g. a disc file, via an exchange 41 and using a common linked chain of descriptors which may form a loop for indefinite repetition of I/O operations without processor intervention. On testing an OC = 1 bit of a descriptor, an I/O control unit may be controlled to skip to the next linked descriptor rather than waiting for the OC bit to be reset. The port interchange unit 16, Figs. 8, 8A (not shown) includes a priority circuit selecting one of a number of conflicting service requests from ports 20-26, a request decoder and control circuit for selecting idle, read, write or swap (read and write) memory operations and dispatch operations.