Patent GB-940636-A (GB)
Title: Computer system
IPC: G06F15/78
Filed: 1962-04-25
Abstract: 940, 636. Programmed computers. NATIONAL CASH REGISTER CO. April 25, 1962 [May 2, 1961], No.15676/62. Heading G4A. An electronic digital computer comprises means for performing logical operations on data in successive operating cycles, a source of clock pulses coupled to timing means adapted to control the timing in the computer operation cycles, pulse forming means being connected to the timing means for supplying a logical clock pulse to the logical circuit means once in each operating cycle. General arrangement. The computer described comprises a main memory 9 having individual memory units MUO-MU3; an auxiliary memory 13 comprising index registers and other special registers; a programme control system 10; timing control apparatus including a clock source 20 and timing control circuits 22, 24, 26, 28, 30; and an arithmetic unit 11. Each memory unit MUO-MU3 is capable of storing 10, 000 words, each word consisting of 12 bits plus a parity bit and occupying a single storage cell. Information transfer and processing is in parallel form. Each 12-bit word may consist of two 6-bit characters or of three 4-bit binary coded decimal digits. A data item, e.g. a command or an operand, is of variable length and may comprise from one to eight adjoining words. Timing control system. Figs. 2A, 2B. The timing control circuit 22 controls the timing of operations in the computer, and similar timing control circuits 24, 26, 28, 30 are provided for the main memory units MO-M3. The clock source 20 supplies clock pulses C at a rate of 167 kc/sec. The circuit 22 includes an electric delay line 21 whose total delay corresponds to the time interval required for a computer operating cycle. The delay line comprises six sections 44-49 each having a 1Ás delay time and being capable of being tapped at intervals corresponding a time interval of 0.1Ás. Flip-flops G1-G6 are set and reset by pulses supplied from various ones of the delay line taps, these flip-flops producing controlling signals required by the computer. When peripheral equipment is coupled to the computer the clock pulses C are synchronized with the operating rate of the equipment by the use of one of a set of auxiliary oscillators 23a-23z, Fig. 2A. Auxiliary memory cycle. If an operation cycle requires access to the auxiliary memory 13, it is termed an auxiliary memory cycle. For such a cycle, the flip-flop G2 is conditioned during the previous cycle so that at pulse time PO of the auxiliary memory cycle the flip-flop G2 is set thereby producing a waveform G2, Fig. 3 during the cycle. The flip-flop G3 then initiates decoding of the address in the address register A, Fig. 1C, of the auxiliary memory and the flip-flop G4 subsequently causes the contents of the selected location to be read out. The flip-flop G1 produces a signal which is effective at the programme control system 10, Fig. 1 to produce control signals on sense lines of the system. Strobe pulses Qa1, Qa2 (Figs. 2B, 3) are then produced which pass the desired portion of the amplified read-out of the addressed cell in the auxiliary memory 13 to the register S, Fig. 1C. When the above logic has been performed, a "logical clock pulse" CL is produced which sets various flip-flops in accordance with the operations to be performed in the cycle, e.g. addition, subtraction &c. The information, if any, in the S register, is then written back into the same cell of the auxiliary memory from which it was read out, under the control of the flip-flop G6. Main memory operating cycle. This is generally similar to an auxiliary memory cycle, but for a main memory cycle, a flip-flop Fl is set to "false" so that an enabling input is applied to gates 34, 36, 38, 39, Fig. 2A, in the inputs to the main memory control circuits, the particular circuit selected being determined by flip-flops L17-18 of the main memory address register L. Each main memory control circuit contains a delay line and associated flip-flops similar to the arrangement shown in Fig. 2B for the auxiliary memory. The provision of the individual delay line timing units enables the main memory to be used simultaneously by various items of equipment or by additional data processing units. Auxiliary memory. This consists of a magnetic core array having 80 rows each containing 19 cores, 32 rows serving as index registers 15, 32 rows serving as "jump registers" 16, eight rows serving as temporary storage registers 19 and eight rows as an accumulator 17. In the index and jump registers 15, 16, each row stores 18 bits plus a parity bit, whereas in the accumulator 17 each row stores 12 bits plus a parity bit. Each row has an individual read and write drive line and each column has an enable line, so that a selection ratio of 3 to 1 can be obtained. Main memory. This also comprises magnetic core arrays, the selection arrangements being described in Specifications 940, 634 and 940, 635. Programme control system. The programme control system 10, Fig. 1B, comprises matrices 152,153 of magnetic core transformers, the matrix 152 being shown in Fig. 7B. The instruction register 155 comprises flip-flops N7-11 and is set at the beginning of the execution of an instruction. For an instruction requiring twelve or fewer operation cycles for its execution, a single column of the array 152 is selected; otherwise a group of up to four columns may be selected. Divide command 13-, for instance, requires two columns. The order in which operation cycles are selected is controlled by programme counter flip-flops N1-4 via a counter decoder 170. The array 153 is a 4x4 matrix of transformers and is adapted to control subsequent operations according to the type of instruction being executed. When a transformer 150 is switched, during an operation cycle, it produces output pulses on all the sense windings (not shown) threading it, which pulses are effective to control operations in the computer equipment. Instruction structure. The computer employs a modified single address system in which normally only one operand is addressed in a single instruction (called single stage instructions). Some instructions, however, are capable of addressing two operands (double stage instructions). A single stage instruction has the structure: i.e. the instruction consists of two 12-bit words. There are two modes of addressing employed in the computer, "implicit addressing", and "relative addressing". In implicit addressing, word No. 2 contains the actual operand instead of the address of the operand. In relative addressing, word No. 2 contains a 12-bit "relative address" which when combined with an 18-bit base number in one of the index registers 15 provides the 18-bit address of the first memory word of the operand. The RX portion of word No. 1 provides the address of the required index register. The F digits represent the number or words (up to eight) to be handled as a group in a "memory field". The C digits represent the command code. A double stage instruction consists of four words and provides information regarding two operands. Flip-flops and associated circuitry. The various registers in the computer employ bistable transistor flip-flops of the diode-coupled type (Fig.4 not shown). Operation. The setting up of a particular instruction in the instruction register 155 causes the energization of the programme control transformers in a predetermined sequence to perform appropriate operating cycle to execute the instruction. The first two operation cycles XX-00-0 and XX-01-0 (see Fig. 10) are controlled by transformers in the array 153 and are common to all commands. The function of the cycle XX-00-0 is to permit the "control number", i.e. the address of the first word in the instruction in the main memory which is to be addressed, to be looked up in the control number register (one of the index registers 15) and set up in the L register, Fig. 1A. Specification 925, 392 also is referred to.