Patent GB-976474-A (GB)
Title: Improvements in or relating to electrical digital data stores
IPC: H04Q3/54
Filed: 1962-07-24
Abstract: 976, 474. Permanent data stores. GENERAL ELECTRIC CO. Ltd., J. M. FALCONER, D. M. LEAKEY, and E. V. NEWBERY. April 19, 1963 [July 24, 1962], No. 28421/62. Heading G4A. [Also in Divisions H1, H3 and H4] A permanent data store for information relative to 1500 telephone subscribers comprises an array of magnetic elements disposed in pairs 3, 4 (Fig. 3) at the intersections of row and column wires 1, 2. The gap between the arms of a pair is such that in the absence of screening a pulse in one wire will induce one in the other but that if an electrically conductive sheet is interposed in the gap no output pulse will effectively result. The store is shown in Fig. 5 and comprises fifteen blocks B00-B14 of data elements, each block storing 10 data words of 36 bits on each of 10 planes 21 which each extend through three blocks. Each plane is constructed from printed circuit boards 22, 23 (Figs. 8, 11) clamped together with spacers 25, 26 to provide thirty apertures 52, between the U- shaped elements 24, into which metallic strips can be inserted. Each strip has 36 positions in which a hole can be punched to remove the screening between the elements 24 (and hence store binary 1). The strip can be marked for visual identification of the subscriber on its protruding end. Readout is by pulsing a selected column wire in a selected block; these column wires extend in series across all planes in that block, so that 10 words are read out, one from each plane. The 36 output wires in each plane are connected in series respectively with the wires of the corresponding planes in all other blocks so that there is a total of 10 x 36 output leads, the signals on the 36 leads from the desired plane being gated out by a further selector. Avoidance of errors at various stages of selection is obtained by triplication of circuits and the use of majority gates (i.e. 2 out of 3) receiving the three (normally identical) signals. In Fig. 5 the block selection is by gates 87, column selection by gates 97, and plane selection by gates 110 (36 gates 110 being opened by a single pulse on line 111, and triplication of gates 110 being provided for each output line). Figs. 14-19 show transistor and diode amplifying and gating circuits. Fig. 14 receives square-wave signals from a triggered flip-flop 68 and acts as a tuned push-pull amplifier with parallel and series tuned circuits 71, 72. Fig. 15 shows a gated push-pull amplifier, shown schematically at 75 in Fig. 5, in which when 82 is non-conductive the potential applied by Zener diode 80 to diodes 83 is such as to make 83 and 84 conduct to cut off transistors 79; when a pulse is applied at 77 to make 82 conduct this potential rises to allow the transistors to conduct. Fig. 16 shows a gate (87 in Fig. 5) in which either diodes 91 or 92 are conductive (passing, or shorting out, the applied signal) according as 95 is conducting or not. Figs. 17 and 18 show similar gates but employing no "shorting" diodes corresponding to 92 of Fig. 16 (used at 97 and 110 of Fig. 5), and Fig. 19 shows an amplifier of cascaded transistor stages 124, 125 followed by D.C. coupled stages 126, 127.