Patent GB-1188370-A (GB)
Title: Improvements in or relating to Information Storage Arrangements
Inventor: BOBECK ANDREW HENRY
IPC: G11C11/14
Filed: 1967-09-13
Abstract: 1,188,370. Magnetic storage arrangements. WESTERN ELECTRIC CO. Inc. 13 Sept., 1967 [16 Sept., 1966 (2)], No. 41786/67. Heading H3B. A storage matrix comprises a continuous sheet 11, Fig. 1, of magnetic material, e.g. yttrium orthoferrite, which is substantially isotropic in the plane of the sheet and has a preferred magnetization direction normal to this plane, discrete bit storage locations BL11-BLNM being defined by orthogonal X and Y conductors each formed with loops, a previously-established single wall domain in each bit location being moved from one position under a loop to a position under an immediately adjacent loop when the latter loop is energized. Fig. 1 shows a random access storage matrix with a " zero " stored in each bit location, the sheet being magnetized throughout in the same sense as indicated by minus signs except at positions adjacent the loops of row conductors X1A-XNA where plus single wall domains are established. To record a " one " in a bit location, a row conductor XlB-XNB is pulsed so that all the single wall domains in the selected row are moved to the loops of the pulsed conductor. A selected column conductor Y1A-YMA is next pulsed so as to transfer the single wall domain in the selected bit location from the position under the loop of a row conductor X1B-XNB to the position under the loop of the pulsed column conductor. Finally the single wall domain in the selected bit storage location is moved to a " one " storage position by pulsing a looped conductor Y1B-YMB. The displaced single wall domains in the other bit locations in the row selected are restored to the binary zero state by pulsing a looped conductor X1A-XNA when the' storage operation is completed. To read out, from a selected bit storage location, a selected column conductor Y1A-YMA is pulsed, followed by pulsing a selected row conductor X1B-XNB, this having the effect of moving a single wall domain in the " one " storage position back towards the zero storage position by two steps and so enabling an output to be induced in a looped sense conductor S. The displaced single wall domain is now in a position immediately adjacent the " zero " storage position, and can be restored to the " one " position by pulsing the associated column conductors Y1A-YMA and Y1B-YMB in turn. In the other hand, by pulsing a conductor X1A-XNA the displaced single wall domain may be moved into the " zero " position. A linear select storage matrix is shown in Fig. 8 in which only one intermediate single wall domain position is provided by omitting one Y conductor of each pair. A domain is transferred from the " zero " position shown to the " one " storage position by selectively pulsing the X and Y conductors as previously described for Fig. 1. A word is read out by selectively pulsing a conductor X1B, X2B so that voltages are induced in the column conductors Y1A-Y4A associated with bit locations storing a binary " one ", the sensed outputs passing over conductors S1-S4 to a utilization circuit 114. Restoration of read-out " one " states is effected by pulsing the column conductors. Non-destructive read-out is provided in the arrangement shown in Fig. 9, additional row conductors X1C, X2C being energized selectively and causing a temporary change in dimensions of each single wall domain associated with the energized conductor. This induces output voltages in the column conductors Y1-Y4 which pass to a utilization circuit 14.