Patent SG-11201810613U-A (SG)
Title: Secured chip
Inventor: DEKKER GERARD JOHAN
IPC: H01L23/00
Filed: 2017-06-02
Abstract: 208 296 298 06 258 1-1 GC N O N O 1-1 C (12) INTERNATIONAL APPLICATION PUBLISHED UNDER THE PATENT COOPERATION TREATY (PCT) (19) World Intellectual Property Organization International Bureau (43) International Publication Date 07 December 2017 (07.12.2017) WIP0 I PCT ill~~~~~~~~ 011101010VIII010um o oitimmuoillowom oimIE (10) International Publication Number WO 2017/207806 Al (51) International Patent Classification: H01L 23/00 (2006.01) HO1L 23/544 (2006.01) H01L 25/065 (2006.01) (21) International Application Number: PCT/EP2017/063575 (22) International Filing Date: 02 June 2017 (02.06.2017) (25) Filing Language: English (26) Publication Language: English (30) Priority Data: 1609781.8 03 June 2016 (03.06.2016) GB (71) Applicant: IRDETO B.V. [NL/NL]; Taurus Avenue 105, LS 2132 Hoofddorp (NL). (72) Inventor: DEKKER, Gerard Johan; Taurus Avenue 105, 2132 Hoofddorp (NL). (74) Agent: BOULT WADE TENNANT et al.; Verulam Gar- dens, 70 Gray's Inn Road, London Greater London WC1X 8BT (GB). (81) Designated States (unless otherwise indicated, for every kind of national protection available): AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DJ, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JP, KE, KG, KH, KN, KP, KR, KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW. (84) Designated States (unless otherwise indicated, for every kind of regional protection available): ARIPO (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW), Eurasian (AM, AZ, BY, KG, KZ, RU, TJ, TM), European (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR), OAPI (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG). Declarations under Rule 4.17: — of inventorship (Rule 4.17(iv)) Published: with international search report (Art. 21(3)) before the expiration of the time limit for amending the claims and to be republished in the event of receipt of amendments (Rule 48.2(h)) (54) Title: SECURED CHIP Figure 2B (57) : A method of individualizing a semiconductor chip of a batch of semiconductor chips with respective individualization data of the semiconductor chip, the method comprising, applying a plurality of circuit layouts to the semiconductor chip to form a plurality of circuits on the semiconductor chip, wherein for each circuit layout, said circuit layout is arranged such that, (a) the corresponding circuit, when triggered, falls into any one of two or more respective triggered states, and (b) one of the two or more respective triggered states is a respective preferred state defined by said circuit layout, wherein the plurality of respective preferred states of the circuits in the plurality of circuits encode the individualization data, and wherein each individualized semiconductor chip of the batch of semiconductor chips comprises a generic circuit.