Patent GB-952997-A (GB)
Title: Data storage system
IPC: G11C19/28
Filed: 1960-07-25
Abstract: 952,997. Electric digital-data-storage apparatus. WESTINGHOUSE AIR BRAKE CO. July 25, 1960 [July 24,1959; July 31, 1959], No. 25838/60. Heading G4C. A data storage system comprises a plurality of storage means for storing data, input means for feeding data to the first of the storage means, transfer means for transferring data sequentially through the storage means for storage in the last vacant storage means, and control means actuated by a storage means having data stored therein for inhibiting the transfer of further data to that storage means. As described, an n-bit binary data word is entered in storage bank C of an array, the data then shifting automatically to successive storage banks until it reaches the last vacant storage bank. The word stored in the final storage bank, bank A, may be read out in serial form to a utilisation circuit. Each storage element of the array, such as 1A, 1B comprises a bi-stable transistor pair circuit (Fig. 3, not shown). Initially the elements such as 1A, 1B of the array are in a first condition and associated transfer circuits C1, R1 which also comprise a pair of transistors are in a second condition. An input negative pulse, representing a binary "1" , on one of the lines O-R switches the element 1A, 1B to its second condition thereby switching the transfer circuit C1,R1 to its first condition. An output from the transistor C1 then reverses the element 2A, 2B, a connection 162 preventing the next transfer circuit C2, R2 from being actuated. An output from the transistor 2B over a line 155 now shifts a control circuit 81 comprising transistors D1, D2 from its first to its second state after a time delay determined by a capacitor 142, the delay being provided to ensure that all the data has been transferred from storage bank C to storage bank B. The output from D2 now changes the transfer circuit C 1, R1 back to the second condition, an output pulse thereby produced at a capacitor 146 being applied to reset the element 1A, 1B to its first state. The second state output from the transistor 2A of the element 2A, 2B switches the transfer circuits C2, R2 to its first condition, and the data is transferred as described above, from row to row until it reaches storage bank A, each row being reset to zero after the data has been transferred from it. If a second input negative pulse, representing a binary "1" is now applied to the transistor 1A, it is transferred as before to the storage bank B, but since a "1" is stored in . the element 3A, 3B, the control circuit 83 is maintained in its second state so that its output, over a line 167 maintains the transfer circuit C2,R2 in its normal second state, thereby preventing any further transfer. The data in storage bank A may be read out in serial form by means of a rotary switch 172 adapted to scan the elements 3A, 3B &c. of the bank A sequentially. The elements in the storage bank A may now be reset to zero by application of a momentary negative voltage from a circuit 174. When the bank A has been cleared, the data in the preceding banks steps forward as described above. Specification 952,996 is referred to.