Patent GB-1187717-A (GB)
Title: Improvements in or relating to Time Division Multiplex Data Transmission Systems
IPC: H04L5/22
Filed: 1968-07-25
Abstract: 1,187,717. Digital transmission systems. SIEMENS A.G. 25 July, 1968 [25 July, 19671, No. 35515/68. Heading H4P. In a digital t.d.m. system including a programmed exchange each change in message bit state transmitted by the exchange is accompanied by a signal indicating the difference ds (here called the delay time) between the time t 3  of arrival of the change at the input of the multiplexer and the time t 4  of transmission of the change over the relevant one of the multiplexed channels. From a t.d.m. signal received by the exchange the theoretical time t 2  of a change in bit state can be determined since a signal indicating the delay time de is also received and the time t 1  of reception of the change on the multiplex channel is known. As described a t.d.m. signal is received on L1 and the time t 2  calculated. This information passes to an exchange ZSt which processes the information without reference to the t.d.m. timing and passes the processed information to a multiplexer which transmits bit changes together with the appropriate delay time signals ds over t.d.m. channel L2. The system described employs a 4-channel transparent t.d.m. cycle, the channels having speed ratios 1: 1: 2: 4. Each cycle is divided into 8 time slots, each slot containing one bit. Each of the 4 channels carries 5-bit words, each word consisting of a start bit, a 3-bit signal representing the delay time and a bit P indicating the change in message bit-state. At the t.d.m. receiver the channels are connected to four 5-bit shift registers in SPU. A timing signal passes to units Z Reg and Reg, the latter controlling unit UCE(I) which generates signals KNe stepping the shift registers at the appropriate instants in each t.d.m. cycle, so that the registers contain demultiplexed data. Each stepping pulse KNe also passes to unit UCE(II) which develops a signal # representative of the scanning rate of the channel to which the stepping pulse is relevant, signal # being passed to unit AdE. Unit AdE also receives the 3-bit delay time signal de and a signal from unit Z Reg indicating the time t 1 , and produces a signal indicating the time t 2 . The stepping pulses KNe are also fed via unit KNC and combined with a signal BNe, identifying the t.d.m. channel L1, to give a signal LNe. The signals LNe, t 2 , and P pass to a store ESP in the exchange which processes them as required. The multiplexer is fed from store ZP which supplies a signal LNs from which is derived a signal KNs indicating on which of the channels in t.d.m. channel L2 a bit P representing a change in message bit-state is to be sent. This bit is placed in the appropriate one of four shift registers in PSU. The signal KNs feeds unit UCS(I) which develops a signal #+#s, # representing the scanning rate of the relevant channel and #s the phase position of the channel in the t.d.m. cycle. Unit Z Reg gives the signal t 3 , which is measured relative to the start of the t.d.m. cycle. Unit AdS receives both t 3  and #+#s and from it develops the delay time ds. Unit Z Reg also gives a timing signal # to UCS(II) which delivers stepping pulses to the registers at the appropriate times so that a t.d.m. signal appears on L2.