Patent GB-1169724-A (GB)
Title: Data Processing Apparatus
IPC: G06F12/10
Filed: 1966-11-28
Abstract: 1,169,724. Multiprogramming; relative addressing. GENERAL ELECTRIC CO. 28 Nov., 1966 [26 Nov., 1965], No. 53196/66. Heading G4A. In a data processing system in which a signal generator provides signals representing the address of a first cell relative to a reference cell, a second cell contains the address of the reference cell and a register contains an indication of the location of the second cell, the register contents are used to access the second cell the contents of which are combined with address represented by said signals to generate the absolute address of the first cell. The address in the register may itself be produced by a relative addressing procedure. The invention is applied to a multi programmed shared-access computer in which a supervisor programme ensures that only those programmes or programme parts which are currently active are stored in the main computer memory at any one time, the particular location in memory to which programme segments are written being determined by said supervisor programme according to current availability of space. To facilitate this flexibility, all addresses are relative addresses relative to the base address of a specific programme segment. The main computer memory (Fig. 2, not shown) which comprises 10<SP>24</SP> word cells of 36-bits each is divided into pages of 1024 cells each. A programme segment may comprise up to 256 pages which may be called in from a backing store as a single block (non-paged segments) or page-by-page (paged segments). Instructions, comprise an 18-bit relative address portion which may be interpreted as an 8-bit page number with a 10-bit word number or (in the the case of non-paged segments) as an 18-bit word number and an 18-bit command portion. In addition to the supervisor programme and the current programme pages and segments, the memory includes a Descriptor Segment (DS) and a plurality of Page Table Segments. The Descriptor Segment contains the base addresses (Segment Descriptor Words or SDW) of all current non-paged segments and of all Page Table Segments corresponding to paged segments. The Page Table Segments contain the base addresses of all current pages (Page Table Words or PTW). In a later processing system as shown in Fig. 1, a Descriptor Segment Base Register (DSBR) 64 stores the base address of the D.S. and a Procedure Base Register (PBR) 61 stores the relative address (or pointer) of that SDW corresponding to programme segment currently being executed. Instructions which are normally selected by an instruction counter (IC) 43, are read from computer memory into register 41 and 40, the relative address portion going to the Y-Register 41, and the command portion to the command Register 40. If the address is internal to the segment currently being executed (bit 29 = 0) then the contents of PBR are transferred to Temporary Base Register (TBR) 60 the contents of TBR and DSBR are combined in Adder and Logic Unit 46, the resulting absolute address of the relevant SDW is transferred to Address Register ADR 58 and this SDW is then accessed from memory and stored in Descriptor Register (DES) 66. If the current segment is unpaged (as indicated by a control portion of the SDW) then the required absolute cell address is generated merely by adding the contents of Y-Register 41 (word relative address) to the contents of DES Register 66 (Segment Base Address). If the current segment is paged then the Page Table Segement base address in DES Register 66 must be combined with the page number in Y-Register 41 to generate the address of the relevant PTW the contents of which, after being retrieved from memory M must be added to the word number in Y-Register 41 to produce the required absolute cell address. If the address in Y-Register 41 is external to the current segment (bit 29 = 1) then the relevant pointer must be obtained from an Address Base Register 62 as specified by bits 0-2 of the instruction and transferred to the TBR (60), after which the procedure continues as before. The ABR's 62 may alternatively contain modified bits for modifying the address in Y-Register 41 in which case bits 18-20 thereof specify a further ABR in which the required pointer may be found. Bit 21 of each ABR indicates whether the contents thereof are modifier bits or pointer bits. An associative memory (AM) 65 may be provided in which are stored the most recently used SDW's together with their pointers and page numbers (if paged). This memory is searched before the above proceedures are initiated. By this means, the required Segment Base Address of a restricted number of segments may be obtained more quickly than by the above procedure. The Descriptor Segment may itself be paged, in which case a further step is added to the above procedures.