Patent GB-1319534-A (GB)
Title: Data signal receiver
IPC: H03K5/01
Filed: 1970-06-23
Abstract: 1319534 Data transmission systems; transistor switching and delay circuits WESTERN ELECTRIC CO Inc 23 June 1970 [26 June 1969] 30338/70 Headings H3T and H4P Binary data frequenoy shift signals use two outer frequencies of a transmission band and a supervisory on-hook signal uses a centre frequency, the receiver ignoring the necessary transition through the centre frequency as the data changes binary state and recognizing an on-hook condition by a persistent uninterrupted reception of the centre frequency for a predetermined time. In Figs. 1 and 2 incoming frequency signals are demodulated and produce a D.C. signal on lead 108 which is analysed by centre frequency detector 111 to give a positive output if the D.C. signal occurs in a middle range corresponding to the centre frequency on-hook signal and a negative output if the D.C. signal is outside this range corresponding to either of the binary data states. A data slicer 112 provides a square-wave signal which changes state upon each transition of the D.C. signal through its centre range to in effect provide an equivalent data signal plus noise transitions. After a short delay (114) the data signal passes through clamping circuit 204, albeit inverted, to set data output driver either positive or negative. When the sending station goes initially off-hook the centre frequency signal is removed, line 109 assumes negative which is timed by circuit 203. After a predetermined time of off-hook condition lead 209 goes negative to set supervisory output driver 205 to a positive off-hook condition. This output signal is fed via lead 210 to reset the timing circuit 203 and remove the clamping of circuit 204 which had previously been holding the data output driver 206 in a mark binary data condition. The timing circuit also applies positive potential to lead 208 whenever the input on lead 209 assumes a positive condition on each transition through the centre frequency, which prevents a change of the data output from a mark to a space. Because of the delay this latter inhibition by the clamping circuit is of no consequence for a normal noise free data signal, but tends to remove noise, and when the sending station finally goes back onhook clamps the output in a mark condition and prevents any misinterpretation of transient onhook signals as binary data signals. Details of transistor circuits.-Frequency shift signals consisting of three frequencies on input 109 are converted to a D.C. signal on lead 108, having an upper positive value, a lower negative value and an intermediate value corresponding to the three frequencies. A detector 111 produces a positive signal on lead 109 in response to a middle range D.C. value and a negative one in response to the upper and lower values. In detector 111, Q4 and Q5 bias Q3 and Q6 to set the upper and lower thresholds. An upper positive value on lead 108 turns on Q3 and Q6, with Q3 holding output line 109 at a relatively negative value. A lower positive value on lead 108 turns off both Q3 and Q6 and lead 109 is held negative through Q5. A middle range D.C. value only turns on Q6 which turns off Q5 permitting the line 109 to rise to a positive value. In a timing circuit 203, Q9 is turned off by a negative signal on 109, indicating an off-hook condition at the transmitting station, and capacitor C2 charges positively. After 15 ms. Q10 turns on and Q12 turns off permitting positive voltage to reach C2 and Q19 which turns off. The application of negative potential to lead 209 turns off Q20 which turns on Q21 and turns off Q22 so giving a positive off-hook signal at terminal 202. The feedback of this signal on lead 210 turns on Q11 which applies ground to Q10 terminating the charging of C1 and puts ground on lead 208. When the sending station goes back on-hook the negative signal on lead 109 to the timing circuit turns on Q9 with Q10 and Q12 turning off in turn. Capacitor C2 discharges and after 15 ms. turns on Q19 and reapplies ground to lead 209. The output driver now reverts to place negative on output 202. The fed back signal turns off Q11 to enable C1 to be ready to time the next off-hook signal. The D.C. signal on lead 208 is sliced (112) to generate a square-wave voltage, corresponding to the transitions in the D.C. signal, which is delayed before reaching a clamping circuit 204. When the sending station is on-hook the lead 210 has a negative potential which maintains Q15 off. Lead 208 is positive maintaining Q13 off so Q14 cannot turn on regardless of the input to the clamping circuit and lead 211 is maintained in a negative marking condition. During signalling lead 210 assumes positive potential and 208 is at ground so that positive and negative signals on lead 115 pass through inverted to the output driver 206. Upon each change from mark to space and space to mark the D.C. voltage at 108 passes through to centre range and lead 109 momentarily assumes positive potential, causing lead 208 to go positive, because of the delay (114) the data signals input to the clamp are unaffected. However when the station finally goes on-hook, but before C2 has timed out, the D.C. signal will fluctuate about its mean level, so creating a square-wave from slicer 112 which could be interpreted as data signals. A negative mark signal to the clamping circuit turns off Q14 which in turn turns off Q15. The positive potential on 208 now turns off Q13 which maintains Q14 off. The output is then held in a mark condition irrespective of changes to its input.