The System-On-a-Chip (SoC) does not properly isolate shared resources between trusted and untrusted agents.

A System-On-a-Chip (SoC) has a lot of functionality, but it may have a limited number of pins or pads. A pin can only perform one function at a time. However, it can be configured to perform multiple different functions. This technique is called pin multiplexing. Similarly, several resources on the chip may be shared to multiplex and support different features or functions. When such resources are shared between trusted and untrusted agents, untrusted agents may be able to access the assets intended to be accessed only by the trusted agents.

Primary

Architecture and Design

Implementation

Access Control
Bypass Protection Mechanism
If resources being used by a trusted user are shared with an untrusted user, the untrusted user may be able to modify the functionality of the shared resource of the trusted user.

Integrity
Quality Degradation
The functionality of the shared resource may be intentionally degraded.

Automated Dynamic Analysis

Pre-silicon / post-silicon: Test access to shared systems resources (memory ranges, control registers, etc.) from untrusted software to verify that the assets are not incorrectly exposed to untrusted agents. Note that access to shared resources can be dynamically allowed or revoked based on system flows. Security testing should cover such dynamic shared resource allocation and access control modification flows.

High

Architecture and Design
Separation of Privilege

When sharing resources, avoid mixing agents of varying trust levels.
Untrusted agents should not share resources with trusted agents.

Consider the following SoC
design. The Hardware Root of Trust (HRoT) local SRAM is memory mapped in the core{0-N}
address space. The HRoT allows or disallows access to private memory ranges, thus
allowing the sram to function as a mailbox for communication between untrusted and
trusted HRoT partitions.

We assume that the threat is from malicious software in
the untrusted domain. We assume this software has access
to the core{0-N} memory map and can be running at any
privilege level on the untrusted cores. The capability
of this threat in this example is communication to and
from the mailbox region of SRAM modulated by the
hrot_iface. To address this threat, information must not
enter or exit the shared region of SRAM through
hrot_iface when in secure or privileged mode.

CVE-2020-8698
Processor has improper isolation of shared resources allowing for information disclosure.
https://www.cve.org/CVERecord?id=CVE-2020-8698

CVE-2019-6260
Baseboard Management Controller (BMC) device implements Advanced High-performance Bus (AHB) bridges that do not require authentication for arbitrary read and write access to the BMC's physical address space from the host, and possibly the network [REF-1138].
https://www.cve.org/CVERecord?id=CVE-2019-6260

Allowed
This CWE entry is at the Base level of abstraction, which is a preferred level of abstraction for mapping to the root causes of vulnerabilities.
Carefully read both the name and description to ensure that this mapping is an appropriate fit. Do not try to 'force' a mapping to a lower-level Base/Variant simply to comply with this preferred level of abstraction.

Arun Kanuparthi, Hareesh Khattri, Parbati Kumar Manna, Narasimha Kumar V Mangipudi
Intel Corporation
2019-10-15
4.0
2020-02-24

CWE Content Team
MITRE
2020-08-20
updated Common_Consequences, Description, Name, Potential_Mitigations, Related_Attack_Patterns, Relationships

CWE Content Team
MITRE
2020-12-10
updated Relationships

CWE Content Team
MITRE
2021-07-20
updated Demonstrative_Examples

CWE Content Team
MITRE
2021-10-28
updated Description, Observed_Examples, References, Relationships, Weakness_Ordinalities

CWE Content Team
MITRE
2022-10-13
updated Detection_Factors

CWE Content Team
MITRE
2023-04-27
updated Observed_Examples, Relationships

CWE Content Team
MITRE
2023-06-29
updated Mapping_Notes, Relationships

CWE Content Team
MITRE
2025-04-03
4.17
2025-04-03
updated Demonstrative_Examples

CWE Content Team
MITRE
2025-09-09
4.18
2025-09-09
updated Relationships

Cycuity (originally submitted as Tortuga Logic)
2021-07-16
Provided Demonstrative Example for Hardware Root of Trust.

Hareesh Khattri
Intel Corporation
2021-10-22
provided observed example

Hareesh Khattri
Intel Corporation
2022-04-18
changed detection method

Improper Isolation of Shared Resources on System-on-Chip (SoC)