The product uses a fabric bridge for transactions between two Intellectual Property (IP) blocks, but the bridge does not properly perform the expected privilege, identity, or other access control checks between those IP blocks.

In hardware designs, different IP blocks are connected through interconnect-bus fabrics (e.g. AHB and OCP). Within a System on Chip (SoC), the IP block subsystems could be using different bus protocols. In such a case, the IP blocks are then linked to the central bus (and to other IP blocks) through a fabric bridge. Bridges are used as bus-interconnect-routing modules that link different protocols or separate, different segments of the overall SoC interconnect.
For overall system security, it is important that the access-control privileges associated with any fabric transaction are consistently maintained and applied, even when they are routed or translated by a fabric bridge. A bridge that is connected to a fabric without security features forwards transactions to the slave without checking the privilege level of the master and results in a weakness in SoC access-control security. The same weakness occurs if a bridge does not check the hardware identity of the transaction received from the slave interface of the bridge.

Primary

Architecture and Design

Implementation

Confidentiality
Integrity
Access Control
Availability
DoS: Crash, Exit, or Restart
Bypass Protection Mechanism
Read Memory
Modify Memory
Medium

Simulation / Emulation
RTL simulation to ensure that bridge-access controls are implemented properly.
High

Formal Verification
Formal verification of bridge RTL to ensure that access control cannot be bypassed.
High

Architecture and Design
Ensure that the design includes provisions for access-control checks in the bridge for both upstream and downstream transactions.

Implementation
Implement access-control checks in the bridge for both upstream and downstream transactions.

This example is from CVE-2019-6260 [REF-1138]. The iLPC2AHB bridge connects a CPU (with multiple, privilege levels, such as user, super user, debug, etc.) over AHB interface to an LPC bus. Several peripherals are connected to the LPC bus. The bridge is expected to check the privilege level of the transactions initiated in the core before forwarding them to the peripherals on the LPC bus.
The bridge does not implement the checks and allows reads and writes from all privilege levels.
To address this, designers should implement hardware-based checks that are either hardcoded to block untrusted agents from accessing secure peripherals or implement firmware flows that configure the bridge to block untrusted agents from making arbitrary reads or writes.

The example code below is taken from the AES and core local interrupt (CLINT) peripherals of the HACK@DAC'21 buggy OpenPiton SoC. The access to all the peripherals for a given privilege level of the processor is controlled by an access control module in the SoC. This ensures that malicious users with insufficient privileges do not get access to sensitive data, such as the AES keys used by the operating system to encrypt and decrypt information. The security of the entire system will be compromised if the access controls are incorrectly enforced. The access controls are enforced through the interconnect-bus fabrics, where access requests with insufficient access control permissions will be rejected.

...
module aes0_wrapper #(...)(...);
...

input logic acct_ctrl_i;

...

axi_lite_interface #(...
) axi_lite_interface_i (
...

.en_o ( en_acct ),

...
..);

assign en = en_acct && acct_ctrl_i;

...
endmodule
...
module clint #(...)(...);
...

axi_lite_interface #(...
) axi_lite_interface_i (
...

.en_o ( en ),

...
);
...
endmodule

The previous code snippet [REF-1382] illustrates an instance of a vulnerable implementation of access control for the CLINT peripheral (see module clint). It also shows a correct implementation of access control for the AES peripheral (see module aes0_wrapper) [REF-1381]. An enable signal (en_o) from the fabric's AXI interface (present in both modules) is used to determine if an access request is made to the peripheral. In the case of the AES peripheral, this en_o signal is first received in a temporary signal en_acct. Then, the access request is enabled (by asserting the en signal) only if the request has sufficient access permissions (i.e., acct_ctrl_i signal should be enabled). However, in the case of the CLINT peripheral, the enable signal, en_o, from the AXI interface, is directly used to enable accesses. As a result, users with insufficient access permissions also get full access to the CLINT peripheral.
To fix this, enable access requests to CLINT [REF-1383] only if the user has sufficient access as indicated by the acct_ctrl_i signal in the boolean && with en_acct.

module clint #(...
) (
...

input logic acct_ctrl_i,

...
);

logic en, en_acct;

...

axi_lite_interface #(...
) axi_lite_interface_i (

...

.en_o ( en_acct ),

...

);
assign en = en_acct && acct_ctrl_i;

...
endmodule

CVE-2019-6260
Baseboard Management Controller (BMC) device implements Advanced High-performance Bus (AHB) bridges that do not require authentication for arbitrary read and write access to the BMC's physical address space from the host, and possibly the network [REF-1138].
https://www.cve.org/CVERecord?id=CVE-2019-6260

Allowed
This CWE entry is at the Base level of abstraction, which is a preferred level of abstraction for mapping to the root causes of vulnerabilities.
Carefully read both the name and description to ensure that this mapping is an appropriate fit. Do not try to 'force' a mapping to a lower-level Base/Variant simply to comply with this preferred level of abstraction.

Arun Kanuparthi, Hareesh Khattri, Parbati Kumar Manna
Intel Corporation
2020-05-19
4.3
2020-12-10

CWE Content Team
MITRE
2021-10-28
updated Observed_Examples

CWE Content Team
MITRE
2022-04-28
updated Applicable_Platforms

CWE Content Team
MITRE
2022-06-28
updated Applicable_Platforms

CWE Content Team
MITRE
2022-10-13
updated Demonstrative_Examples, Description, Detection_Factors, Name, Potential_Mitigations

CWE Content Team
MITRE
2023-04-27
updated Relationships

CWE Content Team
MITRE
2023-06-29
updated Mapping_Notes

CWE Content Team
MITRE
2024-02-29
4.14
2024-02-29
updated Demonstrative_Examples, References

CWE Content Team
MITRE
2025-12-11
4.19
2025-12-11
updated Weakness_Ordinalities

Chen Chen, Rahul Kande, Jeyavijayan Rajendran
Texas A&M University
2023-06-21
suggested demonstrative example

Shaza Zeitouni, Mohamadreza Rostami, Ahmad-Reza Sadeghi
Technical University of Darmstadt
2023-06-21
suggested demonstrative example

Missing Security Checks in Fabric Bridge