Signals between a hardware IP and the parent system design are incorrectly connected causing security risks.

Individual hardware IP must communicate with the parent system in order for the product to function correctly and as intended. If implemented incorrectly, while not causing any apparent functional issues, may cause security issues. For example, if the IP should only be reset by a system-wide hard reset, but instead the reset input is connected to a software-triggered debug mode reset (which is also asserted during a hard reset), integrity of data inside the IP can be violated.

Primary

Implementation
This weakness is introduced when integrating IP into a parent design.

Confidentiality
Integrity
Availability
Varies by Context

Testing
System-level verification may be used to ensure that components are correctly connected and that design security requirements are not violated due to interactions between various IP blocks.

Many SoCs use hardware to partition system resources between trusted and untrusted entities. One example of this concept is the Arm TrustZone, in which the processor and all security-aware IP attempt to isolate resources based on the status of a privilege bit. This privilege bit is part of the input interface in all TrustZone-aware IP. If this privilege bit is accidentally grounded or left unconnected when the IP is instantiated, privilege escalation of all input data may occur.

// IP definition
module tz_peripheral(clk, reset, data_in, data_in_security_level, ...);

input clk, reset;
input [31:0] data_in;
input data_in_security_level;
...

endmodule
// Instantiation of IP in a parent system
module soc(...)

...
tz_peripheral u_tz_peripheral(

.clk(clk),
.rst(rst),
.data_in(rdata),
//Copy-and-paste error or typo grounds data_in_security_level (in this example 0=secure, 1=non-secure) effectively promoting all data to "secure")
.data_in_security_level(1'b0),

);
...

endmodule

In the Verilog code below, the security level input to the TrustZone aware peripheral is correctly driven by an appropriate signal instead of being grounded.

// Instantiation of IP in a parent system
module soc(...)

...
tz_peripheral u_tz_peripheral(

.clk(clk),
.rst(rst),
.data_in(rdata),
// This port is no longer grounded, but instead driven by the appropriate signal
.data_in_security_level(rdata_security_level),

);
...

endmodule

Here is a code snippet from the Ariane core module in the HACK@DAC'21 Openpiton SoC [REF-1362].
To ensure full functional correctness, developers connect the ports with names. However, in some cases developers forget to connect some of these ports to the desired signals in the parent module. These mistakes by developers can lead to incorrect functional behavior or, in some cases, introduce security vulnerabilities.

...
csr_regfile #(

...

) csr_regfile_i (

.flush_o ( flush_csr_ctrl ),
.halt_csr_o ( halt_csr_ctrl ),
...
.irq_i(),
.time_irq_i(),
.*

);
...

In the above example from HACK@DAC'21, since interrupt signals are not properly connected, the CSR module will fail to send notifications in the event of interrupts. Consequently, critical information in CSR registers that should be flushed or modified in response to an interrupt won't be updated. These vulnerabilities can potentially result in information leakage across various privilege levels.
To address the aforementioned vulnerability, developers must follow a two-step approach. First, they should ensure that all module signals are properly connected. This can often be facilitated using automated tools, and many simulators and sanitizer tools issue warnings when a signal remains unconnected or floats. Second, it is imperative to validate that the signals connected to a module align with the specifications. In the provided example, the developer should establish the correct connection of interrupt signals from the parent module (Ariane core) to the child module (csr_regfile) [REF-1363].

...
csr_regfile #(

...

) csr_regfile_i (

.flush_o ( flush_csr_ctrl ),
.halt_csr_o ( halt_csr_ctrl ),
...
.irq_i	(irq_i),
.time_irq_i	(time_irq_i),
.*

);
...

Allowed
This CWE entry is at the Base level of abstraction, which is a preferred level of abstraction for mapping to the root causes of vulnerabilities.
Carefully read both the name and description to ensure that this mapping is an appropriate fit. Do not try to 'force' a mapping to a lower-level Base/Variant simply to comply with this preferred level of abstraction.

Nicole Fern
Cycuity (originally submitted as Tortuga Logic)
2020-05-22
4.1
2020-02-24

CWE Content Team
MITRE
2020-08-20
updated Demonstrative_Examples, Description, Modes_of_Introduction, Name, Potential_Mitigations

CWE Content Team
MITRE
2022-10-13
updated Demonstrative_Examples

CWE Content Team
MITRE
2023-04-27
updated Relationships

CWE Content Team
MITRE
2023-06-29
updated Mapping_Notes

CWE Content Team
MITRE
2023-10-26
updated Demonstrative_Examples, References

CWE Content Team
MITRE
2025-12-11
4.19
2025-12-11
updated Demonstrative_Examples, Weakness_Ordinalities

Chen Chen, Rahul Kande, Jeyavijayan Rajendran
Texas A&M University
2023-06-21
suggested demonstrative example

Shaza Zeitouni, Mohamadreza Rostami, Ahmad-Reza Sadeghi
Technical University of Darmstadt
2023-06-21
suggested demonstrative example

Hardware Block Incorrectly Connected to Larger System