A processor event or prediction may allow incorrect operations (or correct operations with incorrect data) to execute transiently, potentially exposing data over a covert channel.

When operations execute but do not commit to the processor's
architectural state, this is commonly referred to as transient
execution. This behavior can occur when the processor mis-predicts an
outcome (such as a branch target), or when a processor event (such as
an exception or microcode assist, etc.) is handled after younger
operations have already executed. Operations that execute transiently
may exhibit observable discrepancies (CWE-203) in covert channels
[REF-1400] such as data caches. Observable discrepancies of this kind
can be detected and analyzed using timing or power analysis
techniques, which may allow an attacker to infer information about the
operations that executed transiently. For example, the attacker may be
able to infer confidential data that was accessed or used by those
operations.
Transient execution weaknesses may be exploited using one of two
methods. In the first method, the attacker generates a code sequence
that exposes data through a covert channel when it is executed
transiently (the attacker must also be able to trigger transient
execution). Some transient execution weaknesses can only expose data
that is accessible within the attacker's processor context. For
example, an attacker executing code in a software sandbox may be able
to use a transient execution weakness to expose data within the same
address space, but outside of the attacker's sandbox. Other transient
execution weaknesses can expose data that is architecturally
inaccessible, that is, data protected by hardware-enforced boundaries
such as page tables or privilege rings. These weaknesses are the
subject of CWE-1421.
In the second exploitation method, the attacker first identifies a
code sequence in a victim program that, when executed transiently, can
expose data that is architecturally accessible within the victim's
processor context. For instance, the attacker may search the victim
program for code sequences that resemble a bounds-check bypass
sequence (see Demonstrative Example 1). If the attacker can trigger a
mis-prediction of the conditional branch and influence the index of
the out-of-bounds array access, then the attacker may be able to infer
the value of out-of-bounds data by monitoring observable discrepancies
in a covert channel.

Primary

Architecture and Design
This weakness can be introduced when a computing unit (such as a CPU, GPU, accelerator, or any other processor) uses out-of-order execution, speculation, or any other microarchitectural feature that can allow microarchitectural operations to execute without committing to architectural state.

Implementation
This weakness can be introduced when sandboxes or managed runtimes are not properly isolated by using hardware-enforced boundaries. Developers of sandbox or managed runtime software should exercise caution when relying on software techniques (such as bounds checking) to prevent code in one sandbox from accessing confidential data in another sandbox. For example, an attacker sandbox may be able to trigger a processor event or mis-prediction in a manner that allows it to transiently read a victim sandbox's private data.

Confidentiality
Read Memory
Medium

Manual Analysis
This weakness can be detected in hardware by manually inspecting processor specifications. Features that exhibit this weakness may include microarchitectural predictors, access control checks that occur out-of-order, or any other features that can allow operations to execute without committing to architectural state. Academic researchers have demonstrated that new hardware weaknesses can be discovered by exhaustively analyzing a processor's machine clear (or nuke) conditions ([REF-1427]).
Moderate

Hardware designers can also scrutinize aspects of the instruction set architecture
that have undefined behavior; these can become a focal point when applying other
detection methods.
Manual analysis may not reveal all weaknesses in a processor specification
and should be combined with other detection methods to improve coverage.

Fuzzing
Academic researchers have demonstrated that this weakness can be detected in hardware using software fuzzing tools that treat the underlying hardware as a black box ([REF-1428]).
Opportunistic

Fuzzing may not reveal all weaknesses in a processor specification and should
be combined with other detection methods to improve coverage.

Fuzzing
Academic researchers have demonstrated that this weakness can be detected in software using software fuzzing tools ([REF-1429]).
Opportunistic

At the time of this writing, publicly available software fuzzing tools can only
detect a subset of transient execution weaknesses in software (for example, [REF-1429] can only
detect instances of Spectre v1) and may produce false positives.

Automated Static Analysis
A variety of automated static analysis tools can identify
potentially exploitable code sequences in software. These tools may
perform the analysis on source code, on binary code, or on an
intermediate code representation (for example, during compilation).
Limited

At the time of this writing, publicly available software static analysis tools can
only detect a subset of transient execution weaknesses in software and may produce false
positives.

Automated Analysis
Software vendors can release tools that detect presence of
known weaknesses on a processor. For example, some of these tools can
attempt to transiently execute a vulnerable code sequence and detect
whether code successfully leaks data in a manner consistent with the
weakness under test. Alternatively, some hardware vendors provide
enumeration for the presence of a weakness (or lack of a
weakness). These enumeration bits can be checked and reported by
system software. For example, Linux supports these checks for many
commodity processors:
$ cat /proc/cpuinfo | grep bugs | head -n 1
bugs : cpu_meltdown spectre_v1 spectre_v2 spec_store_bypass l1tf mds swapgs taa itlb_multihit srbds mmio_stale_data retbleed
High

This method can be useful for detecting whether a processor is affected by
known weaknesses, but it may not be useful for detecting unknown weaknesses.

Architecture and Design
The hardware designer can attempt to prevent transient execution from causing observable discrepancies in specific covert channels.
Limited
This technique has many pitfalls. For example,
InvisiSpec was an early attempt to mitigate this weakness by blocking
"micro-architectural covert and side channels through the
multiprocessor data cache hierarchy due to speculative loads" [REF-1417].
Commodity processors and SoCs have many covert and side channels that
exist outside of the data cache hierarchy. Even when some of these
channels are blocked, others (such as execution ports [REF-1418]) may
allow an attacker to infer confidential data. Mitigation strategies
that attempt to prevent transient execution from causing observable
discrepancies also have other pitfalls, for example, see [REF-1419].

Requirements
Processor designers may expose instructions or other architectural features that allow software to mitigate the effects of transient execution, but without disabling predictors. These features may also help to limit opportunities for data exposure.

Moderate
Instructions or features that constrain transient execution or suppress its side effects may impact performance.

Requirements
Processor designers may expose registers (for example, control registers or model-specific registers) that allow privileged and/or user software to disable specific predictors or other hardware features that can cause confidential data to be exposed during transient execution.

Limited
Disabling specific predictors or other hardware features may result in significant performance overhead.

Requirements
Processor designers, system software vendors, or other agents may choose to restrict the ability of unprivileged software to access to high-resolution timers that are commonly used to monitor covert channels.

Defense in Depth
Specific software algorithms can be used by an attacker to compensate for a lack of a high-resolution time source [REF-1420].

Build and Compilation
Isolate sandboxes or managed runtimes in separate address spaces (separate processes). For examples, see [REF-1421].

High

Build and Compilation
Include serialization instructions (for example, LFENCE) that prevent processor events or mis-predictions prior to the serialization instruction from causing transient execution after the serialization instruction. For some weaknesses, a serialization instruction can also prevent a processor event or a mis-prediction from occurring after the serialization instruction (for example, CVE-2018-3639 can allow a processor to predict that a load will not depend on an older store; a serialization instruction between the store and the load may allow the store to update memory and prevent the prediction from happening at all).

Moderate
When used to comprehensively mitigate a transient execution weakness (for example, by inserting an LFENCE after every instruction in a program), serialization instructions can introduce significant performance overhead. On the other hand, when used to mitigate only a relatively small number of high-risk code sequences, serialization instructions may have a low or negligible impact on performance.

Build and Compilation
Use control-flow integrity (CFI) techniques to constrain the behavior of instructions that redirect the instruction pointer, such as indirect branch instructions.

Moderate
Some CFI techniques may not be able to constrain transient execution, even though they are effective at constraining architectural execution. Or they may be able to provide some additional protection against a transient execution weakness, but without comprehensively mitigating the weakness. For example, Clang-CFI provides strong architectural CFI properties and can make some transient execution weaknesses more difficult to exploit [REF-1398].

Build and Compilation
If the weakness is exposed by a single instruction (or a small set of instructions), then the compiler (or JIT, etc.) can be configured to prevent the affected instruction(s) from being generated, and instead generate an alternate sequence of instructions that is not affected by the weakness. One prominent example of this mitigation is retpoline ([REF-1414]).

Limited
This technique may only be effective for software that is compiled with this mitigation. For some transient execution weaknesses, this technique may not be sufficient to protect software that is compiled without the affected instruction(s). For example, see CWE-1421.

Build and Compilation
Use software techniques that can mitigate the consequences of transient execution. For example, address masking can be used in some circumstances to prevent out-of-bounds transient reads.

Limited
Address masking and related software mitigation techniques have been used to harden specific code sequences that could potentially be exploited via transient execution. For example, the Linux kernel makes limited use of manually inserted address masks to mitigate bounds-check bypass [REF-1390]. Compiler-based techniques have also been used to automatically harden software [REF-1425].

Build and Compilation
Use software techniques (including the use of serialization instructions) that are intended to reduce the number of instructions that can be executed transiently after a processor event or misprediction.

Incidental
Some transient execution weaknesses can be exploited even if a single instruction is executed transiently after a processor event or mis-prediction. This mitigation strategy has many other pitfalls that prevent it from eliminating this weakness entirely. For example, see [REF-1389].

Documentation
If a hardware feature can allow incorrect operations (or correct operations with incorrect data) to execute transiently, the hardware designer may opt to disclose this behavior in architecture documentation. This documentation can inform users about potential consequences and effective mitigations.

High

Secure programs perform bounds checking before accessing an array if the source of the array index is provided by an untrusted source such as user input. In the code below, data from array1 will not be accessed if x is out of bounds. The following code snippet is from [REF-1415]:

if (x < array1_size)
y = array2[array1[x] * 4096];

However, if this code executes on a processor that performs
conditional branch prediction the outcome of the if statement could be
mis-predicted and the access on the next line will occur with a value
of x that can point to an out-of-bounds location (within the program's
memory).
Even though the processor does not commit the architectural effects of
the mis-predicted branch, the memory accesses alter data cache state,
which is not rolled back after the branch is resolved. The cache state
can reveal array1[x] thereby providing a mechanism to recover the data
value located at address array1 + x.

Some managed runtimes or just-in-time (JIT) compilers may overwrite recently executed code with new code. When the instruction pointer enters the new code, the processor may inadvertently execute the stale code that had been overwritten. This can happen, for instance, when the processor issues a store that overwrites a sequence of code, but the processor fetches and executes the (stale) code before the store updates memory. Similar to the first example, the processor does not commit the stale code's architectural effects, though microarchitectural side effects can persist. Hence, confidential information accessed or used by the stale code may be inferred via an observable discrepancy in a covert channel. This vulnerability is described in more detail in [REF-1427].

CVE-2017-5753
Microarchitectural conditional branch predictors may allow operations to execute transiently after a misprediction, potentially exposing data over a covert channel.
https://www.cve.org/CVERecord?id=CVE-2017-5753

CVE-2021-0089
A machine clear triggered by self-modifying code may allow incorrect operations to execute transiently, potentially exposing data over a covert channel.
https://www.cve.org/CVERecord?id=CVE-2021-0089

CVE-2022-0002
Microarchitectural indirect branch predictors may allow incorrect operations to execute transiently after a misprediction, potentially exposing data over a covert channel.
https://www.cve.org/CVERecord?id=CVE-2022-0002

Allowed-with-Review
This CWE entry is at the Base level of abstraction, which is a preferred level of abstraction for mapping to the root causes of vulnerabilities.

A vulnerability should only map to CWE-1420 if it cannot map to any of CWE-1420's child weaknesses. Follow this diagram:

Scott D. Constable
Intel Corporation
2023-09-19
4.14
2024-02-29

CWE Content Team
MITRE
2024-07-16
4.15
2024-07-16
updated Mapping_Notes

CWE Content Team
MITRE
2025-09-09
4.18
2025-09-09
updated References

CWE Content Team
MITRE
2025-12-11
4.19
2025-12-11
updated References, Weakness_Ordinalities

David Kaplan
AMD
2024-01-22
4.14
2024-02-29
Member of Microarchitectural Weaknesses Working Group

Rafael Dossantos, Abraham Fernandez Rubio, Alric Althoff, Lyndon Fawcett
Arm
2024-01-22
4.14
2024-02-29
Members of Microarchitectural Weaknesses Working Group

Jason Oberg
Cycuity
2024-01-22
4.14
2024-02-29
Member of Microarchitectural Weaknesses Working Group

Priya B. Iyer
Intel Corporation
2024-01-22
4.14
2024-02-29
Member of Microarchitectural Weaknesses Working Group

Nicole Fern
Riscure
2024-01-22
4.14
2024-02-29
Member of Microarchitectural Weaknesses Working Group