The device is missing or incorrectly implements circuitry or sensors that detect and mitigate the skipping of security-critical CPU instructions when they occur.

The operating conditions of hardware may change
in ways that cause unexpected behavior to occur,
including the skipping of security-critical CPU
instructions. Generally, this can occur due to
electrical disturbances or when the device operates
outside of its expected conditions.
In practice, application code may contain
conditional branches that are security-sensitive (e.g.,
accepting or rejecting a user-provided password). These
conditional branches are typically implemented by a
single conditional branch instruction in the program
binary which, if skipped, may lead to effectively
flipping the branch condition - i.e., causing the wrong
security-sensitive branch to be taken. This affects
processes such as firmware authentication, password
verification, and other security-sensitive decision
points.
Attackers can use fault injection techniques to
alter the operating conditions of hardware so that
security-critical instructions are skipped more
frequently or more reliably than they would in a
"natural" setting.

Primary

Architecture and Design
Failure to design appropriate countermeasures to common fault injection techniques can manifest this weakness.

Implementation
This weakness can arise if the hardware design incorrectly implements countermeasures to prevent fault injection.

Confidentiality
Integrity
Authentication
Bypass Protection Mechanism
Alter Execution Logic
Unexpected State
High
Depending on the context, instruction skipping can
have a broad range of consequences related to the
generic bypassing of security critical code.

Automated Static Analysis
This weakness can be found using automated static analysis once a developer has indicated which code paths are critical to protect.
Moderate

Simulation / Emulation
This weakness can be found using automated dynamic analysis. Both emulation of a CPU with instruction skips, as well as RTL simulation of a CPU IP, can indicate parts of the code that are sensitive to faults due to instruction skips.
Moderate

Manual Analysis
This weakness can be found using manual (static) analysis. The analyst has security objectives that are matched against the high-level code. This method is less precise than emulation, especially if the analysis is done at the higher level language rather than at assembly level.
Moderate

Architecture and Design
Design strategies for ensuring safe failure if
inputs, such as Vcc, are modified out of acceptable
ranges.

Architecture and Design
Design strategies for ensuring safe behavior if
instructions attempt to be skipped.

Architecture and Design
Identify mission critical secrets that should
be wiped if faulting is detected, and design a
mechanism to do the deletion.

Implementation
Add redundancy by performing an operation
multiple times, either in space or time, and perform
majority voting. Additionally, make conditional
instruction timing unpredictable.

Implementation
Use redundant operations or canaries to
detect and respond to faults.

Implementation
Ensure that fault mitigations are strong enough
in practice. For example, a low power detection
mechanism that takes 50 clock cycles to trigger at lower
voltages may be an insufficient security mechanism if
the instruction counter has already progressed with no
other CPU activity occurring.

A smart card contains authentication credentials that are used as authorization to enter a building. The credentials are only accessible when a correct PIN is presented to the card.

The card emits the credentials when a voltage anomaly is injected into the power line to the device at a particular time after providing an incorrect PIN to the card, causing the internal program to accept the incorrect PIN.
There are several ways this weakness could be fixed.

add an internal filter or internal power supply in series with the power supply pin on the device
add sensing circuitry to reset the device if out of tolerance conditions are detected
add additional execution sensing circuits to monitor the execution order for anomalies and abort the action or reset the device under fault conditions

CVE-2019-15894
fault injection attack bypasses the verification mode, potentially allowing arbitrary code execution.
https://www.cve.org/CVERecord?id=CVE-2019-15894

Power

Allowed
This CWE entry is at the Base level of abstraction, which is a preferred level of abstraction for mapping to the root causes of vulnerabilities.
Carefully read both the name and description to ensure that this mapping is an appropriate fit. Do not try to 'force' a mapping to a lower-level Base/Variant simply to comply with this preferred level of abstraction.

Jasper van Woudenberg
Riscure
2020-10-14
4.3
2020-12-10

Jasper van Woudenberg
Riscure
2021-01-11

CWE Content Team
MITRE
2021-03-15
updated Description, Functional_Areas, Potential_Mitigations, References

CWE Content Team
MITRE
2021-10-28
updated Demonstrative_Examples, Description, Detection_Factors, Maintenance_Notes, Name, Observed_Examples, Potential_Mitigations, References, Relationships, Weakness_Ordinalities

CWE Content Team
MITRE
2022-04-28
updated Potential_Mitigations, References, Relationships

CWE Content Team
MITRE
2022-06-28
updated Relationships

CWE Content Team
MITRE
2022-10-13
updated References

CWE Content Team
MITRE
2023-01-31
updated Potential_Mitigations, Related_Attack_Patterns

CWE Content Team
MITRE
2023-04-27
updated References, Relationships

CWE Content Team
MITRE
2023-06-29
updated Mapping_Notes

CWE Content Team
MITRE
2025-04-03
4.17
2025-04-03
updated Demonstrative_Examples

Jasper van Woudenberg
Riscure
2021-10-11
Provided detection methods and feedback on demonstrative example

Insufficient Protection Against Instruction Skipping Via Fault Injection