The product uses a trusted lock bit for restricting access to registers, address regions, or other resources, but the product does not prevent the value of the lock bit from being modified after it has been set.

In integrated circuits and hardware
intellectual property (IP) cores, device configuration
controls are commonly programmed after a device power
reset by a trusted firmware or software module (e.g.,
BIOS/bootloader) and then locked from any further
modification.

This behavior is commonly implemented using a trusted lock bit.
When set, the lock bit disables writes to a protected set of
registers or address regions. Design or coding errors in
the implementation of the lock bit protection feature
may allow the lock bit to be modified or cleared by
software after it has been set. Attackers might be able to unlock the system and
features that the bit is intended to protect.

Primary

Architecture and Design
Such issues could be introduced during hardware architecture and design and identified later during Testing or System Configuration phases.

Implementation
Such issues could be introduced during implementation and identified later during Testing or System Configuration phases.

Access Control
Modify Memory
High
Registers protected by lock bit can be modified even when lock is set.

Manual Analysis
Set the lock bit. Power cycle the
device. Attempt to clear the lock bit. If the
information is changed, implement a design
fix. Retest. Also, attempt to indirectly clear the lock
bit or bypass it.
High

Architecture and Design
Implementation
Testing

Security lock bit protections must be reviewed for design inconsistency and common weaknesses.
Security lock programming flow and lock properties must be tested in pre-silicon and post-silicon testing.

High

Consider the example design below for a digital thermal sensor that detects overheating of the silicon and triggers system shutdown. The system critical temperature limit (CRITICAL_TEMP_LIMIT) and thermal sensor calibration (TEMP_SENSOR_CALIB) data have to be programmed by firmware, and then the register needs to be locked (TEMP_SENSOR_LOCK).

Register
Field description

CRITICAL_TEMP_LIMIT
[31:8] Reserved field; Read only; Default 0[7:0] Critical temp 0-255 Centigrade; Read-write-lock; Default 125

TEMP_SENSOR_CALIB
[31:0] Thermal sensor calibration data. Slope value used to map sensor reading to degrees Centigrade.

TEMP_SENSOR_LOCK
[31:1] Reserved field; Read only; Default 0[0] Lock bit, locks CRITICAL_TEMP_LIMIT and TEMP_SENSOR_CALIB registers; Write-1-once; Default 0

TEMP_HW_SHUTDOWN
[31:2] Reserved field; Read only; Default 0[1] Enable hardware shutdown on critical temperature detection; Read-write; Default 0

CURRENT_TEMP
[31:8] Reserved field; Read only; Default 0[7:0] Current Temp 0-255 Centigrade; Read-only; Default 0

In this example, note that if the system heats to critical temperature, the response of the system is controlled by the TEMP_HW_SHUTDOWN bit [1], which is not lockable. Thus, the intended security property of the critical temperature sensor cannot be fully protected, since software can misconfigure the TEMP_HW_SHUTDOWN register even after the lock bit is set to disable the shutdown response.

To fix this weakness, one could change the TEMP_HW_SHUTDOWN field to be locked by TEMP_SENSOR_LOCK.

TEMP_HW_SHUTDOWN
[31:2] Reserved field; Read only; Default 0 [1] Enable hardware shutdown on critical temperature detection; Read-write-Lock; Default 0[0] Locked by TEMP_SENSOR_LOCK

The following example code is a snippet from the register locks inside the buggy OpenPiton SoC of HACK@DAC'21 [REF-1350]. Register locks help prevent SoC peripherals' registers from malicious use of resources. The registers that can potentially leak secret data are locked by register locks.
In the vulnerable code, the reglk_mem is used for locking information. If one of its bits toggle to 1, the corresponding peripheral's registers will be locked. In the context of the HACK@DAC System-on-Chip (SoC), it is pertinent to note the existence of two distinct categories of reset signals.
First, there is a global reset signal denoted as "rst_ni," which possesses the capability to simultaneously reset all peripherals to their respective initial states.
Second, we have peripheral-specific reset signals, such as "rst_9," which exclusively reset individual peripherals back to their initial states. The administration of these reset signals is the responsibility of the reset controller module.

always @(posedge clk_i)
begin
if(~(rst_ni && ~jtag_unlock && ~rst_9))
begin
for (j=0; j < 6; j=j+1) begin
reglk_mem[j] <= 'h0;

end

end...

In the buggy SoC architecture during HACK@DAC'21, a critical issue arises within the reset controller module. Specifically, the reset controller can inadvertently transmit a peripheral reset signal to the register lock within the user privilege domain.
This unintentional action can result in the reset of the register locks, potentially exposing private data from all other peripherals, rendering them accessible and readable.
To mitigate the issue, remove the extra reset signal rst_9 from the register lock if condition. [REF-1351]

always @(posedge clk_i)
begin
if(~(rst_ni && ~jtag_unlock))
begin
for (j=0; j < 6; j=j+1) begin
reglk_mem[j] <= 'h0;

end

end...

CVE-2017-6283
chip reset clears critical read/write lock permissions for RSA function
https://www.cve.org/CVERecord?id=CVE-2017-6283

Allowed
This CWE entry is at the Base level of abstraction, which is a preferred level of abstraction for mapping to the root causes of vulnerabilities.
Carefully read both the name and description to ensure that this mapping is an appropriate fit. Do not try to 'force' a mapping to a lower-level Base/Variant simply to comply with this preferred level of abstraction.

Arun Kanuparthi, Hareesh Khattri, Parbati Kumar Manna, Narasimha Kumar V Mangipudi
Intel Corporation
2020-01-15
4.0
2020-02-24

CWE Content Team
MITRE
2020-06-25
updated Demonstrative_Examples

CWE Content Team
MITRE
2020-08-20
updated Related_Attack_Patterns

CWE Content Team
MITRE
2021-10-28
updated Demonstrative_Examples, Description, Detection_Factors, Name, Observed_Examples, Potential_Mitigations, Relationships, Weakness_Ordinalities

CWE Content Team
MITRE
2022-04-28
updated Related_Attack_Patterns, Relationships

CWE Content Team
MITRE
2023-04-27
updated Relationships

CWE Content Team
MITRE
2023-06-29
updated Mapping_Notes

CWE Content Team
MITRE
2023-10-26
updated Demonstrative_Examples, References

CWE Content Team
MITRE
2025-04-03
4.17
2025-04-03
updated Demonstrative_Examples

CWE Content Team
MITRE
2025-09-09
4.18
2025-09-09
updated Relationships

Narasimha Kumar V Mangipudi
Lattice Semiconductor
2021-10-20
reviewed content changes

Hareesh Khattri
Intel Corporation
2021-10-22
provided observed example

Shaza Zeitouni, Mohamadreza Rostami, Pouya Mahmoody, Ahmad-Reza Sadeghi
Technical University of Darmstadt
2023-06-21
suggested demonstrative example

Rahul Kande, Chen Chen, Jeyavijayan Rajendran
Texas A&M University
2023-06-21
suggested demonstrative example

Improper Implementation of Lock Protection Registers