The product uses physical debug or test
interfaces with support for multiple access levels, but it
assigns the wrong debug access level to an internal asset,
providing unintended access to the asset from untrusted debug
agents.

Debug authorization can have multiple levels of
access, defined such that different system internal assets
are accessible based on the current authorized debug
level. Other than debugger authentication (e.g., using
passwords or challenges), the authorization can also be
based on the system state or boot stage. For example, full
system debug access might only be allowed early in boot
after a system reset to ensure that previous session data is
not accessible to the authenticated debugger.

Primary

Architecture and Design

Implementation

Confidentiality
Read Memory
If a protection mechanism does not ensure that
internal assets have the correct debug access level during
each boot stage or change in system state, an attacker could
obtain sensitive information from the internal asset using a
debugger.

Integrity
Modify Memory

Authorization
Access Control
Gain Privileges or Assume Identity
Bypass Protection Mechanism

Manual Analysis
Check 2 devices for their passcode to authenticate access to JTAG/debugging ports. If the passcodes are missing or the same, update the design to fix and retest. Check communications over JTAG/debugging ports for encryption. If the communications are not encrypted, fix the design and retest.
Moderate

Architecture and Design
Implementation

For security-sensitive assets accessible over debug/test interfaces, only allow trusted agents.

High

Architecture and Design
Apply blinding [REF-1219] or masking techniques in strategic areas.
Limited

Implementation
Add shielding or tamper-resistant protections to the device, which increases the difficulty and cost for accessing debug/test interfaces.
Limited

The JTAG interface is used to perform debugging and provide CPU core access for developers. JTAG-access protection is implemented as part of the JTAG_SHIELD bit in the hw_digctl_ctrl register. This register has no default value at power up and is set only after the system boots from ROM and control is transferred to the user software.

1 bit
0x0 = JTAG debugger is enabled (default)

JTAG_SHIELD
0x1 = JTAG debugger is disabled

This means that since the end user has access to JTAG at system reset and during ROM code execution before control is transferred to user software, a JTAG user can modify the boot flow and subsequently disclose all CPU information, including data-encryption keys.

The default value of this register bit should be set to 1 to prevent the JTAG from being enabled at system reset.

The example code below is taken from the CVA6 processor core of the HACK@DAC'21 buggy OpenPiton SoC. Debug access allows users to access internal hardware registers that are otherwise not exposed for user access or restricted access through access control protocols. Hence, requests to enter debug mode are checked and authorized only if the processor has sufficient privileges. In addition, debug accesses are also locked behind password checkers. Thus, the processor enters debug mode only when the privilege level requirement is met, and the correct debug password is provided.
The following code [REF-1377] illustrates an instance of a vulnerable implementation of debug mode. The core correctly checks if the debug requests have sufficient privileges and enables the debug_mode_d and debug_mode_q signals. It also correctly checks for debug password and enables umode_i signal.

module csr_regfile #(
...

// check that we actually want to enter debug depending on the privilege level we are currently in
unique case (priv_lvl_o)

riscv::PRIV_LVL_M: begin

debug_mode_d = dcsr_q.ebreakm;

...

riscv::PRIV_LVL_U: begin

debug_mode_d = dcsr_q.ebreaku;

...

assign priv_lvl_o = (debug_mode_q || umode_i) ? riscv::PRIV_LVL_M : priv_lvl_q;

...

debug_mode_q <= debug_mode_d;

...

However, it grants debug access and changes the privilege level, priv_lvl_o, even when one of the two checks is satisfied and the other is not. Because of this, debug access can be granted by simply requesting with sufficient privileges (i.e., debug_mode_q is enabled) and failing the password check (i.e., umode_i is disabled). This allows an attacker to bypass the debug password checking and gain debug access to the core, compromising the security of the processor.
A fix to this issue is to only change the privilege level of the processor when both checks are satisfied, i.e., the request has enough privileges (i.e., debug_mode_q is enabled) and the password checking is successful (i.e., umode_i is enabled) [REF-1378].

module csr_regfile #(
...

// check that we actually want to enter debug depending on the privilege level we are currently in
unique case (priv_lvl_o)

riscv::PRIV_LVL_M: begin

debug_mode_d = dcsr_q.ebreakm;

...

riscv::PRIV_LVL_U: begin

debug_mode_d = dcsr_q.ebreaku;

...

assign priv_lvl_o = (debug_mode_q && umode_i) ? riscv::PRIV_LVL_M : priv_lvl_q;

...

debug_mode_q <= debug_mode_d;

...

CVE-2019-18827
After ROM code execution, JTAG access is disabled. But before the ROM code is executed, JTAG access is possible, allowing a user full system access. This allows a user to modify the boot flow and successfully bypass the secure-boot process.
https://www.cve.org/CVERecord?id=CVE-2019-18827

Allowed
This CWE entry is at the Base level of abstraction, which is a preferred level of abstraction for mapping to the root causes of vulnerabilities.
Carefully read both the name and description to ensure that this mapping is an appropriate fit. Do not try to 'force' a mapping to a lower-level Base/Variant simply to comply with this preferred level of abstraction.

CWE-1191 and CWE-1244 both involve physical debug access,
but the weaknesses are different. CWE-1191 is effectively
about missing authorization for a debug interface,
i.e. JTAG. CWE-1244 is about providing internal assets with
the wrong debug access level, exposing the asset to
untrusted debug agents.

Arun Kanuparthi, Hareesh Khattri, Parbati Kumar Manna, Narasimha Kumar V Mangipudi
Intel Corporation
2020-02-12
4.0
2020-02-24

CWE Content Team
MITRE
2020-08-20
updated Demonstrative_Examples, Name, Observed_Examples, Related_Attack_Patterns

CWE Content Team
MITRE
2021-03-15
updated Maintenance_Notes

CWE Content Team
MITRE
2021-10-28
updated Demonstrative_Examples, Description, Detection_Factors, Maintenance_Notes, Name, Observed_Examples, Potential_Mitigations, References, Relationship_Notes, Relationships, Weakness_Ordinalities

CWE Content Team
MITRE
2022-04-28
updated Related_Attack_Patterns

CWE Content Team
MITRE
2023-04-27
updated References, Relationships

CWE Content Team
MITRE
2023-06-29
updated Mapping_Notes

CWE Content Team
MITRE
2024-02-29
4.14
2024-02-29
updated Demonstrative_Examples, References

CWE Content Team
MITRE
2025-09-09
4.18
2025-09-09
updated References, Relationships

CWE Content Team
MITRE
2025-12-11
4.19
2025-12-11
updated Common_Consequences, Description

Hareesh Khattri
Intel Corporation
2021-10-22
clarified differences between CWE-1191 and CWE-1244, and suggested rephrasing of descriptions and names.

Chen Chen, Rahul Kande, Jeyavijayan Rajendran
Texas A&M University
2023-11-07
suggested demonstrative example

Shaza Zeitouni, Mohamadreza Rostami, Ahmad-Reza Sadeghi
Technical University of Darmstadt
2023-11-07
suggested demonstrative example

Improper Authorization on Physical Debug and Test Interfaces
Improper Access to Sensitive Information Using Debug and Test Interfaces