 verilog, standardized as ieee 1364, is a hardware description language (hdl) used to model electronic systems. it is most commonly used in the design and verification of digital circuits at the register-transfer level of abstraction. it is also used in the verification of analog circuits and mixed-signal circuits. ==overview== hardware description languages such as verilog differ from software programming languages because they include ways of describing the propagation time and signal strengths (sensitivity). there are two types of assignment operators; a blocking assignment (=), and a non-blocking (>>. a generate/endgenerate construct (similar to vhdl's generate/endgenerate) allows verilog-2001 to control instance and statement instantiation through normal decision operators (case/if/else). using generate/endgenerate, verilog-2001 can instantiate an array of instances, with control over the connectivity of the individual instances. file i/o has been improved by several new system tasks. and finally, a few syntax additions were introduced to improve code readability (e.g. always @*, named parameter override, c-style function/task/module header declaration). verilog-2001 is the dominant flavor of verilog supported by the majority of commercial eda software packages. ===verilog 2005=== not to be confused with systemverilog, verilog 2005 (ieee standard 1364-2005) consists of minor corrections, spec clarifications, and a few new language features (such as the uwire keyword). a separate part of the verilog standard, verilog-ams, attempts to integrate analog and mixed signal modeling with traditional verilog. ===systemverilog===  systemverilog is a superset of verilog-2005, with many new features and capabilities to aid design verification and design modeling. as of 2009, the systemverilog and verilog language standards were merged into systemverilog 2009 (ieee standard 1800-2009). the advent of hardware verification languages such as openvera, and verisity's e language encouraged the development of superlog by co-design automation inc. co-design automation i
Hardware_description_languages IEEE_DASC_standards