  in computing, a computer bus operating with double data rate (ddr) transfers data on both the rising and falling edges of the clock signal. this is also known as double pumped, dual-pumped, and double transition. the term toggle mode is used in the context of nand flash memory. the simplest way to design a clocked electronic circuit is to make it perform one transfer per full cycle (rise and fall) of a clock signal. this, however, requires that the clock signal changes twice per transfer, while the data lines change at most once per transfer. when operating at a high bandwidth, signal integrity limitations constrain the clock frequency. by using both edges of the clock, the data signals operate with the same limiting frequency, thereby doubling the data transmission rate. this technique has been used for microprocessor front side busses, ultra-3 scsi, graphics ram (the agp bus and gddr), main memory (both rdram and ddr1 through ddr4), and the hypertransport bus on amd's athlon 64 processors. it is more recently being used for other systems with high data transfer speed requirements as an example, for the output of analog-to-digital converters (adcs).  ddr should not be confused with dual channel, in which each memory channel accesses two ram modules simultaneously. the two technologies are independent of each other and many motherboards use both, by using ddr memory in a dual channel configuration. an alternative to double or quad pumping is to make the link self-clocking. this tactic was chosen by infiniband and pci express. ==relation of bandwidth and frequency== describing the bandwidth of a double-pumped bus can be confusing. each clock edge is referred to as a beat, with two beats (one upbeat and one downbeat) per cycle. technically, the hertz is a unit of cycles per second, but many people refer to the number of transfers per second. careful usage generally talks about "500&nbsp;mhz, double data rate" 
Clock_signal Digital_electronics