   montecito is the code-name of a major release of intel's itanium 2 processor family (ipf), which implements the intel itanium architecture on a dual-core processor. it was officially launched by intel on july 18, 2006 as the "dual-core intel itanium 2 processor". according to intel, montecito doubles performance versus the previous, single-core itanium 2 processor, and reduces power consumption by about 20%. it also adds multi-threading capabilities (two threads per core), a greatly expanded cache subsystem (12 mb per core), and silicon support for virtualization. ==architectural features and attributes== * two cores per die * 2-way coarse-grained multithreading per core (not simultaneous). montecito-flavour of multi-threading is dubbed temporal, or tmt. this is also known as switch-on-event multithreading, or soemt. the two separate threads do not run simultaneously, but the core switches thread in case of a high latency event, like an l3 cache miss which would otherwise stall execution. by this technique, multi-threaded workloads, including database-like workloads, should improve by 15-35%. * a total of 4 threads per die * separate 16 kb instruction l1 and 16 kb data l1 cache per core * separate 1 mb instruction l2 and 256 kb data l2 cache per core, improved hierarchy * 12 mb l3 cache per core, 24 mb l3 per die * 1.72 billion transistors per die, which is added up from: ** core logic â 57m, or 28.5m per core ** core caches â 106.5m ** 24 mb l3 cache â 1550m ** bus logic & i/o â 6.7m * die size is 27.72&nbsp;mm &times; 21.5&nbsp;mm, or 596&nbsp;mmÂ² * 90 nanometer design * lower power consumption and thermal dissipation than earlier flagship itaniums, despite the high transistor count and higher clock speeds; 75-104&nbsp;w. this is mainly achieved by applying different types of transistors. by default, slower and low-leakage transistors were used, while high-speed, thus high-leakage ones where it was necessary. * advanced compensation for errors in cache, for reliable operation under mission-critical workloads. this was code-named pellston technology during development, and has recently been renamed intel cache safe technology. * virtualization technology allowing multiple os instances per chip. this was known as silvervale technology during dev
Intel_microprocessors