  in cpu design, the use of a sum addressed decoder or sum addressed memory (sam) decoder is a method of reducing the latency of the cpu cache access. this is achieved by fusing the address generation sum operation with the decode operation in the cache sram. ==overview== the l1 data cache should usually be in the most critical cpu resource, because few things improve instructions per cycle (ipc) as directly as a larger data cache, a larger data cache takes longer to access, and pipelining the data cache makes ipc worse. one way of reducing the latency of the l1 data cache access is by fusing the address generation sum operation with the decode operation in the cache sram. the address generation sum operation still must be performed, because other units in the memory pipe will use the resulting virtual address. that sum will be performed in parallel with the fused add/decode described here. the most profitable recurrence to accelerate is a load, followed by a use of that load in a chain of integer operations leading to another load. assuming that load results are bypassed with the same priority as integer results, then it's possible to summarize this recurrence as a load followed by another loadâas if the program was following a linked list. the rest of this page assumes an instruction set architecture (isa) with a single addressing mode (register+offset), a virtually indexed data cache, and sign-extending loads that may be variable-width. most risc isas fit this description. in isas such as the intel x86, three or four inputs are summed to generate the virtual address. multiple-input additions can be reduced to a two-input addition with carry save adders, and the remaining problem is as described below. the critical recurrence, then, is an adder, a decoder, the sram word line, the sram bit line(s), the sense amp(s), the byte steering muxes, and the bypass muxes. for this example, a direct-mapped 16&nbsp;kb data cache which returns doubleword (8-byte) aligned values is assumed. each line of the sram is 8 bytes, and there are 2048 lines, addressed by addr[13:3]. the sum addressed sram idea applies equally well to set associative caches. ==sum-addressed cache: collapse the adder and decoder== the sram decoder for this example has an 11 bit input, addr[13:3], and 2048 outputs, the decoded word lines. one word line is driven high in response to each unique addr[13:3] value. in the simplest form of decoder, each of the 2048 lines is logically an and gate. the 11 bits (call them a[13:3] and their complements (call them b[13:3]) are driven up the decoder. for each line, 11 bits or complements are fed into an 11-input and gate. for instance, 1026 decimal is equal to 10000000010 binary. the function for line 1026
Digital_circuits