  the q-busschmidt, atlant g.,unibus,q-bus and vaxbi bus, in di giacomo joseph ed., mcgraw hill, 1990 (also known as the lsi-11 bus) was one of several bus technologies used with pdp and microvax computer systems manufactured by the digital equipment corporation of maynard, massachusetts. the q-bus was a less expensive version of unibus using multiplexing so that address and data signals shared the same wires. this allowed both a physically smaller and less-expensive implementation of essentially the same functionality. over time, the physical address range of the q-bus was expanded from 16 to 18 and then 22 bits. block transfer modes were also added to the q-bus. ==main features of the q-bus== thumb|lsi-11/23 q-bus cards and slots thumb|dec ba213 cabinet; 12 q-bus-22 slotslike the unibus before it, the q-bus used: * memory-mapped i/o * byte addressing * a strict master-slave relationship between devices on the bus * asynchronous signaling memory-mapped i/o means that data cycles between any two devices, whether cpu, memory, or i/o devices, used the same protocols. on the unibus, a range of physical addresses were dedicated for i/o devices. the q-bus simplified this design by providing a specific signal (originally called bbs7, bus bank select 7 but later generalized to be called bbsio, bus bank select i/o) that selected the range of addresses used by the i/o devices. byte addressing means that the physical address passed on the unibus was interpreted as the address of a byte-sized quantity of data. because the bus actually contained a data path that was two bytes wide, address bit [0] was subject to special interpretation and data on the bus had to travel in the correct byte lanes. a strict master-slave relationship means that at any point in time, only one device could be the master of the q-bus. this master device could initiate data transactions which could then be responded to by a maximum of one selected slave device. (this had no effect on whether a given bus cycle was reading or writing data; the bus master could command either type of transaction.) at the end of the bus cycle, a bus arbitration protocol would then select the next device to be given mastership of the bus. asynchronous signaling means that the bus had no fixed cycle time; the duration of any particular data transfer cycle on the bus was determined solely by the master and slave devices participating in the curr
Computer_buses DEC_hardware Minicomputers