Multiplication-Free Parallelizable Spiking Neurons with Efficient Spatio-Temporal Dynamics
Authors: Peng Xue
Wei Fang
Zhengyu Ma
Zihan Huang
Zhaokun Zhou
Yonghong Tian
Timothée Masquelier
Huihui Zhou
Venue: NeurIPS 2025 poster ()
Keywords: Spiking Neural Network
SNN
deep learning
spiking neuron
neuromorphic computing
Primary area: neuroscience_and_cognitive_science

Abstract: Spiking Neural Networks (SNNs) are distinguished from Artificial Neural Networks (ANNs) for their complex neuronal dynamics and sparse binary activations (spikes) inspired by the biological neural system. Traditional neuron models use iterative step-by-step dynamics, resulting in serial computation and slow training speed of SNNs. Recently, parallelizable spiking neuron models have been proposed to fully utilize the massive parallel computing ability of graphics processing units to accelerate the training of SNNs. However, existing parallelizable spiking neuron models involve dense floating operations and can only achieve high long-term dependencies learning ability with a large order at the cost of huge computational and memory costs. To solve the dilemma of performance and costs, we propose the mul-free channel-wise Parallel Spiking Neuron, which is hardware-friendly and suitable for SNNs’ resource-restricted application scenarios. The proposed neuron imports the channel-wise convolution to enhance the learning ability, induces the sawtooth dilations to reduce the neuron order, and employs the bit-shift operation to avoid multiplications. The algorithm for the design and implementation of acceleration methods is discussed extensively. Our methods are validated in neuromorphic Spiking Heidelberg Digits voices, sequential CIFAR images, and neuromorphic DVS-Lip vision datasets, achieving superior performance over SOTA spiking neurons. Training speed results demonstrate the effectiveness of our acceleration methods, providing a practical reference for future research. Our code is available at Github.

Multiplication-Free Parallelizable Spiking Neurons with Efficient Spatio-Temporal Dynamics
Peng X, Wei Fang Zhengyu Ma' Zihan Huang* Zhaokun Zhou 1.3
Yonghong Tian 1344 Timothée Masquelier Huihui Zhou
Peng Cheng Laboratory
Shenzhen Institute of Advanced Technology, Chinese Academy of Sciences
Sccooo of Electronic and Computer Engineering. Shenzhen Graduate School, Peking University "Shooo of Computer Science, Peking University
*Centre de Recherche Cerveau et Cognition (CERCO), UMR5549 CNRS-Universic Toulouse 3 University of Chinese Academy of Sciences
Abstract
Spiking Neural Networks (SNNs) are distinguished from Artificial Neural Net- works (ANNs) for their complex neuronal dynamics and sparse binary activations (spikes) inspired by the biological neural system. Traditional neuron models use iterative step-by-step dynamics, resulting in serial computation and slow training speed of SNNs. Recently, parallelizable spiking neuron models have been proposed fully utilize the massive parallel computing ability of graphics processing units to accelerate the training of SNNs. However, existing parallelizable spiking neuron models involve dense floating operations and can only achieve high long-term dependencies learning ability with a large order at the cost of huge computational and memory costs. To solve the dilemma of performance and costs, we propose the mul-free channel-wise Parallel Spiking Neuron, which is hardware-friendly and suitable for SNNs' resource-restricted application scenarios. The proposed neuron imports the channel-wise convolution to enhance the learning ability, induces the sawtooth dilations to reduce the neuron order, and employs the bit-shift operation to avoid multiplications. The algorithm for the design and implementation of acceler- ation methods discussed extensively. Our methods are validated in ncuromorphic Spiking Heidelberg Digits voices, sequential CIFAR images, and neuromorphic DVS-Lip vision datasets, achieving superior performance over SOTA spiking neu- rons. Training speed results demonstrate the effectiveness of our acceleration methods, providing practical reference for future research. Our code available at Github
1 Introduction
Inspired by the biological neural system, Spiking Neural Networks (SNNs) are regarded as the third-generation neural network models []] By emulating neuronal dynamics and spike-based communication characteristics in the brain 2 SNNs effectively capture temporal information and
achieve event-driven efficient computation, providing novel paradigm for building the spike-based machine intelligence
[
Spiking neurons are the key component that distinguishes SNNs from Artificial Neural Networks (ANNs) 4. They integrate input currents from synapses to membrane potentials by complex neuronal
"Coresponding author
39th Conference on Neural Information Processing Systems (NcurIPS 2025).

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dynamics and fire spikes when the membrane potentials cross the threshold. These proceedings are generally described by several discrete-time difference equations [5] 6 in a formulation similar to the Recurrent Neural Networks. The discrete threshold-triggeeed firing mechanism induces the nondifferentiable problem and restricts the application of gradient descent methods. Recently, this problem has been resolved to considerable degree by the surrogate gradient methods [7] 278,8 9
commonly use stateless synapses, i.e., the weights are shared across time-steps and outputs only depend on the inputs at the same time-step, to extract spatial features. Consequently, dynamic spiking neurons play a critical role in SNNs in extracting temporal features, and this has attracted many research interests. Most of the previous research focuses on increasing the neuron model complexity with learnable parameters [S] or adaptive dynamics (14), which strengthens the model capacity but brings extra computation costs, making it unfriendly for resource- restricted neuromorphic hardware. Another issue that traditional spiking neuron models run in serial step-by-step mode, limiting the utilization of the powerful parallel computing capabilities of Graphics Processing Units (GPUs) and resulting in a slower training speed for SNNs compared to ANNs. Recently, parallelizable spiking neuron models [ 16 17 [8 have been proposed that overwhelm traditional serial models in running speed, showing a promising solution to accelerate the training of SNNs.
Deep SNNs IO
One of the most attractive characteristics of SNNs is that the between binary spikes and synaptic weights can be superseded by accumulate (AC) operations during inference in neuromorphic chips 19] However, in previous designs of spiking neurons, the computational costs of the neuronal dynamics have not been paid much attention. For instance, the Complementary Leaky Integrated-and and-FFie (CLIF) neuron [4] introduces the computationally expensive sigmoid exponentiation, the Parallel Spiking Neuron (PSN), and the masked PSN 155 rely on the dense flotinn--ooin matrix multiplication. Compared to PSN and masked PSN, sliding PSN 115 only requires convolutional operations and demonstrates superior performance in handling time series with variable lengths. However, according to the study by 15). sliding PSN only achieves comparable performance to PSN when using a large convolutional kernel size, denoted as the order of the neuron, which significantly increases computational cost and memory usage. Moreover, these neurons still rely on massive multiply-accnee accumulate (MAC) operations between floating-pon moiit neuronal weights and input currents.
(MAC) operations
In this article, we focus on designing new variant of parallelizable spiking neuron models with hardware-frien friendly dynamics, low computation cost, and high long-term dependency learning ability. We propose enhanced neuronal architecture named Multiplication-Fiee Channel-wise Parallel Spiking Neurons (mul-free channel-wise PSN), whose neuronal dynamics are shown in Figure D and validate its performance with ofate-of-the-art (SOTA) accuracy on temporal datasets. Our contributions are as follows.
1) To enhance the temporal information-capturin ability, we derive the sliding PSN by applying the channel-wise separable convolutions. To solve the dilemma of large temporal receptive fields and computational costs, we use dilated convolution. Compared to sliding PSN, our improvement does not introduce any additional floating point operations (FL.Pss) and significantly reduces the inference memory.
2) To avoid the costly multiplication operations, we replace them with bit-shift operations, which are pardware-friendly for resource-restricted neuromorphic chips. The theoretical energy cost and area for hardware implementation with 8-bit integers (INT8) precision under 45nm CMOS is reduced 8x, from 0.2 p. and 282 pm² to 0.024 p./ and 34 um² (20). respectively.
3) We discuss the implementations of SNNs with mul-fre mul-free channel-wiss PSN GPUs for efficient training. We propose an autoselect algorithm to choose the fastest implementations, which is practical for future research about accelerating parallelizable spiking neurons.
4) We achieve superior performance over other SOTA spiking neurons on various temporal tasks, validating the superior capability of the proposed methods in learning long-term dependencies.
Related Work
Hardware-friendly Network Design. deploy neural network models to edge devices such as mobile phones and Field Programmable Gate Arrays with limited energy, memory, and computational

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Iaput
Neuronal Weight
Hidden State H E R
Threshold Vaa E R
Oulput Spike $ E [0.1)*xc
X E Txc
W E g
Shifft
Sum
PESI
Subtract
Heaviside
SPI
Figure 1: The neuronal dynamics of the mul-free channel-wise Parallel Spiking Neuron.
ability, a promising solution is hardware-friendly network design. Various methodologies have been proposed. Network quantization [2 quantizes the original weights and activations to low bits. Typical models in 8-bit integers require 4x less memory consumption and achieve up to 4x faster computation than models in 32-bit floating-poing Network pruning [2 prunes synapses and neurons to reduce the size of the model. Classic pruning methods can achieve 4x compression ratio for ResNer-18 18 on ImageNet with about 5% accuracy drop [23]. Knowledge distillation [24] employs a large teacher network to supervise the learning of small student network, and the student network can obtain a competitive or even higher performance than the teacher network. Apart from the above universal methods, SNNs [[] (25] achieve extreme power efficiency by asynchronous event-driven computation in tailored neuromorphic chips. For instance, Intel Loihi [26] consumes 48x energy efficiency than CPUs in solving the LASSO optimization problem; Tsinghua Tianjic [19] achieves up to 10 times power efficiency over the Titan-Xp GPU when classifying the NMNIST dataset [27).
Spiking Neuron Models. The improvement of spiking neuron models provides a general method to upgrade SNNs, which attracts much interest in the research community. The Parametric Leaky Integrated-and-Firee (PLIF) spiking neuron [5] parameterizes the membrane time constant Tm by sigmoid function and can learn Tm by gradient descent during training, showing better accuracy and lower latency than the traditional Leaky Integrated-ande Fire (LIF) neuron with fixed 7m The Gated LIF (GLIF) neuron 3 assembles the learnable gate units to fuse different bio-features in the neuronal behaviors of membrane leakage, integration accumulation, and reset, achieving impressive performance by these rich neuronal patterns. The Complementary LIF (CLIF) neuron [28 introduces the complementary membrane potential into the LIF neuron, effectively capturing and maintaining information related membrane potential decay. However, the sigmoid used in its neuronal dynamics cannot be removed during inference, which is costly for neuromorphic chips. The Parallel Spiking Neuron (PSN) family [15] and the Stochastic Parallelizable Spiking Neuron (Stochastic PSN) [16] are the first parallelizable spiking neuron models. These two models convert the iterative neuronal dynamics non-iterative formulation removing the neuronal reset. Extending from PSN, several variants are proposed. The Parallel Multi-compartment Spiking Neuron (PMSN) 29 introduces multiple interacting substructures enhance the learning ability over diverse timescales. The Parallel Spiking Unit (PSU) (30 adds fully-connected layer with sigmoid activations inside the neuron approximate the neuronal reset. These methods obtain performance gains over PSN in certain datasets, but increase the complexity of neuron models and slow down training speeds.
3 Preliminary
3.1 Traditional Spiking Neurons
In general, spiking neurons can be described by three discrete-time difference equations 5
H f(V[t X(t)),
(1)
S(t] θ (H Vin).
(2)
Vid [[[] S(t)) + Vreset S(tt, hard reset H Vnn S(1), soft reset
[ illustrates the neuronal charging process, where X(4) is the input current at time-step I, extracted from the original spike input via a synapse layer (e.g., convolutional neural network or multi-layer perceptron). H [t] and Vit are the membrane potentials before charging and after resetting
3

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at time-step t, and f is the charging equation specified for different spiking neurons. In Eq, 2 the Heaviside step function, defined as (z)) 1 for x 2 0 and (()) for When H exceeds the threshold Via, spiking neurons will fire spikes, and the membrane potential is reset as in (3) There are mainly two types of reset methods: hard reset will force the V[(] Vreset, while soft reset will subtract VAA from V
((z)
3.2 Parallel Spiking Neuron
Fang et al. [15] found that for commonly used spiking neurons with a linear sub-threshold dynamic Eq.LI), such as the Integrate-and-F (IF) neuron and the LIF neuron, the neuronal dynamics could be expressed in a non-iterative form after removing the reset equation Eq.
T-1 H W X(I..
(4)
O(t for where W is determined by Eq. For example, W[ Tm -111 Tm -1y-- the LIF neuron whose neuronal charging equation is:
H = Tm -) V(t 1] Tm [t).
(5)
Fang et al. 13 extended Eq. 4 by setting W[]][] as learnable parameter, and proposed the PSN with the following neuronal dynamics:
= WX
WER X XERT Vn ER,,
(6)
S - - ViN,,
(7)
where T is the sequence length. For simplicity, we ignore the batch dimension. The PSN does not involve iteration over time-steps. The core computation of the PSN is the matrix multiplication, which is highly optimized on GPUs and can be computed in parallel. Modified from the PSN, the sliding PSN is proposed by [5] with hidden states generating from the last inputs by a shared weight W E R across time-steps, whose neuronal dynamics are as follows:
H Σ W - +1).
(8)
S(4 O 11 V..),
where X 0 for any j < O and l is the order of the neuron. The sliding PSN can process input sequences with variable lengths, and the number of its parameters is decoupled with T. It can output [[] at the time-step i, while the PSN can only generate outputs after receiving the whole input sequence, making it more suitable for temporal tasks.
4 Methods
4.1
Channel-wise and Dilated Convolution
[-0
In PSN and sliding PSN, the weights of the neu- rons are shared across all channels. However, the visualization of feature maps from an SNN con- ducted by [5] implies that the difference between channels is huge, e.g., channel extracts the edges and another channel extracts the background all time-steps (refer to Figure S4 in [5] for more details). This coarse design concept of sharing weights across channels may fail to capture the subtle disparity of features in channels. To solve this issue, we extend the weights channel-wise.
1=2
1=3
(a) Fonnd chlators
(b) Smwtooth dilations
Figure 2: with depths at a slow rate the sliding PSN with (a) fixed dilations and a fast rate in the channel- wise PSN with (b) sawtooth dilations.
The temporal receptive field increases
To capture long-term dependency, the sliding PSN must use a large order resulting in significant rise in computational cost and memory usage. We overcome this issue through the dilated convolution

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1.4
(-)
1.2 Dir)
2ogg
0.5
W
(xg)(x)
2
(0))
W
(a) The workflow of power-of-2 quantizer.
(b) Using Straight-Througg Estimator (STE) to rede- fine round' (z) will cause discrete gradient Q (x)..
Figure Power-of-2 quantization and the gradient behavior of round' (x) under STE.
31 where the convolution no longer processes consecutive inputs (.... X - 2], 1|. Xt)),
instead X[t 2d]. X[t d], [t)), with d > 1 as the dilation rate.
Specifically, denote the input sequence as X E RT'C where is the sequence length and C' is the number of channels. We propose the channel-wise PSN with the following neuronal charging equation:
8-1
H|d = Σ wid X(t (k-1- -d]cc.
(10)
1=0
where W &RCk is the learnable weight, is is the order of the neuron and E N+ is the dilation rate. The channel-wise PSN has identical FLOPSs to the sliding PSN, and the latter can be regarded as simplified case with setting [[]][] W ... W[C 1] and d = 1 in (1).
Additionally, when using multiple layers of dilated convolutions, setting the same dilation rate will lead to the grid effect. An approach to solving this issue is to assign the dilation rate using sawtooth wave-like heuristic [32]. Specifically, when constructing SNNs with channel-wit wise PSNs, we start by initializing with d for the first spiking neuron layer, where the superscript represents the spiking neuron layer index. Then we update d' as:
(11) This approach ensures that after stacking multiple layers, the convolution in the time domain could effectively incorporate inputs from all time-steps. Figure shows how the temporal receptive field increases with depths with (a) fixed dilations d the channel-wise PSN. The order is k 2 in both cases. It can be found that, with increasing depths, both neurons achieve larger temporal receptive fields. However, the sliding PSN can only capture the
d'1 d' mod 3 + 1.
the sliding PSN and (b) sawtooth dilations in
last time-steps with layers, while the channel-wise PSN can capture the last 7 time-steps.
4.2 Multiplication-Fret Neuronal Dynamics
To future reduce the internal computation costs of spiking neurons, introduce the bit-shift operation to supersede multiplication, which has been successfully employed in quantized neural networks In this way, the entire network can perform inference without any multiplication operations. IEEE 754-defined FP32/FP16 values x with powers of (denoted as w), the operation can be converted a lower-bit integer addition the floating-point exponent bits [35 For integers & multiplied by w, it can be achieved by the bit-shift operation, as shown in Eq 12).
33 34
For multiplication
- x << logg(w);
(12)
where << is the left bit-shift operation. In particular, when log, (w) < O, left shifting an negative number log,(n) (w) of bits is actually right shifting >> log2(w)) To employ the bit-shift operation, quantize W in (0 (10) W whose elements the power of 2, by an quantizing function Q:
Wg = Q(W) = sign W 2round()og
(13)
where (2g)(x) is the sign function and returns the sign (1 or -1) of the input æ; round(x) is the rounding-to-neard function. Figure shows the workflow of Eq.
Remarkably, the gradient of round(2) (x) is almost everywhere, and other operations in Eq.
differentiable. The standard practice is to employ the Traight-Thhouu Estimator [36 to redefine its gradient as
cound'(x) = 1.
(14)
5

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Table 1: Parameters and computational costs of different spiking neurons during inference.
Neuron
Params
Operations
PSN
T + T
(T +7) x ADD, T X MUL
Sliding PSN
k
((T) I=k ) 1T) X ADD, ((T' 1 R) MUL
Ours
O. (k++1
(T ) ADD, ((T + ))) X SHIFT
Then the gradient of Eq. is:
('xx) 2round(ogg2(=11))
(15)
However, Eq. 15 is still unstable because (2)) causes jump points and it oscillates around O, shown in Figure 3b which may cause the collapse. To avoid the numerical instability caused by E5. we redefine (1(x) whole Straight-Through Estimator, rather than using Eq. (4)4 solely:
aw 4 aw
= (() =1
(16)
The neuron model is called mul-free channel-wise PSN when using W, in Eq. and the complete neuronal dynamics is as follows, which is illustrated in Figure
HQl Σ E(1 (k- - d[c << (
(17)
Stt|[c [ Vcl
(18)
where VI, E C is the learnable channel-wise threshold, and log, (W,) E Zx is quantized from W by Eq. (3... Note that (Wg ) is solved beforehand and there are no log and multiplication operations during inference. Table presents an analysis of the parameter and operation costs of various neurons, evaluated under 7 time-steps, l order and C channels.
4.3 Training Acceleration
The motivation for proposing parallelizable spiking neuron models is solve the slow training speed of SNNs on GPUs caused by the step-by-step iterations of traditional serial neuron models. Efficient implementation of mul-free channel- PSN, typical 1-D convolution described in (7). requires elaborate consideration. To tackle this, we explore the implementations under two SNN data layouts: time-first and time-last. The fime-first layout (T, N, C..)., widely adopted in SNN frameworks like SpikingJelly (6) accelerates stateless layers by fusing the T (time-steps) and N (batch size) dimensions, while denotes the channel dimension and "..." represents any additional dimensions. In comparison, the time-last layout (N, C,.., T) arranges T the last dimension.
vanilla implementation of (q. leverages PyTorch's 's 1-D Convolution (Convld), which requires the shape of inputs as (N, C, T".. However, for both time-first and time-last layout, it is unavoidable to perform reshape operations (T, NN C....) = (N*, C) and (N, C,.., ..., T) = (N*, C, T) before and after the Convld to satisfy the shape requirement of Convld, where Nx represents the fusion "..." into the N dimension. Note that physical memory is 1-D,
of any additional dimensions meaning that data in nonadjacent dimensions is also stored nonadjacent in physical memory. These reshape operations involve nonadjacent dimensions and require costly memory reading/writing (R/W) operations to create new contiguous tensor in physical memory. Figure illustrates examples of reshape operations with or without memory R/W.
To address the overhead caused by costly nonadjacent reshape operations in the neuron layer, we have developed several acceleration methods. For the time-first layout (T', N, C,..), we propose two methods. One is a custom CUDA kernel that directly performs convolutions along the T dimension. Another leverages Py PyTorch's 's vectorizing map function (Vmap) parallelize computations over the C' dimension, followed by matrix multiplication (MM) to process other dimensions. For the time-last layout (N, C,.,, T), in addition to the custom CUDA kernel or Vump + MM approach as in the time-first layout, we propose two additional methods. One uses the 2-D convolution to implement the 1-D convolution with the weight and stride as handle " dimension. Another applies Vmmp to vectorize the C' dimension and employs Convld to handle other dimensions. Furthermore, also

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Reshape Without Memory R/W
Physical Memory
Layout out
adjacent reshapes
+ Memory R/W
nonadjacent reshapes
fast speed
shape (T,N.C) (3,2,))
slow speed
Layout
memory R/W
Reshape With Memory R/W
MM
shape
mapping between physical memory and layout
shape (N,C.7) (2,43)
(7N. C) (6,4)
Reshape With Memory R/W
Figure 4: Reshape operations involving adjacent dimensions are free of memory reading/writing and much faster than those involving nonadjacent dimensions.
elaborate on acceleration strategies for stateless layers in the time-last layout. Details for accelerating neuron and stateless layers are provided in Appendix and B, respectively.
The choice of acceleration methods for neuron layers affects the data layout, which subsequently influences the performance of stateless layers. Moreover, the acceleration effect dependent on input shapes and GPUs, making the process of selecting acceleration methods inherently empirical. To eliminate the need for manual selection, shown in Algorithm [ At the start of SNN training, the input sequence's shape is determined. Then the algorithm will run benchmark over data layouts and acceleration methods, selecting the configuration with the highest execution speed. In Algorithm [ each ft.; is evaluated through 2m + 1 repeated executions, with the average execution time of the last m iterations serving as the measured runtime for the corresponding acceleration method. As the autoselect method is invoked only once during the entire training phase, its impact on overall train time negligible.
design an autoselect acceleration algorithm, as
Algorithm 1 Autoselect acceleration algorithm
Require: An SNN stacked with L layers { [Mo. Mi,..., ML-1]. The layer Mt has ny optional acceleration methods. The input sequence Xo-
1: for Ω + [time-first, time-last)
2: Reshape X₂ to Ω
3: in =0
4: for 0,1,,,.---
5: for i < 0,1, 0,1,,..,711 -1
6:
Record the current time To
7:
Execute the forward propagation Y, Mi))
8:
Record the current time Ti
9:
Randomize a tensor Zi with the same shape as Y!
Record the current time
11:
Execute the backward propagation (ii)
Record the current time Ts
13:
ti,s = Tı To + Ts T2
Choose the faster method an.ı argmin, (tr,))
15:
la 4- lg + min(4.::)
Outputs: The layout Ω² argming (tn) and the acceleration method ag.,1 for M,
5
Experiments
In this section, we evaluate the mul-free channel-wise PSN on various kinds datasets. We conduct the ablation experiments the order & and demonstrate that the sawtooth dilations can compensate for the long-term dependencies learning ability. Finally, we provide training speed comparison to validate the efficiency of the autoselect algorithm.
5.1 Learning Long-Terme Dependencies
We evaluate the long-term dependencies learning ability of mul-free channel-wise PSN three widely used classification tasks, including the Spiking Heidelberg Digits (SHD) spoken digit dataset
7

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Table Comparison with the state-of-the-an SNN methods on the SHD dataset.
Method
Network
Parallel
Accuracy(%)
Hammouamri et al. (39
Two-layer FC + LIF + Learned Delay
X
95.07 1 0.24
Li et al. (30
Four-layer FC+ + RPSU
92.49
Chen
Twn-layer FC PMSN
95.10
Yarga and Wood 16
Two-layer PC + Stochastic PSN Learned Delay
95.01
Ours
Two-layer FC Mul-free Channel-wise PSN Learned Delay
95.50 = 0.36
Table 3: Comparison of test accuracy (%) of spiking neurons on sequential CIFAR datasets.
Datasets
Ours
PMSN[29
PSN
Masked PSN
Sliding PSN
GLIF
PLIF[S]
LIF
Sequential CIFARIO
91.17
90.97
88.45
85.81
86,70
83.66 58.92
83.49
81.50
Sequential CIEAR 100
66.21
66.08
62.21
60.69
62.11
57.55
53.33
Table 4: Comparison with the state-of-the art ANN and SNN methods on the DVS-Lip dataset.
Method
Frontend
Backend
Accuracy (%)
Tan et al. (88)
Res 18 (ANN)
BiGRU BIGRUTANN)
72.1
Bulzomi et al. [43]
Modiftdd Spiking ResNet+ +
FC (Stateful Synapses)
60.2
ReaNet-18 (ANN)
BIGRU (ANN)
75.1
Dampfhoffer al.
42
Spiking ResNet-18 PLIF
FC (Stateful Synupses)
68.1
SpikGRU/2+
Spiking ResNet-18 PLIF
(Bi-direction
Sigmoid Gates Termary Spikes)
75.3
Modified Spiking ResNet-18
Ours
PC (Stateful Synapses)
70.9
+ Mul-free Channel PSN
371. the sequential CIFAR dataset, and the high ppatia--tmpporal resolution automatic lip-reading DVS-Lip dataset
(38. These datasets cover the types of voices, images, and neuromorphic events.
Comparison between our method and previous SOTA SNN methods on the SHD dataset is shown in Table 2 Specifically, we replace the LIF neurons the SNN-delay architecture [39] with our neurons. With sawtooth dilations and order & = 2, we achieve test accuracy of 95.50 + 0.36% under three seeds (0, 1, 2).
Sequential image classification tasks have been commonly benchmarks to evaluate spiking neurons by 40 29 In these tasks, images are fed into the model column by column, and the number of time-step is equal to the width of the images. We also conduct experiments on sequential CIFARIO and CIFAR 100 datasets. To ensure fairness, we fully employ the network architecture and hyperparameters as [15], only replacing the spiking neurons with ours. The results are shown in Table 3. where the data for PMSN is sourced from [29). maintaining the same architecture as well, while the data for other neurons is sourced from 11). On the sequential CIFAR 10 dataset, our mul-free channel-wise PSN outperforms PSN by 2.72% and PMSN by 0.2%. Additionally, on the sequential CIFARIO0 dataset, it surpasses PSN by 4% and PMSN by 0.13%. Notably, the order of our neurons here we report is 16, while the order of sliding PSN and masked PSN is 32, 2x than ours.
Furthermore, we demonstrate the capability of mul-free channel-wise PSN in processing complex neuromorphic DVS-Lip dataset, which comprises 100 classes and consists of 19871 samples, each containing approximately 10 events with a spatial resolution of 128 x 128. Half of the words in the dataset are visually similar pairs in the LRW dataset 41 (e.g., "America" and "American") The training and testing sets are derived from different speakers, posing challenge for the model to exhibit robust generalization capabilities with respect to speaker characteristics.
Currently, the SOTA accuracy of 75.3% on the DVS-Lip dataset is achieved by (42 using a Spiking ResNet-18 18 with the channel-wise PLIF neurons fronted, SpikGRU2+ backend, and events are integrated into 90 frames (T' = 90). In our experiments, we introduce several modifications to the frontend. We replace the PLIF neurons with our neurons and remove spiking neurons from the pooling layers, referring to this architecture as Modified Spiking ResNet- 18. As Table 4soows, our method achieves 70.9% accuracy and is only second to 42] with SpikGRU2+ backend. It is worth noting that SpikGRU2+ is bi-directional with two groups of separate hidden states, employs sigmoid gates with floating activations, and outputs ternary spikes (-1, 1, 0), which not a pure SNN module and might be difficult to deploy to neuromorphic chips. The accuracy we report here is based on the neuron order k= = 2 and sawtooth dilations, indicating that our method can effectively capture rich historical information with small order even when handling tasks involving long-tin ting-time& sequences.
8

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training duration (sicepoch)
1,000
RNT 887-3645
100
17.000
44002
464084
$G.9
DRUPP
10
173861
32
the number of time-steps
PSN//liding PSN
Vanilla (k 2)
Vanilla (k = 4)
Vanilla (k 8)
Autosclect (k
Autosclect
Autoselect (k 8)
Figure Comparison of training speed on CIFAR100.
5.2
Ablation Study
0.615
Scruncy
To validate that neurons effectively approximate the effect of larger recep- tive field with a smaller order through sawtooth dilations, we conduct ablation ex- periments on the sequential CIFAR 100 and pixel CIFARIC 10 classification tasks.
0.435
0.35
0.335
195N
LB
05
w/ Sentcoth Tilatses
Mal-Prro charned PBX
w/o Sentock, Distons
Figure (a) illustrates the accuracy of mue-free channel-wise PSN and other neurons on the sequential CIFAR100 dataset, with the highest accuracy marked by red *. When the order is 2, the accu- racy of our neuron already significantly surpasses the whole PSN family. Furthermore, when the more, the accuracy remains roughly around 66%. is evident that neuron
order
Sequential CIEARIO0
(b) Pisel CIFARIO
The order-accuracy curves on (a) the sequen- tial CIFARI00 and (b) the pixel CIFAR10.
Figure
order increases is more robust than the sliding PSN, as it does not exhibit the issue of fluctuating accuracy while increasing order.
To evaluate the effectiveness of sawtooth dilations, we conduct an ablation study on the pixel CIFARIO classification task. In this task, images flattened into -in-einensional vectors time series inputs to the network. Thus, the number of time-step is = 1024. We adopt the same network structure (9)] Figure 5 (b) illustrates the accuracy curves with/without sawtooth dilations. can be observed that the accuracy with sawtooth dilations is consistently higher than that without. Additionally, when the order & is small, which practical case for deployment, the accuracy of our neuron with sawtooth dilations is much higher. These results validate that the sawtooth dilations compensate for the effect of large receptive fields when using a small
5.3 Training Acceleration
We compare the training speed of PSN and the mul-free channel-wiss PSN implemented by the autoselect Algorithm The vanilla implementation, using reshape and Convld operations for neuron layers and time batch dimension fusion for stateless layers, is also compared. The experiments are carried out on a Debian GNU/Linus (bullsseye) server with an Intel(R) Xeon(R) Platinum 8336C CPU, an Nvidia A 1100-XX4-80CE) GPU and 32GB RAM. Following the original PSN 15 settings, we use the batch size of 128 on the CIFAR dataset.
The training duration (slepoch) of different neurons under different order k on CIFARI00 is shown in Figure 6 Note that both PSN and sliding PSN implemented by matrix multiplication in GPUs 15). their speeds are identical and decoupled with k. The results show that our autoselect algorithm greatly improves the efficiency of mul-free channel-wise PSN and achieves much faster training speed than the vanilla implementation. When T < 4, our method is comparable to PSN/sliding PSN. this case, the matrix is nearly stripped in PSN/sliding PSN because T much less than other dimensions, causing inefficient matrix multiplications. When T continuously increases, our method is slower, which caused by the fact that the quantization induces additional overhead, and memory R/W caused by Vmap operations for processing inputs/outputs in our SNNs is slower than

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Table 5: Step-by-step inference memory on the sequential CIFARIOO (T 32) dataset.
Neuron
k
Accuracy(%)
Memory(MB)
Sliding PSN
32
62.11
2635
Ours
65.77
547
Table 6: Computational energy comparison on single CIFARI00 Image.
Neuron Layer
Synaptic Layer Operations
Total Energy
Neuron
Operations
Energy (nJ)
Energy (nJ)
(nJ)
1.91 x 10' MUL
0.041 x 10 FLOPs
PSN
88,56
3.06
91.62
1.97 x 107 ADD
3.194 x 10 SOPs
7.32 SHIS
0.041 x 10 FLOPS
Ours
8.08
2.58
10.66
7.92 x AD
2.660 x 10t SOPs
the dimension fusion. Nonetheless, the speed gaps not significant. The autoselect algorithm itself introduces only negligible time overhead, contributing 1.17%, 0.39% 0.27% for T 2, 32, respectively. Further results for different batch sizes and GPUs can be found in Appendix G
5.4 Inference Memory Analysis
Both our approach and sliding PSN require storing an input sequence whose length is proportional to the neuron order k. According to [15], sliding PSN typically needs large k to maintain stable performance on long-term dependencies. In contrast, our method can achieve more stable and better performance with a much smaller k, as shown in Fig. By substantially reducing the required neuron order, our approach shortens the length of the stored imput sequence and significantly lowers memory consumption during inference. As demonstrated in Table this leads to substantial reduction in memory overhead for storing input sequences, making our solution more suitable for deployment on resource-constrained devices.
5.5 Inference Energy Estimation
Assume implemented on the 45 nm CMOS technology, where 32-bit floating-point (FP32) multi- plication (MUL) and addition (ADD) operation consumes 3.7 pJ and 0.9 pl, respectively [44 In comparison, for the shift operation of 32-bit fixed-point (FIX32) and a power-of-two number,
requires only 0.13 pJ 44 For the multiplication of a FP32 number with power-of-two number, can be performed by one single lower-bit integer addition, which also energy efficient (35).
Here we use the FIX32 shift energy as approximation. Based on the sequential CIFARIOO 100 mod- els (see Appendix D). we estimate the average computational energy of PSN and our method for processing a single CIFAR 100 image, shown in Table Our method achieves nearly 9 lower energy consumption compared to PSN, demonstrating a significant advantage in hardware efficiency. Notably, energy estimation considers the cost of neuronal layers, whereas most previous studies only account for synaptic layers. Moreover, we observe that for PSN, the energy consumption of the neuronal layer is significantly higher than that of the synaptic layer, which is mainly due the dense floating-poii point matrix multiplications involved. Details of the energy estimation procedure can be found in Appendix F
6 Conclusion
In this paper, we introduce novel parallelizable spiking neuron model named mul-free channel- wise PSN, which employs the channel-wise convolutions to process the input sequences, avoids the large neuron order by sawtooth dilations, and gets rid of floating multiplications by efficient bit-shift operations. The considerations of accelerating the training of SNNs with the proposed neuron models are also discussed in detail. Experimental results demonstrate that mul-free channel-wise PSN achieves significant performance improvements in temporal classification tasks, showcasing its superior capability to capture long-term dependencies. Our methods solve the dilemma of performance and computational costs of spiking neuron models, and our acceleration methods will benefit future research practical reference.
10

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Acknowledgments and Disclosure of Funding
This work is supported by National Science and Technology Innovation 2030 Major Project (No. 20252D0215501), Guangdong S&T Programme 2024B0101010003 and National Natural Science Foundation of China (62236009).
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Appendix
A
Acceleration Details of Spiking Neuron Layer
A.1
Acceleration Methods
Based on the aforementioned background, we design the following accelerating implementations as candidates:
(1) Time-last Vmap Convld: this method uses the vectorizing map function (Vmap) in PyTorch to vectorize Convld to process the input sequence with the (N, C, ()) layout over the "*" dimension. The reshape operations (N, T) dimensions are adjacent physically.
C, are nearly cost-free because the reshaped
(2) Time-last Conv2d: this method is similar to the implementation (I), but processes the input sequence with the (N, C, *; T) by Conv2d and sets the weight and stride in the dimension as 1, rather than by Vmap.
(3) Time-first/last Vmap MM: this method uses Vmap to vectorize matrix multiplication (MM) to process inputs over channels (c in Eq. (17). Refer to Appendix A..2 for more details about how the weights for MM are generated.
(4) Time-first/last + Custom CUDA Kernel: this method avoids reshape operations and can be used for any memory layout. However, the convolutions in PyTorch are highly optimized, i.e., implemented by the official NVIDIA CUDA Deep Neural Network (cuDNN) library, which might be much faster than custom implementations. Refer Appendix A..3 for more details.
Note that if the spiking neuron layer implementations adopt the time-last layout, the stateless layers should also use the same layout. Otherwise, reshape operations between time-first and time-last layouts will cause great latency. Correspondingly. the time batch dimension fusion method to accelerate stateless layers in SpikingJelly cannot be applied. In Appendix B we fully discuss the acceleration method of the stateless layer for the time-last layout.
A.2
Details of Time-firstlast + Vmap + MM
In Eq. 17). weight of the standard 1D convolution W, y is shaped [C, R.. The standard 1D convolu- tion operation could be implemented by matrix multiplication and vectorizing map. When the input sequence X R arrives, where the sequence length T is known, for the time-first data layout, the weight matrix A E RCXXx can be generated as:
17),
W [ - 1- -7 i- sisii & (i 1)%d=
(19)
o, otherwise
where []] means the slice operation.
Similarly, for the time-last data layout, the weight matrix A E RCXXXT can be generated as:
W W - 1- i i- 1) < < & (i j)%d =
ABDI
(20)
0, otherwise
Applying the vectorizing map the input sequence and the weight matrix across the channel dimension, the membrane potential H can be calculated through the matrix multiplication operation channels in parallel:
A [c] X [c], time-first layout
c
(21)
[[c] A[c] [c], time-last layout
A.3 Details of Time-first/last Custom CUDA Kernel
Suppose X is the input sequence, H is the hidden states, and 8H is the gradient with respect to H, obtained by automatic differentiation in PyTorch, all of them are shaped as N, C, H) or
14

---

(N, H. W, T). Suppose W and b are the weight and bias of the convolution, shaped as [C, k] and [C], respectively.
The process of forward propagation can be represented as:
H pad( X (k: 1, 1,0)) W + b,
(22)
where pad represents padding l zeros on the left X over the time dimension T, and * denotes the convolution operation the T dimension of X using W.
The process of backward propagation can be represented as:
aL
ax pad(O* ,0,, k 1)) + fWi
(23)
0L
pad(X, (k - 0)) 8
(24)
OW
öL Σ
8 k,n,ww
(25)
0b
L,n,W.w
where (li) represents flip W left and right along the is dimension.
Beyond PyTorch (cuDNN), a custom CUDA implementation for two data layouts also considered. To avoid the reshape and incident memory copying, we design CUDA kernels by OpenAl Triton for processing both data layouts directly. Specifically, we manually implement the Eqs. (2 25
using the Triton framework. We design custom autograd function, where the aforementioned kernel functions are called in the forward and backward methods. Note that the convolution operation in (23) is consistent with that in Eq. (22), so the triton kernel function remains the same. Taking the time-first layout as an example, Eq. (22) and (24) could be implemented as Algorithms 2 and respectively.
Algorithm 2 Triton forward kernel
Input: The input sequence pointer Xptrs weight matrix pointer W Werr, the output sequence
pointer H point to the first address of tensors, shaped ad [T - k - 1, C, H, W), [C, k] and (T, N, C, H, WJ, respectively.
1: Utilize the triton autotune method to determine the BLOCK SIZE NHW (BN) and BLOCK SIZE C(BC)
2: Calculate the offset Xoffact, Wof and Haffset of each thread, shaped as [BN, BC, k).
[1, BC, 1, and [BN, BC,T), respectively
3: Load values of Xper+ + +Xoffsct and Wpt + Woffset from memory to SRAM tensors X and W
4: Utilizing the broadcasting mechanism, perform the element-wise multiplication of X and W
5: Sum the output H along the k dimension
6: Store the values of H to Hpt + Hoffeet address
Algorithm 3 Triton grad of weight kernel
Input:
The grad of output pointer Optr the input sequence pointer Xptr, the grad of weight pointer
Wotr: point to the first address of tensors, shaped ad [7, N, C, W], (T + - N,N, H, W) and [C, respectively.
Utilize the triton autotune method determine the BLOCK BLOCK_SIZE_CLK
BLOCK_SIZE SIZE NHW(BN) and
2: Calculate the offset Onffsets Xoffset and Woffset of each thread, shaped as [BN, BC, 1],
[BN, BC, ki) and [BC, respectively
3: Load values Oper + Ooffset and Xptr + Xoffset from memory to SRAM tensors and X
4: Utilizing the broadcasting mechanism, perform the clement-wise multiplication of O and X
5: Sum the grad of weight W along the and h dimensions
6: Atomic add the values of W to W ptr + Woffset address
B Acceleration Details of Stateless Layer
Stateless layers include the convolutional, batch normalization, pooling, and linear layers. When using the time-first data layout, the stateless layers can be accelerated by fusing the time dimension and the
15

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batch dimension in SpikingJelly. More specifically, the data layout changes as (T,N,*) = (TN,*) before and after processing of the stateless layers. Then GPUs regard the time-step dimension as the batch dimension, leading to fully parallel computing over time-steps. It is worth noting that the dimension fusion is nearly no cost because the time and batch dimensions are physically adjacent in memory. The reshape operation only changes the view of tensors and does not involve memory copying.
When using the time-last layout, the dimension fusion method of SpikingJelly cannot be applied except for the batch normalization layer, which only requires that the channel dimension be the 1-th dimension. Both layouts can be satisfied by a reshape without additional memory R/W. For the convolutional and pooling layer. we introduce two new methods: the vectorizing map provided in Py PyTorch and the high- high-dimension convolution/pooling that has been used in the Lava framework, a software framework for neuromorphic computing.
The vectorizing map vectorizes the stateless layers to process the input sequence with the (N, T) layout over the last dimension T, then the computation over time-steps is in parallel. This method actually implies reshape operation (.. = (V..)....) when splitting and concatenating the sequence. The high-dimension convolution/pooling uses the (n + 1)-D convolution/pooling to implement the n-D convolution/poollee dimension. This method is also in parallel, while the main drawback is that the high- digeniimnnsoon convolution/pooling is complex and not as efficient as the dimension fusion method [6].
with a weight of I and a stride of 1 in the additional
C Neuron Quantization
To reduce the internal covariate shift along the temporal and batch dimensions, and increase the numerical stability of the model, use batch normalization to implement the learnable threshold Vaa Eq. 18 could be rewrite as:
stt[cc = (111 Vogld +e
H [ uB|c] Volle
+ stc)
(26)
where 7 E RC and B E RC are the learnable weight, initialized as 1 and -1. μg E RRC and oß RC are the mean and variance of the input over the dimension C.. Specifically, at train time, they are the mean and biased variance of the input sequence; at inference time, they are the moving average of the mean and unbiased variance of the input sequence on the training stage, which means μg and oi are invariant during inference.
Since quantization goal is to the efficient bit-shift operation replace the multiplication, the convolution layer and the batch normalization layer could be fused to reduce computation during inference, so we need to quantize the fused weights during training. The formula for the fusion of convolution and batch normalization can be represented as follows:
W
W
(27)
V B
+E
bj 3
(28)
V +
Thus, W in 13) actually W in Eq. To implement the quantization of fused weight, during the training stage, input sequence X is first passed to the convolutional layer, resulting in the intermediate variable T update the #ı and o in Eq.(27 (7) and Eq. Then, we use W as W in Eq. (3) and by as Vn in I8) perform the convolution operation on the input X twice. After the training is completed, lu and o is fixed, so we could directly use the quantized W, and by as the weight and bias of the convolution layer, performing the convolution operation only once.
D Network Structure
Table 7 illustrates the details of the network structure for different datasets. c128k3s1 represents convolution layer with output channels = 128, kernel size = 3 and stride = 1, BN is the batch normalization. SN is the mul-free channel-wise PSN, APk2s2 is the avg-pooling layer with kernel
16

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size = 2 and stride 2, FC256 represents the fully connected layer with output feature = 256. RB128 is the residual block with output channels 128, Dcls256 the dilated convolution with learnable spacings with output channels = 256, DP is the dropout layer. LIF( a LIF spiking neuron the threshold le9, and the membrane potential the output, which could be thought of the moving average of the input current. 3D 00_c66k5777s120 12252333 represents the 3D) convolution layer with output channels = 64, kernel size = (5, 7, 7), stride (1, 2) and padding 3, 3). AAPkl is the adaptive avg-pooling layer with output feature 1. Stateful FC 100 is an FC layer with stateful synapses.
represents
Table 7: Network structure for different datasets.
Dataset
Network structure
Sequential CIFARLO/CIFAR Pixel CIFARIO
FELISBRRSS-I1113332224444444223 (RB256) $2-FC10
FC128-BN-SN-
SHD DVS-Lip
100__4445771122223-P33332---pp (2- 3D 3D_
-DP-Stfflll FC 100
E
Setting of Experiments
The main parem--arreeters for different datasets are shown in Table Other training options are listed follows.
Sequential CIFAR The data augmentation techniques include random mixup with = and 0.2, random cutmix with
and 1, random choice between the mix methods with p= = 0.5, random horizontal flip with = 0.5, trivial augmentation, normalization, random erasing with p 0.1, and label smoothing with the amount 0.1 [15]. The number of channels 128. The surrogate function is the arctan surrogate function o 2(1+()
with a
Pixel CIFAR All parameters and experimental settings are the same as Sequential CIFAR.
SHD Augmentation methods include spatio jitter with var 0.55, uniform noise with number 35, drop event with p 0.05, drop event chunk with 0.3 and max drop chunk length 1 = 0.02. The surrogate function is also the arctan surrogate function with a
DVS-Lip The data augmentation techniques include center cropped size 96 x 96, then random cropped size = 88 x 88, random horizontal flip with = 0.5, 2D spatial mask with mask num = 4 and maximum length= 20, random choice between zoom in and zoom with p 0.5 and max scale = 26, temporal mask with mask num = and maximum length = 18 [2]. The surrogate function is (z) I with 10.
Table Training pyree-passmeters for different datasets.
Dataset
Optimizer
Batch Size
Epoch
Leurning Rate
Scheduler
Sequential CIFAR10/100
AdamW
128
256
0.001
CosallAnna
Pixel CIFARIO
AdamW
128
128
0.001
Cosine AnnealingLL
Adam
5e-4 for weights
Annealinnn .. for weights
SHD
(wd=le-5)
128
150
0.05 for delay
OneCycleLR for delay
Adam
fixed 3e-4 for 0- 100 epochs
DVS-Lip
(wd=le-4)
32
200
(1e-4, 5e-6) for 100-200 epochs
AonaalAAne
Details of the Energy Estimation
By combining the neuron operation counts in Table with the corresponding per-operation energy consumption, the theoretical neuronal energy consumption can be estimated, shown in Table 9
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Table Operations and energy of different spiking neurons during inference.
Neuron
Operations
Energy (pJ)
PSN
(T + x)x ADD, 7 MUL
4.67 + 0.97
Ours
((T + 2 kk
+ T)x ADD, ((T 2²² k) SHIFT 1.03(T + 1 k 0.97
When the neuron order k reaches its maximum value T, the maximum theoretical energy consumption of our neuron 0.5157 + 1.4157, which is approximately 9x lower than that of PSN for large T. This result clearly demonstrates the superior energy efficiency of our approach in hardware- constrained scenarios.
Further, we use the sequential CIFARI00 Network structure (see Appendix D more details) to evaluate the energy consumption on single CIFAR100 Image. Following [II], we use Eq. (29) to calculate the energy of synaptic layers, where FL NCnny is the FLOPs of the first layer to encode static RGB images into spike-form, N the number of convolutional layers, and M the number of fully connected layers. fr in Eq. 30 is the firing rate of the input spike sequence of every synaptic layer, and here is the average value of the trained network across the entire test dataset. Assume the MAC and AC operations are implemented on the 45nm hardware, EM and EAC = 0.9p.J Following the experimental setup specified in Table 3 the neuron order & of neuron is 16. Detailed energy analysis is shown in Table where the FLOPs and SOPs of the synaptic layers refer to the FLSNN Cony and (> respectively.
4.6pJ
Coav
SOP SNN Conv +
> .
SOP SNN the Eq. 29
N Σ
M
Esynaptic = EMAC x FL'NN Cone + EAC
SOP
SNN Conv
+
Σ
SNN
(29)
1==
m=1
SOPs(I) = fr x FLOPS()
(30)
G Experimental Results
Table 10 presents the original data depicted in Figure illustrating the performance of mul-free channel-wise PSN across varying orders and datasets.
In addition, we report extra results on the H20 GPU and the A100 GPU with different batch sizes in Tab The results and conclusions Notably, the training duration of our neuron is with the quantization operation, i.e., perform the convolution operation twice, so is inherently slower than PSN on the training stage.
consistent with using the A100 GPU and batch size 128.
For the training speed across different neuron implementations (PSN, vanilla, and autoselect), each method is trained for two epochs, and the training durations of the second epoch In this way, the results have accounted for statistical validity and warm-up GPUs and eliminated the influence of model loading and other initialization processes. Hence, the reported speed is the speed at the steady state.
as the results.
0.6
0.4
0.2
spoch
spoch
Training
Test
Figure 7: The training and testing accuracy curves with gradient of Eq. 14 on the DVS-Lip Dataset.
18

---

Table 10: Test aceuracy (%) of the multiplication- free channel-wise PSN, corresponding to the data presented in Figure
Dataset
Sequential CIFAR100
Pixel CIFAR 10 (w/o dilation)
Pixel CIFAR 10 (w/ dilation)
Order
1
50.24
45.15
45.33
2
63.25
66.21
68.96
3
65.21
69.33
74.21
4
65.77
72.97
76.82
5
66.45
73,90
77.31
65.96
75.44
78,92
7
66.58
75.21
79.49
8
66.97
76.72
81.71
9
66.48
79.97
82.67
10
66.38
79.75
82.36
11
66.87
79.80
82.74
12
66.53
79.39
83.24
13
66.06
79.65
82.85
14
67.15
80.07
83.58
15
66.60
79.37
83.32
16
66.21
79.83
83.65
17
66.73
84,89
18
66.32
80.51
84,84
19
66.41
80.89
84,28
20
66.10
80.56
84.05
21
66.41
81.19
84.04
22
66.23
81.44
84.43
23
66.45
81.00
84.01
24
65.98
80.71
84.11
25
66.56
80.78
83,49
26
66.53
81.26
82.85
27
66.30
81.61
82.60
28
66.40
81.58
82,33
29
66.59
81.70
82.81
30
66.40
80.90
82.71
31
66.62
82.11
82.59
32
66.36
81.84
83.07
Table 11: Training durations (s/epoch).
Method
T= T'
T 8
T 32
GPU=1120, batch size 128
PSN
10.07
16.79
27.47
50.27
102.42
Autosclect (k 2)
12.63
22.25
40.99
84.65
153.95
Autoselect (k 4)
23.09
42.85
83.22
154.06
Autoselect (8 8)
45.33
81.44
154.44
GPU=A100, batch
PSN
20.11
23.57
32.88
50.13
88.62
Autoselect (A: = 2)
29.83
39.73
56.40
105.82
215.23
Autoselect (k: 4)
35.11
50,91
104.40
225.88
Autoselect (A:
52.17
96.41
187.18
GPU=A10U, batch size = 64
Autosclect
13.72
17.46
27.47
45.84
85.79
Autosclect (I: 2)
19.75
31.94
47.13
96.79
197.29
Autoselect (I:
32.98
47.55
101.88
217.38
Autoselect (f)
48.86
105.86
245.72
In Figure 3b we mention that the gradient of Eq. (5) has jump points, which is detrimental to the network. On the sequence CIFAR dataset, we find that the network still able learn quite well. However, on the DVS-Lip dataset, as shown in Figure 7 using the original ste gradient causes the network to crash, resulting in the training and testing aceuracy suddenly dropping to 1%. The reason is that the gradients appear to be the Not a Number (NaN) values.
19

---

H
Limitations
Although we have designed multiple acceleration methods that significantly improve the training speed of the vanilla mul-free channel-wise PSN, its training speed is still slightly slower than that of PSN. This is mainly due to the additional overhead induced by quantization, and the memory read/write operations caused by Vmap during input/output processing in SNNs being slower compared to dimension fusion. Nonetheless, the speed gap is not significant.
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Reviews:
[{"review_id": "bgyDUuBMkp", "reviewer": "Reviewer_ZuQM", "summary": "Traditional neuron models involve iterative step-by-step dynamics (implemented like RNN) which slow down computation. For some popular neuronal dynamics (like IF and LIF), one can express these dynamics in a way that allows for parallel computation as noted by Fang et al. [15]; in particular one can calculate how the membrane potential evolves over time without the resetting mechanism as in eq. (6) and calculate the binary spikes as in eq. (7) with learnable thresholds whose dimension is T (the number of time steps). The sliding PSN proposed by [15] uses shared weights of size k which convolve over the input sequence, allowing this model to use fewer weight parameters and handle variable length sequences (and not just T). This work builds on the sliding PSN of [15] by making the following changes: 1) first, this work uses a dilated convolution processing non-consecutive inputs and sets the dilation rates using a sawtooth wave-like heuristic (eq. (11)) and 2) replace multiplication with bit-shift operations and 3) quantize the the weights W. The authors also propose an autoselect algorithm (Algorithm 1) to choose amongst different acceleration options, which depend on data input shapes and GPUs. Finally, the authors apply these changes to SOTA SNN models for experimental validation, using the same architecture and hyperparameters as in [38] and [15] and benchmarking the results on a few datasets including SHD, (sequential) CIFAR10, CIFAR100, and DVS-Lip.", "questions": "In Figure 6, when comparing to PSN/Sliding PSN it is explained that this work is slower for T > 4. In the introduction, it is explained that the purpose of this work is to address the computational and memory limitations of sliding PSN. Could the authors perhaps comment more on these tradeoffs?", "limitations": "yes", "rating": 4, "confidence": 1, "soundness": null, "presentation": null, "contribution": null, "strengths": "", "weaknesses": "", "quality": 3, "clarity": 3, "significance": 3, "originality": 2, "strengths_and_weaknesses": "Strengths:\n- The experiments seem to show SOTA performance on a few benchmarks (namely SHD, CIFAR10, CIFAR100). \n- The method appears to be practical and (relatively) simple, which seems like it would be useful to many practitioners if the code/implementation were to be integrated into existing libraries.\n\nWeaknesses:\n- I feel that a lot of the ideas in this paper are not necessarily very “new” but pieces together many existing (known) techniques and put them together on top of the existing sliding PSN model/framework\n- The justification for using the straight-through estimator for Q’(W) (and not considering any other methods) was a bit weak, especially considering the previous point. (STE is very simple to use is a first option to try.) Other methods for dealing with discontinuous and almost zero everywhere gradients exist, such as through using smooth surrogates. \n- The improvements in test accuracy seem material but mild, and the uncertainty/error bars are not always reported for the authors’ work (I understand it may not always be available in other works, but having a sense of how tight the error bars are would help interpret some of the results), such as in Table 3 and 4.\n- There doesn’t seem to be any indication that the code will be released publicly, which I think if done would strengthen the paper.", "was_revised": true, "final_justification": "Reviewers have responded to my concerns and other reviewers' concerns with additional experiments which highlight the energy savings and memory-savings of the proposed method (at inference-time only, but that is the common use-case for SNN anyway). Although I am still a bit concerned that the work is not hugely novel, I think it can be a useful paper for practitioners to refer to (e.g., for using the code which will later be released, techniques for their own implementations).", "rebuttal": "> **S1:** ... it would be useful to many practitioners if the code/implementation were to be integrated into existing libraries.\n>\n> **W4:** There doesn’t seem to be any indication that the code will be released publicly, which I think if done would strengthen the paper.\n\nThanks for your recognition. To ensure reproducibility and facilitate the review process, we have submitted our code as supplementary material, and the code will be made publicly available upon acceptance. Additionally, we plan to modularize the neuron implementation and contribute it to SpikingJelly [1] to make it easily accessible to the community.\n\n> **W1**: I feel that a lot of the ideas in this paper are not necessarily very “new” but pieces together many existing (known) techniques and put them together on top of the existing sliding PSN model/framework\n\nOur core contribution does not lie in inventing a wholly new, isolated component, but rather in the first systematic and non-trivial integration of several established techniques to address key bottlenecks in parallelizable SNN models such as Sliding PSN:\n\n1. **Architecture – Resolving the Channel Mixing–Efficiency Trade-off:** A key limitation of PSN and Sliding PSN is their use of channel-shared neuron parameters, which restricts their ability to capture channel-specific features (see [2] Fig. S4). In contrast, our approach incorporates **channel-wise convolutions** into its neuronal dynamics. This design empowers each channel to learn independent temporal characteristics, thereby enhancing the model's representational power **without increasing FLOPs**. As demonstrated in Table 2, our method substantially outperforms both PSN and Sliding PSN, validating the effectiveness of this improvement.\n2. **Efficiency – Resolving the Receptive Field–Resource Trade-off:** Sliding PSN requires a large neuron order $k$ to capture long-term dependencies, which limits its usability on resource-constrained hardware. We address this by introducing sawtooth dilations, which efficiently expand the temporal receptive field even with small $k$ (see Fig. 5b). Additionally, we employ bit-shift operations to replace costly multiplications in neuron dynamics, achieving substantial gains in hardware efficiency—reducing theoretical energy and area by $8×$(see lines 69–72).\n3. **Practical Implementation – Bridging Theory and Real-world Efficiency**: We investigate multiple acceleration strategies that significantly improve the training speed of our neuorn in GPU environments. In spiking neural networks, synaptic layers primarily process spatial information, while neuron layers are tasked with modeling temporal dynamics. **Importantly, as  the neuron design becomes more complex, the memory layout challenges discussed in this paper tend to appear. The solutions and guidelines we present could serve as a valuable reference for a wide range of advanced and complex spiking neuron models.**\n\nIn summary, our work systematically addresses the key challenges of performance and efficiency in the PSN model series. We introduce a fundamentally new parallel spiking neuron that achieves state-of-the-art accuracy across multiple datasets. Critically, our model is not only **highly efficient for GPU-based training** but also **optimized for deployment on resource-constrained edge devices**.\n\n> **W2:** The justification for using the straight-through estimator for Q’(W) (and not considering any other methods) was a bit weak, especially considering the previous point. (STE is very simple to use is a first option to try.) Other methods for dealing with discontinuous and almost zero everywhere gradients exist, such as through using smooth surrogates.\n\nFor the round function, the most straightforward STE approach is as defined in Eq.(14). However, this leads to discontinuous gradients (see Fig. 3b), which can cause training to collapse (see Appendix F, Fig. S1). Therefore, we apply STE for Q'(W) to ensure stable training. Furthermore,  as shown in **Table R3**, the overall performance loss from power-of-two quantization and the STE surrogate gradient is minor and acceptable.\n\n> **W3**: The improvements in test accuracy seem material but mild, and the uncertainty/error bars are not always reported for the authors’ work (I understand it may not always be available in other works, but having a sense of how tight the error bars are would help interpret some of the results), such as in Table 3 and 4.\n\n**Regarding the magnitude of accuracy improvements:**\n\nWe would like to highlight that the contribution of our work is best understood from two key perspectives.\n\n1. Our primary objective is to **design a multiplication-free, hardware-friendly neuron**. By replacing costly floating-point multiplications with efficient bit-shift operations, our method achieves accuracy comparable to SOTA spiking neurons that rely on complex computations. This demonstrates a superior trade-off between accuracy and hardware cost.\n2. More importantly, our model achieves **a significant performance improvement** over the most relevant baseline, Sliding PSN. As reported in Table 2, our method improves accuracy from **86.70%** to **91.17%** on Sequential CIFAR10, and from **62.11%** to **66.21%** on Sequential CIFAR100. These results provide strong evidence that our architectural optimizations result in substantial performance gains.\n\n**Regarding the stability of results and error bars:**\n\nIn response to your suggestion, we have conducted additional statistical experiments on PSN and our method for the task in Table 3 (with five random seeds, 0–4), and on our method for the task in Table 4 (three seeds, 0–2). The results are presented in Table R1. Due to the high computational cost of training on DVS-Lip, we did not conduct extra runs for all baselines. As shown in Table R1, our method demonstrates very low deviation across runs, indicating strong robustness.\n\n| Datasets            | seed      | Baseline            | Ours             |\n| :------------------ | :-------- | :------------------ | :--------------- |\n| Sequential CIFAR100 | 0,1,2,3,4 | $61.79\\pm0.47$([3]) | $66.5\\pm0.2$     |\n| DVS-Lip             | 0,1,2     | $68.1$ ([4])        | $70.68 \\pm 0.11$ |\n\nTable R1: Comparision of average test accuracy with $\\pm$ standard deviation (%).\n\n> Q1: In Figure 6, when comparing to PSN/Sliding PSN it is explained that this work is slower for T > 4. In the introduction, it is explained that the purpose of this work is to address the computational and memory limitations of sliding PSN. Could the authors perhaps comment more on these tradeoffs?\n\nTo achieve multiplication-free computation, during training we quantize the weights to power-of-two (details see Appendix C). This requires an additional forward and backward pass in each training step to reduce quantization error (while inference only needs one forward pass). Besides, practical implementations with operations such as vmap also incur certain memory read/write overhead, resulting in somewhat slower training compared to Sliding PSN. Importantly, the speed gap remains moderate and acceptable. \n\nHowever, we believe that these minor increases in training cost are justified by the substantial improvements in hardware efficiency and memory usage during inference.\n\n1. On the hardware efficiency front, we replace multiplications in neuron dynamics with bit-shift operations, substantially improving hardware friendliness—this yields theoretical reductions in both energy and area consumption (see lines 69–72), addressing the **computational bottleneck** of Sliding PSN for edge deployment.\n2. Regarding memory usage, during inference, both our approach and Sliding PSN require storing an input sequence proportional to neuron order $k$. According to [3], Sliding PSN typically needs a large $k$ to achieve stable performance for long-term dependencies. In contrast, our neuron can converge with a much smaller $k$ and still achieve substantially better performance. For example, Sliding PSN could only achieve $62.11\\\\%$ test accuracy with order $k=32$ on the sequential CIFAR100 dataset, while our method could attain $65.77\\\\%$ test accuracy only under $k=4$ (Figure 5a, Appendix Table 7). Cause our approach dramatically reduces the required order $k$, it greatly reduces the length of the input sequence needs to be stored. As a result, our method requires much less memory during inference (Table R2, **547MB  vs. 2635MB, 4.8× reduction**), significantly reducing **memory limitation** for storing input sequences and making the solution more suitable for resource-constrained devices.\n\n| neuron      | $k$  | Accuracy(%) | Memory (MB) |\n| ----------- | ---- | -------------- | ----------- |\n| Sliding PSN | 32   | 62.11          | 2635        |\n| Ours        | 4    | 65.77          | 547         |\n\nTable R2: **Step-by-step inference memory** on the sequential CIFAR100 ($T=32$) dataset.\n\n```C++\n[1] Fang W, Chen Y, Ding J, et al. Spikingjelly: An open-source machine learning infrastructure platform for spike-based intelligence[J]. Science Advances, 2023, 9(40): eadi1480.\n[2] Fang W, Yu Z, Chen Y, et al. Incorporating learnable membrane time constant to enhance learning of spiking neural networks[C]//Proceedings of the IEEE/CVF international conference on computer vision. 2021: 2661-2671.\n[3] Fang W, Yu Z, Zhou Z, et al. Parallel spiking neurons with high efficiency and ability to learn long-term dependencies[J]. Advances in Neural Information Processing Systems, 2023, 36: 53674-53687.\n[4] Dampfhoffer M, Mesquida T. Neuromorphic lip-reading with signed spiking gated recurrent units[C]//Proceedings of the IEEE/CVF Conference on Computer Vision and Pattern Recognition. 2024: 2141-2151.\n```"}, {"review_id": "KV5mJz7qDA", "reviewer": "Reviewer_DWxU", "summary": "This paper redesigns the core neuron architecture of SNNs by combining per-channel separable convolution, zig-zag dilated convolution, and replacing multiplications with shift operations—augmented by an automated benchmarking system to select the optimal implementation - thereby achieving a multiplier-free design that efficiently captures long-range dependencies while remaining hardware-friendly. Experiments on SHD, sequential CIFAR, and DVS-Lip tasks reach or approach state-of-the-art performance, and training speed rivals that of traditional matrix multiplication.", "questions": "1.\tBy replacing all weights with power-of-two shifts, you remove multipliers—but real weights can be any real number. Have you quantified how much representational capacity you lose, especially for small or negative weights?\n2.\tHow much memory do operations like reshape, depthwise + pointwise convolutions, and dilation actually consume in large models or with long sequences? The paper only reports training speed, but I believe training memory usage is what most researchers care about.\n3.\tDepth-wise + pointwise separation slashes parameters, but it also forces each channel’s temporal filter to be independent before mixing. Could that break important cross-channel correlations in the input spike train? \n4.\tIn the Introduction, the authors claim that the method achieves significant energy savings, but the paper provides no analysis or experiments on energy consumption, nor is any such content found in the supplementary materials.\n5.\tWhile accelerating training is certainly important, for deployable methods acceleration during inference is even more critical. Have the authors evaluated whether this method’s inference speed offers sufficient advantages over PSN-based or sliding-PSN models with comparable parameter counts", "limitations": "Yes.", "rating": 4, "confidence": 3, "soundness": null, "presentation": null, "contribution": null, "strengths": "", "weaknesses": "", "quality": 3, "clarity": 4, "significance": 3, "originality": 3, "strengths_and_weaknesses": "Strengths: \nThe manuscript is well-written, logically rigorous, and clearly presented. This work makes a significant contribution to the field of parallel SNN neurons by avoiding expensive multiplications to accelerate and reduce the energy consumption of SNN computations, while also achieving competitively strong algorithmic performance.\n\nWeaknesses: \nEven though I think this paper is excellent, the method lacks evaluation on more advanced architectures such as Spikformer.", "was_revised": false, "final_justification": "", "rebuttal": "> **W1**: Even though I think this paper is excellent, the method lacks evaluation on more advanced architectures such as Spikformer.\n\nWe note that existing works related to parallel neurons [1-5] all do not conduct experiments on SNN-based Transformer architectures. Therefore, our work has also not conducted experiments on Spikformer-like architectures.\n\n> **Q1**: By replacing all weights with power-of-two shifts, you remove multipliers—but real weights can be any real number. Have you quantified how much representational capacity you lose, especially for small or negative weights?\n\nFrom the perspective of Taylor expansion, [6] suggests that small weights have a limited effect on network performance, which is also the theoretical foundation of pruning. Besides, to our knowledge, there is no theoretical analysis in the literature regarding the potential loss of representational capacity caused by power-of-two quantization of weights. Thus, we rely on empirical evidence to evaluate its impact. As shown in Table R3, on the sequential CIFAR100 dataset, we evaluate the same network with five different seeds (0-4). The test accuracy is $\\pmb{67.2 \\pm 0.1}$% before quantization, and $\\pmb{66.5 \\pm 0.2}$% after applying power-of-two quantization to the neuron weights. This suggests that quantization only results in a minor performance drop.\n\n| Datasets            | seed      | Ours (w/ Q)           | Ours (w/o Q)          |\n| ------------------- | --------- | --------------------- | --------------------- |\n| Sequential CIFAR100 | 0,1,2,3,4 | $\\pmb{66.5 \\pm 0.2}$% | $\\pmb{67.2 \\pm 0.1}$% |\n\nTable R3: Average test accuracy with $\\pm$ standard deviation (%).\n\n> **Q2**: How much memory do operations like reshape, depthwise + pointwise convolutions, and dilation actually consume in large models or with long sequences? The paper only reports training speed, but I believe training memory usage is what most researchers care about.\n\nTable R4 presents the training memory usage of PSN and our methods (on the CIFAR100 dataset. \"Ours (w/o Q)\" uses channel-wise and dilated convolutions without quantization (Equation 10), while \"Ours (w/ Q)\" includes power-of-two quantization (Equation 13). The neuron order is $k=2$ for all cases.\n\nAs $T$ increases, all methods require more memory. Compared to PSN, our methods use slightly more GPU memory for the same sequence length. For instance, when $T=16$, PSN uses 11,867 MB, while \"Ours (w/o Q)\" and \"Ours (w/ Q)\" require 13,529 MB and 16,361 MB, respectively.  **The reason why our method requires more training memory than PSN is that input padding is used to enable parallelized training.**\n\n| neuron\\T    | 2    | 4    | 8    | 16    |\n| ----------- | ---- | ---- | ---- | ----- |\n| PSN         | 2101 | 3467 | 6315 | 11867 |\n| Ours(w/o Q) | 2507 | 3997 | 7333 | 13529 |\n| Ours(w/ Q)  | 2851 | 4835 | 8695 | 16361 |\n\nTable R4: Training memory (MB) on the training of the CIFAR100 dataset.\n\nMoreover, we would like to emphasize the significant practical advantage of our method during inference. Both our approach and Sliding PSN require storing an input sequence proportional to neuron order $k$. According to [4], Sliding PSN typically needs a large $k$ to achieve stable performance for long-term dependencies. In contrast, our neuron can converge with a much smaller $k$ and still achieve substantially better performance. For example, Sliding PSN could only achieve $62.11$% test accuracy with order $k=32$ on the sequential CIFAR100 dataset, while our method could attain $65.77$% test accuracy only under $k=4$ (Figure 5a, Appendix Table 7). Cause our approach dramatically reduces the required order $k$, it greatly reduces the length of the input sequence needs to be stored. As a result, our method requires much less memory during inference (Table R5, **547MB  vs. 2635MB, 4.8× reduction**).\n\n| neuron      | $k$  | Accuracy(%) | Memory (MB) |\n| ----------- | ---- | -------------- | ----------- |\n| Sliding PSN | 32   | 62.11          | 2635        |\n| Ours        | 4    | 65.77          | 547         |\n\nTable R5: **Step-by-step inference memory** on the sequential CIFAR100 ($T=32$) dataset.\n\n> **Q3**: Depth-wise + pointwise separation slashes parameters, but it also forces each channel’s temporal filter to be independent before mixing. Could that break important cross-channel correlations in the input spike train?\n\nThe convolutional layers before neuron layers could effectively enable cross-channel information exchange, while the neuron layers aggregate temporal information within each channel. This division preserves cross-channel correlations rather than breaking them.\n\n> **Q4**: In the Introduction, the authors claim that the method achieves significant energy savings, but the paper provides no analysis or experiments on energy consumption, nor is any such content found in the supplementary materials.\n\nWe have conducted a detailed analysis of energy consumption to support our claims regarding energy efficiency. Due to space limitations, **please refer to our response \"Energy Estimation\" to reviewer Hx7D' W3 for more details**. The analysis shows that our method achieves substantial savings compared to baseline models.\n\n\n> **Q5**: While accelerating training is certainly important, for deployable methods acceleration during inference is even more critical. Have the authors evaluated whether this method’s inference speed offers sufficient advantages over PSN-based or sliding-PSN models with comparable parameter counts\n\nAs shown in Table R6, our method is slightly slower than PSN in inference on GPU. However, it is important to note that our design is primarily intended to minimize the use of multipliers for deployment on edge devices, rather than to optimize GPU inference speed. The key advantage of our approach is its hardware-friendliness—by replacing multiplications with bit-shift operations and reducing the demand of large neuron order $k$, these significantly reduces energy consumption and chip area, which is especially beneficial for resource-constrained scenarios.\n\n| neuron\\T  | 2      | 4      | 8      | 16     | 32      |\n| --------- | ------ | ------ | ------ | ------ | ------- |\n| psn       | 0.8091 | 1.5430 | 2.8370 | 5.4668 | 10.7374 |\n| ours(k=2) | 1.0594 | 2.0243 | 3.4840 | 6.4227 | 12.5305 |\n| ours(k=4) |        | 2.0375 | 3.5812 | 6.5356 | 12.6378 |\n| ours(k=8) |        |        | 3.7819 | 6.7612 | 12.9210 |\n\nTable R6: Inference durations (s/epoch) of RTX 4090 GPUs on the CIFAR100 dataset.\n\n```JavaScript\n[1] Feng W, Gao X, Du W, et al. Efficient Parallel Training Methods for Spiking Neural Networks with Constant Time Complexity[C]//Forty-second International Conference on Machine Learning.\n[2] Chen H, Yu L, Zhan S, et al. Time-independent Spiking Neuron via Membrane Potential Estimation for Efficient Spiking Neural Networks[C]//ICASSP 2025-2025 IEEE International Conference on Acoustics, Speech and Signal Processing (ICASSP). IEEE, 2025: 1-5.\n[3] Li Y, Sun Y, He X, et al. Parallel spiking unit for efficient training of spiking neural networks[C]//2024 International Joint Conference on Neural Networks (IJCNN). IEEE, 2024: 1-8.\n[4] Chen X, Wu J, Ma C, et al. Pmsn: A parallel multi-compartment spiking neuron for multi-scale temporal processing[J]. arXiv preprint arXiv:2408.14917, 2024.\n[5] Fang W, Yu Z, Zhou Z, et al. Parallel spiking neurons with high efficiency and ability to learn long-term dependencies[J]. Advances in Neural Information Processing Systems, 2023, 36: 53674-53687.\n[6] Li X, Liu B, Yang R H, et al. DenseShift: Towards Accurate and Efficient Low-Bit Power-of-Two Quantization[C]//Proceedings of the IEEE/CVF International Conference on Computer Vision. 2023: 17010-17020.\n```"}, {"review_id": "1rOpugly6Y", "reviewer": "Reviewer_Hx7D", "summary": "This paper proposes a novel spiking neuron model called the mul-free channel-wise Parallel Spiking Neuron, designed to improve the training speed and efficiency of SNNs while maintaining strong long-term dependency modeling.\nKey innovations include the use of channel-wise convolution to improve representational capacity, sawtooth dilations to reduce model order (and thus complexity), and bit-shift operations to eliminate costly multiplications.\nExperiments show superior performance compared to existing state-of-the-art spiking neurons, along with demonstrated improvements in training speed.", "questions": "Please refer to the weaknesses.", "limitations": "Yes.", "rating": 5, "confidence": 4, "soundness": null, "presentation": null, "contribution": null, "strengths": "", "weaknesses": "", "quality": 3, "clarity": 3, "significance": 3, "originality": 3, "strengths_and_weaknesses": "## Strengths\n1. I think it is important for the model to be explicitly designed to leverage GPU parallelism, addressing one of the long-standing challenges in SNN training.\n2. Experiments are conducted on multiple benchmark datasets, showing broad applicability and state-of-the-art results.\n3. The theory of the proposed method is complete.\n\n## Weaknesses\nI want to know:\n1. Is the bit-shift replacement of multiplication universally applicable? Or does it introduce constraints on precision or dynamic range in practice, like FP-16, or other precisions?\n2. How does the proposed model balance sparsity with dense operations like channel-wise convolution? \n3. Has the proposed method been evaluated on real neuromorphic hardware (e.g., Loihi)? If not, how were the energy and latency benefits estimated?", "was_revised": true, "final_justification": "The authors have addressed my concerns. This paper is valuable for  parallelly training SNNs.", "rebuttal": "> W1: Is the bit-shift replacement of multiplication universally applicable? Or does it introduce constraints on precision or dynamic range in practice, like FP-16, or other precisions?\n\nFor multiplication of IEEE 754-defined FP32/FP16 values with powers of 2, the operation can always be converted to adding a corresponding integer to the floating-point exponent bits [1]. For integers multiplied by powers of 2, the conversion is even simpler: direct bit shifts suffice.\n\n> W2: How does the proposed model balance sparsity with dense operations like channel-wise convolution?\n\nThe sparsity in Spiking Neural Networks primarily refers to the sparse communication between layers. At the algorithm level, this means that neuron outputs are sparse binary spikes. At the hardware level, communication between computational cores (synapses + neurons) is made up of these sparse spikes, which can be efficiently implemented using sparse representation methods like Address-Event Representation (AER). However, the sparsity of neuronal dynamics itself is generally not constrained (for example, the calculation of membrane potential is typically dense).\n\n> W3: Has the proposed method been evaluated on real neuromorphic hardware (e.g., Loihi)? If not, how were the energy and latency benefits estimated?\n\n**Energy Estimation:**\n\nDeploying and verifying the proposed method directly on chips such as Loihi involves substantial engineering effort, and typically requires further steps including quantization of synaptic weights, which is beyond the current scope. Consistent with previous studies in the field [2-5], we estimate energy through the widely used energy estimation methodology from prior research in this field.  \n\nAssume implementation on the 45nm CMOS technology, FP32 multiplication (MUL) and addition (ADD) operation consumes $ 3.7pJ$ and $0.9pJ$ of energy, respectively. By comparison, a shift (SHIFT) operation with 32-bit fixed-point (FIX32) data consumes $0.13pJ$ [2] and is faster [7].  **As we couldn't find the theortical energy of bit-shift operation of FP32, we use the FIX32 bit-shift energy for estimation, which maybe not necessarily completely precise**. By combining the neuron operation counts listed in Table 1 with the corresponding energy consumption for each operation, we can estimate the theoretical neuron energy consumption, as summarized in Table R7. Note that when the parameter $k$ reaches its maximum value $T$, the maximal theoretical energy cost of our neuron is given by $0.515T^2+1.415T$. For a large $T$, this is nearly $9\\times$ lower than that of PSN, highlighting the substantial energy efficiency advantage of our approach in hardware-friendly scenarios.\n\n| Neuron | Operations                                                   | Energy (pJ)                          |\n| ------ | ------------------------------------------------------------ | ------------------------------------ |\n| PSN    | $(T^2+T)\\times \\text{ADD},T^2\\times \\text{MUL}$              | $4.6T^2+0.9T$                        |\n| Ours   | $((T+\\frac{1-k}{2})\\cdot k + T)\\times \\text{ADD}, ((T+\\frac{1-k}{2})\\cdot k)\\times \\text{SHIFT}$ | $1.03(T+\\frac{1-k}{2})\\cdot k +0.9T$ |\n\nTable R7:  Operations and energy of different spiking neurons during inference.\n\nFurther, we use the sequential CIFAR100 Network structure `{{c128k3s1-BN-SN}*3-APK2s2}*2-FC256-SN-FC100` (see Appendix D for more details) to evaluate the energy comsuption on a single CIFAR100 Image. During inference, we could fuse the convolutional layer with the batch normalization layer and ignore the batchnorm layer. Follow [3], we use Eq.(R1) to calculate the energy of synaptic layers, where $\\text{FL}^1_{\\text{SNN Conv}}$ is the FLOPs of the first layer to encode static RGB images into spike-form, $N$ is the number of convolutional layers and $M$ is the number of fully connected layers.  $fr$ in Eq.(R2) is the firing rate of the input spike sequence of every synaptic layer, and here is the average value of the trained networkd across the entire test dataset. Assume the MAC and AC operations are implemented on the 45nm hardware, $E\\_{MAC}=4.6pJ$ and $E\\_{AC}=0.9pJ$. Following the experimental setup specified in Table 3, the neuron order $k$ of our neuron is $16$. Detailed Energy analysis is shown in Table R8, where the FLOPs and SOPs of the synaptic layers refer to the $\\text{FL}\\_{\\text{SNN Conv}}^{1}$ and $\\left(\\sum\\_{n=2}^N \\text{SOP}^n_{\\text{SNN Conv}} + \\sum\\_{m=1}^M{\\text{SOP}^m\\_{\\text{SNN FC}}} \\right)$ in the Eq.(R1), respectively. Please note that our energy consumption estimation takes into account the energy consumed by the computation of neurons themselves. In contrast, the majority of previous studies have only considered the energy consumption of synaptic layers while neglecting that of the neurons themselves.\n\n$$E_{\\text{Synaptic}} = E\\_{MAC}\\times \\text{FL}\\_{\\text{SNN Conv}}^{1}+E\\_{AC} \\times\\left(\\sum\\_{n=2}^N \\text{SOP}^n_{\\text{SNN Conv}} + \\sum\\_{m=1}^M{\\text{SOP}^m\\_{\\text{SNN FC}}} \\right) \\quad(\\text{R1})$$\n\n$$\\text{SOPs}(l) = fr\\times T\\times \\text{FLOPs}(l)  \\quad (\\text{R2})$$\n\n|               | Neuron Layer                                             |                 | Synaptic Layer                                               |              | Total Energy$(\\mu J)$ |\n| ------------- | -------------------------------------------------------- | --------------- | ------------------------------------------------------------ | ------------ | --------------------- |\n|               | Operations                                               | Energy$(\\mu J)$ | Operations                                                   | Energy$(uJ)$ |                       |\n| $\\text{PSN}$  | $1.91\\times10^7 \\text{MUL},1.97\\times10^7 \\text{ADD}$    | $88.56$         | $0.041\\times 10^6 \\text{FLOPs},3.194\\times 10^6 \\text{SOPs}$ | $3.06$       | $91.62$               |\n| $\\text{Ours}$ | $7.32\\times10^6 \\text{SHIFT},7.92\\times 10^6 \\text{ADD}$ | $8.08$          | $0.041\\times 10^6 \\text{FLOPs},2.660\\times 10^6 \\text{SOPs}$ | $2.58$       | $10.66$               |\n\nTable R8:  Energy of our method and PSN on a single CIFAR100 Image.\n\n**Latency:**\n\nWhile both our approach and Sliding PSN require storing an input sequence proportional to neuron order $k$ for inference on neuromorphic chips, Sliding PSN typically needs a much larger $k$ to achieve stable performance for long-term dependencies. In contrast, our model achieves strong performance even with small $k$ (e.g., $k=2$), significantly reducing memory requirements for storing input sequences and making the solution more suitable for resource-constrained devices. **Details can be found in our reply to Reviewer ZuQM question 1, Table R2.**\n\n```C++\n[1] Li, Xinlin, et al. \"DenseShift: Towards Accurate and Efficient Low-Bit Power-of-Two Quantization.\" Proceedings of the IEEE/CVF International Conference on Computer Vision. 2023.\n[2] Huang Z, Fang W, Bu T, et al. Differential Coding for Training-Free ANN-to-SNN Conversion[C]//Forty-second International Conference on Machine Learning.\n[3] Zhou Z, Zhu Y, He C, et al. Spikformer: When Spiking Neural Network Meets Transformer[C]//The Eleventh International Conference on Learning Representations.\n[4] Rathi N, Roy K. Diet-snn: A low-latency spiking neural network with direct input encoding and leakage and threshold optimization[J]. IEEE Transactions on Neural Networks and Learning Systems, 2021, 34(6): 3174-3182.\n[5] Panda P, Aketi S A, Roy K. Toward scalable, efficient, and accurate deep spiking neural networks with backward residual connections, stochastic softmax, and hybridization[J]. Frontiers in Neuroscience, 2020, 14: 653.\n[6] You H, Li B, Huihong S, et al. ShiftAddNAS: Hardware-inspired search for more accurate and efficient neural networks[C]//International Conference on Machine Learning. PMLR, 2022: 25566-25580.\n[7] Elhoushi M, Chen Z, Shafiq F, et al. Deepshift: Towards multiplication-less neural networks[C]//Proceedings of the IEEE/CVF conference on computer vision and pattern recognition. 2021: 2359-2368.\n```"}, {"review_id": "ue50cnRksB", "reviewer": "Reviewer_yzYg", "summary": "This paper introduces a novel multiplication-free, channel-wise Parallel Spiking Neuron (PSN) model to improve the training efficiency of Spiking Neural Networks (SNNs), particularly in resource-constrained neuromorphic applications. Unlike conventional spiking neuron models that rely on serial iterative updates or costly high-order approximations, the proposed neuron model offers hardware-friendly acceleration by eliminating multiplications and enabling channel-level parallelism. The method is evaluated on neuromorphic audio (Spiking Heidelberg Digits), vision (DVS-Lip), and sequential image (CIFAR) datasets, achieving competitive or superior accuracy and demonstrating significant training speedups over prior SOTA neurons.", "questions": "1. What is the speedup of this new training method on embedded or low-end GPUs?\n\n2. What is the accuracy of this new training method on other datasets such as imagenet?", "limitations": "yes", "rating": 4, "confidence": 3, "soundness": null, "presentation": null, "contribution": null, "strengths": "", "weaknesses": "", "quality": 3, "clarity": 3, "significance": 2, "originality": 2, "strengths_and_weaknesses": "Strengths:\n\n1. Important Problem Area:\nThe work targets a key bottleneck in neuromorphic computing—efficient training of SNNs—by addressing both latency and resource usage, which are crucial in embedded or real-time SNN deployment.\n\n2. Hardware-Friendly Design:\nThe design eliminates multiplication operations, aligning well with the constraints of edge neuromorphic hardware and making it more suitable for low-power, high-efficiency environments.\n\nWeaknesses:\n\n1. Unclear Practical Impact of GPU Speedup:\nThe reported training speedups on a high-end A100 GPU may not convincingly reflect practical gains, especially given that CIFAR training is already fast on such hardware. Since the main selling point is hardware efficiency, evaluations on actual neuromorphic processors (e.g., Loihi, SpiNNaker) or low-resource edge devices would provide more meaningful insights.\n\n2. Lack of Benchmark Diversity at Scale:\nThe paper does not include results on larger-scale datasets such as ImageNet. Demonstrating effectiveness at scale would further validate the method’s generalizability and robustness.", "was_revised": true, "final_justification": "I give a bordline accept. I am not the bottleneck to accept this paper.", "rebuttal": "> **W1**: Unclear Practical Impact of GPU Speedup: The reported training speedups on a high-end A100 GPU may not convincingly reflect practical gains, especially given that CIFAR training is already fast on such hardware. Since the main selling point is hardware efficiency, evaluations on actual neuromorphic processors (e.g., Loihi, SpiNNaker) or low-resource edge devices would provide more meaningful insights.\n\nWe agree that evaluations on neuromorphic chips or edge devices would provide deeper insight into practical hardware efficiency. But due to the presence of time dimension T, training SNNs is significantly slower than ANNs, so improvements in GPU training speed can greatly facilitate research and development in this field.  Implementing and evaluating our method on neuromorphic hardware such as Loihi or SpiNNaker would require substantial engineering effort, and we have not yet completed such hardware-level verification. This remains an important direction for our future work.\n\n> **Q1**: What is the speedup of this new training method on embedded or low-end GPUs?\n\nWhile we have not yet conducted experiments on embedded or low-end GPUs due to hardware limitations, we evaluated the training speed of our method on an RTX 4090 GPU as a representative consumer GPU. As shown in Table R9, the speed gap between our autoselect implementation and PSN on the 4090 is similar to the results reported in the paper. Importantly, compared to the vanilla implementation, our method achieves up to a 10× speedup, demonstrating the effectiveness of our acceleration strategy. We believe these trends will generalize to resource-constrained GPUs.\n\n| Method \\T       | 2     | 4      | 8      | 16     |\n| --------------- | ----- | ------ | ------ | ------ |\n| psn             | 12.16 | 14.20  | 25.76  | 49.84  |\n| Autoselect(k=2) | 18.80 | 23.40  | 47.18  | 83.27  |\n| Autoselect(k=4) |       | 24.86  | 47.52  | 86.81  |\n| Autoselect(k=8) |       |        | 44.57  | 85.05  |\n| Vannilla(k=2)   | 40.84 | 57.66  | 121.00 | 460.04 |\n| Vannilla(k=4)   |       | 407.09 | 439.61 | 576.29 |\n| Vannilla(k=8)   |       |        | 754.39 | 857.46 |\n\nTable R9: Training durations (s/epoch) of RTX 4090 GPUs on the CIFAR100 dataset.\n\n> **W2:** Lack of Benchmark Diversity at Scale: The paper does not include results on larger-scale datasets such as ImageNet. Demonstrating effectiveness at scale would further validate the method’s generalizability and robustness.\n>\n> **Q2**: What is the accuracy of this new training method on other datasets such as imagenet?\n\nWe appreciate the reviewer's suggestion regarding evaluation on large-scale benchmarks such as ImageNet. In response, we conducted preliminary experiments using our method on the ImageNet dataset. Unfortunately, our approach did not outperform PSN under the default settings. Due to the limited rebuttal period, we did not further tune hyperparameters or conduct more extensive trials.\n\nAdditionally, we observe that the Sliding PSN also underperforms PSN for static image classification tasks. We hypothesize that this may be attributed to the advantage of the standard PSN in accessing information from all global timesteps, which could be particularly beneficial in static image scenarios."}]

Author rebuttal:

Meta-review: The authors propose a multiplication-free framework for parallelizable spiking neural networks. Their approach improves state-of-the-art approaches in this area with changes to the architecture by per-channel separable convolutions, bit shifts instead of multiplications, and saw-tooth dilation for convolutions. The reviewers remark that none of these changes by themselves are by themselves necessarily revolutionary. However, they acknowledge that the combination leads to a system with state-of-the-art accuracy on common SNN tasks, while getting rid of multiplications, which is likely to considerably reduce energy expenditure. 

The authors successfully addressed reviewer questions on the variability of the results, energy and memory consumption, the cost of quantization, and the memory comparison with PSN. 

The work would be even more convincing when the expected energy gains would be shown on neuromorphic hardware, and if the accuracy would extend to more complex tasks. However, I agree with the authors that these elements can be addressed in future work. This article will definitely be of interest to practitioners in the field.
Decision: Accept (poster)