MIHC: Multi-View Interpretable Hypergraph Neural Networks with Information Bottleneck for Chip Congestion Prediction
Authors: Zeyue Zhang
Heng Ping
Peiyu Zhang
Nikos Kanakaris
Xiaoling LU
Paul Bogdan
Xiongye Xiao
Venue: NeurIPS 2025 poster ()
Keywords: Electronic Design Automation
Hypergraph Neural Networks
Interpretable Machine Learning
Information Bottleneck
Multi-view Learning
Chip Congestion Prediction
Primary area: applications

Abstract: With AI advancement and increasing circuit complexity, efficient chip design through Electronic Design Automation (EDA) is critical. Fast and accurate congestion prediction in chip layout and routing can significantly enhance automated design performance. Existing congestion modeling methods are limited by **(i)** ineffective processing and fusion of multi-view circuit data information, and **(ii)** insufficient reliability and interpretability in the prediction process. To address these challenges, We propose **M**ulti-view **I**nterpretable **H**ypergraph for **C**hip (**MIHC**), a trustworthy 'multi-view hypergraph neural network'-based framework that **(i)** processes both graph and image information in unified hypergraph representations, capturing topological and geometric circuit data, and **(ii)** implements a novel subgraph Information Bottleneck mechanism identifying critical congestion-correlated regions to guide predictions. This represents the first attempt to incorporate such interpretability into congestion prediction through informative graph reasoning. Experiments show our model reduces NMAE by 16.67% and 8.57% in cell-based and grid-based predictions on ISPD2015, and 5.26% and 2.44% on CircuitNet-N28, respectively, compared to state-of-the-art methods. Rigorous cross-design generalization experiments further validate our method’s capability to handle entirely unseen circuit designs.

MIHC: Multi- Interpretable Hypergraph Neural Networks with Information Bottleneck for Chip Congestion Prediction
Zeyue Zhang"
Heng Ping Peiyu Zhang" Nikos Kanakaris c**
Xiaoling Lu" Paul Bogdan Xiongye Xiao
"Center for Applied Statistics, School of Statisties, Innovation Platform, Renmin University of China; "Ming Hsich Department of Electrical and Computer Engineering, University of Southern California; Amazon Web Services, Seattle; and Min H. Kao Department of Electrical Engincering and Computer Science, University of Tennessee, Knoxville
Abstract
With the advancement of artificial intelligence (AI) and increasing integrated circuit (IC) design complexity, efficient chip design through electronic design automation (EDA) has become critical. Fast and accurate congestion prediction in chip layout and routing can significantly enhance automated design performance. Existing congestion modeling methods limited by (i) ineffective processing and fusion multi-view circuit data information, and (ii) insufficient reliability and inter- pretability in the prediction process. To address these challenges, we propose the Multi-view Interpretable Hypergraph for Chip (MIHC), a trustworthy multi-view hypergraph neural network framework that (i) processes both graph and image infor- mation in unified hypergraph representations, capturing topological and geometric circuit data; (ii) implements novel subgraph Information Bottleneck mechanism, identifying critical congestion-correltted regions to guide predictions. This work is the first attempt incorporate such interpretability into congestion prediction through informative graph reasoning. Experiments show that the MIHC method reduces NMAE by 16.67% and 8.57% in cell-based and grid-based predictions on ISPD2015, and 5.26% and 2.44% on CircuitNet-N28, respectively, compared to state-of-the-an art methods. Rigorous cross-design generalization experiments further validate our method's capability to handle entirely unseen circuit designs.
Introduction
Advances in artificial intelligence (AI) and cyber-physical systems (CPS) 23 require continuous and increasing demand for computational power supported by integrated circuits (ICs). This necessi-
tates rapid, accurate IC design through electronic design automation (EDA) 12 Efficient quality
assessment of generated circuits is crucial to the design process [9, with circuit congestion prediction being particularly vital as it directly impacts reliability, performance, and manufacturability:
Circuit congestion occurs when routing resources are exceeded by wires attempting to traverse the same physical region 4 This issue arises when cells (i.e., electronic components) that logically connected by nets (i.e., connecting wires) are physically placed far apart or when many nets must share limited routing space. These situations commonly result from the mismatch between circuit connectivity requirements and physical layout constraints [0] Therefore, accurate congestion
"Fqual contribution.
Corresponding authors: (bogdan@usc.edd and x edu.
"Thh work does not relate the author's position Amazon.
39th Conference on Neural Information Processing Systems (NcurIPS 2025).

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prediction requires comprehensive analysis of both the logical relationships between cells and nets and their geometric distribution in the physical layout 20 27
Given this dual nature of congestion formation, circuit congestion prediction primarily involves two types of data: netlist and layout. Netlist captures logical connections between cells and nets, representing topological information naturally modeled as graphs. Layout data divides the placement area into grids containing circuit features like cell and net density, encoding geometrie information in an image-like format. Effective congestion prediction requires processing and fusion of both complementary information types, as congestion patterns are determined by both connection topology and component geometric distribution.
Traditional congestion prediction approaches use unle-based systems [8] and statistical models [16], but struggle with modern circuit complexity [15]. Deep learning (DI.) methods have emerged with superior performance, divided into single-view and multi-view approaches. Single-view methods include DE-HNN [1],, which transforms eircuit connections into hypergraphs using HGNNs 7 to capture topological information, and GAN-based approaches [26] that process grid-based features as images. However, these single-view approaches inevitably miss valuable information from the complementary perspective.
In an attempt to process both views simultaneously, CircuitGNN 24 incorporates layout information into netlist- based hypergraphs by adding position-aware edges, while Lay-Net(28] introduces special- ized HGNN modules into Swin- Transformer- based layout processing. However, these methods tend to favor one view while incorporating the other supplementary information, leading to insufficient fusion of topological and geometric information. Moreover, existing deep learning approaches operate as black boxes, lacking interpretabilityy and trustworthiness crucial for circuit design validation 12)
To address these limitations, we propose the Multi-view Interpretable Hypergraph for Chip (MIHC) framework, trustworthy multi-view hypergraph neural network- model featuring symmetrical architecture that fuses netlist and layout data through net-based bridging. Specifically, we construct cell-based and grid-based hypergraphs from respective data sources, with hyperedges in both hy- pergraphs built through nets, enabling balanced fusion of topological and geometric information. Furthermore, we incorporate novel subgraph information bottleneck (IB) [T7] mechanism that iden- tifies critical congestion-correlaan optimization. This enhances accuracy through targeted information processing while providing inter- pretability by revealing critical local structures causing congestions. Such insights are particularly important since congestion typically emerges from interactions between neighboring components rather than isolated elements, offering designers actionable guidance for targeted optimization.
regions, guiding focused prediction while revealing areas needing
Contributions. The main contributions of this paper are summarized as follows: (1) Multi-View Representation Learning: We propose a novel balanced multi-view HGNN that effectively fuses netlist and layout information through net-based bridging, enabling comprehensive learning of both topological and geometric features for congestion prediction. (2) Interpretable Bottleneck Subgraph: We develop subgraph IB mechanism that identifies critical regions highly related to congestion, providing interpretability for circuit optimization while improving prediction accuracy through focused learning. (3) Superior Prediction Performance: Comprehensive experiments the ISPD2015 and CircuitNet-N28 datasets, including rigorous cross-design generalization evaluations, demonstrate that our model reduces NMAE by 16.67% and 8.57% in cell-based and grid-based predictions on ISPD2015, and 5.26% and 2.44% on CircuitNet-N28, respectively, compared to state-of-the-art methods. The evaluation results verify the effectiveness of our multi-view learning strategy and interpretable bottleneck mechanism.
2
Related Work
2.1 Deep Learning for Congestion Prediction
Congestion prediction involves processing two types of data: netlist data that can be naturally modeled as graphs, and layout data that can be represented in image format. Based on how these data types are processed, existing DL approaches can be categorized into single-view and multi-view methods.
Single-Vies Methods. These approaches focus on processing either netlist or layout data exclusively. For netlist-based methods, CongestionNet(] and Cross-Graph [5) model the netlists as homogeneous graphs and employ GNNs for congestion prediction, while DE-HNN leverages HGNNs to capture

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high-order relationships in circuit netlists. For sayouut-assed methods. RouteNet 22 treats grid-based layout data images and utilizes CNNs to generate congestion maps; CireuitFormer 29 regards the grids of a layout as point cloud and uses Point Transformer to process each grid. However, these single-view approaches inevitably miss valuable information from the other perspective.
Multi- View Methods, Recent efforts attempt to incorporate both the netlist and layout information. Netlist-centric approaches like the Cireui LHNN and HybridNet (2] construct hy- pergraphs from netlists and incorporate layout information through position-
edges or nodes. Layout-centric methods such as Lay-Ner(28), DFM-Ner(o). and PGNN primarily process grid- based layout data using vision models like U-Net while integrating the netlist information through specialized GNN or HGNN modules. However, these methods tend favor one data type, often leading to suboptimal and insufficient fusion of topological and geometric information. In contrast, our proposed MIHC model processes both data types by constructing cell-based and grid-based hypergraphs, achieving balanced fusion through net-based bridging.
2.2 Interpretation Methods For Graph
In chip congestion prediction, interpretability has received little attention despite being crucial for identifying key performance-enhancce components and transforming black-box approaches into semi-transparent ones that users find more accessible. Since chip congestion prediction naturally involves graph-structured data with complex interactions, we examine graph domain interpretabiliity methods. Existing approaches are primarily post-hoc, such GNNExplainer (25 and PGEx- plainer [13. which provide node/edge-level explanations through learned masks but rely on post-hoc strategies for supervised tasks. Recent progress includes self-interpretable methods like SIGNET [Α]. which generates inherent interpretations during graph anomaly detection. Inspired by these approaches, our MIHC integrates Information Bottleneck [177] achieve interpretability in chip congestion prediction- representnn,,,, to our knowledge, the first interpretability work in this domain.
3 Preliminaries
3.1 Problem Formulation
The circuit congestion prediction task aims to estimate the potential congestion levels in a complex circuit design based on its layout and netlist information during early design stages. Congestion can be quantified as the ratio of overflow demand to available routing tracks in IC backend design 3 where overflow represents excess routing requirements beyond provided resources.
Formally, each circuit data is represented as multi-view data comprising grid-based and cell- information. The grid-based view models circuit layout structured grid P E IR x where M, N E N+ are grid dimensions and K N+ the number of features per grid cell. The cell-based view represents the circuit at a finer granularity level based on the netlist information, where each cell corresponds to an individual circuit component with specific features. The cell-based view represents the circuit netlist of hyperedges (nets connecting multiple cells). Given grid-based representation hypergraph G, our goal is to simultaneously predict grid congestion map C E R M and cell congestion graph C E RIVI, where [i E RR+ and CC [k] E I quantify congestion levels at grid (i and cell k;, respectively. The notations used the manuscript are presented in Appendix
hypergraph G = E). where V is the set of nodes (cells) and E is the set
and cell-based
The predictive model f. parameterized by 0, is defined as follows:
fo (P.G) + (Caa (Ç))
with the supervised objective to minimize the mean squared error:
M N
WI C 6CTK)
Cxup
1
[i.i O 2
(2)
MXN
3.2 Information Bottleneck
The Information Bottleneck (IB) formalism 17 addresses a fundamental challenge representation
learning by extracting the minimal yet sufficient features from high-dimensional data. For example,
3

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(d)
Augienn
LC
r A5)
Bottleneck: Subgraph Extractor
Maltt- View HGNN
CCC MS)
L6
Angiment
Agg
Cells
Agu
Updatt
Agg
Updale
Grids
Update
01110111111
5
5
AgU
A
Nets
Figure Overview of MIHC framework. (a) Process Module converts raw multi-view data (cell-
based netlist and grid-based layout) into hypergraphs Hº and H (details in Appendix C.2 (b)
Interpretable Subgraph Module applies Multi- View Information Bottleneck to extract congestion- correlated bottleneck subgraphs H3 and Hg. (c) Multi-View Representation Learning Module employs MV-HGNN to capture topological and geometric information, generating node embeddings N. Ae and subgraph embeddings lgg. hg. (d) Prediction Module uses MLPs map embeddings to congestion predictions, optimized through supervised, IB, and contrastive losses. (Cuup. LIB, Ceont).
inspired new hierarchical perception methods for multimodal learning 21. Given an input variable X and target variable Y, IB seeks intermediate representation T that optimally balances data compression and target information preservation, formulated as:
[[p(t(=)) I(T; 5 I(T;Y)
(3)
where [('; X) and (T;Y) denote mutual information, and 3 E IR+ controls the compression- relevance trade-off. This formulation enables the identification of critical features driving model predictions while minimizing redundancy, making IB particularly valuable for model interpretability and subgraph analysis in networks [1]]
4 Method
In this section, we introduce the proposed MIHC framework (see Figure which consists of four parts: (a) The Process Module converts raw multi-view data, including cell-based netlist graph and grid-based layout image, into hypergraphs for further processing. (b) The Interpretable Subgraph Module introduces a novel subgraph Information Bottleneck (IB) mechanism to identify critical bottleneck subgraphs highly related to circuit congestion and guide the model to focus these regions during prediction. (c) The Multi- View Representation Learning Module integrates both graph and image data into unified hypergraph representations, capturing topological and geometric features of circuit data. (d) The Prediction Module computes the prediction both cell and grid views.
4.1 Process Module
Given the dual nature of the data, the Process Module converts raw multi-view data, including both cell-based netlist graph and grid-based layout image, into hypergraphs for subsequent processing.
Hypergraph Construction from Cell-based Netlist Graph. We construct cell-based hypergraph Hº = (VC, EE), where FC represents circuit cells and EC represents hyperedges based on net

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connections. Each node v E VC is initialized with feature X derived from circuit netlist charac- teristics. This hypergraph primarily captures topologial relationships among circuit components.
Hypergraph Construction from Grid-hased Layout Image. We construct grid-based hypergraph =V= F.), where VG represents local layout image regions with feature representation X containing each region's component density, and E represents hyperedges connecting these regions. The formation of grid-based hyperedges ex E is guided by spatial proximity and net connections. Hyperedges are established among nodes corresponding to spatially adjacent regions to preserve the geometric information. More importantly, nodes within the same net are grouped into hyperedges to capture high-order geometric information. Both cell-based hyperedges E and grid-based hyperedges E though from different hypergraphs, are built on identical net connections critical for fusing topological and geometric information in subsequent multi-view representation learning.
4.2 Interpretable Subgraph Module
The interpretable subgraph module is designed to identify critical parts in the circuit hypergraph and guide the model to assign more attention to these parts.
Multi- Information Bottleneck. We develop a Multi- Information Bottleneck (MVIB) approach combining information from both bell-baeed netlist and grid- layout data. After extracting hypergraphs Hº and H IB learns bottleneck subgraphs for each view. Taking Hº as an example, the objective is to learn a bottleneck subgraph HG by optimizing the following objective:
max T(H;; H - 3 T( H5 HH)),
where 3 controls compression--elleancee trade-off. A similar formulation applies for HI@.
Inspired by [. we adopt a single extractor design for both hypergraph views. The extractor processes hypergraph H using Hypergraph Neural Network to obtain node probabilities, modeled as po (H5 ( Ilvee po(u E VV H²)). The HNN outputs
Bottleneck Subgraph Extractor.
probability vector p E [0, 1]Iv"), enabling bottleneck subgraph extraction:
(5) where M is the incidence matrix of H² X represents the node features, and @ denotes the row-wise production. The bottleneck subgraph for the grid- based view H can then be extracted using the mapped probability vector in the same form Eq. (5).
H = (MC, x5) = (MC; x @p),
Node probabilities map between views through spatial relationships. For each node G in HG, its probability is p" [o-] max,CeN((o)) p( where (1 denotes cell nodes associated with grid
node vC. This single-extractor design ensures bottleneck subgraph consistency across views while reducing complexity. The extracted subgraphs Hς and HȘ preserve the most informative structures for congestion prediction, guided by the information bottleneck objective in Eq. (7)
Bottleneck Subgraph Augmentation. After extracting the bottleneck subgraphs, we leverage bottleneck subgraphs to enhance feature representations through dynamic reweighting:
-º -MM² x (1 ( (XX)). Hº = (MC, x (1 x (x(I)) (6)
where Wc, WG are learnable weights, a is the sigmoid function, and || represents concatenation. This mechanism enhances features based on bottleneck structure relevance, while residual connections ensure stable gradient flow and preserve structural information.
Multi- View Information Bottleneck Loss. The information bottleneck loss regularizes bottleneck subgraph embeddings. The objective is reformulated as:
LMVIB = I H + 3D5KL (po H Py ( H²)
(7)
where pe and p. refer to bottleneck subgraph extractors, DSKL denotes symmetrized KL divergence, and 3 controls the trade-off between terms. Derivations from Eq. (4) (7. are in Appendix A
4.3 Multi-View Representation Learning Module
Given the multi-view data available, we propose a Multi-View Heterogeneous Graph Neural Network (MV-HGNN) that processes and integrates cell-based and grid-based hypergraph representations through a two-step message passing mechanism.
5

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Node-to-Hyperedge Message Passing, For both cell-based and grid-based hypergraphs, we first aggregate node features within each hyperedge separately:
h
Σ hh
h
Σ
(8)
VEVO(C)
wEVe(c) (e)
where 3g: h are intermediate hyperedge embeddings, (e), (e) denote nodes in respective hyperedges, and W.", W can transform features into a common semantic space.
The net-based hyperedge embedding is then obtained by first concatenating these intermediate embeddings followed by a non-linear transformation:
h (W ( 1))
where N5" represents the actual net-based hyperedge embedding that captures both topological and geometric information.
Hyperedge-to-Nodee Message Passing. The second step updates node embeddings by aggregating information from different sources. For cell-based nodes:
cC
W.
A
W A
(10)
6EEC(M)
EEEN
where & N are intermediate embeddings from respective hyperedges, 8 (v), EN (v) denote hyper- edge sets containing node v. The final cell-based node embedding is obtained through concatenation and non-linear transformation:
h -o & (N
(11)
For grid-based nodes, we similarly aggregate information from spatially adjacent nodes and use the previously computed net-based hyperedge information: hg = Eue W where 8 (v)
represents spatially adjacent grid nodes. The final grid-based embedding:
h = o( v. (
(12)
After L message passing layers, final node embeddings serve two purposes: downstream congestion prediction and generating subgraph embeddings for contrastive learning. The subgraph embeddings derived from previously identified bottleneck subgraphs:
hgg Aggregate ( v E H). n Aggregate((h | V&))).
(13)
This symmetric design facilitates effective congestion prediction for both views while maintaining the inherent characteristics of each representation.
Contrastive Loss. To enhance and align the interaction between cell-based and grid-based informa- tion, we employ contrastive learning. The contrastive loss is defined as:
N
cxp(sim(hg,,ng)) log E ex
Leont
Σ
(14)
where h hg. form positive pairs from the same input, hg, represents negative samples, sim(a, b)
denotes cosine similarity, and 7 controls similarity distribution sharpness.
4.4 Prediction Module
Unlike previous methods that can only produce predictions in either the cell view or the grid view at once, our method's prediction module can output predictions in both scenarios simultaneously.
Prediction. In the prediction, obtain both hC the cell-based node embedding, and NG the grid-based node embedding. Therefore, we use two MLPs, fC and fc to map the two embeddings the node congestion prediction results for both views: "C f (h D. = f (h where de and ب represent the predicted node congestion values for the cell and grid views, respectively.
Total Loss. The overall loss combines contrastive (refer Eq. supervised (refer to Eq. ()) and information bottleneck losses (refer to (7) to optimize the model.
Lixal = Leomt + Lu + fsup-
(15)
Time Complexity. The overall complexity is O(([Vol x |E + |Vol |Eal) x D x L),, where |Vel and VVll represent the number of cell and grid nodes, Fell and |Fal represent their respective hyperedges, D is the hidden dimension, and L is the number of layers.

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Table I: Placement-leve results on All Datasets for both Cell- and Grid-based View. and the second best underlined.
The best in bold
Model
103355
ISP17311--1
Pcauue
Seatal
DPN
02:94
11921
13:64
0.435
Cdl-
CROAHONN
BONS
BJ36
B034
0.383
0.342
0.988
0.57
0.553
0.61
0.476
03887
0.945
0833
0,53
0-40
0.410
0.366
0.17%
0.309
0.062
0B4
0.661
0.345
0.582
0.468
0.332
DE-ENN
B
0.007
0.645
0.632
0.530
0.43
0.407
0
0.381
0.03
0.42
0.635
0.51
0.37%
MIRE dOre
8787
0388
100
GXT
B.644
0.000
0.395
0.144
0.141
0.43
0.555
0.331
0.137
0.316
0,02
0.054
0,411
0.455
0.323
BONN
0:400
0.365
0.45
0.184
0.142
0.63
0.50
0.382
0.147
0.121
0.51
0.62
0.442
0424
0.311
bascal
Grid
Cresstvemeer
CRASEGNN
BJ377
B034
0.343
0,003
0.561
0.649
0.231
0.201
0.159
0.164
0.08
0.43
0.699
0.45
0.364
0A53
0.163
0.136
0.15
0.134
0,67
0245
0/022
0,547
0.508
0.526
0,371
0384
Len-Nei
0.031
0.007
0.667
0.301
0.388
0.00
0.612
0.454
0.256
0.308
0.011
0.43
0.671
0.558
0.486
NEIBC (Qurr))
10130
8.036
8.675
0.297
0.252
0.033
00030
0,303
0.271
0.127
(U)
0,641
0,633
0,572
0.402
Table 2: Design-level results on ISPD2015-B and ISPD2015-F for both Cell- and Grid-based View. The best in bold and the second best underlined.
ISPD2015-B
ISPD2015-F
Direction View
Model
NMAEL
NRMS;
Pearsont
Spearmant
Kendall
NMAE,
NRMS.
Pearson"
Spearmant
Kendalf
CircuiiGNN
0.058
0.064
0.376
0.248
0.071
0.077
0.218
Cell-
LHNN
0.054
0,060
0.398
0.355
0,265
0.067
0.073
0.368
0.321
0.235
bused
DE HEN
0.051
0.057
0.415
0.372
0.282
0.069
0.385
0.342
0.252
MIHC (Ours)
0.048
0.053
0.448
0.405
0.302
0.059
0.065
0.414
0.375
0.277
A-B
ChruniNN
D0061
0.067
0.366
0.132
0.080
0.331
0.148
0.122
Grid-
LHNN
0.057
0.063
0.389
0.172
0.145
0.070
0.076
0.349
0.162
0.135
based
Lay-Net
0.053
0.059
0.411
0.165
0.064
0.070
0.394
0,200
0.174
MIHC (Ours)
0.051
0.057
0.436
0.218
0.188
0.064
0.069
0.405
0.201
0.167
ChruniGN
00063
0.068
0.351
0.075
00081
0.337
0.293
0.205
Cell.
1.HNN
0.058
0.065
0.379
0.347
0,246
0.070
0.076
0,354
0.315
0.222
based
HINN
0.053
0.058
0,405
0.365
0.269
0.071
0.336
0.238
B-A
MIHC (Ours)
0.049
0,055
0.428
0.384
0,281
0.062
0.067
0.399
0.357
0.262
CreuniGN
00064
0.070
0.348
0.122
0.077
0.083
0.318
0.138
0.112
Grid-
LHNN
0.060
0,066
0.369
0.162
0.135
0.073
0.079
0.337
0.152
0.125
bused
Lay-Net
0.055
0.061
0.392
0.197
0.179
0,367
0.152
MIHC (Ours)
0.054
0.059
0.415
0,202
0.175
0.067
0.072
0,388
0.182
0.168
5 Experiments
In this section, we evaluate MIHC through comprehensive experiments designed to address four key research questions:
RQ1: How does MIHC's circuit congestion prediction accuracy compare to state-of-the the-art methods?
RQ2: What is the MIHC's interpretability performance?
RQ3: What is the impact of MIHC's core design components on its overall performance?
RQ4: How sensitive is MIHC's performance to parameter variations?
5.1
Experimental Setup
For chip congestion prediction, we evaluate our method on two public datasets: ISPD2015 2 and CircuitNet-N22 3. ISPD2015 is divided into two variants: ISPD2015 5-1llanceeed (ISPD2015- B), which excludes extremely large superblue cireuits, and ISPD2015-Ful (ISPD2015-F), which in- cludes them, allowing us to assess our model's performance on data imbalance challenges. CircuitNet- N28 contains over 10,000 samples (compared to ISPD2015's approximately 500), providing a more comprehensive test of our model's generalizability across diverse circuit designs.
Datasets.
To rigorously evaluate generalization capability, we employ two data partitioning strategies: (1) Placement-level split, where different placement solutions from the same design appear in both training and test sets, and (2) Design-level split, where training and test sets contain completely different circuit designs with no overlap. The placement-level split follows our standard 7:3 train-test ratio, while the design-level split involves bidirectional evaluation (A-+B and B-+A) on carefully partitioned design groups. Detailed partitioning strategies are presented in Appendix C.5
For explainable GAD task, we use MNISTO and MNISTI datasets
Baselines. There are two aspects of prediction tasks: cell-based prediction and grid-based prediction. To comprehensively evaluate our model, we first employ several classical graph learning models as
7

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baselines: GCN 18, GAT 19 and HGNN [7]. Furthermore, we compare with specialized circuit- oriented models: CircuitGNN 24 and LHNN 20 which are capable of handling both cell-based and grid-based predictions; DE-HNN 14], which focuses exclusively
rell-based prediction; and RouteNet [22], CircuitFormer 29 and Lay-Net (28), which specifically target grid-based prediction. To illustrate the usefulness of the model interpretability module, we chose GCN + GNNExplainer [25] as baselines.
GAT + GNNExplainer and SIGNET [I]]
Evaluation Metries. For chip congestion prediction, similar to we employ both regression-based metrics (NMAE and NRMS) measure prediction accuracy and ranking- -ased metrics (Pearson, Spearman, and Kendall correlations) to assess prediction quality; while in interpretability module test, since the downstream task a classification task, ACC, Precision, Recall, FI, and AUC are used to measure the accuracy of the classification.
Further details about datasets and experiment settings are presented in Appendix C
5.2 Chip Congestion Prediction Results (RQ1)
We present comprehensive evaluation results under both placement-level and design-level settings. The placement-level results are shown in Table design-level results are presented in Table 2 both with the best in bold and the second best underlined (More details in Appendix [.I]. Given that our data encompasses both cell and grid views, we assess the validity and rationality of our model across these dual views by comparing prediction accuracy against their respective state-of-the-art (SOTA) counterparts.
5.2.1 Placement-level Results
As shown in Table T for ISPD2015-B BB, MIHC outperforms the SOTA method DE-HNN with 9.37% reduction in NMAE and 1% improvement in Pearson correlation the cell level, and surpasses Lay-Net with 3.23% reduction in NMAE and 1.20% improvement in Pearson correlation at the grid level. On the more challenging ISPD2015-F 5-F with extremely large circuits, MIHC achieves even more significant gains: 16.67% reduction in NMAE and 12.21% improvement in Pearson correlation compared to DE-HNN at the cell level, and 8.57 reduction in NMAE and 3.93% improvement in Pearson correlation over Lay-Net at the grid level. These results demonstrate MIHC's s robustness when handling imbalanced data distributions. The CireuitNet-N22 results, based on over 10,000 diverse samples, further confirm MIHC's s generalizability with 5, 5.26% NMAE reduction and 3.60% Pearson improvement compared to DE-HNN at the cell level, and 2.44% NMAE reduction and 1.64% Pearson improvement over Lay-Net at the grid level. This consistent performance across substantially larger dataset validates our method's 's universal applicability for congestion prediction in real-world VLSI design environments.
5.2.2 Design-level Results
To rigorously evaluate generalization entirely unseen circuit designs, conduct additional experiments following the design-level split setting (detailed setup in Appendix C.5). where training and test sets contain completely different circuit designs with no overlap. As shown Table 2, this setting presents significantly more challenging conditions with substantial performance degradation across all methods. Despite these challenges, MIHC maintains superior performance over baselines in the vast majority of metrics. For ISPD2015-B. MIHC outperforms DE-HNN with 7.55% reduction in cell-based NMAE and 5.68% improvement in Pearson correlation in the B B-AA experiments, while achieving 5.87% Pearson improvement in grid-based prediction over Lay-Net. For ISPD2015-F. MIHC achieves 6.35% cell-based NMAE reduction and 7.53% Pearson improvement in the A-BB direction. These results provide strong evidence that our method achieves genuine generalization capability rather than simply memorizing design-specific characteristics, offering realistic evaluation for weal-world deployment scenarios.
5.3 Explainability Results (RQ2)
To validate the effectiveness of our model's explainability module, we examine its capability to identify important structures chip congestion prediction scenarios. As demonstrated in Figure our bottleneck subgraph successfully captures critical congestion regions, and MIHC achieves
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Lay-Net
Our Bottleneck
MIHC (Ours)
Gound Truth
Figure 2: Visualization of heat maps on ISPD201 superblue 16 design showing Lay-Net,
bottleneck subgraph, MIHC (Ours), and ground truth congestion maps.
Table 3: Ablation Study of Model Modules on ISPD2015-B. The best in bold.
Mede Variants
NXIVE:
NRMSS
Callenee Korile
Parset
Speainas
Kastaff
NADEE
NESS.
Gnd loael Boals
Poaset
Spearent
Keecolt
0.006 (0.09)
6.41
0.550 (00.58
0,51 (333))
(1
0.39
0.482 (1698)
0,187
0.444
wio I5M
0.81 (11399)
880 (134.36)
6444 (31.59)
0,643 (116.593
0.3% (n 12
0,055 (113.56)
0,009 ( 1526)
0652 (nds
0353 (142.9 0251 (k527%)
Fall Madel
00029 (
8667
0.689 (x2469)
0.574 (666))
0JA3 (-200))
(1177)
0665
0.207 (6614%)
(.25(4777.8)
Table 4: Ablation Study of Different Loss Functions ISPD2015-B.
Loes Crenseess
Cellbneed Reaehs
Gratbniel Rocks
112-7
12311
11337
1031
0.00 (AU005)
LLON 73%
Dusan 7003:
0.300 (6.21))
59%)
2060
0.E39 I-S (690
0.992 (43,0001
E000 119
0.350 (49-110
DARe 1888
0.565 (68.228)
0.299 (4211
0.348 2031
6U09 12.17
(1165%)
8:08 (a 17%
0.574 12.38%
09066 14.99%)
0,65 (412211))99))
8:39 19%)
0,398 (432.999)
predictions that closely match the ground truth patterns, underscoring its superior interpretability. Additionally, the bottleneck subgraph heat map indicates that our IB bottleneck subgraph can be extracted to reveal regions relevant to the final prediction results. While node-level predictions identify congestion points, our Information Bottleneck identifies the critical local structures that cause these anomalies, revealing the structural patterns that contribute to surrounding node congestion rather than just detecting generic anomalies. This is particularly important in circuit design where congestion typically emerges from interactions between neighboring components rather than isolated elements. Due the lack of publicly available datasets for interpretability in the EDA domain, also briefly evaluated our model on the MNIST 0/1 dataset, where it demonstrated strong consistency across various metrics in Table [6 In comparison, baseline methods showed significant limitations: GAT+GNNEXplainer suffered from low precision while SIGNET failed to capture comprehensive node relationships. These results, combined with the visual evidence from chip congestion heatmaps, confirm that MIHC not only delivers superior prediction accuracy but also provides meaningful explainability for practical VLSI design applications.
5.4 Ablation Study(RQ3)
In ablation studies, we conducted two sets of experiments on ISPD2015-B to evaluate: the contribution of different model modules (Table and the impact of different loss functions 4Ta
The ablation results of model modules in Table reveal several important findings. First, removing the Multi-View Representation Learning Module (w/o MV-HGNN) results in performance similar to the basic HGNN but significantly worse than the Full Model, demonstrating the crucial role of multi-view information fusion. Second, excluding the Interpretable Subgraph Module (w/o ISM) yields better results than basic HGNN but still underperforms compared to the Full Model, with substantial decreases in correlation metrics (13.3% lower Pearson for cell-based results). Finally, the Full Model achieves optimal performance across all metrics by effectively combining ISM for critical information filtering with MV-HGNN for multi-view integration, showing impressive improvements over the baseline HGNN (19.1% % Pearson improvement for cell-based results).
The comprehensive ablation results in Table 4 systematically demonstrate the effectiveness evaluation of different loss functions. The experimental results show that using both Cell and Grid Supervised loss consistently achieves better performance (NMAE=0.031 for cell-based, 0.033 for grid-based)

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Pearssn
Spenrmenn
Kendel
a)
b)
d)
2.7-
0.1
6.7
9.6
0.5-
6.5
2.4
0.4
Hicken
3.3
22yer
0.3
0.5
0.3
0.3
0.3
32
01
1.99
556
32
129
256
0.8
Cell-based
Grid-based
Cell-based
Grid-based
Figure 3: Hyperparameter sensitivity analysis: Impact of hidden dimensions (a,b) and MV-HGNN
layer number (c,d) on cell-based and grid-based performance.
compared to single-view supervision (Cell-Sup only: 0.033, 0.037; Grid-Sup only: 0.035, 0.034), thus validating the fundamental importance of multi-view information fusion by using multi-view loss. Furthermore, through detailed comparative analysis, the removal of IB loss (w/o IB Loss) leads to substantial performance degradation (Pearson correlation decreases by 4.21% for cell-based results), confirming its crucial role in guiding the model to extract essential subgraph components.
5.5 Parameters Sensitivity(RQ4)
We conduct a comprehensive hyperparameter analysis of MIHC on ISPD2015-B, specifically exam- ining the impact of Multi-View HGNN layer number (ranging from I to 6) and hidden dimensions (varying from 32 256) on model performance. As illustrated in Figure 3 MIHC demonstrates robust stability across different hyperparameter configurations. However, notable performance degra- dation occurs two specific configurations: when the model is configured with single Multi View HGNN layer or when the hidden dimension is set to 32. These significant performance drops can be attributed to insufficient model capacity, as either single layer or a small hidden dimension proves inadequate for learning the complex hierarchical features and relationships inherent in the data.
6
Conclusion
This paper presents MIHC, novel interpretable hypergraph neural network for circuit congestion prediction. Through its balanced multi-view hypergraph architecture with net-based bridging. MIHC achieves effective fusion of netlist and layout information, providing a comprehensive understanding of circuit characteristics. The incorporation of subgraph Information Bottleneck mechanism further enhances the model by identifying critical subgraphs correlated with congestion patterns and leveraging this selective information to improve prediction accuracy. Our comprehensive experiments demonstrate MIHC's superior performance compared to existing methods, achieving significant improvements in both cell-based and grid-based prediction tasks. This synergistic combination of balanced multi-view information fusion and interpretable bottleneck analysis represents a meaningful advancement in trustworthy Electronic Design Automation, establishing foundation for future interpretable machine learning approaches in integrated circuit design.
Limitations. While MIHC achieves significant performance improvements, there remain areas for enhancement. The Information Bottleneck mechanism, though effective for interpretability. introduces computational complexity that could be optimized with more efficient algorithms. Additionally, our comparative analysis between ISPD2015-B and ISPD2015-F indicates that performance on imbalanced datasets, while still superior baselines, presents opportunities for improvement- challenge shared across current congestion prediction approaches. Future work will address these aspects while maintaining MIHC's interpretability and prediction accuracy advantages.
Broader impacts. Our interpretable hypergraph model enhances EDA performance with limited impact. There is minimal possibility that without proper validation, over-reliance risks erroncous decisions chip design.
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Acknowledgements
The authors H.P., P.Z., X.X., and P.B. acknowledge the support by the U.S. Army Research Office (ARO) under Grant No. W911NF-23-1-0111, the National Science Foundation (NSF) under the NSF Award 2243104 under the Center for Complex Particle Systems (COMPASS), the Career Award CPS-1453860, Career Award 2337412, CNS-1932620, and NSF Mid-Career Advancement Award BCS-252700 the Defense Advanced Research Projects Agency (DARPA) Young Faculty Award and DARPA Director Fellowship Award under Grant Number N66001-17-1-4044 Intel faculty awards and a Northrop Grumman grant. P.B. is also grateful National Institute of Health (NIH) for the grants RO1 AG 079957 "Interpretable machine learning to synergize brain age estimation and neuroimaging genetics" and RF1 AG 082201 "Neurovascular calcification and ADRD in two nonindustrial Native American populations". . It was wonderful experience designing and writing the grant application entitled "Neurovascular calcification and ADRD in two nonindustrial Native American populations" and awarded under RFI AG 082201. The authors Z.Z. and X.L. acknowledge the support by NSFC (No. 72171229), the MOE Project of Key Research Institute of Humanities and Social Sciences (No. 22JJD1 10001), and Big Data and Responsible Artificial Intelligence for National Governance, RUC. The views, opinions, and/or findings in this article are those of the authors and should not be interpreted official views or policies of the Department of Defense, the National Institute of Health or the National Science Foundation.
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A Muti-View Information Bottleneck Loss Computation
As shown in Eq (4) we wirte the objective of the cell-based hypergraphs HC loss function
as follows:
c ---
1 I1 : + 1 S H
(16)
where B is the trade-off parameter for _ and we aim to minimize Eq (16) during the training. Similarily, the objective of the grid-based hypergraphs HG can be wirtten loss function as follows:
1
C = gG IH H + I(H H H³).
(17)
where 3 is the trade-off parameter for LG.
Then, we compute the average loss of C and L which helps us to optimize both HŠ and Hg:
Leombination 2 3
1 1
11 H I111 H H²)) + 2 3 1 Hg) + 1 (H, Hg (²))
(TH HÓ HO) - THH; H HO) 2
I(HC Hg) + 3G TH H
= 2
2 gc
For term I 1HHC; HH | H)), we can derive his upper bound. The conditional mutual information
C H HC) is defined as:
1,(H1;15 H9) BpHHS [DKL (po(Ht)
H ( H9)],
(18)
where the Kullback-Leibler (KI.) divergence is given by:
p(x)
DKL())lg) ppx())
log
(19)
((x))
Substituting the definition of KL divergence into the conditional mutual information:
log Po H²) po ( HG)
To(HC; HO) EH HC*p(H" HHy.H Her.:
po (HŞ =Hs
HC = H9)
= Ene H Hoy E P
log
pa (HŞ Hs
HG= = H9)
Then, we derive the upper bound of To (HC; H H²):
log Po = Hs HC = HD)
la (1C: Hg 19 = E _ ~pCH" , Pp (om
Po Po HH = Hg HG = HG= HD)
po (H Hs|lI 11) p,(11 Hs 11 11
En no soo E Ha HO)
py (H Hc =
po(11 = Hs = H
DRL (po(H))
HO) p. (HŞ
HO)
DxL (Ho H0) py (H) H))
S DEL (po(Ht) 119) p. (1 HO)).
Similarly, we can get the upper bound for I(HG; Hg H²)):
T(HO; H& H)) S DEL (Ho HO) || (H HO))
Therefore, the upper bound for the first term is:
2 (1HHQ H HD) + T(H H$ HC)
s (Dri (po(H) HO) || p H²) - DKL. (po(HS (H) || ( (H))
= DsKL (po(HS H0) |l (H) H²))
21

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where (-) denotes the symmetrized Kullback-Leibie (SKL) divergence.
Then, look at the T(H;; Hg) in the second term. According to the symmetry of mutual information,
i.e. T(x;Y)= T(Y; and the chain rule of mutual information, i.e., T(x; Y, 2) = T(X;Y)
T(X; Z can have:
I(H: H = ((H::H)) -0) IHH Hg. H
= I[H H + I IHI; H (
Since the conditional mutual information is always non-negative, we can infer:
1 1 20
(20)
Therefore, we can get the lower bound of I(H ( as:
I I(H;; 2 1 TH Hg).
(21)
Similarly, for I(H;; H we can get,
T(HC; H 2 I( :
(22)
Therefore, the second term gets the upper bound:
ス/ go 1111 ($ + 3 11H (1H)
1
s /
2 gc [HH. H + 3G I I H))
BC + 3G
2g TH H
Therefore, the combination loss has an upper bound:
g + gG 233 gG I( H
Leombination S DSKL (po(H)) Hº) ll P. (H H9)
By scaling both terms with 2 मC and re- re-paramcterizing the objective, we derive a tractable
loss function for the MVIB framework:
CMVIB = IIHS H$) + 3Dskl (po H p. (H H))),
(23)
where ( H and p., ( H²) represent the bottleneck subgraph extractors for HC and H parameterized by 0 and respectively, and DsKL(-) denotes the symmetrized Kullback-Leibler (SKL) divergence. The hyperparameter 3 controls the trade-off between the two terms.
B Mathematical Notations
Tables 6 summarize the mathematical notations used throughout the MIHC framework. Table covers the fundamental problem formulation and basic Information Bottleneck concepts, while Table details the components specific to multi-view representation learning and bottleneck mechanisms. Together, these notations describe the dual hypergraph structures that enable balanced fusion of topological and geometric circuit information for interpretable congestion prediction.
C Experimental Details
C.1 Code Availability.
Our code is available in this link: http::///gituub..om//piigggggee
22

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Table 5: Mathematical Notations I: Problem Formulation and Information Bottleneck Framework
Notation
Description
L
Number message passing layers
P
Grid-based layout representation, E RRMXNXK
M,N
Grid dimensions
K
Number features per grid cell
G
Cell-based hypergraph representation, (V, E) Set of nodes (cells)
V
E
Set of hyperedges (nets)
CG
Grid congestion map, E R M
CO
Cell congestion graph, E RI
ČG
Predicted grid congestion map
CC
Predicted cell congestion graph
fo
Predictive model parameterized by 0
Cup
Supervised loss function
X
Input variable in Information Bottleneck framework Target variable in Information Bottleneck framework
Y
T
Intermediate representation in Information Bottleneck framework
I(::))
Mutual information between and
I(:Y)
Mutual information between T and Y
g
Trade-off parameter in Information Bottleneck framework
HC
Cell-based hypergraph
HG
Grid-based hypergraph
ve
Node set in cell-based hypergraph
EC
Hyperedge set in cell-based hypergraph
XC
Feature node cell-based hypergraph
VG
Node in grid-based hypergraph Hyperedge set in grid-based hypergraph
EG
XC
Feature of node in grid-based hypergraph
C.2 Hypergraph Construction Details
As shown in Figure a of our paper, we construct hypergraphs from eircuit data through a specific process. In the layout example of Figure[Taa, we have 10 circuit components (cells), each represented as node the cell-based hypergraph. The layout is simultaneously divided into grid cells, with each grid cell becoming node in the grid-based hypergraph. The circuit nets connecting multiple circuit components are modeled as hyperedges in both representations. For the cell-based hypergraph, cells connected by the same net form hyperedge. As illustrated in Figure (() in the top-left diagram, blue cells 2, 5, 6, and 7 are connected by the same net, thus forming one hyperedge the cell-based hypergraph.
For the grid-based hypergraph, grid cells traversed by the same net are connected via a hyperedge. Additionally, spatially adjacent grid cells are also connected through hyperedges to preserve geometric proximity information. As shown in Figure [c) in bottom-left diagram, green grid cells 1, 4, 5, and 6 are traversed by the same net, thus forming one hyperedge in the grid-based hypergraph. Simultaneously, adjacent grid cells like 1-2, 2-3, 4-5, etc., would form their own hyperedges based on spatial adjacency.
C.3 ISPD-2015 Benchmark Dataset
The ISPD-2015 benchmark consists of 20 industrial designs from various applications, with circuit sizes ranging from 29K to 1.3M cells, shown in Table These designs include both standard cells and macro blocks, presenting realistic challenges in placement and routing congestion prediction. Each design in the dataset includes:
Circuit netlist information with both standard cells and macro blocks
Placement solutions generated using Cadence Innovus v17.1 with varying parameters
23

---

Table 6: Mathematical Notations II: Multi- View Representation Learning and Bottleneck Components
Notation
Description
H
Bottleneck subgraph cell-based hypergraph
H
Bottleneck subgraph of grid-based hypergraph
g
Trade-off parameter for cell-based Information Bottleneck
Po. P-
Probability model for bottleneck subgraph extraction
M
Incidence matrix of cell- hypergraph
XC
Node features of cell-based hypergraph Probability vector for node selection
X
Node features of cell-based bottleneck subgraph Cell nodes associated with grid node g. Learnable weights for feature reweighting
((oC)
WC ww
L
Multi- View Information Bottleneck loss Symmetrized KL divergence
Dskl
he
Hyperedge embedding in cell-based hypergraph
hā
Hyperedge embedding in grid-based hypergraph
(e(e)
Nodes in cell-based hyperedge
(e)
Nodes in grid-based hyperedge
Net-based hyperedge embedding
ic
Intermediate cell-based node embedding
AN
Intermediate net-based node embedding
(v)
Cell-based hyperedges containing node v Net-based hyperedges containing node w Updated cell-based node embedding Intermediate grid-based node embedding
EN
N (c)
Spatially adjacent grid nodes to node r
Updated grid-based node embedding
C
Cell-based subgraph embedding
hi
Grid-based subgraph embedding
Connt
Contrastive loss
Temperature parameter in contrastive loss
GC
Predicted cell-based node congestion
Predicted grid- badd-baed node congestion
Liotal
Total loss function
Ground truth congestion maps derived from global routing solutions
The dataset provides several key features for congestion prediction:
RUDY (Rectangular Uniform wire DensitY): Models the routing demand within bounding boxes of nets
PinRUDY: Represents pin density distribution in grid cells
MacroRegion: Binary indicators for regions covered by macro cells
Horizontal/Verticll MacroMargin: Measures distances between margins of adjacent macros
For experimentation purposes, 533 different placement solutions were generated for each design using Innovus with varying parameters, resulting in a comprehensive dataset for training and evaluating congestion prediction models. The dataset divides the circuit layout into an M x N grid, with each grid cell represented as a pixel containing multiple feature channels. The routing overflow ground truth is provided in both horizontal and vertical directions.
C.4 CircuitNet-N28 Benchmark Dataset
The NircuitNet-N28 comprehensive open-source dataset specifically designed for machine learning applications in VLSI CAD, particularly for cross-stage prediction tasks. It contains 10242

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Table 7: Detailed Information of ISPD-2015 Benchmark Designs
Design
#Cells
#Nets
Category
des perf 1
113K
113K
Medium
des jus__errf__ des_perf_h
109K
110K
Medium
113K
113K
Medium
edit_ adit_diitt_ fft_1 fft_ fī
130K
131K
Medium
35K
33K
Small
35K
33K
Small
34K
32K
Small
ff_b
34K
32K
Small
matrix Latrri_mmlt__
160K
159K
Large
matrix mult 2 matrix mult a
160K
159K
Large
154K
154K
Large
matrix matrix_mult__ b
15IK
152K
Large
matrix_mult_
151K
152K
Large
pei aci_bridge32__
30K
30K
Small
pei_bridge33__
29K
29K
Small
superblue I_a
954K
936K
Very Large
superblue12
1.3M
1.3M
Very Large
superblue14 14
634K
620K
Very Large
superblue
698K
697K
Very Large
superblue19
522K
512K
Very Large
layout samples extracted from versatile runs of commercial design tools based six open-source RISC-V V designs a 28nm technology node, as shown Table
Circuit data is generated from six RISC-V designs (RISCY, RISCY-FPU, zero-riscy, and their variants)
Layouts are generated using commercial tools (Cadence Innovus v20.10) with diverse parameter settings
Ground truth labels include congestion, DRC violations, and IR drop information
The dataset provides several key features for prediction tasks:
Macro Region: Regions covered by macros which are fixed during placement
Cell Density: Cell distribution in each tile
RUDY & Pin RUDY: Routing demand estimation for nets and pin density
Pin Configuration: High-resolution representation pin and routing blockage patterns
Congestion: Overflow of routing demand in each tile
CireuitNet-N28 introduces significant diversity through various design parameters, including five core utilization settings (70%-90%). three macro placement strategies, eight power mesh combinations, and different filler insertion approaches. This results in 240 combinations of settings for each netlist, creating dataset with substantial variation that better reflects real- sal-world design scenarios. The tile size for all feature maps is 1.5 um 1.5 ym, aligning with the global routing cell size in commercial tools.
Table Detailed Information of CircuitNet-N28 Benchmark Designs
Design
#Cells
#Nets
Cell Area (um²)
RISCY-a
45,717
47,759
65,739
RISCY-FPU-a
65,793
68,351
75,985
zero-riscy-a
34,299
43,970
58,631
RISCY-b
31,311
33,970
69,979
RISCY-FPU-D
51,126
54,327
80,030
zero-riscy-b
20,946
22,692
62,648
25

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C,5 Data Split Strategies
We employ two distinct data partitioning strategies to comprehensively evaluate our model's perfor- mance and generalization capability: plabbilmtyppaccmmeett placement-level split and design-level split.
C.5.1 Placement-level Split
The placement-level split follows standard design-level partitioning strategy where all designs appear in both training and testing sets, but with different placement solutions. As shown in Table] 7 the ISPD2015 dataset contains 20 circuit designs, each with multiple placement solutions generated using different synthesis and placement parameters. For each design, we divide its corresponding placements into training and testing sets with a 7:3 ratio. This results in:
ISPD2015-F: 374 training samples and 159 testing samples (all 20 designs including superblue series, 533 total placements)
ISPD2015-B: 269 training samples and 114 testing samples (15 designs excluding superblue series, 383 total placements)
For CireuitNet-N28 (Table 8). we follow a similar approach across its 10,242 samples from six RISC-V designs, resulting in 7,170 training samples and 3,072 testing samples, maintaining the 7:3 ratio. This approach ensures all designs appear in both training and testing sets, allowing for comprehensive evaluation of model performance on known design types.
C.5.2 Design-level Split for Generalization Evaluation
To rigorously evaluate model's generalization capability entirely unseen circuit designs, conduct additional experiments following the design-level split setting. Unlike the placement-level split, this setting ensures training and test sets contain completely different eircuit designs with no overlap between design families, providing a more stringent evaluation that better reflects real- world scenarios where models must generalize new designs during deployment.
ISPD2015-B Design Partitioning For ISPD2015-B containing 15 designs, we partition them into two groups ensuring designs with the same prefix remain together:
Group A (8 designs): des des_perf__. des jess_perf_a_ a, des fis_perf__ b, fft fft_1 fft_2, fft a, fft_b. edit dist_a
Group (7 designs): matrix_mil mult_1, matrix_mule matrix matrix_mult_a, a, matrix matrix_mult_b, mnarrx_mmlttc. voi_bridge32_a, pci_ bridgeeee3_bb
ISPD2015-F Design Partitioning For ISPD2015-F containing 20 designs, we use 10 vs 10 split:
Group A (10 designs); des des_perf series (3 designs: des_perf_1, des_ des_perf_a, a, des_pert (es_perf_bb, fft
series (4 designs: fft fft_1, fft 2, fft fft fft_b), edit dist superblue12, superblue
matrix_mult mult series (5 designs: matrix_mui 1_tt__mut_,1,, ma- trix_mult_2 matrix_miiiii _actiii___ttta__e matrix_mil b, matrix_miit_e bridgee series designs: pei pei_bridge32_a, a, pei_bridge32_b) superblue 1 superblue 14, superblue19
Group B (10 designs):
This partitioning strategy ensures that:
1. Designs with the same prefix (indicating functional similarity) remain in the same group, preventing information leakage between functionally related circuits
2. Both groups contain mix of different design families and sizes
3. The evaluation captures the model's 's true capability to handle entirely unseen circuit archi- tectures
Bidirectional Evaluation
We conduct bidirectional evaluation to provide comprehensive assess-
ment:
A- Train on all placement solutions from Group A designs, test on all placement solutions from Group B designs
26

---

2. B-+A: Train on all placement solutions from Group B designs, test on all placement solutions from Group A designs
This bidirectional approach ensures our evaluation not biased by the specific choice of train- ing/testing groups and provides robust evidence of generalization performance across different design families.
C.6 Evaluation Metrics Details
This study employs a variety of evaluation metrics to assess the performance of the proposed model, including NMAE, NRMS, Pearson correlation, Spearman correlation, Kendall's for chip congestion prediction and Accuracy (ACC) for graph anomaly detection. Below are the definitions and mathematical formulations of each metrie:
Normalized Mean A bsolute Error (NMAE): NMAE measures the average absolute difference between predicted and true values, normalized by the range of the values. It defined
- I=1
y 9:1
NMAE
max min(y)
where Yi is the true value, it is the predicted value, and max(v) and min represent the maximum and minimum values of the true data, respectively. A lower NMAE indicates better predictive accuracy.
Normalized Root Mean Square Error (NRMS): NRMS quantifies the deviation between the predicted and actual values, normalized by the range of the true values. It is computed as:
NRMS
(ve 0.)
max y)) min (y)
This metric penalizes larger errors more heavily, making useful for evaluating prediction accuracy.
Pearson Correlation Coefficient (Pearson): The Pearson correlation coefficient measures the linear relationship between the predicted and true values, with values ranging from -1 (perfect negative correlation) to (perfect positive correlation). It is given by:
E (vs 0) 1)
Pearson
2i=1 (v4 7) Ex (0r 0)
where y and I represent the mean of the true and predicted values, respectively.
Spearman Rank Correlation (Spearman): Spearman's 's rank correlation coefficient assesses the monotonic relationship between the true and predicted values by considering their ranks. It is calculated as:
6 6. d nnn² 1)
Spearman
where d; is the difference in ranks for each pair of corresponding values, and n the number of data points.
Kendall's Tau (Kendall): Kendall's tau another measure rank correlation, specifically focusing on the concordance and discordance between pairs of predictions. It is defined as:
C
Kendall
m(n-1)
2
where C is the number of concordant pairs, D is the number of discordant pairs, and is the number of data points.
C.7 Parameter Setting
In this section, we present the key implementation details of our model. The detailed parameter settings are listed in Table
The key parameters include:
27

---

Table 9: Model Parameter Settings
Parameter
Value
Parameter
Value
Hidden Dimension
128
Learning Rate
le-4
# MV-HGNN Layers
4
Batch Size
4
# MI. Layers
Temperature 7
0.07
IB Weight 3 # Attention Heads
0.1
Dropout Rate
0.1
Optimizer
Adam
Hidden Dimension: The dimension of node embeddings in both cell-based and grid-based views.
# MV-HGNN Layers: Number of Vuew Heterogeneous Graph Neural Network layers.
# MLP Layers: Number layers in the prediction module MLPs.
IB Weight 3: The trade-off parameter in Information Bottleneck loss.
Temperature т: Temperature parameter in contrastive learning.
# Attention Heads: Number of attention heads in message passing.
The model is trained using the Adam optimizer with learning rate of le-4. We apply dropout with rate 0.1 to prevent overfitting. The batch size is set to 32 for training efficiency.
C.8 Time Consumption and Memory Usage
C.8.1 Time Consumption
Our experiments on one NVIDIA A100 80GB GPU show practical performance across circuit scales. Small circuits (3K cells/nets) require only 0.3 seconds for inference and 0.9 seconds per training iteration, while very large circuits (1 (1.3M cells/nets) take 1.6 seconds for inference and 5.0 seconds per training iteration. These measurements confirm that despite the model's sophistication, its computational demands remain manageable for real-world industrial applications, with reasonable inference times even for the largest circuits.
C.8.2 Memory Usage
Our model's memory footprint scales efficiently with circuit size. Small circuits (3OK cells/nets) consume approximately 3GB of GPU memory, while even the largest circuits (1.3M cells/nets) require 22GB during training, well within the 80GB capacity of modern A100 GPUs, ensuring approach remains practical for industrial-scale designs.
D Result Supplement
D.1
Chip Congestion Prediction Results
Table 10: Cell based Results on ISPD2015-B, The best in bold and the second underlined.
ISPD201S-B
Model
NMAE]
NRMS}
Pearson
Spearman 0.498
Kendallf
GCN
0.038
0.044
0.547
0.421
GAT
0.039 (-2.63%)
0.045 (-2.27%)
0.531 (-2.94%)
0.517 (+3.81%)
0.463 (+9.95%)
HGNN
0.036 (+5.26%)
0.042 (+4.55%%
0.577 (45.50%)
0.553 (+11.05%)
0.476 (+13.07%)
CircuitGNN
0.034 (+10.53%)
0.040 (+9.09%)
0.598 (49.33%)
0.611 (422.68%)
0.487 (+15.68%)
LHNN
0.033 (613.
0.038 (+13.64%)
0.629 (+14.99%
0.627 (+25.90%)
0.502 (+19.24%)
DE-HNN
0.032 (+15,79%)
0.037 (+15.91%) 9
0.645 (+ 18.00%
0.632 (426.9195 %
0.520 (423.56%)
MIHC(Ours)
0.029 (+23.68%)
0.034 (+22.73%)
0.687 (+25.669%) %)
0.689 (+38.43%)
0.574 (+36,38%) %)
28

---

Table 11: Grid based Results ISPD2015-B and ISPD2015-F. The best in bold and the second underlined.
ISPD2015-B
Model
NMAE]
NRMS}
Pearsont
Spearmant
Kendall
GCN
0.043
0.049
0.405
0.162
0.137
GAT
0.044 (-2.33%)
0,050 (-2.04%)
0.398 (-1.73%)
0.144 (-11.12%)
0.141 (+2.92%)
HGNN
0.040 (+6.98%)
0.046 (+6.12%)
0,451 (+11.36%)
0.184 (+13.58%)
0.142 (+3.65%)
RouteNet
0.038 (+11.63%)
0.045 (48.16%)
0.522 (+28. 82%)
0.198 (+22.22%)
0.157 (+14.60%)
CircuiIGNN
0.037 (+13.95%)
0.043 (+12.24%)
0.561 (+38.39%%
0.201 (+24.07%)
0.164 (+19.71%)
CircuitFormer
0.034 (+20.93%)
0.040 (+18.37%)
0.649 (+60.74%)
0.231 (+42.59%%
0.169 (423.36%)
LHNN
0.033 (+23.26%)
0.040 (+18.37%)
0,651 (+60.74%)
0.252 (+55.56%)
0.217 (+58.39%)
Lay-Net
0.031 (+27.91%)
0.037 (+24.49%)
0.667 (+64.57%)
0.301 (+85.19%)
0.248 (+81.76%)
MIHC (Ours)
0.030 (+30.23%)
0.036 (+26.53%)
0.675 (+66.67%) %)
0.297 (+83.95%)
0.252 (+83.94%)
Table 12: Cell based Results on ISPD2015-R. The best in bold and the second underlined.
ISPD2015-F
Model
NMAF]
NRMS}
Pearsonf
Spearmant
Kendalf
GCN
0.051
0.058
0.344
0.336
0.309
GAT
0.050 (+1.96%)
0.057 (+1.72%)
0.351 (+2.03%)
0.342 (+1.79%)
0.298 (-3.55%)
HGNN
0.045 (+11.76%)
0.052 (+10.34%)
0.410 (+19.21%)
0.366 (+8.93%)
0.309 (0.00%)
CircuitGNN
0.046 (+9.80%)
0.053 (+8.62%)
0.402 (+16.85%)
0.378 (+12.50%)
0,316 (+2.27%)
LHNN
0.043 (+15,69%)
0.049 (+15,52%)
0.448 (+30.23%)
0.384 (+14.29%)
0,364 (+17.80%)
DE-HNN
0.042 (+17.65%%
0.048 (+17.24%)
0.467 (+35.80%)
0.395 (+17.57%)
0.381 (+23.32%)
MIHCC(Ours)
0.035 (+31.37%)
0.041 (+29.31 %)
0.524 (+52.33%)
0,512 (452.38%)
0.447 )
Table 13: Grid based Results on ISPD2015-R. The best in hold and the second underlined.
ISPD2015-F
Model
NMAEE
NRMS}
Pearsonf
Spearmant 0.152
Kendall
GCN
0.046
0.053
0.357
0.131
GAT
0.048 (+4.35%%
0.055 (43.77%)
0.331 (-7.28%)
0.137 (-9.87%)
0.116 (-11.47%)
HGNN
0.043 (+6.52%%
0.050 (45.66%)
0.352 (-1.40%)
0,147 (-3.29%)
0.121 (-7.63%)
RouteNet
0.042 (+8.70%)
0.050 (+5.66%%
0.362 (+1.40%)
0.161 (+5.92%)
0.137 (+4.58%)
CircuiGGNN
0,042 (+8.70%)
0.049 (+7.55%)
0.364 (+2.00%)
0.162 (+6.58%)
0.134 (+2.29%)
CircuitFormer
0.038 (+17.39%)
0.045 (+15.09%)
0.453 (+26.91%)
0.196 (428.95%)
0.165 +22.022)
LHNN
0.037 (+19.57%)
0.044 (+16.98%)
0.464 (+29.97%)
0.221 (445.39%)
0.182 (+38.93%)
Lay-Net
0.035 (+23.91%)
0.042 (+20.75%)
0.484 (+35.53%)
0.256 (+68.42%)
0.208 (+58.02%)
MIHC (Ours)
0.032 (+30.43%)
0.039 (+26.42%)
0.503 (+41.00%)
0.271 (+78.95%)
0.227 (+73.25%)
Table 14: Cell based Results on CireuitNet- The best in bold and the second underlined.
CircuitNet-N28
Model
NMAEJ
NRMS}
Pearsonf
Spearmant
Kendall
GCN
0,045
0.051
0.516
0..438
0.319
GAT
0.046 (-2.22%.
0.051 (+0.00%)
0.513 (-0.58%)
0.447 (+2.05%%
0.321 (+0.63%)
HGNN
0.044 (+2.22%%
0.048 (+5.88%)
0.552 (+6.98%)
0.468 (+6.85%)
0.332 (+4.08%)
CircuitGNN
0.040 (+11.11%)
0.043 (+15.69%)
0.609 (+18.02%)
0.500 (614.16%)
0.368 (+15.36%)
LHNN
0.039 (+13.33%)
0.043 (+15.69%
0.617 (+19.57%)
0.509 (+16.21%)
0.366 (+ 14.73%)
DE-HNN
0.038 (+15.56%%
0.042 (+17.65%)
0.638 (+23.64%)
0.511 (+16.67%%
0.374 (+17.24%)
OIHC(Ours)
0.036 (+20.00%%
0.039 (+23.53%)
0.661 (+28.10%)
0.522 (+19.18%)
0.396 (+24.14%)
D.2
Expalination Results
Due to the lack of publicly available. interpretable datasets in the EDA domain, we use the commonly adopted MNIST 0/1 dataset to demonstrate the explainability of our proposed MIHC. To validate the effectiveness of the explainability module in our model, we conduct explainability testing experiments on these datasets to test our model's capability in identifying important nodes in the graph through node-level explainability testing. The results of these tests are presented in Table [6] Our proposed method demonstrates strong consistency across both datasets, exhibiting high performance across various evaluation metrics. This suggests that our approach provides reliable and coherent explanations across different types of data, indicating that the model's interpretability is robust and can generalize well. The consistent high scores in all the key metrics underscore the model's 's ability to
29

---

Table 15: Grid based Results CircuitNet-N228. The best in bold and the second underlined.
CircuiNNet-228
Model
NMAEL
NRMS}
Pearsonf
Spearmant
Kendall
GCN
0,052
0.053
0,417
0.399
0.312
GAT
0.052 (+0.00%)
(-5.
0.411 (-1.44%)
0.405 (+1.50%)
0.323 (+3.53%)
HGNN
0.051 (+1.92%)
0.052 (+1.89%)
0.442 (+6.00%)
0,424 (46.27%)
0.331 (+6.09%)
RouteNet
0.047 (+9.62%)
0.049 (47.55%)
0.541 (+29.74%)
0,501 (+25.56%)
0.373 (419.55%)
CircuitGNN
0.047 (+9.62%)
0.048 (49.43%)
0.547 (431.18%)
0,508 (+27.32%)
0.371 (41899%))
CirmuitFormer
0.044 (+15.38%)
0.046 (+13.21%)
0.622 (+49.16%)
0.526 (+31.83%)
0,384 (423.08%)
LHNN
0.043 (+17.31 %6)
0.044 (+16.98%)
0.646 (+54.92%)
0.533 (+33.58%)
0,389 (424.68%)
Lay-Net
0.041 (+21.15%)
0.043 (+18.87%)
0.671 (+60.91%) %)
0,558 (+39,85%)
0.406 (+30.13%) 3))
MIHC (Ours)
0.040 (+23.08 %
0,041 (+22.64%)
0.682 (+63.55%)
0.572 (+43.36%)
0.402 (+28.85%)
Table 16: Node explanation test on MNISTO and MNISTI. The best in bold and the second underlined.
Dataset
Method
ACC
Precision
Recall
F1
AUC
0.742
0.669
0.725
0.696
0.697
GCN+GNNE
0.527
0.343
0.500
0.407
0.554
GAT+GNNE
0.419
0.349
0.917
0.506
0.689
SIGNET
0.650
0.995
0.041
0.078
0.615
0.721
0.642
0.698
0.669
0.685
GCN+GNNE
0.527
0.359
0.583
0.444
0.573
GAT+GNNE
0.419
0.321
0.708
0.442
0.594
SIGNET 0.650
1.000
0.041
0.079
0.522
offer actionable and meaningful insights for decision secision-making in practical applications. In comparison, baseline methods show significant limitations. GAT+GNNE suffers from low precision despite high recall, while SIGNET achieves high precision but fails to capture comprehensive node relationships, leading to low recall scores. The core principle of part of the gemains the same across both MNIST and chip congestion scenarios.
-iaaabiitty-idnnififiinn the most important
Furthermore, to demonstrate MIHC's explainability under realistic congestion scenarios, we present chip congestion heatmap Figure 2 This visualization highlights the model's capability accurately localize critical regions on the chip. As clearly shown, MIHC achieves the closest match to the ground truth, underscoring its superior interpretability.
D.3 Hyper-parameter Sensitivity
Detailed results of paree--ar sensitivity are shown in Table 17 and Table T8
Table 17: Hidden Dimension Sensitivity Analysis on ISPD2015-B
Cell-based Results
Grid-bused Results
Hidden Dim
NMAFJ
NRMS
Pearson"
Spearmant
Kendallf
NMAFJ
NRMS..
Pearsonf
Spearmant
Kendallf
0.040
0.579
0.592
0.484
0.041
0.045
0.477
0.199
0.151
64
0.030
0.036
0.663
0.668
0.551
0.032
0.037
0.662
0.281
0.246
128
0.029
0.034
0.687
0.689
0.574
0.030
0.036
0.675
0.297
0.252
256
0.029
0.034
0.682
0.688
0.577
0.030
0.036
0.676
0.294
0.250
30

---

Table 18: Multi-view HGNN Layer Number Sensitivity Analysis on ISPD2015-B
Cell-based Results
Grid-based Results
#Layers
NMAE,
NRMS}
Pearson
Spearman
Kendall
NMAE
NRMS.
Pearson
Spearman
Kendall
0.033
0.039
0.612
0.619
0.492
0.039
0.044
0,510
0.148
0.030
0.035
0.679
0.672
0.566
0.031
0.036
0.672
0.290
0.251
0.029
0.034
0.690
0.681
0.571
0.030
0.036
0.672
0.294
0.252
0.029
0.034
0.687
0.689
0.574
0.030
0.036
0.675
0.297
0.252
0.030
0.034
0.688
0.684
0,571
0.030
0.037
0.671
0.288
0.247
0.030
0.035
0.666
0.554
0.031
0.037
0.669
0.288
0.248
31


Reviews:
[{"review_id": "N1EJJTo7M1", "reviewer": "Reviewer_ibfY", "summary": "This paper proposes a dual hyper graph approach to congestion prediction for chip design. Congestion prediction is an important problem because during the chip design process, when wiring congestion occurs, it can require a lot of disruptive changes to the design. If it can be predicted, it can be avoided earlier in the design process and therefore save a lot of time and money while improving the quality of results. However, predicting congestion is difficult, and although many prior works have made progress on this problem, it remains challenging. This paper proposes improving the congestion prediction model by using both a netlist hypergraph as well as a layout hypergraph in order to simultaneously understand the circuit as well as the proposed layout, combining them with an information bottleneck in order to better analyze the design. The proposed approach yields impressive results on standard academic benchmarks and also provides interpretability so that engineers can analyze the design and understand how congestion arises.", "questions": "Why is it ok to include subsets of the same designs in both training and test sets? \"This approach ensures all designs appear in both training and testing sets, allowing for comprehensive evaluation of model generalization capability.\" - I'm concerned this reduces the ability to comprehensively evaluate model generation.\n\nHow often do you train a new model and how much compute does it take?", "limitations": "yes", "rating": 4, "confidence": 3, "soundness": null, "presentation": null, "contribution": null, "strengths": "", "weaknesses": "", "quality": 3, "clarity": 3, "significance": 3, "originality": 2, "strengths_and_weaknesses": "The empirical results seem strong, and the high-level components seem reasonable. The paper is also clearly written.\n\nThe biggest weakness in my mind has to do with generalization. I wasn't clear whether the paper trains a single model and tries to generalize across all designs, or whether there were separate models trained for different designs. I had questions about the training/test split from the datasets the authors created, because generally it's easier for a model to make predictions about a design if very closely related circuits are in the training set. And in this case it appears the authors split up designs so that pieces of each design were both in the training set and the test set. \nAdditionally there are quite a few components to the model and it does seem a little complex. However, that is often the case in chip design methods. \nFinally I'd like to see more about training cost and frequency.", "was_revised": true, "final_justification": "I raised my score to reflect the authors' rebuttal and extra experiments. I still don't feel the experiments are 100% convincing, which is why I'm giving a borderline accept score. But I do like the paper.", "rebuttal": "We thank the reviewer for carefully identifying the concern regarding generalization and training cost, which we address in detail below, point by point. We also appreciate the positive remarks on our empirical results, overall design, and writing clarity.\n\n>W1: The biggest weakness in my mind has to do with generalization. I wasn't clear whether the paper trains a single model and tries to generalize across all designs, or whether there were separate models trained for different designs. \n\n**A:** Thank you for bringing this concern about model generalization. To clarify, in this work, we train a single model for each dataset that generalizes across all designs within that dataset. Specifically, we obtain three models in total: one trained on ISPD2015-B, one on ISPD2015-F, and one on CircuitNet-N28. Each model is trained to handle multiple different circuit designs simultaneously. For example, ISPD2015-F contains 20 different industrial designs (as shown in Table 6), and our model learns to predict congestion across all these diverse designs with a single set of parameters.\n\n>W2 + Q1: I had questions about the training/test split from the datasets the authors created, because generally it's easier for a model to make predictions about a design if very closely related circuits are in the training set. And in this case it appears the authors split up designs so that pieces of each design were both in the training set and the test set. \n\n**A:**\nThank you for raising this important and constructive question about our experimental setup. In our original experiments, we followed a placement-level split similar to Exp1 in Lay-Net [1], where different placement solutions from the same design appeared in both training and test sets. While this approach is useful for evaluating model performance on known design types, we notice that it could bring concerns about generalization capability since models might learn design-specific patterns rather than generalizable congestion prediction principles.\n\nTo address your concern and provide a more rigorous evaluation of generalization capability, we have conducted additional experiments following the unseen design experimental setup (Exp2) from Lay-Net [1]. In this setting, we performed design-level splits where training and test sets contain completely different circuit designs, ensuring no overlap between design families. Due to the time limit, we focus on ISPD2015-B and ISPD2015-F datasets for these additional generalization experiments. For ISPD2015-B, we divided the 15 designs into Group A (8 designs: des_perf series, fft series, and edit_dist_a) and Group B (7 designs: matrix_mult series and pci_bridge32 series). For ISPD2015-F, we used a 10 vs 10 split, with Group A containing des_perf series, fft series, edit_dist_a, superblue12, and superblue16_a, while Group B included matrix_mult series, pci_bridge32 series, superblue11_a, superblue14, and superblue19. This partitioning ensures that designs with the same prefix remain together, preventing any potential issues between functionally similar circuits. Following the Lay-Net [1] Exp2 experimental setup, we conducted bidirectional evaluation by training on Group A and testing on Group B, then reversing the roles to train on Group B and test on Group A.\n\nThe results from our unseen design experiments demonstrate significantly more challenging conditions, with substantial performance degradation across all methods compared to the seen design setting. As shown in the following experimental tables, which present the comprehensive results for both A→B and B→A training-testing directions across ISPD2015-B and ISPD2015-F datasets, MIHC maintains superior performance over state-of-the-art baselines in the vast majority of evaluation metrics across both cell-based and grid-based prediction tasks. For instance, in the B→A experiments, MIHC achieves the best performance in 18 out of 20 metrics, with only occasional slight disadvantages in specific cases such as Lay-Net's marginally better performance in grid-based Spearman correlation on ISPD2015-F. These results provide evidence that our method achieves genuine generalization capability rather than simply memorizing design-specific characteristics, offering a more realistic and stringent evaluation that better reflects real-world scenarios where models must generalize to entirely new circuit designs during practical deployment.\n\n**Table 1: Unseen Design Results - Group A Training → Group B Testing**\n\n| Model | ISPD2015-B |||||  ISPD2015-F ||||| \n|-------|-------|-------|----------|-----------|----------|-------|-------|----------|-----------|----------|\n|       | NMAE↓ | NRMS↓ | Pearson↑ | Spearman↑ | Kendall↑ | NMAE↓ | NRMS↓ | Pearson↑ | Spearman↑ | Kendall↑ |\n| **Cell-based** |\n| CircuitGNN | 0.058 | 0.064 | 0.376 | 0.335 | 0.248 | 0.071 | 0.077 | 0.343 | 0.304 | 0.218 |\n| LHNN | 0.054 | 0.060 | 0.398 | 0.355 | 0.265 | 0.067 | 0.073 | 0.368 | 0.321 | 0.235 |\n| DE-HNN | 0.051 | 0.057 | 0.415 | 0.372 | 0.282 | 0.063 | 0.069 | 0.385 | 0.342 | 0.252 |\n| MIHC (Ours) | **0.048** | **0.053** | **0.448** | **0.405** | **0.302** | **0.059** | **0.065** | **0.414** | **0.375** | **0.277** |\n| **Grid-based** |\n| CircuitGNN | 0.061 | 0.067 | 0.366 | 0.158 | 0.132 | 0.074 | 0.080 | 0.331 | 0.148 | 0.122 |\n| LHNN | 0.057 | 0.063 | 0.389 | 0.172 | 0.145 | 0.070 | 0.076 | 0.349 | 0.162 | 0.135 |\n| Lay-Net | 0.053 | 0.059 | 0.411 | 0.192 | 0.165 | 0.064 | 0.070 | 0.394 | 0.200 | **0.174** |\n| MIHC (Ours) | **0.051** | **0.057** | **0.436** | **0.218** | **0.188** | **0.064** | **0.069** | **0.405** | **0.201** | 0.167 |\n\n\n**Table 2: Unseen Design Results - Group B Training → Group A Testing**\n\n| Model | ISPD2015-B |||||  ISPD2015-F ||||| \n|-------|-------|-------|----------|-----------|----------|-------|-------|----------|-----------|----------|\n|       | NMAE↓ | NRMS↓ | Pearson↑ | Spearman↑ | Kendall↑ | NMAE↓ | NRMS↓ | Pearson↑ | Spearman↑ | Kendall↑ |\n| **Cell-based** |\n| CircuitGNN | 0.063 | 0.068 | 0.351 | 0.325 | 0.232 | 0.075 | 0.081 | 0.337 | 0.293 | 0.205 |\n| LHNN | 0.058 | 0.065 | 0.379 | 0.347 | 0.246 | 0.070 | 0.076 | 0.354 | 0.315 | 0.222 |\n| DE-HNN | 0.053 | 0.058 | 0.405 | 0.365 | 0.269 | 0.065 | 0.071 | 0.378 | 0.336 | 0.238 |\n| MIHC (Ours) | **0.049** | **0.055** | **0.428** | **0.384** | **0.281** | **0.062** | **0.067** | **0.399** | **0.357** | **0.262** |\n| **Grid-based** |\n| CircuitGNN | 0.064 | 0.070 | 0.348 | 0.148 | 0.122 | 0.077 | 0.083 | 0.318 | 0.138 | 0.112 |\n| LHNN | 0.060 | 0.066 | 0.369 | 0.162 | 0.135 | 0.073 | 0.079 | 0.337 | 0.152 | 0.125 |\n| Lay-Net | 0.055 | 0.061 | 0.392 | 0.197 | **0.179** | 0.068 | 0.073 | 0.367 | **0.191** | 0.152 |\n| MIHC (Ours) | **0.054** | **0.059** | **0.415** | **0.202** | 0.175 | **0.067** | **0.072** | **0.388** | 0.182 | **0.168** |\n\n\n[1] Lay-Net: Grafting Netlist Knowledge on Layout-Based Congestion Prediction. TCAD 2025\n\n\n>W3: Additionally there are quite a few components to the model and it does seem a little complex. However, that is often the case in chip design methods. Finally I'd like to see more about training cost and frequency.\n\n**A:** \nWe acknowledge that MIHC involves multiple components, but each serves a specific purpose essential for balanced fusion of netlist and layout information and providing crucial interpretability for circuit design validation. As you noted, this complexity is typical in chip design methods given the inherent complexity of circuit data. As shown in Appendix C.8, our experiments on one NVIDIA A100 80GB GPU demonstrate practical performance: small circuits (~30K cells/nets) require ~0.9 seconds per training iteration and 3GB memory, while very large circuits (1.3M cells/nets) take ~5.0 seconds per training iteration and 22GB memory. Based on our experimental setup, the total training time is approximately 1.5 hours for ISPD2015-B, 2.8 hours for ISPD2015-F, and 15.6 hours for CircuitNet-N28. We will include this discussion in the revised version. These measurements confirm that despite the model's sophistication, its computational demands remain manageable for real-world industrial applications.\n\n>Q2: How often do you train a new model and how much compute does it take?\n\n**A:** As shown in Appendix C.8, our experiments on one NVIDIA A100 80GB GPU demonstrate practical performance: small circuits (~30K cells/nets) require ~0.9 seconds per training iteration and 3GB memory, while very large circuits (1.3M cells/nets) take ~5.0 seconds per training iteration and 22GB memory. Based on our experimental setup, the total training time is approximately 1.5 hours for ISPD2015-B, 2.8 hours for ISPD2015-F, and 15.6 hours for CircuitNet-N28. These measurements confirm that despite the model's sophistication, its computational demands remain manageable for real-world industrial applications."}, {"review_id": "G1Prm5Yvue", "reviewer": "Reviewer_8ndm", "summary": "This paper proposes a multi-view hypergraph neural network framework for chip congestion prediction. This framework processes both graph and image information in hypergraph representations to fuse multi-view circuit data information. This framework also implements a subgraph Information Bottleneck mechanism to identify critical congestion-correlated regions. Experiments show this framework achieves great improvement on ISPD2025 and CircuitNet-N28.", "questions": "1. In equation (9),  $h_e^C$ and $h_e^G$ are concatenated. Does this mean cell-based and grid-based hypergraphs share the same topological structure (Because equation (9) concatenates the embedding of the same edge from two hypergraphs)? If not, how do you construct cell-based and grid-based hypergraphs to achieve this?", "limitations": "1. The Information Bottleneck mechanism introduces computational complexity.\n﻿\n2. Performance on imbalanced datasets (ISPD2025-F) is worse than on balanced datasets (ISPD2025-B).", "rating": 4, "confidence": 3, "soundness": null, "presentation": null, "contribution": null, "strengths": "", "weaknesses": "", "quality": 3, "clarity": 3, "significance": 3, "originality": 3, "strengths_and_weaknesses": "**Strengths**\n﻿\n1. MIHC naturally and effectively fuses the cell-based and grid-based information.\n\n2. Chip congestion prediction results (RQ1) show this framework achieves great improvement on ISPD2015-B and CircuitNet-N28.\n\n**Weaknesses**\n1. The illustration of MIHC’s interpretability performance(RQ2) is not clear.", "was_revised": true, "final_justification": "After reading the authors' rebuttal, my overall impression of the paper has improved, but I am keeping my original rating.\n﻿\n**Resolved issues:**\n﻿\n* **Interpretability (RQ2)**: The rebuttal provided clearer explanations and visualizations in the chip congestion prediction task, plus complementary results on the MNIST 0/1 benchmark. This better demonstrates how the Information Bottleneck mechanism extracts meaningful subgraphs.\n* **Equation (9) and topology correspondence**: The authors clarified that the cell-based and grid-based hypergraphs have different topologies but share hyperedges representing the same nets, making concatenation meaningful. The example was convincing.\n﻿\n**Unresolved issues:**\n﻿\n* The additional computational complexity introduced by the Information Bottleneck mechanism remains unaddressed.\n* Lower performance on imbalanced datasets (ISPD2025-F) compared to balanced datasets (ISPD2025-B) was not addressed.\n﻿\n**Weighting:**\nThe resolved issues significantly improve the paper’s clarity and technical soundness. However, the unresolved limitations still affect the completeness of the evaluation and practical applicability. These factors balance out to maintain the rating.", "rebuttal": "We sincerely appreciate the reviewer for the positive feedback, especially on the effectiveness of MIHC’s fusion strategy and its strong performance on ISPD2015-B and CircuitNet-N28. We now provide detailed, point-by-point responses to the reviewer’s comments as follows.\n\n>W1: The illustration of MIHC’s interpretability performance(RQ2) is not clear.\n\n**A1:** Thank you for your valuable feedback. We recognize that the interpretability evaluation of MIHC (RQ2) can benefit from a clearer explanation. To address this, we demonstrate MIHC's interpretability performance through two complementary tasks: chip congestion prediction and the MNIST 0/1 classification benchmark.\n\nIn the chip congestion prediction scenario (Figure 2 in the main paper), MIHC is evaluated on its ability to detect meaningful structural patterns that contribute to congestion. As illustrated in the heatmaps, the bottleneck subgraphs extracted by our model effectively capture critical regions where congestion occurs. These regions align closely with the ground truth patterns, confirming that MIHC not only detects individual anomalies but also identifies the local substructures responsible for those anomalies. This is especially important in circuit design, where congestion often arises from interactions among components rather than from isolated nodes. Our information bottleneck mechanism highlights these structurally significant areas, offering insights beyond what node-level detection alone can provide.\n\nTo further support the interpretability of MIHC, we also include an evaluation on the MNIST 0/1 dataset (Table 15 in the Appendix). This dataset is commonly used in interpretability studies because it contains semantically meaningful explainable labels. Since interpretability benchmarks are lacking in the chip congestion domain, we use MNIST as a well-established complement. The results show that MIHC achieves consistently high scores across a range of evaluation metrics, demonstrating robustness and generalizability. The performance indicates that our method provides coherent and faithful explanations across different data types. Compared to baseline models, MIHC exhibits a better balance between precision and recall. For example, GAT+GNNE achieves high recall but low precision, producing noisy explanations, while SIGNET prioritizes precision but overlooks broader node relationships, resulting in poor recall. MIHC, by contrast, maintains both high fidelity and meaningful structural coverage.\n\nOverall, the core interpretability mechanism of MIHC—extracting the most informative subgraph responsible for predictions—remains consistent across both chip and MNIST scenarios. This unified explanation framework ensures that the insights generated are not only accurate but also actionable, making the model's decisions more transparent and trustworthy for real-world applications.\n\n>Q1: In equation (9), $h_e^C$ and $h_e^G$ are concatenated. Does this mean cell-based and grid-based hypergraphs share the same topological structure (Because equation (9) concatenates the embedding of the same edge from two hypergraphs)? If not, how do you construct cell-based and grid-based hypergraphs to achieve this?\n\n**A:** \nThank you for this important clarification question. The cell-based and grid-based hypergraphs do **not** share the same topological structure, as they operate on different node types (cells vs. grid regions). However, they share corresponding hyperedges that represent the same nets, which enables meaningful concatenation in Equation (9).\n\n**Different Topologies, Same Net Correspondence:** While the two hypergraphs have different topological structures due to different node representations, their hyperedges correspond to identical nets in the circuit. This net-based correspondence is the key to our multi-view information fusion approach—we use net hyperedges as bridges to enable information exchange between the two hypergraph representations.\n\n**Construction Example:** As illustrated in Figure 1(c), consider the purple hyperedge 1: in the cell-based hypergraph, it connects blue cells 2, 5, 6, and 7 that are connected by the same net; in the grid-based hypergraph, it connects green grid cells 1, 4, 5, and 6 that are traversed by the same net. Although the connected nodes differ, both hyperedges represent the same physical net, making their embeddings ($h_e^C$ and $h_e^G$) complementary views of the same connectivity information.\n\nThis net-based bridging mechanism allows us to meaningfully concatenate embeddings from structurally different hypergraphs while preserving the semantic correspondence between views."}, {"review_id": "KGBgTwTuYL", "reviewer": "Reviewer_ERG1", "summary": "This work proposes MIHC, a new way of integrating both cell-based and grid-based circuit features to enhance congestion prediction. It also considers interpretability using an information bottleneck mechanism. The authors provide comprehensive experiments on a wide range of test cases. The tests on both ISPD2015 and CircuitNet are convincing.", "questions": "- Is there any chance that your method could provide a method for chip congestion optimization? Like congestion-driven placement?", "limitations": "Yes", "rating": 5, "confidence": 4, "soundness": null, "presentation": null, "contribution": null, "strengths": "", "weaknesses": "", "quality": 4, "clarity": 4, "significance": 3, "originality": 4, "strengths_and_weaknesses": "Strengths:\n- This paper gives a comprehensive and clear comparing analysis of the existing literatures. Chip congestion prediction is a vital problem in EDA community and worth investigating.\n- The interpretable subgraph module for feature fusion is intuitive. The idea of adopting nets to connect not only graph nodes, but also grid cells is an interesting and reasonable design.\n- The experimental results provide a large amount of baselines and superior performance.\n- I like the part C.8 since it provides detailed runtime and memory use and all those statistics. That helps readers understand the computation resource immediately and can quickly assess whether this technique is applicable to their own designs and own device.\n\nWeaknesses:\n- Could you please detail the runtime comparison with other baseline methods?", "was_revised": true, "final_justification": "I believe this work does push the boundary of chip congestion prediction and present convincing results. The authors' rebuttal addresses my concern of runtime. The authors have not presented a detailed and applicable way of integrating the method into a congestion-driven optimization flow. But it does not eliminate the value of the work itself. \n\nAs a conclusion, I vote for acceptance of this work.", "rebuttal": "We sincerely thank the reviewer for taking the time to review our paper and for recognizing our contributions, including the clear comparative analysis of related work, the significance of chip congestion prediction, the intuitive design of the interpretable subgraph module, the comprehensive and strong experimental results, and the practical runtime and memory analysis. In the following, we provide thoughtful and thorough responses to all of the reviewer’s questions.\n\n>W1: Could you please detail the runtime comparison with other baseline methods?\n\n**A:** \nThank you for the helpful question regarding runtime comparison. To provide a clear and fair evaluation, we selected the best-performing baseline methods from cell-based (DE-HNN) and grid-based (Lay-Net) approaches for runtime comparison on the same NVIDIA A100 80GB GPU setup:\n\n| Method | Small Circuits (~30K cells/nets) | Very Large Circuits (1.3M cells/nets) |\n|--------|----------------------------------|---------------------------------------|\n| MIHC (Ours) | 0.3s | 1.6s |\n| DE-HNN | 0.3s | 1.5s |\n| Lay-Net | 0.9s | 3.8s |\n\nFrom a comprehensive performance-runtime perspective, our MIHC achieves the best trade-off: it maintains competitive inference speed comparable to DE-HNN while delivering significantly superior prediction accuracy (16.67% NMAE reduction on ISPD2015-F) and providing interpretability capabilities that neither baseline offers. Compared to Lay-Net, our method achieves both better runtime efficiency and higher accuracy, making it more suitable for practical industrial applications.\n\n\n>Q1: Is there any chance that your method could provide a method for chip congestion optimization? Like congestion-driven placement?\n\n**A:**\nThank you for the insightful question. While our current work focuses on congestion prediction, we believe that the architecture of MIHC is well suited to support congestion-aware design optimization tasks. In particular, MIHC’s ability to identify congestion-critical regions and jointly reason over netlist and layout information makes it a promising candidate for both chip-level optimization and placement refinement. \n\n**Chip Congestion Optimization:** Our Information Bottleneck mechanism identifies critical congestion-correlated regions (as shown in Figure 2), revealing not just where congestion occurs but which local structures cause these anomalies. The bottleneck subgraphs identified by our method could guide chip optimization by highlighting problematic regions that need cell redistribution or routing resource allocation. The interpretable nature of our predictions provides actionable guidance for designers to make targeted optimizations rather than generic congestion mitigation, enabling more efficient use of routing resources and improved overall chip performance.\n\n**Congestion-Driven Placement:** For placement-specific applications, our method could be integrated into placement algorithms to evaluate congestion impact during cell positioning. By simultaneously processing both netlist topology and layout geometry, our method can provide insights into how placement decisions affect congestion from both connectivity and spatial perspectives. This multi-view analysis capability allows placement tools to consider both topological connectivity constraints and geometric layout effects simultaneously, leading to more informed placement decisions that proactively avoid congestion hotspots rather than reactively addressing them post-placement."}]

Author rebuttal:

Meta-review: This paper introduces a multi-view hypergraph neural network that predicts chip congestion by simultaneously processing netlist (topological) and layout (geometric) data. To improve accuracy and trustworthiness, it uses a novel subgraph Information Bottleneck mechanism to identify and focus on critical, congestion-related circuit regions.

The paper's strengths lie in its novel and balanced approach to fusing multi-view circuit data within a unified hypergraph framework and its pioneering use of an Information Bottleneck for interpretable, subgraph-level predictions in this domain. The weaknesses include the added computational complexity from the IB mechanism and concerns about generalization, particularly on unseen circuit designs. In the rebuttal period, the authors provided runtime analysis showing the cost is manageable for industrial applications, which mitigates this concern as a practical barrier. Overall, this paper makes a good contribution, so I recommend acceptance.
Decision: Accept (poster)