FALCON: An ML Framework for Fully Automated Layout-Constrained Analog Circuit Design
Authors: Asal Mehradfar
Xuzhe Zhao
Yilun Huang
Emir Ceyani
Yankai Yang
Shihao han
Hamidreza Aghasi
Salman Avestimehr
Venue: NeurIPS 2025 poster ()
Keywords: Graph Neural Networks
Gradient-Based Reasoning
Analog and mm-Wave Circuit Design
Layout-Aware Optimization
Design Automation
Physics-Informed Machine Learning
Primary area: machine_learning_for_sciences
TL;DR: We present FALCON, a fully automated machine learning framework for analog circuit design that selects topologies based on performance specifications and infers parameters to satisfy those specifications while minimizing layout cost.

Abstract: Designing analog circuits from performance specifications is a complex, multi-stage process encompassing topology selection, parameter inference, and layout feasibility. We introduce FALCON, a unified machine learning framework that enables fully automated, specification-driven analog circuit synthesis through topology selection and layout-constrained optimization. Given a target performance, FALCON first selects an appropriate circuit topology using a performance-driven classifier guided by human design heuristics. Next, it employs a custom, edge-centric graph neural network trained to map circuit topology and parameters to performance, enabling gradient-based parameter inference through the learned forward model. This inference is guided by a differentiable layout cost, derived from analytical equations capturing parasitic and frequency-dependent effects, and constrained by design rules. We train and evaluate FALCON on a large-scale custom dataset of 1M analog mm-wave circuits, generated and simulated using Cadence Spectre across 20 expert-designed topologies. Through this evaluation, FALCON demonstrates >99\% accuracy in topology inference, <10\% relative error in performance prediction, and efficient layout-aware design that completes in under 1 second per instance. Together, these results position FALCON as a practical and extensible foundation model for end-to-end analog circuit design automation.

FALCON: An ML Framework for Fully Automated Layout-Constrained Analog Circuit Design
Asal Mehradfar'
Xuzhe Zhao² Yilun Huang²
Emir Ceyani
Yankai Yang² Shihao Han
Hamidreza Aghasi
Salman Avestimehr!
University of Southern California University of California, Irvine
mehradfa@usc...
Abstract
Designing analog circuits from performance specifications is complex, multi-stage process encompassing topology selection, parameter inference, and layout feasibil- ity. We introduce FALCON, a unified machine learning framework that enables fully automated, specification-dee lection and layout-constrained optimization. Given target performance, FALCON first selects an appropriate circuit topology using a performance-driven classifier guided by human design heuristics. Next, employs custom, edge-centric graph neural network trained to map circuit topology and parameters to performance, enabling gradient-
analog circuit synthesis through topology se-
parameter inference through the learned forward model. This inference is guided by differentiable layout cost, derived from analytical effects, and constrained by
equations capturing parasitic and Trequency-dependden design rules. We train and evaluate FALCON on a large-scale custom dataset of 1M analog mm- wave circuits, generated and simulated using Cadence Spectre across 20 expert-designed topologies. Through this evaluation, FALCON demonstrates >99% accuracy in topology inference, <10% relative error in performance prediction, and efficient layout-aware design that completes in under 1 second per instance. Together, these results position FALCON as a practical and extensible foundation model for end-to-end analog circuit design automation. Our code and dataset are com cctp///aaaaaeecaaaaaaAAAAA...
publicly available at
1 Introduction
Analog radio frequency (RF) and millimeter-wave (mm-wave) circuits are essential to modern electronics, powering critical applications in signal processing D. wireless communication (2). sensing (3), radar [4) and wireless power transfer systems (5). Despite their importance, the design of analog circuits remains largely manual, iterative, and dependent on expert heuristics (6-8] This inefficiency stems from several challenges: a vast and continuous design space that is difficult to explore systematically; tightly coupled performance metrics (e.g. gain, noise, bandwidth, and power) that create complex trade-offs; and physical and syyout-dependen interactions that complicate design decisions. As demand grows for customized, high performance analog blocks, this slow, expert-driven design cycle has become critical bottleneck. While machine learning (ML) has revolutionized digital design automation, analog and RF circuits still lack scalable frameworks for automating full pipeline from specification to layout.
While recent ML approaches have made progress in analog circuit design, they typically target isolated sub-tasks such as topology generation or component sizing [0] at the schematic level, without addressing the full synthesis pipeline. Many efforts assume fixed topologies (T14 limiting adaptability to new specifications or circuit families. Optimization strategies often rely on black-box methods that do not scale well large, continuous design spaces [15]. Some methods predict
39th Conference on Neural Information Processing Systems (NcurIPS 2025).

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Neciat
Gain: 27
Power: 0.08W
Topelogy Selection
Layent-Aware
Gradient Reasoning
Parumeters
Bandwidth: 45MHz
Simulation Validation
Input Spee
Figure I: Our Al-based circuit design pipeline. Given a target performance specification, FALCON first selects suitable topology, then generates design parameters through layout-aware gradient-based reasoning with GNN model. Then, the synthesized circuit is validated using Cadence simulations.
performance metrics directly from netlists [6]. but do not support inverse design, i.c., generating circuit parameters from target specifications. Furthermore, layout awareness typically handled as a separate post-processing step [7]. missing the opportunity to guide optimization with layout constraints. Finally, many available benchmarks are built symbolic synthetic simulations (18) lacking the fidelity and realism of the process of commercial grade design flows. As a result, current ML pipelines do not allow fully generalizable, layout-aware, and end-to-end analog circuit design.
propose FALCON (Fully Automated Syyout-Constrained analOg circuit desigN), a scalable and modular machine learning framework for end-to-end analog and RF circuit design. Built dataset over one million Cadence-simune simulated circuits. FALCON comprises three core components (Figure I) (I) lightweight multilayer perceptron (MLP) selects the most appropriate topology given a target performance specification; (2) a generalizable graph neural network (GNN) maps circuit topology and element-level parameters performance metrics, operating representation derived from Cadence netlists; and (3) gradient- based optimization over the forward GNN model recovers design parameters that meet the target specification, guided by differentiable layout-aware Ioss that encodes parasitic effects and physical constraints. Notably, the GNN model in FALCON generalizes effectively unseen topologies, enabling inverse design across diverse circuit families, even in low-data regimes, with optional fine-tuning for improved accuracy. By integrating layout modeling directly into the optimization process, FALCON unifies schematic and physical considerations within single differentiable learning framework.
native graph
Our main contributions follows:
We construct large-scale analog/RF circuit dataset comprising over one million Cadence- simulated datapoints across 20 expert-designed topologies and five circuit types.
We introduce a native netlist-to-graph representation that preserves both structural and parametric fidelity, enabling accurate learning over physical circuit topologies.
We design generalizable GNN capable of accurate performance prediction and parameter inference across both seen and unseen topologies. with optional fine-tuning.
We develop modular ML framework for end-to-end inverse design, incorporating performance-driver topology selection and layout-aware gradient-based optimization, with a differentiable loss that enforces area constraints, design-rule compliance, and frequency- dependent modeling passive components.
We show that FALCON enables fast, reliable inverse design under layout and physical constraints, generating high-quality circuits in under one second per instance on CPU.
Related Work
While recent ML-based approaches have advanced analog and RF circuit design, they typically target isolated stages of the design flow-such as topology generation, parameter sizing, or schematic-level performance prediction- without supporting unified, end-to-end synthesis. FALCON bridges this gap by jointly addressing aforementioned stages within a single framework.
Topology generation methods aim to select or synthesize candidate circuit structures 9 19
often using discrete optimization or generative models to explore the circuit graph space. However, these approaches typically target low-frequency or simplified designs [ and may produce physically invalid non-manufacturable topologies. contrast, FAL-CON leverages a curated set of netlists, ensuring manufacturable validity and climinating the need to rediscover fundamental circuit structures.

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Parameter sizing and performance prediction have been explored through various learning
paradigms. Reinforcement learning [TO 21] and Bayesian optimization [5] [2] optimize parameters
via trial-and-error, often requiring large simulation budgets. Supervised learning methods [33 24
regress parameter values from performance targets under fixed topologies. Graph- models [6 incorporate topology-awan representations to predict performance metries from netlists. However, these approaches focus on forward prediction or black-box sizing and do not support inverse design across varied topologies. In contrast, FALCON unifies forward modeling and parameter inference in a single differentiable architecture that generalizes to unseen netlists.
Layout-aware sizing and parasitic modeling have been explored to mitigate schematic-to-lay mismatch. Parasitic-aware methods [25] integrate pre-trained parasitic estimators into Bayesian optimization loops for fixed schematics. While effective for estimation, these approaches rely on time-consuming black-box search and lack inverse design capabilities. Other methods, such as ALIGN (66] and LayoutCopilot [27], generate layouts from fully sized netlists using MI.-based constraint extraction or scripted interactions, but assume fixed parameters and do not support co- optimization or differentiable inverse design. In contrast, FALCON embeds layout objectives directly into the learning loss, enabling joint optimization sizing and layout without relying on external parasitic models. For mm-wave circuits, our layout-aware loss captures frequency-sensttig constraints via simplified models that implicitly reflect DRC rules, EM coupling, and performance- critical factors such as quality factor and self-resonance frequency.
Datasets for analog design are often limited symbolic SPICE simulations or small-scale testbeds that do not reflect real-world design flows. AyalogGym [18] and AutoCkt [13 rely on synthetic circuits and symbolic simulators, lacking the process fidelity, noise characteristics, and layout- dependent behavior of foundry-calibrated flows. In contrast, FALCON is trained on large-scale dataset constructed from over one million Cadence-simulated circuits across 20 topologies and five circuit categories, offering a substantially more realistic foundation for ML-driven analog design.
To the best of our knowledge, FALCON is the first framework unify topology selection, parameter inference, and layout-aware optimization in single end-to-end pipeline, validated at scale using cndustrial-grade Cadence simulations for mm-wan mave analog circuits. A qualitative comparison with representative prior work is provided in Appendix
3
A Large-Scale Dataset and Inverse Design Problem Formulation
3.1 Dataset Overview
We construct large-scale dataset analog and RF circuits simulated using industry- grade Cadence tools (28) with 45nm CMOS process design kit (PDK). The dataset spans five widely used mm- wave circuit types for wireless applications (2 330: low-noise amplifiers (LNAs) (31434), mixers [35)38] power amplifiers (PAs) [39 voltage amplifiers (VAs) (44 and voltage-controlled oscillators
(VCOs) [4] Each circuit type is instantiated in four distinct topologies, resulting in a total of 20
expert-designed architectures.
For each topology, expert-designed schematics were implemented in Cadence Virtuoso, and key design parameters were manually identified based on their functional relevance. Parameter ranges were specified by domain experts and systematically swept using Cadence ADE XL, enabling parallelized Spectre simulations across the design space. For each configuration, performance as gain, bandwidth, and oscillation frequency- were extracted and recorded. Each datapoint therefore includes the full parameter vector, the corresponding Cadence netlist, and the simulated performance metrics. The resulting dataset comprises over one million datapoints, capturing wide range of circuit behaviors and design trade-offs across diverse topologies. This large-scale, high-fidelity dataset forms the foundation for training and evaluating our inverse design pipeline. Detailed metric definitions and per-topology parameter ranges appear in Appendix B
3.2 Graph-Based Circuit Representation
To enable flexible and topology-agnosti learning, we represent each analog circuit as a graph extracted from its corresponding Cadence netlist. Nodes correspond to voltage nets (i.e., electrical connection points), and edges represent circuit elements such as transistors, resistors, capacitors, or sources. Multi-terminal devices-such transistors and baluns- are decomposed into multiple
3

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Components
Componente
expachor
Indlucor
DVD
16.75
VD0
(a) IFVCO
(b) ClassBPA
Figure 2: Graph representations of two analog circuit topologies from our dataset: (a) IFVCO and (b) ClassBPA. Nodes represent electrical nets, and colored edges denote circuit components such as transistors, capacitors, inductors, and sources. Each component type is visually distinguished by color and labeled with name and terminal role (e.g., N2_GS, VO). For transistors, labels such as GS, DS, and DG denote source-to-gan drain-to-source, and drain-to-gate connections, respectively. These graphs serve as input to our GNN-based performance modeling and inverse design pipeline.
edges, and multiple components may connect the same node pair, resulting in heterogeneous, multi-edged graphs that preserve structural and functional diversity.
Recent works such as DICE 54 have explored transistor-level circuit-to-gre touutt conversions for self-supervised learning, highlighting the challenges faithfully capturing device structure and connectivity. In contrast, our approach maintains a native representation aligned with foundry- compatible netlists. Rather than flattening or reinterpreting device abstractions, we preserve symbolic parameters, multi-edge connections, and device-specific edge decomposition directly from the schematic source, enabling scalable learning across diverse analog circuit families.
To support learning over such structured graphs, each edge is annotated with rich set of attributes: (i) a categorical device type, specifying the component and connected terminal pair (e.g., NMOS drain-gate, resistor); (ii) numeric attributes, such as channel length port resistance, fixed by the schematic; (iii) parametric attributes, defined symbolically in the netlist (e.g.. W1, R3) and resolved numerically during preprocessing; (iv) one-hot categorical features, such as source type (DC, AC, or none); and (v) computational attributes, such as diffusion areas (Ad, As) derived from sizing. This rule-based graph construction generalizes across circuit families without task-specific customization. Graphs in the FALCON dataset range from 4-40 nodes and 7-70 edges, reflecting the variability of practical analog designs. Figure 2 shows two representative graph examples from dataset-IFVl and ClassBPA.
3.3 Inverse Design Problem Definition
In analog and RF circuit design, the traditional modeling process involves selecting topology T' and parameter vector x, then evaluating circuit behavior via simulation to obtain performance metrics = f(', æ). This forward workflow depends heavily on designer intuition, manual tuning, and exhaustive parameter sweeps. Engineers typically simulate many candidate (T, x) pairs and select the that best satisfies the target specification slow, costly, and unguided process.
In contrast, our goal is to perform inverse design: given a target performance specification Ylargets we aim to directly infer a topology and parameter configuration (T, .r) such that J(T, ss Murgett without enumerating the full design space. This inverse problem is ill-posed and the search space constrained by both device-level rules and layout-aware objectives.

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Formally, the task is to find the optimal topology T E T and the optimal parameters x" E R" such that f(T*, x²) ~ Murret where f R R the true performance function implemented by expensive Cadence simulations. In practice, is nonlinear and non-invertible, making direct inversion intractable. FALCON addresses this challenge through a modular, three-stage pipeline:
Stage 1:
Topology Selection. We frame topology selection as classification problem over curated of K candidate topologies {Ti,.... Tk]: Given target specification Wharget, lightweight MLP selects the topology 7 E TT most likely to satisfy it, reducing the need for exhaustive search.
Stage 2: Performance Prediction. Given a topology T and parameter vector I, train GNN fo to predict the corresponding performance ÿ = (T..). This model emulates the forward behavior of the simulator f. learning a continuous approximation of circuit performance across both seen and unseen topologies. By capturing the topology-comee condiiiooo mapping from parameters to performance, fo serves differentiable surrogate that enables gradient-base based inference in the next stage.
Stage 3: Layout-Aware Gradient Reasoning. Given Ytarget and a selected topology T", we infer parameter vector x² by minimizing loss over the learned forward model fo. Specifically, we solve:
arg min Cper(f(TT 22), Murrgtt) - X Layouu (2),
(1)
where Spert measures prediction emrrr, and Llayour encodes differentiable layout-related constraints such as estimated area and soft design-rule penalties. Optimization is performed via gradient descent, allowing layout constraints to guide the search through physically realistic parameter space.
4 Stage 1: Performance-Drivee Topology Selection
Task Setup. We formulate topology selection supervised classification task over fixed library of 20 expert-designed circuit topologies T {Ti T2........ ....... ] from scratch-whin often leads to invalid or impractical circuits- select from vetted set of designer-verified topologies. This ensures that candidates are functionally correct, fayout-feasible, and manufacturable. While expanding the topology set requires retraining, our lightweight MLP classifier enables rapid updates, making the approach scalable. This formulation also aligns with practical design workflows, where quickly identifying viable initial topology is critical.
Rather than generating netlists
Each datapoint is represented by 16-dimensional performance vector of key analog/RF metric We normalize features using z-scores computed from the training set. Missing metrics (e.g., oscillation frequency for amplifiers) are imputed with zeros, yielding centecen fixed-length vectors that retain task-relevant variation. Dataset splits are stratified to preserve class balance across training, validation, and test sets. We assume each target vector is realizable by at least one topology in T, though the library can be extended with new designs.
Table I: Classification
Netlist
performance on topology selection.
Netlist
Target
Netlist
Metric
Score
Performance
Accuracy
99.57
Netlist
Balanced Accuracy
99.33
Macro Precision
99.27
Figure In Stage 1, an MLP classifier selects the most
Macro Recall
99.33
suitable circuit topology from a library of human-designed netlists, conditioned on the target performance specification.
Macro Fl
99.30
Micro F1
99.57
Model Architecture and Training. We train 5-layer MLP with hidden size 256 and ReLU activations for this problem. The model takes the normalized performance vector Yuarget E 16 as input and outputs probability distribution over 20 candidate topologies. The predicted topology is selected as T arg maxr, ET MLP(yyurge) k. We train the model using cross-entropy loss and the Adam optimizer (55), with batch size of 256. An overview of this process is shown in Figure
DC power consumption (DCP), voltage gain (VGain), power gain (PGain), conversion gain (CGain), Sn1. S21, noise figure (NF), bandwidth (BW), oscillation frequency (OscF), tuning range (TR). output power (OutP), PsAr, drain efficiency (DE), power-added efficiency (PAE), phase noise (PN), voltage swing (VSwg).
5

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150
1:14
18
5.0
5.0
230
2.3
5.00
5.00
5.8
100
800
0.0
0.9
5.0
8/8
5S1E
100
8000
8.00
6.00
557
4345
4.50
6.0
809
-2
100
A00
3.0
5.0
230
230
2.39
5.00
6.00
6200
18/00e
D-SNE-1
Pedicted
(a) t-SNE of performance vectors
(b) Confusion matrix (errors only)
100
42.4%
Accuracy (Ng
20
CSM
oRAther
DBMMaa
guusher
Dotet
DMA
coco
cavco
Nico
(c) Per-class accuracy across circuit topologies
Figure 4: Topology selection results. (a) Performance vectors form well-separated clusters in t-SNE space, showing that circuit functionality is semantically predictive of topology. (b) Misclassification primarily occur among voltage amplifier variants with overlapping gain-bandwidth tradeoffs. (c) Per-class test accuracy exceeds 93% across all 20 circuit topologies
Evaluation. We begin by assessing the quality of the input representation used for topology classifi- cation. Normalized performance vectors encode rich semantic information about circuit behavior. To validate this, we project them into a two-dimensional t-SNE space (56) (Figure 4a)). The re- sulting clusters align closely with topology labels, indicating that performance specifications reflect underlying schematic structure and are effective inputs for supervised classification.
We assess classification performance using accuracy, balanced accuracy, macro precision, macro recall, macro F1, and micro Fl scores on the test set. As summarized Table [ the classifier achieves overall accuracy of 99.57%, with macro Fl of 99.30% and balanced accuracy of 99.33%, demon- strating strong generalization across all 20 circuit topologies. Micro F1 (identical to accuracy in the multiclass setting) reaches 99.57% while macro metrics-averagel averaged equally across classes classes-highlight robustness to class imbalance. Seed-averaged results with 95% confidence intervals are provided in Appendix
C These trends are reinforced by the per-class accuracy plot in Figure cc., where most topologies reach 100% accuracy.
The confusion matrix in Figure 4b) visualizes only the misclassified instances, most classes achieve perfect accuracy. The few observed errors are primarily concentrated among the two voltage amplifier topologies- common-gar caatmmnnggtteeoo (CGVA) and common-source (CSVA). These cireuits operate near the gain-band bandwidth limit the transistor, and when the main amplifier transistor size is held constant, performance metrics such power consumption, gain, and bandwidth converge across these architectures. This occasional overlap in the performance space introduces ambiguity in classification for small subset of instances. For other circuit categories, significant confusion expected or observed. These results validate our hypothesis that performance vectors contain sufficient semantic structure for accurate, scalable topology classification.
"The 20 circuit lopologies-listed in the same order the numerical labels in Figure 4 aa)-are: CGLNA (Common Gate), CLNA (Cascode), CSLNA (Common Source), DLNA (Differential), DBAMixer (Double- Balanced Active), DBPMixer
Passive), SBAMixer (Single-Balann) Balanced Active), SBPMixer Balanced Passive), ClassBPA (Class-B), ClassEPA (Class-Bi -),, DohPA (Doherty), DPA (Differential), "Single-Balanced
CGVA (Common Gate), CSVA (Common Source), CVA (Cascode), SFVA (Source Follower), IFVCO (Inductive- Feedback), CCVCO (Cross-Corl Coupled), ColVCO (Colpitts). RVCO (Ring).

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Stage 2: Generalizable Forward Modeling for Performance Prediction
Task Setup. The goal of Stage 2 is learn a differentiable approximation of the circuit simulator that maps topology 7' and parameter vector æ to a performance prediction y =fo(', æ), where ý E I Unlike black-box simulators, this learned forward model enables efficient performance estimation and supports gradient-based parameter inference in Stage 3. The model is trained to generalize across circuit families and can be reused on unseen topologies with minimal fine-tuning.
Each datapoint consists of a graph-structured Cadence netlist annotated with resolved parameter values and the corresponding performance metrics. We frame the learning task supervised regression problem. Since not all performance metrics apply to every topology (e.g., oscillation frequency is undefined for amplifiers), train the model using masked mean squared error loss:
masked
m (0: - -y,)²
(2)
Σ, m3
where m, 1 if the i-th metric is defined for the current sample, and 0 otherwise.
Model Architecture and Training. Each cir- undirected multi- edge graph with voltage nets as nodes and cir- cuit components edges. All circuit parame- ters-both fixed and sweepable-are assigned to edges, along with categorical device types and one-hot encoded indicators. For each edge form a
cuit is represented
Performance
Circuit
Parameters
these attributes are concatenated unified feature vector Te. The feature set is con- sistent within each component type but varies across types (e.g., NMOS vs. inductor), reflect- ing the structure defined Section 3.2
Figure 5: In Stage 2, a custom edge-centric GNN maps an undirected multi-cdge graph constructed from the circuit netlist to performance vector.
To account for component heterogeneity, we apply type-specific MLP encoders dlle the raw features of each edge e, producing edge embeddings 2e (1.) (zz), where t, denotes the component type of edge e. Node features are initialized as scalar dummy values and mapped hidden dimension via shared linear layer. We then apply 4-layer edge-centric wessage-passingg GNN with residual connections. At each layer f, every node receives messages from incident edges En, where &, denotes the set of edges connected to u. Messages are computed using shared function ØMsG. which takes the hidden state of the neighboring node sre(e) and the associated edge embedding. Node states are then updated via learnable function dUPD, followed by residual connection and nonlinearity:
ØMSG (M (e))))))=
(E+1) = -ReLU @UPD (m! + A(())
m
BEE.
where ze E Rd is the learned embedding of edge e, and h sete)) E Idd is the hidden state of the node at the other end of edge from at layer L. The update function dUPD is a shared linear transformation applicd to nodes. After L = GNN layers, node embeddings are aggregated using global mean pooling to obtain fixed-size graph representation:
Σ h aEV
Zgrapp
where V is the set of all nodes in the graph. The resulting vector is then passed through fully connected MLP (output_mi) to predict the 16-dimensional performance vector ÿ E R21,, An overview of this GNN-based forward prediction pipeline is shown Figure
To stabilize training, physical parameters are rescaled by their expected units (e.g. resistance by 10²), and performance targets are normalized to z-scores using training statisties. We train the model using the Adam optimizer (learning rate 10-3 batch size 256) and ReduceLROnPPaatee Xavier uniform initialization used for all layers, and early stopping is based on validation loss. We adopt the same splits in Section for consistency in evaluation.
scheduler.

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Evaluation. We evaluate the accuracy of the GNN forward model fo on test set drawn from 19 of the 20 topologies. One topology R------O--- iss entirely excluded from training. validation, and test splits to assess generalization to unseen architectures. Prediction quality is measured using standard regression metrics: coefficient of determination (R3), root mean squared error (RMSE), and mean absolute error (MAE), computed independently for each of the 16 performance metrics. We also report the mean relative error per metric, computed as the average across test samples where each metric is defined. As summarized in Table 2 the model achieves high accuracy across all dimensions, with an average R² of 0.972.
Table 2: Prediction accuracy of the forward GNN on all 16 eircuit performance metrics.
Metric
DCP
VGain
PGain
CGain
NF
BW
OseF
TR
OutP
PAXt
DE
PAR
PN
VSwg
Unit
mW
GHz
dBm
dBm
dBo/Hz
mV
R²
1.0
1.0
0.99
1.0
0.3
1.0
0.99
0.88
0.97
0.83
0.97
1.0
1.0
1.0
0.89
1.0
RMSE
0.27
0.101
0,536
0.833
1.515
0.21
0,534
0.972
0.723
0.293
0.91
0.095
0.226
0.143
2.536
0.071
MAE
0.198
0.072
0.208
0.188
0.554
0.12
0.376
0.184
0.097
0.238
0.066
0.163
0.105
1.159
0.046
Rel.
11.2%
2.6%
19.0%
4.5%
6.5%
0.6%
6.5%
4.6%
4.4%
4.6%
11.0%
1.3%
1.4%
To evaluate end-to-end prediction accuracy at the sample level, we compute the mean relative error per instance, defined as the average relative error across all valid (non-maske monn-masked) performance metrics for each test sample. shsows the distribu- tion this quantity across the test set (trimmed at the 95th percentile to reduce the impact of outliers), The distribution is sharply concentrated, indicating that most predictions closely match their corre- sponding target vectors. Without percentile trim- ming, the overall mean relative error across the full test set is 9.09% %. Seed-averaged results with 95% confidence intervals are provided in Appendix C
Miven: 70%
Median: 1.55%
0.190
Modde: 1.40%
0.129
0.775
0.000
022
0.000
Relative Emro
Figure 6: Distribution relative error (%) across the test set for the GNN forward model. Plot is trimmed at the 95th percentile.
Generalizing to Unseen Topologies via Fine- Fine-Tuning. To assess the generalization ability of our pretrained GNN, we evaluate it on the held-out RVCO topology, which was entirely excluded from the Stage 2 training, validation, and test splits. Notably, the RVCO training partition used here matches that of the Stage experiments (Section enabling consistent cross-stage evaluation.
We fine-tune the GNN by freezing all encoder and message-passing layers and updating only the final output head poutpu__mpl) Fine-tuning is performed on the RVCO training set, which contains approximately 30,000 instances, and completes in under 30 minutes on MacBook CPU.
Even in the zero-shot setting where the model has never seen RVCO topologies- the pretrained GNN achieves a nontrivial mean relative error of 30.4%, highlighting its strong cross-topology gen- eralization. Fine-tuning reduces this error to just 0.9%, demonstrating that the structural and para- metric priors learned during pretraining highly transfcrable. Table reports detailed performance across five key metrics of RVCO, confirming that the pretrained GNN can be rapidly adapted to novel circuit families with minimal supervision.
Table 3: Fine-tuning results on the held-out RVCO topology. Only the output head is up- dated using RVCO samples.
Metric
DCP
OscF
TR
OutP
PN
Unit
w
GHz
GHz
dBm
dBe/Hz
R²
1.0
1.0
1.0
0.97
0.98
RMSH
0.643
0.324
0.026
0.099
0.953
0.508
0.256
0.077
0.619
Rel. Em.
0.75%
0.85%
1.63%
0.69%
0.73%
Stage 3: Layout-Aware Parameter Inference via Gradient Reasoning
Task Setup. Given a target performance vector Vuaget and a selected topology T*, the goal of Stage 3 is to recover parameter vector x: that minimizes a total loss combining performance error and layout-aware penalties, using the learned forward model fo from Stage 2. This formulation enables instance-wise inverse design without requiring circuit-level simulation.
8

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Updated Cireuit
Nettle
Par aarameters
Reasoning
Circnit
Target Performance
Performance
Parameters
Initial Circuit
Total Loss
Leyout Equations
Layout Loss
Figure 7: In Stage 3, gradient reasoning iteratively updates parameters to minimize loss combining performance enror and layout cost, computed via differentiable analytical model.
To initialize optimization, we perturb domain-specific scale factors (e.g., 10-12 for capacitors) to sample a plausible starting point #g- Parameters are iteratively updated via gradient descent, guided by both functional and physical objectives. Topology-spene constants are held fixed, and parameter values are clipped to remain within valid domain bounds throughout the process.
Loss Function. The total loss follows the structure defined in Eqn jointly minimizing performance mismatch and layout cost:
Luial Epert Aurea
Llayout (Cpert);
where Lpent is the masked mean squared error (see Eqn 2 between predicted and target performance vectors, and Llayout is normalized area penalty derived from analytical layout equations. prioritize functionality, layout loss is softly gated by sigmoid function:
((Cerr) - (r<(pert -))
where (-) denotes the sigmoid function, and y, T are fixed scalars controlling the sharpness and center of the gating. This gating attenuates layout penalties when performance encouraging the model to first achieve functionality before optimizing for layout compactness.
exceeds threshold
We set r = 0.05, y 50, and normalize layout area by 1 mm3 to stabilize gradients. The layout weight Auren 0.02 chosen empirically to balance performance accuracy and physical realism without dominating the loss. This gated formulation supports manufacturable parameter recovery and reflects the broader paradigm of minysics-informed learning [77 Further discussion on user-defined objectives is provided in Appendix D
a downstream concern for passive components. Substrate coupling, proximity effects, and DRC- DRC-imposed geometries directly affect key metrics such as reso- nance frequency, quality factor, and impedance matching. To incorporate these effects, we introduce a differentiable layout model that computes total physical area analytically from cireuit parameters. This enables layout constraints to directly guide parameter optimization during inverse design. By minimizing the layout area in distributed mm-wave circuits [58), unwanted signal loss (59) reduced, the self self-resonance frequency of passives can increase 660 and phase and amplitude mismatches across signal paths [61] can be reduced.
Differentiable Layout Modeling. In mm-wave analog design, layout
but a critical determinant of circuit cerioormannc-pariiculliii
The layout model is deterministic and non-learned. It estimates area contributions from passive components-ccpaccioon inductors, and resistors-as as these dominate total area and exhibit layout- sensitive behavior. Active devices (e.g.. MOSFETs) are excluded since their geometries are fixed by the PDK and are negligible (62). For a given parameter vector æ, the total layout loss is computed as: (a) = EegEpain Ag (x), where Epassive is the set of passive elements, and Ax(x) ) is the area of the created layout for the passive component based analytical physics- based equations. The of element is estimated based on its 2D dimensions (c.g., A = L for resistors and capacitors). This area is normalized and used as a differentiable penalty in the optimization objective (see Eqn 3). Further implementation details are provided in Appendix
Gradient Reasoning Procedure. Starting from the initialized parameter vector Pp. we iteratively update parameters via gradient reasoning. each step, the frozen forward model fo predicts the performance [T .r), and the total loss Lioia is evaluated. Gradients are backpropagated with respect to æ, and updates are applied using the Adam optimizer. Optimization proceeds for fixed number of steps, with carly stopping triggered if the loss fails improve over predefined window.

---

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(a) Designed DohPA schematic
(b) Layout of designed DohPA
Figure 8: Stage 3 results for a synthesized DohPA. The schematic (a) reflects optimized parameters to meet the target specification. The layout (b) is DRC-compliant and physically realizable. The final design achieves a mean relative error of 5.4% compared the target performance.
To handle varying circuit difficulty and initialization quality, employ adaptive learning rate strategy. Each instance begins with a moderate learning rate (10 1,0-)), refined during optimization via ReduceLROuPlateen scheduler. If the solution fails meet thresholds performance error layout area, optimization restarts with a more exploratory learning rate. This adjustment balances exploration and fine-tuning, enabling rapid convergence to physically valid solutions, typically within milliseconds to under one second per instance. An overview is shown in Figure
Evaluation. We evaluate Stage 3 on 9,500 test instances (500 per topology) using our gradient-based optimization pipeline. A design is considered converged if it meets both: (i) predicted mean relative error below 10%. and (ii) layout area under lopology-speciff bound- mm² for most circuits and 1.5 mm3 for DLNA, DohPA, and ClassBPA. The 10% error threshold reflects the forward model's 9% average prediction error (Section 5 A design is deemed successful if its final Cadence- simulated performance deviates from the target by less than 20%, confirming real-world viability. Our method achieves success rate of 78.5% and mean relative error of 17.7 % across converged designs, with average inference time under second on a MacBook CPU. Notably, success rate is coupled with the convergence threshold: tighter error bounds yield higher accuracy but require more iterations-critice for large-scale design tasks.
To illustrate the effectiveness of our pipeline, Figure 8 shows a representative result for the DohPA topology: the synthesized schematic is shown on the left, and the corresponding layout is on the right. These results confirm that the recovered parameters are both functionally accurate and physically realizable. Together, they demonstrate that FALCON enables layout-aware inverse design within a single differentiable pipeline- capability not supported by existing analog design frameworks.
7 Conclusion and Future Work
We presented FALCON, a modular framework for end-to-end analog and RF circuit design that unifies topology selection, performance prediction, and layout-aware parameter optimization. Trained on over one million Cadence-simulated mm-wave circuits, FALCON combines lightweight MLP, a generalizable GNN, and differentiable gradient reasoning synthesize circuits from specification to layout- constraind parameters. FALCON achieves >99% topology selection accuracy, <10% prediction error, and efficient inverse design- all within sub-second inference. In addition, the GNN forward model generalizes to unseen topologies with minimal fine-tume fine-tuning, supporting broad practical deployment. Further discussion of training and inference efficiency, as well practical limitations, is provided in Appendix[B FF]
In future work, we aim expand the topology library and support hierarchical macroblocks for scalable design beyond the cell level. We also plan to extend the dataset to cover multiple operating frequencies, enabling validation across diverse bands, and enhance the layout-aware optimization with learned parasitic models, EM-informed constraints, and electromigration considerations for more accurate last-layout estimation. Finally, integrating reinforcement learning or diffusion-bain based models for generative topology synthesis represents a promising step toward general-purpose purpose analog design automation.
10

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Acknowledgments and Disclosure of Funding
We thank Andrea Villasenor and Tanqin He for their assistance with circuit data generation. We also thank Mohammad Shahab Sepehri for his insightful discussions and thoughtful feedback during the development of this work.
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A Qualitative Comparison with Prior Work
To contextualize FALCON within the broader landscape of analog circuit design automation, we provide a qualitative comparison against representative prior works in Table 4 This comparison spans key capabilities including topology selection, parameter inference, performance prediction, layout awareness, and simulator fidelity. We additionally assess reproducibility via dataset and code availability, and introduce a new Mass-FF/mmmmve we/vem-waee support-to highlight methods evaluated on high-free feghfrre circuit blocks such LNAs, mixers, and VCOs. Compared to existing approaches, FALCON is the only framework that unifies all these dimensions while maintaining foundry- grade fidelity and open-source accessibility. Definitions for each comparison axis are provided in Table
Table 4: Qualitative comparison of FALCON with prior works across key capabilities in analog
circuit design automation.
Method
Topology Selection
Parnmeter Inference
Performance Prediction
Awareness
Layont
Foundry Grude
RF/ mmn- Ware
Public Dataset
Public
Code
g
(SPICE)
LaMAGIC P
X
(SPICE)
X
Andlogookrr A0
(SPICE)
OCN-RL
(SPICE/CCkknee)
(incomplete)
Cao et 21
X
X
(ADS/Cadeno)
X
X
15
(Cadence)
ESSAB A3
V
(Cadence)
AlCircuit 23
X
X
V (Cadence)
Krylov
(SPICE)
Deep GEN
10
X
X
V
(SPICE)
et al
X (SPICE Parasitic Model)
ALIGN
(Cadence)
Layoutopplet
V (Cadence)
X
AmmlogGym 11
(SPICE)
AutoCka 13
X
(Cadence)
X
(incomplete)
L2DC [2]
(SPICE)
CAN-RL RL [
(Cadenee)
AnGeL. 7
(SPICE)
(This
(Cadence)
Table 5: Definitions of each comparison axis in Table
Column
Definition
Topology Selection
Does the method automatically seleet predict circuit topology
specification?
Parameter Inference
Does the method infer elemens-level parameters (e.g. transistor sizes, component values) as part design generation?
Prodiction
(e.g. gain, layout considered during optimization training (e.g.,
predict circait performance
noise) topology and parameters?
Awareness
parasities, layout-informed loss)?
Dataset Fidelity
Does dataset refleet realistic circuit behavior SPICE/Cadence simulations. PDK models)?
RF/mmm-Waa Wave
Is the method evaluased en at least one RF mave circuit type that reflects high freeffreueeccy design challenges?
Public Dataset
Is the dataset used in the work publicly released for reproucibility and benchmurking? implementation publicly
documented for reprodacibility?
B Dataset Details and Performance Metric Definitions
During dataset generation, each simulated circuit instance is annotated with a set of performance metrics that capture its functional characteristics. All simulations are performed fixed frequency of 30 GHz, ensuring consistency across circuit types and relevance to mm-wave design. A total of 16 metrics are defined across all circuits spanning gain, efficiency, impedance matching, noise, and requency-domail behavior -trrigh the specific metrics used vary by topology. For example, phase noise is only applicable oscillators. An overview of all performance metrics provided in Table
B.1 Low-Noise Amplifiers (LNAs)
Low-noise amplifiers (LNAs) are critical components in receiver front-ends, responsible for amplify- ing weak antenna signals while introducing minimal additional noise. Their performance directly influences downstream blocks such as mixers and analog-to to-digital converters (ADCs), ultimately de- termining lestem-level fidelity (1 To capture the architectural diversity of practical radio-frequency (RF) designs, we include four widely used LNA topologies in this study- couron-sorre LNA (CSLNA), common-gate LNA (CGLNA), cascode LNA (CLNA), and differential LNA (DLNA) shown in Figure
15

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Table 6: Overview of 16 performance metrics used during dataset generation.
Performance Name
Deseription
Power Consumption (DCP)
Total power drawn from the DC supply indicating energy consumption of the circuit ouigui volage amplitude input volluge amplitude
Volluge Gain (VGiin)
Power Gain (PGain)
Ratio output power input power
Conversion Gain (Cian))
Ratio output power the desired frequency imput power the original frequency
S11
Input rellection voeflicient indicating impedaacee matching at the inpui terminal
S22
Ourput reflaction cocfficient indicating impodance matching the output terminal Ratio input signal-to-acise ratio ouiput signal-to-noiss ratio Frequency span over which
Noise Figure (NF)
Bandwidth
muintains specified performance churacteristics Steady-state frequency which the oscillator generates periodic signal
Oscillation Frequency (OscF)
Tuning Range (TR)
Range of achievable escillation frequencies through variation of control vollages
Output Power (OutP)
Power delivered to the load
PSAT
Maximum output power level beyond which gain compression begins to occar Ratio RF output power DC power consumption.
Drain Efficiency (DE)
Power-Added Efficiency (PAF)
output power and inpot power power consumption Measure of oscillator stability represented the frequency domain specified offset Maximum peak voltage level achiovable the output nods
difference
Phase Noise (PN)
Voltage Swing (VSwg)
The CSLNA valued for its simplicity and favorable gain-noise trade-off, especially when paired with inductive source degeneration (30). The CGLNA, often used in ultra-wideband systems, enables broadband input matching but typically suffers from higher noise figure [32]. The CLNA improves gain-bandwidth product and reverse isolation, making it ideal for high-frequency, high-linearity applications [33]. The DLNA exploits circuit symmetry to enhance linearity and reject common common-mode noise, and is commonly found in high-herreee perhh-rerrraceee RF front-end designs (34). The design parameters and performance metrics associated with these topologies are summarized in Table
Var
=G
W.
107
W
We
%
(a) CSLNA
(b) CGLNA
(c) CLNA
(d) DLNA
Figure 9: Schematic diagrams of the four LNA topologies.
Table 7: LNA topologies with parameter sweep ranges, sample sizes, and performance metrics.
Dataset Type
Topology (Code)
of Samples
Parameter
Sweep Range
Performance Metrics (Unit)
[100-600]
C:
(50-300) IF
[250-750]
CGLNA (0)
52k
L4
[80 580) pll
[0.5-5.5]
Ws [12-23]um
C2
[50-250] IF
La
[140-300] pH
CLNA (I)
62k
T
L
[50-250]
[0.4-2]
DCP (W)
PGain (dB)
Wai
[3-5] pm
LNA
Wxr
[7-9] jm
S₁ı (dB)
C
[100-300]
(dB)
14-6|aHt
BW (11))
CSLNA (2)
I,
[100- 200 pi
Wis
[2.5-4]um
Vp
[0.5 0.9.
Ci
1100-1901 nF
C:
T
[100-250] pH
DLNA (3)
92k
L
[600-900] pH
L.
150-80] pi
WNI
9.49.4]
Wxz
[5-14]pm
16

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B.2 Mixers
Mixers are fundamental nonlinear components RF systems, responsible for frequency translation by combining two input signals to produce outputs at the sum and difference of their frequencies. This functionality essential for transferring signals across frequency domains and widely used in both transmission and reception paths [35]. To capture diverse mixer architectures, we implement four representative topologies in this work work-double balancd active mixer (DBAMixer), double-balanced passive mixer (DBPMixer), single-balanced active mixer (SBAMixer), and single-balanced passive mixer (SBPMixer)-as shown Figure 10
The DBAMixer integrates amplification and differential switching to achieve conversion gain and high port-to-port isolation. Despite its elevated power consumption and design complexity, is well suited for systems requiring robust performance over varying conditions [36]. The DBPMixer features a fully differential structure that suppresses signal leakage and improves isolation, at the cost of signal loss and strong local oscillator drive requirement 37 The SBAMixer includes amplification stage preceding the switching core to enhance signal strength and reduce noise, offering balanced performance trade-off with increased power consumption and limited spurious rejection (30]. The SBPMixer employs a minimalist switching structure to perform frequency translation without active gain, enabling low power operation in applications with relaxed performance demands [38] The parameters and performance metrics for these mixer topologies are listed in Table S
Vi-- g
/r
Via
ViG-
Vie
Ve
W
/1
Wn
-o, Vo
Mo.
Vrn
Vos
Via
WN
R
Vas
Vir.
Ver
W
Me.
WN
Vis
Wn
Win
Jan
Vis-
VLo.
(a) DBAMixer
(b) DBPMixer
(c) SBAMixer
(d) SBPMixer
Figure 10: Schematic diagrams of the four Mixer topologies.
Table 8: Mixer topologies with parameter sweep ranges, sample sizes, and performance metrics.
Dataset Type
Topology (Code)
Samples
Parameter
Sweep Range
Performance Metrics (Unit)
C
[1-10]
R
[1-10]
DBAMixer (4)
42k
Wxi
[10-30] pm
WN2
[5 pm
C
[100-500] IF
DCP (W)
DBPMixer (5)
42k
R
[100-600] Q
Mixer
Wi
p10-30]
CGain
NF (dB)
C
[I-15]pF
R
10.7-211kk2
VSwg
SBAMixer (6)
Wst
[10-30] pm
Wxz
[10 20 pm
Tuil
[3-10] mA
C
[I 1.)
SBPMixer
[1-301k12
Ws
[5-29.5]um
B.3 Power Amplifiers (PAs)
Power amplifiers (PAs) are the most nower-intensive components in audio-freyuency (RF) systems and serve as the final interface between transceiver electronics and the antenna. Given their widespread use and the stringent demands of modern communication standards, PA design requires careful trade-offs across key performance metries 39]. Based on the transistor operating mode, PAs are typically grouped into several canonical classes 40 In this work, we implement four representative topologies-Ciin -lass-B (ClassBPA), Class-E PA (ClassEPA), Doherty PA (DohPA), and differential
PA (DPA)-ou) as shown in Figure I1
17

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The ClassBPA employs complementary transistors to deliver high gain with moderate efficiency, making it suitable for linear amplification scenarios 4T. The ClassEPA uses single transistor configured switch, paired with matching network. By minimizing the overlap between drain voltage and current, this topology enables high-efficiency operation and improved robustness to component variation [30]. The DohPA combines main and peaking amplifiers using symmetric two-stack transistors, maintaining consistent gain and efficiency under varying power levels [42]. The DPA features two-stage cascode structure designed to maximize gain and linearity, offering favorable trade-off between output power and power consumption 43 For this topology, we replace the transformer with T-equivalent network to simplify modeling and training of the graph neural network. Parameter sweeps and performance metrics for these PAs are listed in Table
Vis
Vic
Vio
Vi:
800
100
1000
000
Ven
V. 1.
000
Ww
000
Wr
L.
Vn
Vn
(a) ClassBPA
(b) ClassEPA
(c) DohPA
Ver
Vee
000
000
Vo.
Via
Ver
M1
000
7070
010
W
010
(d) DPA
Figure 11: Schematic diagrams of the four PA topologies.
Table 9: PA topologies with parameter sweep ranges, sample sizes, and performance metries.
Dataset Type
Topology (Code)
Samples
Parameter
Sweep Range
Performance Metries (Unit)
C
[S5-205] IF
[I-1.4]
La
[1-8.5]
ClassBPA
35k
R
[1.5-4] kS2
Wxx
[10-20] pm
We
[3-8] pm
C
[100-200] IF
C:
[500-700]
ClassEPA
46k
1100-300] pH
1g
[100 150) pll
DCP (W)
Wy
[15-30] pm
PGain (dB)
p2
Su (dB)
C2
1200-300] IF
Syz (dB)
Cs
[100-200]
Ca
[300-400]
PSAT (dBmm
Ly Ls
[100-200] pH
DE (%)
DohPA (10)
120k
[350-450] pH
PAE
La
[500 600 ptl
pl
Ls
[300-400] pH
Wsr. Wse
[6 13m
Lip
[100-500] ptl
Li
pll
Tap
[0.8-1.2] nH
(II)
80k
Lee
(400-800) pH
Lm
[50-250|pH
WNT
|6 [6-31]
Wxz
pm
18

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B.4 Voltage Amplifiers (VAs)
Voltage amplifiers (VAs) are fundamental components in analog circuit design, responsible for increasing signal amplitude while preserving waveform integrity. Effective VA design requires balancing key performance metrics tailored to both RF and baseband operating conditions 44. In this work, we implement four widely used VA topologies topologies-coomeeee common-source VA (CSVA), common- gate VA (CGVA), cascode VA (CVA), and source follower VA (SFVA) as shown Figure T2
The CSVA remains the most widely adopted configuration due to its structural simplicity and high voltage gain. It is frequently used as the first gain stage in various analog systems [45). The CGVA is suitable for applications requiring low input impedance and wide bandwidth, such as impedance transformation or broadband input matching [66.. The CVA, which cascades common-souree stage with common-gaa transistor, improves the hain-bandwidth product and enhances stability, making ideal for applications demanding wide dynamic range and robust gain control 47 The SFVA, also known as common-drait amplifier, provides near-unity voltage gain and low output impedance, making it well suited for interstage buffering, load driving, and impedance bridging [48] Parameter ranges and performance specifications for these VA topologies are listed in Table I0.
Voo
Voo
Voo
Vast
Vausa
Wut
Vout
V.-
Wwz
Vost
V
Vatta
WN
V,
Ww
Ww
V.-
Wxz
Vn
V/3
Wno
(a) CSVA
(d) SFVA
(b) CGVA
(c) CVA
Figure 12: Schematic diagrams of the four VA topologies.
Table 10: VA topologies with parameter sweep ranges, sample sizes, and performance metries.
Dataset Type
Topology (Code)
# of Samples
Parameter
Sweep Range
Performance Metrics (Unit)
C
[0.1-1.5]pF
R
[0.1-15)k2
CGVA (12)
33k
Wxi
[m-30]um
Wxz
[5-10]pm
R
10.7-1.5)K
Ws
13-15|um
CSVA (13)
21k
Van
[1-1.8] V
DCP (W)
Ven
[0.6-0.91 V
VGain (dR)
R
[1-3]kB
RW (H>)
CVA
22k
Ws.. Wxz
[1-10]
Wxs
[10-15]pm
Wai
[40-60]um
Wxo
12-8]
(15)
Ven
[1.1-18]
Vane
10.6-1.2V V
Vo
[0.5 0
B.5 Voltage-Controlled Oscillators (VCOs)
Voltage-controlled oscillators (VCOs) essential building blocks in analog and RF systems, responsible for generating periodic waveforms with frequencies modulated by control voltage. These circuits rely on amplification, feedback, and resonance to sustain stable oscillations. Owing to their wide tuning range, low power consumption, and ease of integration, VCOs are broadly used in systems such as phase-locked loops (PLLs), frequency synthesizers, and clock recovery circuits [49] In this work, we implement four representative VCO topologies-indnctivee inductive-feedhanne VCO (IFVCO), cross-coupled VCO (CCVCO), Colpitts VCO (ColVCO), and ring VCO (RVCO) as shown in
Figure 13
19

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The IFVCO employs an NMOS differential pair with inductor based feedback path to sustain oscillations. This topology provides favorable noise performance and compact layout, making well suited for low-voltage, low-power designs [50] The CCVCO achieves negative resistance through cross-coupling, enabling low phase noise and high integration density, and is widely adopted in frequency synthesizers and PI.Ls [5T]. The ColVCO uses an LC tank and capacitive feedback to achieve high frequency stability and low phase noise, making it ideal for precision RF communication and instrumentation [52). The RVCO consists of cascaded delay stages forming feedback loop, offering low power consumption, wide tuning range, and minimal area footprint, though at the cost of higher phase noise. It is commonly used in on-chip clock generation and low-power sensor applications [53]. Design parameters and performance metrics for these VCO topologies are presented in Table II
Vio
Vir
V
Wur
Vuei
Vier
(a) IFVCO
(b) CCVCO
(c) ColVCO
(d) RVCO
Figure 13: Schematic diagrams of the four VCO topologies.
Table 11: VCO topologies with parameter sweep ranges, sample sizes, and performance metrics.
Dataset Type
Topology (Code)
Samples
Parameter
Sweep Range
Performance Metrics (Unit)
Ci
[700-900) IF
C2
(IV)
43k
L1
[400-600] pH
L;
[500-700]pt pH
Wx. W
[5-9]
L
(200-400] pH
CCVCO (17)
54k
Wy
[10 35m
DCP (W)
War
pm
OscF (Hz)
VCO
C
180-140] IF
TR (Hz)
I.
[250 350] pH
OutP (dBm)
ColVCO (18)
90k
War
Ws
[30-50] jm
[5 pm
PN (dBc/H2)
Vu
[0.7-1.2]
Jai
[5-15] mA
C
[300-700] IF
[300-500] pH
RVCO (19)
46k
L:
[50-250]
Wy
[20 40) pm
Wa
[5-25|um
C Robustness Across Random Seeds
Table 12: Topology selection performance with scores and 95% confidence intervals across five random seeds.
To evaluate the robustness of models to ran- dom initialization and data shuffling, we repeated experiments using five distinct random seeds: {42, 123, 777, 2023, 3407). ). Reporting across multi- ple seeds is important for ensuring that observed results are not artifacts of a specific initialization training trajectory, but rather reflect the stable behavior of the method. For each metric, we com- pute the mean and 95% confidence interval across seeds, reporting results in the form j +
Metric
Mean + 95% CI (1))
Accuracy
99.57 0.01
Balanced Accuracy
99.34 + 0.02
Macro Precision
99.27 + 0.01
Macro Recall
99.34 - 0.02
Macro F1
99.30 + 0.01
Micro Fl
99.57 + 0.01
20

---

For the MLP topology selection model, results are highly stable across random seeds. The accuracy reaches 99.57 + 0.01% % with balanced accuracy at 99.34 = 0.02%, while both macro and micro F1 scores exceed 99.3% with confidence intervals no larger than +0.02. These narrow intervals indicate that the MI.P's performance is effectively invariant to random initialization, underscoring its robustness and reliability in the topology selection stage of the pipeline (Section +
For the GNN-based forward performance prediction model, the overall mean relative error across all metrics
(95% CI). Individual performance predictions, including DC power consump- tion, gain, bandwidth, and oscillation frequency, exhibit narrow confidence intervals for example, noise figure achieves 4.48 + 0.07% error and oscillation frequency 0.65 + 0.03%. These results indicate that the GNN achieves consistently accurate predictions across diverse eircuit characteristics. The tight confidence intervals further demonstrate that the model's 's performance is robust to random initialization, underscoring reliability as a generalizable forward predictor within the pipeline (Section 5 The full seed-dependent results for both models are provided in Tables 12 and 13
Table 13: Prediction accuracy of the forward GNN with mean scores and 95% confidence intervals across five random seeds.
DCP
Sa
Psar
VSwg
Drr. (3)
0.155
D User-Defined Loss Functions for Gradient Reasoning
Stage 3 of FALCON employs gradient reasoning with the forward GNN fixed, enabling the op- timization objective to be redefined without retraining or fine-tuning the predictive model. This design allows users to flexibly adapt the loss function to capture specific trade-offs constraints. We illustrate this flexibility with two examples.
Weighted Performance Loss. Rather than treating all performance metrics equally, users specify weights a; for each target metrie:
weirt-weighhed
mia; (0: - y, target )2
Σ, m200
where larger a; prioritize certain specifications (e-g.. gain or noise figure). Here, m, if the i-th metric is defined for the current sample, and 0 otherwise.
Interval-Constraneet Performance Loss. Users may also define acceptable ranges for metrics rather than fixed targets. Given optional lower and/or upper bounds y upper the interval penalty is:
inpertiiterval
Σg ma 1 (opter defined) max (0, DJ Y,
upper + (yprar defined) max(0. V:
Jower
where the indicator [[)) indicates whether the corresponding bound is specified. This formulation naturally handles the cases where only upper bound, only lower bound, or both bounds are provided. As above, m, = the i-th metric is defined for the current sample, and 0 otherwise.
General Extensibility. More generally, the total loss in Eqn. can be replaced with any user-defined formulation, allowing both Epent and Luyouur to be substituted with eustomized objectives. Additional physical constraints, multi-objective trade-offs, or alternative layout penalties can be incorporated with only a few lines of code. This extensibility underscores the flexibility of FALCON and enables the framework to adapt to diverse design objectives.
E
Layout Design and DRC Compliance
E.1 Design Rule Enforcement in 45 nm CMOS
We implemented FALCON using a 45 nm CMOS technology node, applying rigorous Design Rule Checking (DRC) at both the cell and full-chip layout levels. At the cell level, our parameterized layout generators enforeed Soundry-speciffe constraints, including minimum feature width and
21

---

length, contact and via spacing, and metal enclosure rules. At the circuit level, we incorporated physical verification to mitigate interconnect coupling. IR drop, and layout-dependent parasitic mismatches- that are especially critical in high-frequency and precision analog design.
DRC plays vital role in ensuring that layouts comply with process design rules defined by the semiconductor foundry. Adhering to these rules ensures not only physical manufacturabiliit but also electrical reliability. Violations may lead to fabrication failures, including yield degradation, electrical shorts or opens, ddectomiigraiooninnduedd issues, and parasitic mismatches. Moreover, DRC compliance is essential for compatibility with downstream fabrication steps such as photomask generation, optical lithography, and chemical- mechanical planarization (CMP), safeguarding the yield and fidelity of the final IC.
Circuit-Level Layout Guidelines. We enforced several topology-aware layout constraints during full-circuit integration to preserve signal integrity and robustness:
Inductor-to-induccor spacing: 2 35.0 pm to mitigate mutual inductive coupling and magnetic interference.
Guardring placement: Sensitive analog blocks are enclosed by N-well or deep N-well guardrings with spacing 2 5.0 jm suppress substrate noise coupling.
Differential pair symmetry: Differential signal paths are layout-matched to ensure AL < 0.5 μm, minimizing mismatch and preserving phase balance.
DRC Constraints and Layer Definitions. Table 14 summarizes the DRC constraints applied to key analog components across relevant process layers. Table 15 provides the abbreviations used for metal, contact, and via layers in the 45 nm CMOS process.
Table 14: Design rule constraints for key analog components in 45 nm CMOS.
Component
Layer
Physical Constraint
Symbol
Value
Unit
QT/LD
Minimum Cap Width
WMIN
6.05
jm
QTELD
Maximum Cap Width
WMAX
150.0
pm
MIM Capucitor (QT. LD. VV,
QUELD
Cup Length
L
6.0
pm
VV
VV Square Size
VV VV_SIZE
4.0
jm
VV
VV Spacing
VVSPPACE
2.0
jm
VV
VV to Edge Spacing
VV. EDEEEE MIN
1.0
pm
RX
Minimum Width
WMIN
0.462
jm
RX
Maximum Width
WMAX
5.0
RX
Minimum Length
LAIN
0.4
Resistor (RX, MI)
RX
Maximum Length
LAAA
5.0
pm
CA
Contact Size
CA_SIZE
0.06
pm
Contact Spacing
SPACE
pm
to Edge Spacing
EDGE
jm
M3
Minimum Width
M3. W WIM
2.0
jm
Inductor (M3)
Maximum Width
3__
pm
Minimum Spacing
M3.5 S. MIN
jm
Grid
All Layers
Minimum Grid
Min_Gri
0.005
jm
Table 15: Process layer abbreviations in the 45 nm CMOS design flow.
Layer Name
Description
RX
Resistor implant diffusion layer used define integrated resistor geometries.
CA
Contact layer forming vias between diffusion/poly and the first metal layer (MI).
MI
First metal layer, typically used for local interconneets and resistor terinnas..
MB
Third metal layer, used for wider routing tracks and planar inductor layouts.
QT
Top metal plate in MTM capacitor structures, prowiding the upper electrode.
LD
Lower metal plate MIM capacitor structures. acting as bottom electrode.
VV
Via layer connecting different metal layers, especially capacitor and donse routing regions.
OB
Opening/blocking layer used to define restricted zones, often exclude metal or for CMP mask clarity.
22

---

W
Doy-2R
Dx
MIM capacitor layout
(b) Resistor layout
(c) Inductor layout
Figure 14: Layout views of passive components. (a) MIM capacitor with soaddlinnuaato-mettttt stack.
(b) Resistor layout with matching geometry. (c) Spiral inductor with octagonal turns for optimized area and Q-factor.
E.2 MIM Capacitor Capacitance Model
The total capacitance CN a metal-insuulaoor-mtta (MIM) capacitor modeled as:
CN =
C. C W + C,, 2- (L W)
[fF]
where L and W are the layout length and width in μam, C. is the area capacitance density, and Cp is the fringing field contribution per unit length. This model includes both area and perimeter contributions to more accurately reflect layout-dependent capacitance in IC design (see Figure 14 a)).
Area Capacitance Term:
C. L. W
This term represents the primary (parallel-plate) capacitance formed between the overlapping top and bottom metal layers. It arises from the uniform electric field across the dielectric.
Physical Concept:
Layer Physics Explanation:
L W corresponds to the overlap area of the plates.
C. 0.335 fF/mm2 is the area capacitance density, derived from:
Dielectric permittivity of the insulating material.
Dielectric thickness d, with C e/d.
Perimeter (Fringing) Capacitance Term:
2
Physical Concept:
This term models fringing fields at the plate edges, contributing additional capacitance particularly relevant small geometries.
Layer Physics Explanation:
2- 2L W) is the physical perimeter of the capacitor.
. C, = 0.1 fFl1FFmmm accounts for the fringing field contribution per unit length.
Summary:
This composite model enables accurate estimation of MIM capacitance by capturing both parallel-plate and fringing effects. The constants C. and Cp are typically calibrated using process-speciff measurements electromagnetic simulations.
For fixed capacitor length L. 20 pm and width W [6.05, 150.0] pm, the layout-aware capaci- tance is approximated by:
C 6.92 W 4.4
[IF]
The corresponding bounding area estimated from the component's geometric envelope:
Bounding Area = 22W + 44 [um²]
(5)
E.3
N Silicided Polysilicon Resistor Model
The resistance of layout-defined resistor implemented using the ndslires layer is modeled as:
L
R = R.
+ 2R +
[2]
W
AW
23

---

This structure uses heavily doped N* polysilicon overlaid with a silicide layer reduce resistance. Current flows laterally through the poly-silicide film (see Figure [4(b)) and resistance is shaped by the aspect ratio of the layout as well as process-dependent corrections.
Physical Concept:
Layer Physics Explanation:
R = 17 (ohm per square) the sheet resistance the silicided poly layer.
.
W 5.0 jmm is the drawn width; AW 0.048 um accounts for process poocess-induced width bias.
L is the drawn resistor length.
Rend = 1 S2 models terminal resistance due to contact diffusion and current crowding.
0.917 Ω accounts for residual dayout-dependen parasitics.
Summary: The empirical layout relation used in parameterized generation is:
~ 3.5007 + 2.917
[22]
(6)
This model is valid for I. E [0.4, 5.0] um with fixed width W 5.0 pm. 5.0 based on bounding box dimensions is:
The estimated layout area
Bounding Area 5.2L 8.362
[um 2
E.4 Octagon Spiral Inductor Model
Physical Concept: Accurate modeling and layout optimization of planar spiral inductors critical in analog circuit design. Inductor performance is highly sensitive to parasitic elements, achievable quality factor (Q), and layout constraints imposed by process design rules. To support accurate performance prediction and inform layout choices, we adopt modified power-law model that expresses inductance
function of key geometric parameters. The model is validated against empirical measurements and shows strong agreement with classical analytical formulations.
Numerous classical formulations relate inductance geometric factors such the number of turns, average diameter, trace width, and inter-turn spacing. Among these, the compact flosed-form expressions in RF Microelectronics lextbook (30) widely adopted for their balance of simplicity and accuracy. Building on this foundation, we adopt reparameterized monomial model that better fits empirical measurement data:
L = 2.454 10-1. D-1221 W0..603 -22.836, S-0.019
nnH
Layer Physics Explanation:
Dan 2(R W) is the outer diameter,
Table 16: Measured inductance for one-turn in- ductors with fixed W 10um um and S 0.0 pm
Dn = 2(R - W ) is the inner diameter,
2
Davg = (Dout + Dm)/2 2R is the aver-
age diameter,
R (um)
30
40
50
60
R is the radius in μm,
L (nH)
0.123
0.170
0.220
0.276
W the trace width in um,
S is the spacing μm.
This expression is calibrated using measured data from a series of one-turn inductors fabricated with varying radius (Rt), while keeping the trace width fixed at W = 10 pm and spacing at S = 0.0 Table 16 summarizes the measured inductance values used for model fitting.
Summary: With W and S fixed, inductance simplifies to:
L Rc 2.337 10
10-3, 3. -p.164
[[H]
(8)
The bounding area is estimated by:
Bounding Area = 4R² + 108R + 440
[um
(9)

---

The performance of on-chip inductors is fundamentally influenced by layout-dependent factors such as trace width, metal thickness, and inter-turn spacing. Increasing the trace width (nn))) reduces series resistance by enlarging the conductor's cross-sectional area, thereby improving the quality factor, Q = wT// Rugries- However, wider traces also increase parasitic capacitance to adjacent turns and the substrate, which lowers the self-resonance frequency.
Metal thickness (Hlind) also plays crucial role minimizing ohmic losses. At high frequencies, current is confined near the conductor surface due to the skin effect. For copper at 25 GHz, the skin depth is approximately 0.41 jmm; thus, using metal layer thicker than 46 (i.e., 1.6 μm) ensures efficient current flow. However, increasing thickness beyond this threshold yields diminishing returns Q due to saturation in current penetration.
Tum-to-turn spacing (S) affects both inductance and quality factor (Q). Tighter spacing enhances magnetic coupling, thereby increasing inductance density. However, it also intensifies capacitive coupling and dielectric losses- paatess-articllarlyy in modern CMOS processes with high-k inter-metal dielectrics- which can degrade Q. Conversely, excessive spacing reduces inductance without providing a proportionate benefit in loss reduction. As a result, one-turn spiral inductors are commonly favored in RF design due their low series resistance, minimized parasitics, and improved modeling predictability.
These insights guided our design choices for layout- inductor implementation. To balance the competing demands of Q optimization, parasitic control, and DRC compliance, we implemented inductors using Metal 3 and set W 10 um the default trace width. This width offers low- resistance path that enhances Q while maintaining manageable parasitic capacitance and sufficient pitch for lithographic reliability. Metal 3 was selected for its favorable trade-off between thickness and routing density-it is thick enough to mitigate skin-effect losses at high frequencies while offering sufficient flexibility for compact layout integration.
The implemented spiral inductor geometry is shown in Figure [4.c. Table 17
summarizes the compcimpliant tuning ranges, estimated layout areas, and decomposition strategies for single-cell passive components in our layout library.
Table 17: Single-cell passive component limits based on DRC and associated layout area costs.
Component
Tunable Variable
Value Range
Area Range
Decomposition Rule
Resistor
Length L
4.32-20.4212
10.44-34.36 yum?
Series if >> max, parallel if < min Parallel if max, series if min
Capacitor
Width W
46.32-1042.44FF
176-3344 pm?
Inductor
Radius
nH
5640 pm?
Continuous radius scaling
E.5
Layout Examples of Synthesized Circuits
To illustrate the correspondence between schematic and layout representations, we present three synthesized circuits: DBAMixer, IFVCO, and DLNA, shown Figures [5 [6 and respectively.
Vie
15gr
Vir
Vy.
Wio
Wwe
Vlo
22
W
Vio-
Wwr
Ww
Var.
187
157ur
Ronting
W..
Capacitor
Resistor
Wi.
W..
(b) Layout of designed DBAMixer
(a) Designed DBAMixer schematic
Figure 15: Stage results for synthesized DBAMixer. The schematic (a) reflects optimized parameters to meet the target specification. The layout (b) DRC-compliant and physically realizable. The final design achieves mean relative error of 0.2% compared to the target performance.
25

---

000
350 pM
330 pt
Vat
Veradtor
Wirr
000
534
War
Routing
G
Vose
120 jm
Wn
Wy
100
Vasit
Capucitor
Inductor
C2 100 FF
C2 200
W
(a) Designed IFVCO schematic
(h) Layout of designed IFVCO
Figure 16: Stage 3 results for a synthesized IFVCO. The schematic (a) reflects optimized parameters meet the target specification. The layout (b) is DRC-compliant and physically realizable. The final design achieves a mean relative error of 1.3% compared to the target performance.
Wi
R.
112ptt
NMHOS Transiose
Wio
G)
Wie
Ww
124um
Ww
Ve.
11
000
Wer
Wer
000
My.
SARIA
earyet
Routing
Indactor
(a) Designed DLNA schematic
Capacitor
Resistur
(b) Layout of designed DLNA
Stage results for synthesized DLNA. The schematic (a) reflects optimized parameters to meet the target specification. The layout (b) is DRC-complian and physically realizable. The final design achieves mean relative error of 5.0% compared to the target performance.
Figure 17:
In the IFVCO example, the inductor labeled Ly functions as RF choke and is excluded from the on-chip layout due to its large area requirement. Instead, it intended for off-chip implementation at the PCB level and connected to the die via wire bonding. This external connection is indicated by the yellow pad in Figure b)),), which serves as the wire-bonding interface.
Since the current stage of system lacks automated routing, all interconnects in the layout were manually drawn to ensure accurate correspondence with the schematic connectivity. These examples demonstrate that synthesized circuit parameters can be successfully translated into DRC-compliant, physically realizable layouts, bridging the gap between high-level optimization and tapcout-ready design.
F Practical Considerations and Limitations
F.1
Training and Inference Efficiency
Although our codebase supports GPU acceleration, all experiments in this work exccudidnn initial dataset generation- -eee conducted entirely on MacBook CPU. This highlights the efficiency and accessibility of the FALCON pipeline, which can be executed on modest hardware without specialized infrastructure. Our MIPP and GNN models contain 207k and 1.4M trainable parameters, respectively, with memory footprints of just 831 KB and 5.6 MB.
26

---

In Stage 1, the MLP classifier trains in approximately 30 minutes with batch size of 256 and performs inference the order of milliseconds per batch. Stage 2's GNN model takes around 3 days to train on the full dataset using the same batch size and hardware. Fine-tuning unseen topology (e.g., RVCO) using ~30,000 samples completes under 30 minutes.
In Stage 3, the pretrained GNN is used without retraining to perform layout- conotrtnndt parameter inference via gradient-based optimization. Inference is conducted one instance at time (batch size 1), with typical runtimes under second per circuit. Runtime varies based on the convergence threshold and circuit complexity but remains below 2-3 seconds in the worst case across the full test set.
solution is considered successful if the predicted performance meets the target within a specified relative error threshold. While tighter thresholds (c.g., 5%) improve accuracy, they require more optimization steps- particualllll over large datasets. As a result, both success rate and inference time in Stage 3 directly influenced by this tolerance, which be tuned based on design fidelity requirements.
F.2 Limitations
This work focuses representative set of 20 curated analog topologies spanning five circuit families. Consequently, the topology selection stage is limited to suggesting only among the designs present in the training set and cannot synthesize novel circuits. A natural future direction is to either extend the training library to a broader set of topologies or replace the classifier with a generative model capable of directly proposing the GNN-based forward modeling stage is designed to operate on arbitrary circuit graphs and has already demonstrated strong generalization to unseen architectures (e.g., RVCO), indicating that modification to this stage is required to support novel circuits.
netlists conditioned input specifications. In contrast,
Beyond topology considerations, the dataset is constructed at fixed operating frequency of 30 GHz, which ensures consistency across circuit families but constrains frequency generalization. Although the framework can, in principle, extend to other operating points for example, the voltage amplifier topologies already demonstrate scalability across varying gain-bandwidth trade-offs- crude-ofs--yystematti validation across diverse frequency bands beyond the scope of this work. Extending the dataset to cover multiple operating frequencies, or incorporating frequency as an explicit conditioning variable during training. represents important direction for broadening applicability.
Finally, the differentiable layout model FALCON captures parasitic effects through analytical approximations of passive components, which is effective for guiding parameter optimization within the learning framework. However, this approach does not fully replace electromagnetic (EM) simulations or post-layout verification, and electromigration constraints not explicitly incorporated. Incorporating learned parasitic estimators, EM-informec models, and reliability constraints, therefore, remains important extension toward bridging schematic- optimization and silicon-pru proven robustness. In addition, all interconnect routing in the current flow is performed manually to ensure precise control over parasitic management and DRC compliance. While this provides accuracy for the studied designs, it limits scalability for more complex circuits, motivating future integration with automated analog routing tools.
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NeurIPS Paper Checklist
1. Claims
Question: Do the main claims made in the abstract and introduction accurately reflect the paper's contributions and scope?
Answer: [Yes]
Justification: The abstract and introduction clearly state our contributions, including the three-stage pipeline and dataset. These claims are supported by the methodology and results.
Guidelines:
The answer NA means that the abstract and introduction do not include the claims made the paper.
The abstract and/or introduction should clearly state the claims made, including the contributions made in the paper and important assumptions and limitations. A No or
NA answer to this question will not be perceived well by the reviewers.
The claims made should match theoretical and experimental results, and reflect how much the results can be expected to generalize to other settings.
is fine to include aspirational goals as motivation as long as is clear that these goals are not attained by the paper.
2. Limitations
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Reviews:
[{"review_id": "Q2QM7i7Apu", "reviewer": "Reviewer_RMej", "summary": "This paper introduces a new, single, and scalable machine learning framework for the entire end-to-end analog circuit design flow, including such tasks as topology selection, parameter inference, and layout-aware optimization. Analog and RF design flows conventionally tend to be manual, iterative, and strongly reliant on designer heuristics. FALCON addresses these limitations by formulating circuit synthesis as an inverse problem: given a target performance specification, the framework learns both the circuit topology and parameter configuration to meet the target. \nThe system operates in three stages. In the first stage, it demonstrates the performance-directed topology selection by using a light multilayer perceptron. Secondly, it illustrates the performance prediction by a graph neural network that has been trained on Cadence-simulated circuit graphs. Eventually, this stage emphasizes the gradient-based optimization layout-driven with differentiable constraints to parasitic and physical layout rules. Overall, one of the key contributions is to bring layout goals directly into the optimization loop so that schematic and layout concerns can be represented jointly.", "questions": "Question 1: Can you incorporate or evaluate a richer parasitic/EM-aware surrogate (e.g., a simple analytic coupling model or pre-trained EM estimator) in your differentiable layout loss? Your current area-only proxy may underestimate critical mm-wave effects, risking larger errors in post-layout verification. The paper can include a small ablation comparing pure area loss vs. an EM-informed loss on a subset of topologies.\nQuestion 2: Have you measured variability across multiple training runs? Reporting only single-run metrics makes it hard to assess stability, especially for large GNNs. Your team should provide mean±std for key metrics (topology accuracy, forward RMSE, inversion error) over several runs.\nQuestion 3: Have you tested applying FALCON to lower-frequency analog or mixed-signal blocks? Broader applicability would greatly enhance the framework’s impact in EDA. At minimum, discuss the modifications needed or outline a small pilot on one low-frequency topology.\nQuestion 4: Given the high training cost, can you provide a “light” version (e.g., subset of 100k samples) or share pretrained weights to lower the barrier for replication? Accessibility to smaller labs/companies is critical for adoption and follow-up research. Your team can release a trimmed dataset + pretrained model checkpoint for at least one topology family.", "limitations": "No. Suggestions for Improvement: The paper would benefit from an explicit “Limitations” section that summarizes key boundaries of FALCON’s applicability such as its reliance on a fixed topology library, simplified layout surrogate, and exclusive focus on mm-wave blocks so that readers immediately grasp where the approach may fall short.", "rating": 5, "confidence": 3, "soundness": null, "presentation": null, "contribution": null, "strengths": "", "weaknesses": "", "quality": 3, "clarity": 3, "significance": 3, "originality": 2, "strengths_and_weaknesses": "Strengths：\n1. The authors present and publicly release an exceptionally large, high-fidelity dataset of over one million Cadence Spectre simulations spanning 20 expert-designed mm-wave analog/RF topologies. Such an industrial-scale, process-calibrated dataset is exceedingly rare in the academic literature. \n2. FALCON integrates three distinct components—performance-driven topology selection, a graph-neural-network forward model, and a differentiable layout cost—into one seamless, differentiable pipeline. This modular design is among the first to jointly handle inverse circuit design and layout constraints in a unified framework. By embedding parasitic effects and soft design-rule penalties directly into the gradient-based optimization via a differentiable layout loss, the method ensures that the inferred parameters meet both electrical performance targets and physical manufacturability requirements, filling a gap left by traditional “simulate-then-layout” or post-hoc layout workflows.\n3. FALCON demonstrates few-shot generalization by maintaining high accuracy on an entirely unseen topology, indicating its potential for rapid adaptation to new circuit families with minimal additional data. Furthermore, all sub-modules rely on lightweight MLPs or edge-centric GNNs, and the final inversion stage runs in milliseconds to seconds without invoking time-consuming circuit simulators. This real-time performance aligns with the stringent requirements of practical automated design toolchains, highlighting the framework’s clear path to industrial deployment.\n\nWeaknesses：\n1. FALCON assumes a “fixed but extensible” library of expert-designed circuit topologies, which means it cannot autonomously discover or generate novel structures. In contrast to purely generative topology search methods, its capacity for true topological innovation is bounded by the existing template set. This reliance may limit FALCON’s ability to propose entirely new architectures beyond human-curated designs.\n2. The differentiable layout cost in FALCON is based solely on simple two-dimensional area calculations for passive components, omitting more complex parasitic couplings, electromagnetic interactions, and multilayer interconnect effects. In high-precision mm-wave designs, these richer physical phenomena can dominate performance, so a purely area-based surrogate may underestimate post-layout discrepancies, potentially widening the gap between predicted and actual behavior.\n3. All quantitative results in the paper derive from a single training run with fixed random seeds and there is no reporting of standard deviations, confidence intervals, or other measures of variability across multiple trials. For complex models trained on large-scale data, stability and sensitivity to initialization can materially affect conclusions. The absence of statistical significance metrics makes it difficult to assess the robustness of the reported performance gains.\n4. While FALCON covers five key mm-wave circuit type, its evaluation is confined to the mm-wave frequency band. The framework’s generality and performance in lower-frequency analog circuits, mixed-signal systems, or digital-analog co-design scenarios remain untested. This restriction may hinder broader adoption in electronic design automation, where diverse frequency domains and mixed-signal workflows are commonplace.", "was_revised": true, "final_justification": "I keep my \"accept\" score.", "rebuttal": "We sincerely thank the reviewer for their thoughtful and constructive feedback. We appreciate the time and care taken to engage with our work, and we are grateful for the encouraging evaluation and insightful suggestions that have helped us improve the paper.\n\n**Weaknesses:**\n1. We thank the reviewer for raising this important point. FALCON currently operates on a fixed library of expert-designed topologies to ensure physical validity, layout feasibility, and manufacturability. While this limits autonomous discovery of novel architectures, we believe it provides a robust foundation for real-world deployment. We agree that expanding to generative topology search is a promising future direction. In future work, we plan to explore incorporating schematic-level generators that can propose new topologies, which could then be evaluated and optimized within the existing FALCON pipeline.\n\n2. We thank the reviewer for highlighting this important aspect. Our pipeline is designed to generate near-realistic, manufacturable IC layouts for mm-wave circuits at 30 GHz. In this work, we focused on a layout objective that minimizes the physical area of passive components, which serves as a differentiable proxy in Stage 3. This area-based objective is the default loss used throughout the main experiments. In addition, we have implemented two other layout variants—minimizing interconnect length and minimizing congestion—to explore trade-offs among compactness, signal integrity, and routability. We will include these additional variants as an ablation study in the appendix.\n\nWhile the current differentiable loss relies on geometric proxies, our layout generator incorporates several physical constraints, such as self-resonance frequency, quality factor, and DRC compliance, to ensure that passive component layouts remain suitable for baseline mm-wave design. We fully agree that geometric loss alone cannot capture the full range of EM effects. Extending the layout cost to incorporate EM-aware modeling represents a valuable future direction, particularly for capturing coupling and loss at higher frequencies.\n\n3. We thank the reviewer for raising this important point regarding robustness and variability. We have now performed additional experiments to assess the stability of our results across multiple seeds:\n\n- **Topology Selection:** We conducted 5 independent runs with different random seeds. The results, summarized below, show extremely low variance, reflecting the deterministic nature of the classification task given the strong separation between topologies in the performance space:\n\n|Metric|Mean ± 95% CI|\n|-|:-:|\n|Accuracy| 99.57 ± 0.01|\n|Balanced Accuracy | 99.34 ± 0.02|\n|Macro Precision| 99.27 ± 0.01   |\n|Macro Recall| 99.34 ± 0.02|\n|Macro F1| 99.30 ± 0.01|\n|Micro F1| 99.57 ± 0.01|\n\n- **Performance Prediction:** Due to the longer training time per run, we performed 3 runs with different seeds. The mean relative error across 3 random seeds was **8.80 ± 0.34%** (95% confidence interval). Full statistics (including per-performance results) will be included in the final version of the paper. The results show that performance is stable across seeds.\n- **Parameter Inference:** This stage does not involve training and is not sensitive to seed initialization. The only source of randomness is the initial parameter vector for gradient reasoning. However, this has a negligible effect on the final results due to the fixed termination criterion: random noise may alter the number of steps but not the output quality, and the optimization remains highly efficient (under 1 second per sample on CPU). Considering that another reviewer also inquired about the role of initialization in this stage, we will include an ablation study in the final version, analyzing the effect of noise type and variance on convergence and accuracy.\n\nWe appreciate the reviewer’s suggestion and will incorporate these robustness analyses into the final paper to strengthen the experimental evaluation.\n\n4. We sincerely thank the reviewer for raising this important point. We fully agree that extending FALCON to cover lower-frequency analog circuits, mixed-signal systems, and broader co-design scenarios is essential for increasing its practical utility and adoption. While the current version focuses on mm-wave designs, the core architecture of FALCON is adaptable to a wider range of circuit types. Specifically:\n- Our pipeline can naturally incorporate frequency into the design process in two flexible ways. First, frequency can be treated as a user-defined target and concatenated with the performance vector across all stages; in this case, the GNN forward model and MLP predict the corresponding circuit parameters and topology that meet the specified frequency and performance. Alternatively, frequency can be treated as an output of the pipeline, where the gradient reasoning determines the optimal frequency alongside the circuit parameters (the input of the forward GNN model). Although our baseline evaluation is limited to 30 GHz due to the scope of our dataset, this is not a limitation of the framework itself. The pipeline is structurally capable of supporting frequency-aware design given appropriate training data.\n- We chose to focus on mm-wave circuits at 30 GHz for two main reasons: (i) our group’s expertise in RF, mm-wave, and THz design enabled us to select robust and realistic circuit schematics; and (ii) layout effects become increasingly critical at higher frequencies, making layout-aware design especially relevant for mm-wave applications.\n\nThat said, we view this as a natural and exciting direction for future work and believe that FALCON’s modular structure makes such extensions feasible with appropriate data and design targets.\n\n**Questions:**\n1. We thank the reviewer for this insightful suggestion. To mitigate electromagnetic (EM) losses and parasitic coupling in mm-wave and analog layouts, our framework integrates several spatial strategies during placement and routing. These include mandatory spacing rules for interconnects and passive components to reduce both capacitive and inductive coupling.\n\nSpecifically, we enforce a minimum spacing of 5 μm between routed signal traces by defining exclusion zones that prevent nearby routing. For passives such as inductors, which are particularly sensitive to mutual coupling at mm-wave frequencies, we impose an edge-to-edge clearance of at least 15 μm. This threshold was determined based on EM simulations showing negligible coupling beyond this distance. These spacing constraints are automatically handled during layout generation and are reflected in the loss computation used for optimization.\n\nTo further enhance EM-awareness, we will introduce a vertical coupling constraint: limiting the overlap area between stacked upper metal layers (e.g., M8 and M9) to reduce unintended capacitive interactions between interconnects on different layers. This rule will be incorporated into the layout engine and corresponding loss function. In the final version of the paper, we will include an ablation comparing our current area-based layout loss against this enhanced EM-informed variant, using a representative subset of topologies.\n\nWe fully agree that integrating analytic or learned EM surrogates is a valuable direction for future work. While our current implementation does not incorporate such models directly, we view this as a natural extension of the FALCON framework and appreciate the reviewer for highlighting this important point.\n\n2. We thank the reviewer for raising this point and kindly refer to our response to Weakness 3, where we address training variability and provide statistics across multiple runs.\n\n3. We thank the reviewer for raising this important point. As noted in our response to Weakness 4, extending FALCON to lower-frequency analog and mixed-signal circuits is a natural and valuable direction for future work. While this version focuses on mm-wave designs, the core framework is flexible and can be adapted to broader frequency ranges and circuit classes.\n\nAmong the circuits currently included, our voltage amplifiers closely resemble their low-frequency counterparts in structure and design principles, and may serve as a preliminary example of applicability in that domain. That said, we agree that a dedicated evaluation on diverse low-frequency and mixed-signal blocks would strengthen the framework and is a valuable future direction.\n\n4. We appreciate the reviewer’s suggestion to improve accessibility. To support broader adoption and reproducibility, we have already released pretrained weights for the general forward GNN model (FALCON-main/checkpoints/best_gnn_model.pt), along with the fine-tuned GNN model on RVCO and the MLP topology classifier, all included in the supplementary material. All models are compact (e.g., 5.6MB for the GNN) and readily usable for fine-tuning or evaluation.\n\nAdditionally, our released dataset includes a structured directory of circuit graphs and parameter-performance CSVs, and users can easily work with a smaller subset (e.g., 100k samples or a single topology family) without any changes to our codebase. We believe this enables efficient experimentation even for groups with limited resources, and we welcome further feedback from the community on additional lightweight configurations.\n\n**Limitations:**\n\nWe thank the reviewer for this helpful suggestion. As noted, we already include a “Limitations” section at the end of the appendix in the supplementary material, summarizing key constraints of the current framework. We recognize that placing it in the supplement may have made it less visible. If the paper is accepted, we will move this section to the extra page of the main paper, and we will incorporate the additional limitations noted by the reviewers. We agree that making these boundaries explicit will help readers better understand the scope and applicability of FALCON."}, {"review_id": "cL3dlZ84jw", "reviewer": "Reviewer_TBnj", "summary": "This paper presents an ML framework for automating analogue circuit design. The framework consists of: (1) topology selector module, (2) forward GNN mapper that evaluates the performance of a topology-parameter pair, and (3) differentiable layout-constrained optimisation of circuit parameters. The framework is evaluated on a 1 million dataset of millimetre-wave circuits to demonstrate successful end-to-end analogue circuit design.", "questions": "- In Section 3.3 line 165, is the term “reasoning” for describing the optimisation of Eq. (1) the best term to use?\n- In Section 4, line 184, regarding the 5-layer MLP, is it possible to ablate this?\n- For Figure 3(a), can you provide expanded commentary on the t-SNE visualisation. For instance, could you speculate as to what the strands in the pastel purple cluster (north-most) may mean from a circuit topology standpoint?\n- In Section 5, paragraph “Evaluation” (right after line 237), can you repeat evaluation 19 times so that the held-out topology (1 out of 19) is swept across all available topologies? This will help us understand if RVCO is particularly easy (or difficult) to generalise for.", "limitations": "No. This reviewer suggests considering the following additional limitations: \n- The topologies are characterized @30GHz, but this is not sufficient. The topology choice can vary massively depending on the frequency and therefore a design at 2.5GHz is likely to require a different topology, respect to a design at 30GHz\n- The analysis of the parasitics is approximate. The authors admit that the next step is the addition of EM modelling to improve accuracy of the parasitic. Simulating a 30GHz RF block without an adequate EM model of the interconnects is unreliable, in this reviewer’s opinion a waste of time. I am also unclear on how the accuracy is calculated. Does it compare the results of the model vs. inaccurate non-EM extracted Spectre sims? If so, the correspondence with real silicon results is likely to be rather weak\n- For high-power devices (especially PAs), electromigration must be considered. Especially in advanced nodes, this often drives the transistors and interconnect sizing. Ignoring this can lead to underestimation of the parasitics.", "rating": 5, "confidence": 3, "soundness": null, "presentation": null, "contribution": null, "strengths": "", "weaknesses": "", "quality": 3, "clarity": 3, "significance": 3, "originality": 3, "strengths_and_weaknesses": "### Strengths:\n- Advancing the state-of-the-art of automated analogue circuit design is important and timely\n- Releasing a dataset to support further ML-based analogue design research is useful\n- Appendices A to E do a good job at supplementing the core treatment for better understanding in this specialised field of research \n### Weaknesses:\n- From an analogue/RF design standpoint, the work lacks in detail, especially when it presents the results achieved by the Circuit Designer\n- In the Evaluation section, the authors present the results of 9500 test instances (nearly 80% success rate and 17.7% relative error); however, these metrics are highly dependent on the circuit specifications fed into the algorithm. This is a key limitation, as the paper doesn’t explore how performance varies with more challenging or non-standard specs.\n- Appendix F.2 touches on the limitations of the work, but further discussion of limitations needs to be added. See below.", "was_revised": true, "final_justification": "I have read the authors rebuttal and fellow reviewers' comments. Limitations notwithstanding, I believe this work is a solid accept as it advances SOTA in automated analogue design and is likely to seed and inspire further work. The authors are encouraged to consider points raised during the review process in their final manuscript.", "rebuttal": "We sincerely thank the reviewer for their thoughtful evaluation and constructive feedback. We appreciate the recognition of FALCON's contributions and the valuable suggestions that will help strengthen the clarity and impact of our work. Below, we address each of the reviewer’s comments in detail.\n\n**Weaknesses:**\n1. We sincerely thank the reviewer for raising this important point. Given the machine learning focus of the conference, we prioritized ML-related content in the main paper and limited the inclusion of detailed circuit/layout analysis. However, we agree that presenting results from an analog/RF design standpoint is valuable for broader impact. In the final version, we will enrich the discussion with additional circuit-specific interpretations, such as design insights and representative success cases, and would be grateful to incorporate further suggestions from the reviewer.\n2. We thank the reviewer for highlighting this important limitation. Based on this feedback, we have incorporated a fixed bounding mechanism for each circuit type to prevent users from providing illogical or physically infeasible performance targets. While this issue does not arise in our current evaluation, since all performance targets are derived from expert-designed circuits in our dataset, we believe this additional safeguard will enhance the robustness of FALCON in broader applications and for non-expert users.\n\nTo clarify how our system handles target specifications: when a feasible and meaningful performance vector is provided, FALCON uses its learned prior from the 1M-circuit dataset to infer the best corresponding parameters. Naturally, the broader and more diverse the training data, the more generalizable the model becomes. One of the strengths of our framework is its flexibility; FALCON can be retrained or fine-tuned on any analog circuit dataset, enabling the community to extend its capabilities to new specification ranges.\n\n3. We thank the reviewer for pointing this out. We will incorporate the additional limitations the reviewer raised into our existing Limitations section and, if the paper is accepted, will move this section to the extra page of the main paper to ensure better visibility.\n\n**Questions:**\n1. We appreciate the reviewer’s comment regarding terminology. We chose the term “reasoning” to emphasize that the optimization process leverages the differentiable forward model to iteratively refine parameters in a manner akin to how a designer reasons about circuit behavior. However, we understand that this may be unconventional in the context of optimization, and we are open to revising the phrasing to more standard terms such as “gradient-based optimization” if preferred.\n2. We thank the reviewer for this important suggestion. Given the number of topologies and available data points, we conducted an ablation study prior to submission on both the number of layers and the hidden size of the MLP. Although the results were largely similar, with all configurations achieving over 99% total accuracy on the test set, we selected the best-performing and most lightweight configuration to avoid overfitting. We will include the details in the appendix.\n3. We appreciate the reviewer’s thoughtful observation on t-SNE visualization. The pastel purple cluster (corresponding to topology 9) indeed exhibits a filament-like or strand structure in the t-SNE embedding. Our interpretation is that this topology supports a broader range of performance behaviors, likely due to its architectural complexity or greater configurational diversity in the dataset. This diversity leads to more dispersed feature embeddings, resulting in distinct strand-like subgroups rather than a compact cluster.\n\nThis structure may also suggest that the representation space for topology 9 is more sensitive to parameter variations, which causes the learned embeddings to separate more along performance-driven dimensions. We will include this analysis in the final version of the paper to better illustrate how topology complexity manifests in the feature space.\n\n4. We thank the reviewer for this thoughtful suggestion. To clarify, the evaluation results presented in the main paper are based on a test split that includes all 19 topologies. The held-out evaluation, in which the RVCO topology is excluded from training and only used during fine-tuning and testing, is provided in detail in the supplementary material.\n\nRegarding our choice of RVCO as the held-out topology, we aimed to select a complex and representative topology for a fair evaluation. Among the circuit families, PAs and VCOs are particularly challenging due to their structural complexity and intricate performance relationships [1]. Within this group, we excluded topologies that were either too simplistic (e.g., ColVCO, CCVCO) or too structurally unique (e.g., DPA, which is the only topology involving transformer structures modeled as mutually coupled inductors). RVCO offered a balanced choice, complex but not uniquely structured, making it a strong candidate for assessing generalization. In addition, RVCOs are widely used for power generation at mm-wave and THz frequencies [2], further supporting their relevance as a held-out topology.\n\nRepeating this held-out evaluation for all 19 topologies would require training 19 new foundation models, which is computationally expensive (approximately one week per model). However, we agree that understanding generalization across different complexity levels is valuable, and we will add a few additional held-out experiments on diverse topology types to provide further insight.\n\n**Limitations:**\n - We thank the reviewer for this thoughtful comment. We fully agree that the choice of circuit topology is frequency-dependent and that a topology suitable at 30 GHz may not be appropriate at lower frequencies such as 2.5 GHz. As the reviewer insightfully points out, RF circuits designed for different frequency bands often require distinct sizing strategies, layout considerations, and even architectural choices. However, we would like to mention that lumped components, such as inductors and MOM/MIM capacitors, can still be used at frequencies above 30 GHz if enough caution is taken regarding their self-resonance, quality factor, and parasitics [3].  \n\nMoreover, while our current version focuses on 30 GHz circuits, we believe the general pipeline can be extended to broader frequency ranges. In fact, the overall schematic structure of many analog/RF blocks (e.g., voltage amplifiers) remains invariant over moderate frequency shifts, with only the component values or device sizing needing adjustment. To this end, the frequency can be integrated as an input (or target) into the pipeline, enabling future research to handle frequency-aware design, provided sufficient training data is available. We hope that future community efforts can support expanding this dataset across wider operating conditions. We appreciate the reviewer for highlighting this important aspect, and we will explicitly include the fixed-frequency setting as a limitation and discuss how FALCON can be extended to broader frequency ranges in future research.\n\n- We thank the reviewer for this important point. Indeed, the current layout stage uses an analytical parasitic model, which is an approximation. We fully agree that incorporating detailed EM modeling is a necessary next step, particularly for high-frequency designs where interconnect parasitics can have a significant impact. Enhancing layout realism with EM-aware modeling is an active direction we are pursuing.\n\nAt present, the error reported in our results reflects validation at the schematic level using Cadence Spectre simulations. In these simulations, transistor models are already post-layout PDK models, while passive components (such as inductors and capacitors) are based on empirical models provided by the foundry PDK. While this approach does not fully capture parasitics introduced by custom layout or interconnect geometry, our past experience comparing simulation to silicon measurements suggests that this setup remains reasonably accurate up to 30 GHz. Nonetheless, we recognize the reviewer’s concern that schematic-level validation without EM extraction may limit real-world fidelity at higher frequencies, and we appreciate the opportunity to highlight this as an important limitation and motivation for future work.\n\n- We thank the reviewer for raising this important point. We fully agree that electromigration is a critical reliability concern, particularly for high-power devices such as power amplifiers. In our current implementation, we adhered to a maximum current density of 24 mA/µm width for thick RF metals, following the guidelines in the 45 nm CMOS PDK. This is comfortably below the PDK-specified limit of 33 mA/µm width. These constraints were enforced by the trace width limits incorporated into our layout generator. In addition, minimum-width DRC rules in our flow help prevent the generation of overly thin interconnects, which further mitigates electromigration risk. That said, we acknowledge that these steps represent only a first-order safeguard. A more comprehensive treatment of electromigration is an important direction for future work, especially for very high-power blocks such as PAs.\n\n**References**\n\n[1] Behzad Razavi. *RF microelectronics*, volume 2. Prentice hall New York, 2012.\n\n[2] O. Momeni and E. Afshari, *High Power Terahertz and Millimeter-Wave Oscillator Design: A Systematic Approach*, in IEEE Journal of Solid-State Circuits, vol. 46, no. 3, pp. 583-597, March 2011, doi: 10.1109/JSSC.2011.2104553.\n\n[3] N. Rostomyan, M. Ozen and P. Asbeck, *Comparison of pMOS and nMOS 28 GHz high efficiency linear power amplifiers in 45 nm CMOS SOI*, 2018 IEEE Topical Conference on RF/Microwave Power Amplifiers for Radio and Wireless Applications (PAWR), Anaheim, CA, USA, 2018, pp. 26-28, doi: 10.1109/PAWR.2018.8310058."}, {"review_id": "5Z0Zb5ggo3", "reviewer": "Reviewer_fujS", "summary": "This work introduces a fully automated framework, FALCON, for designing analog circuits with the aid of machine learning. While various ML-based approaches have been proposed for analog circuit design, they typically focus on isolated steps of the design process—such as topology generation, parameter sizing, or schematic-level performance evaluation. \nWith three core components—a lightweight MLP that selects circuit topology, a GNN that maps topology to performance metrics, and gradient-based optimization of the design parameters—FALCON enables full automation of the entire design process. \nFinally, through training and evaluation leveraging a dataset of one million analog mm-wave circuits, FALCON demonstrates strong performance in topology inference, performance prediction, and efficient layout-aware design.", "questions": "- **Q1.** This reviewer does think that one unified framework is a meaningful contribution. However, this reviewer is curious about what differences there would be compared to simply concatenating the known approaches for each step. What would be the benefit of a unified framework over using established methods for each procedure individually? Are there aspects that are qualitatively more challenging when developing a unified framework, as opposed to just applying known approaches?\n\n- **Q2.** Table 1 shows that the classification task for topology selection can be performed with a high score, even using a simple MLP. The scores seem notably high, and this reviewer is curious whether there is any risk of overfitting. To the best of this reviewer's understanding, the evaluation is performed on pre-labeled data. However, the ultimate goal of topology selection is to build a proper circuit that fits a specific purpose, not merely to classify pre-labeled data. What is the justification for assuming that a high classification score will lead to good topology selection for new tasks? Or is there a procedure to adjust the topology in a later step? Also, it seems the classification is limited to 20 topologies. This reviewer is curious whether these 20 topologies are general enough to support the design of a wide range of new circuits.\n\n\n- **Q3.** The focus of the framework suggested in this paper seems to be analog/RF circuits, but this reviewer feels the overall structure is flexible enough to handle circuits for different tasks. For example, there is a line of work on designing electrical circuits to solve convex optimization problems or to design new convex optimization algorithms. However, if we want to consider circuits for different tasks, I believe the concrete components of the framework would need to change. For example, the topology classification based on an analog/RF circuit dataset should be replaced with another component. Still, it seems possible to retain the idea of updating parameters with gradient descent by modifying the loss function. Do you think the structure of your framework can be adapted to design circuits for different tasks, with appropriate replacements of the components? Or do you think the required changes would be almost equivalent to developing an entirely new framework? Since this question may be outside the scope of your research, the reviewer would appreciate any high-level thoughts the authors are willing to share, if any.", "limitations": "Yes.", "rating": 5, "confidence": 1, "soundness": null, "presentation": null, "contribution": null, "strengths": "", "weaknesses": "", "quality": 4, "clarity": 4, "significance": 3, "originality": 3, "strengths_and_weaknesses": "**Strengths**\n\n- FALCON is an end-to-end, scalable and modular ML framework for designing analog and RF circuits. \nUnlike other prior works, FALCON provides full automation on the entire process. \n\n- To the best of the reviewer's understanding, this paper  utilizes a dataset constructed by the authors themselves, which in itself is a commendable contribution.\n\n- The paper is clearly written and well organized, which makes the high-level idea easy to understand. This clarity is a notable strength of the paper.\n\n\n**Weaknesses**\n\n- This reviewer has a few questions and minor concerns but couldn’t find any significant weaknesses.", "was_revised": true, "final_justification": "Based on the reasons stated in the Strengths section and after reading the additional discussions during the rebuttal period, I believe this paper deserves to be published in NeurIPS.", "rebuttal": "We sincerely thank the reviewer for their thoughtful and constructive feedback. We appreciate the encouraging assessment of our work and are pleased that the overall structure and contributions of our framework were well received. Below, we address the reviewer’s insightful questions in detail.\n\n**Questions:**\n\n1. We thank the reviewer for this thoughtful and important question. While each individual component in our pipeline (topology selection, performance prediction, and parameter inference) can be implemented using isolated methods, FALCON’s unified design offers several unique advantages that go well beyond simple concatenation:\n\n- **Performance-Driven Topology Selection:** To the best of our knowledge, FALCON is the first framework to treat topology selection as a supervised, performance-driven task. Prior works on topology generation or selection focus on structural validity or schematic feasibility, without explicitly optimizing for target performance specifications. This makes them incompatible with an end-to-end design process and difficult to meaningfully integrate into a circuit design pipeline like ours.\n\n- **Layout-Aware Parameter Inference:** FALCON integrates layout awareness directly into the parameter inference stage via a differentiable layout-based loss. In contrast, previous works often treat layout optimization as a disjoint post-processing step, which restricts the achievable design space by fixing parameters beforehand. Our unified approach allows layout constraints to actively shape parameter optimization, improving both feasibility and area efficiency.\n\n- **Generalizable Forward Model:** Unlike prior methods that train separate models per topology, our GNN-based forward model is trained across a diverse set of 19 topologies using a shared representation. This enables *zero-shot inference on unseen topologies (e.g., RVCO in our evaluation), a capability not supported by existing models.* It also supports a wide variety of analog circuit elements, including inductors, capacitors, resistors, pmos/nmos, current/voltage sources, baluns, and ports, making it suitable for nearly all analog circuit blocks.\n\n- **Scalability via Large-Scale Dataset:** Our framework is trained on *an unprecedented dataset of 1 million Cadence-simulated circuits*, which significantly enhances its generalization and robustness. This scale of data *has not been seen in prior works* and allows us to cover a broad spectrum of performance behaviors and circuit topologies.\n\n- **Flexible Optimization Interface:** FALCON’s parameter inference stage is designed to support arbitrary loss functions without requiring retraining. As suggested by other reviewers, we were able to easily implement support for performance intervals, weighted losses, and other designer-specified constraints in less than 30 lines of code. This flexibility is crucial for real-world use and difficult to achieve with rigid standalone models.\n\n- **Seamless Integration and Modularity:** All stages in FALCON share a consistent circuit representation and interface, enabling seamless integration without the need for conversion logic or compatibility hacks. Each module directly consumes the output of the previous stage, ensuring smooth data flow and facilitating end-to-end optimization.\n\n- **Qualitative Challenges in Unified Design:** Designing a pipeline that remains *differentiable, interpretable, and modular across all stages*—while scaling to unseen topologies—requires careful engineering of graph encodings, performance masking, normalization, and objective formulation. These challenges are often overlooked in isolated approaches but are critical in building a fully unified system.\n\nWe believe these qualitative and technical advantages distinguish FALCON from a mere aggregation of prior techniques and demonstrate the value of a principled, end-to-end design framework.\n\n2. We thank the reviewer for this thoughtful question. Below, we address each aspect in turn:\n\n**Risk of Overfitting:** ```Table 1 shows that the classification task for topology selection can be performed with a high score, even using a simple MLP. The scores seem notably high, and this reviewer is curious whether there is any risk of overfitting.```\n\nThe high classification accuracy is a consequence of the fact that many circuit topologies exhibit distinct performance behaviors. As shown in the t-SNE visualization (Figure 3(a)), the performance specifications form well-separated clusters across topologies, making the classification problem naturally separable. To assess potential overfitting, we performed an ablation study on the number of MLP layers and hidden sizes, which will be included in the appendix. The 5-layer configuration was selected to balance performance and simplicity, and to avoid overfitting. We also emphasize that the reported results are based on a fully held-out test set, separate from training and validation data.\n\n**Justification for High Accuracy and Post-Selection Optimization:** ```To the best of this reviewer's understanding, the evaluation is performed on pre-labeled data. However, the ultimate goal of topology selection is to build a proper circuit that fits a specific purpose, not merely to classify pre-labeled data. What is the justification for assuming that a high classification score will lead to good topology selection for new tasks? Or is there a procedure to adjust the topology in a later step?```\n\nEach sample in our dataset is labeled with its most suitable topology among 20 candidates, selected based on simulation results from Cadence. Thus, the MLP learns a performance-driven mapping, rather than arbitrary classification. While the topology selection step is discrete, our Stage 3 parameter inference module provides continuous fine-tuning of the design by optimizing component values while preserving connectivity. That is, the structure of the chosen topology is retained, and gradient-based parameter refinement ensures the final design aligns with the target performance. We agree that developing a generative model capable of synthesizing new topologies directly from specs is an exciting future direction.\n\n**Scope of the 20 Topologies:** ```Also, it seems the classification is limited to 20 topologies. This reviewer is curious whether these 20 topologies are general enough to support the design of a wide range of new circuits.```\n\nThe 20 topologies span five major analog circuit families—VAs, VCOs, mixers, LNAs, and PAs—and include structural variants to capture diverse performance profiles. While no finite set can cover all possible circuits, this collection includes the most canonical analog blocks. We also highlight that our framework is *modular and extensible*: users can add new topologies and retrain the model as needed. Expanding the training dataset will only enhance the framework’s generalizability, and we view this as an important next step for broader adoption.\n\n3. We thank the reviewer for this insightful question. We agree that the structure of our framework is conceptually broad and adaptable. If the target application shifts from analog/RF design to a fundamentally different domain, such as circuits designed to solve convex optimization problems, some components of FALCON would indeed need to be modified, but *not redesigned from scratch*.\n\n- **Topology Selection (Stage 1):** Our current MLP classifier is trained to map performance specs to one of 20 pre-defined analog/RF topologies. For a different task, such as designing circuits for optimization solvers, this module would likely need to be replaced with a different selector or a generator tailored to the new family of topologies. That said, the concept of learning a mapping from task specifications to suitable structures still applies, and this stage can be retrained accordingly.\n\n- **Performance Prediction (Stage 2):** This stage is inherently general. Given a new dataset of circuit graphs and their corresponding task-specific performance metrics, our GNN model can be retrained to model the new behavior. The architecture supports arbitrary topologies, components, and performance dimensions/types, making it a reusable backbone.\n\n- **Parameter Inference (Stage 3):** This component is fully adaptable to new domains. The optimization loop is guided by a user-defined loss function, and no retraining is required. For new tasks, one can define a loss appropriate to the desired circuit behavior (e.g., a residual from the solution to a convex problem), and the optimization will adjust parameters accordingly.\n\nIn summary, we believe that FALCON's overall structure is flexible and can be adapted to other circuit tasks. The level of modification needed is moderate: the core architecture and methodology remain applicable, but retraining or replacing task-specific components is required. We appreciate the reviewer raising this broader applicability perspective."}, {"review_id": "2UToUefvsw", "reviewer": "Reviewer_Ae6i", "summary": "The paper proposes a unified framework for synthesis of Analog designs. It is aimed at addressing the inverse problem that is given a target specification, design a circuit that meets the spec. The approach involves three steps: a) Topology selection: For a given target performance, choose an optimal topology amongst a fixed set of 20 topologies using a trained MLP classifier b) Performance prediction: For a given topology and parameters, predict the circuit performance using a learned GNN based forward model. c) Parameter inference: Given the target spec and topology, use gradient descent over the learned forward model to find the optimal parameters that meet the requirement.", "questions": "( I am willing to re-consider scores if some of the following are addressed, especially comparison with prior art)\n\n\n1. It would be helpful if the method could handle specification ranges instead of fixed targets, since that’s how design specs are usually defined in practice.\n2. Allowing designers to indicate which specs matter more—or where trade-offs are acceptable—could make the tool more usable in real design workflows. One way to achieve this would be to use weighted inputs\n3. The paper would benefit immensely from comparison with existing work. While no complete framework exists for direct comparison, each component (topology selection, performance prediction, parameter inference) should be compared against relevant existing methods referenced in the supplementary material (Table 3).\n4.  The paper would benefit from ablation studies on layout cost to access its impact, multi-start to evaluate sensitivity local minima, and a study on parameter initialization to understand its effect on design quality.\n5.  In addition to mean error statistics, it would also be interesting to see the maximum error stats for all three steps.\n\n*Minor:*\n1. Confusion matrix in Fig.3(b) is not complete. Can be added to supplementary material.                                  \t   \t\n2. It would be good to include the discussion on limitations in practical considerations/generalization of this approach in the main paper rather than supplementary.", "limitations": "Yes", "rating": 4, "confidence": 4, "soundness": null, "presentation": null, "contribution": null, "strengths": "", "weaknesses": "", "quality": 3, "clarity": 4, "significance": 3, "originality": 3, "strengths_and_weaknesses": "**Strengths:**  \tThe paper is well-structured and clearly written. It addresses the challenging problem of automating Analog design from specifications. The approach combines topology selection with parameter inference while maintaining structural fidelity. The inclusion of early layout-aware optimization adds value.\n\n**Weakness:**      The paper lacks comparison with existing ML/non-ML based techniques, making it difficult to assess relative performance, efficiency and generalizability against prior approaches.  \n\nThe method uses fixed specification targets and a limited set of topologies, which reduces flexibility and scalability. It is also unclear how practical the approach would be for experienced analog designer, given the lack of support for guiding trade-offs or incorporating domain expertise.", "was_revised": true, "final_justification": "This work is a step forward towards using ML automated analog synthesis, a difficult and relatively unexplored problem. After reconsidering the authors rebutal and my fellow reviewers comments, I have decided to raise the score to 4.", "rebuttal": "We thank the reviewer for the constructive feedback. We greatly appreciate the recognition of our contributions and address the concerns below.\n\n**Weaknesses:**\n1. We thank the reviewer for emphasizing the importance of comparison to prior work. Building on Table 3, we provide additional clarification and results to address the reviewer’s concern in more depth:\n- **Topology Selection:** Although prior work includes topology generation/selection, their problem formulation differs fundamentally from ours. These methods aim to construct valid schematics, often without explicit consideration of specifications. In contrast, FALCON frames topology selection as a performance-driven classification task over a fixed library of mm-wave circuits. Moreover, none of the prior work supports the RF frequency, which significantly impacts circuit behavior and design constraints. Therefore, a direct performance comparison is not feasible.\n- **Performance Prediction:** Among existing approaches, Deep-GEN is the only publicly available method. However, their model excludes key components like inductors and does not support AC performance metrics such as bandwidth, both of which are essential in our mm-wave designs. Additionally, similar to AutoCkt, the released code is incomplete and cannot be used to produce results on our dataset. Thus, a quantitative comparison was unfortunately not feasible.\n- **Parameter Inference:** We identified AICircuit and Krylov et al. as the directly comparable baselines. While both works explore similar modeling strategies, AICircuit offers five distinct models and aligns more closely with our goal in terms of Cadence simulation and circuit scope. To provide a fair comparison, we evaluated AICircuit on our held-out topology (RVCO) and compared it to the FALCON fine-tuned model on RVCO. There are several key distinctions between FALCON and AICircuit:\n   - FALCON integrates a layout loss during parameter inference, enabling practical design refinement. In contrast, AICircuit does not incorporate layout modeling during inference. \n   - FALCON uses a single model trained across 19 topologies, enabling generalization and zero-shot inference on new topologies. AICircuit, by design, requires training a separate model for each topology, since its predictors are tied to topology-specific feature spaces.\n   - FALCON's inference quality is governed by a user-defined error threshold, which makes accuracy tunable. In contrast, AICircuit performs direct regression with no adjustable convergence mechanism.\n\nThe relative error results on RVCO are summarized below:\n|Method | Rel Err (%) |\n|-|:-:|\nAICircuit-kNN|4.46|\nAICircuit-SVR|4.09|\nAICircuit-RF|3.91|\nAICircuit-Transformer |3.56|\nAICircuit-MLP|2.42|\nFALCON|2.87|\n\nWhile AICircuit-MLP achieves slightly lower error under these settings, we note that FALCON enables generalization to unseen topologies, layout optimization, and tunable inference precision. Indeed, lowering our termination threshold would yield improved relative error below MLP, but we maintained consistency with the main paper settings for transparency. We will include this comparative study in the revised version of the paper.\n\nWe hope these clarifications and additional evaluations address the reviewer’s concerns. If the reviewer has specific methods they would like us to include, we are happy to consider those as well.\n\n2. We thank the reviewer for highlighting this important point. We address the limitations regarding fixed targets and trade-offs in our responses to Q1 and Q2. Regarding the limited topology set, FALCON currently operates on a library of expert-designed topologies to ensure physical validity, layout feasibility, and manufacturability. We agree that integrating generative topology methods represents a promising direction for future work.\n\n**Questions:**\n1. We thank the reviewer for this valuable suggestion. We agree that extending FALCON to support interval-based reasoning is an important direction. Our framework can already be adapted to handle ranges in the key stages that require them:\n - **Topology Selection:** Although our MLP classifier is trained on fixed targets, it can still support interval-based queries. A simple approach is to input the midpoint of each performance interval or to sweep across the valid range and select the topology that is most frequently predicted across different samples. This preserves the benefits of supervised training while adapting to flexible specs.\n- **Performance Prediction:** This stage maps a given topology and parameter vector to a predicted performance vector. It does not need to process targets directly. Instead, it acts as a surrogate model used in Stage 3 and is independent of how the final loss is defined. Therefore, no changes are needed to this component.\n- **Parameter Inference:** In this stage, the GNN is used as a predictor model to redefine the optimization loss to accommodate performance intervals. We have implemented an alternative loss that supports input spec intervals, where each masked performance may have lower and/or upper bounds (finite or infinite). The loss penalizes deviations from these bounds as follows:\n\n$$L_{\\text{interval}} = \\sum_{i \\in \\text{masked}} \n\\begin{cases}\n\\max(0, \\hat{y}_i - y^{\\text{upper}}_i) & \\text{if upper bound} \\\\\\\\\n\\max(0, y^{\\text{lower}}_i - \\hat{y}_i) & \\text{if lower bound}\n\\end{cases}$$ \n\nThis masked interval loss replaces the masked MSE used and will be included in our final code release. While our current evaluation adopts fixed targets for consistency, we acknowledge that real-world use cases are often goal-dependent. We welcome the reviewer’s feedback on how best to evaluate interval-constrained optimization and would be happy to include additional results in the paper if desired.\n2. We appreciate the reviewer’s suggestion. We agree that enabling designers to express trade-offs is valuable in practical design workflows.\n- **Topology Selection:** Since this stage uses an MLP mapping fixed performance vectors to topology classes, incorporating weights directly into its input space is nontrivial. Exploring approaches to enable trade-off-aware classification remains an open research direction, and we welcome further ideas from the community.\n- **Performance Prediction:** This model does not directly interact with specification weights.\n- **Parameter Inference:** We have implemented a weighted loss function for this stage. Users can now provide per-specification weights, and the loss function scales each performance error accordingly during optimization. This allows the reasoning process to prioritize certain metrics over others, supporting designer-driven trade-offs. The type of loss, masked MSE, interval, or weighted, can now be selected via an input argument to the script. We will release this implementation in the supplementary material. While evaluating performance under arbitrary user-defined weights is inherently application-dependent, we welcome any suggestions the reviewer may have regarding evaluation protocols or result presentation.\n3. We thank the reviewer for raising this important point. As discussed in the weakness section, while direct comparisons are not always possible due to differences in problem formulation, tool availability, or supported circuit types, we have provided clarification on relevant related work and included new results where feasible (comparing our stage 3 to AICircuit).\n4. We thank the reviewer for these excellent suggestions. We have implemented several experiments to address these points:\n- **Layout Cost:** To isolate the contribution of layout-aware optimization, we perform an ablation study where the layout loss weight λ is set to zero. We report the resulting success rate and mean rel error. Since our optimization loop includes hard constraints on layout feasibility (e.g., area exceeding a threshold causes the candidate to be rejected), reporting fine-grained area differences is less informative: minor improvements do not affect success or feasibility. Nevertheless, we remain open to suggestions on additional layout-related metrics the reviewer would like to see.\n- **Initialization:** We will include a study on the effect of initialization noise variance and type. Since our inference process uses a fixed optimization threshold to determine success, increasing variance affects convergence speed, rather than overall success rate or rel error. Given that the inference completes in under 1sec/sample, even with additional steps, this added cost is negligible in practice. We will report detailed results for different noise types and variances in the appendix.\nWe hope these additions address the reviewer’s concerns and are happy to incorporate further evaluations based on reviewer feedback.\n5. We thank the reviewer for this helpful suggestion. We will include maximum error statistics for the regression stages in the main paper. For Stage 2, the maximum rel error was 42.4%, and for Stage 3, the maximum rel error was 32.1%. The latter value is influenced by the optimization termination threshold used in our experiments: lower thresholds yield lower maximum errors. Note that Figure 5 shows the 95th percentile errors, as stated in the caption. For topology selection, maximum error is not meaningful; however, the lowest per-class accuracy was 93.9%, corresponding to a maximum misclassification rate of 6.1%.\n\nMinor:\n1. The omitted classes in Fig. 3(b) correspond to those with 100% classification accuracy: no samples from these classes were misclassified, and no other classes were incorrectly classified as them. We will include the full confusion matrix in the appendix.\n2. We acknowledge that placing the Limitations section in the supplementary material may have made it less visible. If the paper gets accepted, we will move this section to the extra page of the main paper and expand it to incorporate the additional limitations raised by the reviewers."}]

Author rebuttal:

Meta-review: This paper presents FALCON, a novel and comprehensive machine learning framework for fully automated, layout-aware analog circuit design, addressing the long-standing challenge of end-to-end specification-to-design synthesis. 

The reviewers generally agree that the paper is well-written, technically sound, and makes a meaningful advance in ML for electronic design automation, with strong empirical results including >99% topology accuracy and sub-second design times. 

While concerns were raised about the reliance on a fixed topology library, the simplicity of the current layout cost model, limited evaluation on non-mm-wave circuits, and initial lack of statistical robustness reporting, the authors provided thorough rebuttals with additional experiments and clarifications, addressing most issues satisfactorily. 

Finally, all reviewers have provided borderline accept or accept ratings. This is a clear acceptance.
Decision: Accept (poster)