High-Performance Arithmetic Circuit Optimization via Differentiable Architecture Search
Authors: Xilin Xia
Jie Wang
Wanbo Zhang
Zhihai Wang
Mingxuan Yuan
Jianye HAO
Feng Wu
Venue: NeurIPS 2025 spotlight ()
Keywords: Arithmetic Circuit Optimization
AI for Electronic Design Automation
Differentiable Architecture Search
Primary area: applications

Abstract: Arithmetic circuit optimization remains a fundamental challenge in modern integrated circuit design. Recent advances have cast this problem within the Learning to Optimize (L2O) paradigm, where intelligent agents autonomously explore high-performance design spaces with encouraging results. However, existing approaches predominantly target coarse-grained architectural configurations, while the crucial interconnect optimization stage is often relegated to oversimplified proxy models or a heuristic approach. This disconnect undermines design quality, leading to suboptimal solutions in the circuit topology search space. To bridge this gap, we present **Arith-DAS**, a **D**ifferentiable **A**rchitecture **S**earch framework for **Arith**metic circuits. To the best of our knowledge, **Arith-DAS** is the first to formulate interconnect optimization within arithmetic circuits as a differentiable edge prediction problem over a multi-relational directed acyclic graph, enabling fine-grained, proxy-free optimization at the interconnection level. We evaluate **Arith-DAS** on a suite of representative arithmetic circuits, including multipliers and multiply-accumulate units. Experiments show substantial improvements over state-of-the-art L2O and conventional methods, achieving up to $\textbf{27.05}$% gain in hypervolume of area-delay Pareto front, a standard metric for evaluating multi-objective optimization performance. Moreover, integrating our optimized arithmetic units into large-scale AI accelerators yields up to $\textbf{6.59}$% delay reduction, demonstrating both scalability and real-world applicability.

High-Performance Arithmetic Circuit Optimization via Differentiable Architecture Search
Xilin Xia! Jie Wang', i Wanbo Zhang'
Zhihai Wang'
Mingxuan Yuan? Jianye Hao 2-3
Feng Wu!
MoE Key Laboratory of Brain-inspired Intelligent Perception and Cognition,
University of Science and Technology of China Noahs Ark Lab, Huawei Technologies
3 College of Intelligence and Computing, Tianjin University
Abstract
Arithmetic circuit optimization remains a fundamental challenge in modern inte- grated circuit design. Recent advances have cast this problem within the Learn- ing to Optimize (L20) paradigm, where intelligent agents autonomously explore pigh-performance design spaces with encouraging results. However, existing ap- proaches predominantly target coarse-gae saarse--rained architectural configurations, while the crucial interconnect optimization stage is often relegated oversimplified proxy models or heuristic approach. This disconnect undermines design quality, leading suboptimal solutions in the circuit topology search space. To bridge this gap, we present ARITH-DAS
Differentiable Architecture Search framework for Arithmetic circuits. To the best of our knowledge, ARITH-DAS is the first to formulate interconnect optimization within arithmetic circuits as differentiable edge prediction problem over a multi-relational directed acyclic graph, enabling fine-grained, proxy-free optimization at the interconnection level. We evaluate ARITH-DAS on a suite of representative arithmetic circuits, including multipli- ers and over statc-of-the-an L20 and conventional methods, achieving up to 27.05 % gain in hypervolume of area-delay Pareto frontiers, standard metrie for evaluating multi-objective optimization performance. Moreover, integrating our optimized arithmetic units into large-scale Al accelerators yields up to 6.59% delay reduc- tion, demonstrating both scalability and real-world applicability.
units. Experiments show substantial improvements
1 Introduction
Arithmetic circuits, including multipliers and multilyy-ccumuulte units, constitute the computa- tional foundation of modern hardware platforms such as CPUs, GPUs, Al accelerators, and digital signal processors [M-3]. These circuits perform essential arithmetic operations that dominate the computational workload across a broad range of compute-intensive applications [4-6]. In deep neu- ral networks, for example, multiplication operations account for over 99% of total computation [Ø]. As machine learning and high-peeformance computing systems continue to grow in scale and com- plexity, optimizing arithmetic circuits for both latency and area efficiency has become critical challenge for enabling scalable and effective AI hardware systems.
Arithmetic circuit optimization poses a fundamental NP-hard challenge in discrete combinatorial optimization. The discrete design space scales exponentially with the bit width, reaching com- plexity of O(24N²) as detailed in Appendix Bl Recent studies have reformulated arithmetic circuit
"This work was done when Xilin was an intern Huawei Noahs Ark Lab. 1 'Correspondence author. Email: <jiewangx wwwp:aangg@@stcedduu..oo The code is available
39th Conference on Neural Information Processing Systems (NcurIPS 2025).

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optimization as a Learning to Optimize (L20) problem [R D- wherein learning- -baed agents are employed explore efficient design strategies for performance improvement. These approaches typically initialize from expert-crafted designs, iteratively refine local structures, and leverage per- formance improvements between successive designs as reward signals to guide the optimization process, achieving promising results.
However, despite the notable successes, existing L20 approaches remain predominantly confined to coarse-grained architectural optimization, which primarily focuses on basic component allocation at each bit position. Fine- sine--rained interconnect routing still governed by heuristic rules that overlook the complex structural constraints of the design space, thereby compromising circuit quality. Recent efforts [ [T] have attempted model the interconnection in the arithmetic circuits through permu- tation matrix generation, leveraging mixed-integer programming (MIP) and differentiable optimiza- tion enhance interconnect assignment. However, these methods are fundamentally constrained by oversimplified proxy formulations, which fail to faithfully reflect complex post-synthesis physical metries. As circuit complexity increases, the misalignment between proxy and actual performance escalates, causing the optimization to converge prematurely to inferior design solutions.
To address these challenges, we present ARITI-DAS a differentiable architecture search frame- work that directly targets the interconnection design space in arithmetic circuits. In contrast to prior work focused on coarse architectural component allocation. ARITH-DAS formulates fine-graud ane-grained interconnection optimization as an edge prediction task over a capturing signal-level structural semantics. It employs multi multi-relational directed acyclic graph, graph neural networks with attention mechanisms to model connection probabilities across relation types, and adopts proxy- free objective aligned with post-synthesis metrics to ensure fidelity. ARITH-DA DAS further integrates with high-level allocation optimizers, enabling unified, multi- uulti-graanularity circuit optimization.
We conduct systematic evaluations on a suite of representative arithmetic circuits, including multipli- (MAC) units. Experimental results show that our method consistently
ers and multiply-accummll achieves Pareto dominance over state-of-the-ard approaches in area and delay, with hypervolume im- provements of up to 27.05%. Furthermore, when integrating the optimized circuits into large-scale AI computing systems, our approach delivers up 6.59% latency reduction compared to the state- of-the-art baseline designs, demonstrating its scalability and practical engineering applicability.
Contributions of this paper summarized follows: (1) We identify key limitations in existing arithmetic circuit optimization approaches and reveal the critical role of the interconnection design space in determining post-synthesis performance. (2) To the best of our knowledge, ARITH-DAS is the first to formulate the fine-grained interconnect synthesis of arithmetic circuits as a differen- tiable architecture search problem. (3) We propose novel differentiable architecture search frame- work tailored for arithmetic circuits, which combines multi-relational graph neural networks with Graphormer-style attention mechanisms. The entire framework is trained in a proxy-free manner, directly aligning with post-synthesis performance metrics. (4) Extensive experimental results across representative circuits demonstrate that our method achieves state-of-the-arr post-synthesis perfor- mance, while maintaining strong applicability to real-world design flows
2 Preliminary: Arithmetic Circuit Optimization
Arithmetic circuits are typically composed of three main components: the Partial Product Gen- erator (PPG), the Compressor Tree (CT), and the Carry Propagate Adder (CPA). As shown in Figure M1, PPG encodes the inputs into a matrix of partial products based on the arithmetic operations, using schemes such AND-gate encoding, Booth encoding, more complicated methods [[2--]] Then the compressor tree reduces this matrix to two rows through parallel compression, and finally the CPA adds them to produce the final output. The compressor tree dominates both area and delay of the entire arithmetic circuit, making it the primary target for arithmetic circuit optimization [G] 7 The optimization of compressor trees typically involves three key steps:
Compressor Allocation This step determines the number and types of compressors used at each
column of the compressor tree. The allocation must satisfy basic constraints such input/output balance and convergence to two or fewer final rows. It forms the architectural backbone of the compression process and directly influences both the area and delay of the overall circuit.
Compressor Stage Assignment Given a valid compressor allocation, the stage assignment step specifies the exccution order of each compressor, subject to data dependency and topological con-
2

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3125 Opecask
Der
(Lags Waro
Viuaa
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Allocation
Compasses
Vinca hodo
Product
San Aill
Calumns
Singrs
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Compressor Tree
Stage
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(3 Curry-PPapaggacc
Component
(3) Compresser Interconacction
Pormuutttion
(a) Multiplier Architecture
(b) Compressor Tree
(c) Graph Representation
Figure 1: An illustration of a 4-bit multiplier with AND-gate based PPG.
Figure 2: Delay distribution of 1000 randomly interconnected 16-bit multipliers using Wallace Tree compression with both AND and Booth partial product encoding PPG.
Figure 3: Comparison of estimated and post- synthesis delays for multipliers ranging from 4- bit 64-bit, using Wallace Tree with both AND and Booth partial product encoding PPG.
straints. This process enforces legal signal propagation through the stages but does not yet define the exact ordering of partial product summation within each column. The resulting assignment determines the temporal alignment of computation without resolving interconnect details.
Compressor Interconnection With allocation and stage assignment fixed, the final step involves establishing the logical interconnection between compressors, determining how outputs are routed to inputs across stages. This step has been largely overlooked in existing learning- leaming-to-optimizz to-optimizee (L20) frameworks, which typically assume simplistic sequential interconnection. Unlike allocation and stage assignment, which operate on regularized representations, interconnect optimization requires reasoning over graph-structured data and exposes a vast and irregular search space, making it both critical and challenging optimize effectively.
Motivation Challenge: Interconnection Optimization
Existing arithmetic circuit optimization frameworks predominantly focus on allocation-level design using regularized structural representations, whereas interconnections between compressors are typ- ically handled through simplistic sequential wiring schemes. However, recent studies reveal that interconnects constitute critical and nontrivial design space [Iα]. [Т]] with considerable impact post-synthesis delay. In essence, existing approaches exhibit three fundamental limitations: (1) the neglect of interconnect-leved optimization: (2) dependence on oversimplified heuristics and proxy de- lay models; (3) the absence of a unified framework for jointly optimizing coarse-graiin paarse-grained allocation and fine-grained interconnect design. We elaborate these limitations in the following discussion.
Design Space of Interconnection The interconnection of compressors plays critical role in determining the critical path the compression tree. We illustrate this often-overlooked design space through randomized experiment. Specifically, we perform random interconnection assign- ments on 16-bit multipliers using both AND-gate and Booth PPG schemes with fixed compressor allocation, and evaluate the post-synthesis delay of these randomly generated designs. The results are compared against the sequential interconnection strategy adopted by the recent statc-of-the- art L20 method MUTE [Z]. We present the post-synthesis delay distribution of the randomly routed designs in Figure Q revealing that with fixed compressor tree allocation, there exists a substantial timing optimization space of up over 10%. Notably, the sequential wiring scheme does not exhibit a clear advantage over these randomized interconnection designs.
Misaligned Proxy Objective Existing interconnect optimization methods leverage mixed-integer programming (MIP) [I0]] or differentiable approaches [[]],, both relying oversimplified proxy
3

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delay models. However, due to the complex and nonlinear nature of post-synthesis delays, which are closely coupled with the technology library and EDA toolchain, such proxy objectives often fail to reflect the true performance characteristics and lead to suboptimal routing solutions. To illustrate this, we conduct randomized interconnect experiments on 4- to 64-bit multipliers with both AND and Booth PPG. For each bit-width, 50 random interconnected designs are evaluated using the proxy delay model in UFO-MAC [[0O] as well as the actual post-synthesis delay. As shown Figure B the discrepancy between proxy and actual delay metric increases with bit-width, underscoring the growing inaceuracy of proxy-driven optimization in large-scale designs.
To address these challenges and fully exploit the vast yet underexplored design space of compressor interconnections, we propose ARITH-DAS a proxy-free differentiable architecture search frame- work based on graph neural networks. ARITH-DA DAS optimizes complex routing by enabling accurate and efficient interconnect prediction aligned with post-synthesis met- rics. It can be seamlessly integrated with any allocation optimization algorithm, forming unified and extensible framework for circuit-level design optimization.
4 Methodology
We begin with an overview of our proposed ARITH-DAS in Section architecture search formulation in Section 7 including detailed multi-relational graph representa- tion in Section ا and differentiable relaxation in Section 1220 Finally, Section H. provides a detailed description of the components of our framework, along with the training procedure aligned with post-synthesis performance metrics.
1 Next, we propose our
4.1 Overview of Our Framework
As illustrated Figure A. our ARITH-DAS framework consists of three principal components. To thoroughly explore the design space of arithmetic circuits, we first construct coarse-grained compressor allocation using an adaptable circuit evolutionary strategy. This initial configuration is then expanded into multi-relational directed acyclic graph (DAG), which defines rich and expressive interconnect search space. A multi-relational graph neural network is employed to encode both topological and semantic relationships among architectural components, while a graph attention mechanism estimates the probabilistic significance of candidate connections. Finally. the entire framework is trained end-to-end via a PPO-inspired algorithm, enabling proxy-free optimization directly guided by post-synthesis performance metrics.
4.2
Architecture Search Formulation for Arithmetic Circuit
4.2.1 Graph Representation for Compressor Tree
Combinational logic circuits can be naturally represented as directed acyelic graphs (DAGs), exhibit- ing structural equivalence between the circuit and its graph-based abstraction. our representation, partial products and compressors are modeled as nodes, and logical dependencies are modeled as directed edges, as illustrated in Figure IKcc., To address the inherent complexity of fine-grained interconnect modeling, we employ principled graph construction strategy, detailed below.
(1) Topology Ordering via Stage Assignment To preserve acyclicity, fundamental constraint of combinational logic, we assign each compressor to specific stage and allow interconnections only between stages of increasing order. This stage-wise ordering induces a valid acyelic circuit topology and establishes explicit dataflow dependencies.
(2) Virtual Nodes for Cross-Stage Connections To address mismatches in input and output port counts that necessitate signal bypassing, we introduce virtual nodes, which serve as auxiliary 1:1 compressor-like entities that propagate signals across stages. This mechanism enforces stage-wise connectivity while preserving topological consistency and simplifying graph construction.
Graph for Asymmetric Input Semanties While addition is logically com- mutative, the compressor input ports are physically asymmetric. To capture this asymmetry, we rep- resent the compressor tree as multi-relational graph [I I8], where each edge type corresponds to a specific input port of the target node. This formulation enables the model to distinguish structurally similar yet semantically distinct connections.
(3)
More formally, we define the compressor tree as multi-relational directed acyelic graph [I%], de- noted by the tuple (V, E, R). Here, V {ei, ...... ... is the set of nodes, each representing circuit

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element. R= {ri, r2... } is the set of relation types, where each E R corresponds to a seman tically distinct input port. The edge set & C V R V consists of typed directed edges, where each edge (wa,7; r; 11) E & indicates that node ii connects to input port of node vj. The graph can also be encoded as three-dimensional binary tensor G E {0, 1 | where Gr..jj if and only if (vi, r, 0;) E E. Following previous works [[3, 77 IT, 20, 21J, we represent the allocation of compressor tree by matrix s E N+TXN, where 7 the number of compressor types and N the input bit width of the compressor tree. Each entry St,n denotes the number of compressors of type t assigned to column n. We denote the set of valid designs by G and the set of valid structures by The detailed design constraints are provided in Appendix C.3 Finally, our goal is to maximize composite objective function:
max R(g) = -1 (g) W2 delay 9EC
where the objective function R: : G + R is the weighted linear combination of post-synthesis area and delay metrics following prior works [BL 7 IS].
4.2.2 Differentiable Reformulation for Discrete Search Space
Problem (I) constitutes large-scale combinatorial optimization challenge, involving highly irreg- ular graph structures and complex design constraints. To address this, we draw inspiration from differentiable architecture search [22-26] which offers scalable and efficient alternative. By relax- ing discrete structural decisions into continuous probability distributions, these methods enable joint optimization over vast design space within single forward pass, thereby significantly enhancing search efficiency and scalability.
Specifically, we replace the hard edge assignments in the compressor tree graph G E G with soft, learablle probability distributions over candidate source nodes. Each potential connection pa- rameterized by real-valued score and passed through a softmax function, yielding continuous relaxation & E [0, 1 [VI, where Gr,i.j denotes the probability of establishing edge from node Uú. conditioned edge type and target node Uj. with normalization E; Gr.i.j = 1 for each (r: pair. This target-centric formulation arises from the structural constraints and multi-relational graph design, which inherently defined from the perspective of the receiving node. By mod- eling connection probabilities in this manner, each input port selects its optimal driver from valid candidates, enabling fine-grained, port-specific connectivity through softmax- -assd selection. This relaxation implicitly defines a distribution π G > [0, 1] over the graph search space, with corre- sponding parameter space 11. Following previous works (22, 23], the objective relaxed to
max EG [R(G)] FEl
[ [R(G)]
max max REB (1(s)
where II, C II denotes the set of graph distributions associated with given allocation This naturally forms a tto-stage optimization framework where we first determine the allocation of the compressor tree, and next we optimize the corresponding interconnection.
4.3 ARITH-DAS: : Differentiable Architecture Search for Arithmetic Circuit
In this section, we present ARITIIDAS. a novel differentiable architecture search framework tailored to arithmetic circuit optimization. By encoding structural information via multi-relational graph neural network and modeling interconnect prediction through graph attention, it enables end- to-end, saadientt-bsedd optimization directly guided by post-synthesis performance metrics.
4.3.1 Adaptable Allocation Search via Circuit Evolution
The compressor allocation s E specifies the number of compressors across columns, shaping the coarse-grained structure and reduction stages of the compression tree. This aspect has been extensively studied [EL D S III. IE, 20], with methods ranging from reinforcement learning to mixed- integer programming for optimizing compressor configurations under fixed encoding schemes.
To ensure simplicity, extensibility, and structural diversity, we adopt the evolution-basee method introduced in [[]]. Specifically, we maintain population of candidate architectures in an elite pool, each representing a compressor allocation matrix across all columns. New candidates are generated through two key mechanisms: (1) local perturbation, where small number of compressors are randomly added, removed, or shifted across columns, and (2) substructure crossover, where two parent architectures exchange subregions of their compressor allocation matrices.
5

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Relation
Graph Probability Policy 2u
Fdge Types
Multi-Reitional
Graph Structure
Topalagy Order
Atlention Scores
Sampling
Relation
(b) Graph Structure
Representation
Update
Relation
Appepake
Sample
Sample
Musation/ Crossover
Rg
R2
Hidden State of Toch Relation
Multi Relational
Cross Relational Aggregation
Synthesis Environment
Allocation Genne
Elte Pool
Message Passing
(a) Circuit Structure Evaluation
(c) Graph Attention Based Edge Prediction
(d) EDA-Aligned Training
Figure 4: Overview of our proposed ARITH-DAS framework.
This evolutionary process promotes exploration of diverse architcctural patterns while preserving high-performing solutions across generations. Crucially, it operates independently of the intercon- nect structure, enabling seamless integration with the differentiable wiring search described in the next stage. Once a compressor allocation configuration sampled, we construct the corresponding multi-relational graph and optimize its interconnects accordingly.
4.3.2 Multi-Relational Graph Attention Based Link Prediction
Multi-Relational Graph Encoder Given a compressor allocation s S, our objective is to de- termine its optimal interconnect configuration. To this end, we leverage multi-relational graph neural network to encode the underlying circuit topology and model the propagation of physical information through the circuit. Each edge type captures distinct semantic relation, such as a spe- cific input port of a compressor, and is processed independently during message passing, enabling the network to learn asymmetric and relation-spece speciifc connection patterns. Concretely, adopt multi-relational message passing scheme. At layer 1, the hidden state of node &ú under relation is updated by:
8. (1). r E R. JEN-())(() VIV v (W
E
1
(3)
where (1) (u, EV (VI(,, E or (u), E E} denotes set of nodes bidirectionally connected n2 under relation r, and of is relation-specifie message function layer augmented with self-loops and reverse edges support comprehensive message flow, while directional seman- ties are embedded node features. To integrate information across all relations, we concatenate the relation-specific representations and apply shared aggregation function 7
h =n (h( i.
The final node embedding h; encodes the structural context of vertex U;. To predict interconnect probabilities, we employ a Graphormer-style attention mechanism [27]. wherein each target node and its candidate source nodes are projected into relation- specific query and key spaces, respectively. Let O {sum, carry) denote the set of output port types. Given target node vy and port pair (o,r) O R, the attention score from candidate source node U; is computed as:
Graph Attention Based Edge Prediction
exp ((W3h,) (TWSS)))(WWh))) M.T
(5)
Evenyi exp (WGh)) (TWgh))(WWhh (Wghx)] MM
where W and W are linear projections specific to the input and output port types, respectively.
The binary mask M E {0, 1} imposes structural constraints by limiting the softmax normal- ization valid source-target-por combinations, as detailed in Appendix Ckp This formulation conforms to the probabilistic semantics of our relaxation: for each target node and input port type, it defines a distribution over valid source nodes. The target node acts as the query and the source node as the key, ensuring consistency between the attention logits and relaxed edge selection probabilities.

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4.3.3 Post-Synthesis Alignment via Proxy-Free PPO-Like Training
Given fixed compressor allocation s, the attention scores ai define a structured distribution over interconnect candidates. A valid discrete realization is obtained via sequential sampling along a legal topological order, with the legality mask M,j dynamically updated to ensure acyclicity, stage consistency, and port compatibilityy This process yields deterministic graph sample 9 ~ mo( s), where the probability is factorized as To ( s) Ir. Gr,i. "ijj
0." fully parameterized by the
learnable attention logits a.j. To optimize the interconnect structure with respect to post-synthesis performance metrics, we employ a proxy-free, PPO-like training paradigm [28]. Specifically, we treat wy stochastic policy over the graph space and maximize the expected objective defined by post-synthesis metrics Rt:
T9 8) 77(9 R(G)
max J( max E B [[(]]] max (l
(6)
where Ty is a fixed reference policy used for importance sampling. To enforce conservative updates and prevent large deviations from the reference policy, optimize the clipped surrogate objective:
M
j(0) 8)
1 M
Σ m=1
min (pm (Gmm) clip(pm. 1 - e, +.1+
where Pm. To 10 (s) (7( is the likelihood ratio between the current and reference policies, and Gm To(- 8) are i..dd sampled graphs. The hyperparameter controls the trust region for updates. Additionally, we introduce regularization term to promote structural discreteness and enforce port- level sparsity constraints of the output ports [[ The overall loss is defined as:
[( s) =
Σ
o.r Oi (1 (1-021)²
Σ
1
E
Mess OrT dij
JEE, FER
sE[|v]], oeo
JELIVII,
Diseretization penalty
Output port exclusivity constraint
(8)
The first term penalizes probabilities that lie in the ambiguous region (0, 1), thus promoting discrete- like selection. The second term enforces that each output port selects exactly one target input (i.c., normalized to 1). Finally, the complete training objective combines the PPO-style reward maximiza- tion with the regularization:
max C(0) Eg-S [5( s) (L $)
where 77 > O controls the trade-off between reward fidelity and structural regularity. A theorem- guided discussion is detailed in Appendix C.3.6.
5
Experiments
We begin by describing the experimental setup, baseline methods, and evaluation metrics in Sec- tion 5 The experiments are designed to pursue three primary objectives: (1) Evaluate the effec- tiveness of ARITH-DAS in optimizing computing multipliers and MAC units across broad range of input bit-widths (Section D.2);; (2) Assess the generalization ability of ARITH-DAS -optimized multipliers when scaled to large macro designs representative of real-world AI accelerators (Sec- tion B0; (3) Perform ablation studies to quantify the contributions of individual components within ARITH-DAS DAS and elucidate the rationale behind its design (Section 5.4))
5.1 Experiment Setup
Experimental Setup Our framework leverages OpenROAD | for physical implementation. Logic synthesis is performed using Yosys [G0]] with the Nangate45 technology library [EI], while static timing analysis (STA) is conducted through OpenSTA [29]] Functional verification employs Verilator [52] for cycle-accurate simulation. The machine learning pipeline is implemented in Py-
Torch [B and PyTorch Geometric [[_], optimized via the Adam algorithm [35]] We evaluate our methodology across eight distinct multiplier architectures, encompassing 8-bit, 16-bit, 32-bit, and 64-bit implementations employing both AND gate-based and Booth encoding- techniques.
More experiment configurations provided in Appendix C
7

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MUTE
ArthTreeRL
UPO-MAC
DOMAC
GOME
Wallace
Figure 6: Pareto frontiers of ARITI-DAS and baselines on eight multiplier design tasks.
Comparative Baselines We evaluate our methodology against six representative approaches
spanning classical heuristic designs to contemporary leaming-to-optimize (L.20) paradigms: (1)
Wallace
GGG
A foundational heuristic compression technique; (2) UFO-MAC [0T0] and (3)
GOMIL
2
A solution framework based on integer programming: (4) DOMAC []]: A differ-
entiable interconnection optimization framework; (5) ArithTreeRL [Р]] A leading deep reinforce-
ment learning (RL) architecture; (6) MUTE [[]] The current state-of-the-ard hybrid RL-Evolutionary
framework. Extended comparative analyses including implementation specifics and hyperparameter
configurations are provided in Appendix C4
Evaluation Metrics Arithmetic circuit optimization constitutes a canonical multi-objective opti- mization problem. We employ two established evaluation protocols from multi-objective optimiza- tion theory: (1) Pareto Frontier Analysis: Following established methodologies [C), Z-II, [5], we simulate diverse design preferences through parametric target delay configurations. This enables comprehensive synthesis of corresponding solutions and visualization of their Pareto frontiers [57]] (2) Hypervolume (HV) Metric: We conduct comparative analysis of solution quality through hy- pervolume measurements [[ across different Pareto frontiers, quantifying their multi-objective characteristics. More details are provided in Appendix C.3.8.
5.2 Main Evaluation
We highlight the superiority of ARITH-DAS through a comparative analysis with six competitive baselines eight multiplier design problems across a wide range of input sizes. The results in Figure R demonstrate that multipliers optimized by ARITII- DAS consistently and significantly outperform de-
Delay Comparison
Uobay (55)
signs optimized by all baselines across all eight mul- tiplier design tasks. Moreover, we present the hy- pervolume (HV) of the Pareto points discovered by ARITH-DAS in Table II The results demonstrate that ARITH-DAS achieves substantial improve- ment over the previous SOTA, improving the hy- pervolume by up to 27.05 27.05%. Overall, these results demonstrate the strong ability of ARITI-DAS to op- timize multipliers, leading to significant reductions
Ja Jye
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Figure 5: Delay of practical AI chips with our ARITH-DAS and baselines integrated. in both area and delay. More results, including evaluation on multiply-accumulate (MACs) and visualization of results, are provided in Appendix ID)
5.3 Generalization to Large-Scale Computing Circuit
To assess the generalization capability of the optimized computing units, we integrate those pro- duced by ARITH- and baseline methods into six representative Al accelerator circuits from the Koios 2.0 benchmark [39]. In addition, we deploy and evaluate these units within a typical processing element (PF) array architecture, which is widely used in applications, following previ- ous works [7] IT,, 21] As shown in Figure N and Figure M eircuits incorporating ARITH-DAS -optimized units consistently outperform these baseline counterparts across multiple metrics. These
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Table 1: Hypervolume (HV.) of multiplier design.
Mult. (AND)
8 bit
16 bit
32 bit
64 bit
Method
HV. 1
Impx(%%
HV. 7
Impc.(%)
HV. 1
Impr.(%
HV.
Impe.(%)
Wallace
3.43
NA
107.53
NA
793.19
NA
4.796.14
NA
GOMIL
11.56
237.25
265.17
146.60
1,216.48
53.36
8,784.55
83.16
UFO-MAC
12.83
274.08
269.18
150.32
1.076.70
35.74
7,932.19
65.39
DOMAC
4.60
34.29
177.52
65.09
1.267.22
59.76
9,941.63
107.28
ArithTreeRL
9.61
180.29
315.19
193.11
2,779.56
250.43
14,237.63
196.86
MUTE
11.67
240.30
310.89
189.11
2,470.47
211.46
16,656.60
247.29
ARITH-DAS (Ours)
16.30
375.32
361.84
236.49
3,247.06
309.37
19,563.48
307,90
Mult. (Booth)
8 bit
16 bit
32 bit
64 bit
Method
HV. 7
Impr.(%)
HV. 7
Impr.(%)
HV.
Impr.(%)
HV.
Impr.(%)
Wallace
14.92
NA
130.88
NA
878.23
NA
3,146.58
NA
GOMIL
31,50
111.16
274.09
109.43
1,852.58
110.95
5,842.81
85.69
UFO-MAC
31.50
111.18
211.36
1,754.11
99.73
4,408.90
40.12
DOMAC
15.54
4.17
152.25
16.33
1.875.59
113.57
8,440.55
168.25
ArithTreeRL
29.94
100.72
311.13
137.88
2,455.28
179.57
10,728.16
240.95
MUTE
30.61
105.15
346.68
2,961.62
237.23
11,034.68
250.66
ARITH-DAS (Ours)
39.94
167.70
389.63
197.71
3,305.51
276.38
12,212.89
288.13
16-hit And
16-hit Booth
32-bit And
32-bit Booth
Dabe 669
Dolay
Dally
55000
(Um=)
))
(1m²7)
(jmm²)
ArRh-IAS (Mae))
MUTTE
AnthTr
UII-MAC:
DIMMAC
GOME.
Whilacn
Figure 7: Pareto front of PE arrays integrated with designs generated by ARITH-DAS and baselines.
results demonstrate the strong generalization ability of ARITH-DAS in lcrge-scale, computation- intensive circuits, underscoring its potential enhance the performance of real-world AI chips.
5.4 Ablation Study
We conducted carefully designed ablation study targeting the multiplier design task. As has been noted, our method is composed of the following key modules: (1) the Circuit Genetic Evolution (CGE)
Table 2: Ablation study
Mult. (AND)
Method
HV.1 1
Impr(%)
HV. f
Impr(X))
module, (2) the Multi-Relational Graph Encoder (MRG) module, and (3) the PPO-style training mod- ule (PPO). To assess the individual contribution of each module within ARITH-DAS, we conduct a
Wallice
107.53
NA
793.19
NA
ARITI-DAS (Ours)
361.84
236.49
3,247.06
300.37
CGR
336.58
203.71
2427
206.06
MRG
313.57
191.61
2499.68
215.14
w/o PPO
326.49
203.63
3007.14
279.12
comprehensive component-wise analysis focused on the optimization of multiplier architectures. Specifically, we design three ablation experiments by removing each module, respectively, to quan- tify its impact overall performance: (1) w/o CGE where circuit genetic evolution is replaced with a simulated annealing approach; (2) w/o MRG where the multi-relations
graph encoder is replaced by heterogeneous-node graph with uniform edge types; (3) w/o PPO where the PPO-style loss is replaced by the proxy delay model introduced in previous work [[ As shown in Table RL all three modules are critical the overall performance. Removing the CGE module impairs structural ex- ploration and reduces architectural diversity. underscoring the role of genetic search in design space navigation. Removing the MRG module weakens relational reasoning, confirming the necessity of modeling edge semantics for accurate connectivity inference. Substituting the PPO-based optimiza- tion with proxy delay model degrades performance, highlighting the benefit of end-to-end training aligned with post-synthesis metrics.
Conclusion and Limitations
In this work, we propose ARITH-DAS differentiable architecture search framework for arith- metic circuit optimization. Experiments on representative arithmetic units show that ARITH-DAS consistently outperforms statc-of-the-arr baselines in area-delay trade-offs. When deployed in large-

---

scale Al accelerators, it achieves notable timing improvements, demonstrating strong scalability and practical value. These results underscore the effectiveness of ARITH-DAS and offer new directions for optimizing high-performance computing systems.
However, there still remain several limitations. Consistent with prior studies, current experimen- tal setup remains confined to the post-synthesis stage, which does not account for the intricate back- end procedures such as placement, routing, and timing closure. These stages have a profound impact on the circuits final area, timing, and power characteristics, often leading to substantial discrepan- cies between synthesized and implemented results. Hence, exploring muckend-aware optimization strategies for arithmetic circuits constitutes an essential avenue for future research.
7
Acknowledgements
We would like to thank all the anonymous reviewers for their insightful comments. The numerical calculations in this paper have been done the supercomputing system in the Supercomputing Center of the University of Science and Technology of China. This work was supported by the National Key R&D Program of China under contract 2022ZD01 19801, and the National Natural Science Foundation of China grants U23A20388, 62021001, and 624B1011. We would like to thank our lab-mate, Zhaojie Tu, for his valuable technical support.
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A Related Work
A.1 Computer arithmetic
Computational circuits such as adders and multipliers serve foundational components in modern computing systems, enabling performmrrm parallel operations through advanced architectures such as compression trees and prefix trees. The optimization methodologies for these circuits pre- dominantly fall into three categories: (1) Manual Design: This approach relies on domain -meain-ppecific knowledge refine conventional architectures, demanding considerable engineering resources. No- table implementations include partial product reduction techniques using compression tree [36, 20-- A2], and optimized parallel addition through prefix tree [_]. (2) Traditional Algorithmic Approaches (IIO, 20 mi [7]]: These methods employ mathematical programming and heuristic search to generate circuit architectures. However, their dependence on proxy metries (e.g., size, depth) frequently introduces substantial deviations from physical implementation outcomes. (3) Learning-Basse Approaches [E, &. L.S. 21 HS. 89]: Emerging techniques integrate synthesis pro- cesses with reinforcement learning frameworks, directly targeting post-synthesis metrics to mitigate the fidelity loss inherent in proxy-based optimization. RL-MUL [2T]] first proposed a reinforcement learning framework for multiplier optimization, and HAVE [_S] later extended it into a hierarchical multi-task RL framework. Recent work. DOMAC [ introduced differentiable interconnec-
tion optimization algorithm based on an estimated proxy delay model, offering a new perspective for arithmetic circuit optimization. In this work, we similarly focus on optimizing interconnection within arithmetic circuits using post-synthesis metrics.
A.2 Machine learning for chip design
As semiconductor processes advance into the nanoscale era, integrated circuit complexity grows exponentially, creating computational complexity bottlenecks for traditional EDA tools in PPA op- timization. Machine learning-baa based design automation methodologies, particularly Graph Neural Networks (GNNs), have emerged novel paradigm address these challenges. The canonical chip design workflow encompasses critical stages including logic synthesis, floorplanning, clock tree synthesis, and routing. The netlist, serving as intermediate representation compiled from hardware description languages (HDLs), inherently embodies a graph-based data structure that en- capsulates gate-level circuit components and their directed interconnect dependencies. This intrinsic graph topology makes GNNs particularly effective for extracting topological features, as evidenced by several pioneering studies, such LaMPlace[5S]], TP-GNN[SI], and TA3D[52]. There is pub- licly available benchmark for AI solutions in backend layout and routing [53]]
A.3 Differentiable architecture search
Recently, differentiable architecture search has been getting a lot of attention in a variety of areas. In the domain of neural architecture search (NAS), DARTS(22) pioneered a gradient-based approach by relaxing discrete architectures into continuous spaces, enabling efficient optimization through gradient descent. Building upon this, ProxylessNAS [23] directly searches for neural network archi- tectures on the target tasks and hardware, addressing the high computational cost of traditional NAS and the large memory consumption of differentiable NAS. In the domain of logic gate network archi- tecture search, Petersen et al. [[4]] resolves the differentiabbiliy issue of logic gate networks via real-valued logic and continuous relaxation, enabling them to be trained using gradient descent. Fur- ther extending this direction, Petersen et al. [2 presents Convolutional Differentiable Logic Gate Networks, which enhance Differentiable Logic Gate Networks through deep logic gate convolu- tions, logical OR pooling, and residual initialization. In the domain of hardware optimization, Wang al. [25I] proposed neural circuit generation framework using differentiable architecture search and reinforcement learning, enabling precise synthesis of circuits with large-scale nodes while out- performing traditional logic synthesis tools.
A.4 Graph Neural Networks
GNNs learn on graphs via iterative neighborhood aggregation [53 56 and are applied broadly
in graph-related problems [57-60]] Canonical architectures, GCN (spectral/spatial convolution)
55), GraphSAGE (inductive sampling) [6]]] GAT (attention over neighbors) [62]] and GIN (WL-
22

---

strengthened expressivity) [63], define the fields expressivity-scalabbe trade-offs. Depth is lim- ited by over-smoothing and over-squashing, motivating residual/skip connections, normalization, and multi-scale propagation [64, 65]. Beyond homogeneous graphs, multi-elatioma/hheeegeeenuu GNNs parameterize typed edges and meta-relations: R-GCN [19] and CompGiCN [TG) perform relation-specific propagation, while HAN/HGT incorporate relation-aware attention for web-scale heterogeneity [66, bz]j. In parallel, graph Transformers (e.g., Graphormer) inject structural biases into global attention to capture long-range dependencies [27] There is also recent survey of rein-
forcement learning on graphs [68].
B Design Space Complexity Analysis
In this section, we analyze the complexity of the design space of the compressor tree allocation and the compressor interconnection. Previous works [L. 9] have shown the O(2 complexity for compressor allocation design, where N is the input bitwidth of the arithmetic circuit. Here, provide a complexity analysis of the interconnection space.
Without loss of generality. let's take the AND PPG multiplier partial products of the AND PPG multiplier with an input bit-width of N is exactly N Next, a 3:2 compressor compresses partial product while 2:2 compressor doesn't compress. Therefore, at least O(N²) 3:2 compressors are needed to compress the O(N2) partial products into compressed products with complexity of O(N). Finally, the complexity of the shape of 3-relational directed graph representation of the compressor tree is at least 3 x N which indicates an O(23N²) search space. Note that, since the stage assignment determines the topological order of nodes and constrains compression to occur within each stage, interconnection happens only locally. As result, connections established only locally, and the complexity of the interconnection space is linear rather than quadratic with compressor number.
example. First, the number of
Overall, the design space complexity of a compressor tree, considering both its allocation and inter- connection, exhibits extraordinary growth rate of O(21N²).
C Implementation Details
C.1 Hardware Specification
All experiments are executed a computational platform with an Intel Xeon Gold 6246R CPU (3.60 GHz) and NVIDIA RTX 3090 GPU,
C.2 Synthesis Tool Setup
We use Yosys [30] for logic synthesis and OpenSTA [69] for STA simulation in conjunction with Nangate45 open cell library [[II], which is widely used in the semiconductor industry and related
research. Synthesis script and SDC constraints are provided at Listing M1 and Listing 2
All RTL designs generated by method and baselines are functionally verified with Verilator [32]] We randomly generate 10000 input samples, and perform bit-wise comparison between the Verila- tor evaluated result and the ground truth calculated by C++ codes.
Listing 1: SDC Constraints
set set_ www.ddivingeeeee BUF X1 aet_load 10.0 [utl_s]
23

---

Listing 2: Synthesis Script
read -sv (verilog_path)
synth -top {top_name name]
dfflibmap -liberty (liberty_pathe
abc -D (target_delayl -onssr (constr_path) -liberty (liberty.path) vrite_verilog (netlist_path)
C.3 Implementation Details of Our ARITH-DAS
C.3.1 Further Discussion on Multi-Relationas Graph Formulation
In the main paper, we formulate the connection multi-relational directed acyclic graph (V, E, R) and corresponding adjacent tensor G {0, 1 ( |X|XXXX More implemeentation-speciie details are provided in this section.
Vertex Set Vertex set is defined as V {U1, U2,.... where a vertex V; corresponds to one of the following four basic components: (1) 3:2 compressor, which full adder, (2) 2:2 compressor, which a half adder, (3) initial partial product, which is the output of PPG and (4) visual node, which is wire. For the sake of implementation convenience, we also define output nodes virtual nodes within our graph representation. This unification allows for a consistent treatment of nodes during message passing and connectivity inference. Each node belongs to specific column and is assigned to specific stage during stage assignment [G]] The column number and the stage number of nodes topologically specify their interconnection order, i.e., from lower column higher column, and from lower stage to higher stage. This approach leverages the homogeneity among nodes to significantly reduce technical complexity.
Relational Set Relational set is defined sents an input port type. In this work we use 3:2 compressors and 2:2 compressors, and therefore R = {a, cin}. For 2:2 compressors, only input ports {a. cin} are available. For visual nodes, only {a} is available. For PP nodes, no relation is available since they do not have input ports. The relational types are specified according to the input port types, rather than output port types, mainly due to the fact that the input ports are logically indistinguishable, while the output ports are connected to different columns. Accordingly, we aim for each node to learn the semanties of its output connections through training.
(r J. where each relation type T; repre-
Edge Set and adjacent tensor Typed directed edge set is defined as E V R x V. where each edge (V,, F, vy) represents directed logical wire from output port of e connected to the r-th type input port of uy. Since edges are type-specific, construct separate graph for each edge type, |||
referred as a graph channel. Specifically, the value of G E [ is defined
Gr.ss = {
(0,, 0,,) & E, (u,T, E.
(10)
C.3.2 Architectural Design Constraints
In this section, we provide the detailed complex architectural constraints on the proposed multi- relational graph formulation. For node v; V. let Col(w; denote the column index of u; (tage(r;) denote the stage index of and Type(u:) denote the type of e, A legal design should satisfy the following constraints.
Vertex types and relation types constraints pp and:
For any (v, F, Uy) E E, there should be Type(u,) +
(a, b, cin} {a, cin} {a}
Typo(u;) 3:2 compressor,
Type(1,) 2:2 compressor, Type(u,) visual node.
(11)

---

Vertex typological constrains For any (U v.y) ) E E, there should be Sta = Stage(v;) + Col(e;) = Col(v;) c.) for sum wires of U; and Co)( ) Col(u;) + 1 for carry wires of U,-
Port exclusivity constrains Denote the output node of the graph as the primary out (PO), and the input node of the graph as the primary in (PI). PO and Pl nodes are specified according to the compressor allocation and stage assignment, which remain unchanged during the optimization process. Denote the set of primary
and primary out nodes as PI and PO, respectively. In our settings, for any node PI, Type(v) pp; for any node E PO, Type(r) = visual node. Each output port of non-PO nodes should be connected only to one node, i.e., for any node vi
Σ gras { JER.jtSumf()
V PO
Σ
gr =
0
1 E PO
(12)
1/ $ PO
nt & PO
where Sum(i = {j Col(u,) = Co)( Stage (yy) Stage( u.) + 1 is the set of nodes to which the sum of node v; legal, and Carry [i] (j Col(u,) = Col(u;) 1, Stage(u,)
Stage(e;) + 1} is the set of nodes to which the carry out of node e is legal.
Similarly, the input port of non-PI node should only receive logical connection from other node, i.., for any node vy E V and relation r E R,
{1
" E oror r & Input[ý],
Σ Gras
[1
else.
(13)
sE[[V]
where Input[j] C R. denotes the input types of node Vj.
Legalization Mask tion is legal. The value of Mr is:
The legalization mask M E
indicates whether connec-
Mrad { and Colley] or Colls]]=oo(eel]
rElnput j| and
(14)
else.
C.3.3 Multi-Relational Message Passing
To simulate the propagation of circuit information across different types of connections, we adopt a multi-relational message passing mechanism. Message passing occurs over all possible connection types, and each node aggregates incoming messages by merging hidden features from all relation- specific channels. It should be noted that the adjacency matrix used for message passing relation r E R is exactly the r-th channel of legalization mask M. The aggregated representation is then passed through shared single-layer MLP to produce the updated node state. It is worth noting that we do not explicitly fit any physical signal characteristics; instead, the entire process is trained in an end-to-end manner. Ablation studies confirm the necessity of this design choice.
C.3.4 Graphformer-Style Attention Score Calculation
To improve runtime efficiency in such a large and sparse graph space, we compute attention scores and maintain validity masks in a localized manner. caching mechanism employed. whereby computations are only triggered upon cache misses, thus reducing unnecessary overhead.
C.3.5 Regulized Sampling
Directly sampling from the raw probability distribution often leads invalid structures. To address this, we adopt regularized sampling strategy. Specifically, guided by the topological order provided by the stage assignment, we sample input ports for each node's output in sequence based on the connection probabilities. During sampling, mask fill operation is applied to the attention scores prior to normalization eliminate invalid connections. After each sampling step, the corresponding connection masks are dynamically updated to maintain structural legality, and probability logits are maintained for network updating. More specifically, when edge (u, v2) E R sampled with our Mrss = 1, we record corresponding a. value and let Mr 0 for all i.j E [DV]] and M 0 for all i' r| e R.
25

---

C.3.6 Detailed Derivation and Discussion of the Loss Function
We first provide the detailed derivation of (G) as below. When given compressor tree allocation
J(O s) = (0 [R())]
Σ T9 s))(()
GeG.
8) (o s)
Σ
(
R(g)
Tz(9 s)
GEC,
To 8)
(1) (s)
R(g)
(15)
Tg(l S)
Consequently, the unbiased statistical estimator of J( 5) is given by
1 M
To s) TT R(Gm).
J(0 5)
(16)
where 9m i.i.d. TT(' s). In PPO, the clip operation is typically introduced to ensure that the distributional shift between the sampling policy #y and the updated policy my does not become too large, which could otherwise lead to distorted surrogate objectives due to mismatched trajectory distributions [ZO]].
However, in our setting, the problem can be reformulated as a single-step multi-armed bandit sce- nario rather than a sequential Markov Decision Process. Therefore, trajectory mismatch is not an issue. Nonetheless, the clipping mechanism remains crucial for reducing variance during policy updates. We formalize this intuition in the following proposition. First, we introduce Pearson x divergence, which is widely used in machine learning [7T (72].
Definition (Pearson x² Divergence [73, is defined as
[Z
For two distribution p and g, Pearson x? Divergence
p(x)
(pl1)) Bzng
(17)
((x)
Then, we have the following proposition. Proposition
Assume that the objective function bounded; maxgec [R( S Rm Then the variance of estimator of J (( 8) defined in (TT)) is bounded by x2 divergence:
Var (J(0 s)) S
R 1
x²
nO
Tol. (s)) (2(0))
(18)
M
Proof. Let p
(G mm)
Since samples Gn i.i.d., then
n (Gm 1) R((m))
Var Varrg(1b) (J(0)s) Varzy(11s
M
3 9m s)
Varg~ay(11)) (po |s)
(19)
M
Here, we have
Varg (po( R)R(
1g--y((s)) (P {) - Eg (pe(G s)))
Eg [[pe (9 {)))) J²((),
(20)
and
Eg [Pe(( {)) < Eg [pō(9] s)
R² E B [6 s)]
(21)
26

---

Notice that
x² (TTO(-1s) (o00-1)|[a(((1 =
nT
Σ DEG
To (9
-1 T9(
2
TT (9 8)
1 1+ 7 8))
To(g [8)
2
Tg s)
TT(G s)
(9 8)
DEC
T7(G s) 2 Σ
To |s) + Σ
(pōig s)) s))
GEG
gEG
GeG
E (1)))((ss) [0 |s]] -1
(22)
Consequently, we have
Var (1)) -
R2
M (1 (1+ x2 Tol( s) कहल. | [s))s
J2 [s)
(23)
M
Proposition M indicates that the total variance is bounded by the x² divergence between policy my s) and nz(- s). Therefore, clipping the probability ratio reduces the variance of the policy gradient, thus enhancing training stability. This is especially necessary in discrete structural settings, where large updates easily destabilize learning.
C.3.7 Learning Setup
In the multi-relational graph encoder, we convert the directed graph into an undirected one and add self-loops for bidirectional information flow, which is widely used in graph-structured data processing [ 55). The rationale behind this design lies in the fact that the directional information sound and completely contained in node features. The node features used for the graph neural network initialization are provided in Table It is worth noting that all node features are intrinsic the node itself. For a fair comparison, the iterations of all experiments set equal. We provide the hyperparameters of the main evaluations and ablation experiments in Table
Table 3: Node Features
Feature Description
Size
Column number
Stage number
1 4
One-hot encoding for node types, including 3:2 compressor, 2:2 com- pressor, initial pp. visual node
Sequential ID for compressor with the same column, stage, and type
C.3.8 Evaluation Metrics
The design of efficient multipliers involves optimizing multiple competing goals, including area and speed. To assess performance, we employ two key measures. Initially, we graphically compare the estimated Pareto frontiers for area versus latency across our approach and existing techniques. Additionally, we evaluate the hypervolume metric for these frontiers. Further details on these criteria are provided below.
Multi-Objective Optimization Metrics
Generally, for multi-objective maximization task with targets, the goal is identifying the op- timal solution collection called the Pareto set. such problems, solution x is said domi- nate if x performs equally or better in every objective while surpassing in at least one, i.e., Vi E [1, fi(x)) 2 f((y) A 3i ft.xx) fi(y). Pareto-optimal point remains undom- inated, and all such points form the Pareto set. Hypervolume, depicted in Figure & quantifies set
27

---

Table Hyperparameters
Hyperparameter
Value
Learning rate
le-4
Iterations
5000
GNN layers
3
Hidden state dimensions
512
Query/key dimensions
64
Activation function
tanh
Optimizer
Adam
Discretization penalty and output-port exclusivity constraint
0.01
PPO trust region
0.2
Elite pool size
20
Pareto points
Reference points
Dday
Non- Pareto points
Deaay
P())
Hypervolume
P(3)
P(S)
P(4)
Area
Area
(a) Pareto Points
(b) Hypervolume
Figure 8: (a) An example for a Pareto optimal set with 2 objectives and 5 Pareto optimal solutions (Pareto points). (b) An example for hypervolume with selected reference point ro. Integrated area ((P, ro) is the union of the rectangular areas where the reference point To and the Pareto point P(i) are diagonally opposite corners.
quality by measuring dominated space volume. Computing hypervolume requires selecting refer- ence point; with fixed references, larger hy hypervolumes indicate superior Pareto sets.
Definition 2 (Hypervolume metric). Consider a P representing an approximate Pareto frontier in an n-dimensional optimization space, consisting of N candidate points. Given a reference vector ro Rm the hypervolume measure H(P. ra) is formally expressed as:
f [P(
H(P. ro)
where H(P,ro) fa E 2 <is i : = P()). Here, P(i) denotes the i-th entry in P. 3 indicates Pareto dominance between vectors, and 1H(Prr)) is an indicator function returning 1 when z E (r)) and O otherwise.
C.4 Implementation Details of Baselines
GOMIL [20] is a global optimization method that simultaneously considers the CT and CPA. The authors provide C++ implementation. All coefficients related the EDA toolchain and technology library are calibrated under the experimental setup. The resulting mixed integer programming (MIP)
problem is solved using the Gurobi optimizer [[Z]].
UFO-MACII0] is unified optimization CT and CPA framework considering compressor intercon- nections. The resulting integer programming problem is solved using the Gurobi optimizer [[>]]
28

---

DOMAC[IEI is a recent differentiable compressor interconnection optimization algorithm, which optimizes proxy delay model through routing permutation matrix relaxing.
Arith TreeRL a reinforcement learning method for CT optimization. The authors provide Python implementation for AND PPG multipliers, which can be easily extended to MACS and Booth PPG multipliers.
MUTE| is the state-of-the-art (SOTA) hybrid RL-evolution CT optimization framework. The authors provide a Python implementation for multipliers and MACs.
D More Experiment Results
D.1 More Results of Main Evaluation
D.1.1 More Results of Multiplier Evaluation
In this section, provide our evaluations Multiplie architectures, rencompassing 8-bit, 16-bit, 32-bit, and 64-bit implementations employing both AND gate-based Booth encoding-based techniques. The min delay and min area provided in Table HL
Table 5: Min area and min delay of multiplier design tasks
Mull(AND)
bit
16 bit
Method
Arealpon")
Impr:(5)
Delay [xx)
Impr. (8))
Areatymm
Impr(())
Delay (nt)
Impr((9)
Wallace
402
NA
0.74
NA
1,787
NA
1.37
NA
GOMIL
385
5.88
12.6
UFO-MAC
383
4.73
0.69
7.05
1,674
6.32
1.19
13.15
DOMAC
402
0.00
0.72
1.82
1,788
-0.06
1.27
7.05
ArthTTheeR..
385
4,23
1,307
4.48
1.12
18.38
MUTE
388
3.48
1,694
5.2
1.15
16.08
ARITH-DAM DAS (Ours)
384
4.48
0.64
13.15
1,713
4.14
1.06
22.15
Mull(AND)
Method
Area (uma²)
Impr(99)
Delay (rus)
Impz(9)) 1
Area (um²))
Impr()))
Delay (ns)
Impr((9) 1
Wallace
7,402
29,721
NA
2.93
GOMIL
7,029
5.04
2,06
28.602
3.77
2.66
9,33
UTO--MAC
7,027
5.07
2.11
2.96
28,600
3.77
2.72
7.17
DOMAC
7,489
-1.18
1.99
30,055
-1.12
2.49
15.01
AithTTcceL
7,176
29,057
2.23
24.91
MUTE
7.125
3.74
1.64
24.49
28,677
3.51
2.07
29.56
ARITH-DAS (Ours)
7,099
4.09
35.35
28,669
3.54
1.85
36,94
(ooth
8 bit
16 bit
(μm²)
Impr(S))
Deluy (nu)
Impr(*))
(jm²))
Impr(%)
Delay (ma)
Impr(*k)
Wallace
408
NA
0.76
NA
1,505
NA
1.32
NA
GOMIL
406
0.49
0.68
10.09
1,407
6.51
1.16
12,50
DXMAC
415
-1.72
0124
2.07
1,548
-2.86
1.27
3.59
ArihTTrocRL
405
0.74
0.71
6.36
1,425
5.32
1.07
18.73
MUTE
ARITH-DAS (Ours)
403
1.23
0.64
15.91
1,418
5.78
1.01
23.64
Mult.(Booth)
32
64
Method
Area (jem²)
Impr.(k) 1
Delay (ns)
Impr((k)
Area (pm())
Impr.(5) 1
Delay (ma)
Impr((k)
Wallace
5,383
2.24
NA
20.435
NA
2.94
NA
GOMIL
UPO-MAC
5,175
3.86
1.97
12.42
19,675
3.72
2.82
4.04
DOMAC
5,500
-2.17
1.87
16.79
20,787
-1.72
2.22
24.41
ArthTTeeRL
5,227
MUTE
5,328
1.02
1.49
33.6
19,856
2.83
2.03
31.01
ARITI-DAS (Ours)
5,210
3,21
1.44
35.78
19,690
3.65
1.92
34,53
D.1.2
More Results of MAC Evaluation
We provide our evaluations MACs in this section. The visualization of the Pareto front is illus- trated in Figure g The hypervolume recorded in Table and the min delay and min area are provided in Table Q.
29

---

16-bit And
32-bit And
13
26
14
Delay (n.)
Delay (n.)
22
1.3
18
14
1800
2000
2200
2400
2A00
2000
7250
7500
1000
8500
8750
Area (um?)
Area (jum²)
Arith-DAS (Ours)
UFO-MAC DOMAC
GOMIL Wallace
MUTE
ArithrrecLL
Figure 9: Pareto front of MAC designs.
Table Hypervolumn of MACs
MACs
16 bit
32 bit
Method
Hypervolume?
Impr.(%)
Hypervolumet
Impr. (%)
Wallace
103.17
NA
325.72
NA
GOMIL
301.78
192.51
575.14
76.57
UFO-MAC
205.20
98.89
385.01
18.20
DOMAC
173.67
68.33
579.01
77.76
ArithTreeRL
352.35
241.52
1,395.40
328.40
MUTE
265.24
157.08
1,274.29
291.22
ARITH-DAS (Ours)
433.18
319.87
1,684.68
417.21
D.1.3 More Results of Generalization Evaluation
We provide the Hypervolume PE arrays Table The min delays and min areas are provided in Table g The area and delay of Koios benchmark [3%] designs integrated with our ARITH-DAS and baselines are provided in Table ITI
D.2 Visualization Results
To provide an intuitive understanding of the problem, we visualize representative examples of the circuit structure. Due to the large problem scale, we only present the complete results for 8-bit multipliers using AND and Booth encoding and 16-bit multipliers using AND encoding, as shown Figure III Figure IIO, and Figure I2. Additionally, for the 32-bit and 64-bit AND multiplier, we selectively visualize Columns 30-31 and 32-33 to highlight the structural patterns in deeper regions of the compression tree, as shown in Figure IR Figure [4] Figure D and Figure In all figures:
Green nodes represent virtual nodes, typically containing input and or outputs.
Table Min area and min delay MAC designs
MAC
16 bit
32 bit
Area (jm²)
Impe.(16)
Delay(sa)
Impr((%)
Area (jonz)
Impr((5))
Delay(ns)
Impr.(5))
Wallace
1,884
NA
1.38
NA
7.589
NA
2.31
NA
GOMIL
1.20
UFO-MAC
1,770
6.05
1.30
6.23
7.196
5.18
2.34
-1.14
DOMAC
1,916
-1.70
1.28
7.59
7,658
-0.91
2.05
11.31
ArithTrceRL
3.34
3.32
MUTE
1,848
1.91
1.23
11.87
7,472
1.54
1.58
31.91
-RIT--DAS (Ours)
1.814
3.72
1.06
23.54
7.264
4,28
1.44
37.87
30

---

Table 8: Hypervolume of PE arrays.
Array
16-hit
Rooth
Method
Hypervolume
Impe/(S)
Hypervolume
Impe. (1e))
Hypervolume
Impe..5))
Hypervolume
Impe/16)
Wallace
13,023.55 58
NA
12,493.99
NA
64,431131
NA
57,026,10 10
NA
GOMI
3,774
-71.02
18.798.77
50,46
84,133.90
30.58
130,763.99 99
111.71
URO-MAC
5,303.81
76,563.3
18.3
111,945.22
96.27
11,117.57
100.269.
99.131.37
73.80
ArilhTrocRI.
15,767.41
14,94.67
133,033.11
116,160:12
103.66
MUTE
16,100554
24.09
14,380.01
14.70
129,010.95
100.23
151.738.71
166.04
ARITH-DAS (Ours)
16,219.91
24.54
20,680.92
65.53
152,373/47
136.49
194,991.71
241.87
Table 9: Min area and min delay of PE arrays
PE array
16-hit AND
16-hit Booth
Area((on")
Impre(%)
Delay(ns)
Impr. (%i)
Arealyom)).
Impe(5h) 1
Delay(no)
Impr(%)) f
Wallace
149,556
NA
1.72
NA
131,459
NA
1.78
NA
GOMIL
142,729
4.56
-5.23
125,126
UFO-MAC
142,218
4.91
1.82
-5.81
125.024
4,9
4.49
DOMAC
149,522
0.02
1.68
2.33
131,136
0.25
1.79
-0.36
ArihbTreeLL
144,329
125,927
MUTE
143,359
4.14
1.67
2.91
125,637
4.43
1.77
0.56
ARITH-DAS (Ours)
145,249
2.88
1.62
5.81
126.710
3.61
1.67
6.18
arruy
32-bit AND
32-bit Booth
Method
Area(am=)
(mp)(5)
Delay(ns)
Impr(S)
Area(jmn").
Impr(56)
Delay(nu)
Impr. (%)
Wallace
545,126
NA
2.73
417,650
2.78
NA
GOMIL
521,445
4.34
2.62
4.03
404,456
3.16
2.49
10:43
DOMAC
581,526
-1.17
2.56
6.23
425,191
-1.81
2.55
8.27
ArihhTreeRL
$31,540
2.49
12.09
407,691
2.38
2.47
11.15
527,948
ARITU-DAS (Ours)
526,348
3.44
2.34
14.29
407,384
2.46
2.13
23.38
Blue nodes represent half-adder nodes, typically containing 2 inputs and 2 outputs.
Orange nodes represent full-adder nodes, typically containing 3 inputs and 2 outputs.
Gray nodes in the first row represent partial product nodes, typically containing I output. Gray nodes in the last row represent output nodes.
Figure 10: 8-bit Booth Multiplier
D.3 Runtime Comparison
This section compares the runtime of our method with baseline approaches under consistent exper- imental settings. Specifically, we run all post-synthesis driven algorithms for 5000 iterations. For programming based methods, we report the objective gap with hour runtime, which is defined by (Incumbent- BestBd) BeeeeBdd/Innubbbeeee /Innumbentt 100% [[5]] For the proxy-delay-modei driven method, DO- MAC [[]]], we evaluate it with 1000 iterations. Although our method does not outperform traditional solvers in terms of runtime, it offers more flexible and generalizable optimization framework that is well-suited for large-scale scale and complex circuit design problems. The detailed runtime environment provided in Appendix C. and Appendix C2 The runtime results are summarized Table D
E Licenses
We credit the following open-source project used in this paper. Our main codes are provided https://gite com dakf falakfjaakk/aa waliaaaraaaaaaaaaaaaaaaaraarraaa git.
31

---

Table 10: Area and Delay of Koios benchmark integrated with our ARITH-DAS and baselines.
Design
Method
Area(um²)
Area Impr.(%)
Delay(ns) 1
Delay Impr: (6) f
Wallace
1.6590E+06
NA
1.55
NA
GOMIL
1.6483E+06
0.64
1.42
8.39
DOMAC
1.6579F=+06
0.06
1.56
-0.65
attention_layen
UFO-MAC
1.6481E+06
0.65
1,56
-0.65
RrelhTreeRL
1.6487E+06
0.62
1.35
12.9
MUTE
1.6529++06
0.37
1.37
11.61
ARITH-DAR (Ours)
164955+06
0.57
1.29
16.77
Design
Method
Area(um²)
Area Impr. (%)
Delay(ns) |
Delay Impr. (6)
Wallace
1.0407+007
NA
1.74
NA
GOMIL
100400++07
0.07
1.63
6.32
DOMAC
1.0404E+07
0.02
1.76
-1.15
conv_layer
UFO-MAC
1,000F=+07
0.07
1.76
-1.15
ArithTreeRL
1,0402E+07
0.04
1.52
12.64
MUTE
1,0402E+07
0.05
1.47
15.52
ARITH- ARITI-DAS (Ours)
1,0398E+07
0.08
1.41
18.97
Design
Method
Area(jmm²
Area Impr:(%)
Delay(ns) |
Delay (mpr:(%) 1
Wallace
1.3207E+07
NA
0.97
NA
GOMIL
1.3207E+07
0.9
7.22
DOMAC
1.3153E407
0.41
0,95
2,06
layer
UFO-MAC
1.3207E+07
0
0,96
1.03
ArithTreeRL
1.3234E+07
-0.2
0,91
6.19
MUTE
1.3234E+07
-0.2
0.94
3.09
ARITH-DAS (Ours)
1.3145E+07
0.47
0.86
11.34
Design
Method
Arca(um²) 4
Arca Impr(%%)
Delay(ns) |
Delay Impr (%)
Wallace
2.1045E+06
NA
0.97
NA
GOMIL
2,0977E+06
0.32
0,9
7.22
DOMAC
2.1045E+06
0.95
2.06
gemm_layer
UFO-MAC
2.0968E++06
0.36
0.95
2.06
ArithTreeRL
2.0977E+06
0.32
0.91
6.19
MUTE
2.0986E+406
0.28
0.94
3.09
ARITH-DAS (Ours)
2,0984F:+06
0.29
0.86
11.34
Design
Method
Area(um²)
Area Impr(%)
Delay(ns)
Delay Impr
Wallace
7.5409E+06
NA
1.57
NA
GOMIL
7.4785E+06
0.83
1.38
12.1
DOMAC
7.5390F:06
0.03
1.56
0.64
Istm
UFO-MAC
7.4775E+006
0.84
1.43
8.92
ArithTreeRL
7.4885E+06
1.35
14.01
MUTE
7.5078E+06
1.37
12.74
ARITH- DAS (Ours)
7.4927E+06
0.64
1.29
17.83
Design
Method
Area(um²)
Area Impr.
Delay(ns)
Delay Impr.
Wallace
1.2948E+05
NA
0.97
NA
GOMIL
1.2921E+05
0.21
0.91
6.19
DOMAC
1.2948E+05
0.95
2,06
softmax
UFO-MAC
1.2917E+05
0.24
0..55
2,06
ArecLTreRRL
1.2921E+05
0.21
0.91
6.19
MUTE
1,2924E+05
0.18
0.94
3.09
ARITH- DAS (Ours)
1,2924E+05
0.19
0.85
12.37
Figure 11: 8-bit AND Multiplier
32

---

Figure 12: 16-bit AND Multiplier
d18 8
dnd
6.
8 6
Figure 13: 32-bit AND Multiplier (Column 30 and Column 31)
Figure 14: 32-bit AND Multiplier (Column 31 and Column 32)
Figure 15: 64-bit AND Multiplier (Column 62 and Column 63)
Figure 16: 64-bit AND Multiplier (Column 63 and Column 64)
33

---

Table 11: Runtime Comparison
Medthod
8-bit AND Mult.
16-bit AND Mult.
32-bit AND Mult.
Wallace
NA
NA
NA
Programing based algorithms objective gap with hour runtime (%)
GOMIL
0% (solved in 0.51 sec.)
0.08%
0.59%
UFO-MAC 0% (solved in 2.46 sec.) 0% (solved in 70.35 sec.)
33.0%
Proxy-delay-odde driven algorithms runtime for 1000 iterations (minute)
DOMAC
1.50
5.46
19.42
Post-synthesis driven algorithms runtime for 5000 iterations (hour)
ArithTreeRL
5.46
10.42
25.89
MUTE
9.37
12.60
50.83
ARITH-DAS (Ours)
6.40
13.06
38.73
1. OpenROAD BSD 3-Clause License
2. Yosys [60]] ISC License
3. OpenSTA GPL-3.0 License
4. Verilator h+
LGPL-3.0 License
5. ArithTreeRL M-: No License
6. GOMIL 2 No License
7. VTR/Koios 39] VTR License
34


Reviews:
[{"review_id": "6pcf5hRwV2", "reviewer": "Reviewer_B7rW", "summary": "This paper introduces a differentiable architecture search framework for arithmetic circuit optimization, which is set to overcome the existing limitations such as the under-explored design space of interconnection and the misaligned/oversimplified proxy objective, where both challenges are illustrated by case studies with randomized interconnect experiments. The empirical results show that the proposed ARITH-DAS framework can achieve 27.05% gain in hypervolume and 6.59% delay reduction in large-scale designs.", "questions": "N/A", "limitations": "The proposed work is \"proxy-free\" in the sense of synthesis results. What about plugging into the full design flow? It looks like the proxy-gap is limited to a certain degree.", "rating": 5, "confidence": 4, "soundness": null, "presentation": null, "contribution": null, "strengths": "", "weaknesses": "", "quality": 3, "clarity": 3, "significance": 3, "originality": 3, "strengths_and_weaknesses": "- This paper presents a comprehensive differentiable architecture search framework for arithmetic circuits, especially for the multipliers and multiply-accumulate units since they account for major computations. \n\n- The paper is well written with easy-to-follow flows and illustrative figures to show the major contributions. \n\n- The final results show a decent improvement of hypervolume on a suite of selected circuits, as well as significant delay reduction on large-scale designs. \n\nHowever, I do spot certain weaknesses of the work and raise a few questions as follows:\n\n- The authors mention in line 68, “The entire framework is trained in a proxy-free manner.” However, it seems that this applies to the post-synthesis alignment only. \n- The major evaluation metric is hypervolume (HV), and the authors showcase a significant improvement on Pareto frontiers when compared to other baselines. However, with the large-scale computing circuits, the results are limited to the delay reduction only. What is the main reason that area (or more generally, Pareto frontiers) are not shown here?\n- In the ablation study, it looks like neglecting certain key modules will not affect the improvements in general. Can the authors add the runtime difference when these key modules are not considered, since the current total runtime is not outperforming certain baselines? \n- Certain typos are found. For example, line 116 should be “Misaligned”.", "was_revised": true, "final_justification": "I will keep my positive score (5). The authors have done important post submission experiments to clarify some very important statements. Although the back-end proxy has lowered the overall improvements, I think this paper is still valuable. However, I don't know if this is possible but we wanna to make sure the authors do include those back-end experiments and discussions if we accept it.", "rebuttal": "## **Response to Reviewer B7rW**\n\nWe sincerely thank you for your careful review and for your constructive, insightful, and valuable comments. Please find below our detailed responses to your inquiries.\n\n### **Weakness 1 & Limitation 1: Plugging into the Full Design Flow**\n> **The proposed work is \"proxy-free\" in the sense of synthesis results. What about plugging into the full design flow?**\n\nWe sincerely thank you for your valuable suggestions. We have **integrated our framework, along with all baseline methods, into the complete design flow**, and present the corresponding results in the table below.\n\n|  | 16bit-AND | || 32bit-AND ||\n|:---:|:---:|:---:|:---:|:---:|:---:|\n|Methods| Post-Synthesis HV. | Full Flow HV. || Post-Synthesis HV. | Full Flow HV. |\n| Wallace  | $107.53$     | $27.49$    || $793.19$     | $83.95$      |\n| GOMIL    | $265.17_{+146.60\\\\%}$   | $109.91_{+299.82\\\\%}$ || $1216.48_{+53.37\\\\%}$   | $200.14_{+138.41\\\\%}$   |\n| UFO-MAC  | $269.18_{+150.33\\\\%}$   | $106.05_{+285.79\\\\%}$ || $1076.70_{+35.74\\\\%}$   | $159.57_{+90.08\\\\%}$    |\n| DOMAC    | $177.52_{+65.09\\\\%}$    | $53.41_{+94.31\\\\%}$   || $1267.22_{+59.76\\\\%}$   | $130.69_{+55.69\\\\%}$    |\n| ArithTreeRL | $315.19_{+193.12\\\\%}$   | $142.26_{+417.52\\\\%}$ || $2779.56_{+250.43\\\\%}$  | $898.79_{+970.67\\\\%}$   |\n| MUTE     | $310.89_{+189.12\\\\%}$   | $158.20_{+475.51\\\\%}$ || $2470.47_{+211.46\\\\%}$  | $663.50_{+690.39\\\\%}$   |\n||\n| Ours     | $361.84_{+236.50\\\\%}$   | $163.26_{+493.90\\\\%}$ || $3247.06_{+309.37\\\\%}$  | $1079.97_{+1186.50\\\\%}$ |\n\n**1. Rationale for Using Post-Synthesis Metrics**\n\nOur framework can be **seamlessly integrated into the full design flow**, encompassing floorplanning, placement, clock tree synthesis, and routing. However, executing the complete flow is **computationally intensive**, and the resulting metrics are often **highly sensitive to hyperparameter** settings. Consequently, post-synthesis metrics have become the de facto standard in prior works [1,2,3], which we also adopt to ensure **a fair and consistent comparison**.\n\n**2. Integration into the Full Design Flow**\n\nWe **integrate our framework into the full design flow** and summarize the results in the table above. Due to limited runtime and computation resources, we evaluate the full flow on 16-bit AND multipliers and 32-bit AND multipliers as representatives.\n\nSpecifically, we build upon the `test/flow.tcl` script from the OpenROAD project to complete the EDA backend workflow, which includes `initialize_floorplan`, `tapcell`, `pdngen`, `place_pins`, `global_placement`, `detailed_placement`, `clock_tree_synthesis`, `global_route`, and other essential stages. During the flow, the floorplan is initialized with $0.88$ utilization as suggested by the OpenROAD tool, and `aspect_ratio` is set to $1.0$. The global placement density is set to $0.3$ for a faster evaluation, as the default in the `test/flow.tcl` script.\n\n**3. Discussion on the Proxy-Gap**\n\n**The longer and more complex the backend synthesis flow, the larger the proxy gap tends to be in proxy-based methods.** This is primarily due to the **intricate processing stages and optimization algorithms** in the backend, which make it difficult to accurately approximate final outcomes using proxy objectives at the frontend, especially when the results are **highly sensitive to backend parameters**.\n\nTo further illustrate the impact of the proxy gap, we compute the average relative improvement of proxy-based and proxy-free methods with or without full design flow. Then we compare the relative gains before and after incorporating the full flow. As detailed in the table below, we observe that proxy-based methods **exhibit smaller relative gains after applying the full design flow**, highlighting the limitations of proxy objectives in capturing backend-accurate performance.\n\n||16bit-AND||32bit-AND| |\n|:---:|:---:|:---:|:---:|:---:|\n||Post-Synthesis Avg. HV.|Full-Flow Avg. HV.|Post-Synthesis Avg. HV.|Full-Flow Avg. HV.|\n| Wallace  | $107.53$     | $27.49$    | $793.19$     | $83.95$      |\n||\n|Proxy-Based| $237.29_{+120.67\\\\%}$ | $89.79_{\\substack{+226.62\\\\%\\\\\\\\ \\color{orange}{\\uparrow \\times 1.87}}}$ | $1186.8_{+49.62\\\\%}$ | $163.46_{\\substack{+94.71\\\\%\\\\\\\\ \\color{orange}{\\uparrow \\times 1.91}}}$ |\n|Proxy-Free| $329.31_{+206.25\\\\%}$ | $154.57_{\\substack{+462.27\\\\%\\\\\\\\ \\color{orange}{\\uparrow \\times 2.24}}}$ | $2832.36_{+257.08\\\\%}$ | $880.75_{\\substack{+949.13\\\\%\\\\\\\\ \\color{orange}{\\uparrow \\times 3.69}}}$ |\n\n---\n\n### **Weakness 2: Missing Large-Scale Computing Circuits Pareto/area Results**\n> **However, with the large-scale computing circuits, the results are limited to the delay reduction only. What is the main reason that area (or more generally, Pareto frontiers) are not shown here?**\n\n**1. On the Omission of Area Metrics in the Main Paper**\n\n**First**, due to **space constraints**, we report the area metrics of the large-scale computing circuit in Table 10 of Appendix D, as our primary focus lies in interconnection optimization, where **delay is the most relevant performance metric**.\n**Second**, a complete computing system comprises not only arithmetic circuits but also control logic, I/O interfaces, memory blocks, and other components. Consequently, **area optimization within arithmetic submodules has a limited impact on the overall area**. For this reason, we present area-related results in the appendix rather than in the main text.\n\n**2. On the Absence of Full Pareto Frontier Results**\n\n**First**, evaluating complete Pareto frontiers requires extensive experimentation, but logic synthesis and simulation of large-scale computing circuits are **extremely time-consuming and computationally expensive**. To balance feasibility and thoroughness, we conduct a full Pareto frontier evaluation only on a commonly shared computational structure, **the Processing Element (PE) array**, following previous works [1, 2]. The corresponding results are presented in Figure 7 of Section 5.3.\n\n**Second**, as noted earlier, large-scale computing circuits are **composed of multiple heterogeneous substructures**. Area optimization on arithmetic circuits alone often **yields limited overall area improvement**. Therefore, we focus on the delay metric and omit the full Pareto frontier analysis for the entire large-scale design.\n\n---\n\n### **Weakness 3: Runtime for Ablation Study**\n> **Can the authors add the runtime difference when these key modules are not considered, since the current total runtime is not outperforming certain baselines?**\n\nThanks for your suggestion. We conclude **the runtime for the ablation study**, where several key modules are removed, in the following table. We will add those results in the revised version of our submission.\n\n| | 16-bit AND |  | 32-bit AND |  |\n|:---:|:---:|:---:|:---:|:---:|\n|  | Runtime (hours) $\\downarrow$  | HV. $\\uparrow$  | Runtime (hours) $\\downarrow$  | HV.$\\uparrow$ |\n| **Ours** | $13.06$ | $361.84$ | $38.73$ | $3247.06$  |\n||\n| **w/o CGE** | $10.28_{-21.29\\\\%}$ | $326.58_{-9.74\\\\%}$ | $27.92_{-27.91\\\\%}$ | $2427.64_{-25.24\\\\%}$ |\n| **w/o MRG** | $11.10_{-15.01\\\\%}$ | $313.57_{-13.34\\\\%}$ | $26.32_{-32.04\\\\%}$ |  $2499.68_{-23.02\\\\%}$ |\n| **w/o PPO** | $9.18_{-29.71\\\\%}$  | $326.49_{-9.77\\\\%}$ | $22.37_{-42.24\\\\%}$ | $3007.14_{-7.39\\\\%}$ |\n\n---\n\n### **Weakness 4: Typos**\n> **Certain typos are found.**\n\nWe appreciate your careful reading and helpful feedback. The typo has been corrected. We have also conducted a thorough proofreading to eliminate similar minor errors throughout the paper.\n\n---\n\n### Reference\n\n[1] Zuo D, Ouyang Y, Ma Y. Rl-mul: Multiplier design optimization with deep reinforcement learning[C]//2023 60th ACM/IEEE Design Automation Conference (DAC). IEEE, 2023: 1-6.\n\n[2] Wang Z, Wang J, Zuo D, et al. A hierarchical adaptive multi-task reinforcement learning framework for multiplier circuit design[C]//Forty-first International Conference on Machine Learning. 2024.\n\n[3] Xiao W, Qian W, Liu W. GOMIL: Global optimization of multiplier by integer linear programming[C]//2021 Design, Automation & Test in Europe Conference & Exhibition (DATE). IEEE, 2021: 374-379."}, {"review_id": "HnOME3cJT4", "reviewer": "Reviewer_CFYW", "summary": "This paper aims to enhance the Arithmetic Circuit optimization via a differentiable architecture search framework. To do so, the author first model the combinational logic circuits as directed acyclic graphs (DAGs), in which partial products and compressors are modeled as nodes, and logical dependencies are modeled as directed edges. To capture this asymmetry, they represent the compressor tree as a multi-relational graph, where each edge type corresponds to a specific input port of the target node.  Then, the paper proposes a method called **ARITH-DAS**,encoding structural information via a multi-relational graph neural network and modeling interconnect prediction through graph attention, it enables end-to-end, gradient-based optimization directly guided by post-synthesis performance metrics. ARITH-DAS can also perform a proxy-free PPO-like training to optimize the interconnect structure with respect to post-synthesis performance metrics. The experiments shows ARITH-DAS's effectiveness and superiority when comparing it to other heuristic and ML-based baselines in area-delay trade-offs.", "questions": "See weaknesses.", "limitations": "Yes", "rating": 5, "confidence": 2, "soundness": null, "presentation": null, "contribution": null, "strengths": "", "weaknesses": "", "quality": 3, "clarity": 3, "significance": 4, "originality": 3, "strengths_and_weaknesses": "# Strengths\n1. The research questions are very practical.\n2. The paper is able to illustrate the concept of arithmetic circuit to readers who are not familiar with this topic\n3. The proposed method is effective and the ablation study also states the importance of each proposed module.\n\n\n# Weakness\n1. Some details of ARITH-DAS are not fully explained. For example, in lines 168-181, the author mentions \\mathbb{s} as the matrix of allocation of a compressor tree without demonstrating the role of \\mathbb{s} in terms of DAG setup or rest of the method implementation.\n2.  There is one paper: Reinforcement Learning for Combinatorial Optimization [1] which might be associate this submission, and the author may also include it as one reference.\n\n[1] Darvariu, Victor-Alexandru, Stephen Hailes, and Mirco Musolesi. \"Graph reinforcement learning for combinatorial optimization: A survey and unifying perspective.\" arXiv preprint arXiv:2404.06492 (2024).", "was_revised": true, "final_justification": "During the rebuttal the authors provided more details and basically solved my concerns.", "rebuttal": "## **Response to Reviewer CFYW**\n\nWe sincerely thank you for your careful review and for your constructive, insightful, and valuable comments. Please find below our detailed responses to your inquiries.\n\n### **Weakness 1: More Details About Compressor Allocation Matrix**\n> **Some details of ARITH-DAS are not fully explained. For example, the matrix of allocation $\\mathbf{s}$ is mentioned without further demonstration.**\n\nThank you for your valuable suggestion! We provide further demonstration of the compressor allocation matrix below, and **we will add a dedicated subsection in the revised version of our paper** to clarify its definition, role, and how it interacts with the rest of the framework.\n\n**1. Further Demonstration for Compressor Allocation Matrix $\\mathbf{s}$ and Seach Space $\\mathbb{S}$**\n\nFor a compressor tree with bit-width $N$ and $T$ types of different compressors, where $N,T\\in \\mathbb{N} _+$, the allocation matrix $\\mathbf{s}\\in\\mathbb{N} _ +^{T\\times N}$ stands for the number of specific compressors allocated in the column:\n\n$$\n\\mathbf{s} = \\left[\\begin{matrix}\n s_{1,1} & s_{1,2} & \\dots & s_{1,N} \\\\\\\\\n s_{2,1} & s_{2,2} & \\dots & s_{2,N} \\\\\\\\\n \\vdots & \\vdots & \\ddots & \\vdots \\\\\\\\\n s_{T,1} & s_{T,2} & \\dots & s_{T,N} \\\\\\\\\\\n\\end{matrix}\\right].\n$$\n\nHere, $s_{t,n}$ denotes the number of compressors of type $t$ allocated at bit column $n$. Different choices of $\\mathbf{s}$ define different compressor tree configurations, and the collection of all valid allocation matrices forms the allocation-level search space $\\mathbb{S} \\subset \\mathbb{N} _+^{T\\times N}$.\n\nIn our case and all the baselines, we employ two different types of compressors and therefore $T=2$. Without loss of generality, $t=1$ stands for 3:2 Compressor, and $t=2$ stands for 2:2 Compressor. Let $\\mathbf{p}\\in\\mathbb{N}_+^{N}$ denote the partial product array, which is a fixed matrix when given input bit-width and encoding circuit. For example, $\\mathbf{p} = [1, 2, 3, 4, 3, 2, 1]^\\top$ for a 4-bit AND multiplier as illustrated in Figure 1 in the main paper. All allocation matrices $\\mathbf{s}\\in\\mathbb{S}$ should satisfy the following constraints to ensure valid compressor tree reduction:\n\n$$\n\\begin{cases}\np_n - 2 s_{1,n} - s_{2,n} \\ge 1 & n = 1\\\\\\\\\np_n - 2 s_{1,n} - s_{2,n} + s_{1,n-1} + s_{2,n-1} \\ge 1 & n > 1\\\\\n\\end{cases},\n$$\n\n$$\n\\begin{cases}\np_n - 2 s_{1,n} - s_{2,n} \\le 2 & n = 1\\\\\\\\\np_n - 2 s_{1,n} - s_{2,n} + s_{1,n-1} + s_{2,n-1} \\le 2 & n > 1\\\\\n\\end{cases}.\n$$\n\nThese constraints guarantee that at each bit column, the number of remaining signals after compression is feasible for a prefix-adder.\n\n**2. How $\\mathbf{s}$ Interacts with the DAG and the Rest of the Framework**\n\nIn ARITH-DAS, the allocation matrix $\\mathbf{s} \\in \\mathbb{S}$ defines the architectural backbone of the compressor tree and **determines the search space for subsequent interconnection optimization**.\n\nOnce a valid $\\mathbf{s} \\in \\mathbb{S}$ is sampled by the Circuit Genetic Evolution (CGE) module, each compressor is assigned a stage number represented by $\\mathcal{S}\\in \\mathbb{N} _{+}^{S\\times T\\times N}$, where:\n\n$$\n\\sum_{i=1}^{S}\\mathcal{S} _{i,t,n} =\\mathbf{s} _{t,n}.\n$$\n\nThe number of remaining partial products at stage $i$ and column $n$ is then updated as:\n\n$$\n\\mathbf{P}_{i,n} = \\begin{cases}\np_n & i=1 \\\\\\\\\n\\mathbf{P} _{i-1,n} - 2 \\mathcal{S} _{i-1,1,n} - \\mathcal{S} _{i-1,2,n} & i>1,n=1\\\\\\\\\n\\mathbf{P} _{i-1,n} - 2 \\mathcal{S} _{i-1,1,n} - \\mathcal{S} _{i-1,2,n} + \\mathcal{S} _{i-1,1,n-1} + \\mathcal{S} _{i-1,2,n-1} & \\text{otherwise}\\\\\n\\end{cases}.\n$$\n\n$$\n\\mathbf{P} _{i,n} \\ge 0,\n$$\n\nwhere $\\mathbf{P} _{i,n}\\in \\mathbb{N} _+$ is the remaining partial products at stage $i$.\n\nIn our algorithm, we first greedily assign as many 3:2 Compressors as possible, and then assign 2:2 Compressors if needed. Since each compressor is associated with a specific stage number, **we enforce that compressors may only connect to compressors in the subsequent stages, thus forming a DAG (directed acyclic graph) search space**. This additional explanation will be added to Appendix C.3.2 in the revised version.\n\nThe DAG derived from $\\mathbf{s}$ enumerates the valid connection candidates among instantiated nodes. The interconnection optimization module then predicts fine-grained edges on top of this DAG under legality constraints (acyclicity, stage order, and port compatibility). Therefore, **$\\mathbf{s}$ determines the node set and connection options, thus constraining the fine-grained search space of ARITH-DAS**.\n\nIn summary, the allocation matrix $\\mathbf{s}$ defines the coarse-grained search space (compressor allocation) and establishes the structural foundation for the fine-grained interconnection search. We will add this clarification in the revised version to make the explanation more intuitive.\n\n---\n\n### **Weakness 2: Missing Critical Reference**\n> **There is one paper: Reinforcement Learning for Combinatorial Optimization [1] which might be associated with this submission**\n\nWe have carefully read the reference you provided and found it to be an excellent work that is **highly relevant to our study**. We have added a citation to this work in the **revised version of our paper**. Thank you again for bringing it to our attention!\n\n---\n\n### Reference\n\n[1] Darvariu, Victor-Alexandru, Stephen Hailes, and Mirco Musolesi. \"Graph reinforcement learning for combinatorial optimization: A survey and unifying perspective.\" arXiv preprint arXiv:2404.06492 (2024)."}, {"review_id": "Y8vhEx8Ecp", "reviewer": "Reviewer_tJhd", "summary": "Arithmetic circuit design is the basis of modern hardware platforms. A lot of works have aimed to design better arithmetic circuits, and they have focused on coarse-grained designs (compressor allocation in compressor tree). In the meantime, those works have relied on heuristics to design fine-grained parts. \n\nThis work proposes to optimize compressor interconnections, which is a fine-grained design of arithmetic circuits. It denotes compressor interconnection architecture as a graph, regarding compressors as nodes and connections between any two compressors as edges. By doing so, compressor interconnection becomes a link prediction problem that can be solved differentially with GNN and graph attention.\n\nHowever, there is a critical barrier to optimizing compressor interconnections with GNN. The search space of compressor interconnections is discrete, thus it is not suitable for solving the problem with neural networks. To resolve this issue, this work relaxes the discrete search space into continuous search space by denoting edges as softmax-based soft labels, instead of hard labels.\n\nWith the above proposals, the paper achieves Pareto-dominance results than other prior works.", "questions": "It seems that the compressor tree search part is based on MUTE. However, in the experiments in the appendix, the area of the circuits designed by the proposal is smaller than that of MUTE. Is there any difference between the two methods while searching compressor trees, or does it come from the stochasticity of the evolution-based method?", "limitations": "Yes", "rating": 4, "confidence": 2, "soundness": null, "presentation": null, "contribution": null, "strengths": "", "weaknesses": "", "quality": 3, "clarity": 2, "significance": 3, "originality": 2, "strengths_and_weaknesses": "Strengths\n- It is noticeable that propose to design arithmetic circuits differentiably based on GNN.\n- This work optimizes arithmetic circuit design by focusing on interconnections, which haven’t been addressed.\n- Search space relaxation tailored loss function for the problem leads to achieving state-of-the-art results for designing arithmetic circuits.\n- The paper supports the claim well with mathematic formulas.\n\nWeaknesses\n- It seems that the paper’s Compressor Tree design, which previous L2O works have aimed, is highly rooted in the previous work (MUTE).\n- If so, it would be better to demonstrate the effectiveness of the proposed interconnection design by integrating the proposal with other prior works.", "was_revised": true, "final_justification": "With the authors’ feedback and other reviews comments, the reviewer keep the rating of acceptance.", "rebuttal": "## Response to Reviewer tJhd\n\nWe sincerely thank you for your careful review and for your constructive, insightful, and valuable comments. Please find below our detailed responses to your inquiries.\n\n### **Weakness 1 & Weakness 2: Integrating with Prior Works**\n>  **It would be better to demonstrate the effectiveness of the proposed interconnection design by integrating the proposal with other prior works.**\n\nThank you for your valuable suggestion! In response, we have **integrated our proposed interconnection generation method into two representative learning-to-optimize arithmetic circuit optimization frameworks**: RL-MUL [1] and ArithTreeRL [2], and report the results in the table below.\n\n|  | 16bit-AND |  | 32bit-AND |  |\n|:---:|:---:|:---:|:---:|:---:|\n| Method | HV. | Impr. | HV. | Impr. |\n| ArithTreeRL | $315.19$ | NA | $2779.56$ | NA |\n| ArithTreeRL + Ours | $353.17$ | $+12.05\\\\%$ | $2811.92$ | $+1.16\\\\%$ |\n|  |  |  |  |  |\n| RL-MUL | $275.67$ | NA | $2600.24$ | NA |\n| RL-MUL + Ours | $309.07$ | $+12.11\\\\%$ | $2779.85$ | $+6.91\\\\%$ |\n\n**1. Why We Build Our Approach Upon MUTE**\n\nAs noted in the main paper, our method ARITH-DAS is implemented atop the MUTE framework. This decision is motivated by two primary considerations.\n\n**First**, MUTE represents one of **the most recent and competitive State-of-the-Art (SOTA) methods** for arithmetic circuit optimization. It provides a solid and well-maintained baseline, with strong performance across various circuit configurations, making it a reliable foundation for developing and benchmarking our proposed interconnection strategy.\n\n**Second**, **the evolutionary nature of MUTE is particularly advantageous for our learning framework**. Evolutionary methods inherently explore **a broader and more diverse design space** compared to purely gradient-based or heuristic approaches. This **diversity of intermediate designs** generated during the evolution process enables the collection of a larger and more representative training set, which is crucial for effectively learning a **generalizable and robust** interconnection policy. As a result, MUTE not only provides a strong backbone for implementation but also naturally facilitates the data-driven learning required by our method.\n\n**2. Integrating Our Interconnection Approach with Prior Works**\n\nAs demonstrated in the main paper, our method is **modular and compatible** with other learning-to-optimize frameworks as well. Specifically, we integrate our pre-trained model and corresponding interconnection generation strategy into **the full Verilog synthesis pipeline** of both RL-MUL and ArithTreeRL. RL-MUL is a Deep Q-Network (DQN)-based method that sequentially refines a pre-defined compression tree structure, such as a Wallace Tree, by making local decisions. In contrast, ArithTreeRL employs a Proxy-Policy Gradient approach to construct the entire compressor tree from scratch. **In both methods, the original handcrafted sequential interconnection policy is replaced by our *pre-trained* interconnection generator**. Notably, ArithTreeRL is already included as a baseline in our main paper.\n\nTo ensure fairness and tractability given limited compute resources, we evaluate both original frameworks and their integrated versions on two widely used multipliers, 16-bit and 32-bit AND multipliers. The results in the table above show that our interconnection design **substantially improves the hypervolume (HV) for 16-bit designs, and notably enhances the 32-bit designs as well**.\n\nWe attribute the larger gains in the 16-bit case to its smaller design space, where interconnection quality plays a more dominant role. In contrast, the 32-bit design space is much broader, and the relative impact of interconnect optimization is partially diluted by other factors. Nevertheless, **the improvements are consistent across both scales**, validating the **generalizability and effectiveness** of our method.\n\n---\n\n### **Question 2: Area Comparison with MUTE**\n> **Is there any difference between the two methods while searching compressor trees, or does the difference of area come from the stochasticity of the evolution-based method?**\n\n**1. Reason for the Better Area Metric of ARITH-DAS**\n\nOur method leverages the MUTE framework as the compressor allocation search engine, and we do not alter its evolutionary search algorithm. The difference observed in the area metric is **partially attributable to the inherent stochasticity** of the evolution-based search, which relies on randomized mutation and selection operations. Small variations introduced at intermediate generations may propagate through the search process, ultimately leading to different final designs.\n\nHowever, **the major factor underlying the area difference lies in the objective setting**. Both our method and MUTE adopt the same bi-objective optimization formulation:\n\n$$\n\\min_{\\mathcal{G}\\in\\mathbb{G}} - R(\\mathcal{G}) = w_1\\cdot \\operatorname{area}(\\mathcal{G}) + w_2\\cdot \\operatorname{delay}(\\mathcal{G}),\n$$\n\nwhere $\\operatorname{area}(\\mathcal{G})$ and $\\operatorname{delay}(\\mathcal{G})$ represent the synthesized area and delay of a compressor tree $\\mathcal{G}$, and $w_1, w_2$ control the trade-off. Because the objective function is a weighted sum, **a design with excellent area but suboptimal delay may be discarded during the search if its overall weighted cost is not competitive**. In our method, the pre-trained interconnection generator performs targeted optimizations that directly improve the delay of the generated compressor trees. This delay improvement increases the likelihood that certain candidates are retained and refined in later generations. Over multiple iterations, this mechanism shifts the distribution of surviving designs and may result in final circuits that are superior in both delay and, indirectly, area metrics.\n\nCompared with other methods that directly optimize the area metric alone, such as GOMIL and UFO-MAC, **neither MUTE nor our ARITH-DAS is guaranteed to always favor the design with the smallest area**. Instead, designs that strike a **better trade-off between area and delay** tend to be preserved and further refined by the evolutionary search.\n\n**2. Numerical Example**\n\nTo illustrate this more concretely, suppose $w_1=w_2=0.5$, and consider two candidate designs $A$ and $B$:\n\n- $\\operatorname{area}(A) = 2, \\operatorname{delay}(A) = 2, - R(A) = 2$.\n- $\\operatorname{area}(B) = 1, \\operatorname{delay}(B) = 4, - R(B) = 2.5$.\n\nUnder the combined cost function, design $A$ would be the preferred candidate for both MUTE and ARITH-DAS, despite its slightly larger area, because its overall weighted cost is lower.\n\nHowever, ARITH-DAS integrates a delay-aware interconnection generator, and the delay performance of candidate designs is further improved. For example, for the same compressor tree allocation with design $B$, ARITH-DAS optimized  interconnection topology and produces a new design $B'$:\n\n- $\\operatorname{area}(B') = 1, \\operatorname{delay}(B') = 2, - R(A) = 1.5$.\n\nNow, the improved design $B'$ achieves a much lower combined cost than $A$. As a result, ARITH-DAS would preserve $B'$ in the evolutionary search, whereas MUTE would have previously discarded $B$ due to its high delay. Over multiple iterations, this mechanism enables ARITH-DAS to retain and refine higher-quality solutions that strike a better balance between area and delay, ultimately leading to superior final designs.\n\n---\n\n### Reference\n\n[1] Zuo D, Ouyang Y, Ma Y. Rl-mul: Multiplier design optimization with deep reinforcement learning[C]//2023 60th ACM/IEEE Design Automation Conference (DAC). IEEE, 2023: 1-6.\n\n[2] Lai Y, Liu J, Pan D Z, et al. Scalable and effective arithmetic tree generation for adder and multiplier designs[J]. Advances in Neural Information Processing Systems, 2024, 37: 139151-139178."}]

Author rebuttal:

Meta-review: The final scores for the paper unanimously recommend acceptance. Although 2 out of 3 of them come with relatively low confidence, reviewer B7rW - after engaging in a very detailed discussion during the rebuttal - very explicitly voices his support for the paper with enough confidence to (in my opinion) diminish the uncertainty arising from the other reviews.

 For the sake of completeness, all reviewers agree that the proposed method is novel and practical, evaluation shows promising results, and the paper is clearly written and well-argued. As far as shortcomings go: all reviewers asked for clarifications with respect to some aspects of the paper and/or other works, all of which the authors were able to address. From the discussion with reviewer B7rW: the most important missing bit, that was added during the rebuttal, was closure timing experiments on the OpenROAD dataset, which the authors say have been incorporated into a revised paper. The results show diminishing returns in a complex setting, but not to the point where it would undermine contributions of the paper - I would urge the authors to accurately comment on these results and potential arising limitations.

Overall, I find sufficient reasons to recommend acceptance. In particular, I think the paper stands out due to its technical depth in combining two seemingly unrelated fields of differentiable search and circuit optimisation. Together with the in-depth evaluation covering both post-synthesis and full-flow scenarios (the latter coming from the rebuttal), I would consider it to be a particularly noticeable effort in exploring and characterising new directions. Whether this direction will stand the test of time, time will tell, but the submitted work deserves recognition, in my opinion.
Decision: Accept (spotlight)