Towards Next-Generation Logic Synthesis: A Scalable Neural Circuit Generation Framework
Authors: Zhihai Wang
Jie Wang
Qingyue Yang
Yinqi Bai
Xing Li
Lei Chen
Jianye HAO
Mingxuan Yuan
Bin Li
Yongdong Zhang
Feng Wu
Venue: NeurIPS 2024 poster (2024)
Keywords: Electronic Design Automation
Logic Synthesis
Neural Architecture Search
Primary area: machine_learning_for_other_sciences_and_fields

Abstract: Logic Synthesis (LS) aims to generate an optimized logic circuit satisfying a given functionality, which generally consists of circuit translation and optimization. It is a challenging and fundamental combinatorial optimization problem in integrated circuit design. Traditional LS approaches rely on manually designed heuristics to tackle the LS task, while machine learning recently offers a promising approach towards next-generation logic synthesis by neural circuit generation and optimization. In this paper, we first revisit the application of differentiable neural architecture search (DNAS) methods to circuit generation and found from extensive experiments that existing DNAS methods struggle to exactly generate circuits, scale poorly to large circuits, and exhibit high sensitivity to hyper-parameters. Then we provide three major insights for these challenges from extensive empirical analysis: 1) DNAS tends to overfit to too many skip-connections, consequently wasting a significant portion of the network's expressive capabilities; 2) DNAS suffers from the structure bias between the network architecture and the circuit inherent structure, leading to inefficient search; 3) the learning difficulty of different input-output examples varies significantly, leading to severely imbalanced learning. To address these challenges in a systematic way, we propose a novel regularized triangle-shaped circuit network generation framework, which leverages our key insights for completely accurate and scalable circuit generation. Furthermore, we propose an evolutionary algorithm assisted by reinforcement learning agent restarting technique for efficient and effective neural circuit optimization. Extensive experiments on four different circuit benchmarks demonstrate that our method can precisely generate circuits with up to 1200 nodes. Moreover, our synthesized circuits significantly outperform the state-of-the-art results from several competitive winners in IWLS 2022 and 2023 competitions.

Towards Next-Generation Logic Synthesis: A Scalable Neural Circuit Generation Framework
Zhihai Wang
Jie Wang" 1 Qingyue Yang'
Yinqi Bai'
Xing Li²
Lei Chen?
Jianye Hao 2.3
Mingxuan Yuan?
Bin Li!
Yongdong Zhang'
Feng Wu
MoE Key Laboratory of Brain-inspired Intelligent Perception and Cognition, University of Science and Technology of China Nooh's Ark Lab, Huawei Technologies CCollege of Intelligence and Computing, Tianjin University
Abstract
Logic Synthesis (LS) aims to generate optimized logic circuit satisfying given functionality, which generally consists of circuit translation and optimization. It is a challenging and fundamental combinatorial optimization problem in integrated circuit design. Traditional LS approaches rely on manually designed heuristics to tackle the LS task, while machine learning recently offers promising approach to- wards next gext-generation logic synthesis by neural circuit generation and optimization. In this paper, we first revisit the application of differentiable neural architecture search (DNAS) methods to circuit generation and found from extensive exper- iments that existing DNAS methods struggle to exactly generate circuits, scale poorly to large circuits, and exhibit high sensitivity to we provide three major insights for these challenges from extensive empirical analysis: 1) DNAS tends to overfit to too many skip-connections, consequently wasting significant portion of the network's expressive capabilities; 2) DNAS suffers from the structure bias between the network architecture and the circuit inherent structure, leading to inefficient search; 3) the learning difficulty of different input-output examples varies significantly, leading to severely imbalanced learning. To address these challenges in a systematic way, we propose novel regularized triangle-shaped circuit network generation framework, which leverages our key insights for completely accurate and sealable circuit generation. Furthermore, we propose evolutionary algorithm assisted by reinforcement learning agent restarting technique for efficient and effective neural circuit optimization. Extensive experiments on four different circuit benchmarks demonstrate that our method can precisely generate circuits with up to 1200 nodes. Moreover, our synthesized cir- cuits significantly outperform the state-of-the the- results from several competitive winners in IWLS 2022 and 2023 competitions.
Then
Introduction
Complex integrated circuits (ICs) can have billions of transistors, making purely human-based design impossible (. To tackle this problem, the IC industry relies on electronic design automation (EDA) tools [2] that progressively transform high-level hardware design into layout ready for IC fabrication. Logic synthesis (LS) is a fundamental step EDA which aims to transform a behavioral- level description of a design into optimized gete- circuit to minimize its delay and area. As
Thii work done when Zhihai Wang an intern Huawei. Corresponding author. Email: jiewangx @ uuuuccccc.ccm edu.en.
38th Conference on Neural Information Processing Systems (NcurIPS 2024).

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LS is the first step in EDA tool-chains that yields the final IC layout, the quality of its output highly impacts the area, power, and performance of the final ICs 3
LS is a challenging -PP-hard combinatorial optimization problem. Commercial and academic LS tools use sophisticated human-designed heuristics to approximately solve this task, often obtaining sub-optimal solutions. The synthesis of high-level designs to circuits is typically done as a direct translation of hardware description language code coupled with post-processing optimization. Recent works 7 have shown that there exists room for fusing these two steps with neural compiler architectures. Therefore, leveraging machine learning for direct neural circuit generation and optinization emerges as a significant direction towards next-generation LS.
In this paper, we first revisit the application of differentiable neural architecture search (DNAS) methods to synthesize circuits from input-output examples [5] g 7. which seems to offer a promising avenue towards neural circuit generation. Unfortunately, we found from extensive experiments that the existing method not only struggles to generate circuits precisely, particularly in large-scale circuits but also exhibits high sensitivity to hyperparameters. Through comprehensive empirical analysis, we summarize three key insights for these challenges. 1) DNAS suffers from the curse of skip-connections, tending to learn too many skip-connections, which results in low utilization of the large network. 2) there is discrepancy between DNAS and the inherent structure of circuits, leading to redundant search space and inefficient search. 3) the learning difficulties vary greatly across different input-output examples, resulting in a severe imbalance during the training process.
To address these challenges in systematic way, we propose novel regularized triangle-shaped circuit network generation framework, namely T-Net, which leverages our key insights for completely accurate and scalable circuit generation. To further enhance our T-Net for logic synthesis, propose an evolutionary algorithm assisted by reinforcement learning agent restarting technique for further efficient and effective neural circuit optimization. The efficient search and scalable circuit generation of our T-Net come from the following aspects. 1) Multi-Label Transformation of Training Data. To enhance the scalability, T-Net proposes partition the input-output examples into several sub- datasssss based on the Shannon decomposition theorem and merge these sub-datasets to transform the original single-label data into multi-labe data with significantly reduced input data. Jointly learning circuit structures of transformed onput-output examples also exploits inherent circuit functionality symmetry for logic sharing and reducing generated circuit size. 2) Triangle-Shaped Network Architecture. Based on the key observation that the circuit structure generally follows a shagle-shape, T-Net designs Triangle-shaped network architecture, which significantly reduces the search space, instead of common square-shaped architectures. 3) Regularized Training Loss. To mitigate overfitting to many skip-connections, T-Net proposes an inner-architecture regularized loss to suppress excessive skip-connections. Moreover, T-Net further proposes hardness-aware loss function to actively optimize hard input-output examples.
We conducted extensive experiments on 18 circuits from four benchmarks. For circuit generation, our T-Net accurately generates large circuits with up to 1200 nodes, surpassing the state-of-the-ar (SOTA)
DNAS methods( 99. while also producing much smaller circuits compared to traditional methods [10
Based on our generated compact circuits, our evolutionary algorithm further optimizes circuits, significantly outperforming not only traditional methods, but also SOTA approaches from several competitive winners IWLS 2022 and 2023 competitions.
11
We summarize our major contributions as follows. 1) An extensive analysis of the challenges inherent in applying Differentiable Neural Architecture Search (DNAS) for neural circuit generation was conducted, leading to three key underlying insights. 2) Leveraging these key insights, we developed T-Net, a neural circuit generation framework enabling efficient search and scalable generation. 3) Experiments on 18 circuits show that our approach achieves significant 68% improvement in circuit area over the traditional method, and a remarkable 5.36% improvement compared to the SOTA approach employed by the winners of the IWLS 2023 competition.
2 Related Work
Machine Learning in Logic Synthesis In recent years, integrating machine learning (ML) into chip design workflows has garnered significant attention [[22144. The investigation spans two main areas: MI embedded in LS and end-to-end LS using ML. techniques. ML embedded in I.S involves incorporating MI. into specific LS stages to enhance efficiency and quality. Notable efforts include using ML to tune optimization flows [5H17) predict metrics [4], and improve

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decision- decision-makingI.. 18 [9] in LS methods. ML for end-to-end LS includes research exploring replacing traditional LS stages with ML[]] Approaches range from language- based eircuit description (0 [2]
to circuit generation through searches S 7 Notable methods include integrating real- logic
with continuous parameterization and using differentiable neural architecture search (DNAS)
Despite the promising advancements, existing end-to-end methods face challenges in scaling to large circuits and are sensitive to hyperparameters. In this paper, we rethink the traditional DNAS methods for LS and propose novel regularized triangle-shaped circuit generation framework.
IWLS Contest The International Workshop on Logic & Synthesis (IWLS) B annually hosts a contest, with themes in 2022 and 2023 [22] focusing on LS from onput-output examples (i.e., truth tables), scored based on circuit sizes (i.e., node number). Participated teams mainly employ traditional methods [1 (3 26 for circuit synthesis. In 2023, Google DeepMind introduced a DNAS bbssed method 277. achieving first place. We replicated it as a baseline, conducting a detailed analysis and enhancing the ANAS-hasedd generation method. For circuit optimization, various operator sequence optimization approaches have been proposed [28] 29) The 2022 champion EPFL, team utilized Bayesian optimization methods within an EA framework (30]. In contrast, we employed RL methods with strong search capabilities and introduced a restart strategy to mitigate local optima.
Background
Logic Synthesis (LS) from 10 Examples In recent years, a promising direction that synthesizing circuits from IO examples has received increasing attention [27 31 32 7). Specifically, researchers aims to use machine learning to generate circuit given truth table that describes the functionality of the circuit. Note that each line in the truth table is an uuput-output pair, which means that given the input to the circuit it will produce the corresponding output. For machine learning (ML) domain, researchers formulate the truth table as a training dataset consisting of many input-output pairs, and aim to use a ML model to generate circuits that completely fits the dataset.
Circuit Graph Representation Boolean Networks are widely-used discrete mathematical models with applications in various fields (33. In these networks, nodes represent Boolean functions, and edges illustrate connections between them. Boolean functions map from an n-dimensional space 8" to a I-dimensional space B. where B = {0, 1]. In the LS stage, circuits are often depicted as And-Inverter Graphs (AIG), offering a concise representation of Boolean Networks. AIGs consist of constant, primary inputs (Pls), primary outputs (POs), and two-input And nodes. Inverter edges signify an inversion signal. The size of a circuit denotes the number of And nodes in the AIG, while the depth (level) signifies the longest path from a PI to a PO.
propose to leverage DNAS methods for generating circuit graphs from 10 examples, which shows a promising direction towards next-generation logic synthesis. Specifically, they formulate neural network circuit graph (i.e., AIG), where each neuron represents a logic gate (And gate) and connections between neurons represent wires connecting these logic gates. For a parameterized neural network, the neurons are fixed as logic gates, and the connections between neurons are parameterized as learnable parameters. To enable differentiable training via gradient descent, they introduce continuous relaxation into discrete components in the neural network. First, the logical operations of logic gates (neurons) are translated into their differentiable counterparts. For instance, a AND b is relaxed to a b, and NOT is relaxed to 1 - a ( Second, discrete network connections are parameterized, employing Gumbel-softmat (34 during forward propagation to continuousize and sample the connections between nodes, thus enabling optimization through gradient descent to find high-quality solutions.
Traditional DNAS for LS from I0 Examples Recent works
4 Rethinking DNAS for Neural Circuit Generation
In this section, we first present motivating challenges in using DNAS for neural circuit synthesis from input-output examples in Section Then, we present a deep understanding of these challenges in Section 4.2
We provide the detailed experimental setup in Appendix (B.3
4.1 Motivating Challenges
We present two fundamental challenges in neural circuit generation of existing DNAS First, DNAS struggles to generate circuits exactly from input-output examples, especially for large-scale circuits. Second, DNAS exhibits high sensitivity to hyperparameters.
3

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surpett
Hesttong of counectel uctrock
Japa
Tsua Keo
Logiche
Duralies
Mide
Clrcut Loval
(a)
(b)
(c)
(d)
Figure I: (a) DNAS struggles to accurately generate eircuits, especially larger ones. (b) The depth of an output node of the circuit in the circuit. DNAS only connects to very shallow layers, while our method learns deeper layers. (c) The visualization of the converged DNAS network. The dark nodes represent the used circuit nodes, indicating very low utilization of deep-layer nodes. (d) The circuits generated by SOP show that the average number of nodes per layer forms a triangular pattern.
Generating Exact Circuits is Challenging To evaluate whether DNAS can generate circuits exactly, we evaluate the DNAS method as described in Appendix B. and Cn the input-output examples from circuits in two benchmarks. Figure shows that out of the 16 circuits, 14 can not be generated correctly. Therefore, it is extremely challenging for DNAS to generate functionally correct circuits.
Moreover, Figure a) illustrates the relationship between circuit accuracy and circuit scale. The metric for circuit scale is quantified by the number of AIG nodes obtained through the traditional synthesis method. The results reveal nearly 20% degradation in circuit accuracy as the circuit scale increases. This demonstrates the challenge that DNAS confronts in generating accurate circuits as the circuit scale grows, highlighting the poor scalability of the DNAS method.
Sensitivity Hyperparameters We evaluate robustness of DNAS in eircuit generation using various initializations. Results showed up to a 14.5% accuracy variation depending on the random seed, highlighting the challenge of obtaining stable results with DNAS. More details in Appendix C.2
4.2 A Deep Understanding of These Challenges
To elucidate the underlying causes of these challenges, we undertook comprehensive analytical experiments, which yielded the following three key insights. Firstly, DNAS suffers from the curse of skip-connections, tending to learn too many skip-connections, which results in low utilization of large initialization networks. Secondly, there is discrepancy between DNAS and the inherent structure of circuits, leading to an inadequate exploration of the search space. Lastly, the varying learning difficulties among input-output examples cause an imbalance in the training process.
The Curse of Sxip-Connection We observed that existing methods exhibit low utilization of the network when searching within large network. This is attributed to the fact that connections can span across layers, bypassing certain nodes and excluding them from the final circuit. To investigate this, analyzed how the skip connections evolve during training. The output nodes of a circuit are selected within the network through a set of Iearnable connection parameters. To study the cross-layer connection phenomenon of the outputs, we observe the depth of the output nodes within the network. Figure [bb) shows the fluctuation in the depth of an output node during training. It is evident that the depth of the circuit output node undergoes rapid decline nearly 0, followed by a gradual rise and eventual stabilization at a shallow depth of 5. This observation implies that only a fraction of the network layers, specifically about a quarter, effectively utilized in the circuit. The skip connections within the circuit span a considerable depth, significantly constraining the upper limit of the network's expressive capacity. As point of contrast, our approach connects this output to layer 15, allowing for the full utilization of nodes.
Existing methods underutilize large networks because connections can span across layers, bypassing certain nodes and excluding them from the final circuit. To investigate this, we analyzed how skip connections evolve during training. We observed the depth of output nodes within the network to study cross-layer connections. Figure Fig depicts the depth fluctuation of an output node during training. The output node's 's depth initially drops sharply to almost O, then gradually rises and stabilizes at a shallow depth of 5. This indicates that only about a quarter of the network layers are effectively utilized. Our approach connects this output to layer 15, enabling full node utilization.
To further illustrate the circuit structure searched by DNAS, we visualized the positions of circuit nodes within the network in Figure [c). Notably, this circuit has multi-outputs, resulting in layer

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Truth Tublec
Partition X;
Triangle Shaped Architecture
Input
Inpei
Predict Ousput Output
3
Multi Label
D
BB
D
B
0,9
D
0.6
0
Toper
1
0
Hardaess-Aware
0
3
Weighted Regularized Residual Connection
Rogularization
Mutti-Label Transformation of Training Data
Ttipeg Architettee
Regularfird Training
lowards and Search
Figure 2: Framework of the Regularized Triangle-Shaped Circuit Network (T-Net). Our proposed T-Net consists of three key modules: 1) Multi-label transformation of training data to decrease generation difficulty. 2) A shangle-shaper network architecture, designed to align with the structural biases inherent in logic circuits. 3) Regularized training loss for efficient search and exact generation.
configurations distinct from those in the single-output case shown in Figure [b). It can be observed that only subset of bottom- nodes is integrated into the circuit, with about two- two-thirds of the nodes being left idle due skip connections. This visual representation demonstrates that excessively distant skip connections diminish node utilization and the expressive capacity of the network.
We have noted that DNAS shows restricted exploration of the network during training. Specifically, node is classified as explored if it is included in the discretized circuit at any point during training, and exploration is defined as the ratio of explored nodes total nodes in the network. It is evident that exploration is more extensive in shallower layers, decreasing as the layers deepen, as illustrated in Appendix C This finding prompts us investigate whether structural bias within the circuit architecture is responsible for imbalanced exploration. Furthermore, we observed that the skip-layer count of the output bits is highly influenced by the hyperparameter random initialization, exhibiting significant fluctuations. This sensitivity highlights that the accuracy of circuit generation is extremely responsive to hyperparameters. During the training process, the occurrence of extensive skip-layer phenomena is attributed to the fact that choosing skip-connection leads to most rapid error decay during optimization. The network tends to learn skip-connection rather than traversing through more nodes. This is known as the curse of skip-connections, mentioned in 35 36).
The Structure Bias of Circuits To further investigate the structural bias in eircuit design, we examine the structure of circuits generated by traditional methods. Utilizing Sum-of-Produceh (SOP) in ABC synthesis cireuits, we analyze and quantify the node distribution across different layers. Figure d) presents the average node count distribution structural pattern: the circuits are wider in the bottom layers and become narrower the deeper layers, suggesting inherent structural preferences in circuit designs. This is inconsistent with the commonly used rectangular network shape. Utilizing a rectangular network to learn circuit structures may result in a vast, redundant search space in the deep layers, leading to optimization difficulties. Consequently, this can lead to sensitivity to hyperparameters and lower accuracy.
layer in circuits. This reveals distinct
Learning Difficulties of Different Input-Output Examples We have observed that the learning difficulty varies among different output bits and input combinations. The training loss of different output bits shows different convergence speeds, indicating variations in difficulty. For inputs, the convergence speeds for different input samples on the same output bit exhibit substantial variations. challenging the assumption of independent and identically distributed (IID) samples. Detailed experimental results are in Appendix C.2
A Regularized Triangle-Shaped Circuit Network Generation Framework
To address the aforementioned challenges, we have developed novel Regularized Circuit Network Generation Framework, namely T-Net. Our method comprises three modules: multi-label transformation of training data, a triangle-shaped network architecture, and regularized training loss for efficient search and exact generation. Moreover, we propose an evolutionary algorithm assisted by reinforcement learning agent restarting technique for efficient and effective neural circuit optimization. We defer more implementation details to Appendix D
5

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5.1 Multi-Label Transformation of Training Data
To address the scalability challenge posed by the exponential growth of truth tables with increasing input bit widths, we propose a novel approach: the multi-label transformation of training data, leveraging the Shannon decomposition theorem [37]. The Shannon decomposition theorem states that any boolean function (truth table) can be decomposed into two sub-functions (sub-tables) by selecting decomposing variable. Formally, the theorem is expressed as:
f(X1..... X..) = X, fi|x,=1 + (IX;) f2px==0
where f denotes the original boolean function, X; denotes the selected variable, fixx,- and fa x denote the decomposed fub-functions. Based on the key observation that the truth table exhibits a duality of Boolean functions, we first partition a large truth table into two smaller sub-tables by selecting variable and fixing its value 0 and 1, respectively.
After partitioning the truth table, a natural approach is to Iearn each sub-table separately. However, since the decomposed sub-tables share many logical nodes, individual learning prevents the active learning of these shared logical nodes. To overcome this challenge, we propose a multi-label data merge mechanism, which merges the two sub-tables into a multi-output table. This results in doubling the output number while halving the input number.
By recursively applying this partition cwwloon--nnd-mae and-merge transformation, we can transform any large truth table into another truth table with significantly reduced input numbers and increased output numbers. Note that the input size significantly impacts the difficulty of neural circuit generation. Consequently, this transformation strategy provides two major advantages: 1) It enhances the scalability of our T-Net, enabling it to learn from truth tables with large input bit widths. 2) It significantly accelerates the learning process, as the learning difficulty of sub-tables is considerably reduced.
5.2 Triangle-Shaped Network Architecture
Model Structure Our network is structured as a neural network, where the neurons represent two- input NAND gates. During training, the neurons remain fixed while their connections are learned. An And-Inverter Graph (AIG) is a logic circuit composed of NAND gates and wires connecting the gates. By transforming the neurons and connections in the neural network into logic gates and wires, the neural network can be converted into AIG circuit. Inspired by 75, our basic differentiable circuit neural network structure is as follows. The network has depth L and width K, indicating that it consists of L layers, each comprising K nodes. In this notation, / = 0 corresponds to the input of the circuit and 1 = L + 1 are the outputs. It is crucial to emphasize that the nodes in the output layer (L + 1) are not considered gates; instead, they select the node within the network implementing the output signal. The network's 's inputs and outputs mirror the signals of a logical circuit, consisting of Os and 1s. Our nodes has two inputs and one output as NAND gate. We denote the output of the ttth neuron in the 1th layer by o.k We denote the p-th input of the neuron (NAND) gate) o by A,A where p E {0, 1}. During the training phase, the discrete logic circuit undergoes a relaxation and continuousization process in two aspects. Firstly, the logical operations of logic gates are translated into their differentiable counterparts. For instance, a NAND 6 is relaxed to 1 (a b) 6). Next, discrete network connections are parameterized, employing Gumbel-softmax 34 during forward propagation continuousize and sample the connections between nodes, thus enabling optimization J,.k through gradient descent. Note that each neuron o has two inputs 10 and 2. and can be connected to any neuron with layer number smaller than I as its input neuron. We parameterize the connections of each neuron o². by a tensor of learnable parameters 0l.k E =X=xx(- Each parameter in the tensor gl.k represents the probability of connecting the jth neuron in the 7th layer to the pth input of current neuron ol.k The computation of the pth input value for the neuron o/h takes the form of
1-1
K
softmax (ol p.1s P = 0,1
(d.*))
(2)
1=
d : 1
L
(3)
During evaluation, each node's input selects only one connection based on the parameters, using maxinization instead of softmax during forward calculatior restoring discrete logic operations. Triangle-Shape To fit the circuit bias on structure, we propose Triangle-shaped network structure. Due to the inherent structural preference of logic circuits for wider base and deeper top, the

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commonly used rectangular network architecture is not well-suited for them. We employ triangular structure that widens the bottom layers to enhance expressive capability, thereby better fitting the foundational aspects of logic circuits. At the deep layers, the structure is narrower and deeper, which ensures adequate expressive power while reducing redundant nodes. This streamlined search space simplifies optimization, making it more manageable and efficient. Importantly, the last layer's width doesn't 't limit output diversity since any node can serve as an output. Our experiments confirm accurate generation even for circuits with many outputs (see Appendix E.4
5.3 Regularized Training Loss towards Efficient Search and Exact Generation
Regularized Coii-Connection Note that for each node in the T-Net, it maintains learnable prob- ability distribution over all nodes in the T-Net whose layer number is smaller than this node. As shown in Figure [b), this distribution often overfits to shallow-layer nodes, causing too many skip connections. To prevent this, a natural solution is to enforce connections only to nodes in the previous layer. However, this significantly limits the search space, reducing expressive power (as demonstrated in the DNAS with no skip-connection in Table T). To address this challenge, we propose a weighted regularization on the learnable probability distribution softly suppress the probability of connecting to distant nodes across layers, while promoting connections to closer nodes. This approach avoids overfitting excessive skip connections. Due to limited space, we defer the specifics of the weighting implementation to Appendix D.2
Boolean Hardness-Aware Loss To alleviate the problem of extreme imbalance between positive and negative samples in the later stages of training, we introduce Boolean Gordnees-Awaan Loss inspired by [38]. By weighting loss differently for various samples, these components help maintain training speed in the later stages. We also employed a temperature coefficient decay mechanism to reduce the discrepancy between continuous computation during training and discrete testing.
5.4 Neural Circuit Optimization
In this section, we introduce a novel optimization framework combined with our generation methods for comprehensive logic synthesis approach. To optimize circuits, use circuit equivalent transformations called operators, whose order and parameters significantly affect results. The goal is to find an optimal operator sequence that minimizes the circuit's size. Our method is evolutionary algorithm optimization framework assisted by reinforcement learning with a restart strategy. The framework and more details can be seen in Appendix D.5
Reinforcement Learning for Operator Sequence Optimization Inspired by [39, our environment consists of the circuit, the logic synthesis tool ABC40) and nine logic optimization operators. The agent receives the circuit state from the environment and outputs the next action, which includes an operator and its parameters. This operator is then applied to the circuit, resulting in the next circuit state. Ultimately, the RL model learns the optimal sequence of operators for the circuit, which is then used to optimize the circuit and hand it over to the EA.
RL Agent Restart Strategy. After a period of training, the agent parameters may converge and performance may settle into local optima. To address this, we restart the network parameters after a certain training period. Specifically, we reinitialize the agent parameters and recommence training using the optimal circuit while retaining the agent's encoder parameters. This helps escape from local optima and allows continued exploration of the search space for superior solutions. Retaining the encoder parameters preserves learned experiences, guiding subsequent training iterations.
Evolutionary Algorithm Optimization Framework. To better escape local optima, our optimization approach incorporates an Evolutionary Algorithm (EA) framework. The initial population consists of diverse circuits generated by our T-Net. To ensure that the generated circuits closely match functionality constraints with truth tables, we implement a legalization step to ensure functional compliance, as detailed in Appendix D.6 Subsequently, the EA iteratively optimizes circuits by the RL model and maintains an elite circuit population. Finally, the optimal circuit is selected as the output. Compared with only picking one optimal solution when restarting, EA can increase the diversity of the circuit and expand the search scope. A detailed procedure is in the Appendix D.5
Experiments
Our experiments have four main parts. 1) Evaluate our generation and optimization approach on four open-source circuit benchmarks. 2) The scalability of our generation method. 3) Perform carefully
7

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Table 1: Generation accuracy results. Impr. is the percentage decrease in wrong bits.
Beuchmark
Basic DNAS
DNAS Skip
Darts-
T-Net (Ours)
Circuit
Acc
Wrongs|
Acc.(%)
Wrongs!
Wrongs
Wrongl
Impe(())
Espressu3
28
99.21
99.77
74
74
100
D
100
Eapresso4
16
70.99
1900X
100
77.44 44
14784
100
D
100)
Small
Papresso7
LogicNetsl
63
96.78
97.83
395
149
92.80
90.30
1564
885
97. 16
96.23
458
463
100
100
D
0
100
100
Randoral
64.06
98.73
362
Arilhmetic2
81:47
332
99.22
75.61
437
100
0
100
EspressoB
14
8
81.13
20797
86.86
17223
97.66
3056
100
0
100
Large
LogieNets4
Eapressu9
14
79.17
93.82
14167
81.36
87.79
42756
97.29
83.77
6196
1994
99.99
12
99, 99.99
LogieNetof
12
65.34
4259
83.26
2057
96.05
485
100
100
Average
82.51
3974.33
91.99
3995.11
86.31
1938.00
99.99
1.89
99.91
Table 2: Generation size results. Init Node is generated by SOP T-Net and Opt Node is optimized by resyn2. Impr. represents the percentage decrease in nodes achieved by our approach.
Benchmark
SOPsresyn2
Ourseresyn2
Size
Circuit
PI
PO
Init Node
Opt Node
Init Node
Impr((%)]
Opt Node
Imprs 5%
Espresso3
5
28
205
149
155
24.39
136
8.72
Espressoi
16
129
66
37
71.32
27
59.09
Small
Espresso7
334
30.71
275
LogicNetsl
12
194
160
160
17.53
1410
12,50
Randon]
10
168
116
117
30,36
105
9.48
Ardhmetic2
316
268
254
19.62
236
11,94
Espresso8
207
151
Espressu9
14
1221
989
564
55.56
150
$4.50
Large
LagicNets4
12
808
670
636
21.29
601
10.30
LogicNeto6
12
966
796
374
61.28
350
56,03
Average
366.39
262.78
33.42
230.06
designed ablation studies to provide further insight into the DNAS- circuit generation approach. 4) Verify the robustness of our approach through sensitivity analysis.
Benchmarks We evaluate our approach using circuits from four benchmarks: Espresso 41], LogicNets(42), Random, and Arithmetic. Random eircuits are random and decomposable Boolean functions, while Arithmetic circuits involve arithmetic functions with permuted inputs and dropped outputs. We selected 18 circuits (8 circuits are in Appendix E and the average are calculated by all 18 circuits), with inputs ranging from 7 to 16 and outputs from I to 63. Circuit sizes, based on node count synthesized through the SOP method, range from 100 to 1200. The circuits are divided into small (12 circuits, node count < 500) and large (6 circuits, node count > 500) datasets, highlighting synthesis challenges, especially for the large circuits.
Experimental Setup For circuit generation, we implemented our T-Net as in Section 5 We train our model on all input-output pairs of each circuit and evaluate their Boolean correctness. For circuit optimization, we use the RL model inspired by (39] and our EA framework. We conduct the I.S operator sequence by open-source logic synthesis tool ABC [40]. Implementation details, hyperparameters, and hardware specifications can be found in Appendix
Baselines We compare our T-Net with the following generation approaches: 1) Basic DNAS: Based on (6), it learns connections but lacks skip-layer connectivity. 2) DNAS Skip: Proposed by Belcak et [5. and used by Google DeepMind in IWLS 2023 [22]. We re-implemented this method with Gumbel-Softmat as Google did not open-source their code. 3) Darts- An improvement on DNAS that addresses skip-connection issues in traditional NAS task(9] We adapted it for circuit neural networks. 4) SOP
Porduuucts-or:::: A traditional LS method. We used resyn2 43 to optimize circuits synthesized by SOP and our T-Net, showing our method's superior initial solutions. On the other hand, the baselines for optimization include: 1) SOP with resyn2: Traditional LS method with the resyn2 operator. 2) IWLS Competition Results: We compare with the top three teams from 2312 and 2023 These teams mostly used extensive traditional methods, while EPFL employing Bayesian optimization 30) and Google using the DNAS circuit generation method
Evaluation Metrics We evaluate the accuracy and the size of the generated circuits and optimized circuits. 1) Accuracy: The ratio of correctly predicted output bits to the total number of output bits. Importantly, achieving 100% accuracy in the generated logic circuit stands as a fundamental criterion in the task of logic circuit synthesis. 2) Wrong Bits: The number of incorrectly predicted output bits, used to highlight accuracy differences in large-scale circuits. 3) Circuit Node/Size: The number of nodes in the generated AIG circuit, with fewer nodes being better for minimizing chip area.
8

---

Table Optimization results. The term 'Impr' is defined as the percentage decrease in the number of nodes achieved by our approach, relative to the traditional configuration.
Benchmark
Trudition
2022 Teams
Ours
Size
Circuit
P
PO
SOP+regn2
TUW
UCB
EPFL(AT)
NBU
EPFL(AI)
TUW
Google(AD | (Opl Node
Imprs St
Espressad
28
149
77
58.
79
70
72
69
55,60
Espressot
16
1
66
25
25
25
25
25
25
25
25
62:12
Small
LagieNessl
Espresso7
12
63
3
296
160
147
69)
151
70
152
72
146
65
148
62
138
60
141
139
55
53.04
65.63
Randomi
116
39
52
44
38
37
68.10
Anthisetic2
105
Espreso88
Large
Espresso9
NogicNets4
77.01
LogicNeb6
12
796
390
281
208
152
166
106
90
88.69
Average
380.29
132.78
118.33
112.28
134.11
113.89
94.39
88.06
83.33
68.70
6.1 Comparative Evaluation
Generation Evaluation We evaluate generation accuracy and wrong bits across four datasets. The results in Table I show that T-Net significantly outperforms all baselines, achieving 100% accuracy on most eircuits and at least 99. 9% on all. T-Net shows an average accuracy improvement of 17.48% over Basic DNAS and 8% over DNAS Skip. Our approach for circuit neural networks also significantly outperforms general DNAS improvement methods like Darts-. Regarding wrong bits, even with similar accuracy, T-Net shows significantly fewer errors. For instance, in Espresso9, our method reduces wrong bits by 42,000. These results demonstrate the superiority of our approach.
In addition, we evaluate the generation circuit size and the optimized size after applying traditional operators. The results in Thhw that our method significantly outperforms the SOP method in initial node count, with an average improvement of 33.42%. Furthermore, circuits with fewer initial nodes also exhibit better optimization outcomes, with our method showing an average improvement of 23.72% in optimized nodes compared to traditional methods. Notably, for circuits with initial node improvements over 82%, we achieve up to 84.3 84.35% improvement in optimized nodes. These results highlight the effectiveness and superiority of our approach.
Optimization Evaluation We evaluate our proposed optimization framework, as shown in Table By integrating our circuit generation method, we significantly reduced circuit size by 68.70% compared to the traditional SOP+resyn2 method, demonstrating our optimization approach's 's effectiveness. Additionally, our average size outperformed the 2022 first-place team, EPFL, by 25.78 25.78%, and the 2023 first-place team, Google, by 5.36%, significantly ahead of other teams. This highlights the superiority of our generation method and optimization framework in better circuit synthesis.
6.2 Scalability
To validate our multi-label transformation's 's effective- ness in improving accuracy, efficiency, and reducing circuit node count, we tested large circuits from the LogicNets and Espresso datasets. We use SOP to quickly test the truth table transformation method with different bits and select the bits with the small- est size. For LogicNets6, we decomposed it into four parts using two inputs. For Espresso9, we split the truth table into two parts.
Table 4: Scalability results of transformed truth table on large circuits.
Method
Nodes]
Timethij
Acc(%)"
Wrs.]
Default
613
29
99.60
d9
LogiNNes6
Decomp.
374
14
100
0)
Impv.
39%
41%
0.4
100%
Default
699
26
99.97
Espresso9
Decomp.
610
Impv.
13%
38%
0.02
90%
The experimental results in Table show a 90% re-
duction in wrong bits and an average 26% decrease in nodes after transformation. For LogicNetsó, the method reduced generation time by 41 %. These results confirm the efficiency of our decomposition method for large circuits. By isolating complex variables, we mitigate circuit generation complexity, enhancing scalability. Despite doubling the number of output bits, our T-Net maintains high accuracy, indicating its robustness to increased output bits.
6.3 Ablation Study
In this section, we conducted an ablation study on four circuits to understand the contributions of each T-Net component. Our T-Net adds three modules to DNAS: regularized skip-connection, boolean
hardness aware loss, and T-Net, abbreviated in Table 5 as con., loss, and T, which leads to three main

---

Table 5: Ablation results four benchmarks of circuit.
Expresso5
Large: LogicNes2
Artimeeic
Weings]
Asx:190]
Weorgs
Asc-1901
Weings
Wonngs
SUP
NA
NA
N4
NA
252
NA
NA
12
NA
168
bacciie
93.04
277
145
17
79.43
2525
2
94.97
90
193
13
95.73
13
14]
4com
98.24
18
188
19
99.91
10
341
17
99.31
02
276
14
99.40
123
1000-loss
100
18
100
251
100
0
253
15
100
155
4c0e -itss
conclusions. Compared the baseline, the con. significantly enhances accuracy, highlighting the effectiveness of the regularized skip-connection module in mitigating skip-layer degradation and improving network expressiveness. 2) The con. clos+loss approach nearly doubles the reduction in wrong bits compared to +con., showing that the boolean hardness-awe aware loss function significantly boosts accuracy for challenging instances. 3) con. +loss+ improves both accuracy and node count, indicating that T-Net reduces training difficulty and enhances circuit generation effectiveness.
6.4 Sensitivity Analysis
We validate the sensitivity of our method to hyperparameters from two perspectives: random initial- ization and the initial size of the network. Experiments show that our approach uniformly maintained 100% accuracy across various random initialization and network initial sizes, underscoring its robust- ness to these fluctuations. Please see Appendix E.3 for details.
7 Conclusion
We rethink existing DNAS methods and empirically show three fundamenttll challenges pertaining to existing methods: DNAS tends overfit to too many skip-connection: 2) DNAS suffers from the structure bias between the network and the circuit's 's inherent structure, leading to inefficient search; 3) imbalanced learning across different input-output examples. Based on these insightful observations, we propose noval neural logic gate network search framework, which has a Trangle-shaped structure, regularized skip-connection, and boolean hardness aware loss function. Experiments on four circuit benchmarks demonstrate that our method can precisely generate circuits with large AIG sizes. Moreover, our generated circuits have significant 68% improvement area surpassing the performance of the traditional method.
Acknowledgments
We would like to thank all the anonymous reviewers for their insightful comments. This work was supported in part by National Key R&D Program of China under contract 20227D01 19801, National Nature Science Foundations of China grants U23A20388, and 62021001. This work was supported in part by Huawei well.
10

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References
[1] Guyue Huang, Jingbo Hu, Yifan He, Jialong Liu, Mingyuan Ma, Zhaoyang Shen, Juejian Wu, Yuanfan Xu, Hengrui Zhang, Kai Zhong, et al. Machine learning for electronic design automa- tion: survey. ACM Transactions on Design Automation of Electronic Systems (TODAES), 26 (5):1-46, 2021.
[2] Laung-Terng Wang, Yao-Wen Chang, and Kwang-Ting Tim Cheng. Electronic design auloma- lion: synthesis, verification, and test. Morgan Kaufmann, 2009.
[3] Brunno A De Abreu, Augusto Berndt, Isac S Campos, Cristina Meinhardt, Jonata T Carvalho, Mateus Grellert, and Sergio Bampi. Fast logic optimization using decision trees. In 202/ IEEE International Symposium Circuits and Systems (ISCAS), pages 1-5, IEEE, 2021.
[4] Augusto André Souza Berndt, Mateus Fogaça, and Cristina Meinhardt. A review of machine learning in logic synthesis. Journal of Integraled Circuits and Systems, 17(3): 2022.
[5] Peter Belcak and Roger Wattenhofer. Neural combinatorial logic circuit synthesis from input- output examples. In 2nd Workshop on Math-Al (MATH-Aι@ NeurlPS). arXiv, 2022.
[6] Felix Petersen, Christian Borgelt, Hilde Kuehne, and Oliver Deussen. Deep differentiable logic gate networks. Advances in Neural Information Processing Systems, 35:2006-2018, 2022.
[7] Google DeepMind.
Computer Systems with More https://deepmingg www.h///goooooooooooooooooooo //imeect////////// optimizing-compann cysoppute--ssttemseeeee with more - 2023.
Optimizing
Generalized AI Tools.
[8] International Workshop Logic & Synthesis. https://www. https://ww..wvls.crgg wtwp://wws..rggwwi..
2024.
[9] Xiangxiang Chu, Xiaoxing Wang, Bo Zhang, Shun Lu, Xiaolin Wei, and Junchi Yan. Darts-: robustly stepping out of performance collapse without indicators. arXiv preprint arXiv:2009.01027 2020.
[10] Shin-ichi Minato. Fast generation of irredundant sum-of-products forms from binary decision diagrams. Proc. SASIMI 92, pages 64-73, 1992.
[11] Janusz Rajski and Jagadeesh Vasudevamurthy. The sition and factorization of boolean expressions. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 11(():778-75) -73,, 1992.
concurrent decompo-
[12] Azalia Mirhoseini, Anna Goldie, Mustafa Yazgan, Joe Wenjie Jiang, Ebrahim Songhori, Shen Wang, Young-Joon Lee, Eric Johnson, Omkar Pathak, Azade Nazi, et al. A graph placement methodology for fast chip design. Nature, 594(7862)200-2111 2021.
[13] Hung- Yi Liu and Luca P. Carloni. On learning- methods for design-space exploration with high-level synthesis. In 2013 50th ACM/EDAC/EEF Design Automation Conference (DAC), pages 1-7, 2013.
[14] Walter Lau Neto, Matheus Trevisan Moreira, Luca Amaru, Cunxi Yu, and Gaillardon. Read your circuit: leveraging word embedding to guide logic optimization. In Proceedings of the 26th Asia and South Pacific Design Automation Conference, pages 530-535, 2021.
[15] Synopsys. Design space optimization ai, 2020. URL chip-design/dso.. dso-di.....ooooooo ai.mmm
[16] Cadence. Cadence cerebrus. 2021. URL wtw.gg/o/oooocimmmmaaaaaatroaaaa tools chip--ntttllggtttc--------p---
[17] Zhihai Wang, Lei Chen, Jie Wang. Yinqi Bai, Xing Li, Xijun Li, Mingxuan Yuan, Jianye Hao, Yongdong Zhang, and Feng Wu. A circuit domain generalization framework for efficient logic synthesis chip design. Ruslan Salakhutdinov, Zico Kolter, Katherine Heller, Adrian Weller, Nuria Oliver, Jonathan Scarlett, and Felix Berkenkamp. editors, Proceedings of the 4/ International Conference on Machine Learning, volume 235 of Proceedings of Machine Learning Research, pages 50163-50207. PMLR, 21-27 Jul 2024.
11

---

[18] Walter Lau Neto, Matheus T Moreira, Yingjie Li. Luca Amarü, Cunxi Yu, and Sarre-Emmnuuel Gaillardon. Slap: a supervised learning approach for priority cuts technology mapping. In 2021 58th ACM/IEEE Design Automation Conference (DAC), pages 859-864. IEFF, 2021.
[19] Walter Lau Neto, Xifan Tang, Max Austin, Luca Amaru, and Improving logic optimization in sequential circuits using majority-invert graphs. In 2019
Gaillardon.
IEEE Computer Society Annual Symposium on VLSI (ISVLSI), pages 224-229. IEEE, 2019.
[20] Frederik Schmitt, Christopher Hahn, Markus N Rabe, and Bernd Finkbeiner. Neural circuit synthesis from specification patterns. Advances in Neural Information Processing Systems, 34: 15408-15420, 2021.
[21] Frederik Schmitt, Matthias Cosler, and Bernd Finkbeiner. Neural circuit synthesis with pre- trained language models. In First International Workshop on Deep Learning-atee aaddd Verification, 2023.
[22] International workshop on logic & synthesis contest. https://wwat 2024.
[23] Priyank Kalla, Zhihong Zeng, Maciej J Ciesielski, and Chilai Huang. A bdd-based satisfiability infrastructure using the unate recursive paradigm. In Proceedings of the conference Design, automation and test in Europe, pages 232-236, 2000.
[24] AMY Miyasaka and M Fujita. A simple bdd package without variable reordering and its application to logic optimization with permissible functions. In Proc. Int. Workshop Log. Synth, pages 1-8, 2019.
[25] Yukio Miyasaka, Alan Mishchenko, John Wawrzynek, and Nicholas J Fraser. Synthesizing a class of practical boolean functions using truth tables.
[26] Arlindo Oliveira and Alberto Sengiivaann--iiceeeeee Learning complex boolean functions: Algorithms and applications. Advances in Neural Information Processing Systems, 6, 1993.
[27]
Alan Minko et al. IWLS 2023 Logic Synthesis Contest Submissions. https://github. com/ al Seaminko/wwws20225 http://www22222222m wttp://wwooossl22------oooooo contesss 2023.
(28) Yukio Miyasaka. Transduction method for aig minimization. In 2024 29th Asia and South Pacific Design Automation Conference (ASP-DAC), pages 398-403, IEEE, 2024.
[29] Franz Xaver Reichl, Friedrich Slivovsky, and Stefan Szeider. Cireuit minimization with exact synthesis: From qbf back to sat. In # BAAEGHHO.DDDEPPPRTTTTTTAAAAAAAAT _AAUUE pages 98-105, 2023.
[30] Antoine Grosnit, Cedric Malherbe, Rasul Tutunov, Xingchen Wan, Jun Wang, and Haitham Bou Ammar. Boils: Bayesian optimisation for logic synthesis. In 2022 Design, Automation & Test in Europe Conference & Exhibition (DATE), pages 1193-1196. IEEE, 2022.
[31] Alan Minko et al. IWLS 2022 Logic Synthesis Contest Submissions. 2022.
com/
[32] Xihan Li, Xing Li, Lei Chen, Xing Zhang, Mingxuan Yuan, and Jun Wang. Circuit transformer: End-to-end circuit design by predicting the next gate. arXiv preprint arXiv:2403.13838 2024.
[33] Vinícius Neves Possani. Parallel algorithms for scalable logic synthesis verification. 2019.
[34] Eric Jang, Shixiang Gu, and Ben Poole. Categorical reparameterization with gumbel-softmax. arXiv preprint 161iv:1611.011 2016.
[35] Xin Chen, Lingxi Xie, Jun Wu, and Qi Tian. Progressive differentiable architecture search: Bridging the depth gap between search and evaluation. In Proceedings of the IEEE/CVF international conference computer vision, pages 1294-1303, 2019.
[36] Pan Zhou, Caiming Xiong, Richard Socher, and Steven Chu Hong Hoi. Theory-inspired path- regularized differential network architecture search. Advances Neural Information Processing Systems, 33:8296-8388 8307, 2020.
12

---

[37] Xinyu Zang, Nairong Sun, and Kishor S Trivedi. A bdd-based algorithm for reliability analysis of thased-mission systems. IEEE Transactions on Reliability, 48(1):00-60, 1999.
[38] Tsung- Yi Lin, Priya Goyal, Ross Girshick, Kaiming Hc, and Piotr Dollár. Focal loss for dense object detection. In Proceedings of the IEEE international conference on computer vision, 2017.
pages
[39] Jianyong Yuan, Peiyu Wang, Junjie Ye, Mingxuan Yuan, Jianye Hao. and Junchi Yan. Easyso: Exploration-enlie enhannce reinforcement learning for logic synthesis sequence optimization and a comprehensive rl environment. In 2023 IEEE/ACM International Conference on Computer Aided Design (ICCAD), pages 1-9. IEEE, 2023.
[40] Robert Brayton and Alan Mishchenko. Abc: An academic industrial-strennth verification tool. In Computer Aided Verification: 22nd International Conference, CAV 2010, Edinburgh, UK, July 15-19, 2010. Proceedings 22, pages 44.0.. Springer, 2010.
[41] Richard Rudell. Espresso-mv: Algorithms for multiple-valued logic minimization. In Proceed- ings of IEEE Custom Integrated Circuit Conference, 1985, pages 230-234, 1985.
[42] Yaman Umuroglu, Yash Akhauri, Nicholas James Fraser, and Michaela Blott. Logicnets: Co-designed neural networks and circuits for extreme-throughhut applications. In 2020 30th International Conference on Field- Poaddl-rrrummabll Logic and Applications (FPL), pages 291- 297. IEEE, 2020.
[43] Alan Mishchenko, Satrajit Chatterjee, and Robert Brayton. Dag-aware aig rewriting fresh look at combinational logic synthesis. In Proceedings of the 43rd anmual Design Automation Conference, pages 532-535, 2006.
[44] Yao Lai, Yao Mu, and Ping Luo. Maskplace: Fast chip placement via reinforced visual representation learning. Advances Neural Information Processing Systems, 35:24019-24038 2022.
[45] Yao Lai, Jinxin Liu, Zhentao Tang, Bin Wang. Jianye Hao, and Ping Luo. Chipformer: Transferable chip placement via offiine decision transformer. In International Conference Machine Learning, pages 18346-18364. PMLR, 2023.
[46] Xufeng Yao, Haoyang Li, Tsz Ho Chan, Wenyi Xiao, Mingxuan Yuan, Yu Huang, Lei Chen, and Bei Yu. Hdldebugger: Streamlining hdl debugging with large language models. arXiv preprint 2rXiv:2403.11677 2024.
[47] Xufeng Yao, Yiwen Wang, Xing Li, Yingzhao Lian, Ran Chen, Lei Chen, Mingxuan Yuan, Hong Xu, and Bei Yu. Rtlrewriter: Methodologies for large models aided rtl code optimization. arXiv preprint arXiv:2409.1 11414, 2024.
[48] Jiantao Liu, Carmine Rizzi, and I Lana Josipović. Load-store queue sizing for efficient dataflow circuits. In 2022 International Conference on Proera-Pogra Technology (ICFPT), pages 1-9, 2022.
doi: 10.1 11111//F7756566222999977765
[49] Xing Li, Lei Chen, Jiantang Zhang, Shuang Wen, Weihua Sheng, Yu Huang, and Mingxuan Yuan. Effisyn: Efficient logic synthesis with dynamic scoring and pruning. In 2023 IEEE/ACM International Conference on Computer Aided Design (ICCAD), pages 1-9, 2023. doi: 10.1109/
[50] Junfeng Liu, Liwei Ni, Xingquan Li, Min Zhou, Lei Chen, Xing Li, Qinghua Zhao, and Shuai Ma. Aimap: Learning to improve technology mapping for asics via delay prediction. In 2023 IEEE 41st International Conference on Computer Design (ICCD), pages 344-347. IEEE, 2023.
[51] Junfeng Liu, Min Zhou, Shuai Ma, and Lujia Pan. Mata*; Combining learnable node matching with a algorithm for approximate graph edit distance computation. In Proceedings of the 32nd ACM International Conference on Information and Knowledge Management, pages 1503-1512, 2023.
13

---

[52] Zijie Geng, Jie Wang, Ziyan Liu, Siyuan Xu, Zhentao Tang, Mingxuan Yuan, Jianye Hao, Yongdong Zhang, and Feng Wu. Reinforcement learning within tree search for fast macro placement. In International Conference on Machine Learning. PMLR, 2024.
[53] Shixin Chen, Shanyi Li, Zhen Zhuang. Su Zheng, Zheng Liang, Tsung- Yi Ho, Bei Yu, and Alberto L Sangiovanni-Vincenter Floorplet: Performance-aware floorplan framework for chiplet integration. IEEE Transactions on Compuler-Aided Design of Integrated Circuits and Systems, 2023.
[54] Shixin Chen, Su Zheng, Chen Bai, Wengian Zhao, Shuo Yin, Yang Bai, and Bei Yu. Soc-tuner: An importance-guided exploration framework for dnn-targeting soc design. In 2024 29th Asia and South Pacific Design Automation Conference (ASP-DACE pages 207-212. IEEE, 2024.
[55] Dongsheng Zuo, Yikang Ouyang, and Yuzhe Ma. Rl-mul: Multiplier design optimization with deep reinforcement learning, In 2023 60th ACM/IEEE Design Automation Conference (DAC), pages 1-6, IEEE, 2023.
[56] Zhihai Wang, Jie Wang, Dongsheng Zuo, Yunjie Ji, Xinli Xia, Yuzhe Ma, Jianye Hao, Mingxuan Yuan, Yongdong Zhang, and Feng Wu. A hierarchical adaptive multi-task reinforcement learning framework for multiplier circuit design. In Forty-first International Conference on Machine Learning. PMLR, 2024.
[57] Dongsheng Zuo, Jiadong Zhu, Chenglin Li, and Yuzhe Ma. Ufo-mac: A unified framework for optimization of serforerformnce multipliers and multiply aalippl-accuumulttor. arXiv preprint arXiv:2408.000 06935, 2024.
[58] Tuomas Haarnoja, Aurick Zhou, Pieter Abbeel, and Sergey Levine. Soft actor-critic: Off- policy maximum entropy deep reinforcement learning with a stochastic actor. In International conference on machine learning, pages 1861-1870. PMLR, 2018.
[59] Zhihai Wang, Taoxing Pan, Qi Zhou, and Jie Wang. Efficient exploration in resource-restricted reinforcement learning. In Proceedings of the AAAI Conference on Artificial Intelligence. volume 37, pages 10279-10287, 2023.
[60] Zhihan Liu, Miao Lu, Wei Xiong, Han Zhong, Hao Hu, Shenao Zhang, Sirui Zheng, Zhuoran Yang, and Zhaoran Wang. Maximize to explore: One objective function fusing estimation, planning, and exploration. Advances in Neural Information Processing Systems, 36, 2024.
[61] Zhihan Liu, Hao Hu, Shenao Zhang, Hongyi Guo, Shuqi Ke, Boyi Liu, and Zhaoran Wang. Reason for future, act for now: A principled framework for autonomous 1lm agents with provable sample efficiency. arXiv preprint arXiv:2309. /7382, 2023.
[62] Xuhui Liu, Feng Xu, Xinyu Zhang, Tianyuan Liu, Shengyi Jiang, Ruifeng Chen, Zongzhang Zhang, and Yang Yu. How to guide your learner: Imitation learning with active adaptive expert involvement. In Proceedings of the 2023 International Conference on Autonomous Agents and Multiagent Systems, pages 1276-1284, London, UK, 2023.
[63] Michael Janner, Justin Fu, Marvin Zhang, and Sergey Levine. When to trust your model: Model-based policy optimization. Advances in neural information processing systems, 32, 2019.
[64] Zhihai Wang. Jie Wang, Qi Zhou, Bin Li, and Houqiang Li. Samplc-efficient reinforcement learning via conservative model- actor-critic. In Proceedings of the AAAI Conference on Artificial Intelligence, volume 36, pages 8612-8620, 2022.
[65] Chris Gamble and Jim Gao. safety--irst ai for autonomous data centre cooling and industrial control. DeepMind, August, 17, 2018
[66] Chao Jiming Liu, Shamim Nemati, and Guosheng Yin. Reinforcement learning in healthcare: A survey. ACM Computing Surveys (CSUR), 55(1):1-33, 2021.
[67] Zhihai Wang, Xijun Li, Jie Wang, Yufei Kuang, Mingxuan Yuan, Jia Zeng, Yongdong Zhang, and Feng Wu. Learning cut selection for mixed-integer linear programming via hierarchical sequence model. In The Eleventh International Conference on Learning Representations, 2023. httt:httt////eeereeee
14

---

[68] Jie Wang, Zhihai Wang, Xijun Li, Yufei Kuang, Zhihao Shi, Fangzhou Zhu, Mingxuan Yuan, Jia Zeng. Yongdong Zhang, and Feng Wu. Learning to cut via hierarchical sequence/set model for efficient mixed-integer programming. IEEE Transactions on Pattern Analysis and Machine Intelligence, pages 1-17, 2024, doi: 10.1 (09/TPAMM.2004333227666
[69] Zhihai Wang, Zijie Geng, Zhaojie Tu, Jie Wang, Yuxi Qian, Zhexuan Xu, Ziyan Liu, Siyuan Xu, Zhentao Tang, Shixiong Kai, et al. Benchmarking end-to-end performance of ai-based chip placement algorithms. arXiv preprint arXiv:2407.15026, 2024.
[70] Yoshua Bengio, Andrea Lodi, and Antoine Prouvost. Machine learning for combinatorial optimization: methodological tour d' d'rorizon. European Journal of Operational Research, 290(2):405 421, 2021.
[71] Zijie Geng, Xijun Li, Jie Wang. Xiao Li, Yongdong Zhang, and Feng Wu. A deep instance generative framework for milp solvers under limited data availability. In A. Oh, T. Naumann, A. Globerson, K. Saenko, M. Hardt, and S. Levine, editors, Advances in Neural Information Processing Systems, volume 36, pages 26025-26047. Curran Associates, Inc., 2023.
[72] Haotian Ling, Zhihai Wang, and Jie Wang. Learning to stop cut generation for efficient mixed- integer linear programming. Proceedings of the AAA/ Conference on Artificial Intelligence, 38 011207799-20667 Mar. 2024. doi: 10. 609/aaai v38. 1.38188.30664 URL httpt::/ps/ssss... aaai
org/index. php/
30064
[73] Chenguang Wang, Yaodong Yang, Congying Han, Tiande Guo, Haifeng Zhang, and Jun Wang. A game-theoretic approach for improving generalization ability of tsp solvers. 2021.
[74] Chenguang Wang, Zhouliang Yu, Stephen McAleer, Tianshu Yu, and Yaodong Yang. Asp: Learn universal neural solver! IEEE Transactions Pattern Analysis and Machine Intelligence. 2024.
[75] Chenguang Wang, Congying Han, Tiande Guo, and Man Ding. Solving uncapacitated p-median problem with reinforcement learning assisted by graph attention networks. Applied Intelligence, 23(2):201-22255, 2023.
[76] Yixuan Li, Wanyuan Wang, Weiyi Xu, Yanchen Deng, and Weiwei Wu. Factor graph neural network meets max-sum: A real-time route planning algorithm for massive-scale trips. In Proceedings of the 23rd International Conference on Autonomous Agents and Multiagent Systems, pages 1165- 1173, 2024.
[77] Haoxing Ren and Jiang Hu. Machine Learning Applications in Electronic Design Automation. Springer Nature, 2023.
[78] Abdelrahman Hosny, Soheil Hashemi, Mohamed Shalan, and Sherief Reda. Drills: Deep rein- forcement learning for logic synthesis. In 2020 25th Asia and South Pacific Design Automation Conference (ASP-DAC), pages 581-586. IEEE, 2020.
[79] Robert K Brayton. The decomposition and factorization of boolean expressions. ISCA-82, pages 49-54, 1982.
[80] Alan Mishchenko Robert Brayton. Scalable logic synthesis using a simple circuit structure. 15-22, 2006.
[81] Valeria Bertacco and Maurizio Damiani. The disjunctive decomposition of logic functions, In iccad, volume 97, pages 78-82, 1997.
[82] Alan Mishchenko Satrajit Chatterjee Robert Brayton and Xinning Wang Timothy Kam. Tech- nology mapping with boolean matching, supergates and choices.
[83] Alan Mishchenko, Sungmin Cho, Satrajit Chatterjee, and Robert Brayton. Combinational and sequential mapping with priority cuts. In 2007 IEEE/ACM International Conference on Computer-Aided Design, pages 361. IEEE, 2007.
[84] Diederik P Kingma and Jimmy Ba. Adam: A method for stochastic optimization. arXiv preprint 1rXiv.141..6980, 2014.
15

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A Related Work
As chip complexity has grown exponentially with the development of semiconductor technology. using machine learning (ML) to assist the automated chip design workflow has been active topic of significant interest in recent years [2 44 45 The chip design workflow consists of many stages
U. such as high-level synthesis [46448]
logic synthesis 49,51), placement 45 52 53 design
space exploration (54157, etc. Our paper specifically targets ML applications in logic synthesis (LS),
a pivotal area within Electronic Design Automation (EDA). We categorize this domain into two key segments: ML embedded in logic synthesis and ML for end-to-end logic synthesis.
A.1 Machine Learning Embedded in Logic Synthesis
Machine Learning Embedded in Logic Synthesis refers to incorporating MI. into a specific stage of LS, aiming to enhance the efficiency of LS and achieve improved Quality of Results (QoR). For example, [IS] use machine learning to tune the optimization flow of LS operators; [14] use machine learning to predict key metrics after physical design and leverage the prediction to guide LS
optimization; [18] machine learning improve decision-making in traditional LS methods. [I7] apply machine learning to commonly used LS operators and significantly improve the efficiency of these operators. These embedded machine learning methods have significantly contributed to the advancement of LS.
A.2 Machine Learning for End-to-end Logic Synthesis
Logic circuit synthesis is the process of producing a logic circuit that satisfies given specification and is a classical problem in computer science [5]. In contrast to embedded methods that utilize machine learning to optimize specific stages within Logic Synthesis (LS), recent works propose employing machine learning to replace traditional logic synthesis stages, thereby achieving end-to- end logic synthesis. In the realm of logic circuit generation, scholarly efforts diverge into two primary approaches. Works like those of [20] and [21 explore this field through the lens of the languages employed to describe logic circuits. In contrast, other studies concentrate on the generation of logic circuits by conducting searches focused on the circuit structure itself. Notably, [6] integrates real- valued logic with continuous parameterization to create differentiable logic gate network, enabling efficient training and rapid inference, crucial for end-to-end synthesis. [5] proposes a novel approach to directly search exact logic circuits by leveraging differentiable neural architecture search methods, offering significant potential in logic circuit synthesis. However, existing end-to-ena methods show limitations in scaling to large circuits and sensitivity to hyperparameters. Based on these observations, we rethink the differentiable neural architecture search and propose a novel differentiable neural logic gate network search framework. An appealing feature of our method is that it is functionally complete and has low redundancy and high expressiveness.
A.3 IWLS Contest
International Workshop on Logic& & Synthesis (IWLS) is global conference on logic synthesis that hosts a contest annually 8 (2). The themes for the contests in 2022 [1] and [0 were circuit synthesis from truth tables, scored based on the number of nodes, with fewer being better. This is the same setting our paper focuses on. The approaches of the participating teams are mostly based on traditional logic synthesis methods, involving both generation and optimization steps. The generation phase encompasses basic operators such as SOP 100 I1 and others, BDDD-asedd m2thods(23
as well as methods utilizing mutual information (26]. among others. Meanwhile, in 2023, Google DeepMind adopted a deep learning- baasid generation approach 7 (27). They introduced a DNAS- based method to generate circuits, which, after three weeks of subsequent optimization, achieved first place in 2023. Since Google has not formally published their approach, we replicated it as baseline for our study. We deeply analyzed and improved upon the DNAS- based generation method.
Optimizing circuits involves employing series of circuit optimization operators. Given that the sequence of operator executions and their parameter configurations significantly impact the final quality of results, the primary task is to find the optimal operator sequence for a circuit. UCB team proposed new optimization scripts(28) (2), while the TUW team introduced windowing methods to enhance the efficiency of SAT optimization methods 29]. The 2022 champion EPFL team utilized Bayesian optimization methods (30) with EA framework to optimize the operator sequence. Although both EPFL and we have employed the EA framework, what sets us apart is our utilization of RL methods with strong search capabilities and the introduction of restart strategy mitigate the impact of local optima. We achieved a 25% and 5% improvement over the results of the winners in the 2022 and 2023 competitions, respectively, through our comprehensive circuit synthesis approach.
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A.4
Reinforcement Learning (RL)
In general, standard RL fall into two categories: model-free RL 158 and model-based RL 63 64
In recent years, RL has achieved great success in many important real-world decision-makinn tasks In this paper, we propose an evolutionary RL method for circuit optimization.
65
66
56
67
69
Machine Learning for Combinatorial Optimization Circuit generation and optimization is also essentially a combinatorial optimization problem. The use of machine learning to tackle combinatorial optimization problems has been an active topic of significant interest in recent years [70476).
B Background
B.1 Logic Synthesis (LS)
The increasing complexity in modern chip design workflow demands innovations in Electronic Design Automation (EDA) to keep scalability without compromising Quality-of-Resulss (QoR). Multiple EDA tools are incorporated into the chip design workflow to synthesize, simulate, test, and verify different circuit designs efficiently and reliably [77]. Being at the top of most EDA tools, LS aims to transform a behavioral description of design into an optimized gate gate-level circuit implementation. In general, LS consists of translation, circuit optimization, and technology mapping 77 In the translation phase, a given boolean function, represented by a truth table, is transformed into a well- structured circuit. Then, in the circuit optimization phase, lots of logic optimization operators [79 are applied to an input circuit to optimize the circuit. Finally, in the technology mapping phase, the optimized logic circuit is mapped to an available technology library, e.g., a standard-cell netlist [82] or k-input lookup-tables [83]. In this paper, we propose a novel differentiable neural logic gate network search framework to synthesize logic circuits from input-output examples. This framework has the potential to replace the traditional phases of translation and circuit optimization, which introduces innovation to the realm of LS.
B.2 Circuit Representation
Boolean Networks are well-studied discrete mathematical models with broad applications in chem- istry, biology, circuit design, formal verification, etc. [33 A Boolean network is directed acyclic graph (DAG), where nodes correspond to Boolcan functions and directed edges correspond to wires connecting these functions. A Boolean function is a mapping from n-dimensional space 3 to a 1-dimensional space B, i.e. f B" >> B, where B- = (0. 1} denotes the Boolean domain. In the LS stage, cireuit is usually represented as And-Inverter Graphs (AIG), which is concise and uniform representation of Boolean Networks. An AIG contains four types of nodes: the constant, primary inputs (PIs), primary outputs (POs), and two-input And (And2) nodes. Graph edges may be complemented, indicating a complemented signal. Given a node in AIG, its fanins are nodes connected by incoming edges of this node, and its fanouts are nodes connected by outgoing edges of this node. Each node has at most two incoming edges. The PIs are nodes without fanin, and the POs are nodes without fanout. The size of a circuit denotes the number of nodes in the AIG. The depth (level) of circuit denotes the maximal length of a path from a PI to a PO in the AIG. The size and depth of a circuit are proxy metrics for the area and delay of the circuit, respectively.
B.3 DNAS for Logic Synthesis
Differential Neural Network Architecture Search (DNAS) can be effectively applied for logic synthe- sis. where logic modules like AND gates are used as nodes, and connections between these nodes are optimized via gradient descent. The network's 's inputs and outputs mirror the signals of a logical circuit, consisting of Os and 1s. During the training phase, the discrete logic circuit undergoes a relaxation and continuousization process in two aspects. First, the logical operations of logic gates are translated into their differentiable counterparts. For instance, a AND is relaxed to a 6, and NOT is relaxed to 1 a (6). Next, discrete network connections are parameterized, employing Gumbel-softmal 334 during forward propagation to continuousize and sample the connections between nodes, thus enabling optimization through gradient descent to find high-quality solutions. In the evaluation stage, for each input of every logic module, only a single connection is chosen based reinstated.
on the parameters, and discrete logic operations
The DNAS method, as analyzed Section 4 utilizes AND-NOT gates as nodes. The network's structure is defined by its depth I. and width K, signifying I. layers with K nodes each. Here, I, = 0 represents the circuit's input. It's important to note that the nodes the output layer (T. + 1) are not gates and are excluded from the network count. They possess a singular input, selecting which
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node in the network represents the output signal. Let g' denote the htth node in the 1th layer, where 1 I and 1 I & I K. Let in be the pth input of the node g and outl be its output. The method to compute the value of the pth imput for gl during training is as follows:
K
L.k im
outh softmax (ch.m.P) i.j
(4)
There are two common modeling forms for the connections: direct and direct-or-negation Since the AND-NOT gate is sufficient to express all logical functions, learning the connections alone can fully represent the functionality of circuit. However, this may require specific combinations of connections, which can be more easily accomplished using the NOT operation. Therefore, another modeling method allows edges to choose between negation or direct connection. the motivation section of our paper, we utilize the direct connection as referenced in [5], while in our T-Net, we adopt the direct-or-negeee negaatio connection.
C
Motivation
C.1 Settings
Width and Depth of Networks. In DNAS, the method for setting the initial size of the network is as follows. Assuming that circuit synthesized by SOP has N nodes and L levels, the network width set to 5 x [N/(5L)], which is the average number of nodes per layer rounded up to the nearest multiple of five. The network depth is set to 5 [2//5], which is twice the value of L., rounded down to the nearest multiple of five. In our T-Net, we set the total depth as DNAS, while the bottom block depth is 5 or 10 layers. We set the total nodes smaller than the bottom. The network size of the two circuits in Section 4 are shown in Table 6
the DNAS, and the upper block width
Table 6: Network Size of the two circuits evaluated in motivation.
Circuit
SOP
DNAS
T-Net Depth up
Node
Lev
Width
Depth
Width up
Width down
Depth down
Small: Espresso7 (8 P1/33 PO)
482
20
Small:
LogieNets! (12 PI/3 PO)
194
18
15
35
10
25
25
10
Training setting Both the training and validation datasets use the complete set of ouput-output combinations, meaning that the input bit size is K, there are a total of 2* input combinations. The batch size for the network is uniformly set to 20 The number of training iterations is 100 thousand, and we report the optimal results evaluated during the training process.
C.2 Motivation Experiment
Hyperparameter Sensitivity Analysis To verify the stability of generated circuits with different random initializations, we conduct tests using various random initializations. Specifically, we utilized four different seeds to evaluate two circuits from each of the datasets Espresso and LogicNets. Figure 5(a) illustrates the average accuracy and the fluctuation range of accuracy for these two circuits. The fluctuation range reached 14.5% accuracy, indicating that the accuracy of generated eircuits highly sensitive to random initialization, making it challenging to consistently produce stable results with DNAS.
The Curse of Skip-Connection We conduct a motivation experiment on the LogicNets circuit. As shown in Figure 3b), the LogieNets circuit exhibits the same experimental phenomenon as the Espresso circuit in Section 4.2 where the output nodes are located in the shallow layers of the network, and skip connections bypass the majority of the nodes.
We also visualized the positions of circuit nodes of LogicNets within the network in Figure C).. Notably, this circuit has three outputs, resulting in layer configurations distinct from those in the single-output case shown in Figure 3(b). It can be observed that only a subset of bottom-layer nodes integrated into the circuit, with over two-thirds of the nodes being left idle due to skip connections. This visual representation demonstrates that excessively distant skip connections diminish node utilization and the expressive capacity of the network.
Figure illustrates the exploration degree of each network layer after convergence. A node is thus deemed "epplored' if it forms part of the discretized circuit at any stage during the training. The
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Hattopo
Leghtfrn oetet wnf ie enteetk
and Eo
Accarncytii
(a)
(b)
(c)
Figure 3: (a) Average accuracy and enror har of two circuits with four different initializations. (b) The depth for an output for another circuit. The curves labeled DNAS and T-Net in the graph represent the depth of the same output. Comparing network depth, is evident that DNAS is only connected to very shallow layers, highlighting the curse of skip-connection. In contrast, our method learns deeper layers during subsequent training. (c) Network visualization of Logicnet circuit after DNAS convergence. Dark nodes are circuit nodes.
Walked nodes network with Expresso
Walked nodes network LagleNets
Nodes 20
30
Nodes 10
Network depth
depth
Figure 4: We present the exploration of two circuits. The height of the empty bars illustrates the total number of nodes in each layer, with the solid bars indicating the number of nodes that have been explored.
exploration degree is indicative of the number of nodes investigated within each layer. Observations reveal a higher exploration degree in the shallower layers, which progressively diminishes in the deeper layers. This pattern leads us to ponder whether structural bias in circuit architecture contributes to the reduced exploration in the deeper layers of circuits.
Learning Difficulties of Different Input-Output Examples We have observed that the difficulty of learning varies among different output bits and input combinations.
To investigate variations in difficulty among different output bits, we analyzed training loss curves for various output bits within the same circuit. Using Mean Squared Error (MSE) loss, we visualized loss curves for three representative output bits from two circuits. From Figure 5Ja) and (b), it's evident that the convergence speed of loss varies among different output bits -some converge quickly, while others exhibit slower descent. The distinct Boolean functions represented by different output bits naturally lead varying levels of difficulty. Hence, during network training, addressing the challenges posed by harder-to-learn output bits is crucial.
Simultancously, investigate the learning difficulty among different imput samples, we examined the convergence speeds for different inputs on the same output bit. Specifically, we recorded the iteration numbers which the accuracy for each input sample reached 100 during a low iteration training process, representing the convergence time for each sample. Figure (c) and (d) displays the distribution of convergence iterations for input-outpur examples involving three output bits. can be observed that the convergence speed varies among different input samples. While the majority of samples converge within 10 thousand iterations, small subset fails to converge correctly even after 100 thousand iterations. This observation underscores substantial variations in learning difficulty among various input-output pairings, challenging the conventional machine learning assumption of samples being independent and identically distributed (IID). This occurs because different input
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corpet Sigrese
PMfercat entger
Leggehetssttree Logic
Entoretco speet alterem
Leghtnn
Logh Nor
280
40000
C2003
Figure 5: (a) and (b) Loss of different output in the same circuit. The convergence speed of loss varies among different outputs. (c) and (d) Distribution of convergence iterations for input-output examples. Different examples have different converge speeds. The bar between 10 thousand and Inf means these instances do not converge in 10 thousand iterations.
combinations of circuit are interrelated, corresponding to parts of varying difficulty within the logical function.
D Implementation of Our Approach
D.1 Implementation of T-Net
In our specific implementation, we adopted simple two-block structure, consisting of a wide and shallow bottom rectangular block and a narrow and deep upper rectangular block. The size of the network is determined in relation to the scale of the circuit. The initial setting is based on traditional square network. Assuming that a circuit synthesized by SOP has nodes and levels, the network width is set to 5 [N/() which is the average number of nodes per layer rounded up the nearest multiple of five. The network depth is set to 5 x [2L/5], which is twice the value of L,, rounded down to the nearest multiple of five. In our T-Net, maintain the total depth in DNAS, with the bottom block having a depth of 5 or 10 layers. The total number of nodes is kept the same in the traditional rectangular network, but the width of the upper block is smaller than that of the bottom.
D.2 Regularized Skip-Connection
For the node gl its input computation with regulation as follows:
K. out softmax (unith softmax (layer weightt), (5)
in 1.k
weight' having dimensions 1 is non-learnable and solely varies with functions similarly to a soft gating layer, with its values linearly increasing from 0.1 to 1 as per the formula:
0.9
0 0<i54
1-1
weight')
(6)
0.1 + 0.9
4<i<i-1
In the network's shallower layers, we configure the weight to preferentially form connections to the input layer. This design aims to augment the diversity of logical expression sub-formulas. Conversely, in the network's 's deeper layers, the weights are adjusted to favor connections with the more advanced nodes, thereby increasing the complexity of the logical expressions.
D.3 Boolean Hardness-Aware Loss
Our hardness-aware loss has two parts, input-output loss and wrong-rate loss.
First, we use input-output loss enhance the hard input-output examples from individuals. Specifi- cally, we add a weight Wio to each onput-output loss.
Wio = (in)(()))out))--
(7)
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with finn) be the ouiput by the net, out be the label of output, a and ò be hyperperameter. The (f(in) - out represents the difference between the network output and the label, where a larger value indicates a more challenging sample. á controls the boundary for challenging samples, while regulates the extent of reinforcement.
Second, we use wrong-rate loss to enhance the hard input-output examples from global. War T-ace: with 1 - acc being the wrong rate of the current network, which is updated every iteration. As Warr increases with the increase in accuracy, it dynamically maintains the loss at similar magnitude, ensuring that the training speed does decrease due to low error rate. Then the loss function is [.f (in), out) = War uo L MSE(J (in), out)
D.4 Temperature coefficient decay mechanism
We employ decaying т parameter. Due to the disparity between softmax calculations during training and the discretization during testing, there can be instances of accurate training but erroneous input-output combinations during testing. This phenomenon can be alleviated by reducing the hyperparameter in softmax. As increases, softmax approaches one-hot encoding, reducing the disparity between training and testing. However, a significant increase in T may lead to highly discrete network parameters, making training extremely challenging. Therefore, it crucial to set an appropriate size for т. We design a decay mechanism for continuously decreasing it as accuracy improves, ensuring trade-off between training effectiveness and speed.
D.5 Optimization
Action Space We use RL agent to search optimal operator sequence. As shown in Table 7 the action space has 9 operators and their corresponding 16 parameters. For each parameter of an operator, its range is denoted as [a, b] in the table, showing that the parameter can be any integer between a and (inclusively).
State Representation. The state in the environment has three parts: a set of metrics that depict the current circuit design, the raw AIG graph, and the historical actions. The first part is feature vector consisting of the following values at step t: Number of logic gates and logic depth. The current length of the operator sequence. For each step, record the selected operator and parameters normalized vector and form the historical action vector.
Table 7: The action space in our environment, with parameter name '-x' and the range of the continuous parameter [a, b].
Operator
Parameter
&st
N/A
&blut
-m-r-a -C[1.8]
&b
-s -s-d
&dsdb
-C18,400]
&sopb
-C[8.400]
&if -g
-C[8,400]
&dc2
-1
&dch
-x (1N.512)-C11100,10000 -555000,50000
&transtoch
-M [1:4] -R[1:200]
Evolutionary Algorithm Framework Our Evolutionary Algorithm (EA) Framework involves several key steps as shown in Figure Firstly, the exploration space can be defined as circuits of different structures with the same logical functionality.. The initial population size is denoted P. comprising diverse circuits generated by our T-Net. These P circuits, serving as the initial solutions for the RL model, undergo period of training. Following this training phase, each circuit yields Q = M/ Poptimized circuits. Here, mutation is defined as circuit optimization. It is important to note that the optimized circuits resulting from different initial circuits are collectively input into the model without differeentiaion. Subsequently, the M optimized circuits are sorted based on their node count, and the perreorrrinng P circuits are selected as the next generation. This iterative process continues, evolving the population until the optimal circuit is identified as the final result. Compared with only picking one optimal solution when restarting, EA can increase the diversity of the circuit and expand the search scope.
D.6 Legalization
For circuits that are not generated with complete precision, we adopt legalization approach to correct the few erroneous bits in the logic expression. Here, bit refers to combination of a set of inputs and
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EA framework
Updoto generation
Enttumee
Nitt
Select
Appes
Truth
1 emeraate circuit population
W RL optimize
Optomized droilts
H Next generation climalis
Nisti openioo
gent Restart
Loud enoodE
Optnnood
tinvuit
Emvironment
Cinouit gesph
Rncoder
actoc
Pray operroo SANUAROO
Operator
Opentor
RL optimize
States
Aguit
sequence
Figure 6: Framework of the evolutionary algorithm assisted by RL agent restarting technique for circuit optimization.
Table 8: Generation accuracy results. Impr. is the percentage decrease in wrong bits.
Benchmark
Basic DNAS
DNAS Skip
Darts-
T-Net (Ours)
Cärcuit
Acc.(%)
Wrongs]
Acc.
Wrongs!
Ace.(%
Wrongs]
Acc/S/t
Wrongs
Impe:())
Espressul
98.4
79:95
821
97.83
89
100
Espress02
66.67
128
100
(1
70:31
114
100
D
100
Small
Espresso6
Espressod
78.67
72.95
277
97.65
97.85
24
80.47
72.75
500
279
100
100
D
0
100
100
LogicNets2
Arilhmetic!
79.56
2530
98.73
156
$8.61
1400
100
0
100
LegicNets3
12
3
90.17
1207
90.09
1218
88.53
1/09
99.9
12
99.01
Large
LogicNess5
80,14
2440
84,59
1894
92.54
930
99.93
9
99.52
Average
82.51
91.99
86.31
1938.00
single output. Specifically, we represent the input combinations using the method of minterms, and then integrate them into the output bit. For example, if the circuit has three inputs a, b and c, and the output for the input combination /01 should be 1, then the subtree ab' c is combined with the original output node through an OR operation, forming a new output node. This legalization process can complete cases that are only few bits short. However, this approach involves a significant amount of redundancy and is not suitable for situations where there are many errors.
E
Experiment
E.1 Setting
Hyperparameter The batch size is set to 1024, with the learning rate set at 0.02. The temperature coefficient starts at and decays 0.5 when the accuracy approaches 100%. The training process lasts for 100 thousand iterations, and the model with the highest evaluation score is selected as the final result. We use Sum Squared Errors instead the common Mean Squared Errors(MSE) to ensure that the loss does not become too small in later stages. In Equation 7 the hyperparameter is set to 2. and 8 set to 0.3. In Wor. 3 set to 10.
The size of the circuit generation network varies according to the circuit. For DNAS, the network size is determined in relation the scale of the circuit. Assuming that a circuit synthesized by SOP has N nodes and L levels, the network width is set to 5 x [N/(5L)], which is the average number of nodes per layer rounded up to the nearest multiple of five. The network depth is set x [2T./5]. which is twice the value of L, rounded down to the nearest multiple of five. In our T-Net, we maintain the total depth as in DNAS, with the bottom block having a depth of or 10 layers. The total number of nodes is kept the same in the traditional rectangular network, but the width of the upper block is smaller than that of the bottom.
We train our method with ADAM using the PyTorch.
Hardware specification Our experiments were conducted on Linux-based system powered by 3.60 GHz Intel Xeon Gold 6246R CPU and NVIDIA RTX 2080 GPU.
E.2
Main Evaluation
The other 8 circuits mentioned in the main evaluation are shown in Table 8 9 and 10
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Table 9: Generation size results. Init Node is generated by SOP our T-Net and Opt Node is optimized by resyn2. lmpr. represents the percentage decrease in nodes achieved by our approach.
Beachmark
SOPeresyn2
Ourseresyn2
Size
Circuit
Pl
PO
Init Node
Opt Node L
Init Node
Impe/[%)
Opt Node
Impr/ (6
Expressol
19.19
Espresso2
90
Smalll
Espressob
Expresea5
9
187
172
120
133
140
105
25.13
38,95
121
96
20.00
9.02
LogieNets2
292
257
254
13.01
219
14.79
Anthmeticl
LogicNets3
599
490
445
25.71
376
23.27
Large
LogieNets5
12
941
798
611
35.07
549
31.20
Average
459,39
262.78
230.06
Table 10: Optimization results. The default results are synthesized by the traditional SOP method. We use optimization operators to synthesize the circuits as the Opt Node shows. The term 'Impr'' is defined as the percentage decrease in the number of nodes achieved by our approach, relative the default configuration.
Trudition
Size
Cireuit
SOPerogn2
TUW
EPFL((AI)
EPFL.(A)
TUW
Google(AT)
Opt Node
Imsprct St
Espressol
10
4
130
64
47
63.85
Espresea2
3
28
28
78
28
28
78
67.06
Small
Espressod
Espresso6
9
8
4
5
133
120
46
37
47
58
48
37
46
37
46
37
46
37
44
37
46
37
65.41
69.17
LagiNNes22
12
3
257
134
134
138
133
129
118
112
108
$7.98
Anchmeetic2
156
164
105
LogieNers3
Large
LogiNNes5
Average
380.29
132.78
113.89
E.3 Sensitivity Analysis
We validate the sensitivity of our method to hyperparameters from two perspectives: random initial- ization and the initial size of the network.
Random initialization. executed repeated experiments with a diverse set of random initializations. This entailed testing a single circuit from each of the four circuit categories using three distinct random initializations. As Table [T elucidates, our method uniformly maintained 100% accuracy across various random initializations, underscoring its robustness to these fluctuations. Furthermore, the disparity in circuit depth synthesized under different random initializations remained below 20%, showcasing our method's remarkable stability in network depth. This consistent performance helps prevent the descent into local optima, often characterized by an excessive number of cross-layer connections.
Network initial size. We evaluate one circuit with different network initial sizes. Specifically, we change the depth and width of the two network blocks up and down. Table T2 demonstrates that our method consistently generates accurate circuits across range of network initial sizes, thereby evidencing the robustness of our approach to variations in network size.
Table 11: Sensitivity analysis on different initialization.
Method
Small: Espressed
Nodes]
PO)
Small: LogieNess2 (12 PO)
Acce(90f
Nedes
Small: Aithimeicc2 Acc(%)
Nodes]
Acc(?i)
Randoast PV1 PO)
Noded
T.Net
176
267
258
100
T.Net Ini33
100
108
17
100
281
100
287
100
139
Network Depth. Deeper networks are not always better. We demonstrate in the following table the experimental results of a circuit at different network depths. As can be seen from Table 13 when the network is too shallow, it lacks sufficient expressive capacity, thus failing to generate exact circuits; conversely, when the network is too deep, it tends to produce relatively redundant circuits. Therefore, the depth of the network should be as shallow as possible while having enough expressive power to minimize the size of the generated circuit. In our experiments, rounded down the depth of the SOP circuit to 5 as the network depth.
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Table 12: Sensitivity analysis on different ini- tial network sizes.
Table 13: Sensitivity analysis on different net- work depth.
Small: LogieNets2 (12 PV/3 PO)
Width
Width down
Depth
Depth down
Aocuracy
Small: LogieNets2 (12 P1/ PO)
100
Method
Network Depth
Acc.(S)
15
10
100
Defaul (SOP)
N/A
N/A
292
17
100
100
99.05
184
13
20
15
100
20
99.86
213
16
100
10
40
30
20
10
100
100
100
100
258
20
20
100
E.4 Other Experiments
Triangle shape adaptable to circuits with more POs. The output layer of the network is selection layer, allowing any node within the network to be chosen as an output. Consequently, the number of nodes in the final gate layer does not limit the choices for outputs. We conducted an experiment to demonstrate this. For two circuits with extreme multiple POs, we use T--Net and rectangular network with the same base width T-Net to generate circuits. As shown Table [4] even when the width of the upper layers of the network is much smaller than the number of outputs, is still able to generate circuits exactly with fewer nodes compared to rectangular network.
Table 14: Analysis T-Net on circuits with extreme multiple POs.
Circuit
Espresso3 (PI 5/ PO 28)
Espresso7 (PI 8/ PO 63)
Network Width Acc.
Node
Network Width Acc.(%)
Node
Rectangular Net
100
T-Net
up/ 50 down
100
174
15 up/ 135 down
100
377
F
Limitation
Our approach for circuit generation and optimization relies on GPU for training, while the majority of existing logic synthesis tools operate in CPU environments. Consequently, our method may not be well-suited for deployment in CPU environments.
G Broader Impact
Academic Impact This paper provides thorough analysis of the application of differentiable neural architecture search (DNAS) methods to circuit generation. The insights may have positive implications for future work utilizing DNAS for circuit generation.
Social Impact This paper explores the optimization logic circuits. By employing MI. methods for circuit generation and optimization, it becomes feasible to enhance chip design quality and reduce costs in comparison to manual design processes.
H Licence
We include the following licenses for the code, benchmarks we used this paper.
Benchmarks:
Espresso 41 Copyright] LogicNets 42 Licence Random and Arithmatic
Licence Code: DNAS Licence
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NeurIPS Paper Checklist
1. Claims
Question: Do the main claims made in the abstract and introduction accurately reflect the paper's contributions and scope?
Answer: [Yes]
Justification: This paper find the limitations in existing DNAS for circuit generation and pro- poses novel circuit network to generate circuit accurately. With proposed EA optimization method, synthesised circuits outperform the winner in IWLS 2023 competition.
Guidelines:
The answer NA means that the abstract and introduction do not include the claims made paper.
The abstract and/or introduction should clearly state the claims made, including the contributions made in the paper and important assumptions and limitations. A No NA answer to this question will not be perceived well by the reviewers.
The claims made should match theoretical and experimental results, and reflect how much the results can be expected to generalize to other settings.
is fine to include aspirational goals as motivation as long as is clear that these goals not attained by the paper.
2. Limitations
Question: Does the paper discuss the limitations of the work performed by the authors?
Answer: [Yes]
Justification:
The limitations of our T-Net are detailed Section
Guidelines:
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Reviews:
[{"review_id": "fDERqGz3YD", "reviewer": "Reviewer_gSL5", "summary": "The paper tackles the challenges in logic synthesis (LS) for integrated circuit design by proposing a novel neural circuit generation framework. Traditional LS methods rely on heuristics, which can be suboptimal and inefficient. The authors revisit differentiable neural architecture search (DNAS) methods and identify key limitations: overfitting to skip-connections, structure bias, and imbalanced learning difficulties. To overcome these, they introduce T-Net, a regularized triangle-shaped network architecture with a multi-label transformation of training data and a regularized training loss function. Additionally, the paper propose an evolutionary algorithm assisted by reinforcement learning for neural circuit optimization. Extensive experiments demonstrate that T-Net outperforms state-of-the-art methods in generating precise and scalable circuits.", "questions": "1. How the proposed T-Net compare to previous SOTA in terms of model size, latency, energy efficiency etc?\n2. Why no parameter for Appendix Table 7 &st?", "limitations": "No significant negative societal impact", "rating": 7, "confidence": 4, "soundness": 3, "presentation": 3, "contribution": 3, "strengths": "1. The introduction of T-Net, a regularized triangle-shaped network architecture, addresses significant limitations in existing DNAS methods, improving the accuracy and scalability of neural circuit generation.\n2. The paper provides a detailed sensitivity analysis of using DNAS for logic synthesis, which gives valuable insights into overfitting, structure bias, and learning difficulties, etc..\n3. Extensive experiments on multiple benchmarks show that T-Net significantly outperforms state-of-the-art methods, with improvements in both circuit accuracy and size", "weaknesses": "1. The multi-label transformation and regularized loss functions added additional complexity and reduces the efficiency of the model. \n2. More justifications are required for the evolutionary algorithm + reinforcement learning method for the circuit optimization process.\nminor: extra space after line 384 \"T\"", "quality": null, "clarity": null, "significance": null, "originality": null, "strengths_and_weaknesses": "", "was_revised": false, "final_justification": "", "rebuttal": "# Response to Reviewer gSL5\nWe thank the reviewer for the insightful and valuable comments. We respond to each comment as follows and sincerely hope that our rebuttal could properly address your concerns. If so, we would deeply appreciate it if you could raise your score. If not, please let us know your further concerns, and we will continue actively responding to your comments and improving our submission. \n\n## Weakness 1.\n\n> **1. The multi-label transformation and regularized loss functions added additional complexity and reduces the efficiency of the model.**\n\nWe have conducted experiments to demonstrate that our proposed modules not only **enhance accuracy significantly** but also **substantially reduce training time**.\n\n- The multi-label transformation module can significantly reduce input complexity by decomposing the entire truth-table (dataset) into several small sub-truth-tables (sub-datasets). As shown in Table 4 (in the main text), experiments show that using multi-label transformation reduces the wrong bits by 90%, and **reduces the training time by roughly 40%**. \n- Our proposed boolean hardness-aware loss also significantly enhanced the efficiency of our circuit generation. As shown in Table 5 in the attached pdf in Global Response, this loss function **reduces training time by 20%** while preserving accuracy. For your convenience, we quote Table 5 as follows.\n\nTable 5. The ablation study demonstrates that the \nboolean hardness-aware loss significantly reduces training time by 19.9\\%. The reported time is the training time required to achieve 99\\% accuracy.\n| Circuit | Training Time(h) |  | Impr.(%) |\n|:---:|:---:|:---:|:---:|\n|  | w/o. Loss | w. Loss |  |\n| Espresso5 | 10.4 | 9.9 | 4.8% |\n| LogicNets2 | 14.5 | 11.3 | 22.1% |\n| Arithmetic2 | 10.7 | 7.6 | 29.0% |\n| Random1 | 7.3 | 5.6 | 23.6% |\n| Average | 10.7 | 8.6 | **19.9%** |\n\n## Weakness 2.\n\n> **2. More justifications are required for the evolutionary algorithm + reinforcement learning method for the circuit optimization process.**\n\nCircuit optimization is recognized as an NP-hard problem, where traditional methods, often greedy and local, struggle to achieve optimal solutions. Reinforcement learning (RL) has demonstrated robust capabilities in navigating extensive search spaces, prompting the exploration of RL-based strategies to identify optimal sequences of circuit optimization operations.\nNevertheless, due to the expansive and irregular nature of the search space, RL can **suffer from limited exploratory capabilities**, often resulting in **convergence to local optima**. To address this challenge, we incorporate evolutionary algorithms (EA), which preserve a population of diverse circuit solutions, thereby **enhancing the exploration of the search space** and leading to the discovery of superior circuits. Additionally, as shown in Table 3 in the main text, our novel circuit optimization approach outperforms previous state-of-the-art optimization methods.\n\n> **3. minor: extra space after line 384 \"T\"**\n\nThanks for pointing out this typo. We will correct it accordingly.\n\n## Question 1.\n> **4. How the proposed T-Net compare to previous SOTA in terms of model size, latency, energy efficiency etc?**\n\nTable 6 in the attached pdf in Global Response presents a comparison between T-Net and the SOTA DNAS (PR-DARTS [1]) in terms of model size, latency, and training time. The table shows that our method achieves perfect accuracy with **29%** shorter training time. Additionally, our parameters, model size, and latency are comparable to the SOTA.  For your convenience, we quote Table 6 as follows.\n\nTable 6. Comparation of T-Net and the SOTA DNAS baseline in terms of model efficiency. The table shows that our method achieves perfect accuracy with 29\\% shorter training time. Additionally, our parameters, model size, and latency are comparable to the SOTA.\n|  | Acc(%) |  | Parameter (K) |  | Model size(KB) |  | Latency(s) |  | Training Time(h) |  |\n|:---:|:---:|:---:|---:|:---:|:---:|:---:|:---:|:---:|:---:|:---:|\n|  | PR-DARTS | T-Net | PR-DARTS | T-Net | PR-DARTS | T-Net | PR-DARTS | T-Net | PR-DARTS | T-Net |\n| Espresso5 | 98.53 | 100 | 298 | 287 | 1182 | 1138 | 0.114 | 0.113 | 12.6 | 10.1 |\n| Logicnets2 | 97.64 | 100 | 751 | 733 | 2952 | 2882 | 0.246 | 0.190 | 15.4 | 11.7 |\n| Arithmetic2 | 96.15 | 100 | 733 | 718 | 2880 | 2819 | 0.155 | 0.180 | 16.9 | 7.8 |\n| Random1 | 91.89 | 100 | 266 | 224 | 1061 | 898 | 0.103 | 0.084 | 7.2 | 5.8 |\n\n[1] Pan Zhou, et al. Theory-inspired path-regularized differential network architecture search. NeurIPS, 2020.\n\n## Question 2.\n> **5. Why no parameter for Appendix Table 7 &st?**\n\nThanks for the question. Indeed, the &st operator does not possess tunable hyperparameters. We will update the table to indicate 'N/A' for this operator's parameter in the revised manuscript.", "claims_and_evidence": "", "methods_and_evaluation_criteria": "", "theoretical_claims": "", "experimental_designs_or_analyses": "", "relation_to_broader_scientific_literature": "", "essential_references_not_discussed": "", "other_strengths_and_weaknesses": "", "other_comments_or_suggestions": "", "questions_for_authors": "", "summary_of_paper": "", "summary_of_recommendation": "", "technical_quality": "", "clarity_of_presentation": "", "potential_impact": "", "robotics_focus": "", "quality_of_limitations": "", "questions_for_rebuttal": "", "reasons_to_accept": "", "reasons_to_reject": "", "questions_to_authors": "", "extra_scores": {}}, {"review_id": "UvFLBlDRXt", "reviewer": "Reviewer_PMQo", "summary": "Existing DNAS methods face challenges in accurately generating circuits, particularly with large-scale circuits, and exhibit high sensitivity to random initialization. To address these challenges, this paper proposes a framework named T-Net. The experiments demonstrate that T-Net can precisely generate large bit-width circuits and that the generated circuits show a significant improvement in circuit area compared to traditional methods.", "questions": "1. Please include more cases from the four benchmarks (Espresso, LogicNets, Random, and Arithmetic) to make the experiment more convincing.\n2. Please provide a comparison with Google DeepMind's DNAS Skip on the IWLS benchmark, given the claim that T-Net is state-of-the-art in IWLS 2022 and 2023.", "limitations": "Yes, the authors have stated the limitations of their work.", "rating": 5, "confidence": 4, "soundness": 2, "presentation": 3, "contribution": 2, "strengths": "Through a detailed analysis, the paper presents insightful observations that underpin current challenges, showcasing a strong logical progression in its argument. The proposed T-Net highlights its capability to generate exact circuits and precisely generate large bit-width circuits.", "weaknesses": "The experimental section raises some concerns. \n\n1. The paper evaluates T-Net using circuits from four benchmarks: Espresso, LogicNets, Random, and Arithmetic. However, the results seem curated, as the paper does not provide results for specific cases such as Espresso 1, Espresso 2, Espresso 5, and Espresso 6. \n2. The paper claims that T-Net is a state-of-the-art approach based on 72 competitive winners in the IWLS 2022 and 2023 competitions. Additionally, the paper mentions re-implementing DNAS Skip by Google DeepMind for the IWLS 2023 competition. However, the authors should compare T-Net with DNAS Skip on the IWLS benchmark using Google DeepMind's results for a more robust comparison.", "quality": null, "clarity": null, "significance": null, "originality": null, "strengths_and_weaknesses": "", "was_revised": false, "final_justification": "", "rebuttal": "# Response to Reviewer PMQo\nWe thank the reviewer for the insightful and valuable comments. We respond to each comment as follows and sincerely hope that our rebuttal could properly address your concerns. If so, we would deeply appreciate it if you could raise your score. If not, please let us know your further concerns, and we will continue actively responding to your comments and improving our submission.\n\n## Weakness 1 & Question 1.\n\n> **1. The paper does not provide results for specific cases such as Espresso 1, Espresso 2, Espresso 5, and Espresso 6. Please include more cases from the four benchmarks (Espresso, LogicNets, Random, and Arithmetic) to make the experiment more convincing**\n\nThanks for the valuable suggestion. We indeed conducted experiments on circuits such as Espresso 1, Espresso 2, Espresso 5, and Espresso 6 as shown in Appendix E.2 (Tables 8, 9, and 10) in the main text. The results demonstrate that our method **improves the average generation accuracy by 17.5%**, **reduces the number of generated nodes by 33.4%**, and **reduces the optimized circuit size by 68.7%** on these cases compared to traditional baselines. \n\nIn addition, we have conducted experiments on 30 more circuits from the IWLS benchmark. Please see the next response for details.\n\n## Weakness 2 & Question 2.\n\n> **2. Please provide a comparison with Google DeepMind's DNAS Skip on the IWLS benchmark.**\n\nThanks for the valuable suggestion. We have compared our method with Google DeepMind's contest results on **30 more circuits** from the IWLS benchmark as shown in Table 2 in the attached pdf in Global Response. The results show that our method **achieves 3.03% node reduction** compared with Google DeepMind's contest results.  For your convenience, we quote Table 2 as follows.\n\nIn addition, the 18 circuits used in the main text are indeed sourced from the IWLS benchmark as well, and we compared our method with Google DeepMind's contest results on these circuits in Tables 3 and 10 in the main text (achieving 5.36% node reduction).\n\nTable 2. We evaluate our approach on 30 other circuits in the IWLS benchmark. \nOur T-Net surpasses the traditional method by 10.64\\%, and surpasses the IWLS 2023 champion, Google DeepMind, by 3.03\\% after optimization.\n|  |  |  |  | Generation |  |  | Optimization |  |  |\n|---|---|:---:|:---:|:---:|:---:|:---:|:---:|:---:|:---:|\n| Benchmark | IWLS | PI | PO | SOP | T-Net(ours) | Impr.(%)↑ | Google | Ours | Impr.(%)↑ |\n| Espresso | ex49 | 8 | 16 | 133 | 123 | 7.52 | 39 | 39 | 0.00 |\n| Espresso | ex38 | 10 | 11 | 72 | 60 | 16.67 | 27 | 27 | 0.00 |\n| Espresso | ex28 | 8 | 16 | 141 | 123 | 12.77 | 39 | 39 | 0.00 |\n| Espresso | ex46 | 6 | 13 | 55 | 50 | 9.09 | 31 | 31 | 0.00 |\n| Espresso | ex16 | 6 | 4 | 39 | 34 | 12.82 | 17 | 17 | 0.00 |\n| Espresso | ex35 | 8 | 3 | 17 | 18 | -5.88 | 16 | 15 | 6.25 |\n| Espresso | ex48 | 16 | 23 | 2135 | 1913 | 10.40 | 482 | 490 | -1.66 |\n| LogicNets | ex94 | 13 | 6 | 100 | 86 | 14.00 | 33 | 33 | 0.00 |\n| LogicNets | ex86 | 15 | 7 | 406 | 399 | 1.72 | 146 | 125 | 14.38 |\n| LogicNets | ex77 | 15 | 7 | 967 | 828 | 14.37 | 224 | 203 | 9.38 |\n| LogicNets | ex88 | 15 | 7 | 949 | 724 | 23.71 | 261 | 254 | 2.68 |\n| LogicNets | ex68 | 15 | 7 | 925 | 584 | 36.86 | 118 | 111 | 5.93 |\n| LogicNets | ex87 | 15 | 7 | 992 | 741 | 25.30 | 322 | 318 | 1.24 |\n| LogicNets | ex91 | 15 | 7 | 838 | 746 | 10.98 | 200 | 198 | 1.00 |\n| LogicNets | ex93 | 15 | 7 | 73 | 69 | 5.48 | 41 | 39 | 4.88 |\n| LogicNets | ex95 | 13 | 6 | 152 | 140 | 7.89 | 62 | 56 | 9.68 |\n| LogicNets | ex90 | 15 | 7 | 1965 | 1714 | 12.77 | 413 | 432 | -4.60 |\n| LogicNets | ex95 | 13 | 6 | 152 | 164 | -7.89 | 62 | 56 | 9.68 |\n| LogicNets | ex99 | 15 | 7 | 228 | 257 | -12.72 | 79 | 72 | 8.86 |\n| Arithmetic | ex53 | 10 | 5 | 82 | 81 | 1.22 | 35 | 34 | 2.86 |\n| Arithmetic | ex56 | 15 | 7 | 70 | 61 | 12.86 | 29 | 29 | 0.00 |\n| Arithmetic | ex51 | 10 | 5 | 97 | 91 | 6.19 | 26 | 26 | 0.00 |\n| Arithmetic | ex54 | 10 | 7 | 14 | 14 | 0.00 | 12 | 12 | 0.00 |\n| Arithmetic | ex50 | 10 | 5 | 35 | 25 | 28.57 | 18 | 18 | 0.00 |\n| Arithmetic | ex58 | 15 | 7 | 209 | 218 | -4.31 | 77 | 71 | 7.79 |\n| Arithmetic | ex57 | 15 | 7 | 1342 | 531 | 60.43 | 81 | 83 | -2.47 |\n| Random | ex06 | 15 | 4 | 2267 | 2065 | 8.91 | 1075 | 961 | 10.60 |\n| Random | ex07 | 15 | 4 | 1327 | 1256 | 5.35 | 112 | 107 | 4.46 |\n| Random | ex03 | 10 | 3 | 75 | 75 | 0.00 | 24 | 24 | 0.00 |\n| Random | ex02 | 10 | 3 | 149 | 143 | 4.03 | 69 | 69 | 0.00 |\n|  | Average |  |  | 533.53 | 444.43 | **10.64** | 139.00 | 132.97 | **3.03** |", "claims_and_evidence": "", "methods_and_evaluation_criteria": "", "theoretical_claims": "", "experimental_designs_or_analyses": "", "relation_to_broader_scientific_literature": "", "essential_references_not_discussed": "", "other_strengths_and_weaknesses": "", "other_comments_or_suggestions": "", "questions_for_authors": "", "summary_of_paper": "", "summary_of_recommendation": "", "technical_quality": "", "clarity_of_presentation": "", "potential_impact": "", "robotics_focus": "", "quality_of_limitations": "", "questions_for_rebuttal": "", "reasons_to_accept": "", "reasons_to_reject": "", "questions_to_authors": "", "extra_scores": {}}, {"review_id": "JgoAkLZqwn", "reviewer": "Reviewer_Qczw", "summary": "The manuscript describes a method to synthesize logic circuits using neural architecture search (NAS). The authors first evaluate some\nshort-comings of earlier approaches and develop a generation method that adds regularization of skip connections, a prior on the shape of the circuit (triangle shape), transforms truth tables, and adapts a loss function. They also propose a circuit optimization step which\nutilizes reinforcement learning and evolutionary optimization. They use a number of benchmarks to show that the circuit generation performs very well compared to earlier NAS methods, in particular for larger circuit sizes. For the circuit optimization, the proposed method is similar or slightly better to the state-of-the-art.", "questions": "See above", "limitations": "Limitations are addressed.", "rating": 5, "confidence": 3, "soundness": 3, "presentation": 1, "contribution": 2, "strengths": "- Good results compared to the earlier methods, in particular for the  generation of large circuits, slightly improving on the  state-of-the-art for circuit optimization.\n\n- The authors investigate both generation and optimization of logic circuits.", "weaknesses": "- The paper is poorly written in a sense that all relevant methods and many essential details and text sections are pushed into the appendix (that is almost 10 pages long). The main text reads just like a long introduction and discussion. It is not possible to follow what exactly was done when reading only the main text. This is not in line with the 9 page requirement. The appendix should be reserved for truly supplementary data and proofs.\n\n- The paper motivates with saying that differential neural architecture search (DNAS) has weaknesses such as producing\nexcessive skip-connections. However, it turns out that this is (1)  not a problem of DNAS per se, but just an inadequate way to setup up\nand perform the DNAS. In fact, the authors' method also employs  DNAS but just adds some additional constraints and modifies the loss  and adds regularization. Thus the motivation is misleading.  Moreover, (2), as the authors acknowledge, this \"curse of skip\nconnection\" is actually a known issue and already has been addressed by others (e.g. Darts). So there is little novelty in this section.\n\n- The math description e.g. in general is very poor, for instance in section 5.2 (Eq 2) proper math symbols should be used instead of\n  \"in\", \"out\", \"unit\" etc. It is also not clear what the indeces mean,  for instance \"unit^{l, k, p}\" is a tensor with dimension l x K ? So\n  it is just a matrix? What is the third index (p) then? Also there is  no equation in the main text for the loss and other details, such as\n  the evolutionary and RL approaches, making it impossible to follow what actually was done exactly.\n\n- Prior approaches to the problem are not well explained in the main text (only a section in the appendix).\n\n- From the ablation study it seems that regularizing the skip connections has by far the most impact, while the loss adaption and\n  the triangle shape prior improves only relatively little. Given, that the  skip-connection issues was already addressed by others, it seems\n  that the contribution of the study is somewhat incremental.", "quality": null, "clarity": null, "significance": null, "originality": null, "strengths_and_weaknesses": "", "was_revised": false, "final_justification": "", "rebuttal": "# Response to Reviewer Qczw\nWe thank the reviewer for the insightful and valuable comments. We respond to each comment as follows and sincerely hope that our rebuttal could properly address your concerns. If so, we would deeply appreciate it if you could raise your score. If not, please let us know your further concerns, and we will continue actively responding to your comments and improving our submission. \n## Weakness 1.\n> **1. Relevant methods and essential details are pushed into the appendix.**\n\nPlease see Global Response 1.\n## Weaknesses 2 and 5.\n> **2. The motivation that \"DNAS has weaknesses such as producing excessive skip-connections\" is misleading.**\n\nRecent works [1,2] have applied traditional DNAS methods, such as DARTS [3], to circuit generation, revealing a promising direction. Our motivating insight **revisits the direct application of traditional DNAS methods to circuit generation** and identifies several specific challenges for circuit generation, including the curse of skip-connections. Note that the skip-connection problem in circuit generation **is significantly different from** that in traditional DNAS (see the next response).\n> **3. This \"curse of skip connection\" is already addressed by methods like Darts.** \n\n**Differences in the Skip-Connection Challenge** In traditional DNAS, the skip-connection problem arises as **the skip-connection operation often dominates other operations**, such as convolution and zero operations. In contrast, when applying DNAS to circuit generation, a neural network is formulated as a circuit graph, where each neuron represents a logic gate and connections between neurons represent wires connecting these logic gates. The neurons are fixed as logic gates, and the connections between neurons are learnable. Most learnable connections skip layers, called **skip-connections in circuit neural networks**. In this paper, we found that the traditional DNAS method **tends to overfit to skip-connections that bypass a large number of layers**, a phenomenon we call the curse of skip-connections in circuit generation. (1) The **definitions of skip-connections** in DNAS and circuit generation are **different**. (2) In traditional DNAS, it is required to encourgae balance between skip-connection operation and other operations. In contrast, it is required to balance between **numerous skip-connections** that span different layers in circuit generation. \n\n**Inapplicability of Existing DNAS Methods to Circuit Generation**  We have compared our method with DNAS-based methods for addressing the skip-connection challenge, including P-DARTS [4], PR-DARTS [5], and DARTS-ES [6]. As shown in Table 1 in attached pdf in Global Response, the results demonstrate that our method **significantly outperforms** these approaches. The primary reason is that **these methods struggles to balance between numerous skip-connections** in circuit generation tasks. In contrast, our method proposes **a novel layer-aware regularized skip-connection** module, which effectively balances skip-connections that span different layers.\n> **4. The loss adaption and the triangle shape prior improves only relatively little.**\n\nWe have conducted detailed ablation experiments to show that each of our proposed modules is significant. The results in Tables 3, 4, and 5 in attached pdf in Global Response show that the proposed loss **enhances accuracy to 99%**, and the T-architecture achieves an average **node reduction** of **16.9%** and a **training time reduction** of **40.8%**.\n## Weakness 3.\n> **5. The math description is poor. It is also not clear what the indexes p mean.**\n\nThanks for the valuable suggestion. We have revised our math description accordingly. Note that each neuron (And gate) in the circuit neural network has two input signals. The $unit^{l, k, p}$ is a tensor with dimension $l \\times K \\times 2$. The index $p$ represents the $p^{th}$ input signal of current neuron. Details are as follows.\n\n(**Revision**) We denote the output of the $k^{th}$ neuron in the $l^{th}$ layer by $\\textbf{o}^{l,k}$. We denote the $p$-th input of the neuron (NAND gate) $\\textbf{o}^{l,k}$ by $\\textbf{i}\\_{p}^{l,k}$, where $p \\in \\{0,1\\}$. Note that each neuron $o^{l,k}$ has two inputs $i^{l,k}\\_{0}$ and $i^{l,k}\\_{1}$, and can be connected to any neuron with layer number smaller than $l$ as its input neuron. We parameterize the connections of each neuron $o^{l,k}$ by a tensor of learnable parameters $\\mathbf{\\theta}^{l,k} \\in \\mathbb{R}^{2 \\times (l-1) \\times K}.$ Each parameter in the tensor $\\mathbf{\\theta}^{l,k}\\_{p,i,j}$ represents the probability of connecting the $j^{th}$ neuron in the $i^{th}$ layer to the $p^{th}$ input of current neuron $o^{l,k}$. The computation of the $p^{th}$ input value for the neuron $o^{l,k}$ takes the form of \n$$i_p^{l, k} :=\\sum_{i=0}^{l-1} \\sum_{j=1}^{K} o^{i,j}  \\left[\\operatorname{softmax}\\left(\\mathbf{\\theta}^{l, k}\\right)\\right]_{p,i,j}, p=0,1;\\ \\ o^{l,k} := 1 - \\Pi\\_{p=0}^{1} i_p^{l, k}$$\n> **5. There is no equation in the main text for the loss and other details.**\n\nThanks for the suggestion. We will provide these equations in the main text.\n## Weakness 4.\n> **6. Prior approaches to the problem are not well explained in the main text.**\n\nPlease see Global Response 2.\n\n[1] Designing better computer chips. Google DeepMind, 2023, https://deepmind.google/impact/optimizing-computer-systems-with-more-generalized-ai-tools.\n\n[2] Peter Belcak, et al. Neural combinatorial logic circuit synthesis from input-output examples. NeurIPS Workshop, 2022.\n\n[3] Hanxiao Liu, et al. Darts: Differentiable architecture search. ICLR 2019.\n\n[4] Xin Chen, et al. Progressive differentiable architecture search: Bridging the depth gap between search and evaluation. ICCV 2019.\n\n[5] Pan Zhou, et al. Theory-inspired path-regularized differential network architecture search. NeurIPS 2020.\n\n[6] Zela, et al. Understanding and Robustifying Differentiable Architecture Search. ICLR 2020.", "claims_and_evidence": "", "methods_and_evaluation_criteria": "", "theoretical_claims": "", "experimental_designs_or_analyses": "", "relation_to_broader_scientific_literature": "", "essential_references_not_discussed": "", "other_strengths_and_weaknesses": "", "other_comments_or_suggestions": "", "questions_for_authors": "", "summary_of_paper": "", "summary_of_recommendation": "", "technical_quality": "", "clarity_of_presentation": "", "potential_impact": "", "robotics_focus": "", "quality_of_limitations": "", "questions_for_rebuttal": "", "reasons_to_accept": "", "reasons_to_reject": "", "questions_to_authors": "", "extra_scores": {}}, {"review_id": "APuNvQp6qO", "reviewer": "Reviewer_qf83", "summary": "The paper studies the application of differentiable neural architecture search (DNAS) to the problem of logic synthesis from input-output examples. The authors first analyze several challenges when directly applying existing DNAS methods to the problem. Based on those findings three modifications are proposed: (1) A transformation of the input-output examples that decreases the number of input and increases the number of output variabels. (2) Changing the network search space from rectangular to triangular shaped to be more aligned with typical network shapes. (3) Adding a regularization to avoid overfitting to shallow circuits and adding weights to the loss of positive and negative examples. In addition to adapting DNAS methods, the authors present a neural circuit optimization postprocess which learns a sequence of circuit operations to optimize the size of the circuit. The sequence is learned with reinforcement learning and an evolutionary algorithm. In an experimental evaluation, the authors demonstrate that both the modification of the DNAS method and the circuit optimization postprocess yield large gains in terms of correctness and circuit size.", "questions": "Is the circuit optimization evaluated on top of T-Net or is the input circuit obtained in a different way?", "limitations": "The authors only discuss the GPU requirement as a limitation such that important aspects are missing from the discussion. For example, even though T-Net largely improves on accuracy compared to previous methods, it is not guaranteed to reach perfect accuracy.", "rating": 6, "confidence": 3, "soundness": 3, "presentation": 2, "contribution": 3, "strengths": "- Recent International Workshop on Logic & Synthesis (IWLS) contest results sparked interest in the application of neural architecture search (NAS) to logic synthesis. To the best of my knowledge, this paper is the first to extensively study this promising combination. The paper first presents valuable insights into the challenges of applying the NAS methods as is. Derived from those challenges the authors propose well-motivated changes to the standard methods. In the experimental evaluation, it is shown that each change either contributes to improving the accuracy or decreasing the size of the resulting circuit.\n- As part of the framework, the authors introduce a novel circuit optimization based on learning a sequence of circuit operations with reinforcement learning and an evolutionary algorithm. This optimization step does not only seem valuable in combination with the introduced T-Net but also as an independent postprocess on top of other logic synthesis techniques.\n- The size of the circuits is evaluated in comparison with the top teams from recent IWLS contests. The winners of IWLS can be considered state-of-the-art methods and the experimental evaluation demonstrates substantial improvements over them. To perform this comparison the authors re-implemented some of the approaches which have not been open-sourced. If the authors were to make their code publicly available this would also be a valuable contribution to the research community.", "weaknesses": "- Large parts of the paper rely on previous work for the background of the problem and the method itself. For example, the paper does not formally introduce the logic synthesis problem from input-output examples, nor does the paper introduce the notion of differentiable neural architecture search. The exact method of relaxing a logic neural network for training and discretizing for evaluation only becomes evident in the second half of the paper (Section 5.2), making it difficult to understand the first half on motivating challenges. Another difficulty in following the paper is that the authors refer to the appendix for many aspects of the approach. For example, experiments on the motivating challenges, the implementation of the newly introduced regularization and weighted loss, and details on the circuit optimization in general can only be found in the appendix.\n- Since the authors already compare with the top winners from the IWLS contests, it is not clear to me why they do not evaluate the IWLS benchmarks. Instead, the authors choose a smaller (potentially less challenging) set of benchmarks without providing insights into how the benchmarks were selected.", "quality": null, "clarity": null, "significance": null, "originality": null, "strengths_and_weaknesses": "", "was_revised": false, "final_justification": "", "rebuttal": "# Response to Reviewer qf83\nWe thank the reviewer for the insightful and valuable comments. We respond to each comment as follows and sincerely hope that our rebuttal could properly address your concerns. If so, we would deeply appreciate it if you could raise your score. If not, please let us know your further concerns, and we will continue actively responding to your comments and improving our submission. \n\n## Weakness 1.\n\n> **1. The paper does not formally introduce the logic synthesis problem from input-output examples and the notion of differentiable neural architecture search.** \n\nThanks for the valuable suggestions. We have revised the Background Section as follows.\n\n**Formulation of LS from IO examples** In recent years, synthesizing circuits from IO examples has gained increasing attention [1][2][3]. Specifically, researchers aim to use machine learning to generate a circuit based on a truth table that describes the circuit's functionality. Each line in the truth table represents an input-output pair, indicating the output produced by the circuit for a given input. In the machine learning domain, researchers formulate the truth table as a training dataset comprising many input-output pairs and use an ML model to generate circuits that accurately fit the dataset.\n \n**DNAS for LS from IO Examples** Recent works [1][2] propose leveraging traditional DNAS methods for generating circuit graphs from IO examples, showing a promising direction for next-generation logic synthesis. Specifically, they formulate a neural network as a circuit graph, where each neuron represents a logic gate and connections between neurons represent wires connecting these logic gates. For a parameterized neural network, the neurons are fixed as logic gates, and the connections between neurons are parameterized as learnable parameters. To enable differentiable training via gradient descent, continuous relaxation is introduced into discrete components of the neural network. First, the logical operations of logic gates (neurons) are translated into their differentiable counterparts. For example, $a \\ \\textit{AND} \\ b$ is relaxed to $a\\cdot b$ [4]. Second, discrete network connections are parameterized using Gumbel-softmax [5].\n\n> **2. Another difficulty in following the paper is that the authors refer to the appendix for many aspects of the approach.** \n\nThanks for the valuable suggestion. We will revise our manuscript by retaining the key content in the main text and moving the minor content to the appendix. Specifically, we will update the \"Background,\" \"Motivation,\" and \"Method\" Sections as follows.\n\nFor Background, we present the problem formulation of **logic synthesis (LS) from input-output examples**, and details of **the traditional DNAS approach for LS**. \n\nFor Motivation, we first present the main challenge of the traditional DNAS for LS that the method **struggles to generate circuits accurately**, especially for large circuits. We then present two major reasons for this challenge: **the curse of skip-connection** and **the structure bias of circuits**. \n\nFor Method, we first present the three key modules for neural circuit generation. 1) To reduce the learning complexity of **large circuits**, we present the multi-label transformation module to decompose a large truth-table (dataset) into several small sub-truth-tables (sub-datasets). 2) To address **the curse of skip-connection challenge**, we present details of the regularized skip-connections module. 3) To **leverage the structure bias of circuits**, we present details of the triangle-shaped network architecture. We then present details of our circuit optimization approach and **provide the pseudocode of the algorithm**.\n\n## Weakness 2.\n\n> **3. Since the authors already compare with the top winners from the IWLS contests, it is not clear to me why they do not evaluate the IWLS benchmarks.**\n\nThanks for the valuable suggestion. We have compared our method with Google DeepMind's contest results on **30 more circuits** from the IWLS benchmark as shown in Table 2 in the attached pdf in Global Response. The results show that our method **achieves 3.03% node reduction** compared with Google DeepMind's contest results.\n\nIn addition, the 18 circuits used in the main text are indeed sourced from the IWLS benchmark as well, and we compared our method with Google DeepMind's contest results on these circuits in the main text (achieving 5.36% node reduction).\n\n## Question 1:\n\n> **4. Is the circuit optimization evaluated on top of T-Net or is the input circuit obtained in a different way?**\n\nYes, the results of our method are obtained by optimizing circuits generated using T-Net.\n\n## Limitation 1.\n\n> **5. T-Net is not guaranteed to reach perfect accuracy.**\n\nTo ensure perfect accuracy in our circuit generation, we applied a legalization method to our final generated circuits as detailed in Appendix D.6.\n\n## Open-source code.\n\n> **6. If the authors were to make their code publicly available this would also be a valuable contribution to the research community.**\n\nYes, we will make our code publicly available once our paper is accepted.\n\n[1] Designing better computer chips. Google DeepMind, 2023, https://deepmind.google/impact/optimizing-computer-systems-with-more-generalized-ai-tools/.\n\n[2] Peter Belcak, et al. Neural combinatorial logic circuit synthesis from input-output examples. NeurIPS Workshop, 2022.\n\n[3] IWLS Programming Contest Series Machine Learning + Logic Synthesis. IWLS, 2024, https://www.iwls.org/contest/.\n\n[4] Petersen, et al. Deep differentiable logic gate networks. NeurIPS, 2018.\n\n[5] Jang, et al. Categorical Reparametrization with Gumble-Softmax. ICLR, 2017.", "claims_and_evidence": "", "methods_and_evaluation_criteria": "", "theoretical_claims": "", "experimental_designs_or_analyses": "", "relation_to_broader_scientific_literature": "", "essential_references_not_discussed": "", "other_strengths_and_weaknesses": "", "other_comments_or_suggestions": "", "questions_for_authors": "", "summary_of_paper": "", "summary_of_recommendation": "", "technical_quality": "", "clarity_of_presentation": "", "potential_impact": "", "robotics_focus": "", "quality_of_limitations": "", "questions_for_rebuttal": "", "reasons_to_accept": "", "reasons_to_reject": "", "questions_to_authors": "", "extra_scores": {}}]

Author rebuttal:
# Global Response
We would like to extend our sincere gratitude for your valuable feedback and constructive suggestions. For your convenience, we have prepared a summary of our responses and outlined how we have addressed the reviewers' concerns as follows. We sincerely hope that this summary will facilitate your review and lighten your workload.

Our paper has received encouraging positive feedbacks from the reviewers, such as "**addresses significant limitations** (Reviewer gSL5)", "**valuable insights** (Reviewers gSL5 and qf83)", "**significantly outperforms/substantial improvements** (Reviewers gSL5 and qf83)", "**insightful observations** (Reviewer PMQo)", "**strong logical progression**" (Reviewer PMQo), "**the first to extensively study**" (Reviewer qf83), "**well-motivated**" (Reviewer qf83).

We outline how we have addressed the concerns raised by each reviewer as follows.

## Common Concerns
> **(Reviewers Qczw and qf83) 1. All relevant methods and many essential details are pushed into the appendix.** 

Thanks for the valuable suggestion. We will revise our manuscript by retaining the key content in the main text and moving the minor content to the appendix. Specifically, we will revise the "Background," "Motivation," and "Method" Sections as follows.

For Background, we present the problem formulation of **logic synthesis (LS) from input-output examples**, and details of **the traditional DNAS approach for LS**. 

For Motivation, we first present the main challenge of the traditional DNAS for LS that the method **struggles to generate circuits accurately**, especially for large circuits. We then present two major reasons for this challenge: **the curse of skip-connection** and **the structure bias of circuits**. 

For Method, we first present the three key modules for neural circuit generation. 1) To reduce the learning complexity of **large circuits**, we present the multi-label transformation module to decompose a large truth-table (dataset) into several small sub-truth-tables (sub-datasets). 2) To address **the curse of skip-connection challenge**, we present details of the regularized skip-connections module. 3) To **leverage the structure bias of circuits**, we present details of the triangle-shaped network architecture. We then present details of our circuit optimization approach and **provide the pseudocode of the algorithm**.
> **(Reviewers Qczw and qf83) 2. Background on prior approaches to the problem are not well explained in the main text.**

Thanks for the valuable suggestions. We have revised the Background Section as follows.

**Formulation of LS from IO examples** In recent years, synthesizing circuits from IO examples has gained increasing attention. Specifically, researchers aim to use machine learning to generate a circuit based on a truth table that describes the circuit's functionality. Each line in the truth table represents an input-output pair, indicating the output produced by the circuit for a given input. In the machine learning domain, researchers formulate the truth table as a training dataset comprising many input-output pairs and use an ML model to generate circuits that accurately fit the dataset.
 
**DNAS for LS from IO Examples** Recent works propose leveraging traditional DNAS methods for generating circuit graphs from IO examples, showing a promising direction for next-generation logic synthesis. Specifically, they formulate a neural network as a circuit graph, where each neuron represents a logic gate and connections between neurons represent wires connecting these logic gates. For a parameterized neural network, the neurons are fixed as logic gates, and the connections between neurons are parameterized as learnable parameters. To enable differentiable training via gradient descent, continuous relaxation is introduced into discrete components of the neural network. First, the logical operations of logic gates (neurons) are translated into their differentiable counterparts. For example, $a \ \textit{AND} \ b$ is relaxed to $a\cdot b$. Second, discrete network connections are parameterized using Gumbel-softmax.
> **(Reviewers PMQo and qf83) 3. Evaluation on IWLS benchmark.** 

We have compared our method with Google DeepMind's contest results on 30 more circuits from IWLS benchmark. The results show that our method still outperforms Google DeepMind's contest results.


## **Reviewer gSL5**
> **4. Module efficiency.** 

We have conducted an ablation study to demonstrate that multi-label transformation and our loss function reduce the training time by roughly 40%.

> **5. Justification for mombining RL and EA.** 

We have provided detailed reasons for integrating RL and EA in circuit optimization, specifically to enhance the exploration of search space.

> **6. Model metrics.** 

We have conducted experiments to compare the size, latency, and training time of our model against the state-of-the-art method, demonstrating our model's high efficiency.

> **7. Other details.** 

We have provided these details accordingly.

## **Reviewer PMQo**
> **8. More cases from the 4 benchmarks.**

We indeed conducted experiments on circuits such as Espresso 1, 2, 5, and 6 as shown in Appendix E.2 in the main text.
## **Reviewer Qczw**
> **9. The "curse of skip connection" is already addressed by methods like Darts.**

We have explained that skip-connections pose unique challenges in circuit generation. We have evaluated three methods tailored for the challenge in DNAS and our approach significantly outperforms them. 

> **10. The loss adaption and the triangle shape prior improves only relatively little.**

We have conducted experiments to demonstrate that each of our modules are significant for improving generation accuracy, reducing training time and circuit sizes.
> **11. The math description is poor.**

We have revised our math description accordingly.

## **Reviewer qf83**
> **12. Other details.**

We have provided these details accordingly.

Meta-review: The paper studies the logic synthesis (LS) task for integrated circuit design. It thoroughly analyzes current methods and identifies some key limitations: overfitting to skip connections, structure bias, and imbalanced learning difficulties. To tackle these limitations, the author develops a generation method that adds regularization of skip connections, a prior on the shape of the circuit (triangle shape), transforms truth tables, and adapts a loss function. They also propose a circuit optimization step that utilizes reinforcement learning and evolutionary optimization. Experiments demonstrate that T-Net outperforms state-of-the-art methods in generating precise and scalable circuits. The reviews generally appreciate the thorough analysis of current methods and the contribution of the T-Net method. Some concerns have been raised about the soundness of the experiment. The author has addressed them with more results.
Decision: Accept (poster)