LithoBench: Benchmarking AI Computational Lithography for Semiconductor Manufacturing
Authors: Su Zheng
Haoyu Yang
Binwu Zhu
Bei Yu
Martin D.F. Wong
Venue: NeurIPS 2023 Datasets and Benchmarks Poster (2023)
Keywords: Computational Lithography
Inverse Lithography Technology
Semiconductor Manufacturing
Deep Learning
TL;DR: LithoBench is a dataset and benchmarking platform for computational lithography, supporting lithography simulation and mask optimization.

Abstract: Computational lithography provides algorithmic and mathematical support for resolution enhancement in optical lithography, which is the critical step in semiconductor manufacturing. 
The time-consuming lithography simulation and mask optimization processes limit the practical application of inverse lithography technology (ILT), a promising solution to the challenges of advanced-node lithography. 
Although various machine learning methods for ILT have shown promise for reducing the computational burden, this field is in lack of a dataset that can train the models thoroughly and evaluate the performance comprehensively. 
To boost the development of AI-driven computational lithography, we present the LithoBench dataset, a collection of circuit layout tiles for deep-learning-based lithography simulation and mask optimization. 
LithoBench consists of more than 120k tiles that are cropped from real circuit designs or synthesized according to the layout topologies of famous ILT testcases. 
The ground truths are generated by a famous lithography model in academia and an advanced ILT method. 
Based on the data, we provide a framework to design and evaluate deep neural networks (DNNs) with the data. 
The framework is used to benchmark state-of-the-art models on lithography simulation and mask optimization. 
We hope LithoBench can promote the research and development of computational lithography. 
LithoBench is available at https://anonymous.4open.science/r/lithobench-APPL.

LithoBench: Benchmarking AI Computational Lithography for Semiconductor Manufacturing
Su Zheng' Haoyu Yang² Binwu Zhu!
Bei Yu' Martin D.F. Wong
'The Chinese University of Hong Kong
VIDIA, Austin, USA 3 Hong Kong Baptist University
Abstract
Computational lithography provides algorithmic and mathematical support for resolution enhancement optical lithography, which is critical for semiconductor manufacturing. The time-consuming lithography simulation and mask optimization processes limit the practical application of inverse lithography technology (ILT), promising solution the challenges of advanced-node lithography. Although machine learning for ILT has shown promise for reducing the computational bur- den, this field lacks dataset that train the models thoroughly and evaluate the performance comprehensively. To boost the development of AI-driven com- putational lithography, we present the LithoBench dataset, collection of circuit layout tiles for deep-learning-beee based lithography simulation and mask optimization. LithoBench consists of more than 120k tiles that cropped from real circuit designs or synthesized according to topologies of widely adopted ILT testcases. Ground truths are generated by famous lithography model in academia and an advanced ILT method. We provide framework to design and evaluate deep neural networks (DNNs) with the data. The framework used to benchmark state-of- the-art models on lithography simulation and mask optimization. LithoBench is available httpt::://// :/g //gi thub. com/ coomsheellpp wwwaannntneeeccli.
Introduction
Semiconductor lithography transfers circuit patterns drawn on mask onto silicon wafer, which is essential for the fabrication of integrated circuits (IC). It typically accounts for about 30% of the cost of IC manufacturing, As transistor sizes continue to shrink, lithography tends be the technical limiting factor for further advances [T]. Diffraction or process effects may distort the patterns on the wafer, leading to performance degradation and even failures. Given the importance, how to ensure the correctness of semiconductor lithography becomes a critical issue in industry and academia.
Optical proximity correction (OPC) is technique used improve the accuracy and quality of lithography patterns on semiconductor wafers. OPC evoles from rule-based methods [2] to model- based approaches (3(5), improving the resilience manufacturing variation. Inverse lithography technology (ILT) 688 is a mathematically rigorous inverse approach that optimizes the mask to achieve the desired results on the wafer. It has been explored and developed the next generation of OPC, promising a solution to challenges of advanced technology such as extreme ultraviolet (EUV).
However, there exist significant challenges that limit the broad application of ILT. A major reason is that ILT typically consumes a significant amount of runtime, making it challenging to implement ILT production-level scale. Moreover, the patterns generated by ILT algorithms may be too complex to be produced efficiently. To alleviate the problems above, DNN-based ILT algorithms have been proposed to reduce the runtime and complexity 17) Compared with traditional methods, the improvement of DNN-based ILT algorithms has two aspects. Firstly, unlike traditional methods that
37th Conference on Neural Information Processing Systems (NeurIPS 2023) Track on Datasets and Benchmarks.

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Mark A
Princed
Loss Finction
12 Lasee LealZ T)
Lchograply G:M
Evalnation
PVB Lowe: LovalZ.
Cpt. Penalty: 18p (8)
Racl-ymapagaionn
ILT Betiemeet ())
Optimiaed Macic M
Targr Image
Model F(T)
Optimiaed
(a)
(b)
Figure Overview of (a) traditional ILT and (b) DNN-based ILT.
require multiple iterations to optimize the mask, DNN-based methods can generate a mask in one forward pass. A few iterations of finetuning can further improve the quality of the mask. Secondly, by incorporating loss functions for complexity reduction, deep learning methods remarkably improve the printability of ILT results [13 144. Deep learning shows great potential in advancing ILT.
Integrated circuits are represented by multi-layer layouts for manufacturing. A mask contains the patterns of one layout layer, optimized by ILT algorithms to produce desired printed patterns on silicon wafers. To achieve affordable runtimes, ILT algorithmss typically generate the entire mask by optimizing fixed-size tiles cropped from the layout layer (18). Fig. [a prepeennss a representative workflow of traditional ILT algorithms, which optimizes the mask iteratively. At each iteration, the lithography simulation model can output the printed image after the lithography processes. After that, the loss function evaluates the printed image in terms of error (L.2 loss), process variation band (PVB), complexity (cpx.), etc. Given a loss function, the mask can be optimized by gradient descent (7) and other methods [19 20 Fig. lb shows the DNN-based ILT flow. The input is the target image T, which contains the target shapes that should be printed. The DNN ILT model outputs the optimized mask M in one forward pass, which is significantly faster than traditional ILT.
In recent years, researchers have proposed various DNN-based ILT methods (9.17), which can significantly boost the speed and performance of ILT with excellent initialization, refinement, and GPU acceleration. However, since the ILT methods are evaluated in diffcrent scenarios with different training data, it is diffieult to compare them comprehensively and challenging apply them in production. Specifically, circuit layouts typically consist of multiple layers of patterns. The shape, size, and density of the patterns vary from layer to layer. An ILT method may have only been evaluated on metal-layer [44 or via-layer [12] testcases. Nevertheless, a via layer typically contains square shapes, while metal layer can include diverse rectilinear polygons. It is questionable to assert that one of the methods above is better because they are not evaluated in the same scenarios. In addition, some models trained synthetic data (9, while others focus real-world designs (2T). Therefore, a representative and comprehensive dataset should cover metal and via layers, as well as synthetic and real-world designs. It is valuable to construct common dataset that can train and evaluate DNN ILT models in various scenarios.
To evaluate ILT methods, multiple metrics should be considered. For example, L2 loss measures the difference between the printed patterns and the target shapes. PVB estimates the robustness of the mask against process variations. Shot count shows the complexity of the mask, which affects the manufacturing time and cost. Runtime is also an important factor. To choose an appropriate algorithm, users usually need make a trade-off between the metrics. As result, there is need for a platform that can effectively benchmark various II.T methods using comprehensive metrics.
DNN can be employed in ILT for lithography simulation mask optimization. In simple terms, the output of ILT is an optimized mask M', which can get similar results as the target patterns T after the lithography processes G(M"). Existing works [22 23 approximate the lithography processes G G(M") with DNN-based lithography simulation models, which can not only provide faster evaluation of the mask quality but also be used in mask refinement. DNN-based mask optimization models 99 11 12 16) are designed to directly obtain the optimized mask, formulated by M F(T).
To meet the above requirements, we present I LithoBench, a collection of circuit layout tiles to train DNN models for lithography simulation and mask optimization. Its benchmarking platform can provide extensive evaluation of the models. Our contributions summarized as follows.

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We assemble a dataset for DNN-based lithography simulation and mask optimization, which not only contains synthetic and real-world layout tiles but also covers metal and via layers. It is the first large-scale dataset for computational lithography built from real-world designs.
We implement a platform to evaluate the DNN models for lithography simulation and mask optimization. Users can design and select appropriate models with our platform by benchmarking them in terms of quality, robustness, complexity, runtime, etc.
We train and evaluate state-of-thhe-r (SOTA) DNN models for lithography simulation and mask optimization on LithoBench, providing comprehensive assessment of them.
2
Related Work
This section provides the fundamentals of ILT. We begin by discussing the commonly used lithography simulation method. Next, we describe typical ILT methods that solve mask optimization via numerical optimization. Then we review the latest advancements DNN models for lithography simulation and mask optimization. Finally, LithoBench is compared to existing datasets about lithography.
2.1 Lithography Simulation
The lithography simulation targets to approximate the real lithography process in chip manufacturing and provides an accurate estimation of the manufactured designs on silicon wafers. Lithography simulation consists of the optical projection and photoresist models. In optical projection, incident light passes through the mask, transmitting the spatial information of the mask patterns M to the optical projection system. This results in the transformation of the input light intensity distribution into an acrial intensity distribution on the wafer plane. The intensity distribution is commonly represented by an acrial image I. The process can be modeled by Hopkins' diffraction theory (24)
K
I- H = Σ hhe @ MP.
A=1
where h& is the kth optical kernel function and μn is the corresponding weight. The notation x stands for convolution operation. gets the squared modulus of each element.
After optical projection, a photoresist model transfers the aerial image I to the printed image Z, which is also called resist image. To enable gradient descent in ILT algorithms, researchers commonly design the photoresist model as:
Z(z, v) 2 (I (I(z v)) 1 (T-
where Lu is the intensity threshold, a is constant number that controls the steepness of the function, and (x, 3) represents a coordinate on the acrial or resist image. Lithography simulation transforms the mask M to the resist image Z with the optical projection and photoresist models.
2.2 Mask Optimization via ILT
The application of ILT (25 32 in industrial productions began in 2005 33 38
It tries to solve the
mask pattern such that after the lithography process, the remaining pattern on the silicon wafer is as close as the original design. Thus, ILT can be viewed the inverse process of lithography simulation. In recent years, the ICCAD-13 benchmark (39 has facilitated extensive research on ILT in academia, such MOSAIC 7 MultiLevel (40). GPU-LevelSet
[8] 19 etc.
An ILT algorithm usually optimizes a parameter matrix P that can be transformed to the mask image M with the following function:
M v) = o (P(x,))))) 1 (PP(-)(((.)))-
where 3 is the constant steepness factor and y is a constant offset. With this function, the values in M can be limited in [0, 1), while the values in P have limitation. Finally, the transformation from the parameter matrix P to the resist image Z can be formulated as:
Z oz (H ( (P))).
(4)
3

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In mask manufacturing, the printed patterns on the wafer may differ drastically under varying process conditions (e.g. depth of focus, intensity of incident light), ILT algorithms typically consider three process corners, maximum, nominal, and minimum. Specifically, three series of optical kernels are employed to form the optical projection models H maz. H nom, and H min. The corresponding resist images can be denoted by Z mans Z noms and Z mine
L2 loss measures the difference between the nominal resist image and the target image, defined as: T
1.2 Z nom; T) nom
(5)
To enhance the robustness against varying process conditions, ILT algorithms are commonly required to reduce the process variation band (PVB) defined as:
PVB(2 ( maz: minn) 2 7 Z m
(6)
ILT loss functions are usually based on (2 nom T), PVB( maz: min). ). and additional compo- nents like complexity losses. Given the loss function, the parameter matrix P can be optimized by gradient descent. The final parameter matrix P can be binarized to obtain the optimized mask M by checking whether each element satisfies ass [P* (x. 0.5.
2.3 DNN-based Methods
For lithography simulation, conditional generative adversarial network (CGAN) [1 42 is utilized
in LithoGAN [22]. DAMO [12]. and TEMPO [43]. Fourier Neural Operator (FNO) [44] inspires
DOINN [23]. These works suggest that lithography simulation via DNN models is rapidly devel-
oping field. To distinguish the lithography model based on Hopkins' diffraction theory from the
DNN-based models, we refer to the theory-based one as the reference lithography simulation model.
In mask optimization, DNN-based methods also achieve tremendous success. For instance, GAN- OPC (9) trains CGAN guided by reference optimized masks and lithography simulation for mask optimization. Its training scheme inspires subsequent research, such as Neural-ILT [I]] and
DAMO 12] CENO [16] presents a powerful model inspired by Vision Transformer
45 and FNO.
2.4 Lithography Datasets
ICCAD-13 39 is famous benchmark for mask optimization consisting of 2pm 2pm metal- layer clips. However, it is targeting numerical optimization solutions only and the 10 instances are too small fit Al solutions. GAN-OPC (9) releases around 4k synthetic tiles for metal-layer mask optimization. However, its size is small for thorough training and the quality of the optimized masks falls behind SOTA results. Furthermore, it does not provide real-world designs and via-layer tiles, which limits its applications. Another limitation of existing datasets is that they do not support DNN- based lithography simulation, which is also a critical step in computational lithography. To overcome these weaknesses, we propose LithoBench, the first comprehensive dataset that simultaneously supports lithography simulation and mask optimization. Unlike previous datasets, LithoBench includes abundant and diverse data that covers synthetic and real-world layout tiles, well as metal and via layers. The ground truths are generated by SOTA method, providing the high-quality data.
ICCAD-12 [46] is a dataset for lithography hotspot detection |4 (HSD), which aims to find the locations on the mask that may lead to defects on the printed patterns. HSD only indicates the presence of defects in certain regions, but provides little information for mask optimization. LithoBench focuses on lithography simulation, which is more important than HSD, providing detailed information about the printed patterns. Besides, AI approaches for HSD have been deeply studied in literature and are mature in production flows. Therefore, HSD-related benchmarks are not the scope of this paper.
3 Dataset
LithoBench consists of 133,496 tiles that forms four subsets: MetalSet, ViaSet, StdMetal, and StdContact. MetalSet and ViaSet are large subsets primarily used for training, compatible with existing research. StdMetal and StdContact are small subsets for evaluating the generalization ability of the models. In each subset, we prepare the target images, optimized masks, aerial images, and printed images. In lithography simulation tasks, the input of the DNN model is an optimized mask, and the outputs include an aerial image and a printed image. mask optimization tasks, the input and output are target image and the optimized mask, respectively.

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Table I: Summary of LithoBench
Task
Lithography Simulation
Mask Optimization
Subsets
MetalSet
ViaSet
StdMetal
StdContact
MetalSet
ViaSet
SidMetal
StdContact
Training Tiles
14,824
104,733
0
163
14,824
104,733
0
163
Testing Tiles
1,648
11,642
271
165
10
10
271
165
(b)
(c)
(d)
(c)
Figure 2: Samples from (a) ICCAD-13
39
(b) MetalSet, (c) ViaSet, (d) StdMetal, (e) StdContact.
3.1
Data Collection
3.1.1 MetalSet
ICCAD-13 benchmark 39 is a famous benchmark for metal-layer mask optimization, used in various SOTA ILT methods 9 13 15 19). It contains 10 tiles in GLP format (39) that come from 32nm industrial layouts. We design MetalSet to enable the training of DNN-based model that can achieve ICCAD-13 13 benchmark. We synthesize 16,472 tiles using the layout generation method in [88] Each tile is randomly generated following the design rules of ICCAD-13 benchmark. The rules refer to the limitations shape widths, distances, and areas, determined by the technology node. The original ICCAD-13 benchmark is used to evaluate DNN-based mask optimization models that are trained on MetalSet. This setting is compatible with existing methods (9 and Fig. 2b show examples of ICCAD-13 benchmark and MetalSet.
high performance
Fig. 2a
3.1.2 ViaSet
For via-layer ILT, generate the layouts the 45mm technology node with the IC design tool, OpenROAD (49|50) 50). We select the ged and aes circuits from the OpenROAD project and get their layouts in GDSII format, the de facto industry standard for electronic design automation. The Python package python-oi trthonndssii (51) is used to extract the shapes on the first via layers of the circuits and save them in the GLP format. We crop the layouts into 2048 x 2048nm² tiles with stride of 512mm. Following existing ILT methods, we only include the shapes within the central region, which has a size of 1280 1280rm². Finally, get 11,415 clips of the layout. Following the MetalSet, select 10 tiles with different complexity for testing.
3.1.3 StdMetal and StdContact
StdMetal and StdContact subsets include the layout tiles of the Nangate 45mm standard cells [52] Nangate 45mm is an open IC library that widely used in academia. standard cell is group of transistors and interconnect structures that provide boolean logic function (e.g., AND, OR, XOR, XNOR, inverters) or a storage function (flip-flop or latch). Since standard cells are typically the basic building blocks of digital IC, the ILT of standard cells is important for manufacturing. We crop the layouts of the standard cells the same way as ViaSet.
The StdMetal subset consists of the tiles on the first metal layer. Since the standard cells do not use via layers, we use the contact layer build the StdContact subset, which also contains square shapes like the via layer. The 271 tiles in StdMetal are used to evaluate the generalization ability of models trained on MetalSet. Fig. shows an example from StdMetal. StaContact, we test the models trained on ViaSet with 165 tiles. We allow the finetuning shapes StdContact is obviously higher than the density in ViaSet. Fig. 2c and Fig. 2e the examples from ViaSet and StdContact, which can illustrate the difference in density.
another 163 tiles because the density of

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3.2 Data Preparation
Target Images We parse the data in the GLP format and put the shapes in the central region of 2048 x 2048 image. Each pixel in the image corresponds to a x Inm² area of the circuit layout.
Optimized Masks We employ an ILT method inspired by [14 to get the ground truths. The lithography simulation model is given by the ICCAD-13 benchmark, which is for the 32mm technol- ogy node. Since the resolution required by 45mm is lower than 32nm, is also applicable for 45mm designs. In the ILT forward pass, we apply average pooling, (3), ① and to the parameters P:
Z = =z (H (a (AugPool (P)))).
(7)
Considering three process corners H maz. H nom: and H min. we can obtain three resist images Z max: Zoom and Z min- The loss function is defined as:
b (Z Z man, Z Zaazy T) Maza T + 1 Z min 12 + Leurro (Z nom) >
(8)
where 1maaz 2 and 1 Z min 11 are for the minimization of L2 and PVB, respectively. Leare Z nom) is the curvature loss that can improve the smoothness of the mask (14). In the backpropagation, we update the parameters P via gradient descent. Inspired by multi-level ILT (40). we optimize the mask resolutions 256 x 256, 512 512, and 1024 1024 for 200, 100, and T00 iterations, respectively. Finally, we get 2048 2048 mask by interpolating the result.
Aerial and Printed Images
An aerial image I is generated by applying (1) the optimized mask M with the nominal kernel. A printed image Z is obtained by binarizing I with Lea.
3.3 Tasks
3.3.1
Lithography Simulation
Given optimized mask, the lithography simulation model outputs the corresponding aerial and printed image. For MetalSet and ViaSet, we use 90% of the data as the training set and the rest as the test set. The models trained on MetalSet can be tested on StdMetal without finetuning. The models trained on ViaSet are tested on StdContact after the finetuning on a few data.
Mean squared error (MSE) is adopted to measure the performance of lithography simulation. Further- more, intersection over union (IOU) and pixel accuracy (PA) [23] are utilized to evaluate the quality of the predicted printed image. The IOU metric can be defined as:
Z1 n TT
IOU T)
Zi UUT
where Zi and Ti are the regions in printed patterns and target shapes, respectively. PA is defined as:
Z, nTi
PA Z, T)
(10)
Note that we interpolate the output images to 2048 x 2048 before computing any metric.
3.3.2 Mask Optimization
For mask optimization, the model predicts a well-optimized mask according to the target image. The training splits used for mask optimization are the same for the lithography simulation task. However, the test data of MetalSet and ViaSet are different. We use the 10 testcases in the ICCAD-13 benchmark test the model on MetalSet. For ViaSet, we select 10 representative tiles as the testcases. StdMetal and StdContact provide hundreds of challenging samples for testing.
Mask optimization models aim to produce high-quality II.T results, not just mimic the reference optimized masks. We evaluate these metrics
after binarizing the masks and printed images:
1. 1.2 loss, as defined in (5). is metric that measures the difference between the nominal resist image and the target image. Fig. Bal visualizes the 1.2 loss.
2. PVB, as defined ( evaluates the robustness of the mask against varying process condi- tions. Fig. 3b) visualizes the PVB between the maximum and minimum process corners.

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(a)
Torget Shope
Resie Irage (Maximam)
1.2 Loss
EPR Vielsrion (Inner)
Shape on the Mask
Image (Neminal)
Rosid Irage (Miniuum)
Vielsrion (Uuter)
Figure 3: Illustration of the metries. (a) L2 measures the difference between the printed and target images. (b) PVB quantifies the maximum discrepancy between process corners. (c) EPE estimates the distortion of the printed image. (d) #Shots counts the rectangles needed to construct the mask.
Table 2: Comparison on Lithography Simulation
LihoGAN
DAMO
DONNN
[23
CFNO [To]
Subtask
M
MSEp
TOU
PA
MSEA
MSEp
10U
MSEA
MSEp
1OU
MSEA
MSEp
YOU
PA
1.7x0-
0.38
0.43
8.4
7.5
0.97
8.5
6.610
0.97
0.98
19
1.5.00-
0.97
2
2.6.u
1.40
0.47
0.53
3.0
1.5
0.94
0.96
1.9
1.0
0.96
0.98
3.
2.1.u
0.92
0.96
1.4-10-a
2.
0.30
0.34
-5
1.5
0.95
0.97
1.8 10 1.2
0.96
0.98
2.6 ie-
2.3-10-
0.96
2.7
1.2
0.01
0.01
4.6
1.6
0.87
0.93
24
1.3
0.90
0.94
2.1 10
2.2
0.83
0.90
Average
13..0
1.400
0.29
0.33
2.1.u
1.0
0.93
0.96
1.3 10
8.2
0.95
0.97
1.
1.6.0
0.91
0.95
Runtime
0.013 s/ image
0.030 s/ image
0.017 5/ image
0,035 s/ image
(b)
Figure 4: Lithography simulation. (a)Ground wwt.bb/hhhhAAa..DDADDDDOOOO....
3. As shown in Fig. 3c edge placement error (EPE) estimates the distortion of the resist image. We sample probe points equidistantly on horizontal and vertical edges of the target patterns. If the distance from the target pattern to the printed pattern is larger than the EPE constraint, it produces an EPE violation. The number of EPE violations is the EPE score of the mask.
4. Shot count (#Shots) is the number of rectangular shots for replicating the shapes on the mask. It evaluate the complexity of optimized mask. Fig. 3d shows example, where shape is fitted by rectangular shots. In LithoBench, we compute the shot count using adaptive rectangular decomposition [53] with adaptive-boxes [54) (MIT license).
Table 1 summarizes the statistics of LithoBench.
4 Experiments
4.1 Benchmarked Models
4.1.1 Lithography Simulation Models
Multiple SOTA models are implemented using PyTorch [53 and OpenILT [66] on RTX3090 GPU, For
lithography simulation, we implement LithoGAN 22 DAMO [12]. DOINN 23 and CFNO [T6] The last layer each model outputs two channels as the aerial and printed images. These models minimize the MSE between their outputs and the ground truths.
LithoGAN A CGAN is employed to the reference lithography simulation model. The generator of the CGAN is fully convolutional network (FCN) [57] and the discriminator is convolutional neural network (CNN). Images are downsampled 256 256 and input to the model. Note that different models may vary in image resolution to make trade-off's between accuracy and runtime.

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Table 3: Comparison on Mask Optimization
GAN-OPC
Neural-ILT
DAMO
[12
CFSO
Subtask
Fig
PVB
EPF.
Shots
PVB
EPE.
Shots
PVB
FPE
Shots
PVB
FPF.
Shoes
43414
41290
8.7
36670
42666
7.3
476
32579
41173
54
323
47814
46131
302
2
14767
6686
8.3
166
12723
8537
6.2
263
5081
9962
0.0
176
8949
9890
0.1
184
25929
23715
4.6
23796
81378
4931
73.2
276
25422
41537
3,2
265
50445
35673
26.7
458
70740
17950
55.1
396
Average
41372
19156
23.7
368
23715
29072
4.8
344
26056
27651
8.0
394
38578
25196
18.0
279
Runtime
0.010
Image
0.025
image
0.028 s/ image
0.0
image
S
(b)
(c)
(d)
(c)
Figure 5: Mask optimization. (a)Ground htt.://JAN..o......n..m.........
DAMO It improves the CGAN for lithography simulation with the backbone based on UNet++ 58 and the multiscale discriminator inspired pix2pixHD (59). The resolution of DAMO is 1024 1024, which is significantly higher than LithoGAN.
DOINN Inspired by Fourier Neural Operator (FNO) 60 DOINN utilizes novel reduced FNO architecture to fit the lithography simulation model. Its resolution 1024 x 1024.
CFNO Combining the principles of Vision Transformer (ViT) 45 and FNO, the CFNO module is designed for efficient global layout embedding and resolving stitching issues caused by long-range dependency. The resolution for CFNO is also 1024 x 1024.
4.1.2 Mask Optimization Models
For mask optimization, we implement GAN-OPC 99. Neural-ILT (1], DAMO 12 and CENO 16].
GAN-OPC CGAN also inspires the design of GAN-OPC. The training of GAN-OPC consists of two stages. In the first stage called ILT-guided pretraining, we train the generator to minimize the MSE between its outputs and the optimized masks. The second stage is based on the training process
of GAN. During the training of the generator, we use the L2 loss formulated by (5) as an additional objective, where the printed image Z nom is obtained by the reference lithography simulation model. GAN-OPC uses resolution of 256 x 256.
Neural-ILT A UNet (61] is utilized in Neural-ILT predict the optimized mask. Neural-ILT also has a pretraining stage like GAN-OPC. In the second stage, it uses L.2 (2 nom: T) PVB Z maz; Z min) the objective function. The resolution of Neural-II.T is 512 512.
DAMO and CFNO use the same architectures in lithography simulation.
4.1.3 Subtasks
For lithography simulation and mask optimization, we benchmark the models with the following subtask: (1) training on MetalSet, testing MetalSet; (2) training ViaSet, testing on ViaSet; (3) training on MetalSet, testing on StdMetal; (4) training on ViaSet, testing on StdContact. The last two more challenging since high generalization ability is required in these subtasks.
4.2 Results on Lithograph Simulation
Table presents the performance of the tested models on all subtasks. MSEA and MSEp are the MSE losses the aerial and printed images. Fig. shows the outputs images the models. DOINN achieves the best performance with a competitive runtime. DAMO and CFNO have comparable per- formance, which beyond the reach of LithoGAN. shown in Fig. 4b even a coarse generation of the target shapes is too difficult for LithoGAN. This can be explained by two factors. First, LithoGAN

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uses lower resolution than other methods, which makes it harder for LithoGAN to approximate the shapes in a higher resolution. Second, the convolution layers LithoGAN progressively shrink the feature maps until they reach size of 512 x 1 x at the intermediate layer. Since the printed image resembles the input mask, is difficult to decode the complex shapes from such low-resolution feature maps. Thus, high-resolution features and outputs are essential for accurate lithography simulation.
4.3 Results on Mask Optimization
Table 3 compares the mask optimization models on all subtasks. Fig. 5 shows the output masks of the models. While GAN-OPC has the best PVB among these methods, sacrifices 1.2 and EPE. It fails to learn the complicated curves that improve the L2 loss due to its low resolution. With a moderate resolution, Neural-ILT achieves moderate performance on the first three tasks. But it generalizes well to StdContact, enabling it to achieve the best average L2 and EPE. DAMO has the best performance on the first three tasks, while CFNO achieves lower mask complexity due to the small shot counts. In mask optimization, the model designer may consider the trade-off between resolution, generalization, and complexity. It is challenging design a model that is optimal across all metries.
5 Conclusion
In this paper, we present LithoBench, a dataset for DNN-based lithography simulation and mask optimization with an evaluation platform. LithoBench includes 133,496 layout tiles that involve the metal and via layers of circuit layouts. can not only support the typical setup where a model is trained and evaluated unseen data. Given the data, state-of-the-art DNN models for lithography simulation and mask optimization trained and evaluated on LithoBench to show their advantages and weaknesses. We hope LithoBench can contribute to the further development of computational lithography.
similar tiles, but also evaluate the model's generalization ability to
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12


Reviews:
[{"review_id": "GFKE2s48du", "reviewer": "Reviewer_URA3", "summary": "", "questions": "", "limitations": "The effectiveness of the proposed deep learning models for lithography simulation and mask optimization is heavily dependent on the quality and diversity of the LithoBench dataset. If the dataset lacks diversity or does not adequately cover all possible circuit design scenarios, the developed models may not be well-suited for real-world applications.", "rating": 7, "confidence": 3, "soundness": null, "presentation": null, "contribution": null, "strengths": "- The research is closely tied to real-world applications in the semiconductor industry, addressing a significant challenge in this field - the computational burden of ILT.\n- The LithoBench dataset represents a comprehensive collection of real and synthetic circuit design tiles, which fills a significant gap in the field by providing a large-scale, diverse, and practical dataset for training and evaluating deep learning models for ILT.\n- The LithoBench dataset is openly available, which can stimulate further research and model development in the community.", "weaknesses": "", "quality": null, "clarity": null, "significance": null, "originality": null, "strengths_and_weaknesses": "", "was_revised": false, "final_justification": "", "rebuttal": ""}, {"review_id": "2b8tBhXLID", "reviewer": "Reviewer_hRPs", "summary": "", "questions": "", "limitations": "I would suggest the author to also discuss the limitation of the dataset.", "rating": 7, "confidence": 2, "soundness": null, "presentation": null, "contribution": null, "strengths": "1. The paper is well-written, the section 2 does a good job providing reader the background about lithography simulation and ILT, making the paper much friendly to people who are not familiar with semiconductor manufacturing process.\n2. The observations drawn from benchmarking the recent methods can be useful for the community.", "weaknesses": "", "quality": null, "clarity": null, "significance": null, "originality": null, "strengths_and_weaknesses": "", "was_revised": false, "final_justification": "", "rebuttal": ""}, {"review_id": "wncm19Ka3H", "reviewer": "Reviewer_EsWu", "summary": "", "questions": "", "limitations": "Yes. There are no negative implications of this work.", "rating": 8, "confidence": 4, "soundness": null, "presentation": null, "contribution": null, "strengths": "This appears to be the first large-scale lithography dataset for mask optimization and simulation using real world designs/layouts.", "weaknesses": "", "quality": null, "clarity": null, "significance": null, "originality": null, "strengths_and_weaknesses": "", "was_revised": false, "final_justification": "", "rebuttal": ""}, {"review_id": "YWgLkXMyG2", "reviewer": "Reviewer_uJf3", "summary": "", "questions": "", "limitations": "The writing can be improved to be more clear. Many concepts/terms may be obvious to the authors, but lithography is a complex task for readers without a rich background. Detailed suggestions are given in the 'Clarity' part.", "rating": 6, "confidence": 3, "soundness": null, "presentation": null, "contribution": null, "strengths": "The data about lithography can be very sensitive due to its importance in the semiconductor manufacturing industry, making it hardly available to many users. Releasing this will be helpful to AI research in this direction.", "weaknesses": "", "quality": null, "clarity": null, "significance": null, "originality": null, "strengths_and_weaknesses": "", "was_revised": false, "final_justification": "", "rebuttal": ""}, {"review_id": "QdAKnHH95V", "reviewer": "Reviewer_zijQ", "summary": "", "questions": "", "limitations": "I appreciate the authors for acknowledging the limitation of lacking full-chip scale data in the limitation section in supplementary material and mentioning it could be considered in future work. But to be honest, this is my biggest concern after reading the paper. The authors mentioned that the main limitation of traditional ILT methods is the computational overhead, making it challenging to implement ILT at full-chip scale, hence DNN-based ILT methods are proposed to overcome this limitation. Hence, at least one of the target use cases for DNN-based ILT methods is full-chip ILT, but this is not provided in the current dataset, even very simple full-chip patterns. \n\nI'm not an expert in lithography optimization and hence not tracking the recent works in this field, but for me, the value of this dataset is questionable/limited for future DNN-based lithography simulation or mask optimization works given the lack of full-chip data, which is probably the ultimate goal of DNN-based methods. ", "rating": 6, "confidence": 3, "soundness": null, "presentation": null, "contribution": null, "strengths": "- Addresses the need for rigorous benchmarks for deep learning based lithography methods with diverse, realistic data\n- Includes both lithography simulation and mask optimization tasks \n- Tests several recent works on the benchmark and provides analysis and insights\n- Might be the first dataset/benchmark on DNN-based lithography simulation and mask optimization, but I'm not sure, the authors should clarify this.", "weaknesses": "", "quality": null, "clarity": null, "significance": null, "originality": null, "strengths_and_weaknesses": "", "was_revised": false, "final_justification": "", "rebuttal": ""}]

Author rebuttal:

Meta-review: This paper the needs of dataset for using machine learning techniques for for inverse lithography technology (ILT), which is a critical step in semiconductor manufacturing. Given the high computational complexity, ML based solutions can be attractive.  The authors introduce LithoBench, a large-scale dataset (consisting of more than 120,000 tiles for different layers, including metal set, via set, standard cell metal set, and standard cell contact set). It is a good contribution to the community.  There is sufficient discussions between the reviewers and the authors, which help to improve the quality of the manuscript.
Decision: Accept (Poster)