Circuit as Set of Points
Authors: Jialv Zou
Xinggang Wang
JiaHao Guo
Wenyu Liu
Qian Zhang
Chang Huang
Venue: NeurIPS 2023 poster (2023)
Keywords: EDA
Circuit Design
Congestion prediction
DRC violation prediction

Abstract: As the size of circuit designs continues to grow rapidly, artificial intelligence technologies are being extensively used in Electronic Design Automation (EDA) to assist with circuit design.
Placement and routing are the most time-consuming parts of the physical design process, and how to quickly evaluate the placement has become a hot research topic. 
Prior works either transformed circuit designs into images using hand-crafted methods and then used Convolutional Neural Networks (CNN) to extract features, which are limited by the quality of the hand-crafted methods and could not achieve end-to-end training, or treated the circuit design as a graph structure and used Graph Neural Networks (GNN) to extract features, which require time-consuming preprocessing.
In our work, we propose a novel perspective for circuit design by treating circuit components as point clouds and using Transformer-based point cloud perception methods to extract features from the circuit. This approach enables direct feature extraction from raw data without any preprocessing, allows for end-to-end training, and results in high performance.
Experimental results show that our method achieves state-of-the-art performance in congestion prediction tasks on both the CircuitNet and ISPD2015 datasets, as well as in design rule check (DRC) violation prediction tasks on the CircuitNet dataset.
Our method establishes a bridge between the relatively mature point cloud perception methods and the fast-developing EDA algorithms, enabling us to leverage more collective intelligence to solve this task. To facilitate the research of open EDA design, source codes and pre-trained models are released at https://github.com/hustvl/circuitformer.

Circuit as Set of Points
Jialv Zou Xinggang Wang!l,
Jiahao Guo', Wenyu Liu', Qian Zhang? Chang Huang
School of EIC, Huazhong University of Science and Technology "Horizon Robotics
Abstract
As the size of circuit designs continues to grow rapidly, artificial intelligence technologies being extensively used in Electronic Design Automation (EDA) to assist with circuit design. Placement and routing are the most time-consuming parts of the physical design process, and how to quickly evaluate the placement has become a hot research topic. Prior works either transformed circuit designs into images using hand-crafted methods and then used Convolutional Neural Networks (CNN) to extract features, which are liritedd by the quality of the hand- crafted methods and could not achieve end-to-end training, treated the circuit design as a graph structure and used Graph Neural Networks (GNN) to extract features, which require cone-consuming preprocessing. our work, we propose a novel perspective for circuit design by treating circuit components as point clouds and using Transformer- based point cloud perception methods extract features from the circuit. This approach enables direct feature extraction from raw data without any preprocessing, allows for end-to-end training, and results high performance. Experimental results show that our method achieves state-of-the-ard performance in congestion prediction tasks on both the CircuitNet and ISPD2015 datasets, well in design rule check (DRC) violation prediction tasks the CircuitNet dataset. Our method establishes bridge between the relatively mature point cloud perception methods and the fast-deve EDA algorithms, enabling us to leverage more collective intelligence to solve this task. To facilitate the research of open EDA design, source codes and pre-trained models released at hattps://gtthin http://////oo/tt//ooooooooooooo
Introduction
In recent years, the demand for semiconductor chips for various applications has been increasing, and the need to accelerate the chip design and manufacturing process has become increasingly urgent. And with the development of semiconductor technology, the scale of very-large-sete scale integrated (VLSI) circuits is growing exponentially, challenging the scalability and reliability of the IC design process. As result, the industry urgently needs more efficient Electronic Design Automation (EDA) algorithms and tools to enable the processing of huge exploration spaces in a shorter period of time. The layout and routing phase are particularly important in the overall EDA flow. As feature size shrinks, routability becomes more important constraint on the manufacturability of VLSI designs. Routing congestion can significantly affect PPA (Performance, Power, Area metrics, and design rule violations can directly lead to unmanufactured designs, but there is no way to obtain an accurate congestion and design rule violations map without conducting placement and routing attempts, which can lead to longer design cycles and possibly some unpleasant surprises. Therefore, accurate and rapid evaluation of placement advance of routing will be very important, and the exploration of routability becomes one of the key issues in modern placement for VLSI circuits (7)
This work was done when Jialy Zou was interning at Horizon Robotics. Xinggang Wang (xgwange
hust. edu. en) is the corresponding author.
37th Conference on Neural Information Processing Systems (NcurIPS 2023).

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Before global placement, the circuit design is represented as a netlist consisting of nodes and nets, where nodes represent specific components and nets represent link relationships between nodes, containing topological information about the design. After the global placement, we will get information about the specific location of each node, containing the geometric information. How to use this information to make fast and accurate evaluation of the placement is currently divided into roughly two approaches: (I) using hand-crafted features to rasterize the circuit and thus convert them into images. Then, using CNN [24] 38 Generative Adversarial Nets (GAN) [42] I 45 to perform feature extraction on the circuit. (2) converting the circuit design into a graph structure and using
Graph Neural Networks (GNN) 20 35 15 to perform feature extraction the circuit design.
However, both methods have their advantages and disadvantages. The CNN-based methods use some hand-crafted features (e.g.. RUDY [33], node density, pin density) to rasterize the circuit and perform feature extraction on it, where the grids are treated as pixels. Then, use classical image segmentation networks in computer vision (e.g., UNet [32 and FCN (25)) to do the pixel-wise prediction of labels (e.g., congestion and DRC violation). This method is simple and efficient, however, the effectiveness of the hand-crafted features limits the network's 's performance, and it can not achieve end-to-end training. The GNN- -bsed methods involves converting the circuit design into a graph with vertices and edges, where nodes in the circuit are represented as vertices and nets are represented as edges. GNN networks are then used to extract features from the graph, making it suitable for downstream tasks. Although they have small parameters and fast inference speeds, it is worth noting that even though the time consumption of constructing the graph structure has been proven to be linearly related to the design scale, the design scale of chips is very large. The number of nodes is typically in the hundreds of thousands, while the number of edges can be in the millions, so the process of constructing the graph structure often be very time-consuming. In addition, these methods also use hand-crafted features when processing geometric information, which also suffers from the aforementioned problems.
To address the above issues, in this paper, we approach the task of feature extraction in circuit design from novel perspective by treating circuit components point clouds and using Transformer to solve the task, i.e., CircuitFormer. CircuitFormer avoids the two core pain points of the above two methods: (1) there is need to use hand-crafted features, and end-to-end training can be achieved; (2) there is no need for any preprocessing, which greatly reduces the time of the entire process.
As shown in Fig. 1 our model is divided into two parts: an encoder and decoder. The encoder extracts features from the placement information of the circuit design, while the decoder adapts to downstream tasks using conventional backbone and segmentation head, similar to the CNN-based methods
ioou
CA
CA
CA
CA
CA
CA
The architecture of CircuitFormer: The left half of the model is the encoder, which is composed of four grid-based attention (GA) modules with different grid scales, Each GA module extracts circuit features by performing cross-attention (CA) twice with the latent codes, using ConvFFN for information exchange across grids in the middle. For more details on the GA module, please refer to Fig. 2 prediction.
Figure 1:
The right half of the model is the decoder, which is used for pixel-wise
In encoder, in order to model the relationship between nodes, to compensate to some extent the disadvantage that geometric methods cannot use topological information, and to enable the exchange of information across the grids, we introduce the attention mechanism. Considering that most perception tasks for point clouds are focused on 3D point clouds, but circuits can be abstracted as 2D point clouds without a Z-axis, propose an improvement to the voxel-based set attention (VSA)

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module [16], adapting it for use in 2D scenarios to extract 2D node features. In Sec. 3.1 we will provide a detailed introduction.
The decoder consists of a backbone and a segmentation head. We use ResNet-18 17 as the backbone to further refine the rasterized features extracted by the encoder. Finally, we attach UNet++ 46 as the segmentation head to make pixel-wise predictions.
Our experiments were based the publicly available CircuitNet [5] dataset and ISPD2015 4 dataset. Whether is the congestion prediction task or the DRC violation prediction task, the pixel values of their labels continuous values between 0 and 1. The label distribution is highly imbalanced, exhibiting a skewed distribution with a long tail. The imbalance label distribution can make difficult for model to handle corner cases, leading to overfitting and reducing the accuracy and robustness of the model. For the regression on imbalanced datasets, we adopted label distribution smoothing (LDS) 33 to re-weight the loss function and improve the model's performance.
In summary, our contributions are:
Our work takes a novel perspective on circuit design by treating circuit components as point clouds and using a point cloud perception network to extract features for circuit design. To the best of our knowledge, our work is the first to abstract the task of circuit design feature extraction as a point cloud perception task. This bridges the gap between the two fields, allowing to transfer certain structures and conclusions from mature point cloud perception methods to the developing EDA domain.
Our method surpasses hand-crafted features in terms of feature extraction and enables end-to-end training, making superior to CNN-based methods. Additionally, unlike GNN- based methods, our approach eliminates the need for preprocessing, significantly reducing processing time.
Experiments validated the superior performance of our method on the CircuitNet and ISPD2015 datasets. In the congestion prediction task, our method surpassed the baseline [24] by an average of 3.8% and 1.5% on the CircuitNet dataset and ISPD2015 dataset respectively, based on the average of Pearson, Spearman, and Kendall correlation coefficients, achieving a new SOTA. For the DRC violation prediction task, we also achieved the best performance in most of the metrics. Our work has the potential serve as a universal feature extractor for chip design, which can adapt to wider range of downstream tasks by changing the decoder.
2
Related Work
2.1 CNN-based Methods
The core idea of CNN- methods to partition the circuit design into grids and extract features of the components in each grid using some hand-crafted methods. These methods treat the circuit as an image and the grids as pixels. Then, 24
use features as the input to the segmentation network transform the task into generating congestion map from features and uses a Conditional Generative Adversarial Network (CGAN) (28) to solve
38
and performs pixel-wise prediction.
42
45
2.2 GNN-based Methods
The GNN- methods primarily focus on the topology of circuit design, which involves recon- structing the circuit design as a graph with vertices and edges. In [21]. nodes serve as vertices, while nets serve edges, then GAT [35] is used extract features. [ uses GraphSAGE [T5] extract features from a graph with G-cells as nodes. These methods can only utilize the topological informa- tion of the circuit design and are unable to handle geometric information. Recent advancements in graph networks have expanded their capabilities to incorporate geometric information in addition to topological information. LHNN (36) considers the grid as internal nodes and the net as external nodes, constructing homogeneous graph. CircuitGNNN 40) generates heterogeneous graph, treating both nodes and nets as vertices, with information being propagated along both topological and geometric edges.
3

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2.3 Point Cloud Perception
Point cloud perception methods can be classified into two categories: point-based and Point-based methods [30] B1] follow the paradigm of sample, group, and fusion. They perform farthest point sampling in the point cloud, then group points within a certain range of each sampled point, and finally perform the fusion. These methods can preserve the structure of the point cloud without losing information. However, due to the irregularity of point clouds, such methods are often difficult train in parallel and require large amount of memory consumption. Voxel-basee methods 44 assign each point to a specific voxel and extract local features from groups of points within each voxel. This significantly improves computational efficiency but can result in information loss. Transformers can model the relationships between points and have vast potential in point cloud perception tasks. However, due the quadratic computational complexity of transformers, vanilla transformers cannot be directly applied to point clouds. Based on this, [3] performs local attention on a of points after sampling to extract local point cloud relationships. [16] applies cross attention twice between the latent code and point cloud to compress the features into the latent space, reducing computational complexity.
3 Method
We focus on the congestion prediction task and design rule check (DRC) violation prediction task. Congestion defined as the overflow of routing demand over available routing resources in the routing stage of the back-end design, and DRC violation, as the name suggests, refers to the location where design rules are violated. Both tasks can abstracted as making grid-level predictions of the circuit based on the point-wise information (geometric and topological) of the circuit design. Specifically, we consider circuit components such as buffers, inverters, registers, and intellectual property (IP) cores point clouds. Here, we do not differentiate between component categories but only focus on their fundamental geometric features, i.e., the center coordinates, width, and height of each circuit component.
3.1 Encoder
latent codes
Input
Output
Cross Attention
Cross Attention
Scatter-Surn
CurVAFN
Broadcast
ConwTereor
n
nx
nxkxd n
Figure 2: The architecture grid-based attention (GA) module
Multi-scale Grid-based Attention. Due the complexity of eircuit designs, nodes connected by a topological structure may be far apart in geometric positions. The hand-crafted method that only considers the geometric features of each node within grid cannot handle the relationships between different grids. Therefore, we hope to introduce the attention mechanism to expand the receptive field, model long-range dependencies, and enable interaction between different grids. However, vanilla self- attention computation is quadratic, with a computational complexity of Onzdd) where represents the number of nodes, which usually the hundreds of thousands, Such high computational complexity is unacceptable. Inspired by I9 18 23 16]. we use fixed-length. learnable latent code to perform two cross-attentions with the input features instead of one self-attention. This compresses the node information into a more compact latent space and significantly reduces the computational complexity. The validity of this method comes from the observation that the attention matrix is usually low-rank ||] 2)

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The grid-based attention (GA) module is an improvement over the voxel-based set attention (VSA) module [T)], adapted for use with the circuit, which is referred as pseudo-2D point clouds in our work. The structure is shown in Fig. Given an input set P E RTx1 where represents the number of nodes. The features of each node can be represented as {P, = (aig, ys, ws, w;,h;) = 1,...), 3y and yi represent the original coordinates, while wy and h; represent the width and height of the component, respectively, And we also have information on the position of corresponding points Ce R==22, C IC,- = (T 35) i I.).,),, where Vi and y/, represent the normalized coordinates of the nodes. We encode the node features as keys K E Ruxd and values V E Rn*d through linear projection, same as vanilla Transformer. Randomly initialized learnable latent codes serve as queries (k < n) and are fused with linearly projected node features to encode them into the latent
Q E R d space using cross-attention. After that, we obtain the point-wise feature E Raxkxd
Then, we convert the point-wise features to grid-wisc features, the grid coordinates corresponding to each point can be represented as G = { G. = (l., 12, : = 1.....i) ). where d2, dyis the grid size of two dimensions, and |:] is the floor function. By changing d2, dy, we can obtain raster features of different scales, so that we can perform multi-scale grid information exchange. To be more precise, we established four distinct grid scales, for d= dg = [1, 2, 4. 8]. Next, we use the scatter-sum function to add point-wise features belonging to the same grid and obtain the grid-wise feature A E Rxxxxd where m represents the number of non-empty grids. The seatter function is a CUDA kernel library that performs symmetric reduction on various matrix segments. The entire process is highly parallelized.
To introduce local inductive bias, based on the coordinates of the grids, we construct a sparse tensor I E Rexxxx by assembling the grid-wise features into image-like structure, where w and respectively represent the number of grids in the two dimensions, and ( = k x d. To be specific, we pad the empty grids with zeros. After that, the feature / is refined using convolutional feed-forward network (ConvFFN) while enabling information exchange between grids, we use two layers of depth-wiee wise convolution (DWConv) achieve it. Datasets in circuit design are typically small in scale, and this approach of combining attention mechanisms with CNNs has been shown to be effective on small datasets 29.. This because ConvFFN can introduce inductive bias to the model, which plays an important role in improving the convergence of transformer on small datasets, which are difficult to optimize.
To maintain consistency with the input dimensions, we broadcast the sparse tensor / to generate the point-wise feature E Ruxxxd based on the grid indices. Finally, the refined point-wise feature H is used as the key-value pair, with the linear projection of the input serving as the query for cross-attention. This results in output O Rexd with the same dimensions as the input.
The encoder consists of four grid-based attention modules with different grid scales, which can aggregate multi-scale and global geometric information in highly parallelized manner. It has a computational complexity of O(nkd), where < n.. At the end of the encoder, we use the scatter-sum operator to generate grid-wise features and combine them into an image Y E [@W*HX XDD according to the position coordinates of each grid, preparing it for further pixel-wise prediction. Here, Y has the same width and height as the label.
3.2 Decoder
We did not put much emphasis on the design of the decoder. We utilized a ResNet-18 18 [7 as the backbone to further refine and downsample the features extracted by the encoder, and then employed a classic segmentation head, UNet++ [46), to achieve pixel-wise prediction.
3.3 Loss Function with Label Distribution Smoothing
Our label smoothing strategy follows the idea of re-weighting in imbalanced classification problems However, in the case where the labels are continuous values, the empirical label distribution may not reflect the true label distribution. This is because, unlike classification tasks, there no hard boundaries between adjacent label values. When presented with limited samples for certain labels, the model prefers to learn features of labels with similar values.
3.
Inspired by (39], we count the empirical density distribution of the labels in the training set, and then, convolve with it using symmetric Gaussian kernel function to obtain the smoothed effective label
5

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density distribution. The inverse of the square root of the smoothed distribution is used as the weight do the re-weight of the loss function. The label distribution smooth calculation is shown below:
ply') p(y))= = J, k(y, p(yydd
(I)
where ply) the empirical density function of the label, we discretize the labels with a precision of 0.001 and count the frequency of the value y to obtain p(y). p(y') is the effective density function of the label y', and the weight corresponding to a label with value s/ is V k(y. v') symmetric
fu- 20
We use MSE loss, so the re-weighted loss function is given by Eq. 2 where D is the predicted value of the network and y the value of the label.
Gaussian kernel function: kyy 1/) x
a
1 ply))
loss(ú. (00
(U: v12²
(2)
4 Experiments
4.1 Tasks and Datasets
We evaluate our model public CircuitNet (5] and ISPD2015 4 datasets. For the CircuitNet dataset, we focus on the two cross-stage prediction tasks, congestion prediction and design rule check (DRC) violation prediction. For the ISPD2015 5 dataset, our main focus lies in its congestion prediction task.
4.2 Baselines and Settings
We compare our work with two mainstream methods in this field: CNN-based methods and GNN- based methods. The basebased method mostly consists of hand-crafted features as input, extracting features using the backbone, and finally adding segmentation header for pixel-wise prediction. CircuitNet dataset provides Gpdl (24 and RouteNet [3 as baselines for congestion prediction and DRC violation prediction tasks, respectively. Gpdl is a typical CNN-based EIDA-customized deep learning model for congestion prediction, it combines RUDY map. pin RUDY map, and macro region as input features. Similarly, RouteNet is network customized for DRC violation prediction. In addition the three hand-crafted features mentioned above, also incorporates cell density and congestion map input. In this paper, input features of all CNN-based methods follow these settings. For the GNN-based method, we chose the most outstanding models in the field: CircuitGNN [40), heterogeneous graph method where topological and geometrical information are integrated jointly. We evaluate the results in Pearson/Spearman/KKnnn Kendall correlation as with [40 14.
The network is trained end-to-end on single NVIDIA RTX 3090 GPU, for 100 epochs with a cosine annealing decay learning rate schedule 226 and 10-epoch warmup. We use the AdamW optimizer with learning rate y = 0.001.
4.3 Result of Congestion Prediction
CircuitNet. The results are summarized in Table[]] The result shows that our method achieves the best performance, and outperforms the baseline model Gpdl provided by CircuitNet, with an average metric improvement of 3.8%. Our method beats the UNet++ (2.8% average), which means that the features extracted by our method are superior to the hand-crafted features, as our decoder is the same as UNet++. The performance of CircuitGNN on CircuitNet is not very good, possibly because CiN requires node-level labels for training, but the CircuitNet dataset only provides grid-level labels. We assigned the grid label to each node within the grid as the node label. During validation, we performed average pooling on the outputs of nodes within the same grid to obtain the grid-level output, which is consistent with the setting in CircuitGNN.
Fig. 3 visualizes the predicted congestion map generated by different methods. It can be intuitively seen that our method can provide more detailed predictions for the congestion map.
ISPD2015. The results are summarized Table indicates that our model still achieves the best performance on the ISPD2015 dataset. It is worth noting that the ISPD2015 dataset used in our study

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Table 1: Congestion prediction result of CircuitNet dataset
Method
pearson
spearman
kendall
Gpdl 24
0,5032
0.5143
0.3787
Gpdl with LinkNet 6
0.5078
0.4905
0.3623
Gpdl with MANet [2
0.4856
0.5167
0.3797
Gpdl with DeepLabv3 /
0.5091
0.5211
0.3834
Gpdl with Deeplaby3plus
0.5153
0.5160
0.3807
Gpdl with UNet 32
0.5770
0.5103
0.3780
Gpdl with UNet++
0.6085
0.5202
0.3855
CircuitGNN 40
0.3287
0.4483
0.3688
CircuitFormer (ours)
0.6374
0.5282
0.3935
is provided by the developers of the CircuitNet dataset. However, the format they provide is not easily compatible with CircuitGNN, especially when dealing with large-scale designs. Consequently, significant amount of time is required for data conversion in such cases. Therefore, when comparing with CircuitGNN, we excluded the superblue design from ISPD2015, which contains over one million nodes. The experimental results are presented in Table similarly, also showcase the performance of CNN-based models.
Table 2: Congestion prediction result of ISPD2015 dataset
Method
pearson
spearman
kendall
Gpdl 24
0.4345
0.1297
0,0978
Gpdl with UNet 32
0.4173
0.1430
0.1084
Gpdl with UNet+ [46
0.3877
0.1575
0.1189
CircuitFormer (ours)
0.4456
0.1797
0.1360
Table 3: Congestion prediction result of ISPD2015 dataset without superblue
Method
pearson
spearman
kendall
Gpdl 24
0.5202
0.1880
0.1423
Gpdl with UNet 32
0.5253
0.1481
0.1124
Gpdl with UNet+ 46
0.4593
0.1862
0.1423
CircuitGNN 40
0.3940
0.1912
0.1614
CircuitFormer (ours)
0.6534
0.2244
0.1710
4.4 Result of DRC violation prediction
Table Ishows that in the DRC violation prediction task, our work achieved the best performance in terms of Spearman and Kendall, but the Pearson correlation coefficient is relatively low. We speculate that this because hand-crafted methods use the congestion map as an input feature, which contains higher-level information than the raw data. In contrast, our method only uses the original positional information as input to maintain consistency.
4.5
Ablation study
We conducted series of ablation experiments to demonstrate the roles of different components in our model.
Comparison with other point cloud perception methods. Table 5 shows comparison between our method and other point cloud perception methods, where we replace our encoder with them. We compared point-based methods, such as Point-Transforme voxel-based (or grid-based for 2D circuit) methods, such as PointPillars [22] and DSVT (37. The results show that the voxel-basee method outperforms the point- point-based method in both tasks, which
43 and TrgnSrranfrrmrr [13]. and
7

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(a) Input
(b) UNet++
(c) CircuiFFommer (ours)
(d) Ground-truth
Figure 3: Visualization of congestion maps for CircuitNet dataset
Table 4: DRC violation prediction result of CircuitNet dataset
Method
pearson
spearman
kendall
RouteNet 38
0.4206
0.2462
0.19
RouteNet with LinkNet 66
0.4165
0.2213
0.1788
RouteNet with MANet 12
0.3420
0.2395
0.1916
RouteNet with DeepLabv3 7
0.3760
0.2480
0.1989
RouteNet with Deeplabv3plus
0,4224
0.2699
0,2185
RouteNet with UNet 132
0.4415
0.2746
0.2225
RouteNet with UNet++ 46
0.4698
0.2782
0,2261
CircuitGNN 40
0.1171
0.2366
0.2095
CircuitFormer (ours)
0.3707
0.3094
0.2471
may be due to the fact that the voxel-based method directly partitions the circuit design into grids, which is consistent with the labeling modality, whereas the point- method needs to project the point-wise information to the grid-win wise prediction, which may result in information loss. Additionally, the point-based method requires point sampling and cannot utilize information from all points. Our method also outperforms PointPillars, which groups points within the using MLP and Maxpooling like PointNet (30]. Similar to RUDY, this method can only extract local features within the grid and cannot exchange features across grids. It highlights the importance of information exchange across grids.
grid and extracts features
Table 5: Comparison with other point cloud perception methods
congestion spearman
DRC violation spearman
Method
pearson
kendall
pearson
kendall
Msg- Sogg-raanformer
0.3634
0.4033
0.2930
0.1216
0.2155
0.1686
Point- Transformer
0.4086
0.4599
0.2930
0.1307
0.2186
0.1721
PointPillar
0.6151
0.5234
0.3887
0.3617
0.3067
0.2447
DSVT
0.6035
0.5121
0.3802
0.2380
0.3213
0.2557
CireuitFormer (ours)
0.6374
0.5282
0.3935
0.3707
0.3094
0.2471
Label distribution smooth. Tableeninvettigated the improvement brought by the label distribution smooth module on imbalanced prediction tasks.
Preprocessing time. Fig. we show the relationship between the preprocessing time of various methods and the size of the circuit design. GNN-based methods, represented by CircuitGNN, require generating a computation graph based on the geometric and topological information of the circuit design during the preprocessing stage. The time of this process is proportional to the size of the circuit design. CNN-based methods require hand-crafted methods extract geometric information, which involves traversing the position of each node and pin. This process is proportional to the number of

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Table 6: Results on the influence label distribution smoothing
Method
Prediction Task
pearson
spearman
kendall
CircuitFormer (w/o. LDS)
congestion
0.6360
0.5143
0.3833
CircuitFormer
congestion
0.6374
0.5282
0.3935
CircuitFormer (w/o. LDS)
DRC violation
0.3552
0.2944
0.2354
CircuitFormer
DRC violation
0.3707
0.3094
0.2471
nodes and pins. contrast, our method requires no preprocessing and takes the raw position each node as input directly. The time tests were conducted on AMD EPYC 7502P 32-Core 2.5GHz CPU.
GrcutENN
Hand Crafted
Grouifoormrr (ours)
time (3)
40
50000
100000
150000
200000
250000
number of edges
Figure 4: The relationship between preprocessing time and edge number.
Balancing model performance and runtime memory. delve deeper into the relationship between the performance of our model and its runtime memory, and to provide more options to the community, we conducted ablation experiments on the encoder of our model. As shown in Fig. [ our encoder consists of four stages of GA modules, We tested the performance and runtime memory of models with different numbers of stages. Specifically, we test runtime memory on RISCY-FPU-a which is the largest-scale design in the CircuitNet dataset and consists of 77,707 nodes. The results are summarized in Table
Table The performance of models with different numbers of stages on the CircuitNet congestion prediction task, and their runtime memory during the processing of RISCY-FPU-a, which consists of 77,707 nodes.
Method
pearson
spearman
kendall
Runtime Memory/MB
CircuitFormer (4-stage)
0.6374
0.5282
0.3935
2475
CircuitFormer (3-stage)
0,5793
0.4977
0.3683
1519
CircuitFormer (2-stage)
0.5322
0.4972
0.3668
1047
CircuitFormer (1-stage)
0.5260
0.4853
0.3582
811
CircuitGNN 40
0.3287
0.4483
0.3688
1501
Gpdl 24
0.5032
0.5143
0.3787
1887
Gpdl with UNet++ [46
0.6085
0.5202
0.3855
2209
Decoder. We conducted ablation experiments on the decoder selection to explore its impact on the model's performance.

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Table The ablation experiments on the decoder congestion prediction task
Decoder
pearson
spearman
kendall
Lantency/ms
UNet++
0.3574
0,4622
0.3407
26.21
ResNet- 18 and UNet++
0.6374
0.5282
0.3935
32.02
ResNet-34 and UNet++
0.6082
0.5260
0.3911
34.71
ResNet-50 and UNet++
0.6406
0,5243
0.3887
36.64
ResNet-18 and UNet
0.5237
0,5050
0.3731
29.90
ResNet-18 8 and DeepLabvvplus
0.5278
0.5222
0.3878
28.43
ResNet-18 and LinkNet
0,5080
0,4816
0.3553
29.34
5 Conclusion and Future Work
We present a new perspective on circuit design, treating circuit components as point clouds. Based on this, we propose an improved multi-scale grid-based attention module based on VoxelSet [16], which achieves SOTA results on CircuitNet and ISPD2015 datasets. Furthermore, our work can serve as general-purpose feature extractor for chip design and can be adapted a wider range of downstream tasks. This is the first work to transform circuit design evaluation into point cloud perception task, presenting a novel approach to addressing the issue, It has established bridge between the relatively mature point cloud perception methods and the still developing EDA methods, enabling us to apply methods and conclusions that have been proven effective in point cloud pereeption tasks to EDA tasks.
However, should be noted that although our approach can model the relationship between points through the attention mechanism, it still does not use the prior knowledge of topology directly. Graphormer [4 encodes the topological relationships between nodes into the attention matrix, which enables the fusion of topological and geometric information in the transformer. How to incorporate the prior topological information into our model will be our future research direction.
Last but not least, the methods we use are simple and basic ones, while the GNN-based or CNN-based methods compare against have been iterated in EDA for several years. However, thanks the active Transformer community, there are many more advanced methods available. For example, LongNet [I0] and RetNet [34] not only reduce the computational complexity to linear but also improve accuracy. With the rise of Large Language Model (LLM), the use of Transformers for handling long sequential data (corresponding
large-scale circuit designs in the EDA field) has become trend. There has been a wealth of research dedicated to improving the performance of Transformers while reducing computational complexity. We hope bring this trend into the EDA domain through our work, leveraging the advancements in Transformers to enhance circuit design tasks.
Acknowledgement:
This project was supported by National Natural Science Foundation China
(NSFC No. 62276108).
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13


Reviews:
[{"review_id": "aVhVasrL1T", "reviewer": "Reviewer_YScf", "summary": "The manuscript presents several claims. Firstly, it introduces a novel perspective on \"point cloud perception methods\" for performing EDA tasks. By treating circuit components as point clouds and utilizing point cloud perception networks, the paper proposes an innovative approach to solving these tasks. Secondly, it claims superiority over CNN and GNN-based methods commonly used for EDA tasks. The authors assert that their method outperforms these existing techniques. Thirdly, the paper positions itself as the state-of-the-art solution for EDA tasks. The experimental section is well-written, easy to understand, and the overall presentation flow of the manuscript is good.", "questions": " 1. Add more comparison SOTA GNN & CNN based method comparisons for both congestion and DRC violation prediction\n\n2. Show results on other open-source datasets like (ISPD2015 which is available in circuitnet with grid level labels) and DAC 2012.\n\n3. The paper mentions “performance is higher without excessive GPU memory”  but the memory required here is approximately double that Unet. If authors could show the comparison of memories size of graph and memory required by your method and SOTA methods would be fair.\n\n4. The paper mentions that “novel perspective on circuit design” and “work has the potential to serve as a universal feature extractor for chip design” But only showed two tasks. To make these claim needs to perform other tasks in circuit design like power prediction, and delay prediction. \n", "limitations": "•\tThe scope of idea is may be limited by the size of the graph. For example, if the graph contains millions of nodes and edges which requires large GPU memory to process.\n•\tGeneralization of the method presented in paper is explored it might be the limitation since it only works on grid-based dataset. But GNN is more generalized to solve EDA problems since netlist is a graph.\n", "rating": 4, "confidence": 4, "soundness": 3, "presentation": 3, "contribution": 2, "strengths": "In terms of originality, paper uses novel perspective on the solving the EDA problems which novelty in the paper. clear description of the method, and well-structured experimental section, which includes an ablation study to enhance the validity", "weaknesses": "The experimental results provided in the paper are not sufficient. For instance, Table1 shows the comparison of congestion with CNN and GNN methods. However, in case of CNN the cited paper uses ISPD2015 dataset (Open source in circuitnet), while this paper uses circuitnet. It may be better first show comparison with Circuitnet paper \nhttps://www.sciengine.com/SCIS/doi/10.1007/s11432-022-3571-8\nSimilarly, CircuitGNN[39] which uses the ISPD2011 dataset while this paper uses Circuitnet dataset. Maybe add another comparison point cloud perception methods vs CircuitGNN on ISPD 2011 dataset.\n", "quality": null, "clarity": null, "significance": null, "originality": null, "strengths_and_weaknesses": "", "was_revised": false, "final_justification": "", "rebuttal": "We would like to thank you for your detailed comments to help us improve our work, and we will improve our manuscript correspondingly. The responses to the main concerns are as follows.\n\nFirstly, I would like to apologize for the inconvenience caused. Due to the word limit imposed on rebuttal, to provide a more comprehensive response to your questions, we have included the results tables in global rebuttal. Please evaluate our response in conjunction with the information provided in the global rebuttal, thanks!\n\n**Question 1**: Show results on other open-source datasets like ISPD2015 and DAC 2012.\n\n**Response 1**: Firstly, I would like to explain why we did not report results on the ISPD or DAC datasets. Both the ISPD and DAC datasets only provide raw topological information, requiring us to generate the placement ourselves. This step introduces randomness, which can bring challenges for fair comparisons(for more details, please refer to Section 4.1 of our paper).\n\nFortunately, as you mentioned, in an update, the CircuitNet dataset developer provided the ISPD2015 dataset with complete layout information and congestion labels generated by them. To respond to your concerns regarding the generalization of our model, we conducted experiments on the ISPD2015 congestion prediction task. The results are shown in Table G1 in global rebuttal.\n\n**Question 2:** Add more comparison SOTA GNN & CNN based method comparisons for both congestion and DRC violation prediction.\n\n**Response 2:** Here, we have conducted additional comparative experiments on the CircuitNet dataset. The results are shown in Table G2-1 and Table G2-2 in global rebuttal.\n\n**Question 3:** The paper mentions “performance is higher without excessive GPU memory” but the memory required here is approximately double that Unet. If authors could show the comparison of memories size of graph and memory required by your method and SOTA methods would be fair.\n\n**Response 3:** Thanks for your kind suggestion. We want to point out that this statement means our model does not require too large GPU memory and can be inferred on a single low-end GPU (like GTX 1080ti). We will clarify our descriptions in the revision to avoid misunderstanding. We have already compared our runtime memory with other SOTA models, please refer to Figure 5 of our paper for more details. We have conducted a study on the relationship between the runtime memory of our model and circuit scale. The results are shown in Table G3 in global rebuttal. The results indicate that the runtime memory of our model exhibits a linear increase with the circuit size, which aligns with the computed complexity of $O(nkd)$ as derived in Section 3.1 of our paper.\n\n**Question 4:** The paper mentions that “novel perspective on circuit design” and “work has the potential to serve as a universal feature extractor for chip design” But only showed two tasks. To make these claim needs to perform other tasks in circuit design like power prediction, and delay prediction.\n\n**Response 4:** Thank you for your reminder. We have performed additional tasks on our model to broaden its impact. For **power prediction**, CircuitNet offers a similar task known as IR drop. IR drop is defined as the deviation of voltage from reference (VDD, VSS). We compare our model with MAVIREC, which serves as the baseline in the CircuitNet dataset. The experimental results are shown in Table G4 in the global rebuttal.\n\nIt is worth noting that although our model's performance in the IR drop task is slightly inferior to the baseline, MAVIREC uses five power maps as its input, which are generated with power report from Innovus(an EDA tool). These features contain a much higher level of information than the raw data. In contrast, our model only uses the original position as input. We have reasons to believe that if we can have node-wise power as input, our model can achieve better performance.\n\n**Delay prediction** is to predict the delay of each net (the connections between nodes), while our model does not explicitly model it. However, our model is based on Transformer, where the attention map implicitly captures the relationships between nodes. Our model holds potential for accomplishing this task, and we will take it as our future work, to expand our work to a wider range of EDA domains.\n\n**Question 5:** The scope of idea is may be limited by the size of the graph. For example, if the graph contains millions of nodes and edges which requires large GPU memory to process.\n\n**Response 5:** Thanks for your concern, which has provided us with an intriguing idea to delve deeper into the impact of the scaling model on performance and runtime memory. As shown in Figure 1 of our paper, our encoder consists of four stages of GA modules. We tested the performance and runtime memory of models with different numbers of stages. Specifically, we test runtime memory on superblue12, which is the largest-scale design in the dataset and consists of 1,287,038 nodes. The results are shown in Table G5 in global rebuttal. \n\nUsers have the flexibility to choose models of different scales according to their requirements.\n\n**Question 6:** Generalization of the method presented in paper is explored it might be the limitation since it only works on grid-based dataset.\n\n**Response 6:** We would like to provide some clarification on our work. Our model is not limited to grid-based datasets. The encoder in our model extracts node-wise features rather than pixel-wise features. This means that both the input and output shapes are the same, represented as (N, D), where N is the number of nodes. We can modify our decoder based on the requirements of downstream tasks. If we need to do node-level prediction, we can simply replace the decoder with point cloud decoders such as PointNet[29].\n\nIf the clarifications above satisfy your concerns, please consider reassessing this paper. Thanks for your valuable comments and we are expecting further discussions with you."}, {"review_id": "NBmBu8P8Dl", "reviewer": "Reviewer_rfmi", "summary": "This paper proposes a new perspective on circuit design by viewing circuit components as point clouds and using point cloud perception methods to extract features from circuits. This achieves the goals of directly extracting features from raw data, end-to-end training, and high performance. Experimental results show that the method achieves state-of-the-art performance on congestion prediction and design rule checking tasks.", "questions": "N/A", "limitations": "The limitations is not explicitly discussed, but the future work has plotted the current limitation and proposed the next direction that authors will try to tackle such limitation.\nNo negative societal impact", "rating": 6, "confidence": 4, "soundness": 3, "presentation": 3, "contribution": 3, "strengths": "a. Overall summary:\nThe authors propose a novel approach for chip design and manufacturing processes using Electronic Design Automation (EDA) algorithms and tools.\n\nb. Methods:\nThe authors treat circuit components as point clouds and use point cloud perception methods for feature extraction.\nThey utilize a grid-based attention (GA) module to aggregate multi-scale and global geometric information.\nThe encoder converts point-wise features to grid-wise features and generates grid-wise features using a scatter-sum operator.\nThe decoder refines and downsamples the features extracted by the encoder using a ResNet-18 backbone and a UNet++ segmentation head.\nThe loss function incorporates label distribution smoothing to address imbalanced classification problems.\n\nc.  Experimental results:\nThe authors conducted experiments on the CircuitNet dataset.\nThe proposed method achieved state-of-the-art performance in congestion prediction and design rule check (DRC) violation prediction tasks.\nThe method outperformed UNet in terms of performance, with a runtime memory of 3721MB for the proposed method and 1931MB for UNet.", "weaknesses": "N/A", "quality": null, "clarity": null, "significance": null, "originality": null, "strengths_and_weaknesses": "", "was_revised": false, "final_justification": "", "rebuttal": "Dear Reviewer rfmi\n\nThank you for your recognition of our work. If you have any new questions or concerns after reviewing our discussions with other reviewers, we welcome further discussion and are available to address any additional inquiries you may have. Please feel free to reach out to us.\n\nBest wishes\n\nAuthors"}, {"review_id": "cj9RFQFTht", "reviewer": "Reviewer_DbXo", "summary": "This paper proposes to use point cloud perception methods to extract features from the circuit by treating the circuit components as point clouds. The proposed method solves the infeasibility of end-to-end training in the CNN-based method and the limitation of time-consuming preprocessing in the GNN-based method. The evaluation result shows the effectiveness of the proposed method on CircuitNet dataset: it outperforms the mainstream CNN-based and GNN-based methods on congestion prediction and design rule check violation prediction.", "questions": "1. In the decoder part, motivations for using ResNet18 and UNet++ are missing. Is the selection of network architecture in the decoder part based on the downstream tasks? For different tasks, is necessary to use different networks?", "limitations": "The authors addressed limitations. ", "rating": 6, "confidence": 2, "soundness": 3, "presentation": 3, "contribution": 2, "strengths": "1. This paper facilitates Electronic Design Automation (EDA) by using the well-researched point cloud perception methods, providing a new perspective for circuit design.\n2. The encoder part, especially the multi-scale grid-based attention architecture, reduces the computational complexity, and compresses the information as well. ", "weaknesses": "  1. Please give the runtime latency comparison with the CNN-based method to prove the proposed method reduces design cycles.", "quality": null, "clarity": null, "significance": null, "originality": null, "strengths_and_weaknesses": "", "was_revised": false, "final_justification": "", "rebuttal": "Thanks for the valuable comments and suggestions which help us improve this work. Following are our detailed responses to your concerns.\n\n**Question 1**：In the decoder part, motivations for using ResNet18 and UNet++ are missing. Is the selection of network architecture in the decoder part based on the downstream tasks? For different tasks, is necessary to use different networks?\n\n**Response 1**:Your viewpoint is correct. The choice of decoder architecture is closely linked to downstream tasks. The task provided in CircuintNet, the dataset used in this paper, is concerned with prediction for grid-level labels. For example, in the congestion prediction task, we aim to predict the congestion rate for each pixel. This task bears a resemblance to the classical task of image segmentation in computer vision. Therefore, in the decoder part, we opted for the classic combination of a backbone network with a segmentation head. This combination has been proven to be effective for pixel-wise prediction tasks.\n\nIt is worth noting that our model has the potential to be applied to a wider range of downstream tasks. This is because we extract node-level features rather than pixel-level features. By replacing the decoder with other point cloud decoders, such as PointNet and Point Transformer, we can extend our model to node-level prediction tasks. This flexibility is not achievable with CNN-based models, as their inputs and outputs are grid-level (or pixel-level).\n\nThe core contribution of our work is to provide a novel perspective on circuit design. The main innovation lies in the encoder, so we did not focus extensively on the design of the decoder. However, prompted by your suggestion, we realized the significance of conducting more ablation experiments on the decoder. We adopted various decoder architectures, and performed ablation experiments on the congestion prediction task. The experimental results are summarized in Table R1\n\n| Decoder                        | pearson    | spearman   | kendall    | Latency/ms |\n| ------------------------------ | ---------- | ---------- | ---------- | ----------- |\n| UNet++ [45]                    | 0.3574     | 0.4622     | 0.3407     | 26          |\n| ResNet-18 [14] and UNet++ [45]  | 0.6374     | **0.5282** | **0.3935** | 32          |\n| ResNet-34 and UNet++ [45]      | 0.6082     | 0.5260     | 0.3911     | 34.71       |\n| ResNet-50 and UNet++ [45]      | **0.6406** | 0.5243     | 0.3887     | 36.64       |\n| ResNet-18 and UNet [31]         | 0.5237     | 0.5050     | 0.3731     | 29.9        |\n| ResNet-18 and DeepLabv3plus [7] | 0.5278     | 0.5222     | 0.3878     | 28.43       |\n| ResNet-18 and LinkNet [6]       | 0.5080     | 0.4816     | 0.3553     | 29.34       |\n\nTable R1: The ablation experiments on the decoder of congestion prediction\n\nAs shown in Table R1, we can observe that refining the features with ResNet before performing segmentation is necessary. This process allows the node-wise features extracted by the encoder to be adapted to the grid-wise features, which serve as the output of the decoder. Considering the trade-off between model performance and latency, we believe that ResNet-18 and UNet++ is the best choice.\n\n**Question 2**：Please give the runtime latency comparison with the CNN-based method to prove the proposed method reduces design cycles.\n\n**Response 2**: Here we present the preprocessing time and inference time of our method compared to the CNN-based method at different scales of component numbers.\n\n| Method   | Number of Nodes | Preprocessing Time/ms | Inference Time/ms | Total Time/ms |\n| -------- | --------------- | ------------------ | -------------- | ---------- |\n| Gpdl [22] | 29521           | 204              | 5.4        | 209.4    |\n| Ours     | 29521           | 0                  | 32.2        | 32.2     |\n| Gpdl [22]    | 149655          | 906.1            | 5.4         | 911.5    |\n| Ours     | 149655          | 0                  | 96.4         | 96.4     |\n\nTable R2: The time consumption of various methods on circuit designs of different scales.\n\nThe experiment shows that despite our model not outperforming CNN-based methods in terms of inference time, it achieves a shorter overall time compared to them, thereby accomplishing the goal of reducing design cycles. This is because CNN-based methods require extracting hand-crafted features (such as RUDY, Pin RUDY) from the circuit, necessitating time-consuming preprocessing that involves traversing the positions of all components and calculating density. In contrast, our method directly utilizes the raw positional information of the components as input, enabling end-to-end processing. The time tests were conducted on AMD EPYC 7502P 32-Core 2.5GHz CPU and NVIDIA RTX 3090 GPU.\n\nIf the response satisfies your concerns, please consider reassessing the score. Thanks for your valuable comments and looking forward to your reply.\n\n*Due to the limitations in the length of the response, we utilize the reference number from our paper directly, without including an additional citation in the rebuttal. Please refer to Section **References** of the paper."}, {"review_id": "Ekl6rejiab", "reviewer": "Reviewer_SgH5", "summary": "This paper introduces a novel perspective on circuit design by treating circuit components as point clouds and utilizing point cloud perception methods for feature extraction. Previous approaches either relied on hand-crafted methods to transform circuit designs into images for CNN feature extraction or employed GNNs for graph-based feature extraction, which required time-consuming preprocessing. In contrast, the proposed method enables direct feature extraction from raw data without preprocessing, allowing for end-to-end training and achieving high performance. Experimental results on the CircuitNet dataset demonstrate the superiority of the proposed method in congestion prediction and design rule check (DRC) violation prediction tasks. This approach establishes a connection between point cloud perception methods and EDA algorithms, facilitating the application of collective intelligence in solving circuit design tasks. The method outperforms hand-crafted features and CNN-based methods in feature extraction while eliminating the need for preprocessing, thereby reducing processing time. The work shows potential as a universal feature extractor for chip design, adaptable to a wide range of downstream tasks.", "questions": "A few questions:\n\nIn figure 5 shows, 3x model size than unet. Which creates the question of scaling model. If a smaller version of the model with same size of Unet will get better accuracy?\n\nIn figure 4 shows preprocessing times, what is the total runtime and inference time of the model?", "limitations": "The authors addressed the limitations correctly.", "rating": 7, "confidence": 3, "soundness": 3, "presentation": 2, "contribution": 3, "strengths": "The paper introduces a groundbreaking method that addresses circuit congestion prediction and design rule check (DRC) violation prediction in electronic design automation (EDA). By leveraging the concept of point clouds and incorporating a genetic algorithm (GA) module, the proposed approach achieves significant improvements over existing techniques commonly employed in EDA tools. The utilization of point cloud perception enables a fresh perspective on circuit design analysis, allowing for more accurate and efficient prediction of congestion and violations. Additionally, the integration of the GA module enhances the optimization process, leading to enhanced results and performance. This novel method showcases the potential for innovative approaches in EDA, opening doors to advanced techniques that can better handle circuit design challenges and contribute to improved circuit performance and reliability.\n", "weaknesses": "To enhance the comprehensiveness of the paper, it would be valuable to expand the evaluation to encompass other applications within the domain of electronic design automation (EDA), such as circuit placement. By investigating the effectiveness of the proposed method in various EDA tasks, including placement, the authors can provide a more holistic understanding of its capabilities and potential impact.\nFurthermore, conducting additional ablation studies that delve into the runtime and scaling model trade-offs would contribute to a deeper analysis of the proposed approach. These studies would shed light on the performance and efficiency aspects of the method, allowing for a better understanding of its behavior under different conditions and dataset sizes. This information would be particularly useful for practitioners and researchers aiming to apply the method in real-world scenarios.\nAnother aspect worth exploring is the authors' emphasis on the encoder while leaving the decoder section with limited analysis. This raises intriguing questions regarding the possibility of modifying the output format to potentially improve the EDA software pipeline. Investigating alternative output formats or exploring ways to optimize the decoder component could uncover opportunities for further enhancing the proposed method's integration into EDA workflows.\nMoreover, the paper opens up avenues for considering the incorporation of this approach into other areas of EDA tools beyond congestion prediction and DRC violation prediction. Exploring how the proposed method could be leveraged in other stages of the EDA process, such as routing, power optimization, or physical design verification, would demonstrate its versatility and potential for broader application. This could foster innovation in multiple facets of EDA, leading to more efficient and advanced chip designs.\nBy addressing these suggestions, the paper would offer a more comprehensive evaluation, deeper insights into runtime and scaling trade-offs, considerations for optimizing the decoder section, and opportunities for applying the proposed approach in various EDA tool domains. These extensions would further solidify the paper's contribution and provide valuable guidance for future research and development in the EDA field.", "quality": null, "clarity": null, "significance": null, "originality": null, "strengths_and_weaknesses": "", "was_revised": false, "final_justification": "", "rebuttal": "We would like to thank you for your detailed comments to help us improve our work, and we will improve our manuscript correspondingly. The responses to the main concerns are as follows.\n\n**Question 1**：In figure 5 shows, 3x model size than unet. Which creates the question of scaling model. If a smaller version of the model with same size of Unet will get better accuracy? Furthermore, conducting additional ablation studies that delve into the runtime and scaling model trade-offs would contribute to a deeper analysis of the proposed approach. \n\n**Response 1**: As shown in Figure 1 of our paper, our encoder consists of four stages of GA modules, each with different grid sizes to integrate multi-scale information. We test the performance and latency of models with different numbers of stages, aiming to provide the community with more options.\n\n|Number of Stages|pearson|spearman|kendall|Latency/ms|\n|-|-|-|-|-|\n|1-stage|0.5260|0.4853|0.3582|12.15|\n|2-stage|0.5322|0.4972|0.3668|15.70|\n|3-stage|0.5793|0.4977|0.3683|23.21|\n|4-stage|**0.6374**|**0.5282**|**0.3935**|32.21|\n\nTable R1: The performance and latency of models with different numbers of stages\n\n**Question 2**：In figure 4 shows preprocessing times, what is the total runtime and inference time of the model?\n\n**Response 2**: Here we present the preprocessing time and inference time of our method compared to CNN-based method (Gpdl[22]) and GNN-based(CircuitGNN[39]) method at different scales of component numbers.\n\n|Method|Number of Nodes|Preprocessing Time/s|Inference Time/s|Total Time/s|\n|-|-|-|-|-|\n|Gpdl|29521|0.204|0.005|0.209|\n|CircuitGNN|29521|40.43|0.008|40.438|\n|Ours|29521|0|0.032|0.032|\n|Gpdl|149655|0.906|0.005|0.911|\n|CircuitGNN|149655|756.2|0.030|756.23|\n|Ours|149655|0|0.096|0.096|\n\nTable R2:  The time cost of various methods on circuit designs of different scales\n\nThe experiment shows that our model achieves a shorter overall time compared to others, accomplishing the goal of reducing design cycles.\n\nThe time tests were conducted on AMD EPYC 7502P 32-Core 2.5GHz and NVIDIA RTX 3090.\n\n**Question 3**: To enhance the comprehensiveness of the paper, it would be valuable to expand the evaluation to encompass other applications within the domain of electronic design automation (EDA), such as circuit placement. By investigating the effectiveness of the proposed method in various EDA tasks, including placement.\n\n**Response 3**: Thank you for your suggestion, which is very important to enhance the impact of our work in the EDA field. While the experimenting with circuit placement may use reinforcement learning methods, which is beyond the scope of our paper, we'd be happy to discuss the possibility with you. To discuss this issue, let's first have a brief understanding of how the circuit placement task is addressed. In simple terms, circuit placement takes the position of the circuit as input and minimizes the minimum wire length and layout density. This can be represented by Eq.(1)，where $\\min \\left(\\sum WL(x,y)\\right)$ is the minimum wirelength, and$D\\left(x,y\\right)$ is the density penalty. We can add congestion rate as a penalty term to the optimization function, which$L\\left(x,y\\right)$stands for congestion penalty.\n$$\\min\\left(\\sum WL(x,y)\\right)+\\lambda D\\left(x,y\\right)+\\gamma L\\left(x,y\\right)\\tag{1}$$\nThe effectiveness of this approach is demonstrated in Gpdl, where the placement method with the addition of congestion penalty achieved up to a 9.05% reduction in congestion rate and a 5.30% reduction in wire length compared to the SOTA. Compared to Gpdl, our model offers more accurate congestion predictions, with the potential to further reduce congestion and wire length in the layout.\n\n**Question 4**：Another aspect worth exploring is the authors' emphasis on the encoder while leaving the decoder section with limited analysis. Investigating alternative output formats or exploring ways to optimize the decoder component could uncover opportunities for further enhancing the proposed method's integration into EDA workflows.\n\n**Response 4**: This question is similar to **Question 1** raised by Reviewer DbXo. Due to the limitations in the length of the response, please refer to **Response 1** we gave to Reviewer DbXo .\n\n**Question 5**：Exploring how the proposed method could be leveraged in other stages of the EDA process, such as routing, power optimization, or physical design verification, would demonstrate its versatility and potential for broader application\n\n**Response 5**: We would be delighted to discuss the role of our method in other stages of the EDA process. Our model can be effectively employed as a plug-in within corresponding algorithms to enhance their performance.\n\n**Routing and Power Optimization**: Similar to our discussion in **Response 3**, regarding routing, our model can also improve the performance of the routing algorithm by predicting wiring congestion as a penalty term for the optimization objective. For power optimization, by predicting the power of the circuit, we can directly incorporate it as an optimization term in power optimization algorithms.  For specific details, please refer to **Response 3**.\n\n**Physical Design Verification**: Physical design verification consists of three main parts: design rule check, layout versus schematic, and electrical reliability check. In our paper, we extensively discussed the performance of our model in the DRC task(please refer to Section 4.4 of the paper), where it achieved outstanding results. Based on this success, we believe that our method can deliver equally impressive performance in the other two tasks as well\n\nWe hope the explanations and results above solve your concerns. Thanks for your valuable comments and looking forward to your reply.\n\n*Due to the limitations in the length of the response, we utilize the reference number from our paper directly, without including an additional citation in the rebuttal. Please refer to Section **References** of the paper."}]

Author rebuttal:
## 

| Method         | pearson    | spearman   | kendall    |
| -------------- | ---------- | ---------- | ---------- |
| Gpdl [22]       | 0.5202     | 0.1880     | 0.1423     |
| UNet [31]       | 0.5253     | 0.1481     | 0.1124     |
| UNet++ [45]     | 0.4593     | 0.1862     | 0.1423     |
| CircuitGNN [39] | 0.394      | 0.1912     | 0.1614     |
| Ours           | **0.6534** | **0.2244** | **0.1710** |

Table G1: Congestion prediction result on ISPD2015

| Method        | pearson    | spearman   | kendall    |
| ------------- | ---------- | ---------- | ---------- |
| MANet [1*]     | 0.4856     | 0.5167     | 0.3797     |
| DeepLabv3 [2*] | 0.5091     | 0.5211     | 0.3834     |
| Ours          | **0.6374** | **0.5282** | **0.3935** |

Table G2-1:  Additional results on CircuitNet congestion prediction

| Method        | pearson    | spearman   | kendall    |
| ------------- | ---------- | ---------- | ---------- |
| MANet [1*]     | 0.3420     | 0.2395     | 0.1916     |
| DeepLabv3 [2*] | **0.3760** | 0.2480     | 0.1989     |
| Ours          | 0.3707     | **0.3094** | **0.2471** |

Table G2-2:  Additional results on CircuitNet DRC violation prediction

| Number of Nodes | Runtime Memory/MB |
| --------------- | ----------------- |
| 29521           | 1913              |
| 48127           | 2197              |
| 81643           | 2707              |
| 108292          | 3151              |
| 127419          | 3471              |

Table G3: The runtime memory of our model on circuit designs of different scales

| Method       | Input          | pearson | spearman | kendall |
| ------------ | -------------- | ------- | -------- | ------- |
| MAVIREC [3*] | Power Maps (high level)    | 0.7144  | 0.8369   | 0.7344  |
| Ours         | Nodes Position (low level) | 0.6395  | 0.829    | 0.7158  |

Table G4: IR drop prediction results

| Method         | pearson | spearman | kendall | Runtime Memory/MB |
| -------------- | ------- | -------- | ------- | ----------------- |
| Ours (4-stage) | 0.6374  | 0.5282   | 0.3935  | 22487             |
| Ours (3-stage) | 0.5793  | 0.4977   | 0.3683  | 12429             |
| Ours (2-stage) | 0.5322  | 0.4972   | 0.3668  | 7379              |
| Ours (1-stage) | 0.5260  | 0.4853   | 0.3582  | 4867              |
| CircuitGNN [39]     | 0.3287  | 0.4483   | 0.3688  | 12017             |

Table G5:  The performance of models with different numbers of stages on the CircuitNet congestion prediction task, and their runtime memory during the processing of superbule12, which consists of 1,287,038 nodes.

[1*]T. Fan, G. Wang, Y. Li and H. Wang, "MA-Net: A Multi-Scale Attention Network for Liver and Tumor Segmentation," in *IEEE Access*, vol. 8, pp. 179656-179665, 2020, doi: 10.1109/ACCESS.2020.3025372.

[2*]Chen, Liang-Chieh, et al. "Rethinking atrous convolution for semantic image segmentation." *arXiv preprint arXiv:1706.05587* (2017).

[3*]Chhabria, Vidya A., et al. "MAVIREC: ML-aided vectored IR-drop estimation and classification." *2021 Design, Automation & Test in Europe Conference & Exhibition (DATE)*. IEEE, 2021.

*Due to the limitations in the length of the response, we utilize the reference number from our paper directly, without including an additional citation in the rebuttal unless otherwise stated. Please refer to Section **References** of the paper.

Meta-review: The paper proposes a novel approach to Electronic Design Automation (EDA) tasks by treating circuit components as point clouds and employing point cloud perception methods for feature extraction. The authors claim that this approach outperforms existing CNN and GNN methods in congestion prediction and Design Rule Check (DRC) violation prediction tasks. 

The paper presents a novel approach to EDA tasks, which is well-received for its originality and potential impact on the field.  Considering the originality of the work, and the authors' thorough responses to the reviews, I recommend Accept for this paper. It presents a promising avenue for EDA tasks with a unique approach and has the potential for high impact in the field. However, the authors should consider extending their evaluations and providing a more comprehensive analysis to address the weaknesses identified.
Decision: Accept (poster)