Neural Modulation for Flash Memory: An Unsupervised Learning Framework for Improved Reliability
Authors: Jonathan Zedaka
Elisha Halperin
Evgeny Blaichman
Amit Berman
Venue: NeurIPS 2023 poster (2023)
Keywords: WGAN
GAN
Autoencoder
Unsupervised Learning
Generative models
Flash Memory
NAND
Modulation
Reliability
Flash
Communication system

Abstract: Recent years have witnessed a significant increase in the storage density of NAND flash memory, making it a critical component in modern electronic devices. However, with the rise in storage capacity comes an increased likelihood of errors in data storage and retrieval. The growing number of errors poses ongoing challenges for system designers and engineers, in terms of the characterization, modeling, and optimization of NAND-based systems. We present a novel approach for modeling and preventing errors by utilizing the capabilities of generative and unsupervised machine learning methods. As part of our research, we constructed and trained a neural modulator that translates information bits into programming operations on each memory cell in NAND devices. Our modulator, tailored explicitly for flash memory channels, provides a smart writing scheme that reduces programming errors as well as compensates for data degradation over time. Specifically, the modulator is based on an auto-encoder architecture with an additional channel model embedded between the encoder and the decoder. A conditional generative adversarial network (cGAN) was used to construct the channel model. Optimized for the end-of-life work-point, the learned memory system outperforms the prior art by up to 56\% in raw bit error rate (RBER) and extends the lifetime of the flash memory block by up to 25\%.

Neural Modulation for Flash Memory: An Unsupervised Learning Framework for Improved Reliability
Jonathan Zedaka Samsung Semiconductor Israel Research and Development Center {jonathan. 2, elisha. h, evgeny. bl, amit (erman))@annan com
Elisha Halperin Evgeny Blaichman Amit Berman
Abstract
Recent years have witnessed a significant increase in the storage density of NAND flash memory, making a critical component modern electronic devices. How- ever, with the rise in storage capacity comes an increased likelihood of errors in data storage and retrieval. The growing number of errors poses ongoing challenges for system designers and engineers, in terms of the characterization, modeling, and optimization of NAND-based systems. We present novel approach for modeling and preventing errors by utilizing the capabilities of generative and unsupervised machine learning methods. As part of our research, we constructed and trained a neural modulator that translates information bits into programming operations on each memory cell NAND devices. Our modulator, tailored explicitly for flash memory channels, provides smart writing scheme that reduces programming errors as well as compensates for data degradation over time. Specifically, the modulator is based on an auto-encoder architecture with additional channel model embedded between the encoder and the decoder. A conditional generative adversarial network (cGAN) was used to construct the channel model. Optimized for the end-of-line life work work-point, the learned memory system outperforms the prior art by up 56% in raw bit error rate (RBER) and extends the lifetime of the flash memory block by up to 25%.
Introduction
The continued scaling of flash memory technology into smaller process nodes, combined with the increased information capacity of each flash cell (i.e, storing more bits per cell), has placed NAND flash memory at the forefront of modern storage technology. Those advances comes at the cost of increased vulnerability to various eиror mechanisms that can compromise data integrity and system reliability. The endurance of the flash can be measured by the number of program craae (PE) cycles the cells can undergo, before the error-correction-cod (ECC) decoder fails to reconstruct the programmed bits.
Modern flash devices suffer from multiple sources of error, such as write-induced [ data retention 2 and read-induced [4] errors. The impact of these different mechanisms vary between physical locations the chip. addition, the probability of errors to occur on different cells is not independent: The charge stored in a flash memory cell is affected by the state of its neighboring cells (see section 2.1.4.. phenomenon dubbed inter-cell interference (ICI).
To maintain high reliability while pushing for ever-growing storage density, manufactures devote significant resources comprehensive characterization and optimization of flash systems 6 Over the years, the industry has developed numerous strategies for mitigating errors, including robust ECC algorithms 7. smart writing schemes and adaptive read methods 9 10 However, all above
37th Conference on Neural Information Processing Systems (NcurIPS 2023).

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techniques optimize either the data storage or retrieval operations individually, ignoring their built-in dependencies. Furthermore, they typically neglect the inter-cell correlations between the cells. To that end, we introduce the neural-modulatio
framework- end-to-end unsupervised optimization method which is designed to mitigate the complex error patterns of flash memory devices and address the plethora of correlations between their components. By using learning based approach, we enable (i) state-of-the-an modeling and optimization of the system; and (ii) flexibility and generalization: optimization of new flash generation can be done in simple and automatic procedure.
The flash memory stores information in an array of cells, where the information stored in each cell is encoded in its transistor threshold voltage Vzy- Current writing schemes allocate each cell result in minimal error-rate with an emphasize
with a target Vth- The targets are optimized on the end-of-life workpoint. So far, such prior art modulation methods base the choice of the target voltage solely on the data stored in the cell. This kind of modulation, illustrated in Fig D is referred to as a pulse amplitude modulation (PAM). In this work, we propose novel ap- proach to mitigate the ICI by optimizing the target Ush of the memory cells with respect to the data designated to their neighbors. By employing such scheme, preemptively counteract the ICI.
We optimize the Uth target modulation by per- forming an end-to-end training of the flash memory system (see Fig 2 Our method is based on the analogy between memory cells and communication channels-boit systems re- ceive and transmit data. Consequently, we can follow recent advances in communication re- search [T 12 13]. We use an unsupervised learning method, jointly training the transmit- ter and receiver of a communication system as an auto-encoder. The channel auto-encoder is trained using a reconstruction loss between the input of the encoder and the output of the de- coder (see Fig. [). In the flash memory domain, define the transmitter of the system, which we dub the modulator, as the module translating the information bits into eth targets.
Via targets
[b)
Figure 1: An illustration of 4-PAM modulation for Multi-Level cell NAND device (storing 2 bits per cell). Each data symbol is allocated with sin- gle VeA target that minimize the BER at the end-of life work-point. Panel (a) shows the distribution of the cells oth around the chosen targets immediately after the writing operation. Panel (b) illustrates the same data, at the end-of life work point. Cells with ets within the overlap region between the distribu- tions are susceptible to read error.
The joint optimization of the transmitter and receiver, using standard back-propa,ation, re- quires calculating the channel gradient with re- spect to the transmitted signal (see in Fig. 5).. Since, however, the flash channel is non- differentiable, cannot naively implement this technique. To overcome this issue, we train conditional generative adversarial network (cGAN) based channel model as proposed in 14]. Recent work by [15 showed that GANs can be useful in modeling the UtΛ distribution of the flash cells by using the data symbols. In this work, the trained channel model learns produce samples from the UsA distribution of a memory cell given the Vr targets of the cell and its neighbors. Using the neighbors data, the channel model is able to capture the inter-cell interference statistics, allowing the modulator to counteract this phenomenon.
To reduce the additional programming latency caused by our neural modulator, develop novel shared pulses programming scheme. The suggested scheme, which is based on the Incremental Step Pulse Programming (ISPP) scheme [16). achieves accurate programming, without increasing the amount of programming pulses, and with only a minor increase in programming time.
When optimized for the EOL work-point, the learned memory system outperforms the prior art by up to 56% in terms raw bit error rate (RBER), extending the tested BOL work-point of the chip by 25% in terms of PE cycles. This gain is achieved without increasing the read latency.

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Trainable block
Neighbors data
Symbol
Target
Read
Recovered symbol
Modulator
Channel Generator
Demodulator
Neighbors symbols
Neighbare
targets
Defauit
Targets
Figure 2: The neural modulation system architecture. The channel generator is a pre-trained model of the NAND device. The modulator is trained to output the optimal program target for each cell, considering its input symbol and the symbols of its neighbors. The output targets flow through the GAN based channel model that simulates the programming operation, data retention process and subsequent read operation, to output a stochastic tth read for the cell. From there, the Uth read is passed to the demodulator to recover the original programmed symbol.
2 Preliminaries
2.1 Flash memory basies
2.1.1
The 3D NAND flash architecture
The basic unit of a 3D-NAND Flash Memory is cell-a semiconductor based charge trap transistor. The cell's information is encoded its transistor threshold voltage 4th. which is real value E [Mmin, m. The range (Umin, Umax] is referred to as the dynamic range.
Modern flash devices typically store multiple bits per cell (BPC). The dynamical range is divided into BCC segments, each corresponding to a different information bits dubbed symbol. We define a level the group of cells that hold the same symbol. Flash devices that store 1/2/3/4 BPC are usually referred to as single-level cell (SLC)multi-level cell (ML.)/rriple-eeeel cell (TL.C)Qquaruupte-eeel cell (QLC), respectively.
The flash cells are organized in three dimensional arrays called blocks (see Fig. 3). The three dimensions of the block the pillar/string axis, the wordline (WL) axis and the bit-line (BL) axis. The two dimensional cross section of the block consisting of the pillar and WL axes called the string select line (SSL).
2.1.2
The flash memory interface
The two most basic operations on the flash mem- ory device programming and reading.
1. Programming the block with informa- tion; and more specifically, bringing the Ves of each flash cell to the volt- age target assigned to the symbol that should be stored in that cell. This oper- ation is done using the ISPP algorithm described in the supplementary mate- rial.
WLL
string/ pillar
2. Reading the data stored in WL. This operations is done by segment- ing [Vmin: "mmax into BPC voltage re- gions, corresponding the PBC data symbols.
Figure 3: Top view of the 3D NAND flash block structure
3

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2.1.3 Errors in NAND flash memory
Read errors occurs if there is mismatch between the symbol designated for the cell and its actual threshold voltage. The fraction of bits which were incorrectly assigned by the reading algorithm out of all bits read is called the Bit Error Rate (BER).
Errors in flash memory devices can be induced by many factors 1. but for the purpose of this work we will focus only on two of them programming variation and retention disturb.
The eth of memory cell after receiving programming pulse is stochastic function of the initial cell Et and the pulse magnitude. Therefore, programming a level in some WL w will result in some distribution of the Uth close to the desired target, regardless of the writing algorithm. We define the programming variation as the noise injected by the programming algorithm.
The retention disturb 2 3 is defined as the change during the data storage time, after the programming phase has completed. The retention disturb happens because charge leaks out of the cell over time, thus changing its Vtk-
The shift in eth due to programming variation and retention disturb varies between WLs and SSLs. Furthermore, it is also function of the number of PE cycles experienced by the block. Each PE cycle wears down the block cells, making them more vulnerable for disturbs, and therefore increases the BER of the block.
2.1.4 Inter-cell interference in the 3D-NAND block
The most dominant coupling between cells in a 3D-NAND, and hence Inter-Cell Interference (ICI), occurs along the pillar axis, and it includes phenomena such as programming interference and lateral migration. The programming inter- ference is the phenomenon at which program- ming of a flash cell increases the Ush of adjacent neighbor cells [1. The programming interfer- ence effect on a flash cell is a stochastic function of the amount and magnitude of the pulses its neighbors experience. Therefore, it is also function of the vu, targets of its neighbors.
Meen vey charge (a:11)
-44
Neighbors' symbo
The lateral migration [ [7], which takes place during data retention period, describes charge migration between cells with different Uth. Fig f Iillustrates the lateral migration phenomenon measured on a 3D-NAND chip programmed with QLC data. We measure the Vea of cach cell immediately after programming the block, and again after effective retention period of one month at room temperature] [ The figure shows the mean Vta change of the cells programmed to data symbol 15 as function of the symbol of its two adjacent cells. We obtained that low-symbol syb-soooll-nngbbbrrs cause higher voltage loss over time.
Figure 4: Lateral migration out of a 3D-NAND memory cell as a function of its neighbor symbol. The change of Ut of level 15, shown in the figure, was measured on a single WL of QLC flash mem- ory device. The charge loss grows as the neighbors' symbol is lower. The figure is presented with 95% confidence interval.
2.2 Generative adversarial networks
Generative adversarial networks (GANs) 19 are class of generative models consisting of two separate neural networks (NNs), generator Ge and discriminator Dy. The basic setup of GANs consists of set of samples {x; ] C X' drawn from some distribution of interest p, which we wish to produce new samples from. GANs learn the distribution p by fixing a rather simple distribution pz (Gaussian for example) over a latent space Z and then optimizing the generator function Ge Z + X such that the push-forward measure PG == G, (pz) = P2 G will be as close as possible to
'The effective data retention time simulated at 100% C' according to Arthenius" Law described in 18

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In this work we apply a conditional version of the Wasserstein GAN (WGAN) proposed in [20 21] which uses the Wasserstein distance as the training loss of the generator. WGANs were proven to enable more stable training and convergence 20
2.3 End-to-end training of autoencoder- communication systems
End-to-end training of autoencoder-based communication systems a relatively new approach [3 for the joint optimization of both the transmitter and the receiver of the system. With this approach, an autoencoder-lice like architecture is used, where the transmitter acts as the encoder and the receiver as the decoder. Both are represented as NNs with parameters Or and θR respectively, which we train jointly using back paop-propagttion. The training uses a reconstruction loss between the symbol 8 the input of the transmitter, and the reconstructed symbol & at the output of the receiver (see Fig 5) where
á = fe (C (Ser (s)))
This reconstruction loss is commonly defined as the categorical Cross-Entropy (CE) between and 8, where C' represents the system channel.
3 End-to-end learning based modulation for the flash memory
The basic program-read flow of the 3D-NAND flash memory suffers from multiple sources of error, degrading its endurance both in terms of PE cycles, as well as data retention time. To mitigate the effects of those errors we introduce a neural-modulatio
system, which is inspired by the end-to-end training approach described in Section 2.3 Given some programming scheme, the neural-Modulation system optimizes the Ut targets of the 3D-NAND block. On top of optimizing the Uth targets, our system performs pre-distortion of the target of each cell, to counter the ICI phenomenon (see section 2.1.4). For this purpose, the Vea target is optimized conditioned on the symbols of its pillar neighbors. This novel approach gives rise a significant BER reduction, and by that, extend the EOL work-point of the NAND flash block.
3.1 Flash memory as classical communication system
In order to fully describe the end-to-end training approach outlined in the previews section, we first turn to formally define the NAND flash memory as a classical communication system. The three components of classical communication system are the transmitter, channel and receiver. We adjust their definition to memory devices in the following way:
The transmitter fe which we dub the modulator, the component responsible for translating the input symbols s into tth. targets for the programming algorithm.
2. The channel C' is the composition of the programming scheme, the data retention process, and the Uth read operation. simulates the disturbs and errors deseribed in Section 2.1.3)
3. The system receiver fen. which dub the demodulator, is the component which re- constructs the data symbols & from the Ves readings.
Using this formulation we adopt the end-to-end learning based approach described in Section 2.3 to learn an optimal modulation for our channel. Bellow we elaborate on the three main components of our system.
3.2 eWGAN NAND channel model
We model our NAND channel as a cWGAN 21 Modeling the NAND as a cGAN is essential for training the auto-encoder because allows differentiating the channel 14]
The generator trained
9
Transmitter
Channel
Recelver
P(y|
Figure 5: The structure of an end-to-er learning based communication system.
5

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to learn the cell's threshold voltage oi distribution given its "context" the cWGAN condition which includes the following:
1. The program target of the cell yeeR.
2. The target Ush of the two nearest pillar neighbors of the cell Treighbors E IR2
3. The SSL index, ssl E [Nasta] and WL index wl E [Neie] of the programmed WL.
Including Theighhorr in the cell context is crucial for modeling the ICI effects. Consequently, allows the neural- counteract the ICI. Since different WLs in the block exhibit different reactions both to programming pulses as well as the ICI noise, the SSL and WL indices of the programmed WL are also used to condition our eWGAN. We can therefore formulate the cWGAN objective as learning to produce a sample of Ush (Uaa reads from the NAND) given the conditional density
to adjust the target of each cell according to dyh. of its neighbors and
coll IP (uth (t Tneighhors. ssl,, wl)
For full model specification see the supplementary material.
3.3 The neural modulator and demodulator
The next two components of our system are the modulator and the demodulator. The modulator is a function
fem- [2BrC] x C - [Uminn Umaz]:
mapping information symbols E [2 to Uth targets to be programmed to the NAND, conditioned on the "context" of the target cell e E C. The context e comprises of the symbols designated to the two neighboring cells along the SSL (one on each side of our given cell), the SSL index and WL index of the target cell C = [2BPC] x [2BC]] x [Nasts] x [Nwis]-
The demodulator,
B BPC
Sep [Umin Umaz]
[Nasts] [Nunt]]
receives UyΛ read from the channel. It then reconstructs the programmed symbol by learning the log likelihood ratio (LLR) of each symbol E [2BPC] given the ut read. Note that the demodulator does not receive any information about the cell's 's neighbors. This forces our system to exploit the information about the neighbors only at the modulation stage, and thus perform pre-distortion to offset the ICI. In other words, all the information about the neighbors is already encoded by the modulator into its output. This independence of the demodulator from the cell's neighbors also guarantees that our system will not require any changes to be made the current reading algorithm. As there are physical differences between different sections of the block, we use the SSL and WL indices as input both the modulator and the demodulator.
The number of layers and other NN parameters of both modulator and demodulator are given in the supplementary material. The output of the modulator is passed through tanh function, to enforce it to be in the range of (-1, 1). This output is then scaled to the dynamic range of the chip (Umin Umaz). ), forcing the modulator to choose only targets that are feasible for programming.
3.4
The training procedure
The meuual-modulation training procedure divided into two steps. In the first step we train the cWGAN based channel model. The data we use as train set is a set of U.A reads of single block programmed with given targets 2 The critic utilized solely to train the generator, and afterwards discarded. The second step includes the joint training of the modulator and demodulator. As a prerequisite, we assume to have the pretrained, frozen channel model (i.e. the generator from the previous step). At each iteration batch B of samples b E [2 x C. flows through the modulator, generating a program target for each sample. At this point each cell has a corresponding target, but still require the targets of its neighbor cells well, to be used model. We choose the neighbor cells targets according to some constant set of BBCC targets that spread uniformly over the dynamic range [Umin; Umnaz] (we refer those targets as the "default
input for the channel
We set of 2 BPC 1 targets that spread uniformly over the dynamic range [umin Umox

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Colls count (a.u.)
real date generated
Figure 7: Comparison of the real and generated Ueh histograms of single QLC WL.
targets"). The targets and neighbor targets then pass through the channel model to sample from the oth distribution of the cells when programming them to those targets. Finally, the demodulator is used to predict the original symbols given the simulated Uea and the SSL and WL indices the cells. As the CE loss between the recovered symbols and the input symbols described in Section 3 The supplementary material provides the full details of all training parameters.
training loss
3.5 Programming the learned targets
The modulator, which translate block of information symbols into Vsh targets, trained upon completion of the second stage. However, the number of target values suggested by the system is significantly larger than the number of data symbols, it is equal to the number of possible values of the input. As the number of unique targets in- creases, programming operation latency increases, making impractical with the conven- tional programming scheme. Therefore, we propose performing the following two steps:
Quantization of the modulator output, by grouping together close targets to single target.
real data
generated data
DER [a.0.]
2. Expanding the ISPP program scheme, to enable it to program simultaneous- lymultiple, relatively close, targets, us- ing shared pulses mechanism. The proposed scheme preserves the current number of programming pulses and in- troduces solely read operations. As per [22]. the effect of these read operations on the programming latency is deter- mined to be negligible.
[mV]
Figure 6: The real generated BER function of the targets shift. The shaded area marks the standard deviation of the tested WL..
Using these steps, are able program learned targets, while still maintaining a state-of- the-art art programming time. detailed descrip- tion of both steps is given in the supplementary material.
4 Experiments
One of the main goal of the modural-ooulttionn system is to extend the end-of-life work-point of the chip in terms PE cycles and data retention time. Therefore, we conduct our experiments at work-point with high amount of errors, to simulate an EOL scenario.
4.1 GAN channel model experiments
To evaluate the channel model, we first train our eWGAN on a dia read of single block programmed with 15 linearly spread targets (for QLC modulation) over the dynamic range. We then evaluate the

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trained model over a test set which include six blocks. In each test block, we perturb the linearly spread targets {Tārain 1==1 by setting T, T + A where
0
E (1, 6, 15) iE (2, 8,,, 11,14)
A
1
-1
ie e (4,1
for A in {15, 30, 45, 60, 75, 90). The evaluation itself uses two criteria:
1. BER: We compare the real and generated BER of each WL in the block.
2. Histograms: We compare between the histograms generated by our model and those mea- sured on a real chip (i.e. when programming an actual batch of cells to the same target).
The quality of both train and perturbed predicted Bth histograms can be seen in Fig. 7 Specifically, we measure Wasserstein distance of 6 + 2 mV between the real and generated histograms. For comparison, the average Wasserstein distance between two real blocks in the same chip is 6 mV as well. A detailed description of the distance calculation is given in the supplementary materials. In Fig. we compare the real and predicted BER of a QLC block for different target voltages, i.c., values of A. Again, we see that the BER prediction is very good and has error margin of up to 5%. This reassures us we can indeed use the trained model to generate targets from the entire Uty range (including targets it did not train over).
4.2
Neural-modulation experiments
We train the morulalodulltion system as described in Section Table GoooleTssmmnn summarizes the perfor- mance of the model in terms of average block BER at the EOL work-poing We note that not only did the model significantly improve the BER compared to the baseline targets, but it also accurately predicted the BER results via the channel model GAN (see the 'GAN prediction' column of Table [T. Specifically, we pass the modulator targets through the GAN, and use the generated Uza distribution calculate the predicted BER.
Fig. 8 illlsstatte the pulse amplitude modulation (PAM) constellation the modulator learned for a single QLC WL, compared to the original 16 PAM constellation. The modulator found lower targets for cells with higher symbol neighbors. Such scheme consistent with the observation discussed in Section 2.1.4. that the charge lose depends symbols of the cell and its neighbors.
Next, we analyze the model effect as function of the data retention time. We measure the average BER as result of programming with the default and modulated targets, at different time points during the data retention process. Fig. (a) presents the BER reduction of the modulated targets compared to the default targets. We found that the pre-distortion of the targets helps keeping the BER low over
Delault targets
Neural Modulation targets
Target
Figure 8: The original and learned PAM constellations. The first row presents the original targets of the WL which we used for the channel model training. The second row shows the learned by the neural modulator; zoom in symbols 12 and 13 displayed in the bottom row. In agreement with the observation from Section 2.1.4, the modulator found lower targets for cells with higher symbol neighbors, as we saw that such cells tend to lose less charge over time.
8

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Table 1: The BER reduction achieved by the neural modulator. We extract the redaction by calculating the BER after programming the cells once with the targets found by the neural modulator and once with the default targets.
Average
Worst case WL
BPC
GAN prediction
Empirical result
GAN prediction
Empirical result
QLC
16%
17%
8%
9%
TLC
54%
56%
35%
36%
longer retention periods. Interestingly, the pre-distortion slightly deteriorate the BER at short times. Since the BER at these time is overall small, there is no real price for using our modulator.
The ultimate purpose of our modulator to extend the EOL work-poing would, therefore. like to estimate the change in the number of PE cycles before the the memory device reaches its EOL. The EOL. point is determined by threshold BER value above which the data cannot be reconstructed. This information can be extracted from Fig. (b), where we show the BER after a constant retention time as function of PE cycles. We found that the modulator extends the number of PE cycles by 25% (notice that the BER is normalized to its EOL value)
the NAND block. We
5 Conclusions and limitations
In this work, we demonstrated the potential of pre-distorted programming the flash memory device to mitigate errors caused by ICI. We applied state-of-the-art optimization methods for the program- ming Ut targets by performing end-to-end training of the channel's ' modulator and demodulator through pre-trained channel model. To the best of our knowledge, an unsupervised learning based modulation for the flash memory. The importance of our modulator in reducing the BER for the stored information by 56% compared conventional writing schemes, and extending the NAND FOL work point by 25% in terms of PE cycles. Currently, our modulator was optimized for single work-point with a constant read disturb and PE cycles. Future work may generalize the channel model and modulator to overcome this limitation using a dedicated input features. Another drawback is that implementing the modulator in flash controller requires allocating extra write buffers for the neighbors data
work is the first introduce
targets Modulated targets
12
BER rocuction
(a)
Retention time [a.u.]
(b)
PE Cycles [a.u.]
Figure 9: Comparison between the default and modulated targets BERs. Panel (a) shows the model's BER reduction at different time points during the data retention process, measured on QLC flash. The modulated targets BER is higher right after programming the block, and lower along the rest of the retention process due to the effect the ICI on the programmed cells. Panel (b) presents the block's ss BER at different PE cycle workpoints and effective data retention time of one month at room temperature. Programming the block with the modulator generated targets extends the EOL point of the block by 25% in terms of PE cycles, while maintaining the same BER. The shaded area marks the standard deviation of the tested WLs.
Mooeern programming schemes already compromise about the buffer size for increased programming
accuracy p2

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[17] A. Maconi, A. Arreghini, C. Monzio Compagnoni, G. Van den bosch, A. S. Spinelli, J. Van Houdt, and A. I.. Lacaita. Impact of lateral charge migration on the retention per- formance of planar and 3d sonos devices. In 201 Proceedings of the European Solid-Stor Device Research Conference (ESSDERC), pages 195-198, 2011. 2.1.4
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[18] Yixin Luo. Saugata Ghose, Yu Cai, Erich F. Haratsch, and Onur Mutlu. Heatwatch: Improving 3d nand flash memory device reliability by exploiting self-recovery and temperature awareness. In 2018 IEEE International Symposium High Performance Computer Architecture (HPCA), pages 504-517, 2018.
[19] Ian Goodfellow, Jean Pouget-Abadie, Mehdi Mirza, Bing Xu, David Marde-FFrrley, Sherjil Ozair, Aaron Courville, and Yoshua Bengio. Generative adversarial networks, 2014. 2.2
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Martin Arjovsky, Soumith Chintala, and Léon Bottou. Wasserstein gan, 2017. 2.2
[21] Ying Yu, Bingying Tang, Ronglai Lin, Shufa Han, Tang Tang, and Ming Chen. Cwgan: Conditional wasserstein generative adversarial nets for fault data generation. In 2019 IEEE International Conference on Robotics and Biomimetics (ROBIO), pages 2713-2718, 2019, 2.2
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[22] Seungjae Lee et al. A 1Tb 4b/cell 64-stacked-Wi WI 3D NAND flash memory with 12MB/s program throughput. 20/8 IEEE International Solid State Circuits Conference (ISSCC), pages 340-342, 2018.


Reviews:
[{"review_id": "uSFHkdPn27", "reviewer": "Reviewer_yAhR", "summary": "The authors propose a generative model architecture for compensating for errors in NAND flash memory, with the goal of extending flash memory block lifetime. The architecture consists of a GAN and an autoencoder, where the encoder and decoder represent the memory’s modulator and demodulator respectively. The encoder predicts an optimal $v_{th}$ target for a cell, to which the GAN adds noise simulating errors that occur during writing and storage. The decoder then creates a recovered symbol from the perturbed $v_{th}$ value output by the GAN.", "questions": "- We customize the $v_th$ target for a given cell, but assume the neighbors use default target values. Would it not be better for the encoder to predict target values for the entire vector of symbols for the WL, then see how the GAN would distort the WL?\n- If the GAN is trained based on a channel model, how realistic does this model have to be? For instance, should we make a new GAN for each class of flash device, for each operating condition such as varying temperatures, etc.?\n- Section 4.1: Why do you perturb like this? What is the range of the targets?\n- In a real-world application, it would be necessary to run the encoder on each write operation. Does this greatly increase writing latency?", "limitations": "No", "rating": 7, "confidence": 3, "soundness": 3, "presentation": 3, "contribution": 4, "strengths": "-\tMemory lifetime and reliability are very important, and an ML approach to model and counteract memory errors sounds promising. In particular, using a GAN to simulate the errors that occur during storage by taking into account the ICI appears novel and is quite clever. A search returned no prior works on unsupervised ML for flash memory modulation.\n-\tBecause the proposed technique modifies only the writing stage, the reading algorithm does not need to change.\n-\tThe work is well-written and easy to understand, especially in explaining the workings of flash memory.\n-\tThe graphics are useful for summarizing and visualizing the proposed method.\n", "weaknesses": "-\tThough this appears to be the first unsupervised ML approach to flash memory modulation, no reference is provided to similar prior works on ML and flash memory. A quick search returned several, such as \n   - https://ieeexplore.ieee.org/abstract/document/9205258\n   - https://iopscience.iop.org/article/10.35848/1347-4065/aba5e0/meta?casa_token=JMOIMn_8RJoAAAAA:EoRkZ4ZeYNlOcGh22YIgLcWTwCxmrbKxvvZF6sbHY3Blc7Nj93sAeaxFCbLdE1aaBL-CgyWbkGY\n   - https://ieeexplore.ieee.org/abstract/document/9013031?casa_token=YNITahKT5uEAAAAA:f0HrohD0iLmhUh5PhI_lKSk2GL5rNulHxe3dBhO4nnHo_8iTJdO6mp7uIVi0aFcWrEV9bGBPJA\n-\tThe figure references on lines 315 and 322 (for figures 9a and 9b) appear to be switched.\n-\tThe error bars on figure 9a suggest that the difference in retention time between default and modulated targets is not significant.", "quality": null, "clarity": null, "significance": null, "originality": null, "strengths_and_weaknesses": "", "was_revised": false, "final_justification": "", "rebuttal": "Dear reviewer,\n\nThank you for carefully reading our manuscript. We plan to extend the discussion in the revised version to increase the clarity of the paper, incorporate the references and fix the labeling of Fig 9. Specifically, in figure 9a we plot the BER as a function of retention time for several hundred different WL. The curve represents the average BER while the shaded area marks the standard deviation of the test WLs and not an error bar. Indeed, such a plot may not clearly reveal our main achievement. The large overlap between the presented distributions reflects the large variation between the BER of different WLs. As our modulator takes into account the WL index, it assigns optimal targets for each WL. Therefore, it would be better to consider the difference between the BER obtained using the default and modulated targets per WL. We plan to replace the figure with a new one showing the evolution of the BER reduction per WL (the figure is included in the global response PDF).\nWe also attach a set of histograms of this quantity measured at different retention times.\nThe new figures clearly show BER improvement for all WLs after long retention times. It also demonstrates that the pre-distortion slightly deteriorates the BER at short times. As explained in the paper (lines 316-317), since the BER at these times is overall small, there is no real price for using our modulator.\n\nBelow are detailed answers to your questions:\n\nQ: We customize the Vth target for a given cell, but assume the neighbors use default target values. Would it not be better for the encoder to predict target values for the entire vector of symbols for the WL, then see how the GAN would distort the WL?\n\nA: We tested the option of using the predicted target voltages instead of the default values, and found a negligible change to the final targets’ constellation as well as the final BER. For this purpose, we passed the neighbors cell symbols through the modulator before the channel model. We are attaching a figure comparing the target voltages obtained using the two training methods to the global response PDF. \n\nThe modulator converges to a marginally different set of targets because there is an order of magnitude difference between the width of each level programmed using the modulator and the level spacing. In other words, the targets assigned to a specific level are typically separated from the default target by no more than 100mV while the difference between neighboring levels are on the order of thousands of mVs. Consequently, the main effect of the neighboring cells arises from the rough position of their level rather than the precise one.  Since training the neural modulation system with the predicted target voltages of the neighbors takes much longer time and requires additional resources, we decided to implement the simplified model.\n\n\nQ: If the GAN is trained based on a channel model, how realistic does this model have to be? For instance, should we make a new GAN for each class of flash device, for each operating condition such as varying temperatures, etc.?\n\nA: New generations of flash devices frequently introduce significant physical and operational differences compared to their ancestors. Therefore, each generation will likely require a new channel model. By contrast, we can incorporate operational conditions such as temperature into the channel model by generalizing it to include additional parameters. For this purpose, both the channel model and modulator should use these additional parameters as input features during the training stage. Consequently, it would be possible to employ a single channel model and modulator for all such conditions.\n\nQ: Section 4.1: Why do you perturb like this? What is the range of the targets?\n\nA: The perturbation experiment was designed to evaluate the channel model, and to reassure us that the GAN reflects the real NAND channel given out-of-sample sets of targets. Specifically, we choose those perturbations from two main reasons:\n\n1.\tThey produce a non-trivial level shifts where some of the levels get closer while others depart.\nFor example, as shown in Figure 7, levels 1 and 2 depart, while levels 2 and 3 become closer.\n\n2.\tThe chosen values of delta test the model at \"interesting\" parts of the target space, i.e., at targets in which the resulting BER is not too high.\n        \nObviously, there are many other perturbations that would have achieve the same goals. \n\nQ: In a real-world application, it would be necessary to run the encoder on each write operation. Does this greatly increase writing latency?\n\nA: To ensure no additional latency is introduced due to the modulator, the set of targets for WL_n+1 is calculated while WL_n is programmed. Thus, as long as target calculation is not slower than WL programming, it allows for sufficient time to calculate the targets for WL_n+1 before we begin programming it.\n\nThe time it takes to program a single QLC WL is ~2800us. This is because a QLC WL consists of 4 pages, and the time it takes to program a page is ~700us [1]. For every QLC WL, the modulator generates 15X16^2 targets [2]. Consequently, the budget for a single target is ~0.73us, which is equivalent to ~300 clock cycles under an assumption of a HW clock of 400-500Mhz. The cost of a forward pass through the modulator is ~25K multiplication operations (with other operations such as additions and activations adding only a negligible cost). These multiplication operations can be performed in ~200 clock cycles using 128 parallel multipliers – well under our budget.\n\nFinally, implementing the modulator in hardware (the 128 multipliers, as well as other components) requires 40-70K gates. For a typical SSD controller with several million of gates, this added area cost is small.\n\n[1] C. Kim et al., \"A 512-Gb 3-b/Cell 64-Stacked WL 3-D-NAND Flash Memory\"\n\n[2] 16^2 targets are assigned for each level (besides the erase) according to its neighbors.\n"}, {"review_id": "MaokI2hfHO", "reviewer": "Reviewer_KCDD", "summary": "* This paper introduces a unsupervised learning method using GAN for flash memory.", "questions": "* On Figure 7, it does give a view of generated WL from the generated model, is there quantized way to measure the quality?\n* On 3.5, quantization, to what degree to quantize and is there any effect on the overall performance?\n* How much resource does it take to run the modulator? Considering it is to be run on flash controllers.", "limitations": "The authors have discussed the limitation of modulator and channel model.", "rating": 6, "confidence": 2, "soundness": 3, "presentation": 3, "contribution": 3, "strengths": "* The paper is well written and organized, generally easy to follow.\n* To the best of my knowledge, this paper is the first to introduce an unsupervised technique to this kind of problem. \n* The core problem is well formatted. The idea of using a cWGAN as channel model looks interesting and intuitive in section 3.\n* Experimental results look promising, especially on extending storage life. ", "weaknesses": "Please see questions", "quality": null, "clarity": null, "significance": null, "originality": null, "strengths_and_weaknesses": "", "was_revised": false, "final_justification": "", "rebuttal": "Dear reviewer, \n\nWe appreciate your thoughtful engagement with our work and the valuable feedback.\nBelow are detailed answers to your questions:\n\nQ: On Figure 7, it does give a view of generated WL from the generated model, is there quantized way to measure the quality?\n\nA: In the paper we measured the quality of the generated histograms using two different metrics:\n   1. The BER of the generated WL (compared to the real data histograms we read from the flash). This is the most important metric, as it measures almost exactly the quantity that the modulator aims to optimize.\n   2. The 1-Wasserstein distance between the real and generated distributions (see lines 294-298). We measured a 1-Wasserstein distance of 6 ± 2 mV between the real and generated distributions, which is equivalent to the average 1-Wasserstein distance between two real blocks on the same chip. We note that 6 mV is less than 2% of the width of a level.   \n\nQ: On 3.5, quantization, to what degree to quantize and is there any effect on the overall performance?\n\nA: We have tested the change in the overall BER predicted by the model for different choices of level quantization (number of programming targets). The result, presented in Appendix D.2, reveals that the BER decreases as the number of levels increases, as one might expect. Ideally, we would have a set of levels for each cell in the word line. In practice, each target slightly adds to the latency because it requires an additional verify operation. [As explained in the supplementary materials, the latency overhead of performing successive verify operations with close values is small compared to a single verify operation [3]]. Thus, we based our choice of quantization on the tradeoff between the gain and the latency. As implied from Fig. 1, ~90% of the gain is achieved by increasing the number of targets to about 60, i.e., 4 per level (there is an elbow in the quantization loss curve in the vicinity of 60 levels). The latency introduced by multiplying the number of levels by 4 is reasonable for actual implementation, and hence, it is a natural choice. \n\nQ: How much resource does it take to run the modulator? Considering it is to be run on flash controllers.\n\nA: Following is an analysis of the resource consumption of the modulator. \n\nFirst, to ensure no additional latency is introduced due to the modulator, the set of targets for WL_n+1 is calculated while WL_n is programmed. Thus, as long as target calculation is not slower than WL programming, it allows for sufficient time to calculate the targets for WL_n+1 before we begin programming it.\n\nThe time it takes to program a single QLC WL is ~2800us. This is because a QLC WL consists of 4 pages, and the time it takes to program a page is ~700us [1]. For every QLC WL, the modulator generates 15X16^2 targets [2]. Consequently, the budget for a single target is ~0.73us, which is equivalent to ~300 clock cycles under an assumption of a HW clock of 400-500Mhz. The cost of a forward pass through the modulator is ~25K multiplication operations (with other operations such as additions and activations adding only a negligible cost). These multiplication operations can be performed in ~200 clock cycles using 128 parallel multipliers – well under our budget.\n\nFinally, implementing the modulator in hardware (the 128 multipliers, as well as other components) requires 40-70K gates. For a typical SSD controller with several million of gates, this added area cost is small.\n\n[1] C. Kim et al., \"A 512-Gb 3-b/Cell 64-Stacked WL 3-D-NAND Flash Memory,\" in IEEE Journal of Solid-State Circuits, vol. 53, no. 1, pp. 124-133, Jan. 2018, doi: 10.1109/JSSC.2017.2731813.\n\n[2] 16^2 targets are assigned for each level (besides the erase) according to its neighbors.\n\n[3] S. Lee et al., \"A 1Tb 4b/cell 64-stacked-WL 3D NAND flash memory with 12MB/s program throughput,\" 2018 IEEE International Solid - State Circuits Conference - (ISSCC), San Francisco, CA, USA, 2018, pp. 340-342, doi: 10.1109/ISSCC.2018.8310323."}, {"review_id": "mek0rtGu7E", "reviewer": "Reviewer_EdAW", "summary": "This paper presents a novel approach for improving the reliability of NAND flash memory by utilizing unsupervised learning and neural modulation techniques. The authors constructed and trained a neural modulator that reduces programming errors and compensates for data degradation over time. The proposed framework outperforms prior art by up to 56% in raw bit error rate (RBER) and extends the lifetime of the flash memory block by up to 25%.", "questions": "When quantizing the target, how 60 target is decided (in Appendix)? is it the goal to control BER gap within 0.02? Any rationale?", "limitations": "The authors have clearly described the limitations and proposed the next works to tackle.\nNo negative societal impact.", "rating": 6, "confidence": 4, "soundness": 3, "presentation": 3, "contribution": 3, "strengths": "a. Overview:\nThe study proposes a novel approach for modeling and preventing errors in NAND flash memory using generative and unsupervised machine learning methods. The authors utilize a neural modulator that translates information bits into programming operations on each memory cell, reducing programming errors and compensating for data degradation over time. The modulator is based on an auto-encoder architecture with a channel model embedded between the encoder and the decoder. The channel model is constructed using a conditional generative adversarial network (cGAN).\n\nb. Methods:\nThe neural-modulation training procedure consists of two steps. In the first step, a cWGAN based channel model is trained using a set of vth reads of a single block programmed with given targets. The critic is used solely to train the generator and is then discarded. In the second step, the modulator and demodulator are jointly trained. The modulator translates a block of information symbols into vth targets.\n\nc. Experimental results:\nThe trained channel model shows good performance in predicting the bit error rate (BER) and generating accurate histograms. The Wasserstein distance between the real and generated histograms is measured to be 6 ± 2 mV, which is comparable to the average distance between two real blocks in the same chip. The predicted BER has an error margin of up to 5%. The modulator extends the number of program/erase (PE) cycles by 25% before the memory device reaches its end-of-life (EOL) point.", "weaknesses": "The overhead from programming such models is not adequately discussed ", "quality": null, "clarity": null, "significance": null, "originality": null, "strengths_and_weaknesses": "", "was_revised": false, "final_justification": "", "rebuttal": "Dear reviewer,\n\nThank you for carefully reading our manuscript, and pointing out some unclear points.\nSpecifically, we plan to further elaborate on the required resources:\n\nFirst, to ensure no additional latency is introduced due to the modulator, the set of targets for WL_n+1 is calculated while WL_n is programmed. Thus, as long as target calculation is not slower than WL programming, it allows for sufficient time to calculate the targets for WL_n+1 before we begin programming it.\n\nThe time it takes to program a single QLC WL is ~2800us. This is because a QLC WL consists of 4 pages, and the time it takes to program a page is ~700us [1]. For every QLC WL, the modulator generates 15X16^2 targets [2]. Consequently, the budget for a single target is ~0.73us, which is equivalent to ~300 clock cycles under an assumption of a HW clock of 400-500Mhz. The cost of a forward pass through the modulator is ~25K multiplication operations (with other operations such as additions and activations adding only a negligible cost). These multiplication operations can be performed in ~200 clock cycles using 128 parallel multipliers – well under our budget.\n\nFinally, implementing the modulator in hardware (the 128 multipliers, as well as other components) requires 40-70K gates. For a typical SSD controller with several million of gates, this added area cost is small.\n\nBelow are detailed answers to your question:\n\nQ: When quantizing the target, how 60 target is decided (in Appendix)? is it the goal to control BER gap within 0.02? Any rationale?\n\nA: We have tested the change in the overall BER predicted by the model for different choices of level quantization (number of programming targets). The result, presented in Appendix D.2, reveals that the BER decreases as the number of levels increases, as one might expect. Ideally, we would have a set of levels for each cell in the word line. In practice, each target slightly adds to the latency because it requires an additional verify operation. [As explained in the supplementary materials, the latency overhead of performing successive verify operations with close values is small compared to a single verify operation [3]]. Thus, we based our choice of quantization on the tradeoff between the gain and the latency. As implied from Fig. 1, ~90% of the gain is achieved by increasing the number of targets to about 60, i.e., 4 per level (there is an elbow in the quantization loss curve in the vicinity of 60 levels). The latency introduced by multiplying the number of levels by 4 is reasonable for actual implementation, and hence, it is a natural choice. \n\n[1] C. Kim et al., \"A 512-Gb 3-b/Cell 64-Stacked WL 3-D-NAND Flash Memory,\" in IEEE Journal of Solid-State Circuits, vol. 53, no. 1, pp. 124-133, Jan. 2018, doi: 10.1109/JSSC.2017.2731813.\n\n[2] 16^2 targets are assigned for each level (besides the erase) according to its neighbors.\n\n[3] S. Lee et al., \"A 1Tb 4b/cell 64-stacked-WL 3D NAND flash memory with 12MB/s program throughput,\" 2018 IEEE International Solid - State Circuits Conference - (ISSCC), San Francisco, CA, USA, 2018, pp. 340-342, doi: 10.1109/ISSCC.2018.8310323.\n"}, {"review_id": "hiDfWOyz0L", "reviewer": "Reviewer_8xzT", "summary": "The paper introduces a programming method for 3D NAND flash memory. In 3D NAND, data is stored in the voltage level of cells. A cell can typically store a few bits of information (2,3,4 etc). As device density increases, the data is prone to multiple types of errors. The paper is targets two types of errors, those caused by inter-cell interference, and those caused by charge loss in time (retention error). The authors propose a machine learning scheme, based on an auto-encoder architecture with an additional cGAN (conditional generative adversarial network) between the encoder and the decoder. The auto-encoder model has been proposed before for communication systems. The addition of the cGAN is novel, and it is used to model the channel noise. The cGAN is used in order to overcome the fact that the flash channel is non-differentiable. The goal of the scheme is to predict better voltage thresholds for programming (data writing), by taking into account a more informative context for each cell (the value of its neighbors along the vertical channel dimension, and the position in the block). The new model is trained on data coming from on block of NAND and tested on data from 6 other blocks. Experimental evaluation shows a reduction of bit error rate by 56% and an extension of the program-erase cycles", "questions": "1. It seems not clear whether any part of the experimental evaluation was performed on a physical device, or it was simulated. Could you please give some details?\n\n2. It seems that when you move to a new block, the SSL would be a new physical location. I'm wondering if it is useful to include this value in the context. In a similar vein, the ICI in 3D NAND is characterized in various sources, for example the one cited below. As we see there, of the two immediate neighbors in the pillar, the one that was programmed before has small ICI, while the one that will be programmed after has high ICI. Similarly, the neighbors along the logical wordline have significant ICI. Would it help to include this information, perhaps in a weighted fashion in your context?\n\nS. K. Park and J. Moon, \"Characterization of Inter-Cell Interference in 3D NAND Flash Memory,\" in IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 68, no. 3, pp. 1183-1192, March 2021, doi: 10.1109/TCSI.2020.3047484.\n\n3. In a 3D NAND there are potentially thousands of blocks. Do you have a proposal for scaling your scheme, how should the training be performed? ", "limitations": "N/A", "rating": 7, "confidence": 4, "soundness": 3, "presentation": 3, "contribution": 2, "strengths": "The topic is good application of modern machine learning tools the a specific problem of data storage in 3D NAND flash memory. The presentation is very clear, and the paper offers a good amount of details and background about all the components of the scheme.", "weaknesses": "The paper has a very specialized focus, and the techniques that are presented may have limited impact. The experimental assessment is relatively small. ", "quality": null, "clarity": null, "significance": null, "originality": null, "strengths_and_weaknesses": "", "was_revised": false, "final_justification": "", "rebuttal": "Dear reviewer,\n\nWe appreciate your thoughtful feedback on our work. Below are detailed answers to your questions:\n\nQ: It seems not clear whether any part of the experimental evaluation was performed on a physical device, or it was simulated. Could you please give some details?\n\nA: We used data collected from real, currently in mass production, VNAND flash memory chips (TLC as well as QLC) for training and evaluating the model. Thus, while the channel model is generated by the GAN, the calculation of the loss is performed on actual experimental data.\n\nDue to the nature of our model, the data has to be measured at the end-of-life work-point and after long retention time. For this purpose, we perform a series of programming and erase cycles, to wear the block and get to an end-of-life work-point, before starting the data retention period. The long retention period is simulated by heating the device to 100 deg C. The threshold voltage is read with resolution of 20 mV at room temperature.\n\nAs part of the channel model evaluation experiment, we trained our model over data from a single block, and tested our model over six, unseen blocks. Overall, the training set includes several hundred WLs and the testing set several thousand WLs.\n\nQ: It seems that when you move to a new block, the SSL would be a new physical location. I'm wondering if it is useful to include this value in the context. In a similar vein, the ICI in 3D NAND is characterized in various sources, for example the one cited below. As we see there, of the two immediate neighbors in the pillar, the one that was programmed before has small ICI, while the one that will be programmed after has high ICI. Similarly, the neighbors along the logical wordline have significant ICI. Would it help to include this information, perhaps in a weighted fashion in your context?\n\nS. K. Park and J. Moon, \"Characterization of Inter-Cell Interference in 3D NAND Flash Memory,\" in IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 68, no. 3, pp. 1183-1192, March 2021, doi: 10.1109/TCSI.2020.3047484.\n\nA: In the specific NAND devices we work with, the effect of the neighbors along the logical WL on the target cell is negligible compared to the two neighbors along the pillar. Therefore, in our case, the gain of using those neighbors as part of the context vector is very small, while the implementation overhead (in real NAND device) is very high. Generally, adding the WL neighbors to the context of the model is an easy and trivial extension of our work, and can be easily implemented in flash devices in which the inner WL correlations are significant.\n\nIt is important to note that the variation between blocks in the same NAND device are small in our system. In particular, the similarity between the SSLs in different blocks is prominent. The physical location of the block may have a more significant effect on physical properties in other NAND devices. For such system we will have to introduce a new feature which account for the physical location and/or the mapping between the SSL on different blocks. This is possible as long as there is a continuous dependence on location, or, alternatively, as long as blocks can be characterized into a few classes.\n\nQ: In a 3D NAND there are potentially thousands of blocks. Do you have a proposal for scaling your scheme, how should the training be performed?\n\nA: As part of the channel model evaluation experiment, we trained our model over data from a single block, and tested our model over different six blocks. We found that the model predicts the Vth histograms very well both in terms of the BER, and histogram similarity (see lines 285-300). In general, we consistently find that the variation between blocks with similar conditions (such as PE cycles) are relatively small. To scale our scheme for different kind of blocks (such as blocks with High/Low PE cycles) we can extend both the modulator and channel model’s context, to include the PE cycle of the block as an input parameter. Using this extra feature will allow the system to optimize the programming operation for the specific block state."}, {"review_id": "4FVQK4eO5S", "reviewer": "Reviewer_zVdi", "summary": "A neural modulator is proposed and sufficient results are presented.", "questions": "1. What kind of noise added in the figure 1.\n2. Elaborate briefly about the neural modulation comparison with conventional modulation.\n3. Explain the experimental setup.\n", "limitations": "No", "rating": 7, "confidence": 5, "soundness": 2, "presentation": 3, "contribution": 3, "strengths": "Sufficient results are presented.", "weaknesses": "No", "quality": null, "clarity": null, "significance": null, "originality": null, "strengths_and_weaknesses": "", "was_revised": false, "final_justification": "", "rebuttal": "Dear reviewer, \n\nThank you for the time and effort you have dedicated to reviewing our manuscript.\nBelow are detailed answers to your questions:\n\nQ: What kind of noise added in the figure 1.\n\nA: Figure 1 is only an illustration of a real Vth distribution. We used a gaussian noise to generate the levels.\n\n\nQ: Elaborate briefly about the neural modulation comparison with conventional modulation.\n\nA: Conventional modulation schemes assign each memory cell with a Vth target based only on its designated data symbol. Our neural modulation, on the other hand, assigns each cell a Vth target, based both on its data symbol, the WL index, and the data symbols designated to its pillar neighbors. By taking into account the data of the neighbor cells, our proposed modulation preemptively addresses the inter-cell interference (ICI) between adjacent cells in the block. The ICI is one of the main sources of error in flash memory devices, and, therefore, our modulator allows for a significantly lower error-rate at the end-of-life work point.\n\n\nQ: Explain the experimental setup.\n\nA:  The data collected from a real, currently in mass production, VNAND flash memory devices chips (TLC as well as QLC) is used both for training and evaluating the model. Specifically, the experimental data is used for calculating the loss. Due to the nature of our model, the data has to be measured at the end-of-life work-point and after long retention time. For this purpose, we perform a series of programming and erase cycles, to wear the block and get to an end-of-life work-point, before starting the data retention period. The long retention period is simulated by heating the device to 100 deg C. The threshold voltage is read with resolution of 20 mV at room temperature."}]

Author rebuttal:
Dear reviewers, 

Following your feedback, we would like to provide a detailed answer for two specific questions, both have relevant figures in the attached PDF:

Q: We customize the Vth target for a given cell, but assume the neighbors use default target values. Would it not be better for the encoder to predict target values for the entire vector of symbols for the WL, then see how the GAN would distort the WL?

A: We tested the option of using the predicted target voltages instead of the default values, and found a negligible change to the final targets’ constellation as well as the final BER. For this purpose, we passed the neighbors cell symbols through the modulator before the channel model. We are attaching a figure comparing the target voltages obtained using the two training methods to the PDF. 

The modulator converges to a marginally different set of targets because there is an order of magnitude difference between the width of each level programmed using the modulator and the level spacing. In other words, the targets assigned to a specific level are typically separated from the default target by no more than 100mV while the difference between neighboring levels are on the order of thousands of mVs. Consequently, the main effect of the neighboring cells arises from the rough position of their level rather than the precise one.  Since training the neural modulation system with the predicted target voltages of the neighbors takes much longer time and requires additional resources, we decided to implement the simplified model.

Q: The error bars on figure 9a suggest that the difference in retention time between default and modulated targets is not significant.

A: In figure 9a we plot the BER as a function of retention time for several hundred different WL. The curve represents the average BER while the shaded area marks the standard deviation of the test WLs and not an error bar. Indeed, such a plot may not clearly reveal our main achievement. The large overlap between the presented distributions reflects the large variation between the BER of different WLs. As our modulator takes into account the WL index, it assigns optimal targets for each WL. Therefore, it would be better to consider the difference between the BER obtained using the default and modulated targets per WL. We plan to replace the figure with a new one showing the evolution of the BER reduction per WL (see the attached PDF).
We also attach a set of histograms of this quantity measured at different retention times.


Meta-review: This is a paper on reliable data storage in flash memories. A variety of work in error-correcting codes has sought to handle the various specific errors that arise in these devices, but directly modeling the resulting channel tends to be hard.

This paper proposes a generative model to learn the channel, providing the ability to capture far richer error patterns than manually-built models do. 

The basic idea in this paper is simple, but it is well-executed. It joins other papers that show how learned components can provide excellent performance in information theory settings. The reviewers were uniformly positive.
Decision: Accept (poster)