Graph of Circuits with GNN for Exploring the Optimal Design Space
Authors: Aditya Hemant Shahane
Saripilli Venkata Swapna Manjiri
Ankesh Jain
Sandeep Kumar
Venue: NeurIPS 2023 poster (2023)
Keywords: Analog design optimization
Analog synthesis
Graph Neural Networks
EDA
Graph learning
Optimization
TL;DR: A graph-based surrogate model for obtaining most optimal design for Analog circuits

Abstract: The design automation of analog circuits poses significant challenges in terms of the large design space, complex interdependencies between circuit specifications, and resource-intensive simulations. To address these challenges, this paper presents an innovative framework called the Graph of Circuits Explorer (GCX). Leveraging graph structure learning along with graph neural networks, GCX enables the creation of a surrogate model that facilitates efficient exploration of the optimal design space within a semi-supervised learning framework which reduces the need for large labelled datasets. The proposed approach comprises three key stages. First, we learn the geometric representation of circuits and enrich it with technology information to create a comprehensive feature vector. Subsequently, integrating feature-based graph learning with few-shot and zero-shot learning  enhances the generalizability in predictions for unseen circuits. Finally, we introduce two algorithms namely, EASCO and ASTROG which upon integration with GCX optimize the available samples to yield the optimal circuit configuration meeting the designer's criteria. The effectiveness of the proposed approach is demonstrated through simulated performance evaluation of various circuits, using derived parameters in 180nm CMOS technology. Furthermore, the generalizability of the approach is extended to higher-order topologies and different technology nodes such as 65nm and 45nm CMOS process nodes.

Graph of Circuits with GNN for Exploring the Optimal Design Space
Aditya Hemant Shahane'
Swapna Manjiri² Ankesh Jain²
Sandeep Kumar Electrical Engineering
Bharti School of Telecommunication Technology and Management
3 Yardi School of Artificial Intelligence Indian Institute of Technology Delhi
{bsy217530, een212025 ankesh, ksandeep) @iitd. ac. in
Abstract
The design automation of analog circuits poses significant challenges in terms of the large design space, complex interdependencies between circuit specifica- tions, and resource-intensive simulations. To address these challenges, this paper presents an innovative framework called the Graph of Circuits Explorer (GCX). Leveraging graph structure learning along with graph neural networks, GCX en- ables the creation of a surrogate model that facilitates efficient exploration of the optimal design space within a supervsueee learning framework which reduces the need for large labeled datasets. The proposed approach comprises three key stages. First, we learn the geometric representation of circuits and enrich it with technology information to create a comprehensive feature vector. Subsequently, integrating naature-based graph learning with few-shot and zero-shot learning en- hances the generalizability in predictions for unseen circuits. Finally, we introduce two algorithms namely, EASCO and ASTROG which upon integration with GCX optimize the available samples to yield the optimal circuit configuration meeting the designer's 's criteria. The effectiveness of the proposed approach is demonstrated through simulated performance evaluation of various circuits, using derived pa- rameters in 180 nm CMOS technology. Furthermore, the generalizability of the approach is extended to higher-order topologies and different technology nodes such as 65 nm and 45 nm CMOS process nodes.
Introduction
Designing Electronic Design Automation (EDA) tools for analog circuits challenging as it involves optimizing multiple parameters and their non-linear dependencies. Machine learning models increasingly being integrated within EDA tools aiming to make this process flexible and suited for analog design across different circuits and technology nodes. Instead of simulation-basee global optimization [14], which can be time-consuming for stricter requirements [8]. a surrogate-model- assisted optimization approach using less computationally expensive approximation models have been proposed.
Regarding surrogate models, Bayesian optimization and Gaussian process models have been more effective than standard artificial neural networks and radial basis functions. However, Gaussian process modeling is computationally expensive 3 and circuit complexity increases, inter-sample relations become harder to capture, training time increases and generalization ability is lost. To address these challenges, graph-base have emerged as a powerful technique in high-level synthesis, behavior modeling 9., placement
models that integrate Graph neural networks (GNNs) [ 22 17 29)
and routing 20 18 28 [3] analog and mixed-signal layout exploration (25), making them
plausible choice for graph-based surrogate models. Graphs capture both topological and feature- based information, resulting in faster modeling and optimization of complex systems. Despite their
37th Conference on Neural Information Processing Systems (NcurIPS 2023).

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success, graph based methods still require improvement in terms of independence from labeled data and generalization ability across different circuit topologies and technology nodes. For optimization algorithms, previous works have employed reinforcement learning [26]. and evolutionary algorithms [6]. However, the models or policies that are learned via these methods are highly tailored to the environment or the objective of the optimization and lack reproducibility. Another popular method is the particle swarm intelligence [23] however, it easily falls into local optima in the high dimensional space and suffers from low convergence rate.
This paper introduces novel and innovative approach to optimize eircuit design by leveraging graph representation and graph- based semi-supervised learning. The approach is designed to enhance accuracy and efficiency while reducing the reliance on extensive labeled datasets. To achieve this goal, a supervvie learning framework is employed for the graph-baser surrogate model. The accuracy of the approach is compared against the benchmark model ParaGraph [22] and its superior
performance is demonstrated. Additionally, new method is introduced to create comprehensive feature vector that integrates information about various technology nodes and topologies, emphasizing generalizability in zero-shot and few-shot learning frameworks. By integrating these approaches, two new optimization methods on graph-based surrogate models are proposed: Efficient Analog Sizing via Constrained Optimization (EASCO) and Analog Sizing through Real-time Online Graphs (ASTROG). The paper is structured into seven sections, covering graphs, graph graph-based techniques, optimization strategies, the proposed approach, simulation results, and concluding remarks.
2 Related work
Construction of graph- based surrogate model starts with circuit representation as graphs and the creation of a labeled graph dataset. The task is formulated as a graph-level regression problem with each graph mapped to its corresponding label vector (performance metric) using Graph Neural Networks (GNNs).
Graph representation for Analog and Mixed-signal circuits A graph is a data structure used to store semantic information with the help of its unique structure formed using nodes and edges. A graph with features is denoted by G = (V, E, W, Y) where V = {u1, 22 ..... Un is the vertex set, E' C V x V is the edge set and W is the adjacency (weight) matrix. We consider a simple undirected graph without self-loop: Wiy O, if (i,j) E and Waj O, if (i, & E. Finally, X R2xd = [X1, X2.... X,,"' and Y E Raxm [Y1, Y2, Yn!" are the feature matrix and label matrix respectively, where the row vectors X; E I& and Y; E IR" are the feature vector and label vector, respectively associated with one of nodes of the graph The most common approach
Vdd
TM
VCC
Vo
GNN
A
Vis
N
Performa are metric prediction
N
Sar
Vss
Yo
Inverter Schemark
PareGraph
Pre Insining GNNs
Grapph Datacet
Figure 1:
The figure (a) depicts two distinct methods for representing circuits as graph. In 2 circuit
components are depicted as nodes while nets carry edge-based information. To this, [5] suggested explicitly representing device terminals nodes to avoid ambiguity when the device has identical net connections between two or more terminals. Meanwhile, in figure (b), we can see the training framework of ParaGraph [22] method. For the example circuit used, multiple graphs and corresponding label vectors are used for training, and prediction on the unlabeled graph is performed.
for creating a cireuit graph is based on the circuit's topological design. In this approach, circuit components such as resistors, capacitors, and transistors are depicted as nodes, while the circuit wiring (net) mapped using edge-based information that connects different nodes [22]. This approach results in heterogeneous graph that is useful for analyzing and developing complex electronic systems. As a result, a graph-level prediction problem 22 17 arises where we have a set of graphs denoted by {G1, Gg...., ..., G. each with its own set of nodes and edges, a function f which

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maps these graphs to corresponding prediction metric (Y)) where = Let X; be the feature matrix for jth graph where X; E R= where n. is the number of nodes in a single graph and F the features of each node. Overall, the problem of graph-level prediction using GNNs involves learning the function f based on graph structure and node features that map the input graphs to the desired prediction metric. Building upon the previously presented method for representing circuits as graph, [S] proposed a refined approach by explicitly including device terminals as nodes in the graph. This modification results in featureless edges.
While this approach offers a detailed understanding of the interconnection between different cir- cuit components, it suffers from several limitations: (i) As the circuit size increases, the graph becomes densely interconnected, leading to a large number of nodes and edges, making it challenging to comprehend the overall behavior of the circuit. (ii) Creating large labeled graph dataset is iime-consuming and computationally expensive, which hinders effective GNN training. (iii This framework lacks inter-graph connections, which reduces its reliability. (iv) Since graph regression problems cannot be applied to semi-supervised frameworks, the reliance on labeled datasets is in- evitable. (v) Additionally, training and validating over multiple graphs (n) with N nodes and E edges when passed through L layer GNN makes the process slow, and the high time-comeee tie-compllxit (O(n* LN² and caape-comyy (O(n N2L)) further adds to the computational burden. (vi) Finally, transferring knowledge across different topologies becomes challenging due to varying graph sizes.
3 Proposed Formulation and Background
For our case, consider number of circuit instances indexed as i I,.... ,, where X, RRd be the feature vector and Y; E R the label vector corresponding to i-th circuit. A feature vector X; contains the circuit-level parameters e.g. resistance, capacitance, transistor widths, lengths, junction voltages etc and the corresponding label vector Y; contains performance parameters, including Gain, Bandwidth, Noise, etc. The problem under consideration
Given n =1 =l+ u circuit instances and their parameters X = (X1, X.) along with labels of only I number of circuit instances as Yi, how can we predict the labels of the remaining u number of circuit instances Yu?
The circuit performance parameters or the labels Y, are generally obtained using expensive SPICE simulation, thus having a large set of labeled data is a luxury. Limited labeled data where < u is a significant hurdle in learning models for EDA. Graph-based Semi-supervise learning attempts to address this by learning from both labeled as well as unlabeled data.
Consider sets Ti = {(X,, YOH E X x y and T. = {((x)) E X. where X' is the domain set and Y is the label set. Suppose the elements of the set Ti be sampled from probability distribution P over the ordered pair X x y. Samples of the domain set X; E X will follow the marginal distribution Fx of IP. For the limited labeled data scenario, the goal of learning algorithm is to estimate conditional distribution XX) using both the labeled and unlabeled data as the training data. To incorporate the additional information of Pxx obtained because of the unlabeled data by capturing the intrinsic geometry of the marginal distribution through the graph of both unlabeled and labeled data and performing label propagation and feature aggregation over the neighborhood. The guiding principle is that if two data points from the domain set are close in the intrinsic distribution 1xx then the corresponding conditional distributions should be similar. For the circuit prediction, it means that given two circuit instances with similar features X; ~ Xj then the corresponding label vectors should also be similar Y Yy-
To build a learning framework based on the above guiding principle, these are the two main steps i) First use the feature space to obtain geometric representation such that the samples having similar features are represented closer and connected ii) Build a learning model such that geometric information be leveraged for learning the labels of unknown samples.
3.1 Proposed Framework for Semi-Supervised Learning on Graph of Circuits
We introduce graph-based semi-supervised learning technique for building a surrogate model (GCX) for analog circuit simulation with limited labels. The proposed framework consists of four main stages: i) Firstly for obtaining feature-aware geometrical representation we construct graph of circuits using circuit features X (Xi, X.) in the form of an adjacency matrix A, where each circuit
3

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i is a node of the graph and the cireuit-level parameters, such as resistance, capacitance, transistor widths and lengths, and junction voltages, as its corresponding feature vector X; R ii) Further using the graph adjacency matrix, feature matrix, and available set of circuit performance matrix together, i.e., G(X, A, Yi) with the graph neural network pipeline to build a machine learning model, iii) Constructing a comprehensive feature vector that facilitates generalizabilltyddsscnn predicting the performance parameters Y, corresponding to Xys. Fig illustrates the outline of the proposed framework:
later), iv)
W2
12
Yo
14
02
05
GNN
1,5
05
64
D= (X: X; X2)
G(V, E, W. X.,, X
G.V,E,,,X,Y
Figure 2: Graph of Circuits Explorer (GCX): The original dataset (D) contains both labeled (X,.i) and unlabeled (X..) samples, each circuit is a node of the graph and sample as the feature vector of the associated node that will serve nodes in the graph: the graph is learned (weighted adjacency- W) using the suggested formulation; and the learned graph passed through GNN model for label prediction for unlaheled nodes. This forms GCX(GNN) surrogate model. For the above circuit X = (Vaa. W1, L1, W2, L.2, Von) and Yi: = Vo.
Algorithm GCX(GNNN
Input: Feature matrix (Xt, Xu), label matrix (Yr) Output: Optimal design (X;)
1. G (V, E, W)+ - Learning Graph of Circuits Using (X1, X.)
2. Yu < Label prediction of unlabeled circuits using GNN with G(V, E, W, X,, Xu, Y));
3. GCX(GNN) + G (V, E, W, X,,, X1, Yi) GNN; surrogate model
4. Xi < GCX(GNN) + EASCO/ASTROG
Algorithm 1, which we denote by GCX(GNN), summarizes the outline of the proposed framework. The implementation details of each step are discussed subsequently.
This approach allows us to incorporate multiple circuit instances into single graph while accom- modating different technology nodes and topological diversity. We achieve this while maintaining a homogeneous graph with node feature vectors of equal lengths, making the training of GNNs in a semi-supervised framework efficient and cost-effective. Compared to the previous approach that handles circuits as graphs, our approach with N nodes in graph with E edges when passes through L layer GNN has an overall time complexity of O [L. E) and space complexity of O (N)..).
3.2 How to Learn Graph of Circuits to Encode Circuit Similarity
Consider the feature matrix of circuit instances X = X2, Xx,"' where X; is the feature of 7th circuit which corresponds to ith node of graph. In the context of modeling signals or features with graphs, the widely used assumption that the signal residing on the graph changes smoothly between connected nodes [10]. For example, if two circuit instances X, and X, have similar features then their Euclidean distance |X X2,1² 11 should be smaller but connecting edge weight which quantifies similarity i.e. Way should be large. The Dirichlet energy (DE) is used for quantifying the smoothness of the graph signals which is defined as:
DE
Σ 1.J
wi
|X,
X11
2
The lower value of Dirichlet energy indicates a desirable configuration 31 10
Smooth graph signal
methods are an extremely popular family of approaches for variety of applications in machine learning and related domains [12 [0]. In order to build graph of circuits we will use the smoothness

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of signals on graph assumption. Nodes connected with stronger weights indicate similar features and performance indices, facilitating knowledge transfer new circuit instances. Finally, we learn weighted adjacency matrix W by minimizing the Dirichlet energy combined with other sparsity regularization terms which entails solving the following optimization problem:
SEw why |X, 1,,1- al log (Sw) f|
= arg min WC Wm 2
where 0 and 3 controlling the properties of the resultant graph, / ensures the graph is sparse, while 1 log (Sw) ensures that every node will have some connections. This problem is convex optimization problem and efficiently solvable [2 [0].
3.3 Comprehensive feature vector representation for GCX
To streamline GNN training across various technology nodes and topologies, we extend the initial feature vector with one-hot encoded bits, specifically allocated for the technology file and topology. This augmentation generates a new feature vector that facilitates relevant pattern learning by the GNN. This approach significantly reduces computational costs, making it more viable for practical applications. With this trained GNN model, it becomes possible to accurately predict the performance of circuits that are yet to be seen, thereby enhancing circuit design and optimization. Further information about proposed method is available in Figure
L1
W2
12
C
VISI
W1
122
12
VIM
0
35
120
65 am, 45mm
stage
King Uscillator 180mm, 3-stage
Ring Oscillator
To enhance the feature vector, we append with one-hot encoded technology files and circuit topology details, resulting in new feature vector. The technology files used, 180nm, 65nm, and 45nm, are represented using. 3 bits. To represent the original and higher-order topology, bits are used, with an additional & bits assigned for circuit element features. The first figure shows the ring oscillator implemented with the 65mm technology file, while the second figure displays the S-stage topology of the circuit.
Figure 3: Knowledge Transfer:
3.4 Graph Circuit Explorer- Graph Neural Networks: GCX(GNN) surrogate model
VAl
Vil
Vd
M6
M8
M1
M3
MM5
M1
M2
C1
Nn
Message passing in GNNs
Graph of circuits
Label propagation
M4
M5
Graph is passed through the GNN architecture; nodes interact with each other via message passing and feature aggregation for target node carried out. Unlabeled nodes gather information from labeled neighborhood in form embeddings. Embeddings updated over layers is used for label prediction. To better understand GNN architectures, refer: [I]] [7]] Mcanwhile, in figure (b), we can see schematics of (i) Two-stage OTA with Miller Compensation and (ii) Three stage Ring Oscillator on which the algorithms will be implemented.
Figure 4: The figure (a) depicts message passing in GNNs:
After learning a graph using the feature vector description provided, the graph undergoes label propagation through the GNN architecture. In this process, each node represents a circuit instance and the graph consists of both labeled and unlabeled nodes. During each layer of the GNN, the nodes interact through message passing, and feature aggregation is carried out. The unlabeled eircuit instance acquires information from its labeled neighbors in the form of embeddings. The embeddings
5

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are iteratively updated across the L layers of the GNN, ultimately leading to the prediction of label for the unlabeled circuit instance (node). The formulation for the embedding update can be understood from the equation given below. The process can be understood from Fig:4
Wi + W-(A)
Σ VEN.
h + B(A)
neigh
ha (k-1) E Rdd Node embeddings of target node at layer k. W(() w.(k neigh E Rddl)
self' :
are the learnable parameters, 5(4) E Rd represents the bias term and σ: represents elementwise non-linearity (e.g., a tanh or ReLU). GCX, the approach of creating a graph of circuits, seamlessly integrates with any GNN architecture, showcasing its flexibility across circuits and architectures. Extensive experiments provide conclusive evidence of its effectiveness.
4 Efficient Analog Sizing via Constrained Optimization (GCX-EASCO)
Optiral design parmele
Var
M..
Mi
GNN
M,
D Xx, G(V, E,W,E,WAR X,,, XIXI
G(V. E, XYY
D - (X:1) X (W1, W
VoD)
Figure 5: GCX-EASCO algorithm: Initially points are uniformly sampled and labels are generated based on the value of I: graph G (V, E, W.....; X1, Yi) is learned using all the points based on features; GNNs in semi-supervised framework learn the embeddings corresponding to labeled samples, which are used for label prediction corresponding to unlabeled nodes (V, E, W, X, Y). Ultimately, constrained optimization over the subset D of the original dataset gives optimum parameters X;
Our new algorithm employs more efficient graph-based surrogate model to obtain optimal circuit parameters. The algorithm uses a static, offline training framework that has been recommended in The algorithmic flow is described in Fig:5 and the following is the step-by-step overview:
15 16
The EASCO algorithm consists of four main components. Firstly, in the data generation phase, n points are uniformly sampled from d-dimensional feature space such that X; E [u,, bi] where a; and b, are the lower bound (LB) and upper bound (UB) for each feature. This creates a dataset (D) such that D E Ra Next, a graph is learned (as previously discussed) using all the sampled points, with a subset of these points simulated under different labeled data settings (l), such as 30%, and 50%, by adopting
supervise learning framework. The labeled points, Xtrain E Ixd are used for training, while the rest, Xtest xn= are reserved for testing. In the third component, GNN models [ 7 (27) are used to make predictions. Lastly, in the constrained optimization component, uniform sampling and integration with label propagation over unlabeled samples offer an overall comprehension the fearur)(search) space. With constraints in place, the process returns a subset of
the original search space D e gkxd where ks << n. The objective function is optimized using Differential Evolution (DE) algorithm applied to the resulting parameter space, yielding the most optimal parameters.
5 Analog Sizing Through Real-time Online Graphs (GCX-ASTROG)
The previous algorithm efficiently minimized simulations once coarse boundaries were established. However, handling an increasing number of specifications made challenging to identify these boundaries. To overcome this, we developed an online training version of the algorithm that requires minimal initial data. utilizes an optimization algorithm, a surrogate model, and an infill sampling criterion 21 to guide the search towards global optima. The algorithm updates iteratively and provides the optimal circuit design parameters upon meeting the stopping criterion. Our adoption of the ranking criterion from 2 ensures consideration of all constraints and enables precise approach

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per proparatinn
rankung
Demrioo J
the poNnts
Label graerated from CNN
D(X,Y)
E, W,, X,,
D(
Figure 6: GCX-ASTROG algorithm: The process starts with sampling and labeling a small set of points (a). A novel sampling criterion guides the algorithm towards a specific feature space region. The top X points create a population (P) for the DE algorithm, generating m unlabeled points at every iteration of ASTROG. A semi-supervised learning framework uses À + points learn graph G (V, E, X.. X,, Yi). A pre-trained GNN propagates labels over the m points each iteration. The best solution is integrated into the original dataset, and the process continues until the iteration budget met.
to achieving optimal design outcomes. See Fig. 6 for the algorithm flow, and the step-by-ster overview is as follows:
Initially, dataset (D) is generated with a samples such that D E Roxd The initial dataset is created using SPICE simulations within the bounds, denoted as aj and by for each design metric. Stopping criteria are predefined, and the optimal design is outputted if these criteria are met; otherwise, the process moves to the next step. In step three, all designs the database are ranked using the adopted
infill sampling criterion (2). and the À best designs are selected. New bounds X, = (ā,, 6,] are obtained based on these designs, where X, E RAxd, The Differential Evolution (DE) algorithm 4 is used to optimize the objective function by generating m child solutions from the population within the newly obtained bounds. Next, a graph is learned (with the previously discussed approach) by combining the features of best À labeled points with the unlabeled points obtained from the DE algorithm. The obtained graph is passed through the pre- pre-trained GNN models and labels are predicted for the m unlabeled nodes. After the label prediction, the À + m labeled points re-ranked using the infill sampling criterion (2). The optimal design and its corresponding performance metric (label) then selected from the m labeled points and incorporated into the original database. This process is repeated until the predetermined iteration budget for each circuit is exhausted.
6 Experiments
In this section, we showcase the experimental results of our two proposed algorithms: EASCO and ASTROG. To evaluate the effectiveness of these algorithms, we chose Two-stage OTA with Miller Compensation which is operating mostly in linear region, and the Ring Oscillator (Three-stage) which is operating mostly in nonlinear region as our test cases. The Miller Compensated OTA has 11 design variables, while the Ring Oscillator has 6 design variables. The performance evaluation of our algorithms was conducted using multiple metrics, which will be discussed in detail later. Our experimental workflow comprises four stages. We initiate with comprehensive description of dataset generation using SPICE simulation and subsequently provide an exhaustive analysis of the algorithm's 's operational efficiency.
6.1 Harnessing EDA tools- SPICE simulator for Dataset generation
We have considered two test cases belonging to different families of circuits: Amplifiers and Oscillators. Design space bounds, Performance metrics and Specifications carefully considered after designer's recommendation (mentioned subsequently). Features (design space points) X = (Xu, X1) are generated by uniformly sampling points across the dddimensional space forming matrix of size X E R Since employ semi-supervised learning we simulate labels corresponding to only samples where I << n (samples are randomly chosen to avoid bias). The dataset obtained is (X,, X., Yi).
Two-stage Miller Compensated OTA: Design parameters (X,) are: Reference current (Tre,)
Reference Voltage (Vaa), Transistor widths and length (Wi-s, Ls-s), Capacitance (Ces Ct.) and load resistance (r1). Performance metries (Y,) are Gain, Unity Gain Bandwidth (UGB), Gain Margin (GM), Phase Margin (PM), Noise and Power.
7

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Three-stage Ring Oscillator: Design parameters (X2) are: Reference Voltage (Vaa), Transistor widths and length (, 2 and Capacitance (C₁). Performance metries (Y₁) are: Frequency, rms Jitter, Delay and Power.
6.2 Performance evaluation of GCX surrogate model
To evaluate the efficacy of our proposed approach of learning graph of circuits, we conducted tests by
integrating it with various GNN architectures [ 7 27 For each test case we learned a graph with n = Ik nodes and training was performed under different labeled data settings, with being set to 30% and 50%. We compared the results of our proposed node-level regression approach with benchmark method ParaGraph [22]. which is graph-level regression setting, and ESSAB [2], a novel two-layer neural network for regression. The methods used for comparison do not facilitate semi-supervised learning hence experimental setup was adopted as in mentioned in [2 2]
We implemented the graph formation technique described in ParaGraph 22 for selected test cases. We established a graph level regression problem consisting of 15k graphs along with their corresponding label vectors. Additionally, we constructed GNN architecture outlined in the paper. However, during experimentation, we observed that the resulting It² scores were predominantly negative. Consequently, we opted not to showcase the results for the surrogate model. We attribute this failure to two main factors: (i) The scarcity of node and edge features specific to the circuit under study. The ParaGraph [22] method was initially designed for industrial circuits with longer feature vectors, which might have impacted the performance on our dataset. (ii) The limited number of graphs available for training. Although the training loss initially decreased, quickly reached saturation, leading to ambiguous predictions. Considering these factors, we believe that a more comprehensive feature set and larger training dataset would be necessary to achieve more accurate results with the proposed approach.
We utilized the ESSAB surrogate model with dataset of 1K labeled samples. To ensure consistency in training conditions, we maintained a 50% training-to-testing ratio, similar to our approach.
Miller Compensated Two-stage OTA (Rt scores)
GCX()
Gain (dB)
UGB (MH2)
GM
(dB)
PM (deg)
Noise (cV)
Power ( (WW)
1=30%
[-50%
1=30%
1=50%
[=309
I=50%
I=30%
[=508
1=30%
(=90%
I=10%
I=50%
(GCN)
0.17
0.22
0.36
0.43
0.52
0.81
0.70
0.81
0.35
0.64
0.42
0.61
(SAGE)
0.42
0.60
0.43
0.60
0.89
0.91
0.93
0.94
0.96
0.97
0.97
0.99
(GAT)
0.19
0.41
0.33
0.41
0.89
0.91
0.79
0.85
0.41
0.61
0.60
0.71
Table 1: /t2 scores with different GNN architectures (Included value is the mean, averaged across 5 runs)
Three-stage Ring Oscillator (H² scores)
GCX()
Frequency (Ma
Delay (uS)
Power (pW)
1=30%
I=50%
1=30%
1=50%
I=30%
1=50%
(GCN)
0.30
0.44
0.28
0.55
0.35
0.63
(SAGE)
0.45
0.83
0.56
0.82
0.84
0.91
(GAT)
0.41
0.50
0.34
0.58
0.36
0.58
Table 2: R² scores with different GNN architectures (Included value the mean, averaged across 5 runs)
Model
Nosse
Prequency
Delay
GCX/SAGE)
0.60
0.60
0.94
0.97
0.99
0.83
0.91
ESSAB 2
0.57
0.50
0.81
0.93
0.89
0.39
0.89
0.71
0.88
Table 3: Rt scores comparison between our best model GCX(SAGE) and ESSAB
2 surrogate model.
Our proposed approach, based on the semi-supervised learning framework, outperforms competing methods even when provided with minimal labeled data. We demonstrate the flexibility of our approach by evaluating it on two test cases representing different classes of circuits. Furthermore, we obtain a highly accurate graph-based surrogate model that will be utilized in the subsequent algorithms proposed in this work. Results of our approach are presented in Tables: ,,233 respectively.
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6.3 Comparative analysis between different Optimization strategies
Our approach involves first obtaining a highly accurate surrogate model, which we subsequently employ in two algorithms, discussed carlier, to determine the optimal parameters for the given design problem. To evaluate the efficacy of our proposed algorithms, we compare them against two benchmark optimization methods the DE algorithm [24] and the BO-EI algorithm proposed in [. To ensure reproducibility, we run each algorithm ten times. We then solve a single objective constrained optimization problem, based on the designer's 's recommendations, for each circuit, and report the obtained results. We selected the Figure of Merit (FOM) as the objectíve function to be minimized in our study. To define the FOM, we extensively reviewed the literature [19 30 and derived a customized expression that aligns with our specific requirements. Further details regarding the formulation of this FOM can be found in the supplementary materials. The FOM expression we developed effectively balances the trade-off between different specifications, enabling us to optimize the input parameters for the given test cases. The best-case results are depicted in blue, while the second- best results are highlighted in black.
Miller Compensated Two-stage OTA (Optimization)
Objective: Minimize FOM al. Gain > 50 dB ; UGB > 100 Mhs; PM
45 deg: GM
15 ; Power < 900 W Noise < 600 Weems
Model
Gain (dB)
UGB (MH)
GM
((B)
PM
(deg)
Noise (vV)
Power (aW)
Success
(specs)
Max
Min
Max
Min
Max
Min
Max
Min
Max
Min
Max
Min
(out of 10)
DE [24]
58.6
53.3
190
165
19.2
17.8
46.7
45.0
478
463
815
633
04/10
BO-EI[]
68.3
65.6
225
190
18.9
17.8
52.0
45.6
470
462
627
505
03/10
EASCO
67.3
64.4
215
192
19.2
18.5
47.2
45.5
470
462
722
490
04/10
ASTROG
80
61.6
145
106
26
23.5
52.5
47.9
497
446
716
318
06/10
Table 4: Comparison table for different optimization strategies [ with EASCO and ASTROG
ASTROG stands out as the undisputed champion among all competing algorithms. The convergence speed achieved by ASTROG is approximately 8x faster compared to the BO-EI algorithm (.. The results are shown in Table:4.
Three-stage Ring Oscillator (Optimization)
Objective: Minimize FOM Freq
1000 Milz Jitter
p0 Delay
200 pS: Power W/
Model
Frequency (MH))
litter(s)
Delay
Power
Success
(specs)
Max
Min
Max
Min
Max
Min
Max
Min
(oast of 10)
DE [24]
1265
1005
5.07
0.99
165
131
302
256
02/10
BO-EI[II
2103
1047
2.73
10
159
79
407
66.4
06/10
EASCO
1444
1396
1.7
10
119
115
360
331
09/10
ASTROG
2033
1175
6.05
0.2
141
81.9
502
182
04/10
Table 5: Comparison table for different optimization strategies
24
with EASCO and ASTROG
Among the competing algorithms, BO-EI proved to be a formidable rival for our proposed algorithms. Although EASCO maintained its higher rank in terms of reproducibility, ASTROG delivered the second best results. However, the key factor in determining the champion algorithm lies in the speed of convergence towards the optimal value. In this regard, ASTROG's s impressive 4x faster convergence clearly establishes it as the ultimate winner. The results are as shown in Table:5. For a comprehensive analysis of the timing results for each algorithm, please refer to the supplementary materials.
6.4 Knowledge Transfer using Zero-shot and Few-shot learning
To broaden the scope of our approach, we incorporated different technology nodes and topologies into our study. We selected a Three-stage ring oscillator as our initial test case and implemented the procedure for creating a comprehensive feature vector. We specifically focused on conducting few- shot (FS) learning experiments using 180 nm technology nodes. We then assessed the generalization of the trained model to 65 nm technology nodes and five-stage topology. Additionally, we performed zero-shot (ZS) learning experiments using 45 nm technology nodes. This allowed us to evaluate the model's 's performance without any prior training on the specific technology node.

---

Ring Oscillator (Three and Five-stage, 180 nm, nm, 45 nm)
Model
3-S,FS
3-S.Z8
3105-S,FS
3to5-S,ZS
(65 nm)
(45 nm)
(65 nm)
(45 nm)
/=30%
(=0%
(=30%
t=0%
SAGE
0.41
0.09
0.28
0.04
Table Few-shot and Zero-shot generalization technology and topology
In our experimental setup, we focused on utilizing limited number of labeled samples to address the challenge computational burden associated with generating labeled data. We considered total Ik labeled samples and evaluated the performance based the percentage of data (l) representing the infusion of technologytopology information for both few-shot and zero-shot Icarning. Given the constraints on labeled data availability, zero-shot learning was found to be ineffective in achieving satisfactory performance. However, there was some promising progress observed with few-shot learning, which indicates the potential of utilizing small amount of labeled data enhance the learning process.
7 Conclusion
Our new method for creating graph of circuits produced a consistent, homogeneous graph that be used across multiple circuits. This approach lead to accurate surrogate model with computationally inexpensive node-level regression problem. By utilizing semi-supervised learning algorithms, we significantly reduced reliance on labeled datasets. The proposed GCX(GNN) surrogate model was further incorporated into EASCO and ASTROG. For the above mentioned test cases these algorithms outperformed the competing state-of-the-art optimization methods and yielded the most optimal design parameters that precisely meets the designer's criteria.
8 Acknowledgements
We extend our gratitude the reviewers for their valuable comments and insightful suggestions. which have significantly enhanced the quality of this paper. We also appreciate the contributions of the entire MISN lab community for their engaging discussions related this work. Our research has been made possible through the support of the DST Inspire faculty grant M102322G.
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12


Reviews:
[{"review_id": "4KCb4zxarF", "reviewer": "Reviewer_LVTs", "summary": "The design automation of analog circuits poses significant challenges in terms of the large design space, complex interdependencies between circuit specifications, and resource-intensive simulations. To address these challenges, this paper presents an innovative framework called the Graph of Circuits Explorer. GCX enables the creation of a surrogate model that facilitates efficient exploration of the optimal design space within a semi-supervised learning framework which reduces the need for large labelled datasets. The proposed approach comprises three key stages. The effectiveness of the proposed approach is demonstrated through simulated performance evaluation of various circuits, using derived parameters in 180 nm CMOS technology. Furthermore, the generalizability of the approach is extended to higher-order topologies and different technology nodes such as 65 nm and 45 nm CMOS process nodes.", "questions": "as written in Weaknesses", "limitations": "as written in Weaknesses", "rating": 5, "confidence": 3, "soundness": 3, "presentation": 2, "contribution": 2, "strengths": "- This paper introduces a novel and innovative approach to optimize circuit design by leveraging graph representation and graph-based semi-supervised learning. The approach is designed to enhance accuracy and efficiency while reducing the reliance on extensive labelled datasets. \n- To achieve this goal, a semi-supervised learning framework is employed for the graph-based surrogate model. a new method is introduced to create a comprehensive feature vector that integrates information about various technology nodes and topologies, emphasizing generalizability in zero-shot and few-shot learning frameworks. By integrating these approaches, two new optimization methods on graph-based surrogate models are proposed: Efficient Analog Sizing via Constrained Optimization (EASCO) and Analog Sizing through Real-time Online Graphs (ASTROG).\n", "weaknesses": "- This paper leverage a GNN,  more experiences about how to extract the feature need to be performed, such as transformer \n- The process of training is not claimed clearly, the paper claims that \"Semi-Supervised Learning on Graph of Circuits\", More details need to be added. such as the process of Semi-Supervised Learning. \n- How to define the node weights of a graph? when training process, does the relation between two nodes is neccessary for training?\n-\"Stopping criteria are predefined, and the optimal design is outputted if these criteria are met; otherwise, the process moves to the next step.\", the definition of \"Stopping criteria\" is not claimed clearly.\n- the details of dataset is not claimed clearly.\n- \"Given the constraints on labelled data availability, zero-shot learning was found to be ineffective in achieving satisfactory performance. However, there was some promising progress observed with few-shot learning, which indicates the potential of utilizing a small amount of labelled data to enhance the learning process.\" more details and analysis need to be provided", "quality": null, "clarity": null, "significance": null, "originality": null, "strengths_and_weaknesses": "", "was_revised": false, "final_justification": "", "rebuttal": "**W1**: Thanks for the feedback. We tried experimenting with Graph Transformer architecture across different performance metrics with appropriate hyper-parameter tuning. The loss function shows a swift decline  however the obtained $R^2$ scores are very poor. \nWith our current time constraints in mind, our focus remains on investigating the implementation details to better understand the underlying factors influencing our outcomes.\n\n**W2**: Thanks for raising the concern. We hope the following discussion provides a more detailed description: \n(1) Start by generating a detailed dataset (details described in W4) and $l$ labels are simulated to corresponding samples, where $l << n$. (2) Subsequent step is creation of a graph comprised of circuit instances, denoted as $X=(X_l, X_u)$; represented as a weighted adjacency matrix ($W$).(3) Within this graph, each circuit instance $i$ corresponds to a node. Corresponding circuit-level parameters form a feature vector $(X_i \\in \\mathbb{R}^{k})$.(4) Termed as the Graph of Circuits Explorer (GCX), this graph, $G(V,E,W,X_u,X_l,Y_l)$, is seamlessly integrated with Graph Neural Networks (GNNs) to facilitate label propagation across unlabeled samples. (5) Semi-supervised learning framework of GNNs accurately learn the underlying graph function while constraining loss computation solely to the available labeled samples. (6) We employ label propagation—on performance metrics such as Gain, UGB, GM,  PM etc—across unlabeled circuit instances ($|X_u|$-nodes).(7) We have  two distinct labeled data scenarios, specifically $p= 30\\\\%$ and $p=50\\\\%$ , for training the Graph Neural Networks (GNNs).\n\n **W3**: **Node weights in a graph**: Thanks for raising the concern. The weights assigned to nodes in a graph are obtained based on the proximity of design parameters among different circuit instances. When the Euclidean distance between these design parameters is minimal, the corresponding instances are assigned higher edge weights.  This leads to more pronounced connections between circuit instances that share similar design parameters within a $d$-dimensional space, in contrast to  instances characterized by distinct parameters. The resulting node weights are derived as a weighted adjacency matrix, achieved through the resolution of an optimization formulation outlined in the paper.\n\n**Significance of node weights**: \n(1) **Sparsity in graph**- Computational time reduces during training, over-smoothing problem can be controlled.\n(2)**Identifying prominent neighbors**- Edge weights help to get rid of unnecessary connection of the node. Information via message passing is obtained only through important neighbors.\n\n**Stopping criteria**: For both the test cases we exclusively define our objective function as Figure of Merit (FOM). Details about FOM can be found in the supplementary material. \nStopping criteria is achieved when optimum value of FOM is reached i.e $[ (FOM)_n - (FOM)_{n-1} ] \\leq \\epsilon$ where $n$ is the number of iterations  in both EASCO and ASTROG algorithms. Each algorithm is run TEN times to ensure reproducibility (specifications are satisfied). \n\n**W4**: Thanks for raising the concern.  Design space bounds, Performance metrics and Specifications are carefully considered after designer's recommendation (mentioned in experiment section). Features (design space points) $X = (X_u, X_l)$ are generated by uniformly sampling points across the $d$-dimensional space forming a matrix of size $X \\in \\mathbb{R}^{n \\times d}$ . Since we employ semi-supervised learning we simulate  labels corresponding to only $l$ samples where $l << n$ (samples are randomly chosen to avoid bias). The dataset obtained is : $(X_l,X_u,Y_l)$. Refer table for better understanding:\n\n| Samples | Design parameters | Performance metrics |\n|---------|-------------------|--------------------|\n| 1       | $X_1$             | $Y_1$              |\n| 2       | $X_2$             | $Y_2$              |\n| -       | -                 | -                  |\n| $l$     | $X_l$             | $Y_l$              |\n| $l+1$   | $X_{l+1}$         | $\\times$           |\n| -       | -                 | -                  |\n| $n$     | $X_n$             | $\\times$           |\n**Sample Distribution**: $X_{1-l}, Y_{1-l}$ corresponds to labeled samples; Samples from $X_{(l+1)-n}$ constitute $X_u$ unlabeled samples.\nTwo-stage Miller Compensated OTA: Design parameters ($X_i$) are: Reference current ($I_{ref}$), Reference Voltage ($V_{dd}$), Transistor widths and length ($W_{1-8}, L_{1-8})$, Capacitance ($C_c,C_L$) and load resistance ($r_L)$. Performance metrics ($Y_i$) are : Gain, UGB, GM,PM, Noise, Power.\n\nThree-stage Ring Oscillator: Design parameters ($X_i$) are: Reference Voltage ($V_{dd}$), Transistor widths and length ($W_{1,2}, L_{1,2})$ and Capacitance ($C_1$). Performance metrics ($Y_i$) are: Frequency, rms Jitter, Delay, Power.\n\n**W5**: Thanks for raising the  concern. We performed two set of experiments with $p$= 350 and  450 labeled samples for technology nodes $65\\,nm$ and $45\\,nm$ with $180\\,nm$\nTechnology transfer: $180\\,nm \\rightarrow 65\\,nm$ and $45\\, nm$ for 3-stage.\nTechnology + Topology transfer: $180\\,nm \\rightarrow 65\\,nm$ and $45\\, nm$ from 3-stage to 5-stage.\n| Model GCX(SAGE) | 3-S,FS (65,45nm) $p$=350 | 3-S,FS (65,45nm) $p$=450 | 3to5-S,FS (65,45nm) $p$=350 | 3to5-S,FS (65,45nm) $p$=450 |\n|----------------|------------------|------------------|-------------------|-------------------|\n| **Frequency**  | 0.73             | 0.86             | 0.45              | 0.78              |\n| **Delay**      | 0.76             | 0.85             | 0.66              | 0.72              |\n| **Power**      | 0.81             | 0.88             | 0.67              | 0.80              |\n| **Average**    | **0.77**         | **0.86**         | **0.59**          | **0.76**          |\n\n\n\n\n\n"}, {"review_id": "Nb3aGlsEj4", "reviewer": "Reviewer_pjdD", "summary": "This article proposes a graph-based circuit design framework to help address the issue of label scarcity in circuit design. The paper is well-written, virtually free of errors or inconsistencies. Information is presented accurately and timely, creating a smooth narrative flow between the main paper and supplementary content. However, I do have some queries regarding the specific technical aspects of the paper. I would be immensely grateful if the authors could provide satisfying answers.", "questions": " (1) Please include more detailed analysis of the specific GNN networks, especially addressing potential issues such as over-smoothing.\n\n(2) Is it feasible to conduct experiments in real circuits? If so, please include such tests, which could involve smaller, simpler circuits. If not, it would be helpful to clearly explain the reasons for not testing in real-world situations.", "limitations": "(1) Please include tests on various GNN frameworks.\n\n(2) Please clarify in the experiment why only simulation results are presented.", "rating": 6, "confidence": 3, "soundness": 3, "presentation": 3, "contribution": 3, "strengths": "(1) The technology presented is quite innovative, successfully merging popular Graph Representation Learning with the semi-supervised nature of GNNs and the fundamental characteristics of circuits.\n(2) The writing exhibits smooth logic, with technical details clearly expressed.", "weaknesses": "(1) The citations in this paper primarily focus on circuit design and system-related conferences or journals. I would like to see more analysis related to GNNs, as GNNs typically require deeper layers for larger circuits (components of which should be quite complex). However, an overly deep receptive field might lead to an over-smoothing issue. Is there a chance of over-smoothing occurring when each device is learning within the network?\n\n(2) While this paper presents many circuit-related simulation experiments, it lacks validation in real-world scenarios. To my knowledge, circuit design in practical settings is costly, which may present challenges for the authors in testing on specific circuits. Nevertheless, I am still interested in querying this issue and hope the authors could offer some related thoughts.\n\n(3) The importance of each device in the circuit might vary. In certain situations, some key devices are crucial to the entire circuit. Therefore, I believe the authors' discrete encoding approach may be unsuitable.", "quality": null, "clarity": null, "significance": null, "originality": null, "strengths_and_weaknesses": "", "was_revised": false, "final_justification": "", "rebuttal": "**W1, Q1, L1**: Thanks for raising the concern. We experimented by creating deeper GNNs and the results are as follows:\n| GCX(.)    | Gain ($p$=50%) | Gain   ($p$=70%) | UGB ($p$=50%) | UGB ($p$=70%) | GM ($p$=50%) | GM ($p$=70%) | PM ($p$=50%) | PM ($p$=70%) | Noise ($p$=50%) | Noise ($p$=70%) | Power ($p$=50%) | Power ($p$=70%) |\n|-----------|----------------|----------------|---------------|---------------|--------------|--------------|--------------|--------------|----------------|----------------|----------------|----------------|\n| SAGE      | 0.33           | 0.58           | 0.30          | 0.55          | 0.76         | 0.81         | 0.65         | 0.79         | 0.73           | 0.93           | 0.90           | 0.92           |\n| GAT       | 0.07           | 0.11           | 0.05          | 0.06          | 0.64         | 0.78         | 0.63         | 0.66         | 0.32           | 0.40           | 0.50           | 0.51           |\n| GCN       | 0.03           | 0.09           | -0.05         | -0.01         | 0.09         | 0.33         | 0.13         | 0.13         | 0.08           | 0.10           | 0.40           | 0.45           |\n\n**Table 1: $R^2$ scores with different GNN architectures with deeper layers - Sparse Graph: (Average Degree- 3.5)**\n| GCX(.)    | Gain ($p$=50%) | Gain ($p$=70%) | UGB ($p$=50%) | UGB ($p$=70%) | GM ($p$=50%) | GM ($p$=70%) | PM ($p$=50%) | PM ($p$=70%) | Noise ($p$=50%) | Noise ($p$=70%) | Power ($p$=50%) | Power ($p$=70%) |\n|-----------|----------------|----------------|---------------|---------------|--------------|--------------|--------------|--------------|----------------|----------------|----------------|----------------|\n| SAGE      | 0.36           | 0.52           | 0.44          | 0.49          | 0.36         | 0.70         | 0.78         | 0.83         | 0.82           | 0.88           | 0.79           | 0.89           |\n| GAT       | 0.00           | 0.00           | 0.00          | 0.00          | 0.28         | 0.52         | 0.44         | 0.52         | 0.12           | 0.18           | 0.38           | 0.40           |\n\n**Table 2: $R^2$ scores with different GNN architectures with deeper layers - Dense Graph: (Average Degree- 10.1)**\n\nGCN exhibits worst performance when subjected to deeper layers. Initial experiment (best performing model) was conducted with GCN (2 Hidden layers), GraphSAGE (1 Hidden layer) and GAT (1 Hidden layer). To demonstrate over-smoothing we incorporate additional layer to the corresponding architectures.\n\nWe have acknowledged the occurrence of \"over-smoothing\" as GNNs become deeper, potentially compromising surrogate model accuracy. To counter this, we've adopted strategic measures during algorithm development to curb over-smoothing's adverse effects effectively:\n\n**Construct Sparse graph**- The optimization formulation suggested in the paper controls the sparsity of the graph, thus reducing the effect of over-smoothing.\n\n**Use variants of GNNs**: Architectures such as SAGE and GAT exhibit enhanced resilience to over-smoothing. Our proposed GCX(SAGE) model, showcases superior performance in mitigating the over-smoothing challenge.\nBy adopting the above mentioned preventive techniques we obtain significant resilience to the over-smoothing problem with deeper GNNs.\n\n**W2, Q2, L2**:Thanks for asking this question. It is true that performance of circuit design is finally tested on a silicon. However, process of designing, fabricating it in chip and validating in lab is a costly and time taking affair. Hence these designs are first validated through extensive simulation to ensure the performance. As the model used in these simulations are obtained from real validation on silicon hence they closely predict the behaviour of circuits realized on silicon. Currently we have also simulated all the optimized circuits using the same models (180nm CMOS process TSMC foundry models which are made available by foundry) to ensure its correctness and our results are shown in supplementary material. We have a plan to validate it on silicon however this process will require another year as we are currently in design process and fabrication and getting chip back will take at least an year or so. Hence we at this stage are providing simulation results which in circuit community is a close confirmation of validity of a circuit.\n\n**W3**: Thanks for the comments. Our present encoding technique efficiently consolidates crucial circuit information into a singular feature vector. Nonetheless, it remains evident that specific components within a circuit might hold greater significance than others. While our current encoding methodology assigns uniform weightage to all components, our approach offers the advantage of tailoring weightage to specific design parameters. This adaptability enhances the comprehensibility of feature encoding and enables a finer grasp of the overall circuit configuration."}, {"review_id": "MME9cylt7V", "reviewer": "Reviewer_LaWa", "summary": "This paper proposes a graph based semi supervised framework that is capable of driving analog design", "questions": "* on conclusion, from what I understand the result is more optimal than other methods, how to determine that it yields the most optimal parameters?\n* For different technologies, does it need separate training or the knowledge is transferrable across technoilogies?", "limitations": "* The authors discuss some of the limitations in knowledge transfer.", "rating": 6, "confidence": 1, "soundness": 3, "presentation": 3, "contribution": 3, "strengths": "* The paper is generally well written and organized.\n* The figures are nicely drawn to make understanding necessary concept easier.\n* The proposed mehtod is well illustrated, the idea of using semi-supervised methods looks interesting and promising.\n*  Experimental results are well demonstrated and explained, comparison against existing methods look promising. ", "weaknesses": "Please see questions.", "quality": null, "clarity": null, "significance": null, "originality": null, "strengths_and_weaknesses": "", "was_revised": false, "final_justification": "", "rebuttal": "**Q1**: This is a very important question and thanks for pointing it out.\n\n**Algorithmic viewpoint**: Optimality of the design parameters depends on how well the objective function is optimized. For the test cases we considered, FOM was chosen as the objective function (details are discussed in supplementary). When the stopping criteria (discussed in Q3- reviewer LVTs) is met the algorithm gives out the most optimal set of design parameters. \n\n**Designer's viewpoint**: The significance assigned to each metric transforms across different circuits and applications. For an amplifier, gain might reign supreme, whereas Phase Margin (PM) might command precedence elsewhere. Conversely, lower power consumption could be paramount in other scenarios. In each case the definition of optimality changes and results in different set of design parameters. For our case, after taking the designer's recommendation we assign equal importance to all the specifications under consideration and the algorithm provides the optimal parameters. Notably, our algorithm can easily incorporate these additional attributes and give out the parameters accordingly.\n\n**Q2**: Thanks for asking this question. As discussed in the paper we attempted to perform few-shot and zero-shot learning by generating a comprehensive feature vector which facilitates knowledge transfer across technology nodes and topology. Our proposed approach achieved an encouraging performance in few-shot learning and the results are as follows:\n| Model GCX(SAGE) | 3-S,FS (65,45nm) $p$=350 | 3-S,FS (65,45nm) $p$=450 | 3to5-S,FS (65,45nm) $p$=350 | 3to5-S,FS (65,45nm) $p$=450 |\n|----------------|------------------|------------------|-------------------|-------------------|\n| **Frequency**  | 0.73             | 0.86             | 0.45              | 0.78              |\n| **Delay**      | 0.76             | 0.85             | 0.66              | 0.72              |\n| **Power**      | 0.81             | 0.88             | 0.67              | 0.80              |\n| **Average**    | **0.77**         | **0.86**         | **0.59**          | **0.76**          |\n\n So, by fine-tuning our pre-trained model to the newer set of samples our approach facilitates knowledge transfer.\n\n**L1**: After thorough experimentation across various paradigms we observe our proposed approach has following limitations:\n\n(1) **Low $R^2$ score**: We currently observe that $R^2$ score corresponding to metrics like Gain and UGB are low, which results in incorrect predictions. We intent to explore techniques like encoding of the design space to further elevate the score.\n\n(2) **Limited success in knowledge transfer**: Our current approach shows promising results in facilitating knowledge transfer. However, to realize a more comprehensive replacement of SPICE simulations, it is imperative to enhance the implementation of our surrogate model to ensure its accuracy and reliability.\n\n\n\n\n"}, {"review_id": "KiaDsuL7KJ", "reviewer": "Reviewer_ufxr", "summary": "- This paper propose a GNN based framework, dubbed as Graph of Circuits Explorer (GCX), to optimize circuit design by predicting the performance parameters of the nodes in circuits, e.g., Gain, Bandwidth, Noise, etc.\n- This paper 1) utilizes a semi-supervised learning framework is employed for the graph-based surrogate model, and 2) creates a comprehensive feature vector that integrates information about various technology nodes and topologies, emphasizing generalizability in zero-shot and few-shot learning frameworks.\n- With the proposed techniques, this work can enhance circuit performance prediction accuracy and efficiency while reducing the reliance on extensive labelled datasets.\n- It demonstrated the proposed frameworks's effectiveness via simulation under 180nm CMOS technology, with model generalizability tested on 65nm and 45nm CMOS process nodes.", "questions": "Please address the comments in the weakness section.", "limitations": "The authors have not yet included the limitations and broader impacts.", "rating": 7, "confidence": 1, "soundness": 3, "presentation": 4, "contribution": 3, "strengths": "- The presentation of this paper is very solid and clear, both in terms of the text description and the figure illustration.\n- This work conduct comprehensive validation across different GNN model variants, other circuit performance prediction methods, and different ablation settings. The improvements show are consistent.", "weaknesses": "- The contribution and distinction over the inherent characteristics of GNNs can be stressed out more. This paper extensively leverages the GNN's ability of predicting the unknown nodes' results based on their surrounding neighbors. However, this part has been widely researched for in the transductive learning scenario of GNNs and the label propagation in earlier graph processing works. The authors could better stress out these inherent (vanilla) techniques' limitations and what they do to specifically address them.\n- Practical significance of the results' improvements could be supplemented. Although the evaluations consistently generate improvements, it is a little unclear what the technique can enable in the practical EDA tasks while the existing methods can be lacking. Also, the tested metrics' significance in actual applications can be added.\n- Is there any potential limitation of the proposed methods? ", "quality": null, "clarity": null, "significance": null, "originality": null, "strengths_and_weaknesses": "", "was_revised": false, "final_justification": "", "rebuttal": "**W1**: Thanks for the feedback. We had performed following set of experiments highlighting the robustness of our proposed algorithms to some of the commonly encountered problems with vanilla GNN architectures:\n\n(1)**Over-smoothing in GNNs**: Over-smoothing is an inherent problem with deeper GNNs and result in performance degradation.\n\n**Proposed solution**: (1) Generate sparse graphs: the formulation discussed in the paper provides sparsity control on the graph. As a result over-smoothing is controlled. (2) Use variants of GNN: GCX(SAGE) as proposed in the paper provides highest resilience to over-smoothing. (refer table for experimental results)\n\n| GCX(.) | Gain ($p=$50%) | Gain ($p=$70%) | UGB ($p=$50%) | UGB ($p=$70%) | GM ($p=$50%) | GM ($p=$70%) | PM ($p=$50%) | PM ($p=$70%) | Noise ($p=$50%) | Noise ($p=$70%) | Power ($p=$50%) | Power ($p=$70%) |\n|-------|------------|------------|-----------|-----------|----------|----------|----------|----------|-------------|-------------|-------------|-------------|\n| SAGE  | 0.33       | 0.58       | 0.30      | 0.55      | 0.76     | 0.81     | 0.65     | 0.79     | 0.73        | 0.93        | 0.90        | 0.92        |\n| GAT   | 0.07       | 0.11       | 0.05      | 0.06      | 0.64     | 0.78     | 0.63     | 0.66     | 0.32        | 0.40        | 0.50        | 0.51        |\n| GCN   | 0.03       | 0.09       | -0.05     | -0.01     | 0.09     | 0.33     | 0.13     | 0.13     | 0.08        | 0.10        | 0.40        | 0.45        |\n\n\n**Table 1: $R^2$ scores with different GNN architectures with deeper layers - Sparse Graph: (Average Degree- 3.5)**\n\n| GCX(.) | Gain ($p=$50%) | Gain ($p=$70%) | UGB ($p=$50%) | UGB ($p=$70%) | GM ($p=$50%) | GM ($p=$70%) | PM ($p=$50%) | PM ($p=$70%) | Noise ($p=$50%) | Noise ($p=$70%) | Power ($p=$50%) | Power ($p=$70%) |\n|-------|------------|------------|-----------|-----------|----------|----------|----------|----------|-------------|-------------|-------------|-------------|\n| SAGE  | 0.36       | 0.52       | 0.44      | 0.49      | 0.36     | 0.70     | 0.78     | 0.83     | 0.82        | 0.88        | 0.79        | 0.89        |\n| GAT   | 0.00       | 0.00       | 0.00      | 0.00      | 0.28     | 0.52     | 0.44     | 0.52     | 0.12        | 0.18        | 0.38        | 0.40        |\n\n**Table 2: $R^2$ scores with different GNN architectures with deeper layers - Dense Graph: (Average Degree- 10.1)**\n\n(2) **Rigidity to specific topologies**: Incorporating multiple topologies to facilitate generalizabilty has not been widely explored.\n\n   **Proposed solution**: We attempt to perform knowledge transfer across different technology files and topologies. We observe encouraging results for test case under study (refer the following table).\n\n| Model GCX(SAGE) | 3-S,FS (65,45nm) $p$=350 | 3-S,FS (65,45nm) $p$=450 | 3to5-S,FS (65,45nm) $p$=350 | 3to5-S,FS (65,45nm) $p$=450 |\n|----------------|------------------|------------------|-------------------|-------------------|\n| **Frequency**  | 0.73             | 0.86             | 0.45              | 0.78              |\n| **Delay**      | 0.76             | 0.85             | 0.66              | 0.72              |\n| **Power**      | 0.81             | 0.88             | 0.67              | 0.80              |\n| **Average**    | **0.77**         | **0.86**         | **0.59**          | **0.76**          |\n\n**W2**:\n**Practical Significance**: \nMinimize the dependence on extensive labeled datasets, consequently leading to a reduction in the duration of the design cycle.\n\n**Comparison with practical EDA tools**: (1) Current EDA tools completely leverage supervised learning framework which required extensive simulations. This makes the process resource and time intensive. Our proposed method employs semi-supervised learning to act as proxy to simulations under limited label scenario. (2) The usage of graph and graph-based surrogate models have not been widely explored in the EDA techniques and current works are very restrictive in terms of generalizability. \n\n**Significance to Applications**: We consider different metrics like Power consumption, Noise, PM etc which contribute to stability and efficient performance of the circuit. The demonstrated results validate that our proposed algorithm balances the trade-off between performance (metrics like Gain, UGB, Noise, PM) and resource consumption (power).\n\n**W3**: After thorough experimentation across various paradigms we observe our proposed approach has following limitations:\n\n**Low $R^2$ score**: We currently observe that $R^2$ score corresponding to metrics like Gain and UGB are low, which results in incorrect predictions. We intent to explore techniques like encoding of the design space to further elevate the score.\n\n**Limited success in knowledge transfer**: Our current approach shows promising results in facilitating knowledge transfer. However, to realize a more comprehensive replacement of SPICE simulations, it is imperative to enhance the implementation of our surrogate model to ensure its accuracy and reliability."}, {"review_id": "yruY1DV0aT", "reviewer": "Reviewer_5fbs", "summary": "Automatic circuit design and optimization is an active field of research. Many different algorithms have been proposed with different design objectives, e.g., layout optimization, size optimization, and topology generation. Prior works adopted GNNs to represent circuit topologies, but the authors suggest a different approach in this work. After constructing a dataset consisting of sample circuits and their labels, they are mapped as a node in a graph. Then, a GNN model is employed to predict the labels of unlabeled samples. Two different optimization algorithms are proposed, and they exhibited relatively good performance in experiments.", "questions": "- The optimized two-stage OTAs display good performances in Table 4. However, analog circuits often show totally different behavior in transient simulations. Were all the final designs verified in transient simulations?\n- 2-stage OTA and ring oscillator are very simple circuits. Did the algorithm work well for more complex circuits?\n", "limitations": "- Not a practical substitute for SPICE models\n- Only tested on simple circuits\n", "rating": 3, "confidence": 4, "soundness": 2, "presentation": 2, "contribution": 2, "strengths": "- This is a new approach to applying GNNs to circuit design.\n- The method can be applied to a wide range of circuit topologies (in theory).\n- The surrogate model works relatively well in experiments.\n", "weaknesses": "- Probably the most interesting idea in this work is how to use graphs for circuit optimization. The way of embedding circuits into a node of a graph looks novel. However, the performance of the surrogate model is quite low, as displayed in Tables 1 and 2. It might be slightly better than prior methods, but its accuracy is still too low, so the method is not very practical. Can this really substitute conventional SPICE simulations when optimizing the design? There is no guarantee that this algorithm can produce an equally good circuit compared to SPICE-based approaches.\n- Since the GNN models and optimization algorithms are not entirely new, this work might not see much interest in the machine learning community, especially considering prior works have been mostly published in EDA conferences and journals (e.g., DAC, ICCAD, and TCAD).\n", "quality": null, "clarity": null, "significance": null, "originality": null, "strengths_and_weaknesses": "", "was_revised": false, "final_justification": "", "rebuttal": "**W1, L1**: Thanks for your comments. \n\n**Accuracy of the surrogate model**: \nThe model under consideration exhibits somewhat modest performance in metrics such as GAIN (0.6) and UGB (0.6). However, a contrasting trend emerges when evaluating metrics like GM, PM, Noise, Power, Frequency, and Delay, where the $R^2$ scores consistently surpass 0.8. This performance has been achieved under a very limited labeled scenario (comprising merely 500 labeled samples). This dataset size stands in stark contrast to the larger datasets employed by comparable studies. \n\nIt's worth noting that the potential for performance enhancement remains by introducing a small number of additional samples. We also intend to explore encoding of the design space to further improve the $R^2$ score.\n\nHence we believe that the proposed surrogate model can act as an effective proxy to the SPICE simulations during optimization.\n\n**Substituting SPICE simulations during optimization**: \n The pre-trained surrogate model was employed during optimization and we performed an actual (through simulation) vs predicted value comparison corresponding to the most optimal design parameter's performance metrics. We observed that the predicted results from the surrogate model closely resembles with the simulated values across most metrics. Thus providing strong evidence that the proposed model can act as a proxy to SPICE simulations. \n\n**W2**: Thanks for your comments. Though graph has been introduced in the circuit designing problem this work is first to incorporate semi-supervised learning framework. This significantly reduces the reliance over extensive labeled datasets. Furthermore, our work yields the following benefits:\n\n(1) Formulating a node regression problem  by considering each node to be a circuit. \n\n(2) Incorporate technology and topology information to facilitate knowledge transfer.\n\n(3) Since the graph obtained is homogeneous it allows any GNN architecture to be easily integrated as opposed to prior works which generate heterogeneous graphs.\n\n(4) Incorporating semi-supervised learning framework, which has reduced the reliance on extensive labeled datasets.\n\n(5) Create a static and online framework incorporating graph-based surrogate models to obtain the most optimal parameters.\n\n**Focus to Machine Learning Community**:\nThough the algorithms underpinning our contributions draw upon existing knowledge but we provide a distinctive way of integrating them together and provide an efficient and accurate end-to end pipeline for the circuit designing problem.\n\nThe integration of existing algorithms has become a highly intriguing and well-received area of research, capturing considerable attention in top-tier conferences like **NeurIPS** [2,3], **AAAI**[1], **ICLR** [6] and **ICML** [4,5] in **2022-23**. This integration is especially focused on circuit optimization, covering both analog and digital circuits.\n\n**References**:\n[1] Domain Knowledge-Based Automated Analog Circuit Design with Deep Reinforcement Learning, author={Weidong Cao and Mouhacine Benosman and Xuan Zhang and Rui Ma}, year={2022}.\n\n[2] Versatile Multi-stage Graph Neural Network for Circuit Representation, author = {Yang, Shuwen and Yang, Zhihao and Li, Dong and Zhang, Yingxueff and Zhang, Zhanguang and Song, Guojie and Hao, Jianye}, year = {2022}.\n\n[3] Learning to Design Circuits, author={Hanrui Wang and Jiacheng Yang and Hae-Seung Lee and Song Han}, year={2020}.\n\n[4] Learning to Design Analog Circuits to Meet Threshold Specifications,\n  author =       {Krylov, Dmitrii and Khajeh, Pooya and Ouyang, Junhan and Reeves, Thomas and Liu, Tongkai and Ajmal, Hiba and Aghasi, Hamidreza and Fox, Roy}, year = \t {2023}\n\n[5]  Circuit-{GNN}: Graph Neural Networks for Distributed Circuit Design,\n  author =       {Zhang, Guo and He, Hao and Katabi, Dina}, year = {2019}\n\n[6] CktGNN: Circuit Graph Neural Network for Electronic Design Automation, author = {Zehao Dong and Weidong Cao and Muhan Zhang and Dacheng Tao and Yixin Chen and Xuan Zhang}, year = {2023}\n\n**Q1**: Thanks for asking this question and in fact this is a very important point. In this work we have simulated the design using optimized parameter obtained from our algorithm. The results shown in table.4 and table.5 in main paper as well as Table.1 and table.6 are generated from simulations only using the optimized parameter. Further, we have also performed a transient step response  of unity gain amplifier which uses our designed opamp. We observed from this step response that the system is stable and phase margin of this circuit should be somewhere between 50-55 degree (as there is only 1 visible peaking in the ringing response and then it settles) and thus it meet the desired performance. Kindly refer the simulation results supplemented.\n    \n**Q2, L2**: Thanks for asking this question. Although two stage amplifier and ring oscillator are simple circuit but they cover a wide variety of circuits as two stage amplifier is an example of circuit which mostly works in linear region of operation where small signal analysis is valid and operating points are calculated only once while on the other hand ring oscillator operates mostly in large signal region where transistor operates in different region of operation and analysis are mostly performed using periodic steady states where operating points are continuously changing in a repetitive fashion. Further two stage OTA process voltage domain signal while in ring oscillator time domain information of signal is important. Therefore even though these circuits may look simple but it covers different and important category of analog circuits and covers a wide range of analog circuits. Most of the analog circuit can be thought of an extension and combination of these simple building blocks. \n\n\n"}]

Author rebuttal:
**Q1)** **Reviewer-5fbs**: Transient Analysis Simulation results

Meta-review: This paper applies graph neural networks to circuit design and optimization. 4 reviewers are positive about the work, and 1 reviewer has a negative opinion after the rebuttal. Most reviewers have relatively low confidence because this paper is not a very common topic in machine learning conferences, but the authors have pointed out that there have been several papers on this topic in the past two years in NeurIPS/AAAI/ICML. The authors are recommended to add the discussion on SPICE simulations and surrogate models to the paper. Overall, a new and interesting approach is proposed to circuit design optimization with satisfactory performance. Thus, I would recommend acceptance of this paper.
Decision: Accept (poster)