Versatile Multi-stage Graph Neural Network for Circuit Representation
Authors: Shuwen Yang
Zhihao Yang
Dong Li
Yingxue Zhang
Zhanguang Zhang
Guojie Song
Jianye HAO
Venue: NeurIPS 2022 Accept (2022)
Keywords: EDA
Circuit Design
logic synthesis
graph neural network
graph representation learning

Abstract: Due to the rapid growth in the scale of circuits and the desire for knowledge transfer from old designs to new ones, deep learning technologies have been widely exploited in Electronic Design Automation (EDA) to assist circuit design. In chip design cycles, we might encounter heterogeneous and diverse information sources, including the two most informative ones: the netlist and the design layout. However, handling each information source independently is sub-optimal. In this paper, we propose a novel way to integrate the multiple information sources under a unified heterogeneous graph named Circuit Graph, where topological and geometrical information is well integrated. Then, we propose Circuit GNN to fully utilize the features of vertices, edges as well as heterogeneous information during the message passing process. It is the first attempt to design a versatile circuit representation that is compatible across multiple EDA tasks and stages. Experiments on the two most representative prediction tasks in EDA show that our solution reaches state-of-the-art performance in both logic synthesis and global placement chip design stages. Besides, it achieves a 10x speed-up on congestion prediction compared to the state-of-the-art model.

Versatile Multi-stage Graph Neural Network for Circuit Representation
Shuwen Yang
Zhihao Yang
School of Intelligence Science and Technology Peking University swyangāpku. edu.
School of Software and Microelectronies
Peking University zhihaoyang@stu pku edu. cn
Dong Li Huawei Noah's s Ark Lab 1 1idong1066ma wewpnng066@hwwei..cmm com
Yingxue Zhang
Huawei Noah's 's Ark Lab
yingxue whwngghuawei..c..o.. com
Zhanguang Zhang Huawei Noah's 's Ark Lab
z zhang@huaweii.com
Guojie Song"
Jianye HAO*
School of Intelligence Science and Technology Peking University gjsongāpku. edu. cn
Huawei Noah's 's Ark Lab
maojianye@haweei com
Abstract
Due to the rapid growth in the scale of circuits and the desire for knowledge transfer from old designs to new ones, deep learning technologies have been widely exploited in Electronic Design Automation (EDA) to assist circuit design. In chip design cycles, we might encounter heterogeneous and diverse information sources, including the two most informative ones: the netlist and the design layout. However, handling each information source independently is sub-optimal. In this paper, we propose novel way integrate the multiple information sources under unified heterogeneous graph named Circuit Graph, where topological and geometrical information is well integrated. Then, propose Circuit GNN to fully utilize the features of vertices, edges as well as heterogencous information during the message passing process.
the first attempt design versatile circuit representation that is compatible across multiple EDA tasks and stages. Experiments on the two most representative prediction tasks EDA show that our solution reaches state- of-the-art performance in both logic synthesis and global placement chip design stages. Besides, it achieves 10x speed-up on congestion prediction compared the state-of- satte-of-the-arr model.
Introduction
Integrated circuits (ICs) are extensively used in modern electronic products like computers, smart- phones, and cars. Electronic Design Automation (EDA) includes set of tools for eircuit design in different development stages especially logic synthesis stage and placement stage (Fig [ As
"Corresponding Author
36th Conference on Neural Information Processing Systems (NcurIPS 2022).

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the scale and complexity of circuits continuously grow, the design efficiency and precision of EDA tools have become an essential problem. which attracts researchers to adopt deep learning techniques to assist the circuit design process [ Remarkable progress has been made in predicting circuits' quality and practicability in the earlier stage of the chip design to speed up optimization and reduce design cost 2 3. For example, predicting congestion for circuits in physical design stage can help detect their flaws and avoid producing defective chips, and chip design production cycle time can be further saved if such prediction could be done in logic synthesis stage.
Panmecter
Value
CPU
DMA
Comarpplis
Arhoo
Arhiler
Click Propency
WCM
Diss
System Specification
Architectural Design
Functional & Logic Design
Logic Synthesis
Placement & Routing
Fabrication & Packaging
Figure 1: Chip Design Flow
1,2,
3
2
3.4
5
5
3.5.6
DDD cell
net
cell
grid
cell
|cell-link
net
link
(a) Circuit Design
(b) Circuit Layout
(c) Homo. Graph (cell-oriented)
(d) Homo. Graph
(net-oriented)
Figure Convert circuit design to a grid feature matrix and homogeneous graph.
Because of the sophisticated process of circuit design, we will encounter diverse information sources from various design stages, among which logic synthesis and placement & routing determine the quality, e.g. time delay, of circuit and consume the majority of design pipeline time, as shown in Fig In the logic synthesis stage, a circuit design is represented as a Netlist composed of cells and nets, where celly refer to the electronic units and nets refer to the connectivity (i.e. hyper-edges) among the cells. After the placement & routing stage, we will obtain the circuit layout with the position of each electronic unit provided after they have been fully placed on the circuit board. Besides, the downstream tasks might require learning representations on both cells and nets, tailoring for specific downstream tasks. Thus, how to better organize and fuse the diverse and heterogeneous information provided in the context of circuit representation an important research question.
Although the information underlying the circuit design varies according to the input stages, we can divide into geometrical information and topological information. The netlists only contain the topological information (e.g. cell type and logical relationship between cells and nets), while some geometrical information (e-g. positions of standard cells) available after placement stage. According to which information they focus on, we categorize the existing prediction methods in circuit designs into topological methods and geometrical methods. The topological methods convert circuit designs into homogeneous graphs (Fig
(Fig()c)(d) cd)) and solve the problems with Graph Neural Network (GNN) 4 []6], while most recent geometrical models convert the circuit designs into grid feature matrices (see Def and Fig 2 bb) and adopt Computer Vision (CV) technologies to predict their properties g 9].
However, the topological methods only consider the topological information in netlists and cannot effectively perceive geometrical structure introduced after the placement stage, so their performance on circuits after placement is greatly stifled. Besides, the geometrical models heavily rely on geometrical information and neglect the topology underlying the netlists, so they cannot handle circuits in stages earlier than global placement where geometry is not available. In a word, they can

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only work well on circuits either in logic synthesis stage or placement stage but are not compatible with both. Moreover, most of the existing prediction methods design modules with prior knowledge to serve certain applications, so they are not flexible enough to handle diverse EDA tasks. Therefore, is necessary to: (1) design data structure to represent the circuit, which is adaptive circuits in both logic synthesis and placement stages; (2) propose an efficient and effective circuit representation model which is compatible with two stages and various downstream tasks.
In this paper, we first convert the circuit design to Circuit Graph (see (Fig 3 a heterogeneous graph which preserves most of the topological and geometrical information, with a linear time consumption to the scale of the design (see Appendix B.2 for proof), A circuit graph contains two types of vertices iee cells and nets. We use pins which connect cells and nets to represent the topology. which are also noted as topo-edges, When handling circuits in placement stage, we additionally link the cells which are geometrically close (named geom-edges) to represent the geometry.
Then, we design Circuit GNN to process Circuit Graphs with optimal efficiency and produce representations for cells and nets to handle diverse tasks on circuits in both logic synthesis stage and placement stage. To collect and enrich the topological and geometrical information, we conduct message-passing 100 on topo-edges and geom-edges individually and later fuse the messages to update cells and nets representations. Multiple layers of such "message-passing & fusion" inference further exploit the deep relationships between topology and geometry and facilitate Circuit GNN to output nutritious representations. Circuit GNN is also compatible with Circuit Graphs converted from eircuits in logic synthesis stage because geom-edges's absence will not disable the message-passinn over topo-edges and the topological information can still be collected.
In summary, our contributions are:
To address the challenge posed by the diverse and heterogeneous information source in the context of circuit representation, we propose a novel way to integrate the information named Circuit Graph, a heterogeneous graph where topological and geometrical information are integrated jointly, which is able to handle diverse circuit tasks on cell, nets level and on different stages. To our best knowledge, this is the first unified circuit representation approach that can be easily compatible across EDA tasks and stages.
We propose a novel message- paatggng-aiingggggg paradigm Circuit GNN that tailors the aforementioned graph dataset structure. We design message-passing on both topological and geometrical edges distinctively and then fuse the messages to update cells and nets representations. The efficiency and effectiveness of our design are demonstrated both methodologically and experimentally.
Experiment results validate the superior performance and efficiency of Circuit Graph across multi sualti-stagesttasss For circuit congestion prediction task at logic synthesis stage, it improves the average grid-level accuracy by 16.7% against SOTA. At placement stage, it achieves 5.6% accuracy gain with 10x speed-up in congestion prediction task and 16.9% error gain in net wirelength prediction task.
2 Related Work
2.1 Topological Methods
The topological methods in EDA focus on the logic relationships between the cells and nets and usually reconstruct the circuit designs into graphs with vertices and edges. CongestionNet(5] and solutions in (6) link the cell-pairs connected via nets (F) and adopt popular GNNs (c.g. GAT(II) to generate cell representations for congestion prediction. To handle net length identification and net delay prediction, Net² [12] links the nets connecting to one cell (Fig d))
d)) and designs a customized GNN to obtain net representations. All these methods perceive the circuit designs as homogeneous graphs and neglect the underlying heterogeneity, e.g. the interaction between cells and nets like signal input/output, so their solutions suffer from information loss and will affect the performance of downstream GNN.
3

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2.2 Geometrical Methods
The geometrical methods in EDA focus on the spatial information of the circuit designs. A universal approach is to cut a circuit into small rectangles i.e. grids and convert it into RGB channels, where the grids are treated as pixels | [ Then, they encode the netlist structure and circuit features into green and blue channels while red channels are left for prediction targets (e.g. congestion). Finally, they use image translation methods (e.g. pix2pix (9) to output new images with red channels filled and indirectly solve the EDA tasks.
The cutting-edge LHNN 14, however, converts the circuits into lattice networks [3] instead of images, where each grid serves an internal node in the network and each net, as extemal node, is connected the grids it covers geometrically. LHNN successfully enhances topological information in geometrical method and achieves SOTA performance, but it can only handle congestion prediction task and can only work on circuits with placement information.
3 Circuit Graph
Circuit Graph
cell
pin
a
cell E
net
b
5
topo-edge (f.e. pin) &
(a) Circuit Design
(b) Topo-cdge construction
geom-odge E Eg
(c) Circuit Layout
(d) Link the cells appearing the same window
(c) Graph with geom-edges
Figure 3: Convert circuit design Circuit Graph. (b): Take cell-ner connections i.e. pins as topo-
edges. (c)::))): Link the geometrically close cell-pairs to construct geom-edges.
3.1 Circuit Featurization
circuit design is initially represented netlist composed cells V and nets (Fig and we define Xv, Xzx to be their feature matrices. Xy mainly contains the size and degree (to net) of the cells, and X stores the net span [4] and the degree (to celf).
Besides the basic attributes of cells and nets, the topology and geometry also play important roles in featurizing the circuit designs. The pins C V 21 stand for the bipartite topology between cells V and nets U. and Xp, the feature matrix of P. preserves their interaction details e.g. the signal direction (input/output). After placement, the positions of cells Pa. Py are obtained, which serve as major geometrical information. When carrying out deep learning on EDA, how to arrange the features of circuit design varies according the downstream model.
The geometrical methods cut the circuit into smaller rectangles i.e. grid and generate raw features on them by synthesizing the positions of cells Pa, Py along with cells' and nets' features Xv, Xu
and their connections P (Fig b)) 9 14)
where Xer = RC. Dar is Definition (Geometry-driven Circuit Featurization). FG =o=
the feature matrix of grids. Note that Cz, Cy are the column and row numbers of grids and Dae is the dimension of grids' raw features.
The grid feature X mainly includes pin density and net density 7
As the structure of Xg similar to RGB channels of image data, CV models (e.g. CNN(2) can be easily adopted to handle EDA tasks where geometrical information are provided as input.
In this paper, grid size 32pm 40pm.

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The topological methods prefer to construct the circuit design as bipartite graph (Def 2 [2]
Definition 2 (Topology-drie) driven Circuit Featurization). Fr (V.u. P, Xv, Xu, Xp ), where cells and nets Ul are two types of vertices, and pins P are the edges connecting them.
However, Fr is usually simplified homogeneous graph, and is fed to some popular GNNs, such as GAT (see Fig (d) and See 2.1 6 12). which leads to loss of heterogencous information.
Note that the explicit raw features of grid, cell, net and pin are listed in Appendix A.
3.2 Definition of Circuit Graph
To better benefit from both the above two commonly used fcaturization system for circuit, we propose novel way to encode both the topological and geometrical information (when available) underlying the circuits into a unified heterogencous graph. As shown in Fig we first take pins as topo-edges (Er P and Xey x)) Then we link the geometrically-clon cells with geom-edges &g and store the cell-pair distances in feature matrix X Finally, we define Circuit Graph as follows:
Definition 3 (Circuit Graph). A Circuit Graph G = {V, Er, &G; Xy, Xu, XET XEah where V,u. &r V S VV refer the of cells, nets, topo-edges and geom-edges, respectively, and Xv, Xu, XEr: Xeo are their feature matrices.
featuee
To preserve the topological information, we completely inherit V,2, P and their features from Fr in Defß rather than simplify them as homogeneous graphs with loss of heterogeneity. For geometrical information, to avoid calculating all O (2))2) cell-pairs' distances and reduce time cost to O(VI), we split the cells by shifted windows[Io. with size (Wz, Wy) and link the cells with up to (named "link capacity") neighbouring cells located the same window (see explicit steps in Appendix B.1). we need to handle the problem at the nee-placement phase such as the logic synthesis stage, we will have the geom-edges among the cells and will set &g = 0 for the representation learning phase, which shows that Circuit Graph is compatible with circuits in logic synthesis stage.
Note that the time consumption of converting cireuit design into Circuit Graph ((V))) which is linear to the scale of the circuit (see proof in Appendix B.2).
4
Circuit GNN
4.1 Overview
Circuit GNN
He.
geom-edge
M geom
(
M Millccom
b
H 00)
Geometrical Dessage--aassing
Mux-Pooling
M
Circuit Graph
Readout
m) i
topo-edge
topo- edge
M topo
M
Downstream Tasks
H
M
M
cell
Feature Initializer
Circuit Design
Topological Message-Passee
Fusion and Updating
Figure 4: Framework of Circuit GNN. The topological messages between cell and net are passed through topo-edge, while the geometrical messages among cells are passed through geom-edge. Circuit GNN can be set to L layers.
The framework of Circuit GNN shown in Fig We first input the Circuit Graph and initial- ize the feature of cells V, nets U, topo-edges Ey and geom-edges Eg to hidden representations
5

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H H (0) H H&g with Multi-Layer Perceptrons (MLPs). Then deeper representations of cells and nets are generated via L layers of circuit passage-passing. Finally, the output cell and net representations used for downstream tasks after passing through task-adaptive readout layers. Note that Circuit GNN's model sensitivity is justified in Appendix D.
4.2 Topo-Geom Message-passing
Inside each layer out of L Topo-Geom Geom dressage-passinggg layers, topological and geometrical informa- tion are collected by passing messages through two types of heterogeneous edges (Er and &g). Then, the messages are used to update cell representations Hy and net representations Hu- In Topological dessage-passing the messages between cells V and nets are transmitted through topo-edges Er:
M to
E ET, H H&T)
msg
Fr
M
o < S (V. "V,, H. H
(1)
where / is the number of current layer and &ll <IvV is the message function which collects topo- Sou
logical messages from nets and sends them cells V via topo-edges er ( Geometrical Message-passing, we consider the geom-edges &g and collect geometrical messages for cells V:
may similarly). In
Ed
My g...com
(V, Ea, H .HEa)
msy
Then, fuse the topological and geometrical messages and update the representations:
M MaxPooling( M (0.geom
(3)
H (1+1) 1 update (H )
H 4 Pupdate (HO M())
(4)
where the update function & Pusdaatl
(H,M) M) = H - Tanh(MM.
The efficiency and the capability of perceiving heterogeneous information (e.g. the edge embeddings in ε and &g which encode topological and geometrical information) should be considered when designing the exact message functions & 2mag. In Topological Message-passing, inspired by [17), for a net u, we fuse the representations of surrounding cells {vl(u, u) E Er} and topo-edges connecting them:
(We, V ET (((h) SIM(((()) (oa)) -& Σ (We, (We (oro)) (Wv-uh") mag
(5)
(K,))Er
where by is the representation vector of cell v. h is the representation vector of topo-edge connecting u, u, Wy-uu, Wey are learnable weight matrices and & the element-wise multipli-
cation. As topo-edge's representations have already been collected in Ty only consider net's representations h in the messages passed back to the cells, which speeds up message-passing (because of less computation) with minor topological information loss:
ST Hell T ((h E Erl) = Σ Wu-sh'y msg
(6)
(v.u)EET
In Geometrical Message-passing, to enhance the geometrical information, the geom-edge's represen- tations are used compute the edge weights when convolving the cells:
V >y
([(h))
Eo (wwer M[,, v²) EG))
Σ (a hee (o.er)) Wv-yhh
(1,8))E&o
where a is learnable weight vector and Wy-y is a learnable weight matrix.
Discussion of Inference Time. Assume that the hidden layer dimensions of cell, net, topo- eT
edge, geom-edge are Fu, Fez: Pec. The inference times of $ vV- sut -Iv msg
msg & &vv are ([EE Fuu+ + FuFuu Fu)), Fv), O(EEa + F3)), respectively. The time com- plexities of fusing (MaxPooling) and updating are (()))E), + respcticcy As

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the dimensions are constant numbers and |1 - | |&cl =0(V)) (see Appendix B.2), the
total inference time in one Topo-Geom Message-passingg layer is O [2] + IPI). which is linear
to the scale of input Circuit Graph. Therefore, our wessage-passing method can handle Circuit Graph with optimal efficiency, and is further demonstrated to be as fast as CongestionNet(S). deep
GAT architecture, in Tab
4.3 Task-adaptive Readout
After T. iterations of message-passing, passing, we read out the cell and net representations H H to handle diverse downstream tasks on circuits. For tasks on Cell-level (e.g. congestion prediction for each cell (5)), to enhance the raw features, we concatenate the cell representation and its raw features and pass them through an MLP (similarly for Net-level tasks e.g. net length prediction [2) ):
cell M (L) y
Xv)
Ynet MLP(H (L) + Xu)
(8)
However, Grid-level tasks (e.g. congestion prediction for each grid in chip map 9 assign targets on each grid, which our model is not aware of. To enable model's 's training and evaluation on these tasks, we generate an output representation on each grid by mean- weaa-pooling the representation of cells inside the grid:
Igrid- = MLP(M (2)
where M E (gCxxC,x(M) is the transformation matrix with Σx M.s,A = 1, Vi,
5
Experiments
5.1 Tasks and Datasets
Congestion Prediction is the task of predicting the routing congestion before the wires routed in the detailed routing stage. It is widely used in placement tools to provide quick feedback about the quality of placement and avoid placement solutions with poor routability [18] 200 In order to identify and solve potential congested structures earlier, multiple works have attempted to predict cell-level congestion in logic synthesis stage, before cells are placed 26 We conduct the experiment on ISPD2011 which contains 12 VLSI designs in total. We use 10 de- signs (1/2/3/5/6//9//111 1/14/16) for training, design #18 for validation, and #19 for testing. We use DREAMPlace 18] to place cells and initialize the raw features of cells, nets and grids. NCTU-GR 2.0 a popular global router, is used generate the congestion targets on the grids. The congestion target of each cell is set as the value of the grid it is located in. For congestion prediction in logic synthesis stage, we only use the topology of the circuits and the geometry-insensitee insensitive features. For prediction in placement, we additionally use the cells' positions generated by DREAMPlace.
Similar to 66, we compare the prediction and ground-truth in Pearson/SperrmnnKenndaa correlation on both Cell-level and Grid-level. We also divide the congestion values to [0, 0.9] and (0.9, oo) and use precision/recallFF/-scoo
further evaluate their ability of identifying congestion [14
Net Wirelength Prediction aims to deduce the wire length of each net, which is an important indicator of the eventual chip performance (24). We use half-perimeter wirelength (HPWL) as the wirelength estimator, which is the most commonly used method for wirelength calculation [2]. We conduct the experiment DAC2012 where we use 7 designs (3/6/7/9/1 1/12/14) for training. design #16 for validation and #19 for testing. DREAMPlace 18) is used to generate the targets for every net. The featurization of circuits in both stages is the same with Congestion Prediction mentioned above.
As the regression targets of wirelength range from 0 to about 25k, we take the log of them to make the distribution of targets more smoothing. We evaluate the results in correlation as well as Mean Average Error (MAE) and Root Mean Square Error (RMSE).
Transfer Task is designed to further evaluate the representativeness of extracted GNN features. Here, we first train Circuit GNN/LHNN with Congestion Prediction task and then evaluate/fine-tune them with Wirelength Prediction.
http://wwwwinnpp.cc/oomtss///// 1/spp2201 1at0111__ooottmmmmm http://rrciii.sgggga...ddeeebbee
contest.html
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5.2 Baselines and Settings
When conducting the two tasks above, we compare our model with the following base- lines. Traditional machine learning methods include MLP, typical graph representation models and pix2pix(9V, typical image translation model in CV. We also carry out results on EDA-customized machine learning models: (1) CongestionNett
a multi-layer graph attentive architecture designed to predict circuit congestion; (2) Net [12], pre-placement net representation models with customized GNN; (3) LHNN[[4]: a geometrical congestion prediction method supplied with topological information i.c. net span. To further validate model's s ability to fuse the topological and geometrical information, we test two variants of our model: Ours (w/o. geom.) which throws all geom geom-edges and Ours (w/o. topo.) which throws all topo-edges in Circuit Graph (Def(3).
For cited methods, we use their default model settings. For Circuit GNN, we set hidden layer dimensions of cell, net, lopo-edge, geom-edge (Fv, Fu, Fey, Fee) (64, 128, 8, 4) and message passing layers I, We have default settings window size (Wy; wy) = (32, 40) and link capacity = 5, and their parameter sensitivity is tested in Appendix C to show the robustness of our model. When training our model with Adam Optimizer, we use learning rate y = 0.0002, learning rate decay An 0.02, weight decay 0.0002 and training epoch 100.
5.3 Result of Congestion Prediction
Table Congestion prediction result in logic synthesis stage
Time (s/epoch)
Cell-level pearson
Grid-level
Baseline
spearman
kendall
pearson
spearman
kendall
GCN
9.43
0.777
0.265
0. 099
0.221
0.366
0.260
GraphSAGE
11.79
0.776
0.252
0.188
0.208
0.375
0.268
GAT
13.90
0.777
0.267
0,200
0.215
0.399
0.280
CongestionNet
22.31
0.777
0.269
0.200
0.277
0.394
0.280
MPNN
116.24
0.780
0.289
0.217
0.292
0.458
0.319
Ours (w/o. geom.)
21.62
0.779
0.289
0.217
0.315
0.468
0.329
Table 2: Congestion prediction result in placement stage (in correlation)
Time (s/epoch)
Cell-level
Grid-level
Baseline
pearson
spearman
kendall
pearson
spearman
kendall
GAT (w. geom.)
16.21
0.777
0.263
0.197
0.210
0.397
0.279
pix2pix
4.46
0.562
0.554
0.392
LHNN
305.47
0.703
0.695
0.540
Ours (w/o. topo.)
21.54
0.883 0.887
0.713
0.573
0.684
0.730
0.536
Ours
27.07
0.714
0.575
0.697
0.770
0.577
(a) Input
(b) pix2pix
(c) LINNN
(d)
(e) Ground-truth
Figure 5: Visualization of congestion maps of circuit ispa2011//superbuuee1 produced by the basclines.

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We first evaluate the congestion prediction result on circuits in logic synthesis stage when geometric information not available (Tab[]). Then we perform the same task in placement stage shown in Tab and Appendix Tab. 12. Note that geometrical methods pix2pix and L.NNN are not aware of cells circuit design, so they are not evaluated on Cell-level. GAT (w. geom.) is regular GAT with cell positions as additional features.
The results show that: (1) logic synthesis stage, our method with only topo-edges achieves the best performance (16.7% over cutting-edge CongestionNet) with a similar time cost compared to traditional GNN models (5x faster than MPNN which has time-expensive and underused edge function for netlist input). (2) In placement stage, our method beats the cutting-edge LHNN in most metries (5.6% on average) while taking only one-tenth of the run-time. The superior performance of our model is primarily attributed to the fusion of both topological and geometrical information.
5 visualizes the predicted congestion values using different methods. Compared to vision-based method 9 and lattice network-based method [55. our proposed method can generate finer congestion prediction with better discriminability.
5.4 Result of Net Wirelength Prediction
Table 3: Net wirelength prediction in placement stage (4 means "lower is better")
Baseline
Time (s/epcoh)
pearson
spearman
kendall
MAET
RMSEL
MLP
2.22
0.493
0.547
0.415
0.626
0.819
2et
10.42
0.517
0.635
0.525
0.615
0.825
2a
19.83
0.632
0.656
0.553
0.614
0.821
LHNN
260.00
0.801
0.796
0.603
0.581
0.780
Ours
14.79
0.848
0.835
0.646
0.483
0.683
(a) MLP (b) Net
(c) ?e
(d) LHNN
Ours
Figure 6: Scattering the models' output (axis-y) and ground- (axis-x) (placement stage).
The result of net wirelength prediction shown in Appendix Tab. 11 (logic synthesis stage), Tab and Fig (placement stage). We obtain LHNN's result on this task by reading out its net representations generated in the intermediate stage. The result shows that our model achieves SOTA performance (16.9% error gain) with similar time cost to Ne and 2a
5.5 Result of Transfer Task
Here the experimental settings:
For the evaluation setting, different readout module is trained from scratch, but GNN's parameters are fixed.
For the fine-tuning setting, a different readout module is trained from scratch, and GNN's parameters are fine-tuned at the same time.
For evaluation & fine-tuning, L.HNN and Ours are only trained for 1/5 epochs of default setting, show the transferability of leamed features.

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Table 4: Transfer experiment from congestion prediction to wirelength prediction. Results are evaluated in Grid-level.
Baseline
Time (s/epoch)
pearson
spearman
kendall
MLP
2.22
0,493
0.547
0,415
LHNN (evaluate)
192.45
0.689
0.715
0.563
Ours (evaluate)
9.55
0.799
0.811
0.622
LHNN (fine-tune)
248.96
0.805
0.794
0.612
Ours (fine-tune)
14.8
0.842
0.829
0.639
LHNN Ours
260
0.801
0.796
0.603
14.79
0.848
0.835
0.646
The results show that the knowledge Circuit GNN learns from Congestion Prediction can be eas- ily transferred another task (no matter for direct use fine-tuning), while LHNN is weak in transferability.
Conclusion and Future Work
We present a versatile graph neural network to facilitate EDA circuit design process. To this end, we design hetcrogeneous graph, Circuit Graph, to integrate topological and geometrical information further propose message message-passing and fusion into unified data structure. based on which representation method applied to multiple EDA approach named Circuit GNN. It is the first circuit tasks and stages. By integrating multi-source information, Circuit Graph outperforms previous methods in prediction performance and computation time. Our work further supports the EDA process "shift-left', new future direction that aims to speed-up circuit design by deeply combining artificial intelligence in all EDA tool chains.
Limitations Although AI for EDA becomes hot research topic recently and some deep learning- driven techniques have been adopted the main-stream EDA tools (Cadence, Synopsys, etc.), there still gap between the novel machine learning algorithms and their application in commercial tools. Moreover, in early EDA stages, other circuit representations like data-flow graph or And-Inverter Graph (AIG) graph might be used. As the meaning of nodes and edges in these graphs different from netlist graph used in the paper, our method might not apply to these graphs in early EDA stages.
Societal Impact. Our solution explores dual-stage circuit representation to serve various EDA downstream tasks, which have limited socictal impact. Whatever, there is a minimal possibility of misuse that violate some ethics of life science.
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Reviews:
[{"review_id": "s-NDb9krlhC", "reviewer": "Reviewer_i4MY", "summary": "This work constructs a modeling framework that aims to solve various problems in the circuit design process. This work incorporates \n1. A novel circuit graph that is able to jointly integrate the topological and geometrical information and is claimed to be the first unified circuit representation approach that can be easily compatible across EDA tasks and stage.\n2. A novel message-passing paradigm, CircuitGNN, that is tailored towards the aforementioned graph dataset structure. The structure can conduct message-passing on both topological and geometrical edges distinctively and then fuse the messages to update cells and nets representations\n3. Extensive experiments validates the merits of the proposed methods in terms of both the task accuracy and execution speeds.", "questions": "1. Would be great to provide more summarized details on the proposed models and the baselines in terms of the number of parameters and operations and their types.", "limitations": "Yes, it's addressed.", "rating": 6, "confidence": 2, "soundness": 3, "presentation": 3, "contribution": 3, "strengths": "", "weaknesses": "", "quality": null, "clarity": null, "significance": null, "originality": null, "strengths_and_weaknesses": "Strength:\n1. This work does a good job on analyzing and illustrating the tasks and problems of circuit EDA in light of the machine learning methods.\n2. The methodology is described in much detailed but straight-forward way.\n3. Overall this work provides decent improvements over the existing methods. Just per the results alone, it is impressive.\n4. The code provided in the supplementary materials is certainly a plus, contributing to the transparency and reproduction of the works in the fields.\n\nWeakness:\n1. Apart from the improvements on the message passing methods, one of the key contributions of this work is to be able to jointly integrate the topo and geom information in one model. However, I do not see clearly the motivation for this point from both the application and results perspectives. For actual application, is there a significant disadvantage of simply using two sets of models or even methods respectively for logical synthesis and place-and-routing? One of the reasons, I would perceive, is that a joint model may yield a better task performance due to the complementary information. However, as Table 2 suggests, the joint model's improvements against the proposed method with only geom message passing.", "was_revised": false, "final_justification": "", "rebuttal": "", "claims_and_evidence": "", "methods_and_evaluation_criteria": "", "theoretical_claims": "", "experimental_designs_or_analyses": "", "relation_to_broader_scientific_literature": "", "essential_references_not_discussed": "", "other_strengths_and_weaknesses": "", "other_comments_or_suggestions": "", "questions_for_authors": "", "summary_of_paper": "", "summary_of_recommendation": "", "technical_quality": "", "clarity_of_presentation": "", "potential_impact": "", "robotics_focus": "", "quality_of_limitations": "", "questions_for_rebuttal": "", "reasons_to_accept": "", "reasons_to_reject": "", "questions_to_authors": "", "main_review": "", "summary_of_the_paper": "", "summary_of_the_review": "", "strength_and_weaknesses": "", "limitations_and_societal_impact": "", "review_text": "", "extra_scores": {"ethics_review_area": ""}, "extra_text": {}}, {"review_id": "fxG-3WqEPBB", "reviewer": "Reviewer_73KN", "summary": "The authors propose a unified way to construct graphs in different phases of EDA flow, and develop a general GNN model for downstream EDA tasks. Specifically, the proposed approach first constructs a heterogeneous graph by incorporating cell-cell connections (geometrical information) and cell-net connections (topological information). The node and edge features are generated based on physical properties of cells, pins, and nets. Then, a circuit GNN model is proposed to apply message passing on cell-cell and cell-net connections separately, which produces the representations of cells and nets for downstream tasks. The experimental results show that the proposed method increases 16.7% accuracy on congestion prediction and reduces 16.9% error on wirelength prediction.", "questions": "  - For the wirelength prediction task in placement stage, authors use DREAMPlace to generate both the ground truth and node/edge features. If the ground truth is already known, why does it even need to generate features for GNN?\n  - Is there any reason/insight why two different message-passing functions are used for topo-edges (Equation 5) and geom-edges (Equation 7)?\n  - Apart from logic synthesis and placement, how does the proposed work incorporate graphs in other EDA stages (e.g., data-flow graph in high-level synthesis)?\n  - Is it necessary to have geom-edges? Can we encode the cell positions into node feature vectors instead?", "limitations": "Thanks authors for mentioning potential limitations of this work. One key challenge of deploying ML models into commercial EDA tools is the model generalizability. Authors can evaluate the trained model on more unseen designs to see if it is truly generalizable.", "rating": 6, "confidence": 4, "soundness": 2, "presentation": 3, "contribution": 2, "strengths": "", "weaknesses": "", "quality": null, "clarity": null, "significance": null, "originality": null, "strengths_and_weaknesses": "**Key Strength**\n\n  - The paper is clearly written. All the technical steps are easy to follow.\n  - The proposed method can be used to solve multi-stage EDA tasks.\n  \n\n**Key Weakness**\n\nAlthough the proposed circuit graph construction and GNN model are all reasonable, they lack some technical significance. For example,\n  - For circuit graph construction, it is straightforward to construct a bipartite graph based on cell-net connections from netlist, in order to produce representations of cells and nets for downstream tasks. Hence, the contribution is limited for the graph construction, especially in logic synthesis stage where placement information is not available.\n  - For GNN model, it is a common way to apply message passing individually per edge type for handling heterogeneous graphs (e.g., [2]). Thus, the novelty of the proposed model is limited.\n  \n\nAlthough the experiments show promising accuracy gains for downstream EDA tasks, further clarification could make the improvements more convincing:\n  - Missing strong GNN baselines: The chosen baselines (i.e., GCN, GraphSAGE, and GAT) only consider node features. Since edge features are important in this paper, authors should compare the proposed model against stronger baselines (e.g., MPNN[1]) that incorporate edge features, on the same input graph. Without a stronger baseline, the contribution of the proposed GNN model is unclear.\n  - Not tuning hyperparameters for baselines: Authors choose the default hyperparameters for baselines from their original papers. Since the datasets used in those papers (e.g., [3]) are different from this paper, hyperparameter tuning is necessary.\n  - Not comparing against DREAMPlace: The purpose of wirelength prediction is to speedup EDA design closure. Nonetheless, there are no results of the runtime comparison between the proposed model and the placement method DREAMPlace, which is a very fast placement method by exploiting GPUs. Without this comparison, it's unclear about the motivation of wirelength prediction in placement.\n\n[1]: Gilmer et al. \"Neural message passing for quantum chemistry.\" ICML'17. \\\n[2]: Zhang et al. \"Heterogeneous graph neural network.\" KDD'19. \\\n[3]: Xie et al. \"Pre-Placement Net Length and Timing Estimation by Customized Graph Neural Network.\" TCAD'22.", "was_revised": false, "final_justification": "", "rebuttal": "", "claims_and_evidence": "", "methods_and_evaluation_criteria": "", "theoretical_claims": "", "experimental_designs_or_analyses": "", "relation_to_broader_scientific_literature": "", "essential_references_not_discussed": "", "other_strengths_and_weaknesses": "", "other_comments_or_suggestions": "", "questions_for_authors": "", "summary_of_paper": "", "summary_of_recommendation": "", "technical_quality": "", "clarity_of_presentation": "", "potential_impact": "", "robotics_focus": "", "quality_of_limitations": "", "questions_for_rebuttal": "", "reasons_to_accept": "", "reasons_to_reject": "", "questions_to_authors": "", "main_review": "", "summary_of_the_paper": "", "summary_of_the_review": "", "strength_and_weaknesses": "", "limitations_and_societal_impact": "", "review_text": "", "extra_scores": {"ethics_review_area": ""}, "extra_text": {}}, {"review_id": "6AY9psURFST", "reviewer": "Reviewer_vsvz", "summary": "This paper proposed a novel graph representation: Circuit Graph, integrating the heterogeneous circuit information from logic synthesis and placement to facilitate the EDA design process. The proposed graph structure considers both topological (cell connection in the netlist) and geometric information (positioning of the standard cells on the layout). A corresponding graph neural network (GNN) structure is proposed for extracting circuit representation for various downstream tasks. The experimental results demonstrated the effectiveness of the graph in congestion and net wirelength prediction tasks with efficient NN computation.", "questions": "1. The reviewer wonders if the authors can make comments about how transferrable the proposed GNN features are.\n1. The authors claimed the proposed GNN is very efficient in terms of computation. To be used in practical cases, the time consumed in training and inference of GNN should be compared with the traditional EDA routing tool. Some simple statistics over this can help justify the actual impact of the usage in EDA.\n1. Detailed GNN formulation question 1): In equation 5, a matrix $W_{\\varepsilon^T\\rightarrow\\mathcal{U}}$ is used in topological message passing, and in equation 7, a vector $a$ is used in the geometric message passing. What is the consideration underneath the difference here?\n1. Detailed GNN formulation question 2): To fuse the topological and geometrical messages, maxpooling is used (equation 3). What is the underlying thought process to use maxpooling for fusion, and what may be the effect of other fusion methods (e.g. adding, concatenation, averagepooling)?\n1. Detailed GNN formulation question 3): The readout for cell and net also include the raw features. The reviewer wonders how important those raw features are. If excluding them from the readout results in significant performance drops, the usefulness of the extracted GNN representation should be questioned. ", "limitations": "The paper mentioned that one limitation is to test the proposed method under commercial products and more complex scenarios. The reviewer appreciate that the authors bring up this and understand the difficulty behind it.", "rating": 6, "confidence": 3, "soundness": 3, "presentation": 3, "contribution": 3, "strengths": "", "weaknesses": "", "quality": null, "clarity": null, "significance": null, "originality": null, "strengths_and_weaknesses": "Strengths:\n1. Heterogeneous information fusion across multiple EDA design stages. Typically, circuit designs are divided into multiple phases. Each phase may have its own unique representation for the same underlying circuit. The proposed circuit graph brings two representations (netlist and cell placement) into a unified graph representation, which provided a more informative data structure embedding knowledge from multiple EDA design phases.\n1. The proposed circuit graph is general enough to be extended to inspire future work. The paper only touches on congestion and net wirelength prediction tasks for detailed routing, and the graph featurization contains only related basic topology information and simple geometric information. The reviewer believes the proposed graph can inspire more work in EDA areas. For example, by adding standard cell delay as one new feature in the cell node, the proposed graph may also help with the timing analysis of the circuit.\n1. The overall GNN structure follows the design of the circuit graph, which sounds promising. The topological and geometric message passing structures preserve the structure of the original circuit graph, \n\nWeaknesses:\n1. The paper didn't touch on how representative the extracted GNN features are. The two tasks (congestion prediction and net wirelength prediction) in the paper are experimented independently. Although these two tasks have different readouts, they shared the same input graph features and extract GNN feature representation. It would be interesting to check if the knowledge can be transferred from one task to another using the proposed GNN.\n1. Although the overall GNN structure sounds promising, some detailed formulation or design choice of GNN needs to be further justified. Detailed comments are made in the questions.", "was_revised": false, "final_justification": "", "rebuttal": "", "claims_and_evidence": "", "methods_and_evaluation_criteria": "", "theoretical_claims": "", "experimental_designs_or_analyses": "", "relation_to_broader_scientific_literature": "", "essential_references_not_discussed": "", "other_strengths_and_weaknesses": "", "other_comments_or_suggestions": "", "questions_for_authors": "", "summary_of_paper": "", "summary_of_recommendation": "", "technical_quality": "", "clarity_of_presentation": "", "potential_impact": "", "robotics_focus": "", "quality_of_limitations": "", "questions_for_rebuttal": "", "reasons_to_accept": "", "reasons_to_reject": "", "questions_to_authors": "", "main_review": "", "summary_of_the_paper": "", "summary_of_the_review": "", "strength_and_weaknesses": "", "limitations_and_societal_impact": "", "review_text": "", "extra_scores": {"ethics_review_area": ""}, "extra_text": {}}]

Author rebuttal:

Decision: Accept