Bridging Layout and RTL: Knowledge Distillation based Timing Prediction
Authors: Mingjun Wang
Yihan Wen
Bin Sun
Jianan Mu
Juan Li
Xiaoyi Wang
Jing Justin Ye
Bei Yu
Huawei Li
Venue: ICML 2025 spotlightposter (2025)
Keywords: .+Knowledge Distillation.+RTL timing predict.+Electronic Design Automation
Primary area: applications->everything_else
TL;DR: We use the distillation learning method to improve the accuracy of prediction of the information above the layout on the RTL level circuit.

Abstract: Accurate and efficient timing prediction at the register-transfer level (RTL) remains a fundamental challenge in electronic design automation (EDA), particularly in striking a balance between accuracy and computational efficiency. While static timing analysis (STA) provides high-fidelity results through comprehensive physical parameters, its computational overhead makes it impractical for rapid design iterations. Conversely, existing RTL-level approaches sacrifice accuracy due to the limited physical information available. We propose RTLDistil, a novel cross-stage knowledge distillation framework that bridges this gap by transferring precise physical characteristics from a layout-aware teacher model (Teacher GNN) to an efficient RTL-level student model (Student GNN), both implemented as graph neural networks (GNNs). RTLDistil efficiently predicts key timing metrics, such as arrival time (AT), and employs a multi-granularity distillation strategy that captures timing-critical features at node, subgraph, and global levels. Experimental results demonstrate that RTLDistil achieves significant improvement in RTL-level timing prediction error reduction, compared to state-of-the-art prediction models. This framework enables accurate early-stage timing prediction, advancing EDA's ``left-shift'' paradigm while maintaining computational efficiency. Our code and dataset will be publicly available at https://github.com/sklp-eda-lab/RTLDistil.

Bridging Layout and RTL: Knowledge Distillation based Timing Prediction
Mingjun Wang" 1234 Yihan Wen 52
Bin Sun 13 Jianan Mu
Juan Li
Xiaoyi Wang
Jing Ye 14 Bei Yu'
Huawei Li 134
Abstract
DFF1
DFF2
Accurate and efficient timing prediction the register-transfer level (RTL) remains funda- mental challenge in electronic design automation (EDA), particularly in striking a balance between accuracy and computational efficiency. While static timing analysis (STA) provides high-fidelity results through comprehensive physical parame- ters, its computational overhead makes imprac- tical for rapid design iterations. Conversely, ex- isting RTL-level approaches sacrifice accuracy due to the limited physical information avail- able. We propose RTLDistil, a novel cross-stage knowledge distillation framework that bridges this gap by transferring precise physical characteris- ties from a layout-aware teacher model (Teacher GNN) efficient RTL-level student model (Student GNN), both implemented as graph neu- ral networks (GNNs). RTLDistil efficiently pre- diets key timing metrics, such as arrival time (AT), and employs a multi granularrauu distillation strat- egy that captures ceriiicc features at node, subgraph, and global levels. Experimental results demonstrate that RTLDistil achieves significant improvement in RTL-level timing prediction ror reduction, compared to state-of-the-an predic- tion models. This framework enables accurate carly-stage timing prediction, advancing EDA's "left-shift" paradigm while maintaining computa- tional efficiency. Our code and dataset will be publicly available at http:://ithu..com/kippoa lab/RTLDistil.
Slow EDA Flow
OP2
Change Agate, topology
Generate parasitic param.
RTL
[0]
DFF3
Layout
RTL-level Timing mode!
Physical Lavout-level Timing model
CLK
Early stage for optimization / Accuracy X
Early stage for optimization X
(b)
Accuracy v
Figure 1: (a) Gap between RTL-level representation and layout-level representation in the chip design process. (b) RTL-level timing models provide faster and earlier predic- tions compared the slower and later layout-level models.
1. Introduction
Digital circuits constitute the cornerstone of contemporary computing infrastructure (Agarwal & Lang, 2005; Clements, 2006). As illustrated in Figure I(a), integrated circuit (IC) design involves a complex evolution spanning multiple stages of abstraction and representation paradigms (Chang, 1997; Chen et al., 2024). This progression moves from high- level behavioral descriptions to the topological interconnect of logic cells and ultimately culminates in transistor- and interconnect-level layout ready for physical manufactur- ing (Bryant et al., 2001). However, traditional EDA flows often follow a top-down, waterfall-like methodology, where performance bottlenecks typically emerge late in the de- sign cycle, resulting in lengthy verification and iteration periods (Wang al., 2009). Layout-level timing predic- tion is too late and too slow. Consequently, recent research efforts have advocated an EDA "left-shift", wherein perfor- mance prediction and issue detection are introduced at ear- lier stages- surc as the RTL level to facilitate more timely design adjustments and optimization of key metrics (Xing, 2024; Zeng, 2024).
"Equal contribution Sttte Key Lab of Processors, In- stitute Computing Technology, Chinese Academy of Sci- ences, China 'The Chinese University of Hong Kong, HKSAR l "University of Chinese Academy of Sciences, China CASTEST Co., Ltd., China Beijing University of Technology, China. Cor- respondence to: Jianan Mu <mujianan @ @ect.ac.cn>, Bei <byu@cse.cufhe www..cdu.hk...........
Proceedings of the 42nd International Conference Machine Learning. Vancouver, Canada. PMLR 267, 2025. Copyright 2025 by the author(s).

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Bridging Layout and RTL: Knowledge Distillation based Timing Prediction
As shown in Figure I(b), integrating such left-shift strate- gies not only lowers the cost of late-stage rework but also opens new avenues for pinpointing critical physical charac- teristics and performance bottlenecks sooner in the design flow (Jiang, 2024; Yang et al., 2022).
layout-aware timing characteristics RTL-level pre- dictions. This is a valuable early attempt apply the concept of knowledge distillation to the EDA domain.
Muati-Granularity Distillation Learning. We design alignment mechanisms at node, subgraph, and global levels to strengthen the model to capture layout fea- tures across different granularities. Each of the three granularities naturally corresponds to specific circuit structures relevant to timing.
However, as in Figure I(b), despite its efficiency for early- stage optimization, performing accurate performance anal- ysis and prediction at the RTL stage remains challeng- ing (Yang et al., 2015). Existing models, such as RTL- Timer (Fang et al., 2024), estimate timing by synthesizing RTL code without accounting for actual parasitic parame- ters, producing moderately accurate results. Yet a substan- tial gap persists between these RTL-based estimates and true post-layout timing. In contrast, layout-level timing analy- sis inherently incorporates more precise physical details- ranging from each cell's 's realistic Resistor and Capacitance (RC) parameters to complex interconnect RC models-thon delivering more reliable predictions (Huang et al., 2023). Our experiments indicate that even applying the state-of-the- art RTL model trained end-to-end with layout-level labels yields only around 60% accuracy in layout-level timing predictions.
Efficient Forward and Reverse Propagation. We de- velop a domain-specifiic asynchronous forward-reverse propagation strategy that balances accuracy with com- putational efficiency by combining the iterative for- ward and reverse propagation of the teacher model with a lightweight inference of the student model.
Experimental results on broad variety of circuits demon- strate that the proposed RTLDistil achieves impressive re- sults compared with state-of-thee the-art RTL-level timing pre- diction models. These results validate RTLDistil'ss i effec- tiveness in enabling accurate early-stage timing prediction, supporting the "left-shift" paradigm in industrial workflows while maintaining computational efficiency.
When compared with predicting the performance of post- synthesis circuit, the core bottleneck in accurately forecast- ing layout-level timing lies in the intricate physical param- RC catameterss-peseee in the actual circuit netlist (Sait& & Youssef, 1999). This dis- tribution critically affects the final timing but is difficult to derive purely from RTL descriptions (Kundert& & Zinke, 2005). Consequently, a critical question in early-stage per- formance prediction arises: how can one effectively extract such underlying physical layout phenomena from the more abstract RTT. representation? It is precisely at this juncture that knowledge distillation becomes especially relevant, of- fering a structured means to transfer these crucial physical insights.
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2. Background and Related Work
The research spans several domains, including traditional static timing analysis (STA). RTL-based timing prediction, the application of GNNs in EDA, and knowledge distillation (KD). Below, we summarize the relevant prior works and highlight the core challenges in this field.
Statie Timing Analysis and Timing Prediction. Static tim- ing analysis (STA) is a critical assessment in chip electronic design automation (EDA) for evaluating whether circuit satisfies timing constraints (Sapatnekar, 2018; Blaauw et al., 2008). By performing parasitic parameters extraction on the chip physical layout and the timing metrics in the pro- cess library, post-layout stage STA calculates precise timing metrics such as the arrival time (AT) at each flip-flop, the circuit worst negative slack (WNS), and the circuit total neg- ative slack (TNS) (Licastro, 2022; Chowdhary et al., 2005). However, analytical STA methods incur heavy runtime due to the complexity of delay propagation calculations (Guo et al., 2024b). Consequently, timing prediction methods have been widely explored in recent research.
To address these challenges, we propose a knowledge distil- lation framework, RTLDistil, which bridges the gap between the carly-stage RTL and the final layout design. Specifically, at the layout stage, a high-precision teacher model captures realistic physical effects through iterative forward and re- verse propagation. Simultaneously, a lightweight student model at the RTL stage assimilates critical timing charac- teristics, such as arrival time, by drawing this distilled knowledge. Adopting a cross-stage perspective, RTI.Dis- til employs a multi-granulard subgraph, and global levels) to enhance both precision and efficiency. The primary contributions of RTLDistil can be summarized as follows:
alignment strategy (node,
Layout-stage timing prediction methods emphasize extract- ing features from the physical layout and mapping them to the gate-level netlist corresponding to the process li- brary (Guo et al., 2022; Ye et al., 2023). These approaches enable direct prediction of timing metries with high ac- curacy. However, they are not suitable for meeting the
Pross-Stage Knowledge Distillation. We propose an efficient cross-stage learning approach that transfers
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Bridging Layout and RTL: Knowledge Distillation based Timing Prediction
requirements of RTL-level prediction. STA at the layout stage depends on complete mapping to the specific process library and physical layout, making it computationally ex- pensive and impractical for early design stages (Lienig et al., 2020). To support the EDA left-shift paradigm, which ad- vances critical tasks earlier in the design process (Guo et al., 2024a), several studies have explored early-stage timing estimation at the RTL level.
et al., 2023; Lopera et al., 2021b; Wang et al., 2025).
Some recent works (Fang et al., 2023; Zheng et al., 2024; Lopera & Ecker, 2022) applied GNNs to RTL-level cir- cuit modeling. However, these methods primarily rely on KTL-llevel features and fail to effectively integrate physi- cal characteristics at the layout stage, overlooking parasitic effects that significantly influence the prediction accuracy, These factors are challenging to model using RTL-level logical abstractions alone. Therefore, leveraging GNNs to combine RTL and layout information across stages remains critical and underexplored avenue for research.
On the other hand, some recent works utilize statistical or simplified models to predict the delay of critical paths to each register based on logical structures (Sengupta et al., 2023; Xu et al., 2022: Lopera et al., 2021a). While these methods enable RTL-level predictions, they exhibit signifi- cant inaccuracies due to the absence of physical characteris- tics, such capacitance and interconnect delays.
Knowledge Distillation. Knowledge Distillation (KD) is modeling technique that facilitates the transfer of repre- sentational and predictive capabilities from a high-capacity model (teacher) to a simpler counterpart (student) (Hinton, 5; Zhao et al., 2022; Tang et al., 2020). By guiding the student model to mimic the output distributions of the teacher model, KD enables the student achieve compara- ble performance with reduced complexity (Park et al., 2021; Cho & Hariharan, 2019). Traditional KD methods primarily rely on soft targets, where the student learns to approximate the teacher's output logits (Gou et al., 2021; Wang & Yoon, 2021). Recent advancements extend KD to intermediate feature representation, allowing the student model to learn hidden representations from the teacher, further enhancing its capability (Wang et al., 2021).
Recent works such as MasterRTL (Fang et al., 2023) and RTL--Timer (Fang et al., 2024) have made progress in RTL- based timing prediction. MasterRTL leverages a bit-level Simple Operator Graph (SOG) and multi-stage machine learning models to estimate TNS and WNS, while RTL- Timer employs bit-level graph structure with customized loss functions for fine-grained timing predictions at the reg- ister and design levels. However, these methods are lim- ited to RTL or gate-level abstractions and fail to effectively incorporate physical characteristics, such as parasitics, in- terconnect delays, and cell drive strengths (Jariwala, 2011; Kahng et al., 2011), 1). As a result, they struggle to achieve sign-off-leve accuracy and provide timing predictions that closely approximate the ground truth of layout-level timing information required in industrial workflows. Moreover, previous works focus on independent paths, which overlook the broader circuit environment, further limiting predictive accuracy.
In circuit design tasks, KD presents unique challenges due to the significant differences in features and dimensionality between RTL and Layout stages. The RTL stage focuses on high-level abstractions, such as logic functionality and registers distribution (Chu, 2006), while the Layout stage in- cludes detailed physical characteristics, such as capacitance, interconnect delay, and parasitic effects (Sherwani, 2012). Transferring high-fidelity physical characteristics from the teacher model to the student model is the key to achieving accurate and efficient timing prediction at the RTL stage. However, designing a KD framework capable of bridging such heterogeneous representations remains a significant challenge.
In conclusion, the existing body of work reveals a fundamen- tal challenge: relying solely on RTL-level logical properties for timing prediction cannot bridge the information gap, and directly depending on STA tools is impractical for rapid early-stage iterations. Consequently, transferring physical characteristics into RTL-level models to enhance prediction accuracy remains an open problem.
Graph Neural Networks in EDA. Graph neural networks (GNNs) have emerged as a powerful tool for modeling un- structured data and have been extensively applied in the EDA domain (Ma et al., 2020; Li et al., 2023). In circuit design, circuits are naturally represented as graphs, where nodes correspond to logic elements (e.g., registers, standard cells), and edges represent signal paths (Bairamkulov & Friedman, 2022). GNNs, through graph convolutions and attention mechanisms, can capture rich contextual informa- tion between nodes, demonstrating superior performance in tasks such as gate-level network modeling, congestion pre- diction, and power estimation (Ghose et al., 2021; Sánchez
3. Problem Formulation
Given a digital circuit in RTL format, represented as graph, G= (V, E), where V is the set of register/DFF nodes and the logic nodes, and E represents data flow edges, the goal is to predict the timing-related metrics, such as the arrival time (AT) AT (e) for each node V at the RTL stage. The ground truth of the arrival time from the layout stage is denoted as AT (v).
The objective is to minimize the error between the predicted and ground truth AT values across all register/DFF nodes,
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Bridging Layout and RTL: Knowledge Distillation based Timing Prediction
for example:
Table I: RTL SOG vs. layout netlist features.
1 IV
AT prea (v) - AT ATiabe (v)
Features
Type
Width
MAPEAT
(1)
(T (v)
SOG (Student)
VV
SOG cell type
One-hot
12
Fanout number
Int
where [V] is the total number of register/DFF nodes. The output is the predicted arrival time AT (t) for all regis- ter/DFF nodes E V, aligning with the layout-level timing characteristics.
Fanin number
Int
Depth Per Input (DPI)
Int
Depth Per Output (DPO)
Int
Total
16
Layout Netlist Graph (Teacher)
4. RTLDistil Overview
Gate cell type
One-hot
78
Gate Depth Per Input (DPI)
Int
We propose RTLDistil, dual-model framework compris- ing Teacher Model and a Student Model, to address the cross-stage timing prediction problem. The teacher model, operating on the layout-level Netlist Graph, utilizes high- capacity Graph Neural Network (GNN) to capture complex physical characteristics and generate accurate AT values. The student model, operating on the RTL SOG, employs a lightweight GNN for efficient inference, making suitable for large-scale RTL-stage prediction.
Gate input pins
Int
Cell drive strength
Int
Fanout capacitance (Rise, Fall)
Float
2
Fanout resistance
Float
Input slew (4 ares)
Float
Output slew (4 arcs)
Float
4
Delay (4 ares)
Float
4
Total
edges describe data flow relationships. Each node has a 16-dimensional feature vector, including operator types, fan-in/out characteristics, and operators' depth per input (DPIY/epth per output (DPO) values.
Figure 2 illustrates the proposed RTLDistil overall workflow. The approach includes four main steps: A Graph Con- struction: Extract the SOG from RTL and the Netlist Graph from Layout, with respective graph features for each stage.
Teacher Model Training: Train the teacher model using Layout data as features and labels to produce high-aceuracy AT values. Knowledge Distillation: Transfer the physi- cal knowledge encoded in the teacher model to the student model through three levels of granularity, enabling the stu- dent to efficiently predict AT at the RTL stage. D Student Model Fine Tuning: The student model undergoes further fine-tuning on downstream tasks, such as predicting timing information like AT.
The student model is lightweight graph neural network (GNN), as multi-head attention-based graph attention net- work (GAT), which generates 1 128-dimensional embeddings for each node. To ensure scalability, the student model only requires two rounds of forward-reverss asynchronous prop- agation to predict node-level timing metrics, such as arrival time (AT) and worst negative slack (WNS), while produc- ing low-dimensional embeddings embeddings for distillation.
By transferring physical characteristics on layout the RTL stage, this framework bridges the abstraction gap be- tween RTL and Layout stages, improving prediction accu- racy while maintaining computational efficiency.
Layout Netlist Graph and the Teacher Model. The Lay- out stage employs Netlist Graph, and nodes carry 96- dimensional physical features, including drive strength, ca- pacitance, parasitic resistance, capacitance, and LUT delays.
The teacher model is a bigger GAT that produces 512- dimensional embeddings and performs three rounds of forward-reverse asynchronous propagation to simulate re- alistic STA-like long-path accumulation while seeing a broader view of the surrounding circuitry. It outputs high- precision timing values while generating high-dimensional embeddings (DFFF for knowledge distillation.
5. Methodology and Model Design
5.1. Dual Graphs and Model Architecture
In cross-stage modeling, the RTL and Layout stages differ significantly in information dimensions and features. Ta- ble 1 contrasts the features of the Simple Operator Graph (SOG) used at the RTL stage, and the Netlist Graph em- ployed at the Layout stage, highlighting their dimensional and informational differences.
5.2. Forward-Reverse Propagation Strategy
To imitate the delay propagation of signals in circuit, both the teacher and student models utilize asynchronous forward-reverse propagation to update node representations, which capture the neighboring structure in the fanin and fanout cones, which illustrated by Figure 3. The forward
RTL SOG and the Student Model. The RTL stage uti- lizes Verilog/System Veriilo code to construct a simple op- erator graph (SOG). SOG nodes represent logical opera- tors (e.g., adders, logic gates, registers) or registers, while
4

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Bridging Layout and RTL: Knowledge Distillation based Timing Prediction
|
B
Arrival time
B
Student Model
RTL code
SClG graph + Abstract Featunes
FullGraph
I
Lanast limine
Saannd Truth
GNN
B
|
IDD
Teacher Madel
Layout
Notlist Physical Featunex
Graph Construction
B Teacher Model Training
Distillation from teacher to student model
Student Model Fine Tuning
Figure 2: Overview of the RTLDistil framework. The teacher model operates the layout netlist graph generate accurate physical timing metrics, while the student model operates on the RTL SOG for efficient inference. Knowledge distillation transfers timing information from the teacher to the student.
propagation update for node v at (i + de-depth per input node formulated as Eq. (2a):
Forward Update
(a)
R1
OP1
R3(0)
OP4
R4(0)
h
(++) =0
Σ (E)(1))
For For auv
(2a)
R1
(c)
OP2
OP3
R3
OP5
R4
R2 0
h(+1) =0
Σ (E)(
Re RewwReh Our
(2b)
Reverse Update
R1
OP1
R3
OP4
R4
where N(v) represents the forward neighboring nodes of node v; h denotes the feature vector of nodes; W denotes the linear transform weight and denotes the coefficients calculated by the attention mechanism in (Velickovic et al., 2017), where For means forward and Re means reverse. Similarly, the reverse propagation update for node v at (j + de-dephh per output node is formulated as Eq. (2b), where Rv)) denotes the reverse neighboring nodes of v.
R1
OP2
OP3
R3
OP5
R4
02
Asynchronous Forward-Reverse Propagation
(a)
(b)
(c)
Round
Figure 3: Asynchronous forward-reverse propagation strat- egy. The RTL SOG is used as an example to show a one- round flow.
Teacher Model. By leveraging complete physical features, the Teacher executes 2 2 rounds of forward-revent prop- agation. The forward pass accumulates path delays, while the reverse propagation spreads information about the sur- rounding circuitry situation, thus achieving timing analysis accuracy that is closer to the real physical layout.
suring effective representation alignment during distillation. This mechanism proved crucial to bridging the gap between abstract RTL data and high-accuracy physical layout-level timing insights.
Student Model. To ensure computational efficiency, the Student performs only propagation rounds for rapid node- level timing estimation. Despite fewer iterations, the Stu- dent compensates for its limited propagation through knowl- edge distillation by learning contextual information from the Teacher.
5.3. Multi-Granulan caatiiGranularity Knowledge Distillation
Multi- nulti-granullrityy knowledge distillation (KD) a corner- stone of the proposed RTLDistil framework for cross-stage timing prediction.
facilitates the transfer of physical knowledge from the teacher model to the student model across multiple granularity levels relevant to timing-nove node- level, subgraph-level, and global-level-enabinng the stu- dent to approximate the teacher's 's high-dimensional physical characteristics effectively and capture timing-critical tures at multiple scopes. This hierarchical strategy ensures
We actually emphasize domain-specift asynchronous forward-reverse propagation for iterative feedback from the sink node back to the source node, capturing RC parasitic and register slack constraints that typical GNNs cannot di- rectly encode. This strategy achieves high accuracy with the Teacher while maintaining the Student's efficiency, en-
critical fea-
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Bridging Layout and RTL: Knowledge Distillation based Timing Prediction
RTL-Jeve
Layoutelevel Netlist Graph
register/DFFF node. At the same time, align the dimension- ality between teacher and student embeddings, we employ two-layer MLP transformation MLPaligs align that projects the student's ' 228-dimensional embeddings to the same 512- dimensional space as the teacher's. This alignment network uses ReLU activation and maintains the semantic informa- tion while expanding the feature space.
Global-Levelr Distillation
R100
R1
R20
DFF2
DFF3
OP1
OP2
b. Subgraph
Level Distillation
OP4
OPG
Node-Level Distillation
Subgraph-Leeee Distillation. While node-level distillation aligns single-register features, may overlook the influence of surrounding logical structures. Subgraph-
R
R
DFF
DFFS
distillation addresses this by modeling the fan-in cone of each register, capturing its contextual logic depth, operation types, and timing dependencies.
Figure 4: Multi-granularinn knowledge distillation frame- work. Knowledge hierarchically transferred from the Teacher the Student across three levels: (a) Node-Level, (b) Subgraph-Level. and (c) Global-Level Distillation. The RTL.-level SOG and Layout-level Netlist Graph are aligned to enable accurate cross-stage timing prediction.
For a register/DFF node v. the fan-in cone subgraph is de- noted as (v), representing the sub-circuit encompassing all combinational logic between e and its contributing regis- ters within a single clock cycle. The fan-in cone of a target register is determined by traversing the SOG or netlist graph forward from node collecting all logic gates and connections that influence node v, until the traversal termi- nates at other registers/DFFs. It serves as an intermediate granularity that bridges the gap between fine-grate mne-grained node- level features and the global circuit graph, enhancing model adaptability for various timing prediction tasks.
that the student model comprehensively learns physical tim- ing dependencies, capturing both local and global circuit behaviors to predict AT, WNS, and TNS robustly during the RTL stage.
Traditional KD methods align the output distributions of a large teacher model and a lightweight Student model by minimizing their divergence. However, in cross-stage tim- ing prediction, the sigmificant differences between RTL and Layout feature spaces render output-only alignment insuf- ficient. To address this, we design multi- granulartttl KD strategy that hierarchically transfers knowledge from the Teacher to the Student, ensuring comprehensive learning of physical characteristics across granularities, as illustrated in Figure 4.
For subgraph-level distillation, the Teacher and Student generate subgraph embeddings e (v) and embedding (Grus (w)).. These embeddings are aggregated using mean pooling over the nodes in (v and aligned using the smooth L1 loss:
Lsubgraph
Σ
smoothy, (embeddinn,
M
BEV
ML (embeddiiggs
Node-Level Distillation. Node-level distillation focuses on aligning the feature representations of individual regis- ter nodes (DFF-level) to ensure that the Student accurately learns the timing properties of each register/DFF. For a register/DFFF node u, the Teacher and Student generate em- beddings embedding, (v) and embeddings(t). These em- beddings are directly compared using the smooth L1 loss, defined as:
This loss encourages the Student to capture the logic and timing interactions within each register's 's fan-in cone and to focus more on the local timing-relevant information related to each register.
Global-Level Distillation. Global-level distillation aligns the representations of the entire circuit to ensure that the Student learns global timing distributions and long-term dependencies. This strategy is particularly effective in cor- recting biases induced by variations in circuit scale and structure.
LRez
smoothr,, (embedding,,
V
VEV
(3)
MLP align (embedding:(())),
where |V] is the total number of registers/DFF nodes, and the smooth L, loss is given by:
The Teacher and Student generate global embeddings (9be and embeddingg for the entire circuit graph G using mean pooling. The global embeddings are aligned with the smooth L, loss:
0.5(z - -. | yl < 1, (4) |z yl - 0.5, otherwise.
smooths,
This loss ensures that the Student Model's feature repre- sentations align closely with those of the Teacher for each
Lglobal smooths, (embedding,,
(6)
MLP align (embeddings(()))
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Bridging Layout and RTL: Knowledge Distillation based Timing Prediction
By minimizing Lighbbl. the Student aligns with the Teacher's global characteristics, improving its ability to capture criti- cal paths across the circuit.
"super-convergent" setting and instead generate diverse yet high-quality layouts that are more representative of indus- trial standards. Our approach reflects robust and converged implementation quality, providing meaningful basis for our timing prediction framework.
Integrated Distillation Loss. The total distillation loss com- bines the contributions of node-level, subgraph-level, and global-level losses, along with supervised timing prediction losses:
Importantly, this means our model is not tuned to predict timing under a specific tool configuration, but rather aims to approximate the best achievable timing performance after re- alistic optimizationan objective more aligned with industrial design goals.
Lioall supervised (AT) to + 8 Laubgraph + Ligobal, (7)
where Lappervised (AT) ensures that the Student's predictions for arrival time (AT) align with ground truth, and the weights a, 3, y are hyperparameters controlling the relative impor- tance of each distillation granularity. They are tuned based on grid search for optimal performance.
For dataset splits, circuits are split into 80% for training, 10% for validation, and 10% for testing, ensuring a fair eval- uation of the model's s ability to generalize across different circuits.
Through iterative gradient descent, the Student progressively aligns its feature representations and timing predictions with the Teacher.
Evaluation Metrics. We evaluated timing predictions for arrival time (AT). worst negative slack (WNS), and total negative slack (TNS) using three standard metrics: (1) Pear- son correlation coefficient (PCC), which assesses the linear correlation between predictions and ground truth; (2) Coeffi- cient of determination (R²), which measures the proportion of variance explained by the model; (3) Mean absolute per- centage error (MAPE), which Quantifies prediction error as a percentage of ground truth, with lower values indicating better performance.
6. Experiments and Implementation Details
6.1. Experimental Settings
Datasets. To enable a comprehensive evaluation of seal- ability and adaptability, we collected 2004 RTL designs with diverse functionalities and complexities sourced from platforms including GitHub, Hugging Face, OpenCore, and RISC-V V projects to reflect real-world industrial needs, in- cluding small arithmetic blocks, DSP modules, RISC-V subsystems, etc. This makes the prediction task harder, but we think it's more practical, pervasive, industrially valu- able, and closer to the needs of actual industrial processes. In constructing our dataset, we designed unified, fully- automated back-end flow using otate-of-the-art commer- cial tools-Synopsys Design Compiler (DC) and Cadence Innovus a consistent set of optimization switches (e.g., gate sizing, buffer insertion, cell movement, etc.). However, the circuits in our dataset were not finalized under a single fixed configuration. For each design and each back- end aptimizatioo-relatte parameter (e.g., density thresholds, routing constraints, clock constraints), we automatically tried multiple sets of values and iteratively explored multi- ple different configurations, often conducting tens of design runs, until the circuit reached state where:
Platform Configuration. Experiments were conducted on 8 NVIDIA A100 GPUs, and models were implemented using Py PyToorch and PyTorrch Geometric (PyG). The optimiza- tion employed the Adam optimizer with an initial learning rate of 2 x 10-1 and batch sizes of 8. Multi-granularity knowledge distillation used grid-searched weights for node- level (a), subgraph-level (3), and global-level (7) distil- lation. With the change of loss weights, we observed small fluctuations across different metrics and believed that the optimal balance varies depending on the data proper- ties, circuit complexity, and the focus of the task objective. Through a coarse graunne-griindd grid search, we find equal weights (a = 3 7) that exhibit superior multi-task average perfor- mance, thereby clarifying the ablation experiments.
6.2. Comparison with Existing Models
We compared RTLDistil against two state-of-the-art (SOTA) models, MasterRTL (Fang et al., 2023) and RTL- Timer (Fang et al., 2024), which represent current advance- ments Raleb timing prediction. We used their open- source code for comparison. Table lists the comparison results. RTLDistil demonstrates consistent superiority over the previous SOTA methods across all metrics.
Placement density no longer increased, and
Timing metries converged stably through repeated op- timization.
This convergence point serves as a practical proxy for phys- ical design quality, reflecting an optimization level com- parable to that of manually refined industrial flows. By doing so, we avoid biasing our dataset toward a singular
Specifically, as shown in Table 2, for AT, RTLDistil achieves a PCC of 0.9227, significantly surpassing MasterRTL (0.3498) and RTL-Timer (0.8782). Additionally, RTLDistil
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Bridging Layout and RTL: Knowledge Distillation based Timing Prediction
Table 2: Comparison of MasterRTL, RTL-Timer, and RTLDistil on timing prediction tasks.
Arrival Time (AT)
Worst Negative Slack (WNS)
Total Negative Slack (TNS)
Model
PCC
R
МАРE
PCC
R
MAPE
PCC
R
MAPE
MasterRTL. (Fang et al., 2023)
0.3498
-0.8718
81.20%
0.7381
0.5161
61.88%
0.6255
-0.2967
65.26%
RTI--Timer (Fang et al., 2024)
0.8782
0.7568
23.39%
0.8812
0.7596
40.55%
0.8451
0.6114
40.31
RTLDistil (Full Model)
0.9227
0.8486
16.87 %
0.9066
0.8141
31.37% %
0.9586
0.9181
37.95 %
MasterRTL and RTL-Timer previous state-of-the-ard (SOTA) models. RTLDistil outperforms both in all timing metrics.
Table 3: Performance of Layout Teacher Model, RTL Student Model-RTI.Disti (without Distillation, without Fine Tuning,
and Full Model with Distillation & Fine Tuning).
Arrival Time (AT)
Worst Negative Slack (WNS)
Total Negative Slack (TNS)
Model
PCC
R
MAPE
PCC
R
MAPE
PCC
R²
MAPE
Layout Teacher Model
0.9797
0.9583
11.20%
0.9580
0,9112
19.87%
0.9901
0.9802
21.86%
RTLDistil (w/o Distillation)
0.8787
0.7554
22.04%
0.8658
0.6919
37.37%
0.9100
0.8216
40.31%
RTLDistil (w/o Fine Tuning)
0.9107
0,8231
17.77%
0.8874
0.7849
32.84%
0.9468
0.8955
33.30%
RTLDistil (Full Model)
0.9227
0.8486
16.87 %
0.9066
0.8141
31.37% %
0.9586
0.9181
37.95%
RTLDistil (w/ Distillation) refers to RTLDistil trained without knowledge distillation. RTLDistil (w/o Fine Tuming) refers to RTLDistil trained after knowledge distillation but without Fine Tuning.
reduces the MAPE to 16.87%. For WNS and TNS, RTLDis- til achieves PCC values of 0.9066 and 0.9586, outperform- ing RTL-Timer by 2.88% and 1 11.35%, respectively. The reductions in MAPE across WNS and TNS further empha- size RTLDistiil' ' ability to closely approximate layout-level timing.
timing. RTLDistil without Fine Tuning demonstrates a sub- stantial improvement over RTLDistil without Distillation, reducing the AT MAPE to 17.77%, which underscores the effectivvness of the knowledge transfer from the teacher model. Further downstream fine-tuning enhances RTLD- istil's 's accuracy, achieving a PCC of 0.9227 and an MAPE of 16.87% for AT. These results confirm that RTLDistil can closely approximate the teacher model's performance while maintaining computational efficiency, demonstrating its practicality for early-stage timing prediction and opti- mization.
This consistent improvement across all metrics demonstrates the efficacy of the multi multi-graaulariity knowledge distillation strategy in bridging the abstraction gap between RTL and layout stages, enabling accurate and reliable timing predic- tions at the RTL level. The RTLDistil's high performance is sufficient for early-stage RTL optimization, allowing the design flow to shift left.
6.3. Ablation Study
Ablation Study on Multi-Granularity Distillation. Ta- ble 4 compares each ablation setting with a baseline that excludes all distillation. The RTLDistil (Full Model) config- uration, which jointly employs node-, subgraph- and global- level distillation, achieves the highest correlation gains in Arrival Time (AT), Worst Negative Slack (WNS), and Total Negative Slack (TNS). Specifically, it boosts APCC by up to 0,0486, A A22 by up to 0. and consistently lowers AMAPE across the three metrics. A closer inspection of the partial variants clarifies the role of each distillation level. Node-Ievel distillation alone captures fine-grained register features, ignoring the global information, occasionally pro- ducing large AMAPE improvements (c.g.. 5.64% on AT, - 8.53% on WNS), but it yields weaker performance in cor- relation metrics (PCC, R) for AT, WNS, and TNS overall than the full model, not giving the best results. Incorporat- ing subgraph-leve information further exploits local fan-in cones, improving contextual sensitivity. Meanwhile, global- level distillation refines cireuit-wide alignment, preventing
Teacher-Student Model Evaluation. We also conducted a high-capacity Layout Teacher Model trained on physical features and an RTL Student Model trained without knowl- edge distillation to analyze the role of multi- granularity knowledge transfer.
Table 3 compares the performance of the Layout Teacher Model, the RTL Student Model-RTLL RTLDistil (without Distil- lation, without Fine Tuning, and Full Model with Distilla- tion& & Fine Tuning), offering insights into the effectiveness of the proposed knowledge distillation framework. The Layout Teacher Model achieves the highest performance across all metrics, achieving a PCC of 0.9797 and a MAPE of 11 11.20% for AT, thereby establishing an upper bound RTLDistil's achievable accuracy. In contrast, RTLDistil without Distillation, which lacks knowledge distillation, ex- hibits significantly lower accuracy, with an AT MAPE of 22.04% This result highlights the inherent limitations of relying solely on RTL-level features to predict layout-level
8

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Bridging Layout and RTL: Knowledge Distillation based Timing Prediction
Table 4:
Ablation study on RTLDistil components, measured as the difference in performance relative to the RTLDistil
model without distillation.
Ablation
Arrival Time (AT)
Worst Negative Slack (WNS)
Total Negative Slack (TNS)
Configuration
APCC
AR
AMAPE
APCC
ARt
AMAPE
APCC
AR'
AMAPE
RTLDistil (Full Model)
0.0440
0,0932
-5.17%
0.0480
0.1222
-6.00%
0.0486
0.0965
-2.36%
RTLDistil (w/ Node)
-0.0038
0.0750
-5.64%
0.0195
0.0413
-8.53%
0.0022
0.0046
-6.90%
RiTDistti (w/ Node & Global)
0.0254
0.0710
-5.42%
0.0336
0.0946
-7.30%
0.0300
0.0410
10.19%
RTLDistil (w/ Subgraph & Global)
0.0071
0.0339
-4.35%
0.0204
0.0655
-5.51%
0.0105
0.0134
-8.70%
Ablation settings measure the performance difference (A) between each configuration and the RTLDistil model without distillation. Node, Subgraph, and Global are respectively shorthand for node-level, subgraph- and global-level distillation.
Positive APCC and A indicate improved performance, while negative AMAPE indicates reduced error.
biases that purely local methods may overlook. Conse- quently, partial combinations like (w/ Node & Global) or (w/ Subgraph & Global) often enhance AMAPE in TNS more aggressively but do not achieve the strong correla- tion improvements delivered by the full multi--ranularrty approach.
0.5
0.3
0.4
Liotal
Leng
0.3
0.2
0.2
0.1
25
50
75
100
25
50
75
100
These observations highlight that simultaneously capturing localized node-level timing details, subgraph-level contexts, and holistic circuit characteristies offers the best balance between reduced timing error and improved predictive cor- relation at the RTL stage.
Training Epoches
Training Epoches
(a) Total distillation loss
(b) Node-Level loss
1.0
0.20
Lobbrraph
0.8
Lgvobll
0.15
Analysis of ure 5 illustrates the training dynamics of the multi- granularity knowledge distillation process, showcasing the hierarchical alignment between the teacher and student mod- els. The total distillation loss (Tumaa) steadily declines and converges, indicating successful overall alignment. The node-level distillation loss (TRey) decreases rapidly and stabilizes carly, reflecting the efficient alignment of local register-level features, while the subgraph-level distillation loss (Lsubgrapp) declines more gradually, capturing contex- tual relationships within fan-in cones. The global-level distillation loss (Lglobal) starts higher due to the complexity of global timing distributions but steadily reduces, demon- strating the model's 's ability to capture overall circuit informa- tion. These results validate RTLDistil's 's hicrarchical strategy, where muult--gaauulartyy alignment ensures comprehensive learning of timing dependencies and progressively improves prediction accuracy.
Distillation Losses. Fig-
0.6
0.10
0.05
0
25
50
75
100
25
50
75
100
Training Epoches
Training Epoches
(c) Subgraph-Level loss
(d) Global-Level loss
Figure 5: Losses of multi multi-granularrty knowledge distillation.
7. Conclusion
This paper presents RTLDistil, a cross-stage knowledge dis- tillation framework that bridges the abstraction gap between RTL and Layout stages by transferring figh-precision phys- ical characteristics from layout stage Teacher Model to an RTL Student Model. Through mullt-granularity distilla- tion at the node, subgraph, and global levels, the framework achieves layout-level accuracy in timing prediction while ensuring high inference efficiency. The proposed method significantly improved with less MAPE and larger R22 than the SOTA models in timing evaluation, making suitable for early-stage design optimization. Future extensions in- clude scaling to large SoC designs, incorporating multi- clock domain constraints, and integrating multi-objective optimization for power and area, thereby further enhancing its applicability to industrial chip design workflows. We believe RTLDistil is a valuable early attempt to apply the concept of knowledge distillation to the EDA domain and contributes potentially to AI4EDA and EDA's "Ieft-shift".
The experimental results comprehensively demonstrate that RTLDistil achieves state-of- -ftc-----hhharrrr the-art performance in timing prediction at the RTL stage. By leveraging multi-granularit knowledge distillation, RTLDistil successfully bridges the abstraction gap between RTL. and layout stages, achieving high prediction accuracy. These findings confirm RTLDis- til's potential as a practical solution for early-stage timing optimization in industrial EDA workflows.
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Bridging Layout and RTL: Knowledge Distillation based Timing Prediction
Acknowledgement
Clements, A. Principles of computer hardware. Oxford University Press, USA, 2006.
This paper is supported in part by the Chinese Academy of Sciences under grant No. XDB0660103, and in part by the National Natural Science Foundation of China (NSFC) under grant No.( 62090024).
Fang, W., Lu, Y., Liu, S., Zhang, Q. Xu, C., Wills, L. W.,
Zhang, H., and Xie, Z. MasterRTL: A Pre-Synthesis PPA Estimation Framework for Any RTL Design. In IEEE/ACM International Conference on Computer-Aided Design (ICCAD), pp. 1-9. IEEE, 2023.
Impact Statement
This paper presents work whose goal is to advance the field of Machine Learning. There are many potential societal consequences of our work, none which we feel must be specifically highlighted here.
Fang, W. Liu, S., Zhang, H., and Xie, Z. Annotating slack directly on your verilog: Fine-grained rtl timing evaluation for early optimization. In ACM/EEE Design Automation Conference (DAC), pp. 1-6, 2024.
Ghose, A., Zhang, V., Zhang, Y., Li, D., Liu, W., and Coates, M. Generalizable cross-graph embedding for gnn-based congestion prediction. In /EEE/ACM International Con- ference on Computer-Aided Design (ICCAD), pp. 1-9. IEEE, 2021.
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Bridging Layout and RTL: Knowledge Distillation based Timing Prediction
A. Appendix: Performance Correlation and Comparative Analysis
This appendix section provides detailed analysis of the performance of different models for timing prediction, specifically focusing on Arrival Time (AT), Worst Negative Slack (WNS), and Total Negative Slack (TNS). The correlation plots in Figures 6, 7, and illustrate the relationship between the predicted values and the ground truth for each metric. These plots compare the results of MasterRTL, RTL-Timer, RTLDistil without distillation, and RTLDistil with distillation. The red solid line represents the ideal 1 correlation, where the predicted values perfectly match the ground truth, while the dashed black lines mark the 30 confidence boundaries, which provide a statistical measure to evaluate the consistency and reliability of predictions by identifying significant deviations. The evaluation highlights the improvements brought by the RTLDistil framework, particularly after incorporating the multi gualti-ranularity knowledge distillation process.
A.I. Arrival Time (AT) Correlation Analysis
Oound Becturr
Sound Botva
Coand Ba
Gownd Buti
(a) MasterRTL
(b) RTL-Timer
(c) RTLDistil Without Distillation (d) RTLDistil With Distillation
Figure 6: Arrival Time (AT) correlation plots for different models. The proposed RTLDistil with distillation exhibits the best alignment with ground truth AT values.
Figure 6 presents the correlation plots for Arrival Time (AT) predictions across four models: MasterRTI, RTL-Timer, RTLDistil without distillation, and RTLDistil with distillation. The red solid line represents the ideal 1 correlation, while the dashed black lines mark the 3a confidence boundaries. These plots highlight the progressive improvements achieved by RTLDisti in aligning predictions with ground truth AT values.
In Figure 6(a), MasterRTL exhibits significant scatter, with many predictions deviating beyond the 3o boundary, indicating poor alignment due to its inability model physical characteristics effectively. Figure 6(b) shows that RTL-Timer improves correlation but still suffers from noticeable outliers, reflecting limited accuracy in capturing timing dependencies.
Figure 6(c) demonstrates that RTLDistil without distillation further reduces scatter, achieving better alignment with the 1:1 line. However, some deviations persist, highlighting the need for more robust physical information transfer. Finally, Figure 6(d) shows that RTLDistil with distillation achieves the best alignment, with predictions tightly clustered along the 1: line and well within the 30 boundary. This improvement attributed to the multi- granularity knowledge distillation strategy, which transfers physical timing characteristics from the teacher model to the student model, effectively bridging the abstraction gap between RTL and layout stages.
In summary, RTLDistil with distillation significantly outperforms prior methods, demonstrating its ability to achieve highly accurate AT predictions by capturing surrounding circuit information and leveraging layout-level knowledge.
A.2. Worst Negative Slack (WNS) Correlation Analysis
Figure 7 illustrates the correlation plots for Worst Negative Slack (WNS) predictions across four models: MasterRTL, RTL-Timer, RTLDistil without distillation, and RTLDistil with distillation. The red solid line represents the ideal 1 correlation, while the dashed black lines indicate the 30 confidence boundaries. These plots evaluate how well each model predicts critical timing violations in a circuit.
In Figure 7()), MasterRTL shows poor alignment with ground truth WNS values, characterized by significant scatter and numerous points falling outside the 30 boundary. This reflects the model's 's inability to capture critical physical timing
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Bridging Layout and RTL: Knowledge Distillation based Timing Prediction
Groad Tush ANC
Oruud Gruid PariAR
Gruud Tuts WMC
(a) MasterRTL
RTL-Timer
RTLDistil Without Distillation (d) RTLDistil With Distillation
Figure 7: Worst Negative Slack (WNS) correlation plots for different models. The proposed RTLDistil with distillation achieves the closest alignment with ground truth WNS values.
dependencies due to its reliance on logical abstractions. Figure 7(b) demonstrates that RTL-Timer improves over MasterRTL by reducing scatter and outliers, achieving moderate alignment with the line. However, it still struggles to accurately predict severe timing violations.
Figure 7(c) presents the performance of RTLDistil without distillation, which further reduces the number of outliers and achieves better alignment with the 1 line. While this indicates improved predictive capability, some deviations persist due to the lack of physical knowledge transfer. Finally, Figure 7(d) shows that RTLDistil with distillation achieves the closest alignment, with predictions tightly clustered along the line and most points well within the 30 boundary. This highlights the effectiveness of the multi-granularity knowledge distillation framework in transferring critical physical characteristics from the teacher model to the student model, enabling precise WNS predictions.
In summary, RTLDistil with distillation outperforms all prior methods, demonstrating its ability to accurately predict WNS by bridging the abstraction gap and effectively incorporating layout-level timing information into RTL-stage models.
A.3. Total Negative Slack (TNS) Correlation Analysis
GrunsTurm
Grond Tusk 795
GraesTurre
Grees
(a) MasterRTI.
RTI.-Timer
RTLDistil Without Distillation (d) RTL.istii With Distillation
Figure 8: Total Negative Slack (TNS) correlation plots for different models. The proposed RTLDistil with distillation achieves the best alignment with ground truth TNS values.
Figure illustrates the correlation plots for Total Negative Slack (TNS) predictions, which quantify the aggregate severity of timing violations in circuit. The red solid line represents the ideal correlation, while the dashed black lines indicate the 3o confidence boundaries. These plots reveal the progressive improvements achieved by RTLDistil in predicting TNS values accurately.
In Figure 8(a), MasterRTL performs poorly, with significant seatter and numerous predictions deviating beyond the 30 boundary. This highlights its inability to capture critical timing dependencies due to the absence of physical characteristics its modeling. Figure 8(b) shows that RTL-Timmr improves upon MasterRTL., reducing seatter and aligning better with the
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Bridging Layout and RTL: Knowledge Distillation based Timing Prediction
line. However, it still suffers from noticeable outliers, limiting its reliability in predicting TNS.
In Figure 8(c), RTLDistil without distillation achieves further improvements, with reduced scatter and better alignment with ground truth TNS values. However, some deviations persist, reflecting the challenges of accurate timing prediction without knowledge transfer. Finally, Figure 8(d) demonstrates that RTLDistil with distillation achieves the best aligmment, with predictions tightly clustered along the 1 line and most points well within the 30 boundary. This superior performance is attributed to the multi-granullrity knowledge distillation framework, which transfers critical physical characteristics from the teacher model the student model, enabling precise modeling of aggregate timing violations.
In conclusion, RTLDistil with distillation significantly outperforms prior approaches in TNS prediction, effectively bridging the abstraction gap between RTL and layout stages. By leveraging the forward-reverse propagation strategy and incorporating physical knowledge, RTLDistil enables highly accurate and reliable TNS predictions, critical for early-stage design optimization.
The correlation plots for AT, WNS, and TNS demonstrate the progressive improvements achieved by RTLDistil, particularly after incorporating the multi-gramularity knowledge distillation process. RTI.isttil with distillation consistently outperforms MasterRTL, RTL-Timer, and RTLDistil without distillation across all timing metries. By effectively transferring physical characteristics from the teacher model to the student model, RTLDistil bridges the abstraction gap between RTL and layout stages, achieving superior timing prediction accuracy. These results highlight the practical applicability of RTLDistil in early-stage design optimization workflows.
B. Appendix: Analysis of Forward and Reverse Propagation Strategies
In this appendix section, we analyze the impact of different propagation strategies on the performance of the RTL-level student model. Specifically, we investigate how varying the number of forward (F) and reverse (R) propagation passes affects the model's ability to predict timing-critical metrics, including Arrival Time (AT), Worst Negative Slack (WNS), and Total Negative Slack (TNS). This analysis is conducted on set of challenging timing benchmarks, which were selected for their high complexity and difficulty. These benchmarks were used to train downstream tasks with the RTL model under various propagation configurations.
B.1. Experimental Setup
We experimented with several combinations of forward and reverse propagation passes, including:
(Forward Reverse): A single round of forward and reverse propagation.
2 (Forward + Reverse): Two rounds of forward and reverse propagation.
2 Forward: Two forward-only propagation passes.
5 (Forward + Reverse): Five rounds of forward and reverse propagation.
The experiments aim to demonstrate that: 1. A combination of forward and reverse propagation outperforms forward-only propagation by capturing bidirectional dependencies in the circuit graph. 2. Neither too few nor too many forward and reverse passes are optimal; instead, a balanced configuration achieves the best performance.
B.2. Results and Discussion
The results of the experiments are summarized in Table 5. Key observations are as follows:
Forward + Reverse vs. Forward-Only: The results show that configurations with both forward and reverse propagation consistently outperform forward-only configurations. For instance, the "2 (Forward Reverse)" model achieves higher Pearson Correlation Coefficients (PCC) and R² values across all metrics compared to the "2 Forward" model. Specifically, for WNS, the PCC improves from 0.8815 to 0.8870, and the Mean Absolute Percentage Error (MAPE) increases slightly from 33.21% % to 36.87% This demonstrates that reverse propagation effectively captures timing dependencies and wider range of information about the surrounding circularity that forward propagation alone cannot.
Optimal Number of Passes: Among the configurations tested, "2 (Forward + Reverse)" achieves the best balance between performance and computational complexity. achieves the highest PCC for AT (0.8446), the best R² for TNS
15

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Bridging Layout and RTL: Knowledge Distillation based Timing Prediction
Table 5: Performance comparison of different propagation strategies for the RTL-level student model.
Arrival Time (AT)
Worst Negative Slack (WNS)
Total Negative Slack (TNS)
Propagation Strategy
PCC
R22
MAPE
PCC
R²a
MАРE
PCC
R2
MAPE
I (Forward + Reverse)
0.8328
0.6742
23.10%
0.8794
0.7599
34.30%
0.8788
0.7685
36.38%
(Forward + Reverse)
0.8446
0.6808
24.63%
0.8870
0.7507
36.87%
0.8875
0.7860
40.18%
2 Forward
0.8373
0.6805
24.80%
0.8815
0.7601
33.21 %
0.8801
0.7590
38.03%
(Forward + Reverse)
0.8325
0.6456
24.33%
0.8820
0.7280
35.51% %
0.8786
0.7675
41.58%
Propagation Strategy: Different combinations of forward (Forward) and reverse (Reverse) passes used during training and testing.
(0.7860), and competitive MAPE across all metrics. In contrast, "1 (Forward + Reverse)" underperforms due to insufficient propagation depth, while "5 (Forward Reverse)" shows slight degradation in performance, likely due to overfitting or noise amplification from excessive propagation. This finding highlights the importance of selecting an appropriate number of propagation passes.
The "5 (Forward + Reverse)" configuration demonstrates diminishing returns and even slight performance degradation compared "2 (Forward Reverse)." For example, the MAPE for TNS increases from 40.18% 41.58% This suggests that excessive propagation may introduce noise or overfit the model spurious relationships in the graph, reducing its generalizability.
Impact of Pver-Propagttion:
B.3. Implications of Results
These findings provide strong evidence for the effectiveness of our propagation strategy. The combination of forward and reverse propagation enables richer contextual learning by incorporating bidirectional information flow, which is critical for accurately modeling timing dependencies in circuit graphs. Moreover, the experimental results validate our hypothesis that an optimal balance of propagation rounds is necessary for achieving the best performance. Too few passes fail to capture sufficient information, while too many passes may amplify noise or cause overfitting.
The results presented in this section reinforce the effectiveness of the proposed Norward-reverss propagation strategy in the RTL-level student model. By carefully selecting the number of propagation passes, our approach achieves state-of-the-aa art performance on timing-critical tasks, demonstrating its suitability for challenging benchmarks with high timing complexity. These findings further substantiate the robustness and generalizability of our method for early-stage timing prediction in industrial workflows.
C. Appendix: Expanded Mathematical Formulation of Knowledge Distillation
This appendix further extends the mathematical details of our cross-stage Knowledge Distillation (KD) process, emphasizing the core principles behind node-level. subgraph-level, and global-level alignment. We focus on equations and derivations with minimal textual explanation while ensuring clarity and correctness.
C.1. Preliminaries and Notation
GT (V, E): Graph representing the circuit (layout) for the Teacher model, with [V] nodes.
G (V. E): Graph representing the circuit (RTL) for the Student model, with [V] nodes.
T - dr de: Final-layer embeddings for node from Teacher and Student, respectively (typically dr ds).
M dR + Rd:; Learnable alignment transform (e.g., an MLP) that maps Student embeddings to the Teacher's embedding space.
|| lpp: p-norm (often 1 p 2), used for measuring distance between vectors.
(xx,))L((x,y)) The smooth L1 (a.k.a. Huber) loss between vectors x and defined as
2 (x: - yz) if [x - Vıl < otherwise.
smoothLl(x.y)- =
Σ mm1
(8)
[ Val
16

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Bridging Layout and RTL: Knowledge Distillation based Timing Prediction
This function behaves quadratically (like L.2) near and transitions linear (L1) penalty for larger errors, thus often providing more robust gradient profile than purely L1 or 1.2.
C.2. Teacher Student Outputs
We consider the Teacher model having more rounds of forward-reverse propagation and seeing rich physical layout features. The Student sees only RTL features with fewer propagation steps:
Teacher forward-reverse. r-round propagation formulated as:
The forward propagation update for node at (i (i+ deepth from input DFF node (DPI) in
h ((+1),r =
Ova Forword W Porward (.)r) i= Levelp.r
(9)
(EN(()
where (V)) represents the forward neighboring nodes of denotes the feature vector of nodes; W denotes the linear transform weight and a denotes the coefficients calculated by the attention mechanism in (Velickovic et al., 2017). Similarly, the reverse propagation update for node at (j + 1) deptt from output DFF node (DPO) in r-round is formulated as: vu
h h(++)rr
Reverse W Reverse Reeersee
( h()))r)
O,... Levelpro.
(10)
(ER(e)
where R(v) denotes the reverse neighboring nodes of The teacher typically uses more rounds (Rr) capture stronger physical effects.
hy
Rt
z
(11)
Student forward-reverse. Student model share the same revvere propagation with teacher model. The student model typically uses less rounds (Rg) to ensuring the reference efficiency.
h - 8
(12)
where Rs Rr, reflecting fewer propagation rounds.
C.3. Basic KD Approaches (Distribution- -Based)))
In classification-styee KD, one often aligns teacher and student soft targets p and p
Softmax s
Softmax D
(13)
where > 0 is the temperature. The classical KD objective is:
72
ExT(pt P..).
LiD,
(14)
V VEV
KL(a|b) Σ ag log
(15)
b
which encourages the Student distribution pd approximate p"
However, in regression-focused timing prediction, instead align continuous embeddings real-valued outputs (e.g.. arrival time). Below, we detail node-level, subgraph-level, and global-level alignment for feature-based KD.
C.4. Feature-Based KD for Timing (Multi-Granularity)
C.4.1. NOVE-LEVEL FEATURE ALIGNMENT
Each node yields final embeddings 2. z To align dimensions, define:
z S,aliga
(Z.)).
(16)
17

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Bridging Layout and RTL: Knowledge Distillation based Timing Prediction
Then common choice is the L1 Ly distance:
Lndde
Z
Stalinn
(17)
BEV
This captures fine-grained alignment at each node (c.g., each register).
C.4.2. SUBGRAPH-LEEVE FEATURE ALIGNMENT
For local contextual alignment, let (()) be s's subgraph (e.g., fan-in cone). We pool Teacher embeddings:
Q² (v) Pool(zz, प : u G² (b)).
(18)
and similarly for the Student:
Qº (v) Pool(z, E G (v)
(19)
Applying M.
Σ ( (()))
Laub
(20)
This enforces local structural insight in the Student.
C.4.3. GEOBAL-LEVEI FEATURE ALIGNMENT
We also encourage global similarity:
g" = Pool 25 VVE],
= Pool =o
(21)
leading to
Cglobal
g" - M(g
(22)
This term addresses overall circuit-level properties (e.g., average load or total distribution shifts).
C.5. Overall Distillation Objective
In addition to the above feature-based losses, we incorporate a supervised term, Lxups that aligns the Student's predicted timing metrics (e.g., arrival time AT with reference labels AT (Teacher or sign-off data). Hence,
Liotal
Leup Luode 3 Laub + y Eglobal.
(23)
where a, B, y weight the importance of each distillation granularity.
C.6. Training- Testing Dynamics
Teacher Training. Using lasout-based features and full forward-reverse passes, we minimize the Teacher's own supervised objective (e.g., MSE w.r.t. sign-off AT). Let z!! be the final teacher embeddings.
Student Distillation. We fix pretrained teacher embeddings (z.") and then train Student on the lighter RTL graph by jointly optimizing:
Lsupi e.g., L1/L2 between AT, and AT! V
Lnodes Laubs Cylobal (Equations (17), (20), (22), and we used smoothL1 for good measure.).
Inference. For a new RTL design, the learned Student GNN (with embedded distillation knowledge) performs limited forward-reverse propagation to estimate timing. Despite minimal overhead, this yields near-layout accuracy in arrival time, WNS, TNS, etc.
18

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Bridging Layout and RTL: Knowledge Distillation based Timing Prediction
C.7. Conclusion of KD Formulation
By combining distribution-based KD concepts with mualti-graullarity feature alignment, we robustly transfer high-precision physical knowledge from the Teacher to the Student. Equations (14)-(23) form the mathematical backbone of our cross stage distillation and enable staly-stage RTL timing prediction comparable sign-off results.
C.8. Fan-in Cone Construction and Mathematical Formulation
Fan-in cone construction plays critical role in multi- gualtiigaaullrity knowledge distillation framework, particularly for subgraph-level alignment between RTL and layout stages. Here, we present rigorous mathematical formulation of fan-in cone construction and its hierarchical representation.
C.8.1. FORMAL DEFINITION OF FAN-IN CONE
Definition C.1 (Fan-in Cone), Given a circuit graph G (V, E), where V represents the set of nodes (including registers and combinational cells) and represents the set of directed edges. For any register node e E fan-in cone is defined as fan-in ( (Vran-in (v), (tan-in())) where:
Vian in (v) {u E V exists directed path from a to v),
(24)
Fraa in (V) {(u, w) E E u, Vianiin (v))-
(25)
C.8.2. FAN-IN CONE STRUCTURE
To facilitate effective knowledge transfer across different abstraction levels, develop level-based hierarchical fan-in representation:
Definition C.2 (Fan-in cone Representation). The level node relative to target register is defined recursively as:
0,
Levelaan (u,
max (Levelaa-in (W., v}} +1, a reaches v, w:( 00,
(26)
otherwise.
The nodes at each level I (from the target register/DFF) are defined as:
in,, Vi(v) {u E Via (v) Level (u, v) = 1).
(27)
The representation of the whole fan-in cone is defined as:
Qua Pool{ 2.T Vunn-i(u))
(28)
where h, represents final-layer embeddings for node in the fan-in cone, and mean pooling here.
The fan-in construction and its hierarchical representation
as the foundation for subgraph-level knowledge distillation, enabling the effective transfer of timing characteristics from the layout-level teacher to the RTL-level student model. Our experimental results demonstrate that this structured approach significantly improves the accuracy of timing prediction while maintaining computational efficiency.
19


Reviews:
[{"review_id": "mEQKujxIyM", "reviewer": "Reviewer_DZ14", "summary": "The paper describes a multi-level distillation framework to train a tool that can predict final timing characteristics of a synthesis flow from RTL-level description.  The paper provides interesting detailed analysis of their results and argues that their results are much more accurate than prior efforts, many of which stop at an intermediate \"gate-level\" presentation.", "questions": "", "limitations": "", "rating": 4, "confidence": null, "soundness": null, "presentation": null, "contribution": null, "strengths": "", "weaknesses": "", "quality": null, "clarity": null, "significance": null, "originality": null, "strengths_and_weaknesses": "", "was_revised": false, "final_justification": "", "rebuttal": "**Dear Reviewer DZ14,**\n\nThank you for your constructive comments and recognition of our work's core contributions. We greatly appreciate your thoughtful feedback, which has helped us further refine and clarify several key aspects of our methodology. Below, we provide a structured response to your concerns.\n## 1. Multiple EDA Back-end Parameters for Iterative Design Optimization\nIn constructing our dataset, we designed a unified, fully-automated back-end flow using state-of-the-art commercial tools—Synopsys Design Compiler and Cadence Innovus—with a consistent set of optimization switches (e.g., gate sizing, buffer insertion, cell movement, etc.). However, the circuits in our dataset were **not finalized under a single fixed configuration**.\n\nFor each design and each back-end optimization-related parameter (e.g., density thresholds, routing constraints, clock constraints), we **automatically tried multiple sets of values and iteratively explored multiple different configurations**, often conducting **tens of design runs**, until the circuit reached a state where:\n- Placement density no longer increased, and\n- Timing metrics converged stably through repeated optimization.\n\nThis convergence point is a practical proxy for physical design quality, reflecting an optimization level comparable to manually refined industrial flows. By doing so, we avoid biasing our dataset toward a singular \"super-convergent\" setting and instead generate diverse yet quality layouts more representative of industrial standards.\n\nImportantly, this means our model is **not tuned to predict timing under a specific tool configuration**, but rather aims to approximate the **best achievable timing performance** after realistic optimization—an objective more aligned with industrial design goals.\n## 2. Industrial Relevance and Methodological Scalability\nWe acknowledge that experienced experts in the industry may pursue further manual tuning to push timing closure closer to its theoretical optimum. However, given our goal of building a large RTL-to-Layout database covering many diverse designs, it is tough to explore every possible EDA configuration or foundry setting exhaustively.\n\nWhile our approach may not guarantee absolute optimality for each circuit, it reflects a **robust and converged implementation quality**, providing a meaningful basis for our timing prediction framework. By generating datasets by \"trying multiple parameters iterations until convergence\", our multi-granularity cross-stage distillation framework maintains strong generality across various designs, process nodes, and EDA flows. The student model is designed to be easily extensible—new designs, tools, or manufacturing conditions can be seamlessly integrated. Rather than overfitting to a specific toolchain or configuration, our framework demonstrates that cross-stage learning is broadly applicable and practical. Once more finely tuned industrial data become available, our method can directly incorporate such data to enhance model accuracy further.\n## 3. Runtime and Computational Efficiency\nPerforming the full RTL-to-Layout timing analysis flow—including synthesis, place-and-route, STA, etc.—typically consumes **hours or even days** for large circuits. In contrast, our GNN-based predictor operates at the RTL level, completing end-to-end inference in **seconds to a few minutes** for circuits ranging in size from thousands to millions of gates.\n\nFor example, on a 400K-gate CPU design running on an A100 GPU server:\n- Logic synthesis takes ~30 minutes\n- Backend optimization (e.g. place-and-route, etc.) takes over 6 hours\n- STA requires ~33 minutes\n\nBy comparison:\n- SOG extraction: ~65 seconds\n- Final GNN inference: <100 seconds\n\nThis enables a **speedup of over 10×**, even against standalone STA, and far more when compared to the entire back-end flow. Moreover, our GNN model supports **parallel processing**, enabling efficient handling of large-scale circuits and making it viable for early design-stage performance estimation.\n## 4. Data Availability and Reproducibility\nTo support reproducibility and peer evaluation, we have anonymized and **released a subset of our code and data through an anonymous repository (https://anonymous.4open.science/r/icml2025RTL-CBFD/)**.\n\nDue to the large file sizes and platform storage limitations, only a partial dataset is available at this stage (a clearer description of the data aspects is included in the reply to Reviewer wjHP; please check it out). We intend to release the **full dataset and code** upon paper acceptance, ensuring transparency and enabling broader research engagement.\n## Conclusion\nThanks for your thoughtful feedback. Your comments have helped us improve the clarity of our presentation, particularly around our data collection methodology, the generalizability of the proposed framework, and its practical runtime advantages.\n\n*We sincerely appreciate your review and very much hope to earn your affirmation and a higher rating!*", "claims_and_evidence": "The paper argues their accuracy is much better than SOTA algorithms on a range of circuits.  They argue and use ablation studies to evaluate the benefits of their multi-hierarhical approach.  Their reported numbers are indeed impressive and their approach IMHO has value. However, I think the evidence is not convincing. In particular, the results from final layout of a circuit depend on a myriad of specific parameters to the specific place and route tool and defined characteristics of the clock tree and whether or not certain optimizations are set or not (e.g., joint clock and data optimization), which can yield a run-time vs performance trade-off. A small change in initial area utilization during placement, for example, can yield quite significant differences post place-and-route. The description of the experiments do not describe these tool parameters in any detail and this reviewer is left to assume that the parameters are left the same between training and evaluation. This suggests that the model they train may only good be good for predicting timing for this specific set of tool parameters.  Given experts often tweak these parameters from design to design, this issue should at the very least be discussed. I have no doubt that their approach has the potential benefits they claim, but I think the actual numbers they provide should be explained and the limitations of their approach should be more fully described..\n\nThe paper also claims that the models are computationally efficient, but do not provide any run-time analysis of the models. This should be added.", "methods_and_evaluation_criteria": "The set of benchmark circuits is only vaguely designed. In most EDA/CAD papers the results of each benchmark should be included and this is missing from this paper. I would have expected to see this in an anonymous git or a table in the appendix. Not sure why this is not here, but it makes re-producing these results quite difficult.", "theoretical_claims": "There are no theoretical claims in the paper.", "experimental_designs_or_analyses": "See above.", "relation_to_broader_scientific_literature": "This paper is fundamentally about using ML for EDA and in that domain seems like reasonable work. It is not clear how useful or interesting it will be to the ICML community, but I am reviewing it as if it is.", "essential_references_not_discussed": "None.", "other_strengths_and_weaknesses": "None.", "other_comments_or_suggestions": "None.  My score has been adjusted to account for the very nice rebuttal the authors wrote. Thanks for the clarification.", "questions_for_authors": "Please address the questions I raised above.", "summary_of_paper": "", "summary_of_recommendation": "", "technical_quality": "", "clarity_of_presentation": "", "potential_impact": "", "robotics_focus": "", "quality_of_limitations": "", "questions_for_rebuttal": "", "reasons_to_accept": "", "reasons_to_reject": "", "questions_to_authors": "", "extra_scores": {}}, {"review_id": "Xtu6yPMuLX", "reviewer": "Reviewer_55gZ", "summary": "The paper proposes RTLDistil, a framework aimed at bridging the gap between early-stage RTL timing prediction and accurate layout-level timing analysis. The method leverages a dual-model setup: a high-capacity teacher model operating on a layout netlist graph and a lightweight student model working on an RTL-level Simple Operator Graph (SOG). The core idea is to use multi-granularity knowledge distillation that encompasses node-, subgraph-, and global-level alignments, along with an asynchronous forward-reverse propagation strategy to transfer precise physical characteristics from the teacher to the student. The authors claim that RTLDistil reduces prediction errors compared to previous methods such as MasterRTL and RTL-Timer.", "questions": "", "limitations": "", "rating": 3, "confidence": null, "soundness": null, "presentation": null, "contribution": null, "strengths": "", "weaknesses": "", "quality": null, "clarity": null, "significance": null, "originality": null, "strengths_and_weaknesses": "", "was_revised": false, "final_justification": "", "rebuttal": "**Dear Reviewer 55gZ,**\n\nThanks for your insightful comments. Your feedback greatly helped us refine our work. Below, we address your major concerns.\n## 1. Efficiency vs. STA and Left-Shift\nThe entire flow from RTL to Layout to STA completion usually takes hours to days under rough quantitative estimation. Our method achieves several orders of magnitude faster runtime (see our response to Reviewer DZ14 for runtime details), with PCC 0.92, R² 0.85, and MAPE 16.87% for AT prediction—sufficient for early-stage RTL optimization [1], allowing the design flow to shift left.\n## 2. Domain-specific Asynchronous Forward-Reverse Propagation\nWhile bidirectional GNNs exist, we focus on an asynchronous forward-reverse approach tailored to timing semantics and physical contexts. This provides a deeper coupling between AI modeling and timing prediction domain-specific requirements:\n- We incorporate multi-round, asynchronous updates to capture the long-range dependencies of registers, cells, and wires.\n- This schema includes a form of \"reverse constraint\" flow, reflecting the physical insight that timing slack on downstream cells can impose constraints on upstream segments, especially under realistic RC conditions.\n- Ablation results (Appendix) confirm simpler forward-only or fewer propagation rounds significantly degrade accuracy. This is caused by insufficient access to information about the surrounding circuit.\n\nOur design goes beyond standard message passing to encode domain-specific timing semantics.\n## 3. Multi-Granularity Distillation: Tailored to Circuit Structures\nOur contribution lies in adapting multi-granularity distillation to **EDA-specific adaptation**:\n- **Tailoring to timing.** Each granularity naturally corresponds to specific circuit structures relevant to timing: node-level for register endpoints, subgraph-level for critical local paths (fan-in/out cones), and global-level for capturing overall congestion (e.g., WNS/TNS).\n- **Simultaneous cross-stage distillation.** By tuning the student at three granularities during distillation under the teacher, we alleviate the lack of physical cues at RTL by implicitly embedding critical layout-level physical information into the RTL GNN while focusing on the circuit's local and overall situation. As reviewer said, different distillation goals exhibit different behaviors because each of the three granularities plays a different role.  As in Table 4, removing any one or two granularities reduces performance, confirming their complementary roles.\n\nW/ Node performs well on AT's MAPE because it ignores the global or several paths in relation to each other and focuses only on registers. This leads to relatively good predictions in numerical values (MAPE) but weaker performance in correlation metrics (PCC,  R²) than the full model, not giving the best results.\n## 4. Teacher Model Limits and Distillation Balance\nOur layout-level teacher is more accurate than the student but less precise than full STA due to the complexity of real RC extraction and GNN inherent limitations. The teacher’s precision naturally binds the student.\n\nRegarding grid search of distillation-loss weights (α, β, γ), we observed small fluctuations across different metrics. We believe the optimal balance varies with data properties, circuit complexity, and task objective focus. Via coarse-grained grid search (lower computational overhead), we find equal weights (α = β = γ) that show superior multi-task average performance and make the ablation experiments clearer.\n## 5. Distinction from Related Work\nCompared to prior methods:\n- [2] uses LLMs but lacks scalability and physical layout fidelity. \n- [3] operates at layout stage, limiting early RTL optimization. \n- [4] targets dynamic runtime behavior, not static timing.\n\nOur method uniquely shifts accurate physical timing prediction to the RTL stage via cross-stage distillation.\n## 6. Scalability to Industrial Designs\nWe are scaling to large designs (e.g., BOOM). While back-end optimization of million-gate designs is very demanding regarding runtime (more than days) and hardware resources, our graph-based architecture has shown scalability in principle, and we will endeavor to report results as large circuits are available.\n## Conclusion\nThanks for your constructive input, which helped us better articulate our approach's novelty and practical utility.\n\n*We appreciate your time and look forward to further suggestions. Hope to get a higher rating from you!*\n## References\n[1] Fang, Wenji, et al. \"Annotating slack directly on your verilog: Fine-grained rtl timing evaluation for early optimization.\"\n\n[2] Moravej, Reza, et al. \"The Graph's Apprentice: Teaching an LLM Low Level Knowledge for Circuit Quality Estimation.\"\n\n[3] Zhong, Ruizhe, et al. \"Preroutgnn for timing prediction with order preserving partition: Global circuit pre-training, local delay learning and attentional cell modeling.\"\n\n[4] DynamicRTL: RTL Representation Learning for Dynamic Circuit Behavior", "claims_and_evidence": "The claims in the paper are generally well-supported by corresponding analyses and experiments. Building on this, I have the following question:\n\n- To facilitate an effective \"left-shift\" in the design process, it would be beneficial to compare the results with analytical STA methods in terms of computational efficiency. This comparison would provide readers with a clearer understanding of the achieved accuracy-efficiency trade-off.", "methods_and_evaluation_criteria": "Overall, I believe the proposed method is a valuable exploration in bridging the gap between early-stage RTL timing prediction and accurate layout-level timing analysis. The approach appears well-reasoned. However, I have the following concerns regarding its technical contributions:\n\n- Forward-Reverse Propagation Strategy: The bidirectional propagation mechanism, which aggregates fan-in and fan-out information, closely resembles standard bidirectional message-passing techniques widely used in GNNs for RTL [1]. The asynchronous adaptation seems like a minor modification, making the technical contribution of this aspect relatively limited.\n\n- Multi-Granularity Alignment: Aligning features at the node, subgraph, and global levels is a common technique in GNNs, as seen in [2]. While its integration within a knowledge distillation framework tailored for EDA is interesting, it represents an incremental improvement rather than a fundamentally novel contribution.\n\n[1] Lopera, Daniela Sánchez, and Wolfgang Ecker. \"Applying GNNs to timing estimation at RTL.\" Proceedings of the 41st IEEE/ACM International Conference on Computer-Aided Design. 2022.\n\n[2] Zhang, Muhan, and Pan Li. \"Nested graph neural networks.\" Advances in Neural Information Processing Systems 34 (2021): 15734-15747.", "theoretical_claims": "Not applicable.", "experimental_designs_or_analyses": "- The performance achieved by the teacher model still appears relatively limited. A more in-depth analysis of the teacher model’s quality and the current limitations of the student model’s performance would be beneficial. It would be helpful to clarify whether these limitations stem from the teacher model’s capability, the learning process, or other factors.\n\n- How are the losses across the three granularities balanced? Is this parameter sensitive to performance? What is the computational cost of a grid search? Additionally, is the grid search a one-time process, or does it need to be adjusted for different models, tasks, or datasets?", "relation_to_broader_scientific_literature": "N/A", "essential_references_not_discussed": "It would be helpful to add a detailed discussion on the similarities and differences in terms of method and results of many closely related papers on the same topic, such as: \n\n[1] Moravej, Reza, et al. \"The Graph's Apprentice: Teaching an LLM Low Level Knowledge for Circuit Quality Estimation.\" arXiv preprint arXiv:2411.00843 (2024).\n\n[2] Zhong, Ruizhe, et al. \"Preroutgnn for timing prediction with order preserving partition: Global circuit pre-training, local delay learning and attentional cell modeling.\" Proceedings of the AAAI Conference on Artificial Intelligence. Vol. 38. No. 15. 2024.\n\n[3] DynamicRTL: RTL Representation Learning for Dynamic Circuit Behavior", "other_strengths_and_weaknesses": "Please refer to the above sections.", "other_comments_or_suggestions": "Please refer to the above sections.", "questions_for_authors": "- Although the paper demonstrates improvements over baseline approaches, to what extent do the current results meaningfully enable the claimed 'left-shift' of the design process? A more detailed analysis of the achieved results, supported by relevant references, would be beneficial.\n\n- This may be an ambitious question, but I am curious about how RTLDistil performs on large-scale industrial designs (e.g., SoCs with millions of gates). The experiments primarily focus on medium-sized designs, yet scalability to larger designs is crucial for practical adoption.\n\n- In Table 4, why do different distillation objectives lead to varying results for RTLDistil? Specifically, why does the w/ Node objective yield a promising MAPE while other metrics show less favorable outcomes? Are there insights into the underlying distribution of the achieved results?", "summary_of_paper": "", "summary_of_recommendation": "", "technical_quality": "", "clarity_of_presentation": "", "potential_impact": "", "robotics_focus": "", "quality_of_limitations": "", "questions_for_rebuttal": "", "reasons_to_accept": "", "reasons_to_reject": "", "questions_to_authors": "", "extra_scores": {}}, {"review_id": "pzItSveJX5", "reviewer": "Reviewer_wjHP", "summary": "This paper presents a cross-stage knowledge distillation framework for timing prediction. Under this framework, the layout aware teacher model distills layout charactersistics to an RTL-level student models. Experimental results demonstrate significant improvement compared with other prediction models.", "questions": "", "limitations": "", "rating": 4, "confidence": null, "soundness": null, "presentation": null, "contribution": null, "strengths": "", "weaknesses": "", "quality": null, "clarity": null, "significance": null, "originality": null, "strengths_and_weaknesses": "", "was_revised": false, "final_justification": "", "rebuttal": "**Dear Reviewer wjHP,**\n\nWe sincerely appreciate the reviewer's positive remarks and valuable suggestions regarding our work, particularly concerning the sources of our benchmark data, the open-source plan, the fairness of comparisons with MasterRTL/RTL-Timer, and the discussion on comparison with other models. Below, we provide detailed answers to the points you raised.\n## 1. Benchmark and Dataset Explanation\nWe have carefully chosen not to rely exclusively on certain existing publicly available datasets (e.g., ISCAS-89, ITC-99) because they are limited in size and diversity relative to our specific RTL-Layout prediction goals. For some large circuits, such as some large-scale CPUs or other designs, there may be many duplicate or essentially identical paths in the circuit, but the timing analysis is more associated with paths, which makes the distribution of the existing datasets not particularly satisfying; we wanted to minimize the occurrence of duplicate paths in the datasets and to make the dataset distribution as even and diverse as possible in order to allow more physical information to be learned by our model.\n\nInstead, we collected more circuits of **different types, functions, and sizes** to reflect real-world industrial needs, including small arithmetic blocks, DSP modules, RISC-V subsystems, etc. This makes the prediction task harder, but we think it's more practical, pervasive, industrially valuable, and closer to the needs of actual industrial processes. These 2000+ designs come from GitHub, OpenCore, Hugging Face, and the open-source RISC-V project, ensuring broad functionality and design complexity coverage. The construction and cleaning of the dataset took us close to 5 months (see the reply to Reviewer DZ14 for more information on Layout data construction).\n## 2. Open-Source Plan of Dataset and Codes\nFurthermore, we have partially anonymized and **released a subset of these designs and codes on public repositories (https://anonymous.4open.science/r/icml2025RTL-CBFD/)**; however, the size of back-end data and the space limitations on anonymous platforms prevent a complete release at this stage. We will expand our open dataset, aiming to foster community progress in AI4EDA.\n\nWe will keep enhancing our open-source repository (both the dataset and the code) to facilitate replication and iterative improvement by the community. Thanks to its graph-oriented modeling and distillation-based learning, we strongly believe our framework can be generalized to more designs.\n\n## 3. Comparisons with MasterRTL and RTL-Timer\nAll results reported in the paper were derived by re-training and evaluating both MasterRTL [1] and RTL-Timer [2] on precisely the same dataset and evaluation protocols used by our method. Specifically:\n\n1. Both are open-source implementations, and we reproduced them faithfully on our data, adhering to the authors' original procedures.\n2. We used the **same train/validation/test partitioning and ground-truth labels** for all methods.\n3. We evaluated using identical error metrics (MAPE, PCC, R²) for consistency.\n## 4. Comparison with Other Models\nWe appreciate your recommendation to compare more thoroughly with related methods. Given that MasterRTL and RTL-Timer are among the most competitive open-source approaches for RTL-level timing prediction, demonstrating improvements over them provides a fair and substantial benchmark. According to prior works (e.g., [3], [4]), they didn't show the same performance as MasterRTL and RTL-Timer (e.g., > 10% gap in MAPE). We chose MasterRTL and RTL-Timer as the strongest public baselines. \n## Conclusion\nThanks again for the reviewer's supportive review and for highlighting the significance of benchmark diversity, fair comparisons, and open-source work. We will refine the discussion on data sources, continue expanding our dataset for broader coverage, and work to open-source the code with the full dataset. We hope the clarifications and updates will further underscore the practicality and robustness of our method.\n\n*We greatly value the reviewer's feedback and look forward to any additional suggestions. Looking forward to getting a higher rating from you!*\n## References\n[1] Fang, Wenji, et al. \"Masterrtl: A pre-synthesis ppa estimation framework for any rtl design.\" *2023 IEEE/ACM International Conference on Computer Aided Design (ICCAD)*. IEEE, 2023.\n\n[2] Fang, Wenji, et al. \"Annotating slack directly on your verilog: Fine-grained rtl timing evaluation for early optimization.\" *Proceedings of the 61st ACM/IEEE Design Automation Conference*. 2024.\n\n[3] Xu, Ceyu, Chris Kjellqvist, and Lisa Wu Wills. \"SNS's not a synthesizer: a deep-learning-based synthesis predictor.\" *Proceedings of the 49th Annual International Symposium on Computer Architecture*. 2022.\n\n[4] Sengupta, Prianka, et al. \"How good is your Verilog RTL code? A quick answer from machine learning.\" *Proceedings of the 41st IEEE/ACM International Conference on Computer-Aided Design*. 2022.", "claims_and_evidence": "The claims seem supported by experiments. Experiments on Table 3 clearly demonstrate the benefit of both distillation and finetuning, with distillation being more important. Table 4 further demonstrate importance of multi-granularity knowledge distillation.", "methods_and_evaluation_criteria": "Benchmarks used seemed to be unclear. The authors claimed to use 2k RTL designs sourced from open-source projects. No further details are presented. Also remains unclear why not use similar data compared with open-source versions of prior work.", "theoretical_claims": "The paper does not make any theoretical claims.", "experimental_designs_or_analyses": "Experiments seem solid. Ablation studies are well conducted.", "relation_to_broader_scientific_literature": "The authors improve upon prior work by distilling layout-aware models to RTL code level models. Authors were able to present improvements compared with prior works.", "essential_references_not_discussed": "None.", "other_strengths_and_weaknesses": "The authors idea of distilling layout aware models to RTL-level models is novel and effective. However the dataset and test used in the paper remains unclear. More comparision with prior work could also benefit the paper.", "other_comments_or_suggestions": "None.", "questions_for_authors": "(1) Can the authors clarify on the dataset used for training/testing? Why not direct use already open-source data from prior work. Will new data (and models) from authors be open-sourced?\n\n(2) How did the authors conduct experiements with MasterRTL and RTL-Timer? Were they retrained on same data?\n\n(3) Can the authors compare with more existing prior work other than from Fang?", "summary_of_paper": "", "summary_of_recommendation": "", "technical_quality": "", "clarity_of_presentation": "", "potential_impact": "", "robotics_focus": "", "quality_of_limitations": "", "questions_for_rebuttal": "", "reasons_to_accept": "", "reasons_to_reject": "", "questions_to_authors": "", "extra_scores": {}}]

Author rebuttal:

Meta-review: This paper presents RTLDistil, a cross-stage knowledge distillation framework that enables accurate timing prediction at the RTL level by leveraging layout-aware GNN-based teacher models. The key contribution lies in transferring physical characteristics from the layout domain into the early-stage RTL domain, using a multi-granularity distillation strategy (node-, subgraph-, and global-level) and an asynchronous forward-reverse message-passing scheme that captures timing-critical constraints more effectively than conventional GNNs. Empirical results show significant improvements in prediction metrics over strong baselines like MasterRTL and RTL-Timer, suggesting RTLDistil enhances both accuracy and efficiency for early design-stage optimisation.

While some reviewers noted that components like multi-granularity alignment and bidirectional propagation resemble existing techniques, the authors effectively clarified that their asynchronous design was tailored to timing semantics and physical propagation constraints unique to EDA tasks. They also addressed concerns about benchmark construction, reproducibility, and scalability to industrial designs through detailed responses and by releasing anonymized datasets and code. Additional experiments showed the generalizability of their KD framework when adapted to other models such as SNS, highlighting both its benefits and the challenges of path-based approaches.

Overall, the method offers a practical and scalable solution to bridging layout-level precision and RTL-level efficiency in timing prediction. The combination of robust experimental results, thoughtful design choices tailored to EDA, and clear evidence of broader applicability makes this work a valuable contribution to AI4EDA. Therefore, I recommend acceptance.
Decision: Accept (spotlight poster)