EGPlace: An Efficient Macro Placement Method via Evolutionary Search with Greedy Repositioning Guided Mutation
Authors: ji deng
Zhao Li
Ji Zhang
Jun Gao
Venue: ICML 2025 poster (2025)
Keywords: Chip Placement
Evolutionary Search
Mutation
Primary area: applications

Abstract: Macro placement, which involves optimizing the positions of modules, is a critical phase in modern integrated circuit design and significantly influences chip performance. The growing complexity of integrated circuits demands increasingly sophisticated placement solutions. Existing approaches have evolved along two primary paths (e.g., constructive and adjustment methods), but they face significant practical limitations that affect real-world chip design. Recent hybrid frameworks such as WireMask-EA have attempted to combine these strategies, but significant technical barriers still remain, including the computational overhead from separated layout adjustment and reconstruction that often require complete layout rebuilding, the inefficient exploration of design spaces due to random mutation operations, and the computational complexity of mask-based construction methods that limit scalability.  To overcome these limitations, we introduce EGPlace, a novel evolutionary optimization framework that combines guided mutation strategies with efficient layout reconstruction. EGPlace introduces two key innovations: a greedy repositioning-guided mutation operator that systematically identifies and optimizes critical layout regions, and an efficient mask computation algorithm that accelerates layout evaluation. Our extensive evaluation using ISPD2005 and Ariane RISC-V CPU benchmarks demonstrate that EGPlace reduces wirelength by \textbf{10.8\%} and \textbf{9.3\%} compared to WireMask-EA and the state-of-the-art reinforcement learning-based constructive method EfficientPlace, respectively, while achieving speedups of 7.8$\times$ and 2.8$\times$ over these methods.

EGPlace: An Efficient Macro Placement Method via Evolutionary Search with Greedy Repositioning Guided Mutation
Ji Deng' Zhao Li
Ji Zhang 3 Jun Gao
Abstract
1. Introduction
Macro placement, which involves optimizing the positions of modules, is a critical phase in modern integrated circuit design and significantly influ- ences chip performance. The growing complex- ity of integrated circuits demands increasingly sophisticated placement solutions. Existing ap- proaches have evolved along two primary paths (e.g., constructive and adjustment methods), but they face significant practical limitations that af- feet real-world chip design. Recent hybrid frame- works such as WireMask-EA have attempted to combine these strategies, but significant technical barriers still remain, including the computational overhead from separated layout adjustment and reconstruction that often require complete layout rebuilding, the inefficient exploration of design spaces due to random mutation operations, and the computational complexity of mask-based con- struction methods that limit scalability. To over- come these limitations, we introduce EGPlace, a novel evolutionary optimization framework that combines guided mutation strategies with efficient layout reconstruction. EGPlace introduces two key innovations: greedy repositioning-gait -giddd mutation operator that systematically identifies and optimizes critical layout regions, and an effi- cient mask computation algorithm that accelerates layout evaluation. Our extensive evaluation using ISPD2005 and Ariane RISC-V CPU benchmarks demonstrate that EGPlace reduces wirelength by 10.8% and 9.3% compared to WireMask-FA and the state-of the-arrt reinforcement learning-based constructive method EfficientPlace, respectively, while achieving speedups of 7.8x and 2.8x over these methods.
The exponential growth in integrated circuit complexity has made chip placement critical challenge in electronic de- sign automation (MacMillen et al., 2000). The task involves positioning thousands of macro blocks and millions of stan- dard cells on chip, creating a solution space even more complex than advanced strategic games like Go (Mirhoseini et al., 2021). Research has been focused on macro place- ment optimization (Geng al.. 2024b; Mirhoseini al., 2021; Lai al., 2022; Shi et al., 2023) these functional blocks significantly impact overall circuit performance.
The macro placement problem presents a complex optimiza- tion problem with three interrelated technical objectives that determine circuit viability (Chen et al., 2006). Minimizing total wirelength between connected models reduces signal delays and improves chip performance, while managing routing congestion ensures adequate resources for signal transmission (Wang et al., 2009). The complete climina- tion of physical overlaps between models remains essential for manufacturing feasibility (Lai et al., 2022). The tech- nical complexity emerges from the nonlinear relationships between model positions and performance metrics, where local modifications can have significant effects on global optimization goals. This challenge compounds with the intricate connections between models, which together cre- ate an enormous combinatorial solution space. Achieving high-quality placement solutions requires simultaneously balancing these competing objectives and addressing the complex challenges.
Research in macro placement optimization has developed two different categories of approaches: adjustment-bass methods that iteratively improve existing layouts, and con- structive methods that build solutions progressively. The adjustment-based category includes both stochastic and an- alytical optimization techniques. Stochastic methods such as simulated annealing (Sechen & Iangiovanni-Vincenten 1985) and evolutionary algorithms (Cohoon & Paris, 1987; Shahookar & Mazumder, 1991; Kling & Banerjee, 1989) modify layouts through random perturbations to explore di- verse solutions. However, this undirected exploration often leads to low sample efficiency. Analytical approaches (Lu et al., 2015; Cheng et al., 2018; Kahng et al., 2005) trans-
'School of Computer Science. Peking University, BeiJing, China *Zhejiang Lab. Zhejiang, China "Nanjing University of Acronautics and Astronautics, China. Correspondence to: Jun Gao <gaojun crojiun@pku.dd..co pku.edu.cn..
Proceedings of the 4 International Conference Machine Learning. Vancouver, Canada. PMLR 267, 2025. Copyright 2025 by the author(s).

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EGPlace: An Efficient Macro Placement Method via Evolutionary Search with Greedy Repositioning Guided Mutation
form the placement problem into mathematical equations solved through techniques like gradient descent. These methods face practical limitations from relaxing overlap constraints and difficulty in handling non non-differentiable con- gestion metrics. Constructive methods build layouts from scratch using different strategies. Recent advances on con- structive methods have focused on reinforcement learning approaches (Mirhoseini al., 2021; Cheng et al., 2022: Lai et al., 2022; Geng et al., 2024b) that model placement Markov Decision Process with sequential model position- ing. While these methods have shown promising results, they require substantial computational resources for training. The sequential nature of their decision-making also means each placement choice lacks sufficient reception field about future layout configurations.
over, this mutation operator seamlessly integrates lay- out adjustment and reconstruction phases, eliminating the computational overhead caused by full layout re- construction after local modifications.
An advanced mask computation algorithm that reduces the computational complexity from quadratic to linear time per module. This improvement enables rapid eval- uation of potential module positions and accelerates the overall optimization process.
Extensive experimental validation on standard ISPD2005 benchmarks demonstrates that EGPlace achieves 11% better Half Perimeter Wire Length (HPWL) (Chen et al., 2006) than WireMask-EA (Shi et al., 2023), 9% improvement over EfficientPlace (Geng et al., 2024b), and a 7.8x x speedup compared to WireMask-
The integration of constructive and adjustment methods leads to promising approaches to macro placement opti- mization. A recent ofate-of-the-art method WareMas (Shi et al., 2023) implements this concept through an evolu- tionary algorithm framework. The method applies random mutations to layouts and uses greedy reconstruction to im- prove solution quality. However, the hybrid approaches still encounter three major technical challenges: Executing lay- out adjustments and reconstructions sequentially can lead to inefficiencies, as local changes may require complete layout overhaul; random mutations in stochastic optimiza- tion can waste computational resources by exploring less promising configurations; the mask computations needed for assessing module positions can become a performance bottleneck due redundant calculations during placement.
2. Related Work
Current chip placement methods are maninly classified into constructive and adjustment-base techniques. In a signifi- cant development, recent research has focused on combining these approaches to create more effective hybrid solutions.
Constructive Methods. Constructive methods generate layouts from scratch. Early constructive methods rely on heuristic rules, such as greedy placement rule (Magnuson, 1977; Fukunaga et al., 1983). Those methods place intercon- nected modules in proximity to reduce wirelength. Although they are efficient, it is challenging to determine rules that perform well across different chip benchmarks. Breuer et al. introduces partition partition-based methods, which divide circuits into clusters to minimize inter-cluster connections and place them in corresponding subregions (Breuer, 1977). Later improvements include terminal propagation to account for inter-cluster connections (Dunlop & Kernighan, 1985) and advanced hypergraph partitioning techniques (Fiduccia & Mattheyses, 1988; Karypis et al., 1997). However, these methods optimize placements within each partition indepen- dently, limiting overall performance.
To solve the aforementioned technical challenges, we intro- duce EGPlace, an evolutionary optimization framework for macro placement that integrates guided mutation with effi- cient reconstruction techniques. Unlike previous approaches that separate adjustment and construction phases (Shi et al., 2023), EGPlace implements a unified mutation operator that selects modules for repositioning based their quality impact scores and employs an efficient greedy strategy for module relocation. To enhance sample efficiency during exploration within the vast search space, the framework in- corporates guidance mechanisms at multiple levels- using fitness functions to identify promising layouts for evolution and prioritizing poorly placed modules for repositioning. This targeted optimization approach, combined with an op- timized mask computation algorithm, enables EGPlace to achieve superior results with significantly reduced compu- lational requirements. The main contributions of this work include:
Recent work utilizes Reinforcement Leaning (RL) to learn constructive placement strategies. Mirhoseini et al. (Mirho- seini et al., 2021) introduced sequential module placement using a trained RL agent. Many studies have focused on improving the performance of RL-based methods. PRNet (Cheng & Yan, 2021) integrated chip routing considera- tions to refine reward signals. MaskPlace (Lai et al., 2022) leveraged CNNs to better capture pin location information. Subsequent work prioritizes computational efficiency. Chip- former (Lai et al., 2023) employed pretrained decision trans- formers (Zheng et al., 2022) for rapid adaptation to new circuits. EfficientPlace (Geng et al., 2024b) further ad- vanced efficiency through a learning-inside-onn indiddoottttoioiiiationn
A novel and efficient mutation operator with a guid- ance mechanism that identifies critical modules for repositioning based on their impact on overall layout quality, thereby improving sample efficiency. More-
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EGPlace: An Efficient Macro Placement Method via Evolutionary Search with Greedy Repositioning Guided Mutation
framework that combines state storage with Monte Carlo Tree Search guidance. Despite these innovations, existing RL-based constructive approaches face two persistent lim- itations: the substantial computational overhead of agent training and the inherent myopia of sequential placement decisions, where each choice does not sufficiently consider future module positions.
outlined in the introduction. In addition, the recent work LaMPlace (Geng al., 2024a) integrates a learned mask, designed to reflect final Power, Performance and Area (PPA) objectives, into the WireMask-EA framework, and use it in place of the original WireMask to guide macro placement. This enhancement leads to substantial improvements in PPA performance. The learned mask from LaMPlace can also be incorporated into EGPlace to potientially improve the final layout quality.
Methods. Adjustment-basee methods iteratively adjust module locations to improve layout qual- ity. These methods include stochastic-based and analytical- based approaches. Stochastic-basee approaches typically use simulated annealing algorithms and represent layouts with data structures like sequence pairs (Murata et al., 2002), B*-trees (Chang et al., 2000) and corner block lists (Hong et al., 2000). These approaches apply perturbations to their data structures explore the search space, then transform them back to the original layout representation for evalua- tion. However, such transformations are computationally expensive (Shi et al., 2023), while random perturbations of- methods, ten lead to low sample efficiency. Analytical-bas including quadratic (Viswanathan & Chu, 2005) and non- linear approaches (Cheng et al., 2018: Lin al., 2019; Lu al., 2015), model optimization objectives with analytical equations. Nonlinear methods like ePlace (Lu et al., 2015) treat module density as charge density in an electrostatic sys- tem and have shown strong performance. Analytical-based methods often treat overlap as a soft constraint, addressing it during a subsequent legalization phase, which may lead to significant increase in wirelength or even fail to generate valid layouts. They also ignore congestion, which is non- differentiable and hard to optimize with gradient descent. Some recent RL-based methods (Xue et al., 2024; Chiang et al., 2025) adopt novel adjustment paradigm, where placement begins with a complete layout and policies are learned to adjust the position of one or a group of modules at each step. While this approach benefits from a comprehen- sive state representation that captures the full layout context, it incurs considerable computational overhead.
Adjustment-based
3. Problem Description & Overall Framework
The input of macro placement comprises a rectangular chip substrate and a circuit netlist represented as hypergraph, where modules serve as nodes while nets function as hyper- edges that connect the pins located on different modules.
Layout quality evaluation involves three key metries. The primary metric, wirelength, measures total routing resources and affects circuit performance. Since the exact wirelength can be determined only after routing, a more efficient ap- proximation, Half Perimeter Wire Length (HPWL) (Chen et al., 2006), is typically used, calculated from the sum of half-perimeters of net-bounding boxes. For routing con- gestion analysis, the Rectangular Uniform wire DensitY (RUDY) metric (Spindler & Johannes, 2007) gauges re- source utilization density. Additionally, minimizing physi- cal overlap between modules, quantified by an overlap rate (Lai et al., 2022), is crucial for manufacturabbiityy While ideal layouts aim for zero overlap, practical methods (Lin et al., 2019; Lai et al., 2022) may relax this constraint to improve optimization efficiency, especially where modules occupy a large proportion of the placement region, such as the "ariane" benchmark in Appendix D D.4. Detailed metric definitions and calculations are found in Appendix B.
benchmarks
The optimization objective combines these metries through weighted sum formulation shown in Equation (1). The hyperparameters \ and X control the relative importance of RUDY and overlap penalties compared to the primary HPWL objective, to produce the layouts that balance com- peting design constraints:
Hybrid Methods. Some recent research has focused on synthesizing the strengths of constructive and adjustment methods in macro placement optimization. For instance, WireMask-EA (Shi et al., 2023) employed a simple (1+1)- EA (Zhou al., 2019) as its backbone, which maintains population of only one layout. In each iteration WireMask- EA applies random module swapping adjustments the layout to explore the search space, and reposition modules with greedy constructive method to improve the quality. It takes advantage of both the efficiency of greedy placement methods and the capability to broadly explore the solution space of adjustment methods, and achieves better layout quality than many of-te-of-the-art RL-based methods. How- ever, despite its innovative design, the method still confronts several computational and optimization challenges that were
Objective HPWI. + X1 RUDY ooverlpp (1)
In this paper, we propose EGPlace for efficient macro place- ment. The framework of EGPlace is illustrated in Fig. 1. It utilizes an evolutionary backbone combined with greedy puositioning-guidee mutation.
4. Evolutionary Backbone
EGPlace employs evolutionary search as its optimization backbone due to its effectiveness in handling complex, non- differentiable objectives and discrete optimization problems.
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EGPlace: An Efficient Macro Placement Method via Evolutionary Search with Greedy Repositioning Guided Mutation
Outpul
Layout Selection
Fitness Based
Repooation
ast
Scoring
Guided Midule
Nottitt
Chip
Initaiization
Select
Greedy Repositinn
Modulle be Repoellooee
Layout Popuiation
Effiiint Calculation
Prpuiation Menrinance
Groidy Reposition ane Medule
(4] Evolutionary Search Backbone
(b) Greedy Repositioning Guided Mutation
Figure EGPlace Framework. We employ an evolutionary search backbone and propose greedy repositioning- guideed mutation. The mutation process operates in two phases. In the first phase, modules selected for repositioning based on scores that measure their impact on layout quality. In the second phase, mask-guided greedy strategy is applied to determine new positions for selected modules.
The population- -assed approach can also naturally maintain solution diversity while exploring the vast configuration space of circuit layouts.
This fitness-guided selection is based on the intuition that layouts with higher fitness are more likely to result in high- quality layouts after adjustment. It ensures a more effective search while still allowing for random exploration.
The search evolves fixed-size population of layouts through successive iterations. By maintaining bounded population, we avoid memory and runtime overhead while preserving solution diversity, critical for escaping local op- tima macro placement. During each iteration, a layout undergoes the proposed mutation operator, which integrates both constructive and adjustment strategies. We focus exclu- sively on mutation operations as our experiments showed that crossover mechanisms often disrupt critical local opti- mization patterns in circuit placement. The modified layout may enter the population based on its fitness evaluation, replacing the lowest-performing existing solution. This selective pressure drives the population toward optimized configurations until reaching the specified iteration limit.
Layout Maintenance. The selected layout undergoes mu- tation described in Section 5 to generate a new layout. Then, the mutated layout is added to the population. If the population size exceeds the specified limit, the layout with the lowest fitness is discarded. This helps maintain a man- ageable population size and improves efficiency by stopping the mutation of less promising layouts.
5. Greedy Repositioning Guided Mutation
Our proposed mutation operator builds on three key de- sign principles: unified integration of construction and ad- justment phases, guided mutation processes that maintain beneficial randomness, and computationally efficient imple- mentation of masks for rapid iteration.
Initialization. The population is initialized with layouts constructed using the greedy placement strategy described in Section 5.2. This constructive strategy is highly efficient and generates promising layouts for evolution.
Guided by the above principles, mutation operator functions through two-phase process. In the selection phase, mod- ules receive quality scores based on their impact on overall layout metrics. Modules with poorer placement quality have higher selection probability for repositioning, focusing com- putational resources on the most promising improvement opportunities. The repositioning phase then applies greedy strategy to the selected modules, determining new positions that optimize local quality metrics while maintaining global layout coherence. The following sections detail these selec- tion and repositioning mechanisms that form the core of our mutation strategy.
Fitness-based Layout Selection. The fitness function eval- uates layout quality and guides layout selection. The fitness fL, of layout L; defined as the negative of the optimiza- tion objective in Equation (1), where higher fitness values correspond to better layout quality. The weights A and X2 can be adjusted by the user to obtain layouts with congestion and overlap below desired thresholds.
layout Lg is selected from the population with a proba- bility p( p(L)) positively correlated to its fitness, as defined in Equation (2), where P denotes the layout population.
etu
p(L:) = Eljepetes
(2)

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EGPlace: An Efficient Macro Placement Method via Evolutionary Search with Greedy Repositioning Guided Mutation
Algorithm 1 Greedy Placement Strategy
Input: The placement area divided into B x B bins, the netlist N, and the set of modules M selected be placed. During population initialization, M includes all macros. In greedy repositioning, consists of macros selected according to Section 5.1.
Output: Layout after greedy placement
1: if [M = the total number of modules then
2: Sort the modules according to their size and connection, and store the results in the list
3: end if
4: while [T]] > 0 do
5: m <- the first module from
6: Compute Wi VireMask OverlapMaste ask and BoundM ask for m
7: Select the set of valid bins Beat,
s.t. for each bin b E Beat. BoundMask(b
and OverlapMask(i] min((OerllapMask)
8:
Select a set of bins for greedy placement Bereedy from Beat,
where vb E Bgreedy: b E Buat A Wire byreedy] = min (ask)ssk)
9:
Randomly select a bin byreedy E Byreedy
10: Place the bottom left corner of m into byreedy
11:
Remove m from L
12:
end while
Return: A layout
5.1. Module Selection for Repositioning
and heights of net bounding boxes, quantify module m m's contribution to congestion by counting the number of nets that contain pins on yn and significantly contribute to layout congestion. Specifically, the RUDY value of a net is defined as the maximum RUDY value of the bins covered by its bounding box. We compute congm as the number pins on m belonging to nets whose RUDY values exceed r% of the overall layout's RUDY value, where r% is hyperparameter set to a high value (e.g. 98%). The formal definition is given in Equation (5), where rudy( (F.)) and rudy( [.) represent the RUDY value of the net containing pin p and the RUDY value of the entire layout L, respectively.
We perform guided module selection to enhance perfor- mance, where poorly placed modules are more likely to be removed and repositioned. This is achieved by scoring modules according to their impact on layout quality, with the removal probabilities proportional to their scores.
For a given module m, its scoring function defined as a weighted sum of three terms that reflect its influence on HPWL, congestion, and overlap, respectively, as shown in Equation (3). Each term undergoes normalization before being combined to compute the module score.
congm
Trudy(E,)> (.rdu(E,)2r%rrudy. PEP
Σ
(5)
overlapm scorem = wirelenm + λ1 congm + A2
(3)
Im Im
The third term quantifies the overlapped area of m with other modules, normalized by the size of m.
The first term, wirelenm represents the module m's 's impact on the wirelength. It is defined as the average Manhattan distance from each pin of the module to the center of the bounding box of the net that contains the pin, as shown in Equation (4), where Pmm denotes the set of pins on module m, and ep denotes the center of the bounding box of the net that contains pin p. A larger wirelen, implies that the module is placed farther from the center, increasing the likelihood of longer wirelength.
Subsequently, a specified ratio of modules is selected for removal and repositioning, with the selection probability being proportional to their respective scores. The selection probability of module is calculated by Equation 6, where M denotes the set of all modules.
Pm
select
EIEM score;
SCOrEm
(6)
5.2. Greedy Reposition with Efficient Mask Calculation
wirelemm
Σ d(p, ep) PEPm
(4)
The greedy placement strategy primarily optimizes the HPWL and overlap metrie, while the congestion metric is mitigated by identifying and repositioning modules that sig- nificantly contribute to congestion. The greedy placement strategy places modules in valid locations that minimize overlap while keeping them close to their connected coun- terparts to optimize HPWL. We employ this strategy for module repositioning because is highly efficient and has
PPm
The second term, congm. measures the module's impact congestion. We use RUDY as the congestion metric. The RUDY value of the layout is defined as the maximum RUDY value among all bins in the placement region (Spindler & Johannes, 2007). Since RUDY is determined by the widths
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EGPlace: An Efficient Macro Placement Method via Evolutionary Search with Greedy Repositioning Guided Mutation
been shown yield promising results in the previous work (Shi et al., 2023).
overlopy
1bg
9
The sequence of module placement substantially affects the final layout quality (Lai et al., 2022; Shi et al., 2023; Geng et al., 2024b). Our method orders module placement by both size and connectivity, placing larger and highly connected modules first. This strategy proves effective because larger modules constrain future placement options, and highly con- nected modules influence many other components through their wire dependencies.
Dus
covriey,
overlap between in and
placod models
model place
pin
bounding
MoundMari(Dss) =
(bre + w - 3 1 1- (verlopttsh -2 BommdHask(bu) = 0, (breMark(b..) OveriapMask((
To determine the placement location for a module, we com- pute masks to evaluate the quality of its placement at each position. Following previous methods (Lai et al., 2022; Shi et al., 2023; Geng et al.. 2024b), we use wire masks to evaluate the increase in HPWL and bound masks identify whether the module exceeds the chip boundaries. We further introduce overlap masks to quantify the additional overlap introduced by placing the module. Overlap masks calculate the exact increase in overlap between models, which differs from previous methods that use binary values to indicate whether placing a module at each position causes overlap. This helps reduce overlaps in scenarios with large module area coverage, where placement methods struggle to com- pletely eliminate module overlap, such as in the "ariane" benchmark in Appendix D.4.
Figure 2. Demonstration of Mask Calculation in Module Place- ment. When module m is placed in bin bs,7, exceeds the place- ment region, so the bound mask is set to 1. When m is placed in ba,1, the wire mask is determined by the increase in the half- perimeter of the net bounding box, while the overlap mask is computed by summing the overlapping area between mi and previ- ously placed modules. The overlap between two modules m and is efficiently calculated in linear time along the x- and y-directions and combined using an outer product. Placing m in ba,4 results in a bound mask of O, no increase in overlap, and minimal HPWL growth. Therefore, ba.4 is selected by the greedy strategy.
in one direction increases linearly, stays constant over a range, and then decreases linearly. This allows the overlap along the x-- direction to be computed in linear time. The same approach can be applied to calculate the overlap in the y-direction. The overlap results from both directions are combined using the outer product to compute the total overlap between the two modules. The overall overlap mask is obtained by summing the overlaps between module m and all placed modules. Suppose m is the i-th module to be placed, this computation has a time complexity of O(iB), which improves upon the OiiB²) complexity of the straightforward implementation. A detailed computation of module overlap is provided in Algorithm 2 in the Appendix.
Guided by these masks, the greedy strategy selects the valid position for each module that minimizes both HPWL and overlap increase. The valid positions are those that do not cause boundary violations. A detailed overview of this process is provided in Algorithm 1. Note that the population is also initialized using greedy placement, where the set of modules to be placed includes all modules in the circuit. When considering the placement of module m in Fig. 1, the meaning of the masks and how the placement location is chosen based on these masks are shown in Fig. 2.
Efficient Mask Computation. A straightforward imple- mentation of mask computation requires iterating over all bins in the placement area, resulting in a time complexity proportional to 12, where B is the number of bins per row in the placement region. Lai et al. (Lai et al., 2022) has provided an efficient method for computing wire masks and bound masks.
6. Experiments
Benchmarks, Baselines and Settings. Our experimental evaluation uses eight benchmark circuits from the widely used ISPD2005 dataset (Nam et al., 2005) and one circuit from the Ariane RISC-V V CPU design benchmark (Zaruba & Benini, 2019). The ISPD2005 benchmarks have been extensively used in previous macro placement research (Lai et al., 2022: 2023; Geng et al., 2024b), which en- ables direct performance comparisons with existing meth- ods. The Ariane benchmark provides an important real- world test case. Dataset characteristics are described in Appendix D.I. We benchmark EGPlace against leading placement methods, including reinforcement learning ap- proaches GraphPlace (Mirhoseini et al., 2021), DeepPR
We further propose an efficient algorithm for computing overlap masks to facilitate fast module repositioning. We compute the overlap between the current module m and each placed module to derive the overlap mask before placing module m. The efficient computation of overlap between two modules m and is demonstrated in Fig. 2. We exploit the linearity of overlap between modules m and n along both the z- and y-axes compute overlap in linear time. As module moves across the placement region, the overlap
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EGPlace: An Efficient Macro Placement Method via Evolutionary Search with Greedy Repositioning Guided Mutation
Table/ 1. HPWL Values (x 10") Achieved by Different Macro Placement Methods on the ISPD2005 Dataset The results of baseline methods are taken from Shi et al. (2023) and Geng et al. (2024), All results, except for those of the deterministic method MTUPlace3, are averaged over 5 runs with different random seeds and reported as mean + std. The symbols '4', '-', and 'ss" indicate the number of circuits where the method performs significantly better than, worse than, or comparable to EGPlace, based on the Wilcoxon rank-sum test at 0.05 signifieance level. Runtime comparisons for WireMask-FA -a,, EfficientPlace, and EGPlace are also provided to highlight the computational efficiency of our method. The best results are marked bold.
Method
adaptecl
adaptec2
adaptec3
adaptec4
bigbluel
bigblue3
+/- / =
Avg. Rank
SP-SA
18.84 + 4.62
117.36 8.73
115.48 + 7.56
120.03 4.25
5.12 1.43
164.70 + 19.55
0/6/0
7.7
NTUPlace3
26.62
321.17
328. 44
462.93
22.85
455.53
0/6/0
10.2
RePlace
16.19 1 2.10
153.26 1 29.01
111.21 1 11.69
37.64 1 1.05
2.45 1. 0.06
119.84 1. 34,43
1/5/0
5.8
DreamPlace
15.81 = 1.64
140.79 = 26.73
121.94 + 25.05
37,41 + 0.87
2.44 = 0.06
107.19 + 29.91
1/5/00
5.3
GraphPlace
30.10 + 2.98
351.71
+ 38.20
358.18 + 13.95
151.42 + 9.72
10.58 +: 1.29
357.48 +: 47.83
0/6/0
9.8
DeepPR
19.91 +: 2.13
203,51 +: 6.27
347.16 +: 4.32
311.86 +: 56.74
23.33 + 3.65
430.48 + 12.18
0/6/0
10.0
MaskPlace (3k)
7.62 0.67
100.24 + 13.54
87 37.99-2 + 3.25
3.04 = 0.06
90.04 = 4.83
0/6/0
5.7
Chipformer (2k)
6.62 1: 0.05
67.10 4: 5.46
76.70 1: 1.15
68.80 1: 1.59
2,95 + 0.04
72.92 1: 2.56
0/6/0
4.7
WireMask-EA (Ik)
0.05
64.38 + 4.43
58.18 1.04
59.52 + 1.71
2.15 2.15 0.01
59.85 +: 3.39
2/3/1
3.0
(3.16h)
(1.96h)
(L42h))
(2.44h)
(1.02h)
(6.99h)
EfficientPluce (Ik)
5,94 + 0.04
46.79 + 1.60
56,35 + 0.99
58.47 + 1.61
2.14 0.01
58,38 0.54
2/3/1
2.0
(0.84h)
(1.03h)
(2.11h)
(4.50h)
(1.20h)
(3.77h)
EGPlace (Ik)
5.85 + 0.08
37.39 + 1.58
61.09 + 1.00
55.54 + 1.64
2.24 = 0.03
50.89 + 4.69
1.8
(0.32h)
(0.76h)
(0.75h)
(1.18h)
(0.35h)
(1.30h)
(Cheng al., 2022), MaskPlace (Lai al., 2022), Chip- former (Lai et al., 2023), EfficientPlace (Geng et al., 2024b), the hybrid optimization method WireMask-EEA (Shi et al., 2023), analytical based methods DreamPlace (Lin et al., 2019), NTUPlace3 (Chen et al., 2008), RePlace (Cheng et al., 2018) and simulated annealing based method SP-SA (Murata et al., 2002). All evaluations run on standardized platform with NVIDIA RTX 3090 Ti GPU and Intel Xeon Silver 4210R CPUs (2.00GHz). Our code is provided at https://giuub..om//enggill I/APlace.
results in Appendix D.5.
We further compare EGPlace with existing methods by ana- lyzing the HPWL progression during the optimization pro- cess. The trend of the best HPWL over the number of iterations and runtime (in seconds) are plotted Fig. 3 and Fig. 9 in the Appendix, respectively. The results demon- strate that EGPlace outperforms existing methods 6 out of 8 benchmarks in terms of both sample and time efficiency.
Congestion Results. We investigate the congestion results of EGPlace, measuring congestion with the RUDY metric (Spindler& & Johannes, 2007). First, we set x in Equation (1) to O, focusing solely on optimizing HPWI. and overlap. The HPWL and RUDY values for the 8 benchmarks are presented in Table 8 in the Appendix. EGPlace achieves smaller HPWL and RUDY on 6 out of 8 datasets, aligning with the findings in Shi et al. (2023), where shorter HPWL may lead to smaller congestion.
Macro Placement Results. The macro placement results of EGPlace and the comparison methods on six benchmark circuits are summarized in Table D.2. For the two largest cir- cuits, "bigblue2" and "bigblue4", only subset of macros is considered to ensure computational feasibility, and the corre- sponding results are provided in Appendix D.2. Each place- ment method is executed with five different random seeds, and the mean and standard error of HPWL are reported. Among the six circuits, EGPlace achieves the best average ranking across all methods based on the Wilcoxon rank-sum test. In addition, as shown in Appendix D.2, EGPlace con- sistently outperforms all baseline methods on both bighlue2 and bigblue4. Across the entire ISPD2005 dataset, EG- Place surpasses the state-of-the ofitee-o-the-esse art EfficientPlace method, yielding a 9.3% reduction in HPWI.. EGGPlae also demon- strates high computational efficiency, completing 1,000 iter- ations in an average of 0.81 hours, which is 2.8 x and x.8x faster than EfficientPlace and WireMask- EAA, respectively. These results highlight the effectiveness of our guided mu- tation strategy in efficiently exploring the solution space, particularly for large-scale circuits such as "bigblue3" and "bigblue4". Additionally, we have conducted further ex- periments on the ICCAD2015 benchmark and present the
Moreover, we allow users to specify a1 to generate lay- outs with desired congestion levels. As "adaptec2" achieves the best results among benchmarks containing full set of modules, we conduct congestion experiments, along with ab- lation and parameter analysis, on this benchmark to demon- strate the advantages of our method and the functionality of its components. The RUDY and HPWI. values of layouts generated by EGPlace with A ranging from [0, 2.5] on "adaptec2" are shown in Fig. 4. We observe that increas- ing A leads to reduced congestion and increased HPWL in general. However, HPWL also influences congestion, as smaller HPWL values tend to result in lower global conges- tion and higher local congestion, as shown in previous work (Wang et al., 2000). This might explain the fluctuations in the HPWL and RUDY curves.
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EGPlace: An Efficient Macro Placement Method via Evolutionary Search with Greedy Repositioning Guided Mutation
adaptec1
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HPWLixee5)
(PWL(11e5)
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Iterations
Iterations
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EGPlace
WireMask
Efficienflaac
MaskPlace
Chiffommer
Figure 3. Comparison of HPWL Trend Over the Number of Iterations. We run the released code of WireMask-Ei EAA and EfficientPlace generate the results.
HPW CA 055
Normalized Fitness
RUDY
38
0.88
36
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EGPlace
W/o module order
34
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w/o guided removal
w/o greedy placement
(a) RUDY
(b) HPWL
0.24
0.36
0.00
200
400
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800
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Figure RUDY and HPWL of Layouts Generated by EGPlace with Different D Values. We run EGPlace the "adaptec2" benchmark and present the RUDY and HPWL results subplots (a) and (b), respectively.
Iterations
Figure 5. Ablation Studies. test EGPlace on different con- figurations using the "adaptec2" benchmark and plot the average normalized fitness values of all individuals in the population each iteration. The shaded area represents the standard error of the fitness values across the individuals.
Mixed-size Placement Results. Modern integrated circuits contain both macro blocks and numerous smaller standard cells, making mixed-sizz placement critical real-world requirement. In this experiment, we demonstrate the effec- tiveness of our method in mixed-size placement by using EGPlace for macro placement and DreamPlace (Lin al., 2019) for standard cell placement. The mixed-size place- ment results is provided in Table D.7 in the Appendix. The results show that our macro placement approach positively impacts the mixed-size placement quality.
selecting them with probability proportional to their impact on the layout quality; (4) EGPlace: The full configuration of our method. Performance evaluation uses normalized fitness values tracked across optimization iterations, with results presented in Fig. 5. The complete EGPlace system consistently outperforms all ablated variants. The greedy repositioning strategy proves particularly important, with its removal causing the most substantial performance degrada- tion. The quality-guided module removal mechanism also provides significant benefits, improving both convergence speed and final solution quality. The module ordering strat- egy contributes measurably overall system performance.
Ablation Studies. We conduct ablation studies to investi- gate our choices' impact on performance by testing the per- formance on "adaptec2" with different configurations: (1) w/o greedy reposition: We randomly choose valid loca- tion position the modules, rather than placing them in the location that minimizes the increase in HPWL; (2) w/o mod- ule order: In each step, we randomly select a module for placement, rather than ordering the modules based on their sizes and connections; (3) w/o guided removal: We select modules for removal with uniform probability, instead of
Parameter Sensitivity Analysis. We analyze the impact of population size and the module removal ratio on the muta- tion operator. The fitness value and HPWL of the layouts on "adaptec2" generated by EGPlace with population sizes between [1, 9] over 1,000 iterations are shown Fig. The
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EGPlacc: An Efficient Macro Placement Method via Evolutionary Search with Greedy Repositioning Guided Mutation
Normalized Fitness
0.8-
Limitations and Future Research. While the proposed EGPlace method demonstrates strong performance in macro placement and achieves competitive results surrogate metrics such as HPWL and RUDY, the current design does not sufficiently account for mixed-size placement and does not directly target final Power, Performance, and Area (PPA) design objectives. Extending EGPlace to better support mixed-size placement and align more closely with PPA- driven optimization represents important direction for future work. Recent advances, including MaskRegulate (Xue et al., 2024), which introduces a Regulate Mask to guide mixed-size placement, and LaMPlace (Geng et al., 2024a), which leverages a learned L-Mask to reflect PPA objectives, offer promising techniques. Integrating those masks into EGPlace holds potential for further improving placement quality and enhancing real-world applicability.
HPMLLXTES)
0.6
38
0.4
0.2
36-
Population Size
Population HPW
Normalized Rinness Values
Figure 6. Layout Quality of EGPlace with Different Population Sizes. We run EGPlace for 1,000 iterations on "adaptec2" and plot the normalized fitness values and HPWL of the resulting layouts in subfigures (a) and (b), respectively.
HPAA/xle5
60
(ime(min)
000010 1.
20
46
Acknovledgements
400 Iterationn
600
1000
80
Remove Ratio(56) (b) Bunlime
(4) Normalized Fitness Values
This work is supported by NSFC (No. 62272008). We would like to thank the reviewers for their valuable sugges- tions.
Figure 7. Layout Quality of EGPlace with Different Removal. We run EGPlace for 1,000 iterations on "adaptec2" and plot the normalized fitness values and runtime in subfigures (a) and (b).
Impact Statement
The increasing complexity of modern integrated circuits demands more sophisticated electronic design automation (EDA) tools, particularly for chip placement optimization. Our work advances this critical area by introducing EGPlace, an efficient placement method that significantly improves both placement quality and computational efficiency. The method's 's ability reduce wirelength by 6.7% to accelerate optimization by 7.8x compared to state-of-the-art methods demonstrates its practical value for industrial chip design.
results indicate that a population size that is too small (e.g.. 1 or 2) may lead to under-exploration of the solution space, resulting in lower layout quality. Conversely, a population size that is too large (e.g.. or 9) can reduce the average number of mutations applied to each layout within the spec- ified total number of iterations, thus lowering the quality. The optimal population size lies between 3 and 6.
We test different ratios (ranging from 10% to 100%) of modules for removal and repositioning in EGPlace, and run our method for 1,000 iterations on "adaptec2". The HPWL and runtime are shown in Fig. We observe that a higher removal ratio leads to a slightly smaller HPWL, but also increases the runtime.
Beyond immediate performance gains, EGPlace's unified optimization approach establishes new directions for seal- able placement tools. These innovations become particu- larly valuable the semiconductor industry moves toward more complex designs involving 3D integration and het- erogeneous architectures. The method's 's flexible conges- tion control also enables designers to generate application- specific layouts, supporting diverse requirements across different market segments from mobile computing to high- performance systems.
7. Conclusion and Future Work
This paper presents EGPlace, evolutionary search place- ment method with a novel greedy repositioning guided muta- tion operator for macro placement optimization integrated circuit design. In order to overcome the challenges in hybrid methods, EGPlace performs greedy repositioning guided mutation achieve good performance, and integrates layout reconstruction into the mutation operator to improve effi- ciency. Experimental evaluation on industry-standard bench- marks show that EGPlace achieves consistent improvements in layout quality while significantly reducing computational requirements compared to state-of-the-an methods.
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EGPlace: An Efficient Macro Placement Method via Evolutionary Search with Greedy Repositioning Guided Mutation
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EGPlace: An Efficient Macro Placement Method via Evolutionary Search with Greedy Repositioning Guided Mutation
Mutation
Greedy Genotype-to- phenolype
WireMask-EA
Random Swap
d Reposition
HPWL HPr HPPWL
A Layout
Population
Mutation
EGPlace
Module
Pins
Select Modules
Morkiiwe Repositio
Ner1
Repositioning
Nel2
Greedy Reposition
Figure 8. Comparison between EGPlace and WireMask EA.
Appendix
The Appendix provides a comprehensive technical exploration of EGPlace, offering detailed insights into its algorithmic design, computational strategies, and experimental validations. It elaborates on further technical details that underpin proposed macro placement approach.
The supplementary materials four primary areas: comparative analysis with WireMask- -A,, in-depth examination of fundamental placement concepts and metrics, rigorous assessment of the computational complexity of the proposed algorithms, and an extensive presentation of experimental results across multiple benchmarks.
By presenting these technical details, the appendix offers researchers and practitioners a thorough understanding of the methodological innovations and performance characteristies of EGPlace, which extends beyond the summarized findings in the main manuscript. This supplementary content not only substantiates the research claims also provides a transparent view into the algorithmic intricacies that enable the framework's superior performance integrated circuit macro placement optimization.
A. Comparison between EGPlace and WireMask-EA
We analyze the differences between our EGPlace and the statc-of-thed of-thh--tttetttt combined method WireMask-ER (Shi et al., 2023), both of which utilize evolutionary search as the backbone. Fig. illustrates the layout adjustment process for layout selected from the population both methods. The main improvement of our method compared to WireMask EAA lies two aspects: firstly, WireMask-FA utilizes random swap mutations, where poorly selected module pairs may lead to low-quality solutions. In contrast, EGPlace selects and repositions modules based their impact layout quality, increasing the likelihood of producing higher-qualit mutated layouts. Secondly, WireMask-E. EA requires a separate step to transform the genotype into a phenotype. This step positions all modules in locations that minimize HPWL increment and are closest to those in the genotype. In comparison, EGPlace incorporates greedy placement directly into the mutation operator, requiring only the repositioning of selected modules, which significantly improves efficiency.
B. Basic Concepts and Placement Metrics
The key concepts in chip placement are described bellow.
Chip: A chip a rectangular region, often divided into B x B bins to facilitate metric calculations, A larger value provides higher resolution for module placement.
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EGPlace: An Efficient Macro Placement Method via Evolutionary Search with Greedy Repositioning Guided Mutation
Table 2. Notations for Complexity Analysis
Symbols
Meanings
B
The number of bins in each row column of the placement region
A module
M
The set of modules
P
The set of pins
Pm
The set of pins on module m
N
The set of nets The greedy placement process described in Algorithm The module selection process outlined in Section 5.1 The ratio of modules that undergo repositioning
f fgreedy eeelect
rm%
Modules are rectangles with fixed sizes and orientations. Macro cells are primarily functional modules, such as Dynamic Random Access Memory (DRAM) and caches. Standard cells are smaller in size, mainly consisting of logic gates.
Module:
A pin is an input/output interface on a circuit module. It is fixed relative to the module and connects the module to others through nets.
Pin:
Port:
A port is an input/output interface located at fixed positions on the chip. It connects to other pins or ports through
nets.
Net: A net consists of set of connected pins. In digital circuits, pins in a net receive the same 0/1 signal.
Metrics measuring the layout quality include Half Perimeter Wire Length (HPWL) (Chen et al., 2006), Rectangular Uniform wire DensitY (RUDY) (Spindler & Johannes, 2007) and overlap rate (Lai et al., 2022). HPWI. is an commonly used estimation of the routing wirelength. A short HPWL implies low routing resources, low delay, and low energy consumption. In HPWL calculation, the net bounding box is defined the smallest rectangle enclosing all the pins of the net. The total HPWL of layout is the sum of the HPWL of all nets, shown in Equation (7) (Chen et al., 2006), where E is net containing pin p.
HPWL =
Σ (max Ps E
min Pz + max Py -min Py) PEE
PEE
PEE
P
RUDY measures the congestion of the layout. Higher congestion may result in increased signal transmission delay, larger power consumption, and lower performance. The value of RUDY for each bin of the placement region is defined the sum of the reciprocal of the height and width of the bounding boxes of all nets covering it. The value of the layout's RUDY is the maximum of the RUDY values for all bins.
The overlap rate is defined as the ratio between the modules' overlapping area and the total chip area.
C. Implement Details and Complexity Analysis
C.1. Efficient Computation of Module Overlaps
We provide detailed explanation of the efficient computation of module overlap along the x-direction in Algorithm 2. This algorithm computes the overlap in O(B), where B denotes the number of bins per row in the placement region. The total overlap is obtained by combining the overlap lengths along the x- and y-directions between each pair of modules.
C.2. Workflow of the Evolutionary Search Backbone and Overall Complexity Analysis
The overall workflow of the evolutionary search backbone is outlined in Algorithm 3. The notations for complexity analysis demonstrated in Table 2. The time complexity is analyzed as follows: it takes C( to initialize the population. In each iteration, a layout selected, and a mutation operator is applied to the layout. The mutation operator consists of two phases: module selection and repositioning, leading time complexity of C'Ssctect + rm% fgreedy). Therefore, the
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EGPlace: An Efficient Macro Placement Method via Evolutionary Search with Greedy Repositioning Guided Mutation
Algorithm 2 Calculation for Overlap between Two Modules in the x-direction
Input: The placement area divided into B x B bins, a module m to be placed, and module n with its bottom right corner placed at (n.zz n.y).
Output: The overlap between module m and in the x-direction, denoted as overlaps.
1: overlap=[B|[B] + O
2: col t t (0, n.z - m. m.wihth)
3: while col < min(n.x, n. + n.width w.wihhh) do
4: overlap, < col m.width n.
5: col +- col +1
6: end while
7: while col < n.E + n.wiith - m.width do
8: overlaps [col, [col,
< m.width
9: col +- col +
10: end while
while col < .mnn(B, n. + n.width) do
12: overlapz [col,; <- n.x + n.width col
13: col +- col +
14: end while
Return: overlaps
overall time complexity is O(ng (( + Amaz (C(feelect + rm% fgreedy))). A detailed analysis of the complexity of feelect and fgreedg is provided in the following paragraphs.
The module selection process, Santent, involves calculating the score for each module based on Equation (3), which consists of three terms. The first term, wirelemm. computes the sum of the Manhattan distances between each pin the module and the center of its net bounding box. The net bounding box positions are recorded during the greedy placement, so the center coordinate of each bounding box can be calculated in O(1) time. Thus, the calculation of wirelen, for all modules requires 0(1) time for each pin, resulting in a total time complexity of O(P)). For the second term, congm. we first compute the congestion of each bin in O( time using the recorded net boundaries. Then, the RUDY value for every net and the layout computed by aggregating the values of the corresponding bins, resulting complexity of O( When calculating congm for each module, we check whether the congestion of the net associated with each module exceeds the threshold with in (1)) time. The total time for this is O(P))). Therefore, the overall time complexity for this term is O(I (PI), which can be simplified to O(IPl) as |N| < [P]. The third term, overlapm. can be calculated in O([M)) by aggregating the module coverage for each bin recorded during greedy repositioning. The overall module selection process results in a complexity of O() PI M.
fgrendy involves the computation of the wire mask, bound mask and overlap mask before the placement each module. We adopt the idea in MaskPlace(Lai al., 2022) optimize wire mask calculations, which reduces the complexity O(BPm) by caching the boundaries of nets. The bound mask computation can be easily simplified to (BB) by directly verifying the grids near to the chip boundaries. Suppose is the i-th module to be placed, the overlap mask computation for results in a time complexity of O (Bi). Therefore, the total computation time before placing one module result in O([PI + [M and the overall computation time of fgreedy is (((PP) + [M]
D. Experimental Details and Additional Results
D.I. Dataset and Experimental Details
The statistics of the ISPD2005 circuit benehmark (Nam et al., 2005) and the Ariane RISC-V CPU design benchmark (Zaruba & Benini, 2019) are demonstrated in Table 3, where "Macros(to place)" stands for the number of macros that is chosen for placement by EGPlace. We have also conducted further macro placement experiments on the modern ICCAD2015 benchmark (Kim et al., 2015), and present the statistics in Table 4.
The hyperparameters used in the experiments are configured as follows: the population size is set to 5; the number of bins is 224 x 224; the removal ratio in the mutation operator is set to 50%; the ratio r% in module score computation is set to 98; A in the objective function set to 0.1 As congestion is not considered previous methods, we set the congestion weight
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EGPlace: An Efficient Macro Placement Method via Evolutionary Search with Greedy Repositioning Guided Mutation
Algorithm 3 Workflow of Evolutionary Search Backbone
Input: placement region divided into B bins, netlist N that defines the features and connectivity of the modules, population size n, number of initial layouts no S n, hyperparameters X1 and x2 balance the metric weights in the objective function, and the maximum number of iterations I mazz
Output: An optimized layout of circuit modules.
1: Initialize an empty layout population P of size n1
2: 5-0
3: while Ygg do
4: Generate initial layout L using Algorithm and add it to P
5: end while
6: 5-0 0
7: while i < Imaz do
8: Select a layout I. from with probability given by Equation (2)
9: Select set of modules M for repositioning from according to Section 5.1.
Remove M from L
11:
Obtain the mutated layout In by repositioning M according Algorithm 1.
12:
P 1-- P }
13:
while P|> k: do
14:
Remove the layout in P with the lowest fitness
15:
end while
16:
i i+i+1
end while
Return: The layout in P with the highest fitness
Table Statistics of the ISPD2005 Circuit Benchmark
Circuit
Macros
Macros(to place)
Standard Cells
Nets
Pins
Ports
Area Util%)
adaptecl
543
543
210904
221142
944063
0
55.62
adaptec2
566
566
254457
266009
1069482
0
74.46
adaptec3
723
723
450927
466758
1875039
0
61.51
adaptec4
1329
1329
494716
515951
1912420
0
48.62
bigbluel
560
560
277604
284479
1144691
0
31.58
bigblue2
23084
1024
534782
577235
2122282
0
32.43
bigblue3
1293
1293
1095519
1123170
3833218
0
66.81
bigblue4
8170
1024
2169183
2229886
8900078
0
35.68
ariane
932
932
0
12404
22802
1231
78.39
A to 0 in the objective function for fair comparison. Notably, A₁ and X2 can be adjusted by the user to generate desired layouts.
D.2. Results on the "bigblue3" and "bigblue4" Circuits
To ensure computational feasibility on the large-scale circuits "bigblue2" and "bighlue4", we select the first 1,024 macros based on our module ordering strategy described in Section 5.2. The results are presented in Table ??. The results show that EGPlace achieves the lowest HPWL on both benchmarks, outperforming the recent EfficientPlace method by 8.5% and 28.7% %, respectively. addition, EGPlace demonstrates substantially lower runtime compared to both EfficientPlace and WireMask-EA.
D.3. Time Efficiency
Figure 9 demonstrates the HPWL trend over runtime in EGPlace and the comparation methods. The results show that EGPlace achieves better results on out of benchmarks.
15

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EGPlace: An Efficient Macro Placement Method via Evolutionary Search with Greedy Repositioning Guided Mutation
Table 4. Statistics the ICCAD2015 Circuit Benchmark
Circuit
Macros
Macros (to place)
Stdandard Cells
Nets
Pins
superbluel
56898
512
1159346
1215710
3767494
superblue3
58970
512
1160765
1224979
3905321
superblue4
45289
512
756979
802513
2497940
superblue5
76676
512
1014341
1100825
3246878
superblue7
72256
512
1865884
1933945
6372094
superblue10 10
101837
512
1786523
1898119
5560506
superblue16
4868
512
981140
999902
3013268
superblue18
27099
512
744947
771542
2559143
adaptec1
adaptec2
adaptec3
adaptec4
7.5
HPWL(X1e5)
HPW (1)
HPWWLix1e5)
90
7.0
60
HPVL(x1en
6.5
30
80
70
70-
6.0
60
2000
1000
2000
1000
4000
Time(min)
Timelmin)
Timelmin)
Time(min)
bighluel
bigblue2
bigblue3
bigblued
3.25
HPWLixess (el.ee
3.00
HPWL (11e)
26
1.00
24
HPWLIS
100
2.50
80
2.25
50
250
500
750
1250
500
1000
1500
2000
1060
2000
3000
4000
2000 Time(min)
3000
4000
Time(min)
Time/min)
MaskPlace
Chipformer
Figure 9, Comparison of HPWL Trend Over the Runtime(s).
16

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EGPlace: An Efficient Macro Placement Method via Evolutionary Search with Greedy Repositioning Guided Mutation
Table 5, HPWL Values( 10*) Obtained from Macro Placement Methods on "bigblue2" and "bigblue4" circuits. modules as macros for "bigblue2" and "bigblue4" run the comparison methods with their default hyperparameter configurations. We report the runtime of WireMask-EA, EfficientPlace, and EGPlace to highlight the efficiency of our method. The best results are marked in bold.
circuiits. We select 1,024
Benchmark
MaskPlace (3k)
Chipformer (2k)
WireMask-EA (1k)
EfficientPlace (1k)
EGPlace (Ik)
bighlue2
18.64 0.63
14.06 + 0.47
11.35 + 0.15 (19.83h)
12.20 + 0.29 (2.00h)
11.16 0.47 (0.58h)
bigblue4
117.96 + 5.62
120.66 8.03
82.96 = 2.32 (13.87h)
86.86 + 3.41 (2.85h)
61.90 2.73 (1.26b)
Table HPWL and Overlap Results the "ariane" Benchmark. We obtain the result of MaskPlace and DreamPlace running their released code. We modify the code of EfficienttPaaee to run on the "ariane" benchmark and include ports in HPWL calculation for fair comparison.
Method
MaskPlace
DreamPlace
EfficientPlace
EGPlace
Overlap rate (%)
3.27
LG failed
3.37
1.24
HPWL (x109)
14.63
LG failed
12.47
7.91
D.4. Results on the "ariane" Benchmark
We conduct experiments on the "ariane" benchmark to evaluate the effectiveness the overlap mask described in Section 5.2. As shown in Table 3, the "ariane" benchmark consists of macro modules covering 78.39% of the chip area, so is difficult for chip placement methods to generate layouts without overlap. Our goal is produce layouts with minimal HPWL and little overlap possible.
We compare EGPlace with the ttate-of-the-arr analytical method DreamPlace and RL-baaeed methods MaskPlace and EfficientPlace. MaskPlace and EfficientPlace use position masks with binary values to indicate whether module placement causes overlap, whereas our method employs an overlap mask that calculates the exact overlap value and combines it with wire mask for greedy placement. Table presents the results on the "ariane" benchmark. The result shows that DreamPlace results in significant overlap, leading to legalization failure. EGPlace achieves significantly lower overlap rate than MaskPlace and EfficientPlace, demonstrating the effectiveness of the overlap mask in reducing module overlap.
D.5. Results on ICCAD2015 Benchmark
We further conduct experiments on the ICCAD2015 benchmark. The placement files in LEF/DEF format are converted into bookshelf format using ChiPBench (Wang et al., 2024), and the 256 largest modules in each circuit are selected for macro placement. The results are presented in Table 7. EGPlace achieves HPWL reductions of 49.5%, 17.4%, and 7.4% compared to the baselines DreamPlace, WireMask-EA, and EfficientPlace, respectively. These results demonstrate the effectiveness of our method in macro placement.
Table Comparison of HPWL Results( 10") on the ICCAD2015 benchmark different methods. We run WireMask-FA and EfficientPlace with the number of grids set to 224 and 512, respectively, while other settings remain default. We highlight the hest results in bold and underline the second best results.
Method
superbluel superblue3
superblue4
superblue5
superblue7
superblue
superblue16
superblue 18
DreamPlace Place
2.53
15.19
3.44
21.36
5.09
12.99
1.02
KoreMas-EAAlIl
1.37
4.40
2.11
11.00
2,86
1.18
2.85
1.46
EfficientPlace( Ik)
1.26
3.81
1.99
9.70
2.86
0.93
2.79
1.12
ECPlace(1k)
1.31
3.22
1.91
8.62
2.90
1.00
2.03
0.96
D.6. Congestion Results
A comparison of RUDY and HPWI. between EGPlace and the comparative methods is illustrated in Fig. 8. We set the weight of RUDY in the objective function A₁ to O, and demonstrate the congestion levels of layouts obtained by optimizing solely HPWL and overlap. The results indicate that EGPlace achieves lower congestion on 6 out benchmarks, aligning with findings in EAA (Shi et al., 2023), which suggest that lower HPWL may contribute to reduced congestion. Furthermore, by adjusting \₁, we can generate layouts that meet specific congestion requirements.
17

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EGPlace: An Efficient Macro Placement Method via Evolutionary Search with Greedy Repositioning Guided Mutation
Table Comparasion on HPWL(x 109) and Congestion Results. We obtain the results the comparison methods by running their
publicly released code. For a fair comparison, the RUDY values are calculated on the placement region divided into 224 x 224 bins. Following previous methods (Shi et al., 2023; Geng et al., 2024b), we standardize the RUDY value of EGPlace We highlight the best
results in bold.
Benchmarks Metrics
adaptec1 HPWL
adaptec2
adaptec3
adaptec4
highluel HPWL
bigblue2 HPWL
bighlue3
highlue4
Cong.
HPWL
Cong.
HPWL
Cong.
HPWL
Cong.
Cong.
Cong
HPWL
Cong.
HPWL
Cong.
MaskPlace
7.09
1.51
78.57
3.23
118.32
1.00
91.22
3.80
2.67
1,00
17.49
2.17
96.91
2.56
112.87
0.59
WireMask EAA
5.93
0.97
54.76
1.23
59.31
1.01
59.47
3.10
2,16
2.63
11.23
1.34
66.15
1,56
79.59
0137
EfficientPlace
5.99
1.05
45.37
2.45
57.37
1.69
59.04
2.20
2.30
1.18
12.30
1.00
58.08
1.22
88.60
0.26
EGPlace
5.75
1.00
37.99
1.00
63.05
1.00
$6.09
1.00
2.23
1.00
10.49
1.00
50,50
1.00
$8.96
1.00
D.7. Mixed-size Placement Results
We perform mixed-size placement by adopting the two-phase approach in EfficientPlace (Geng al., 2024b): (1) In the first phase, we fix all macros placed by EGPlace, and utilize the global placement step of DreamPlace to position the standard cells, generating coarse layouts. (2) In the second phase, we set all modules movable and carry out a comprehensive mixed-size placement process using DreamPlace, which includes the global placement step, legalization, and the detailed placement step. The mixed-size placement results are shown in Table D.7. The results of the comparison methods are taken from the EfficientPlace paper (Geng et al., 2024b) which adopts previous version of DreamPlace for mixed-size placement. However, since recently DreamPlace 4. 4.1.0 (Chen et al., 2023) has shown significant improvements over its previous version in mixed-size placement, we also conduct experiments using DreamPlace 4. 4.1.0 O and reported the results. The results show that layouts generated by EGPlace followed by DreamPlace 4.0 achieve average HPWL reduction of 6.5% across eight circuits compared to EfficientPlace, demonstrating that good quality macro placement results serve good initial solutions for mixed-size placement. We also find that integrating EGPlace with DreamPlace 4.1.0 leads to substantial improvements over the previous version of DreamPlace, however, these results remain slightly inferior to those achieved by DreamPlace 4.1.0 alone. As this work primarily focuses on macro placement, we leave further enhancements in mixed-size placement for future work.
Table Comparison on HPWL(x10") for Mixed-size Placement on Different Datasets. We conduct further experiments on DreamPlace 4.1.0 Da as they achieve significant improvement in placement quality than the previous versions. The results for comparison methods is are from the paper of EfficientPlace (Geng et al., 2024b). We mark the best results in bold and underline the second best results.
Method
adaptecl
adaptec2
adaptec3
adaptec4
bighluel
bigblue?
bighlue3
bigblue4
DreamPlace
13.84
1.74
24.37 4: 1.13
10.06
36.51
0.56
175.86 2.23 63.34
DreamPlace 4.1.0
6.85 0.24
8.50
0.20
13.23
0.15
13.15
+ 0.22
8.17 = 0.01
9.89 0.24
28.52
0.46
0.55
10.86 0.01
12.98
0.58
26.14 1 0.07
23.52
0.01
10.64 0.01
54.98
1.06
WireMask EAADreamPlace
8.93 1 0.01
9.20 1 0.05
21.72
0.01
20.51
1. 0.01
10.35 0.02
14.88 1 0.01
42.52
0.11
171.23 1 0.48
EfficienPlace+Dreemmee
7.20 = 0.12
9.20
0.61
16.49 = 1.07
14.70
0.25
8.67 = 0.10
9.98
0.02
0.96 28.48
125.02 + 0.02
EGPlace++ DreummPlcee
- 0.11
9.06
0.36
14.15
0.19
15.69 + 0.09
8.99
0.06
9.63 + 0.03
29.08
0.23
62.32
0.32
Drraace-DDeamaaeeeeeea 4.1.0
6.70
0.36
8.02 0.22
13.84
13.44
0.03
8.38 0.08
9.57
0.03
32.01
0.32
66.63 0.07
18

---

EGPlace: An Efficient Macro Placement Method via Evolutionary Search with Greedy Repositioning Guided Mutation
adaptec1
adaptec2
adaptec3
adaptec4
bigblue1
bigblue2
bigblue3
bigblue4
Figure 10. Visualization of Mixed-size Placement Results the ISPD 2005 Dataset. Macros marked in red, while standard cells are marked in blue.
19


Reviews:
[{"review_id": "uWDMoBWWBA", "reviewer": "Reviewer_pQfq", "summary": "This paper presents EGPlace, an evolutionary optimization framework for macro placement. EGPlace addresses these issues with two key parts: 1) a greedy repositioning: guided mutation operator that targets critical layout regions and 2) an efficient mask computation algorithm. Experimental results on ISPD2005 and Ariane CPU benchmarks show that EGPlace reduces wirelength compared to WireMask-EA and EfficientPlace while achieving speedups. It also performs well in congestion control and mixed-size placement scenarios.", "questions": "", "limitations": "", "rating": 3, "confidence": null, "soundness": null, "presentation": null, "contribution": null, "strengths": "", "weaknesses": "", "quality": null, "clarity": null, "significance": null, "originality": null, "strengths_and_weaknesses": "", "was_revised": false, "final_justification": "", "rebuttal": "Thank you for your constructive review and valuable suggestions! Below, we provide a detailed response to your questions and comments. If any of our responses fail to sufficiently address your concerns, please inform us, and we will promptly follow up.\n\n**Experiments on the ICCAD 2015 Benchmark**\n\nIn order to show the generalizability of EPlace, we further conduct tests on 5 circuits on the ICCAD 2015 dataset, selecting 1024 macros with the largest sizes for placement. The macro placement results, compared to EfficientPlace, are presented in Table (a).\n\n## Table (a): HPWL (×10⁷) for Macro Placement on the ICCAD 2015 Benchmark\n| Method          | Superblue1 | Superblue3 | Superblue4 | Superblue5 | Superblue7 |\n|--------------- |------------|------------|------------|------------|------------|\n| EfficientPlace | 77.59      | 34.33      | 84.93      | 539.40     | 29.05      |\n| EGPlace       | 12.47      | 29.47      | 17.60      | 78.57      | 29.21      |\n\nThe results show that EGPlace outperforms EfficientPlace on 4 out of 5 benchmarks. The significantly higher HPWL of EfficientPlace on Superblue1, 4, and 5 may result from the poor placement of the first few modules in nodes close to the root in MCTS, which ultimate affects the overall placement quality. We plan to include the full results in the revised version. \n\nWe also attempted macro placement using DreamPlace 4.1.0 on the BookShelf file but encountered failures during the legalization stage. We will continue to investigate this issue and, if time permits, report the full results on the ICCAD 2015 benchmark, along with results for DreamPlace and other baseline methods.\n\n**Discussion on Recent Related Work**\n\nWe will incorporate related work [1-3] into the related work section. Both [1] and [2] train RL policies that iteratively adjust module locations, as refining modules on the full layout enables capturing more comprehensive state information, which is beneficial for improving layout quality. We share the same observations with these methods. However, unlike these methods, we adjust the layout using efficient heuristic rules combined with a certain degree of randomness instead of training RL agents. Specifically, we select modules based on their scores and reposition them greedily, while utilizing an evolutionary algorithm to maintain a pool of good layouts. The search strategy we used is simple but effective in obtaining good quality layouts. Additionally, our method provides significant advantages in terms of efficiency.\n\nLaMPlace [3] makes significant advancements in incorporating cross-stage PPA metrics to guide layout generation. It trains a predictor to estimate these metrics through offline learning and generates learnable masks to assist placement. Our method, EGPlace, which leverages an evolutionary framework and adjusts module locations through a greedy reconstruction-based operator, is orthogonal to LaMPlace. The learnable masks related to PPA metrics generated by LaMPlace can be integrated into our approach to guide module adjustment, potentially achieving better performance in terms of PPA metrics.\n\n**Response on PPA Evaluation**\n\nWe have attempted to use OpenRoad to evaluate the PPA metrics over the past few days. However, as noted in the ChipBench paper, OpenRoad is not compatible with the ISPD2005 and ICCAD2015 datasets due to the lack of essential information (e.g., necessary design kits). Therefore, We have to switch to \"ariane133\" benchmark which is supported by OpenRoad. The evaluation process is time-consuming. Due to time constraints, we plan to upload our results once the evaluation is completed.\n\n**WireMask-EA is proposed at NeurIPS 2023 rather than 2024**\n\nWe sincerely apologize for the typo. We will correct this issue in the revised version.", "claims_and_evidence": "Yes, the empirical claims are well supported. However, there are some concerns about the evaluation criteria.", "methods_and_evaluation_criteria": "The proposed approach demonstrates promising efficacy in optimizing HPWL.\n\nHowever, there are several key considerations:\n\n1. PPA Evaluation Gap. While HPWL serves as an important proxy metric, numerous studies in EDA and ML have highlighted its limited correlation with final PPA performance (e.g., timing, routed length, etc). I strongly recommend incorporating PPA evaluations using established open-source platforms such as OpenRoad [1] or the framework described in [2]. These tools enable final PPA evaluation, which would substantially imrpove this paper.\n\n2. Expanded Benchmark. Testing on a broader range of more recent industrial chip designs (e.g., ICCAD 2015) would strengthen the generalizability claims, providing a more robust validation of the algorithm's adaptability.\n\nReferences:\n[1] OpenRoad Project. https://github.com/the-openroad-project\n\n[2] Benchmarking End-to-End Performance of AI-Based Chip Placement Algorithms. arXiv, 2024.", "theoretical_claims": "N/A", "experimental_designs_or_analyses": "The experiments and analyses on HPWL make sense to me.\n\nMy main concerns are regarding the evaluation and the need for more benchmarks.", "relation_to_broader_scientific_literature": "N/A", "essential_references_not_discussed": "There are many recent papers on reinforcement learning for chip placement [1-3], which I believe should be at least discussed if not be compared.\n\n[1-2] can be categorized into RL for adjustment-based methods. [3] applies a learnable mask and achieves sota performance.\n\n[1] Reinforcement Learning Policy as Macro Regulator Rather than Macro Placer. NeurIPS, 2024.\n\n[2] Mixed-Size Placement Prototyping Based on Reinforcement Learning with Semi-Concurrent Optimization. ASPDAC, 2025.\n\n[3] LaMPlace: Learning to Optimize Cross-Stage Metrics in Macro Placement. ICLR, 2025.", "other_strengths_and_weaknesses": "Strengths \n1. The proposed mutation operator make sense to me, which can significantly improve exploration efficiency and HPWL results compared to random mutations in WireMask-EA. \n2. The efficient mask computation is also important to rapidly evaluate potential module positions, reducing computational complexity from quadratic to linear. \n3. The framework illustration figure is impressive and clear.\n\nWeaknesses\n1. See the evaluations mentioned above.", "other_comments_or_suggestions": "1. WireMask-EA is proposed at NeurIPS 2023 rather than 2024.", "questions_for_authors": "N/A", "summary_of_paper": "", "summary_of_recommendation": "", "technical_quality": "", "clarity_of_presentation": "", "potential_impact": "", "robotics_focus": "", "quality_of_limitations": "", "questions_for_rebuttal": "", "reasons_to_accept": "", "reasons_to_reject": "", "questions_to_authors": "", "extra_scores": {}}, {"review_id": "xTXCKuTVOo", "reviewer": "Reviewer_WoFK", "summary": "This article presents a new mutation operator for evolutionary algorithms designed for the problem of macro placement. The new operator, the Greedy Repositioning Guided Mutation, constructs a set of good placements for a module and then randomly selects one. Compared to a traditional mutation operator, it therefore encourages good placement of the module, while still allowing for search. This mutation operator is combined with a standard evolutionary algorithm and tested on a standard benchmark in macro placement.", "questions": "", "limitations": "", "rating": 3, "confidence": null, "soundness": null, "presentation": null, "contribution": null, "strengths": "", "weaknesses": "", "quality": null, "clarity": null, "significance": null, "originality": null, "strengths_and_weaknesses": "", "was_revised": false, "final_justification": "", "rebuttal": "Thanks for your valuable suggestions! \n\n**Motivation for choosing ISPD2005 and Additional Experiments on ICCAD2015**\n\nThe major competitors, including MaskPlace, EfficientPlace, and WireMask-EA, conduct experiments on ISPD2005, so we use the same setting for a fair comparison. We also perform experiments on ICCAD2015, with results shown in Table (a) (see feedback to Reviewer pQfq), where the HPWL for placing the largest 1024 macros is reported and will be included in the revised version.\n\n**Response Regarding Baseline Methods**\n\nWe omitted baselines SP-SA, NTUPlace3, RePlace, DREAMPlace, Graph Placement, and DeepPR, as they have been compared with our main competitors, MaskPlace and WireMask-EA, in their respective papers, where our competitors outperformed them. We plan to include results from these baselines in revised version for a more comprehensive comparison.\n\n**Statistical Analysis for Table 1**\n\nWe conducted 5 independent trials, consistent with comparison methods, and report results as mean ± standard error. This will be included in the caption of Table 1 in revised version.\n\nA Wilcoxon rank-sum test was performed based on 5 trials. The symbols “+,” “–,” and “≈” indicate where the baseline method’s HPWL is significantly better, worse, or similar to EGPlace at a 0.05 significance level. The analysis is based on results from the released code. Due to time constraints, we ran WireMask-EA and EfficientPlace with 5 seeds on bigblue2 and bigblue4, so only partial results are reported. Additional results with 5 seeds will be included in revised version.\n\nThe results show that EGPlace outperforms MaskPlace and Chipformer on all 8 benchmarks (confidence probability 0.0061). It also outperforms EfficientPlace on \"bigblue2\" and \"bigblue4,\" and WireMask-EA on \"bigblue4\" (confidence probability 0.0061). EGPlace is statistically similar to WireMask-EA on \"bigblue2\" (confidence probability 0.2654).\n\n**Code is Not Included**\n\nWe have uploaded our code into https://anonymous.4open.science/r/EAPlace-31A4.\n\n**The Article does not Engage as Fully with the Evolutionary Literature**\nWe primarily focus on improving macro placement quality and efficiency, using an evolutionary framework for efficient iterations and broader search space exploration. However, we do not delve into the specifics of evolutionary algorithms.\n\nThe key differences between WireMask-EA and EGPlace are: 1. WireMask-EA uses random mutation, while EGPlace employs guided reconstruction-based mutation for better sample efficiency; 2. EGPlace improves efficiency by selectively repositioning modules, avoiding the overhead of full layout reconstruction.\n\nWe appreciate the recommended paper and believe the tool could help visualize the search trajectories of EGPlace and WireMask-EA, aiding comparison. We plan to conduct such visualizations and analyze their differences in future work.\n\n**Discussion of Related Paper**\n\nWe appreciate the recommended paper and plan to include LaMPlace in related work section of our revised version. We also analyze the relationship between LaMPlace and EGPlace in our response to Reviewer pQfq. The trajectory visualization tool in the second paper is useful, and we plan to incorporate visualizations in future work.\n\n**Response Regarding the Evolutionary Framework**\n\nOur key ideas are as follows: 1.Mainstream RL methods suffer from high training costs and limited global context in decision-making. 2. Greedy adjustments to the entire layout can efficiently improve results. 3.An evolutionary search framework enables efficient iterations and broader exploration of the search space. Based on this, we adopt an evolutionary framework, focusing on improving layout quality and efficiency, rather than the specifics of evolutionary algorithms. We will remove the term Novel in revised version to avoid confusion.\n\nWe have considered various strategies regarding selection and recombination in genetic algorithms. We think recombination is challenging, as merging different layouts often causes significant overlap. Post-processing methods like legalization and greedy reconstruction can reduce overlap but may compromise our efficiency advantage. For selection, we observe that high-quality layouts require sufficient refinement. Both EGPlace and WireMask-EA use small populations—WireMask-EA with 1, EGPlace with 5—for broader exploration. Given this setup, we did not implement a complex selection process. We use fitness-proportionate selection to determine which layout undergoes mutations, ensuring better layouts are adjusted with greater possibility while maintaining exploration. Our focus is on a simple yet effective approach that balances efficiency and layout quality.\n\nIn future work, we plan to explore whether recombination can be efficiently implemented without excessive overlap while improving layout quality. If recombination is used, a larger population may be needed for sufficient exploration, requiring more effective selection strategies.", "claims_and_evidence": "The main claim is that the introduced mutation operator improves search for chip configurations. This is demonstrated clearly by the comparison between the proposed method EGPlace and a similar evolutionary method WireMask-EA, as well as other baseline methods.", "methods_and_evaluation_criteria": "The proposed method is a mutation operation for the problem of macro placement. In that context, it is appropriately evaluated, however in the \"Experimental Designs Or Analyses\" section, I provide some improvements to the experimental analysis which would strengthen the claims.", "theoretical_claims": "There are no theoretical claims.", "experimental_designs_or_analyses": "The experiments appear well designed, using the ISPD2005 dataset and the Ariane RISC-V CPU benchmark. The method is compared against 4 baseline methods; the EGPlace method consistently improves over other methods. There are a few points of improvement:\n+ ICCAD2015 is a more recent benchmark than ISPD2005 - what is the motivation for ISPD2005?\n+ The number of baseline methods included is limited. Wiremask-EA compares with SP-SA, NTUPlace3, RePlace, DREAM-\nPlace, and Graph placement, DeepPR, MaskPlace. It would be especially helpful to include baselines from the RL literature, as this represents a significant part of the literature.\n+ The results presented in Table 1 could be improved through statistical analysis; best results are marked in bold, but it is not indicated if they are significant, nor for how many independent trials the comparison is performed.\n+ Code is not included.", "relation_to_broader_scientific_literature": "The article places itself well in the literature on the macro placement problem. It does not engage as fully with the evolutionary literature. For example, visualizing the different search trajectories taken by EGPlace compared to WireMask-EA would be a useful demonstration of the benefits of this new mutation operator.", "essential_references_not_discussed": "Geng, Zijie, et al. \"LaMPlace: Learning to Optimize Cross-Stage Metrics in Macro Placement.\" The Thirteenth International Conference on Learning Representations.\n\nOchoa, Gabriela, Katherine M. Malan, and Christian Blum. \"Search trajectory networks: A tool for analysing and visualising the behaviour of metaheuristics.\" Applied Soft Computing 109 (2021): 107492.", "other_strengths_and_weaknesses": "The article positions the contribution as a \"novel evolutionary framework,\" however the main contribution is the mutation operator, as confirmed by the ablation study. At what point could other parts of the evolutionary algorithm be specified for this problem? It is surprising that a fitness-proportionate selection is used, for example; in genetic algorithms, tournament selection is now standard. Was elitism or truncation selection explored? Is recombination possible? A greater study of the evolutionary algorithm's details that engages with recent evolutionary literature would improve the article, especially if the contribution is intended to be the evolutionary framework in full and not only the mutation operator.", "other_comments_or_suggestions": "None.", "questions_for_authors": "None.", "summary_of_paper": "", "summary_of_recommendation": "", "technical_quality": "", "clarity_of_presentation": "", "potential_impact": "", "robotics_focus": "", "quality_of_limitations": "", "questions_for_rebuttal": "", "reasons_to_accept": "", "reasons_to_reject": "", "questions_to_authors": "", "extra_scores": {}}, {"review_id": "vPmr3YCOZR", "reviewer": "Reviewer_nQ5x", "summary": "The manuscript proposes EGPlace, an innovative evolutionary optimization framework for macro placement in IC design, introducing a greedy repositioning-guided mutation operator and efficient mask computation algorithm. Experimental results show that EGPlace achieves significant improvements in wirelength reduction and computational speed compared to existing methods.", "questions": "", "limitations": "", "rating": 3, "confidence": null, "soundness": null, "presentation": null, "contribution": null, "strengths": "", "weaknesses": "", "quality": null, "clarity": null, "significance": null, "originality": null, "strengths_and_weaknesses": "", "was_revised": false, "final_justification": "", "rebuttal": "Thank you for your constructive review and valuable suggestions! \n\n**Regarding Mixed-size Placement**\n\nWe conduct mixed-size placement following the same approach in Chipformer and EfficientPlace. We first fix all macros placed by EGPlace and apply the global placement step of DreamPlace to position the standard cells. We then set all modules as movable and perform a complete mixed-size placement process using DreamPlace, which includes global placement, legalization, and detailed placement. \n\nNote that in this paper, our primary focus is on macro placement, and the mixed-size placement process is not fully optimized, which may be further improved by incorporating standard cell clustering and considering additional surrogate metrics, as suggested in MacroRegulate and LaMPlace.\n\n**Regarding PPA Metrics**\n\nWe fully agree that optimizing the final PPA metrics is the ultimate goal. However, we must note that incorporating final PPA metrics into online optimization is challenging, as obtaining them is time-consuming.\n\nEGPlace focuses on guided layout generation, including selecting layout candidates from the pool and choosing poorly-placed modules for reconstruction. Currently, the guidance comes from HPWL and other easily-computed metrics. It is not difficult for EGPlace to incorporate final metrics, such as those learned from the mask in LaMPlace (ICLR 2025).\n\nWe perform placement using the current EGPlace method on the \"ariane133\" dataset and evaluate the PPA metrics through OpenRoad. As the process is slow, we will report the results when they become available.\n\n**Our Relationship with ML**\n\nModule placement is a well-known machine learning problem, and we have included ML baselines for comparison, showing that EGPlace achieves better performance with less running time. We believe that the audience at ICML would have sufficient interest in our work (if accepted).\n \nThe current version of EGPlace serves as a strong starting point that can be further enhanced by machine learning algorithms. For instance, EGPlace can potentially be combined with the learned masks for PPA metrics improvement from LaMPlace. \n\n**Lack of Comparison with Analytic Methods**\n\nThe results of analytical methods, including NTUPlace3, RePlace, and DREAMPlace, have already been compared with our primary competitors, MaskPlace and EfficientPlace, in their respective papers. Notably, MaskPlace and EfficientPlace have shown superior performance over these baselines. However, we plan to include results from additional competitors in the revised version to make our paper more comprehensive.\n\n**Only Applicable to Macro Placement**\n\nSimilar to some baseline methods, including MaskPlace, EfficientPlace, and WireMask-EA, our work primarily focuses on macro placement, based on the observation that macro placement has a significant impact on layout metrics. \n\nNote that EGPlace supports mixed-size module placement. We have conducted mixed-size placement using DreamPlace and reported the results in Table 6 of our manuscript. \n\n**Performance of Dreamplace**\n\nWe conduct mixed-size placement following the same approach in Chipformer and EfficientPlace. We first fix all macros placed by EGPlace and apply the global placement step of Dreamplace to position the standard cells. We then set all modules as movable and perform a complete mixed-size placement process using Dreamplace, which includes global placement, legalization, and detailed placement. \n\nFor the results obtained by Dreamplace, we report the outcomes in Table 5 of the baseline method EfficientPlace for a fair comparison, where the results are close to those of Dreamplace 4.0.0. However, we observe that Dreamplace 4.1.0 on the mixed-size placement dataset are improved significantly, outperforming EGPlace. \n\nAs our work primarily focuses on macro placement, we further evaluate the macro placement performance of EGPlace and Dreamplace 4.1.0 on the ISPD2005 dataset. The results in table below indicate that EGPlace outperforms Dreamplace 4.1.0 on 7 out of 8 benchmarks, achieving an average HPWL improvement of 25.1%.\n\n## Table: Comparison to Dreamplace 4.1.0 on Macro Place over ISPD2005.\n| Method        | Adaptec1 | Adaptec2 | Adaptec3 | Adaptec4 | Bigblue1 | Bigblue2 | Bigblue3 | Bigblue4 |\n|---------------|----------|----------|----------|----------|----------|----------|----------|----------|\n| EGPlace | 5.75| 37.99 | 60.01 | 54.45| 2.23 | 10.55 | 49.98 |59.73 |\n| DreamPlace|10.24| 31.14 | 62.63 | 63.78| 6.07| 14.20 | 77.81 |92.51 |\n\n**Typo on MaskPlace**\n\nWe apologize for the typo in Table 5. The HPWL achieved by MaskPlace is 96.91 × 10⁵ rather than 9.69 × 10⁵. We will correct this error in the revised version.", "claims_and_evidence": "Yes.", "methods_and_evaluation_criteria": "- The main concern is that the method optimizes the macro's wire length. However, the results show that the mixed-size place method can also achieve the best HPWL results. However, the reason is not clearly explained in the paper.\n\n- Also, there are works [1, 2] claim that optimizing wirelength does not directly optimize PPA. Therefore, whether it can ultimately improve chip performance remains open to discussion.\n\n- The main contributions of this paper lie in the proposal of a novel mask computation method and improvements to the evolutionary algorithm. Its contributions to the ML community are relatively limited.\n\n[1] Benchmarking End-To-End Performance of AI-Based Chip Placement Algorithms.\n\n[2] Reinforcement Learning Policy as Macro Regulator Rather than Macro Placer.", "theoretical_claims": "There are no theoretical claims.", "experimental_designs_or_analyses": "The experiments cover most placement benchmarks and baselines. However, the experiment lacks a comparison with other analytic methods.", "relation_to_broader_scientific_literature": "The contributions of this paper seem only applicable to macro placement tasks.", "essential_references_not_discussed": "NA", "other_strengths_and_weaknesses": "While ICML is a prestigious conference in machine learning, its primary focus is on advancing the theoretical and practical aspects of machine learning algorithms and their applications. Evolutionary algorithms, unless tightly integrated with machine learning tasks (e.g., neural architecture search, hyperparameter optimization, or reinforcement learning), might not align well with the core interests of the ICML community. The paper may be more suitable for a domain conference.", "other_comments_or_suggestions": "NA", "questions_for_authors": "- How to get the results of Table 6 (mixed-size placement)? According to the Dreamplace repo (https://github.com/limbo018/DREAMPlace), the bigblue1 can get 8.62e7. However, all baselines are worse than Dreamplace.\n\n- Table 5, MaskPlace get the 9.69 in HPWL for bigblue3. Is there a typo.", "summary_of_paper": "", "summary_of_recommendation": "", "technical_quality": "", "clarity_of_presentation": "", "potential_impact": "", "robotics_focus": "", "quality_of_limitations": "", "questions_for_rebuttal": "", "reasons_to_accept": "", "reasons_to_reject": "", "questions_to_authors": "", "extra_scores": {}}, {"review_id": "i0lgcjbW8q", "reviewer": "Reviewer_iifF", "summary": "This paper proposes EGPlace, an evolutionary search-based approach for macro placement. It incorporates the wirelength, congestion, and overlap into its score computation. It achieves better HPWL and faster speed than previous RL-based approaches.\n\n## update after rebuttal\nAfter carefully reviewing the rebuttals and comments, I would like to maintain my current score.", "questions": "", "limitations": "", "rating": 2, "confidence": null, "soundness": null, "presentation": null, "contribution": null, "strengths": "", "weaknesses": "", "quality": null, "clarity": null, "significance": null, "originality": null, "strengths_and_weaknesses": "", "was_revised": false, "final_justification": "", "rebuttal": "Thank you for your constructive review and valuable suggestions! Below, we provide a detailed response to your questions and comments. If any of our responses fail to sufficiently address your concerns, please inform us, and we will promptly follow up.\n\n**The Results of MaskPlace on Circuit Ariane**\n\nThanks for your feedback. We notice that the results in Table 4 of MaskPlace are normalized, so our results for MaskPlace and Chipformer are taken from Table 7 in the Chipformer paper. For further verification, we have run the released code of MaskPlace on the ariane benchmark for 1K iterations with grid size set to 224, and observed an overlap ratio of 3.33%. This suggests that on datasets with large module coverage areas, completely eliminating overlap can be challenging.\n\n**Difference Between EGPlace and WireMask-BBO**\n\nAlthough both WireMask-BBO and EGPlace employ a greedy strategy, there are several key differences between the two methods. 1) The evolutionary search variant in WireMask-BBO relies solely on random mutations to explore the search space, whereas EGPlace performs guided mutations to enhance layout quality and improve sampling efficiency. 2), EGPlace is significantly more efficient than WireMask-BBO. WireMask-BBO first applies layout mutation, followed by a greedy genotype-to-phenotype transformation that requires removing and repositioning all macros in the circuit. In contrast, EGPlace introduces a mutation operator that integrates layout adjustment and reconstruction phases, eliminating the computational overhead caused by full layout reconstruction after local modifications.\n\nFrom the perspective of experimental results, EGPlace achieves an average 10.79% improvement in HPWL and a 7.8× speedup in runtime (Table 1), which also verifies the new technical contribution of EGPlace.\n\n**Typo Correction**\n\nWe sincerely apologize for the typographical errors. The macro placement results are listed in Table 1, where EGPlace is 2.8× more efficient than EfficientPlace. We will correct these errors in the revised version.\n\n**How to Address the Case where a Pin is Shared by Multiple Pins**\n\nA pin serves as an input/output interface of a module, and we do not think that pins contain each other. We assume that your question pertains to how the scores of modules are computed when a pin is associated with multiple nets. Based on this understanding, we provide our response bellow accordingly. \n\nIn most cases, a pin belongs to only one net, as noted in Appendix A.1 of MaskPlace. In our implementation, we follow the same approach in competitors like MaskPlace, EfficientPlace, and WireMask-EA, by treating each input and output interface of a net in the .nets file as a separate pin. Consequently, if there exist a pin that appears in multiple nets, each occurrence is treated as an independent pin.\n\nWe sincerely apologize if we have misunderstood your question. Please let us know if further clarification is needed.\n\n**How to Determine Module Placement Order**\n\nWe determine the module placement order in the same manner as MaskPlace. We will include an algorithm for determining the module order into the appendix in the revised version. Specifically, the placement order of a module m is computed considering the size of the module (Size[m]), the number of nets (NodeNetNum[m]), and the number of direct neighbors placed previously (NeiScore[m]). Each time, we select one module and add it into the order list, and then update NeiScore[n] for each neighbor n of m. \n\n**Input**: A set of all modules M, a hash table Size storing the area of each module, a hash table NodeNetNum storing the number of nets each module belongs to, an adjacency matrix Adj where modules within the same net are considered as neighbors. α and β are hyperparameters set according to MaskPlace.\n\n**Output**: A sequence I that stores M in order.\n\n```text\n1. I ← ∅\n2. NeiScore[m] ← 0 for all m ∈ M\n3. While I ≠ M DO\n4.   m ← Argmax(Size[m]*α + NodeNetNum[m]*β + NeiScore[m]) for m ∉ I\n5.   I ← I ∪ {m}\n6.   For Each n ∈ Adj[m] DO\n7.     NeiScore[n] ← NeiScore[n] + 1\n8. Return I\n```\n\n**Performance of DreamPlace**\n\nPlease refer to our feedback for Reviewer Nq5X.\n\n**Consideration of other PPA Objectives**\n\nEGPlace focuses on guided layout generation, including selecting layout candidates from the pool and choosing poorly-placed modules for reconstruction. Currently, the guidance comes from HPWL and other easily-computed metrics. It is not difficult for EGPlace to incorporate final metrics, such as those learned from the mask in LaMPlace (ICLR 2025).\n\nWe have run OpenRoad to collect PPA metrics on layouts produced by EGPlace using the ariane133 dataset, without considering PPA metrics during the layout generation. As the process is slow, we will report the results when they become available.", "claims_and_evidence": "Yes.", "methods_and_evaluation_criteria": "Yes.", "theoretical_claims": "Yes. There are no issues about the correctness of any proofs for theoretical claims.", "experimental_designs_or_analyses": "The validity of mixed-size placement is questionable. For the comparison between the proposed method EGPlace and analytical DREAMPlace, please see the \"Reference Results for Macro Placement\" part in https://github.com/limbo018/DREAMPlace. The results by DREAMPlace 4.1.0 are better than the EGPlace. Please discuss these results properly.", "relation_to_broader_scientific_literature": "The proposed method contributes to the application of ES algorithms into real and complex scene.", "essential_references_not_discussed": "No.", "other_strengths_and_weaknesses": "**Strengths**\n1. An efficient approach to fast construct the overlap mask between current block and placed blocks. And it is capable to reflect the exact overlap value.\n\n**Weaknesses**\n1. The overlap rate of circuit ariane with approach MaskPlace, which is shown in Table 4 in the appendix, is 3.27%. However, in the paper of MaskPlace [1], the overlap of \"ariane\" shown in Table 3 with method \"MaskPlace (hard constraint)\", is 0.00. Please discuss the inconsistency between the overlap.\n2. For the comparison between the proposed method EGPlace and analytical DREAMPlace, please see the \"Reference Results for Macro Placement\" [2] part in https://github.com/limbo018/DREAMPlace. The results by DREAMPlace 4.1.0 are better than the EGPlace. Please discuss these results properly. In the authors' submission, the results of DREAMPlace is much worse than other baselines, but according to the reference results shown in the github pages of DREAMPlace, EGPlace is worse than DREAMPlace. I think it is very significant to figure out this inconsistency since the gap between DREAMPlace in submission and github is very huge.\n3. The overall technical contribution is limited, and the full pipeline is similar to the WireMask-BBO.\n4. Other critical objectives are not taken into consideration, such as the post-routing wire length, timing metrics including WNS and TNS.\n\n\n[1] Lai, Yao, Yao Mu, and Ping Luo. \"Maskplace: Fast chip placement via reinforced visual representation learning.\" Advances in Neural Information Processing Systems 35 (2022): 24019-24030.\n\n[2] https://github.com/limbo018/DREAMPlace", "other_comments_or_suggestions": "1. Macro Placement Results seem to be listed in Table 1 in the main paper, instead of Table 6 in the Appendix.\n2. Typo: \"araine\" -> \"ariane\" in caption of Table 4.\n3. In line 966, maybe it should be \"it is 2.8x more efficient than EfficientPlace\" instead of \"EGPlace\"?", "questions_for_authors": "1. In the calculation of $wirelen_m$ in Eq. 4, the authors claim that $e_p$ is the bounding box center of a net which contains pin $p$. If there are multiple pins containing pin $p$ simultaneously, how to address this case?\n2. The same question for the $cong_m$ in Eq. 5, where $E_p$ is the RUDY value of the net containing pin $p$. If there are multiple pins containing pin $p$ simultaneously, how to address this case?\n3. How to determine the sequence of module placement? It is better to directly show the sequence, instead of justing writing \"larger and highly connected modules first\".", "summary_of_paper": "", "summary_of_recommendation": "", "technical_quality": "", "clarity_of_presentation": "", "potential_impact": "", "robotics_focus": "", "quality_of_limitations": "", "questions_for_rebuttal": "", "reasons_to_accept": "", "reasons_to_reject": "", "questions_to_authors": "", "extra_scores": {}}]

Author rebuttal:

Meta-review: The paper addresses a known bottleneck in EDA with a demonstrably effective yet conceptually simple idea that is easy for practitioners to adopt. While the study seems to provide limited improvement and not as comprehensive on PPA as desired, its quality/efficiency trade‑off and open implementation make it a worthwhile contribution to the audience interested in optimization methods for real‑world design problems. We highly encourage the authors to incorporate reviewers' feedback. I will recommend a weak acceptance.
Decision: Accept (poster)