Chip Placement with Diffusion Models
Authors: Vint Lee
Minh Nguyen
Leena Elzeiny
Chun Deng
Pieter Abbeel
John Wawrzynek
Venue: ICML 2025 poster (2025)
Keywords: macro placement
diffusion
machine learning
chip design
synthetic data
Primary area: applications->everything_else
TL;DR: We train diffusion models using synthetic data to perform macro placement, a key step in chip design.

Abstract: Macro placement is a vital step in digital circuit design that defines the physical location of large collections of components, known as macros, on a 2D chip. Because key performance metrics of the chip are determined by the placement, optimizing it is crucial. Existing learning-based methods typically fall short because of their reliance on reinforcement learning (RL), which is slow and struggles to generalize, requiring online training on each new circuit. Instead, we train a diffusion model capable of placing new circuits zero-shot, using guided sampling in lieu of RL to optimize placement quality. To enable such models to train at scale, we designed a capable yet efficient architecture for the denoising model, and propose a novel algorithm to generate large synthetic datasets for pre-training. To allow zero-shot transfer to real circuits, we empirically study the design decisions of our dataset generation algorithm, and identify several key factors enabling generalization. When trained on our synthetic data, our models generate high-quality placements on unseen, realistic circuits, achieving competitive performance on placement benchmarks compared to state-of-the-art methods.

Chip Placement with Diffusion Models
Vint Lee ! Minh Nguyen'
Leena Elzeiny? 2
Chun Deng"
Pieter Abbeel John Wawrzynek
Abstract
performance, and area of the produced chip. In particular, the placement of macros. which is the focus of our work, is especially important because of their large size and high connectivity relative to standard cells.
Macro placement is vital step in digital circuit design that defines the physical location of large collections of components, known macros, on 2D chip. Because key performance metrics of the chip are determined by the placement, op- timizing it is crucial. Existing learning-base bbsed methods typically fall short because of their re- liance on reinforcement learning (RI.), which slow and struggles generalize, requiring on- line training on each new circuit. Instead, we train a diffusion model capable of placing new circuits zero-shot, using guided sampling in lieu of RL to optimize placement quality. To enable such models to train at scale, we designed ca- pable yet efficient architecture for the denoising model, and propose a novel algorithm gener- ate large synthetic datasets for pre-training. To allow zero-shot transfer real circuits, we em- pirically study the design decisions of our dataset generation algorithm, and identify several key fac- tors enabling generalization. When trained on our synthetic data, our models generate high-quality placements on unseen, realistic circuits, achiev- ing competitive performance placement bench- marks compared to state-of-the-art methods.
Traditionally, macro placement is done with commercial tools such as Innovus from Cadence, which requires input from human experts. The process is also tomecconuming and expensive. On the other hand, the use of MI techniques shows promise in automating this process, well cre- ating better-optimized placements than commercial tools, which rely heavily on heuristics.
Even so, existing works mostly rely on reinforcement learn- ing (RL) (Mirhoseini et al., 2020; Cheng Yan, 2021; Lai et al., 2022; 2023; Gu et al., 2024), an approach with sev- eral key limitations. First, RL is challenging to scale it is sample-inefficient, and has difficulty generalizing to new problems. Many of these methods, for instance, treat each new circuit as a separate task, training a new agent from scratch for every new netlist (Cheng & Yan, 2021; Lai et al., 2022; Gu et al., 2024). Despite efforts to miti- gate this by incorporating offline pre-training, the scarcity of publicly-available data means that such methods strug- gle to generalize, and still require significant amount of additional training for each new netlist (Mirhoseini et al., 2020; Lai et al., 2023). Second, by casting placement as a Markov Decision Process (MDP), these works require agents to learn a sequential placement of objects (standard cells or macros), which creates challenges when suboptimal choices near the start of the trajectory cannot be reversed.
1. Introduction
Placement is an important step of digital hardware design where collections of small components, such as logic gates (standard cells), and large design blocks, such as memories, (macros) are arranged on 2-dimensional physical chip based connectivity graph (netlist) of the components. Because the physical layout of objects determines the length of wires (and where they can be routed), this step has sig- nificant impact on key metrics, such as power consumption,
To circumvent these issues, we instead adopt different ap- proach: leveraging powerful generative models, in particular diffusion models, to produce near-optimal chip placements for a given netlist. Diffusion models address the weaknesses of RL approaches because they can be trained offline at scale, then used zero-shot on new netlists, simultaneously placing all objects as shown in Figure 1. Moreover, our approach takes advantage of the great strides made in tech- niques for training and sampling diffusion models, such as guided sampling (Dhariwal & Nichol, 2021; Bansal et al., 2023), to achieve better results.
'Department of EECS, UC Berkeley. CA, USA 'SambaNova Systems Inc., Palo Alto, CA, USA 'Computer Science Depart- ment, Stanford University, CA, USA. Correspondence to: Vint Lee <vint@ berkeley.edu>..
Training a large and generalizable diffusion model, how- ever. comes with its own challenges. First, the vast majority of circuit designs and netlists of interest are proprietary,
Proceedings of the 42nd International Conference Machine Learning. Vancouver, Canada. PMLR 267, 2025. Copyright 2025 by the author(s).

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Chip Placement with Diffusion Models
severely limiting the quality and quantity of available train- ing data. Second, many of these circuits are large, con- taining hundreds of thousands of macros and cells. The denoising model used must therefore be computationally efficient and scalable, in addition to working well within the poise-prediction framework.
data available, requiring hours of online training on each new netlist for good results, even in-distribution circuits. EfficientPlace (Geng et al., 2024) reduces the exploration needed by combining global tree search with a local policy, A Although this improved efficiency, their method still relies on online training for the local policy, leading to runtimes of several hours per placement.
Our work addresses these challenges, and we summarize our main contributions as follows:
In contrast, Flora (Liu et al., 2022a) and GraphPlanner (Liu al., 2022b) deviate from sequential placement for- mulations by leveraging variational autoencoder (VAE) (Kingma & Welling, 2022) to generate placements. Flora further introduces a synthetic data generation scheme; how- ever, it lacks variation in object sizes and restricts con- nections to only the nearest neighbors, which, as our ex- periments indicate, limits generalization to realistic circuit layouts (see Section 5.1 and Table 4). Furthermore, their models struggle to learn the underlying distribution of legal placements, frequently producing overlapping results.
Synthetie Data Generation We present method for eas- ily generating large amounts of synthetic netlist and place- ment data. Our insight is that the inverse problem pro- ducing a plausible netlist such that a given placement is near-optimal - is much simpler to solve. This allows us to produce data without the need for commercial tools or higher-level design specifications.
Dataset Design We conduct extensive empirical study investigating the generalization properties of models trained on synthetic data, identifying several factors, such as the scale parameter, that cause models to generalize poorly. We use these insights to design synthetic datasets that allow for effective zero-shot transfer to real circuits.
Other approaches avoid the use of machine learning alto- gether. WireMask--BB3 (Shi et al., 2023) utilizes black-box optimization algorithms to find optimal macro placements over continuous coordinates, while legalizing and evaluat- ing the solution quality on a discrete grid. However, their usage of black-box optimization, such as evolutionary algo- rithms, leads to lengthy search times that must be started from scratch for each new circuit.
Model Architecture We propose novel neural network architecture with interleaved graph convolutions and atten- tion layers to obtain model that is both computationally efficient and expressive.
3. Background
By combining these ingredients, our method can gener- ate placements for unseen netlists in a zero-shot manner, achieving results competitive with state-of-the- oftt---rt- on the IC- CAD04 (or IBM) (Adya et al., 2004) and ISPD2005 (Nam et al., 2005b) benchmarks. Remarkably, our model accom- plishes this without ever having trained on real circuit data.
3.1. Problem Statement
Our goal is to train a diffusion model to sample from [(accc) where the placement is set of 2D coordinates for each object and the netlist e describes how the objects are con- nected in a graph, as well as the size of each object. We normalize the coordinates to the chip boundaries, so that they are within [-1,
2. Related Work
We represent the netlist as graph (V,E) with node and edge attributes {p: hev and (..)E)) We define p; be 2D vector describing the normalized height and width of the object, while dıj is a 4D vector containing the positions of the source and destination pins, relative to the center of their parent object. We convert the netlist hypergraph into this representation by connecting the driving pin of each netlist to the others with undirected edges. This compact representation contains all the geometric information needed for placement, and allows to leverage the rich body of existing GNN methods.
Google's RL-based approach, CireuitTraining (Mirhoseini al., 2021; Yue et al., 2022), employs graph neural net- work (GNN) generate netlist embeddings for multiple RL agents. While this method demonstrated state-of-the-arr re- sults, it requires computationally expensive online training on new circuits. Several RL. approaches follow to improve on runtime (Cheng & Yan, 2021; Lai et al., 2022; Gu et al., 2024), macro ordering (Chen et al., 2023a), and proxy cost predictions (Zheng et al., 2023a;b; Wang et al., 2022; Ghose et al., 2021).
Several recent works have focused on reducing the long runtimes of RL methods. ChiPFormer (Lai et al., 2023) uses offline RL to reduce the amount of online training required. Despite strong results on several benchmarks, their method is constrained by the diversity and quantity of
3.2. Evaluation Metrics
To evaluate generated placements, we use legality, which measures how easily the placement can be used for down-
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Chip placement with Diffusion Models
Figure 1. Denoising process for generating placements. In contrast to RL approaches, our method places all objects simultaneously. The middle 4 panels show the predicted output to at intervals of 200 steps, while the first and last panels are xvr (Gaussian noise) and zo (generated placement).
stream tasks (eg. routing); and half- half-perimeter wire length (HPWL), which serves as a proxy for chip performance.
training Eg to predict the noise added to samples from the dataset, DDPMs are able to model arbitrarily complex data distributions.
While legal placement has satisfy other criteria, in this work we focus (Mirhoseini et al., 2020; Lai et al., 2023): the objects cannot overlap one another, and must be within the bounds of the canvas. We can therefore define legality score as Au/A, where A, is the area, within the circuit boundary, of the union of all placed objects, and A, is the sum of areas of all individual objects. A legality of indicates that all constraints are satisfied.
simpler, commonly used constraint
4. Methods
4.1. Generating Synthetic Data
We obtain datasets (Table 1) consisting of tuples (z, c) using the method outlined below.
First, we randomly generate objects by sampling sizes uni- formly and placing them at random within the circuit bound- ary; ensuring legality by retrying if objects overlap. Follow- ing Rent's Rule (Lanzerotti et al., 2005), we then sample number of pins for each object using power law.
Routed wirelength influences critical metrics because long wires create delay between components, influencing timing and power consumption. HPWL is used as an approxima- tion to evaluate placements prior to routing (Chen et al., 2006; Kahng Reda, 2006). Because the scale of HPWL varies greatly between circuits, for our experiments on syn- thetic data we report the HPWL ratio, defined for given netlist as Wgan/Waata where W gen is the HPWL for the model- -eeneatted placement, while Wama is the HPWL of the placement in the dataset.
To generate edges, we start by computing the distance / for each pair of pins on different objects, then sample in- dependently from Bernoull((p()), where p(l) E [o, 1] is a distance-dependent probability which we refer to as the edge distribution To approximate the structure of real circuits and bias the model towards lower HPWL placements, choose p x exp(-1/s) so that the probability of generating edges decays exponentially with LI distance normalized by a scale parameter s.
Our objective is therefore to generate legal placements with minimal HPWL.
This simple algorithm, depicted in Figure 2, allows us to efficiently generate large numbers of training examples for our models without the using any commercial tools design specifications. Using 32 CPUs, we are able to produce 100k "circuits" " each containing approximately 200 objects in day.
3.3. Diffusion Models
Diffusion models (Song et al., 2021; Ho et al., 2020) are a class of generative models whose outputs are produced by iteratively denoising samples using process known Langevin Dynamics. In this work we the Denoising Diffusion Probabilistic Model (DDPM) formulation (Ho et al., 2020), where starting with Gaussian noise ær, we perform 7 denoising steps to obtain æT- PT-,,------. -.. 20. with the fully denoised output zo as our generated sample. In DDPMs, each denoising step is performed according to
Our algorithm also highly flexible, allowing many choices for the distributions of the number of objects, their sizes, the edges, scale parameters, and so on. To better understand the design space of synthetic datasets, empirical study in Section 5. identifying several factors that are vital for training models that transfer zero-shot to real circuits.
conduct extensive
Æt-1
It + B. éo ( ł, c) + o.
(1)
where 022, 3r, Jg are constants defined by the noise sched- ule, z ~ No, I) is injected noise, and ég is the learned denoising model taking Zt, & and context e as inputs. By
'p is not, however, probability distribution
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Chip Placement with Diffusion Models
of potentials for each of our optimization objectives.
3
2
The legality potential Plogality (2) for netlist with objects V is given by:
1. Place abjects 2. Generate pins 3. Compute pin 4. Sample edges
Plegality (x) =
Σ IJEV
min(0, dig(2))
(2)
distances
Figure Visualization the steps involved generating synthetic data.
where di is the signed distance between objects i and j. which we can compute easily for rectangular objects. Note that the summand is 0 for any pair of non-overlapping ob- jects, and increases as overlap increases.
Based on our results, we designed 2 synthetic datasets, v and v2, with parameters listed in Table 1.
We define (Pppel (2) simply as the HPWI. of the placement 2. We compute this in a parallelized, differentiable manner by casting HPWL computation in terms of the message- passing framework used in GNNs (Gilmer et al., 2017) and implementing custom GNN layer with no learnable parameters in PyG (Fey & Lenssen, 2019).
4.2. Model Architecture
We developed a novel architecture for the denoising model, shown in Figure 3. We highlight below several key ele- ments of our design that we empirically determined (see Section 5.2) to be important for the placement task:
Instead of gradients from a classifier (Dhariwal & Nichol, 2021), we use the backwards universal guidance force g(x,) Agdn- Here, dn is the prediction of xo based the denoising model's output at time step t. and Ap is the ---optimal change in ito-space,, computed using gradient descent. The combined diffusion score is then given by sa(e)) + Wg g(xx). ). We refer the reader to Bansal et al. (2023) for more details.
Interleaved GNN and Attention Layers We use the peessng-passing GNN layers for their computational ef- ficiency in capturing node neighhorhood information, while the interlcaved attention (Vaswani et al., 2017) layers ad- dress the oversmoothing problem in GNNs by allowing information transfer between nodes that are distant in the netlist graph, but close the 2D canvas. We find that com- bining the two types of layers is critical, and significantly outperforms using either type alone.
In the simple implementation, Uflealitty and Wapwi are set as constant hyperparameters. However, the optimal weights can vary depending the circuit's connectivity properties. Instead, we take inspiration from constrained optimization to automatically tune the weights. To solve
MLP Blocks We found that inserting residual 2-layer MLP blocks between each GNN and Attention block im- proved performance significantly for a negligible increase computation time.
min (2))
s.t.
Plegality (2)) = 0,
(3)
Sinusoidal 2D Encodings The model receives 2D sinu- soidal position encodings, in addition to the original (Ir, v) coordinates, input. This method improves the precision with which the model places small objects, leading to place- ments with better legality.
we optimize the Lagrangian C(),z) (hpwi((r) + Plegality (z) simultaneously with respect x and the La- grange multiplier X. We instantiate this idea during guid- ance by performing interlcaved gradient descent steps of Phpell (x) + Weeaality Plegality (z) with respect to I, and Wiegality (Piegaliity (z) - E) with respect to Wlegality-
In this work, we use sizes of models: Small, Medium, and Large, with 233k, 1.23M, and 6.29M parameters respec- tively. A full list of model hyperparameters can be found in Appendix A.
4.4. Training and Evaluation
Due to the lack real placement data, we train our models entirely on synthetic data (see Section 4.1). For placing real circuit netlists, we train our models in two stages: we first train on our v/ dataset smaller circuits, then fine-tune on v2 which contains larger circuits. Details on dataset design are provided in Section 5.1.
4.3. Guided Sampling
One key advantage of using diffusion models the ease of optimizing for downstream objectives through guided sam- pling. We use backwards universal guidance (Bansal et al., 2023) with easily computed potential functions to optimize the generated HPWL and legality without training additional reward models or classifiers. The guidance potential (zx) is defined as the weighted sum Wlgality Pleeality + Whpel (Phpwl
We evaluate the performance of our model on circuits in the publicly available ICCAD04 (Adya et al., 2004) (also known as IBM) and ISPD2005 (Nam et al., 2005a) benchmarks. Because these circuits contain hundreds of thousands of

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Chip Placement with Diffusion Models
Block (xN)
Encoder
ResGNN block
AttGNN block
Sinusoidal Encodings
Atte ntion
Attention
SWS
NN
MLP layers
GNN
GNN
MLP 2 layers
Linear
Figure 3.
Diagram our denoising model. Residual connections, edge feature inputs, nonlincarities, and normalization layers have been
ommitted for clarity.
small standard cells, we follow prior work (Mirhoseini et al., 2020) and cluster the standard cells into 512 partitions using hMetis (Karypis et al., 1997). Each cluster is assigned to the nets of its constituent standard cells (nets within a single cluster are removed) with pins located at the cluster center, while the size of each cluster is the total area of its standard cells.
1.00
1.00
Legality
Legality
0.98
0.98
Irann Set
0.96
0.96 100
0.94
1000
10000
100
500
1000
Edges
Vertices
4.5. Implementation
Figure 4. Legality decreases on circuits with fewer edges, while adding edges does not degrade performance. The training data has 1740 edges on average.
Figure 5. Legality decreases on circuits with more vertices, indi- cating poor generalization. The training data has 230 edges on average.
Our models are implemented using Pytorch (Paszke et al., 2019) and trained on machines with Intel Xeon Gold 6326 CPUs, using a single Nvidia A5000 GPU. We train our models using the Adam optimizer (Kingma & Ba, 2014) for 3M steps, with 250k steps of fine-tuning where applicable.
(Fey & Lenssen, 2019), and
the GNN layers to propagate information more efficiently, improving or maintaining the model's performance.
5. Experiments
In contrast, Figure 5 shows that the model struggles to gen- eralize larger circuits than it was trained on, with legality decreasing as the number of vertices increases.
5.1. Designing Synthetic Data
To generate synthetic datasets that allow for zero-shot trans- fer, we first have to understand which parameters are impor- tant for generalization, and which ones are not. We there- fore investigate the generalization capabilities of our model along several axes by evaluating a single trained model datasets generated using various parameters. By identifying parameters that the model struggles to generalize across, we can design our synthetic dataset to facilitate zero-shot transfer by ensuring that for such parameters, the synthetic distribution covers that of real cireuits (see Section 5.1.4) 1.).
1.1.2. SCALE PARAMETER
In our data generation algorithm, the scale parameter 8 de- termines the expected length of generated edges. A larger s means that distant pins are more likely to be connected, while a small value of means that only nearby pins are connected. Thus, the scale parameter has significant im- pact on the properties of the graph generated, such as the number of neighbors per vertex, as well as the optimality of the corresponding placement. To understand how these effects influence the placements generated by the model, we evaluate our model, trained on data with a fixed value of s, on datasets with different scale parameters.
In this section, evaluate model trained dataset with narrow distribution, with key parameters listed in Table 1. The full set of parameters is listed in Appendix A.
1. NUMBER OF EDGES AND VERTICES
Figure 6 shows that the model performs well longer scale parameters up to 0.4, with legality dropping sharply past it. Meanwhile, lowering causes HPWI. to worsen significantly, with the model generating placements more than 1.5x worse than the dataset.
Figure 4 shows how legality changes with the number of edges in the test dataset. The model generalizes remarkably well datasets with more edges than it was trained on, while performance degrades quickly when fewer edges are present. We hypothesize that an increased number of edges allows
This could be because for small 8, the presence of edges
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Chip placement with Diffusion Models
Table Parameters of datasets used. For v/ and v2, we sample for cach eircuit from log-uniform distribution, then compute scale-dependent multiplier 7ss) to control the number of edges in each circuit.
Name
Circuits
Vertices
Edges
Scale Parameter (s)
p(l)
v
40000
230
1740
0.2
7. exp (-1/8)
vl
40000
230
1600
log (0.05, 1.6)
((s) exp (-1/s)
v2
5000
960
9510
log (0.025, 0.8)
7(s) exp
exp (-1/s)
1.0
1.75
Table 2. Test performance is near-identical to training performance on datasets using various p(I). a is the sigmoid function, and s is the scale parameter, which we choose such that the mean edge length matches that training data.
HPWL Ratio
Legality
0.9
1.25
0.8
Train
0.75
Exponential e(-t/s)
Sigmoid al s)
Linear max( --
0.0
1.2
p(l) x
Scale Parameter
Scale Parameter
Legality HPWI. Ratio
0.982
0.983
0.982
Figure 6. Legality drops sharply when increasing scale parameter past certain point, while scale parameters smaller than the train- ing data causes HPWL to worsen significantly. The training data is generated using scale 0.2.
1.003
1.012
1.003
In Table 2, we see that our model performs well, both in le- gality and HPWL, on circuits where edges are sampled from different distributions. This is a promising indication that our training data allow models to generalize zero-shot to unseen circuits that lie outside the training distribution.
between objects means that they are very likely near each other the dataset placement, providing the model with lot of information on where objects should be placed. If the model is then evaluated circuits with larger s, the increased number of neighbors causes the model to place too many objects in the same vicinity, leading to clumps forming (see Figure 7) and poor legality. Conversely, when evaluated on circuits with smaller s, the model's inductive biases are not strong enough to place connected objects as close together as possible, leading to longer, worse, HPWL.
5.1.4. ZERO-SHOT TRANSFER TO REAL CIRCUITS
These results allow us to design new datasets, which we refer to as v and v2, that better enable zero-shot transfer to real circuits. Because our models generalize poorly to larger circuits, they require training on circuits similar in size to real (clustered) circuits, which contain 1000 components. To satisfy this while maintaining computational efficiency, we pre-train on a large set of smaller circuits (v/) before fine-tuning on small set of larger circuits (v2), keeping the number of edges low in both datasets. To ensure model performance across different length scales, we also train on broad distribution of scale parameters. Finally, since an exponentially decaying p generalizes well to other distribu- tions without sacrificing HPWL, continue using in new datasets.
(a) 0.2
(b) s = 0.6
(c) 8 1.2
Figure 7. Increasing scale parameter causes the diffusion model, trained only on circuits with 0.2, to clump objects together.
The parameters for generating the vl and v2 datasets are summarized in Table 1, with a full list provided in Table 8.
We find in Table that training on these broad-distribution datasets allow for effective zero-shot transfer the real- world circuits in the IBM benchmark, with legality increas- ing significantly when training v/ and v2, compared to the narrower vO dataset.
5.1.3. DISTRIBUTION OF EDGES
To bias the model towards generating placements with low HPWL, we sample edges with probability p(!) that expo- nentially decays with edge length L. However, there is no guarantee that optimal placements for real circuits follow such a distribution. We therefore investigate how this choice of affects generalization other edge distributions p(l).
Moreover, models trained on our synthetic dataset far outper- form those trained on the existing data generation algorithm proposed by Flora (Liu et al., 2022a;b). We see in Table
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Chip placement with Diffusion Models
that v/ dataset achieves legality of 0.821, far higher than Flora's 0.264, demonstrating that dataset allows for much better zero-shot generalization.
Table 4. Average HPWI. and legality achieved by our models on the clustered IBM benchmark. DREAMPlace figures, and results model trained on Flora's dataset are included comparison.
Thus, although our simple data generation algorithm does not capture all the nuances of real circuits, such as the multimodal distributions of both edges and object sizes, it covers the important features well enough for our model learn to produce reasonable placements on IBM circuits, some of which are shown in Figure 8.
Model
Legality
HPWL (103)
DREAMPlace
3.724
Large+Flora
0.2640
3.740
Large+v0
0.7794
3.252
Largetvl
0.8213
3.281
Large+v2
0.8835
3.203
5.2. Model Architecture
La (Guided)
0.9970
2.976
We demonstrate the importance of several components of model architecture through ablations, shown in Table 3. When either the sinusoidal encodings MLP blocks are removed, the model performs substantially worse in both legality and HPWL. Replacing attention layers with graph convolutions also causes sample quality to plummet, as evidenced by poor legality scores.
(a) Large+v0
(b) Large+v2
(c) Large+v2 Guided
Table Legality and HPWL of various models on the v/ dataset after IM steps. Our models scale favorably, and our ablations validate the importance several components of our model.
Figure 8. While our Large model, when trained on v2 data, can produce reasonable placements, guided sampling improves quality significantly. ibm04 is shown here, with macros in yellow, while standard cell clusters colored blue.
Model
#Param.
Legality
HPWL Ratio
Small
0.233M
0.948
1.072
better than those produced by the sfate-of-the-arr DREAM- Place (Lin et al., 2019; Chen et al., 2023b), with 20% lower HPWL. on average. While we note that DREAMPlace, mixed-size placer, is not optimized for placing clustered circuits, this result is nevertheless a strong indication of our method's ability to generate high-quality placements for real circuits. This is especially remarkable, showing that models trained entirely on synthetic data can transfer effectively to real circuits in zero-shot manner.
Medium
1.23M
0.960
1.039
- -oo attention
1.42M
0.799
1.035
No MLP
0.698M
0.946
1.060
- No encodings
1.21M
0.949
1.061
Large
6.29M
0.976
1.032
Our model also exhibits favorable scaling properties, with Table 3 showing significant and monotonic improvements in model performance (both legality and HPWL) with in- creasing model size. This suggests scaling up models as attractive strategy for improving performance on more com- plex datasets, particularly since synthetic data is unlimited.
5.4. Macro-only Placement of Real Circuits
To compare our method to existing macro placement tech- niques, we also generated placements in the macro-only setting by removing all standard cells from the IBM and ISPD circuit netlists. For brevity, we present only aver- ages for each benchmark in this section, with results for individual circuits found in Appendix B.
5.3. Guided Sampling on Real Circuits
To determine the effectiveness of guidance in improving sample quality, we used our model to generate placements for the IBM benchmark with standard cells clustered.
We see from Table that our method outperforms existing macro placers by a large margin, reducing average HPWL by over 50% compared to prior works in both the IBM and ISPD benchmarks.
As shown in Table 4, guidance dramatically improves legal- ity and HPWL during zero-shot sampling, with legality in- creasing to nearly 1 while simultaneously shortening HPWL by 7.1%. This result shows that our guidance method is ef- fective in optimizing generated samples without requiring additional training. An example of the generated placements with and without guidance shown in Figure 8.
Moreover, Table 5 also shows that placements generated by our method have far lower congestion that those produced by existing methods. Here, we measure the RUDY conges- tion (Spindler & Johannes, 2007) using the method in Shi et al. (2023). The strong performance of our method on the
Moreover, we find that our placements are significantly
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Chip Placement with Diffusion Models
congestion metric, despite explicitly optimizing for it, is consistent with Shi al. (2023)'s observation that RUDY congestion and HPWL are positively correlated.
the macro positions fixed during standard cell placement. This is in line with earlier works (Lai et al., 2022; Shi et al., 2023; Mirhoseini et al., 2020; Cheng & Yan, 2021) but contrasts with Lai et al. (2023), where the contribution of the macro placement technique is not as clear because the macros move significantly during standard cell placement.
Table 5. Average HPWL and RUDY congestion of our model com- pared to various baselines on the IBM and ISPD benchmarks in the macro-only setting. Our model significantly outperforms existing methods, achieving much lower HPWL and congestion.
In Table 6, we compare results from our method other macro placement baselines, as well as DREAMPlace. The baselines include both the learning- leaseing-based ChiPFormer (Lai et al., 2023) and MaskPlace (Lai et al., 2022), as well as the learning-free WireMask-BBO's (Shi et al., 2023). All of these baselines use DREAMPlace for standard cell place- ment. We find that our method outperforms prior macro placement methods by a wide margin, while improving over DREAMPIace by 4% on average. This indicates that the strong performance of our model clustered macro place- ment transfers well to mixed-size placements. Moreover, our method, by design, can be easily applied zero-shot to new circuits and takes minutes to run (see Table 13), while other methods require RL fine-tuming or black box optimiza- tion, spending hours on each new circuit.
Method
HPWL (109) Congestion
IBM Average
MaskPlace
8.72
345
WireMask-BBO
7.43
324
ChiPFormer
7.33
336
EfficientPlace
8.32
367
Diffusion (Ours)
2.49
196
ISPD Average Timeout on 2/8 circuits.
MaskPlace
WireMask-BBO
154
1485
ChiPFormer
116
836
Diffusion (Ours)
45.9
546
6. Conclusion
5.5. Mixed-Size Placement of Real Circuits
In this work, we explored an approach that departs from many existing methods for tackling macro placement: using diffusion models to generate placements. To train and apply such models at scale, we developed a novel data generation algorithm, designed synthetic datasets that enable zero-shot transfer real circuits, and designed neural network archi- tecture that performs and scales well. We show that when trained on our synthetic data, our models generalize to new circuits, and when combined with guided sampling, can generate optimized placements even on large, real-world circuit benchmarks.
While our results (Table 4 and Table 5) have shown that our method can produce high-quality macro placements for clustered and macro-only circuits, we also wish to investi- gate if these macro placements are useful for downstream tasks, particularly for mixed-size placement.
Even so, our work not without limitations. RL methods, while slow, provide a means of trading test-time compute for better sample quality. We believe applying such meth- ods, through DDPO (Black et al., 2024) for instance, could combine the strengths of generative modeling and RL fine- tuning. We also note that our synthetic data does not capture all the nuances of real data, such as multimodal edge dis- tributions, and believe this is an interesting area for further study.
(a) Diffusion model (b) Initialize and fix (c) Place standard placement.
macros.
cells.
Figure 9. Our model can be used for mixed-size placement by first placing macros and clusters, then using our placements as inputs standard cell placer. ibm03 is shown here.
To perform mixed-size placement (which requires placing all standard cells and macros) using our method, we first use our diffusion models to place clusters and macros (Fig- ure 9a). We then initialize the position of each standard cell to the position of the corresponding cluster, and copy the positions of the macros (Figure 9b). Finally, we use DREAMPlace 4.1 (Chen et al., 2023b) to place the stan- dard cells, thus obtaining a full placement of standard cells and macros (Figure 9c). To elucidate the impact of our macro placements on the final placement quality, we keep
In conclusion, we find that training diffusion models on synthetic data is promising approach, with our models generating competitive placements despite never having trained on realistic circuit data. We hope that our results inspire further work in this area.
WireMask-BBBO fails to place ibm12 and ibm 15 so a lower- bound average computed by substituting the smallest HPWL in the corresponding rows
8

---

Chip Placement with Diffusion Models
Table 6. Comparison of HPWL (10") averaged over seeds, using various techniques for mixed-size placement, on the IBM benchmark.
Circuit
MaskPlace + DP
WireMask- + DP
ChiPFormer + DP
DREAMPlace
Diffusion (Ours)
ibm01
3.33
2.84
3.35
2.23
2.09
ibm02
7.30
6.87
6.24
5.79
4.43
ibm03
10.1
9.81
10.9
10.4
7.30
ibm04
10.4
9.65
10.1
9.13
8.00
ibm05
7.67
7.67
7.67
7.60
7.79
ibm06
7.62
8.41
7.76
6.15
8.31
ibm07
13.3
13.0
13.4
11.1
9.60
ibm08
15.5
15.9
15.7
12.3
13.3
ibm09
16.2
15.4
16.9
12.8
12.6
ibm10
46.8
45.2
45.4
44.8
30.2
ibm11
23.5
24.6
23.6
16.6
17.3
ibm12
46.1
Failed
48.8
31.0
34.0
ibml3
28.2
28.0
28.4
23.2
23.0
ibm14 14
45.4
48.2
46.5
31.3
34.5
ibm15 15
53.4
Failed
55.8
51.3
45.0
16
65.9
63.2
67.3
53.0
52.7
ibm17
72.9
69.7
71.4
57.9
60.4
ibm18
42.2
41.6
41.1
37.6
38.6
Average
28.7
27.0
28.9
23.6
22.7
Acknowledgements
Brody, S., Alon, U., and Yahav, E. How attentive graph attention networks?, 2022.
This work was supported in part by an ONR DURIP grant and the BAIR Industrial Consortium. Pieter Abbeel holds concurrent appointments as Professor at UC Berkeley and as an Amazon Scholar. This paper describes work per- formed at UC Berkeley and is not associated with Amazon.
Chen, T-c., Jiang, Z.-w., Hsu, T.-c,, Chen, H.-c,, and Chang, Y.-.. A high-quality mixed-size analytical placer considering preplaced blocks and density con- straints. 2006 IEEE/ACM International Conference on Computer Aided Design, pp. 187-192, 2006. doi: 10.1 N0.1109/CCCDD.2000..22000
Impact Statement
This paper presents work whose goal advance the field of Machine Learning. There are many potential societal consequences of our work, none which we feel must be specifically highlighted here.
Chen, Y., Mai, J., Gao, X., Zhang, M., and Lin, Y. Macrorank: Ranking macro placement solutions leveraging translation equivariancy. In Proceedings of the 28th Asia and South Pacific Design Automa- tion Conference, ASPDAC '23, pp. 258-263, New York, NY, USA, 2023a. Association for Computing Machinery. ISBN 9781450397834, 3566097.3567899. URL https://dol orr/0000.00...... 1 0t35/33660977.3566
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Chip placement with Diffusion Models
A. Implementation Details
Hyperparameters for our model are listed Table 7. used the DDPM formulation found in Ho et al. (2020) with a cosine noise schedule over 1000 steps. We also list parameters for generating our synthetic datasets in Table
Table Hyperparameters for models. We refer the reader to code for more details.
Small
Medium
Large
Model Dimensions
Model size
64
128
256
Blocks
2
Layers per block
2
AtGNN size
32
32
256
ResGNN size
64
256
256
MLP size factor
4
MLP layers per block
2
Input Encodings
Timestep encoding dimension Input encoding dimension
32
32
GNN Layers
Type
GATv2 (Brody et al., 2022)
Heads
4
Guidance Parameters
WHPWL
0.0001
áo optimizer
SGD
fo optimizer learning rate
0.008
Wlegality optimizer
Adam
Wlegality optimizer learning rate
0.0005
Wlegality initial value
0
Gradient descent steps
E
0.0001
12

---

Chip placement with Diffusion Models
Table Parameters for generating our synthetic data. Unless otherwise stated, v/ and v2 use the same parameters as v0, We refer the reader our code for more details. Sizes and distances are normalized that value of corresponds the width of the canvas.
v
v2
Stop Density Distribution Distribution type
Uniform
Low
0.75
High
0.9
Aspect Ratio Distribution
Distribution type
Uniform
Low
0.25
High
1.0
Object Size Distribution Distribution type
Clipped Exponential 0.08
Scale
0.04
Max
1.0
0.5
Min
0.02
0.01
Edge Distribution
Distribution p(l)
> - exp (-1/8)
Scale
0.2
log (0.05, 1.6)
log (0.025,, 0.8)
Max p
0.9
7
0.21
0.212 -1.42
0.00792. s 1.44
13

---

Chip Placement with Diffusion Models
B. Additional Results
We present results for macro placements for each circuit the IBM and ISPD benchmarks below. HPWL figures are shown in Table and Table 10, congestion in Table 11 and Table 12, and runtime in Table and Table 14.
In cases, our values differ from those in the original papers because some baselines select and place only subset of the macros, with differing selection criteria among baselines, while we place all macros for all baselines to ensure fair comparison.
Table Comparison of HPWL (10") for macro-only placements the IBM benchmark. ihm05 has heen omitted because it contains no macros.
Circuit
MaskPlace
WireMask-BBO
ChiPFormer
EfficientPlace
Diffusion (Ours)
ibm01
4.30
2.78
3.88
3.66
1.16
ibm02
5.54
4.19
5.05
4.42
2.68
ibm03
3.31
3.30
3.74
3.87
1.07
ibm04
6.91
5.43
5.96
6.10
2.40
ibm06
0.93
0.85
0.87
0.84
0.32
ibm07
2.67
2.66
2.36
3.42
0.78
ibm08
20.6
19.2
19.9
19.3
9.32
ibm09
2.45
1.76
1.77
2.57
0.44
ibm10
23.8
18.2
18.2
20.6
5.28
ibmll
4.15
3.75
3.25
4.70
0.78
ibm12
14.9
11.8
13.0
12.1
2.85
ibm13
4.58
4.41
4.02
5.37
1.05
ibm14
8.43
9.80
7.44
11.7
2.42
ibm15
4.68
7.77
2.67
5.98
1.06
ibm16
18.3
14.8
15.5
15.2
6.11
ibm17
16.8
12.2
13.7
17.9
3.20
ibm18
5.98
3.44
4.19
3.64
1.52
Average
8.72
7.43
7.33
8.32
2.49
Table 10. Comparison of HPWL (10") for macro-only placements on the ISPD benchmark.
Circuit
MaskPlace
WireMask-BBO
ChiPFormer
Diffusion (Ours)
adaptecl
8.57
5.81
6.75
9.19
adaptec2
77.7
54.5
63.8
31.0
adaptec3
108
59.2
73.2
54.4
adaptec4
91.9
62.7
85.8
54.5
bigbluel
3.11
2.12
3.05
2.64
bigblue2
Timeout
186
85.8
38.8
bigblue3
84.0
66.2
79.2
35.9
bigblue4
Timeout
798
548
141
Average
154
116
45.9
14

---

Chip Placement with Diffusion Models
Table Comparison of congestion (RUDY estimator) for macro-only placements on the IBM benchmark. ibm05 has been omitted
because it contains macros.
Circuit
MaskPlace
WireMask-BBO
ChiPFormer
EfficientPlace
Diffusion (Ours)
ibm01
289
253
266
316
160
ibm02
228
243
205
257
178
ibm03
176
173
173
214
117
ibm04
449
483
490
480
260
ibm06
79.2
77.1
76.9
76.7
42.8
ibm07
154
164
160
177
83.0
ibm08
1232
1198
1261
1288
776
ibm09
127
119
111
153
49.1
ibm10
480
463
466
538
362
ibml1
180
183
172
240
69.2
ibm12
392
212
357
360
190
ibm13
163
202
177
209
86.0
ibm14
378
375
378
418
232
ibm15
162
173
173
227
69.2
ibml6
574
497
528
534
334
ibm17
531
464
488
483
204
ibm18
271
221
229
266
111
Average
345
324
336
367
196
Table 12. Comparison of congestion (RUDY estimator) for macro-only placements the ISPD benchmark.
Circuit
MaskPlace
WireMask-BBi
ChiPFormer
Diffusion (Ours)
adaptecl
312
139
140
149
adaptec2
1068
1084
1180
668
adaptec3
990
672
677
579
adaptec4
945
793
779
584
bigbluel
98.5
25.1
19.0
23.4
bighlue2
Timeout
1924
500
523
bigblue3
970
955
956
391
bigblue4
Timeout
6290
2436
1451
Average
1485
836
546
15

---

Chip placement with Diffusion Models
Table 13. Comparison of runtime (minutes) the IBM benchmark. ibm05 has been omitted because it contains macros.
Circuit
MaskPlace
WireMask-BBO
ChiPFormer
EfficientPlace
DREAMPlace
Diffusion (Ours)
ibm01
154
209
98
54
0.308
1.85
ibm02
165
204
87
0.411
2.25
ibm03
123
217
75
0.393
2.17
ibm04
63
208
82
61
0.401
2.21
ibm06
34
224
80
29
0.229
2.38
ibm07
58
223
80
63
0.261
2.87
ibm08
75
207
105
79
0.260
3.38
ibm09
50
221
71
46
0.257
3.08
10
516
228
236
268
0.455
4.50
ibml1
79
224
106
80
0.303
3.40
ibm12
390
253
196
206
0.469
5.24
ibm13
93
225
127
95
0.613
4.19
ibm14
393
266
187
216
0.760
5.95
ibm15
83
254
113
86
0.923
6.81
ibm16
107
217
137
130
0.784
7.88
ibm17
489
266
250
358
0.839
10.33
ibm18
60
216
93
0.742
8.06
Average
172
227
124
114
0.475
4.39
Table 14. Comparison of runtime (minutes) on the ISPD benchmark.
Circuit
MaskPlace
WireMask-BBD.
ChiPFormer
DREAMPlace
Diffusion (Ours)
adaptecl
139
211
223
1.07
4.78
adaptec2
195
209
234
1.34
4.53
adaptec3
224
207
284
2.06
4.73
adaptec4
718
212
467
2.43
4.94
bigbluel
274
204
256
1.30
4.83
bigblue2
Timeout
1396
5220
3.80
122
bigblue3
648
233
494
3.14
5.13
bigblue4
Timeout
596
1210
8.86
18.9
Average
408.5
1049
3.00
21.2
16


Reviews:
[{"review_id": "cS0QuseRlh", "reviewer": "Reviewer_KAy5", "summary": "This paper applies diffusion models to macro placement. The motivation is that existing RL-based methods for macro placement are slow and lack flexibility. To provide more data for training, this paper generates synthetic data by randomly placing objects, sampling pins, and creating edges based on a distance-dependent probability. The model architecture combines GNN and attention layers, with MLP blocks and sinusoidal encodings. Guided sampling is used to optimize placement quality. Experiments on synthetic data and the ICCAD04 benchmark show that the model can achieve competitive results in terms of legality and HPWL, and it performs well in mixed-size placement.", "questions": "", "limitations": "", "rating": 3, "confidence": null, "soundness": null, "presentation": null, "contribution": null, "strengths": "", "weaknesses": "", "quality": null, "clarity": null, "significance": null, "originality": null, "strengths_and_weaknesses": "", "was_revised": false, "final_justification": "", "rebuttal": "Thank you for your insightful feedback and suggestions. We hope the following can address your concerns. \n\n**PPA evaluation:** We agree that PPA evaluation and optimization is important. As a step towards analyzing and optimizing downstream objectives, we also evaluated congestion of our macro placements, with the results in Table 1 below showing that our method significantly outperforms the baselines not just in HPWL, but in congestion.  \n\nHowever, optimizing for PPA is difficult, with many similar works focusing on simple proxy objectives like HPWL. Moreover, the commonly used benchmarks such as ISPD2005 and IBM do not support timing analysis. Because the goal of our work is to explore and develop a novel approach - training a diffusion model - to macro placement, we have therefore chosen to focus our contributions on developing the techniques necessary for such an approach, such as synthetic data generation, rather than simultaneously tackling PPA optimization. We believe that despite its shortcomings, HPWL is a reasonable optimization objective, particularly as a first step when exploring a new approach.\n\nTherefore, while PPA optimization is an important end-goal, we leave it as a direction for future work.\n\n**Table 1** Congestion on IBM macro placements.\n||Wiremask-BBO|Chipformer|MaskPlace|EfficientPlace|Ours|\n|-|-|-|-|-|-|\n|Average Congestion (RUDY)|323.6|335.9|345.02|366.7|195.5|\n\n**Validity of synthetic data:** We trained different-sized models on a dataset generated using Flora’s algorithm and found that models trained on their dataset show much poorer legality than ours when evaluated on the clustered IBM circuits. This indicates that the Flora dataset generalizes poorly, in contrast to ours. The results below are after 1M training steps.\n\n**Table 2** Performance of Large and Medium models trained on different datasets.\n||Large+Flora|Medium+Flora|Large+v1 (Ours)|Medium+v1 (Ours)|\n|-|-|-|-|-|\n|Legality|0.283|0.349|0.806|0.784|\n|HPWL (10^7)|3.058|3.306|3.330|3.527|\n\n**Training RL with synthetic data:** This is a good point, and we believe this to be an interesting experiment to perform in the future.\n\n**Clustering standard cells:** We performed mixed-size placement on the IBM benchmark using clustered standard cells (our approach), and the suggested approach (also commonly used in literature) of first placing macros only. The results below show that using clustered standard cells performs better, likely because the macro positions can be informed by connectivity and space needed for standard cells.\n\n**Table 3** Mixed-size placement performance with and without standard cell clusters.\n||Clustering|Placing Macro-only|\n|-|-|-|\n|Average HPWL (10^6)|22.7|27.9|\n\n**Recent papers:** We have conducted additional experiments comparing with EfficientPlace[1] in the macro-only setting, which we show below. Although EfficientPlace uses tree search to address the shortcomings of RL, our method still produces higher-quality samples in HPWL, while requiring a fraction of the sampling time. \n\n**Table 4** Comparison of various methods, including EfficientPlace, on the IBM benchmark.\n||Wiremask-BBO|Chipformer|MaskPlace|EfficientPlace|Ours|\n|-|-|-|-|-|-|\n|Average HPWL (10^6) | 7.432|7.931|8.723|8.316|2.495|\n\n**Answers to questions:**\n1. We used the official implementations and trained on the test (ie. IBM benchmark) circuits.\n2. We post-processed the macro placements with our own gradient-based legalizer. Combined with legality guidance, this method is effective in ensuring almost no overlaps.\n3. As mentioned in section 5.1.4, we do use a diverse range of scales to generate our dataset, sampling the scale from a log-uniform distribution, with a range of (0.05, 1.6) and (0.025, 0.8) for the v1 and v2 datasets respectively. \n\nWe thank the reviewer for the helpful comments on the writing and clarity of our paper, and will be sure to make the necessary changes. We hope we have been able to address your concerns.\n\n[1] Reinforcement Learning within Tree Search for Fast Macro Placement. ICML'24.", "claims_and_evidence": "“WireMask-BBO must be started from scratch for each new circuit.” Incorrect claim. The original WireMask-BBO paper show that it can fine-tune existing placements. I think the one of drawbacks of WireMask-BBO is the generalization ability and search efficiency, compared to those learning-based RL approaches.", "methods_and_evaluation_criteria": "There is no PPA evaluation. Although wire length is important, many articles have actually found that its impact on the final result is also limited. Recently, there are some open-source platforms have provided PPA evaluation such as OpenRoad and [1].\n\nI believe adding PPA assessment could significantly enhance the quality of this paper.\n\n[1] Benchmarking End-To-End Performance of AI-Based Chip Placement Algorithms. arxiv, 2024.", "theoretical_claims": "No theory part.", "experimental_designs_or_analyses": "1. I believe the validity of synthetic data requires more discussion. If synthetic data is a contribution, some experiments should be included to demonstrate that the previous method (e.g., Flora) is ineffective.\n2. Followed by point 1, I believe an important contribution is the study of the role of synthetic placement datasets. If the dataset proposed in this paper truly \"covers the important features\" as stated in line 311, it should also improve the reinforcement learning methods; however, the authors have not compared this aspect.\n3. Clustering standard cells: How does it compare to placing only several macros and then using DMP to place standard cells? How does it compare to other RL methods with the same clustering approaches?", "relation_to_broader_scientific_literature": "Chip placement is an vital tasks to EDA. Previous chip placement relies on RL and suffers several limitations. This paper first propose to use diffusion model to conduct chip placement and perform well.", "essential_references_not_discussed": "There are many recent papers on reinforcement learning for chip placement in AI conferences [1-3], which I believe should be at least discussed.\n\n[1] Reinforcement Learning within Tree Search for Fast Macro Placement. ICML'24. \n\n[2] Reinforcement Learning Policy as Macro Regulator Rather than Macro Placer. NeurIPS'24. \n\n[3] LaMPlace: Learning to Optimize Cross-Stage Metrics in Macro Placement. ICLR'25.", "other_strengths_and_weaknesses": "Strengths:\n1. Completely using synthetic data has demonstrated good generalization ability.\n2. The authors studied the impact of synthetic data on generalization and conducted extensive analyses, including the number of edges and vertices, etc.\n\nWeaknessess:\n1. The writing should be improved. Besides, adding some discussions of the background and recent related works would also be very beneficial.", "other_comments_or_suggestions": "1. More references should be added; for example, the first paragraph of the introduction has no references at all. It is necessary to include more articles on EDA background so that people in the machine learning field can understand the context of the problem.\n2. The third contribution - Model Architecture, cannot be considered a contribution, as it does not seem novel to me since many papers apply similar architectures. It would be better to list the application of diffusion for chip placement as a contribution here.\n3. Please use \"DMP\" rather than \"DP\" in Table 5 to represent DREAMPlace.", "questions_for_authors": "1. Where were the other RL methods in Table 5 trained?\n2. How are overlaps handled? Is the legalization method provided in DREAMPlace used?\n3. Fig. 6: Increasing the scale parameter significantly causes legality to violate constraints. Would using a diverse range of scales (e.g., randomly samling in a large range) during training lead to better results?", "summary_of_paper": "", "summary_of_recommendation": "", "technical_quality": "", "clarity_of_presentation": "", "potential_impact": "", "robotics_focus": "", "quality_of_limitations": "", "questions_for_rebuttal": "", "reasons_to_accept": "", "reasons_to_reject": "", "questions_to_authors": "", "extra_scores": {}}, {"review_id": "V8prMh5MVd", "reviewer": "Reviewer_QY6P", "summary": "The authors proposed a diffusion model-based chip placement strategy. They also developed a novel data generation algorithm and a synthetic dataset, training the model to enable zero-shot transfer to real circuits. Additionally, they introduced a neural network model that demonstrates strong performance and scalability.", "questions": "", "limitations": "", "rating": 3, "confidence": null, "soundness": null, "presentation": null, "contribution": null, "strengths": "", "weaknesses": "", "quality": null, "clarity": null, "significance": null, "originality": null, "strengths_and_weaknesses": "", "was_revised": false, "final_justification": "", "rebuttal": "We thank the reviewer for their helpful feedback. Our response is as follows:\n\n**Additional benchmarks:** We have included experiments on the ISPD2005 benchmark, which we show in the table below. To facilitate comparison with baselines, we follow the suggestion of reviewer m7a3 and present HPWL and congestion in the macro-only setting. These results show that our method significantly outperforms baselines on this benchmark as well.\n\n**Table 1** Congestion and HPWL of macro placements on ISPD2005\n||Wiremask-BBO|Chipformer|MaskPlace|Ours|\n|-|-|-|-|-|\n|Average Congestion (RUDY)|1837|988.7|1291|539.4|\n|Average HPWL (10^6) |19.534|13.689|14.925|4.393|\n\nWe hope we have been able to address your concerns.", "claims_and_evidence": "The major claims by the authors:\n1. Synthetic data generation: The approach generates a plausible netlist ensuring that the given placement is near-optimal while enabling data generation without relying on commercial tools or higher-level design specifications. Tables 1, 2, and 3 provide evidential support for this claim.\n\n2. Dataset design: An extensive empirical study was conducted to investigate the generalization properties of models trained on synthetic data, identifying several factors—such as the scale parameter—that contribute to poor generalization. These insights were utilized to design synthetic datasets that enable effective zero-shot transfer to real circuits. Once again, Tables 1, 2, 3, and 7 provide evidential support for this claim.\n\n3. Model architecture: The authors proposed a novel neural network architecture incorporating interleaved graph convolutions and attention layers, resulting in a model that is both computationally efficient and highly expressive. Tables 5 and 6 provide support for this claim.", "methods_and_evaluation_criteria": "The proposed method is thoroughly evaluated using a well-designed experimental setup and relevant metrics. The authors provide an in-depth analysis, effectively demonstrating proof-of-concept to support their claims. Additionally, the combination of proposed strategies enables the generation of placements for unseen netlists in a zero-shot manner, achieving competitive performance with state-of-the-art (SOTA) methods on the IBM benchmark dataset ICCAD04.", "theoretical_claims": "Yes, the theoretical claims regarding the quality of synthetic data generation, dataset design, scalability, and generalization impact have been quantified through experimental validation.", "experimental_designs_or_analyses": "Yes....... soundness/validity of experimental designs has been validated against:\n1. Synthetic data generation: The approach generates a plausible netlist ensuring that the given placement is near-optimal while enabling data generation without relying on commercial tools or higher-level design specifications. Tables 1, 2, and 3 provide evidential support for this claim.\n\n2. Dataset design: An extensive empirical study was conducted to investigate the generalization properties of models trained on synthetic data, identifying several factors—such as the scale parameter—that contribute to poor generalization. These insights were utilized to design synthetic datasets that enable effective zero-shot transfer to real circuits. Once again, Tables 1, 2, 3, and 7 provide evidential support for this claim.\n\n3. Model architecture: The authors proposed a novel neural network architecture incorporating interleaved graph convolutions and attention layers, resulting in a model that is both computationally efficient and highly expressive. Tables 5 and 6 provide support for this claim.", "relation_to_broader_scientific_literature": "The research topic and the presented idea, despite certain limitations, are interesting and hold potential significance for the broader research community. This is particularly true from two perspectives: synthetic data generation and dataset design. Additionally, the combination of the proposed strategies enables the generation of placements for unseen netlists in a zero-shot manner, achieving competitive performance with state-of-the-art (SOTA) methods on the IBM benchmark dataset ICCAD04.", "essential_references_not_discussed": "NA", "other_strengths_and_weaknesses": "Mentioned and discussed in previous sections as \"Methods And Evaluation Criteria*\" and \"Experimental Designs Or Analyses*\".", "other_comments_or_suggestions": "The authors should benchmark the proposed approach on other private or public datasets to establish its generalization and scalability, such as any modern IC design netlists.", "questions_for_authors": "I would like to hear the authors' thoughts on conducting an additional experiment using other private or public datasets to establish the generalization and scalability of the approach, such as modern IC design netlists.", "summary_of_paper": "", "summary_of_recommendation": "", "technical_quality": "", "clarity_of_presentation": "", "potential_impact": "", "robotics_focus": "", "quality_of_limitations": "", "questions_for_rebuttal": "", "reasons_to_accept": "", "reasons_to_reject": "", "questions_to_authors": "", "extra_scores": {"ethical_review_concerns": "No ethical review concerns noticed."}}, {"review_id": "rQE1yfamsu", "reviewer": "Reviewer_m7a3", "summary": "The authors propose a new diffusion-based method to address chip placement. Compared to existing RL approaches, pre-trained diffusion models can obtain the placement results on new circuits within minutes, which are much more efficient. After global placement, users can fix the positions of macros and optimize the cells using other cell placer like DREAMPlace.\n\n## update after rebuttal\nBased on the reply, I would like to increase the score to 3. I hope the authors could add these new experiments and illustrations to the revised manuscript for a more transparent presentation.", "questions": "", "limitations": "", "rating": 3, "confidence": null, "soundness": null, "presentation": null, "contribution": null, "strengths": "", "weaknesses": "", "quality": null, "clarity": null, "significance": null, "originality": null, "strengths_and_weaknesses": "", "was_revised": false, "final_justification": "", "rebuttal": "We thank the reviewer for their insightful feedback. Our response is as follows:\n\n**Choice of dataset:** We choose the IBM dataset for several reasons. First, it contains more circuits - 18, compared to 8 for ISPD2005. Second, the IBM dataset allows for easier comparison with other macro placement methods. The ISPD2005 benchmark contains circuits with a large number of macros (up to 23k), causing prior works to omit these circuits or pick macros to place according to various criteria. The IBM dataset avoids this issue, and allows for consistent evaluation of macro placement methods on all 18 circuits. \nNevertheless, we have evaluated our method on the ISPD2005 dataset, using the macro-only setting for easier comparison, with the results shown in Table 1 below. Our method achieves significantly improved performance over the baselines.\n\n**Macro-only Evaluations:** We agree with this suggestion, and present our results in the tables below. \n\n**Table 1** HPWL on ISPD2005 benchmark\n||Wiremask-BBO|Chipformer|MaskPlace|Ours|\n|-|-|-|-|-|\n|Average HPWL (10^6) |19.534|13.689|14.925|4.393|\n\n**Table 2** HPWL on IBM benchmark\n||Wiremask-BBO|Chipformer|MaskPlace|EfficientPlace|Ours|\n|-|-|-|-|-|-|\n|Average HPWL (10^6) | 7.432|7.931|8.723|8.316|2.495|\n\n**Time overhead:** We present the runtimes for our method and baselines in the table below. Our method is significantly faster than other macro placement methods, taking on average 4 and 20 minutes on the IBM and ISPD benchmarks respectively, compared to RL or BBO methods that take 10 times longer. We note however that we are slower than Dreamplace, and further optimization of our code and diffusion sampling is an interesting area of future work.\n\n**Table 3** Runtimes in minutes\n||Wiremask-BBO|ChipFormer|Dreamplace|Ours|\n|-|-|-|-|-|\n|IBM Average|227.2|124.88|0.475|4.39|\n|ISPD Average|886.5|1048.5|3.000|20.89| \n\nTo clarify, we used Dreamplace 4.1, and will correct the citation to reflect this.\n\n**Answers to questions:**\n\n1. Our motivation for choosing IBM is detailed above. We have also performed additional experiments on the ISPD05 benchmark, with results shown in Table 1 above.\n\n2. Yes, Table 2 in the ChipFormer paper reports macro-only HPWL, whereas Table 5 in our paper reports mixed-size HPWL.\n\n3. x is a (V x 2) array, where V is the number of objects in the netlist, containing the 2D positions of all objects, which includes macros and standard cell clusters.\n\nWe hope we have been able to address your concerns.", "claims_and_evidence": "The authors claim that RL methods are slow and suffer from flexibility, however, they do not show diffusion models’ detailed time overhead.", "methods_and_evaluation_criteria": "Yes, the proposed method intuitively makes sense, but the procedure is not that clear in Sec. 4.3. I suggest the authors provide a detailed algorithm box.", "theoretical_claims": "No theoretical claim is provided.", "experimental_designs_or_analyses": "The datasets used in the experiments are not in line with those in existing work. For example, this paper tests the approach on ibm01-18, but the baselines test the ispd05/25 benchmarks.", "relation_to_broader_scientific_literature": "This paper is an approach for chip placement, which is in the field of physical design in electronic design automation.", "essential_references_not_discussed": "Yes, I think the references are sufficient.", "other_strengths_and_weaknesses": "Other Strengths:\n- The authors address chip placement under the perspective of diffusion models, which can obtain chip placement results on new circuits within minutes.\n- The motivation is clear, as existing RL methods take a long time to complete the placement.\n\nOther weaknesses:\n- Non-learning methods, especially the DREAMPlace, are not included in the related work section.\n- DREAMPlace has lots of versions with significantly different performance, so it is important for the authors to mention the version that they used in the experiments. I note that the authors mentioned DREAMPlace 4.1 but cited their paper in 2019.\n- The datasets used in the experiments are not in line with those in existing work. The author could give a suitable explanation to address this weakness.", "other_comments_or_suggestions": "- The authors can display placement visualizations of different methods on the same circuit.\n- As the fixed-size performance significantly depends on cell placers (e.g, DREAMPlace), the authors could display more comparison results on macro-only settings.", "questions_for_authors": "- Why did the authors choose IBM benchmarks as the test dataset? I note that (all) the baselines the authors compared used ISPD05/15 as the datasets.\n- The experimental results of HPWL on ibm01-04 are quite different from those displayed in ChipFormer. Is this because the results of ChipFormer are macro-only and the results in this work are mixed-size?\n- What is the placement $x$? Is it the positions of all macros?", "summary_of_paper": "", "summary_of_recommendation": "", "technical_quality": "", "clarity_of_presentation": "", "potential_impact": "", "robotics_focus": "", "quality_of_limitations": "", "questions_for_rebuttal": "", "reasons_to_accept": "", "reasons_to_reject": "", "questions_to_authors": "", "extra_scores": {}}, {"review_id": "PdKmgjVUHV", "reviewer": "Reviewer_izVP", "summary": "This paper proposes to address the challenges faced in RL-based placement methods, including 1) scalability to larger circuits, and 2) the trajectory cannot be reversed in RL-based methods. A method to synthesize placement data, and a diffusion-based method to tackle the placement task are proposed.\n\n## update after rebuttal\nAfter carefully reviewing the rebuttals and comments, I would like to maintain my current score.", "questions": "", "limitations": "", "rating": 2, "confidence": null, "soundness": null, "presentation": null, "contribution": null, "strengths": "", "weaknesses": "", "quality": null, "clarity": null, "significance": null, "originality": null, "strengths_and_weaknesses": "", "was_revised": false, "final_justification": "", "rebuttal": "We thank the reviewer for the insightful feedback. Our response is as follows:\n\n**EfficientPlace:** Although EfficientPlace uses tree search to address the shortcomings of RL, it still requires significant training on every new circuit to perform well. We present additional experiments on the IBM benchmark below, showing that our method significantly outperforms EfficientPlace in both HPWL and congestion, while requiring a fraction of the time.\n\n**Table 1** Congestion and HPWL on IBM\n||Wiremask-BBO|Chipformer|MaskPlace|EfficientPlace|Ours|\n|-|-|-|-|-|-|\n|Average Congestion (RUDY)|323.6|335.9|345.02|366.7|195.5|\n|Average HPWL (10^6) | 7.432|7.931|8.723|8.316|2.495|\n\n**DreamPlace:** We highlight that our method outperforms DreamPlace, a very strong baseline, while other macro placement methods fall far short. This could be because DreamPlace relies on gradient descent, which performs a local search, whereas the diffusion model can perform a global search based on the training data. We agree that this additional performance comes at a cost, with our method having a longer runtime as shown in Table 2 below, and requiring several days of training.\n\nNevertheless, we emphasize that our work explores and develops a novel approach - training diffusion models - for the placement problem, and to our knowledge is the first to apply diffusion to this domain. Developing a method that is competitive with, even marginally outperforming, DreamPlace is still a significant improvement over prior macro placement approaches, and demonstrates that this approach has strong merits. We believe showing this is one of the contributions of our work.\n\n**Table 2** Runtimes in minutes\n||Wiremask-BBO|ChipFormer|Dreamplace|Ours|\n|-|-|-|-|-|\n|IBM Average|227.2|124.88|0.475|4.39|\n|ISPD Average|886.5|1048.5|3.000|20.89| \n\n**Non-overlap:** While it is true that our method does not enforce hard constraints to prevent overlap, we find that in practice this is not an issue. Legality guidance, combined with gradient-based legalization, is effective in ensuring almost no overlaps in our macro placements.\n\n**Optimization of other objectives:** We presented results on congestion in table 1 above, which shows that our method achieves significantly lower congestion than the baselines. This result is consistent with findings from prior work [1] that finds congestion to be correlated with HPWL. \n\nWe agree that downstream metrics such as PPA are important targets for optimization. However, optimizing for PPA is difficult, with many similar works focusing on simple proxy objectives like HPWL. Moreover, the commonly used benchmarks such as ISPD2005 and IBM do not support timing analysis. Because the goal of our work is to explore and develop a novel approach - training a diffusion model - to macro placement, we have therefore chosen to focus our contributions on developing the techniques necessary for such an approach, such as synthetic data generation, rather than simultaneously tackling PPA optimization. Therefore, while PPA optimization is an important end-goal, we leave it as an area for future work. \n\n**Answers to Questions:**\n1. We believe the magnitude in the ChipFormer paper should be 1e5. Table 15 of the MaskPlace paper [2] has the same numbers as those in Table 8 of the ChipFormer paper, but with a scale of 1e5, which is the same as us.\n\nWe hope we have been able to address your concerns.\n\n\n\n[1] Shi et. al. \"Macro Placement by Wire-Mask-Guided Black-Box Optimization.\" Neurips, 2023.\n\n[2] Lai et. al. \"MaskPlace: Fast Chip Placement via Reinforced Visual Representation Learning.\" Neurips, 2022.", "claims_and_evidence": "Yes.", "methods_and_evaluation_criteria": "Yes.", "theoretical_claims": "Yes. There are no issues about the correctness of any proofs for theoretical claims.", "experimental_designs_or_analyses": "Yes. There are no issues about the soundness/validity of any experimental designs or analyses.", "relation_to_broader_scientific_literature": "The idea of constructing synthesized data to support the training of model is valuable.", "essential_references_not_discussed": "A fast and strong RL+MCTS method [1] for macro & mixed-size placement, which is not discussed and compared.\n\n[1] Geng, Zijie, et al. \"Reinforcement learning within tree search for fast macro placement.\" Forty-first International Conference on Machine Learning. 2024.", "other_strengths_and_weaknesses": "**Strengths**\nA new approach to construct the synthesized data to alleviate the scarcity of data in the EDA field.\n\n**Weaknesses**\n1. Optimization of other objectives are not consideration, such as timing metric (WNS, TNS), final wirelength.\n2. Constraints such as the non-overlap constraint cannot be guaranteed by the diffusion method, which need a post-processing legalization to further eliminate the overlap. in the contrary, overlap can be avoided in RL-based method like MaskPlace and ChipFormer through the filtering out invalid positions in the actions which lead to overlap, e.g., through the position mask proposed in MaskPlace.\n3. The motivation of using diffusion-based method is not promising enough. The authors only discuss the weaknesses of RL-based methods, while the discussion of analytical methods such as DREAMPlace is ignored. The advantage of diffusion and the motivation should be further analyzed.\n4. Performance between the proposed approach and DREAMPlace is very similar, with only decreasing from 23.6 to 22.7, while other cost, including the congestion, timing metrics (WNS & TNS), runtime (speed), and the resources cost for training the diffusion model are not compared.", "other_comments_or_suggestions": "1. Compare the inference speed of diffusion-based method and analytical method.\n2. Consider other objectives, such as post-routing wire length, timing metrics, power, are hard to represent into a differentiable form, it is more attractive to inject these objectives into the optimization of diffusion-based methods, rather than merely concentrating on the optimization of HPWL.\n3. For other suggestions, please refer to the weakness part.", "questions_for_authors": "In Table 5, the magnitude of the mixed-size placement HPWL is 1e6, while in ChipFormer, the magnitude of mixed-size placement HPWL is 1e7 (shown in Table 8 in [1]). Could the authors to explain the inconsistency or check the correctness of the presented data?\n\n[1] Lai, Yao, et al. \"Chipformer: Transferable chip placement via offline decision transformer.\" International Conference on Machine Learning. PMLR, 2023.", "summary_of_paper": "", "summary_of_recommendation": "", "technical_quality": "", "clarity_of_presentation": "", "potential_impact": "", "robotics_focus": "", "quality_of_limitations": "", "questions_for_rebuttal": "", "reasons_to_accept": "", "reasons_to_reject": "", "questions_to_authors": "", "extra_scores": {}}]

Author rebuttal:

Meta-review: **Summary**: Paper used the standard DDPM diffusion pipeline  with a denoiser whose architecture has interleaved attention and Graph neural Net layers and many other modifications to adapt to the problem of placing macros (large components as I understand it ) on 2d Chip layouts. A lot of prior works use RL algorithms where they sequentially commit to placement of components with RL rewards reinforcing the policy. Authors point out that this problem calls for a simultaneous placement and therefore diffusion could play a role.

Authors come up with a simple method that randomly generates rectangular components and places them randomly obeying some overlap constraints and placement of pins satisfy some wire-length constraints. Authors show that by training a DDPM model with a novel architecture for denoiser using GNN layers, it shows impressive performance on many downstream metrics on real world benchmarks.

**Discussion/Rebuttal points**
1) From the discussion, it is acknowledged by reviewers and authors that this method is very competitive with DREAMplace - a state of the art method that uses a lot of domain specific information to optimize placements. Given that it is trained only on synthetic data and guided at test time by differentiable proxies, I see value in this being competitive with a good custom prior alternative.

2) Authors acknowledge that the benchmarks they have chosen are not compatible with other metrics like timing analysis but congestion based metrics are used to evaluate in the rebuttal. Different synthetic datasets were tried and their dataset generation method seems to outperform. 

**Overall**: Main weakness is lack of algorithmic novelty - its the same standard DDPM pipeline. However, the architecture for denoiser is novel and tailored to this domain and that is the main punchline. I don't consider lack of all downstream metrics in evaluation to be a potential block against publication. For the potential impact of diffusion to an important domain, novel architectural choices and demonstration that purely pre-training on synthetic data suffices, I am recommending accept.

Note to authors: Please include all the experimental results from rebuttal (including on new metrics and ablations on other synthetic dataset) to the paper.
Decision: Accept (poster)