DeepLayout: Learning Neural Representations of Circuit Placement Layout
Authors: Yuxiang Zhao
zhuomin chai
Xun Jiang
Qiang Xu
Runsheng Wang
Yibo Lin
Venue: ICML 2025 poster (2025)
Keywords: Circuirt representation
Pre-training
Self-supervised learning
Primary area: applications->everything_else
TL;DR: We introduce a layout-oriented self-supervised learning approach designed explicitly for circuit layout representation.

Abstract: Recent advancements have integrated various deep-learning methodologies into physical design, aiming for workflows acceleration and surpasses human-devised solutions. However, prior research has primarily concentrated on developing task-specific networks, which necessitate a significant investment of time to construct large, specialized datasets, and the unintended isolation of models across different tasks. In this paper, we introduce DeepLayout, the first general representation learning framework specifically designed for backend circuit design. To address the distinct characteristics of post-placement circuits, including topological connectivity and geometric distribution, we propose a hybrid encoding architecture that integrates GNN with spatial transformers. Additionally, the framework includes a flexible decoder module that accommodates a variety of task types, supporting multiple hierarchical outputs such as nets and layouts. To mitigate the high annotation costs associated with layout data, we introduce a mask-based self-supervised learning approach designed explicitly for layout representation. This strategy involves a carefully devised masking approach tailored to layout features, precise reconstruction guidance, and most critically—two key supervised learning tasks. We conduct extensive experiments on large-scale industrial datasets, demonstrating that DeepLayout surpasses state-of-the-art (SOTA) methods specialized for individual tasks on two crucial layout quality assessment benchmarks. The experiment results underscore the framework’s robust capability to learn the intrinsic properties of circuits.

DeepLayout: Learning Neural Representations of Circuit Placement Layout
Yuxiang Zhao 12 Zhuomin Chai 13
Xun Jiang
Qiang Xu 24
Runsheng Wang 156 Yibo Lin 156
Abstract
1. Introduction
Modern chip design has become extremely complex due to the continuous advancement of manufacturing technol- ogy and the ever-increasing scale of circuits (e.g- TPU, GPU). Recently, advanced Al methods have been widely employed across various stages of circuit design, signifi- cantly enhancing both automation and intelligence (DSO.ai, 2020; JedAI, 2022). the back-end (physical design) do- main, researchers have successfully leveraged Al for tasks such as macro placement (Mirhoseini al., 2020; Chen et al., 2023; Lai al., 2023; 2022), parameter tuning (Luo et al., 2024; Hsiao al., 2024; Geng al., 2023), and lay- out hotspot detection(Shao et al., 2024; Geng et al., 2022), thereby accelerating design cycles and, in certain instances, achieving performance that surpasses human-devised solu- tions.
Recent advancements have integrated various deep-learning methodologies into physical de- sign, aiming for workflows acceleration and sur- passes human-devised solutions. However, prior research has primarily concentrated on develop- ing lask-specific networks, which necessitate a significant investment of time to construct large, specialized datasets, and the unintended isolation of models across different tasks. In this paper, we introduce DeepLayout, the first general represen- tation learning framework specifically designed for backend circuit design. To address the dis- tinct characteristies of post-placement circuits, in- cluding topological connectivity and geometric distribution, we propose hybrid encoding chitecture that integrates GNN with spatial trans- formers. Additionally, the framework includes a flexible decoder module that accommodates a va- ricty of task types, supporting multiple hierarchi- cal outputs such as nets and layouts. To mitigate the high annotation costs associated with layout data, introduce baase self-supervised learning approach designed explicitly for layout representation. This strategy involves carefully devised masking approach tailored to layout fea- tures, precise reconstruction guidance, and most critically- two key supervised learning tasks, We conduct extensive experiments on large-scale in- dustrial datasets, demonstrating that Deepl Layout surpasses state-of-the-art (SOTA) methods spe- cialized for individual tasks on two crucial layout quality assessment benchmarks. The experiment results underscore the framework's 's robust capa- bility to learn the intrinsic properties of circuits.
Fig. shows chip design flow. To reduce reliance on time- intensive EDA tools, the aforementioned methods construct task-specific datasets and train corresponding circuit repre- sentation models to enable efficient assessment of circuit performance. Constructing such large-scale, specialized, and labeled datasets requires extensive domain expertise and significant human resources. However, some raw cir- cuit designs can be acquired from these sources: (1) open-
Front-end design
Back-end design
module test input inj3;
endmodula RTL
Netlist
Floorplan
Fabricate
Routing
Placereent
Peking University National Technology Innovation Center for EDA 'Wuhan University "The Chinese University of Hong Kong Institute of Electronic Design Automation, Wuxi, China 'Beijing Advanced Innovation Center Integrated Circuits Correspon- dence to: Yibo Lin <yibolin @ piku.edu.cn>.
Back-end design
Figure The chip design flow is primarily divided into front-end functional/logic design and back-end physical design. Compared to front-end design, the back-end phase significantly more time- consuming. The finalized chip layout is sent to the foundry for fabrication.
Proceedings of the ndnd International Conference Machine Learning. Vancouver, Canada. PMLR 267, 2025. Copyright 2025 by the author(s).

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DeepLayout: Learning Neural Representations of Circuit Placement Layout
Self-suporvised Pre-training
network that progressively captures geometric and topologi- cal relationships, providing the rich feature representations essential for downstream tasks at both node and layout lev- els. Secondly, unlike front-end representation emphasizing functional attributes, back-end design primarily targets ge- ometric characteristics rather than functional behavior. As a result, simply masking irrelevant nodes at random and restoring node-category attributes inadequate. We adopt size-adaptive masking approach based on grid units to ensure that masked grid regions retain consistent macro- scopic attributes, such as cell density. Thirdly, to foster synergy between local and global feature reconstruction, we go beyond restoring the masked nodes' coordinates by incorporating additional routing-related features to enhance the network's representational capacity. Specifically, we introduce an easy-calculated intermediate routing feature (RPA), enabling the encoder capture and exploit routing information and thus mitigate potential biases caused by particular routing algorithms.
Essy-coloulated Layout Supervision Signals
Gruggh
Rotiee Pank Ietomationn
Netioz
Placensent Deta
Dappl aspul Laseit Reprscatation
Encoder
Fine- Fine-ttning
Congasiun Wine Lingth DRC
Netlst
Trangfer Applicatioos
Dewsemmom Tisis
Target Tisks
Data
Visiation
Figure 2. Illustration of the DeepLayout paradigm for circuit layout representation. This paradigm enables self-supervised pre pre-training on placement-only datascts and applics the Icarned representations to multiple applications.
source repositories (e.g., GitHub), (2) intermediate design parameter configurations, and (3) legacy design databases. These unlabeled circuit data can potentially be leveraged using self-supe learning techniques- demonstrated to be highly effective in the image (He et al., 2022b) and text (Devlin et al., 2018 - to extract strong and general repre- sentations. Motivated by these considerations, we pose a key question: Can we harness massive collections of raw circuit data to deeply uncover intrinsic circuit properties thereby yielding a general model that generalizes across a broad spectrum of downstream tasks?
Our contributions are as follows:
We are the first to propose general circuit represen- tation framework for placement layout learning, en- abling fine- tne-grained feature learning from unlabeled data through novel mask strategies and self-supervised tasks.
In recent years, some research has focused applying cir- cuit representation learning to front-end (logic) design by transforming circuits into AIG (And-Inverter Graph) struc- tures and leveraging unsupervised or contrastive learning strategies to uncover latent relationships between circuit functionality and logic (Li al., 2022; Shi et al., 2023; 2024; Wang et al., 2022b). However, these methods exhibit significant limitations when extended to back-end circuit representation tasks. As circuit logic functionality is not strongly correlated with circuit performance, existing ap- proaches often fail to adequately emphasize the extraction of physical attributes relevant to PPA (Power, Performance, Area), thus limiting their applicability to back-end design scenarios.
We propose a hybrid encoder that jointly models topo- logical connectivity and geometric layouts via hetero- geneous GNNs and spatial attention mechanisms. The pre-trained encoder demonstrates remarkable transfer- ability across diverse downstream tasks.
We conduct extensive experiments on industrial scale benchmarks, demonstrating Deeplayout's 's superiority over SOTA methods in congestion prediction and post- routing wirelength estimation.
2. Preliminary
1. Masked-based Representation Pre-training
To address these challenges, we propose layout-oriented masked autoencoder, called DeepLayout, for back-end self- supervised representation learning. Fig. 2 illustrate the DeepLayout framework. We model the post-placement circuit as a heterogeneous graph enriched with geometric information, employing node and net as two distinct node types to capture the circuit's hierarchical structure. Com- pared with masking strategies for images or generic graphs, layout-oriented masked autoencoder must satisfy three key requirements. Firstly, both geometric and topological information are vital in post-placement circuits. For exam- ple, nodes that are topologically adjacent may be widely separated in physical space. Therefore, we develop a refined
There has been longstanding desire to achieve deeper data understanding without relying on numan-annotatee labels. Masked-based representation pre-training, a self- supervised learning paradigm, addresses this challenge by employing a process of Masking and Restoration.
In this approach, certain portions of the data are masked, and the model is trained to restore the missing parts based on the visible ones. By learning to predict these hidden components, the model can develop more meaningful and generalizable representations, enhancing its ability to per- form well on downstream tasks. This concept underpins many state-of-the -he-rr- art models across a variety of domains,
2

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DeepLayout, Learning Neural Representations of Circuit Placement Layout
a
3. DeepLayout
Cell Node
Do
Net
Node
Achieving effective pre-training requires careful consider- ation of two critical factors: the learning strategy and the supervision signal. For now, few studies attempt to apply mask-style self-supervised representation learning methods to circuits after placement. We attribute this to two primary challenges: (i) the difficulty in selecting suitable objects to mask (e.g., nodes? modules?), and (ii) it is challenging to simply use the original input information as the restoration target that is commonly done in vision tasks.
Net b
Cell-cell edge
Cell-net edge
(a)
(b)
Figure 3. Illustration of circuit heterogeneous graph. (a) Original circuit netlist with cells and connecting nets. (b) Correspond- ing heterogeneous graph, where cells and nets are represented as distinct node types, connected by cell-cell and cell-net edges to capture both structural and hicrarchical information.
Considering this, our DeepLayout introduces novel frame- work that paves the way for the achievement of mask-based self-supervised circuit representation pre-training. The or- ganization is as follows: Section 3.1 introduces a graph data structure used to represent post-placement circuits. Sec- tion 3.2 and Section 3.3 discuss the masking strategy and the two pre-trained supervision tasks. Section 3.4 presents the network architecture design.
such as BERT (Devlin et al., 2018), where masked words or tokens are predicted, and Masked Autoencoders (MAE) (He et al., 2022b), which mask image patches and train the model to restore them. The pre-trained models can thereby be fine-tuned for specific tasks, such as classifica- tion, segmentation, or object detection, yielding superior results. This masked-based pre-training paradigm is partic- ularly well-suited for scenarios where obtaining negative samples is challenging, such in circuit representation. It enables the model to approximate the underlying data distri- bution and learn intrinsic data features without the need for explicit labels, thus making it a powerful tool for enhancing representation learning in these contexts.
3.1. Circuit Heterogeneous Graph
Graph Structure. We start by modeling the circuit netlist as graph. Fig. 3()) represents the circuit's logical con- nectivity through cells (i.e., AND/OR gates flip-flops) and nets (connecting cell terminals). We represent each cell as node e E V in the graph, while edges encode predefined physical or interconnect relationships between connected cells. To address the inherent hierarchy of cir- cuit blocks (e.g.. arithmetic units), we introduce virtual net nodes u E U that aggregate connectivity patterns within sub-circuits. This dual-node formulation transforms into heterogeneous graph (Fig. 3(b)) that explicitly preserves both structural connectivity and functional hierarchy. To this end, we maintain three critical circuit properties- in- cluding signal propagation paths, fanout/fanin relationships, and block-level abstraction.
2.2. Circuit representation learning
Circuit representation learning has recently emerged as a pivotal research direction for enabling machine learning- driven analysis and optimization of electronic circuits (Chen et al., 2024). In the realm of front-end design, the repre- sentation of circuits commonly involves the utilization of the synthesized netlist to depict the internal configuration of the circuit. The concept introduced in a study by Wang et al. (2022b) aimed to investigate netlist representation, proposing a contrastive learning framework that allows the network to comprehend both the structural elements and embedding functionality of netlists. Subsequently, Deep- Gate (Li et al., 2022) approached this issue from different angle by developing neural representations of logic gates, incorporating signal probability supervision to account for both the structural characteristics and logical operations of circuits for various downstream applications. Building upon this work, subsequent study by Shi et al. (2023) sought to overcome the limitations of its precursor by implement- ing more direct supervision strategy utilizing Bair-wise differences in truth tables, thereby enhancing the ability to capture circuit functionality more effectively. However, as the logical functionality of a circuit is not closely tied to per- formance, these function-oriento front-end representation approaches are not applicable in back-end circuits.
Graph Feature. We formally define the heterogencous graph G UV X,,, Xu). where E represent edges that encode cell-to-cell direct dependencies and cell-to-net membership. The feature matrices X, and X, contain cell and net features. X, including cell size and spatial coor- dinates, which jointly govern routing related PPA learning. X,, storing the connected pins degree and net span on each axis. Here, ny and n., denote the total cells and nets in the design. Tab. shows the graph features in detail. Notably, we omit edge features to avoid over-engineering connectiv- ity patterns. Unlike prior works (Yang et al., 2022; Wang et al., 2022a) that relied on handcrafted features like local cell density or pin density, We pose DeepLayout operates directly on the circuit's native structural and geometric at- tributes. This benefits DeepLayout by eliminating tedious task-specific preprocessing, enabling unified circuit repre- sentation adaptable to diverse physical design downstream
3

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DeepLayouu Learning Neural Representations of Circuit Placement Layout
dy
dy
Cell node with shape
MASK
Masked cell node
Cell-cell Connection
Cell-net Comection
W
Heterngeneous Graph
(a) Layout Spliting
(b) Masked cells Select
(c) Topology guided
Mashed Graph
restoration
Figure 4. The pipeline of layout masking strategy, Cell-to-net heterogencous relation also retained but are hidden in figure for simplify.
Algorithm Layout-oriented Masking Algorithm. Heterogeneous graph G, input layout size W x H, pre-defined mask ratio 7 grid size dx x dy. Masked graph and corresponding processed fea- tures.
Table I. The features utilized in circuit heterogeneous graph.
Input:
Node
Type
Feature
Definition
h
Cell Height
Output:
Cell
w
Cell Width
(cell)
Pr
Number of pins
Extract the coordinates (x, y) of each cell node in the graph Partition the layout of size W H into grid set {g} using fixed grid size dx, dy
Geometric
x
Cell coordinate in X asix
y
Cell coordinate in Y asix
Connections
d
Net degree
Align each cell to the corresponding grid according to its coordinates (zz, y);
u (net)
hy
Net span asix
Span
W/a
Net span in X asix
Count the number of non-empty grids N and compute the number grids to be masked N,. = x
Randomly select the grids to be masked: {fm} +
tasks.
RANDOM (1g),,N,,) Initialize the set of masked cell node indices: Im = Ø for = 1 Nm do
3.2. Layout-oriented Masking
for each cell E the current grid ga do 8
Fig. 4 depicts the masking strategy in DeepLayout. We systematically demonstrate this through modular decompo- sition, outlined below.
L Add the cell index to Lmi Im + Im U {index]
9
Extract the cell node c₁ features X, of the graph G, ck
Layout Splitting is inspired by Hc et al. (2022b). Since circuit layouts can be represented as images, we are in line with this philosophy by partitioning the layout into 12 for each index v; E Jm do Padding cell node coordinates x, y to 0 Set X [0, 0, h, w.pl
U, E V
Copy cell features X! processed + X.
11
set number of non-overlapping grids {g}. treating all cells within the same grid independent masked entity (Fig. 4(a)). Specifically,
processed
pre-define the single grid size 14 Replace the original features of the graph G with the pro- cessed features X processed
as dn x dy and the layout plane, with dimensions W x H, is split into W H. grids, denoted as {9 Each cell d, dy
ca(cx= v, u V) is then aligned to corresponding grid Ji. based on its coordinates (Ik; yk).
within each grid, maintaining consistent physical charac- teristics from a global layout perspective. We empirically set the grid size d,, dy to correspond to 30 routing track lengths. In some corner cases where standard cells span across multiple grid boundaries, we assign them to the grid where they have the largest coverage area.
91,5 = ct [xx/d=] =, L = (1)
where i,j represent the grid indices (1 sis 1, $5is #)) and [x] symbolizes the floor function of coordinate xr Unlike the fixed patch numbers in image-based models like VIT (Dosovitskiy et al., 2020), Deeplayout employs variable number of grids for each design. This offers two distinct advantages: (i) it accommodates a wide range of floorplan sizes, from small modules to full-scale SoCs, and (ii) it guarantees a relatively uniform distribution of cells
Masked Grid Selection Unlike image masking methods that permit arbitrary patch selection across the entire can- vas, the post-layout floorplan includes vacant regions devoid of cells, necessitating the selection of masked grids exclu- sively from non-empty candidates (gi.; # Ø). We designate the selected candidates as masked grids { with the

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DeepLayout: Learning Neural Representations of Circuit Placement Layout
Task Cell Coordinate Reconstraction
Normalized
Cooedinites
Decoder
Aepsord Isate
Scale 1x
Tank Routing Process Prediction
Xx
Multi-Seule Geometric
Og
Heteragenous
4%
Sx
Placenent Layout
GNN
Attention
Decoder
Footing
Probabilay Algrritm
Mashad Graph
Routing
Encoder
Figure 5. Overview of the DeepLayout pre- wre-tranning pipeline. DeepLayout encodes masked heterogeneous graph using multi-scal geometric attention and heterogeneous GNNs at increasing spatial resolutions [1x, 2x, 4x,8x It is trained via two objectives: cell coordinate reconstruction and routing process prediction, optimized by t coordsnate and Lroning
remainder classified as visible grids } We hold the hyperparameter 7 to balance between these two subsets. Thus, visible and masked cells are aggregated by combin- ing cells from {gTn] and { respectively, formalized as: { Ui, J and U -. The graph G is subsequently updated by replacing cell node features with processed features (X (Xprocessed) For cells in masked grids (mm) the coordinate values (zx, yk) are padded while retaining the original size and property features [h, w. p).
3.3. Pre-training Supervision Signal
The supervision signal plays critical role in determining the knowledge acquired during pre- pre-training. Fig. 5 illus- trates the pre-training framework of DeepLayout,, which in- corporates two carefully designed tasks to exploit the unique properties of post-layout circuits: #1 Cell coordinate re- construction: recover masked cell coordinates. #2 Routing process prediction: modeling interconnect behavior.
Task #1 Cell Coordinate Reconstruction.
Placed cell coordinates provide essential geometric constraints for phys- ical design's 's downstream tasks. We implement a coordinate reconstruction objective through a single-layer multilayer perceptron (MLP) that predicts normalized coordinates of masked grid nodes. Formally, for each masked node {cx] ). the MLP generates predicted coordinates P = { k 1, 2, ..., K). while the ground-truth normalized coordinates are denoted P {Px kk 1, 2, ..., K}. The reconstruc- tion loss is computed using the mean squared error (MSE) between i and P as formulated below:
[0,0, [0,0, 1,0,h,,,1 w. if E %
m
X processed ok
(2)
X
if cr & m ck
Mask ratio is typically determined empirically. We can cast the previous unsupervised pre-training works (Zhu et al., 2022; Li al., 2022) as a special case of DeepLayout, where the 7 is fixed 0 to enable autoregressive learning- In practice, we found that setting pre-training performance, which contrasts with the higher 75% mask ratio commonly used in MAE. We hypothesize that this difference arises due to the nature of the data. Im- ages tend to exhibit a high level of information redundancy. In contrast, circuits contain rich information among sub- circuits.
50% yields optimal
L#1
1
Σ PLEP
1lpk Px
(3)
K
Restoration Guidance is another crucial aspect to consider. Typically, circuits exhibit weaker global correlations than images. This makes it particularly challenging for the net- work to accurately reconstruct masked regions from the vis- ible parts-akin to attempting to restore a QR code without any prior knowledge. To address this, we preserve the origi- nal topological connections between masked cells (v - v) and cells-to-me (u u) to aid in the restoration process. Fig. 4(c) illustrates masked graph with topological connec- tions. From a physical design standpoint, this approach is analogous to the incremental placement or Engineering Change Order (ECO) process, where local modifications are made while maintaining the overall eircuit design integrity.
Task #2 Routing Process Prediction. Compared to cross-stage evaluation from the placement, routing is time- intensive yet provides more accurate performance metrics, especially for timing and power consumption. However, directly training a machine learning model mimic the routing process is highly challenging. To address this, we guide the model to learn an intermediate routing represen- tation that captures essential aspects of the routing process. Specifically, we use computationally efficient Routing Probability Algorithm (RPA) as the supervision signal. This algorithm estimates the probability of routing paths within the net bounding box of sub-circuit, defined as follows:
5

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DeepLayout: Learning Neural Representations of Circuit Placement Layout
Proxy vector
pxd
Inpor
K1
1
V1
H
Align
Scatter Conv
H
Remap
11
@
A2
x
V.
Ousqui
W xhxpxd
xixpxx
11,
11
xpx
xyxx
(b)
Figure 6. Encoder's geometric and topological module: (a) Multi-scale Geometrie Attention (MSGA), (b) Heterogencous GNN (HGNN).
application across multiple downstream tasks. We introduce
(x,
1
(4)
each component as follows:
Encoder. The encoder designed as cascaded architecture, as shown in Fig. 5(a), which alternately stacked geometrie and topological modules. It operates on all graph's 's nodes and encodes each node's ' feature into the latent space. Dur- ing both pre-training and fine-tuning, the encoder's archi- tecture remains unchanged. A detailed description each module the following parts.
where Tu Yu represents the cell or pin positions within the net u, and xt = max Zu. xy = min Zu. v = max Yus v' = min you denotes the net bounding box. And RPA, y) outside the region [o att yle vål set to O. The total routing probability across the layout is then computed as:
RPA =
E
RPA, (x. v).
(5)
O< O. H,EE
Multi-scale Geometric Attention (MSGA) captures spa- tial relationships between standard cells in geometric space by combining local and global perspectives, as illustrated in Fig. 5(b). In the local perspective, we aggregate multi-scale sparse convolution features from 2D-mmppedd cells. In the global perspective, to address the computational complexity (nn"d) d) of native trans- former attention mechanisms (where n is often large in circuits), MSGA reduces complexity by decomposing global attention into two independent parts, inspired by He et al. (2022a). The MSGA module operates exclusively on the standard cell features X, E R= of graph G, where d is the feature dimension.
where W. H is corresponds to the layout size and RPA E R W xH This RPA is similar to the algorithm introduced in Spindler & Johannes (2007). The objective is defined as minimizing the MSE between the RPA among masked nodes and the ground-truth R.A., formulated as:
Nm
RPA, - RPA, 1
C
#12 routing
(6)
m
where Nm denotes the number of masked grids. We sum- marize the benefits of using RPA in twofold: (i) it allows routing related features to be derived solely from placement information, without the need for additional labels, thereby simplifying computation; and (ii) it helps the model general- ize better and reduces bias caused by the label randomness inherent in heuristic routing algorithms.
The first part of global attention is generated by apply- ing Multi-Layer Perceptron (MLP) to linearly project X., producing key (K1) and value (V1) vectors. To address the inefficiency of directly using the native projected query from X, in attention calculations, we introduce a learnable proxy query P E Rxd where p (the length of P) much smaller than n,. The first attention matrix A is computed using P and K1, and the hidden feature H1 is obtained by multiplying Vi with A,, Ki Id.xxd xd V1 E g The formulation for the first attention is as follows:
Overall Loss. To this end, the overall loss function for DeepLayout's supervvidd pre- tre-training is formulated by integrating the two component losses:
C L #1
#
coordinate moting
Throughout the pre-training phase, we iteratively minimize the loss until the model attains numerical convergence.
K1, V1 = MLP MLP,
(8a)
3.4. Layout Representation Network
A Softmax(K ( P?), A R
(8b)
We instantiate DeepLayout network, with an asymmetric architecture consisting of a task-agnostic encoder and task- specific decoders. This flexible architecture ensures unified pre-training during the physical design stage and facilitates
H ATVi, H1 E x
(8c)
Next, we aggregate multi-scale local features by map- ping the hidden feature H2 to a 2D plane using the
6

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DeepLayout: Learning Neural Representations of Circuit Placement Layout
scale parameter 8, outlined in line 3 of Section 3.2. This produces the scale-mapped feature H1, where aligns with the grid size dæ dy from the layout parti- tioning algorithm. The feature dimensions v x h are calculated as vi sxdr
Table 2. Pre-training and downstream learning parameters, Pred
and Esti are abbreviation of Prediction and Estimation.
Tasks
Epoch
Weight Decay
Decoder
W and h = exdy with W and H representing the layout size. The encoder employs four MSGA modules with scales s progressively increasing as [1x,2 2x, 4x, Sx] to capture broader range of lo- cal features. Sparse convolutions extract local features Hi,, which are remapped back to the original sequence order as H2, based on the indices of X.,, formulated as follows:
Pre-training
4c-3
100
lc-2
U-Net + MLP
Congestion Pred.
3e-4
50
le-4
U-Net
Wirelength Esti
4e-4
50
MLP
then applied to
iteratively aggregates topological information, updat- ing cell and net representations. The final cell and net features are generated through MLPs. For example, cell-to-cell (u -> v) aggregation within V, the core mechanism of graph message propagation described by the following formula:
fi AH
Hi Rixhxxxd
(9a)
H2 = Scatter conv( (H)), Hg e Roxhxpxd
(9b)
m AGGREGATE
H2 RE))
H2 Roxxpxd
(9c)
(12a)
Finally, in the second part of global attention, the in- put and hidden feature H2 generate the query Q, key K2, value V22 with linear projection. Given matrices Q.Q Ro the output of MSGA module can be calculated:
h00h = a (W(() m + b(K)),
(12b)
O, = MLP.(h.!))
(12c)
where (x(1 is the hidden feature of the cell net from the (k: - 1) layer. AGGREGATE(()) is the func- tion that aggregates neighboring node features ((v), resulting in the aggregated message m at layer k. The node features are updated using a weight matrix W(k), bias ((()) and activation function o. Cell-to-net (u - u) message propagation as the same.
A2 = Softmax Softmax(H2Q"),
A2 E
RR
(10a)
O = V2. V2,
O Ro.xd
(10b)
The overall computation complexity reduced from (n?2d) to (npd). The extracted cell features in MSGA are fed into the subsequent module for further extraction of topological relationships.
After pre-training, the encoder can serve as a powerful neu- extractor, providing comprehensive high-level circuit representations decoders for various downstream tasks.
Heterogeneous GNN (HGNN) aggregates node features X, and X, in the topological space, illustrated in Fig. 5(c). The input graph G includes all nodes V and U, with V's features derived from the output of the pre- ceding MSGA module and U's features sourced from either the raw input data or the output of the previous HGNN module. We aggregate topological features in three sub-steps, beginning with the transformation of cell and outputs into hidden representations via separate single-layer MLP networks.
Decoder. The decoder configurations used for both pre- training and fine-tuning are presented in Tab. 2. During fine-tuning, we explore two decoder configurations in our case study, each designed for a specific predictive objective: 1D -ereerssssonn, 2D 2Drrgreessio.
4. Experiments
4.1. Experimental Setting
We conduct experiments on CircuitNet (Chai et al., 2022: 2023), a large-scale public dataset of IC designs for real- world industrial applications. The CircuitNet-N288 (28nm) version comprises over 10,241 samples from 6 RTL de- signs, including 54 synthesized netlists with variations in macros, frequencies, and back-end flow settings. In our ex- perimental setup, the pre-training set contains four designs (RISCY-a, RISCY-b, RISCY-FPU-a, RISCY-FPU-b), total- ing over 6,000 samples that only utilize the raw input data
h, (O.,, ML..(O.)) or (X,,
(11)
where O, and O,, represent the outputs of the previous MSGA and HGNN modules, respectively. We set the dimension of h, across the encoder's four modules to {32,66 64, 128, 256} and set h, dimension remains 128. The heterogeneous graph message passing layer

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DeepLayout: Learning Neural Representations of Circuit Placement Layout
Table 3. A comparative analysis of Leeplayoout with existing methodologies in congestion prediction.
5 samples
10 samples
20 samples
Method
Pearson
MAE
RMSE
SSIM
Pearson
MAE
RMSE
SSIM
Pearson
MAE
RMSE
SSIM
GPDL
0.2679
0.2418 0.2476 0.2926
0.2663
0.1061 0.1117 0,5193
0.3174
0.0662 0.0724 0.6601
CircuiLGNN
0.2978
0.0166 0.0520 0.7395
0.2155
0.0128 0.0397 0.7681
0.2374
0.0127 0.0392 0.7693
CircuitPoint
0.2783
0,10
0.1148
0.0943
0.3000
0.0951
1056 0.0899
0.1910
0.1059
0.1161 0.0514
Deeplayout
0.4270
0.0146
0.0379 0.7718
0.4383
0.0130
0.0360 0.7820
0.4418
0.0121
0.0349 0.7909
Table 4, A comparative analysis of DeepLayout with existing methodologies in post-routing wirelength estimation.
5 samples
10 samples
20 samples
Method
Pearson
MAE
RMSE
Pearson
MAE
RMSE
Pearson
MAE
RMSE
Net²
0.1155
0.1441 0.1849
0.3141
0.1424 0.1766
0.2578
0.1441 0.1793
CireuitGNN
0.3683
0.1323
0.1722
0.3691
0.1371
0.1730
0.3691
0.1319 0.1727
DeepLayout
0.3704
0.1305
0.1695
0.3806
0.1290
0.1689
0.3961
0.1270 0.1682
treating layouts as multi-channel images; 2) CircuitGNN (Yang et al., 2022), which integrates geometric information into graphs via a graph neural network; and 3) CircuitPoint (Zou et al., 2023), which uses sparse convolution to perceive spatial relationships, treating standard cells as a point cloud.
Gpdl
w/o pre-train
DccpLayout
Ground Truth
samples
samples
samples
Figure 7. Visualization results of congestion prediction.
0.60
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to represent a large corpus of unlabeled samples. The fine- tuning and test sets each introduce two additional designs, zero-riscy-a and zero-riscy-b. Specifically, the fine-tuning set comprises small amount of labeled mata--coffigured as 5, 10, or 20 samples-whin samples. This test set is used to evaluate quality predictions for these two additional designs under various parameter configurations.
Setricc
0.50
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Spearmanr
the test set contains 100
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Mask Ratio
Mask Ratio
Mask Ratio
Figure 8. The impact of different mask ratios congestion pre- diction.
4.2. Downstream Tasks
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xamples
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samples
0.42
20 samples
0.18
LeepLayout is pre-trained on our proposed layout-oriented masking strategy. Predictions from these tasks facilitate targeted early optimizations during the placement stage, thereby reducing dependency on time-intensive EDA tools throughout the design process. Notably, these tasks focus assessing circuit quality after routing, presenting significant challenges in practical applications.
0.17
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0.39
Paarenn
0.16
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Mask Ratio
Mask Ratio
Mask Ratio
Congestion Prediction. Routing congestion poses a thorny problem in the design process. Addressing this issue early in the placement stage effectively reduces redundant un- routability and minimizes the need for complex routing iterations, and ML methods are widely used to predict con- gestion throughout the process.
Pearson
-on
MAE
RMSE
Figure 9, The impact of different mask ratios on post-routing wire- length estimation.
Tab. 3 presents comparative analysis of DeepLayout and other three prediction methods across different data scales, DeepLayout demonstrates significant performance dispari- ties among the evaluated methods. Fig. shows the exam- ples of congestion prediction results. Deeplayout demon- strates systematic dominance, achieving the highest Pearson
We comprehensively compare the SOTA baseline methods with diverse methods, including based, graph-based. point- based machine-learning methods. Compared methods are: 1) Gpdl (Liu al., 2021). a fully convolutional model
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DeepLayout: Learning Neural Representations of Circuit Placement Layout
scores (0.4270-0.4418), lowest RMSE (0.0349-0.0379), and best structural fidelity (SSIM: 0.7718-0.7909) across all configurations.
Acknowledgments
This work was supported in part by the National Key Re- search and Development Program of China under Grant in part by the Natural Science Foundation of Beijing, China, under Grant Z230002; in part by the Na- tional Science Foundation of China under Grant 62034007; and in part by the 111 Project under Grant B 110011; in part by the Hong Kong Research Grants Council (RGC) under Grant No. 14212422 and 14202824.
Post-routing Wirelength Estimation. Wirelength esti- mation is longstanding challenge in the design process, where traditional algorithms often rely on the simpler half- perimeter wirelength (HPWL) metric. However, the more accurate post-routing wirelength, which better models net behavior, remains difficult to estimate effectively.
We comprehensively compare the SOTA baseline methods with diverse methods. Compared methods are: Enhance- ments to the comparative method (Xie et al., 2020) and improvements to CireuitGNN (Yang et al., 2022) by integrating topological and geometric edges, which enabled more accurate post-routing wirelength estimation.
Impact Statement
This paper presents work whose goal is to advance the field of Machine Learning. There are many potential societal consequences of our work, none of which we feel must be specifically highlighted here.
Tab. 4 evaluates DeepLayout and other post-routing wire- length estimation methods. DeepLayout demonstrates sys- tematic superiority across all metrics, achieving the highest Pearson scores (0.3704-0.3 0.3961) and the lowest error rates (MAE: 0.127-0. 1305; RMSE: 0. 1..16.22.02 1695), with perfor- mance improving consistently as dataset size increases.
Analysis of Mask Ratio. In this section, amalyze the im- pact of mask ratio on the performance of downstream tasks. We select three different mask ratios matios-20% 50%, and 80% -to pretrain the LyepL framework, followed by fine- tuning on two downstream tasks. As shown in the line graphs in Fig. 8 and Fig. 9, 50% mask ratio consistently yields the best performance for both routing congestion and wire length estimation, across varying numbers of finetuning samples. This result suggests that circuit layouts exhibit sig- nificant differences from images, and therefore, selecting relatively lower mask ratio leads to more optimal outcomes.
5. Conclusion
In this paper, we present DeepLayout, the first circuit repre- sentation learning framework tailored for backend design, addressing critical limitations in prior approaches that rely on task-specific models and costly annotated datasets. By integrating a hybrid graph neural network (GNN) and spa- tial Transformer architecture. our framework effectively captures the topological and geometric characteristics of post-placement circuits while enabling flexible multi-task outputs through modular decoder design. To overcome la- beling bottlenecks, we introduce a self-supervised learning strategy incorporating layout-aware masking mechanisms and dual supervision objectives. Extensive evaluations on industrial-scale benchmarks demonstrate DeepLayout's 's su- periority over specialized state-of-the-an -tt--rrtt methods in two layout quality assessment tasks, validating its ability to learn intrinsic circuit properties robustly. DeepLayout paves the way for promising new direction in layout pre-training.
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DeepLayout: Learning Neural Representations of Circuit Placement Layout
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Reviews:
[{"review_id": "UG0Mcd59a8", "reviewer": "Reviewer_eM95", "summary": "This paper proposed a mask-based approach for circuit layout representation learning. Specifically, a grid-based partition is dedicated to dealing with the mask operation on layout. Two tasks are utilized to illustrate the potential, including wirelength estimation and congestion prediction. The results outperform previous approaches.", "questions": "", "limitations": "", "rating": 3, "confidence": null, "soundness": null, "presentation": null, "contribution": null, "strengths": "", "weaknesses": "", "quality": null, "clarity": null, "significance": null, "originality": null, "strengths_and_weaknesses": "", "was_revised": false, "final_justification": "", "rebuttal": "R1\nQ1:\n\"Congestion and wirelength ... strength the paper.\"\n\nA1\nWe have additionally designed post-routing timing prediction task that is directly related to evaluating post-routing layout quality.\nTiming is directly correlated with the chip's performance.  The results are presented below.\n| Model     | 5| 5|5     | 10|10|10 | 20    |20    |20    |\n|--|--|----|--|--|---|---|--|-|---|\n|   | Pearsonr   | R2      | MAE    | Pearsonr   | R2      | MAE     | Pearsonr   | R2      | MAE     |\n| timergcn  | 0.4269     | 0.1434  | 0.1391 | 0.4432     | 0.1647  | 0.1382  | 0.5421     | 0.2598  | 0.1285  |\n| DeepLayout| 0.7644     | 0.5046  | 0.0970 | 0.7974     | 0.5893  | 0.0877  | 0.8101     | 0.5933  | 0.0833  |\n\nArea prediction is unnecessary since post-routing layout area remains nearly unchanged from placement, allowing direct calculation.\nThe current public datasets we employ lack power-related labels and critical information such as input vectors or toggle rates. We therefore designate power prediction as a primary downstream task for our future work.\n\nQ2:\nLine 92, \"Therefore\"\nAlgorithm 1, line 13, should the index i be involved?\n\nA2：\nWe appreciate your identification of this typo in the manuscript. additionally, in  Line 12, \"i\" should be corrected to \"vi,\" and in  Line 13, \"vk\" should be updated to \"vi.\" These corrections will be reflected in the final version of the paper.\n\nQ3\n\"A 50% mask ratio ... for this?\"\n\nA3:\nWe hypothesize that this difference arises due to both the nature of circuit data and our specialized masking strategy:\nFrom the data aspect, Images tend to exhibit a high level of information redundancy, while circuits contain rich information among sub-circuits, which is not easy to restore from the neighbour.\nFrom the pre-training method aspect, DeepLayout implements mask nodes within selected grid cells, where each grid size is significantly smaller than the image patches (e.g., 16×16 in MAE). Meanwhile, each grid contains multiple graph nodes, different from the individual node mask style of graph SSL.\nThus, the optimal 50% mask ratio emerges as an intermediate value between these two modalities. Due to character limitations, I had to shorten the content. If you have other questions, we can discuss them below.\n\nQ4\n\"I'm wondering ... networks used.\"\nA4\nAblation study of encoder modules\nCongestion prediction\n\n| Method   | 5 | 5 | 5 | 5 | 10 | 10 | 10 | 10 | 20 | 20 | 20 | 20 |\n|---|---|---|---|--|--|--|--|--|---|--|--|--|\n|  | Pearsonr  | MAE | RMSE      | SSIM      | Pearsonr   | MAE        | RMSE       | SSIM       | Pearsonr   | MAE        | RMSE       | SSIM  |\n| train from scratch | 0.1154  | 0.0508    | 0.0874 | 0.1428 | 0.3047 | 0.0289 | 0.0423  | 0.2560 | 0.3398 | 0.0225 | 0.0386  | 0.4513 |\n| wo/ MSGA  | 0.4142 | 0.0288   | 0.0684    | 0.7152    | 0.4271 | 0.0135 | 0.0363  | 0.7755 | 0.4391 | 0.0132 | 0.0356  | 0.7777  |\n| wo/ HGNN   | 0.4138    | 0.0143 | 0.0376    | 0.7670    | 0.4298  | 0.0324  | 0.0728  | 0.7048| 0.4240 | 0.0335  | 0.0756 | 0.6996 |\n| DeepLayout  | 0.4270 | 0.0146 | 0.0379   | 0.7718  | 0.4383  | 0.0130  | 0.0360  | 0.7820 | 0.4418  | 0.0121  | 0.0349 | 0.7909  |\n\nPost-routing net length prediction\n\n|Method|5|5|5|10|10|10|20|20|20|\n|------|---------|---------|---------|----|--|--|-|----|---|\n|   |Pearsonr|MAE      |RMSE     |Pearsonr  |MAE       |RMSE      |Pearsonr  |MAE       |RMSE      |\n|train from scratch|0.3342|0.1332|0.1737|0.3048|0.1330|0.1765|0.3233|0.1313|0.1764|\n|wo/MSGA|0.3634|0.1279|0.1712|0.3743|0.1270|0.1706|0.3848|0.1290|0.1684|\n|wo/HGNN|0.3593|0.1311|0.1705|0.3667|0.1326|0.1701|0.3694|0.1303|0.1698|\n|DeepLayout|0.3704|0.1305|0.1695|0.3806|0.1290|0.1689|0.3961|0.1270|0.1682|\n\nQ5\n\"Robustness. ... performance?\"\nA5\nIn response, we adopted a  50% mask ratio and conducted three repeated pre-training runs, followed by evaluations on two downstream tasks. \nCongestion prediction:\n| Samples   | Pearsonr (Mean ± Std)    | MAE_1D (Mean ± Std)     | RMSE_1D (Mean ± Std)    | SSIM (Mean ± Std)       |\n|----|--|---|--|---|\n| 5 samples | 0.4270 ± 0.0002    | 0.0138 ± 0.0000 | 0.0371 ± 0.0001 | 0.7743 ± 0.0005  |\n| 10 samples| 0.4393 ± 0.0015          | 0.0128 ± 0.0002          | 0.0356 ± 0.0002          | 0.7828 ± 0.0020          |\n| 20 samples| 0.4412 ± 0.0011          | 0.0123 ± 0.0001          | 0.0351 ± 0.0001          | 0.7890 ± 0.0013          |\n\nPost-routing wire length prediction\n| Samples    | Pearsonr (Mean ± Std)  | MAE_1D (Mean ± Std)   | RMSE_1D (Mean ± Std)  |\n|--|---|--|---|\n| 5 samples  | 0.3688 ± 0.0039 | 0.1331 ± 0.0009   | 0.1698 ± 0.0004  |\n| 10 samples | 0.3830 ± 0.0027        | 0.1316 ± 0.0020       | 0.1690 ± 0.0002       |\n| 20 samples | 0.3949 ± 0.0016        | 0.1313 ± 0.0012       | 0.1681 ± 0.0004       |\n\nQ6\nWill the code ... reproduction?\nA6\nWe promise to open-source the DeepLayout code upon paper acceptance.", "claims_and_evidence": "Yes", "methods_and_evaluation_criteria": "Yes", "theoretical_claims": "No theoretical claims are involved.", "experimental_designs_or_analyses": "Yes. The experiments are conducted on public benchmarks and compared with previous methods. Meaningful data is reported.", "relation_to_broader_scientific_literature": "Not applicable.", "essential_references_not_discussed": "No.", "other_strengths_and_weaknesses": "Congestion and wirelength are typical proxies for ultimate metrics of a chip, such as power, performance, and area. Conducting experiments targeting these ultimate metrics may further strength the paper.", "other_comments_or_suggestions": "1. Line 92, \"Therefore\"\n2. Algorithm 1, line 13, should the index i be involved?", "questions_for_authors": "1. A 50% mask ratio leads to the best performance, and not the higher the better. Any analysis or insights for this?\n2. I'm wondering if the performance difference has any potential correlation to the backbone networks used.\n3. Robustness. For a specific mask ratio, if multiple experiments are conducted, what's the variation in the performance?\n4. Will the code be publicly available for reproduction?", "summary_of_paper": "", "summary_of_recommendation": "", "technical_quality": "", "clarity_of_presentation": "", "potential_impact": "", "robotics_focus": "", "quality_of_limitations": "", "questions_for_rebuttal": "", "reasons_to_accept": "", "reasons_to_reject": "", "questions_to_authors": "", "extra_scores": {}}, {"review_id": "hll2LjlmnJ", "reviewer": "Reviewer_xVSW", "summary": "This paper proposes a representation learning framework for backend circuit design by integrating GNNs and spatial transformers to capture both topological connectivity and geometric distribution of circuits. Also the authors propose a self-supervised learning method based on mask-based autoencoder for layout representation to improve sample efficiency. The results show that the proposed method outperformed SOTA methods in congestion and post-routing wire length estimation.", "questions": "", "limitations": "", "rating": 3, "confidence": null, "soundness": null, "presentation": null, "contribution": null, "strengths": "", "weaknesses": "", "quality": null, "clarity": null, "significance": null, "originality": null, "strengths_and_weaknesses": "", "was_revised": false, "final_justification": "", "rebuttal": "Q1\nIt could mention other graph-based learning techniques in EDA beyond CircuitGNN and discuss RL-based methods for backend placement to strengthen the background. if we miss any related papers, please feel free to point out. We will incorporate them in the final version. \n\nA1\nWe sincerely appreciate your valuable suggestions. In the revised manuscript, we will augment the related work section with a discussion of graph-based learning methods in EDA and reinforcement learning techniques for physical backend design. \n\nQ2\nSwap Figure 1 and Figure 2 for better readability.\nTypo in Page 2, line 93: “Therefor” → “Therefore”.\nText and details in Figure 5 are too small to read clearly.\nVisualizations of congestion predictions in Figure 7 are not clear. Please consider improving contrast and resolution.\n\n\nA2\nWe sincerely appreciate your valuable suggestions. We will incorporate these improvements in the final manuscript, including: 1) making the specified revisions to the content; 2) enhancing the clarity of all visualizations.\n\n\nQ3\n\"How does DeepLayout perform on larger circuits with millions of components?\"\n\nA3\nWe sincerely appreciate your valuable suggestion. However, preparing larger circuit design data is extremely time-consuming. As a result, we have not been able to complete all the experiments related to large circuit designs at present. We will make every effort to update the experimental data related to large designs in the following days and discuss them with you.\n\n\n\n\nQ4\n\"What are the computational resource requirements for pretraining DeepLayout?\"\n\nA4\nThe pre-training phase of DeepLayout is performed on an 8 A800 machine, achieving a per-epoch training time of 16 hours. These implementation specifics will be incorporated into the methodology section of our paper. \n\n\n\nQ5\n\"Can DeepLayout generalize to other layout tasks (e.g., DRC prediction, power estimation)?\"\n\nA5\n\nThank you for your valuable suggestions. We have additionally designed post-routing timing prediction task that is directly related to evaluating post-routing layout quality.\n\nPost-Routing Timing Prediction:\nTiming is directly correlated with the chip's performance. The encoder of DeepLayout is initialized with pre-trained weights, while the decoder employs a specially designed graph neural network. We fine-tune the network using regression loss and perform timing prediction after few-shot fine-tuning. Following common practice in related literature, we report widely adopted metrics including Pearsonr, R², and MAE. The results are presented below.\n\n| Model      | 5     |5|5                | 10 |10|10                    | 20|20|20                    |\n|-------|-----|----|-----------|----------------|-------------------------------|------------------|--|--|---------|\n|            | Pearsonr   | R2      | MAE    | Pearsonr   | R2      | MAE     | Pearsonr   | R2      | MAE     |\n| timergcn  | 0.4269     | 0.1434  | 0.1391 | 0.4432     | 0.1647  | 0.1382  | 0.5421     | 0.2598  | 0.1285  |\n| DeepLayout| 0.7644     | 0.5046  | 0.0970 | 0.7974     | 0.5893  | 0.0877  | 0.8101     | 0.5933  | 0.0833  |\n\n\nThese experimental results further demonstrate that our proposed pre-training methodology and network architecture can effectively support downstream tasks for characterizing post-routing layout performance.\nDue to the time-consuming nature of data preparation and network training, we were unable to complete all the experiments related to DRC prediction within the limited number of days. We will make every effort to update the experimental data related to large-scale DRC in the following days and discuss it with you.\nConcerning the power prediction task: The current public datasets we employ lack power-related labels and critical information such as input vectors or toggle rates. We therefore designate power prediction as a primary downstream task for our future work.\n\n\nQ6\n\"Do the authors plan to extend this to full-chip routing prediction?\"\n\nA6\n\nWe acknowledge the reviewer’s question regarding whether our prediction method operates on full-chip designs.  Our approach indeed performs post-routing performance prediction on complete circuit chips. Specifically:\n1.Full-Chip Input Representation: Throughout all stages—pre-training, fine-tuning, and testing—DeepLayout processes  complete circuit graphs that represent the entire chip design.\n2.Post-routing prediction target: In DeepLayout, the labels for all downstream tasks are extracted after the routing process. In other words, the current objective of DeepLayout is to make routing predictions.\nThis distinguishes our work from partial or tile-based prediction approaches, ensuring relevance for real-world chip design optimization.", "claims_and_evidence": "The proposed Deeplayout provides a general representation learning framework for backend circuit design that captures key circuit attributes without requiring task-specific engineering. The proposed masking strategy preserves key geometric and topological circuit characteristics so that it effectively reconstructs the routing prediction. Tables 2 and 3 provide quantitative comparisons showing Deeplayout outperforming SOTA models in congestion and post-routing wirelength estimation.", "methods_and_evaluation_criteria": "The authors evaluated Deeplayout using two downstream tasks, congestion prediction and post-routing wirelength estimation. Also the performance of Deeplayout was compared to four other existing methods.", "theoretical_claims": "The paper modeled the circuits as heterogeneous graphs for general circuit representation adaptable to diverse physical design downstream tasks. The author claims that a masked autoencoder can effectively pre-train circuit layouts, reducing the need for labeled data. The paper also suggests masking strategy and shows that a 50% masking ratio achieves the best trade-off between feature learning and model generalization.", "experimental_designs_or_analyses": "The study uses a large-scale public database of IC designs for real-world industrial applications. The authors carried out performance comparison across baselines, ablation study on mask ratio, and provided both statistical and visualization results.", "relation_to_broader_scientific_literature": "Application-wise, the paper extends prior work on front-end circuit representation learning to backend design. Methodology-wise, it leverages a masked autoencoder, contrastive learning, and graph-based techniques to enhance layout representation.", "essential_references_not_discussed": "It could mention other graph-based learning techniques in EDA beyond CircuitGNN and discuss on RL-based methods for backend placement to strengthen the background.", "other_strengths_and_weaknesses": "Strengths:\n-The paper effectively acknowledges the multi-level dependencies in EDA workflows, considering both upstream and downstream tasks.\n\n-General-purpose representation learning eliminates the reliance on task-specific models, improving flexibility.\n\n-Strong empirical results demonstrate that the proposed method outperforms existing SOTA approaches.\n\n-Well-structured experimental design, with comprehensive benchmarking against multiple baselines.\n\nWeakness:\n-Scalability concerns are not addressed.", "other_comments_or_suggestions": "Swap Figure 1 and Figure 2 for better readability.\n\nTypo inPage 2, line 93: “Therefor” → “Therefore”.\n\nText and details in Figure 5 are too small to read clearly.\n\nVisualizations of congestion predictions in Figure 7 are not clear. Please consider improving contrast and resolution.", "questions_for_authors": "How does DeepLayout perform on larger circuits with millions of components?\n\nWhat are the computational resource requirements for pretraining DeepLayout?\n\nCan DeepLayout generalize to other layout tasks (e.g., DRC prediction, power estimation)?\n\nDo the authors plan to extend this to full-chip routing prediction?", "summary_of_paper": "", "summary_of_recommendation": "", "technical_quality": "", "clarity_of_presentation": "", "potential_impact": "", "robotics_focus": "", "quality_of_limitations": "", "questions_for_rebuttal": "", "reasons_to_accept": "", "reasons_to_reject": "", "questions_to_authors": "", "extra_scores": {}}, {"review_id": "yo6yrZ3D1e", "reviewer": "Reviewer_PTE9", "summary": "This paper presents a method to learn the layout representation of circuit for downstream tasks. The method is based on an graph neural network (GNN) and a mask training strategy.\n\n## update after rebuttal\nI keep my rating since the authors have answered my question, and I still slightly lean toward accept.", "questions": "", "limitations": "", "rating": 3, "confidence": null, "soundness": null, "presentation": null, "contribution": null, "strengths": "", "weaknesses": "", "quality": null, "clarity": null, "significance": null, "originality": null, "strengths_and_weaknesses": "", "was_revised": false, "final_justification": "", "rebuttal": "Q1\n“most of the design in the proposed network seems not novel and exists in network/method for other domains. I personally think this is not critical as long as the method is working well for this specific domain..”\n\nA1\n\nWe appreciate your thoughtful response and the opportunity to address our concerns more comprehensively. As you have rightly pointed out, we have drawn inspiration from the network architectures and self-supervised learning methods in the field of artificial intelligence in designing DeepLayout. However, our direct adaptation of these methodologies to circuit layout representation learning revealed three critical technical challenges:\n\n1） Distinct Graph Structures of Circuit Layouts\n\nAn integrated circuit's graph structure, derived from Verilog netlists, differs from traditional graph learning domains. It incorporates gate-level physical properties during technology mapping (e.g., TSMC N3), layout positions, and routing interconnect details—unlike point clouds or social networks, as shown in the table below:\n\n\n|                | Social Network Graph | Point Cloud | Circuit Graph Structure |\n|----------------|----------------------|-------------|-------------------------|\n| ​**Node Attributes** | Yes                  | No          | Yes (height, width, power) |\n| ​**Geometric Information** | No               | Yes         | Yes (x, y coordinates)   |\n| ​**Edges**       | Yes                  | No          | Yes (length, resistance, capacitance) |\n\n\nTo address this issue, we propose a novel encoder architecture that jointly learns the topological structure and geometric information of the circuit graph structure through the combination of Multi-Scale Graph Attention (MSGA) and Heterogeneous Graph Neural Networks (HGNN). By fully extracting these two types of features, DeepLayout enables comprehensive extraction of topological and spatial features, generating layout representations applicable to routing prediction - a computationally intensive critical phase in circuit design.\n\n2） Limitations of Self-Supervised Learning in Circuit Layouts\n\nSelf-supervised learning in computer vision and graph learning relies on inherent labels for restoration tasks, but this approach has limitations in circuit layout learning. First, circuit graphs have low redundancy, making it hard to restore masked node attributes without extra guidance. Second, layout representation learning aims to predict routing-phase quality, but traditional node-masking methods fail to capture routing characteristics.\n\n|                     | MAE       | GraphMAE2 | DeepLayout                              |\n|---------------------|-----------|-----------|-----------------------------------------|\n| ​**Input**           | Image     | Graph     | Heterogeneous Graph                     |\n| ​**Masking Unit**    | Patch     | Independent Nodes | Set of Nodes in the Grid         |\n| ​**Masking Ratio**   | 75%       | 50%       | 50%                                    |\n| ​**Is there guidance?** | No      | No        | Yes (Topological edges on the graph serve as guidance) |\n| ​**Number of Masks** | Fixed     | Varies with the number of nodes on the graph | Varies with the layout size |\n| ​**Supervisory Signal** | Masked Pixels | Node Attributes | Node Geometric Coordinates + Routing Probability Algorithm (RPA) |\n\n\nTo overcome these challenges, we propose a self-supervised learning approach tailored for circuit layouts. Our key design points include: 1) introducing a grid-based masking strategy, 2) masking only the geometric information of nodes while retaining edge information as guidance for restoration, and 3) designing two distinct supervised tasks. Notably, Supervised task #2 utilizes the easily computable Routing Probability Algorithm (RPA) feature as a supervisory signal to captures essential aspects of the routing process.\n\n3）Downstream Tasks in Circuit Layout Representation Learning\n\nIn graph representation learning, downstream tasks typically involve learning global graph attributes or predicting node classifications, without the need for a specialized decoder. However, downstream tasks in circuit layout learning span multiple levels, from individual nodes to 2D representations.\n\n| ​**Hierarchy** | ​**Downstream Tasks in Graph Learning** | ​**Downstream Tasks in Circuit Graph Learning**       |\n|---------------|----------------------------------------|----------------------------------------------------|\n| ​**Node**      | Node Classification                    | Line length of each net after routing              |\n| ​**Edge**      | Whether an edge exists or not          | Timing prediction after routing                    |\n| ​**Whole**     | Graph Classification                   | Overall power consumption prediction              |\n| ​**2D**        | None                                   | Layout congestion prediction, DRC violation prediction |", "claims_and_evidence": "The reported experiment results support the claim of contribution.", "methods_and_evaluation_criteria": "The overall network and loss seems reasonable to me but not novel in my opinion.\nIt seems borrow some existing method and make it work for circuit design data.", "theoretical_claims": "There is no theoretical claims that requires proofs. Or at least, I believe there is no way to prove the effectiveness or performance of this kind of neural network work.", "experimental_designs_or_analyses": "The experiment seems overall reasonable, and the authors try to perform thorough comparisons.", "relation_to_broader_scientific_literature": "To be honest, since I am not familiar with this community.\nSo even though I think this work will be useful and impactful for a large circuit design community, I am not sure whether this method will be useful or not..", "essential_references_not_discussed": "Not that I know.", "other_strengths_and_weaknesses": "From an outsider (from the circuit design communitiy) point of view:\n\nStrength:\n- if the claim of authors is true, the representation learning will be useful for other downstream tasks just like similar thing happen in other field.\n- the evaluation results suggest that the proposed method outperform existing works.\n\nWeakness:\n- most of the design in the proposed network seems not novel and exists in network/method for other domains. I personally think this is not critical as long as the method is working well for this specific domain..", "other_comments_or_suggestions": "None.", "questions_for_authors": "None.", "summary_of_paper": "", "summary_of_recommendation": "", "technical_quality": "", "clarity_of_presentation": "", "potential_impact": "", "robotics_focus": "", "quality_of_limitations": "", "questions_for_rebuttal": "", "reasons_to_accept": "", "reasons_to_reject": "", "questions_to_authors": "", "extra_scores": {}}, {"review_id": "nt9n7z4qqN", "reviewer": "Reviewer_9pA3", "summary": "This paper proposes a framework to implement pre-training on circuit netlist and physical layout. Two loss functions are designed to realize the pre-training task. And the pre-training network can be applied to downstream tasks, such as wirelength and congestion prediction.\n\n## update after rebuttal\nAfter carefully reviewing the rebuttals and comments, I would like to maintain my current score.", "questions": "", "limitations": "", "rating": 3, "confidence": null, "soundness": null, "presentation": null, "contribution": null, "strengths": "", "weaknesses": "", "quality": null, "clarity": null, "significance": null, "originality": null, "strengths_and_weaknesses": "", "was_revised": false, "final_justification": "", "rebuttal": "Q1\n1.Ablation studies of ... is encouraged.\n2.Ablation studies ... taken.\nA1\nAblation study of encoder modules\nCongestion prediction\n\n| Method   | 5 | 5 | 5 | 5 | 10 | 10 | 10 | 10 | 20 | 20 | 20 | 20 |\n|---|---|---|---|--|--|--|--|--|---|--|--|--|\n|  | Pearsonr  | MAE | RMSE      | SSIM      | Pearsonr   | MAE        | RMSE       | SSIM       | Pearsonr   | MAE        | RMSE       | SSIM  |\n| train from scratch | 0.1154    | 0.0508    | 0.0874    | 0.1428    | 0.3047     | 0.0289     | 0.0423     | 0.2560     | 0.3398     | 0.0225     | 0.0386  | 0.4513 |\n| wo/ MSGA  | 0.4142    | 0.0288    | 0.0684    | 0.7152    | 0.4271     | 0.0135     | 0.0363     | 0.7755     | 0.4391     | 0.0132     | 0.0356     | 0.7777  |\n| wo/ HGNN   | 0.4138    | 0.0143    | 0.0376    | 0.7670    | 0.4298     | 0.0324     | 0.0728     | 0.7048     | 0.4240     | 0.0335     | 0.0756     | 0.6996 |\n| DeepLayout       | 0.4270    | 0.0146    | 0.0379    | 0.7718    | 0.4383     | 0.0130     | 0.0360     | 0.7820     | 0.4418     | 0.0121     | 0.0349     | 0.7909  |\n\nPost-routing wire length prediction\n\n|Method|5|5|5|10|10|10|20|20|20|\n|------|---------|---------|---------|----------|----------|----------|----------|----------|----------|\n|   |Pearsonr|MAE      |RMSE     |Pearsonr  |MAE       |RMSE      |Pearsonr  |MAE       |RMSE      |\n|train from scratch|0.3342|0.1332|0.1737|0.3048|0.1330|0.1765|0.3233|0.1313|0.1764|\n|wo/MSGA|0.3634|0.1279|0.1712|0.3743|0.1270|0.1706|0.3848|0.1290|0.1684|\n|wo/HGNN|0.3593|0.1311|0.1705|0.3667|0.1326|0.1701|0.3694|0.1303|0.1698|\n|DeepLayout|0.3704|0.1305|0.1695|0.3806|0.1290|0.1689|0.3961|0.1270|0.1682|\n\nAblation study of pretrain loss:\nCongestion prediction\n\n| Model  | 5| 5|5|10|10|10| 20 |20 |20 |\n|--|-|-|-|-|-|-|-|-|-|\n|  | Pearsonr | MAE  | RMSE | SSIM | Pearsonr | MAE | RMSE | SSIM   | Pearsonr | MAE  | RMSE   | SSIM   |\n|--|-|--|--|--|--|-|--|--|--|--|--|-|\n| train from scratch | 0.1154  | 0.0508 | 0.0874 | 0.1428 | 0.3047   | 0.0289 | 0.0423 | 0.2560 | 0.3398   | 0.0225 | 0.0386 | 0.4513 |\n| task #1 loss| 0.1507  | 0.0454 | 0.0954 | 0.2020 | 0.3203 | 0.0293 | 0.0440 | 0.2534 | 0.3667  | 0.0235 | 0.0387 | 0.3875 |\n| task #2 loss | 0.4050  | 0.0135 | 0.0368 | 0.7760 | 0.3785  | 0.0183 | 0.0455 | 0.7408 | 0.3755 | 0.0141 | 0.0381 | 0.7673 |\n| DeepLayout   | 0.4270  | 0.0146 | 0.0379 | 0.7718 | 0.4383   | 0.0130 | 0.0360 | 0.7820 | 0.4418  | 0.0121 | 0.0349 | 0.7909 |\n\nPost-routing wire length prediction\n| Model | 5|5| 5 | 10|10|10 | 20 |20|20|\n|-|-|-|-|--|-|--|-|-|-|\n|  | Pearsonr | MAE  | RMSE | Pearsonr | MAE | RMSE | Pearsonr | MAE | RMSE |\n| train from scratch | 0.3342 | 0.1332 | 0.1737 | 0.3048 | 0.1330 | 0.1765 | 0.3233 | 0.1313 | 0.1764 |\n| task #1 loss | 0.2737 | 0.1391 | 0.1837 | 0.2878 | 0.1393 | 0.1841 | 0.3064 | 0.1343 | 0.1808 |\n| task #2 loss | 0.3336 | 0.1373 | 0.1761 | 0.3301 | 0.1365 | 0.1779 | 0.3522 | 0.1321 | 0.1737 |\n| DeepLayout  | 0.3704 | 0.1305 | 0.1695 | 0.3806 | 0.1290 | 0.1689 | 0.3961 | 0.1270 | 0.1682 |\n\nQ2\nx∈W,y∈H ... format?\nA2\nWe will updating the notation to explicitly use range(W) and range(H).\n\nQ3\nFor the pre-training task 1... K in line 266?\nA3\nK denotes the total number of masked cells, where |Iₘ| = K (Algorithm 1, line 6). \n\nQ4\nIf there is an one-to-one ... Eq. 3?\nA4\n'min' indicates the optimization objective to minimize the loss. We will remove this notation from Eq 3 in our paper update.\n\nQ5\nFor the pre-training task ... RPA?\nA5\nAs shown in Figure 5 (bottom left), RPA is computed for each net u covering area (xul,xuh,yul,yuh) using Eq 4 at every point (x,y) within this rectangle. The final layout RPA is obtained by aggregating values from all nets. We will enhance this explanation with additional visual aids in our final paper to improve clarity.\n\nQ6\nIn my personal ... RPA.\nA6\nOur explanation is divided into two parts to address your concerns.\n1. RPA Feature Computation Without Masking:\nInitially, we compute the RPA feature without considering any masking. Utilizing Eq4 and 5, we perform a global routing probability overlay for all nets across the layout. This process generates a two-dimensional (2D) RPA feature map (w x H), which represents the global routing probability distribution across the entire layout. This feature map encapsulates the inherent routing characteristics of the layout, serving as a foundational element for subsequent processing.\n2. Self-Supervised Masked Reconstruction:\nOur objective is to enable the network to reconstruct the routing probabilities of masked grid nodes to their original states before masking. To achieve this, we employ a self-supervised reconstruction loss based on Equation 6. Specifically, our loss function calculates the difference between the predicted routing probabilities of the masked grids and their original routing probabilities prior to masking. This approach aligns with the implementation details of Masked Autoencoders (MAE), ensuring consistency and effectiveness in the reconstruction process.", "claims_and_evidence": "Yes.", "methods_and_evaluation_criteria": "Yes.", "theoretical_claims": "Yes. There are no issues about the correctness of any proofs for theoretical claims.", "experimental_designs_or_analyses": "Yes. There are no issues about the soundness/validity of any experimental designs or analyses.", "relation_to_broader_scientific_literature": "The pre-trained network could be integrated mature commercial EDA tools to accelerate the design process.", "essential_references_not_discussed": "No.", "other_strengths_and_weaknesses": "**Strengths**\n1. The presentation of the paper is good, making the approach easy to follow and understand.\n2. The idea of masking grid in spatial modality and back to cells in graph modality is novel, which is effectively to capture the spatial and graphic (functional) information.\n3. A new supervision signal, the RPA, is proposed to guide the pre-training.\n4. Performance on multiple downstream tasks are better than previous baselines, including the congestion and posted-routed wirelength prediction, making the approach a more universal representation learner.\n\n\n**Weaknesses**\n1. The presentation of the pre-training loss should be polished to make it more formal and clearer.\n2. Ablation studies about the pre-training loss and the proposed heterogeneous GNN architecture + MSGA are not taken.", "other_comments_or_suggestions": "**Typos**\n1. $x \\in W, y \\in H$ below the summation symbol in Eq. 5 is incorrect. Maybe $W$ should be modified to $\\text{range}(W)$ or other format?\n\n\n**Suggestions**\n1. Ablation studies of the effectiveness of each pre-training loss and model architecture are not presented. Analyze their seperate effectiveness is encouraged.", "questions_for_authors": "I have some questions about the calculation of the pre-training loss.\n1. For the pre-training task 1 Cell Coordinate Reconstruction, what is the meaning of K in line 266?\n2. If there is an one-to-one mapping between the ground-truth coordinate of cell and the predicted coordinate of the cell, why the operation `min' is applied in Eq. 3?\n3. For the pre-training task 2 Routing Process Prediction, the definition of $\\text{RPA}(x,y)$ in Eq. 4 is not clear. What is the meaning of $x,y$ in the left hand side (LHS), and which $u$ is involved in the calculation of this RPA?\n4. In my personal understanding, assume the number of masked grids is $N_m$, the number of nets is $n_u$, and the chip size $W,H$, the RPA for all cases should be a 4D tensor with shape $(N_m \\times n_u \\times W \\times H)$, and $\\text{RPA}(i,j,w,h)$ is the RPA: given a specific net $j$, the masked grid $i$ occupies the region $[x_i, y_i] \\times [x_i + d_x, y_i + d_y]$, and for each $(w,h) \\in [x_i, y_i] \\times [x_i + d_x, y_i + d_y]$, the $\\text{RPA}(i,j,w,h)$ can be calculated with Eq. 4. If I misunderstanding the calculation, please give a more clearer and formal definition of the RPA.", "summary_of_paper": "", "summary_of_recommendation": "", "technical_quality": "", "clarity_of_presentation": "", "potential_impact": "", "robotics_focus": "", "quality_of_limitations": "", "questions_for_rebuttal": "", "reasons_to_accept": "", "reasons_to_reject": "", "questions_to_authors": "", "extra_scores": {}}]

Author rebuttal:

Meta-review: This paper proposes DeepLayout, a self-supervised learning framework for circuit layout representation that integrates graph neural networks (GNNs) and a masked autoencoder (MAE) strategy. The method introduces a grid-based masking approach tailored to circuit layouts, combining geometric and topological information through a heterogeneous GNN encoder. It demonstrates strong empirical performance on key downstream tasks—congestion prediction, wirelength estimation, and post-routing timing. By reducing reliance on labeled data and offering a generalizable representation, the work bridges machine learning and electronic design automation (EDA), providing a practical tool for chip design optimization.

Reviewers acknowledged the paper’s strengths but raised concerns about: 1. limited architectural novelty, as the GNN and masking components build on existing techniques; 2. scalability and generalization, with questions about performance on larger circuits (millions of components) and other downstream tasks (e.g., DRC, power estimation); 3. ablation and robustness, as pre-training losses and encoder modules lack ablation studies and the performance variability across masking ratios needs justification. The authors addressed most concerns effectively during the rebuttal phase. Some additional experiments were provided, including post-routing timing prediction, ablation studies, and robustness tests. The masking ratio is justified via circuit-specific redundancy analysis. However, there exist some remaining gaps, such as theoretical insight into masking ratio trade-offs and full-chip routing prediction results.

Overall, this paper presents a practically valuable framework for circuit layout learning, with strong empirical results and thorough rebuttals. After rebuttal, all the reviewers leaned toward acceptance. Thus, I recommend acceptance and highly recommend the authors to revise the paper based on all the reviews.
Decision: Accept (poster)