AnalogGenie-Lite: Enhancing Scalability and Precision in Circuit Topology Discovery through Lightweight Graph Modeling
Authors: Jian Gao
Weidong Cao
Xuan Zhang
Venue: ICML 2025 poster (2025)
Keywords: Graph modeling
Application of Generative Models
Electronic Design Automation
Primary area: applications->chemistry_physics_and_earth_sciences
TL;DR: Lightweight graph modeling for enhancing circuit generative model's scalability and precision

Abstract: The sustainable performance improvements of integrated circuits (ICs) drive the continuous advancement of nearly all transformative technologies. Since its invention, IC performance enhancements have been dominated by scaling the semiconductor technology. Yet, as Moore's law tapers off, a crucial question arises: ***How can we sustain IC performance in the post-Moore era?*** Creating new circuit topologies has emerged as a promising pathway to address this fundamental need. This work proposes AnalogGenie-Lite, a decoder-only transformer that discovers novel analog IC topologies with significantly enhanced scalability and precision via lightweight graph modeling.
AnalogGenie-Lite makes several unique contributions, including concise device-pin representations (i.e., advancing the best prior art from $O\left(n^2\right)$ to $O\left(n\right)$), frequent sub-graph mining, and optimal sequence modeling. Compared to state-of-the-art circuit topology discovery methods, it achieves $5.15\times$ to $71.11\times$ gains in scalability and 23.5\% to 33.6\% improvements in validity. Case studies on other domains' graphs are also provided to show the broader applicability of the proposed graph modeling approach. Source code: https://github.com/xz-group/AnalogGenie-Lite.

Enhancing Scalability and Precision in Circuit Topology Discovery through Lightweight Graph Modeling
Jian Gao
Weidong Cao Xuan Zhang'
Abstract
ered fundamentally by the semiconductor integrated circuits (ICs) technology. The relentless performance improvements of ICs have been the driving force behind the continuous advancement of these innovations and will continue to play a key role in enabling future technological breakthroughs. Historically, remarkable progress in IC performance has been primarily driven by semiconductor process scaling, evolving from 10 pm in the early 1960s to the cutting-edge 2 nm nodes of today and nearly 100000x in performance improvement. This progression laid the foundation for the well-known Moore's law, which predicts that computing power (i.e., CPU perfor- mance) doubles approximately every 18 months a princi- ple that has shaped the trajectory of modern technology. Yet, the end of Moore's 's law is looming (Theis & Wong, 2017) and the continuous performance enhancements of ICs can no longer be expected from technology scaling, a crucial question thus arises: How can we sustain and advance IC performance in the post-Moore era?
The sustainable performance improvements of integrated circuits (ICs) drive the continuous ad- vancement of nearly all transformative technolo- gies. Since its invention, IC performance en- hancements have been dominated by scaling the semiconductor technology. Yet, as Moore's law tapers off, a crucial question arises: How can we sustain IC performance in the post-Moore era? Creating new circuit topologies has emerged promising pathway to address this funda- mental need. This work proposes AnalogGenie- Lite, a decoder-only transformer that discovers novel analog IC topologies with significantly en- hanced scalability and precision via lightweight graph modeling. AnalogGenie- makes several unique contributions, including concise device- pin representations (i.e., advancing the best prior art from O (n²) to O (n)), frequent sub-graph mining, and optimal sequence modeling. Com- pared to oftee-of-the-at circuit topology discov- ery methods, it achieves 5.15x to 71.11x x gains in scalability and 23.5% to 33.6% improvements in validity. Case studies on other domains' graphs are also provided to show the broader applicability of the proposed graph modeling approach. Source code: https:://sstt //t::///gttht////// com/ nom/xz-10 gomn/xzggrop////// Ana mellooGGnie--itee
5000 in dimension reduction
Developing novel circuit topologies, especially for analog ICs, has emerged as a promising pathway to meet this criti- cal challenge (Schuman et al., 2022; Mohseni al., 2022; De Leon et al., 2021). Analog ICs essentially bridge the physical world and cyberspace by dealing with continuous signals and enabling seamless interaction with digital ICs in the cyber domain that handle binary data, Their topologies (i.e., interconnections between different devices) primarily determine the performance, functionality, and efficiency of circuit once a semiconductor process is finalized to implement the circuit, akin to protein structure that dic- tates the generation of amino acids. Yet, unlike their digital counterparts that can be easily synthesized with high-level hardware description languages (c.g.. Verilog and VHDL) or programming languages (e.g.. C) or even multiple gener- ative Al- tools (Blocklove al., 2023; Thakur et al., 2024; Fu et al., 2023; Wu et al., 2024; Liu et al., 2023), analog ICs have relied process. This is mainly due to their inherent complexity, which makes them resistant to the universal and hierarchical abstraction that digital ICs benefit from. Thus, the discov- ery of novel analog circuit topologies has been significantly limited since the invention of ICs and remains critical challenge to be addressed.
1. Introduction
Nearly every transformative technology over the past several decades, ranging from medical devices and 5G communica- tion to generative Al and quantum computing, has been pow-
Deparrment of Electrical and Computer Engineering, North- eastern University, Boston, MA, USA 'Department of Electrical and Computer Engineering, The George Washington University, NW Washington, DC, USA. Correspondence to: Xuan Zhang <xuan aaataang@@ntthhhsteen...t
longstanding handcraft design
Proceedings of the 42nd International Conference Machine Learning, Vancouver, Canada. PMLR 267, 2025. Copyright 2025 by the author(s).

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AnalogGenie-Lite: Enhancing Scalability and Precision in Circuit Topology Discovery through Lightweight Graph Modeling
Generative AI has recently emerged as a promising solution for automating analog circuit topology discovery. To facili- tate the discovery, pioneering methods have explored two typical representations to model analog circuit topologies, i..., text (Lai et al., 2024; Chen et al., 2024) and graph (Dong et al., 2023; Chang et al., 2024; Gao et al., 2025). Text repre- sentation uses PySpice codes or natural language to describe SPICE (Simu-
mains such as protein generation (Jumper et al., 2021) and community detection (Fortunato, 2010). Our key contribu- tions are as follows:
Precise and efficient graph modeling: AnalogGenie- Lite significantly improves the efficiency of graph rep- resentation at the device-pin level for analog circuit topology modeling. It exploits opportunities to elimi- nate redundant device self nodes and simplifies multi- pin shared edge connections, reducing space complex- ity from O (n²) to O (n).
analog circuits, which can be converted lation Program with Integrated Cireuit Emphasis) netlist- a textual high-level description of device connections used for circuit simulation. Graph representation formulates the topology design as a graph/sequence generation task, as cir- cuit topologies of analog ICs can be naturally represented as graph structures. Yet, these representations face significant limitations that must be addressed to enable precise and scal- able discovery of topologies. Text-based representations are prone to errors, as generating even single device con- nection often involves predicting multiple text tokens. Even advanced LLM models such as GPT-4 (Lai et al., 2024) struggle to generate circuits with fewer than 10 devices accurately. While graph- based representations can signifi- cantly mitigate errors by predicting device-pin connections, they still suffer from scalability and accuracy. Specifically, these methods (Dong et al., 2023; Chang et al., 2024; Gao et al., 2025) do not efficiently and precisely model circuit graphs. When leveraging auto-regressive models such as transformers that have a limited context window for circuit graph generation, they are unable to generate circuits at scale and are limited to accuracy due to the error propagation of long-sequent song-equence predictions (Zhu et al., 2022).
Compact subgraph modeling: Analog em- ploys frequent subgraph mining to identify commonly reused subgraphs in the database. It further simplifies these subgraphs by pruning isolated nodes and restruc- turing the remaining non-isolated nodes into a cycle.
Optimal sequence modeling: AnalogGenie- Lite mod- els the graph as shortest closed path that visits every edge of an undirected graph at least once by solving the Chinese Postman Problem (Edmonds & Johnson, 1973). This significantly reduces sequence length com- pared to previous non-optimal methods.
Experimental results show that Analog achieves remarkable generation performance, i.e., 5.15x 71.11x x reduction in average sequence length across the entire database and 23.5% to 33.6% im- provement in validity, compared to the best prior art. Case studies on other domains" graph datasets (e.g.. protein, ego, community, molecule, and 3D point cloud graphs) further showcase the broad applicability and superior scalability of our graph modeling approach.
This work proposes AnalogGenie-Lite a generative engine based on decoder-only transformer for discovering novel analog circuit topologies with enhanced scalability and pre- cision through lightweight graph modeling. Compared to its predecessor (Gao et al., 2025), AnalogGenie-Liin har- nesses a lightweight circuit graph modeling to address the limitations of existing methods. At the graph level, it simpli- fies the cutting-edge device-pin graph representation (Gao et al., 2025) by removing redundant nodes and edges, reduc- ing graph complexity for multi-pin shared edge connection from O (n²) to O (n). At the subgraph level, it employs data mining on a database (Gao et al., 2025) of more than 3000 topologies across tens of circuit types to identify and simplify frequently reused subcircuits, replacing them with compact representations. Finally, it models a circuit graph as a shortest closed path that visits every edge of an undi- rected graph at least once by solving the Chinese Postman Problem (Edmonds & Johnson, 1973) and significantly re- duce sequence length compared to previous non non-optimal methods (Gao et al., 2025). These innovations remarkably enhance the scalability and precision of topology discov- ery. Moreover, this efficient graph modeling method from AnalogGenie-Lite can also be broadly applied to other do-
2. Preliminaries and Related Work
2.1. Analog Circuit Design Flow
The analog circuit design process generally involves three key stages. First, it starts with creating the circuit topology, which entails selecting device types (e.g., transistors and resistors), determining the number of devices, and defining their interconnections. Next, designers carry out device sizing, i.e., optimizing the physical dimensions of the de- vices to achieve specific performance objectives. Finally, the physical layout based on the topology and device di- mension is created for fabrication, which represents ICs as stacked physical layers used in manufacturing. While significant advancements have been made in automating the device sizing ( (Wang et al., 2020; Cao et al., 2022; Gao et al., 2023; Cao et al., 2024) and layout design stages (Ku- nal et al., 2019; Xu et al., 2019), the problem of topology generation remains significantly underexplored due to its ab- stract, complex nature, requiring creativity and human-level intelligence. Our work addresses this challenging problem.
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AnalogGenic-Lite: Enhancing Scalability and Precision in Circuit Topology Discovery through Lightweight Graph Modeling
Circuit Topology
Device Graph
LaMAGIC(Chang al., 2024) fine-tunes masked lan- guage model (MLM) generate fixed-node circuits, achiev- ing high success for simpler designs like power converters (fewer than four devices). AnalogGenie (Gao et al., 2025) uses non-optimal Fulerian circuits to model the graph. This efficient representation avoids encoding non-cxistent edges, enabling scalability to larger circuits (e.g., 63 devices). In this work, AnalogGenie- further advances analog circuit topology generation with lightweight graph modeling.
NMID, NMIG, NM2G share the same net
NHL
NM2
Imprecise modeling since it's unclear which pin an edge connects to
NM1
NM2
(b)
Device Pin Graph
Shared connection
NMID
3. Approach
NNIB
NM1
NMIG
NM2G
NM2
NM28
AnalogGenie-Lite is a domain-speciife generative model tailored to discover novel analog circuit topologies of ver- satile types with exceptional scalability and precision. To achieve this, AnalogGenie-Lite leverages three key innova- tions in its lightweight graph modeling. First, it significantly improves the efficiency of the device-pin graph, which ac- curately represents circuit topologies. By eliminating re- dundant nodes and edges, it simplifies the graph structure, enabling more efficient and precise topology discovery. Sec- ond, AnalogGenie- to identify commonly used subcircuits and introduces cus- tomized tokenizer that incorporates both fundamental device and subcircuit pins. This approach allows for the versatile generation of custom circuits while enabling efficient reuse of existing subcircuits. Third, it models circuit graphs as the shortest closed path visiting all edges at least once by solving the Chinese Postman Problem (Edmonds & Johnson, 1973). This technique significantly reduces sequence length compared non-optimal methods (Gao al., 2025).
Redundant nodes
NM15
NM25
Precise but inefficient modeling (redundant nodes & edges)
(c)
AnalogGenie-Lite Graph
Shared
NM1D
connection
NM2D
employs frequent subgraph mining
NINZG
Device pins cycle
NM15
NM25
Accurate and efficient modeling runing redundant nodes & edges)
(d)
Figure 1. AnalogGenie- Lite's accurate and efficient graph model- ing by pruning redundant nodes and edges from device pin graph.
3.1. Precise and Efficient Graph Modeling
2.2. Existing Analog Circuit Topology Generation
Abstracting the efficient and precise representation of an analog circuit topology is long-standing challenge. Graph representations have recently emerged promising model- ing methodology. Early works (Dong et al., 2023; Lu et al., 2023; Lohn & Colombano, 1999; Mattiussi & Floreano, 2007) rely on high-level graphs to generate circuit topolo- gies, where each node represents a device. Although this approach offers efficient representations, omits essential low-level device details, resulting in ambiguous generation. Consider NMOS transistor (NM) with four pins, i.e., drain (D), gate (G), source (S), and body (B) in Figure la for illustration. Abstracting the entire device as a single node makes it unclear which pin an edge connects to. On the other hand, AnalogGenie (Gao et al., 2025) represents circuits at the pin level, ensuring unique mapping between the graph and circuit topology, where every connection is explicitly represented (Figure Ic). Specifically, it represents the topology of an analog circuit as finite connected undi- rected graph G = (V, E),, where V = (1. .2} is the node set representing each device pin with [V] = n and
Generative Al has demonstrated significant potential in tack- ling topology generation, with early approaches focusing on text-based or graph-based methods. For example, Analog- Coder (Lai et al., 2024) models circuits as Python-style SPICE (PySpice) netlists, using domain-specift, prompt engineering with large language models (LLLMs). While this flexible representation allows diverse and scalable de- signs, its reliance on high-level text introduces challenges in generating valid circuits due to the need for multi-token predictions for each device or connection. Artisan (Chen et al., 2024) avoids this complexity by focusing on topology selection rather than generation. Using natural language to represent topology names, Artisan reuses existing topolo- gies, avoiding the complexity of low-level design. How- ever, this limits its ability to generate novel and custom topologies. Graph-based methods, such as CkIGNN (Dong et al., 2023), use adjacency matrices and a graph variational autoencoder (VAE) to generate topologies for specific ana- log ICs like operational amplifiers (20 devices). Similarly,
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AnalogGenie-Lite: Enhancing Scalability and Precision in Circuit Topology Discovery through Lightweight Graph Modeling
E E V x V is the edge set. Yet, this approach inevitably increases graph complexity by introducing more nodes and edges and does not scale well as the number of devices in circuit grows. AnalogGenie- Lite significantly improves the efficiency and accuracy of this graph modeling by pruning redundant nodes and edges.
Identify Frequent Subgraphs
Circuit dataset
F Frequent subgraphs
9$ pan algorithm
In the device pin-level graph structure (Gao al., 2025), each device is represented by its pins (e.g., NMID, NMIG, NMIS, NM1B) and the device node itself (e.g.. NM1 for an NMOS). The device node pri- marily models situations where device pins are connected to themselves or remain unconnected. However, here reduu- dancy exists, as representing the connection between device pins that belong to the same device is not required. As an ex- ample, the edge NMID + NMIG is redundant with NMID ++ NM2G in device pin graph (Figure lc). Consequently, AnalogGeeie- removes all device itself nodes from the graph and connects device pins nodes as a cycle (Figure Id).
Pruning redundant nodes:
Simplify Frequent Subgraphs
P Pruning isolated nodes
Frequent subgraph
O Isolated nodes o Non-isolated nodes
Figure 2. A simplified diagram illustrates how AnalogCenie-IIie identifies and simplifies frequent subgraphs.
Pruning redundant edges: When n device pins share the same connection (Figure la), the device-pin graph (Gao et al., 2025) represents this case using s(n-1l edges, con- necting every pair of pins explicitly. For example, if three pins (NMID, NMIG, and NM2G) share a connection (Fig- ure Ic), existing work uses three edges: NMID ++ NMIG, NM1D ++ NM2G, and NMIG ++ NM2G. AnalogGenie- Lite simplifies this representation by selecting a single node that does not cause edges overlapping with the device pins cycle and connecting all other nodes to it. Thus, only n - edges are required. In the example, AnalogGenie- se- leets NM2G as the node since selecting NMIG or NMID will result in NMIG ++ NMID edge that overlaps with NM1 device pins cycle. As a result, it uses only two edges: NM1D + NM2G and NMIG <> NM2G to describe the shared connection. This technique remarkably enhances the scalability, as n 1 edges scale linearly compared to the quadratic growth of n(=-1) edges. More examples of this edge pruning method can be found in Appendix A.
employs domain-specific tokenizer to encode and decode sequences. Each token in AnalogGenie- 's tokenizer corresponds to either a device pin (e.g., NMIG, NMID, NMIS, NMIB) or a circuit-level pin for the overall analog topology (e.g., VIN1, VOUTI, VDD, VSS). This approach allows AnalogGemie-Lice to generate topologies at the most fundamental level by predicting the next device pin token. Additionally, AnalogGenie-Lin Lite incorporates special tokens to represent the pins of subgraphs or SG (e.g.. SGI VDD, VGU_VOUT, SGI LtermA, SGI .termB, SGI [tGemC..). These tokens enable the generation of only the outer pins of a subeircuit, omitting inner low-level design details. This sig- nificantly simplifies the graph structure while maintaining the ability to represent hierarchical topologies. Detailed tokenizer table is shown in Table 2 in Appendix A.2.
2
Additionally, existing approaches either construct an ex- tensive design library (i.e., tokenizer table) to significantly simplify the graph structure, which includes numerous in- frequent subcircuits and inefficiently utilizes the design brary's 's space (Gielen & Rutenbar, 2000; Zhao & Zhang, 2022; 2020), or rely solely on heuristic design knowledge to identify frequent subcircuits, which may lead to inac- curacies (Dong et al., 2023). AnalogGenie-Lite on the other hand, employs rigorous data mining on a large ana- log circuit topology database (Gao et al., 2025) comprising over 3000 unique topologies and 11 types of analog cir- cuits to accurately identify the frequent subeircuits that are actively reused within the database (Figure 2). Specifi- cally, AnalogGenie -ite utilizes the gSpan algorithm (Yan & Han, 2002) to mine frequent subgraphs. gSpan discovers frequently connected subgraphs in a graph dataset with- out explicitly generating candidate subgraphs, overcoming the limitations of earlier Apriori-based approaches and sig- nificantly reducing runtime. Once frequent subgraphs are
2
3.2. Compact Subgraph Modeling
Analog circuit topologies naturally exhibit hierarchical structure, combining low-level unique devices essential for novel configurations with high-level subcircuits that are ver- satile and reusable across various circuits. Yet, existing approaches either focus solely on generating analog circuit topologies at the most fundamental device level from scratch (i.e., device pin), resulting in heavyweight sequential struc- tures (Gao et al., 2025), or operate exclusively at the high level (i.e., subcircuit), limiting their versatility to represent diverse topology structures and restricting them to specific circuit types (Dong et al., 2023). AnalogGenie-Lin bridges this gap by enabling the simultaneous exploration of both custom and hierarchical structures. First, LnalogGenie--.ite
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AnalogGenie-Lite. Enhancing Scalability and Precision in Circuit Topology Discovery through Lightweight Graph Modeling
Frequent Subcircuits
Tequent
Simplified Subgraphs
Vdd
16
PM1
PM2
TB
Vout
P
14 nodes and 20 edges
nodes and edges
Vdd
Vb
PHUS
ING
PMTR
HODS
PECK
PM1
PM2
10 nodes and 14 edges
nodes and edges
Figure 3.
Two frequent subgraph examples (over 25% appearing frequency in the dataset and over 50% of nodes within subgraphs isolated) that AnalogGenie- selects to identify and simplify (red: isolated nodes; blue: non-isolated nodes).
identified, AnalogGenie- Lite classifies the nodes within sub- graphs as isolated nodes (nodes connected only to other nodes within the subgraph) or non-isolated nodes (nodes also connected to the rest of the graph) based on their de- gree. To simplify the frequent subgraphs, AnalogGenie- prunes the isolated nodes and their edges (Figure 2). Next, connects the remaining non-isolated nodes cycle and replaces the original subgraph within the graph to simplify its structure. The non-isolated nodes are renamed sub- graph pin names (e.g., SG1. VDD, SGI_VGGI SGI_ttrmn _termA, etc) and added to the tokenizer table. AnalogGenie-Litt simplifies subgraphs only if the number of isolated nodes exceeds certain threshold, balancing lightweight graph structures with the overhead in the tokenizer table. Figure 3 presents examples of AnalogGenie-Lite mined subgraphs with a large number of isolated nodes. Excitingly, these structures differ significantly from those used in previous work (Zhao & Zhang, 2022: 2020) based on human heuris- tics, underscoring the necessity of rigorous data mining.
Eulerizing a Graph (Early Work)
Eulerizing a Graph (AnalogG enie-Liee
KIH
61N
MILD
Early work Eulerian circuit (23 tokens)
('Vss' 'NMIS' 'NMIG' 'vin' 'NM1G' 'NM1D' 'Vout" 'RIN' 'RIP' 'Vdd' 'R1P' 'RIN" 'Vout' 'NM1D' 'NM1B' 'Vss' 'NM18' 'NM1S' 'NM18' 'NM1D' 'NM1G" 'NM1S' VVss']
AnalogGenie-Lit Eulerian circuit (18 tokens)
'NM15' 'Vin' 'NM1G' 'Vout" 'R1P" 'Vdd'
3.3. Optimal Sequence Modeling
'RIP"RIN' "Vout" 'NM1D' 'NM1B' 'NM1S' 'NM1B' VVs'']
Harnessing efficient data structure model the circuit graph is the last key innovation of AnalogGenie-LLite mod- cling method, Previous work (Dong et al., 2023; Lu et al., 2023) uses adjacency matrices to represent circuit graphs. However, an adjacency matrix requires
Figure 4. Comparison between early work (Gao et al., 2025) and AnalogGenie- Eulcrizing method (red: odd degree nodes in the original undirected graph; blue: non-duplicated edges).
(n²) space to store nodes, regardless of the number of edges, which is inefficient for sparse graphs. Analog circuit topologies are typically sparse, as most devices connect only their ad- jacent neighbors. In contrast, AnalogGenie-LLite optimally
represents the circuit graph the shortest closed path that visits every edge of finite connected undirected graph at least once by solving the Chinese Postman Problem.
Definition 3.1 (Chinese postman problem, (Edmonds
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AnalogGenie-Lite: Enhancing Scalability and Precision in Circuit Topology Discovery through Lightweight Graph Modeling
Johnson, 1973)). Chinese postman problem is combina- torial optimization problem that tries to find the shortest circuit that visits every edge of finite connected undirected graph at least once.
Algorithm 1 Chinese Postman Algorithm
Require: A weighted, undirected graph G = (V,
1: Step 1: Identify odd-degree vertices
odd vertices <- {u V degree(u) mod 2 * 0}
Step 2: Pair up odd-degree vertices to minimize cost
When a graph contains an Eulerian circuit, that eircuit rep- resents the optimal solution.
4: CompleteGraph < Construct complete graph where vertices are the odd-degree vertices, and edge weights are the shortest path distances between each pair of odd-degree vertices in the original graph.
Definition 3.2 (Fulerian circuit, (Biggs et al., 1986).. Eu- lerian circuit is a graph trail that visits every edge exactly once and starts and ends at the same node.
5: pairs <- Solve the minimum weight perfect matching problem on CompleteGrraph using the Blossom algo- rithm (Edmonds, 1965).
However, not all finite connected undirected graphs contain Eulerian circuit unless all of their nodes have even degree. Definition 3.3 (Eulerian graph, (Biggs et al., 1986)). If all the nodes in a finite connected undirected graph have even degree, the graph is Eulerian and contains at least one Eulerian circuit.
6: Step 3: Duplicate edges to make degrees even
7: for each pair (u, v) E pairs do
8: path <- ShortestPath(u, v, G) using Dijkstra algo- rithm (Dijkstra, 2022)
9: for each edge (I, y) E path do
10: Add duplicate edge (z,y) to
Thus, the optimization problem for non-Eulerian graph is to find the smallest number of graph edges to duplicate so that the resulting multigraph does have an Eulerian cir- cuit (Roberts & Tesman, 2024). As shown in Figure 4, existing non-optimal method (Gao et al., 2025) duplicates all the existing edges in a finite connected undirected graph to ensure the graph to be Eulerian by replacing each undi- rected edge {u, e} E E with two directed ares (u, v) and (v, u) (i.e., traverse all the undirected edge exactly twice). This causes a large overhead in its sequence representation since not all the edges need to be duplicated to make the graph Eulerian. On the other hand, AnalogGenie- finds the optimal sequence by employing Algorithm (Mei-Ko, 1962; Edmonds & Johnson, 1973) to Fulerize the undirected graph. Since the topology graph G = EV) consists of unweighted edges and Algorithml I requires a weighted undi- rected graph, we assign a weight of 1 to all edges in G. The algorithm begins by identifying vertices with odd degrees. then pairs the odd-degree vertices in a way that minimizes the total cost of connecting them, leveraging a shortest-pane -ath strategy. Finally, it duplicates the edges along these short- est paths to ensure all vertices have even degrees, thereby Eulerizing the graph. Through this process, AnalogGenie- Lite minimizes the duplication of existing edges, efficiently transforming the graph into an Eulerian circuit.
11: end for
12: end for
Training setup: During pretraining, Analog split the data into train and validation sets with a 9 to ratio. It augments the dataset by generating multiple unique Fu- lerian circuits per topology. It uses decoder-only trans- former with 6 layers, 6 attention heads, and 11.825 million parameters, with a vocabulary size of 1029 and maxi- mum sequence length of 1024. For performance evaluation, AnalogGenie-Lite leverages reinforcement learning with hu- man feedback (Ouyang et al., 2022) to target specific types of analog circuits optimized for given performance metrics.
Baseline: We select AnalogCoder (Lai al., 2024) and Artisan (Chen et al., 2024) as the representative of text gen- eration work. Then, we select CkIGNN (Dong et al., 2023), LaMAGIC (Chang et al., 2024), and AnalogGenie (Gao et al., 2025) as the representative of graph generation work. The differences between these methods and AnalogGenie- Lite are discussed in Section We follow original work to produce their results.
Evaluation tasks and metries: We evaluate the generative quality of each method using the following metrics: (I) Validity: An unsized circuit is considered valid if it can be simulated in SPICE without errors (e.g.. floating or shorted nodes). Each method generates 1,000 topologies, and we report the percentage of valid designs.
4. Results
4.1. Experiment Setup
The AnalogGenie-LLin Lite uses a dataset (Gao et al., 2025) that comprises 3350 unique and real-world topologies across 11 types: Op-Amps, LDOs, Bandgap references, Comparators, PLLs, LNAs, PAs. Mixers, VCOs, Power converters, and SC Samplers from public resources (Razavi, 2000; Razavi & Behzad, 2012; Johns & Martin, 2008; Gray et al., 2009; Allen & Holberg, 2011; Camenzind, 2005).
Datasets:
(2) Scalability: The largest valid circuit generated by each model, based on the number of devices. (3) Versatility: The versatility of model is determined by
the number of distinct analog circuit types it generates. (4) Novelty: To evaluate novelty, each method generates 1,000 topologies, and we measure the percentage of these that differ from those in the dataset. Topology differences
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AnalogGenie-Lite: Enhancing Scalability and Precision in Circuit Topology Discovery through Lightweight Graph Modeling
10
Adjacency matrix
Analo sequence
AnalogGerie Lite sequence(Graph)
70
Sequence langth (# tokens)
AnsiogGenie-LLte sequencae(rapph-Suuuggggnnh
AnalogGenne-Lite sejencaiCipp--uxxpppn----uuuueee
Mean conpresiion ratio
80
10"
40
10
30
20
10
10
1000
2000
3000
Melhods
Graph ID
Figure 5. Comparison between adjacency matrix (Dong et al., 2023; Lu et al., 2023), AnanlogGenic (Gao et al., 2025) sequence, and AnanlogGenie-I Lite sequence for representing each topology graph within the dataset in terms of sequence length (left) and mean compression ratio (right). We flatten adjacency matrices to sequences for comparison.
are quantified by converting the circuits into graphs and computing the maximum mean discrepancy (MMD) (Guo & Zhao, 2022) between these generated graphs and real- world graphs derived from the dataset.
2.91 x over AnalogGenie. The AnalogGenie-Litt sequence (Graph+Subgraph) further prunes isolated nodes and edges within subgraphs. improving compression to 49.91 and 3.61 over the respective baselines. However, the compres- sion benefit varies across circuits as shown in Figure 5, par- ticularly for those with unique structures (e.g., PA circuits), emphasizing the need for flexible generation approach ca- pable of predicting both device pins and subcircuits. Finally, (Graph-Subgraph--Seeemm
(5) Performance: Each generated topology is sized using genetic algorithm, and the resulting figure-of-meri (FoM) considering all major metrics (c.g., gain, bandwidth, and power for operational amplifiers) - is used as a compre- hensive performance indicator: We compare the best FoM achieved by circuits generated from each model.
integrates all optimizations, solving the Chinese Postman Problem for optimal Eulerian circuit representation. This method achieves a 71.11x compression over adjacency matrices and 5.15 x over AnalogGenie. These results demonstrate that AnalogGenie- offers scalable and precise repre- sentation, crucial for robust circuit topology discovery.
AnalogGenie-
4.2. Evaluating the Compression Rate
We begin by evaluating AnalogGenie-Lite lightweight graph modeling in terms of mean compression ratio for rep- resenting circuit topology. Figure 5 compares the sequence length required to encode each topology using AnalogGenie- Lite, the adjacency matrix baseline (Dong et al., 2023; Lu et al., 2023), and the state-of-thh-art sequeeee representation, AnalogGenic (Gao et al., 2025). The adjacency matrix ap- proach, based on the device- graph (Gao al., 2025), re- sults in sequences of approximately 1 to 10 tokens due its (nr²) space complexity, making it impractical for train- ing with typical LLMs (Radford et al., 2019; Brown al., 2020; Achiam et al., 2023). AnalogGenie mitigates this issue by encoding graphs as non-optimal Fulerian circuits, reducing sequence length by 13.81x to around 10 tokens. However, it still struggles with large circuits exceeding 100 devices, where sequences reach 10 tokens. To enhance scalability, AnalogGenie-Lite employs graph modeling strategy. The AnalogGenie-Lite (Graph) method prunes redundant nodes and edges while main- taining the non-optimal Eulerian representation, improv- ing compression by 40.28x over adjacency matrices and
4.3. Evaluating the Generation Quality
Then, we evaluate LanalogGenie--itte generation quality by comparing to prior methods, as shown in Table
Validity: AnalogGenie-Linn achieves 97% validity, signif- icantly surpassing prior methods. AnalogCoder generates only 63.4% valid circuits due to errors in code genera- tion, while CkiGNN, LaMAGIC, and AnalogGenie achieve 66.3%, 72%, and 73.5% validity, respectively, using graph- based techniques. Artisan, focused on topology selection, reaches 82% validity but cannot generate novel circuits. In contrast, AnalogGenie-Lite lightweight graph modeling mitigates error propagation, achieving 23.5% to 33.6% improvement over previous methods while generating 99% novel circuits.
efficient
Scalability: AnalogGenie-Lite achieves unmatched scala- bility. CktGNN and LaMAGIC, limited by quadratic costs

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AnalogGenie-Lite:
Enhancing Scalability and Precision in Circuit Topology Discovery through Lightweight Graph Modeling
Table I. Performance comparison between AnalogCenic--Lite Lite and existing analog circuit topology generation work.
Novelty
FoM
Evaluation metric
Validity (%)
Scalability
Versatility
Difl circuit (8)
MMD
Op-Amp
Power converter
AnalogCoder (lai et al., 2024)
63.4
10
7
0
233.4
N/A
AnalogGenic (Gao et al, 2025)
73.5
11
98.8
0.0532
13744.8
3.3
Artisan (Chen et al., 2024)
12769.5
N/A
CRIGNN (Dong
2023)
943.2
N/A
LaMaGiC(Chang al., 2024)
3
0.001
N/A
2.7
AnalogGenie-Iee Lite (Graph)
80.1
183
II
99.7
0,0498
14727.3
3,71
AnalogGenic- Lite (Graph--Subgraph)
87.3
227
11
99 .8
0.0467
14767.5
3,76
AnalogGemie-Lan (Graph--Sulggrapp:-Squeee
99.8
0.0408
15017.7
4.02
of adjacency matrix representations, handle circuits with up to and 22 devices, respectively. AnalogCoder and Ar- tisan, constrained by prompt templates, generate circuits with maximum of 10 and 18 devices. AnalogGenie im- proves scalability 63 devices with efficient sequence representation. AnalogGenie-Lice leveraging a lightweight representation, extends this further to 324 devices, achieving a 5.15x to 71.11x x improvement over prior methods.
Analog circuit 3350 graphs f3=133
Protein 918 graphs ri=258
Ego 757 graphs 14=145
AnalogGenie-Litt surpasses Artisan, CkIGNN, and LaMAGIC, which are restricted to designing only sin- gle circuit type. AnalogCoder, while supporting seven types, is limited by synthesis library containing 20 topologies.
Versatility:
Community 500 graphs 7-
Molecule 133865 graphs 7=18
Novelty: AnalogGenie-Lite outperforms other methods in discovering novel circuits. AnalogCoder and Artisan primar- ily reuse existing topologies or subblocks, while LaMAGIC restricted to small design space, significantly limiting its ability to explore new topologies. Although both Ckt- GNN and AnalogGenie-Lite support the generation of larger circuits, CktGNN is trained synthetic datasets that lack critical real-world features. AnalogGenie-LLin trained on real-world circuit, improves the MMD metric by over 7.67x and generates approximately 99% novel circuits. Compared to AnalogGenie, AnalogGenie-Linn produces more realistic circuits with lower MMD values due lightweight graph modeling, which eliminates redundant edges and nodes and lets the model focus generating essential components.
3D paint cloud graphs 7=1377
500
1000
1500
2000
Moan runtime (seconds)
Figure 6. Runtime of Algorithml on processing circuit (Gao al., 2025). protein (Dobson & Doig, 2003), ego (Sen et al., 2008), community (ERD & Renyi, 1959), molecule (Ramakrishnan al., 2014), and 3D point cloud (Ncumann et al., 2013) graph datasets.
4.4. Evaluating the Computation Cost
We begin by conducting detailed theoretical analysis of Algorithm I's time complexity for solving the Chinese post- problem (CPP). As noted in (Grötschel & Yuan, 2012), approach reduces CPP to matching problem, which can be solved in polynomial time. In particular, Theorem 12. 10 in Section 12.2 (page 307) of (Korte et al., 201 1) shows that the minimum weight perfect matching problem can solved in O (m=)), where n is the number nodes.
Performance: In op-amp design, AnalogCoder achieves low FoM of 233.4 due to limited design options, while Ckt- GNN performs better at 943.2 by selecting optimized subeir- cuits. Artisan achieves an even higher FoM of 12769.5 by selecting state-of-the- -ftte--rt designs. AnalogGenie and AnalogGenie-LLiee by pretraining diverse circuit topolo- gies, discover unseen topologies with superior FoM values of 13744.8 and 15017.7, respectively, outperforming ded- icated synthesizers. AnalogGenie-Licc 's advantage comes from its lightweight graph representation, eliminating re- dundant circuit details while focusing on learning essential components. A similar trend is seen in power converter design, where AnalogGenie-Lite achieves an FoM of 4.02, surpassing AnalogGenie (3.3) and LaMAGIC (2.7).
Next, we empirically evaluate the computational cost of Algorithm 1. Our experiments were conducted on PC equipped with 16-core 19-1290 3.20 GHz CPU and 32 GB of RAM. Figure 6 shows the mean runtime results for total of 5 runs on diverse graph datasets. Our Python pro- gram for Algorithm requires at most 29 minutes and 4.36 seconds on average to preprocess the entire dataset. Impor- tantly, this preprocessing step is performed only once during
8

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AnalogGenie-Lite: Enhancing Scalability and Precision in Circuit Topology Discovery through Lightweight Graph Modeling
10
Adjacency matrix
Adjacency vector
Recursive binary tree
Mean compression ratio
Graph token sequence
Chinese postman sequence
10"
10
10
Protein
Ego
Community
Molecule
3D point cloud
Figure 7. Comparison between adjacency matrix, adjacency vector (You et al.. 2018b), recursive binary tree (Dai et al., 2020), graph token sequence (Chen et al., 2025) our Chinese postman sequence protein (Dobson Doig, 2003), ego (Sen et al., 2008), community (ERD& & Renyi, 1959), molecule (Ramakrishnan et al., 2014), and 3D point cloud (Neumann al., 2013) graphs.
training. This one-time cost is justified by the substantial benefits in compression and scalability that our approach offers.
the number of edges.
Graph token sequence (Chen et al., 2025): In this approach, the sequence consists of two parts. The first part is tuple to represent all the nodes' definitions in the graph (e.g., its type and unique index), followed by special token marking the transition to the edge definition. In the second part, each edge is then encoded as triple containing the source node index, the destination node index, and the type. The space complexity
4.5. Cross-Domain Case Study
Finally, beyond circuits, we believe that AnalogGenie's s lightweight graph modeling can also be applied to other domains, such as protein generation (Jumper et al., 2021), personalized recommendation (Epasto al., 2015), com- munity detection (Fortunato, 2010), drug discovery (You et al., 201 8a), and 3D) object recognition (Shi & Rajkumar, 2020) that can also be represented as graphs. To demon- strate its general applicability, we conduct a case study on protein (Dobson & Doig, 2003), ego (Sen et al., 2008), com- munity (ERD & Renyi, 1959), molecule (Ramakrishnan al., 2014), and 3D point cloud (Neumann al., 2013) graphs. Besides the basic adjacency matrix, evaluate AnalogGenie-Lite Chinese postman sequence by compar- ing it with the following graph data structures that have been developed recent years.
is (n + m).
As illustrated in Figure AnalogGenie- Lite's Chinese Postman sequence achieves compression ratios of 9.33 to 572.56x over adjacency matrices and 2.61 to 3.61x over the strongest prior-art approach (graph token se- quences). By definition, the Chinese Postman sequence is the shortest closed path that traverses every edge of an undirected graph at least once, resulting in a linear space complexity of O (m). These results confirm that sparse graphs-3D 3D point clouds, ego networks, and protein interac- tion graphs-satist m << n² and compress exceptionally well, while denser graphs (community and molecular) with m closer to n² remain more challenging.
Adjacency vector (You et al., 2018b): For a given node ordering n, each node (1x) (except the first) is encoded via adjacency vector S. that captures its connections to all previously added nodes. Without ordering constraints, the length of these vectors grows linearly (e.g. the first node has no vector, the second one entry, the third two entries, etc.), resulting in an overall space complexity of (n?).
5. Conclusion and Future Work
This work presents AnalogGenie-Lite a decoder-only trans- former model for discovering novel analog IC topologies with enhanced scalability and precision through lightweight graph modeling. While it sets new standard in circuit topology discovery, several challenges remain. Key issues include efficiently mining representative subgraphs from di- verse datasets and further improving the compression while preserving essential features for effective model learning.
Recursive binary tree (Dai et al., 2020): This method uses binary tree-structured conditioning on the matrix's 's and columns reduce the complexity from O (n²) to O((n + m) log n),, where is the number of nodes and

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AnalogGenie-Lite: Enhancing Scalability and Precision in Circuit Topology Discovery through Lightweight Graph Modeling
Acknowledgements
Chen, Z., Huang, J., Liu, Y., Yang, F., Shang, L., Zhou, D., and Zeng, X. Artisan: Automated operational ampli- fier design via domain-specific large language model. In Proceedings of the 6lst ACM/IEEE Design Automation Conference, DAC '24, New York, NY, USA, 2024. Asso- ciation for Computing Machinery. ISBN 9798400706011. doi: 10. 145/3344332 URL https: //doi. org 10
This work was partially supported by NSF Award #2526432.
Impact Statement
"This paper presents work whose goal is to advance the field of Machine Learning. There are many potential societal consequences of our work, none which we feel must be specifically highlighted here."
Dai, H., Nazi, A., Li. Y.. Dai, B., and Schuurmans, D. Scalable deep generative modeling for sparse graphs. In International conference on machine learning, pp. 2302- 2312. PMLR, 2020.
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AnalogGenic-Lite: Enhancing Scalability and Precision in Circuit Topology Discovery through Lightweight Graph Modeling
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A. Appendix
A.1. More Details about Redundant Edges Pruning
As shown in Figure 8a, a total of seven pins- PMIB, PM2S, PM2B, PM3S, PM3B, and Vdd share the same net within the topology. The device-pin graph (Gao et al.,
Theis, T. N. and Wong, H.-S. P. The end of moore's law: A new beginning for information technology. Computing in science & engineering, 19(2):41-55) 2017.
2025) connects each pair of these pins directly, forming
fully connected subgraph that requires [x(T-1] 21 edges to represent the shared net. In contrast, AnalogGenie-Liit selects Vdd and connects the remaining pins directly to it. This avoids overlapping device-pin cycles, effectively pruning redundant edges and reducing the edge count to just 7 1 = 6, achieving a 3.5x reduction in edges compared to the device-pin graph.
2
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Circuit Topology
PM1S, PMIB, PM25, PM2B, P PM3S, PM3B, Vdd share the same net
Vdd
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1
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PM2
B
D
G
P
PM3
Vout
D
(a)
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Device Pin Graph
21 edges used describe the shared net
VM
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Zhao, Z. and Zhang, L. An automated topology synthesis framework for analog integrated circuits. IEEE Transac- tions on Computer-Aided Design of Integrated Circuits and Systems, 39 (9(1)):33254433 43377, 2020.
(b)
AnalogGenie-Lite Graph
edges used to describe the shared net
Zhao, Z. and Zhang, L. Analog integrated circuit topology synthesis with deep reinforcement learning. IEEE Trans- actions on Computer-Aided Design of Integrated Circuits and Systems, 41(12):5138-511 2022.
PMOS
FNER
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Vest
(c)
Figure 8. An example of circuit topology, device-pin graph (Gao ct al., 2025), and AnalogGenie-Lite graph.
12

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AnalogGenie-Lite: Enhancing Scalability and Precision in Circuit Topology Discovery through Lightweight Graph Modeling
A.2. Tokenizer Lookup Table
Table 2 presents the tokenizer table used by AnalogGenie- Lite for its versatile generation scheme, which predicts the next device, subcireuit, circuit pin. The token indices are structured as follows: indices 0 to 549 represent basic device pins, covering NMOS, PMOS, NPN, PNP, resistors, capacitors, inductors, and diodes. Indices 550 to 890 corre- spond to subcircuit pins, including mined subgraphs, XOR gates, inverters, transmission gates, etc. Lastly, indices 891 1027 define circuit pins such VIN, IIN, VTRACK, VDD, VSS, etc. The TRUNCATE token (index 1028) is used to pad sequences to uniform length for training.
Table Tokenizer look-up table with basic devices, subcircuits,
and circuit pins.
Device
Index
Device
Index
Device
Index
NMID
0
NMIG
NMIS
2
NMIB
3
NM2D
4
NM25B
99
PMID
100
PMIG
101
PMIS
102
PMIB
103
PM2D
104
PM25B
199
NPNIC
200
NPNIB
201
NPNIE
202
NPN2C
203
NPN25B
274
PNPIC
275
PNPIB
276
PNPIE
277
PNP2C
278
PNP25R
349
RIP
350
RIN
351
R2P
352
R25N
399
CIP
400
CIN
C2P
402
C25N
449
LIP
450
451
452
L25N
499
DIO1P
500
DIOIN
501
DIO2P
502
DIO25N
549
SGIVDD
550
SGIVOUT
551
SGITA
552
SGITB
553
SGITC
554
SGITD
555
SGITE
556
SG2VDD
557
XORIA
726
XORIB
727
XORIVDD
728
VORIVSS
729
XORIY
730
XORSY
750
INVIA
751
INVIQ
752
INVIVDD
753
INVIVSS
754
INV2A
755
INVIS
790
TGIA
791
TGIB
792
TGIC
TGIVDD
794
TGIYSS
795
TG2A
796
TG20VSS
890
VINI
VIN2
892
VIN3
893
VIN4
894
VINS
895
896
IN2
897
VTRACKI
1024
VTRACK2
1025
VDD
1026
VSS
1027
TRUNCATE
1028
13


Reviews:
[{"review_id": "YlzbPFaKH0", "reviewer": "Reviewer_9Exr", "summary": "This paper addresses the challenge of sustaining integrated circuit (IC) performance in the post-Moore era by proposing AnalogGenie-Lite, a decoder-only generative model for discovering novel analog circuit topologies. Leveraging lightweight graph modeling, the framework incorporates concise device-pin representations, frequent sub-graph mining, and optimal sequence modeling to significantly enhance both scalability and precision.", "questions": "", "limitations": "", "rating": 3, "confidence": null, "soundness": null, "presentation": null, "contribution": null, "strengths": "", "weaknesses": "", "quality": null, "clarity": null, "significance": null, "originality": null, "strengths_and_weaknesses": "", "was_revised": false, "final_justification": "", "rebuttal": "> **Q1:** Compared to the original AnalogGenie work, the innovation appears incremental. Although the improved scalability is promising, the performance gains also seem relatively modest in scope.\n\nWe appreciate the reviewer’s insightful comments and would like to elaborate on our innovations in this paper. **Our approach is novel on three levels—graph, subgraph, and sequence—and each contributes significantly to improving circuit generation quality in terms of validity, scalability, and performance**.\n\nAt the graph level, we introduce **a new graph representation that is considerably simpler than the current SOTA device-pin graph representation [1]**. Specifically, for multi-pin shared edge connections, our method achieves a space complexity of $O\\left(n\\right)$, compared to the $O\\left(n^2\\right)$ required by existing approaches. This advancement results in a 6.6% improvement in generation validity, a scalability boost of 2.9$\\times$, and a performance (FoM) increase of 982.5 compared to the current SOTA [1].\n\nAt the subgraph level, **we are the first, to our knowledge, to apply frequent subgraph mining techniques to an analog circuit database to identify frequently reused subcircuits and replace them with compact representations.** This novel contribution leads to an additional 7.2% improvement in generation validity, enhances scalability by 1.24$\\times$, and increases performance (FoM) by 40.2 on top of the improvements achieved at the graph level.\n\nAt the sequence level, we model a circuit graph as an **optimal sequence** by formulating it as the shortest closed path that visits every edge of an undirected graph at least once, effectively **solving the *Chinese Postman Problem* [2].** This approach significantly reduces sequence length and further improves generation validity by 9.7%, scalability by 1.43$\\times$, and performance (FoM) by 250.2 relative to the subgraph-level method.\n\nFinally, we clarify that **our method's performance improvements are significant by comparing it to the historical development of electronic design automation algorithms for analog circuits' topology discovery**. For instance, while op-amp circuits have been extensively studied by existing EDA algorithms [3-6], **early works such as Artisan [3] achieved an 1847.7 FoM gain** using LLM-based op-amp synthesis over traditional reinforcement learning methods [4]. On top of that, the current SOTA [1] further secures an additional **975.3 FoM gain relative to Artisan**. By integrating our three innovative techniques mentioned earlier, AnalogGenie-Lite attains an overall improvement of 23.5% in generation validity, a scalability enhancement of 5.14$\\times$, and a **FoM gain of 1272.9 compared to the current SOTA [1]**. These results underscore the substantial advancement our approach offers in tackling the challenging domain of analog circuit design, **pushing the circuit performance's limit in the post–Moore's law era**.\n\n[1] Gao, Jian, et al. \"AnalogGenie: A Generative Engine for Automatic Discovery of Analog Circuit Topologies.\" *arXiv preprint arXiv:2503.00205* (2025).\n\n[2] Edmonds, Jack, and Ellis L. Johnson. \"Matching, Euler tours and the Chinese postman.\" *Mathematical programming* 5 (1973): 88-124.\n\n[3] Chen, Zihao, et al. \"Artisan: Automated operational amplifier design via domain-specific large language model.\" *Proceedings of the 61st ACM/IEEE Design Automation Conference*. 2024.\n\n[4] Chen, Zihao, et al. \"Total: Topology optimization of operational amplifier via reinforcement learning.\" *2023 24th International Symposium on Quality Electronic Design (ISQED)*. IEEE, 2023.\n\n[5] Lu, Jialin, et al. \"Topology optimization of operational amplifier in continuous space via graph embedding.\" *2022 Design, Automation & Test in Europe Conference & Exhibition (DATE)*. IEEE, 2022.\n\n[6] Zhao, Zhenxin, and Lihong Zhang. \"An automated topology synthesis framework for analog integrated circuits.\" *IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems* 39.12 (2020): 4325-4337.", "claims_and_evidence": "Yes", "methods_and_evaluation_criteria": "Yes", "theoretical_claims": "NA", "experimental_designs_or_analyses": "Although I did not personally execute the code, I carefully reviewed the experimental setup and the corresponding analyses, which appear to be reasonable.", "relation_to_broader_scientific_literature": "The current paper offers a lightweight decoder version of AnalogGenie, which was recently accepted at ICLR 2025.", "essential_references_not_discussed": "To my knowledge the most important references are discussed", "other_strengths_and_weaknesses": "**Strengths**  \n1. The paper is engaging, well-structured, and presents a computationally leaner version of the AnalogGenie Decoder.  \n2. While it leverages established concepts, the paper offers a meaningful contribution by combining subgraph pruning and modeling approaches to enhance scalability.\n\n**Weaknesses**  \n1. Compared to the original AnalogGenie work, the innovation appears incremental. Although the improved scalability is promising, the performance gains also seem relatively modest in scope.", "other_comments_or_suggestions": "The paper is both interesting and technically solid. While the main contribution lies in enhancing scalability and thus appears incremental, these improvements meaningfully advance existing approaches. Overall, the strengths outweigh the limitations, and I recommend acceptance.", "questions_for_authors": "Please see weaknesses.", "summary_of_paper": "", "summary_of_recommendation": "", "technical_quality": "", "clarity_of_presentation": "", "potential_impact": "", "robotics_focus": "", "quality_of_limitations": "", "questions_for_rebuttal": "", "reasons_to_accept": "", "reasons_to_reject": "", "questions_to_authors": "", "extra_scores": {}}, {"review_id": "GdUlLWNfdI", "reviewer": "Reviewer_4Q4T", "summary": "The paper proposes AnalogGenie-Lite, a generative model for discovering analog circuit topologies using lightweight graph modeling. The main contributions of this work are converting device-pin representations from graph to sequence and employing LLMs to design the compressed sequence which implicitly contains topological information. In experiments, this work validates the effectiveness on circuit discover and does case study on protein and social analysis.", "questions": "", "limitations": "", "rating": 3, "confidence": null, "soundness": null, "presentation": null, "contribution": null, "strengths": "", "weaknesses": "", "quality": null, "clarity": null, "significance": null, "originality": null, "strengths_and_weaknesses": "", "was_revised": false, "final_justification": "", "rebuttal": "Thanks for the constructive comments. We address your concerns below.\n\n> **Q1:** Why the baseline, AnalogGenie, is the version without fine-tuning? This work also does fine-tuning by reinforcement learning with human feedback. It seems that there is an unfair comparison.\n\nOur evaluation is designed to ensure **fairness between our work and the baseline AnalogGenie**. As discussed in Section 4.1 on the training setup, **our work is not fine-tuned for evaluations of validity, scalability, versatility, and novelty. We apply RLHF only when evaluating its performance on a specific circuit type**, thereby optimizing it for high-performance circuits. This approach allows us to assess our work both as a versatile foundation model and as a specialized agent. For our baseline, AnalogGenie is evaluated under the same conditions—it is **pre-trained solely for assessing validity, scalability, versatility, and novelty. For performance evaluation, AnalogGenie is also fine-tuned with RLHF**. \n\n> **Q2:** While the authors compress the graph to sequence, which reduce the complexity of the problem to linear, it should also be important analyze the computational complexity of the 'Chinese postman problem'.\n\nWe would like to empirically evaluate the computational cost of Algorithm 1 for solving the Chinese postman problem. Our experiments on a 16‐core i9-12900KF (32 GB RAM) show that Algorithm 1 takes, on average, 937.36 seconds for the Protein dataset while the Analog circuit and Ego datasets took 783.30 and 296.06 seconds, respectively. **This one-time preprocessing cost is justified by the substantial memory savings during training**.\n\n> **Q3:** Could the authors also discuss other algorithms converting graph to sequence? I am just curious why the authors choose this method to compress the graph.\n\nPrior method like **adjacency vector** encodes each node by its connections to all preceding nodes, which results in a $O\\left(n^2\\right)$ complexity ($n$ is the number of nodes and $m$ is the number of edges). Alternatives include a **recursive binary tree [3]** that conditions on matrix rows and columns, reducing complexity to $O((n+m) \\log n)$, and a **graph token sequence[4]** that first encodes node definitions followed by edge, achieving $O(n+m)$.  We choose the Chinese postman sequence for two reasons. First, it has a complexity of $O\\left(m\\right)$, which is **efficient for representing sparse graphs like analog circuits**. Second, representing the graph as a traversal path not only **preserves critical structure information** but also **aligns well with the behavior of language models** by predicting the next token based on the current context.\n\n> **Q4:** Graphs can also be compressed by other algorithms, the simplest one is just record the edges and their corresponding nodes. However, the authors only compare it with vanilla adjacency matrix and sounds like overclaim their scalability (compression rate).\n\nWe appreciate the reviewer's suggestion. While an edge list is compact, **prior work LaMAGIC has already explored this approach by representing graphs as a list of hyperedges**. In that work, the **edge-list underperformed compared to the adjacency matrix**. This indicates that, despite its compactness, the oversimplified structure of an edge list makes it harder for language models to learn and generate complex graph patterns. In contrast, our method is designed to **not only compress the graph but also to preserve structural information critical for effective generation**. Moreover, **our experiments are not limited to comparisons with the adjacency matrix**. We also compare our work with the **AnalogGenie sequence in Figure 5** and the **adjacency vector in Figure 6**. In response to the reviewer's valuable suggestion, **we will extend our case study in Q5 to include additional graph compression algorithms**.\n\n> **Q5:** Why only the authors only conduct case study for protein and ego graphs? While discovering circuit topologies is an interesting problem, I think the contribution will be greatly improved if the proposed methods can be applied to more fields.\n\nWe have expanded our case study to include molecules [1] and 3D point cloud graphs [2]. As shown below, our method consistently outperforms alternatives in compression rate relative to the adjacency matrix.\n\n| Data      | Adj. Vec | Rec. Bin [3] | Graph Tok [4] | Ours     |\n| --------- | -------- | ------------ | ------------- | -------- |\n| Mol [1]   | $2.12$   | $2.16$       | $3.57$        | $9.33$   |\n| 3D PC [2] | $2.00$   | $39.46$      | $158.41$      | $572.56$ |\n\n[1] Ramakrishnan, et al. \"Quantum chemistry structures and properties of 134 kilo molecules.\" *Scientific data,* 2014.\n\n[2] Neumann, et al. \"Graph kernels for object category prediction in task-dependent robot grasping.\" *MLG*. 2013.\n\n[3] Dai, et al. \"Scalable deep generative modeling for sparse graphs.\" *ICML*, 2020.\n\n[4] Chen, et al. \"Graph Generative Pre-trained Transformer.\" *arXiv,* 2025.", "claims_and_evidence": "Yes. The claims are generally convincing.", "methods_and_evaluation_criteria": "Yes. The benchmarks look reasonable.", "theoretical_claims": "The authors do not prove the claims theoretically.", "experimental_designs_or_analyses": "Why the baseline, AnalogGenie, is the version without fine-tuning? This work also does fine-tuning by reinforcement learning with human feedback. It seems that there is an unfair comparison.", "relation_to_broader_scientific_literature": "This work employs a new way to represent the graph and uses LLMs to model it.", "essential_references_not_discussed": "None.", "other_strengths_and_weaknesses": "Strengths:\n1. The discussed problem is interesting and important. \n2. The results are generally promising and good.\n\n\nWeaknesses:\n1. While the authors compress the graph to sequence, which reduce the complexity of the problem to linear, it should also be important analyze the computational complexity of the 'Chinese postman problem'.\n2. Could the authors also discuss other algorithms converting graph to sequence? I am just curious why the authors choose this method to compress the graph.\n3. Graphs can also be compressed by other algorithms, the simplest one is just record the edges and their corresponding nodes. However,  the authors only compare it with vanilla adjacency matrix and sounds like overclaim their scalability (compression rate).\n4.  Why only the authors only conduct case study for protein and ego graphs? While discovering circuit topologies is an interesting problem, I think the contribution will be greatly improved if the proposed methods can be applied to more fields.", "other_comments_or_suggestions": "None.", "questions_for_authors": "Please answer my question in experiments setting and weaknesses. I am happy to turn to positive scores if the answers are satisfactory.", "summary_of_paper": "", "summary_of_recommendation": "", "technical_quality": "", "clarity_of_presentation": "", "potential_impact": "", "robotics_focus": "", "quality_of_limitations": "", "questions_for_rebuttal": "", "reasons_to_accept": "", "reasons_to_reject": "", "questions_to_authors": "", "extra_scores": {}}, {"review_id": "mP15H8Wleg", "reviewer": "Reviewer_EghR", "summary": "AnalogGenie-Lite presents a decoder-only framework designed to discover novel analog circuit topologies by leveraging lightweight graph modeling. Its key contributions lie in three innovations:\n- A precise and efficient graph modeling approach that prunes redundant nodes and edges.\n- Optimal sequence modeling via solving the Chinese Postman Problem to derive near-optimal Eulerian circuits.\nExperimental results on a dataset of over 3350 real-world topologies across 11 analog circuit types demonstrate marked improvements.", "questions": "", "limitations": "", "rating": 3, "confidence": null, "soundness": null, "presentation": null, "contribution": null, "strengths": "", "weaknesses": "", "quality": null, "clarity": null, "significance": null, "originality": null, "strengths_and_weaknesses": "", "was_revised": false, "final_justification": "", "rebuttal": "Thanks for the reviewer's valuable and constructive feedback.\n\n> **W1 & Q1:** Ablation: Additional discussion on the sensitivity of performance to hyperparameter choices in the pruning and subgraph mining processes could be beneficial. How sensitive is the overall performance to the threshold used for pruning isolated nodes in subgraph modeling?\n\nWe conducted an ablation study to assess how AnalogGenie-Lite's performance responds to two key hyperparameters in our subgraph pruning process: (1) the frequency threshold of subgraph occurrence in the dataset and (2) the threshold for the number of isolated nodes in a subgraph. Specifically, we experimented with frequency thresholds of 5%, 25%, and 50% along with isolated node thresholds of 4 and 8. A subgraph is pruned if its occurrence frequency exceeds the chosen threshold and if it contains more isolated nodes than the specified limit. After compressing the dataset, we followed our standard pretraining and finetuning procedure for AnalogGenie-Lite. The results are summarized in the table below:\n\n|                       | Validity (%) $\\uparrow$ | Scalability $\\uparrow$ | MMD $\\downarrow$ | Op-Amp FoM $\\uparrow$ | Power converter FoM $\\uparrow$ |\n| --------------------- | ----------------------- | ---------------------- | ---------------- | --------------------- | ------------------------------ |\n| 5% freq & 4 isolated  | 96.9                    | 341                    | 0.0419           | 15015.9               | 3.99                           |\n| 5% freq & 8 isolated  | 97.1                    | 330                    | 0.0409           | 15016.4               | 4.00                           |\n| 25% freq & 4 isolated | 97.3                    | 324                    | 0.0408           | 15017.7               | 4.02                           |\n| 25% freq & 8 isolated | 96.5                    | 322                    | 0.0409           | 15012.5               | 4.01                           |\n| 50% freq & 4 isolated | 95.3                    | 306                    | 0.0420           | 14998.3               | 3.99                           |\n| 50% freq & 8 isolated | 94.2                    | 293                    | 0.0433           | 14982.8               | 3.99                           |\n\nOverall, **most performance metrics are relatively insensitive to these hyperparameters**. The one exception is scalability, which is notably affected by changes in the thresholds due to their direct impact on the number of subgraph pruning candidates. Notably, in 5% frequency results, aggressively lowering the thresholds to achieve higher compression introduces a large number of infrequently used special tokens into the tokenizer, which adversely affects training and ultimately hurts performance on metrics other than scalability.\n\n> **C1 & Q2:** More detailed analysis regarding the integration of reinforcement learning with human feedback—specifically, how this impacts circuit FoM—could further enhance the paper. Could you elaborate on how reinforcement learning with human feedback is integrated into the generation process, in detail?\n\nAnalogGenie-Lite pretrained-only model can initially produce a wide variety of analog circuit topologies without inherent bias toward specific performance metrics. To optimize it for generating high-performance circuits, we integrate RLHF in a two-step fine-tuning process. First, **a reward model—trained on human-labeled examples—is used to score generated circuit topologies based on type and performance**.  Then, we **fine-tune the pretrained model with PPO: the model generates new designs, the reward model assigns scores, and PPO updates the model to maximize the expected accumulated reward**. This process directs the pretrained model toward optimal circuits, boosting the FoM for Op-Amps from 291.3 to 15017.7 and for power converters from 2.6 to 4.02.\n\n> **Q3:** How does AnalogGenie-Lite handle circuits with highly irregular or non-repetitive topologies that may not benefit from subgraph simplification?\n\nOur approach is robust even for highly irregular circuit topologies that do not benefit from subgraph simplification. Specifically, we **exploit a common feature in all analog circuits: the ground node, which connects to multiple device pins within the circuit**. By consolidating these multi-pin shared edge connections through graph-level simplification, AnalogGenie-Lite can maintain compression rate without subgraph simplification. As shown in Figure 5, **our graph-level method delivers a mean compression rate of 40.28$\\times$ compared to adjacency matrix representation without the subgraph simplification**. Furthermore, because **analog circuit graphs are inherently sparse**, our optimal sequence modeling strategy can **maintain an additional 1.43$\\times$ improvement in compression performance**. These two approaches ensure that our method remains effective even when subgraph simplification is less applicable.", "claims_and_evidence": "**Main Claims**:\n- AnalogGenie-Lite achieves a dramatic reduction in sequence length (up to 71.11× over traditional adjacency matrix representations) and substantial improvements in validity.\n- The method is broadly applicable, as evidenced by case studies extending to domains like protein graphs and social networks.\n\n**Evidence Provided**:\n- Quantitative comparisons (e.g., Table 1 and Figure 5) show improved compression ratios, higher validity percentages, and enhanced performance metrics (FoM) over baselines.\n- Algorithmic pseudocode support the claims regarding efficiency and optimality in sequence .", "methods_and_evaluation_criteria": "**Methods**:\n- Lightweight Graph Modeling and Optimal Sequence Modeling\n\n**Evaluation Criteria**:\n- Validity: Percentage of generated circuits that are SPICE-simulatable without errors.\n- Scalability: Maximum circuit size (in terms of devices) that can be generated.\n- Versatility & Novelty: Diversity of analog circuit types generated and the percentage of designs that differ from those in the training dataset.\n- Performance (FoM): A figure-of-merit combining key circuit performance metrics such as gain, bandwidth, and power.", "theoretical_claims": "N/A", "experimental_designs_or_analyses": "**Design**:\n- 3350 unique analog circuit topologies spanning 11 types.\n- The experimental design is robust, with ablation studies to isolate the contribution of each innovation (pruning, subgraph mining, and optimal sequencing).", "relation_to_broader_scientific_literature": "N/A", "essential_references_not_discussed": "N/A", "other_strengths_and_weaknesses": "**Strengths**:\n- Innovation: The paper introduces a highly innovative and technically rigorous approach to analog circuit topology generation.\n- Efficiency: The significant reduction in sequence length and improved compression ratios are compelling, addressing a critical bottleneck in training large language models on graph representations.\n\n**Weaknesses**:\n- Ablation: Additional discussion on the sensitivity of performance to hyperparameter choices in the pruning and subgraph mining processes could be beneficial.", "other_comments_or_suggestions": "More detailed analysis regarding the integration of reinforcement learning with human feedback—specifically, how this impacts circuit FoM—could further enhance the paper.", "questions_for_authors": "1.\tHow sensitive is the overall performance to the threshold used for pruning isolated nodes in subgraph modeling?\n2.\tCould you elaborate on how reinforcement learning with human feedback is integrated into the generation process, in detail?\n3.\tHow does AnalogGenie-Lite handle circuits with highly irregular or non-repetitive topologies that may not benefit from subgraph simplification?", "summary_of_paper": "", "summary_of_recommendation": "", "technical_quality": "", "clarity_of_presentation": "", "potential_impact": "", "robotics_focus": "", "quality_of_limitations": "", "questions_for_rebuttal": "", "reasons_to_accept": "", "reasons_to_reject": "", "questions_to_authors": "", "extra_scores": {}}, {"review_id": "MuCRSjI7ES", "reviewer": "Reviewer_Xhyg", "summary": "This work introduces a decoder-only transformer for analog topology generation by solving three critical challenges. At the graph level, it simplifies current approach by removing redundant nodes and edges. At the sub-graph level, it employs subsequent subgraph minging to identify commonly reused subgraphs in the database.  Lastly, it models a circuit graph as a shortest closed path by solving the Chinese Postan problem.", "questions": "", "limitations": "", "rating": 4, "confidence": null, "soundness": null, "presentation": null, "contribution": null, "strengths": "", "weaknesses": "", "quality": null, "clarity": null, "significance": null, "originality": null, "strengths_and_weaknesses": "", "was_revised": false, "final_justification": "", "rebuttal": "We appreciate the reviewer's valuable comments.\n\n> **Q1:**  It would be better if there is a discussion for time cost of each method. The two techniques introduced in this work, subgraph mining and solving Chinese Postman problem, seems to introduce much time.\n\nWe would like to evaluate the time cost of our subgraph mining algorithm and Algorithm 1 for solving the Chinese postman problem empirically. Our experiment is conducted on a PC with a 16‐core i9-12900KF CPU and 32 GB RAM. We run each algorithm 5 times on the analog circuit dataset. The mean runtime for the subgraph mining algorithm is 1473.74 seconds, and Algorithm 1 is 783.30 seconds. **This one-time preprocessing cost can be amortized by the substantial memory and time savings during model pre-training**.\n\n> **Q2:**  From the formulation of the task, it is possible to leverage pre-trained language model, e.g., old models such as T5 or new models such as Llama and GPT-4o, as a prior and conduct fine-tuning on it. It would be better if there are discussion about them and a comparison with current train-from-scratch approach.\n\nWe appreciate the reviewer’s suggestion. In our study, we have already compared our train-from-scratch approach with methods that leverage pre-trained language models. Specifically, our experiments included:\n\n- AnalogCoder [1]: a **GPT-4o-based model** using domain-specific prompt engineering.\n- LaMAGIC [2]: a model fine-tuned on a **FLAN-T5-base** backbone.\n- Artisan [3]: a model fine-tuned on a **Llama2-7b** backbone.\n\nAs detailed in Table 1 of our paper, our approach outperforms these baselines across several key metrics, including validity, scalability, versatility, novelty, and FoM. \n\n> **Q3:**  the generation task in this work seems to mean unconditional generation, where we cannot control what will be generated. Is that right? Can it be used for text-based generation, where text describes the design requirements.\n\n**Our approach is not limited to unconditional generation**. We incorporate mechanisms to **steer the generation process toward a specific type of analog circuit topologies optimized for key performance metrics** (e.g., Figure of Merit) by leveraging **reinforcement learning with human feedback (RLHF)** to fine-tune our pre-trained model. The process begins with training a reward model that evaluates generated topologies based on validity, circuit type, and performance using a dataset labeled by humans. Once this reward model is trained, we apply proximal policy optimization (PPO)  [4] to iteratively refine the pre-trained model. In each training epoch, the model generates a batch of candidate topologies that are scored by the reward model, and the model parameters are adjusted to maximize the expected accumulated reward scores, effectively steering the generation toward high-performance designs. **Although AnalogGenie-Lite currently does not support text-based input, its underlying next-token-prediction mechanism makes it naturally compatible with text generation**, and by augmenting the netlist dataset with text-based descriptions of design requirements, we can extend our approach to **include text-based control in future iterations (as acknowledged by the reviewer in Relation To Broader Scientific Literature section)**.\n\n\n\n[1] Lai, Yao, et al. \"Analogcoder: Analog circuit design via training-free code generation.\" *arXiv preprint arXiv:2405.14918* (2024).\n\n[2] Chang, Chen-Chia, et al. \"Lamagic: Language-model-based topology generation for analog integrated circuits.\" *arXiv preprint arXiv:2407.18269* (2024).\n\n[3] Chen, Zihao, et al. \"Artisan: Automated operational amplifier design via domain-specific large language model.\" *Proceedings of the 61st ACM/IEEE Design Automation Conference*. 2024.\n\n[4] Ouyang, Long, et al. \"Training language models to follow instructions with human feedback.\" *Advances in neural information processing systems* 35 (2022): 27730-27744.", "claims_and_evidence": "The three techniques in the paper are well supported by the experimental results.", "methods_and_evaluation_criteria": "This paper introduces though evaluation metrics during the experiments. It would be better if there is a discussion for time cost of each method. The two techniques introduced in this work, subgraph mining and solving Chinese Postman problem, seems to introduce much time.", "theoretical_claims": "There is no theoretical claim.", "experimental_designs_or_analyses": "From the formulation of the task, it is possible to leverage pre-trained language model, e.g., old models such as T5 or new models such as Llama and GPT-4o, as a prior and conduct fine-tuning on it. It would be better if there are discussion about them and a comparison with current train-from-scratch approach.", "relation_to_broader_scientific_literature": "It proposes a compact way to represent circuit topology. Although it is only trained on unconditional generation task, it can be used on conditional generation (e.g., text as condition) in the future.", "essential_references_not_discussed": "No.", "other_strengths_and_weaknesses": "No additional comments.", "other_comments_or_suggestions": "No additional comments.", "questions_for_authors": "1) the generation task in this work seems to mean unconditional generation, where we cannot control what will be generated. Is that right? Can it be used for text-based generation, where text describes the design requirements.", "summary_of_paper": "", "summary_of_recommendation": "", "technical_quality": "", "clarity_of_presentation": "", "potential_impact": "", "robotics_focus": "", "quality_of_limitations": "", "questions_for_rebuttal": "", "reasons_to_accept": "", "reasons_to_reject": "", "questions_to_authors": "", "extra_scores": {}}]

Author rebuttal:

Meta-review: This paper proposes AnalogGenie-Lite, a decoder-only generative framework for discovering novel analog circuit topologies. By leveraging lightweight graph modeling, frequent subgraph mining, and sequence optimization via the Chinese Postman Problem, the method improves both efficiency and generation quality. Experiments on real-world analog circuits demonstrate its effectiveness in generating diverse and high-quality designs.

All reviewers recommended accepting the paper.
Decision: Accept (poster)