CircuitNet 3.0: A Multi-Modal Dataset with Task-Oriented Augmentation for AI-Driven Circuit Design
Authors: Mingjun Wang
Yihan Wen
Yuntao Lu
Fengrui Liu
Yuxiang Zhao
Boyu Han
Jianan Mu
Yibo Lin
Runsheng Wang
Bei Yu
Huawei Li
Venue: ICLR 2026 Poster (2026)
Keywords: Dataset
Benchmark
Machine learning
Electric design automatic
Primary area: datasets and benchmarks

Abstract: Integrated circuit (IC) designs require transforming high-level specifications into physical layouts, demanding extensive expertise and specialized tools, as well as months of time and numerous iterations. While machine learning (ML) has shown promise in various research domains, the lack of large-scale, open datasets limits its application in chip design. To address this limitation, we introduce CircuitNet 3.0, a large-scale, comprehensive, and open-source dataset curated to facilitate the evaluation of ML models on challenging timing and power prediction tasks. Starting with a diverse set of 8,659 validated open-source designs, we employ a systematic framework to generate over 15,000 instances. Through specialized syntax-tree mutation strategies and principled, task-oriented filtering methodology, we enrich each design with multi-modal information spanning multiple design stages, including complete design flow documentation, register-transfer-level (RTL) designs and corresponding netlists, detailed physical layouts, and comprehensive performance metrics. The experimental results demonstrate that ML models leveraging the enriched multi-stage, multi-modal circuit representations significantly improve performance over existing open-source datasets in electronic design automation (EDA) tasks, paving the way for efficient and accessible circuit representation learning. The dataset and codes are available in \url{https://github.com/sklp-eda-lab/iclr-circuitnet_3.0/}.

Published as a conference paper at ICLR 2026
CIRCUITNET 3.0: A MULTI-MODAL DATASET WITH TASK-ORIENTED AUGMENTATION FOR AI-DRIVEN CIRCUIT DESIGN
Mingiun Wang*. 1.223, Yihan Wen *.3 Yuntao Lu Fengrui Liu Yuxiang Zhao", Boyu Han Jianan Muf Yibo Lin", Runsheng Wang", Bei Yut.3, Huawei Li
State Key Lab of Processors, Institute Computing Technology, Chinese Academy of Sciences
University of Chinese Academy of Sciences "The Chinese University of Hong Kong *Peking University SStanford University
"Equal contribution *Corresponding authors
ABSTRACT
Integrated circuit (IC) designs require transforming high-level specifications into physical layouts, demanding extensive expertise and specialized tools, as well as months of time and numerous iterations. While machine learning (ML) has shown promise in various research domains, the lack of large-scale, open datasets limits application in chip design. To address this limitation, we introduce Circuit- Net 3.0, large-scale, comprehensive, and open-source dataset curated to facil- itate the evaluation of MI. models on challenging timing and power prediction tasks. Starting with diverse set of 8,659 validated open-source designs, we em- ploy a systematic framework to generate over 15,000 instances. Through special- ized syntax- tree mutation strategies and principled, task-oriented filtering method- ology, we enrich each design with multi-modal information spanning multiple design stages, including complete design flow documentation, register-transfer level (RTL) designs and corresponding netlists, detailed physical layouts, and comprehensive performance metrics. The experimental results demonstrate that ML models leveraging the enriched multi-stage, multi-modal circuit represen- tations significantly improve performance over existing open-source datasets electronic design automation (EDA) tasks, paving the way for efficient and ac- cessible circuit representation learning. The dataset and codes are available 37
sttps::/qiian com/
INTRODUCTION
Digital circuits constitute the comerstone of contemporary computing infrastructure, enabling the advancement of modern technology (Agarwal & Lang 2005). The intricate process of IC design en- compasses the systematic transformation of abstract functional specifications into manufactured sil- icon implementations while adhering to increasingly demanding performance requirements (Lienig Scheible, 2020 Calhoun al., 2008). A fundamental challenge lies in maintaining functional correctness and achieving performance objectives, particularly as design complexity continues to scale (Bryant al. 2001).
IC design traditionally follows a waterfall methodology comprising three sequential stages: Register-Transfer Level Design, where designers create and validate functional specifications (Chul 2006); (2) Logic Synthesis. which converts these specifications into optimized gate-level netlists (Kaeslin 2014); and (3) Physical Design, which implements these netlists as manufacturable silicon layouts (Kulkarni & Chopde (024). While this hierarchical ap- proach facilitates focused optimization at each stage, introduces substantial design inefficiencies. The conventional flow requires complete layout implementation before performance validation, sulting in verification cycles that can span weeks (Kahng, 2018). When designs fail to meet specifi- cations, Engineering Change Orders (ECOs) trigger cascading modifications across multiple stages, often necessitating fundamental RTL redesign (Huang et al. 2013). This linear progression signifi- cantly hampers design convergence and extends development timelines.
As illustrated in Figure ((a)

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Waterfall Model
ECO
Violations
Violations
Violations
Shift-Left Model
Analysii
Prediction ECO
Prediction RCO
KTL Design
Netlist
Layout
KTL Design
Netlist
Layout
Timeline
Lengthy Iterative Design Cycles
Timeline
c Time Saving by Shift-Left Model
(a) The traditional waterfall model.
(b) The modern shift-left model.
Figure I: Comparison of IC design workflows. The shift-left model (b) accelerates the design cycle by incorporating early, predictive feedback loops, avoiding the lengthy, iterative ECOs inherent in the traditional waterfall model (a).
Nowadays, advanced EDA tools have embraced ML-driven approaches Xing 2024). The shift-left methodology, depicted in Figure [(b) introduces predictive violation detection and ECO mecha- nisms at earlier design stages, enabling proactive optimization of power, performance, and area (PPA) metries (Zeng] 2024). However, the widespread adoption of ML-driven EDA faces several fundamental challenges. The first is for data scarcity. EDA domains lack comprehensive design datasets due intellectual property restrictions, unlike established ML fields such computer vi- sion and natural language processing (Srivastava et al. (024)). Another challenge is the complexity of data generation. Developing realistic EDA datasets requires sophisticated commercial tools, ex- tensive domain expertise, and considerable computational infrastructure (Kamat et al., 2011), as well as months of numerous iterations. Finally, achieving high prediction accuracy for various tasks in EDA is challenging. In industrial practice, the value of predictive model is determined not by its average-case performance, but by its accuracy on designs that push the limits of timing and power budgets[Lavagn et al. (2018), 8). Current early-stage estimation techniques fail to achieve commercial- grade accuracy and lack integration with realistic layout representations. limiting the effectiveness of multi-modal analysis approaches (Chai et al. 2023).
To address these fundamental challenges in ML-driven EDA, we propose CircuitNet 3.0, a compre- hensive multi-stage and modti dataset that enables advanced AI-driven circuit design through innovative cross-stage data augmentation and filtering. Our contributions are as follows:
A large-scale, multi-modal, and multi-stage digital circuit dataset with full RTL-to-layout traceability. CircuitNet 3.0 contains 8,659 unique and validated source RTL designs and over 15,000 total augmented designs, cach with corresponding netlist and layout representations. Through an industrial EDA workflow, we extract rich cross-modal features at each design stage, providing valuable resource for research in multi-stage multi-mode representation learning.
A principled framework for data augmentation. For the critical scarcity of open-source RTL. designs, we develop a novel data augmentation framework based on Verilog syntax trees. This framework systematically enhances dataset diversity through stage-aware transformations and task-specific filtering mechanisms, focusing on industrially valuable cases (c.g., designs contain- ing critical timing paths high dynamic power). This enables robust learning for ML models, providing simultaneous cross- stage analysis and early-stage prediction capabilities.
A comprehensive set of new baselines and rigorous experimental protocols. Through com- prehensive evaluation with state-of-the--ar ML models, we demonstrate significant prediction accuracy improvements over single-modal datasets, with approximately 36.0% and 12.9% error reductions for timing and power tasks, respectively, compared to the existing dataset. Models trained on CircuitNet 3.0 consistently outperform single-modal approaches, establishing new performance benchmarks for ML-driven EDA tasks.
2 PRELIMINARIES
Representations of Designs. IC designs are represented in multiple forms throughout the chip development process, each serving specific purposes and containing different levels of design in- formation (Wolf, 2002). These representations evolve through the EDA flow, ensuring functional correctness and manufacture (Wang et al. 2009). As illustrated in Figure O these representations can be categorized into three distinct stages and modalities.
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Spec
RTL
Netlist
Layout
Design Compiler
Cadence
Innovus
Text Modality
Graph Modality
Image Modality
Description
RILe
Simple Openator Graph
Gate-T Lvel Netlist
Layout Image
Features/ Ground Truths
LLM Embedding
Graph Embedding
Figure 2: Design representations from different stages in the EDA workflow.
Setup and Hold Time Checks
Powiiiiing ofC2VDD
Com binati mnal Logics
CLK
Clock Path
(b)
Figure 3: (a) Timing analysis of designs; (b) Power estimation of designs.
The design flow progresses through three key representations (Lienig et al. 2020b The repre- sentation serves as the primary entry for digital circuit design, providing abstract behavioral de- scription that enables designers to focus on functionality while abstracting lower-level details (Vahid] 2010 Churiwala Garg 2011). The following netlist representation implements logical circuits through the synthesis of RTL, comprising standard cells and their connectivity, while bridging be- havioral and physical implementations (Gayathri & Taranath 2017: [Skouoon et al.] 2020) Lienig et al. 2020a). The last representation of layouts deñnes physical implementations through geomet- ric patterns on silicon (Lienig & Scheible, 2020), including precise cell placement and metal inter- connect routing (Cong et al. 2005), which ultimately determine the timing, power, and area metrics of circuits (Baker 2019). Each representation plays a crucial role in the whole design flow, with an increasing level of detail and complexity aligning with design progress from RTLs to layouts.
Closure Objectives of Design. The primary goal of digital circuit design is to meet key performance Sajeetives-ppinciiallly timing and power closure- across all stages of EDA workflow (Huang et al., 2021]. Accurately predicting these metrics at early stages is a critical application for ML models.
Timing Closure is essential for ensuring circuit operates correctly its target frequency (Golshan 2020). As shown in Figure (a), this is governed by setup and hold time constraints on all signal paths between sequential elements. To quantify timing performance, three key metrics are used (Guo & Lin 2022): Arrival Time (AT), the signal propagation delay along path; Worst Negative Slack (WNS), the timing violation of the single most critical path in the design; and Total Negative Slack
(TNS), the sum of violations across all failing paths. A non-negative WNS indicates all timing constraints are met, making a primary objective for design closure (Kahng al. 2011).
Power Closure primarily targets the management of dynamic power consumption, which arises from the switching activity of transistors (Benini & DeMicheli 1997). As illustrated in Figure Bb) this power (PSwitehing) is mathematically expressed as x J x XC, x CV.XVB where represents switching activity, f is clock frequency, Cr, load capacitance, and VDD is the supply voltage. Accurate early estimation is crucial for meeting power budgets and managing thermal constraints (Kawal 2007).
Predicting these closure metrics early in the design flow, such as at the RTL stage, is highly valuable for reducing design iterations and time-to-market. However, early-stage predictions are challeng- ing because key physical information (e.g., parasitic resistance and capacitance from the layout) is not yet available. This creates critical need for ML models that effectively leverage multi- modal representations (RTL, netlist, layout) to learn the complex relationships between early design choices and final physical outcomes.
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Table 1: Comparison of Open-Source EDA Datasets for Circuit Design
Datasels
VerilogEval V2
RTLLMZ.0
CircuitNet 2.0
RTLCoder
CircuitNet 3.0
Open Source
Dula Augmentation
Design Validation
Pass- Syntheisss
Pass-Simulation
x
X
Stage Coverage
Front-End (RTL)
Back-Eind (Layout)
X
Data Modalitles
Text Only 156 N/A Evalunting I.I.M
Only 50 N/A
TextKGraph/Image 8
Text Only 26,532 N/A Training L.M on RTL generation
Text/Graph/Imagg
# of RTL Designs
8,659 (wlo Augment)
# Layout Designs
10,791 Routability! IR-Drop/ Timing Analysis
15,863
Evalinting L.M
Farly-Stage
Target Tasks
on RTL generation
on RTL generation
Timing/Pwwer
Prodiction
RTI Data Collection
Data Generation and
Multi-Stage Data Gene. ration and Extract
and Cleaning
Task-Oriented Augmentation
Original Data
Data Cleaning
Expansion
Refinement
EDA
Feature Extract
Github Hugging Face
RTL AST-Based Rewrite
RTL
Slack AT Power Map
Compile
EDA Task Oriented Refinement
donshara
Stredie
OpenCore RISC-V
Synthesize
Netlist
Simulate
FAR
Lavout
Figure 4: CircuitNet 3.0 workflow framework of multi stage and multi-modality dataset.
Datasets of Designs. Datasets are essential for advancing ML methodologies in EDA tasks. Cir- cuitNet 1.0 and 2.0 (Chai et al., 2023 Jiang et al. 2024) datasets target logical and physical design stages. providing extensive layout data for functions as routability prediction. However, they lack sufficient RTL designs, limiting their applicability in early-stage modeling. RTL-focused datasets like VeriLogos (Min et al. 2025), RTLLM (Lu et al. 2024) and Verilog-Evall (Liu et al.) (023) con- centrate on RTI. generation from specifications but lack corresponding netlist, layout, and perfor- mance metrics. While recent works have focused on EDA representation benchmarks, they exhibit key limitations. Although ForgeEDA provides diverse circuit representations for benchmarking logic synthesis tasks (Shi et al. 2025). lacks the final physical implementation stage and is not open-source. EDALearn (Pan et al.) 2024), which presents an end-to-end flow to study the impact of varying open-source EDA tool parameters, limited in scale to only a few designs, lacking sufficient diversity. Consequently, these contributions do not offer the complete, industry-standard RTL-to-Layout workflow and design variety necessary to train robust and generalizable ML mod- els. Furthermore, most open-source datasets are primarily for single-stage tasks, with few contain- ing comprchensive. synthesizable RTL implementations of designs and complete multi-stage data extending to the physical level. To bridge this gap, present CircuitNet 3.0. advanced large- scale dataset that provides multi-modal multi-stage circuit representations, spanning from RTLs to layouts, along with corresponding performance metrics. This enables ML models to explore the complete design flow and achieve inter-stage collaboration.
3 OVERVIEW OF CIRCUITNET 3.0
CircuitNet 3.0 is an open-source dataset containing 15, 863 design schemes, each of which encom- passes data with RTL, netlist, and layout representations from all stages of the entire IC design workflow for EDA tasks. Among the data, 8, 659 samples are original circuits collected directly, while the rest of the designs were optimized and rewritten for timing and power prediction tasks to generate new designs. We design large-scale, diverse, and comprehensive dataset to meet the needs of machine lcarning-driven circuit modeling.
Table I provides a summary of CircuitNet 3.0 compared with other existing datasets for EDA tasks. CircuitNet 3.0 includes multi-stage RTL, netlist, and layout descriptions, covering all three circuit representation stages and verified using synthesis and simulation tools. In contrast, other datasets lack both the richness of circuit representations and the diversity of designs. For instance, although CircuitNet 2.0 includes complete multi-staee data, it contains insufficient RTL entries. Conversely, RTLcoder offers more RTT. designs but does provide data for the netlist and layout stages. More
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Table 2: LLM & expert-based categories of the original RTL dataset. The dataset comprises 16
subcategories across four main functional categories.
Main Calegory Subcalegory
Main Category
Subcalegory
Arithmetic & Logic Units (23.6%)
Data Processing Units (29.9%)
Addter'Subtracoor
645
Comparakoor/Seeetaa
1,453
Multiplier/Divddrr
774
Encoder/Deooder
431
ALU/Accumuallor
519
FIFO/Buller
407
Others
114
Others
292
Control & Sequential C Circuits (17.9%)
Communication & Memory (28.6 %c
Counter Timer
Memory/ /eenory/Register
1,061
FSM/Sequencer
392
Bus Interface
94.
Cantrol Logic
242
Serial Interface
445
Others
Others
27
Total RTL Designs:
8,659
importantly. CircuitNet 3.0 introduces a task-driven EDA data augmentation strategy, improving the representativeness and utility of the dataset.
DATA GENERATION AND AUGMENTATION
4.1 OVERVIEW OF CHALLENGES AND METHODOLOGIES
Constructing effective datasets for complex circuit design tasks presents fundamental challenges. Simply collecting internet-sourced data proves insufficient due to its limited availability and incon- sistent quality. Random eircuit generation typically yields low-quality designs that fail synthesis validation or contribute minimal value to predictive modeling. To address these limitations, we pro- pose a systematic multi-stage data augmentation framework that leverages circuit representations at different abstraction levels. This combines efficient RTT.-level generation with task-oriented re- finement at netlist and layout stages, ensuring scalability and task-specific representativeness while maintaining design validity through rigorous EDA tool validation.
Figure illustrates the completed data construction and augmentation procedures for the dataset. First, collected more than 100, 000 RTL code lines from open-source websites, cleaned up illegal samples, resulting 8, 659 high-quality RTL implementations as the original dataset. Then, using the coarse-grained characteristies of the RTL, efficiently generate large number of various circuits based on the cleaned dataset through the Verilog syntax tree rewriting method. Finally, at the netlist and layout level (i.e., the stage where circuit structures we perform task-oriented data augmentation to generate more representative and instructive circuit data. In the following sections, we will first describe our data collection and cleaning process, then introduce our fast RTL source data rewriting generation scheme, and present our EDA task-oriented multi-stage data augmentation method of IC designs.
implemented at finer resolution),
4.2 RTL DATA COLLECTION AND CLEANING
We systematically collected RTL designs from established platforms, including GitHub, Hugging Face, OpenCore, and RISC-V projects, ensuring compliance with open-source licensing require- ments. All designs underwent rigorous validation using commercial synthesis and simulation tools to guarantee functional correctness and eliminate circuits with errors or combinational loops.
Our final curated dataset, classified using Claude Opus with expert validation, comprises 8, 659 high-quality RTL designs spanning four primary categories of arithmetic and logic units (23.6%), control and sequential circuits (17.9%), data processing units (29.9%), and communication and memory (28.6%). The category ensures comprehensive coverage of fundamental circuit building blocks while maintaining design diversity essential for robust ML model training.
Notably, approach prioritizes modular and well-characterized designs over large- scale CPU im- plementations that often contain repetitive structures. This strategy enhances dataset uniformity and enables precise performance analysis across different circuit categories, facilitating targeted model optimization and systematic comparison of MI-drrven EDA methodologies.
4.3 RAPID AND EFFICIENT DATA GENERATION
Leveraging a higher abstraction level of RTL implementations compared to netlists, we implement systematic circuit generation through Verilog abstract syntax tree (AST) rewriting. Rather than
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(b) Timingg-Tssk-rrieiiee Data Augment Refinement
Mutation operator
Notile
Insocacotirzie
90%
Layout successful optimzed by innovas
(a) AST-based Rewrit
oode
Netlii
axii Aaaiy 98%
Irsconoppivie
Leyout
Tuning- Tink- Orleated Dataset
Laysul
Layout unsurcessful optimoed by innovus
RT.
RTT passed power check by Vollus
Natiie
axii Jawiy 98%
Layout
RTL. failed power check by Vollus
(c)
Data Augment and Refinement
DC compiieentyy
Netlist version with the optimal power
Valto report parse
DC comple malgg
Netist
JBNe
UC comple sitr
comple caff?? 2
Netler
Design Compiler's systhesis mand
Netle
Myrmaal
Valuo reprt_poner
Vollue's power analysis command
Netiot
DC complie coufig12
Asgratted
different Compile Config
Figure 5: Data Augmentation Process for Enhancing Diversity and EDA Task Representativeness
Table 3: Examples of AST-based Mutation Operators for RTL Data Augmentation
Mutation Type
Operators
Transformation
Constraints
Artthmettc
X, s.e..
Bidirectional substitution
Type preservation
Logical
&& |1. e.c.
Cross operalor replacement
Context-ave awwrr
Relational
1, 2, S. etc.
Comparison inversion
Type safe
Temporal
posedge negedge
Edge polarity toggle
Sequential blocks
Assignment
<= ++ Integer
Blocking type conversion 1.1 modification
Always-block consistency
Constant
Bit-width preservation
generating random RTL code, apply sophisticated transformation rules to validated designs, as illustrated in Figure 5 (a) and detailed in Table which ensures that our rewriting results are more reliable and trustworthy.
This methodology offers two key benefits, which are minimal code modifications to RTLs and gen- eration with validated models. The coarse granularity of RTLs enables few code modifications to produce significant structural variations, efficiently generating diverse circuit instances. Moreover, focusing on localized modifications of cleaned validated designs rather than randomly generated RTLs, we substantially improve synthesis success rates and design quality.
The AST-based rewriting employs context-aware mutation operators including arithmetic substitu- tions, logical transformations, and temporal edge modifications, all constrained by type preservation and synthesis validity requirements. This approach ensures generated circuits maintain functional correctness while achieving substantial structural diversity.
4.4 ORSKETRIENTED DATA AUGMENTATION
A primary goal of CircuitNet 3.0 is to create dataset that effectively focuses challenging, performance-criiee designs. In industrial practice, the value of a predictive model is determined not by its average-case performance, but by its accuracy cases that push the limits of timing and power budgets. During logic and physical design stages, we leverage fine-grained circuit representations for task-specific augmentation through two complementary strategies: multi-stage generation and intelligent selection tailored to timing and power requirements. Through the systematic approaches, generate high-quality, task-specific datasets that effectively capture the structural and behavioral characteristics essential for accurate timing and power prediction in industrial EDA workflows. By leveraging commercial EDA tools such as Synopsys Design Compiler (Synopsys 2025a) and Ca- dence Innovus (Cadence 2025a), this workflow generates three distinct data modalities: text (from specifications and RTT. codes), graph (from RTL. and netlist stages), and image (from layout stage).
Data Augmentation for Timing Prediction Task. (/) Multi-stage data generation. Timing predic- tion fundamentally requires accurate estimation signal propagation delays across logic elements and interconnects. For each RTL design, we perform comprehensive logic and physical optimiza- tion to generate timing-optiall netlists and layouts, as shown in Figure training labels. (2) Data selection. Timing closure is often dictated by a circuit's longest paths. Models trained only on designs with ample timing slack may fail to generalize to the timing- ciiina-rrtical scenarios that engineers focus on. We prioritize circuits with substantial path lengths, longer
providing high-quality

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paths present the most critical challenges for timing closure and represent worst-case scenarios sential for model robustness. The filtering excludes trivial short-path circuits, concentrating training resources on challenging, industrial cases for training efficiency.
Data Augmentation for Power-Prediction Task. (1) Multi-stage data generation. Power predic- tion requires accurate modeling of switching activity across diverse logic topologies. Since KTL- level granularity may be insufficient-singl RTL statements can map to vastly different gate-level implementations-wwe focus on netlist-level analysis. As illustrated in Figure c), for the same RTL code, we generate multiple netlist variants using different synthesis constraints. capturing the im- pact of logic topology on power while maintaining functional equivalence. (2) Data selection. For power- pewerrprediction model training. circuits with meaningful variations in switching activity under dif- ferent inputs are most valuable. Suppose a module's logic is unreachable or never toggles under any input (possibly due to logic unreachability introduced by rewriting). In that case, it contributes little to the training and may even reduce efficiency. Therefore, we further use the EDA tool Cadence Voltus (Cadence, 2025b) to perform vectorless dynamic power analysis and select circuit designs where the fraction of inactive logic is low, excluding circuits with large amounts of ineffective logic. The result is a curated dataset that improves training efficiency for power prediction.
5 EVALUATIONS ON CIRCUITNET 3.0
5.1 EXPERIMENTAL. SETUP
We conduct comprehensive experiments on CircuitNet 3.0, comprising 15, 863 unique circuit de- signs with complete representations across RTL, netlist, and layout stages. Each design instance encompasses Verilog code with functional specifications at the RTL stage, gate-level representa- tions with connectivity graphs at the netlist stage, and physical implementation data with parasitic parameters at the layout stage. Ground-truth performance metrics, including arrival time (AT), the worst negative slack (WNS), the total negative slack (TNS), and power, are generated using Syn- opsys Design Compiler (Synopsys] 2005a)) with comp 1 e_ull luuuurr tra optimization for synthesis, Ca- dence Innovus (Cadence (2025a) with multi-corner multi-mode (MCMM) optimization for physical design, and Synopsys PrimePower (Synopsys 2025b) for power analysis.
All experiments utilize 8 NVIDIA A100 GPUs with PyTorch 2.0.1 and PyTorch Geometric 2.3.1. Training employs A optimization with learning rate 2 x 10-4 and cosine annealing. Models are trained for 50 epochs with early stopping based on the validation loss. The dataset partitioned at the source design level into training (80%), validation (10%), and test (10%) sets. To create a stringent test of generalization, the test set is composed exclusively of original, un-augmented designs. Crucially, suppose a source design is allocated to the test set. In that case, all of its augmented variants are entirely excluded from the training and validation pools, preventing any leakage of structural information. To further bolster the reliability of our evaluation, the test set is also supplemented with submodules from open-source projects external to our dataset.
Two fundamental EDA prediction tasks evaluate the effectiveness of the proposed CircuitNet 3.0. The timing prediction task takes RTL code as input to predict post-layout timing metrics (WNS, TNS, AT), enabling early-stage timing closure assessment. The power prediction task utilizes both RTL. and netlist representations to estimate circuit power consumption, facilitating power-aware de- sign optimization across abstraction levels. We evaluate against ttate--f-theeart baselines, including RTL-only models (MasterRTL (Fang et al. (2023), RTL-Timer (Fang et al. (0024), GRASPE (Rakesh) al. 2023). VIRTUAL (Lu et al.) (025)), netlist-only models (DeepSeq2 (Khan al. (024).
MOSS Wang et al. (025a) without mudii- learning), and our proposed multi--tage/mull-
modal approaches (RTLDistil (Wang et al.] (0226) for timing. MOSS (Wang et al.) 2025a) for power). Three dataset variants assess augmentation impact on Resyn-27k from RTLCCoder (Liu
et al. 2024), our original data, and augmented CireuitNet 3.0.
5.2 MULTI-STAGE AND MULTI-MODAL LEARNING SUPERIORITY
Table demonstrates the effectiveness of multi-modal representations compared to single-modal approaches. For timing prediction, RTLDistil employs cross-stage knowledge distillation between RTL and layout representations, achieving a PCC of 0.885 for anrival time prediction, a 70.4% im- provement over MasterRTL and 6.0% over RTL-Timer. WNS prediction achieves a PCC of 0.871 with a 28% MAPE, reducing the error by 45.8% compared to MasterRTI. TNS prediction at-
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Table 4: Performance comparison of multi-modal models.
(a) Timing prediction on RTL stage, where RTLDistil leverages multi stage knowledge distillation.
Arrival Time (AT)
WNS
TNS
Model
PCCT
MAPEL
PCC1
MAPEL
PCC1
MAPEL
MasterKTI.
0.520
43.25%
0.698
65.
0.593
68. 68.45%
KTL-TTmmer
0.835
26.48%
0.842
44.36%
0.801
43.92%
KTLDistil
0.887
19.72%
0.871
35.28%
0.918
40.15%
(b) Power prediction netlist stage, where MOSS demonstrates the effectiveness of multi-modaa learning.
Toggle Rate
Total Power
Model
PCCT
PCCT
MAPEЧ
DeepSoq2
0.739
29.5%
0.872
22.2%
MOSS w/o Multi-Modal learning
0.674
34.7%
0.815
27.7%
MOSS (Full)
0.871
14.4%
0.948
7.4%
Case power (mW))
Care whs
Case power
Case byout denaity
Case layout density
Case layout density
Case layout density
(a) Pre-Augment WNS (b) Post-Augment WNS (c) Pre-Augment Power (d) Post-Augment Power
Figure 6: Distributions of Worst Negative Slack (WNS) and Total Power across layout density cases before and after data augmentation.
(a) WNS distribution before augmentation and (b) after augmentation. (c) Power distribution before augmentation and (d) after augmentation.
Table 5: Comparison of RTL timing prediction across various datasets
Dataset
Model
Arrival Time (AT)
WNS
TNS
FCCT
R- f
MAPEL
FCCT
T
MAPEL
PCCT
T
MAPE]
MasterRTL.
0.465
-0.384
48.32%
0.612
0.217
73.45%
0.541
-0.127
72.38%
Resyn-27k
RTLTimer
0.762
0.567
31.65%
0.768
0.581
52.17%
0.743
0.529
49.85%
RILDisti
0,842
0.705
23.86%
0.825
0.676
40.73%
0.876
0,763
44,27%
MusterRTL.
0.520
0.216
43.25%
0.698
0.462
65.12%
0.593
0.184
68.45%
Original
RTT
0.692
26.48%
44.36%
0.801
43.92%
RTLDistil
0,887
0.785
19.72%
0.871
0.756
35.28%
0.918
0,841
40.15%
MasterRTT.
0.613
0.287
74%
0.752
0.549
58.65%
0.641
0.363
62.18%
Angmented Data
RTLTimer
0.873
0.760
22.35%
0.878
0.769
38.42%
0.843
0.707
39.67%
KTLDisti
0.935
0,863
15.28%
0.926
0.846
28.96%
0.968
0.927
35.42%
tains the highest PCC of 0.918, demonstrating superior capability in capturing cumulative timing violations. In the power prediction task, MOSS jointly processes RTT. code and netlist graphs, achieving toggle rate accuracy of 85.6% with PCC of 0.871, surpassing DeepSeq2 by 21.4% and single-modal MOSS by 31.1%. Total power prediction reaches 92.6% accuracy with PCC of 0.948, improving 19.0% over DeepSeq2. The ablation study confirms that incorporating RTL behavioral information with netlist structural features enables comprehensive power characterization by cap- turing both functional intent and gate-level switching activities. The substantial gains validate that layout-level physical information, when distilled into RTL-stage models through multi-granularig knowledge transfer, enables accurate early-stage predictions. This cross-stage paradigm effectively bridges the abstraction gap between behavioral descriptions and physical implementations.
5.3 DATA DISTRIBUTION ANALYSIS: PRE- AND POST-AUGMENIATION
Figure 6 visualizes how task-oriented augmentation transforms performance metric distributions. Pre-auge rre-augmentatiin timing characteristics exhibit limited diversity, with the WNS clustered between -2 ns and zero at high layout densities, with percentage greater than 94%. Post-augmentation, the dataset exhibits enriched timing diversity spanning -6 ns to zero across layout densities ranging from 86% to 100%, ensuring that models encounter comprehensive scenarios, from highly optimized to critically constrained designs. Power distribution similarly evolves from a limited variation con- centrated below 60 mW to uniform coverage ranging from zero to 160 mW. This diversification enables robust model training for range of power profiles, from ultra-low loweewwerr edge applications to high- sech-performacce computing applications. The expanded distributions confirm that augmentation successfully addresses the limited diversity in original datasets while maintaining design validity.
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5.4 PERFORMANCE ANALYSIS ON AUGMENTED DATA
Timing Prediction Enhancement. Table S demonstrates substantial improvements in timing pre- diction accuracy achieved through our task aask-orietted data augmentation strategy. All models consis- tently achieve superior performance on the augmented dataset across three critical timing metrics of AT, WNS, and TNS. MasterRTL. achieves PCC improvements of 31.9% of AT, 22.9% of WNS, and 18.5% of TNS compared to Resyn-27k data, with R² values transitioning from negative to positive, confirming the effective learning of timing relationships. RTL-Timer shows balanced gains with PCC improvements exceeding 13% across all metrics and MAPE reductions of from 20% to 29%. The RTLDistil attains state-of-thee of--off--tt-t--- performance on augmented data with PCC values of 0.935 AT, 0.926 WNS, and 0.968 TNS. The Rd values exceeding 0.85 indicate the model captures over 85% of timing variance, while achieving the lowest MAPE of 15.28% AT, 28.96% WNS, and 35.42% TNS, which represents 36.0%, 28.9%, and 20.0% improvements over Resyn-27k data. These con- sistent improvements across all models validate the effectiveness of our task-oriented augmentation strategy for enhancing timing prediction capabilities.
Power Prediction Enhancement. Tee veals substantial improvements in power pre- diction accuracy through our augmentation framework. All models achieve peak perfor- mance on the augmented dataset, establishing new benchmarks for RTL power analysis. The VIRTUAL attains best performance with PCC of 0.753, R² of 0.867, MAPE of 23.92% with 11.6%, 23.2%, and 12.9% improvements over Resyn-27k data. Additionally, GRASPE and MasterRTL. demonstrate significant gains with PCC improvements of 9 14%, R² improve- ments of approximately 30- 36,, and MAPE reduction of approximately 13 11%. The consis-
Table Comparison of RTL power prediction
across datasets.
Total Power
Dataset
Model
POCT
R²T
MAPE,
Graspe
0.642
0.655
30.41%
Resyn-27k
MasterRTL
0.609
0.620
32.67%
VIRTUAL
0.675
0.704
27.48%
Original
Graspe
0.671
0.845
28.45%
MasterRTI.
0.647
0.825
30.28%
Dataset
VIRTUAL
0.672
0.858
26.85%
Augmented
Graspe
0.701
0,850
26.55%
MasterRTI.
0.696
0.845
27. 16%
Dataset
VIRTUAL
0.753
0.867
23.92%
tently higher PCC and R² values, along with lower MAPE values, on augmented data, demonstrate that our augmentation strategy successfully creates more predictable power consumption patterns while preserving realistic design characteristics. These results validate the effectiveness of task- oriented augmentation for addressing critical data quality challenges power-aware circuit design.
Our evaluation demonstrates three key contributions. First, multi-modal models consistently out- perform single-modal baselines: on timing prediction, RTLDistil improves PCC by an average of 8.0% and reduces MAPE by an average of 18.2% across AT, WNS, and TNS relative to the strongest RTL-only baseline (RTL-Timer), demonstrating the efficacy of cross-stage information fusion. Sec- ond, task-oriented augmentation expands timing coverage from -6 ns to and power range from 0 mW to 160 W. while preserving design validity. Third, CircuitNet 3.0 enhances model general- ization in power prediction, with VIRTUAL trained PCC gain and a 12.9% MAPE reduction in total power compared with training on existing dataset. These results establish CircuitNet 3.0 comprehensive foundation for MI-driven EDA research.
augmented dataset, achieving 11.6%
6 CONCLUSION
We present CircuitNet 3.0, a comprehensive multi-stage multi-modal dataset designed for ML- driven EDA. Through systematic data collection and rigorous validation, the dataset comprises over 15,000 designs, along with corresponding netlists, layouts, and performance metrics, addressing the critical shortage of high-fidelity public data for AI4EDA. Experimental evaluation demonstrates multi-modal models trained on CircuitNet 3.0 achieve significant performance improvements over existing dataset baselines, with approximately 36.0% and 12.9% eтror reductions for timing and power tasks, respectively. The multi-stage design representation enables effective cross-abstraction information fusion, facilitating accurate early-stage prediction to guide early optimization. Task- oriented augmentation strategies successfully expand design diversity while maintaining EDA tool validation, extending timing coverage, and power ranges. This enhanced diversity enables robust model training and superior generalization across a wide range of design specifications and func- tions. As the first large-scale public benchmark for multi-modal circuit analysis, CircuitNet 3.0 establishes reproducible evaluation standards and accelerates collaborative research in ML-driven EDA tools and methodologies.

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ACKNOWLEDGEMENT
This paper is supported by the Chinese Academy of Sciences under grant No. XDB0660100, XDB0660102, and XDB0660103.
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SUPPLEMENTARY MATERIALS
APPENDIX A: THE PIPELINE OF DATA GENERATION AND PROCESSING
A. MULTI-STAGE EDA FLOW WITH ITERATIVE OPTIMIZATION
The construction of CircuitNet 3.0 employs a sophisticated multi-stage EDA flow utilizing com- mercial tools including Synopsys Design Compiler and Cadence Innovus. Unlike conventional approaches that rely on fixed tool configurations, our methodology implements an iterative opti- mization strategy to achieve industrial- -gaade design quality.
A.1.1 ITERATIVE OPTIMIZATION METHODOLOGY
Our iterative optimization framework, illustrated in Figure represents significant departure from traditional single-pass EDA flows. Each design undergoes multiple optimization iterations, where tool parameters are systematically adjusted based on convergence metrics. This approach ensures that the final layouts represent realistic industrial-quality implementations rather than artifacts of specific tool configurations.
The iterative process begins with RTL synthesis using Synopsys Design Compiler, where multiple synthesis strategies are explored through varying optimization directives. The synthesized netlists then proceed to Cadence Innovus for physical implementation. At each iteration, monitor three critical convergence indicators:
Design
Cadence Innovus P&R
RTL Design
Compiler
(.v files)
Synthesis
Not Converged
Parameter
Convergence Check
Converged
Final Design
Adjustment
Figure 7: Iterative optimization flow for dataset generation. The process continues until meeting convergence criteria across placement density, timing metrics, and power consumption.
For each design, automatically explore multiple parameter configurations, including:
Ranging from 85% to 95% placement utilization. Lower densities provide more optimization flexibility but may result larger die areas, while higher densi- ties challenge the routing algorithms and timing closure capabilities.
Density thresholds:
Routing constraints: Various congestion and optimization settings including layer assign- ment preferences, via minimization objectives, and antenna rule compliance strategies.
Clock constraints: Multiple timing scenarios from relaxed to aggressive, exploring clock periods from 10% above to 20% below the eritical path delay.
A. 1.2 CONVERGENCE CRITERIA
The optimization process continues until stringent convergence criteria met:
1. Placement density convergence: Density changes less than 0.5% between consecutive iterations, indicating that further cell movement provides negligible area improvement.
2. Timing stability: WNS and TNS metrics stabilize within 2% tolerance across three con- secutive iterations, ensuring timing closure reliability.
3. Power convergence: Total power consumption variations fall below 3% threshold, con- firming that power optimization has reached practical limit.
This iterative approach typically requires 10-50 iterations per design, with complex designs requir- ing more iterations to achieve convergence. The resulting dataset quality justifies the computational
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overhead each design represents practically optimized implementation comparable manually refined industrial flows.
1.1.3 QUALITY ASSURANCE
The iterative optimization process incorporates multiple quality checks:
Design rule checking (DRC) compliance: Each iteration verifies the remaining DRC vi-
olations in acceptable limits.
Layout versus schemati (LVS) correctness: LVS ensure maintaining the functional equiv- alence.
Timing closure: Setup and hold time violations are monitored to prevent timing degrada- tion.
Power integrity: drop and electron migration checks validate power distribution net- work robustness.
A.2 DATASET COLLECTION AND VALIDATION
A.2.1 SOURCE SELECTION STRATEGY
The dataset construction required approximately months of dedicated effort, reflecting the com- plexity of collecting, validating, and processing high-quality RTL designs. Our source selection strategy prioritized diversity and quality over quantity:
We systematically searched for repositories containing synthesiz- able Verilog or SystemVerilogg codes, focusing on projects with active maintenance, com- prehensive documentation, and proper licensing. Over 50, 000 repositories were examined, yielding more than 8, 000 suitable designs.
GitHub repositories:
OpenCores platform: As a dedicated hardware design repository, OpenCores provided hundreds of validated IP cores spanning various application domains. These designs often include testbenches and documentation, facilitating validation.
Hugging Face hardware collections: Emerging hardware design datasets on Hugging Face contributed more than 10, 000 designs, many featuring modern design patterns and coding styles.
RISC-V open-source projects: The RISC-V ecosystem provided hundreds of designs, including processor cores, accelerators, and peripheral controllers, representing state-of- the-art open hardware development.
A.2.2 DESIGN SELECTION CRITERIA
We specifically avoided over-reliance on traditional benchmarks (e.g., ISCAS-89, ITC-99) or large- scale CPU or GPU due to several limitations:
Limited diversity: Traditional benchmarks often contain similar circuit structures, limiting the diversity needed for robust MI model training.
Path duplication: Large designs like CPUs contain many structurally identical paths, lead- ing to dataset imbalance.
Outdated design styles: Many benchmark circuits use obsolete design patterns not repre- sentative of modern RTL development.
Instead, we prioritize the following criteria that designs meet:
Functional diversity: Selected designs span arithmetic units (adders, multipliers, di- viders), control circuits (FSMs, sequencers), data processing elements (encoders, decoders, FIFOs), and communication interfaces (UART, SPI, 12C).
Cireuit sizes range from simple combinational blocks (less than 200 gates) to complex subsystems (greater than 100, 000 gates), ensuring model exposure to varied optimization challenges.
Size variation:
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Logic
Design
Timing/Power
XGBoost
Prediction
Physical
GNN
Optimisation
Design
CNN
LLM
Multi stages /modalities
Models
Figure 8: Prediction tasks of timing and power closure through multi-stage and multi-modal de- sign representations. The framework demonstrates how different ML models (XGBoost for tabular features, GNN for graph structures, LLM for text processing, and CNN for layout images) can lever- age the multi-modal data from logic design to physical design stages for comprehensive timing and power optimization.
Modern coding practices:
Designs utilize contemporary RTL coding styles, including parameterized modules, generate statements, and System implementations.
Synthesis cleanliness: All designs pass synthesis without errors using commercial tools, eliminating problematic constructs that could bias training.
A.2.3 VALIDATION PIPELINE
Each collected design underwent rigorous validation:
Syntax verification: Initial parsing using open-source tools (Icarus Verilog, Verilator) to identify basic syntax errors.
2. Synthesis validation: Commercial synthesis using Synopsys Design Compiler with striet eтror checking enabled.
3. Simulation testing: Functional verification using provided test benches automatically generated test vectors.
4. Lint checking:
Static analysis to identify potential issues including combinational loops, unconnected ports, and synthesis-simulation mismatches.
5. Complexity analysis: Extraction of design metries including gate count, path depth, and sequential element ratio to ensure dataset balance.
This comprehensive validation process resulted in final collection of 8, 659 high-quality RTL. de- signs, representing approximately 8.7% of initially collected designs, highlighting our commitment to dataset quality over quantity.
A.3 MULTI-MODAL PREDICTION FRAMEWORK
The comprehensive validation process ensures that CircuitNet 3.0 provides high-quality data suitable for various machine learning approaches. Figure g illustrates how the multi-stage and multi-mode representations extracted from our dataset enable diverse ML models to perform timing and power prediction tasks.
The prediction framework leverages the multi-modal nature of CircuitNet 3.0:
Text Modality: RTL code and specifications processed through Large Language Mod- els (LLMs) to extract semantic features and design intent
Graph Modality: Both RTL operator graphs and gate-level netlists are analyzed using Graph Neural Networks (GNNs) to capture structural dependencies
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Image Modality:
Physical layout images processed through Convolutional Neural Net- works (CNNs) to extract spatial and geometric features
Tabular Features: Traditional MI models like XGBoost process extracted statistical fea- tures for rapid inference
This multi-modal approach enables models learn complementary representations across abstrac- tion levels, significantly improving prediction accuracy compared to single-modal baselines as demonstrated in our experimental results (Section 5.2).
APPENDIX B: ANALYSIS OF CIRCUIT CLASSIFICATION OF THE GENERATED
DATASET BY LLM
B.I CLASSIFICATION ARCHITECTURE
B.I.I SYSTEM OVERVIEW
Our classification system leverages the API of Claude Opus 4, a state-of-the-art language model, combined with expert validation achieve accurate and consistent circuit categorization. The sys- tem architecture incorporates multiple innovative components designed to maximize classification accuracy while minimizing computational costs.
The classification pipeline, formalized Algorithm implements a sophisticated multi-stage ap- proach.
Algorithm LLM--Based RTL Classification
Require: RTL code C, API key K
Ensure: Classification
result (category, subcategory, con con fidence)
structure + Extrac(CoodeStmuuuuee(()
2: cache key +- (6
then 4: return LoadFromCaacheecccce..ke
3: if CacheExistsscachhe
5: end if
6: prompt CreateExxperttrrmmpiC. structure)
7: result + CalLLLMAP((promptt K)
8: if result.con coaiit.coofidence
fidence < 0.7 then
9: verify prompt &- Create VerificatiooPPomppiCCCC result)
10: verificd CalILLMMAP(veerifuu (arppeeeeryypprrpppl pprompt, K)
11: if not verified.is icorert then
corrrec result verified
13: end if
end if
15: SaveToCCcheecachee key, result)
return resull
1.1.2 STRUCTURAL ANALYSIS ENGINE
Before invoking the LLM, our system performs a comprehensive structural analysis to extract key circuit characteristics. This pre-processing step serves multiple purposes:
Context reduction: By extracting relevant structural features, we reduce the token count required for LLM processing, improving efficiency and reducing costs.
Feature highlighting: Structural indicators guide the LLM's attention to classification- relevant patterns.
Consistency enhancement: Standardized feature extraction ensures consistent classifica- tion across similar designs.
The structural analysis examines multiple code aspects:
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Module hierarchy: Extraction of module names, port declarations, and instantiation pat- temss.
Signal patterns: Identification of clock signals, networks, and control paths.
Operational constructs: Detection of arithmetic operations, state machines, and memory structures.
Coding patterns: Recognition of design idioms indicative of specific circuit types.
B. 1.3 INTELLIGENT CACHING SYSTEM
To optimize API usage and ensure reproducibility, we implement a sophisticated caching mecha- nism:
Content-based hashing: Each RTL design is hashed using SHA-256, with the first 16 characters serving unique identifier
Persistent storage: Classification results are stored in JSON format, enabling cross-session persistence
Cache validation: Periodic cache cleaning removes outdated entries and validates stored results
This caching system reduced API calls by approximately 40% during dataset construction, signifi- cantly decreasing processing time and costs.
B.2 STRUCTURAL FEATURE EXTRACTION
B.2.1 COMPLEXITY INDICATORS
The classification system analyzes multiple structural indicators to inform the categorization pro- Table 7
presents the key patterns used for feature detection.
Table 7: Complexity Indicators for Classification
Indicator
Detection Pattern
has f'sm
(state STATE /nxt_staaee current.state)
has arithmetic
[+)-+/8] ([]a+:)a+)]] (a) [d+(] mmem| ram] rom)
has memory
has hos_tcunter has comparison
(count counter ent) (ntt)
[<>]=?|=>> =-!
Indicators serve as strong markers for circuit functionality:
FSM detection: The presence of state-related identifiers strongly indicates control logic, with 92% of FSM-containing circuits correctly classified in the Control..Squentiaal category.
Circuits with arithmetic operators predominantly fall into the Ari wwwetttetiii. Lclgic category, though their presence alone is insufficient for subcate- gory determination.
Arithmetic operations:
Memory structures: Two-dimensional arays and memory-related keywords reliably in- dicate Communi i C on_Memory circuits, particularly Memory/Register subcategories.
Counter patterns: Counter-related identifiers provide strong evidence for Counter/Timer classification within control. www.oooue.eneeeeeeoeeee
Comparison operations: While common across categories, comparison operators com- bined with other indicators help distinguish Comparator or Selector circuits.
B.2.2 PROMPT ENGINEERING
Our classification system employs carefully crafted prompts that leverage the LLM's understanding of hardware design patterns. The expert prompt includes:
Role definition: Establishing the LLM as senior RTL design expert with over twenty years of experience.
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2. Context provision:
Supplying extracted structural features and code snippets. 3. Category definitions: Clear descriptions of each category and subcategory with examples.
4. Classification instructions: Step-by-step guidance for analysis and categorization.
5. Output formatting: Structured JSON response format ensuring parseability.
B.2.3 CONFIDENCE- BAADSE BASED VERIFICATION
For classifications with confidence scores below 0.7, the system initiates a verification phase:
Secondary analysis:
verification prompt challenges the initial classification, asking the LLM to reconsider based on additional context.
Consistency checking: The verification process examines whether the assigned category aligns with detected structural features.
Expert override: Manual expert review is triggered for persistently low-confidence classi- fications, ensuring dataset quality.
This multi-stage approach achieved 94.3% agreement with human expert classifications, demon- strating the effectiveness of our LLM-b methodology.
B.3 CLASSIFICATION RESULTS
B.3.1 CATEGORY DISTRIBUTION ANALYSIS
The final classification results, presented in Table g reveal a well-balanced distribution across the
four main categories:
Table 8: RTL Classification Results
Main Category
Subcategory
Count
Percentage
Avg Confidence
Adder/Subtractor
645
7.5%
0.940
Multiplier/Divider
774
8.9%
0.920
Arithmetic Logic (23.6%)
ALU/Accumulator
519
6.0%
0.911
Others
114
1.3%
0.877
Counter Timer
906
10.5%
0.909
FSMM/equencer
392
4.5%
0.911
Sequetollequential (17.9%)
Control_Logic
242
2.8%
0.883
Others
0.1%
0.881
Comparator/Selector
1,453
16.8%
0.886
Encoder/Decoder
431
5.0%
0.917
Processin (29.9%)
FIFO/Buffer
407
4.7%
0.902
Others
292
3.4%
0.881
Memory/Register
1,061
12.3%
0.925
Bus Interffce
943
10.9%
0.917
Communication Memory (28.6%)
Serial Interface
445
5.1%
0.921
Others
27
0.3%
0.926
Total
8,659
100.0%
0.910
B.3.2 CATEGORY CHARACTERISTICS
Circuits within the same category exhibit distinctive structural and functional characteristies:
Arithmetic Logic Units (23.6%): These circuits implement mathematical operations and logical functions. The prevalence of multiplier/divider circuits (8.9%) reflects modern design requirements for DSP and Al accelerators. Notably, these circuits typically exhibit:
Deep combinational logic paths.
Regular data-path structures.
Minimal state elements relative to combinational logics.
Bit-width parameterization for reusability.
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ControL-Sequentee Circuits (17.9%): Dominated by counter/timer implementations (10.5%), this category encompasses circuits managing temporal behavior and control flow. Characteristic features include:
High ratio of sequential combinational elements.
Explicit state encoding and transitions.
Clock and reset sensitivity.
Control signal generation patterns.
Data Processing Units (29.9%): The largest category reflects the importance of data manipulation in modern designs. Comparat or or Selector circuits (16.8%) form the majority, indicating the prevalence peciiion-maainng logie. Common patterns include:
Moderate complexity with balanced sequential/coombinatooaal ratios.
Data steering and multiplexing structures.
Pipeline stages for throughput optimization.
Parameterized data widths and depths.
Communication. Memory (28.6%): This category spans storage elements and communication in- terfaces. The high proportion of memory/register (12.3%) and bus interface (10.9%) circuits reflects modern SoC architectures. Typical characteristics include:
Array structures for storage.
Protocol-specific state machines.
Synchronization logic for clock domain crossing.
Standardized interface implementations.
B.3.3 CLASSIFICATION QUALITY METRICS
The classification quality was validated through multiple approaches:
Inter-rater reliability: Three hardware design experts independently classified random sample of 500 designs, achieving 91.2% agreement with the LLM classification.
Synthesis statistics (gate types, timing characteristics) correlate strongly with assigned categories, validating the functional relevance of classifications.
Functional validation:
Cross-validation: Leave-one-out testing on category exemplars demonstrates 96.5% clas- sification consistency.
This categorization enables targeted augmentation strategies for each circuit type, ensuring that mu- tations preserve category-specific characteristics while introducing meaningful variations for robust model training.
APPENDIX C: AST-BASED MUTATION FRAMEWORK
C. MUTATION METHODOLOGY
C.I.1 OVERVIEW AST-BASED APPROACHI
Our AST-based mutation system represents a fundamental advancement over traditional text-based RTL modification approaches. By operating at the abstract syntax tree level, ensure syntactic validity while introducing semantically meaningful variations. The mutation process, formalized in Algorithm 2 leverages the hierarchical structure of Verilog code identify and transform specific language constructs systematically.
The AST approach offers several critical advantages:
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Algorithm 2 AST-Based RTL Mutation Process
Require: RTL code R. mutation count N
Ensure: Mutated RTL code R'
1: as! <
2: node_poths +- BuildNoodPPaths(ass))
3: mutations []
4: for each node in ast do
5: if IsMutable(node) then
6: candidates + Cediiaaaaaaanniaaddiiaeeenonnooo
7:
8: end if
9: end for
10: selected - -r-RandoSSmmmmmmtattinnsss N)
for each mutation in selected do
12: ast <- ApplyMutation((sst mutation)
CheckConnisteeey((sst))
14: end for
15: VeeTilooolog(s)))
16: if not PassesSynthesis((F)) then
17: return Apply Tepp, N)
18: end if
19: return R'
Syntactic guarantee: All mutations preserve the grammatical structure of Verilog, elimi- nating syntax errors that plague text-based approaches.
Semantic awareness: mantics.
Mutations respect scope rules, type constraints, and language se-
Targeted transformation: Specific node types can be selectively mutated based on their functional impacts.
Preservation of design intent: High-level design structure remains intact while low-level implementations vary.
C.1.2 NODE PATH CONSTRUCTION
A crucial innovation in approach is the node path construction mechanism. Each AST node is assigned a unique path from the root, enabling precise node location even after structural modifi- cations. The path consists of tuples (parent, attribute, index) that encode the traversal route:
Parent reference:
The parent node the AST hierarchy.
Attribute name: The attribute containing the child node (e.g., 'left', 'right',
sstatement
Index value: Position within list attributes (-1 for scalar attributes).
This path-based approach ensures that mutations be applied reliably even when the AST struc- ture changes during the mutation process, maintaining referential integrity throughout the transfor- mation pipeline.
1.3 MUTATION SELECTION STRATEGY
The mutation selection process balances diversity with validity through multi-criteria approach:
1. Node type filtering: Only nodes with defined mutation operators are considered.
2. Context validation: Mutations are filtered based on surrounding context (e.g. no arith- metic mutations in sensitivity lists).
3. Diversity maximization: Selected mutations span different node types and locations to ensure comprehensive coverage.
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4. Synthesis feasibility; Mutations likely to cause synthesis failures deprioritized.
The random sampling of N mutations from the candidate pool ensures that each generated variant explores a different aspect of the design space while maintaining functional validity.
C.2 MUTATION OPERATORS
C.2.1 OPERATOR CATEGORIES AND DESIGN RATIONALE
Table 9 presents our comprehensive mutation operator set, carefully designed to introduce realistic design variations while preserving synthesizability. Each operator category targets specific aspects of digital design:
Table 9: AST Mutation Operators and Constraints
Category
Original
Constraint
b
Type preservation
a b a a $ b a & b
+ b / b
Type preservation
Arithmetic
Non-zero divisor
+ b
Type compatibility
a b
Boolean context
Logical
b
Bit-width match
a a a >= b a
a & b
Bit-width match
b
Same operand types
<= b != b == b
Same operand types
Relational
Type compatibility
!= b
Type compatibility
( (posedge clk) q
(negedge clk)
Sequential blocks
Temporal
q= d
Always block consistency
8' d10
d'd11
Bit-width preservation
Constant
16' hFF
16'hFE
Base preservation
Arithmetic Operators: These mutations explore different mathematical relationships while main- taining type compatibility. The bidirectional nature of addition/subtraction mutations reflects com- mon design alternatives. Multiplication division mutations are constrained to prevent division- by-zero scenarios through static analysis of divisor ranges.
Logical Operators: Mutations between logical AND/OR operations model different decision logic implementations. Bitwise operator mutations (AND/ /OR/ XOR) explore alternative bit manipulation strategies commonly found in data processing circuits. The bit-width matching constraint ensures signal compatibility.
Relational Operators: These mutations model boundary condition variations critical for control logic. The systematic exploration of comparison operators (>, <, >=, <=, !=) ensures comprehensive coverage of decision boundaries in FSMs and control paths.
Temporal Operators: Edge mutations (posedge/ negedge) explore different clocking schemes, particularly relevant for interface circuits. Assignment type mutations (block aeckiing// non- blocking) model different hardware implementation strategies while always respecting block semantics.
Constant Mutations: Limited to #1 modifications, these mutations explore adjacent design points in the parameter space. The preservation of bit-width and base notation ensures that mutations remain within the original design constraints.
C.2.2 CONSTRAINT ENFORCEMENT MECHANISMS
Each mutation operator is accompanied by constraints that ensure the transformed code remains valid:
Type preservation: Ensures operand types remain compatible with operators.
Context awareness: Mutations respect their syntactic context (c.g., no blocking assign- ments in continuous assignments).
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Algorithm 3 Assignment Consistency Enforcement
Require: Always block A with assignments
Ensure: Consistent assignment types
1: assignments <- ExtractAsssinmeente
2: blocking_count +
3: nomblocking count <-
4: for each assign in assignaments do
5: if assign is KonblockingSubssttutinn then
6: nonblocking.com ccount + nonblocking.cmm _cunt + 1
7: else if assign is BlockingSubstitttinn then
8:
.count &- blocking .ounn +
9: end if
10: end for
if blocking count AND nonblocking count then
12:
if nomblocking.coount 2 blocking _cwuntt then
13:
target.type +- nonblocking
14:
else
15:
target.type t- blocking
16: end if
17:
ConvertAllAssigmmnnt(AA. target type)
18:
end if
Semantic validity: Transformations maintain semantic correctness (e.g.. no mixed assign- ments in always blocks).
Synthesis compatibility: Mutations avoid constructs known to cause synthesis issues.
C.3 ASSIGNMENT CONSISTENCY ENFORCEMENT
C.3.1 MIXED ASSIGNMENT PROBLEM
A critical challenge in RTL mutation is maintaining assignment consistency within always blocks. Verilog's distinction between blocking (-) and non-blocking (<=) assignments has profound impli-
cations for synthesis results. Mixed assignments within single always block can lead to:
Race conditions: Unpredictable behavior due to simulation/synthesis mismatches.
Synthesis warnings/errors: Many synthesis tools reject mixed assignments.
Unrealistic designs: Mixed assignments rarely appear in professional RTL code.
C.3.2 CONSISTENCY ALGORITHM
Algorithm implements our solution to the mixed assignment problem:
The algorithm employs a majority-rule approach: when mixed assignments are detected, all assign- ments are converted to the predominant type. This strategy:
Preserves design intent: The majority type likely represents the designer's intended style.
Minimizes changes: Fewer assignments require modification.
Maintains functionality:
The conversion preserves logical behavior while ensuring syn-
thesis compatibility.
C.3.3 IMPLEMENTATION DETAILS
The assignment conversion process handles several edge cases:
Nested blocks: Assignments within nested begin-end blocks are tracked recursively
Case statements: Assignments within case branches are included in the consistency check.
Conditional assignments: If-else structures are traversed ensure complete coverage.
Generate blocks: Dynamically generated assignments analyzed the AST level.
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Density Comparison: Original Augmented Data
WNS Comparison: Original Augmented
98
0.0
Notru: $7.00
Mikuut 92.44
96
Deasily (%)
WNS (as)
92
-1.5
40.8 5003311
Moai sul
96
2.0
Original
Augmented
Original
Augmented
(a) Layout Density Distribution
(b) Worst Negative Slack Distribution
INS Comparison: Original vs Augmented Data
Power Comparison: Original vs Augmented Data
Sad 2021
Power (ma))
TNS (mx)
-30
-40
-90
10-
Mow lul PooM
5-
-70
Original
Augmented
Original
Augmented
(c) Total Negative Slack Distribution
(d) Power Consumption Distribution
Figure 9: Distribution comparison of key metrics before and after augmentation. The box figures show median (center line), quartiles (box edges), whiskers (1.5 IQR), and outliers (individual points) for each metric. Original distributions (left) show limited diversity, while augmented distributions (right) demonstrate significantly enhanced coverage.
This comprehensive approach ensures that the mutated RTL maintains professional coding standards while exploring meaningful design variations.
APPENDIX D: DATASET DISTRIBUTION ANALYSIS
D.1 PRE- AND POST-AUGMENTATION DISTRIBUTIONS
D. VISUAL DISTRIBUTION ANALYSIS
Figure provides a comprehensive visualization of how our augmentation strategy transforms the dataset characteristics across four critical metrics. The box figure representation enables direct com- parison of distributional properties, revealing the substantial improvements in dataset diversity and coverage.
D.1.2 DENSITY DISTRIBUTION ENHANCEMENT
The layout density distribution (Figure ((a) reveals fundamental transformation in placement characteristics:
Original dataset: Highly concentrated around 87% to 89%, reflecting default tool behavior with minimal optimization variations.
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Augmented dataset: Spans 85% to 100% with increased presence of outliers, representing diverse optimization scenarios from relaxed to extremely constrained placements.
Upper quartile expansion: The 75th percentile shifts from 89.5% to 93.2%, indicating successful generation of high-density designs.
This expansion is crucial for training robust models that can handle both conservative and aggressive placement strategies encountered in industrial settings.
1.1.3 TIMING DISTRIBUTION ANALYSIS
The timing metrics (WNS and TNS) show complementary improvements:
Worst Negative Slack (Figure 9b)
Range expansion: From |-2.5, 0) ns to 1-6, 0] ns, covering more critical timing scenarios.
Increased variance: Standard deviation grows by 52%, providing richer training data.
Outlier generation: More extreme negative slack values represent challenging timing clo-
sure cases.
Total Negative Slack (Figure 9(c)
Distribution shape: Transforms from highly skewed to more symmetric, indicating bal- anced representation of timing violations.
Median shift: From -8.71 to 11.996 ns, reflecting realistic timing challenges.
Reduced extreme outliers: While maintaining diversity, the augmentation avoids unreal- istic TNS values.
D. POWER DISTRIBUTION TRANSFORMATION
The power consumption distribution (Figure (d) undergoes the most dramatic transformation:
Skewness correction: Original heavily right-skewed distribution (mean/median ratio:
2.65) becomes more balanced (ratio: 2.31).
Coverage expansion: From concentrated low-power designs comprehensive coverage up to 160mW.
Quartile redistribution: Interquartile range increases from 8.2mW to 15.3m providing better representation of medium-power designs.
D.2 STATISTICAL SUMMARY
D.2.1 QUANTITATIVE ANALYSIS
Table 10 provides precise statistical measurements confirming the visual observations:
Table 10: Distribution Statistics: Original vs Augmented Dataset
Original Median
Augmented Median
Metric
Mean
Std
Mean
Std
Density (%)
88,49
87.58
3.16
90.75
90.84
3.63
WNS (ns)
-0.88
-0.49
2.31
-1.20
-0.59
3.51
TNS (ns)
-42.17
-8.71
256.04
-41.69
-11.96
200.60
Power (mW)
12.92
4.88
23.00
18.14
7.85
29.21
D.2.2 STATISTICAL INSIGHTS
The statistical analysis reveals several key improvements:
Variance Enhancement:
Density: 22% increase in standard deviation while maintaining realistic bounds.
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WNS: 52% increase in variability, crucial for timing prediction tasks.
Power: 27% increase in standard deviation with better mean-median alignment.
Distribution Balance:
TNS: Reduced standard deviation (22% decrease) indicates removal of extreme outliers while maintaining diversity.
Power:
Although the mean-median difference increases from 8.04 mW 10.29 mW, the meeantoo-ediial ratio decreases from 2.65 to 2.31, indicating reduced skewness and more balanced power distribution.
Central Tendency Shifts:
All metrics show meaningful shifts central values, indicating successful generation of diverse operating points.
Median changes are more moderate than mean changes, suggesting controlled augmenta- tion without extreme bias.
D.3 DISTRIBUTION ENHANCEMENT ANALYSIS
D.3.1 COMPREHENSIVE IMPACT ASSESSMENT
The augmentation process achieves multiple objectives critical for ML model training:
range from 87% 89% to broad range from 85% to 100% coverage enables models to learn placement strategies across the entire feasible spectrum. This diversity is essential for:
Density: The expansion from
Handling various design constraints in industrial applications.
Learning trade-offs between area efficiency and routability.
Generalizing to different technology nodes with varying density limits.
Timing (WNS): The 52% increase in standard deviation (2.31 to 3.51 ns) while maintain- ing realistic timing values ensures:
Exposure both timing-critical and relaxed designs.
Better calibration of timing prediction models.
Improved handling of edge cases in timing closure.
Timing (TNS): The more balanced distribution with reduced skewness provides:
Better coverage of cumulative timing effects.
Reduced bias toward designs with minimal violations.
Improved learning of system-wide timing impacts.
Power: The transformation from heavily right-skewed (median 4.88mW, mean 12.92mW) to more balanced distribution (median 7. 7.85m W, mean 18. 1)mW) enables:
Accurate power modeling across diverse design styles.
Better representation of modern low-power and high-performance designs.
Reduced model bias toward low-power circuits.
D.3.2
BENEFTTS
The distribution enhancements directly benefit specific EDA tasks:
For Timing Prediction:
Wider WNS range improves model robustness to timing variations.
Balanced TNS distribution enables better multi-path timing analysis.
Density diversity teaches sencemennt-iiinggg correlations.
For Power Prediction:
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Comprehensive power range covers edge-to-cloud applications.
Improved distribution symmetry reduces prediction bias.
Density-power correlation learning from diverse samples.
D.3.3 VALIDATION OF AUGMENTATION QUALITY
The augmented distributions maintain several critical properties:
Physical feasibility: All values remain within realizable bounds for the target technology.
Correlation preservation: Inter-metric correlations (e.g., density-timing remain consis- tent with physical principles.
Industrial relevance: Distribution ranges align with real-world design specifications.
These enhancements collectively ensure that models trained on CircuitNet 3.0 encounter compre- hensive design scenarios, ranging from highly optimized critically constrained cases, thereby improving their generalization capability for industrial applications. The careful balance between diversity expansion and realistic constraint maintenance distinguishes augmentation approach from random perturbation methods, resulting in a dataset that truly advances the state-of-the-art in ML-driven EDA research.
APPENDIX E: INDUSTRIAL-GRADE PHYSICAL IMPLEMENTATION METHODOLOGY
E.I TECHNOLOGY FOUNDATION AND DESIGN PREPARATION
E.I.I COMMERCIAL PDK INTEGRATION
The physical implementation of CircuitNet 3.0 leverages the GSCLIB 45nm commercial Process Design Kit (PDK), providing industrial-grade accuracy for layout generation and performance char- acterization. This mature technology node ensures realistic parasitic effects and manufacturing con- straints essential for training robust ML models. The PDK configuration encompasses:
Standard Cell Library: GSCLIB04S with comprehensive cell variants including combi- national logic (e.g.. INVXI-X8, BUFXI-XI6. AND/OR/NAND/NOR gates with multi- ple drive strengths), sequential elements (e.g., DFFHQXI-XXX complex cells (e.g., MUX, XOR), and
Technology Files: Complete LEF abstracts (gscl (gsclib045 10:00455tcchhh lef, gsclib045.
f fixed2. 1) defining physical geometries, pin locations, and routing obstructions
Parasitic Models: QRC technology files calibrated for accurate resistance and capacitance extraction across 11 metal layers
Timing Libraries: Multi-corner characterization at typical conditions with comprehensive setup/hold timing models
E. 1.2 NETLIST FLATTENING STRATEGY
To ensure consistent optimization and analysis across diverse design complexities, all synthesized netlists undergo hicrarchical flattening before physical implementation:
set flatten true -effort high ungroup -all -flatten compile_ultra
This flattening approach eliminates hierarchical boundaries, enabling:
Global optimization opportunities across module boundaries
Uniform timing analysis without hierarchy-induced pessimism
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Consistent power grid distribution across the entire design
Standardized parasitic extraction and analysis methodologies
The flattened netlists are filtered based structural characteristics to ensure design quality:
Minimum instance count threshold: 200 gates
Combinational to---t-----sse to-sequential ratio: 5 < ratio < 10,000
These constraints eliminate trivial or structurally imbalanced designs
E.2 SCALABLE POWER DISTRIBUTION NETWORK
E.2.1 ADAPTIVE PDN ARCHITECTURE
The power distribution network implementation employs a systematic approach with layer-specific parameters optimized for different current-carrying requirements:
sayer-specifie stripe generation with progressive sizing
addStripe -nets (VSS VDD) -layer Metal2 direectoo vertical \
-width 0.2 -spacing 0.8 -set_to_seet set set_ se__seettttaeneeeeee___sssssss_e addStripe -nets (VSS VDD) -layer Metal3 -direction horizontal \ -width 0.2 -spacing 0.8 -set_to_set_distaee
addStripe -nets (VSS vDD) -layer Metal4 -direction vertical \
-width 0.4 -spacing 0.8 -set_to_set_ cettttoss_dsssttte _iettnce
... continuing through Metal10 with increasing dimensions
The multi-layer PDN architecture implements:
Standard cell layer (MI): Reserved for intra-cell routing and local power rails
Lower distribution layers (M2-M3): Fine-pitch stripes (0.2um width, 6μm pitch)
Intermediate layers (M4-M7): Medium-pitch stripes (0.4pm width, 6-8pm pitch)
Upper layers (M8-M10): Wide stripes (1.0pm width, 10am pitch) for global distribution
Pad connection layer (M11): Top-level power/ground pad connections
F.2.2 VIA INSERTION AND CONNECTIVITY
Comprehensive via insertion ensures robust vertical connectivity:
foreach layer_ idx $PG_ ses__strie__a_____
idx {
editSelect -layer Metal$layer idx -net (VDD VSS}
editPowerVia seetween_seleeted_wieeeee -add_vias 1 -top_layer Stop_layer
-nets (VDD vSS \
E.3 AUTOMATED PHYSICAL OPTIMIZATION FLOW
E.3.1 PLACEMENT OPTIMIZATION
The placement stage employs Cadence Innovus's advanced optimization algorithms with industrial- grade settings:
set.laceMode
detormddeesttyyy true \
true
place_opt_design -place
setOptMode -ixDre false -addInst true -deleteInst false \
-moveInst true -downsizeInst true optimizeFF true -maxDensity 0.7
optDesign -preCTS
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Key optimization techniques include:
Progressive Density Control: Staged utilization targets 70% (placement), 80% (CTS), 95% (routing) providing optimization headroom at each stage
Position Exchange: Iterative cell swapping for wirelength and timing improvement
Density Control: Target utilization of 60-70% for pre-CTS optimization headroom
Instance Prefixing: Systematic naming (PLC. prefix) for tracking optimization history
E.3.2 CLOCK TREE SYNTHESIS
Clock tree implementation with useful skew optimization:
setOptMode
true stsefull www.ffllleeecottttcc standard
-maxenniity 0.8
ccopt_design optDesign -postCTS
E.3.3 ROUTING AND POST-ROUTE OPTIMIZATION
Advanced routing with comprehensive optimization:
SetNannRRuteMMoee -route@Wtthriiiinggiiieee true
dioote@Pottooottsppreeddiie true dbrotcePPssttoouueeed.ddddiiirr true routeDesign -globalDetail
setOptMode -fiDDre true -addInst true -moveInst true -dwnsizeenns true -optimizeFF true -maxDensity 9. optDesign in -postRoute -setuu ecoRoute -fix_drc
Optimization capabilities include:
Gate Sizing: Dynamic adjustment across multiple drive strength variants (typically XI, X2, X4, X8) per cell type
Buffer Insertion/Deletion:: Automated buffer tree optimization for timing closure
Wire Spreading/Widening: Post-route enhancements for signal integrity
DRC Fixing: Automatic violation repair with ECO routing
Density Target: Up to 95% utilization for arca-efficient implementations
E.4 PERFORMANCE CHARACTERIZATION AND LABEL GENERATION
E.4.1 TRAPH-BASED STATIC TIMING ANALYSIS
Post-routing timing characterization employs graph- STA for comprehensive path analysis:
Extract detai led timing after routing completion
cimeDesign -postRoute -pathReports -slackReports -numPaths 100 -prefix postRoute_setup
Hold time analysis and fixing setOptMode -holdTargetSlack 0.05 optDesign -postRoute hhold timeDesign -postRoute -hold -pathReports -slackReports
The STA engine generates (implemented in post-processing scripts):
Arrival Time (AT); Accurate signal propagation delays including wire parasitics
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Worst Negative Slack (WNS): Critical path timing margin after optimization
Total Negative Slack (TNS): Cumulative timing violations across all endpoints
Setup/Hold Reports: Comprehensive timing closure verification
E.4.2 PARASITIC EXTRACTION WITH QUANTUS RC
High-fidelity parasitic extraction using Cadence Quantus RC technology:
setExtracttRMooe -engine postRoute -effortieeel high -coupling_c_th 003
extractRC
reOut -spef design.spef
Extraction parameters ensure:
Coupling capacitance threshold: 3fF for crosstalk aware analysis
High effort level for detailed metal and via modeling
SPEF generation downstream power analysis integration
E.4.3 VECTORLESS POWER ANALYSIS WITH STATISTICAL PROPAGATION
Dynamic power characterization through vectorless activity propagation:
set _et_pover_amalysis_nnoo
-method vector_free analysis_viee _vwew typical -input_activife 0.2 -period 10. Ons
set_ htr__eefanl__swithhhnn_eccoo
propagate_activvity report__cwer -hierarchy -threshold 0.01
Power analysis methodology:
Activity Propagation: Statistical switching activity propagation through combinational logic
Toggle Rate: Default 20% switching activity for realistic power estimation
Hierarchical Reporting: Instance-level power breakdown for detailed analysis
Dynamic Power: Paymamic = a Ceff VīD with extracted parasitics
E.5 QUALITY ASSURANCE AND VALIDATION
E.5.1 DESIGN RULE COMPLIANCE
Comprehensive DRC verification ensures manufacturing readiness:
verify_dre -limit 10000 -type all -noAntenna
checkPlace -noPreplace
E.5.2 DATASET QUALITY METRICS
Each generated layout undergoes rigorous quality assessment, shown in Table
Note: The 96.8% timing closure rate reflects our intentional inclusion of challenging designs near timing limits, providing valuable training cases for ML models targeting critical-path scenarios.
E.5.3 INDUSTRIAL RELEVANCE VALIDATION
The physical implementation methodology ensures:
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Table 11: Physical Implementation Quality Metrics
Metric
Target
Achieved
Placement Density
60-95%
88.3% (avg)
DRC Violations (post-fix)
0
0
Timing Closure Rate
>> 95%
96.8%
Power Correlation (dt²)
> 0.9
0.92
Routing Congestion
< 8.5%%
78.5% (avg)
Tool Compatibility: Scripts compatible with Synopsys DC 2020.09 and Cadence Innovus 19.11
Process Portability: Adaptable to different technology nodes through PDK abstraction
Optimization Depth: Multiple optimization stages matching industrial tape-out flows
Label Accuracy: training
Post-layout labels incorporating all physical effects for realistic MI.
This comprehensive methodology ensures CircuitNet 3.0 provides industrially relevant physical im- plementations with accurate performance characterization, enabling robust ML model training for real-world EDA applications. The systematic approach from synthesis through post-route optimiza- tion mirrors commercial design flows, ensuring trained models can generalize to industrial design challenges.
APPENDIX F: DETAILED EXPERIMENTAL SPECIFICATIONS FOR REPRODUCIBILITY
To ensure full reproducibility of all experimental results reported in this paper, this appendix consol- idates the complete experimental specifications, including process technology, operating conditions, EDA tool configurations, and machine learning training settings. These details complement the physical implementation methodology described in Appendix E and address the specific require- ments raised during the review process.
F.1 PROCESS TECHNOLOGY AND OPERATING CONDITIONS
All designs in CircuitNet 3.0 are implemented using single, consistent process technology and operating condition, summarized in Table [2]
Table 12: Process Technology and Operating Conditions
Parameter
Specification
Technology Node
45 nm CMOS
Process Design Kit (PDK)
GSCLIB 45nm (commercial-grade)
Standard Cell Library
GSCLIB045
Technology LEF Files
gsclibe Seclib045_teed 1ef, gsclib045. fixed2. lef
Metal Stack
11 metal layers
Parasitic Model
QRC technology file (calibrated for nm)
PVT (Proess-Volagg--eeppruurr Corner
Process Corner
TT (Typical-Typical)
Supply Voltage (VnD)
1.05
Temperature
85
Clock Specifications
Target Clock Frequency
GHz
Target Clock Period
1.0
Clock Uncertainty
Tool default (auto-computed by CTS)
Hold Target Slack
0.05 ns
We chose the GSCLIB 45 nm commercial PDK for two primary reasons. First, reproducibil- ity and openness: advanced technology nodes (c.g.. TSMC 7/5 nm) are subject to strict non- disclosure agreements, making it impossible to release physical design data (GDSII, DEF, SPEE,
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etc.) openly. The GSCLIB 45 nm PDK enables full transparency of all design artifacts while maintaining catustrial-grade accuracy in parasitic modeling and timing characterization. We did not adopt purely academic emulation PDKs (e.g., FreePDK45) because the GSCLIB library pro- vides more realistic standard cell characteristics and a richer set of cell variants with multiple drive strengths. Second, technology independence: the entire CircuitNet 3.0 pipeline from synthesis scripts to physical implementation and feature extraction-is not tied to this specific technology node. Users with access other PDKs can substitute their own technology files and rerun the flow using the same scripts, enabling the methodology to generalize across technology nodes.
For the data augmentation stage described in Section 4.4, the clock period is systematically varied to explore multiple timing scenarios. Specifically, we explore clock periods ranging from 10% above to 20% below the critical path delay of each design, generating designs under both relaxed and aggressive timing constraints. This variation enriches the timing diversity of the dataset (as shown Figure 6) while maintaining physical feasibility.
F.2 EDA TOOL CHAIN SPECIFICATIONS
The complete EDA tool chain used for dataset generation and ground-truth label extraction is sum- marized in Table 13 All tools are commercial-grade, ensuring that the generated designs and per- formance metrics are representative of industrial practice.
Table 13: EDA Tool Chain and Version Information
Tool
Version
Purpose
Synopsys Design Compiler
2020.09
Logic synthesis
Cadence Innovus
19.11
Physical implementation (P&R)
Cadence Quantus RC
bundled with Innovus 19.11
Parasitic extraction
Synopsys PrimePower
compatible with DC 2020.09
Power signoff (ground-truth labels)
Cadence Voltus
bundled with Innovus 19.11
Vectorless power analysis (data filtering)
Icarus Verilog
11.0+
RTL compilation verification
PyVeilog
1.3.0
Verilog AST parsing and code generation
The roles of the power analysis tools are distinguished as follows. Cadence Voltus employed during the data augmentation and filtering stage (Section 4.4) to perform vectorless dynamic power analysis for identifying and excluding circuits with large fractions of inactive or unreachable logic. Synopsys PrimePower is used for the final ground-truth power label generation (Section 5.1), pro- viding signoff-quality power estimates that serve as prediction targets for ML models.
F.3 LOGIC SYNTHESIS CONFIGURATION
leppllleuttrrr All RTL designs are synthesized using Synopsys Design Compiler with the compi eeultr ra op- timization directive, which enables advanced area, timing, and power optimizations including auto- matic ungrouping, boundary optimization, and adaptive retiming. The detailed synthesis configura- tion is summarized in [4
Table 14: Logic Synthesis Configuration
Parameter
Setting
Synthesis Command
compile.ultra set_flatten true -effort high ungroup -all -flatten GSCLIB045 (TT, 1.05 85 1.0 (default); varied per augmentation Ultra (highest)
Flattening Strategy
Ungrouping
Target Library
Clock Period Constraint Optimization Effort
The hierarchical flattening strategy (set.flatter true followed by ungroup -all flatten) eliminates module boundaries before optimization, enabling global optimization op- portunities across the entire design. This ensures that the synthesized netlists represent fully opti- mized implementations comparable to industrial tape-out quality, rather than artifacts of hierarchical boundary constraints.
For the weweer-tak--orintte data augmentation (Section 4.4, Figure 5(c)), multiple synthesis config- urations explored for each RTL design by varying optimization directives and constraints (e.g..
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different clock periods, area vs. timing trade-offs). This generates functionally equivalent but struc- turally distinct netlist variants, capturing the impact of synthesis choices on power characteristics.
F.4 PHYSICAL. IMPLEMENTATION CONFIGURATION
Physical implementation is performed using Cadence Innovus with an iterative optimization flow, as described in Appendix A.I. Table 13 summarizes the key configuration parameters at each stage
of the physical design flow.
Table 15: Physical Implementation Configuration
Stage
Parameter
Setting
Uniform Density
true
Placement
IO Pin Placement
true (automatic)
Max Density (pre-CTS)
0.70 (70%)
Useful Skew Optimization
true (standard mode) 0.80 (80%)
Clock Tree Synthesis
Max Density (CTS)
CTS Engine
ccopt_design
Timing- Driven Routing
true
Routing
Post-Route Wire Spreading
true
Post-Route Wire Widening
true
Routing Mode
Global + Detailed
DRC Fixing
true
Instance Addition
true
Post-Route Optimization
Instance Movement
true
Instance Downsizing
true
Max Density (post-route)
0.95 (95%)
Explored Range
85%-95% placement utilization
Density Exploration
Timing Exploration
10% above to 20% below critical path
Typical Iterations
10-50 per design
The progressive density control strategy- -70 at placement, 80% CTS, and 95% at post-route provides sufficient optimization headroom at each stage while maximizing final area utilization. The iterative optimization process (Appendix 1) continues until three convergence criteria simul- taneously satisfied: (1) placement density changes less than 0.5% between consecutive iterations, (2) WNS and TNS metrics stabilize within 2% tolerance across three consecutive iterations, and (3) total power consumption variations fall below 3% threshold.
F.4.1 POWER DISTRIBUTION NETWORK CONFIGURATION
The power distribution network (PDN) is implemented with multi-layer architecture optimized for current-carrying requirements at each metal level, as detailed in Table I6
Table 16: Power Distribution Network Layer Configuration
Metal Layer
Direction
Width (pm)
Spacing (ęm)
Pitch (μm)
MI (std cell)
Horizontal Vertical
Reserved for intra-cell routing
M2
0.2
0.8
M3
Horizontal
0.2
0.8
6
M4
Vertical
0.4
0.8
M5-
Alternating
0.4
0.8
6-8
M8-M10
Alternating
1.0
10
M11
Top-level pad connections
F.5 TIMING ANALYSIS AND SIGNOFF CONFIGURATION
graph-based Post-route timing characterization employs graph based static timing analysis (STA) within Cadence Innovus, supplemented by parasitic extraction using Cadence Quantus RC. The complete timing analysis configuration is summarized in Table
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Table 17: Timing Analysis and Parasitic Extraction Configuration
Parameter
Setting
Static Timing Analysis
Analysis Mode
Post-route (setup and hold)
Number of Critical Paths Reported
100
Hold Target Slack
0.05 ns
Report Prefix
postRoute.setup
Parasitic Extraction (Quantus RC)
Extraction Engine
Post-route
Effort Level
High
Coupling Capacitance Threshold
ffF (0.003)
Output Format
SPEF
Ground Truth Timing Metrics
Arrival Time (AT) Worst Negative Slack (WNS) Total Negative Slack (TNS)
Signal propagation delay including wire parasitics Critical path timing margin after optimization Cumulative timing violations across all endpoints
The high-effort parasitic extraction with a 3 fF coupling capacitance threshold ensures accurate mod- eling of crosstalk effects, which is critical for timing accuracy the 45 node. The extracted SPEF files are subsequently used for both timing signoff and power analysis.
F.6 POWER ANALYSIS CONFIGURATION
Power analysis in CircuitNet 3.0 serves two distinct purposes, each employing a different tool and configuration, summarized in Table [8
Table 18: Power Analysis Configuration
Parameter
Data Filtering (Voltus)
Ground Truth (PrimePower)
Purpose
Augmentation filtering
Label generation
(Section 4.4)
(Section 5.1) Vectorless
Analysis Method
Vectorless
Analysis View
Typical
Typical
Default Toggle Rate (a:)
0.2 (20%)
0.2 (20%)
Switching Period
10.0
10.0
PVT Corner
TT, 1.05 V, 85 CC
TT. 1.05 85 "C
Parasitic Data
Post-route SPEF
Post-route SPEF Enabled
Hierarchy Reporting
Enabled (threshold 0.01)
The vectorless power analysis methodology is deliberately chosen the canonical power estima- tion approach for CircuitNet 3.0. With a uniform toggle rate of 0.2 applied to all primary inputs, the analysis effectively approximates average switching activity across many random input scenarios, rather than depending on specific hand-crafted testbench. This design choice ensures that the re- ported power differences across designs primarily reflect structural fartorr factors-such as logic topology, load capacitance, and combinational depth-rathhr than arbitrary differences in input stimuli. The dynamic power for each gate computed as:
Paynami a f Ceff ViD::
where a = 0.2 is the switching activity factor, f is the clock frequency (1 GHz), Car is the effective capacitance extracted from post-route parasitics, and VOD 1.05 V.
worth noting that CircuitNet 3.0's infrastructure fully compatible with vector-based power analysis. The per-gate toggle rate annotations support user-provided simulation-derived activity factors, enabling future work on workload-ave power modeling.
F.7 DESIGN QUALITY FILTERING CRITERIA
To ensure that all designs CircuitNet 3.0 are of sufficient quality and complexity for meaningful MI model training, apply the filtering criteria summarized in Table T9
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Table 19: Design Quality Filtering Criteria
Criterion
Threshold
Rationale
Minimum Gate Count
2 200 gates
Exclude trivially small designs
Comb./Seq. Ratio
5 < ratio 10,000
Exclude structurally imbalanced designs
DFF Ratio
25%
Exclude overly sequential/trivial designs
Synthesis Status
Pass (no errors)
Ensure synthesizability
Simulation Status
Pass (functional)
Ensure functional correctuess
Combinational Loops
None
Prevent synthesizable structures
Inactive Logic Fraction
Low (Voltus check)
Exclude designs with unreachable logic
Augmented Design Filtering
Structural Similarity
< 97% (graph comparison)
Prevent near-duplicate designs Aggressive quality filtering
AST Mutation Acceptance Rate
27%
For augmented designs, approximately 73% of AST-mutated variants are discarded during the filter- ing process. Only variants that (1) synthesize cleanly, (2) pass compilation-base verification, and (3) contribute non-redundant structural and PPA diversity are retained.
F,8 MACHINE LEARNING EXPERIMENTAL CONFIGURATION
All ML experiments in Section are conducted under the unified configuration summarized in Table 20
Table 20: Machine Learning Training Configuration
Parameter
Setting
Hardware
GPU
8x NVIDIA A100 GBOGB)
Software Framework
Deep Learning Framework
PyTorch 2.0.1
Graph Learning Library
PyTorch Geometric 2.3.1
Training Hyperparameters
Optimizer Learning Rate
AdamW
2 x 10-4
Learning Rate Schedule
Cosine annealing
Maximum Epochs
50
Early Stopping
Based on validation loss
Dataset Partitioning
Training Set
80%
Validation Set
10%
Test Set
10%
Split Strategy
Source design level
Test Set Composition
Exclusively original (un-augmented) designs
Data Leakage Prevention
All augmented variants of test designs excluded from training and validation
External Test Supplement
Submodules from open- sourcs projects not used
training (verified via netlist-level graph comparison)
Evaluation Metrics
Correlation
Pearson Correlation Coefficient (PCC)
Goodness of Fit Error
Coefficient of Determination (R²) Mean Absolute Percentage Error (MAPE)
The dataset is partitioned at the source design level to prevent information leakage: source design is allocated to the test all of its augmented variants entirely excluded from the training and validation pools. The test set further supplemented with submodules from external open- source projects that wholly excluded from the training partition. We verify via netlist-level
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graph comparison that synthesized netlist in the test set is structurally identical to any design in the training or validation sets.
F.9. SUMMARY OF KEY SPECIFICATIONS
For quick reference, Table 21 consolidates the most critical experimental specifications that define the evaluation conditions for all results reported in this paper.
Table 21: Summary of Key Experimental Specifications
Specification
Value
Technology Node
45 nm CMOS (GSCLIB)
Process Corner
TT Sypical-Typpcal)
Supply Voltage (VDD)
1.05
Temperature
85
Target Clock Frequency
1 GHz (period = 1.0 ns)
Switching Activity (Toggle Rate)
0.2 (20%)
Synthesis Tool
Synopsys DC 2020.09 (compile.ultra)
P&R Tool
Cadence Innovus 19.11
Power Signoff Tool
Synopsys PrimePower
Parasitic Extraction
Cadence Quantus RC (high effort, 3 fF threshold) 85%-95% (88.3% average achieved)
Placement Density Range
Timing Closure Rate
96.8%
35


Reviews:
[{"review_id": "1ymMLD8Bfj", "reviewer": "Reviewer_cZe1", "summary": "CircuitNet 3.0 is presented as a large-scale, open-source, multi-modal, multi-stage dataset for ML-driven EDA. It starts from 8,659 curated RTL designs and is expanded to ~15k+ designs via augmentation. For each design, the authors claim to provide RTL, synthesized netlist, placed-and-routed layout, and timing/power metrics, to enable benchmarking of timing and power prediction models.", "questions": "1.\tExactly which PDK / tech node, voltage was used?\n\n2.\tIn the augmentation stage, you apply transformations like bidirectional substitution, comparison inversion, operator replacement (e.g. change + to *). But if you take an adder design and turn + into *, now functionally it's just… a multiplier. That might already exist somewhere else in the dataset as an actual multiplier module. So:\nHow do you avoid generating duplicates / near-duplicates of other designs you already have (e.g. two semantically different source modules collapsing into the same behavior after mutation)?\n\n3.\tHow many AST-mutated samples survive functional verification? Give the acceptance rate.\n\n4.\tPower. Dynamic power strongly depends on input activity (toggle rates). If you only use one stimulus style (or even vectorless estimation), then the reported “power” is tied to that specific workload assumption. Did you generate multiple activity patterns per design (e.g. different input vectors / switching factors / functional scenarios), or is each design labeled with just a single power number?\n \n5.\tTiming. Timing depends heavily on physical context: floorplan, macro placement, routing congestion, target clock, etc. You say you're doing “early-stage timing prediction,” but what exactly is the task setup? Is the model supposed to take only RTL (plus spec like clock target) and directly predict final post-route arrival time / slack? Or are you also giving it partial physical info (e.g. rough floorplan, utilization target, cell library corner)? Please show a concrete example input/output pair for the timing benchmark: what does the model see, and what exactly is it supposed to predict? Without that, it's unclear how this task is meant to be used outside your own flow.", "limitations": "", "rating": 4, "confidence": 4, "soundness": 2, "presentation": 2, "contribution": 2, "strengths": "1. Cross-stage supervision. The multi-modal / multi-stage angle (RTL text, graphs/netlists, and layout images) is sensible.\n\n2. Building this dataset required significant engineering effort, including full synthesis, place-and-route, and signoff-style timing/power extraction for thousands of designs", "weaknesses": "1. The practical impact is limited. Timing closure in real digital design is safety-critical and requires signoff-level accuracy under specific PDK, voltage, frequency, corners, etc. An ML model that only predicts approximate WNS/TNS or power from dataset patterns cannot be trusted in an actual tapeout flow, so the gains shown here are academically interesting but not directly usable.\n\n2. The paper withholds critical details (PDK, voltage, frequency, corners, clock constraints, placement density targets).\n\n3. Table 1 is overfull / too wide for the page.", "quality": null, "clarity": null, "significance": null, "originality": null, "strengths_and_weaknesses": "", "was_revised": false, "final_justification": "", "rebuttal": "", "claims_and_evidence": "", "methods_and_evaluation_criteria": "", "theoretical_claims": "", "experimental_designs_or_analyses": "", "relation_to_broader_scientific_literature": "", "essential_references_not_discussed": "", "other_strengths_and_weaknesses": "", "other_comments_or_suggestions": "", "questions_for_authors": "", "summary_of_paper": "", "summary_of_recommendation": "", "technical_quality": "", "clarity_of_presentation": "", "potential_impact": "", "robotics_focus": "", "quality_of_limitations": "", "questions_for_rebuttal": "", "reasons_to_accept": "", "reasons_to_reject": "", "questions_to_authors": "", "extra_scores": {}}, {"review_id": "cIt2FFmFDd", "reviewer": "Reviewer_zFQL", "summary": "The paper presents CircuitNet 3.0, which is a comprehensive multi-stage and multi-modal dataset that enables advanced AI-driven circuit design through cross-stage data augmentation and filtering.\n\n\nThe paper makes 3 contributions:\n\n--A large-scale, multi-modal, and multi-stage digital circuit dataset with full RTL-to-layout\ntraceability. CircuitNet 3.0 contains 8,659 unique, validated source RTL designs and over\n15,000 total augmented designs, each with corresponding netlist and layout representations.\nThrough an industrial EDA workflow, we extract rich cross-modal features at each design stage,\nproviding a valuable resource for research in multi-stage multi-modal representation learning.\n\n-- A principled framework for data augmentation.  This enables robust learning for ML models,\nproviding simultaneous cross-stage analysis and early-stage prediction capabilities.\n\n--A comprehensive set of new baselines and rigorous experimental protocols.", "questions": "1. What types of circuits suit this tool the best---this is not clearly spelled out.\n2. It seems like using your tool requires significant computational power. Is it suitable for single-GPU users, and if so what generation times should one expect?", "limitations": "", "rating": 8, "confidence": 4, "soundness": 3, "presentation": 4, "contribution": 4, "strengths": "This system seems like it can be a useful addition to the circuit generation process. It clearly addresses the multiple modalities of data required for the entire process. The article does a good job of covering the sourcing, curation and inference properties of the different datasets.\n\nThe paper also details a comprehensive evaluation, which uses state-of-the-art ML models. The papers empirically demonstrates significant prediction accuracy improvements over single-modal datasets, with approximately 31.52% and 3.95% error reductions for timing and power tasks, respectively, compared to the existing dataset. Models trained on CircuitNet 3.0 consistently outperform single-modal approaches, establishing new performance benchmarks for ML-driven EDA tasks.", "weaknesses": "As a systems paper, there are different evaluation criteria. I think that there are few if any  clear weaknesses, as the overall system covers the full gamut of data, good curation/evaluation, and corresponding inference tools.", "quality": null, "clarity": null, "significance": null, "originality": null, "strengths_and_weaknesses": "", "was_revised": false, "final_justification": "", "rebuttal": "", "claims_and_evidence": "", "methods_and_evaluation_criteria": "", "theoretical_claims": "", "experimental_designs_or_analyses": "", "relation_to_broader_scientific_literature": "", "essential_references_not_discussed": "", "other_strengths_and_weaknesses": "", "other_comments_or_suggestions": "", "questions_for_authors": "", "summary_of_paper": "", "summary_of_recommendation": "", "technical_quality": "", "clarity_of_presentation": "", "potential_impact": "", "robotics_focus": "", "quality_of_limitations": "", "questions_for_rebuttal": "", "reasons_to_accept": "", "reasons_to_reject": "", "questions_to_authors": "", "extra_scores": {}}, {"review_id": "ShdgRzsC1B", "reviewer": "Reviewer_xPrq", "summary": "This work proposes CircuitNet 3.0, which contains 8,659 unique and validated source RTL designs and over 15,000 total augmented designs, each with corresponding netlist and layout representations.", "questions": "1. For the augmentation, does it maintain the original functionality on the augmented cases? If yes, then if the advanced synthesis tool, such as DC, is adopted, will these augmented RTL lead to the same post-synthesis PPA results as the original RTL?  \n\n2. After the AST-based rewriting, how specifically do the authors convert the AST back to RTL code (which tool and major command)? Is the AST in bit-level or word-level? Does the AST-converted RTL code still look similar to human-generated RTL code?", "limitations": "", "rating": 4, "confidence": 4, "soundness": 3, "presentation": 3, "contribution": 3, "strengths": "In summary, this work proposes a promising and valuable open dataset that helps address the scarcity of digital circuit data. \n\n1. The writing is very clear. Especially, sufficient related prior works have been referred to. Good visualization and tables have been provided. \n\n2. This work tried to address the data limitation problem of IC design, which is a long-lasting problem.\n\n3. This work tries to provide sufficient new RTL design, introducing diverse functionalities in the dataset. This brings much more design information to the dataset compared with CircuitNet 2.0.  \n\n4. This work tries to validate the dataset in cutting-edge research works in the ML-assisted EDA direction.", "weaknesses": "Despite the contribution of the dataset, there is some key information not provided in this manuscript, triggering some additional questions. The author may consider adding them during the revision. The reviewer is ready to raise the score if these concerns can be well addressed. \n\n1. There should be a detailed list showing all sources of these  8659 samples, possibly in the Appendix. Currently, the paper only mentions \"We systematically collected RTL designs from established platforms, including GitHub, Hugging Face, OpenCore, and RISC-V projects\". \n\n2. To allow users to better understand the dataset, there should be statistical information describing the distribution of key features of all circuits in this dataset. How large are these circuits? For example, the user may provide the distribution of the number of RTL lines of all circuits and the number of gates in all corresponding netlists. These basic statistics have been adopted in many prior works. \n\n3.  Following point 12 about dataset information, Tables 2 & 8 show the design types. Do they indicate that there are 645 different adders and 906 different counters, which are all directly collected from human-crafted projects? If they are adder/counter modules only, then these components seem to be smaller and more repetitive than the reviewer had expected. How come there are so many different adders/counters from real designs? How are they extracted from realistic whole designs? Are some of them exactly equivalent to each other (not easy to believe there are 600+ different adder RTL designs and leading to completely different post-synthesis implementations)?   \n\n4. The Anonymous repo is empty now.", "quality": null, "clarity": null, "significance": null, "originality": null, "strengths_and_weaknesses": "", "was_revised": false, "final_justification": "", "rebuttal": "", "claims_and_evidence": "", "methods_and_evaluation_criteria": "", "theoretical_claims": "", "experimental_designs_or_analyses": "", "relation_to_broader_scientific_literature": "", "essential_references_not_discussed": "", "other_strengths_and_weaknesses": "", "other_comments_or_suggestions": "", "questions_for_authors": "", "summary_of_paper": "", "summary_of_recommendation": "", "technical_quality": "", "clarity_of_presentation": "", "potential_impact": "", "robotics_focus": "", "quality_of_limitations": "", "questions_for_rebuttal": "", "reasons_to_accept": "", "reasons_to_reject": "", "questions_to_authors": "", "extra_scores": {}}, {"review_id": "mUiWhUttA8", "reviewer": "Reviewer_myKG", "summary": "The paper presents CircuitNet 3.0, a benchmark dataset designed to support AI-driven EDA research. It introduces a multi-modal framework that integrates RTL, gate-level netlist, and layout representations, enabling cross-stage learning for circuit-level prediction tasks such as timing and power estimation.", "questions": "1. The claimed 3.95% error reduction in power prediction (e.g., line 92, 467 and 485) lacks exact calculation and appears inconsistent with MAPE reductions between 11–23% shown in Table 6.\n\n2. The paper highlights \"a novel data augmentation framework based on Verilog abstract syntax trees (ASTs)\" (Section 4.3) as a core contribution. However, AST-guided code mutation and transformation have been widely explored in software-engineering contexts [1]. So it would be better if the authors could elaborate on how the proposed AST-based augmentation differs technically from prior AST mutation and program-transformation works.\n\n3. The paper states (line 357) that the test set was 'supplemented with submodules from external open-source projects,' but does not justify the need for this supplementation or provide details on the data's origin. This omission raises concerns about potential overlap between the training and test data, especially since section A.2 lists GitHub, Hugging Face, RISC-V, and OpenCores as sources for both training and validation data\n\n4. In Figure 6(b) and 6(d), both the post-augmentation WNS and total-power distributions exhibit an unusual concentration of samples around layout-density ≈ 94.5%, which is not present in the pre-augmentation distribution shown in Figure 6(a) and 6(c). Could the authors clarify:\n(1) what specific synthesis or placement-density configurations led to this clustering?\n   (2) why this effect appears near the 94.5% density rather than being smoothly distributed?\n   (3) whether such clustering introduces dataset bias that may influence model evaluation or overfit models toward a narrow design-density region?\n\n5. It would be beneficial for the authors to discuss how this work relates to recent benchmarks such as ChiPBench [2], which also targets AI-based EDA evaluation with a complete open-source flow.\n\n[1] Petrović, Goran, et al. \"Practical mutation testing at scale: A view from google.\" IEEE Transactions on Software Engineering 48.10 (2021): 3900-3912.\n\n[2] Wang, Zhihai, et al. Benchmarking end-to-end performance of ai-based chip placement algorithms. The Thirty-ninth Annual Conference on Neural Information Processing Systems Datasets and Benchmarks Track.", "limitations": "", "rating": 6, "confidence": 3, "soundness": 3, "presentation": 3, "contribution": 3, "strengths": "The paper presents a well-structured and comprehensive effort to advance dataset resources for AI-driven EDA research. Its originality lies in integrating multiple design representations (RTL, gate-level netlist, and layout) into a unified multi-modal dataset, and provides a new level of data granularity for model training. The proposed task-oriented augmentation framework demonstrates an application of AST-based code mutation in the EDA context, contributing to the diversity and robustness of learning samples.", "weaknesses": "1. All reported improvements are based on models trained with augmented datasets that are larger than the original data or baseline benchmark (Section 4.4 and Table 5–6). The paper lacks ablation or control experiment to verify that the observed gains stem from the augmentation methodology rather than simply from increased volume of the training set. \n2. For the timing-prediction task (Table 4a), the authors attribute performance gains of RTLDistil to multi-modal learning, yet the compared non-multi-modal baselines (MasterRTL, RTL-Timer) may differ substantially in architecture, capacity, and parameter count. There lacks controlled \"with/without multi-modal input\" experiment for timing.\nSimilarly, for MOSS in the power-prediction task (Table 4b), the attribution of performance gain solely to \"multi-modal representation\" is not fully justified without evaluating RTL-only, netlist-only, and combined-input variants under identical configurations.\n3. CircuitNet 3.0 is positioned as a task-oriented benchmark, yet the tasks are limited to timing and power prediction. Other critical circuit-design objectives—e.g., routability and IR-drop mentioned in CircuitNet 2.0—are absent. By focusing narrowly on two metrics, the dataset may bias models toward timing/power trade-offs at the expense of broader PPA generalization.", "quality": null, "clarity": null, "significance": null, "originality": null, "strengths_and_weaknesses": "", "was_revised": false, "final_justification": "", "rebuttal": "", "claims_and_evidence": "", "methods_and_evaluation_criteria": "", "theoretical_claims": "", "experimental_designs_or_analyses": "", "relation_to_broader_scientific_literature": "", "essential_references_not_discussed": "", "other_strengths_and_weaknesses": "", "other_comments_or_suggestions": "", "questions_for_authors": "", "summary_of_paper": "", "summary_of_recommendation": "", "technical_quality": "", "clarity_of_presentation": "", "potential_impact": "", "robotics_focus": "", "quality_of_limitations": "", "questions_for_rebuttal": "", "reasons_to_accept": "", "reasons_to_reject": "", "questions_to_authors": "", "extra_scores": {}}]

Author rebuttal:

Decision: Accept (Poster)