OSIRIS: Bridging Analog Circuit Design and Machine Learning with Scalable Dataset Generation
Authors: Giuseppe Chiari
Michele Piccoli
Davide Zoni
Venue: ICLR 2026 Poster (2026)
Keywords: electronic design automation
analog circuits
reinforcement learning
layout design
parasitic-aware
dataset generator
Primary area: datasets and benchmarks
TL;DR: Osiris is a scalable pipeline for generating analog IC datasets comprising circuit variations and performance metrics enabling ML-driven research in electronic design automation.

Abstract: The automation of analog integrated circuit (IC) design remains a longstanding challenge, primarily due to the intricate interdependencies among physical layout, parasitic effects, and circuit-level performance. These interactions impose complex constraints that are difficult to accurately capture and optimize using conventional design methodologies. Although recent advances in machine learning (ML) have shown promise in automating specific stages of the analog design flow, the development of holistic, end-to-end frameworks that integrate these stages and iteratively refine layouts using post-layout, parasitic-aware performance feedback is still in its early stages. Furthermore, progress in this direction is hindered by the limited availability of open, high-quality datasets tailored to the analog domain, restricting both the benchmarking and the generalizability of ML-based techniques. To address these limitations, we present OSIRIS, a scalable dataset generation pipeline for analog IC design. OSIRIS systematically explores the design space of analog circuits while producing comprehensive performance metrics and metadata, thereby enabling ML-driven research in electronic design automation (EDA). In addition, we release a dataset consisting of 87,100 circuit variations generated with OSIRIS, accompanied by a reinforcement learning (RL)–based baseline method that exploits OSIRIS for analog design optimization.

Published as a conference paper at ICLR 2026
OSIRIS: BRIDGING ANALOG LAYOUT CIRCUIT DESIGN AND MACHINE LEARNING WITH SCALABLE DATASET GENERATION
Giuseppe Chiari, Michele Piccoli Davide Zoni
DEIB
Politecnico di Milano
Milano, MI 20133, Italy
{giuseppe. chte.cchirrri matarriiiiceeeeeeee mimmiiheele scchele.picollo davee.
davide. zoni @ imi,
ABSTRACT
The automation of analog integrated circuit (IC) design remains longstanding challenge, primarily due to the intricate interdependencies among physical layout, parasitic effects, and circuit-level performance. These interactions impose com- plex constraints that are difficult to accurately capture and optimize using conven- tional design methodologies. Although recent advances in machine learning (ML) have shown promise in automating specific stages of the analog design flow, the development of holistic, end-to-end frameworks that integrate these stages and it- eratively refine layouts using post-layout, parasitic-aware performance feedback is still in its early stages. Furthermore, progress this direction is hindered by the limited availability of open, high-quality datasets tailored to the analog do- main, restricting both the benchmarking and the generalizability of ML-based techniques. To address these limitations, we present OSIRIS, scalable dataset generation pipeline for analog IC design. OSIRIS systematically explores the de- sign space of analog circuits while producing comprehensive performance metrics and metadata, thereby enabling ML-driven research in electronic design automa- tion (EDA). In addition, we release dataset consisting of 87 100 circuit variations generated with OSIRIS, accompanied by reinforcement learning- driven baseline method that exploits OSIRIS for analog design optimization.
INTRODUCTION
Analog integrated circuits (ICs) are critical in wide range of modern electronics applications, including telecommunications, power electronics, audio engineering, biomedical engineering, and instrumentation. They enable precise sensing, amplification, and filtering, serving a critical bridge between digital systems and the physical environment. This capability ensures robust data acquisi- tion and signal processing across various applications. However, unlike digital ICs, which benefit from highly automated and increasingly ML-driven design flows (Razavi 2005 Carusone et al,
2011 Allen & Holberg 2011 Cui et al. 2024 Fang al. 2025 Liu et al. 2022a Zhao et al.
Liu et al.) 2025b). analog circuit design remains largely manual due to (i) complexity, un- like digital design based on simple logic gates, analog circuits diverse components (MOSFETs, resistors, capacitors) with intricate interconnections, (ii) sensitivity, small changes can drastically affect functionality, leading a vast search space. particular, the analog design flow di- vided into front- and back-end phases. The front-end phase targets schematic-level optimization, including component parameter tuning (e.g., transistor sizing) and topology selection. The back- end phase tackles the complex task of translating the optimized schematic into manufacturable physical layout, encompassing layout generation and feasibility verification. the front-end phase, designers determine the circuit's 's functional structure by selecting a topology and sizing devices to meet electrical specifications under idealized or schematic-level models. These tasks operate on abstract representations, focusing biasing, gain, bandwidth, or noise through symbolic optimiza- tion. The back-end phase then converts the validated schematic into manufacturable physical layout. This requires solving placement and routing under striet geometric constraints, where small
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Single-pass back-ends
Layonner Verifeation
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Automation
Req
Front-eud
Schemmtt
OSTRIS
Layouserr
Verihcation
Autonation
Layout
Exploration Strategy A
Exploration
Expploratiin Stratoyy
Figure 1: The analog design flow comprises two phases (i) front-end, which translates design re- quirements into schematic, (ii) back-end, which generates the corresponding layout. Unlike ex- isting back-end methods that rely on single-pass automation, OSIRIS enables iterative exploration strategies.
spatial modifications can alter matching, introduce parasitics, break critical symmetries. Design- ers must manage layout-dependent effects, process variations, and wiring-induced parasitics, ensur- ing that the final layout passes DRC, matches the schematic through LVS, and undergoes parasitic extraction followed by post-layout validation. Because analog performance is extremely sensitive to layout geometry, this stage iterative and expert-driven, constituting a major bottleneck. These challenges motivate datasets and frameworks that expose physically accurate, parasitic-awand layout information suitable for ML-based methods. At present, the research effort mainly targets front-end optimizations encompassing the optimization of the topologies of analog circuits leveraging graph neural networks (GNNs), e.g.. CkIGNN (Dong et al. 2023), large language model (LLM) solu- tions, e.g., AnalogCoder (Lai et al. 2025a b). LaMAGIC (Chang al. [2024] and TopoSizing (Wei) et al. 2025) reinforcement learning (RL) e.g., AutoCircuit-IL. (Vijaaraghhaan et al.) or decoder- only transformers, c.g., EVA (Gao al. 2025cp. Notably, AnalogCoder employs domain-speciffe prompt engincering and feedback optimization loop to produce PySpice code, which can be trans- lated into SPICE netlists. LaMAGIC, instead, fine-tunes the Flan-T5 model (Chung et al., 2024) to directly map textual specifications to optimized designs in single forward pass, mainly targeting power converters. More recently, AnalogGenie (Gao et al. (025b) introduced a domain-specific GPT-based decoder model that represents each device pin fine-grained modeling of circuit connectivity. AnalogFed (Li et al. 2025), an advanced version of AnalogGenie, targets analog topology discovery within federated learning framework. allowing the integration multiple private datasets while preserving confidentiality. The inherent complex- ity (Noori Zadeh & Elamien 2025) of the analog layout design phase, which is highly sensitive to parasitic effects, tightly bound to specific technology nodes, and constrained by intricate manufac- turability requirements, hinders back-end automation. Few seminal works employ GNNs predict placement performance and guide its optimization (Li et al. (0200) or to increase the accuracy of front-end simulation (Ren al. 2020). At the same time, variational autoencoders have been ap- plied to analog routing by learning expert-like strategies from manually crafted layouts (Zhu et al.) 2019). RL., instead, has been applied to place FinFET modules on grid, optimizing for symmetry and alignment errors, area, and wirelength (Ahmadi & Zhang 2021 and to minimize total routing cost in terms of wirelength, number of vias, and design rule violations (Chen et al. 2023a). Despite promising research efforts, back-end automation remains comparatively underexplored. Current analog layout optimization methodologies are human-centric, relying on trial-and-error strategies, making the process time-consuming and sesouree-intessivee This work introduces OSIRIS, novel end-to-end back-end flow designed to enable scalable machine learning research in analog layout automation. As illustrated in Figure OSIRIS differs from existing back-end flows by enabling the instantiation of iterative, performance-driven layout design space exploration strategies rather than single-pass automation. It offers three primary contributions to the state of the art:
individual graph node, enabling
OSIRIS: an efficient pipeline to generate, validate, and evaluate large volumes of layouts for generic analog circuits, producing tens of thousands DRC-clean and LVS-verified de- signs. A representative dataset, generated by OSIRIS comprising 87 100 layouts, is released to demonstrate its capabilities.
RL-driven optimization: reinforcement learning framework that leverages OSIRIS to it- cratively explore the layout design space and optimize circuit implementations based on parasitic-aware performance feedback.
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I
B
(a) 2-finger transistor.
(b) 1-finger transistor.
(c) Halo.
Figure 2: Degrees of freedom explored by OSIRIS. da) a 2-finger transistor, (b) a 4- 4-finger transistor,
and O a halo wraps each component, allowing it to move freely within the designated space.
Dataset use case: using the DSIRIS--enerater dataset to fine-tune an L.M that automati- cally generates DRC-free and -VS-verified component layouts from sizing specifications.
The OSIRIS code and the accompanying dataset are made available online.
2 RELATED WORK
The optimization of analog IC physical design is particularly challenging due to tight performance constraints, sensitivity to parasitics, and complex design rules that traditional techniques often fail to handle effectivelyy, requiring time-consuming intervention of expert engineers. Recent advances in
machine learning, particularly reinforcement learning and graph neural networks, are being explored improve placement (Mirhoseini al.
2021 et al. 2020) and routing (Liao et al. 2020b a)
although their application to analog design remains in early development (Huang et al.
2021 Zhu
al. 2019).
Back-end automation frameworks The vision of a back-end automated analog IC design flow envisions seamless pipeline, starting from netlist-level specifications and concluding with manufacturing-reade physical layout, with each stage executed automatically or with minimal hu- man intervention. This streamlined process seeks to accelerate development and reduce design cycles by integrating diverse tools, established methodologies, comprehensive device libraries, and standardized procedures into unified framework. The Berkeley Analog Generator (BAG) (Cross- ley et al. 2013 Chang et al.] (0188) enables parameterized generator creation for analog and mixed- signal circuits, automating schematic instantiation and layout synthesis to satisfy specified perfor- mance criteria. Despite its utility, BAG depends on predefined templates and often requires substan- tial domain expertise and parameter tweaking. More recent frameworks adopt a place-and-rom -ootte centric paradigm, framing layout generation an optimization problem. ALIGN (Kunal et al. 2019
Dhar et al. 2020; Sapatnekar 2023) translates SPICE netlists into GDSII layouts, supporting multi- ple analog circuit families. Likewise, the open-source MAGICAL framework (Xu et al.) 2019 Chen et al.) 2020 202I) offers a fully automated flow from an unannotated netlist to complete GDSII lay- out by employing custom place-and-route algorithms and constraint extraction techniques. Despite recent progress, the state of the art lacks back-end automation frameworks specifically designed for iterative design space exploration and layout optimization. MAGICAL has been employed, along with DNN-Opt (Ahmadi & Zhang (201)) and Bayesian optimization, as the deterministic layouter in closed-loop methodologies that adjust transistor sizing by leveraging post-layout performance in- formation (Budak et al.) 2023 Gao et al., 2024). These methodologies are orthogonal to OSIRIS, which directly optimizes circuit layouts. Recent efforts have investigated the use of RL with Steiner trees (Basso et al.) 2024) and relational GNNs (Basso et al. 2025 Della Rovere et al. (025) in au- tomatic flows to tackle floorplanning by optimizing wirelength and area consumption. However, the state of the art does not offer frameworks specifically intended to enable adaptive layout refinement environments,
through repeated evaluation and learning in parasitic-award leaving critical gap in back-end analog layout design space exploration and optimization. Consid- ering (i) the importance and complexity of delivering an optimized backend flow and (ii) the lack of layout datasets, OSIRIS presents an ML-driven layout generator and dataset than can effectively fuel further research in the design of innovative ML back-end optimization strategies.
performance-constraiinn
Open analog datasets Analog circuits datasets are crucial enable ML-based research in topology generation, specification-driver design, or performance prediction. Recent efforts have begun to cu- rate and label significant front-end analog datasets. The OCB dataset of CtkGNN (Dong al. 2023) contains 10 000 generated operational amplifiers annotated with device parameters and simulator-
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Datcosed
ML
GDS
DoSi
Fingers
Permotattio
NL
PAR
OoS
PARR
Ps
Shin
X
Validare
GDS
0o5
TB
Variunls Geraenation
Random Exploration
GDS
RoSa
OSIRIS
Figure 3: The OSIRIS pipeline. It takes as inputs netlist template (TP), testbench (TB), and pairs of parameters matching transistors (Ps). For each TP, OSIRIS generates M netlists (NL). For each NL, it generates N layout variants (characterized by GDS and QoS files). Therefore, it generates MxN layout variants. It is divided into two stages, (i) Fingers Permutation and (ii) Variants Generation.
computed gain and bandwidth. ALIGN (Kunal et al. 2019), in addition to a place-and-route frame- work, offers diverse set of circuit netlists. More recently, AnalogGenie (Gao et al. (025a) pro- posed dataset comprising 3 350 distinct analog circuit topologies, each labeled with performance metries, while AMSNet (Tao et al.] 2024) provides set of transistor-level SPICE netlists paired with schematic images. Despite recent progress, the availability of open datasets targeting back- end remains highly limited, restricting the practical use of MI techniques. Modern MI. methods require large-scale datasets that comprehensively represent the analog circuit design space to learn and identify optimal solutions effectively.
DATASET GENERATION INFRASTRUCTURE
3.1 DESIGN SPACE DIMENSIONS IN DATASET GENERATION
In analog physical layout design, estimating the impact of parasitic elements is critical. These ele- ments arise from layout geometries and the proximity of components, often degrading circuit perfor- mance. While increasing the distance between components can reduce parasitic effects, minimizing the total area remains essential for efficient design. To balance these trade-offs, OSIRIS is structured around two hierarchical dimensions: (i) the number of transistor fingers and (ii) component place- ment. By systematically varying these factors, OSIRIS effectively explores the layout design space, capturing the parasitic effects structural and spatial configurations.
Number of transistor fingers In transistor layout, fingers the gate segments that share source and drain regions, enabling a single transistor to be split into multiple parallel segments to improve layout compactness, reduce parasitic effects, and enhance performance. Given circuit netlist, each transistor may support multiple valid finger counts while keeping its width and length fixed. Figure 2a and Figure 2h show examples of two- and four-finger transistors, respectively; fingers are highlighted in red.
Component placement A surrounding boundary, referred as halo, placed around each netlist component, i.e., transistors, resistors, and capacitors. This configuration permits unrestricted move- ment of components within their respective halos. Figure 2c shows the halo mechanism applied to two generic components A and B. Each component is wrapped in bounding box, which allows it to move freely inside.
OSIRIS is designed to be extensible beyond the two degrees of freedom presented here. While the current release explores variability through finger permutations and spatial perturbations, the under- lying infrastructure is meant to be easily extended with novel and complex layout transformations
3.2 OSIRIS PIPELINE
Figure 3 iillustrates the OSIRIS dataset generation pipeline. OSIRIS aims to systematically generate a diverse and structured collection of layout variants suitable for statistical design analysis, training machine learning models, exploring layout optimization strategies. The pipeline takes inputs circuit netlist template (IP), which specifies the connectivity and device-level specifics (e.g., sizing) of the design, set of transistors pairs (Ps) to specify matching transistors and an accompanying
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Datases
data
netlists
metaddata
layouts
mettrics
simulations
circuity
circuity
circuity
circuity
circuita
template,
pains,
netlista
netlistep
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Figure 4:
Dataset structure. It contains two directories, netlists and data. The latter is further divided into four subfolders, simulation metrics, layouts, and metadata.
simulation testbench (TB) employed to verify the functionality and performance of the variants pro- duced throughout the generation process. These elements, which the user provides, define both the design's logical behavior and evaluation criteria. OSIRIS generates as output dataset comprising a layout (GDS) and quality of solution (CoS) files. GDS physical representation the layout, while OoS is report describing the corresponding layout.
Fingers Permutation The first stage, referred to as Fingers Permutation, receives as input TP and Ps and generates output set of netlists to be explored further in the pipeline. This stage in- troduces structural diversity by varying the number of fingers assigned to transistors in the circuit. Since finger count affects the layout topology and electrical characteristics such parasitic capaci- lance and matching, this variation allows for exploring alternative physical implementations without altering the circuit's logical function. All valid combinations of finger assignments are enumerated, resulting in a total of M distinct permutations. A permutation of fingers is valid if it adheres (i) to matching requirements, for instance, current mirrors and differential pairs require their transistors to be as identical as possible, therefore to have the same number of fingers and (ii) the minimum gate dimension specified by the PDK in use. Each valid permutation then used to annotate the TP to produce new netlist NL; for i ,,...,M, M, thus generating a set of M netlists.
Variants Generation The Variants Generation stage processes each of the generated netlists to generate set of GDS and Qos. It takes inputs the set of netlists and TB. This stage is further divided into two steps (i) Baseline P&R and (ii) Random Exploration. Variants Generation processes one netlist NL; at time for i O....,M.
First, for a given NL,, Baseline P&R performs a complete place-and-route flow to synthesize a baseline layout. Notably, Baseline P&R comprises a placer and a router. The placer encodes cir- cuits using sequence-pairs (Murata et al. 2002), from which placement constraints are derived and solved with geometric ILP formulation. Simulated annealing (Kirkpatrick al. 1983) acts as a meta-heuristic, permuting the sequence pairs to explore alternative placements to minimize the half-perimeter wire length (HPWL). The routing process is split into two stages, global routing, per- formed with Dijkstra's 's algorithm (Dijkstra 2022). and detailed routing, handled with the A search algorithm (Hart al. 1968) to resolve local congestion. The generated baseline layout is faithful physical realization of NL: Baseline P&R integrates the place-and -nuuuue process along with the necessary steps to assess the validity of the generated layout, i.e., design rule checking (DRC), lay- out versus schematic (LVS), parasitic extraction (PEX), and simulation. This step produces three objects, baseline layout GDS,, the corresponding Qost, and an internal representation (IR?), containing the coordinates (upper right and lower left corners) and type (nmos, pmos, capacitor, resistor) of each component of NL,- The baseline plays a dual role in the dataset generation process. It is directly included in the final dataset the baseline, i.e., variant b, representing unmodified, post-P&R instance of the design. Moreover, it the initial configuration from which all subsequent layout perturbations are derived.
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Table Dataset statistics. For each circuit, the number of explored netlists, the number of generated layout variants per netlist, the metrics, and the acquisition time are reported.
Miller
Aluja
Feed Forward
S-Tramistoos
LPF
nmos
10
5
Circuits components
3
cap
1
3
2
Explored netlist
140
143
221
129
229
Generated layouts per netlist
100
100
100
100
Total generated layouts
600
14:000
22:400 400
12900
22:900
and var. score (volts)
0.0794 0.0007
0.0005
0.1044 0.0012
0.0874 0.00005
0.3201
Mean (pmm" " and var. (nom)) ") area
1 1748 028
177 - 753
768 778
414 3314
5 3:001 1530
Mcan generation time (per layout)
48
45
29
Total generation time [h]
195
191
156
162
187
Second, the Random Exploration step explores spatial variability. It receives as input IRă and produces outputs set of N incremental variants each described by a GDS and a CoS? for j= 0.....,, N. Thus, iteration j serves as baseline for iteration j+1, with TR. TR The Random Exploration is divided into three sub-steps, (i) Shift (ii) P&R and (iii) Validate, executed in a loop for successful iterations. Shift rolls two dice, one to choose which component to move and the other to choose the cardinal direction, i.e., up, down, left, right, to move the component towards. Shift, also, perturbates IRI to reflect the shifting. P&R reads IRi, shifts the selected component accordingly, and, since the new placement invalidates the components connections, performs the routing of all netlist components considering the coordinates of the newly shifted component to ensure electrical connectivity, thus yielding GDS;. Lastly, Validate assesses that the perturbed layout remains logically equivalent to the original netlist and estimates its behavior. To this end, the classic analog design flow performs DRC, LVS, PEX, and simulation. An iteration i is successful if the Validate sub-step completes correctly. If it fails, the perturbation is reverted and the j-th iteration repeated. At the conclusion of this process, the dataset contains total of variant includes the layout in GDSII format (GDS)) and set of resources that reflects design quality in terms of physical and electrical metrics along with auxiliary metadata such as the specific netlist configuration and the nature of component displacements ). Notably, to carry out LVS, PEX, and simulation, OSIRIS fully integrates with Netgen, Magic, and Ngspice, respectively, while DRC is respected by construction during place and route processes.
variants. Each
ANALOG LAYOUT DATASET
4.1 DATASET STRUCTURE
Figure Adpicts the organization of files in the randomly generated dataset. It comprises all relevant information on each generated layout variant. It is divided into two main folders: net betlists and data. The dataset was recorded on a Rocky Linux 8.10 machine equipped with an Intel Xeon 2.90GHz with 32 cores and 128GB of RAM. No GPU was used.
Netlists The netlists directory contains C' subfolders, one for each circuit class processed by OSIRIS. Each circuit subfolder refers to a specific analog circuit and comprises the cir- cuit netlist template, which is a base netlist that serves as the canonical representation of the ci riruit,, the testberch, in SPICE format, used to assess pre- and post-layout functionality, the pa pairs irs file reporting the matching transistors, and netlist files SPICE format. Each netlist inherits from the templat latplate information component names, types, connectivity, and sizing while adopting a different permutation over the number of fingers. The template files are provided by the user while the sets of net 1 list files are the results of the Fingers Permutation stage of the OSIRIS as described Section 3.2
Data For each circuit, the data directory includes all necessary information to describe its corresponding design variations. This directory is organized into four subfolders, each containing relevant data for the N layout variants associated with every net 1 sst of the given e reuit:

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Table 2: Analog datasets comparison. OSIRIS is the first framework aimed back-end design that systematically explores and extensively covers the layout design space.
CUIINN (Dog at 2025
AnalogGioni Gto 20256
AMSNar (To ct 2014
ALIGN (Kundl A et 2019
OSTRIS
Design plase
Freet-end
Front-end
Frontendd
Back-and
Backeend
Trems type
Netlists
Neilists 3350
Netlists
Layonts
Volume
00000
521
Physical validity check
N.A.
N.A.
N..
Pamsitic awrreness
synthesis
X
Extensibility
X
Simulat comprises the pre- and post-layout simulation results for each layout vari- ant, respectively in pre and post files. These files are obtained by testing each variant with the corresponding e reuit's testbench. Testbenches consist of AC small-signal simulations. The frequency is swept from 1 kHz to 1 GHz with 50 points per decade.
Metrics captures the QoS associated with each layout variant in terms of physical and electrical properties. The metries are (i) pex_score and (ii) area. The former quantifies the degradation in performance due to parasitic effects introduced during the layout process root mean square error between the pre and post results. At the same time, the latter measures the total silicon footprint of the layout. See Section [433 for a detailed description of the metrics. For both metrics, lower values indicate better performance.
Layouts contains the physical layout files, GDS, generated for each variant in GDSII format. GDS provides a precise geometric representation of the layout encoding polygons distributed across multiple metal layers, defining the physical implementation of the chip. Metadata contains the GDSII files for each individual component, t tiles, and the cumulated movements, moves, performed on each tile up to iteration j-th.
Beyond serving as a large-scale physical-design benchmark, the OSIRIS dataset is explicitly struc- tured for ML pipelines. Its paired pre- and post-layout simulations, detailed parasitic degrada- tions, and spatial metadata enable tasks such as parasitic prediction, MI.-guided placement, and component-lever layout synthesis. The fine-grained organization of geometry, metrics, and traces provides supervision signals tailored to learning layout-dependent behaviors.
4.2 STATISTICS
Amplifiers and filters are widespread in analog design, serving as core components within wide range of more complex systems, e.g., ADC/DAC and sensor interfaces (Franco) 2002] HHujsing 2011 Carusone et al. 2011). Their widespread use and inherent component diversity, encompass- ing NMOS/PMOS transistors, resistors, and capacitors, as well as structural diversity with current mirrors and differential pairs, provide an ideal circuit template to investigate automatic layout flows.
All circuits have been implemented in Skywater 130nm process development kit (PDK) (KY as it is mature, open-source, and well-integrated into available open-source CAD tools (Kahng 2020
Herman et al. 2023 Chen et al. 2023b Tsuchiya 2024 Teo et al. 2025). Notably, a PDK is defined set of files and rules provided by manufacturer to enable chip designers create layouts of integrated circuits that comply with manufacturing capabilities, i.e., that can be taped out. Table summarizes key statistics of the generated dataset, including the number and types (PMOS/NMOS transistors, resistors, and capacitors) of circuit components. It also reports the number of finger per- mutations, i.c., netlists, explored along with the number of layout variants produced per netlist and circuit. Up to 229 finger permutations were explored for single circuit, with 871 permutations evaluated across all circuits, resulting 87 100 DRC-clean and L.VS-erifieed layout variants. The generation of single layout required an average of 39 seconds while the exploration of a single circuit required between 156 and 195 hours to complete. Table 2 compares the dataset generated by OSIRIS with state-of-the-arr analog datasets. The comparison emphasizes its key contribution: providing a framework capable of generating extensive quantities of layout data specifically tar- geting the back-end phase of analog IC design. The dataset weighs 5 GB and required around 37 days to acquire. Appendix illustratss the schematics the four amplifier circuits used for dataset generation, along with samples of layout variants included in the dataset.
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GDS
0oS
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FinPerm Search
Baseline PE-R
JoS
PacR
GDS
cDS
NL
+
Shift
XN
Validate
0o5 0o5
[o5
RL Explocstion
Compuie
R
Reward
RL Variants Generation
Figure 5: RL Variants Generation employs two-level iterative RL-driven optimization process. It takes as inputs a set of netlists NL and a TB and generates as outputs a set of GDS and Qos. The outer level navigates transistor fingers permutations (stage FinPerm Search), while the inner level explores components movements (stage Spatial Exploration).
4.3 METRICS
PEX Score When evaluating an analog layout, it is essential to validate the design's 's accuracy and ensure its performance reliability. A critical aspect of this evaluation involves accounting for par- asitic elements, such as interconnect capacitances and resistances, which can significantly impact circuit behavior and degrade functionality. To quantify the influence of parasitics, comparison between schematic-level (pre-layout) and post-layout simulation results is performed. This compar- ison is captured by the pscore, metric that measures the discrepancy between pre- and post-layout outputs in volts (V). As defined Equation [ the pscore computed as the RMSE between the pre-layout simulation results (pre) and the post-layout results (post):
K
pscore
(pre; -posl))
where denotes the number of sampled points in each simulation trace. By construction, the pscore quantifies the impact of iyduut- parasitics, which degrade key analog performance metrics such as gain, bandwidth, noise, and stability. Its optimization is crucial for reliable circuit operation.
Area In addition to electrical performance, physical layout characteristics, such as silicon area, are critical factors in analog circuit evaluation, particularly in cost-sensitive or space-constrained appli- cations. The total layout area directly measures the silicon occupied by design and is often used as a proxy for manufacturing cost and integration density. We compute the area of each generated layout the summation of the areas of each component reported in Equation
T W H.
area
where W, and H, represent the width and height (μm) of the bounding rectangle enclosing component I, and T is the number of components. This metric reflects the overall footprint of the design and serves as an essential objective in layout optimization.
5 DESIGN SPACE EXPLORATION BASELINE
OSIRIS presents two main stages: Fingers Permutation and Variants Generation. The latter can implement different strategies explore the layout design space for given circuit. Sec- tion 3.2 presents random exploration approach, while Section 5.1 introduuce an RL-driven baseline methodology.
5.1 RL BASELINE METHODOLOGY
Figure shows the Variants Generation implementation a RL-driven iterative approach, i.e., RL Variants Exploration. It takes inputs the set of netlists generated by Fingers Permutation and a TB. The output is a comprehensive set of GDS and CoS files. The implementation based on two level of RI. optimization loops, for each degree of freedom. The outer pivots around
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searching the number of fingers permutations space while the inner one explores spatial movements for each component.
Outer loop The outer loop processes all netlists and the reward R2 from the previous iteration to produce N GDS and QoS files per netlist. It comprises four steps: (i) FinPerm Search, (ii) Baseline P&R, (iii) RL Exploration, and (iv) Compute Reward. FinPerm Search selects the next netlist NL; to explore and includes translating SPICE-formater, transistor finger permutations into RL-compatible inputs. Notably, FinPerm Search employs fully connected agent that receives vector containing the number of fingers for each transistor as input, and produces probabilities over possible finger values and maps them categorical actions. trained via REINFORCE (Williams) 1992) as a straightforward. model-free policy gradient method. Appendix [A] details its architecture. Baseline P&R generates a baseline layout (GDS)), quality metrics (Qos)), and internal representation (TRŞ)- The RI. Exploration step uses these as inputs and produces N improved GDS and Qos variants for each baseline. Lastly, Compute Reward extracts R₁ from the set of Qos files as reported in Equation 3
R1 = max a (pscore) -pscore]-pscoree) + 3 (area) - areaa) 1
(3)
where area! area and pscoref pscorel while 3 and are tuning parameters. Notably, if the outer loop's agent chooses an invalid finger configuration, a negative reward is fed to it and a new choice is made.
Inner loop The RI Exploration is the inner loop, depicted in Figure 5 It mirrors the Random Exploration strategy (Section 3.2p. It takes as input IR. and outputs N GDS and QoS files for each baseline, which are passed to the outer loop for further processing and storing. RL Exploration comprises three steps: (i) RL Place, (ii) P&R, and (iii) Validate. RL Place uses an actor-critic agent operating on an input vector that encodes each component's 's type and coordinates. The agent includes an initial shared portion which splits into two branches (i) actor and (ii) critic, providing the action to move a component and the state value of the current iteration TR. The inner agent is trained with Proximal Policy Optimization (cPPO) (Schulman et al.) (017), which is well-suited for handling discrete action spaces. Appendix A details its architecture. P&R implements the action by shifting the selected component and performing components routing. Validate ensures adherence to netlist NL; and assesses functionality. Moreover, Validate computes the agent's reward (r)) as reported in Equation
rj = a (pscore} - pscoree) ) + B (area) - area?)
(4)
where and / are tuning parameters. The sub-steps of RI. Exploration performed in loop for N iterations. Opposite to Random Exploration, if an iteration is unsuccessful, it is not repeated, the episode ends, and a penalty reward is fed to the inner agent.
6 OSIRIS DATASET USE CASE
This section illustrates representative use enabled by the OSIRIS-generated open-source dataset described in Section focusing on automated component-level layout generation. In analog back-end design, each circuit layout is constructed from the physical layouts of its constituent com- ponents. Layouting each component instance of a circuit is a time-consuming and error-prone task that requires PDK-specific knowledge. To this end, the OS/R//-generated dataset used to fine-tune an LLM-based generator to deliver DRC-free and LVS-verified layouts at component level. The use case leverages the OSIR/S-generated dataset to fine-tune the Qwen3- 14B (Yang et al. 2025) LLM to generate DRC-free, LVS-verified capacitor layouts in Sky Water 130 nm directly from sizing tar- gets. The model is fine-tuned using low rank adaptation (LoRA) (Hu al., (02T)) and evaluated on test samples to verify dimensional correctness and syntactic validity. Fine-tuning involved 000 samples (split between training, validation, and test sets) extracted from the tives of the OSTRIS-generated dataset. Fine-tuning employed H100 GPU equipped with 96 GB of dedicated RAM, rented specifically for this task. The fine-tuned model produces 100% valid outputs and per- fect dimensional fidelity, whereas the vanilla Owen3-14B model lacks any geometric competence and fails to produce valid layouts. Appendix provides in-depth details on data pre-pree precpessss,ng, fine-tuning hyperparameters selection, and prompt and generated capacitor layout examples.

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Published as a conference paper at ICLR 2026
Table Results comparison between ALIGN (Kunal al. 2019). MAGICAL Xu et al. 2019) the random baseline (Section B), and the RL-driven methodology (Section 5p. Each circuit block spans three rows showing pscore (volts), area (um²), and acquisition time (hh:mm:ss).
Circuit
MAGICAL
pscore (1)
area (1)
time
psccre (1)
2rea (1)
time
pscooe (1)
area (1) (pen")
time
pecore (1)
arta (J)
cime
(V)
(anc²)
(N::mm:36)
(V)
(wnn")
(thmmmos))
(V)
(V)
(uon")
(Ni:mmis5)
Miller
0.2721
00:02:06
1836
00.01088
0.0012
1770
395:00:00
0.00069
96,02..0
Aluja
0.5184
2.150
00001557
0.315
1.00
00:01088
0.120
1805
191:0200
1.797
70:00-00
Feod Forward
0.2087
795
00:01:20
0.230
806
00.01:18
0.087
808
10600:00
0.024
768.5 5
62:00:00
S- Traniistors
0.2554
347
0001:00
0.013
185
0000:45
0.050
290.3
162:0:00
0.017
414.5
50:00:00
LPP
00:0:20
7916
18790:00
7 EXPERIMENTAL RESULTS
To evaluate the benefits of integrating learning-drive strategies within OSIRIS, the RL-based ex- ploration method (Section 5 is compared against (i) state-of-the-art single-pass layout generators MAGICAL and ALIGN, and (ii) the random exploration strategy inherent to OSIRIS (Section 3)- The comparison's 's aim is to show that when OSIRIS is paired with different exploration approaches, including RL, it can produce layouts with improved parasitic metries and area compared single- pass baselines. MAGICAL and ALIGN provide meaningful references as they represent the most capable open-source automatic back-end flows currently available. Two NVIDIA GeForce GTX 1080Ti GPUs were used for the RL-related experiments. Appendix details hyperparameter selec- tion. Table 3 presents the comparative analysis of the four approaches. The evaluation considers three metrics for each circuit benchmark: pscore, layout area, and total acquisition time. The RL- based approach achieves lower pscore values across all benchmarks, suggesting improved handling of parasitic effects in the resulting layouts. For the Miller and Feed Forward amplifiers, in par- ticular, the RL method reports pscore values more than an order magnitude smaller than those produced by ALIGN and MAGICAL, indicating that learning-guided placement when integrated with OSIRIS -eneertee layouts. Regarding layout area, the RL baseline usually yields comparable or smaller designs. For example, the Miller and Feed Forward amplifiers pro- duce the lowest pscore and the most compact layouts. For the Ahuja amplifier, although RL and Random yield the same pscore, the RL-based layout occupies slightly less area (1 797 um? vs. 1 805 )m² One exception is the 5- T-Tannsistors OTA, where the RL approach results in a larger layout area (444.5 jm²) than baselines. However, still attains a lower pscore, indicating trade- off favoring electrical performance over area reduction. The RL-based exploration strategy remains effective across different circuit families. For instance, on the low-pass filter (LPF) benchmark, attains both the smallest layout area and the lowest pscore. Notably, MAGICAL failed to generate any valid LPF layouts. The RL-based method also demonstrates reduced acquisition time compared to the Random baseline due to more efficient exploration of the solution space, converging faster to- wards high-qualit, solutions. For example, in the Miller and Ahuja circuits, achieves nearly a 50% reduction in runtime. Across all benchmarks, it reports the shortest acquisition times. These results indicate that reinforcement learning can be a viable strategy for efficient and performance-aware analog layout space exploration.
be beneficial
8 CONCLUSIONS
This work presents OSIRIS, an end-to-end back-end framework for generating large quantities of DRC-clean, LVS-verified analog layouts to advance ML research in circuit design. OSIRIS enables scalable creation of annotated datasets and provides a public release of 87 100 layout variants across four designs. An RL baseline demonstrates its use for optimizing functional and non-functional metrics, such as parasitics and area. Unlike prior datasets, OSIRIS is open-source, configurable, and tailored for ML-driven optimization. While the current release targets five circuits in a single tech- nology node, the OSIRIS pipeline is inherently extensible. Ongoing development includes support for additional circuit families, richer perturbation operators, and transfer-learning functionality to layout the same circuit targeting different PDKs. By providing modular and open-source founda- tion for iterative parasitic-on parasitic-aware aware exploration, OSIRIS lays the groundwork for future learning-drive analog back-end flows.
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ETHICS STATEMENT
Research in analog design automation has the potential to indirectly impact a wide range of indus- tries, including healthcare, autonomous systems, and communications. By accelerating the develop- ment of high-ppeffrmmnce, energy-efficient analog ICs, frameworks such OSIRIS may contribute to faster innovation in medical devices, sensing platforms, and safety-critical applications like au- tonomous driving. While these applications are broadly beneficial, they also raise ethical considera- tions. Improved design productivity could lower entry barriers, enabling broader access to advanced technologies, but it may also be leveraged in sensitive domains (e.g., surveillance military sys- tems). We emphasize that OSIRIS is released as an open, transparent research tool intended to foster reproducibility, fairness, and broad participation in the ML-for-EDA community. Responsible use should remain a guiding principle, particularly in safety-critical or high-stakes domains.
10 REPRODUCIBILITY STATEMENT
OSIRIS is released at the anonymous HuggingFace repository link mentioned Section T It in- cludes (i) OSIRIS end-to-end pipeline delivering DRC-free and LVS-verified layouts (ii) random exploration strategy, and (iii) RL-driven exploration strategy. The random exploration strategy is described in Section 3 while the RL-driven one is detailed in Section 5 Moreover, the repository contains instructions on how to install and run the code. In addition to the code, a dataset generated by the random exploration strategy is also released the same HuggingFace repository mentioned in Section [ Section provides an in-depth description of the dataset. Appendix A provides imple- mentation details regarding the RL agents, while Appendix AppendiiBBrrpoot repoots the schematics of the analyzed circuits and samples of layouts released in the dataset.
4
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A AGENTS AND HYPERPARAMETERS
Action
mpot NF alo
Input
IR
Dx
PC
D
Softin
Da
Rnges
Go
C. 125
C2.12)
State Valvo
Shazed
R
Critic
(a) Outer agent exploring the permutations of number (h) Inner agent exploring components movement of fingers. Part of FinPerm Search step.
within their halo. Part of Shift sub-step of RI. Explo- ration stage.
Figure 6: Agent architectures employed in the two-level iterative optimization process of RL Vari- ants Generation. (a) explores the different permutations of the number of fingers for each transistor and (b) explores the components" movement inside their halo.
Figure 6 shows the two agents' architectures used in the two-level iterative optimization process presented in Section 5.1
In particular, Figure 6a shows the outer loop agent, part of the FinPerm Search step. It receives as imput vector (NF) with the number of fingers (nf) for each transistor iteration i i-1, outputs probabilities over possible finger values, and maps them to discrete choices to assign updated counts. The network consists of blocks (B) made of a fully connected layer (FC) with ReLU activation, followed by an FC layer and softmax. Here, D is the number of transistors in the netlist and K is the number of allowable finger values for the given TP.
Figure 6b reports the inner agent, part of the Shift sub-step of RI. Exploration. It determines the ac- tion (A) by selecting a component (c) and a movement direction (d), and estimates the state value (v) of IR. It operates on an input vector (IR) encoding each component's type (one-hot) and coordi- nates, yielding an 8 x C array. The agent adopts an actor-critic structure with Shared, Actor, and Critic modules. Shared consists of B blocks defined as the outer agent. Actor has two heads, He for component selection and H₃ for direction (up, down, right, left), each implemented one FC layer with softmax, jointly defining A. Critic includes a head (H,) outputting the estimated value of IR.
RL Place uses an actor-critic agent, see Figure 6b operating on an input vector IR that encodes each component's type (one-hot) and coordinates, yielding 8 features per component. The agent includes Shared P FCs layers, and two branches: Actor, with softmax heads HI, and Hair selecting component and movement direction (defining action A), and Critic, producing scalar estimating the value of IR.
Table 5: Inner agent.
Table 4: Outer agent.
Parameter
Value
P
Purameter
Value
Units per block
128
K
(2 10, 12, 14, 16)
{5.
15)
7.
0.99, 0.2
Units per block
64 x 1)
Learning
lc-5
14} le-5 Adam -10
Learning rate
Optimizer
Adam
Optimizer
Entropy coeff.
0.01
Roward penalty
Batch size
16
Replay memory size
128
Reward penalty
-0.001
Table 4 and Table 5 detail the parameters used to design and train both agents. In particular, D is the number of transistors while C is the total number of components in each circuit. respectively, 5-Transistors, Miller, Ahuja, and Feed Forward. Notably, a and 3 = 1.5 to prioritize pscore improvements. The shifting amount is fixed to 100nm.
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B CIRCUITS SCHEMATICS AND LAYOUT SAMPLES
Figure reports the schematics of the four amplifier circuits employed throughout this work, while Figure Figure Figure I0 and Figure I1 show two representative layout variants, generated by OSIRIS and included in the released dataset, for Miller, Ahuja, Feed Forward, and 5-Transistors eircuits respectively.
VDD
VDD
net
t net 2
IN
IN
OUT
net 2
net
OUT
IN
net
2
net
net 1
GND
(a) Miller.
(b) Ahuja.
VDD
IN
GND
VDD
GND
IN
OUT
VBIAS
GND
(c) Forward.
(d) T-aansistors.
Figure 7: Schematics of the four representative circuits explored using OSIRIS
(a) Miller A
(b) Miller
Figure 8: Examples of Miller layout variants generated by OSIRIS.
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(a) Ahuja A
(b) Ahuja B
Figure 9: Examples of Ahuja layout variants generated by OSIRIS.
(a) Feed Forward
(b) Feed Forward B
Figure 10: Examples of Feed Forward layout variants generated by OSIRIS.
(a) 6-Transistors. A
(b) 5- T-Tannistors B
Figure 11: Examples of layouts generated by OSIRIS and included the released dataset.
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Table 6: Qwen3-14B fine-tuning configuration.
Component
Setting
Base model
Qwen3- 1eee3-144
Quantization
4-bit NF4 (QLoRA)
LoRA rank
64
LoRA
16
LoRA target modules
Attention and MLP projections
Trainable params
As 67M (0.48% of total)
Optimizer
Adam
Learning rate
2 10
Betas
(0.9, 0.999)
Weight decay
0.01
Scheduler
Cosine with warmup
Warmup steps
1,000
Batch size (per device)
4 samples
Gradient accumulation
step
Max sequence length Epochs
4,096 tokens
Loss
Next-token cross-entropy (completion-only)
C LLM FINE-TUNING
C.I. FINE-TUNING SETUP
Table 6 details the setup to fine-tune Qwen3-14B to generate DRC-free and LVS-verified layouts of capacitor components. In particular, the fine-tuning dataset comprises 10 000 capacitor layouts extracted from the primiti i ives of the open-source released dataset, with 90% training, 5% val- idation, and 5% testing splits. The model uses 4-bit quantization and LoRA-64. The fine-tuning process took epochs on H100 GPU equipped with 96 GB of RAM.
C.2 DATA PRE-PROCESSING
The raw dataset comprises approximately 10 000 capacitor designs, each represented by com- plementary files: (i) a SPICE netlist that specifies electrical parameters (length and width jm), and (ii) GDS layout file that encodes the physical geometry collection of polygons distributed across process-specific layers. To make these heterogeneous data suitable for sequence-basee fine- tuning, we apply a systematic pre-processing pipeline. First, we parse the SPICE netlist extract target dimensions and derive the design capacitance using technology-specifi model files. Next, we load the corresponding GDS file and convert each of its polygon, regardless of its original vertex count, into its axis axis-aligned bounding box, represented as a six-element tuple: (llayer, datatype, To ensure uniform input dimensions, each layout is padded to a fixed maximum length, filling missing entries with zeros. Spatial coordinates are, then, normalized to stabilize gradients. Finally, structured prompts are constructed by pairing each layout's specifica- tions (capacitance, length, width, and polygon budget) with its corresponding JSON-encoded poly- gons sequence. This end-to-end transformation converts raw data and netlists into a numerically conditioned, token-based representation that the LLM can learn map from specifications to man- ufacturable 2D geometries.
C.3 PROMPTS EXAMPLES
Figure presentss the prompt used to query the fine-tuned Qwen3-14B model to synthesize the lay- out of capacitor with target capacitance 200pF' and geometry 10pm 10pm. The corresponding output also shown: for each polygon in the generated layout, the model produces the fabrication layer and the associated coordinates, which together define complete, manufacturable capacitor layout. For comparison, Figure [3] illustrates the prompt used to query the not fine-tuned Qwen3- 14B model. Although the prompt deliberately more structured to guide the model, the base L.M
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Published as a conference paper at ICLR 2026
Fine-tuned Qwen3-14B prompt and response
You are Khufu, an analog layout assistant. Given the capacitor targets, reply with striet JSON: ("polygons": [[layer, datatype, xmin, ymin, xmax, ymax], ...]). Each polygon is 6-element array.
Only output JSON and stay within the canonical layer/datatype pairs.
Input:
capacitance 2.000000e-10
length m: 1.000000e-05
width 1 1.000000e-05
bryggonbudgets 250
Response:
("polygons": [["metall", 0, O, 0, le-5, 1e-5], ["metall", 0, le-5 1e-7, 1e-5, 2c-5 le-7, 2e-5 1e-7]]}
Example of prompt, and corresponding response, used to query the layout of a capacitor given the required values of capacitance, width, and length.
Figure 12:
lacks the PDK-specific geometric knowledge that the fine-tuned version acquires from the OSIRIS dataset, and therefore cannot generate valid physical layouts.
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C.4 GENERATED CAPACITORS LAYOUT EXAMPLES
Figure 14 compares the layouts produced by the fine-tuned and vanilla Qwen3-14B models for 10um 10um capacitor. The fine-tuned model generates physically valid structure: two correctly overlapping metal plates forming the parallel-plate capacitor, along with well-positioned connection pins, yielding DRC-clean and LVS- -VS-consistent layout. In contrast, the vanilla one fails generate the required plate overlap and instead outputs disjoint shapes that do not satisfy the geometric and electrical requirements of functional capacitor.
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Vanilla Qwen3-14B prompt and respouse
You are Khufu, expert analog layoul ussistani specialized in generating capucitor layouts. Your task is generale a complete
layout strict JSON format based on the given eapacitor specifications.
CRITICAL: Layer/Datutppe Requirements
You MUST generate polygons ONLY using these specific layerdatatype pairs:
-Layer 89, Datatype 44; Active_Area (main capacitor body)
Laaer 235, Datatype 0: Deviee Boundary (alcemnative 1)
-Layer Datatype
Boundary (alternative
Layer 70, Datatype 20: Device DeviceBBoundarg (altemnatvv
LLaye 71, Datarype 20: Terminal.1 and Terminal 2
LLaer 70, Datalype 44: Contacts
DO NOT use any other layer/äatatype combinations. These are the ONLY valid pairs.
#*# Geametric Validity Constraints (MANDATORY):
You must eusure the following spatial relationships:
*Teemnnnal 18* (layer datatype 20) must be FULLY
A*ttivve Area* (layer dalatype 44)
This means: Terminal, I.mmn 2 Active_Ares Aren, xmin AND Terminal, J. Lamax Active_Aree Area.Arraammaa xmax
AND: Terminal. .1ymiiil...mmmm.mm ActiveeArea.ymib AND Terminall lymax j= Acive-Area.ymux.
* =TTemminal 2* (layer 71, datatype 20) must be FULLY CONTAINED within **Device Boundary (use ONE of: layer 70Vdttatype 20, OR layer 235/datatype 0, OR layer 235/datutype 4) Same containment rule applics
3. *All contacts** (layer 70, dalatype 44) must be FULLY CONTAINED within their respective terminals (layer 71, datatype 20) *CCottaimment fommula**: For any child polygon inside a parent polygon:
child.xmin marent.xmin xmin AND
ymiid >= yareni.ymin AND
child parentxxmax AND
child. ymax <= parent.yma
Layout Structure Requirements:
Your layout MUST include AT MINIMUM:
polygon Active_Area (89 (89.44)- the capacitor sinucture
-I polygon for Device_Boundas Boundary (choose from 70,20 or 235,0 235,4)
2 polygons for Temninals (71,20) one for each terminal
Multiple polygons for Contacts (70,44) distributed across both terminals
#*# Ourput Format (STRICT ISON):
""json
"polygons":
[layer, datatype, xmin, ymin, xmax, ymax].
[aaee,, datatype, xmin, yıin, xmax, ymax] ...]
Each polygon is a 6-element array: [layer, datatype, xmin, ymin, xmax, ymax] micrometers (Jum)
Coordinates
жmax must be xmin
yıaax must be ymin
Design Flexibility:
have creative freedom
Terminal placement (as long containment rules satistied)
Contact arrangement and distribution
Number
(within bulygon.budget)
Polygon positioning and sizing
Device. Boundary layer (70,20
235,4)
Input Specifications:
capacitance.fi ITARGET. CAPACITANCE] (in Farads, e.g., 1.5o-15) longth m. [TARGET LENGTH] (in meters, c.g., 2.0e55)
width,m: [TARGET WIDTH (in meters, e.g. 5.
polygon.budget,
number of polygoas)
IMPORTANT REMINDERS:
ONLY specified layer/datatype pairs
Verify ALL containment constraints hefore finalizing
-Oupput ONLY valid ISON with no additional text
'The Active Area (89,44) dimensions should upproximate the target length width All conedinates must be positive and progerly ordered (min ; max)
Required design layout INPUT:
capacitance E: 4,050000e 09
length
width_mt: m: 4,500000-005
polygon budget: 500
Response:
"polygons" : [[89, 44, 0.0. 0.0, 10.0, 10.0). (70. 20, 0.0 0.0. 10.0, 10.0). [71, 20. 20. 8.0, 10.0]. (71, 20, 2.0. 0.0, 8.0, 2.0 170. 44, 2.5, 9.5]. 4.5, 8.5, 5.5, (70, 44, 8.5, 9.5]. [70, 2.5, 0.5. 3.5, 1.5), [70, 0.5, 1.5]. [70, 44, 6.5, 0.5. 7.5. 1.5), [235, 0,0.0 0.0, 10.0, 10.0]]
Figure 13: Example of prompt, and corresponding response, used to query the layout of a capacitor given the required values of capacitance, width, and length.
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(a) 10pmm x 10para capacitor generated by fine-tuned Qwen3-14B
(b) 10pmm x 10pmm capacitor generated by not fine- tuned Qwen3-14B
Figure 14: Examples of capacitor layouts generated by (a) fine-tuned Qwen3-14B LLM and (b) not fine-tuned Qwen3-14B.
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Reviews:
[{"review_id": "FrXCJMQH7q", "reviewer": "Reviewer_JYCi", "summary": "The scarcity of open, high-quality datasets has constrained the use of machine learning in automating analog circuit design. This paper introduces OSIRIS, a scalable dataset-generation pipeline that uses reinforcement learning to systematically explore analog design spaces and produce DRC/LVS-clean layouts with comprehensive performance metrics and metadata, enabling robust benchmarking and generalizable ML methods.", "questions": "1．\tHow do you handle cases where the RL agent fails to produce a valid solution after multiple iterations?\n\n2．\tIs component rotation included in the set of layout operations?\n\n3．\tCan the method scale to larger circuits like ADC/DAC?", "limitations": "", "rating": 6, "confidence": 4, "soundness": 2, "presentation": 3, "contribution": 2, "strengths": "1．\tIntroduces a dataset-generation pipeline for analog layouts and releases an open-source dataset augmented with post-layout simulations that guarantee the sample is LVS-, DRC-clean.\n\n2．\tEfficient design-space exploration. Proposes a reinforcement-learning-driven, iterative variant-generation method that enables efficient, performance-aware exploration of the analog layout space.", "weaknesses": "1．\tLimited circuit type. The dataset currently covers only amplifier circuits at the 130 nm node.\n\n2．\tIn Table 3, it’s not fair and confusing to compare with the MAGICAL and ALIGN, which are only analog layout generation tools without any design-space exploration.\n\n3．\tConstrained variant generation and diversity. Variants are created mainly by permuting device fingers and component placement within the halo, which limits structural diversity; some schematics permit fundamentally different layout topologies. Moreover, RL optimizes score and area only, without an explicit diversity objective, increasing the likelihood of many near-duplicate samples.\n\n4．\tMissing some usage examples. Include concrete examples of how the dataset can be used, e.g., training a post-layout performance predictor to guide place-and-route.", "quality": null, "clarity": null, "significance": null, "originality": null, "strengths_and_weaknesses": "", "was_revised": false, "final_justification": "", "rebuttal": "", "claims_and_evidence": "", "methods_and_evaluation_criteria": "", "theoretical_claims": "", "experimental_designs_or_analyses": "", "relation_to_broader_scientific_literature": "", "essential_references_not_discussed": "", "other_strengths_and_weaknesses": "", "other_comments_or_suggestions": "", "questions_for_authors": "", "summary_of_paper": "", "summary_of_recommendation": "", "technical_quality": "", "clarity_of_presentation": "", "potential_impact": "", "robotics_focus": "", "quality_of_limitations": "", "questions_for_rebuttal": "", "reasons_to_accept": "", "reasons_to_reject": "", "questions_to_authors": "", "extra_scores": {}}, {"review_id": "BfgcRdViFQ", "reviewer": "Reviewer_c6mf", "summary": "This paper presents OSIRIS, a scalable dataset generation pipeline for analog IC layout design, producing over 64,200 circuit variations with detailed metrics to enable ML-driven research in EDA. It also introduces a reinforcement learning baseline that leverages the dataset for parasitic-aware layout optimization.", "questions": "- In Table 3, why does the Random method perform better than the open-source design tool MAGICAL?", "limitations": "", "rating": 4, "confidence": 3, "soundness": 2, "presentation": 2, "contribution": 3, "strengths": "- The dataset is substantial, comprising more than 64,200 circuit variations, which could be highly valuable for future research.\n- Since publicly available back-end analog circuit datasets are rare, this work has the potential to fill an important gap in the field.", "weaknesses": "- The main issue is that the paper is difficult to read. Given that ICLR is primarily an AI-focused venue, the paper should better explain the fundamental principles of analog back-end design and clearly describe the intended applications of the proposed benchmark. In its current form, it reads more like a technical report than a research paper.\n- The experimental section is relatively short, even for a benchmark-oriented paper.", "quality": null, "clarity": null, "significance": null, "originality": null, "strengths_and_weaknesses": "", "was_revised": false, "final_justification": "", "rebuttal": "", "claims_and_evidence": "", "methods_and_evaluation_criteria": "", "theoretical_claims": "", "experimental_designs_or_analyses": "", "relation_to_broader_scientific_literature": "", "essential_references_not_discussed": "", "other_strengths_and_weaknesses": "", "other_comments_or_suggestions": "", "questions_for_authors": "", "summary_of_paper": "", "summary_of_recommendation": "", "technical_quality": "", "clarity_of_presentation": "", "potential_impact": "", "robotics_focus": "", "quality_of_limitations": "", "questions_for_rebuttal": "", "reasons_to_accept": "", "reasons_to_reject": "", "questions_to_authors": "", "extra_scores": {}}, {"review_id": "goq1qqIGhA", "reviewer": "Reviewer_z7C5", "summary": "In order to address the issue of the lack of open-source high-quality datasets in the field of analog integrated circuits(IC), this paper presents a pipeline called OSIRIS, which is an end-to-end back-end framework for generating large quantities of analog layouts to advance ML research in circuit design. At the same time, it provides a public release of 64200 layout variants across four designs and an RL baseline.", "questions": "1. The dataset only covers 4 types of amplifiers. How can it be demonstrated that it has generalization capabilities for other analog circuits  and advanced processes? And It is advisable to verify the advantages of the dataset in some specific tasks.\n\n2. The process of generating the dataset takes a considerable amount of time (more than 50 hours for a single circuit). Is it practical for large-scale machine learning tasks? Are there any optimization plans?", "limitations": "", "rating": 4, "confidence": 3, "soundness": 3, "presentation": 3, "contribution": 3, "strengths": "1. Systematically generated a full-link dataset covering 4 types of typical amplifiers and 64000+ samples. All samples passed the “Design Rule Check” and “Layout-Circuit Consistency Check”, ensuring the “industrial-grade reliability” of the data. It is the first publicly available, reproducible, and fully annotated large-scale simulation IC layout dataset.\n\n2. The process and methods have strong scalability. The automated processing flow has potential to handle other types of analog circuits and advanced manufacturing processing, without requiring significant modifications.\n\n3. The supporting methods is highly consistent with the conference theme. The proposed two-level RL optimization framework  integrates machine learning technology deeply into the post-synthesis design process of analog ICs. It not only reflects the core direction of \"machine learning-driven electronic design automation (EDA)\", but also provides method validation for the practical value of the dataset, and is highly consistent with the positioning of ICLR, which focuses on innovative applications of machine learning.", "weaknesses": "1. Only covering 4 types of amplifiers and 130nm process, the circuit and process coverage is insufficient. \n\n2. The experimental part of the main text does not fully elaborate on the quality comparison of the data set and the model effect based on it, to prove the lightweighting. Without conducting verification in conjunction with specific simulation IC design tasks, there is a lack of quantitative results demonstrating the improvement in model performance of this dataset in actual tasks. As a result, the practical value and superiority of the dataset have not been fully verified through experiments, and the argumentation is not very persuasive.\n\n3. Based on the data, the generation method is inefficient. It fails to meet the requirements of \"millions of samples\" in machine learning research or the \"rapid iterative design\" scenarios in the industrial sector. However, the article does not deeply analyze the core sources of the time-consuming bottlenecks, nor does it propose targeted optimization solutions.", "quality": null, "clarity": null, "significance": null, "originality": null, "strengths_and_weaknesses": "", "was_revised": false, "final_justification": "", "rebuttal": "", "claims_and_evidence": "", "methods_and_evaluation_criteria": "", "theoretical_claims": "", "experimental_designs_or_analyses": "", "relation_to_broader_scientific_literature": "", "essential_references_not_discussed": "", "other_strengths_and_weaknesses": "", "other_comments_or_suggestions": "", "questions_for_authors": "", "summary_of_paper": "", "summary_of_recommendation": "", "technical_quality": "", "clarity_of_presentation": "", "potential_impact": "", "robotics_focus": "", "quality_of_limitations": "", "questions_for_rebuttal": "", "reasons_to_accept": "", "reasons_to_reject": "", "questions_to_authors": "", "extra_scores": {}}, {"review_id": "OnyUJDlTLD", "reviewer": "Reviewer_E2BV", "summary": "This work presents a synthetic pipeline that can generate large volumes of analog circuit layouts. This work also presents an RL design framework that can optimize circuit performance based on post-layout performance and show competitive performance compared to early SOTA MAGICAL and ALIGN. The entire framework will be open-sourced.", "questions": "see weakness", "limitations": "", "rating": 8, "confidence": 5, "soundness": 4, "presentation": 4, "contribution": 4, "strengths": "1. This work addresses an important problem for analog circuit design automation and provides an invaluable contribution\nWhile the existing analog circuit dataset only contains basic netlists, this work is able to provide its layout, which is essential for determining the circuit's real-world performance. The entire synthetic pipeline is automated and can address the data shortage issue faced by the entire analog circuit design flow (front-end and back-end). I believe this work will drive the entire analog EDA filed forward. \n2. Excellent presentation and writing\n3. Strong experiment results and supplement material support\nThe attached anonymous link contains all the material needed for determining this work's reproducibility.", "weaknesses": "1. More examples and results beyond the op-amp can further strengthen this paper", "quality": null, "clarity": null, "significance": null, "originality": null, "strengths_and_weaknesses": "", "was_revised": false, "final_justification": "", "rebuttal": "", "claims_and_evidence": "", "methods_and_evaluation_criteria": "", "theoretical_claims": "", "experimental_designs_or_analyses": "", "relation_to_broader_scientific_literature": "", "essential_references_not_discussed": "", "other_strengths_and_weaknesses": "", "other_comments_or_suggestions": "", "questions_for_authors": "", "summary_of_paper": "", "summary_of_recommendation": "", "technical_quality": "", "clarity_of_presentation": "", "potential_impact": "", "robotics_focus": "", "quality_of_limitations": "", "questions_for_rebuttal": "", "reasons_to_accept": "", "reasons_to_reject": "", "questions_to_authors": "", "extra_scores": {}}]

Author rebuttal:

Decision: Accept (Poster)