Si-GT: Fast Interconnect Signal Integrity Analysis for Integrated Circuit Design via Graph Transformers
Authors: Yuting Hu
Tarek Mohamed
Chenhui Xu
Hua Xiang
Hussam Amrouch
Gi-Joon Nam
Jinjun Xiong
Venue: ICLR 2026 Poster (2026)
Keywords: Graph Transformer
Integrated Circuit
Signal Integrity
Primary area: applications to physical sciences (physics, chemistry, biology, etc.)

Abstract: Signal integrity issues present significant challenges in modern integrated circuit (IC) design, as crosstalk-induced delay variation and transient glitches caused by capacitive coupling among interconnects can severely impact IC functional correctness. Although circuit simulators like SPICE can deliver accurate signal integrity analysis, their computational cost becomes prohibitive for large-scale designs. In this paper, we propose Si-GT, a novel transformer-based model for fast and accurate signal integrity analysis in IC interconnects. Our model elaborates three key designs: (1) virtual NET token to encode net-specific signal characteristics and serve as net-wise representation, (2) mesh pattern encoding to embed high-order mesh structures at each node while distinguishing uncoupled wire segments, and (3) intra-inter net (IIN) attention mechanism to capture structures of signal propagation path and coupling connections. To support model training and evaluation, we construct the first interconnect signal integrity dataset comprising 200k delay examples and 187k glitch examples using SPICE simulations as the golden reference. Our experiments show that our Si-GT surpasses state-of-the-art graph neural network and graph transformer baselines with substantially reduced computation compared to SPICE, offering a scalable and effective solution for interconnect signal integrity analysis in IC design verification. We release the code, model, and datasets at https://github.com/xlab-ub/Si-GT.

Published as a conference paper at ICLR 2026
SI-GT: FAST INTERCONNECT SIGNAL INTEGRITY ANALYSIS FOR INTEGRATED CIRCUIT DESIGN VIA GRAPH TRANSFORMERS
Yuting Hu' Tarek Mohamed Chenhui Xu Hua Xiang Hussam Amrouch² Gi-Joon Nam Jinjun Xiong!*
University at Buffalo, Buffalo, NY, USA University of Stuttgart, Stuttgart, Germany & IBBM Research, Yorktown Heights, NY, USA
ABSTRACT
Signal integrity issues present significant challenges in modern integrated circuit (IC) design, as crosstalk-induced delay variation and transient glitches caused by capacitive coupling among interconnects can severely impact IC functional cor- rectness. Although circuit simulators like SPICE can deliver accurate signal in- tegrity analysis, their computational cost becomes prohibitive for large-scale de- signs. In this paper, propose Si-GT, novel transformer-based model for fast and accurate signal integrity analysis
interconnects. Our model elaborates three key designs: (1) virtual NET token to encode net-specific signal character- istics and serve as net-wise representation, (2) mesh pattern encoding to embed high-order mesh structures at each node while distinguishing uncoupled wire seg- ments, and (3) intra-inter net (IIN) attention mechanism to capture structures signal propagation path and coupling connections. To support model training and evaluation, we construct the first interconnect signal integrity dataset comprising 200k delay examples and 187k glitch examples using SPICE simulations the golden reference. Our experiments show that our Si-GT surpasses state-of-the-art graph neural network and graph transformer baselines with substantially reduced computation compared to SPICE, offering a scalable and effective solution for in- terconnect signal integrity analysis in IC design verification. We release the code, model, and datasets at https://github.co http://iiiib.ooo/aaabbaabb////i/
INTRODUCTION
Signal integrity (SI) analysis is essential integrated circuit (IC) design to ensure reliable signal transmission and correct timing behavior (Caignet et al. 2001). Among signal integrity problems, crosstalk is the primary culprit. Dense interconnect layouts and high-speed signaling in modern ICs exacerbate crosstalk-induced noise and delay variations, leading to potential functional errors, performance degradation, and even chip failure Li et al. (2022); Song et al. (2013). Engineers have to SPICE simulations (Quarles al. 1994) repeatedly throughout IC design flow identify circuit behavior and crosstalk-induut noise and delay violations, allowing careful crosstalk mitigations (Vittal & Marek-Sadowskal 1997 Stöhr et 1998 Duan et al. (2100) Gao & Liu 1996). which is computationally prohibitive for very-large-scale integration (VLSI) (Achar & Nakhla|
computationally efficient surrogate for signal integrity analysis in IC design (Kahng et al., 2015) Lu & Lim 2022] Swaminathan et al., 2020) Wang & Luo 2019 Cheng et al. 2020 Liang et al. 2022 Liu et al.) 2025). However, most prior efforts primanly concentrate on timing prediction, aiming to "unravel the mystery" of black-box timing estimation formulas in sign-off timers. These works generally not model crosstalk effects explicitly with aggressor-victim switching interactions and signal pattern-dependent analysis.
Recently, machine learning (ML) has emerged
"Corresponding author: jinjun@bu

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Crosstalk Glitch
Crosstalk Delay
Aggressor
VatogeeV)
Aggressor
Buspb
Coupling
0.Stlaas
Coupling
Delay
Capacitance
Fall Oltihh
Poskive Crosstak
Negative
Glitch
Crosstalk
Vietien
Emrott
Victim
Delay Emoott
Vidin ino
Prediction Error
Graphomer
GraphGPP
130
S-GT
Nopeago
120
Net segments from drive to sink
Figure Prediction tasks illustration and Si-GT model performance.
Advances in graph neural networks (GNNs) (Wu et al., 2020) and graph transformer (GT) (Dwivedi & Bresson 2020) have revolutionized machine learning capabilities for graph-structured data, en- abling breakthrough applications in electronic design automation (EDA) from precise timing (Guo
et al. 2022 Hu et al.
2023: Lin al. 2025 Zhong al. 2024 Guo et al.
2025) and parasitics
prediction (Ren et al.
2020;
Shahane et al.
2023
2023) to complex Yoon et al. 2025 Liu et al.
optimization tasks like placement (Lu al.
2020
2025 and routing Ding al. 2024 Hou et al.
(Cheng & Yan 2021 Liao et al. 2020 Wang et al,, 2024). However, developing graph learn-
ing model for signal integrity analysis is challenging due to the complex crosstalk effect (Aragones) & Rubio 2003). In IC interconnects, the crosstalk effect arises from electromagnetic interference between signals propagating on adjacent wires. On the one hand, the severity and nature of this interference depend on multiple factors, including switching directions, active/quiet net states, slew rate, coupling capacitance, and wire characteristics (Wong al.) 2000 You & Soma 1990). the other hand, the crosstalk effect exhibits both long-range dependencies (i.e., signal propagating from drive to distant load) and adjacent net-wise dependencies (i.e, energy transfer between coupled nets). The successful application of GNNs to EDA tasks relies on incorporating domain physics into the graph's 's inductive bias (Haoxiang et al. 2022 To design an effective graph learning model for signal integrity analysis, it's important encode both signal switching patterns and structural fea- tures into the graph inductive bias while accounting for the unique circuit behaviors under crosstalk effect.
Graph transformers are excellent at capturing long-range dependencies through self-attention mech- anisms. To this end, we propose Si-GT, novel graph transformer model for IC interconnect signal integrity analysis. Si-GT incorporates three key designs: (1) Mesh pattern encoding, which embeds local mesh structures at each node enrich node features and separate uncoupled nets; (2) Virtual <NET> tokens, which encode net-specific signal characteristics (e.g., switching direction and slew rate) and serve as net-level representations, with their receptive fields restricted the corresponding nets via attention masks; (3) Intra-Inter Net (IIN) attention, which explicitly models both the spatial relationships among nodes within net the coupling effects from adjacent nets connected by coupling capacitors. Our contributions are summarized follows:
We propose Si-GT, Transformer-basee model for fast interconnect signal integrity anal- ysis. To enhance graph inductive bias, Si-GT leverages virtual NET tokens for net-level signal encoding, mesh pattern encoding for local coupling structures, and intra-inter net attention to capture signal propagation and coupling effects.
We construct a dataset for ML-based signal integrity analysis of IC circuits, comprising 200,200 crosstalk delay examples and 187.309 crosstalk glitch examples referring to golden SPICE simulations. To the best of our knowledge, this the first large-scale dataset dedi- cated to IC interconnect signal integrity analysis.
Experiments highlight the superior performance of Si-GT over advanced GNNs and graph transformers, as well as computational efficiency compared to SPICE simulation. We validate the effectiveness of each design in Si-GT through ablation studies.
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2 RELATED WORK
Crosstalk Effect. Crosstalk is severe signal interference that degrades signal integrity in circuits (Hall & Heck 2011). As illustrated in Figure when a signal transitions on the interconnect (ag- gressor), it induces a voltage disturbance manifest either as a crosstalk glitch on the victim, leading to a logic error, or as crosstalk induced de- lays in signal propagation. causing timing failures (Vittal et al. 1999). Different switching pattems of aggressor and victim can create distinct delay scenarios. When aggressor and victim switch the same direction, constructive interference occurs, accelerating the victim's transition and potentially causing timing violations. When they switch in opposite directions, destructive interference occurs, slowing the victim's 's transition and increasing delay (Wong et 2000 You & Soma 1990).
the adjacent interconnect (victim). This interference can
ML for SI. ML has been applied to reduce the cost of SI analysis in circuit design cycles (Lu & Lim 2022). Related studies mainly fall into three categories: (1) early-stage crosstalk mitigation
at the global routing stage, including critical net classification (Liang et al. 2020; (022). crosstalk-
aware placement (Gao al., [022 Yu et 2025). gate sizing (Zhou al. [022 Lu al. 202I).
and buffer insertion (Ding et al. 2024); (2) pre-routing timing estimation (Jin et al. 2024): (3)
post-routing timing estimation (Kahng et al. 2015] Cheng et al., 2020; Liu et al. 2025
et al.)
2023). These works for SI only serve for timing prediction and share key limitation that none of
them consider signal pattern variability both their dataset and model design, which is central to accurate and practical signal integrity analysis.
Graph Transformer. Graph transformer (Kreuzer et al., 2021 Yuan et al. 2025 Ying et al. 2021) encodes structural information into the graph inductive bias and leverages the graph atten- tion mechanism to capture the long-range dependencies, breaking the limitation of message-passing GNNs in capturing global context due to its inherent over-smoothing and over-squashing issues (Pei et al.). A graph transformer layer is composed of a self-attention module followed by a feed-forward neural network (FFN). Given graph G having n nodes with node feature matrix X E Rexd where d is node feature dimension, self-attention module will project X into query, key, and value matrices: Q XWq. K XWK, and V XWy with three trainable weight matrices Wo. WK Raxdx, Wy Raxdy respectively. Then global attention calculated with JV.
self-attention module: Attn(X) softmax( QK" vdx
FORMULATION AND BACKGROUND
3.1 INTERCONNECT FEATURIZATION
Apgressor
6
24
Vidim
Aggresste
Coupling in ciossty Coupled Interconnects
Wire Segment
Intanet
Interint
Equivatent Circult
Interconnect
Figure 2: Graph representation for coupled IC interconnects.
IC interconnects are typically modeled distributed RC circuits using wire-load models (Jin al., 1999). As shown in Figure [ for three coupled interconnects (two aggressors and one victim) driven and loaded by inverters, equal-length segments with IT model (Chu & Wong 2001) and parameterized with wire parasitics extracted from the physical layout. For each interconnect net we define the wire resistance as R and wire capacitance as C for every segment, while Oü denotes the coupling capacitance between net and net segment
equivalent RC circuit can be derived by breaking the wire into
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Mesh Pattern Encoding
Transformer Attention
Mash Subgraphs
<NET> Tokens
MarMul
SoftMac
IN-AAtn Blas
Fartion
Ago
Node
Embeddings
CNN
R
MarMul
round rodeo
Agg1
R
Inpurt Node Sequeece
Agg?
Node Features R
Input Interconnect Graph
Figure 3: Overview of Si-GT.
Given configuration of M coupled interconnects {net') / i=1" as shown in Figure represent its equivalent RC circuit as graph g(V, E). Here, V denotes the vertex set and & denotes the edge set. Each net nel' is node subset V/3 = {uP, ot. uz. of] C V, where L is the number of length- equivalent wire segments. Nodes in V are connected in their physical sequence along net' and characterized by the wire capacitance Cw, and each edge is associated with the wire resistance Ryy- Edges the graph represent two types of connections: intra-net connections between nodes within the individual net, and inter-net connections between nodes of different nets connected with coupling capacitors. For intra-net connections, we assign [R as the edge feature of wire connection, while for inter-net connections, we assign [0, CJ as the edge feature of coupling connection. More graph construction methods are discussed in Appendix
3.2 PROBLEM DEFINITION
Crosstalk problems concerning the signal integrity in integrated circuits manifests through three fundamental scenarios: (1) victim net quiet: (2) victim net active and switching in the opposite direction to the aggressor; (3) victim net active and switching in the same direction to the aggressor. Given the above critical scenarios for signal integrity analysis, we address two prediction tasks:
Task1: Crosstalk Glitch Prediction. As shown in Figure when the aggressor is switching and the victim is quiet, the potential difference across the coupling capacitor will generate a leakage current flowing to the victim, resulting undesirable raising or falling glitch on the victim. The height and width of a glitch indicate the potential severity of a crosstalk event. Therefore, for the quiet victim case (1), estimate two key parameters of crosstalk noise each interconnect segment the victim: the peak voltage vaax and noise width t-adth Here, noise width is defined as the time interval between the glitch's rising and falling edges at the 50% of its peak voltage.
Task2: Crosstalk Delay Prediction. As shown in Figure [ when both aggressor and victim are switching, the coupling capacitor will affect the signal transition on victim leading to slower or faster transition time by At. Net delay D is defined as the time delay of voltage waveform propa- gating through the net measured the 50% of the waveform's 's voltage level. With crosstalk-induce variation, the net delay becomes ò + At. In scenarios (2) and (3) where both aggressor and victim nets are actively switching, we predict the net delay D of the signal propagating through each segment along the net'.
4 SI-GT
In this section, we present Si-GT framework. As shown in Figure 3 Si-GT incorporates several key designs, including mesh pattern encoding, virtual NET tokens, and intra-inter net (IIN) attention. To integrate the structural information of interconnect graphs into the Transformer model and account for circuit-specific behaviors under crosstalk effects, we first decompose the interconnect graph into local mesh structures at each node and encode these structures using GNN layers for absolute po- sitional encoding. Since the driving signals propagating along nets present different characteristics, introduce virtual NET tokens to represent individual nets and encode the net-level information
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such net state, slew rate, and switching direction. Additionally, to structurally differentiate nodes within a specific net and coupled from different nets, we introduce IIN attention bias into the self- attention mechanism of Transformer to further improve the graph inductive bias.
4.1 MESI PATTERN ENCODING
In the equivalent RC circuit, coupling capacitors connect pairs of wire segments, forming a mesh unit defined as follows: [Couple Mesh Unit.] A couple mesh unit at a node vf on nel' is defined as subgraph of E(V,E) with set of nodes {v==), , uf- ) in direction from source to sink, assuming net' is coupled with an adjacent wire net? with coupling capacitance C.. In coupled interconnects, we define mesh units represent the coupling interactions between aligned segment pairs on aggressor and victim nets. As illustrated in Figure [] for node of located at the end of the s-th segment on net', the number of mesh units constructed at us is determined by the number of couplings with other nets. For example, if net is coupled with two nets nets and net at the s-th segment, we construct a subgraph mesh(uf) to capture its local structural information with two mesh units: (vf-}, uff -r-1 v2) and (o.-), of, rg- ...) As shown in Figure 2 an aggressor net typically coupled with single victim net, while victim net may be coupled with multiple aggressor nets. Therefore, we decompose the interconnect graph into local mesh subgraphs at each node, enabling the model to capture each node's local neighborhood while preserving the separation of uncoupled nets. Since mesh subgraphs small, we then employ shallow GNN model with I layers GNN' to aggregate the local mesh structure information as the embedding of ui, effectively encoding high-order mesh structural information into the node features. Finally, we add the GNN embeddings to the linear projected node feature as the input to Transformer encoder:
(1) Since the interconnect is decomposed at the end node of each wire segment, we initialize the em- beddings of driving nodes (i.e., the starting nodes of each net) to a zero vector: (0) (v?) = 0 E Rd.
h (uf) GNN' (mesh(uf)) + en(x(u;)) IR
4.2 INTRA-INTER NET ATTENTION MECHANSIM
Connections between nodes on each individual net are termed intra-net connections, while those linking pair of coupled nets are referred to as inter-net connections. Both types play critical role in the crosstalk effect. Intra-net connections capture incremental signal distortions and noise transformations along the net, whereas inter-net connections provide pathways for signal energy to transfer between nets. To capture this structural information, we introduce IIN-Attn, novel attention mechanism that incorporates both intra-net and inter-net connections through specialized attention biases. First, as the signal is propagating forward on a single net, both the net delay and crosstalk noise attributes at any specific node are highly dependent on its former nodes that the signal has passed through. To this end, we design an intra-net encoding @nntro vz)) : V x V + R to capture the net structural feature and relative position between intra-nodes:
{
if (ej
5 Vs.
Pintr (V of))
duv R 0,
otherwise.
here, due = |0 ul denotes the distance from U. to of along the net. @intra (o ofr) aggregates the wire resistance along the path from u to u on net. If u and v are not from the same net, we set the value to be O. The intra-net encoding explicitly captures the relative positional information of nodes connected in a net. Second, considering the interconnections between coupled nets, for net' corresponding to node set V/S and net' corresponding to node set V we define function @i (o" , uff x R:
ON if net', net' are coupled at (u + 1)-th segment,
Dinter (o m
0.
otherwise.
6Inter (Vf', , u measures the coupling capacitance between u/ and uj when the (u + 1)-th net seg- ment of net' and net are coupled: otherwise, this value is set to O. Intuitively, the inter-net encoding captures the connections between coupled net segments.
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To encode structural information of coupled interconnects into attention layers, directly incorpo- rate the intra-net and inter-net biases into the attention logits:
'QKT
Attn-IIN(X) softmax
+ PIN + D + $5p)
Vdx
where the bias matrix in has entries given by: QuN Plnnra + dimer- Here, Pimrr and 0intm are obtained by applying learnable linear transformations to Qlntra and Pmmia respectively. Additionally, to capture global typological features, we use spatial encoding and edge encoding as extra attention bias terms to the attention module. Specifically, & encodes the distance of the shortest path (SP) between two connected nodes using learnable embedding table indexed by the distance scalar, while & encodes the edge features along the path SP,j (e1, e2: en) from node to j via (ip(i,j)
1 +_ ====1 ex=ug Here, is the edge feature, and w E R is the weight embedding with edge feature dimension R Ying et al. 2021).
4.3 VIRTUAL NET TOKEN
As signals propagate along interconnects from source to sink, local electromagnetic interference between adjacent wire segments not only affects signal integrity at individual segments but also accumulates, leading significant distortions at the sinks of all nets. To capture this global net-level interaction, we introduce virtual <NET> tokens that represent individual nets and attend to all nodes in the self-attention mechanism. Besides, for net-level attributes such the switching direction and slew rate of signals propagating on each net, Si-GT encodes these features into learnable embeddings of <NET> tokens. Specifically, for each distinct net, we assign a learnable embedding
vector hESET> E Rd as the input embedding for the special <NET> node. These embeddings are then processed alongside other node features within the transformer architecture. To restrict the receptive field of <NET> token to its corresponding net, as illustrated in Figure 3 we define an attention mask M E R/VXXVV applied to the softmax logits of the IIN attention:
[-0, represents net' and j ş V's.
(ser(i,j)
(5)
0, otherwise.
MEET ensures that each <NET> node aggregates information exclusively from nodes within its spective net while remaining visible to all other nodes.
5
EXPERIMENTS
5.1 SIGNAL INTEGRITY DATASET
To benchmark graph learning-basse based models for signal integrity analysis, construct dataset elaborating on crosstalk delay and glitch prediction tasks that covers various net lengths and signal characteristics. Our dataset is based on the circuits of two aggressors and one victim. To simulate the circuit behavior of coupled interconnects, we construct RC circuits of the interconnect wires for SPICE simulation. In practice, circuit simulation begins by converting a physical layout into an RC model through parasitic extraction, where wires are divided into multiple equal-length segments and replaced with RC networks. model varying interconnect lengths, we sweep the number of segments and follow Intel's 14 FinFET (Fischer et al.) 2015) to set the wire capacitance and resistance for every segment. Additionally, we sweep other key parameters such as wire separation, input slew rate, and signal switching direction to create diverse signal and coupling configurations, as summarized in Table T More details on coupling capacitance calculation, circuit simulation, and dataset construction pipeline are provided in the Appendix A. For each setup of RC circuit and its driving signals, we use Synopsys HSPICE simulator to measure the crosstalk delay and glitch along the nets, which results in 200.200 delay examples and 187,309 glitch examples in total.
5.2 EXPERIMENTAL SETTINGS
Baselines. We compare our Si-GT model with following baselines: 1) GNNs, including standard GCN (Kipf & Welling 2016), GAT' (Veličković et al. 2017), GIN (Xu al. 2018). GraphSAGE

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Published as a conference paper at ICLR 2026
Table I: Circuit parameters of signal integrity dataset.
Fixed Parameters
Sweeping Parameters
Segment Length
Wire Resistance
Wire Capacitance
Net Length
Wire Separation
Coupling Capacitance
Victian State
Swilching Direction
Slew
Rate
5pm
2.7 12 ym
pm
10-100
1-20pm
0,2214-7.908
ActivoQuuiet
Low-To-High/Highhe
40-60ps
(aamltoo et al, 2017). and advanced DeepGCN (Li et al. 2019) with residual connections; 2)
recent SOTA graph transformers, including Graphomer (Ying et al. (021), GraphGPS (Kampášek)
et al. 2022). and SGFormer (Wu et al. (2023); and 3) variations of Si-GT using different standard
GNN backbones for mesh pattern encoding. We also evaluate Si-GT against baseline models using
different position/ structural encodings (PE/SE), such as RWSE and LapPE (Dwivedi et al. 2021
as detailed in Appendix D.I
Settings. In the main results, we use 5 convolutional layers for standard GNNs and 20 layers for DeepGCN. For Graphomer, we follow its original configuration with 5-step limit for shortest path encoding. while GraphGPS is implemented with RWSE using 16 walk length. Full implementation details and experimental tests for hyperparameter setting of all baseline models are provided in Appendix C.3 For Si-GT, we use 1 = 2 GNN layers with hidden dimension of 64 to encode the mesh patterns. We use 6 encoder layers with attention heads and set the embedding size to 64 for the self-attention module and 128 for the feed-forward network. We train our Si-GT for 60 epochs with 256 batch size using the A optimizer with polynomial learning rate decay and linear warmup, where the learning rate decays to le-9 over the total training steps, with weight decay set to le-4. All experiments in this paper are implemented with Py PyToch 2.2.2, DGL 2.4.0, and Pytorch- geometric 2.6. 1. Models are trained with 2 x NVIDIA A100 80GB GPUs. Detailed training setup of baseline models are in Appendix C.1
due to space constraints.
5.3 EXPERIMENTAL RESULTS
Table 2: Mean relative accuracy (%) of crosstalk delay prediction results.
GNNs
Gnaph Transfarmr
Experiment
Metric
GCN
GIN
SAGE
DecPCCN
SGiFomeer
Graphomer
GraphCiPg
SI-GT GCN
SI-GT
SI-CT
SIGT
SAGE
AV Segment
Dus
65.21
58.68
60.02
68.50
85-40
64.64
88:23
88:23
88.32
88,28
88.27
88
Das
57.38
43:27
54.17
62:41
71.61
52.60
72.58
72.65
73.67
73.18
73.30
73.81
AV Sink
Dos
51.14
45.96
51.12
46.67
50.17
53.63
$8.52
87.38
87.38
87.39
87.33
87.31
Dags
39.72
95.34
45.12
47.58
35.11
44.58
71.02
70.65
71.17
71,82
71.60
71.05
Segment
Dec
60.03
60.90
02.61
61.99
59.51
68.31
88.34
V Sink
Dus
51.97
42.77
43.65
43.50
43.80
$5.53
87.11
87.18
87.19
87.21
87.38
87.20
Table 3: Mean relative accuracy (%) of crosstalk glitch prediction results.
GNNs
Graph Transformer
Experiment
Metric
GCN
GAT
GIN
SAGE
DeepCCN
SGFFormer
Graphomer
GraphCiPS
Si+GT GCN
GAT
Si-GT
GIN
Si-GT
SAGE
V Segment
Ivies
87
85.44
85.79
88.38
87.01
83.45
88.23
85.65
83.20
87.04
82.84
84.17
93.38
94.07
96.61
97.99
97.89
97.71
97.08
96.62
97.
98.36
97.47
96-80
Sink
Aiiss
83.97
84.01
83.99
98.53
Man
62.61
83.10
82.12
62.6
68
82.56
79.08
91.17
97.91
98.63
97.16
87 02.62
97.96
Main Results. We first report the main experimental results for crosstalk delay prediction in Table 2 and crosstalk glitch prediction in Table Models are separately trained to predict delay and glitch metrics at each segment (Segment) along individual nets and specifically at their sinks (Sink). The sink-level results can provide an overview of model performance in predicting pin-to ai--oo-pi delay and glitch. For delay prediction, we report accuracy for both aggressor and victim (AV) cases, as well as for victim-only (V) cases, since the victim is of greater concern in ensuring signal integrity. Predictions are evaluated against SPICE ground truth using mean relative accuracy.
The results show that: (1) Graph transformer models, particularly Graphomer, GraphGPS, and our Si-GT, consistently outperform traditional GNNs in signal integrity analysis, achieving significantly higher accuracy across both delay and glitch prediction tasks; and (2) for the more challenging delay prediction task, our proposed Si-GT model outperforms all baselines across all experiments. While GraphGPS also demonstrates strong performance, Si-GT variants consistently achieve the highest mean relative accuracy in nearly every case.
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SHITT-REN GCN
S-GTT-II
S-GI-AEEE
GraphGiPS
Grspharer
SiTormer
GAT
GIN
SAGE
DeepGCN
Crosstalk Glitch feser Prediction
Crosstalk Glitch Vinar Prediction
10C
00-
Pelativo Acc (6
Reliativ 251
20
Crosstalk Vegy Prediction
Vee Prediction
70
Reletive Acc 176)
00
60
Relativ Act
42-
3.1
Wirr Sog monnts
Wire Segmants
Figure Comparison of models in signal integrity analysis under various IC interconnect lengths.
Accuracy with Interconnect Length. To illustrate the performance of our model across different interconnect scales, Figure [ the model prediction accuracy with the number of wire seg- ments of RC circuits for all prediction tasks. From the results, can observe that: (I) Traditional GNNs exhibit notably lower accuracy for all tasks, with performance degrading on long intercon- nects, highlighting their inherent limitations in capturing long-range interactions critical for signal integrity analysis. (2) While DeepGCN shows improved accuracy on longer interconnects, its gen- eralization across varying interconnect lengths remains limited. (3) Transformer-based models, par- ticularly our Si-GT, achieve consistently higher accuracy and demonstrate robust performance even on longer interconnects. (4) All models struggle to generalize effectively small interconnects. We analyze that short interconnects present less coupling variety, reflected in fewer data examples in dataset (detailed Appendix (.2)), resulting in poor generalization to those sparse examples.
Segment Models in Sink-level Prediction. Table 4 compares the performance of seg- ment models (trained with segment data) and sink models (trained with sink data) on sink- level prediction tasks by evaluating their differ- ences in prediction accuracy. The results show that: (1) for victim delay prediction, training Transformer-bate based models with segment data can improve sink-level predictions compared to solely with sink data, while for other tasks, training with sink data can yield better results; and (2) compared to baselines, the segment-traie trained Si-GT exhibits the smallest performance variation, demonstrating its robustness and adaptability to sink-level prediction, highlighting the robustness of Si-GT in capturing complex crosstalk behaviors even with limited structural context.
Table 4: Accuracy comparison of segment and sink models in sink-level prediction tasks.
Sink Delay
Sink Glitch
Model
AD..
AD
Atwiah
Aram.
DeepGCN
+6.36
+11.48
22.32
+0.51
SGFormer
2.30
12.86
-3.1
6.08
Graphomer
10.81
1.02
-1.73
5.83
GraphGPS
+0.48
+0.89
-0.34
-1.35
Si-GT-GCN
+0.08
1.42
-0.12
0.18
Ablation Study. We evaluate the impact of core design components in Si-GT through ablation studies, with results summarized in Table The components under investigation include the intro- duction of virtual <Net> tokens (NET), mesh pattern encoding (MPE), and intra-inter net attention (IIN). When MPE is removed, we use centrality encoding of Graphomer to construct the input node features. In the absence of IIN, we only adopt the spatial and edge encoding of Graphomer for the attention bias in equation [ More implementation details and fine-grained ablation experiments are provided in Appendix D33 Our ablation study shows the critical importance of virtual <Net> nodes to Si-GT in all prediction tasks, as it yields large margin performance boost in comparison
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with other modules. For crosstalk delay prediction, MPE particularly shows the impact to aggres- sor delay prediction. Additionally, IIN attention mechanism combining both intra- and inter-net attention, consistently enhances accuracy across most tasks, which indicates that incorporating IIN encoding as an additional attention bias effectively enables the Transformer to capture the structural characteristics of coupled interconnects.
Table 5: Ablation study results on crosstalk prediction with different designs.
Mudule
Delay Prediction
Glitc
Segment
Sink
Segment
Sink
NET
MPE
HNN
IIN
Das
Dass
Dye
Dax
88.
72.58
86.52
7L.02
91,97
89.49
95, 101
94.11
X
58.25
73.48
87.34
015
68.22
73-40
87:21
71
98..12
07:83
97.98
88.27
73.66
87.26
70.87
97.97
97.59
97.98
97.
88.32
73.67
87.39
71.82
98.36
97.75
98.53
98.63
WIYY
WITE
08
06
U6
06
Aggh
4682
Ag02
Agp2
lopl
60
6m
60
(a) Delay Si-TT
(b) Delay Graphomer
(c) Glitch Si-GT
(d) Glitch Graphomer
Figure 5: Comparison of attention maps between Si-GT and Graphomer.
Attention Visualization. GraphGPS applies global attention after local message passing updates, while Graphormer and our Si-GT directly integrate structural information into attention. We com- pare the learned attention maps of Si-GT and Graphomer in Figure 3 For delay prediction, without explicitly encoding the coupling patterns into attention bias, Graphomer (Figure (5) shows strong attention among coupled segments, highlighting the structural importance of coupling in signal in- tegrity analysis concerning crosstalk effect. Compared with Graphomer, Si-GT (Figure (5 further enables the isolation of two aggressors, aligning with the fact that aggressors are not coupled with coupling capacitors physical layout. For glitch prediction, the attention map of Si-GT (Figure shows clear coupling pattern, while Graphomer (F) only concentrates on the neighbor nodes of the same net, limiting its ability to model noise propagation across coupled nets.
Computation Efficiency. We compare the computational efficiency of promis- ing Transformer-based model Graphomer, GraphGPS, and our Si-GT model against SPICE simulation in this section. All reported
0.300
Graphomer
0.75 0
Inference Time [s]
GraphGies
SPICE Simu ation
0.50
runtimes are measured on CPU. Details of the computing environment and additional runtime benchmarks across different hardware platforms are provided in Appendix C.2 As shown in Figure 6 the computational cost of SPICE increases substantially with intercon- nect length, while Transformer-basee models maintain consistently low inference times. On average, Graphomer, GraphGPS, and Si-GT achieve inference times of 2.4 ms, 6.8 ms, and 4.0 ms, respectively, compared to over 100 ms required by SPICE even for short interconnects, highlighting the practicality of transformer-batt models efficient and scalable alternatives for signal integrity analysis in large-scale IC designs.
0.255
0.004
0.200
0.003
0.002
0.150
0.125
0.001
0.000
10 12111441
18110020
Number Segments
Figure 6: SPICE vs. Transformer-base models running time across varying interconnect scales.

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CONCLUSION
In this paper, we propose Si-GT, a Transformer-based model for signal integrity analysis of IC interconnects, and construct the first large-scale benchmark dataset comprising crosstalk predic- tion tasks relevant to practical SI challenges. We demonstrate that Si-GT consistently outperforms state-of-thee-rr GNN and GT baselines across nearly all tasks, while significantly reducing runtime compared to SPICE. These results highlight the strong potential of Si-GT as an efficient surrogate for interconnect signal integrity analysis accelerate IC design verification.
ACKNOWLEDGEMENT
This work was supported, in part. by the SUNY-IBM AI Collaborative Research Alliance, the SUNY Empire Innovation Program, and the Graduate School "Intelligent Methods for Test and Reliability" the University of Stuttgart.
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A DATASET DETAILS
A. DATASET PREPARATION
Given the separation between adjacent wires, as the length, width, and the relative electric permittiv- ity er of the substrate are constant per wire segment, we calculate the coupling capacitance according
6
based on the two-dimensional capacitance formula from (Sakurai Tamaru 1983).
Segment Length of Wire * Wire Width
C. = EY
(6)
Wire Seperation
Algorithm I to create the netlist of various RC circuits modeling coupled interconnects. After the netlist created, we supply a pulse input with 0.7 magnitude to every active interconnect wire. SPICE simulation is carried out measure the voltage waveforms at each segment along individual nets. Only examples that successfully complete SPICE simulations without failures retained in the dataset.
With the sweeping parameter setting in Table I
Algorithm Generate RC netlist for coupled interconnects
Require:
wire resistance per micron, we: wire capacitance per micron, {C.): set of coupling capacitance values; {(}: wire segment length.
Sample number of segments N ~ U(2, 20) Initialize segment index 8 +
Set wire segment length: 1 <- 5pm while N do
Set wire resistance: Rw +- I wr
Set wire capacitance: C. + 1- we
Sample coupling capacitance between victim and aggressor 1: C2 ~ Random Select( ((C.)
Sample coupling capacitance between victim and aggressor 2: Ć, Random (elect(CC.)
+ 8 +
end while =0
A.2 DATASET DISTRIBUTION
To show the composition of our signal integrity dataset, we analyze the distribution of examples across different wire segments. Figure 7 illustratees the number of examples for both the crosstalk delay (Figure
7al and crosstalk glitch (Figure (b prediction tasks.
20000
20000
Number Exammles
Number Examples
15000
15000
20000
12 Segments
10
20
Wire Segments
(a) Crosstalk Delay
(b) Crosstalk Glitch
Figure 7: Distribution of the signal integrity dataset across wire segments.
B GRAPH PEATURIZATION.
Directed or Undirected. As illustrated Figure 2 we construct the interconnect graph by mod- eling edges within each individual net directed from source sink. In this section, evaluate
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model performance using undirected interconnect graphs input, aiming to assess the impact of edge directionality on prediction accuracy. We primarily report the prediction accuracy difference between undirected and directed settings on segment-level prediction tasks for both aggressor and victim nets for comparison. The results are reported in Table A positive difference indicates im- proved performance with undirected graphs, while negative difference suggests that maintaining directionality is beneficial for capturing the underlying signal behavior in the circuit.
Table 6: Comparison of segment-level prediction accuracy using directed vs. undirected intercon- nect graphs.
Undirected
Model
Segment Delay
Segment Glitch
A
A
Awidth
A Amaax
GCN
+3.80
+3.62
+1.05
-0.10
DeepGCN
+7.98
+11.48
-0.10
-1.08
Graphomer
+1.89
+1.26
-0882
-3.28
GraphGPS
-133
-0.28
+0.39
-1.53
Si-GT-GCN
-0.13
-0.20
+2.30
-0.16
C EXPERIMENT DETAILS
C.I DETAILED EXPERIMENTAL SETTINGS
For the model training, we use different training schemes for the models included in our experiments:
Standard GNN models. We train the model using the Adam optimizer with learning rate of 2e-3 and weight decay of 6e-4. Models trained with 256 batch size for 100 epochs.
DeepGCN. We train the model using the Adam optimizer with a learning rate of le-3 and a weight decay of 6e-4. Models are trained with 256 batch size for 100 epochs.
GraphGPS. We train the model using the Adam optimizer with a learning rate of 5c-4 and a weight decay of 1e-5. Models are trained with 256 batch size for 100 epochs.
SGFormer. We train the model using the Adam optimizer with learning rate of 5e-5 and a weight decay of 1e-5. Models are trained with 256 batch size for 200 epochs.
Graphomer and Si-GT. We train the model using the AdamW optimizer with an initial learning rate of le-4, polynomial learning rate decay, and linear warmup. where the learning rate decays to le-9 over the total training steps, with weight decay set to le-4. Models are trained with 256 batch size for 60 epochs.
All experiments in this paper are implemented with PyTorch 2.2.2, DGL 2.4.0, and Pytorch- geometric 2.7.0.
C.2 COMPUTING ENVIRONMENT
All models are trained with 2x NVIDIA A100 80GB GPUs. SPICE simulations are carried out with
the commercial Synopsys HSPICE simulator on an Intel Core 17-1 Processor. In Figure 6 Intel Xcon Gold 6448Y
report the rumning time of Transformer-basee Processor. Additionally, we compare the rumning time of Graphomer, GraphGPS, and Si-GT on the A100 GPU in Figure As our graph sizes relatively small, GPU inference may exhibit higher latency due to kernel launch overhead and underutilization of GPU parallelism.
models executed
C.3 BASELINE IMPLEMENTATION.
For crosstalk delay prediction, the model outputs single delay value. so the output dimension is set to 1. For crosstalk glitch prediction, we predict both the peak voltage and noise width, so the output dimension is set to 2. The model architectures of the baselines summarized as follows:
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0.010
(CPU)
(CR6) Graphomer
[CPL] Crasecors
5:4F
0.008
Inference Time is!
0.006
0.004
0.002
0.000
Number Segments
Figure 8: Model inference time.
Standard GNN models. We convolutional layers to and the hidden dimension 64 for glitch prediction and 128 for delay prediction. Each convolutional layer is followed by ReLU activation and PairNorm normalization, except for the final layer.
DeepGCN. We set convolutional layers to 20 and the hidden dimension to 64 for glitch prediction and 128 for delay prediction. It stacks 20 DeepGCNLayer blocks, each composed of a GCNConv layer for message passing, LayerNorm for normalization, a ReLU activation, and 0.1 dropout. These blocks use a configurable residual connection strategy to enable stable training of deep GNNs (Li
et al. 2019).
SGFormer: SGFormer integrates GCN- GraphModule and a Transformer-se stylle SGModule. In our implementation, set the hidden dimension to 64. The SGModule uses 2 transformer layers, each with attention heads and 0.5 dropout, to model long-range interactions via dense attention. In parallel, the GraphModule applies 3 layers of GCNConv with dropout 0.5 and residual connections to extract localized features. The outputs from both modules are averaged to form the final node representation.
Graphomer. We use 6 encoder layers with a hidden dimension of 64 and 4 attention heads; each layer includes feed-forward network with an embedding dimension of 128, and dropout rate of 0.1 is applied after multi-head self-attention. Graphomer uses the shortest path between any pair of nodes for spatial and edge encoding. Follow (Ying al. 202T). the length limit of the shortest path set to 5 by default.
GraphGPS. For the PE/SE of GraphGPS, our implementation, the input node features are projected to 64 dimensions, with 16 dimensions for PE/SE. The model stacks 10 GPSConv layers, each integrating GINEConv-based local aggregator and multi-head attention mechanism with 4 heads to capture global interactions. A 3-layer MLP with decreasing dimensions is applied for the final prediction.
RSWE with walk length of 16 by default. In
Si-GT. We use 6 encoder layers with a hidden dimension of 64 and attention heads; each layer includes foed-forward network with an embedding dimension of 128, and dropout rate of 0. is applied after multi-head self-attention. For mesh pattern encoding, we use 2 convolutional layers (e.g., EGATCoнw, GraphConv, SAGECony, GINConv in DGL.) with residual connection, and we set 0.2 dropout rate for node embeddings.
report the trainable model parameters of models Table 7
Table 7: Trainable parameter size of models.
Model
SAGE
DesPGCN
SCFormer
Grphhmmrr
GraphiPP
Si-T
Si-GT
Si-CT
S6-GT 290,221
49,921
52,486
99,329
85.953
210.561
273.261
282
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C.4 TRAINING CURVE
We plot the training loss curves for crosstalk delay and glitch prediction tasks in Figure 9 Across both tasks, Si-GT consistently achieves faster convergence and lower final training loss compared to other models.
0.030
GraphGPS
GraphGPS
Training Loss
Si-GT
Training Loss
0.025
Si-GT
Graphomer
Graphömer
DeepGCN
0.020
DeepGCN
0.010
0.005
3000 5000
5000
6000
Training Iteration (=7000Steps)
Training Iteration (<7000Steps)
(a) Crossall Delay Training Curve
(h) Crosstak Glitch Training Curve
Figure 9; Training curve of models for signal integrity analysis tasks.
D MORE EXPERIMENTS
D. MORE EXPERIMENTS WITH DIFFERENT STRUCTURAL ENCODING
In this section, conduct experiments with random walk structural encoding (RWSE) and Laplacian-based positional encoding (LapPE) for GraphGPS and our Si-GT. Specifically, we replace the mesh pattern encoding in Si-GT with RWSE and LapPE variants, and compare the performance against GraphGPS. In the experiments, we vary the random walk length with 4, 8, 16 for RWSE- based position encoding of GraphGPS model (e.g., RWSE16) and set 8 top eigenvectors of the graph Laplacian for LapPE (e.g., LapPE8). Additionally, we compare Si-GT with GraphGPS using composite position encoding (e.g.. LapPES-RWSEI6)) following the implementation in (Rampášek et al. 2022). we concatenate the LapPE and RWSE vectors to form the final positional encoding. Experimental results are reported Table g
Table 8: Mean relative accuracy (%) of crosstalk delay and glitch prediction results.
Segment Delay
Segment Glitch
Model
PE/SE
Dise
Dagg
wwihh
Umax
GraphGPS
LapPE8
87.76
71.69
96.15
97.30
GraphGPS
RWSE4
88.12
72.19
95.67
97.21
GraphGPS
RWSE8
88.24
71.97
95.14
97.69
GraphGPS
RWSE16
88.23
72.65
96.61
97.99
GraphGPS
RapPE8+RWSE166
88.28
72.92
96.49
97.83
Si-GT
LapPES
87.72
73.50
95.25
93.18
Si-GT
RWSE16
88.21
73.78
97.44
96.30
Si-GT
LapPE8+RWSE16
87.85
73.47
96.87
95.32
Si-GT
MPE
88.32
73.67
98.36
97.78
As shown in Table 8 Si-GT consistently achieves higher accuracy in delay and glitch width predic- tion tasks compared GraphGPS across various positional encoding configurations. These results highlight the effectiveness of our mesh pattern encoding (MPE) and demonstrate the robustness of Si-GT when combined with both LapPE and RWSE encodings.
D.2 INFERENCE EXAMPLES
We visualize the predicted values of key signal integrity metrics against the SPICE-measured ground truth in Figure IO For crosstalk glitch and crosstalk delay of victim prediction tasks, Si-GT con- sistently provides the closest match the ground truth across all metrics, demonstrating its ability
18

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Published as a conference paper at ICLR 2026
0.15
Ewicth (ms)
Vmarr (
Glitch
0.10
Glitch
0.10
0.05
0.05
S1GT
Graphomer
GraphGPS
Graphörs
0.00
DesyCCN
0.00
DespOCh
Node Index Along Victim Net
Node Index Along Victim Net
(a) Crosstalk Glitch Tustas
(b) Crosstalk Glitch Klaus
40
Grunn
S:GT
Delay (ps)
30
Graphomer
GraphiPS
Aggressor Delay (ps)
GraphePS
Graphomer
Victim
Doepoch
DeepUCN
20
10
0-
20
22
Node Index Along Victim Net
Node Index Along Aggressor Net
(c) Crossalk Delay Dise
(d) Crostalk Delay Dags
Figure 10: Comparison of crosstalk prediction accuracy with the number of wire segments.
to accurately model both local coupling effects and global signal dependencies. Additionally, present an example of aggressor delay prediction. Since capacitive coupling primarily affects the victim net, signal integrity analysis mainly focuses victim-side behavior.
D.3 FINE-GRAINED ABLATION EXPERIMENTS
summarizes the ablation results for the core architectural components introduced in Si-GT. All ablations are performed using the strongest Si-GT backbone selected for each prediction task, e.g., GCN for delay-segment, GAT for delay-sink, GIN for glitch- segment, and GCN for glitch-sink, following the configurations reported Table 2 and Table 3
Ablation experiment setup. Table 5
Additional analyses. To further understand the contribution of each component, we conduct more fine-grained ablation studies. In Equation 4 spatial encoding and edge encoding are incorporated as attention bias terms to better capture the global structural context of interconnect topology. In this section, we remove @dd and ssp from the attention bias to isolate their effect model performance.
Table 9: Ablation study the removal of spatial and edge encoding biases.
Delay Prediction
Glitch Prediction
Model
Segment
Sink
Segment
Sink
Dosc
D
Dac
Daxs
fussh
fusas
Si-GT--ithout dod, 6ap
72.84
87. 87.03
71.50
97.74
97.67 97.13
97.
Si-GT
88. 32
73.67
87.39
71.82
96.36
97.78
98.55
98.63
19


Reviews:
[{"review_id": "GUdsMBaQVN", "reviewer": "Reviewer_nnvC", "summary": "The authors addressed the challenge of signal integrity analysis in modern integrated circuits, where crosstalk-induced delay variations and glitches caused by capacitive coupling between interconnects can lead to performance degradation and functional failures. Traditional SPICE simulations, while accurate, are computationally expensive and inefficient for large-scale designs. They proposed Si-GT, a transformer-based framework that enables fast and accurate signal integrity analysis by incorporating virtual NET tokens for net-level representation, mesh pattern encoding for capturing high-order coupling structures, and an IIN attention mechanism to model both intra- and inter-net interactions.", "questions": "See the 'weakness' part", "limitations": "", "rating": 6, "confidence": 2, "soundness": 3, "presentation": 3, "contribution": 3, "strengths": "* The paper is well written, easy to follow\n* The authors performed various experiments with good performances.\n* The problem the authors aimed to address is an important one in this field.", "weaknesses": "* The authors evaluated the model performance with fixed hyperparameters. However, it would be more informative for other AI researchers if a broader hyperparameter search space were explored and a hyperparameter sensitivity analysis were conducted to examine how each hyperparameter affects the model’s performance.\n* In Figure 6, the performance of the graph transformer–based model is not clearly visible. Although this does not prevent readers from understanding the main conclusion of the experiment, there could be a better way to visualize the results.\n* It appears that the experiments were conducted only once and the performance was reported based on that single run. To ensure that the model’s performance is not dependent on a specific random seed but is statistically meaningful, it is necessary to repeat the experiments multiple times and report the mean and standard deviation of the performance.", "quality": null, "clarity": null, "significance": null, "originality": null, "strengths_and_weaknesses": "", "was_revised": false, "final_justification": "", "rebuttal": "", "claims_and_evidence": "", "methods_and_evaluation_criteria": "", "theoretical_claims": "", "experimental_designs_or_analyses": "", "relation_to_broader_scientific_literature": "", "essential_references_not_discussed": "", "other_strengths_and_weaknesses": "", "other_comments_or_suggestions": "", "questions_for_authors": "", "summary_of_paper": "", "summary_of_recommendation": "", "technical_quality": "", "clarity_of_presentation": "", "potential_impact": "", "robotics_focus": "", "quality_of_limitations": "", "questions_for_rebuttal": "", "reasons_to_accept": "", "reasons_to_reject": "", "questions_to_authors": "", "extra_scores": {}}, {"review_id": "4VHdlavumq", "reviewer": "Reviewer_Eseo", "summary": "This paper proposes Si-GT, a novel Graph Transformer model for fast and accurate signal integrity (SI) analysis in integrated circuit (IC) interconnects, specifically targeting crosstalk-induced delay and glitch prediction. The main contributions are:\n1. Model Design: Si-GT introduces three key components to embed physical priors into the Transformer architecture: (a) a virtual <NET> token to encode net-level signal characteristics (e.g., switching direction, slew rate); (b) Mesh Pattern Encoding (MPE) to capture local coupling structures at each node; and (c) an Intra-Inter Net (IIN) attention mechanism to explicitly model both intra-net signal propagation and inter-net capacitive coupling.\n2. Dataset Construction: The authors construct a large-scale dataset with 200,200 crosstalk delay examples and 187,309 crosstalk glitch examples, using SPICE simulations as ground truth. They claim this is the first dataset dedicated to interconnect SI analysis.\n3. Empirical Validation: Experiments show that Si-GT outperforms state-of-the-art GNN and Graph Transformer baselines in prediction accuracy while achieving orders-of-magnitude speedup over SPICE.", "questions": "1. Dataset Openness and Comparison: Will the proposed dataset be publicly released? If so, please confirm. Additionally, please provide a detailed statistical comparison (e.g., net count, coupling complexity, segment distribution) with datasets used in prior works such as Liang et al. (2020) and Liu et al. (2025).\n2. Missing Baselines: Why were GraphCAD (Liu et al., 2025) and Routing-Free Crosstalk Prediction (Liang et al., 2020) not included as baselines? Please add experimental results comparing Si-GT against these task-specific SOTA models.\n3. Attention Bias Design: The model combines IIN bias with Graphormer’s shortest-path (SP) and edge biases. What is the motivation for this combination? Specifically, could the SP bias conflict with \\phi_{Intra}, which already encodes distance via accumulated resistance ? Please clarify through ablation or analysis.\n4. Granular Ablation of IIN: The current ablation removes the entire IIN module. Please perform a finer-grained ablation by separately disabling \\phi_{Intra} and \\phi_{Inter} to quantify their individual contributions.\n5. Architecture Fairness: Since Si-GT uses GNN features as input to the Transformer, please compare against GraphGPS or GraphTrans variants that also use GNN-preprocessed features, to isolate the benefit of your proposed components (MPE, <NET>, IIN) from the general “GNN+Transformer” paradigm.\n[1] Liu et al., GraphCAD: Leveraging graph neural networks for accuracy prediction handling crosstalk-affected delays, ISPD ’25.\n[12] Liang et al., Routing-Free Crosstalk Prediction, ICCAD 2020.", "limitations": "", "rating": 4, "confidence": 3, "soundness": 3, "presentation": 3, "contribution": 2, "strengths": "1. Problem Significance: The paper addresses a critical and practical challenge in modern IC design—crosstalk-induced signal integrity degradation, which directly impacts chip reliability and timing closure.\n2. Physics-Informed Architecture: The proposed designs (<NET> token, MPE, IIN) are well-motivated by circuit physics and aim to inject domain-specific inductive bias into the model, moving beyond generic graph learning.\n3. Potential Community Impact: If made publicly available, the dataset could serve as a valuable benchmark for future research in ML for EDA, especially for crosstalk-aware modeling.", "weaknesses": "1. Dataset Limitations and Lack of Clarity:\n(1)\tThe paper does not state whether the dataset will be open-sourced, which is essential for reproducibility and community adoption.\n(2)\tThe synthetic data is based on a highly simplified topology of “2 aggressors + 1 victim”, which fails to reflect the complex multi-net coupling scenarios in real VLSI layouts. In contrast, recent work like GraphCAD (ISPD '25) uses real post-routing circuits from design contests, offering far greater realism and diversity.\n(3)\tThere is no quantitative comparison with statistics from prior datasets (e.g., number of nets, coupling density, net length distribution), weakening the claim of being “large-scale” and representative.\n2. Inadequate Baseline Comparisons:\n(1)\tThe paper omits comparison with task-specific SOTA models, notably GraphCAD (2025) and Routing-Free Crosstalk Prediction (Liang et al., 2020) , both of which directly address crosstalk modeling. This is a major oversight.\n(2)\tSi-GT uses a “GNN → Transformer” pipeline, yet it does not compare against generic GNN-Transformer hybrids (e.g., GraphTrans or GraphGPS variants with GNN preprocessing), making it unclear whether gains stem from architecture or the proposed inductive biases.\n3. Questionable Experimental Design:\n(1)\tIn ablation studies (Table 5), different Si-GT variants (e.g., Si-GT-GCN, Si-GT-GAT) use different GNN backbones, introducing confounding variables. A fair ablation should fix the GNN type.\n(2)\tThe performance gains over strong baselines like GraphGPS are marginal, raising questions about the practical significance of the added complexity.\n(3)\tThe paper adds Graphormer-style shortest-path (SP) and edge biases on top of IIN, but provides no justification for this design choice or analysis of potential redundancy/conflict between SP bias and the intra-net resistance-based bias.\n4. Presentation Issues:\n(1)\tFigure 3 (model overview) is abstract and poorly aligned with the text, reducing clarity.\n(2)\tExperimental details referenced in the main text (e.g., ablation setup) are missing in the appendix, undermining reproducibility.", "quality": null, "clarity": null, "significance": null, "originality": null, "strengths_and_weaknesses": "", "was_revised": false, "final_justification": "", "rebuttal": "", "claims_and_evidence": "", "methods_and_evaluation_criteria": "", "theoretical_claims": "", "experimental_designs_or_analyses": "", "relation_to_broader_scientific_literature": "", "essential_references_not_discussed": "", "other_strengths_and_weaknesses": "", "other_comments_or_suggestions": "", "questions_for_authors": "", "summary_of_paper": "", "summary_of_recommendation": "", "technical_quality": "", "clarity_of_presentation": "", "potential_impact": "", "robotics_focus": "", "quality_of_limitations": "", "questions_for_rebuttal": "", "reasons_to_accept": "", "reasons_to_reject": "", "questions_to_authors": "", "extra_scores": {}}, {"review_id": "LOZmJNfkcg", "reviewer": "Reviewer_kjJC", "summary": "This work proposed a fast interconnect signal integrity analysis by graph transformers. Their work modeled crosstalk effects explicitly with aggressor-victim switching interactions and signal pattern-dependent analysis, which are missing in the current works. They verified their ideas on the artificial dataset, whose samples were generated based on two aggressors and one victim.", "questions": "1. Why don't the authors compare their work with the related works in Section 2? I think the comparison will enhance the credibility of this work.\n2. The method in this work, whose goal is to reduce the computation of SPICE, may be more suitable for signal integrity analysis in the standard cell design. I suggest the authors perform experiments based on a standard cell library, e.g., ASAP7 or other commercial libraries. I wonder if the authors have plans to test their methods on this type of dataset?", "limitations": "", "rating": 2, "confidence": 5, "soundness": 2, "presentation": 3, "contribution": 2, "strengths": "1. Good modeling of the signal integrity analysis problem. Their work modeled crosstalk effects explicitly with aggressor-victim switching interactions and signal pattern-dependent analysis, which are missing in the current works. The consideration about net-specific signal characteristics (e.g., switching direction and slew\nrate) is meaningful for the prediction of crosstalk delay and glitch.\n2. The experiment shows more efficiency when compared with the simulation tool, e.g., SPICE.", "weaknesses": "1. The artificial dataset deviates from the realistic circuit design. Although the authors generate a massive dataset, they rely on only three nets: two aggressors and one victim. In the integrated circuit design, even the smallest circuits have more than three nets to build a specific function. I am concerned about the usability of this method in a realistic design flow.\n2. The experiments mainly compare with some classic graph learning algorithms, lacking comparison with other ML-based signal integrity analysis methods. In Section 2, the authors have a survey of related works in \"ML for SI\" and criticize them for not explicitly modeling signal pattern variability. But I still think this paper should be compared with the related works in some metrics, e.g., sink delay.", "quality": null, "clarity": null, "significance": null, "originality": null, "strengths_and_weaknesses": "", "was_revised": false, "final_justification": "", "rebuttal": "", "claims_and_evidence": "", "methods_and_evaluation_criteria": "", "theoretical_claims": "", "experimental_designs_or_analyses": "", "relation_to_broader_scientific_literature": "", "essential_references_not_discussed": "", "other_strengths_and_weaknesses": "", "other_comments_or_suggestions": "", "questions_for_authors": "", "summary_of_paper": "", "summary_of_recommendation": "", "technical_quality": "", "clarity_of_presentation": "", "potential_impact": "", "robotics_focus": "", "quality_of_limitations": "", "questions_for_rebuttal": "", "reasons_to_accept": "", "reasons_to_reject": "", "questions_to_authors": "", "extra_scores": {}}, {"review_id": "dKNcLwuesI", "reviewer": "Reviewer_DwGg", "summary": "The paper is trying to make better Graph transformers for modeling analog-level effects in circuits, which is quite a pressing problem. ML approaches for digital IC are developing, but for analog/mixed-signal-level interference and crosstalk, the efforts are in a nascent stage. The approach seems to outperform other graph-network like approaches for the problem, and they also make their own simulated dataset based on ground truth labels via synopsys tools.", "questions": "Please see the \"weaknesses\" section - in particular - the questions about industrial relevance and benchmarking to other methods.", "limitations": "", "rating": 6, "confidence": 3, "soundness": 2, "presentation": 2, "contribution": 2, "strengths": "Analog / mixed-signal modeling via ML models is understudied, and datasets are also hard to make and standardize. The paper takes steps towards both, and makes some effort to customize vanilla GT to make Si-GT work. Ablations seem reasonable as well.", "weaknesses": "There are some major weaknesses with this paper, stemming from setup, empirical eval, and industrial relevance.\n\nSetup : It is not clear at all why graph transformers or for that matter graph networks are the right lens to study this kind of circuit. Yes, it can be represented as a graph, but it is a highly regular, patterned graph. One can represent an image as a grid graph, but that does not make the graph neural network ideal for images. Why is it obvious that we need to solve this problem via GT ?\n\nEval : The dataset is mostly simulation-level, and it's very unclear that it reflects the industrial circuits (I understand that the standards are Intel/Synopsys based, but that does not mean the random sweep generates circuits relevant to industry). Further, the paper is evaluating its own methods on its own dataset, which makes it impossible to gauge impartially. (I do agree it is kind of a chicken and egg problem, which is why selecting pre-existing datasets will ease the question of impartiality). The baselines are fairly ad hoc and \"generic\" GT/GNN models, which may not be suitable. The layers also look a bit deep for this problem (GNNs are well known to suffer with depth)\n\nRelevance : In analog or digital IC, there are already pre-existing tools that can create the labels in question (indeed the paper uses them). The abstract says that this is not always feasible due to computational costs (true) but then the question becomes : what is the computational tradeoff of the papers' models vs running the tool itself ? This is not studied. We are of course ignoring the fact that even slight losses in accuracy relative to industrial standards are generally considered unacceptable.", "quality": null, "clarity": null, "significance": null, "originality": null, "strengths_and_weaknesses": "", "was_revised": false, "final_justification": "", "rebuttal": "", "claims_and_evidence": "", "methods_and_evaluation_criteria": "", "theoretical_claims": "", "experimental_designs_or_analyses": "", "relation_to_broader_scientific_literature": "", "essential_references_not_discussed": "", "other_strengths_and_weaknesses": "", "other_comments_or_suggestions": "", "questions_for_authors": "", "summary_of_paper": "", "summary_of_recommendation": "", "technical_quality": "", "clarity_of_presentation": "", "potential_impact": "", "robotics_focus": "", "quality_of_limitations": "", "questions_for_rebuttal": "", "reasons_to_accept": "", "reasons_to_reject": "", "questions_to_authors": "", "extra_scores": {}}]

Author rebuttal:

Decision: Accept (Poster)