Topology Matters in RTL Circuit Representation Learning
Authors: Mingyu Zhao
Xun He
Jiawei Liu
Jianwang Zhai
Chuan Shi
Venue: ICLR 2026 Poster (2026)
Keywords: RTL repressentation
EDA
Primary area: other topics in machine learning (i.e., none of the above)
TL;DR: A paper on learning RTL-level circuit behavior and topology representation.

Abstract: Representation learning for register transfer level (RTL) circuits is fundamental to enabling accurate performance, power, and area (PPA) prediction, efficient circuit generation, and retrieval in automated chip design. Unlike general programming languages, RTL is inherently a structured dataflow graph where semantics are intrinsically bound to the topology from a hardware view. However, existing language-model-based approaches ignore the nature of RTL circuits and fail to capture topology-sensitive properties, leading to incomplete representation and limited performance for diverse downstream tasks. To address this, we introduce TopoRTL, a novel framework that explicitly learns topological differences across RTL circuits and preserves the behavior information. First, we decompose RTL designs into register cones and construct dual modalities initialized with behavior-aware tokenizers. Second, we design three topology-aware positional encodings and leverage attention mechanisms to enable the model to distinguish topological variations among register cones and RTL designs. Finally, we introduce a topology-guided cross-modal alignment strategy, employing contrastive learning over interleaved modality pairs under topological constraints to enforce semantic consistency and achieve superior modality alignment. 
Experiments demonstrate that explicit topological modeling is critical to improving RTL representation quality, and TopoRTL significantly outperforms existing methods across multiple downstream tasks.

Published as a conference paper at ICLR 2026
TOPOLOGY MATTERS IN RTL CIRCUIT REPRESENTA- TION LEARNING
Mingyu Zhao's ; Xun "e'",, Jianwang Zhai"t CChann Shi Beijing University of Posts and Telecommunications, Thhe Chinese University of Hong Kong zhaomingyu@bur edu. en, hexungbupt. edu. en, liujw#cse cuhk. edu, hk zhai jheuutt eddu en, shichuar@bupt. edu. cn
ABSTRACT
Representation learning for register transfer level (RTL) circuits is fundamental to enabling accurate performance, power, and area (PPA) prediction, efficient cir- cuit generation, and retrieval in automated chip design. Unlike general program- ming languages, RTL is inherently a structured dataflow graph where semantics are intrinsically bound to the topology from hardware view. However, exist- ing language-model model- based approaches ignore the nature of RTL circuits and fail to capture aapology-sensitiie properties, leading to incomplete representation and limited performance for diverse downstream tasks. To address this, we introduce TopoRTI., a novel framework that explicitly learns topological differences across RTI circuits and preserves the behavior information. First, we decompose RTL. designs into register cones and construct dual modalities initialized with behavior- aware tokenizers. Second, we design three topology-aware positional encodings and leverage attention mechanisms to enable the model to distinguish topolog- ical variations among register cones and RTL designs. Finally, we introduce topology-gun -ggiddd cross-modal alignment strategy, employing contrastive learning over interleaved modality pairs under topological constraints enforce seman- tic consistency and achieve superior modality alignment. Experiments demon- strate that explicit topological modeling is critical to improving RTL represen- tation quality, and TopoRTL significantly outperforms existing methods across multiple downstream tasks.
INTRODUCTION
Artificial intelligence transforming electronic design automation (EDA) through representation learning. This approach maps circuits across abstraction levels into low-dimensional vector spaces, enabling unified modeling for critical tasks like PPA prediction, SAT solving, and circuit genera- tion (Li al. 2022b) Shi et al.] 2023 2024 Zheng al., 2025 Liu al., 2024bb 2025a b) Fang ct al. 2025). 3. This capability supports the design left-shift paradigm, moving performance prediction and issue detection to earlier stages, which reduces costs and accelerates optimization (Xing 2024
Zeng 2024).
Among digital circuit abstractions, register-transfer level (RTL) is crucial. It is typically described using Verilog as the industry-standard hardware description language. Naturally, many approaches treat RTL as software programming code, focusing on learning syntax and semantic meaning through text-based representations. For example, CodeV (Zhao et al., 2025) uses GPT-3.5 to gen- erate natural language descriptions from high-quality Verilog code and fine-tunes different large language models (LLMs) to enhance Verilog generation. Similarly, DeepRTL. (Liu et al.) 2025a) fine-tunes CodeTS+ on datasets connecting Verilog code to detailed descriptions, excelling in un- derstanding and generating RTL. DeepRTL2 (Liu et al. 2025b) further integrates generation and embedding tasks within a unified framework.
Unlike software programming languages, RTL is inherently a structured dataflow graph where behavior and topology coexist from a hardware view. explicitly specifies the flow data
" Equual contribution. 'Corresponding authors.

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Published as a conference paper at ICLR 2026
Functionally Inequivalent
Functionally Equivalent
Circuit
Circuit
Circuit C.
assign 0. - essign 2 always plpasedge 2,
assign assign 1 essign always Diposedge dik) sum 2
zssign assign always @iposeddee sum 2,
Sparse
Sparse
Denns
Structurally Similar
Struciurally Dissimilar
Figure 1: RTL is structured dataflow paradigm where behavioral intent is inseparable from dataflow topology. Circuit A and share similar topology but implement different functions. Circuit B and C implement identical four-input adders but with divergent topologies.
between hardware registers and the logical operations performed on that data, which reflects quite closely the logic structure of the circuit being modeled (TEEE) 2006). Crucially, RTL is not purely behavioral description (which abstracts away hardware structure) nor purely structural one (which specifies gate-level connectivity). Instead, represents structured dataflow paradigm where be- havioral intent is inseparable from topology (Micheli 1994). This tight coupling between behavior and topology necessitates that RTL be treated as a general programming language to learn.
While this text-based approach seems straightforward, we argue that topology matters in RTL repre- sentation learning. The topological structure of circuits directly influences their physical constraints and implementation details (Micheli 1994). For instance, in Figure Circuits A and B have similar topologies but produce different functions, while Circuits and C, both four-input adders, demon- strate performance variations due their topological differences. Circuit B's chain structure is less timely but more power-efficient than Circuit C's tree structure. Current methods typically use text- based approaches, often relying LLMs that struggle with graph-structured data (Li et al., (0224) making it challenging to capture circuit topological properties, leading to the following question:
Can we model RTL circuits by incorporating both behavioral functions and topological structure information?
To address the question, we analyze the fundamental nature of RTL circuits. As previously men- tioned, the sequential RTL circuit consists registers and combinational logic. When a signal propagates through the circuit, it undergoes cyclic process:
Computation Phase. Signals traverse through combinational logic networks where functional transformations occur. This phase determines the circuit's operational behavior. The density of in- tercomnections directly impacts implementation quality, as densely connected logic regions increase power consumption in physical implementation (Chandrakasan Brodersen] 2002). Meanwhile, the depth of propagation paths serves as critical determinant of timing performance.
Storage Phase. At clock edges, registers capture and maintain the results of computational pro- cesses, enabling sequential behavior and stateful operations. The bit-width of registers determines the precision data representation, directly influenced by the accuracy needs of functional opera- tions. It also acts as practical indicator of operational complexity in circuit design, significantly impacting circuit performance optimization (Lee et al. 2006).
This dual- dual-phase perspective highlights that topology is not just about combinational logic connec- tions; it is also an intentional representation behavioral function. Building on this idea, we propose TopoRTL, a novel framework that explicitly captures variations in topology while maintaining the semantics of behavior. Specifically, we design three topology-aware positional encodings that reflect the essential characteristics of storage and computation dimensions. And we utilize atten- tion mechanisms to enable the model recognize topological variations among different circuits. In addition, introduce a topology-guiie guided cross-modal alignment strategy that ensures semantic consistency between graph and textual modalities while adhering to topological constraints. This approach effectively models the intrinsic relationship between behavioral and dataflow structure.
To assess the efficacy of our proposed method, we carried out comprehensive experiments focused on PPA prediction and circuit retrieval tasks. These downstream applications are pivotal for effective
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eircuit optimization and generation. Our findings reveal that TopoRTL, characterized by its efficient and lightweight architecture, consistently outperforms or, at the very least, matches the performance of several advanced methodologies, including numerous large-scale language models. In addition, detailed analysis through circuit representation visualization and further analysis robustly reinforces central premise: topology matters in RTI. representation learning. This research offers fresh perspectives that significantly contribute to the advancement of circuit representation learning.
2 RELATED WORKS AND PRELIMINARIES
In this section, we provide systematic review of RTL representation learning approaches and present our data preprocessing pipeline. In Section 2.1 we analyze previous methods, categoriz- ing them into behavioral methods and topological methods, while also discussing their limitations stemming from the nature of RTL. Section 2.2 we outline our data preprocessing pipeline, which comprises two main components: register cone generation (Section 2.2.1 and multimodal data gen- eration (Section22) 2.2.2).
2.1 RELATED WORKS
Level in EDA. Register Transfer Level (RTL) a crucial abstraction in digital circuit design, where behavioral intent and structural topology cocxist. This unique abstract level makes RTL an excellent target for circuit representation learning, which supports downstream EDA applications by reducing design time and enhancing performance.
Register Transfer
Behavioral Modeling for RTL. Most approaches treat RTL as software code, focusing on learn- ing syntax and semanties through text representations, particularly with LLMs. For instance, Code' (Zhao et al.] 2025) uses GPT-3.5 to produce natural language descriptions from Verilog code, followed by fine-tuning LLMs enhance Verilog generation. DeepRTL (Liu al. (025a) presents a unified model for understanding and generating Verilog by fine-tuning CodeTS+ on dataset linking Verilog detailed language descriptions. DeepRTL.2 (Liu al. 2025b) extends this by combining generation with embedding- bbased tasks in RTL.
Topology Modeling for RTL. Traditional methods (Xu al. 2022 Fang al. 2023) for topology
modeling primarily use feature engineering to transform Verilog code into graph structures, relying on hand-crafted features that may lack semantic depth and generalizability. Recently, SNS v2 (Xu et al. 2023) categorizes circuits into register cones and employs functionally equivalent contrastive learning for pretraining, using this representation for downstream tasks. However, this approach sacrifices topological awareness in the process. For instance, it cannot differentiate between Circuit and Circuit C as shown in Figure [
Multi-modal Modeling for RTL. CireuitFusion Fang et al. (2025) pioneers multimodal represen- tation learning for RTL by integrating code, summaries, and graphs. To capture topological in- formation, it employs a cross-stage alignment strategy that utilizes post-synthesis netlists during pretraining, leveraging the physical implementation details to guide the behavior-aware contrastive learning process.
Overall, these approaches face significant limitations. Text-centric models often overlook the in- trinsic structured nature of RTL, while traditional topological methods lack semantic generalization. Furthermore, recent multimodal attempts like CircuitFusion rely on costly logic synthesis to implic- itly infer topology, limiting their efficiency and applicability in the design "left-shift" paradigm. In contrast, we propose TopoRTL, an RTL-native framework. Instead of depending on synthesis out- comes, TopoRTL. explicitly captures topological variations directly from RTL. via hardware-specific inductive biases while preserving behavioral semantics.
2.2
PRELIMINARIES: DATA PREPROCESSING
2.2.1 REGISTER CONE GENERATION
In line with the concept of sub-design partitioning, extract register cones through register- driven backward traversal. This process outlined in Algorithm [ and occurs in three phases. Phase 1. Given RTL design V with total of registers {R.) build signal dependency
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(CLS) token
Node token ① Add
Frozen Trainable
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(b) Topology-Awer Aware Positional Encoding with Transformer
(e) Topology-Guided Cross-Modal Alignment
Dual Modal Tokenizers
Figure 2: Overview of TopoRTI.
dictionaries that include signal declarations and combinational dependency information. Phase 2. We traverse the combinational logic from each register R, to its inputs/connected registers. Phase Using the identified signals, we generate syntactically correct subcircuits V which are verified using Yosys (Wolf et al. 2013), open-sourced logie synthesis tool. This implementation ensures complete and scalable decomposition for RTL designs. Details are provided in Appendix D.I
2.2.2 MEL.TIMODAL DATA GENERATION
Drawing on multimodal learning advances (Li et al. 2022a 2021: Liu et al. 2024a Zhao et al.
2023), construct two modalities explicitly modeling structural topology and behavior function:
(1) Graph modality: we transform each subcircuit V into a control-data flow graph (CDFG) G
where the nodes represent combinational logic and registers. while the edges encode signal connec- tivity. This approach is similar to the method described by Fang et al. (2025), explicitly modeling the topological structure. (2) Summary modality: we prompt GPT-OSS- 120B (OpenAl (025) to generate behavioral descriptions S:: capturing high-level functional intent for each subcircuit R. This dual-reprrsnntatiion framework enhances circuit behavior and topology learning.
METHODOLOGY
We introduce TopoRTL, a framework that integrates behavior functions with topology structure in- formation. As illustrated in Figure 2 TopoRTL has three key components: (1) Behavior-Awar Dual-Modal Tokenizers for extracting semantics from topology graphs and functional descriptions; (2) Topology-Aware Positional Encoding that incorporates bit-width centrality, signal path depth, and interconnection density into Transformer attention; and (3) Topology-Guided Cross-Modal Alignment that merges modalities while maintaining topological constraints. The representations generated by TopoRTL can be applied to tasks such as PPA prediction and circuit retrieval.
3.1 BEHAVIOR-AWARY DUAL-MODAL TOKENIZERS
To capture the behavior information circuits, we utilize behavior-aware dual-modal tokenizers that are trained through behavior equivalence contrastive learning task and mask modeling task.
Graph-Based Tokenizer. To capture topology-aw aware circuit semantics, we employ pretrained graph tokenizer that maps sub-cireuits to compact latent representations. For design decomposed
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into N sub-cireuits {G circuit GR, These representations are combined with global design-level [CLS]] token R to form the input sequence for downstream tasks:
Ji=1 the tokenizer outputs representation x E R for each sub-
X (x , x RN Fyr [
(1)
This sequence preserves hierarchical design semanties while enabling efficient processing by transformer-based models. For more details, please refer to Appendix
Summary-Basee Tokenizer. To capture behavioral semanties from circuit descriptions, we employ a pretrained summary tokenizer based on BERT that encodes textual summaries into semantic em- beddings. For a design with N sub-circuits and their textual summaries {S the tokenizer
outputs global [CLS] token embedding jR, E I These embeddings are combined with learnable global design-level [CLS] token (oo to form the input sequence:
T = =tt""" ,!"1² ....,,tRR"" E ()++N))
(2)
This sequence enables transformer models to jointly reason over circuit functionality, For more details, please refer to Appendix[D.2) D.2.2.
3.2
TOPO1.0YY-AAAR POSITIONAL ENCODING WITH TRANSFORMER
3.2.1 BIT- WIDTH CENTRALITY ENCODING
During the storage phase, registers preserve computational results where bit-width directly deter- mines the precision range of data representation. practice, complex operations (e.g., 32-bit arith- metic units) inherently require wider bit-widths to maintain accuracy, while simpler control signals (e.g., 1-bit flags) operate effectively with minimal precision (Lee et al. 2006). To enable the model to distinguish such functional hierarchies from circuit topology, we propose Bit- Width Centrality Encoding.
Bit-width Encoding. For each register R, we extract (R;) from Verilog declarations (e.g., reg [31:0] data;) ) to encode precision constraints as topology features. We first process the initial node features X and 5 from dual modalities through multi- luyti-layerrppe perception (MLP):
X MLP(X*) E (2++N)x S MLP((5)) E ((I+N)xd
where S E (1+ and N denotes the total number of registers and d is the feature dimension.
Subsequently, assign two learnable embedding vectors abit and az for each possible bit- witthidth value. These embedding vectors are accessed through a lookup table mechanism based on each register's actual bit-width:
l J. R.
OG
R: h =
as
BiX(R))
ISiS N,
(4)
where Re and s Rs are the features after MLP processing, and AG embedding vectors corresponding to the bit-width of register R, This positional encoding method helps the model associate bit-width values with functional complexity during topological learning.
bit(R)) and 0g
bit(H,)) are the learnable
3.2.2 MAX-PATH AND DENSITY DISCREPANCY ENCODING
During the computation phase, signals traverse through combinational logic networks, where high interconnection density raises power consumption due to increased parasitic capacitance (Chan- drakasan & Brodersen 2002). The propagation path depth also influences timing performance through the critical path length. To help the model differentiate these structural factors from cir- cuit topology, we introduce Max-Path and Density Discrepancy Encoding.
Max-Path Encoding, For each register cone GR, where i < N. we extract the maximum path length set:
I Rs = [dist R2, R2) exist path Rg + R; in GR.} 1 I where dist(R, Ry. R₂) represents the number of pseudo logic gates between registers R, and R,- Rather than relying solely on the absolute maximum path length, which can sensitive to out- liers, we select the Top-K longest paths and compute their mean for robust representation:
(5)
R MEAN(TOp-K(TT.)
S
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This approach captures the typical critical path behavior while mitigating the impact of anomalous paths. We then construct a relative matrix AL E RRXX X
where
Aly p 1 1 i
representing the discrepancy in critical path characteristics between register pairs.
Graph Density Encoding. For each GR,, we compute graph density as:
E.. No. (N - 1 i S
(8)
where ER, and N., denote the number of edges and nodes in the register cone, respectively. This metric quantifies how interconnected the logic surrounding register R; is, with higher values indi- cating more complex, tightly coupled functionality, We then compute a relative density discrepancy matrix Ap E RNXN, where
Apij = - ISiJSN.
3.2.3 TRANSFORMER WITH TOPOLOGY-AWARE ATTENTION
The Transformer architecture consists of composition of Transformer layers, each containing two key components: a self-attention module and position-wise feed-forward network (FFN). To illus- trate our approach, we specifically describe the process using the graph modality HG. Here, Ha serves as the input to the self-attention module with hidden dimension d, where each position repre- sents the i-th register in the RTL circuit. This input is projected into three matrices through learnable weight parameters W E Rdxdk, W E Rdxdk, and W E Ra to obtain the corresponding representations QG. KG, Vg:
Qa = HoW
KG = HaW Va = HaWW
(10)
Ag = QaKe
Attn(Hal = softmax (Aatmax(AG)Ve....
(11)
Vdk
where Ag captures the similarity between queries and keys. For clarity, we consider the single-head self-attention mechanism, assuming that dx dy d. This analysis is presented in the context of graph modality, where the summary modality is the same.
The vanilla Transformer architecture is powerful for sequential data but fails account for the unique topological properties of RTL circuits. Unlike linear natural language sequences, RTL cir- cuits have complex hierarchical structures where signal paths and connection densities are crucial for functionality. To overcome this limitation, we integrate our previously proposed Max-Pull and Density Discrepancy Encodings into the attention mechanism:
(1 W
(h R WkY
AGy-
ag Sa(( + 30 gG(Ap)))
(12)
Vd
where fa(-), 9a(+) R R exteed are learnable mapping functions implemented as MLPs, and og, 3G are learnable scaling parameters, and 1 S i, S N. This formulation enables the attention mechanism to dynamically adjust its focus based on both the timing characteristics and structural complexity of register relationships.
For the virtual node Ro representing the entire circuit, we manage its connections uniquely by re- setting all spatial encodings to distinct learnable scalars. The final circuit representation produced by processing the inputs through modified Transformer layers:
HG = Traphh-rramformrrHH... (Hc), Ag = -ummary- SSummmay-Transfomee Transforme(((HHH
(13)
3.3 TOPOLLOGY-GUIDED CROSS-MODAA ALIGNMENT
Achieving effective alignment across various modalities is essential for a thorough understanding of circuit representation learning. To enhance the model's ability to comprehend circuit topology,

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Table 1: PPA prediction results, and model specifications. The best, second-best, and third-best
results in each column are highlighted with bold, underlined, and italic fonts, respectively.
Circuit Data
Area
Power
Method
Type
Size
Dim
PCC1
R²t
RAPE,RRSE
R²T
MAPE, RRSEL
GCN-MLP
Graph
1.20M
7k
768
0.507
-0.934
20.878
0.873
0.378
-7.217
55.454
0.929
Graph
1.20M
7k
768
0.340
880062
17.569
0,969
0.314-82.122
125
50.316
0.972
Owen3-E-0.6B
Text
0.6B
1024
0.694
0,422
13.735
0.858
0.743 0.515
37.917
0.796
Qwen3-E-4B
Text
4B
2560
0.760
0.560
11.541
0.753
0.716 0.382
38.341
0.939
Qwen3-E-8B BBBB
Text
8B
4096
0.720 0.451
12.079
0.876
0.766 0.556
37.826
0.821
V-CI
Text
7B
165k
4096
0.795 0.596
11.574
0.661
0.812 0.633
39.448
0.623
V-DD
Text
6.7B
165k
4096
0.814 0.637
10.778
0.626
0.827 0.673
36.544
0.624
Code V-QC
Text
7B
165k
3584
0.818
0.662
10.830
0.648
0.805
0.622
37.314
0.678
CircuitFusion Multi 150.59M
768
0.647
0.378
13.242
1.085
0.657
0.393
43.073
0.993
TopoRTL
Multi 29.13M
7k
768
0.863
0.683
7.952
0.574
0.884
0.712
25.033 0.585
Slack
TNS
WNS
PCCT
MAPE|RRSE,
H²T
RRSE,
H²T
MAPE,
GCN-MLI
0.708
0.500
42.414
0.945
0.733
0.510
41.095
0.793
0.679
0.425
47.647
0.903
GCN-GNN
0.532
0.243
52.620
1.347
0.889
0.770
33.430
0.498
0.634
0.336
47.506
0.952
Qwen3-Eon E-6.6B
0.876
0.724
35.587
0.554
0.885
0.753
30.944
0.555
0.860
0.667
40.477
0.728
Qwen3-F-44B
0.881
0.753
35.162
0.570
0.884
0.777
39.324
0.520
0.839
0.686
52.680
0.718
Qwen3-E-8B
0,888
0.784
34.241
0.563
0.899
0.781
33.802
0.534
0.849
0.659
43.880
0.674
CodeV-CL
0.909
0.822
30.472
0.465
0.922 0.846
28.108
0.428
0.806
0.643
41.267
0,716
Code
0.881
0.758
32.712
0.579
0.928
0.848
31.857
0.383
0.780
0.600
41.750
0.735
Code V-QC
0.868
0.754
34.618
0.575
0.927
0.856
29.920
0.402
0.762
0.464
47.401
1.400
CircuitFusion 0.893
0.788
30.944
0.494
0.885
0.727
34.454
0.544
0.817 0.572
38.227
0.808
TopoRTL
0.909
0.821
31.249
0.443
0.872
0.743
32.016
0.521
0.862
0.723 40.
0.580
introduce topology-guide cross cross-modal alignment mechanism. This innovative approach capi- talizes on our previously encoded structural information, ensuring that meaningful correspondences established between modalities while honoring the inherent topology of the circuits.
Let Y (Ha, iis) E x2(+N)xxd and Z (fic, Hs) E R(1+N)x2d represent two complementary fusion patterns between the graph modality (Hc, HG) and summary modality (Hs, Hss) where N is the number of registers and d is the feature dimension. We compute their global representations
by taking the mean across nodes:
y MEAN(Y) R 1x22d
MEAN(Z) E R122d
(14)
Our topology guided approach uses structural constraints to align and while maintaining circuit topological properties. We employ a quadruplet loss that pulls positive pairs closer and ensures topological consistency by requiring the difference between y and 2 to be smaller than that of em- beddings from topologically dissimilar paths. Negative samples are randomly selected as graph modality fused embedding Yney and summary modality fused embedding Zneg from the batch. The contrastive learning loss is:
Lfuse y = l12 y| y Zneg 112 +3]+
- 112 -12-11 yneg +
(15)
where 3 is a hyperparameter that controls the margin of the distance between pairs of positive and negative samples, and [+]+ denotes max(0,.). This loss serves as the pretraining loss.
EXPERIMENTS
In this section, we conduct experiments address the following research questions:
RQ1: How does TopoRTL excel in deeeedent tasks? Does it effectively capture essen- tial topological dependencies for precise predictions?
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Lm5
L
L-10
L-15
0.8
0.8
0.5
0.4
0.1
0.0
Qwen3-E:0 dBQwen3-E:4B Qwen3-E-BB E-88
CodeV
CodeV-DS
CodeviQC
TopoRTL
Figure 3: Circuit Retrieve Performance.
RQ2: How well does TopoRTI. integrate topological structure behavior-sensitive tasks? Can
overcome the topological neglect in existing methods?
RQ3: Do TopoRTL embeddings maintain both local structural details and global topological relationships in hidden spaces?
RQ4: What unique contributions do its encodings make to representation quality?
4.1 EXPERIMENTAL SETUP
We begin by briefly outlining the dataset, baseline methods, and the evaluation tasks and metrics. For more detailed descriptions of the experimental settings, please refer Appendix B and C
Evaluation Tasks and Metrics. To evaluate the capability of RTL representation learning, we selected two downstream tasks: Performance, Power, Area (PPA) Prediction and Natural Lan- guage Code Search. The first is a regression task, using evaluation metrics such as PCC, R² MAPE, and RRSE. The second task is framed as a retrieval classification (Lu et al. 202I). with AUC as the evaluation metric. For further details, please refer to Appendix C
Circuit Dataset. We construct a dataset with 115 RTL designs collected from OpenCores (Albrecht
2005), VexRisev (Papon & Spinal 2024). IT (Corno et al., [2002), and DeepCircuitX (Li et al.,
2025 The circuit dataset has a wide range of circuit sizes, with different scales and functions. After extracting register cones, the dataset consists of 7,576 sub-circuits. For more information data collection, processing, and statistics, please refer to Appendix
Baseline Models and Implementation Details. We compare TopoRTL with baselines in three categories. (i) Graph modality models: Graph Convolutional Networks (GCN) with two types of finetune methods, c.g., GCN-MLP and GCN-GNN. (2) Text modality models: Open-source models
(abbreviated as Qwen3-E) (Zhang et al. (025) and Verilog-speciallzee CodeV (Zhao et al. (025). CodeV includes three variants: CodeV-CL- CLBBBB CodeVV-D-66.7 CodeV-
QC-7B. (2) Multimodal models: CircuitFusion (Fang et al. 2025 For more baseline information
and implementation details, please refer to Appendix C.4 and
4.2 PERFORMANCE ON PPA PREDICTION (RQ1)
To assess the ability to represent topology information, performed five PPA prediction tasks covering Slack, Worst Negative Slack (WNS), Total Negative Slack (TNS), Area, and Power metrics. Further details about PPA tasks can be found in Appendix I.I] while the experimental analysis area is detailed in Appendix D Based on Tables T we can draw the following observations:
Obs 1: TopoRTI. achieves holistic RTL modeling superiority through topology-behavior integration with lightweight architecture. Specifically, it dominates ppa metrics (1 5.5% Area PCC. t 6.9% Power PCC. 26.2% Area MAPE, 131.5% Power MAPE) and sets the timing benchmark (WNS PCC=0.862, RRSE=0.580, outperforming all baselines in critical- while matching Slack accuracy. Crucially, these improvements come with fewer parameters and training data, showcasing TopoRTL's effectiveness in capturing global topological dependencies that text-based models struggle with.
analysis
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Area
Power
Slack
-200
(a) Distribution of CircuitFusion. Power
Area
Slack
Componnt
TSKE Component
T998 Componett
(b) Distribution TopoRTL.
Figure 4: The distribution of hidden representations across different models and tasks.
4.3 PERFORMANCE ON CIRCUIT SEARCH (RQ2)
To evaluate behavioral representation capabilities, we conduct a natural language code search task critical for hardware design reuse and verification. Following [u et al. (2021), we evaluate with L negative designs (L E (5, 8, 10, 15)) per query, measuring performance via AUC. Further details regarding this task can be found in Appendix C.2 while the analysis of detailed experiment results
is presented in Appendix D.3.2 Based on Figure we derive the key insight below:
Obs 2: TopoRTL demonstrates superior performance and robustness across retrieval sce- narios. Our model maintains a stable performance near 0.8 AUC for all L values (5-15 negative samples), outperforming all baselines. This consistency stems from TopoRTL's joint modeling topology and behavior, emphasizing the importance of topology in RTL representation learn- ing. The topology-guided alignment mechanism filters out irrelevant samples, ensuring reliable behavioral matching even in noisy conditions, thus enhancing cross-modal retrieval accuracy and supporting scalable design across various hardware applications.
4.4 HIDDEN REPRESENTATIONS ANALYSIS (RQ3)
As demonstrated in the previous sections, TopoRTL effectively learns both topological and behav- ioral circuit characteristics. To further validate this, visualize the learned representations using t-SNE (Maaten & Hinton 2008). Embeddings are projected into 2D space. colored by normalized Area, Power, and Slack metrics. The analysis of detailed experiment results is presented in Appendix According to Figure 4 we can find that:
D.3.3
Obs TopoRTI produces well-structured embeddings that clearly distinguish between topologically diverse regions. The representations illustrate both continuous topological trends and distinct design regimes. For Area and Power, smooth gradients show how circuit scale sys- tematically corresponds to embedding position. In contrast, for Slack, non-overlapping clusters align with critical-pane topologies. However, CircuitFusion produces fragmented distributions, characterized by abrupt value jumps and severe cluster entanglement, which fail maintain ei- ther continuity or clear separation between design regimes. Additionally, isolated outliers within TopoRTL's Slack clusters suggest unresolved mismatches between RTL and gate-level implemen-

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Power
Power
Slack
Area
Retrieval
TNS
PCC
RASE
AUC
TopoRTL
wo_cross cacoss_moaaa__aaa Jess
wo we_graph, denssity
wo wo_mex_path
wo, wo_bit, didth
Figure 5: Ablation Study.
tations, resulting from abstraction loss and hierarchical misalignment. This points opportunities for further refining the topology features.
4.5 ABLATION AND FURTIER ANALYSIS (RQ4)
Abalation Study. To validate the contribution of each TopoRTL component, we conduct compre- hensive ablation experiments by systematically removing key modules. More details and analysis are provided in Appendix D.3.4 As shown in Figure 5 these experiments reveal:
Obs 4: Positional encodings improve performance across tasks. Bit-width encoding effectively captures topology and complexity, while max-path and density encodings show inconsistent re- sults, highlighting the need for complementary topological signals in circuit representation.
Obs 5: Topology-guided alignment favors topology fidelity. This approach prioritizes topology-semantic consistency, which may slightly reduce timing accuracy but significantly boosts other topological and behavioral tasks, underlining its importance for design optimization.
We recommend readers check Appendix D.3 for detailed experiments and analysis.
5 LIMITATION AND FUTURE DISCUSSION
While TopoRTL demonstrates significant improvements in RTL representation learning, several lim- itations warrant attention. First, scaling larger and more diverse RTL datasets would enhance the model's generalization across circuit architectures. Second, our current decomposition approach assumes synchronous sequential circuits and disrupts clock domain relationships during register cone extraction; future work should extend to handle asynchronous circuits through clock-aware decomposition strategies. Additionally, developing more sophisticated topology-award positional encodings could better capture complex signal propagation patterns. Addressing these limitations would further strengthen the framework's applicability to practical chip design scenarios.
CONCLUSION
In this work, we analyze RTL circuits that fundamentally operate as structured dataflow graphs where behavioral semantics and topological structure are inseparable. Inspired by this, we propose TopoRTL, novel framework that explicitly encodes topological relationships while preserving be- havioral functionality, Specifically, we develop dual modalities that are initialized using behavior- aware tokenizers and create three topology-aware positional encodings grounded in signal propaga- tion. Additionally, we introduce a topology-guite -ugdded cross-modal alignment strategy, enhancing the integration and interaction between the modalities. Extensive experiments across ppa and retrieval tasks definitively demonstrate TopoRTL's superiority in jointly capturing topological and behavioral characteristics, proving that topology matters in RTL representation learning.
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ETHICS STATEMENT
This work enhances representation learning for RTL circuits to improve automated chip design. Our research aims for more efficient hardware development, potentially leading to energy savings and advanced computational capabilities. While focusing on circuit representation, we acknowl- edge the broad societal implications of chip design automation. We adhere to the ICLR Code of Ethics, ensuring rigorous experimentation and accurate reporting of results. Our datasets consist of standard benchmark circuits, with no personal information or human subjects involved. We urge the chip design community to consider environmental impacts, maintain human oversight, and pro- mote transparency in Al-assisted design systems, committing to responsible research for societal well-being.
REPRODICIBILITY STATEMENT
To ensure reproducibility, we provide detailed descriptions of our methodology and experimental setup. All circuit datasets are sourced from open-source benchmarks, which provide complete doc- umentation of data processing procedures and statistical characteristics. These details can be found in Appendix B and Appendix Additionally, the source code publicly available at the following URL: htt.::ttps//// httpipp:://qitubb /wwptttttttt///////e com/ WTtp://BUT-GGAAAPPAOOTTII
ACKNOWLEDGMENTS
This work is supported by the National Natural Science Foundation of China (No. 62550138. 62192784, 62572064. 62472329, 62404021). the Beijing Natural Science Foundation (No. 4244107, QY24204), the State Key Lab of Processors. Institute of Computing Technology, CAS (No. CLQQ202544), the Fundamental Research Funds for the BUPT (No. 2025A14S20), and the Research Initiation Project for Introduced Talents of BUPT (No. 510224062).
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Appendix Table of Contents
The Use of Large Language Models
16
Dataset Details
16
Source Benchmarks
16
B.2 Dataset Process
17
Evaluation Details
18
PPA Prediction Task
18
Natural Language Code Search
19
Evaluation Framework
19
4 Baselines
19
C.5
Implementation Details
20
D
Pretraining and Experiment Result Details
21
D.I Register Cone Extract
D,2
Behavior-Aware Tokenizers Pretraining
22
D.3 Detail Experiment Analysis
23
Further Analysis: Robustness and Generalization
26
Circuit Scale Analysis
26
E.2
Cross-PDK Generalization Analysis
................................
27
Robustness Ability on Summary Noise
28
Circuit Functionality and Topology Similarity Analysis
29
Further Discussion and Future Outlook
30
Other Details
31
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Table 2: Circuit Benchmarks Statistics
Source Benchmarks
Circuit Size (Min, Avg, Max)
#Circuit
#Gate
#Token (Code)
#Register
ITC'99
18
(135, 5K, 22K)
(2K, 284K, 262K)
(5, 45.0, 252)
OpenCores
12
(360, 5K, 28K)
(IK, 182K, 1M)
(7, 59.8, 371)
VexRisev
13
(7K, 14K, 63K)
(112K, 232K, 1M)
(67, 141.2, 434)
DeepCircuitX
72
(64, 4K, 66K)
(187, 53K, IM)
(1,58.5, 1326)
Total
115
711K
14M
7576
A THE USE OF LARGE LANGUAGE MODELS
In preparing this manuseript, utilized Large Language Models (LLMs) solely general- purpose writing assistance tool for minor language refinement and grammatical correction. Specifi- cally, we utilized LLMs identify basic syntax errors, enhance sentence clarity, and ensure proper academic phrasing in non-technical sections of the text. We carefully reviewed and verified all con- tent produced with LLM assistance ensure accuracy and maintain scientific integrity. We responsible for all content in this manuscript, following ICLR's s policies on LLM usage.
B DATASET DETAILS
B.1 SOURCE BENCHMARKS
In this section, we provide an overview of the various hardware description languages (HDLs) circuit datasets used in this work.
B.1.1 ITC'99
The ITC'99 (Corno et al. 2002) benchmark circuits represent standardized set of circuits with char- acteristics typical synthesized designs. As one of the established unimodal benchmark datasets alongside ISCAS' 89 and EPFL, it continues to serve an important resource for circuit verification and testing methodologies.
B.1.2 OPENCORES
OpenCores (Albrecht 2005) is a prominent online community established in 1999 the devel- opment and sharing of gateware Intellectual Property (IP) cores. It serves as a collaborative plat- form where digital designers can showcase, promote, and discuss their work through forums and news channels. The OpenCores repository hosts diverse RTL designs, including DSP cores, crypto cores, memory cores, and various system-level implementations. As one of the largest open-source
hardware communities, provides version control system for source management and supports vibrant user community dedicated to free and open-source hardware collaboration.
B.1.3 VEXRISCV
VexRisev (Papon & Spinal, 2024 an FPGA-friendly 32-bit RISC-V CPU implementation. VexRisev supports M. C, and A RISC-V instruction set extensions with numerous optimizations, in- cluding multi-stage pipelines and data caching capabilities. Implemented SpinalHDL. VexRisev utilizes complementary plugins enhance functionality while maintaining streamlined core chitecture, making it particularly suitable for FPGA-based system-on-chip designs.
B.1.4 DEEPCIRCUITX
DeepCireuitX [Li et al. 2025 represents a holistic, repository-level dataset specifically curated to address limitations in existing RTL datasets. It provides comprehensive data and annotations across multiple abstraction levels, like chip. IP. module, and RISC-V. V. The dataset features multi-level source RTT. code spanning repository, file, module, and block levels, with corresponding annotations
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Frequency
Arca
40
D-tribttion staggrom
Frequency
Hatagram
Frequency
Wrns
Distrouzion Haltgran
-06
-A
Frequency
10
Distiiure
Histagram
-10
Irequency
Slack Dis oucion Histogram
400
-1.0
-0.8
-A.6
-04
-02
0.0
6.
Log-normalized Value
Figure 6: Label Distribution Statistics
generated by GPT-4o. establishes specialized benchmarks for RTL understanding, generation, and completion tasks, with detailed data distributions across different RTL categories as documented in its comprehensive dataset summaries.
B.2 DATASET PROCESS
This section details our data processing methodology and label generation approach for different downstream tasks. We first selected 115 syntactically correct sequential circuits from the afore- mentioned four open-source benchmarks that can be directly synthesized. We then generated task- specific labels for PPA prediction and circuit retrieval tasks.
PPA Label Generation. To address the heterogeneity of HDLs across different sources, including VHDL, Verilog. and SpinalHDL, we employed Yosys standardize all designs into a unified Verilog representation. Subsequently, synthesis tool, to automatically synthesize each RTL circuit into gate-level netlists. These netlists represent the actual circuit implementations composed of logic gates (e.g., ADD, INV, AND, etc.) and registers (DFF) from a specific technology library. The synthesis process employed the open- source NanGate 45nm standard cell library, with the comp le_ul tra command to ensure high- quality PPA metrics on the Pareto frontier, as verified by Fang et al. (2023). Finally, Synopsys PrimeTime was utilized analyze the gate-level netlists, extracting detailed PPA labels, which include timing metries such as Slack, WNS, and TNS, as well as measurements for Area and Power. The statisties related the RTL designs post-synthesis are presented Table Additionally, the distribution of labels can be found in Figure
utilized Synopsys Design Compiler, industry-standar logic
Query Generation. For natural language code retrieval experiments, we developed a two-stage query generation pipeline using large language models (LLMs) followed by embedding encoding. First, we prompted the LLM to generate detailed descriptions for each module within cireuit, cov- ering its name, inputs, outputs, functionality, and sub-module instantiations. Second, we concate- nated all module descriptions from the same circuit and prompted the LLM to produce a high-level functional summary that mimics human retrieval behavior. This two-stage approach offers two sig- nificant advantages: (1) it effectively mitigates the context window limitations of LLMs through modular processing, and (2) the resulting high-level circuit summaries present more challenging test for circuit representation models, better evaluating their ability to capture semantic function- ality rather than merely syntactic patterns. Here use GPT-OSS-120B to obtain descriptions
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and Drren3-Emeedding-e 8B embed them. For the prompts to generate module-level and design-level descriptions, please refer to Appendix
C
EVALUATION DETAILS
This section first introduces the two downstream tasks for evaluating pre-trained models, PPA pre- diction and natural language code retrieval, along with our unified evaluation framework. We then detail the selected baselines and their parameter configurations.
C.I PPA PREDICTION TASK
The Performance, Power, and Area (PPA) prediction task represents a critical design quality evalu- ation at the RTL stage, enabling early assessment of circuit implementation characteristies without full synthesis. We evaluate five key prediction tasks:
Register slack prediction: forecasting timing margins for individual registers, which identifies potential timing violation points in the circuit.
WNS prediction: estimating the Worst Negative Slack, representing the most severe timing vio- lation across the entire design.
TNS prediction: predicting the Total Negative Slack, which aggregates all timing violations to
indicate overall timing quality.
Power prediction: assessing the circuit's power consumption for energy efficiency evaluation.
Area prediction: determining the silicon footprint required for implementation, crucial for phys- ical feasibility and cost considerations.
Notably, register slack prediction operates at the sub-cireuit level, while the remaining four metrics are evaluated at the complete circuit level.
Metric. We employ four complementary metrics comprehensively assess prediction quality:
PCC: Pearson correlation coefficient, which assesses the linear correlation between predictions and ground truth. Formally, given the prediction value vector æ and the truth label y. it calculated as follows:
PCC E(e m myy)
V( m,) 2 my)??
where my is the mean of x: and my is the of y. The metric varies between -1 and 1. R2: Coefficient of determination, which measures the proportion of variance explained by the model. Formally, prediction value x and the truth label y with n samples, it is calculated as follows:
E.= -v,-
xz)²
R-
En (3) g)
where y= Σi= Vr. The best value score is 1.0, and it can be negative (because the model can be arbitrarily worse).
MAPE: Mean absolute percentage error, which Quantifies prediction error percentage of ground truth. Formally, prediction value x and the truth label with samples, it is calculated as follows:
MAPE = 100%
I1 y/
y4
This metric is nonnegative, and the lower the better. RRSE: Root relative squared error, which is a commonly used regression metric measure the prediction enror. Formally, prediction value and the truth label y with n samples, it is calculated as follows:
Σn (#; 31
RRSE
i=l (ys 77)
where # Σ. Vi-
This multi-metric approach provides a balanced evaluation, capturing both correlation strength and absolute prediction accuracy.
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C.2 NATURAL LANGUAGE CODE SEARCH
Natural language code search enables hardware designers to locate relevant RTL implementations through intuitive natural language queries, significantly enhancing design productivity and code reuse. This task involves embedding both natural language queries and circuit implementations into a shared semantic space, where relevance determined by vector similarity. For hardware design contexts, this capability is particularly valuable as it bridges the gap between high-level specifi- cations and concrete RTL implementations, accelcrating the design process and reducing manual search effort.
Metric. Following Lu et al. (202T), we formulate this as a retrieval classification problem. For each query, sample L negative circuit designs and measure ranking quality using AUC (Area Under the ROC Curve), a robust information retrieval metric that evaluates the model's ability to distinguish relevant from irrelevant designs across all possible classification thresholds. AUC values range from 0 to 1, with higher scores indicating superior retrieval performance, where 1.0 represents perfect ranking and 0.5 indicates random performance.
C.3 EVALUATION FRAMEWORK
To ensure fair and rigorous evaluation across diverse representation models, we implement stan- dardized assessment framework with strict separation of training, validation, and test phases. Our methodology proceeds as follows: First, models undergo pre-training on unlabeled RTL circuits, with hyperparameters carefully adhering to original publications to maintain implementation fi- delity. After pre-tree vre-training completion, we systematically extract circuit representations from multiple training epochs. For each downstream task, we then fine-tune consistent classification/regress head architecture using these representations, with the optimal pre-training checkpoint selected ex- clusively based on validation set performance. Crucially, the test set remains completely isolated throughout both pre-training and fine-tuning processes, guaranteeing unbiased evaluation.
This approach offers two significant advantages: (1) it decouples representation quality from down- stream task optimization, providing a cleaner assessment of learned representations; and (2) it en- sures fair comparison by standardizing the fine-tuning process across all models. Crucially, the test set remains completely isolated throughout both pre-traing pre-training and fine-tuning phases, guarantecing unbiased performance evaluation.
C.4 BASELINES
We evaluate TopoRTL against a comprehensive set of representative baselines spanning three fun- damental paradigms in circuit representation learning. These baselines were strategically selected to address critical research questions:
1. Can conventional graph approaches effectively capture RTL topology?
2. Can text-based models overcome their inherent limitations when processing structured RTL cir- cuits?
3. How do existing multimodal frameworks integrate topological and behavioral information?
By comparing against these diverse approaches, we establish rigorous evaluation framework that isolates the specific contributions of TopoRTL's topology-aware architecture while addressing the fundamental question of whether explicit topological modeling provides measurable advantages over conventional representation learning methods.
Graph Modality Models. Graph Convolutional Network (GCN) (Kipf & Welling 2017 has
demonstrated success in general graph representation tasks. Following the methodology established by bu et (2023), we implement a 3-layer GCN pre-training on functional equivalence contrastive learning tasks. Notably, [u et al. (2023) employs a hierarchical graph structure that constructs reg- ister dataflow graphs based on subgrahu connections during downstream tasks. To ensure both methodological fidelity and evaluation consistency, we implement two variants: GCN-GNN, which preserves the original hierarchical approach with graph-based fine-tumine tne-tuning: GCN-MLP, which aligns with unified evaluation framework by replacing hierarchical processing with standard MLP head. This bascline specifically tests whether topology alone, without explicit behavioral modeling, can adequately capture both topological structure and behavioral semantics of RTL circuits.
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Text Modality Models. We evaluate two leading text-based upproaches: (1) Qwen3-Embedding (Qwen3-E) (Zhang et al. 2025), a state-of-the-art open-source embedding model with excep- tional cross-linual capabilities and strong performance actoss multiple natural language processing benchmarks; and (2) CodeV (Zhao et al. 2025). a specialized Verilog code understanding frame- (finetune based
work with three variants- Code
laaallllaaa---ssttuuue (Roziere al.)
2.23), CodeV-DS-6.7B (finetune based on DeepSeek-Coder-6. 7 (Guo et 2024g), and
CodeV-QC-TI (finetune based on Qwen2.5-Coder-7B (Hui et al. 2024)). Qwen3-E serves as
general- pprepssee text representation benchmark, while CodeV variants represent the current state-of- the-art in hardware-speciff text modeling. These baselines collectively address the critical question of whether treating RTL as unstructured text (rather than recognizing its inherent graph structure) can effectively capture the essential characteristics of hardware designs, particularly the structured dataflow relationships that define circuit behavior.
Multimodal Models. CircuitFusion (Fang et al., 2025) represents the current frontier in multi- modal circuit representation, integrating graph topology, natural language summaries, and raw RTL code through cross-modal attention mechanisms. Unlike TopoRTL, CircuitFusion relies on cross- stage netlist representations during pre-training to indirectly infer topological information, rather than explicitly modeling RTL's inherent graph structure. This baseline employs multiple contrastive learning objectives during the pretraining stage, including functional equivalence tasks. For fair comparison, we remove the netlist encoder and only maintain the RTL. encoder.
C.5 IMPLEMENTATION DETAILS
All experiments adhere to rigorous implementation protocol designed to ensure fair, reproducible comparisons while maintaining fidelity to original methodologies.
Graph Modality Models. For GCN-based approaches, we implement a 3-layer GCN following the functional equivalence contrastive learning framework established in prior work (Xu et al. 2023). Functional equivalence pairs are systematically generated using Yosys for pre-training objectives. We maintain subgraph representation dimension at 768 across all graph models, with graph-level embeddings derived through sum-poo -oo-ppoling operations. For GCN-GNN, we preserve the hierarchical graph processing approach with 3-layer GCN fine-tuning heads as in the original implementation. For GCN-MLP, we replace hierarchical processing with standard MLP heads to align with our uni- fied evaluation framework. This dual- implemeeeentnnnnnn strategy enables direct comparison between architecture-peecfii optimizations and standardized evaluation protocols.
Text Modality Models. For text-based approaches, we directly interface with Hugging Face APIs to obtain embeddings from Spwen3-Embeddee and Code series models. Each circuit's 's representation
is generated by concatenating the function description with corresponding RTL code, with truncation applied for sequences exceeding maximum token limits. Notably, we adopt different embedding extraction strategies aligned with each model's design philosophy: for Code variants, we use the mean of all hidden states in the final layer the text embedding, while for DweendEEmeddding we utilize the last hidden state following its original implementation specifications. This approach ensures optimal utilization of each model's architectural strengths while maintaining consistent input processing across the text modality category.
Multimodal Models. For CircuitFusion implementation, we carefully follow its open-source code and published paper. The graph encoder employs a 7-layer Graphormer (Ying et al.. 2021), pro- ducing 768-dimensional graph representations. The summary encoder utilizes the first 6 layers of BERT (Devlin et al., 2019) (768- 1768-dimensional hidden and output spaces), while the code en- coder substitutes
for the originally proposed NV-Embd-V V1 (Lee et al., 2024) due to hardware constraints on NVIDIA RTX 3090 GPUs. This substitution is justified by (0wen3-Eibeedding-0..f1
superior performance on the Massive Text Embedding Benchmark (MTEB) while maintaining the same 32K maximum input token capacity. Code embeddings (1024 dimensions) are linearly projected to 768 dimensions to maintain representation space consistency, with modality fusion handled by the final 6 layers of BERT.
Evaluation Framework. All models employ a standardized -68-iiennsiona output representation and undergo 50 pre-training epochs, with batch sizes adapted to graph scale: 128 for subgraph- based pre- pre-training and 6 for full-graph pre- pre-traine training. Text modality models are excluded from pre-training as their representations directly obtained via API inference. Crucially, our evaluation protocol
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extracts circuit representations at multiple pre-training epochs, with downstream task performance determining the optimal checkpoint selection based solely on validation set metrics. Dataset parti- tioning follows 30%-30%--40% (trainvalliatiion-eey) split at the circuit level, rather than subgraph level, to accommodate both global and subgraph-Ievel downstream tasks while preventing data leak- age. This partitioning strategy reflects real-world scenarios where substantial unlabeled data ists, emphasizing model generalization capabilities. All experiments were conducted on NVIDIA GeForce RTX 3090 GPUs.
D PRETRAINING AND EXPERIMENT RESULT DETAILS
D.1 REGISTER CONE EXTRACT
Algorithm Register Cone Extraction via Register- Driven Backward Traversal
Input: RTL circuit V, Total registers {
Output: Register cones {V R. J.V
Phase 1: Build Signal Dependency Dictionaries
1: D.C + Parse Verilog(V)
Extract signal declarations D and combinational dependencies C
Phase 2: Backward Traversal from Registers
2: for each register Rg E (R,) do
3:
Q + GeiDriiingSignalss
>> Initialize with RHS signals of R;
4:
$ - [Ra]. Ln + [R.). CÓ1 + Ge1OutuuDeec((R.) do u + Q deequeee
5:
while Q
6:
7:
if u E S then
8:
< SU {w]
9:
Inn < Inn [u} IenppttOOee
Register-to-input conversion >> Add signal latlarattioonsssnnmmeoeo
10:
CO1 + COI GeiCodeLines u, D, C))
Q - ExtractDepeedencies/ C)
> Backward propagate RHS signals
& Note: If is input/registerr, ExtractDependdeccies u. C) returns empty set
end
13: end while
Phase 3: Sub-circuit Generation and Verification
14: R:: <- GenerateModule(((n. R2, COI)
15:
VenifyWithYosss(\3) 16: end for
Check for syntax correctness
17: return [V
The register cone extraction process (Algorithm [ systematically decom- poses RTL design into functionally complete subcircuits through three stages, ensuring both accuracy and scalability.
Algorithm Overview:
Phase 1: Build Signal Dependency Dictionaries. Verilog code is parsed to extract two critical data structures: D. dictionary mapping signals to their declarations; C, a directed graph encoding combinational dependencies between signals. These dictionaries enable precise tracking of signal origins and propagation paths, forming the foundation for subsequent traversal.
Phase 2: Backward Traversal from Registers. For each register R,, the algorithm initializes queue Q with its driving signals (RHS signals) and collects output declaration information COI. It then performs backward traversal through combinational logic: starting from R. it dequeues signals u, adds them to the signal set S if unvisited, and converts their input connections Iix. to corresponding declaration types (c.g., mapping register inputs to wire declarations). The traver- sal propagates upstream by enqueuing signals from u's dependencies in C, recursively capturing all signals causally influencing RG value, including indirect paths through intermediate regis- ters. This phase ensures completeness by exhaustively tracing all upstream dependencies while avoiding redundant processing.
Phase 3: Sub-cireuit Generation and Verification. Using the collected signals S and converted declarations, the algorithm generates a syntactically correct Verilog module R for each register cone. This module includes: (1) all signals in S, (2) the original register R; and its driving combinatorial logic, and (3) corrected input declarations to ensure standalone functionality. To validate correctness, the generated subcircuit is verified using Yosys (Wolf et al., 2013), checking
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for proper syntax, valid assignments, and resolved signal references. This step guarantees that each partitioned subcircuit is synthesizable and maintains behavioral integrity.
This framework achieves scalable and accurate decomposition by leveraging backward traversal to capture causal dependencies, ensuring completeness without over-inclusion. The integration of Yosys validation further enforces syntactic and functional correctness, making the approach robust for large-scale RTL designs.
D.2
BEHAVIOR-AWARD TOKENIZERS PRETRAINING
D.2.1 GRAPH TOKENIZER
Graph Transformers have emerged as a powerful paradigm for modeling graph-structured data, directly addressing critical limitations of traditional message-passing GNNs, such the over- smoothing problem. By replacing localized neighborhood aggregation with global attention mech- anisms, Graph Transformers dynamically capture long-range dependencies while preserving struc- tural uniqueness across all nodes. In this work, we adopt Graphormer (Ying et al.) (021) as our graph tokenizer to encode circuit topologies. Formally, given sub-circuit G with N nodes, the output of tokenizer is:
x R4
R = Graph-Tokeeizerr(G""
(16)
where R E R xd is the node feature matrix, and R: E Rixd a learnable [CLS] token to represent the global information.
Behavior Equivalence Contrastive Learning. To embed behavioral semantics into topology rep- resentations, we enforce that functionally equivalent circuits map similar latent spaces. Given sub-circuit GR,, we generate positive samples G using Yosys, which applies random structural transformations (e.g., gate resynthesis. buffer insertion) while preserving functional equivalence. Negative sample G is randomly selected from the same batch. We then optimize contrastive loss using the TripletMarginl
LCL = ||| x
pos
n.
21
Ineg 112 +B]+, -
(17)
where 3 is a hyperparameter that controls the margin of the distance between pairs of positive and negative samples, and [+]+ is shorthand for max(0,-).
Masked Node Modeling, To help the model learn the topology connection relationships, we intro- duce reconstruction task where random nodes are masked and their features predicted. For encoded node features X R2, we use a learnable [MASK] token to randomly mask nodes and obtain masked features X The model then reconstructs the original features of masked nodes via a lightweight decoder head, optimized with mean squared error (MSE) loss:
Lmask
Σ
|| (Xecoder(XX.)) x, 112
(18)
I
JEMØ
where M denotes the set of masked nodes. The total pretraining loss combines both objectives:
-tkeniseo AiCeL + Amasks
(19)
where Å1 A2 balance task contributions.
Input Representation. After pretraining the graph tokenizer, we initialize the representation using the [CLS] token in each sub-cireuit and construct the input sequence for the entire design with a learnalle global [CLS] token Ro:
X Ro RR "...,,RR'' TyT E R1+Nix
(20)
D.2.2 SUMMARY TOKENIZER
Transformer-based language models have revolutionized natural language processing by effec- tively capturing contextual relationships through self-attention mechanisms. In this work, we adopt BERT (Devlin al., 2019) as our summary tokenizer to encode textual descriptions of circuit be- haviors. Formally, given textual summary SR for sub-circuit R; the output of the tokenizer is:
R. R. Honmmary-Tokenizerrr
(21)
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where T TT xd is the token feature matrix with TL representing the sequence length, and R:: E IR 1xd is the [CLS] token embedding that captures the global semantic representation of the summary.
Behavior Equivalence Contrastive Learning. To align textual representations with functional cir- cuit semanties, we enforce that summaries describing functionally equivalent circuits map similar regions in the embedding space. Given a sub-cireuit Sth;, we generate positive samples Spo. by applying random but tunetion-preserving transformations the original circuit using Yosys, then re-generating the textual summary. Negative samples S Sne, are randomly selected from the same batch. We optimize the following contrastive loss using TripletMagginLos::
LeL - - 1| th.
Reg 1l +
(22)
where 3 is hyperparameter that controls the margin of the distance between pairs of positive and negative samples, and [+]+ is a shorthand for max(0,.).
Masked Language Modeling. To enhance the model's understanding of linguistic structure and circuit-specific terminology, we implement the standard BERT pretraining objective. After ran- domly masked tokens, the model then predicts the original tokens at masked positions through classification head over the vocabulary. Formally, given masked token features T',. the mask loss is computed as:
Cmlm
1
Σ JEM
log (T, ,T A )::,
(23)
MM
where S denotes the set of masked token positions, A Rt, the attention mask, and pa repre- sents the probability distribution predicted by the model. The total pretraining loss combines both objectives:
Ssummary- tokenizer Aahor. + Xa
(24)
where A3 A4 balance task contributions.
Input Representation. After pretraining the summary tokenizer, we extract the [CLS] token em- bedding from each summary to represent its semantic content. We then construct the input sequence for the entire design by concatenating these embeddings with a learnable global [CLS] token Ro:
7 (t , RRTTT
Rx T 7TT (1+NN)x
(25)
D.3 DETAIL EXPERIMENT ANALYSIS
D.3.1 RQI: PPA PREDICTION
To assess the ability to represent topology information, we performed five PPA prediction tasks focused on key metrics in circuit optimization. Timing Performance: Slack measures timing com- pliance post-synthesis, with Worst Negative Slack (WNS) indicating the largest timing violation, and Total Negative Slack (TNS) summing all violations to guide optimization efforts. Area Perfor- mance: Area refers to the total silicon area required for the circuit, crucial for feasibility and cost. Power Performance: Power measures the circuit's energy efficiency. Based on Tables we can draw the following observations:
Obs: TopoRTL achicves superior area and power prediction with minimal resource over- head. Specifically, it outperforms the best baseline by 5.5% in Area PCC and 6.9% f in Power PCC, while slashing MAPE errors by 26.2% J for area and 31.5% J for power. Crucially, these im- provements come with fewer parameters and training data, showcasing TopoRTL's effectiveness in capturing global topological dependencies that text-based models struggle with. Obs: TopoRTI. exhibits competitive timing performance due
lightweight design. achieves the highest WNS prediction (PCC=0.862, RRSE=0.580), outperforming all baselines critical-path topology modeling. Although doesn't match the CodeV family for some tim- ing tasks, it matches Slack PCC and surpasses most in RRSE, emphasizing the significance of topology-belin behavior integration. TopoRTL's WNS performance highlights its potential for timing optimization and scalability.
Obs: CodeV highlights domain-specific fine-tuning benefits but faces task-specific limita- tions. It shows substantial gains over non-finetuned Qwen3, underscoring the critical role of
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specialized training for RTL tasks. However, its improvements constrained e.g., it underper- forms Qwen3-E-0.66 in WNS prediction and fails to achieve balanced results across all ppa tasks, revealing inherent limitations in model generalizability.
exhibit poor accuracy due to topology- agnostic pretraining. Their functional-aware contrastive learning discards essential eircuit topol- ogy, as evidenced by identical graph representations for structurally distinct circuits (c.g., Circuit B vs. Circuit C in Figure D.. GCN-MLP typically outperforms GCN-GNN due the invalid ho- mophily assumption in circuit graphs and ovor-sno effects, while GCN-GNN excels in TNS tasks, indicating an edge in global analysis. Both models highlight that simple graph conversion isn't enough, emphasizing the need for topology-integrant weak performance arises from topology information loss in architec- ture and pretraining. CircuitFusion processes RTT. code using functional contrastive pretrain- ing focused on behavioral equivalence rather than topological relationships. While it converts RTL to CDFG representations, it fails to capture crucial copology-sensitiin circuit information, as confirmed by GCN-GNN and GCN-MLP models. Our analysis shows that topology awareness depends cross-stage netlist alignment: without this data, the model's topological awareness diminishes, degrading the reliability of timing predictions and underscoring the importance of topology.
Obs: GCN-based models (GCN-MI.P/GCN-GAN
designs in effective circuit modeling.
Obs: Circuit
Table 3: Detailed results of retrieval experiments.
AUC1
Method
L.=5
L-8
L=10
T==55
GCN-MLP
0.684
0.630
0,504
0.499
GCN-GNN
0.664
0.507
0,500
0,500
Qwcn3-F-006B
0.495
0.545
0.531
0.497
Qwen3-E-4B
0.489
0.512
0.505
0.500
Qwen3-E-8B
0.511
0.509
0.499
0.500
CodeV-CL
0.629
0.655
0.637
0.485
CodeV-DS
0.551
0.523
0.572
0.631
V-CC
0.522
0.530
0.509
0.509
CircuitFusion
0,674
0.674
0.666
0.670
TopoRTL
0.787
0.804
0.760
0.783
D.3.2 RQ2: CIRCUIT RETRIEVE
To evaluate behavioral representation capabilities, we conduct a natural language code search task critical for hardware design reuse and verification. Following [u et al. (2021). we evaluate with L negative designs (L E (5,8, 8, 10, 15)) per query, measuring performance via AUC. Further details
regarding this task can be found in Appendix C.2 Based Figure 3 and Table 3 we derive the key insights below:
Obs: TopoRTL demonstrates superior performance and robustness across retrieval scenar- ios. Our model maintains a stable performance near 0.8 AUC for all L values (5-15 negative samples), outperforming all baselines. This consistency stems from TopoRTL's joint modeling of topology and behavior, emphasizing the importance of topology in RTL representation learn- ing. The topology-guided alignment mechanism filters out irrelevant samples, ensuring reliable behavioral matching even in noisy conditions, thus enhancing cross-modal retrieval accuracy and supporting scalable design reuse across various hardware applications.
Obs: CodeV validates domain adaptation efficacy in retrieval tasks through consistent gains over Qwen3. It achieves a higher AUC than non-finetuned Qwen3 across all negative sample lengths (5-15 negative samples), demonstrating that RTL-specific fine-tuning effectively captures behavioral semantics for retrieval. This reinforces domain adaptation as a critical strategy, though its task-specific limitations persist.
Obs: GCN models approach behavioral retrieval performance but reveal topology's 's critical role. While GCN models generally trail behind CircuitFusion, they surpass LLMd-baeed models in retrieval AUC, confirming that graph modality with functional contrastive learning effectively captures behavioral semanties. However, their consistent underperformance against TopoRTI.
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demonstrates that behavioral modeling alone is insufficient; precise topological integration mains indispensable for robust cross- modal retrieval.
D.3.3 RQ3: HIDDEN REPRESENTATION ANALYSIS
As demonstrated in the previous sections, TopoRTL effectively learns both topological and behav- ioral circuit characteristics. To further validate this, we visualize the learned representations using 1-SNE (Maaten & Hinton, 2008). Embeddings from our model and CircuitFusion (selected as it matches TopoRTI's output dimension and training data scale) are projected into 2D space, colored by normalized Area, Power, and Slack metrics. According to Figure we can find that:
Obs: TopoRTL preserves continuous topologiaal trends in representation space. In Area and Power visualizations (Figure 4b). TopoRTL exhibits smooth, coherent gradients along t-SNE dimensions, evidenced by seamless purple-to-yellow shifts for Area and Power. This reflects pre- cise modeling of topological scaling effects (c.g., larger circuits systematically mapping to higher Area/Power regions). Conversely, CircuitFusion (Figure4aa) shows fragmented, discontinuous dis- tributions with abrupt value jumps (e.g., isolated high-Power clusters amid low-Power regions), indicating failure to capture topological continuity. This validates TopoRTL's copology-guides alignment in preserving quantitative design variations.
Obs: ToLoRTL achieves topology-awars clustering for discrete design regimes. For Slack prediction (Figure 4b),, TopoRTL forms distinct, non-overlapping clusters: high-Slack circuits (orange/yellow) cleanly separate from low-Slack regions (blue/purple), directly corresponding to critical-path path topologies. CircuitFusion (Figure 4a) exhibits severe cluster entanglement, proving its inability to disentangle topologically critical states. This confirms TopoRTL's unique capacity encode discrete topological regimes essential for timing-critical decision making, a capability absent in behavior-only models.
Obs: Discrete representation gaps TopoRTL hint at RTL-to-gate-level topological mis- matches. While TopoRTL successfully clusters Slack values, isolated outliers (e.g., yellow points) suggest unresolved discrepancies between abstract RTL descriptions and concrete gate-level im- plementations. These gaps likely stem from: (1) Abstraction loss: RTL netlists omit low-level details (e.g., buffer insertion, wire routing) critical for precise timing analysis; (2) Hierarchical misalignment: Modular RTL components may map non-linearly to flat gate-level structures, dis- rupting topological continuity. This observation highlights the necessity for improved and well- designed topology features.
D.3.4 RQ4: ABLATION AND FURTHER ANALYSIS
Abalation Study. To rigorously validate the contribution of each TopoRTL component, we conduct ablation experiments by systematically removing key modules: (1) w/o Bit-width: eliminating bit- width centrality encoding a hit and feeding initial embeddings directly to the transformer; (2) w/o Max-path: discarding max-path discrepancy encoding AL during attention score computation; (3) w/o Graph density: removing graph density encoding Ap from attention mechanisms; (4) w/o Cross- loss: replacing topology-guides alignment with standard contrastive learning between isolated graph and text modalities. As shown in Figure and Table 4 these experiments reveal:
Obs: Positional encodings yield balanced performance across diverse downstream tasks. Bit-width centrality encoding improves performance by effectively capturing both topology and functional complexity. In contrast, max-path and density encodings demonstrate varying impacts due to gaps between RTL and netlist representations. This suggests that comprehensive repre- sentation of a circuit requires complementary topological signals.
Obs: Topology-guidee accuracy. By enforcing copology-semantee consistency, the alignment ensures behavioral descrip- tions honor physical constraints, which is necessary trade-off for design left-shift that slightly constrains timing prediction (e.g.. TNS) while significantly boosting other topological and be- havioral tasks. This confirms that apology-guiide alignment is helpful for end-to-end design optimization.
cross-modal alignment prioritizes topology fidelity over pure timing
Effect of Dataset Scale. As noted earlier, TopoRTL slightl underperforms larger models timing tasks due to its small pretraining dataset. Given EDA's scarcity of labeled data, evaluating low-label generalization is critical for real-world deployment. To assess scalability and data efficiency,
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Table 4: Detailed results of the ablation study
Area
Power
Slack
Model
PCC1 R MAPE, RRSE. PCC1 R² HAPEURRSE,
R²'t
MAPE RRSE,
TopoRTL
0.863 0.683
7.952
0.574
0.884
0.712 25.033
0.585
0.909
0.821 31.249
0,443
w/o cross modal loss 0.839 0.662
8.992
0.602
0.859 0.695 28.098
0.636
0.892 0.792
32.720
0.491
w/o graph density
0.851 0.692
8.794
0.572
0.874 0.689 29.777
0.621
0.873 0.744 38.662
0.536
w/o max path
0.854 0.705
8.634
0.565
0.871 0.694 27.998
0.616
0.890
33.599
0.525
w/o bit width
0.838 0.693
9.354
0.645
0.792 0.553 34.159
0.755
0.854 0.709 32.479
0.707
only graph density
0.836 0.696 9.652
0.632
0.812 0.627 37.818
0.649
0.837 0.690 35.348
0.717
only max path
0.816 0,660
10.085
0.730
0.831 0.637
32.198
0.645
0.838
0.605 40.505
0.664
only bit width
0.835 0.663 8.889
0.614
0.814
0.611
29.139
0.669
0.856
0.717 39.541
0.557
TNS
WNS
Retrieval
PCC1
H8t
HAPE,RRSES PCC1 R²t
MAPEIRRSE
AUC1
TopoRTL
0.872 0.743 32.016
0.521
0.862
0.723
40.130
0.580
0.787
w/o cross modal loss
0.902 0.800 31.776
0.444
0.869 0.710
35.936
0.633
0.759
w/o graph density
0.867 0.723 32.821
0.515
0.867 0.734 41.962
0.555
0.771
w/o max path
0.901 0.778 32.937
0.503
0.896 0.760 41.148
0.564
0.781
w/o bit width
0.882 0.722 37.991
0.601
0.813 0.545 41.096
0.913
0.723
only graph density
0.893 0.762 36.002
0.504
0.855 0.642 42.884
0.840
0.709
only max path
0.858 0.663 34.672
0.584
0.726 0.265 55.031
0,988
0.684
only bit width
0.896 0.773 33.819
0.446
0.867
0.739 44.679
0.526
0.760
CircuiiFusion
Coowk-DS-6.7 CodeV-gG-78
E-Enb-ddiigiiggggg GCN_GNN
PCCINUC
TopoRTL
Slack
TNS
WNS
1.55
0.8
08
122
<.5
0.2
08
0.2
0.2
6.4
02
Solt: Ball
Retrieval
0.85
2.35
3.0
0.75
1.25
04-
100
-25
9.6
10
5olt Pate
5c 7u
Spli:
Figure 7: Split Ratio Results.
train TopoRTL at 10%, 20%, 30% (default), and 40% label rates, using equal validation splits with the remainder test data. As shown in Figure 7 results reveal:
Obs: TopoRTL surpasses larger models across more tasks at sufficient label rates. The model initially underperforms baselines at lower label rates (10% and 20%), but consistently surpasses or at least matches all competing approaches when label rates reach 30% and 40%. This progression confirms that TopoRTL's topology-aware architecture efficiently learning the topology and behav- ior information, proving its viability for industrial EDA pipelines where labeled data gradually accumulates.
E FURTHER ANALYSIS: ROBUSTNESS AND GENERALIZATION
E CIRCUIT SCALE ANALYSIS
Real-world applications involve diverse circuits with varying functionalities and sizes, necessitating representation models that possess both robustness and scalability. To further investigate model
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Table 5: Performance comparison across different circuit scales. (MAPE%)
Method
Task
Small
Medium
Large
Mean
Std
Area
8.178
6.231
11.924
8.778
2.893
Power
28.4
18.846
29.094
25.447
5.727
TopoRTL.
Slack
62.187
37.242
33.587
44.339
15,565
TNS
45.243
15,834
24.954
28.677
15.054
WNS
53.362
25.937
27.414
35.571
15.425
Area
14,001
8,273
24.285
15.520
8.113
Power
54.046
24.835
50.857
43.246
16.024
CircuitFusion
Slack
59,419
36.396
25.491
40.435
17.321
TNS
50.146
12.485
33,930
32.187
18.891
WNS
46.580
30.336
27.172
34.696
10.413
Area 11.818
8.504
13.058
11.127
2.354
Power
48.724
22.734
26.950
32.803
13.948
CodeV-DS
Slack
63.297
32.643
30.260
42.067
18.425
TNS 46.043
18.053
14,222
26.106
17.372
WNS
52.151
31,809
28.311
37.424
12.874
performance across different scales, we partitioned the test set based on post-synthesis logic cell counts into three categories: Small (< 1k cells), Medium (1k-10k cells), and Large (> 10k cells). We selected three representative uop-perfrmmnn models for comparison: CodeV-DS (text-based), CircuitFusion (multimodal), and TopoRTL. As shown in T the results reveal two key insights:
Obs: TopoRTL demonstrates superior robustness on large-scale designs. On topology- sensitive metrics such as Area and Power, TopoRTL maintains high accuracy even circuit complexity increases. Notably, on Large circuits, TopoRTI. achieves an Area MAPE of 11.92%, reducing the error nearly 50% compared to CircuitFusion (24.2%%). This confirms that explicit topology encodings effectively capture the complexity of large-scale combinational logic blocks.
Obs: TopoRTL exhibits large scale invariance. While baseline models often show signifi- cant performance fluctuation across different groups, TopoRTL maintains consistent low variance across Small, Medium, and Large categories. This suggests that our model generalizes well to unseen designs across different scales.
E.2 CROSS-PDE GENERALIZATION ANALYSIS
During logic synthesis, RTL circuits mapped to physical gates based on specific Process De- sign Kit (PDK). Consequently, PPA metrics derived from different manufacturing processes (e.g., varying nanometer nodes) exhibit significant discrepancies. However, since RTL descriptions fun- damentally specify functional behavior and logical topology rather than physical implementation, the representations learned by TopoRTL should should theoretically be PDK-agnostic, enabling early-stage optimization across diverse technologies.
To validate this cross-PDK generalization, we re-synthesized the dataset using two additional open- source PDKs, SkyWater 130nm and GlobalFoundries 180nm, distinct from the default NanGate 45nm. As illustrated in Figure 8 PPA distributions vary significantly across process nodes, with performance metrics naturally degrading the node size increases. To address absolute scale differ- ences while preserving relative circuit rankings, we applied a log-transformation the PPA labels. We compared TopoRTI. against CodeV-DS and CircuitFusion, with results summarized in Table The analysis yields two key observations:
Obs: TopoRTI achieves robust generalization across technologies. TopoRTL consistently outperforms baselines on 45mm, 130nm, and 180nm tasks when prediction heads are trained on the corresponding data. For instance, in Area prediction on GlobalFoundries 180nm, TopoRTL achieves a PCC of 0.808, significantly surpassing CircuitFusion (0.620) and CodeV-DS (0.791).
This confirms that model learns universal circuit properties.
Obs: Performance trends. All models show slightly reduced accuracy on older PDKs (130nm/180mm vs. 45nm), primarily because open-source PDKs have limited standard cell li-
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Published as a conference paper at ICLR 2026
Area tLog sOMé)
Power scae)
Steck 2ong coalet
WKS flng scoei
TMS [ong scalel
Figure 8: Label distribution statistics on different PDKs.
Table 6: Performance comparison on different PDKs.
NanGate 45nm
Sky Water 130nm
GlobalFoundries 180nm
Model
Task
PCCT
MAPEЗ
PCC1
MAPE!
PCC1
MAPE3
Area
0.863
7.952
0.833
7.351
0.808
6.313
Power
0.884
25.033
0.896
16.624
0.873
14.649
TopoRTI.
Slack
0.909
31.249
0.876
26.957
0.830
11.025
TNS
0.872
32.016
0.901
13.036
0.902
7.849
WNS
0.862
40.130
0.820
17.890
0.806
8.553
Area 0.647
13.242
0.643
10.804
0.620
8.664
Power 0.657
43.073
0.643
34.308
0.640
28.268
CircuitFusion
Slack 0.893
30.944
0.885
25,408
0.865
9,451
TNS
0.885
34.454
0.848
18.315
0.831
11.983
WNS
0.817
38.227
0.798
21.267
0,852
7.399
Area 0.814
10.778
0.806
8.989
0.791
7.397
Power 0.827
36.544
0.818
27.850
0.819
21.950
V-DS
Slack 0.881
32.712
0.900
22.761
0.905
7.325
TNS
0.928
31.857
0.918
15.977
0.917
9.397
WNS
0.780
41.750
0.763
17.954
0.790
7.330
braries, causing synthesis tools to map complex functions to suboptimal cells and thus introducing noise in ground-truth PPA labels.
E.3 ROBUSTNESS ABILITY ON SUMMARY NOISE
In TopoRTL, we leverage dual modalities, graph and summary, to capture structural topology and behavioral semanties, respectively. For the summary modality, employ LLMs generate func- tional descriptions from Verilog code, which are then processed by behavior-aware tokenizer. However, given the varying capabilities of different LLMs human-written types, the quality of generated text can fluctuate. To investigate the sensitivity of RTL representation learning to text quality, we conducted experiments from two perspectives: semantic quality variation and extreme information mismatch.
Impact Semantic Quality. We first simulated a scenario with lower-qualis textual inputs by re- placing the summaries generated by GPT-OSS-120B with those from a significantly smaller model, GPT-OSS-20B. The TopoRTI. model was then retrained using these coarser summaries. As illus- trated in Figure 9 the results reveal:
Obs: TopoRTL is robust to variations in LLM capability. The performance degradation across all downstream tasks remains minimal (PCC, < 4%) when switching to the smaller 20B model. This indicates that while not strictly depend state-of-the -frtthe-rt LLMs. The graph modality acts structural anchor, stabilizing the learned representation even when textual nuances are less precise, ensuring broad applicability even with resource-constrained generation models.
summaries optimize performance, TopoRTL does
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Published as a conference paper at ICLR 2026
0.87
6.76
PCC //ACC Score
23.1
0.6
288
25.0
MAPE
0.2
1.
10
Slack
Retrieval
GPT-O5S:120B
GFT-OSS-200 208
PCC
MAFE
AUC
Figure Performance using different LLMs to generate functionality summary.
Table Performance comparison across different summary shuffling ratios.
0%
%
5%
10 %
Task
PCC1
MAPE]
PCC1
MAPET
PCC1
MAPET
PCC
MAPE
Area
0.8629
7.9521
0.869
7.7672
0.8421
9.0629
0.8057
9.5074
Power
0.8842
25.0326
0.8315
28.6588
0.8196
31.9563
0.8384
31.1551
Slack
0.9089
31.2487
0,8778
34.2507
0.8695
39.4997
0.8795
34.1435
TNS
0.8723
32.0156
0.8798
33.1328
0.8666
34.0015
0.8734
34.0001
WNS 0.8621
40.1298
0.8814
43.4544
0.8851
37.3168
0.8926
39.2374
Retrieval 0.787
0.7705
0.7651
0.7675
Impact of Textual Accuracy. We further introduced extreme noise to test the model's ability to correct misinformation. During pretraining, we randomly shuffled the textual summaries for spe- cific ratio (0%, 1%, 5%, 10%) of the dataset (effectively pairing circuits with completely incorrect descriptions), forcing the model to reconcile conflicting modal signals. As shown in Table 7
Obs: Topology encodings act as a correction mechanism for behavioral noise. We observed that timing-related tasks remain highly resilient to textual noise. Remarkably, WNS prediction performance actually improves under high noise conditions. We attribute this to the intrinsic conflict between high-level summaries and worst-case timing. Text summaries provide prior for "average" functional behavior but lack specific information about the critical path. When textual inputs noisy, the model effectively gates these vague semantic signals and is forced to rely exclusively on the precise, explicitly encoded topology. This confirms that our topology- aware architecture provides robust backbone that compensates when behavioral descriptions fail. Small circuits have few registers (<5), making global property (Area/Power) estimation vulnerable semantic corruption.
E.4 CIRCUIT FUNCTIONALITY AND TOPOLOGY SIMILARITY ANALYSIS
From a hardware perspective, an RTL cireuit is inherently a structured dataflow graph where behav- ioral intent and topological structure are intimately bound. As illustrated in Figure circuits can share identical functions (e.g., Circuit and C) yet exhibit divergent topologies that dictate physical performance (PPA). Therefore, ideal RTL representation must simultancously capture behavioral equivalence while distinguishing topological variations.
To further validate TopoRTL's capability in disentangling these aspects, we employed Yosys to gen- erate functionally equivalent but structurally diverse variants for each circuit in our dataset. For every original-variant pair, extracted both global embeddings (derived from the [CLS] token) and subgraph embeddings (register cone level), and computed their cosine similarities. The result- ing distributions are presented in Figure 10 The analysis yields two critical observations:
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limited to RTL but Published as a conference paper at ICLR 2026
Global Grout Distrbution
Simiiat Ditribution
1.000
8:68
5.55
5im bar
Sindarity
Figure 10: Cosine similarity histogram of functionally equivalent circuits.
Obs: TopoRTL achieves near-perfect behavioral consistency. The global embeddings of func- tionally equivalent pairs exhibit an extremely high mean similarity of 0.999. This confirms that our behavior-aware dual-modal tokenizers successfully align the high-level semantic representa- tion of circuits, ensuring that structural transformations do not distort the model's understanding of the underlying functionality.
Obs: TTPoRTL. maintains acute topological sensitivity within functional equivalence. con- trast to the global alignment, the subgraph embeddings show a noticeably lower mean similarity 0.868. This distinct "similarity gap" proves that our topology-aware encodings and alignment effectively detect and encode local structural variations (such logic depth changes intercon- nection density) even when the overall function remains unchanged. This capability is pivotal for precise PPA prediction, it allows the model differentiate between implementation choices that affect timing and power without losing functional context.
This directly addresses ioral equivalence preservation with topological differentiation.
question from the introduction: TopoRTL uniquely balances behav-
F FURTHER DISCUSSION AND FUTURE OUTLOOK
While TopoRTL successfully demonstrates the importance of topology in RTL representation learn- ing for PPA prediction and retrieval, our framework opens up several promising directions for future research and industrial applications.
Application Functional Verification Tasks. Current evaluations focus on static analysis (PPA and Retrieval). However, the principles of TopoRTLL are theoretically well-suited for dynamic func- tional verification, such as coverage prediction (e.g., Design2 Vasudevan et al. (202T)). Ver- ification is fundamentally problem of state reachability and logic dependency. Our Bid-Whdth Centrality Encoding inherently captures state space dimensionality, while the Register Cone de- composition mirrors the "Cone of Influence" analysis used in formal verification. Future work will explore leveraging these topological priors to predict verification complexity and guide testbench generation, bridging the gap between static representation and dynamic behavior.
Generalizing to Gate-Level Representations. The core insight of TopoRTI. explicitly model- ing the interplay between topological structure and functional behavior, is transferrable to lower levels of abstraction, such as gate-level netlists. The concept of register cones naturally extends Flip-Flop (DFF) cones in netlists. At this level, our positional encodings become even more physically meaningful: Max-Part maps directly to critical path delays through standard cells, and Graph Density correlates strongly with routing congestion. Adapting TopoRTL to netlists could enable fine-grained physical design prediction, creating a unified representation learning framework across the design flow.
Towards Real-Time EDA Integration. Unlike large-scale LLMs that suffer from high latency, TopoRTL is lightweight (29.13M parameters) and efficient, with an average inference time of less than one second per circuit. This efficiency, combined with our superior accuracy in PPA prediction, makes TopoRTL an ideal candidate for integration into real-time EDA flows. We envision TopoRTL functioning interactive "copilot" within design tools, providing instant feedback power and timing implications as engineers modify code, thereby accelerating the iterative loop of agile chip design.
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Published as a conference paper at ICLR 2026
G
OTHER DETAILS
Prompts to generate module-level and design-level descriptions
Module-level Generation
You are professional VLSI designer and expert at Verilog coding. Your task to analyze Verilog module and provide structured description in JSON format.
System Prompt
Analyze the following Verilog module. Your response MUST be single, valid ISON object.
Do not include any introductory text or explanations outside of the JSON structure.
The JSON object should have the following keys:
"suggested name": A short, descriptive, and functional name for the module (e.g., "ALU", "FIFO Controller"). 2. "inputs": A list of strings, where each string is high-level description of inputá purpose (e.g.. "Clock signal", "Data to be written", "Reset signal"). Do not use signal names from the code.
3. "outputs": A of strings, similar to inputs, describing each outputś purpose (e.g., "Result of calculation", "Indicates buffer is full").
User Prompt
4. "functionality":: concise paragraph describing what the module does, its main operations, and its purpose. Avoid im- plementation details.
5. couu_mmodles___ called": : A list of strings containing the names of any other modules instantiated within this module. If none, provide an empty list [].
Here is the Verilog module code: "verillg (module_code)
Design-level Generation
You are professional VLSI designer and an expert technical writer. You synthesize descriptions of individual circuit mod- ules into cohesive, high-level overview of the entire design.
System Prompt
You are given descriptions for individual hardware modules that make up a larger digital circuit. Your task to generate a single, high-level natural language description of the **entire circuit's functionality Follow these requirements:
1. Focus the overall purpose and main operations of the complete design. Synthesize. do not just list the parts.
2. Do not include any variable names, signal names, or the suggested module names from the provided context.
User Prompt
3. The description should be concise, clear, and written if a human user is describing what they want the final circuit to achieve.
4. Keep the final description under 400 words.
Here are the descriptions of the individual modules:
(context_stry
31


Reviews:
[{"review_id": "zPrDzgXHid", "reviewer": "Reviewer_mC1Q", "summary": "The authors designed a method that integrates two modalities of circuit with considerations for circuit topology. The authors used behavior-aware dual-modal tokenizers with three positional encodings (bit-width, max-path, graph-density) and adopted grahp transformer to encode circuits to representations.", "questions": "See the 'Weakness' part.", "limitations": "", "rating": 6, "confidence": 2, "soundness": 3, "presentation": 3, "contribution": 3, "strengths": "* The paper is well written, easy to follow.\n* The authors tackled an important problem that the field needed to address.\n* The authors performed extensive experiments with good results.", "weaknesses": "* In table1, the proposed model consistently outperforms baselines in Area, Power and WNS while not in Slack and TNS. The authors explained why their model shows good performance in Area, Power and WNS, however, they do not explained the possible reason behind relatively lowever performance in Slack and TNS.\n* It appears that the experiments were conducted only once and the performance was reported based on that single run. To ensure that the model’s performance is not dependent on a specific random seed but is statistically meaningful, it is necessary to repeat the experiments multiple times and report the mean and standard deviation of the performance.", "quality": null, "clarity": null, "significance": null, "originality": null, "strengths_and_weaknesses": "", "was_revised": false, "final_justification": "", "rebuttal": "", "claims_and_evidence": "", "methods_and_evaluation_criteria": "", "theoretical_claims": "", "experimental_designs_or_analyses": "", "relation_to_broader_scientific_literature": "", "essential_references_not_discussed": "", "other_strengths_and_weaknesses": "", "other_comments_or_suggestions": "", "questions_for_authors": "", "summary_of_paper": "", "summary_of_recommendation": "", "technical_quality": "", "clarity_of_presentation": "", "potential_impact": "", "robotics_focus": "", "quality_of_limitations": "", "questions_for_rebuttal": "", "reasons_to_accept": "", "reasons_to_reject": "", "questions_to_authors": "", "extra_scores": {}}, {"review_id": "VI6CUO53p7", "reviewer": "Reviewer_MxUV", "summary": "This work proposes a topology-aware RTL circuit representation method. They analyze the topology and functional behavior to design the structure ofthe  network, which provides meaningful insights. Finally, their algorithm shows better performance than CircuitFusion and other LLM models.", "questions": "1. In Table 1, I find the performance on timing-related metrics (e.g., Slack, TNS, and WNS) is better than that on Area and Power. Can authors explain the reason for these results? I thought area and power would be easier to predict because they do not depend on topology.\n2. Can authors explain the generalization ability of their works if the PDK is changed?", "limitations": "", "rating": 8, "confidence": 4, "soundness": 3, "presentation": 3, "contribution": 4, "strengths": "1. Good performance compared with competitive works, e.g., CircuiFusion and other LLM models.\n2. Meaningful insights about explicitly encoding the topological information in RTL.", "weaknesses": "1. The scale of designs is relatively small, where only 7,576 sub-circuits are extracted from 115 RTL designs. Meanwhile, I cannot find a difference in model performance between large designs (>200 registers) and small designs (<30).\n2.  The prediction ability of the trained model seems to depend on PDK, which will affect the generalization ability.", "quality": null, "clarity": null, "significance": null, "originality": null, "strengths_and_weaknesses": "", "was_revised": false, "final_justification": "", "rebuttal": "", "claims_and_evidence": "", "methods_and_evaluation_criteria": "", "theoretical_claims": "", "experimental_designs_or_analyses": "", "relation_to_broader_scientific_literature": "", "essential_references_not_discussed": "", "other_strengths_and_weaknesses": "", "other_comments_or_suggestions": "", "questions_for_authors": "", "summary_of_paper": "", "summary_of_recommendation": "", "technical_quality": "", "clarity_of_presentation": "", "potential_impact": "", "robotics_focus": "", "quality_of_limitations": "", "questions_for_rebuttal": "", "reasons_to_accept": "", "reasons_to_reject": "", "questions_to_authors": "", "extra_scores": {}}, {"review_id": "axX5I683ef", "reviewer": "Reviewer_UiRb", "summary": "This paper proposes TopoRTL, an RTL-stage circuit representation learning framework that incorporates topological information while preserving functional behavior. The RTL is partitioned into register cones and represented in both graph and summary modalities. These two representations are then encoded and fused through a multimodal learning architecture. Experimental results on downstream prediction tasks show that the learned embeddings improve the accuracy of RTL design quality estimation.", "questions": "Please refer to the weakness part.", "limitations": "", "rating": 2, "confidence": 4, "soundness": 3, "presentation": 3, "contribution": 1, "strengths": "1. The paper addresses an important problem in AI for EDA: circuit representation learning, and effectively leverages the multimodal nature of RTL format. The writing is clear and the methodology is easy to follow.\n2. The proposed approach incorporates topology-aware positional encodings within a transformer-based architecture to model RTL graphs. The use of bit-width encoding and max-path/density encodings is well-motivated and aligns naturally with RTL structural characteristics.\n3. The experimental results demonstrate that fusing the graph and summary modalities leads to improved performance, validating the effectiveness of the multimodal representation learning strategy.", "weaknesses": "1. The main concern is that the proposed multimodal RTL representation learning framework appears highly similar to CircuitFusion [ICLR’25]. Although the authors provide an empirical comparison, the paper does not sufficiently clarify the methodological differences or improvements. In the related work section, the discussion focuses primarily on behavior-based and topology-based models, but does not address prior multimodal fusion approaches. Moreover, key components such as register-cone decomposition, graph and summary modalities, contrastive/masked pre-training objectives, and multimodal fusion design closely resemble those of CircuitFusion. A deeper analysis of novelty is needed.\n2. For the topology-aware graph transformer, the paper lacks comparison with recent graph transformer architectures widely explored in the AI/graph community (e.g., Graphormer, SGFormer, GPS, SAN). It is unclear whether the proposed topology encodings provide advantages over standard positional or structural encodings used in these models.\n3. The downstream evaluation focuses on high-level RTL quality prediction, but does not explore whether the proposed topology encoding can capture structural variations that affect post-synthesis PPA. Since synthesis outcomes are highly topology-dependent, examining whether TopoRTL embeddings can reflect such differences would provide stronger evidence of the model’s effectiveness. Some discussion or experiments in this direction would be beneficial.\n4. Additionally, the evaluation is limited to PPA prediction tasks. There also exist functional verification tasks where representation quality matters, such as verification coverage prediction (e.g., Design2Vec [NeurIPS’21]). Demonstrating that the embeddings are useful across both functional verification and PPA prediction tasks would make the contribution more comprehensive and significantly strengthen the impact.", "quality": null, "clarity": null, "significance": null, "originality": null, "strengths_and_weaknesses": "", "was_revised": false, "final_justification": "", "rebuttal": "", "claims_and_evidence": "", "methods_and_evaluation_criteria": "", "theoretical_claims": "", "experimental_designs_or_analyses": "", "relation_to_broader_scientific_literature": "", "essential_references_not_discussed": "", "other_strengths_and_weaknesses": "", "other_comments_or_suggestions": "", "questions_for_authors": "", "summary_of_paper": "", "summary_of_recommendation": "", "technical_quality": "", "clarity_of_presentation": "", "potential_impact": "", "robotics_focus": "", "quality_of_limitations": "", "questions_for_rebuttal": "", "reasons_to_accept": "", "reasons_to_reject": "", "questions_to_authors": "", "extra_scores": {}}, {"review_id": "YQSjjq86a3", "reviewer": "Reviewer_e2DU", "summary": "This paper introduces TopoRTL, a novel framework for representation learning of RTL circuits that explicitly models both behavioral semantics and topological structures. Existing LLM-based or text-only RTL methods (e.g., CodeV, DeepRTL) treat Verilog code as pure text, overlooking the inherent dataflow topology of circuits. TopoRTL addresses this limitation through three key components: behavior-aware dual-modal tokenizers, which capturing both graph-based (structural) and textual (behavioral) modalities; topology-aware positional encodings, which integrating bit-width, path length, and graph density into Transformer attention to represent structural hierarchy and timing characteristics; topology-guided cross-modal alignment, which ensuring semantic consistency between the two modalities under topological constraints. Experiments on PPA prediction and natural language circuit retrieval show substantial gains over prior baselines such as CodeV, Qwen3, and CircuitFusion, with fewer parameters. The results confirm that explicit topology modeling is crucial for RTL representation learning.", "questions": "1.\tDuring training, how sensitive is the model to the quality of text summaries? If summaries are partially inaccurate, does the topology encoder still preserve robustness?\n2.\tCould the proposed topology-aware encoding generalize beyond RTL (e.g., to gate-level netlists or analog blocks)?\n3.\tWhat is the quantitative contribution of each topology encoding (bit-width, path, density) when combined pairwise, rather than removed individually?\n4.\tCould TopoRTL be integrated into synthesis or verification tools for real-time PPA estimation?", "limitations": "", "rating": 6, "confidence": 4, "soundness": 3, "presentation": 3, "contribution": 3, "strengths": "1.\tThe paper introduces a novel perspective on RTL representation learning by emphasizing the importance of topological structure in addition to behavioral semantics. The idea of integrating bit-width, signal-path, and graph-density encodings into Transformer attention is new in the RTL/EDA domain. Furthermore, the cross-modal alignment strategy between topology and textual modalities represents a creative extension of multimodal learning techniques into hardware design contexts.\n2.\tThe methodological pipeline—from register cone extraction to dual-modal embedding and topology-guided alignment—is technically sound and carefully justified. Experiments are extensive and clearly show that TopoRTL achieves consistent improvements across PPA prediction and circuit retrieval benchmarks, outperforming both large-scale LLMs (e.g., CodeV, Qwen3) and graph-based methods.\n3.\tThe paper is well organized, with a clear motivation and coherent narrative flow. Figures (especially Fig. 1–3) effectively illustrate the problem and model design. The appendices provide detailed implementation and dataset descriptions, enhancing reproducibility.\n4.\tThis work bridges two rapidly growing research areas—representation learning and EDA automation—demonstrating that explicitly modeling topology leads to superior circuit representations. The framework could meaningfully impact early-stage chip design optimization and inspire future work on structure-aware learning across code and graph modalities.", "weaknesses": "1.\tThe t-SNE visualization (Figure 4) shows separation but doesn’t analyze how topology encoding affects cluster formation. A more explicit comparison of embedding similarities (e.g., through cosine distances between functionally equivalent circuits) could strengthen the argument.\n2.\tThe summary modality relies on GPT-OSS-120B to generate textual circuit descriptions. The paper doesn’t analyze how summary quality affects downstream performance or whether the model could generalize with human-written or noisy summaries.", "quality": null, "clarity": null, "significance": null, "originality": null, "strengths_and_weaknesses": "", "was_revised": false, "final_justification": "", "rebuttal": "", "claims_and_evidence": "", "methods_and_evaluation_criteria": "", "theoretical_claims": "", "experimental_designs_or_analyses": "", "relation_to_broader_scientific_literature": "", "essential_references_not_discussed": "", "other_strengths_and_weaknesses": "", "other_comments_or_suggestions": "", "questions_for_authors": "", "summary_of_paper": "", "summary_of_recommendation": "", "technical_quality": "", "clarity_of_presentation": "", "potential_impact": "", "robotics_focus": "", "quality_of_limitations": "", "questions_for_rebuttal": "", "reasons_to_accept": "", "reasons_to_reject": "", "questions_to_authors": "", "extra_scores": {}}]

Author rebuttal:

Decision: Accept (Poster)