PCB-Bench: Benchmarking LLMs for Printed Circuit Board Placement and Routing
Authors: Jindong Li
Lianrong Chen
Bin Yang
Jiadong Zhu
Ying Wang
Yuzhe Ma
Menglin Yang
Venue: ICLR 2026 Poster (2026)
Keywords: LLMs
Printed Circuit Board
Placement and Routing
Multimodal Benchmark
Primary area: datasets and benchmarks

Abstract: Recent advances in Large Language Models (LLMs) have enabled impressive capabilities across diverse reasoning and generation tasks. However, their ability to understand and operate on real-world engineering problems, such as Printed Circuit Board (PCB) placement and routing, remains underexplored due to the lack of standardized benchmarks and high-fidelity datasets. To address this gap, we introduce PCB-Bench, the first comprehensive benchmark designed to systematically evaluate LLMs in the context of PCB design. PCB-Bench spans three complementary task settings: (1) text-based reasoning with approximately 3,700 expert-annotated instances, consisting of over 1,800 question-answer pairs and their corresponding choice question versions, covering component placement, routing strategies, and design rule compliance; (2) multimodal image-text reasoning with approximately 500 problems requiring joint interpretation of PCB visuals and technical specifications, including component identification, function recognition, and visual trace reasoning; (3) real-world design comprehension using over 170 complete PCB projects with schematics, placement files, and design documentation. We design structured evaluation protocols to assess both generative and discriminative capabilities, and conduct extensive comparisons across state-of-the-art LLMs. Our results reveal substantial gaps in current models’ ability to reason over spatial placements, follow domain-specific constraints, and interpret professional engineering artifacts. PCB-Bench establishes a foundational resource for advancing research toward more capable engineering AI, with implications extending beyond PCB design to broader structured reasoning domains. Data and code are available at https://github.com/digailab/PCB-Bench.

Published as a conference paper at ICLR 2026
PCB-BENCH: BENCHMARKING LLMS FOR PRINTED CIRCUIT BOARD PLACEMENT AND ROUTING
Jindong Li; Lianrong Chen; Bin Yang, Jiadong Zhu; Ying Wang, Yuzhe Ma, Menglin Yang! The Hong Kong University of Science and Technology (Guangzhou)
ABSTRACT
Recent advances in Large Language Models (LLMs) have enabled impressive ca- pabilities across diverse reasoning and generation tasks. However, their ability understand and operate on real-world engineering problems, such as Printed Cir- cuit Board (PCB) placement and routing, remains underexplored due the lack of standardized benchmarks and figh-fidelity datasets. To address this gap, we intro- duce PCB-Bench, the first comprchensive benchmark designed to systematically evaluate LLMs in the context of PCB design. PCB-Bench spans three comple- mentary task settings: (1) text-based reasoning with approximately 3,700 expert- annotated instances, consisting of over 1,800 question-answe pairs and their corresponding choice question versions, covering component placement, rout- ing strategies, and design rule compliance; (2) multimodal image-text reasoning with approximately 500 problems requiring joint interpretation of PCB visuals and technical specifications, including component identification, function recog- nition, and visual trace reasoning; (3) real-world design comprehension using over 170 complete PCB projects with schematics, placement files, and design doc- umentation. We design structured evaluation protocols to assess both generative and discriminative capabilities, and conduct extensive comparisons across state- of-the-art LLMs. Our results reveal substantial gaps in current models' ability to reason over spatial placements, follow domain-specific constraints, and interpret professional engineering artifacts. PCB- FCB-Bench establishes foundational resource for advancing research toward more capable engincering AI, with implications ex- tending beyond PCB design to broader structured reasoning domains. Data and code are available at https: :// / thub. com/ di wawggaaaaaaaaaaaaee
INTRODUCTION
Printed Circuit Board (PCB) placement and routing are essential yet challenging steps in the elec- tronic design automation (EDA) workflow (Ling & Isa, 2023; Soon et al., 2024; Li et al., 2023; Vassallo & Bajada, 2024). These tasks require engineers to determine the precise spatial arrange- ment and interconnection of components, while strictly adhering to physical, electrical, and manu- facturing constraints (Petkov & Ivanova, 2024). Historically, layout automation relied on classical EDA algorithms such analytical/global placement and congestion- driven routing. More recently, advances in reinforcement learning (RL) have demonstrated competitive macro placement and joint place-and-route (P&R) learning IC scale, while the first PCB-specific RL systems have begun to emerge (Cheng et al., 2018; Lin et al., 2019; 9; Xu et al., 2009; Mirhoseini et al., 2021; Cheng & Yan, 2021; Li et al., 2023; Vassallo & Bajada, 2024). They remain limited geometric objectives under fixed rules, without tackling multimodal reasoning over authentic PCB design artifacts.
In recent years, large language models (LLMM)) (e-g., GPT-4o (Hurst et al., 2024), GPT-5 (OpenAl, 2025), Claude-Opus-4.1 (Anthropic, 2025), Gemini-2.5 (Comanici et al., 2025), DeepSeek-V3 (Liu al., 2024). DeepSeck-Vas V3.1 (AI, 2025), Qwen-2.5 (Team al., 2024), LLaMA-2 (Touvron al., 2023), LLaMA-3 (Dubey et al., 2024). ) have demonstrated remarkable capabilities in open-ended reasoning, code generation, semantic understanding, and even multimodal grounding. This progress has sparked increasing interest in applying these models to engineering domains, where structured
"quual contribution. Corresponning author.

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Published as a conference paper at ICLR 2026
Table 1: The comparison between publicly available benchmarks. (DSLR: digital single-lens reflex)
Datanet
Vivsal Duta
Text
Schemalke Maagram
Saune Cude
Manufacture Setling
Software Fnstramment
Collettion Mathodk
Purpenr (Tadk)
Viar
DSLR Prannsdeiia Karzpel 2015)
RGB Iruge
DSLR
Desetios
2015
(ltungg
Digitl Minossope
Depiec (Tang st 20199
Rivury Trage
X
x
Tinor Son OCD
nhvectin
2019
PCB Mati pfainiinggas of 2019)
XCBB Irage
x
x
DSLK
Dexctice
2019
FICS-IC (Lu at. 20230
JeCis Imuge
/
Dipital Micresorpe, DSLR
Deleciie
2020
FICS PCB (Melta 20C2)
3D Volunerii
Ray Michine
Devetlon
2023
19IC
2023)
Visim LArteah al, 2024)
Heprregooaal
REM Iaagge
DSSLIC, Lmpuzn Spuctmematr
Dexction
2014
PCB-Besch (ours)
JGB Image
PTTS Disign Siftwom
PCB Design 2015
PCB Desiga File
constraints and real-world semantics intertwine. However, a critical question remains largely unan- swered: can these models truly understand and operate on expert-level engineering tasks that require precise interpretation of domain conventions, physical representations, and high-level design logic?
The Challenge of PCB Evaluation. The application of foundation models to PCB evaluation faces several fundamental challenges. First, PCB design requires reasoning across multiple modalities such as textual specifications, visual layouts, and structured design files, while maintaining strict adherence to domain-speciio rules and constraints. Second, the scareity of high-quality, large-scale datasets limits systematic evaluation. PCB design is costly, with labor reaching 0.2~0.5 USD per pin, and designs must undergo expensive validation through hardware fabrication and testing. Due to time, cost, and intellectual property constraints, PCB data is rarely open-sourced, making large-scale evaluation difficult. Even in state-of-the-art academic research ccircut-board-relle research field, e.g., (Vassallo & Bajada, 2024), FanoutNet (Li et al., 2023)), experiments are typically conducted on fewer than 20 boards, severely limiting reproducibility and benchmarking.
Current Limitations in LLM Evaluation. While existing research has explored learning-based approaches for physical design optimization, including deep reinforcement learning for IC macro floorplanning (Mirhoseini al., 2021) and joint P&R learning (Cheng & Yan, 2021), these ap- proaches primarily optimize geometric objectives under fixed constraints. Similarly, recent work evaluating L.MS in EDA contexts has focused on text-to-HDL design assistants (Chang et al., 2023) and Verilog code generation (Liu et al., 2023). However, none of these directions system- atically evaluate cross-modal alignment (text < image ++ design files) and rule-driven reasoning under PCB constraints, leaving a clear evaluation gap for foundation models on engineering tasks.
PCB-Bench. As shown in Table 1, no existing benchmarks could support the evaluation of LLMs for PCB design. Therefore, we introduce PCB-Bench, the first comprehensive benchmark to systematically evaluate LLMs on real-world PCB placement and routing tasks. PCB- Bench spans three complementary task settings and incorporates three key modalities: (1) text-based reasoning (e.g.. design requirements and technical questions); (2) multimodal image-text reasoning (e.g.. annotated raw PCB visuals); and (3) real-world design comprehension, such as schematic diagrams, design intents, and routing files.
Our Contributions:
This multi-modal composition reflects real PCB design, capturing abstract semantics and physical constraints. It aligns with L.MM//MLLMs text tests reasoning, images assess spatial grounding, and structured files provide domain knowledge. Together, these modalities form challenging testbed for evaluating foundation models on complex engineering problems.
The first task in PCB-Bench is a large-scale text-lo-text Question and Answer (QA) and Choice Ques- tion (CQ) benchmark, containing about 1,800 free-form QAs with corresponding CQs, for total of roughly 3,700 questions. This dual-formal design enables evaluation of both generative reasoning with BERTScore and SBERT similarity, and factual accuracy in CQ via accuracy. The second task is image-and-text multimodal reasoning, comprising about 500 questions, including choice, cloze-style, and free-form QA formats. Each problem pairs natural language prompt with PCB placement image, requiring models to integrate visual and textual information for accurate reason- ing. The third task centers on understanding real-world PCB designs. We collect over 170 complete designs from OSHWHub! each including schematic diagrams, design intents, component libraries,
'https:// com/ (operated hy JI.CPCB), an EDA platform providing accessible PCB designs.
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and final placement and routing files. From these, extract representative editor screenshots as inputs for description tasks, where models are asked to explain board functions, structural features, or application scenarios, thereby evaluating their ability to interpret professional design artifacts.
Our evaluation shows that current LLMs struggle with reasoning under real-world engineering con- straints, often producing errors in rule adherence, logical consistency, component semantics. Especially in multimodal settings, performance varies across models and task types, suggesting that significant gaps remain in adapting foundation models structured, high-stakes design scenarios. Our contributions are summarized as follows:
Comprehensive Multimodal Benchmark. We propose PCB-Bench, to knowledge the first comprehensive multimodal benchmark for assessing LLM/MLLM capabilities in PCB placement and routing, featuring text text-based QA, image-text reasoning, and schematic-to- description tasks.
High-Qualite Dataset Curation. We curate and release high-quality dataset of over 170 real-world PCB designs, providing a valuable resource for research on LLM-driven PCB design.
Systematic Model Evaluation. We systematically evaluate state-of-the-art models across multiple tasks and modalities, uncovering limitations in reasoning, compliance, and visual- semantic alignment.
Standardized Research Protocols. We provide unified task formats, evaluation metrics, and prompt design protocols to support reproducible research and standardized comparison in this emerging field.
PCB- -CB-Bench serves foundation for future research into engineering-capable foundation models and offers a standardized platform to evaluate real-world readiness in PCB design automation.
RELATED WORK
In recent years, several PCB datasets have been introduced, covering tasks such as defect detec- tion, component recognition, and multimodal inspection. These resources provide valuable bench- marks for evaluating computer vision and deep learning methods across different application sce- narios. PCB-DSLR (Pramerdorfer & Kampel, 2015) provides 748 images from 165 boards with annotations for segmentation, IC bounding boxes, and chip text, supporting classification and recog- nition tasks. PCBA-defect (Huang & Wei, 2019) includes 1,386 images with annotated defects across six categories for automated optical inspection. DeepPCB (Tang et al., 2019) offers 1. 1,500 aligned image pairs of defect-free templates and defective boards for defect detection and localiza- tion. PCB-METAL (Mahalingam al., 2019) contains 984 images with bounding boxes for major components, enabling component-level analysis. FICS-PCB (Lu et al., 2020) provides 9,912 im- ages with over 77k annotated components for robust detection and classification, while its X-ray extension (Mehta et al., 2022) introduces tomographic data for inter-layer inspection. FPIC (Jes- surun et al., 2023) offers 261 images with fine-grained annotations of over 71k instances including components, silkscreen text, and logos. PCB- PCB-Vision (Arbash et al., 2024) integrates 53 RGB images with paired hyperspectral cubes for multimodal component detection and recycling-oriented inspec- tion. Additional benchmarks such as CIRCUIT (Skelic al., 2025) and REE-Bench (Li al., 2025) target general circuit or electronics reasoning rather than PCB-specific layout and routing, and are therefore complementary rather than overlapping with our setting. Concurrently, LLM-based assis- tants for text-to-HDL. and HDL oode-generation benchmarks with simulation verified correctness examine textual competence (Chang et al., 2023; Liu al., 2023), while position papers discuss op- portunities and limitations of L.MSs in EDA workflows (He & Yu, 2024). Due to space constraints, more detailed information is provided in Appendix
PCB-BENCH
3.1
DATASET DESCRIPTION
integrates three types of datasets to support multimodal evaluation (Multimodal) Large Language Models in PCB placement and routing tasks. These datasets constructed inde-
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Plocement Hand CQ
Routing Hard
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Figure 1: Overview of PCB-Bench with representative cases.
pendently to reflect different reasoning modalities and input formats, including text-only, image-texi and real-world placement screenshots (see Figure 1). More details are provided in Appendix B.
Text-to-Text QA and CQ Set. We construct a separate collection of over 1,800 text-based question-answering (QA) instances, independent of the PCB design repository. For each QA in- stance. we additionally provide a corresponding single-choice question, resulting in total of about 3,700 questions. These questions are written by domain experts to cover core placement and rout- ing concepts across two levels, namely macro-level and micro-level, where the former emphasizes global design principles (e.g., module placement, power/ground planning) and the latter targets fine- grained implementation details and complex scenarios (e.g., signal integrity, high-speed routing). In total, they span over 25 subtopics (e.g., signal integrity, DFM, EMI/EMC, power delivery, dif- ferential pairs). Each QA point contains both free-form open-ended question and structured CQ version, enabling both generative and discriminative evaluation. All instances are manually reviewed and annotated with topic labels (see Figure? 2 for overview of the QA topic categories).
Image-and- Text QA and CQ Set. We construct a multimodal dataset of about 500 instances that combine PCB layout images with textual prompts. Specifically, it includes 300 single-choice ques- tions, 100 cloze-style fill- tn-the-bbank questions, and 100 open-ended QA instances. The questions cover diverse risual-semante subtasks such as component identification, functional block recogni- tion, trace type detection, via presence checking, and differential pair continuity analysis. The layout
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Meto Information
Attschments Aree merr cotes foadingree doot
PCB Design
PCB dadeeee
And
Schematic Diogram
(a) PCB placement.
(b) PCB routing.
(c) The contents of PCB designs.
Figure 2: The category information of PCB-Bench.
images are collected from both real and simulated PCB designs, ensuring visual clarity, semantic richness, and engineering relevance. This dataset supports both objective evaluation through CQ and cloze questions, well semantic evaluation through free-form QA.
Real-World PCB Design Repository. We collect 174 complete PCB designs (Figure 2) from JL- CPCB Each design includes schematic diagrams, placement and routing files, design descriptions, component libraries, and representative screenshots from EDA software. Some designs also include video tutorials explaining the design intent and construction process. These designs span a diverse range of applications, such USB hubs, power modules, and development boards, and are primar- understanding tasks. This repository serves as a rich
ily used in JCB-Bench for screenshot-bar resource for future supervised training and pretraining on realistic EDA artifacts.
More detailed descriptions of these datasets are provided in Appendix B. And all datasets are veri- fied for correctness, cleaned for language elarity, and formatted for compatibility with open-source and proprictary foundation models. We release PCB-Bench with open licensing to support repro- ducibility, evaluation standardization, and future model development in LLM-based EDA tasks.
3.2 TASK FORMULATION
PCB-Bench consists of three task settings designed to evaluate the multimodal understanding and reasoning abilities of (Multimodal) Large Language Models in the context of PCB placement and routing, These tasks are formulated based real-world engineering scenarios and reflect how human designers interpret, analyze, and describe PCB designs through textual, visual, and schematic information. Each task aligns with specific modality combination and reasoning objective:
Task 1: Text-to-Text QA and CQ. This task is constructed from 1,800+ text-based QA instances derived from realistic PCB placement and routing contexts. For each QA instance, we additionally provide corresponding choice question, resulting in total of approximately 3,700 questions. The free-form QA setting reflects how models respond under open prompts, where performance may vary depending on prompt design model-specific generation behavior. In contrast, the choice for- mat offers a more objective and standardized evaluation, though it is inherently easier since models can resort to guessing or elimination strategies when lacking domain knowledge. The questions span two major domains, placement and routing, and are further categorized by difficulty (Easy and Hard) and subtopics such as signal integrity, EMI, power planning, and high-speet routing.
Task 2: Image-and- Multimodal QA and CQ. This task evaluates a model's 's ability to an- swer questions based on both PCB layout images and accompanying textual prompts. It includes approximately 400 questions, presented in either choice question or cloze-style (fill-in-hhe blank) formats, and 100 QA-form questions. The questions cover wide range of visual-semantic subtasks, including component recognition, functional block identification, trace type detection, signal layer classification, and via presence checking. Each instance presents real PCB placement image along with a natural language query. This task assesses the model's 's ability to align textual understanding with spatial and symbolic patterns present in PCB images.
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Figure 3: Several samples of PCB designs (Screenshots of PCB design in the development soft- ware/environment for presentation).
Task 3: PCB Design Understanding. This task focuses high-level interpretation of profes- sional PCB placement artifacts through visual imput alone. We utilize the 174 real-world PCB designs collected from OSHWHub, from which we extract representative placement and routing screenshots (Figure 3) directly from EDA tools (e.g., editor views with silkscreen, copper layers, or via/pad structures). Each screenshot is used standalone input, without accompanying textual deseriptions or schematic information. The model is prompted to generate a free-form textual de- scription that explains the board's function, structure, or intended application scenario. Unlike Task 2, which provides both image and language input for classification-basee answering, this task re- quires models produce open-ended, coherent descriptions based solely on visual placement cues. It tests model's 's ability in structured visual interpretation such as identifying key component zones, understanding spatial partitioning, and inferring board-level functionality, based on real, noisy, and heterogeneous PCB design screenshots. This setting simulates how human engineers inspect PCB visually to form an initial technical assessment before delving into schematics or netlists.
Together, these tasks provide comprehensive and multimodal framework for evaluating the capa- bilities foundation models on practical, structured engineering problems.
3.3 BENCHMARK CONSTRUCTION
The construction of PCB-Bench follows a rigorous pipeline of knowledge collection and process- ing, as illustrated in Figure 4. We begin by gathering knowledge from multiple complementary sources, including textbooks, web resources, outputs of commercial multimodal LLMs, domain ex- perts, and syllabi from PCB education institutes. This ensures that the foundation of the dataset both comprehensive and aligned with real engineering practice.
Based on these sources, human experts first design a structured syllabus and refine the scope of knowledge points that should be covered. Each selected knowledge point is then transformed into candidate questions through a multi-stage generation process. This process involves three key steps: (i) designing questions in both open-ended and structured forms, (ii) standardizing the annotation schema and formatting rules to maintain consistency, and (iii) performing quality assurance to min- imize ambiguity redundancy.
All generated questions undergo iterative human expert review to guarantee correctness, clarity, and practical relevance. The review process not only validates technical accuracy but also adjusts phrasing to better reflect authentic engineering reasoning and instructional suitability.
Knowledge Source
Books
Commercial MLLMs
Question Generction Guestien Destin
Web Pages
Experts Design
Knowledge Points
Human Expert Review
Question Set
Arsutation
PCB Training Curricula
Formet ceaddardaaeiios
Syllobus
Experts
Quality Assunance
Figure 4: The pipeline of knowledge collection and processing.

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The benchmark further benefited from feedback provided by engineers from PCB design and manufacturing company, who validated the practical relevance of the tasks. While they were not involved in dataset authoring, their input ensured alignment with real industrial workflows.
In addition, the PCB designs used in ICB-Bench are collected from the open-source platform OS- HWHub. During data collection, strictly comply with open-source licensing terms, and for each design, we provide the corresponding URL link to ensure transparency and the protection of intel- lectual property. More details are provided in Appendix B.1.
EXPERIMENTS AND FINDINGS
4.1 EXPERIMENTAL SETUP
We evaluate diverse set of (M)LLMs under unified zero-shot setting across all three tasks in PCB-Bench. Each question or input instance is presented to the model independently, without access to prior examples task-specific demonstrations. This simulates realistic deployment sce- narios, where foundation models are expected to generalize directly to engineering problems without fine-tuning or prompt tuning. The detailed task formulations have been introduced in Section 3.
Task 1. Text-based QA tasks are used to assess models' understanding of PCB design knowl- edge. The following models are evaluated: GPT-5 (OpenAI, 2025), GPT-4o (Hurst et al., 2024), Comanici et al. (2025), Deepseck-Chie Laakk-Chat-Vi V3.1-
Claude-Opus-4.1 (Anthropic, 2025), Gemini-2.5- (Team et al., 2024), 4.MMA-4-Maerrice
671B (AI, 2025), Qwen2.5-7B-Insten 2025), Intern VI.3-78B (Zhu et al., 2025), MythoMax-1.2-1338 --31-3 (Gryphe, 2024), Rocinante-12B (The- Drummer, 2025), Ministral-3B (AI, 2024). We further evaluate two domain-specifie variants de- rived from gains. Task 2. Multimodal QA tasks combine PCB layout images and textual queries. We evalu- ate: GPT-5 (OpenAI, 2025), GPT-5-nano (OpenAI, 2025), Gemini-2.5-Pro (Comanici al., 2025), (Comanici et al., 2025), L..aMAA--Mavvrric---- VL-Max (Bai et al., 2023). Intern VLB-78B (Zhu al., 2025), Twee3-VV--S8 VL-8B-Instruc Instruct (Yang al., 2025), ---.--------22---tihni-e
(Meta AI,
to examine whether PCB-oriented specialization yields measurable
2.5mni-2.5-Flash-
(Meta AI, 2025), Qwen-
(Yang et al., 2025). Task 3. PCB layout understanding tasks require models describe full-boane sereenshots. We evaluate the same set of vision-language models as in Task 2. More details are provided in Appendix C.I.
4.2 EVALUATION METRICS
For CQ, we adopt top-1 accuracy. For free-form QA, we employ BERTScore (Zhang et al., 2020) and Sentence-BERT similarity (SBERT) (Reimers & Gurevych, 2019) to assess semantic consistency with reference answers. Compared with exact string matching, these semantic metrics are more suitable for PCB layout and routing QA, where correct answers often involve technical terminology, synonyms, or varying descriptive expressions. For Task 3, we further report precision, recall, and Fl-score to capture complementary aspects of prediction quality, ensuring a more comprehensive evaluation. More details are provided in Appendix C.2.
4.3 RESULTS AND ANALYSIS
The main results are summarized below, with more detailed results provided in Appendix C.
4.3.1
TASK 1: TEXT-BASED QA AND CQ PERFORMANCE
As shown in Table 2 and Figure 5, GPT-4o, Claude-Opus-4.1. and CrapSeek-Chat-VVe form the top tier: Claude leads CQ accuracy, while GPT-4o and DeepSeek show stronger semantic align- ment in QA. GPT-5 remains competitive but slightly weaker in QA fidelity. Open-source models such as Intern VL3-78B perform well on CQ but show lower QA alignment, and domain-specific variants (QLoRA, RAG) improve semantic similarity without surpassing frontier models. Overall, Task 1 exhibits complementary strengths across models and clear divergence between CQ accuracy and QA alignment metrics, reflecting the different reasoning demands of selection generation tasks. These results highlight that semantic evaluation and accuracy- based evaluation do not always correlate, especially in fine-gratd ane-graieed PCB reasoning scenarios.

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Teak3-00 19
24
Tak
Figure 5: Radar visualization of model performance across different tasks. The charts highlight comparative strengths and weaknesses of each model under diverse evaluation metrics.
Table 2: Performance comparison on task 1. (Acc: Accuracy (%); D.S.: domain specific. Notation: best; sccond-best; worst.)
Piacement
Ronting
Masro-Landd
MicnoLLoed
Macn-LLvee
Mazuo-Leei
QA
Acc.
BERTS
SBERT
Aus:
BERTScree
SBERT
Auc:
BERTS
SBERT
Acc.
BERTS
SBERT
92.24
GPTS
88.27
0.3150
(14502
91.79
0.8214
0.5334
99.16
03193
0.4588
90.17
0.5211
0.5137
Clande Opus-L.1
93.30
0.3138
0.4772
94.35
0.8054
0.5643
99.16
0.164
0.4857
92.32
0.8119
0.5735
Pro
88.73
DeppSeii-Che-VV... 1-77
92:74
0,3366
014013
99
0.8177
0.5652
97.48
03318
0.4919
88.49
0.5217
0.9657
LLM 4LaMA--MMeeccl-00g
77.66
0.3155
0.0931
40.07
0.8074
0.5689
92.43
08186
0.5149
71.70
0.8104
0.5364
IneeVVL3
93.91
97.43
91.37
0,8056
0
MythoMMas-12-1158
65.91
0.3257
014496
54:37
0.8101
0.5405
09.02
03262
0.4676
53.00
0,3115
0.5111
Recimste-128 12B
82.12
0.5174
0.4707
77.41
0.8054
0.5755
89.92
0.8227
0,4953
77.70
0.5141
0.5590
Minstral-3 39
59.21
0.3196
42.71
74.79
0.4918
54.68
0,8108
0.5552
$4.30
0.2978
0.2005
0.31.10
82.50
0,727
012001
Quend 4-77--nerrat-ii..e (0.5)
90.90
0.6203
0.4687
59 30
0.6329
0.9971
97.48
0.6297
0.4764
82.50
0.6367
0.5414
RAG-Qwes2.5 5.78 Itstrcct (O.S.
0.6145
57.44
92.43
0.5368
85.61
0.6122
0.5456
4.3.2 TASK 2: IMAGE-AND-TEXT MULTIMODAL QA AND CQ PERFORMANCE
Task 2 requires integrat- ing textual prompts with
Table 3: Performance comparison on task 2. (CBC: Common Basic CQ, CBFB: Common Basic Fill in Blank, BWEI: Basic Wiring Error Identification, QAP: QA of Placement, QAR: QA of Routing. Nota- tion: best; second-best; worst.)
PCB placement images for multimodal QA and CQ. As shown Table and Figure 5, GPT-5 delivers the most balanced perfor- mance, achieving strong CBC and BWEI accuracy while leading in QAP/QAR alignment. GPT-5-nano ex- cels in semantic similarity but remains mid-tier in ac-
CBC
CBFR
RWEI
Midel
Acc. (15)
Acc. (15)
Acc. (%)
BERTScooe
SBERT
BEXTS:o0e
SBEKT
CIPT-S
83.26
00:00
0.8734
0.6700
0.8561
0.6055
GirE-S-une
72.72
0,6347
Semini-255:B
81.05
$4.00
100.00
0.8355
0.6637
0.5362
0.6311
Gemini-2 S.anini--5.Plaaeelll S.PlashLLite
22:20
75.66
$4.54
0.8500
0 06662
0.8361
0.6312
LLaMA Moverick
77.60
54.54
06319
0.5226
0.6108
InternVL.33- 2815
76.83
45.45
0.8552
0.688
0,8357
0,6242
curacy. Gemini-2.5-Pro at- tains top CBFB accuracy and perfect BWEI scores, though its semantic align-
Owen VL Max
75.67
62.66
72.72
0.8321
0.6476
0.5170
0,6093
Moen--VV--llllmmmmer
75.28
45.45
08111
0.610
0.5161
0.9997
Qwend VL-2358--0 A228 thinkin
76.13
0.6057
ment trails GPT-5. Among open-source models, LLAMA- achieves moderate CBC accuracy (77.60%) but struggles with BWEI (54.54%). Qwen-VL-Man shows unremarkable re- sults, while Qwwe3-VV-223B--AM -hinkiin demonstrates mid-tier performance despite chain- of-thought. InternVL-3-78DD and Qwen3 Twen3-VL-BB-Ing -L-tt----tt exhibit the weakest BWEI performance (45.45%), with Qwen3- WLL-8B-Instruc additionally achieving the lowest semantic similarity scores. Results reveal a clear trade-off between structured accuracy and semantic coherence, with no single model dominating all dimensions. This underscores the complexity of multimodal PCB understand- ing, where visual grounding and textual reasoning require sophisticated alignment mechanisms.
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4.3.3 TASK 3: PCB DESIGN UNDERSTANDING.
The results for Task 3 are shown in Table 4 and Figure 5, which evaluate how well models interpret PCB designs from editor screenshots through free- form functional and structural descrip- tions. Overall, performance differences across models are relatively small: most achieve BERTScore around 0.82 and F1 in the 0.85~0087 range. Qwen3-VL-235B- 122B-thinking and IntemVL-33-788 de- liver the strongest semantic alignment, with the highest BERTScore (0.8293 and 0.8267), while Bwve3--VL-8B-Insiee tains the best recall (0.8955) and competi- tive FI. LLaMA-4-Maverick reaches the highest precision (0.9123), reflecting strong pattern recog- nition but slightly lower SBERT. GPT-5 maintains balanced performance (F1 0.8591. SBERT 0.6134), whereas GPT-5-nano shows moderate results across all metrics. These findings illustrate that while models can capture high-level PCB layout descriptions, deeper structural understanding remains challenging and varies across semantic metrics.
Table 4: Performance comparision on task 3. (Nota- tion: best; second-best; worst.)
Model
BertSeor:
Precision
Rrcall
Ft
GPIS
0.8156
0.6144
0.8495
0.8691
0,8591
GPTS-am auno
0.5199
0,5358
0.5729
0,8352
0,8507
0/7507
Gamini-2 S-Flashe Geminn-2--Paabeiii
0.8194
0.5083
0.5657
0,8518
0.656
0,8253
0,5101
0.9123
0,8044
0.811
IntcaVLL-3-888
0.9044
0.8716
0.5449
Qwen-V1-Mas
Qwea3-VL. VL---B-lmtttt
0,8242
0,5760
0.8433
0.8155
0.5675
0,8293
0.6168
0.5403
0.8391
0.8405
at-
4.4 DISCUSSION AND FINDINGS
Across all tasks, CQ remains easier than free-form QA, while QA consistently shows lower semantic alignment. We also observe that semantic metrics such as BERTScore and SBERT do always agree, reflecting that existing evaluation tools capture different aspects of answer quality and may miss PCB-specific correctness. Larger models outperform smaller ones, with Gemini-2.5, GPT- 4o/5, Claude, and Qwen- VL-Max leading performance, and domainn-seciinn variants (QLoRA fine- tuning, RAG) offering further gains. Despite these improvements, current LLMs still fall short in realistic PCB placement and routing, particularly in fine-grained or open-ended settings. These findings highlight the need for domain-adapted training, HDA-aware integration, and a dedicated evaluation system tailored to PCB design tasks. We can draw several preliminary conclusions:
1. Model behaviors differ both across Lasks and dimensions (perspec.ives). Targar-acale modals parforn better
er-scale modela.
3. Overall, the etrongest performance is achieved by Gemini 2.5, GPT 44/5, Claude, and Qwen- VL-Xax.
4. Domain-spacific varianzs (a.g., ULORA fine-turing BAG) can further beost the
capabl lities of general madels.
5. Current LIMs show basic knowledge of PCB placement and routing but remain incomplete; in reslistic open-ender ended settings they are still insufficient and cannot reglace humans.
Meaningtul progreas
lixely require comain-adapted training integration with SDA-
specific toels te bridge the gap between generic reasening and PCB design requirements. placement routing is also needed to enable mare rigarous and reclistic capability assasanent.
dedicated, comsin-specific evaluation system
CONCLUSION
In this work, we present PCB-Bench, a multimodal benchmark designed evaluate the capabilities of large language models on PCB placement and routing tasks. Our study demonstrates the feasibil- ity of integrating text, image, and design artifacts into a unified evaluation framework, providing a first step toward systematic assessment of LLMs in PCB analysis.
ACKNOWLEDGEMENTS
This work is supported by the Hong Kong University of Science and Technology (Guangzhou) (Grant No. G0101000266). We gratefully acknowledge the support of Qiyunfang Technology Co., LTD. We also thank HubWHub and JLCPCB for providing access to publicly available PCB design resources.

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ETHICS STATEMENT
The main contribution of this work lies constructing PCB-Bench, a benchmark for systematically evaluating large language models (LLMs) on PCB placement and routing tasks. All PCB designs included in PCB-Bench are collected from publicly available and legally accessible sources, with no proprietary or sensitive industrial data involved. The benchmark and experiments are intended solely for academic research and evaluation, not for direct deployment in high-stakes industrial scenarios. By focusing on transparent dataset construction and responsible assessment of LLM capabilities, we aim to support the community in developing safer and more reliable Al techniques for electronic design automation.
REPRODUCIBILITY STATEMENT
To ensure reproducibility, we describe all experimental settings in detail, including model versions, evaluation metrics, and task formulations, All results are obtained under unified zero-shot setting without additional fine-tuning, making the evaluation straightforward replicate. Upon acceptance of this paper, will release ICB-Bench along with the evaluation scripts and configuration files, enabling the community to reproduce our results and extend the benchmark. When releasing the benchmark, will also comply with open-source licenses and clearly acknowledge all data sources.
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APPENDIX CONTENTS
Related Work Supplement Materials
16
PCB-Bench Supplement Materials
17
B.1 PCB-Bench Construction
17
Experiments Supplement Materials
18
C.1 Experimental Setup Supplement Materials
18
C,2 Evaluation Metrics Supplement Materials
19
C.3 Prompt Template
19
C,4 Experimental Results
22
C.5 Case Study
30
LLM Usage Statement
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A RELATED WORK SUPPLEMENT MATERIALS
In Section 2, we present concise overview of eight representative PCB datasets. For completeness, this appendix includes the extended versions with detailed statistics, annotation formats, and use cases, which complement the brief summaries in the main text.
PCB-DSLR (Pramerdorfer & Kampel, 2015) is a dataset for computer-vision-aane based PCB analysis, primarily targeting recycling applications. It contains 748 high-resolution DSLR images from 165 different boards, with annotations including board segmentation masks, 9,313 IC bounding boxes, and text labels for 1, 1,740 chips. The dataset supports multiple tasks such as PCB classification, IC localization, and text recognition, and it provides a benchmark for evaluating vision- based PCB analysis methods under realistic recyeling conditions.
PCBA-defect (Huang & Wei, 2019) is designed for PCB defect detection and classification. It con- sists of 1,386 color images of bare PCBs, each containing 3-5 defects from common categories: missing hole, mouse bite, open circuit, short, spur, and spurious copper. The dataset provides bound- ing boxes and rotation information for every defect, enabling tasks such as detection and classifi- cation. Images are captured with high-resolution industrial camera under controlled illumination, and the dataset serves as a benchmark for evaluating automated optical inspection methods.
DeepPCB (Tang et al., 2019) provides 1,500 aligned image pairs, each consisting of defect-free template and a defective tested image. It covers common defect categories, with each tested image containing around 3-12 annotated defects represented by bounding boxes. Images captured by a linear scan CCD and aligned through template matching, ensuring high consistency for training and evaluation. DeepPCB serves benchmark for PCB defect detection, supporting both defect localization and classification tasks.
PCB-METAL (Mahalingam al., 2019) provides 984 high-resolution images from 123 unique PCBs, each captured under controlled lighting and rotation to ensure consistency. It includes bound- ing box annotations for 5,844 ICs, 3,175 capacitors, 2.679 resistors. and 542 inductors, supplied in both text and XML (PASCAL VOC) formats. The dataset is designed for component-level PCB analysis, enabling tasks such as object detection, classification, and circuit design extraction.
FICS-PCB (Lu et al., 2020) introduces multi-mode resource for automated PCB visual inspec- tion, consisting of 9,912 images from 31 boards with 77,347 annotated components. It incorporates two imaging modalities, digital microscope and a DSLR camera, and includes variations in il- lumination, scale, and sensor type to reflect realistic application scenarios. The dataset supports component-lever detection and classification across 6 categories, and it serves benchmark for developing robust PCB assurance methods under diverse visual environments.
FICS-PCB X-ray (Mehta al., 2022) is the first publicly available tomographic dataset targeting inter-layer PCB inspection. It consists of X-ray projection data, reconstructed 3D volumes converted into Tiff stacks, and annotated slices covering features such as vias, traces, and pads. The dataset contains five PCB samples of varying sizes and layer counts, enabling tasks such as inter-layer defect detection, feature segmentation, and automated netlist extraction. By providing volumetric data beyond surface-level imaging. FICS PCB X-ray facilitates research in hardware assurance, reverse engineering, and multimodal approaches that combine optical and X-ray inspection.
FPIC (Jessurun et al., 2023) is a large-scale semantic dataset for optical PCB assurance, consisting of 261 high-resolution RGB images from 93 boards with over 71,000 annotated instances, includ- ing components, silkscreen text, and logos. Unlike previous datasets that only provide binary or RGB images, FPIC offers fine- mme-grained semantic annotations support tasks such component detection, text recognition, and hardware assurance. The dataset is collected using DSLR camera under controlled conditions and is primarily designed for optical inspection and semantic-level PCB analysis.
CrB-Vision (Arbash et al., 2024) introduces the first multiscene benchmark integrating both RGB and hyperspectral imaging for PCB analysis. It consists of 53 high-resolution RGB images paired with corresponding hyperspectral cubes in the VNIR range, annotated for three primary component classes: integrated circuits, capacitors, and connectors. Designed in an industrial conveyor belt set- ting. PCB-V Vision facilitates research on multimodal learning, component detection, and recycling- oriented PCB inspection under realistic conditions.
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CIRCUIT (Skelic al., 2025) focuses analog circuit interpretation, providing dataset of 510 question-answe pairs to evaluate LLMs' ability to reason about circuit topologies using both dia- grams and netlists. The dataset spans variety of analog circuit topics. challenging models with tasks that require multi-step reasoning and deep understanding of circuit configurations.
EEE-Bench (Li et al., 2025) evaluates LLMs in electrical and electronics engineering, offering 2,860 problems across 10 subdomains such as analog circuits and power electronics. combines visual (circuit diagrams, system images) and textual requirements, challenging models reason across both modalities in real-world engineering tasks.
While the above resources advance imaging-based PCB inspection, they remain largely vision-only and do not assess whether foundation models can reason over textual requirements, layout images, and authentic design files in tandem. This gap motivates benchmarks that couple visual layouts with textual requirements and authentic design artifacts. For method-centre physical design, classical IC global placement casts optimization over density and wirelength, while global/detailed routing relies on congestion-aware Steiner construction and maze or A A*-style search. (Cheng et al., 2018; Lin et al., 2019; Xu et al., 2009). Subsequent learning-driven physical design shows that deep RL can achieve human-competitive IC macro floorplans within hours (Mirhoseini et al., 2021), and follow-up work jointly learns placement and routing to improve end-to-end routability (Cheng & Yan, 2021). On PCBs, RL has been explored for component placement and fan-out automation in detailed routing (Li et al., 2023; Vassallo & Bajada, 2024). These optimize geometric/graph objectives under design rules, but none of these approaches evaluate multimodal understanding or natural- Haturae- reasoning over layouts and design files, which is the focus of our benchmark.
In contrast to the dataset-centric, optical-nnspection line, the algorithm-centric placement/routing lit- erature, and the text-centric LLM-for-HDL line, our work evaluates multimodal reasoning for PCB placement and routing across text, image, and real design artifacts such as schematics and editor screenshots. Thus, CCB-Bench complements coorithm-centrid P&R and text-only HDL bench- marks by supplying multi-modal, rule-aware evaluation target aligned with real EDA artifacts.
B PCB-BENCH SUPPLEMENT MATERIALS
Figure 6 presents the word clouds PCB-Bench across different tasks and granularity levels, in- cluding placement and routing under both macro- and micro-levels. The visualization highlights the frequent occurrence of domain-specifee concepts such as power, ground, thermal, signal, and copper, which correspond to key concerns in PCB design like power integrity, signal integrity, electromag- netic compatibility, and thermal management.
These word clouds serve that
intuitive validation of the dataset construction. They demonstrate captures a wide range of terminology and technical aspects at different abstraction levels, thereby ensuring both breadth and depth of coverage for evaluating LLMs and MLLMs on PCB-related reasoning tasks.
B.1 PCB-BENCH CONSTRUCTION
To further strengthen reliability, the entire curation and annotation workflow was supervised by two domain experts in circuit and PCB design- senior professor and one PhD-level researcher. Ev- ery question was either authored or reviewed by these experts, ensuring that all knowledge points, reasoning steps, and answer choices are technically precise. When disagreements emerged, such as ambiguous wording or borderline-acceptable distractors, experts discussed the case and refined the item until reaching full consensus both the target reasoning path and the correct answer. Although we did not compute formal inter-annotator agreement, each item in CCB-Bench has undergone ex- pert oversight and revision, guarantecing high-quality and instructionally sound content.
In addition, the construction of CCB-Bench benefited from external validation provided by engineers from industrial PCB design and manufacturing company. Their feedback helped verify that the tasks align with practical engineering workflows and reflect roal-world design considerations. While these engineers did not participate directly in dataset creation authorship, their input ensured that the benchmark remains grounded in authentic industrial practice.
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ding
leageti
serdes
flash
sball
zone
differential
power
samp
ump
requency
To anternna
high
imped
ldo voringg f
impedance
youthhr
return
the diraaly td
signal
thermal lepgth
muncing
entilation
placement
dcbug
I
separiiit
input
ffrequeheys
ground
deeell
pehet!
ind
Crystall
analog
isolation
seriicahilty
less
ve
smmetoal
iisolatiion
path fed
bridge
pairt
crosstalk
dc emi
tree
inlegrity
coto
distributed Io egge ground
reslundanl
copper speed dheed backup
if
control tVV
daylic
unlegritt
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ssymmetry
alganso
look
area
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imatching
the oscillator filtermupi
hdmi
g
ground
poe
path digital battery
Aiberin
cuea
source
pinic
heat
power
lave
thermal
high meu
connecter
poise
usb
ddr
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sensto cooling
module via
p
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mnna mrent
blacemen
pour industria
layout
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co
feedline
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syimietry
pa
Iconuroll
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routipg
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magneti charging,
interface plane
partitioning
plas
felier
p place
clock multi aie higk
symmetric mixer
rf
point
can
wnder
em speed
pour
Iepass
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crystal
Test
Peili
(a) Placement- - Macro-Level.
(b) Placement Micro-Level.
Ses 12s low push frequency
integrity 1
suttiping crosstalk SPg
pin edge
signal
orthogonal
isolation ii.. skew
grou ground ps232
mode gnss
raliaiiity
differential symmetry
control
clarity
thermal Touting
quantum 2od
mu.
twisted
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bender. digital puuu spi
Termination
Toop De
via
isolation
power
decoupling
routing
Ivds
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inductor
direen
serd rsolation iipiusb
matching gromnd buffer
yultoue pos load_ re
mostet
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redundant
re
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sink high signal
beat
lakk
structree detection
tap ad 3d esd
eryogemec
delay projocolg
ethermet
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hdmi
mipi mipi
are
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spacing
matching
Cresmannce
plane
spening
placofest
split coppet
Sount
pair
length
i20
crossing
emi, nuc
ower noise
degree
long
45
decoupling starn clock
french
Ido
Ido
conth
Symmettry
satellite
loop
ddr
layer
accelerator
induclor conflict
50 gssg
impedance
daisybymp chain
phase
brigge
tas 7
Jength interepnnect
-ifffrrettal cap
soft
coinmon island
copper
Genidl
cara
eme chiple
autompgee
guard
path
reflection
coupling gnd width line
short
emi blos
filter
return is
termarostiggan
path analog coniittt
sd
control
power ew axr flexray
protection yoae
Rair
unified channel
poority
traee
(c) Routing- Macro-Level.
(d) Routing- Micro-Level.
Figure 6: The word cloud of PCB-Bench.
C EXPERIMENTS SUPPLEMENT MATERIALS
C.I EXPERIMENTAL SETUP SUPPLEMENT MATERIALS
Domain-Specitne Model I: QLoRA-Tuned Qwen2.5-7B. We fine-tuned Qwen2.5-7B-Insttuun us- ing curated PCB corpus consisting of approximately 3,000 samples extracted from authoritative engineering documents (e.g.. RK3588 Design Guide) via rule-based templates. The dataset inte- grates sosoming-focusee multiple-choice questions and open-ended technical QA. The model is trained with 4-bit QLoRA A (rank 16, 32) to achieve efficient adaptation under limited com- putational cost. This specialized model exhibits substantial improvements in semantic alignment (SBERT) compared with its base version, confirming that lightweight domain tuning can enhance PCB knowledge comprchension.
Domain-Specific Model 2: RAG-Enhanced Qwen2.5-7B. We additionally construct a Retrieval- Augmented Generation (RAG) system based on Qwen2.5-7B 7--.5--7-B-nntucctt The retrieval corpus contains 178 PCB-related documents (== 4.5M tokens), indexed using FAISS with all- all-MiniLMM-6-y embed- dings (chunk size 512/50, Top-K = 8). The architecture retrieves relevant PCB knowledge before generation, enabling more grounded reasoning. As shown in Table 2, the RAG-enhanced model
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Published as a conference paper at ICLR 2026
significantly surpasses the standalone Qwen baseline in accuracy and hallucination reduction, par- ticularly on complex engineering queries requiring factual grounding.
C.2 EVALUATION METRICS SUPPLEMENT MATERIALS
We include BERTScore and SBERT as they widely adopted semantic evaluation metrics in the community. Since our open-ended tasks emphasize semantic correctness and factual grounding, exact-match metries alone are insufficient. Embedding- bbaed metries provide more reliable as- sessment for technical QA and domain- language generation, as demonstrated in prior work (Gehrmann et al., 2021; Chang et al., 2024; Manakul al., 2023; Zhou et al., 2024; Gao al., 2021; Saakyan et al., 2021; Liu et al., 2025).
BERTScore (Zhang et al., 2020) compares candidate and reference sentences in a semantic space using contextual embeddings from BERT (Devlin et al., 2019), which computes token-level cosine similarities and aggregates them into precision, recall, and Fl scores. Unlike n-gram overlap met- rics such BLEU (Papineni al., 2002) and ROUGE (Chin- Yew, 2004), BERTScore prioritizes semantic similarity over surface-fort matching. making more robust to paraphrasing. We adopt the F1 aggregation (BERTSccre-F1) and refer to it BERTScore throughout.
SBERT (Reimers & Gurevych, 2019) adapts BERT (Devlin et al., 2019) using Siamese or Triplet architectures (Bromley et al., 1993; Schroff et al., 2015) to produce fixed-size sentence embeddings. Compared with vanilla cross-encoder BERT, SBERT allows efficient computation of semantic sim- ilarity by encoding sentences into embeddings, between which cosine similarity is measured to quantify sentence-level proximity.
We also report token-level Precision, Recall, and F1 based lexical overlap between the prediction and the reference. Let d be the set of tokens in the prediction and R the set of tokens in the reference; define:
P |P]
|POR| R
F1 2. Precision Recall
Precision
Recall
(1)
Precision RReaall
Precision measures exactness, Recall measures coverage, and Fl summarizes both via the harmonic mean.
To further examine how existing semantic metrics behave in PCB reasoning tasks, Figure 7 visu- alizes the relationship between BERTScore and SBERT across all three tasks. The results reveal consistent pattern: although both metrics aim to quantify semantic similarity, they capture different tends to reward surface-
aspects of model outputs. BERTScore, being aiken-alignmenttoriintiee form overlap, while SBERT, sentence-embedding metric, more sensitive to global structural coherence. As consequence, models do not lie along single diagonal trend; their positions vary across tasks and modalities.
This divergence is particularly visible in Task 1, where free-form QA often leads to lexical variations that affect BERTScore more than SBERT, with Qwen2.5 and its domain-specific variants showing especially large gaps between the two metrics. Task 2 exhibits tighter clustering, reflecting more structured answers driven by visual grounding. Task 3 shows the smallest spread in BERTSScoee but broader variation in SBERT, indicating that unout-unddrst descriptions differ more in discourse structure than in token choice. Together, these observations highlight that general-purpose semantic metries do not provide a unified stable signal for evaluating PCB reasoning quality, especially when answers differ in style, granularity, or engineering specificity.
C.3 PROMPT TEMPLATE
To ensure fair and meaningful evaluation, we also provide the prompt templates used in our exper- iments. These templates are derived from extensive practical testing under the current accessibility settings mainstream LLMs, aiming to preserve formatting consistency while allowing models to fully express their reasoning capabilities. When using this benchmark to evaluate other models, please first verify that the chosen template enables the model to perform at its best. Our templates serve reference rather than the only the optimal choice.
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Published as a conference paper at ICLR 2026
Mocoment Lavrl
Mocament
0.22
0.42
0.63
0.33
0.33
0.3
BERTSom
BE4TSooe
Routing Macro Level -QA
Routing - Micre Level -
0.532
0.5
0.39
0.3
0.15
1.72
0:50
0.70
0.02
BE9TSoom
GTT-4c
Conini25-ho
HentL3-788
Minstullpp Cwen25-BBrrsio
Owend 5-18 inttrrutuull
OTT-
Mydhohas- 3-320
Méc Owent 5-18 recruct 30-5
Opade-Qpa--11
Recrente-228
(a) Comparison in Task
Task Piscement (OAP)
Routing
0.55
6.07
0.600
0.60
0.600
0.65
0.09
0.65
0.53
3.04
0.55
0.09
5.57
0,05
0,800 0.25
0800
0.08
0.000
0.66
5800
0803
GITS
Garen:25 me
Gren Vi Mix
caro
Goreno
Qwend vi inarrc
(b) Comparison in Task 2.
0.50
0.54
3816
0.018
0.020
2.802
0.624
5.605
0.823
SFES
Geminod 5-flwes- S- to
Ownn-i aMa
LLate--- dk
Ownn 1D intruct
Semini-2 5-rr
Owen-3Vu 20e-333---55-------0 A225-thnkrr
(c) Comparison in Task 3.
Figure 7: Comparison of BERTSccre and SBERT across the 3 tasks, illustrating their differing sensitivity model outputs.
C.3.1 TASK
Prompts of task CQ
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Published as a conference paper at ICLR 2026
#single_choice. lttee_chooie__uuueeeeeeeeee wtt.euuuuttttttssseereeeeeee pyy.see_pronget
You are a professional PCS design and electrenic engineering expert with extensive krowledge circuit design, layout, signal integrity analysis, related aceas.
Please
the Iollowing FCB related multiple choice queations based expectise For each ques:ion:
carefully analyze the quastion end esch option.
2. A.ppyy your FCS design knowledge for reasoning.
accurate
1.0nly provide the letter of the option (A, B, C, D, or R), no explanation is needed.
Prompts of task 1 QA
snvestior_anavee aaseraaasaaammmmmm prommpt:::
professional design electronics engineering expert with extensive knowledge in circuit design, PCB layout, and signal integrity analysis.
Using your experLise,
the Icllowing PCB related Carefully snalyze what the question asks.
questiens. For each queatien:
Apply your PCB design knowledge to enalyze and solve the problem. 3. drovide an acourate, detal led, and profesatons anawer.
Keep
Locused; emphasize the key points.
Meintain professionsl securete tone.
C.3.2 TASK 2
Prompts of task 2 CQ
You craiic__qeesion_rye. in PCR design and electronics engineering with extenaive knowl in circuit dealgn, FCB layout, and sigral integrity analyais.
For each PCB-related milsipe--choiee question:
1. Consider the quastion
options internally.
2. Use your 2CB expertise decide the single most
option.
3. Output exactly one uppercase latter: A, в, C, D, or E.
Do not include any
explanations, panctuation, spaces, line breaks. The
response must be exactly one character, with so trailing or leading whitespace.
5. sultiple optiens appear correct,
output only
6. Do v generate any content than the letters A, B, C, D,
Mointain profeasioral and accurate tone.
Prompts of task 2 Fill in Blank
#fill_ in blank_questteee sppettio__yyataaeee aw promppt:::: You are an expert in PCB design and electronics engineering with extenaive knowledge in cireuit design, PCB layout, and signal integrity anslysis.
Using your expectise, anawer the following PCD zelated fill in the blank questions. Each '_' without causing any gremmatical issues. question
answer must
1. Consider the question internally.
2. Use your 2CB design knowledge to determine the cerrect value.
3. Provide each easwer as an Arabic nuneral.
Reply only
answer; provide any explanation.
Maintain
professional securete tone.
Prompts of task 2 - QA
Eguestion_answers naawer__ystee__pamee You are en export in PCB design and electronias engineering with axtenaive knowledge in circuit desiga, layout, and signal integrity anslysis.
Caing your expertise, answer the lowing PCR-rolated open quest ona, question:
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Published as a conference paper at ICLR 2026
Carefully analyze
questicn asks.
2. Apply your FCB design knowledga to analyze and sclve the problem.
3. Provide an accurate, detalled, and professional anawer.
4. Keep the
concise and focused; emphesize the key points.
Mointain profeasional and
C.3.3 TASK
Prompts of task 3
iquestion_answe eyswer_
You are an expert in PCB design and elactronics engineering with extensive knowledge in cfreuit ge, PCR layout, and sigral irtegrity ara maalyss..
Using your expertise, ansver the following PCB-related open questions. For each question:
1. Carefully analyze what the questien asks.
2. Apply your FCR design knowledga to anslyze and solve the problam.
an accurate, detailed, 4. Keep the answer concise and focused; emphasize the key pointo.
professicnal answer.
Maintaia professional and accurate Lone.
C.4 EXPERIMENTAL RESULTS
In this supplementary section, we provide the complete results of PCB-Bench across different sub- tasks, covering both placement and routing under macro- and micro-level settings. For placement, the results are reported in Table 5, Table 6, Table 7, and Table 8 (Figure 8, Figure 9, Figure 10, and Figure 11); while for routing. the corresponding results can be found in Table 9, Table 10, Ta- ble 11, and Table 12 (Figure 12, Figure 13, Figure 14, and Figure 15). These tables and Figures report detailed scores of multiple state-of-the LLMs, including both choice question accuracy and open-ended QA metries (BERTScore, SBERT, and etc).
These additional results complement the main text by offering a lineggrained comparison of model capabilities under diverse scenarios. They allow readers to examine not only the overall trends but also the strengths and weaknesses of each model with respect to specific subtopics PCB design.
Table 5: Performance comparison on task Placement Macro-Level Question Answer. (Acc.: accuracy reported in percentage (%))
Placement - Macro-Level Choice Question
Model
Module Placement
Power Ground Planning
Signal EMI EMC
DFM Practical Concerns
GPT-4e
90.48
GPT-5
90.91
85.71
89.47
86.36
Clade-OOus-4.1
90.91
92.86
92.11
97.73
Gemini-2.5-Pro
89 09.09
85.71
81.82
DeopSeck-Chai-3.1-677
92.11
LLaMAA-tMaerrsk-O000
82.82
64.29
84.21
79.55
IntemnVL337888
87.27
90-48
94.74
90.91
MythooMax-L2-13B
69.00
52.38
68.42
72.73
Rocinamte-128
80:00
78.57
84.21
86.36
Ministral-3B
45.45
$7.14
$7.99
79.55
Qwen-2.5-7B.dl I--strnnttt
78.18
80.95
92.11
88.64
Qwen2.5-7B- 1-178--Inssuutt-uoool (D.S.)
89.09
90-48
92.11
90.91
Satee-een....7--eeeeee (I..S))
81.82
85.71
97.73
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Published as a conference paper at ICLR 2026
Facemant HarrsLove On Cuantion
00
DMYa
dem
Modio Facrest
Scrund Poeney
Piarical Cancerts
Figure 8: Performance comparison on task 1. (Acc.: accuracy reported in percentage (%))
Table 6: Performance comparison on task Placement Macro-Level Question Answer. (BERTSccore and SBERT for open-ended QA; B.: BERTSSore, S.: SBERT)
Placement Macro-Leve Question Answer
Module Placement
Power Ground Planning
Signal EMI EMC
DFM Practical Concerns
BERTScone
SBERT
BERTScore
SBERT
GPT-4o
0.8234
0.4772
0.8234
0.4545
0.8240
0.4679
0.8281
0.5012
GPT:5
0.8133
0.4681
0.8203
0,4102
0.819]
0.4528
0.8209
0.4639
Clide-Opus--411
0.834
0.4986
0.8131
0.4467
0.8141
0.4615
0.8142
0,4932
Gemini-2.5.Po
DeepSeek- Chanec-hhht--3-6777 V
0.8282
0.5111
0.8293
0.4553
0.8310
0.4744
0.8347
0.5164
LLaMA-4 4-aavrrccct-00000
0.8151
0.5048
0.8153
0.4645
0.8150
0.4708
0.8174
0.5244
InterVVL3-78B
0.7913
0.4196
0.7911
0.3857
0.7827
0.3868
0.8083
0.4663
MylboMax-L2-133B
0.4526
0.8311
0,1805
Rocinante-128
0.8142
0.4803
0.8157
0.4361
0.8170
0.4539
0.8235
0.5061
Ministral-39
0.8179
0.4779
0.8162
0.4670
0.8194
0.4634
0.8253
0,5084
Qwen-2 Decan2.5-7B--aae 2.--7------ssttret
0.7321
0.2441
0.7292
0.2033
0.7280
0.1991
0.7305
0.2394
Twen2.5-78-Iastruce QLoRk
0.4967
0.4829
0.6196
0.1656
AxG-Quea2..57BB-teee (D.S.)
0,6102
0.4675
0.6165
0.5309
0.6182
0.5175
0.6149
0.5164
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Published as a conference paper at ICLR 2026
Obsie d
Deptentriatad abbutt
Amsoit
Myliaete
Recraad
Sel "Bomatee (1.)
Iener Ground Namiigg
SOEETE LDIson
Figure 9: Performance comparison on task 1.
Table 7: Performance comparison on task Placement Micro-Level Choice Question. (Ace.: accuracy reported in percentage (%))
Plarement- - Micro-Leeel Choice Question
& System Placement
High Specd fiorenntia Routing
Interiace Connecee Placement
Spacing Clomnee & Orientsioon
Crickal Componenn Placement
Vis & hetelayer Ciimecivityy
Man Cumffactuabiltgg at Testaility
Gesenal Rules de Proctical Tips
FMT& Consiieemtinn
Model
up Layer Design
Themml Mangeumant
Mecumical Conmiicaloooouiiiii Construins
Powes Integrtry
Signa Interiky
GPT-4o
95.96
92.86
100.0
GPES
91.41
94.83
94.17
87.39
92.16
82.35
75.00
50.77
95.77
92.86
92.31
90,00
100.0
100.0
Clande-ppus44)
95.96
94.83
95.00
91.89
93.63
84.31
83.33
92.31
97.18
85.71
97.44
100.0
96.67
100.0
Gemini-2.5.PP
93.94
78.57
93.33
DeepSeck-CCha--311..777
13.1-7718
94,04
93.08
96.67
92.79
94.61
$2.35
75.00
84.62
97.18
85.71
96.15
93.33
93.33
100.0
78.57
LLtemVL31-88
92.42
95.40
97.50
91.89
95.59
84.31
75.00
$4.02
100.00
78.57
94.87
100,00
90.00
100.00
MytheMax-1.213B
61.62
47.70
52.50
45.05
38.73
55.82
75.00
61.54
59.15
21.43
78.21
93.33
66.66
71,43
Racimmte-133
79.80
83.91
75 68
70.11
76.9
$0.00
100.00
70.00
64.29
Ministral-BB
71.92
32.18
47.50
39.64
36.27
43.14
50.00
23.08
33.90
21.43
64.10
96.67
66.67
71.43
Qwen-2.5-78-am In78-
64.29
Qwen2.5:17 S.BB Instrucs QLoRA (D.S.)
94.44
89.06
92.50
88.29
85.29
84.31
100.00
$4.62
90.14
64.29
87.18
100,00
89.66
84,62
RACI-Qwa22 5-7B-Instret (D.S.)
90.40
85.63
90.83
90.99
84.31
78.43
83.33
76.92
85.92
71.43
91.03
96.67
93. 10
84.62
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Published as a conference paper at ICLR 2026
Racement- Chrice Quession
GPC
Drepheet Chelry Ad71
SP
Sogt poreut
Steaa Sumprra
Backin
Figure 10: Performance comparison on task 1. (Acc.: accuracy reported in perventage (%))
Table 8: Performance comparison on task 1 Placement Micro-Level Question Answer (BERTScore and SBERT for open-ended QA; B.: BERTScore, S.: SBERT)
Phumond Mare Locdl Qerden
1000
VONT
EITU
SEIT
CALL
KETI
ESTO
EJ0 CODY XMDO KEDU
AINE
LOO
CAKE
CAIDE
OFTEF
EXIS
EIIK CHET Y40 BAAK CROA
CAUL
DAND
CART
DAVT
CATO
DAZE
SIMIT
EXIC
EASH CIDO SIDE XISO CHLE DASK
SHOU
KMU
CALT
SIOW
SOM
EMIT
DANE
SIGH
CIMO
EEST
DATE
SYNE
CAMI
SCM
SM91 EXTL
KTTU CITD SOMR EXIT CTSO OUTO
KINT
CTIO
SONS
ATIO
CTDC
JUICE
STMA
CAITE
OTTA
COKC
CTILL
ETDP
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Published as a conference paper at ICLR 2026
Plcement Mireland Quenter lowe"
0017
can cereereer
U.C Redis BrS
1807
Figure 11: Performance comparison task 1.
Table 9; Performance comparison on task Routing Macro-Level Choice Question. (Acc.: accuracy reported percentage (%)
Ronting Macro-Level Question
Model
Basic Shape and Routing Rules
Groound and Return
High Speed and Signal Integrity
GPT-4o
98.31
100.00
97.30
GPT-S
100.00
100.00
97.30
Claude-Opus-441
Gemini-2.5-Pro
100.00
100.00
DeppSeck-Cha--3...
100.00
100.00
91.89
LLaMA-4- M-0erc---ne
83
95.65
94,59
VntermVL.3-788
MytheMax.I.2-130
61.02
69.57
78.38
Rocinante-122 12B
89.83
$6.96
91.89
Ministral-38
71.19
73.91
81.08
Owen-2.5-7B.Inssssst
91.30
Qwen2.5-7RB TR--Insreet-OLoRR (D.S.)
98.31
95.65
97.30
RAG- L.G--wen2.5.777 Instrrctt (D.S.)
96.61
91.30
86.49
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Published as a conference paper at ICLR 2026
bouing Quasion
Acuncc
Geotet
pourlea Chatrid 4728
Mem
Oeea SRlatret
inttuct qtad
all alc-weeaa not tosteeeeii (1.
Model
Dasic Snape and Souting Rutes
Power Ground and Satur Fath
High Spaed Integriy
Figure 12: Performance comparison on task 1. (Acc.: accuracy reported in percentage (%)
Table 10: Performance comparison task 1 Routing Macro-Level Question Answer.
(BERTScore and SBERT for open-ended QA; B.: BERTScore, S.: SBERT)
Routing
Question
Model
Basic Shape and Ronting Rules
Power Ground and Return Path
High Speed and Signal Integrity
BERTScore
SBERT
BERTScore
SBERT
BERTS
SBERT
GPT-40
0.8261
0.5201
0.8293
0.5086
GPT-5
0.8173
0.4575
0.8189
0.4186
0.8228
0.4859
Chude-Opus-1.1
0.8158
0.1969
0.8175
0.1359
0.8158
0.1923
Grmini-11..PPr
0.8067
0.4470
0.8059
0.4057
0.8071
0.4586
DeepSok-Chuu-V3311-55
0.8309
0.5107
0.8262
0.4320
0.8336
0.5047
LLAMA--Maveriik44000
V13-781
0,8067
0,4853
0.8002
0.4028
0.8121
0,4800
MythoMax-L2-15 L2-11-
0.8234
0,4830
0.8184
0.3980
0.8355
0.4864
Rocinante-
0.8220
0.5001
Ministml-38
0.8197
0.5083
0.8168
0.4519
0.8236
0.4904
Qwen-2 5----..-----sstre
0.7329
0.2351
0.7276
0.1920
0.7280
0.1907
Qwen2.5.7B. Intruct-OLoR. (D.S.)
0.6333
0.4839
0.6223
0.4907
0.6286
0.4554
RAG-QwenZ (-aen22--78--aae 5-78-Instrus (D.S.)
0.6226
0.5348
0.6178
D.5309
0.6280
0.5427
27

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Published as a conference paper at ICLR 2026
clerd
Heeer Mi
d3sk Shape and Houting Rures Be-15core
Power Se sund and Hutum Huth 20 scare Power Ground and Ratur 20.57
Hiy speed and Sijro innegrity 0::155ore Figh Spaed and Signa imnegrty
Basic Stape and Bouting
Figure 13: Performance comparison task 1.
Table 11: Performance comparison task 1 Routing Micro-Level Choice Question. (Acc.: accuracy reported in percentage (%))
Routing Miero-Level Choice Question
Interiace Isalation and Domain Crossing
Diaribution Timing Conrrll
Delivery Ground Recurn
SeDes and Hlgh Speed Scrial Links
High Speed Layout Challenges
High Speed Differential Pairs
DDR and Menory Interfaces
RF and Mixed Signal Routing
Signal Quality and Impoddncce
Model
Crosstalk and Coupling
GPT-4o
90.99
95.00
78.95
87.10
100.00
GPT-5
85.59
Clande-Opes
92.79
87.50
100.00
85.48
91.38
97.30
93.10
94.44
100.00
96.30
Gemini-2.5-PP
86.49
90:00
89.47
85 48
87.93
94,59
86.21
88.89
100.00
92.59
87.39
92.50
94.74
85.48
87.93
97.30
79.31
88.89
93.75
85.19
LLLMA---Maversd--000
73.87
70.00
73.68
69.35
70.69
83.78
62.07
61.11
50.00
85.19
InlemVL33788
88.29
90.00
100.00
88.71
98.28
91.89
89.66
94.44
93.75
88.89
MythoMax-I.2-13P
45.05
80.00
36.84
50.00
31.03
Rocinante-12B
Ministrl-3B
$9.46
77.50
42.11
59.68
44.88
51.35
34.48
61.11
43.75
48.15
Qwen-2.5-78-Innse
86.49
82,50
68.42
72.58
89.66
86,49
72.41
83.33
87.50
85.19
Qwea2.5-7BB- Lea.s-----nstuut-Loee (D.S.)
85.59
92.50
78.95
74.19
89.66
81.08
75.86
72.22
75.00
$1.48
RAG. Dwen2.5.7B..m 5-7B-Instrud (D.S.)
84.68
92.50
68.42
75.81
91.38
91.89
89.66
72.22
100.00
88.89
28

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Published as a conference paper at ICLR 2026
Bouring Memotevil Prreeeevl--Dreeee queetion
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Speed Layest Crallengs
Mardd Sgral looting
Clock Diintoution Timiing
Serbien Speed Serai Links
Figure 14: Performance comparison task 1. (Acc.: accuracy reported in percentage (%))
Table 12: Performance comparison on task Routing Micro-Level Question Answer.
(BERTScore and SBERT for open-ended QA; B.: BERTScore, S.: SBERT)
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0245
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3,503
EDIT3
29

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Published as a conference paper at ICLR 2026
Layal damen 281
New Celvery wnt8 and Nta Bloee
Sigul Quclly and lrymii secces and
and hauri 58MM
Cook dindaa trai aurtscos
Creatigg
Figure 15: Performance comparison task 1.
C.5
CASE STUDY
C.5.1 TASK
Case of task 1 CQ
30

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Published as a conference paper at ICLR 2026
Text-Text cheice question
Questioo:
Now to plan low impedance current sensing paths in power chipe?
A. Dae iscmetric sampl lines to pair parallel current paths and add protect diode structure in the midele to atabilize the sampling
B. The sampling resistor is connected to the signel line at the shortest time, and the sampling line is routed close to the formation and the structura is connected using Ke vin
C.Add filtering devices
power input and enaance voltage compensalion through the sampling centrol unit
D.Place the sample pointa at the end of the output channel to avold 1oop interference and facilitate centralized management of signal ports
N.No of the above options are correct
Model: googge//eminii22.55r
Prompt:
You are a professional FCB design and electrenics engineering expert with extensive knowledge in circuit design, PCB leyout, and signal integrity analysis.
Using your expertise, answer the fallowing PCs-relsted open questions. for each questien: Carefully analyze what the question asks.
2. Apply your PCB design knowledge to analyze and solve the problem.
Provide accurate, detailed, and professional answer.
4. Keep the answer concise and focused; emphasize the key points.
Maintain a professionsl and accurate tone.
Reascning Fronesa icorraspending to the reasoning field in chattomplddiionleenns-----. MMS)
oojects
"viänalyzing Current Senaing Pathsuslalaa'n curreatly focused on the challenge of designing lox-impedance current sensing paths within power chips.
evaluating varieus options, and righ: new I'm carefully considaring option A, regarding isemetric sampling lines and prosective diede structures. The goal is to optimize the perallel current psths for stability. i' weighing the pros and Exomining PCB Routing sarattggea=+<rrat"" been drilling down on the intricacies of exploring investigating
of this spprosch.\nnniae
iow-ingedance current sensing. Whlle still think isometric 1ines are 2'm now focusing en comparing option B to A. By intuition tells me optica B is less flawed than option A, which seems have mistranslsrion. pl placement of the sarpling resister, and its connaction time can improve current accuracy, Baanin the Beat Strategy+<\nknT4 now prioritizing the question planning low-impedancn eusrent sensing paths. Option alearly atands emphsaines ses a short connection to the sampl ing resistor, close routing to the ground place, Kelvin connections misleading use of dicdes. Optiens C and D address aspects that are less crucial then Option H, such as genersi filtering and port placement, the Optimal Answerva (nnntrv now carefully ana analyzing the answer options to pirpoint the best strategy for designing low impedance current aensing paths. Optioa continues to stand out due to its emphaaia and a focus on grounding, Option A still seems to have issues, with the inclusion of diodes sampling stability. Options
the
accuzacy. Option seens flawed
the
connaction, Kelvin connectiors,
offer useful tips, are ast as directly relevant to the core goals of accuracy as Uption H's grounding and Kelvin connections, AmAn\n",
"Index': D, 'type': "reasoning text", text'; Aeannayying Curcent Sensing Pathee<\alnnI'n currently focused on the challenge designing lox-impedance current sensing paths within power chipa. various options, and right аоw I'm carefully considering op.ion & regarding isometric structures.
sarpiing__etttsss_____ (31''
avalvating
sampling lines and protective current paths for stability. z' weighing the pros and cons of this ap Examining PCR Routing (rraatggeeax)rrltt
geal is to optimize the parallel Anin)ze
been drilling down on the intricacles of low ingedanee current sensing, Walle I still think isometric lines are worth exploring I'm new focusing on comparing option to A. By intuition tells me option is less flawed than option A, which seema placement of the sempling resistor, and its connection time can improve current azcurazy, evaluuaig the sest strategy+<nttnl" now prioritizing of planning low-impadance eusrent sensing patha. option clearly atanda out, It emphasizes a shor: connection to the sampling resistor, close routing to the ground place, and Kelvin connections for accuzacy. Option A seens flawed due te the misleading use of diedes. Options C and D address aspects that are less crusial then Colion B, suct. as general filtering and port placement, respectively, AnvalavsSeeelliig the Optimal Answerv<\annlf the best strategy to stand out due to ita emphaais a short connaction, Kelvin connect and a focus on grounding, Option still seems to have issues, with the inclusion of diodes for sampling stability. Options and effer useful tips, but are aot directly relevent to the core goals of accuracy as uption s's grounding and Kelvin consections, \sAala"))
mistranslation.
investigating
the
question
new carefully snelyzing the answer optiens to pinpoint designing low-impedance current sensing paths. Option
Final Answer Icorrasponding to tha content field ChatComp htt.rommppiiinntttssog--g-i objects returned MM3)
'B'
31

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from Published as a conference paper at ICLR 2026
Case of task QA
Text-Text Placement question answer case:
"question":
"Where should external
buttons be placed?"
"reference_answer"" "Near KCU resat pins with proper ESD protection."
"G2T-40 prediction": Put the reset button where usezs can reach it without disassembly- ideally board edge or uncbstructed panel.
good mechanical support /around the button to avoid PCB flex and damage. (3) Keep reaet traces short; route over solid ground plane to reduce noise. (41 Baadle debounce in hardware or firmware reeded. (51 Add protection le.g., low-cap diodes; right the button. (6) Jabel claarly and diffarentiata from other keys; use preess/uuad/covar to prevent accidental pressea.
users can and intentionally, (2) Put the reset conditioning (pull-up, filter/supervierr, series resistor) right next to the device being reset. (3) Put ESD protection right the button connector that Einger/cable touches.
prediction":
user-accessible
safely
"claude-Opue-4.1 prediction"
edge edge for easy resch; ideally en the same side other user I/O (power switch, LEDs). circuits:
accesa:
beard
Keep away
sigh-freguency/powe areas. (2) Away
Maintain clearance from cryatal oscillators, PLLs, and analog sections. Keep least 10-15 mm from RE circuits/entennt and avoid proximity to high-speed differential pairs.
pio prediction" (1) Prioritise electrical integelly: place up/RC close to the XCU zeset pin, keep the trace short over a solid ground, noisy nodes. (2) Ensure user accessibility
prevent accidental presses (edge for consumer productsl 13) Match rechanical/eme /encl osura constraints: align with openings and provide Pts support under the switch. (4) Add protection and robuatnesa: 2S8/TVS the button, RC debounce, small series pu_1-u9 at the MCU.
pl placement, vecensed/pinholl
Bhegsseek-Cha--33.--1 prediction" :external reset buttens should be strategically placed PCB ensure functionality usability. Pesition the eastly reachable the user, typically near the edge the board or enclosure, avoiding obstruction by other components. (2) Place the resst butzon clase to the roocontioll
where
length, reducing susceptibi ity not and enauring clean, :eliable signal, (3) Use ground shield IE necessary, (4) II using
min'ml
aee--accessible, include prozection (e.g., debounze circuit (&C filter or Schmitt trigger) to prevent felse resets.
disde)
prediction"s (1/Fiaae the reset button close to the XCU/processor reset pin to minimize signal path length. (2] the button away from high-frequercy signals sensizive circuits reduce operation typically on the board edge or front side and consider surroundiag composent placement avoid crowding. (4) poasible to roduze delay and intesference; avoid running them through nongested routing areaa preserve signal integrity. (5) decoupl capacitor near the reset button to reduce transient currents the stabl liy. (The model's "eason'ng process usea chinese.!
(3) Poaition
easy
traces
straight
rails and inprove system.
"LLeKA K-vee--rikkk-eee 4008 predicsion": (1) should be placed in location that is convenient user or technician to press the exterior of the device or enclosure. The exact location can depand the design of the device and ita intended use. Conaided the design and layout constraints. The placement of external reset button must slso censider the overall design and layout of the device. It should not interfere with other components or the normal operation
E2teraal reset buttons placed
designed withstand expected environmental conditicns, such temperature, humidity, and mechanical stress. Determine practions suggest that external reset buttons should be placed accessible
device. Additionally,
appzopriste
based on common practices commer.
location that is accessible but no; prone to accidental activation. For many devices, this means small
placing the recess to prevent accidental preases. In conclusios, external reset buttons ahould be placed in an accessible location on the device, such and potentially in recessed area prevert accidental activation
button the edge
the bottom of the device,
the edge near
"TaternV13-799" External reset buttens should strategically placed on FCB to enaure reliable operation and ease of use while minimizing pozential issues. lleze are the key considerations for their placement: (lJAccessibilsty: Place the button accessible leeation on the SCB or encloncre, such as near the edge or on panel, to press without difficulty. (2)hhchei Constraints: suffizient clearance around the button to accommodata the actuator and prevent interference other components or the enclosure. (3)Rlactrica) constderatoons:
easily
is
32

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Published as a conference paper at ICLR 2026
Route reset signal sway from high-speed ez sensitive analog circuits avoid noise coupling. Use dedicated trace with appropriata shielding or spacing if necessary, ddDDeccupling: Flace a decoupl ing capacitor near the reset pin of the microcontreller or IC filter
noise and place external reset buttons in accessible, mechanically secure lecatiens, away from sensitive circuits, with proper signal routing and prozection. Ensure compliance with deaign and safety standares to maintain relfabi and functionality.
clean reset signal. In sunmary,
"Ministral-33 External reset buttons should be placed strategically they are easily accessible, provide clear visual indication of their function, and minimize the risk of secidental astivation. llere placement: (11 Accessibility: Place the reset butter in z locstion that is easily accessible for both location that is difficult to reach or obscured by other components. (2)Visual Indication: Enaure the reset button clearly labeled
a PCR to ensure
the key considerations for
the mairtenarce personnel. Avold placing
essily sdontsfiable. this nearby legend the PCB, (3) satety and
can be done through physical lanel Reliability: Place the zese: but:on in location that minimises the zisk ascidental activation. avoid placing zear other buttons switches that could be confused with it. In summary, the placement of external reset buttons should Hty,
signal integrity. The location will depend on the specific design and user requizementa.
prloritize
indication, safety,
"Mythomax- 12 13b1; External reset butlons should be placed in location that is essily accessible and visible to the user. They should be placed on the PCB in such a way that they Additionally, they should be aabeled clearly with text or aymboll to indicate thair function, It is
easily damaged sczidentally triggered during normal operation.
recommended inolude pull-up input to ensure proper operation when the button is no: pressed.
button's
"Rocinante 120"; Ixternal reset buttens should placed the front panel of the enclosure, neer the power switch, for easy access, Here are some key considerations: (L/Acceasibility:
button should ba easily ascessible near the power switch a lows usera to eastly find and operate both controls. (2) Safely: preven. accidental resete, between the two buttons can help avoid unintended
the
Placing it
button should not placed
to the power switch. A small presses. 13) considerations: knsure that tha reses butson compatible with the enclosure's front and force required to press it, as these factors can affect the user experience, (4)
cutout size. Also, consides the button's travel distance
Circuit Besign: The microcont or the zeset circuit. Ensure that the button's electrical chatecteristics (e.g., resistance, capacitance) are compatible with reset circuit' a requirements. By fellowing these guidelines, button is essily accessible, safe use, and reliahla in your dasigr.
button should connected tha
of the
can ensure that the external reset
"5wen2.5-75-Ime -t-.------tnatrut--iio... " To ensure the nignal quality of the reset button and reduce interference, the external key modules: (1)Micrcconttollle Unit (MCU): The reset signal is directly connected to the MCD's reset pin. transmitted to the XCU quickly and effectivaly. Fower Kanagement Module: If the reset operation is related to power status, the reset button should placed near tha the
buttor should placed close the following
care component, this ensures
reset signal
power management circuit stable. 13) Cenaration Kodule: If the reset operation relies on a stable clock algral, the guarentee the reset opecation fuastions propecly when the clock signal is stable. In summary, reses butson should be positicned close рower managament module and clock generation madule to ensure the afficiency and re. fabl of the reset operation.
signal is valid when the power supply is
posit
generation module
microcentroller unit,
:Resstt buttons should typicall ly be placed near modules that easily accesaible uaers, allowing for convenient and quick reset operations when needed. Sperifically, the reset button should be laid out in relation te the following madules: (1)Main Control Module: aystem' a oparation, the reset butter should be placed closs to the main control module enabling a swif: reset case of system abrocmalities. (2) Importtnn: Functional Modules: If specific functiensl nodule requires resecting due to issues, the reset button ahould be located near that module, allowing users to quickly identify and particular function. (3)User Interface Module: impacts the user interaction experience, the reset butzon should be placed nesr the user interface madule, enabling users to reset promptly if problems arise during operation, Tn summary, the placement of the reset buttor should be determined based on the specific application scenario and usez needs, ensuring it l8 easy for users to locate and operate.
reses operstion affests the entire
reset operation
Case of task 1-QA QA
Text-Text Routing question answer case:
"queation": "Nhy recommended route sensitive signals on internal layers?"
33

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Published as a conference paper at ICLR 2026
"referenze_ =atseer "internal Layers can provide better elestromagnetic shielding reduce external interference."
"32T-4o prediction": (1) (L)eleettomgneeti shielding: internal layers are naturally shielded by the outer layers of the which typically inalude ground and pewer planes. This sh'elding helps protec: senaitive algnals from external elactronagnet interference reduces the Tmpedance: Internal layers al ow for better control of the impedance of the traces, This is crucial for high speed signals where maintaining consistent impedaace is aecesssry to prevent signal reflections and Crosstalk: By routing sensitive signals on internal layers, you can minimize crosstalk adjacant signal praces, The proximity to ground planas helps cortain electromagnetic rields and reduce coupling between traces. (4) Stability: Internal layera are leas exposed to rovirrttttall changes. This can important maintaining aignal integrity in varylng temperature conditions.
of radisting noise other parts of
circuit. Controoldd
signal integrity. Reddced
"32T-5 prediction"; (1) Shielding planes: This greatly reduces both radiated emissions and susceptibilsty to external naise (RF, ESD, handling, nearby aggressoral, (2oxmmmyyy to continuous ground plane under the Liace, minimizing loop area and reducing croastalk and :inging, (3:More consistent impedance: The dielectric environment is uniform tightes impedance control and lower discontinuitien
tight, low-inouctance
ourrent di
predictable, enabling than surIace microstrip exposed to sir. Reduced coupling to external souices: Internal reuzing is less exposed te capacitive pickup and magnstic coupling from other boards, cablas, and the enviranment which is critical for high-ttpodarrce aralag nodes and low-leval aignals.
"Claude Opus 4.1 prediction"; (1)euptrio: EMI Shielding: Internel Interrss layers are asturelly shielded by ground/power planes above and below them. (2)tonreeleed impedance iniironmen::lteerne layers maintain consistent dielesiric thickness to reference planes. (3) Protection:Protected from mechenical damage, scratches, and handling, (4)aetter signal integrity:stripliiee configuration isignal between plares) provides auperior signal integrity compared to microstrip.
"Semini-2.5-ee S-pre prediction": (1) Superior RMI/DNC Performance (Shielding) :Internal layers, whan placed betwsen two solid reference planes (typically Srinternal layers typically stripline configurations (traces between two reference planes), which provide better impedance control and lower cresstalk compared to microstrip (outer layer traces) .ound or Power), form stripline configuration. This structure flattened coaxial cable, provicing excellent shielding, (2) Emisaions:The electromegnttic fields generated by the high current signal are lergely coatained between the two reference planes. This prevents the signal from rediazing outwards, which critical interference with other components in the system. (ighig Impedance Control and cleaner Keturn Fath:For high-speed signals, msintaining constant characteristic impedance is eruaial prevent afgral reflactions and preserve algnal quality.
like
passing EMC emisaions testing (a.g., FCC, CE) and preverting
"DeepSeek Chat-Va V3.1- 671B prediction"; Electromagneta, interference (BMI) reductios and signal integrity (SI) protection: Saielding from External Noise: Internal layers are naturally sandwiched between ground power planes, which act as shields. (2)
Internal layers typically use stripline configurations Itraces between two referance planes), which provide better impedance control and lower crosstalk compared microstrip (oster layar tracea). (3) BMI Emissions Reduction:Ry confining sensitive aignals internally, radiated emiasions are minimised, helping comply with requlatory standazds (#.g., BCC, CE).
"gven-2.5-78-11 S-18-nntrutt prediction": (1) Lower 3I: Internal layers are less expased to external fields, reducing eleagnenatett interference. (2)Tess couplings They cut down inter-signal coupling, especially high fraquencies. (3) Better signal intagrity : Reduced external noige meana fewer reflections and lesa croastalk, Therma) layers can from ovechesting. (The model's reascning process uses Chinese.)
management:
patha, preventing pertormance loss
"LIaNA- MH1aM----aavrriob-40f prediction": (1)nnderstand the context of the question. (2)Recal1 the principles of signal integrity and eomagromageetis interference (EMI). A3)Aaaly the benefits of routing sensitive signals internel Jeyers:Firstly, it reduces the exposure of these signals to external romagnettic interference (BMT) since they are sandwiched belween other layers, typically ground power planes, shields. Consider the role of ground and power planes in μк reductier. Ground and power planes on adjacent layers can act Foraday sage or shield, protecting internal signal layers from external RMT and reducing the omiaston of EMT from the signals on these internal layers.
act as
"Rocinante 12b": Bouting sensitive signals on internal layers of PCB offers several edvantages: (1)Reduced IXI/2CC Issues: Internel layers shielded by the outer layers, reducing the electromagnetic interference (8ML) and electremagnetic competibility (EMC) issues. This ia particularly important for high-apend digital signals and analog circuits. Improved Signal Integrity: Internal layers provide more contrelled enviroument fer signal treasmission. They are less affected by and other noise
externsl factors like semperature changes, mechanicsl This zesults in better signel integrity and reduced crosstalk. (3)Beiler Control over Impedance: Internsi layers silow for more precise control over impedaace of
34

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Published as a conference paper at ICLR 2026
traces. This is crucial high-speed signals where maintaining consistent impedance is vital to prevent signal reflections and distorsions. (3) Trace Length: By routing signals on internal layera, you can often reduce the overall trace length. This is beneficial for high speed signals as is reduces the propagation delay and potentisl signal degradation, =t summary, routing sensi:ive signals on internal layers helps to impreve aignal integrity, raduce EMI/EMC issues, and prevides better control over trace impedance and thermal management. I: a key atrategy 1a high-apeed high-parffrrance PCE design.
"Mythomax 12 13b": It is recommended to route sensitive aignals on internal layers of printed circuit beard (PCB) for several reasens: (1)Shielding: Internal layers previde better shielding frem external electromagnatic interference (X21) and radio frequency interference
outer layers.
ia because the internal layers
are suzrounded by the other layers of the PCB, which act as a shield against external sigrals. Reduaed crosstalk: Creastalk is the unsented coupling of signals between adjacent traces on different layers of the PCB. Since the sensitive signals are routed on internal layers, Lhey are less likely to experience crosstalk from other signals routed on the outer layers. Reduced noiss: internal layers also provide lower noise environment for sensitive signals, as they are furthar away from the pever and ground planea which routing sensitive signals on internal layers can help improve the signal Lategrity and reduce noise the PCB design, leading to better circuit performance.
be
of noise. Inproved signal integrity: overall,
"Ministrei "Ministrel-33" Routing sensitive signals on internal layers is recommended for several 
less susceptible rloctromagaatic interference (EMT) and crosstalk from externsl layers. This is bacausa the aubstrate material, (21Signal Integrity: Internal layers provide more controlled and predictable environment for signel routing. This helps maintain signal integrity, reducing noise accurate signal transmission. (3)lleat Diesipation: Internal layers the heat sinks or other heat dissipaticn machanisms, which can help manage the heat help reduce
reasons: (1) Reduced interference: internal layers
signals are ahlelded by outer layera
easuring
eften closer to
generated by sensitive components. (4)Miise Reduction: Internal layers notse by providing a more colt ed and isolated path for sensitiva signala, This is patticularly impoztan: routing seasitive signals on internal layers helps maintain signal integrity, reduce noise, and improve overall porformance and reliability of Fis.
high speed signals and analog circulls, summary,
aaatezmeee "Laternvl3-79e": Aouting sensitive signals on internel layers of a PCB is reconmended for several key reasons, primarily related sigral integrity, electramogeetic
interference (DMI), and overall board reliability: a detailed analysts: (1) Crosstalk: Interns: layers
Reduced EMI planes, which act as nstural shields. this configuration helps to contain and reduce elactromanaotic interference (EMI) both from and to the sensitive aignals. planes provide llw- low-impedance radicted emiasicns, (2) Improved signal integrity: Internal layers can be designed with effectively die the coze material. This is crucial for high-spees speed signals, where maintalniag a sigasl consistent charasteristic impedance is essential to prevent reflectioas degradation. Enhanced Machanica'. Protection: Internal layers are less exposed to physica) damage compared to outer aayers This is particularly important for sensitiva signals that could be compromised by soldering, handling, envirenmental factors. In summary, routing sansitive signals on internal layars laverages the shielding effect of ground croestalk, and provides nechenical protection. This approach is best practice in PCB design to ensure reliable bigf-pezformance electronic systems.
typically surzounded by ground or power
ground
path, minimiring loop
and reducing
cortrolles impedance
consisten: dialectrio properties
power planea, improves aignal integrity,
EMT and
ngwent
"Owen2 "Qwen2.b-7R- .5-75- Tnot
(D.S.)"; The inner layera can provide better elect romagnetic shielding and reduce the impact of external interference. Placing sensitive signal traces or the inner layers is common practics in PCR design for the following reasons: [l)Reduced Electromagnetic Iaterference (EXI): Signal
on the layers are less suscepsible to externel environmentel influences, as the outer layers are more prone to interfereace from external elestromagnetic fields. The inner layers can better shield against interfering signals from other layers, improving signal purity, (2) Lower Parasitic Incuctance and Capacitances Inner-layer traces are typically closely edjacent to power planes and ground planes, which helps achieve effective ivve decoupl ing and minimize the Impact of parasicic Inductance and capacitance. (3) Inproved Signal Insegrity: Inner layer routing can more effectively leverage advantages of mul=ilayez FCBs (e.g., miltilayer stack-up structures), thereby optimizing signal patha and reducing reflection and cresatalk. In aummary, placing sensitive signal traces on the inner layers can significantly improve signal qual reduce interference, and optinize overall circuit pezformance, Tais practice is the result of considerations across multiple aspects, including elecssemagnetic compstibility (EMC), signal integrity, and physical layout.
(U.S.)*: The main reason fer routing sensitive signal traces on reduce romggrottt interference (EXT) and sigral irtegrity
the inner layers issues. Specifleally, routing traces the inner layers provides better electromagnetic shielding, thereby zeducing the likelihood of signals radiating into externsl space. Additionally, inner-layer routing signals, as they are closer to the power and ground layers, which helps form a propez signel return path and improves signal integrity. Therefore, routing sensitive signal
minimize crosstalk between
35

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Published as a conference paper at ICLR 2026
traces en: layers common practice design ensure signal quality and stability.
C.5.2 TASK 2
Case of task -CQ
Tmage-Text choiica quest case:
Question:
that type electronic devices the composent package shown in the rigure typically used fnd? Resistor'nß. Snall signs. transister\aG, Electrolytic capacitor\aD. Inductor Ank. None of the above options is correct
Model: googlee/emini-2.5ee
Frompt:
You are an expert in PCB design and electronics engineering with extensive knowledge in circuit design, PCB layout, and signal integrity anslysis.
for each PCe-related multiple-choice question:
1. Consider the queation
all options internally.
2. Use your 2CB expertise to decide the single most correct option.
Output exactly one uppercase letter:
B, C, D, worda, explanations, punctuation, spacea, Line breaks. The response must be exactly one character, with no trailing or leading whitespace.
4. Do not Include
5. if multiple optiens appear
select the best and still output only its letter
generate ary content other Maintain professional and accurate Lone.
D,
Reasening Frocess leorreapending to the reasoning Rield in ChatComplet Lon.eeeess like objects returned by LLMs)
*nnalyzing the AsquestVs intent>* fecused grasping the instractiona. TtMss about taking or the role of a PCR design expert and answering a multiple-chone question component footprints. accuracy in selecting the optimel answer and edhering to the specified output format. consdengons rco:print tharacteristicsv \aknil imagel's foatprin; details. The shrough-hola pads and the uniqua D-shaped si kkacren outline are key clues. The arrangement of three pins in line, alengside the through- options and the Componen: Type*=\n\nTV now packaye.
of the user\'s
structure erphasizes
carefully examining the
hole
of the pada, component types cons worrabby..nnnnr.eate zeroing
rule
the potantial
fcolprint cleatly indicales Considering this, options à, C, and appear incorrect. The three leads and the D- shaped silkscreen strongly point decision basad on this "eason' ng. MMinnnnaRefiring the volutioonuannnnt consolidating my thoughts. Considering the packagel's design and crrangement pins, and knowing that the image presenta TD-92 fostprint, my selection of *5* remaina tha optima choice, It aligns completely with the characteristics of the component type identified. AnAAAa
the correct answer,
small signal transistor,
finslizing my now
Final Answer icorraspanding to content returned LTMs)
chatCompletionteennne
objects
'B'
Case of task 2 CQ
Image Text choice question
Question:
type electronic devices the companent package shown the figure typically fnr? Realstorins, Snall aigna transistorVno, Mlactrolytic capacitor(1D. Irductor \nE, None of the above options is correct
Model: openal/qpt-5
#rompt:
are expert PCR dasign alectronics engineering with extensiva knowledge circuit deaign, PCB layout, and signal integrity analysis.
For each PCB related aultiple choice question:
1. Consider the question and all options internslly.
2. Une your scB expertise to decide the single most correct option.
Output exactly one uppercase lester: A, B, C, D,
4. Da not include any warda, explanctions, pinctuation, spaces, line breaks. The reaponse must exactly one character, with trai leading whitespace.
36

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Published as a conference paper at ICLR 2026
5. multiple opticns appear correct, the one output only
6, Do not generate any corten: other than the letters &, B, C D, or E. Maintain professional and sccurate
Reascning Frosess lcorraspending the reasoning field in chatoomplettionneenng----
cojects returned by tiMs)
*=Idennifying the companent shape= trying identify a component that appears b8 shaped 1ike semiefrels *D," with three pads stacked vertical which looks reminiscent of T0-92 tranaistor package. The outline is definitely the arrangement of the three pins suggests itV's small-signal transistor. Khile there are other packages like SUT-23, the TO-92 is distinctive due to its through-hols dasign.
shape, and
need to conticm whether the pads are in straight 1ine for through- hole footprints. think the
TC-92 connector, typical pin pitch spacing la 1.27 mm. The leads are usually radlally apaced, but in this image, they're re stacked vertically, possibly because it's rotated 90 degrees. That acceptable! Overall, this package commenly used for smell-signal transistors, 50 can confidently concluda it's option B. I'll make sure to output just ane uppercase
Bettermining pin arrangament
analyzing
letter, which
be
Finsl Answer Icorresponding returned LIMs)
centent field ChatCommietiiinteezza---- objects
rB'
Cases of task 2 QAQA
Figure 16: Example case of Image-Texx Placement Question Answer (Task 2).
Tmage-Text Placement question answer csse:
"question"; "Shere is the main power connector locsted the PCB?"
rrefarence_answer". "Tt is on the far right edge, narked with +12 V, -12 v, VOUT, and GNn pade."
"32T-5 prediction": "The main power connector is the two-pin screw terminal on the right- edge
lower-right corner,
"+12y" (Mith GND)
"G2T-5-nano prediction"; "The main power input on the right edge of the PCB, It'a the power header locssed the bostem right three-pin power connector that feeds the +12V rail)."
labeled with 112V and 3ND (the two/
Deminii-2--22e prediction": "Based en the analysis of the PCB lsyout: AaknThe main power connecter is **P2**, 3-pin connector labeled =*CoN__.<r, located right cornere* of the Board.An)neskee indicators:e *181 kscreen tabels:** The pine of connector 72 are clearly labeled with "<\"/127,".. and ..!" 127(".., indicating it is the input for dual-rail red traces originate from P2 to distrioute power acrosa the beard, which is charecteristic
++bottom-
supply, \a+ .*oower Traces:** Thick
power lines designed Protection carcuiszy: viodes ul and 24 (1N4004) are placed immediately after the connector pins, serving as reverse-polarity protaction, common feature for power input."
higher current.
"jemini-2. S-r predicsion"; "The main pover connector is labeled ++ and is located on tha righ: aide of the PCB, near the bottom right corner. it has three pine, labeled v*t12Ves, v*p2xx, *4-12ves, indicating it's likely milti-voltgge power input."
37

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Published as a conference paper at ICLR 2026
"Laeea-d-Ravesick prediction"; determine location the PCB, nend analyze the given image and identify the relevant componerts. Ar **Step 1: Identify Powe:-Related Componentsv various composents labeled. To find the main power connector, should look for components or labels related to power input. Steep 2: Anelyze Labels and Compenent notice several labels and
power connectee on
Image ahows FC3 layout with
Namesxv'n innessviinnnnoooo examining the image, The lanels (*+127\" and \*-12V)* are associsted with connectir labeled \"P2\* and \ CONS_3X* This suggests that the ponnector++<nnnni the PCB layout, It has three pins labeled \*1129\", middle pin (not explicitly labeled in the text buz visible in the imagel, and \*-12V\", This configuration is typical for a power input connector providing both pesitiva and negative voltage suppliea, ConnauConnllsioon \nkaThe main power the .*bottom right of the PCB, It is designed to accept both +12V and -12V power inputs."
likely related to power input. Snan 3: Locate connector \*F2)" or \*CDNN_3 is located at the bottom right
is (CDNN_31 located
"Iaternv13 736 prediction". "The main power connecter on the PCB is located at the bottom right
labeled *22" and includes connections for "+12V," *GNE and *-22v." This connecter in responsible for providing the necessary power supply to the board."
"wen-VVLXax prediction";
.+CON located the varight sidexs of the board. It is 4-pin consector labeled with kv112Ve,, <>-12V **, v.GNDe and AAVOUTAY, and it is clearly marked in the schematic layout, Veaathis connecter
power connector
the primary power input for the circuit, providing botà positive and negative 12V supplies, along with ground. The power traces (shown in redl distribute power throughout the
originate this connecto:
"2wen3-v1- -b-iistrunttttt prediction": "gased
previded PCB layout image, conrector is localed in the k-bostem right cornerva of the Anlad. is labeled **CNM__ and has three pias clearly marked:in- 14= +*380=a 4 athis connector is designed
power
provide the primary power input the sircuit, aupplying both positive and negative 12V rails alorg with ground reference. right edge
AninThe reference.IntoThe
connector is posi.ioned near Rax_32K0- component and the ..Uš.. chip."
PCB, adjaceat
"Qwen3-vi v1-23-b- -1-2331b--22bb a22b s2bb--hiibiign prediction": "ValaTe detesnine the main power connector location: Anl. Analyze power-relsted labels and connections: The PCB shows .**1 ..-12ve, +*NND. labels
connectar. \n2. Identify the connector: The component labeled **Cо8T3** (botton right aectior) is associated with these power dedicated pins
1122, 12V, and routing: Red power traces (indicating power distrsbuticr) originate from this connector. a The mair power connector is vACOMM3NA, loested at bottom right of the PCB.
\n3. Confizm, power trace
C.5.3 TASK 3
Case of task 3
BRASS
BORRD
R2400
Figure 17: Example case of PCB design understanding (Task 3).
Design Underatanding case:
lon": "Briefly describe the function of this PCB board, covering as aspecta possible while keeping the language concise." "reference_ensver"" K Gigabit Switch with SPF interface
1. Overviex
RTL83679 RTL4213B chips, forning a gigabit switch with an SEP interface. It supporta both gigabit Ethernet and sFe intesfaces, providing high-speed network connect fona for variors devicea. power input section 18
combination
38

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Published as a conference paper at ICLR 2026
compatible with two types interfaces: standard De jack rype-C interface, offering users flexibility in choosing the appropriate power input method.
2. Punction Deacription
Gigabit Switch Function: Integrated with the RIL83678 switch chip, it supports high speed dats forwarding, previding gigabit network connections.
Interfase: The board offers SP3 interface, alloking for with optical medules for long-distance network connectiors.
Power Supply:
board supports two power input interfaces, stendard 5.5mm jack a Type-C interface.
Voltage Regulator Chip: The TPS54335A DC DC buck converter from Ti is used, aupporting a wide input voltage range of 1.5V to 28V. It avoids using the internal buck output of the switch chip, reducing chip hest generation.
3. Working Principle
The switch usea the RIL83678 chip as the core for nanaging multiple Ethernet ports, while tha intarfaca provides long-distanso network connectiviny. Power is supplied through either the 5.5mm DC Jack or Type-C interface, and the voltage is regulated the 12554335A buck converter, ensuring stable operation for all components on the board.
4. Test Farameters
Tnppu Voltage:
supporta wide input voltage range (4.5V 28V1, with different power Input options available.
Network Performance: supports sigabit-sped
transmiesion, suitable for apehd
data exchange.
Power Consumption and Tempereture: The external veltage regulator reduces heat generation within the chip, ensuring stable operation.
5. circuit Overview
circuit the RTG83675 chip
switch, supporting multiple gigabit
Ethernet ports and the SEP interface. The TPS54335A chip is used for power management, converting input voitage to Capacitors, resistors, and other components used for and signal filtering, ensuring efficien: operation.
eomponents on the board.
6. Notas
Power Selection: The power yupply muat be within the recommended range of 4.5V to 28V to ensure proper sys.em. operation.
are laterfare Usage: The SEP interface requires ccmpatible optical modules for use, ensuring stable netwer's connections and long-distance cormunication.
"GPT=5 pradiction": *- function: 4-port 10/130-Mb Ethernet switch. \n- Central CFP the switch ASIC; tour R545 connectors along the botton are the LAM porta, Different each jack through integrated nagaetica/BM parts. Power: y vBUs input (via the usH connector at left). Two UC/D2 supplies create 3.3 (E/0/PHY) and "1.1 (corel) additional 100a/filters power analog blocks. An- stotus/ UX: LED arrays the top provide per-port lick/activizy and 100-M: speed indicaters (VACt, \" \"READY, \* ("FXLED-20ONA" An- control/Uebug: Headers lsbeled SDA/SCK (12C), TX/RX (CART),
pairs out
all configuration, fi tirmarr//cnsoll hardwaze zeset. Small MCU/manager near U2 likely handles
ard ionniittiio////t
Timing/Signsls: Crystal/oscillato: boot options. Length-matched differential routing and ground stirching indicate attention to signal incegrity. Protection/EMT RSD/RMT parts near the jacks; ground -connested nounting holes for chassis/earth. AnAnin short, this board is USe-powered, mi cereoonttaller-mmnne ler-managed 4-port Fast-Sthernat switch with acatus LEDS and debug interfaces."
strap resistors around the switch set clock/
"32T-S-aano prediction";
description (functicnal overview)
Type and purpose: campact microcentrallar//e development and expansicn baard. It providea power, central procesaing block, ard multiple T/O expanaton paths for testing, prototyping, and debugging, An'n
Power and clock: Powered from USS (VRG3) with an on-board regulator generating ing 3.3 V 13 for Centrel logic: & centrel BCU/So2 !U? in the middle) with support chips around it (U2, U4, etc.). The layous and surrounding parts suggest
V3_R). There
atatua Indicalors
controller,
interfacing, clock distribation,
and signal conditioning for high-spead or mi mixed-signal operation.An)n Interfaces and I/O:\n
USB zelsted signals and power support).
IVBUS, 3V3, regulator, likely USB transceives
bebug/programinn headers: TX/3X (UARI), SCA/SCK (I2C/821 family), GND, 3V3, RESE,, etc., for easy access to the core.
Four expansion/comaator banks at the
labaled RJI-RJ4, likely extarnal
modules, sensora, pertpheral Anses.An
Froat panel iadicators: ACT/READY and multiple PxIED indicators plus a bank of displays for status simple readouts.
Lefi-side I/0: additional header holes/pads for more GPTO, power, or signals. denze routing and speed nets imply mixed signal intended fer rapid prozotyping of peripherals, bus interfaces (12C/SP1/UART), and external module integration;
Leyout and purpose:
four RJ ports quick connection lon and visibility of activity, status, and measurements Anin In short: a USB powered, 3.3 logic development board with centrel NCU/SoC, multiple buses (12C/SP1/UAKT) several expansion ports, and visible status indicators for debugying, Lesting, and fast protolyping.*
frant-panel indicators support
39

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Published as a conference paper at ICLR 2026
"Gem:ni-2.9-33 pradiction": "Basad en an expert analysia of the PCR loyout, here is concise resoription of Its function: AnkoThis tunction-kalaThis network switch complex network iaterface carday, Aalnf44 cardar,\alnf44
PCB is a hirh-performanne, multi-port Key Ponetional Aspects: \ne c>Core suncrion:*s The beard's a primary role is to manage and route network dadicated ssnetwork switch
traffin. the contral BGA chip (U3) is FRGA/BoCAv that acta aa the system's core, hardling data packet awitching between the various ports. AnAaa **Network Interfaces:+e
AYoour RJ45 Ethernat Ports (RJ1 -RJ4) f*r These provide standare 10/103/1000 Mops copper Ethernet connect The associated LEDs (labeled 100/1000, ACT/Readyl indicate 1ink speed and activity status for each pert.
vAOse SP2 PortivA The feosprin: the left is for Small form-factor Pluggable (SFF) cage, this allows for flexible, high-speed connectivity, higher-speed f-ber optic copper transcelvers. Anina
typicallly ly for Control and ieaagement:avlyy
vaSysten
**Management MCU (U2) à smaller microcontro (32) likely manages board-level functions, such as inizializing the main switch IC, controlling LEDs, and providing external management inzertaces.
ConfigurationnDeeuug Ports:*a The beard includes a AVUSB porlAY (For powez, configuration, or firmwere updates), *AUART seriel conscles. (TX/RX pins), and 12c header.* (SCA/SCK), all common for device managemant and debugging. ArAa **Powrr Ma The cireuft includea an orboard power delivery system featuring DC-DC switching regulators (U4, US) and Inductors (LI, 12)."
"Semini-2 2.5 2.5--1ash Site prediction"; "This FC3 board appeara to be contrel interIace board, likely for a system invelving multiple commuicatiion channels and status indicators. indicators.kninkey functions and components observedr'min-
**Fover Distributions. Multiple \"VeUsy" and \"OND\" connectora/pate auggest power input and distribution. voltage requlatora power corditioning components (e.g., M, 12, U4, USI likely providing different voltage rails (e.g., 3V3_R, 1V1_R) Aa+ .+LED indicaters: Numezous LEUS (1aD1-1E010: are present, along with associated current- limiting resistors (R5 RiO, R35 343, 357 R801, These likely indicate system status, activity, or error cenditions. The labels \"ACTV" \"READY"", \"xxEED0"" , and ("FXLEDI **Cormnicattion interfaces:+*1n \" signals indicaçe an T2C or simt ar serial comurication interface. tranamission interface, Aa The presence of multiple 3J connecters 1831, RJ2, RJ3, RJ4) with labeled pins (PI- 210) implies modular or external connestivity, passibly for sensers, astuators, or other peripherals.Ine
There
further support thi
\*SDA\" and ASSCK (*TX("
\"XX* signals suggest UART other secial
vaCentrol and LogicivA The central IC (U2, likely
mi microcontreller or FPSA) is the core processing unit, managing the varieus functions and interfaces. Components like R12, R13, R14, R16, R19, R23-R35, R44-R56, C7-C15, C36 642, 044, 045, 047-551, 054, C5 C57-C60, C62, C68, CT2, C13, C75, and 31 (Likely a crystal or oscillater) support the opezation this central In. **Rsst and configuration:: \"HK_ and \"S_RESET>" signels indicate hardware and software reset sapabilitiss, \CCPI003>* suggests genaral-purpose imput/output pins additional control monitering, Aninin summary, this board acts central hub for receiving power, processing data, commnicating with external davices via serial interfaces and modu lar connectora, providing visual feadback through 1339."
"LLeKA-4 1a-la-4-Xavee --vverickk prediction"; "The beard depicted the image is complex electromic circuit heard with multiple companents and functionalities. The beard appears to be network switch or similar devies, given the presensn of four R.45 conrectors (RJ1- commenly used for Ethernet connections. inl \n\p<<Ke +*8245 Connectors (RJ1-RI4) :.. These connectors are
8J4) at the bottom, which Components and Featuras: used for Ethernet connections, indicating that the board designed applications, \n2. AvLED Indicators:As à series of LBDs (IED1 1ED10) are present on the board, which are likely used to indicate the status of various functions such as link activity, power, or other operational statas. presence of vol regul atora le.g., J4 and US) auggeats that the board is deaigned operate with different voltage levela, passibly converting input voltage stable octput vol for the comporenta on the hoard. Ar4. * ler or Processor:*s Although not explicilly labeled, microcontreller or processor, given its size and the complexity of the surrounding circuitry. This component Power Supply:av The board has power input sectior, indicased by the \*VRUS)" labels, suggesting that it is designed to be powered via USB connection or another external power source, An6. v*Reset and Configuration Optiens:*> The presence of reset buttons or switchea (e.g., 3_RESET and HM RESETI allows for reaetting the device to its default state configuring board is designed to manage and facilitate Ethernet connections through the four 8J45 connectors. it likely includes features such an:inine Network switching or routing'ns TFD indicators for stacus mon't toringln Voltage regulstion for stable operationnns Control and proceasing via a riorocont:oller or procesaor Reset and configuration options for device device designed for nezwocking appl icatiinn,,,, with a rance of features and functionalities that enable
networking
viVoltage Regulators:as The
central component (03) is likely a
crucial for controllang the board's operations. Ar5.
in differeat modes,
balaeverlllll the beard is a sophisticated electronic
manage and facilitate Ethernet connectioas."
"Interne13-79h predictian". *This BCB appears to ba complex interface heard, likely for networking or communication application. Here's a concise overview of its furctionar alnl. .-Bower Management in Includes voltage requlators (3V3, 191) for power supply regulatien. vBus lines indicate connections for powez distribation. AnAn2. s-Commuziattin Inter[acesAAsha 331, 3J2, RJ3, RJ4 connectors suggest Ethernet or serial commuiicacion po SDA, SCK, TX, RX pins indicate and UART
40

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Published as a conference paper at ICLR 2026
interfaces for data commuiication. AE\a3. waJeD indicators++: Multiple LED arrays (P6L8D0, PXIED0) for status indi caticiionn... (e.3., astivity, link and Controlxv:
.*Bstt EM RESST and GFTOU3 pina for tardware reset and general-purpose input/output control. An'n5. i-Comnetivatyyx:la ensure stable power and signel integrity, modules (e.g., USB, CPIO). wvSignal Integrizyva:le decoupling capacitors (C48, 045, etc.) to minimise notae and ensure reliable operation Annnnwerall, the monitoring in networked or embedded system."
Multiple ground (GND) conrections Connertors for external devices or Careful routing and
facilitetes commenication, power management, status
WW-K-VL-Kax prediction": "This PCB is amicracontzoller
development interface board.. designed for embedded applications, featuring power management, commurication interfaces, and feedback elemerts. Key functions includes *xPowar Supplyas: Incorporates voltaçe requlatore (I1: 3,39, uss 1.19) to provide atable power to digital components
vaus input, likely USB-powered. An- **tiarocontraller
Interfacev:: Peatures central rolle (02) with SPIC, UART (TX/RX), T2C (SC) /SDA), and reset (IK_ RESET) signals, enabling commuicatiio and control, v1IED indicators Kul=iple LEDS (LADI-LED10: with current-limiting resistors provide visuel statua feadback (e.g., ACT, READY, PLED) An- **xxterns connectivity-e:
Tncludea multiple headers (RT1-RJ4) for periptersl exparston, 1i sensors, actuatore, or other modules.'nn =<Clockinges: Usea external crystal (X1) with load capacitors (07, (a) Lraces suggest USB connectivilyy possibly Ior programming power, x*Rese and Debugas: IM RESET and GPI03 suggest support for hardware reset and debugging (e.g., JTAG/SNU via GP10s) An= veUccupling and Filteringa::
precise timing. \a-
Interfaceve: The VBUS USB-related
capacitors (c1-030)
enaure stable power dalivery and mirimize noise. In- *+layou***: Dual-layer design with power distribation IVBUS, indicating attention to signel integrity and EXI control. Annn@verall, this beard serves as vecempact, uSs-powered eabedded platformrs integration, supporting digital I/O, seriel commuicaation, and real Lime feedbeck."
clear signal routing, ground planes,
1VI1,
protozyping system
"bxen3-21-@b-inatree" prediction"; "This is +emulti-port USB 3.0 hub controller board **, designed to expand a single USA host port into muiziple deanst uSR ports we managing power and
Key Puactions:<< AnAea. **Port Expansion: Provides miltiple USB ports (likely 4x US3 3.0, indicated by RJ1-RJ4 connecters) for connecting paripherals. An2. vXPoNeE Management Features dedicated power regulators (U4, US) convert and distribute 5V/3.3V/2.8V rails for the controller and ports. Includes power monitoring (#GLEVS, PSLED1) and surrent limiting (K60-877) .n... vabata Routing hub controller (U3)
Usea uss and the downstream Ane. v*Communication control:* Includes an I2C interface (SD&/BCK) configuration status monitoring, and a hardware reses RESET) and software reset (S_AE)TT) for systen control. **Status indicationie- L2D indicators (LED1-1ED10) provide visual feedback port activity, power status, potentially
data betwean the
VRUS
conditions. An6, A*Signal integrity: Uses differential pairs (e.g TX/RX, SDA/SCK) for high-speed use 3.C data transmiasion, with proper routing and termination, An7, **Power Distributions ensuring adequate power delivery to connected devices. AAAaIa essence, it acts as bridge, allowing single
VRUS
routed each port,
host to connect multiple devices while managing рower, data, and status signsis."
-wen--o1-23b--22-ttiie
prediction": "aaarhii PCB functions Asmulti port Ethernet switch/hub with Fower over Ethernet (POE) capabili-y.e. Key aspects: \n- connectivityes::
ports (RJ1-3J4) support 100M/1000M Ethernet, enabling network data transmission. \n <xPower Nanagement Voltage regulaturs (01/05 for 3.3 v/2.1v) and vaus distribution provide zegulated power;
implied via AJ45 (cemmon in Ethernet pawered devices). Ar- kyStatus Indicationas: LEDS (ACT, READY, 36LED3 /11 monitor port activity, 1ink status, and apeed (100M/1000M), \n- exControl Commuicattions 12C (SDA/SCK), UART (TX/EX), and reset aignels (S_RESET, 3N_RESET) enable mi micracontroller based configuration and diagnostics. \n- +*3ggrl Trtegrity high
planes (GND) controlled transmiseion. \nAnIt integrates network switching, power delivery, and system monitoring compaes layout."
zouting ensuze
data
D LLM USAGE STATEMENT
We use large language models (LLMs) only as a general-purpost. assistant tool for minor tasks, including grammar checking, correcting formatting errors, and polishing individual sentences.
As our paper is a benchmark-oriented study, we also use LLMs as tools during dataset construction (e.g., format conversion). These usages explicitly described in the corresponding sections of the main text.
In addition, we evaluate several widely used LLMs as part of our experimental study. This consti- tutes standard benchmarking practice and is reported in the experimental section.
41


Reviews:
[{"review_id": "s5wvE44mhu", "reviewer": "Reviewer_LXVR", "summary": "This paper presents PCB-Bench, a comprehensive benchmark for evaluating the reasoning, multimodal understanding, and real-world engineering capabilities of large language models (LLMs) and multimodal LLMs (MLLMs) for printed circuit board (PCB) placement and routing.\n\nPCB-Bench has three complementary task settings and integrates three modalities: textual reasoning, image-text reasoning, and real PCB design comprehension. It includes over 3,700 text QA instances, 500 multimodal tasks, and 170 complete design projects with schematic diagrams and placement files.\n\nThe benchmark aims to bridge the current gap between foundation models' open-domain reasoning and the highly structured, constraint-driven nature of electronic design automation (EDA).\n Results from multiple state-of-the-art models (GPT-4o, GPT-5, Gemini-2.5, Claude-Opus-4.1, Qwen-VL-Max, etc.) show that while these models exhibit some knowledge of PCB principles, they struggle significantly in multimodal reasoning, domain rule adherence, and real-world design understanding.\n \nPCB-Bench fills an important gap by providing standardized tasks, expert-curated questions, and reproducible metrics for EDA-oriented foundation-model assessment.", "questions": "- Annotation Process and Quality Assurance:\nHow many domain experts contributed to the curation process, and how were disagreements resolved? Was inter-annotator agreement assessed, or were examples reviewed by several experts?\n\n-Difficulty Calibration: Are \"easy/hard\" tags assigned objectively (e.g., the number of design rules involved) or subjectively by annotators?Could the authors provide a question breakdown by subtopic (e.g., EMI, differential pair routing, power delivery)?\n\n-Representation Bias\nThe dataset depends mainly on open-source OSHWHub designs. Do these projects overrepresent specific device categories (such as USB hubs)? Could this bias affect generalization to industrial boards with more dense routing?\n\n- Have the authors considered testing domain-specific systems(such as RL-based tuned models or retrieval-augmented models)? Will combining PCB-Bench with simulation-based feedback loops (such as constraint violation detection) give more realistic metrics?", "limitations": "", "rating": 6, "confidence": 3, "soundness": 3, "presentation": 3, "contribution": 4, "strengths": "- Novel Domain and Multimodal Integration\nPCB-Bench is the first dataset to integrate textual, visual, and structured PCB design data, covering the entire reasoning chain, from physical layout interpretation to rule-based design explanations.  This bridges the gap between EDA and current MLLM benchmarks.\n\n- Expertly curated and Content.\nThe QA and CQ datasets are based on validated engineering principles (e.g., impedance control, EMI, high-speed routing).  The inclusion of over 25 subtopics across macro and micro-level placement ensures depth and realism.\n\n-Comprehensive Model Evaluation\nThe authors benchmarked eight major LLM/MLLM systems under a unified zero-shot protocol, revealing clear differences in factual reasoning and semantic generation quality.\n\n- High Practical Impact.\nThe paper connects foundation models to PCB design automation, a real-world domain where LLMs could help with debugging, constraint checking, and educational tools.", "weaknesses": "- Limited Novelty in Dataset Construction Approach\nAlthough the domain is new, the methodology (expert-curated QA pairs + image-text matching) follows established benchmark pipelines. The contribution lies in domain adaptation rather than methodological innovation.\n\n- Missing fine-grained statistical validation.\nThere is no explicit agreement among annotators or confidence interval analysis. To improve the dataset's credibility, a quantitative quality measure could be used beyond relying on expert curation.\n\n- Evaluating Diversity\nOnly foundation models trained on general data were tested, and no domain-specific baselines (such as fine-tuned models or SPICE-guided reasoning agents) were included. This limits one's ability to distinguish between reasoning limitations and domain unfamiliarity.\n\n- Lack of Complexity or Difficulty in stratification.\nWhile \"easy\" and \"hard\" labels exist, difficulty calibration is not quantified (for example, through expert scoring or performance correlation).  Future releases may benefit from difficulty metadata.\n\n- Fairness in Model Comparison.\nThe paper does not specify whether all models were evaluated with identical input resolutions, context lengths, or prompt templates. This may complicate the interpretation of differences between GPT-5, Gemini, and Qwen-VL.", "quality": null, "clarity": null, "significance": null, "originality": null, "strengths_and_weaknesses": "", "was_revised": false, "final_justification": "", "rebuttal": "", "claims_and_evidence": "", "methods_and_evaluation_criteria": "", "theoretical_claims": "", "experimental_designs_or_analyses": "", "relation_to_broader_scientific_literature": "", "essential_references_not_discussed": "", "other_strengths_and_weaknesses": "", "other_comments_or_suggestions": "", "questions_for_authors": "", "summary_of_paper": "", "summary_of_recommendation": "", "technical_quality": "", "clarity_of_presentation": "", "potential_impact": "", "robotics_focus": "", "quality_of_limitations": "", "questions_for_rebuttal": "", "reasons_to_accept": "", "reasons_to_reject": "", "questions_to_authors": "", "extra_scores": {}}, {"review_id": "NkhXe1SQgm", "reviewer": "Reviewer_3Nqz", "summary": "This paper proposes a benchmark containing three types of datasets: text-to-text QA and CQ, Image-and-Text QA and CQ, and a real-world PCB design repository. Based on this, the authors execute three corresponding tasks and benchmark various LLM backbones.", "questions": "- The authors claim that domain experts write the questions. I just wonder what kind of domain experts they are, like academics or industry professionals.\n- It seems that lots of LLMs achieve 100% accuracy on task 1, routing. Maybe it is too simple for these SOTA LLMs to do this job, right?", "limitations": "", "rating": 6, "confidence": 4, "soundness": 3, "presentation": 3, "contribution": 3, "strengths": "- The collection of the PCB datasets is important and meaningful, which is a basic reason I am leaning towards giving a positive rating.\n- The authors give a clear comparison between current benchmarks, which I believe PCB-BENCH is competitive and advanced.\n- The dataset is released. Though it is incomplete, I am convinced of the comprehensive quality.", "weaknesses": "- The introduction of how to construct the datasets requires a more detailed clarification.\n- The benchmark could benefit from providing statistical results of the datasets, such as how many instances are in each class/topic/difficulty.\n- The visualizations in Figure 1 really help with understanding, but some figures are vague, and I cannot see any information on them. It would be beneficial for the authors to use clearer or even vector graphs.\n- The instances in task 3 are directly collected from OSHWHub, which makes this paper weak in workload.", "quality": null, "clarity": null, "significance": null, "originality": null, "strengths_and_weaknesses": "", "was_revised": false, "final_justification": "", "rebuttal": "", "claims_and_evidence": "", "methods_and_evaluation_criteria": "", "theoretical_claims": "", "experimental_designs_or_analyses": "", "relation_to_broader_scientific_literature": "", "essential_references_not_discussed": "", "other_strengths_and_weaknesses": "", "other_comments_or_suggestions": "", "questions_for_authors": "", "summary_of_paper": "", "summary_of_recommendation": "", "technical_quality": "", "clarity_of_presentation": "", "potential_impact": "", "robotics_focus": "", "quality_of_limitations": "", "questions_for_rebuttal": "", "reasons_to_accept": "", "reasons_to_reject": "", "questions_to_authors": "", "extra_scores": {}}, {"review_id": "T6Y6affo4u", "reviewer": "Reviewer_Gqgu", "summary": "The paper introduces PCB-Bench, a novel and comprehensive benchmark designed to evaluate the capabilities of Large Language Models (LLMs) and Multimodal Large Language Models (MLLMs) on real-world Printed Circuit Board (PCB) design tasks. Authors evaluate several strong models on PCB-Bench.", "questions": "How the answers are parsed from model responses?", "limitations": "", "rating": 6, "confidence": 4, "soundness": 3, "presentation": 3, "contribution": 4, "strengths": "1. The multimodal PCB task is an important and meaningful direction. PCB-Bench is the first benchmark designed to evaluate MLLMs’ capabilities in PCB design.\n\n2. The benchmark’s three-task structure is comprehensive and well thought out.\n\n3. The paper is exceptionally well-written and clearly presented.", "weaknesses": "1. The evaluation is somewhat limited. Only a few models are tested. It would be beneficial to include more models, such as the Intern-VL series and models of different sizes, to provide a more thorough understanding of the benchmark’s effectiveness.\n\n2. In the benchmark construction pipeline (Figure 4), \"Commercial MLLMs\" are listed as a \"Knowledge Source.\" Could the authors elaborate on how these models were used in this process?\n\n3. Some related works are missing. For example, EEE-Bench [1] and Circuit [2] are relevant benchmarks related to circuit design and understanding, and they should be discussed in related works.\n\n4. The performance of most models on the benchmark appears relatively high, which raises questions about its difficulty and suitability for driving future research.\n\nReferences:\n[1] EEE-Bench: A Comprehensive Multimodal Electrical and Electronics Engineering Benchmark. CVPR 2025.\n\n[2] Circuit: A Benchmark for Circuit Interpretation and Reasoning Capabilities of LLMs.", "quality": null, "clarity": null, "significance": null, "originality": null, "strengths_and_weaknesses": "", "was_revised": false, "final_justification": "", "rebuttal": "", "claims_and_evidence": "", "methods_and_evaluation_criteria": "", "theoretical_claims": "", "experimental_designs_or_analyses": "", "relation_to_broader_scientific_literature": "", "essential_references_not_discussed": "", "other_strengths_and_weaknesses": "", "other_comments_or_suggestions": "", "questions_for_authors": "", "summary_of_paper": "", "summary_of_recommendation": "", "technical_quality": "", "clarity_of_presentation": "", "potential_impact": "", "robotics_focus": "", "quality_of_limitations": "", "questions_for_rebuttal": "", "reasons_to_accept": "", "reasons_to_reject": "", "questions_to_authors": "", "extra_scores": {}}]

Author rebuttal:

Decision: Accept (Poster)