A Hierarchical Circuit Symbolic Discovery Framework for Efficient Logic Optimization
Authors: Yinqi Bai
Jie Wang
Tong Xialiang
Longdi Pan
Jilai Pan
Mingxuan Yuan
Jianye HAO
Venue: ICLR 2026 Poster (2026)
Keywords: Electronic Design Automation; Logic Synthesis; Large Language Models;
Primary area: neurosymbolic & hybrid AI systems (physics-informed, logic & formal reasoning, etc.)
TL;DR: Chip Design; Logic Optimization; Symbolic Regression; Graph Neural Networks

Abstract: The efficiency of Logic Optimization (LO) has become one of the key bottlenecks in chip design. To prompt efficient LO, many graph-based machine learning (ML) methods, such as graph neural networks (GNNs), have been proposed to predict and prune a large number of ineffective subgraphs of the LO heuristics.  However, the high inference cost and limited interpretability of these approaches severely limit their wide application to modern LO tools.  To address this challenge, we propose a novel **H**ierarchical C**i**rcuit **S**ymbolic Discovery Framework, namely HIS, to learn a *lightweight* and *interpretable* symbolic function that can *accurately* identify ineffective subgraphs for efficient LO.  Specifically, HIS proposes a hierarchical tree structure to represent the circuit symbolic function, where every layer of the symbolic tree performs an efficient and interpretable message passing to capture the structural information of the circuit graph. To learn the hierarchical tree, we propose a circuit symbolic generation framework that leverages reinforcement learning to optimize a structure-aware Transformer model for symbolic token generation.  To the best of our knowledge, HIS is *the first* approach to discover an efficient, interpretable, and high-performance symbolic function from the circuit graph for efficient LO.  Experiments on two widely used circuit benchmarks show that the learned graph symbolic functions outperform previous state-of-the-art approaches in terms of efficiency and optimization performance. Moreover, we integrate HIS with the Mfs2 heuristic, one of the most time-consuming LO heuristics. Results show that HIS significantly enhances both its efficiency and optimization performance on a CPU-based machine, achieving an average runtime improvement of 27.22% and a 6.95% reduction in circuit size.

Published as a conference paper at ICLR 2026
A HIERARCHICAL CIRCUIT SYMBOLIC DISCOVERY FRAMEWORK FOR EFFICIENT LOGIC OPTIMIZATION
Yinqi Bai', Jie Wang Xialiang Tong", Longdi Pan', Jilai Pan', Mingxuan Yuan', Jianye Hao"
MMoE Key Laboratory of Brain-inspired Intelligent Perception and Cognition, University of Science and Technology of China
Huuawii Technologies Co., Ltd. *College of Intelligence and Computing, Tianjin University byg000 32 A6mail. ust edu. cn,
ABSTRACT
The efficiency of I Logic Optimization (LO) has become one of the key bottlenecks in chip design. To prompt efficient LO, many graph- machine learning (ML) methods, such as graph neural networks (GNNs), have been proposed to predict and prune a large number of ineffective subgraphs the LO heuristics. However, the high inference cost and limited interpretability of these approaches severely limit their wide application to modern LO tools. To address this challenge, we propose novel Hierarchical Circuit Symbolic Discovery Framework, namely HIS, to learn a lighteeigh and interpretable symbolic function that can accu- rately identify ineffective subgraphs for efficient LO. Specifically, HIS proposes a hierarchical tree structure to represent the circuit symbolic function, where every layer of the symbolic tree performs an efficient and interpretable message passing to capture the structural information of the circuit graph. To learn the hierarchical tree, we propose a circuit symbolic generation framework that leverages reinforce- ment learning to optimize ken generation. To the best of our knowledge, HIS is the first approach to discover efficient, interpretable, and segh-perffrmance symbolic function from the cir- cuit graph for efficient LO. Experiments on two widely used circuit benchmarks show that the learned graph symbolic functions outperform previous state-of-the- art approaches in terms of efficiency and optimization performance. Moreover, we integrate HIS with the Mís2 heuristic, one of the most time-consuming LO heuristics. Results show that HIS significantly enhances both its efficiency and optimization performance on a CPU-based machine, achieving an average run- time improvement of 27 22.22% and 6.95% reduction in circuit size. The code is available
strucure-awars Transformer model for symbolic to-
con/ Swt.://AALaaUUSSSAAAA
INTRODUCTION
The modern chip design workflow leverages variety of Electronic Design Automation (EDA) tools to efficiently and reliably synthesize, simulate, test, and verify different circuit designs (Huang et al., 2021 Logic Optimization (LO) is one of the most important EDA tools in the front-end workflow (Berndt et al.; 2022]] Pasandi et al. (023). Specifically, LO aims to optimize circuits-modelle modeled transformations and reduced size and/or
by directed acyclic graphs-wai with functionality-equivaleee depth. It is crucial to well tackle the LO task as it can significantly improve the circuits' Quality of Results (QoR), i.e., various metrics such as size, level, and edge evaluate the quality of designed chips. (De Abreu et al. [ Bertacco et al. 1997). However, the LO task is a challenging / hard & Sarratzadch 1994). which makes extremely hard tackle. To approximately tackle the LO task, many effective LO heuristics such as Mfs2 (Mishchenko et al., 2011]. Resub (Brayton 2006). and Rewrite (Bertacco et al. 1997) have been developed. These
problem (Micheli] 1994]
1 Corresponding author. Email: wtapannnx@utttccu.cc.

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Published as a conference paper at ICLR 2026
heuristics follow common paradigm in which specific transformations sequentially applied to the subgraph rooted at each node (i.e., node-level transformations) for all nodes of an input circuit.
The efficiency of LO heuristics in LO tools has become of the key bottlenecks in chip de- sign, thus significanlly impacting the final circuit performance and all duration for developing and commercializing new chips (Neto et al.) [021 Sabbavarapu et al.) 2014 Reddy et al.] 2014). However, previous studies found that executing LO heuristics can be highly time-consuming due large number of ineffective and redundant node-Ievel transforma- tions (Wang et al.). To address this, they propose a pruning framework, which leverages a key scoring function identify and avoid the ineffective transformations. Specifically, (Li et al. (023) proposes lightweight mathematical expression as the scoring function. However, this method fails to capture the rich structural information of the subgraph, resulting in limited optimization perfor- mance. Recently, (Wang et al.) proposes well-designed graph neural network (GNN) model, which can effectively capture the subgraphs' structural information to accurately identify ineffective trans- formations. Nevertheless, the high inference cost and limited interpretability of GNNs significantly restrict their adoption in modern LO tools.
i.c., the over-
To address these challenges, we propose a novel Hierarchical Circuit Symbolic Discovery Frame- work, namely HIS, to learn a lightweight and interpretable symbolic function from the circuit seggraph-alwayye modeled by computation tree-that can accurately identify ineffective transfor- mations for efficient L.O The key technical challenge lies in designing a symbolic function that can effectively capture subgraph structural information. Inspired by the message-passiing passing mechanism in GNNs, HIS proposes a hierarchical symbolic function representation, where each layer performs an interpretable and computationally efficient form of message aggregation to capture the multi-level structural information, as shown in Figure [ To learn hierarchical symbolic functions, we intro- duce circuit symbolic generation framework. In this framework, structure- aware Transformer is employed to effectively encode tree- structured information and generate distribution over sym- bolic subtrees ar each layer. Subtrees sampled from this distribution are merged to form hierarchical symbolic trees, which are then evaluated using group reward. The reward signal is leveraged to optimize the model through a policy gradient algorithm. Ultimately, the target hierarchical symbolic tree is generated according to the optimized model.
Experiments on two widely used benchmarks show that the symbolic scoring functions learned by our HIS outperform previous sfate-of-the the-ttt art approaches in terms of efficiency and optimization performance. Moreover, we incorporate HIS with the Mfs2 heuristic the most conecconu one among commonly used L. heuristies. The empirical results widely used circuit benchmarks demonstrate that HIS achieves an average runtime improvement of 27.22% and a 6.95% reduction in eircuit size compared with the default Mfs2 heuristic. Furthermore, our HIS learned hierarchical symbolic functions offer strong interpretability, revealing how specific structural patterns in the circuit graph impact the final node embedding.
We summarize our major contributions as follows: (1) To the best of our knowledge, HIS is the first approach to discover an efficient, interpretable, and ser-orerfor graph symbolic function for efficient LO. (2) The major technical contribution of HIS is the novel hierarchical symbolic tree representation that enables interpretable and efficient message aggregation to capture the structural information of circuit graphs. (3) Experiments show that the learned interpretable symbolic func- tions outperform state-of-the-art approaches in terms of efficiency and optimization performance.
2 BACKGROUND
Logic Optimization (LO) Driven by Moore's law, the complexity of chip design has increased ex-
ponentially [Khailany| 2020 Lopera et al.) 2021 Huang et al.) 222TT Mirhoseini et al.) 202T] Ren & Hu 2023 Bai et al. (026). To address this growing complexity, modern design workflows integrate suite of Electronic Design Automation (EDA) tools to synthesize, simulate, test, and verify dif- ferent circuit designs efficiently and reliably. Among these tools, logic optimization (LO)-which optimizes circuits represented as Boolean tewoorks-serve as key component. LO typically in- volves two stages: pre- mappiag optimization and post-mapping optimization (Hosny et al.) 2020 Ren & Hu 2023 Wang et al. [2024; Brayton et al. 2010). In the pre- mraping stage, heuristics such as Rewrite [Bertacco et al.] 1997), Resub (Brayton 2006), and Refactor (Brayton 1982) are used to optimize the input circuit. The optimized logic circuits then mapped onto the target technology
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Computation Tree
HIS
Hierarchical
Symbolic Tree
score
score = FFo(fro)
min
Fo
Hro = F1 (Hto, Hvol
F1
Sum
Hp = F2 (H2z. Hyg
F2
s score By, Layer nodes Hp Layer 1 nodes Byy Layer 2 nodes
message passing
Figure 1: Our HIS framework learns hierarchical symbolic tree which performs interpretable and efficient message aggregation motivated by the graph neural networks (GNNs).
library, e.g., a standard-cell netlist (Brayton & Kamb or k-input lookup tables (Mishchenko al, 2007). Consequently, the post-mapping heuristics like Mfs2 (Mishchenko et al. 2011 are employed further enhance the mapped circuit.
The pruning framework for LO Heuristics Many effective LO heuristics have been developed to tackle the LO task. These heuristics follow the same paradigm as illustrated in Figure A Specif- ically, they apply specific transformations to a subgraph rooted at each node (i.e., the node-level transformations) sequentially for all nodes in an input circuit. These LO heuristies constitute cornerstone of logic optimization, enabling substantial improvements in circuit quality. However, recent work (Wang et al.) has shown that a large number node-level transformations in many LO heuristics ineffective, which makes applying these heuristics highly time-consuming. To address this challenge, several studies (Wang et al.; Li et al. 2023) have proposed pruning framework, which leverages scoring function identify and avoid transformations those ineffective nodes to improve the efficiency of LO heuristics. Within the pruning framework, the accuracy and effi ciency of the scoring function significantly determine the optimization performance and runtime of LO heuristics. Therefore, it is crucial to discover an accurate and efficient scoring function.
Computation Tree of Graph Neural Networks (GNNs). GNNs have been developed solve the LO task. Let G = (V,8) E) denote a circuit graph with node set V and edge set E. For a target node E V. the input to the GNN for LO defined as subgraph centered at u. which can be equivalently represented by its depth-L computation tree T as shown in Figure | Specifically, we set T c, and recursively construct T for T!-1. The GNN encoder takes T as input and performs iterative message passing to learn node embeddings. Formally, the L-th layer of a GNN encoder can be written as:
by expanding T with the neighbors of all leaf nodes in
h = -PDUTAAATEL ACCRRAAATT (hl (1-1)) :u :uE-")=EN(())) EEN())))
AGGGGGATE
is initialized from its feature vector, where (2) denotes the embedding of node at layer L, h (0) and (w)) denotes the set of neighbors of
RELATED WORK
Scoring functions for LO heuristics. variety of approaches have been developed address the LO task, which can be broadly categorized into heuristic and machine learning based methods. Heuristic methods, such as (Li et al. 2023), manually design lightweight scoring functions derived from circuit structure. However, these approaches often fail to capture the rich structural information of subgraphs, resulting in limited optimization performance. In contrast, machine learning methods, such as (Bai al.) and (Wang et al.). employ graph convolutional networks either to generate scoring functions or to directly serve as them. Nevertheless, their high inference cost and limited interpretability significantly hinder their adoption in modern LO tools. These limitations highlight the need for a scoring function that is accurate, interpretable, and computationally efficient.
Graph Symbolic Distillation from GNNs Motivated by the high expressive power but opaque nature of GNNs, prior research has focused on distilling interpretable symbolic functions to ap- proximate their mapping mechanisms. For example, (Cranmer et al. 2020) proposed framework
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that extracts symbolic functions from trained GNNs for scientific discovery. The approach first trains neural network models and then employs a symbolic learning model to approximate both the message-passing and aggregation functions with symbolic representations. However, this method requires extensive process labels to train the symbolic model, which limits its scalability and prac- ticality. More recently, (Kuang al.) proposed end-to-end framework to learn interpretable symbolic policies from a general bipartite graph representation Nevertheless, we observe that this method struggles to effectively capture circuit structural information, often leading to suboptimal performance. To address these limitations, we propose a hierarchical symbolic tree representation that learns structural symbolic functions in an end-to-end fashion without relying on process labels.
4 METHOD
In this section, we provide a comprehensive description of our Hierarchical Circuit Symbolic Dis- covery (HIS) framework. We begin by introducing the hierarchical circuit symbolic tree representa- tion in Section where the structural properties circuits are captured in a symbolic form. Then, present the circuit symbolic generation framework (see Figure 2), which proposes a reinforce- ment learning based approach for discovering the symbolic tree, as detailed in Section 4.2
4.1 THE HIERARCHICAL CIRCUIT SYMBOLIC TREE REPRESENTATION
Motivation To prompt efficient LO, graph neural networks (GNNs) (Wang al.) have been applied as the scoring function to predict and prune the ineffective node-level transformations. While this method achieves high performance on node classification, the complex architecture and extensive parameters significantly restrict its deployment in pure CPU-based industrial scenarios. To address this limitation, we propose to distill the GNN into a symbolic representation for efficient deploy- ment. However, it is challenging to learn a lightweight symbolic function that preserves expressive graph representation capabilities. Motivated by the layered message- message-passing mechanism of GNNs, which integrates structural information from neighboring nodes, we propose the hierarchical circuit symbolic function representation. This representation comprises multi-layer functions that emulate the message-passing process across layers, enabling the resulting symbolic functions capture both local and global graph structural information effectively for node classification.
Graph features and Symbolic library Given circuit subgraph rooted node un follow (Wang et al.) and represent it as an L-layer computation tree T (see more details about the subgraph construction process in Appendix D.4). By traversing all nodes in the circuit graph, we can thus construct a training dataset D = [[T: 11) In our experiments, we set L = 2, which is consistent with the 2-layer GNN configuration adopted in (Wanget To learn a symbolic function from the graph, we first define the graph features and symbolic library. Each node v E TL. is initialized with a 5-dimensional structural feature vector h,, as defined in (Bai et al.). Let V; = (ur n. denote the set of nodes layer i. Then the node features at layer i can be represented as
H v; h
h h
E R
Finally, the graph features are represented as the union of node features across all layers
JF U H.
1=0
where H R. denotes the j-th column of the node feature matrix at layer i. Moreover, con- sidering the symbolic library, we employ (+,-. x, +,,o, exp) as the mathematical operators and 0.1, 0.5) as constants. To aggregate neighborhood information, we follow (Kuang et al.) and employ four unary operators, {min, max, mean, sum}, each mapping features from layer to layer i 1, i.c., g" + R" The aggregation is performed according to edge connectivity, ensuring that only features of adjacent nodes combined. These aggregation operators play the same role as those in GNNs, which can effectively capture the graph structural information. Finally, the symbolic library comprises mathematical operators, aggregation operators, and constants.
Hierarchical Symbolic Tree To represent the hierarchical symbolic functions, we employ a tree- structured representation in which the leaf nodes correspond to features constants, and the internal
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1. Circuit Data Preparation
3. Policy Optimization
target node
Layer 0
data: {Tii=1
Layer
update:
0. += aV)
Layer
0 += aVo,(00)
Circuit Subtree
Computation T'ree
02 += aVo,)(0)
graph features
policy 0 action
min
HD
Hoy
parent
parent sibling
H
Transformer (Layer O, no,)
Transf ormer (Layer 1, No,)
Transformer (Layer To₂))
H
sum
softmax: Hbp
softmax:
softmax: H
H
Generating the symbolic tree layer by layer
Symbolic Tree
2. Learning Hierarchical Symbolic Function
Figure 2: Illustration of the Circuit Symbolic Generation framework. The circuit is first represented as computation tree to provide graph features. Then, hierarchical symbolic function is generated layer by layer using Transformer-basee policies that incorporate both parent and sibling information. Finally, the model parameters are optimized via policy gradient methods.
nodes denote mathematical operators (Kuang et al. 2024, Sun et al., 2023; Petersen et al. 2020). Unlike traditional symbolic functions that take node features as input, our circuit symbolic tree directly operates on the circuit computation tree to aggregate the structural information for node classification. Specifically, given an L-layer computation tree T% rooted at node vo. the hicrarchical symbolic tree is organized into L layers (see Figure I. For each node at layer of the computation tree, the learned function F, aggregates messages from its neighboring nodes to update its feature representation. In general, the aggregation function in layer can be expressed
score = (H...)::
i = 0,
Hv... = =
(H,, Hy..),
H
if i 0,
where Hy.., Roi-1xd denotes the updated node feature matrix at layer i- 1, and F; represents d aggregation functions that update the features of layer nodes based on their current features and the features of nodes in layer 1. The parameter d, which denotes the dimensionality of the updated feature vectors, set to 10 in our experiments. By combining the learned symbolic functions F,, construct hierarchical symbolic tree. This symbolic tree captures the structural information of the circuit through layer-wise aggregation while retaining the efficiency of symbolic operations, which is deployable in industrial settings.
4.2 THE CIRCUIT SYMBOLIC GENERATION FRAMEWORK
Symbolic Sequence Formulation In this section, provide detailed explanation of the learning process for symbolic trees at each hierarchical layer. Previous works usually employ a pre-order traversal sequence 7 {T1, 72 - to represent the symbolic tree. Therefore, the task of gener- ating symbolic trees can be formulated as a sequence generation task. At each generation step, we output categorical distribution over all possible tokens to sample the current token т; Finally, we can generate a symbolic sequence r with the probability given by
(T( = Po m TT-1);
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where po(r) is the probability of generating the sequence T, 0 is the generation model parameter, and TI. Ti-1) is the conditional probability of generating token т; at i-th step.
Transformer Model for Symbolic Generation To generate the hierarchical symbolie tree, de- sign L encoder-only Transformer models, each model Te, responsible for generating the symbolic functions at layer i. At each generation step k. the layer i generation model takes the previously sampled token sequence as input and predicts the next token T.. However, a standard Transformer is limited in capturing the tree-structural dependencies of symbolic expressions, which often leads to suboptimal results (Holt et al. 2023] Petersen et al. 2020). To overcome this limitation, we design tree-aware embedding aggregation mechanism inspired by (Kuang al.). Specifically, during the generation period of token Tie we first identify its parent and sibling tokens, denoted as Tps and 8., respectively. After pass-
The and then encode them Parent(r).) ) = 3, and Sibling(r).) ing through several encoder layers- each consisting of multi-head attention and a feed-forward network- we compute the representation of T/. by averaging the embedding vectors of T/ and Taa We then apply softmax function to this representation obtain the probability distribution po, (Tf : - which used to generate the token TŞ at step k.
Training Model via Reinforcement Learning Since the symbolic tree is not differentiable with respect to the model parameters reinforcement learning problem. Specifically, network, treat the sampled tokens as states, and consider each generated token as an action. Further- more, we regard complete sequence of tokens signal that is computed only upon the completion of the expression. In each episode, we sample group of symbolic expressions and use them optimize the policy parameters via Proximal Policy Optimization (PPO). Specifically, we define the objective function as
(0g, , we formulate the sequence generation as a
formulate the transformer models as the policy
episode, and define the reward as a terminal
(T( Pê (T) Ao,s (T), clip
po (o(T) po.u (T) -1-,, 11,,1+))) Ae Abo(())
J(0) E (0)) min
where + = -r), ................................ 7 denotes the hierarchical symbolic tree obtained by sequentially merging
the generated symbolic trees 7¹ from each layer, (T = Po, Po. (r*) denotes the probability of generating the hierarchical symbolic tree under the policy parameters 0, Ag... (T) is the advantage function, and is the clipping threshold that constrains the policy update. Unlike traditional PPO, which requires training resource-intensiv critic network for advantage prediction, we compute the advantage as the sequence reward relative to the group mean reward, achieving both lower resource consumption and more stable training. The advantage is defined as
r(T)-
Ao(T)
O
where F [ [r(T) and o,
E p
r)2 denote the mean and standard (F(())
deviation of rewards the generated function groups. Given a symbolic tree T and the training data
D [[T,, ,)); the reward is computed using the focal loss (Lin et al. 2017). defined as
r(r) = Σ o0 - 0;)"" log(ū:) + (1 - a1(( - y:) log(1 - 0:)
where 0 = TTT,) o;) is the predicted score, a is a balancing factor. The detailed training algorithm
illustrated in Algorithm| T Overall, this reinforcement learning framework allows model to efficiently discover high-quality symbolic expressions.
5 EXPERIMENT
In this section, we conduct extensive experiments to evaluate HIS, which consist of four main parts: Experiment 1. Demonstrate the superior performance of our HIS in terms of node classification ac- curacy and heuristics efficiency. Experiment 2. Demonstrate that our method can not only enhance the efficiency but also improve the Quality of Results (QoR) of one of the most time-consuming LO heuristics, Mfs2. Experiment 3. Perform ablation experiments to provide further insight into HIS. Experiment 4. Show the appealing features of HIS in inference efficiency and interpretabillity

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Published as a conference paper at ICLR 2026
Benchmarks We evaluate HIS on two widely used public benchmarks, EPFL (Amarú et al. 2015) and IWLS (Albrecht) 2005). The EPFL benchmark comprises 20 circuits, including large-scale cases with up to 214.335 nodes. The IWLS benchmark contains 21 circuits, including challenging cases with up to 1,130 inputs and 1 1,416 outputs. We defer more benchmark details to Appendix C.
The results show that HIS consistently outperforms all graph-based and node-based base- lines in terms of generalization top 50% prediction recall.
Table I:
Circuits
Hyp
Square
Multiplier
DesPerf
Ethernet
Conmax
Method
Recallf
Recall
Recallf
Recall
Recallf
Recallf
COG
0.87
0.81
0.82
0.81
0.55
0.75
CMO
0.79
0.94
0.87
0.79
0.59
0.73
Effisyn
0.18
0.04
0.13
0.28
0.88
0.05
Random
0.50
0.48
0.44
0.50
0.47
0.50
HIS (Ours)
0.82
0.94
0.94
0.83
0.99
0.75
Online Evaluation on Six Challenging Circuits
0.8
Normalias alized Runtime
0.7
0.6
0.5
0.4
0.3
0.2
HIS-Mfs2 (Ours)
Effisyn-Mfs2
COG-Mfs2
0.1
CMO-Mfs2
Random-MFi
0.0
Hyp
Multiplier
Square
DesPerf
Ethernet
Conmax
Figure 3: We compare our HIS with four competitive baselines online runtime. The results demonstrate that our approach achieves significant runtime improvement with the baselines.
Experimental setup Throughout all experiments, we use ABC (Brayton et al. 2010) as the backend LO framework. ABC is state-of-the-ar open-source LO framework and widely used research machine learning for LO. Morcover, choose the Mfs2 (Mishchenko et al. 2011 one of the most cinnuinn LO heuristics as the backend heuristic. Experiments are performed on single machine that contains 32 Intel XeonR E5-2667 v4 CPUs, which closely resembles real- world industrial deployment environment. More details are provided in Appendix [D]]]
Evaluation Metrics and Evaluated Methods Throughout all experiments, evaluate method in two separate phases, i.e., the offline and online phases. In the offfine phase, we focus on evaluat- ing the prediction recall of effective nodes. The evaluation setup detailed two parts follows: (1) Evaluation metrics Under the pruning framework (see Figure 4 we formulate the prediction task as node scoring problem, where nodes with the top l scores are predicted to be positive. Based on this formulation, we define the top k accuracy metric, which measures the fraction of true positive nodes among those predicted as positive, i.e., prediction recall. As shown Appendix B.I. higher prediction recall consistently leads to improved QoR. Therefore, achieving high recall essential for obtaining QoR comparable to the default heuristics. Further details of this metric
are provided in Appendix D.1.2 (2) Evaluated methods We compare five main approaches: COG Wang et al.). CMO (Bai et a.)) Effisyn (Li et al. 2023). Random and our proposed HIS. COG is
carefully designed 2-layer GNN. CMO is graph-enhanced symbolic learning method. Effisyn a -dsigned nonlinear function with parameters derived from circuit features. Random is heuristic method which randomly predicts the score between 0 and Implementation details of

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Published as a conference paper at ICLR 2026
We compare the Default Mfs2 heuristic with our HIS-MIs2 heuristic with the hyperparam- eter k set as 30%, 40% and 50% on six challenging circuits. Optimized Nd denotes the node number (size) of circuits, and Lev denotes the level (depth) of circuits. We define an Improvement metric by M (D (Our)) where (.) denotes the Optimized Nd, Lev, or Time.
Table 2:
M(Default)
Hyp
Square
Lev 4
Impeovement ? (Lev, %%)
Time (8)
Improvement (Time, %))
Optimized Nd
(Optimized Nd. %)
Improvement
Time (4)
Improvement (Time, %))
DefauhiM6s2)
8259.00
NA
265, ,3
NA
5701.00
NA
21.48
NA
HIS MG-2 (0.5, Ours)
8259,00
0.00
85,46
67.86
5703.00
-0.01
10.69
50.24
2H15 Ours)
S762.
147.62
49
5553,
2.60
16.21
2HIS-M (0 Ours)
5762.00
30.23
192.51
27.61
5542.00
2.79
19.97
7.03
Muttiplier
DesPerf
Method
Optimized Nd 4
(Opiiizzed Ná %%
Imprevement 1
Time (6) L
Improvement (Time, %
Optimized Nd
Improvement (Optimiiedd NJ. %)
Time (6)
Improvement
NA (Time, ()
Defaul((Mss2)
7799.00
NA
16.91
NA
30853.00
NA
28,8
HIS-MI52 (0.5, Ours)
7799.00
20.03
31035.00
2H1S-M62 (0.3, Ours)
7661.00
1.27 L.00
16.48
2.50
30104.00
2,43
24.88
13,65
FHIS-MIS2 (0.4. Ours)
7659.00
20,60
-21.83
29493.00
4.41
31,71
-10.03
Ethernet
Commax
Method
Optimized Ná 4
(Oqiimized Nd %t)
Improvement T
Time (6) L
Improvement (Time, %)
Optimized Nd.
Improvement (Optimized Nd. 53)
Time (s)
Improvemeni
(Time, 5)
Defaul(MMss)
13638.00
01.00
NA
16519.00
NA
19.93
(0.5, Ourr)
13639.00
51.16
16760.00
-1.52
13.63
31.59
2HIS-MIS (0.3, Ours)
13511.00
0.93
14.84
45.06
15890.00
3.75
13.33
33.09
2HIS-MIs2 (0.4, Qurs)
13509.00
0.95
19.36
2X.31
15782.00
4.40
16.77
15.87
these baselines are deferred to Appendix D.2 In the Online phase, we evaluate both the efficiency and QoR of HIS. The evaluation setup is as follows: (1) Evaluation metrics For efficiency, we measure the runtime of the heuristics. For QuR, we primarily consider the number of optimized circuit nodes, as this directly influences the final chip area. In addition, we evaluate the circuit depth (i.e., level) of the optimized circuits, which serves methods We introduce a new heuristic, X-Mfs2, which incorporates a learned scoring function "X" into the default Mfs2 heuristic. In our experiments, "X" corresponds the baselines and our HIS.
proxy metric for chip delay. (2) Evaluated
Generalization Evaluation Strategy In practical industrial settings, it is desirable for the trained model generalize effectively unseen circuits. To evaluate this capability, we design two gener- alization strategies. In the first setting, we use the IWLS circuits as the training dataset and select three tord-to-optimize circuits- Hyp. Multiplier, and Square from the EPFL benchmark as test cases. In the second setting, we reverse the roles by training on the EPFL. circuits and testing on three challenging
PesPef, Ethernet, and Conmax- ffrom the IWLS benchmark. Due to limited space, we provide more details about our designed generalization strategy in Appendix C.2
Experiment 1. Comparative Evaluation In this subsection, we compare the offline and online met- rics of our HIS framework with the baselines. Following the established generalization strategy, we conduct experiments on six challenging circuits from two widely used open-source benchmarks. In the offline phase, adopt the top 50% accuracy as the evaluation metric. Results in Table [ show that HIS consistently outperforms all baselines in terms of the prediction recalls, highlighting the superior generalization ability of our method. Moreover, HIS achieves a prediction recall exceeding 80% on the majority of test circuits, indicating that it can preserve most of the effective transforma- tions. In the online phase, we primarily focus on evaluating the efficiency of the X-Mis2 heuristics. To ensure fair comparison for efficiency, we compare the runtime of different methods when they achieve similar optimization performance. As larger top k accuracy improves the final performance, we employ top 50% for our HIS, top 60% for COG and CMO, and higher k for the Effisyn and Random baselines to achieve comparable optimization performance (see Table 7 in Appendix [B.2 for the optimization results). Specifically, the results in Figure 3 indicate that our M1S- achieves an average improvement of 11.96%, 21. 21.82% 19.24%, and 22.91 % over CMO-Mfs2, EffisynMMf22, Random-Mís2. and COG-Mfs2 in terms of the runtime, respectively. Overall, the offline and on- line results show that our HIS can not only accurately predict the effective transformations but also outperform all competitive baselines in terms of heuristic efficiency.
Experiment 2. Improving Efficiency and QoR of the LO heuristic In this subsection. we conduct experiments six challenging circuits to demonstrate that method not only reduces runtime but also improves QoR, measured by the size and level of the optimized circuits. These two metrics are critical in chip design, they serve as proxies for the final chip area and delay. We first show that
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Table 3: The ablation results demonstrate that each component contributes significantly to the overall performance of HIS. Removing any individual module leads to noticeable performance degradation, indicating that the effectiveness relies on the complementary design.
Circuits
Hyp
Multiplier
Square
DesPerf
Ethernet
Conmax
Method
Recallf
Recallt
Recallt
Recallf
Recallf
Recallt
HIS (Ours)
0.82
0.94
0.94
0.83
0.99
0.75
w/o hicrarchical
0.81
0.91
0.74
0.77
0.81
0.72
w/o group optimization
0.88
0.89
0.90
0,51
0.87
0.74
w/o tree-structured aggregation
0.81
0.51
0.94
0.79
0.91
0.75
HIS can enhance the efficiency of the Mfs2 heuristic while maintaining comparable optimization performance. Results in Table 2 demonstrate that our HIS with top 50% accuracy achieves an aver- age runtime reduction of 40.27% with only a marginal 0.38% degradation in eircuit size and level across the six test circuits. In particular, HIS attains up to 3.1 x faster runtime on the Hyp circuit. Building on this efficiency advantage, we explore applying HIS-Mfs2 sequentially rather than once (denoted as 2HIS-Mfss) to further improve QoR. Since HIS-M HI'2 runs significantly faster than the default Mfs2 heuristic, this repeated application is computationally feasible. To accelcrate runtime, we additionally consider smaller hyperparameter settings, using k 30% and 40% instead of 50%. When prioritizing optimization performance in real-world scenarios, we can set = 40%. Table shows that 2HIS-MfSS with & = 40% achieves an average reduction of 7.43% in size and depth while also reducing runtime by 7.82% on the test circuits. When prioritizing runtime in real- world scenar- ios, results in Table 2 show that 2HIS- with k 30% achieves average reduction of 6.95% in size and depth, along with a runtime reduction of 27 17.22%. Overall, these results demonstrate that the proposed HIS-MIs2 framework can simultaneously deliver faster runtime and improved QoR, highlighting its potential to yield significant economic benefits in practical chip design.
Experiment 3. Ablation Study In this subsection, we perform an ablation experiment to evaluate the individual contribution of each component in HIS. Specifically, the results in Table indicate three key findings as follows. (1) The 'w/o hierarchical' variant, which learns complete symbolic tree from the training data end to end rather than layer by layer, led to significant degradation in the prediction recall. This highlights that our proposed hierarchical symbolic function representa- tion can effectively capture circuit structural information for node classification; (2) The 'w/o group optimization" variant, which employs the single symbolic function's ' reward rather than the group rewards the advantage, exhibits a noticeable reduction in prediction recall across the majority of circuits. This demonstrates the effectiveness of the group advantage in improving symbolic expres- siveness; (3) The 'w/o tree-structured aggregation' variant, which omits the aggregation of parent and sibling embeddings during token generation, exhibits a substantial decline in prediction recall. This result highlights the necessity and effectiveness of our proposed approach in capturing tree- structured information for high high-perffrmance symbolic trees generation.
Experiment 4. Strengths for Deployment In this subsection, we conduct extensive experiments to demonstrate the appealing features of our HIS on inference efficiency and interpretability. Specifi- cally, we present detailed analysis as follows.
Inference Efficiency
We compare the inference time of our HIS against both the SOTA graph-based based method COG and several lightweight baselines under a pure CPU industrial environment. As shown in Table 5 in Appendix B.3 HIS achieves an average inference speedup of 296x over COG on the EPFL circuits and 254x on the IWLS circuits, while maintaining inference times comparable to other lightweight methods. These results demonstrate that HIS successfully learns a lightweight graph symbolic scoring function that achieves both high prediction recall (see Table T and efficient inference, making it well-suitable for deployment in real industrial scenarios.
Interpretability We visualize the discovered hicrarchical symbolic functions for EPFL and IWLS benchmarks in Table 6 and Figure 55) in the Appendix. Owing to the high interpretability of the symbolic functions, these learned symbolic policies allow researchers to gain deeper insight into the patterns extracted from circuit graphs and trace how information is aggregated. Specifically, we observe that: (1) All the discovered expressions aggregate information from both the root node and the candidate node, which is consistent with the design in previous GNN-based approaches. (2) The hierarchical symbolic tree structure successfully performs an efficient message-passing across layers, wherein the node features in Layer i 1 are updated through aggregation from Layer i.

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6 CONCLUSION
To enable efficient Logic Optimization (LOO, previous machine learning methods propose to use scoring functions predict and prune ineffective nodes LO heuristics. However, the high in- ference cost and limited interpretability of these approaches severely limit their wide application to modern LO tools. To address this, we propose HIS, novel Hierarchical Circuit Symbolic discovery Framework that learns efficient, interpretable, and tegh--erffrmacce symbolic functions from the circuit graph. Extensive experiments on two widely used benchmarks show that the learned graph symbolic functions outperform previous state-of-the-arr approaches in terms of efficiency and op- timization performance. Moreover, HIS significantly enhances both the Mfs2 heuristic's 's efficiency and optimization performance CPU-based machine, achieving average runtime improvement of 27 .2% and a 6.95% reduction in circuit size.
ETHICS STATEMENT
This research does not involve any personally identifiable information. All datasets used are pub- licly available and widely adopted in the community, and we have verified that their licenses per- mit research use. In accordance with the ICLR Code of Ethies /ettps://iclr.ce//
CodeOfEthi hiccs,, hic,), we ensure that our work adheres principles of fairness, transparency, and re- sponsible Al research. We also disclose that LLMs were used for text polishing, while all conceptual contributions and validation remain the responsibility of the authors in Appendix
REPRODUCIBILITY STATEMENT
We will provide open access to all source code, configuration files, and preprocessing scripts, to- gether with detailed instructions to reproduce the main experimental results. All datasets employed are publicly available, and we specify the exact versions and preprocessing steps. We report all hyperparameters, model versions, and API parameters in full, and we describe the computational environment (hardware type, GPU model, and software dependencies) in the supplemental mate- rial. We also include ablation studies and negative results to ensure transparency. Collectively, these resources and specifications enable reliable and faithful reproduction of our results.
ACKNOWLEDGGENTT
This work was supported in part by National Key R&D Program of China under contract 2022ZD01 19801, National Nature Science Foundations of China grants U23A20388 and 62021001 This work was supported in part by Huawei as well. We would like to thank all the anonymous re- viewers for their insightful comments.
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Start
Default LO heuristic
Prune Framework
Input: Original Circuit
Node features extraction
Collect all nodes
Scoring function
Extract node id set
Full node id set
Effective node id set N
N[O]
Optimization For Loop
|N|?
++=1 1
N
N
Y
Gain 0?
Trans node Nji]
Y
Update circuit
Output: Optimized Circuit
End
Figure 4: An illustration of the pruning framework for LOO heuristics. The scoring function aims to predict and prune the ineffective node-level transformations prompt efficient LO.
Yilong Xu, Yang Liu, and Hao Sun. Reinforcement symbolic regression machine. In The Twelfth International Conference on Learning Representations, 2024. URL [tL/htttp:://operevveee Ftte//oornn111==2VV0
A MORE DETAILS OF THE BACKGROUND AND RELATED WORK
Logic Optimization heuristics To tackle the LO task, many researchers have developed rich set of LO heuristics. For instance, researchers have developed Rewrite (Bertacco et al.. 1997) and Resub (Brayton| 2006) for pre-mapping optimization, while Mfs2 (Mishchenko et al. 2011) is designed for post-mapping optimization. These LO heuristics follow the paradigm as shown in Figure 4 Specifically, these heuristics traverse the Boolean network in a topological order from Pls to POs and apply transformations to subgraphs rooted at each node sequentially for all nodes. However, previous literature found that these heuristics can be highly time-consuming due large number of ineffective transformations. To address this problem, we follow the new heuristics paradigm proposed by (Wang al.) that can significantly improve the efficiency of LO heuristies by learning a classifier to predict nodes with ineffective transformations and avoid applying transformations on these nodes.
Circuit Representation In the LO stage, circuit is usually modeled by a directed acyclic graph (DAG), where nodes correspond Boolean functions and directed edges correspond to wires con- necting these functions. A Boolean function takes the form f: B - B, where B = {0, 1) denotes the Boolean domain. Given a node, its fanins are nodes connected by incoming edges of this node, and its fanouts nodes connected by outgoing edges of this node. The primary inputs (PIs) are nodes with no fanin, and the primary outputs (POs) are nodes with no fanout. The size of a circuit denotes the number of nodes in the DAG. The depth (level) of circuit denotes the maximal length of a path from a Pl to a PO in the DAG. The size and depth circuit are proxy metrics for the area and delay of the circuit, respectively.
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Deep Symbolic Discovery Several recent approaches utilize deep learning for symbolic discovery. These methods generally fall into two categories: pre-trained and search- based. The pre-trained symbolic regression methods have shown advantages in fast inference and have successfully discov- ered large input (with up to twelve) symbolic functions (d' Ad'Asc et al.) 2023 Biggio et al., [021] Kamienny et al.] 2022). However, these methods are limited by high training costs and data gen- cralization challenges. The search-based approach explores the discrete symbolic operator space to identify functions that maximize the fitness with respect to the given dataset. Mainstream symbolic regression frameworks based on this paradigm typically employ sequence prediction models, such as Transformers (Kuang et al.) |Holt et al. (023) and RNNs (Petersen al. (2020), or leverage Monte Carlo tree search (Sun et al.) 2023] Xu et al. 2024). These methods have achieved state-of-the-art performance across multiple benchmarks.
B ADDITIONAL RESULTS
B.1 THE IMPORTANCE OF THE PREDICTION RECALL ON OPTIMIZATION PERFORMANCE
In this subsection, we explore how prediction recalls of effective nodes influence the optimization performance of heuristics. To do this, assess the performance of the Random method with dif- ferent values of the hyperparameter k, which denotes the percent of nodes to apply transformations. Note that Random is baseline that randomly assigns score between [0, 1] for each node. The recall and optimization outcomes (i.e., And Reduction) of Random for various values
are sum- marized in Table 8 The results reveal a near-linearly positive relationship between the value of and the recall, with similar trend observed between the recall and the optimization performance as well. Therefore, to maintain the optimization performance of heuristics, is essential for our model to maximize prediction recall.
B.2 MORE RESULTS FOR COMPARATIVE EVALUATION
In this subsection, we provide further insights into the efficiency of our HIS compared to several baselines, including COG-Mfs2, CMO-Mfs2, Effisyn-Mfs2, and Random-Mis2. To ensure a fair comparison, we select higher hyperparameter values for & in the baselines, which are necessary to achieve comparable online optimization performance. While higher values of k: improve optimiza- tion performance, they also increase time costs, so this parameter is adjusted differently for each use & 60% for COG and CMO across most circuits, and higher values
circuit. Specifically, of k for Effisyn and Random, based on the specific circuit. The results and details are shown in Table Additionally, when compared to COG-Mfs2 and CMO-Mfs2, our HIS achieves average runtime improvements of 22. 91% and 11. 96%, respectively, while maintaining or even improving the optimization performance across most circuits. Moreover, when compared to Random-Mfs2 and Effisyn-Mis,, with & values not lower than 70%, our HIS demonstrates average improvements of 19.24% and 21.82%.
B.3 MORE RESULTS FOR INFERENCE EFFICIENCY
In this subsection, we present further details on the inference efficiency of our HIS, compared to COG, CMO, and Effisyn. Note that our HIS and COG both rely on graph inputs, which enhance optimization performance but result in lower inference efficiency. As shown in Table 3 our HIS achieves an average inference speedup of 296 x on the EPFL circuits and 254x on IWLS circuits. These results reveal that HIS successfully learns a lightweight graph-based symbolic scoring func- tion, delivering both high prediction recall and efficient inference. This makes HIS well-suited for deployment in real-world industrial applications. Although CMO and Effisyn show higher inference efficiencies than HIS, their actual runtimes are comparable.
C DETAILS OF DATASETS USED IN THIS PAPER
C.I DESCRIPTION OF TWO WIDELY USED BENCHMARKS
We provide detailed statistics the circuits from two open source benchmarks EPFL and IWLS in Tables 9 and TO respectively. These benchmarks contain 41 circuits in total. In general, nodes
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denote logic gates and edges represent the wires connecting them. The fanins refer the nodes that provide imputs to it, while its famouts are the nodes it drives. Primary inputs (PIs) are nodes without fanins, and primary outputs (POs) are subset of the network's 's nodes. Latches are specialized nodes found in sequential circuits, and cubes denote specific subsets of input variables. Lev refers to the depth of the circuit, measured by the maximum number of edges between Pls and POs.
C.2 DATASETS FOR EVALUATION ON SOUNCE BENCHMARKS
For each circuit and a given X heuristic, we generate the circuit dataset by applying the X heuristic optimize the circuit, then collecting the graph features {G.) y and labels h We observe that a few circuits contain no effective nodes, and we exclude these from our analysis since no transformations need be applied to them, thus negating the need for model training.
In particular, employing the generalizable evaluation strategy with the EPFL benchmark, we con- struct three datasets for evaluation. One of the three circuit catasets-cooleette from Hyp, Mul- tiplier, and Square- -erves as the testing dataset, while the circuits from the IWLS are used for training. Similarly, using the generalization strategy with the IWLS benchmark, we create three datasets, selecting one of these circuit datasets from DesPerf, Ethernet, and Conmax the testing dataset and using the EPFL circuits for training.
D DETAILS OF METHODS AND EXPERIMENTAL SETTINGS
D.1 DETAILS OF EXPERIMENTAL SETUP
D.1.1 OPTIMIZATION SEQUENCE FLOWS
Optimization Sequence Flows for Data Collection and Evaluation In industrial practice, a se- quence of Logic Optimization (LO) heuristics is typically applied to optimize input eircuit. We adopt the same setting throughout all experiments unless stated otherwise. Specifically, for the Mfs2 heuristic, we use the sequence strash; dch; -C 12; mfs2 -W 4 -M 5000 collect graph data and evaluate both the Default Mfs2 heuristic and our proposed HIS. Note that the optimization sequence flow is standard academic flow for evaluating the Default Mfs2 heuristic, which follows previous work (Mishchenko et al. 2011 Li et al. 2023 Wang et al.).
Optimization Sequence Flows for Evaluating MHIS- To apply our HIS twice, we adopt the heuristic sequence strash; dch; if -C 12; mfs2 -W 4 -M 5000; strash; if -C 12; mfs2 -W 4 -M 5000 for evaluating the performance of 2HIS. The Mfs2 heuristic is post-mapping optimization technique that operates on k-input look-up table graph (K-LUT). Specifically, the strash heuristic (Rai et al. (202I) converts the circuit into an And-Inverter Graph (AIG) using one-level structural hashing, while the if heuristic (Mishchenko et al. (007)) maps the AIG into K-LUTs. Finally, the Mfs2 heuristic performs optimization on the resulting K-LUTs twice.
D.1.2 TOP K ACCURACY METRIC
common challenge in many LO heuristics is the ineffective node-level transformations problem, where the number of ineffective nodes substantially exceeds the number of effective ones. This im- balance introduces a significant distribution shift in the training dataset, making the normal threshold of 0.5 unsuitable for determining whether a sample is positive. To mitigate this issue, we adopt the approach proposed in (Wang et al.), which reformulates the classification task as a ranking problem. Specifically, all nodes are ranked according to the prediction scores assigned by the learned sym- bolic functions, and the top-k nodes are selected as positives while the remainder are classified as negatives. The evaluation metric, referred to top-k accuracy, is defined as the proportion of true positive nodes in the top-k predictions that are correctly identified, i.c., recall.
D.2 IMPLEMENTATION DETAILS OF THE BASELINES
In this part, we present detailed description of all the baselines used in this paper.
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COG. COG is well-designed 2-layer graph convolutional neural network that achieve high optimization performance (Wang et al.). Specifically, it constructs a bipartite graph as input and learns domain Nomain-invariant representation to achieve high generalization capability.
CMO. CMO is a novel graph-enhanced symbolic discovery framework (Bai et al.). Specifically, employs Monte Carlo method explore the symbolic function space, while leveraging a well- designed GNN as a teacher model to guide the search process. This approach achieves state-of-the- art performance among lightweight scoring function methods.
Effisyn. Effisyn is a human-designed nonlinear symbolic function (Li et al. 2023). Specifically, in human-designed symbolic scoring functions, experts manually design the structure of the function and extract key parameters from training circuit data to form a complete symbolic scoring function. This process involves identifying relevant characteristics of the circuit and carefully selecting or engineering the symbolic terms that best capture the underlying behavior of the system. However, designing and developing these functions is extremely challenging it requires extensive expert knowledge and manual tuning.
Random. Random baseline that randomly predicts a score between [0, 1] for each node, and selects the top k nodes positive samples to apply node-level transformations.
D.3 IMPLEMENTATION DETAILS OF THE TRAINING DETAILS
In this subsection, we provide further details of the training process. The overall procedure of our algorithm is illustrated in Algorithm T and the corresponding parameter settings summarized in Table 4 covering model, reinforcement learning, and symbolic tree configurations. Moreover, we adopt Best-of-N (BON) strategy during training. Specifically, the top-N expressions with the highest training rewards are selected to construct an ensemble model. Owing to the lightweight nature the symbolic functions learned by HIS, the additional computational overhead is negligible, while yielding substantial performance improvements. In our experiments, we set N 4.
D.4 IMPLEMENTATION DETAILS OF THE CIRCUIT SUBGRAPH CONSTRUCTION
In this subsection, we describe the procedure for constructing circuit subgraphs and modeling them computation trees. Following (Wang al.),, a subgraph in LS heuristics is constructed by select- ing a root node along with a limited set of its neighboring nodes. To enable more effective node embedding alignment,
first transform the subgraph into bipartite graph, where the root node and the non-root nodes are treated as two distinct types of nodes. This bipartite graph is then con- verted into two-layer computation tree: the root node corresponds the O-th and 2-th layers, while all candidate nodes in the subgraph are placed in the 1-th layer.
E THE USE OF LARGE LANGUAGE MODEL
In accordance with the ICLR 2026 policy, we disclose the use of Large Language Models (LLMs) as an assistive tool in preparing this manuscript. The primary role of LLMSs was to support improve- ments in writing clarity and presentation quality.
Specifically, LLMs were used for the following purposes:
Grammar and Spelling Correction: Detecting and correcting grammatical emror and
typographical mistakes.
Clarity and Readability: Rephrasing sentences and suggesting alternative formulations to enhance readability and flow.
Conciseness: Streamlining sentences and paragraphs to make the writing more direct and succinet.
All scientific contributions, analyses, and claims in this paper are solely the work of the human authors. The use of LLMS was limited to language refinement and carried out responsibly in accor- dance with academic and ethical standards.
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Hierarchical Symbolic Tree for IWLS
Hierarchical Symbolic Tree for EPF
H
1
Vo
H23
+
+
H 2
0.1
+
H
v0
H
mean
min
0.2
mean
H Vo
X
H
H
X
H
H
Layer 0
Layer
Layer 2
Figure 5: Visualization of the hierarchical symbolic functions for EPFL and IWLS benchmarks.
Algorithm Circuit Symbolic Generation Framework
Input:
Transformer model pe. symbolic library L, dataset D {(T/, w:)) number of gener- ated expressions m, number of layers L
Output: Updated parameter O. for i = to training epoch do
Initialize empty list of hierarchical symbolic trees for 1 to m do Initialize empty sequence 7 for = 0 down to L do
while sequence not completed do Sample token: T/. po, (T 7f-1)
Apply constraints r/. end while end for
Merge L sequences {= frijzonnto into a hierarchical symbolic tree if t contains updated feature tokens then
Substitute feature tokens with corresponding sequences end if
Add the list of generated trees
end for
Compute rewards for each tree
((T)
ooy (1 log()) + (1 (1-1)((1 - v:)0? log(1 b1))
Update model parameters using PPO objective:
(T( Powa (T) Anae (T), clip po(
1 e, 1 1.1+) Abu(tt)
J(0) E7--pp(0) (0)
min
Paw. (T)
end for
17

---

Published as a conference paper at ICLR 2026
Table 4: We provide comprehensive implementation details, including the arguments for training, the Transformer model, and RL algorithms, along with subset of the tokens library.
Parameter
Value
Train Kwargs
number of expressions generated each epoch data_batch_sin
512
10240
number of expressions for RL training
96
number of expressions for recording training epoch
16
2000
Transformer K Kwargs
Transformer mengte of each layer Transformer max_length of each layer Transformer embedding dimension Transformer attention heads Transformer feedforward model dimension Transformer number of layers
[4, 4, 4]
[48, 16,
32
4
128
4
RL Kwargs
PPO learning rate PPO epochs at each iteration PPO clipping threshold
5e-5
10
0.2
Symbolic Tree Kwargs
Constant operators
[0.1, 0.2, 0.5] {+, - x, x, l,g exp) {min, max, mean, sum)
Math operators
aggregation operators
18

---

Published as a conference paper at ICLR 2026
Table 5: The model inference results show that our HIS is extremely efficient for inference compared the SOTA graph-based approach (COG) when executed CPU-based 1.O tools.
Benchmurk
Hop
Square
Multipier
Avcruae
larpeonetenni
CDG
3,63]
NA
6.418
NA
0.865
NA
2,304
NA
CMO
0.003
2007
0.001
7el
0,001
1050
0.001
1313
Ertignn
0
1226
0.001
760
B000
1087
0.002
1025
(Oum)
0.009
0.000
[W1.8 Benchmark
DoPPor
Fihemel
Conmes
Asuraag
Medhod
Inproveneci
COG
2,507
NA
1,050
NA
1.385
NA
1.648
NA
CMO
0.002
1995
0.000
2501
0.001
1370
0.001
1823
Ediism
0.003
907
0.001
1304
0.001
961
0.002
1057
HIS (Oum)
0.007
942
0.009
197
0100
0.065
Table 6: The discovered hierarchical symbolic functions for the IWLS and EPFL benchmarks.
IWIS
layert)
Final colput
Exprescion
M/L (0.1 (M) (2.0)
Updoted
x12,
Irg, XFL
fft,
172.
layer1
Expression
14.
saww/0.1 (
mox 1ff))
mox(Af), 12,))
(eto Aff))
layer2
Uplated Feature
68.
#2, A93
Expression
44,
moan (3t
mo 12
EPPL
layert)
Final cuiput
Expression
(cre, 0.2) 1P 1f
Uplated Feuture
162.
182.
442
A/e
117
AP2 min(A))
layer1
Expression
112,
mén(Aff 0.5)
méniAA), AF2))
max( Lif, 1f2))
minnf..
Uplated Feature
AFA
layer2
Eapecscio
monel
Mt.)
(M),
min(O1) Nt
m2n(0.2 M2.
HG,)
Table 7: We compare HIS with four competitive baselines. The results demonstrate that ap- proach consistently outperforms all baselines in terms of online heuristics efficiency and optimiza- tion performance. And Reduction (AR) denotes the reduced number of nodes, i.e., optimization performance. Normalized AR denotes the ratio of the AR to that of the default heuristic.
Hyp
Square
Mathod
And Reducrion(AR))
Normalized AR
Times(s)
Method
And (AdinctionAR)
Normalized AR
Times(s)
0.66
0.75
14.70
CMO
142
0.21
129.56
CMO
0.75
13.60
Random
563
0.85
238.22
Random
0.38
15.62
Effisyn
498
HIS (Ours)
566
0.85
85.46
HIS (Gurs)
0.75
10.69
Multiplier
Mathod
And Reducrion(AR) Normalized AR
Times(s)
Method
And Redhction(AA))
Normalized AR
Times(s)
0.65
CMO
22
1.00
15.08
CMO
900
0.81
22.82
Random
18
0.82
14.99
Random
906
0.81
23.30
Effisyn
HIS (Ours)
22
1.00
13.52
HIS (Gurs)
936
0.84
22.84
Ethernet
Commax
Mathod
And Reducrion(AR)
Normalized AR
Times(s)
Method
And Rednction(AA) Normalized AR
Times(s)
16.66
CMO
2
0.05
20.88
CMO
730
0.93
14.43
Random
19
0.50
19.04
Random
579
0.74
14.25
Effisyn
HIS (Gurs)
37
0.97
13.19
HIS (Gurs)
647
0.83
13.63
19

---

Published as a conference paper at ICLR 2026
Table 8: We report the recall and optimization performance of the Mfs2 heuristic incorporated with Random models. Percent denotes the hyperparameter i.e., the percent nodes to apply transfor- mations. And Reduction denotes the reduced number of nodes, i.e. optimization performance.
Hyp
Multiplier
Percent
Recall
And Reduction(AR)
Percent
Recall
And Reduction(AR)
0.10
0.11
33.33
0.10
0.10
3.00
0.20
0.20
69.00
0.20
0.18
5.33
0.30
0.30
111.33
0.30
0.28
6.67
0.40
0.40
164.67
0.40
0.39
9.33
0.50
0.50
225.33
0.50
0.44
10.00
0.60
0.60
295.00
0.60
0.56
12.33
0.70
0.70
374.33
0.70
0.67
14.00
0.80
0.80
464.33
0.80
0.78
16.67
0.90
0.90
561.33
0.90
0.89
19.00
1.00
1.00
664.00
1.00
1.00
22.00
Square
DesPerf
Percent
Recall
And Reduction(AR)
Percent
Recall
And Reduction(AR)
0.10
0.10
114.67
0.10
0.10
114.67
0.20
0.21
210.33
0.20
0.21
210.33
0.30
0.31
318.33
0.30
0.31
318.33
0.40
0.41
421.33
0.40
0.41
421.33
0.50
0.50
529.67
0.50
0.50
529.67
0,60
0.60
657.67
0.60
0.60
657.67
0.70
0.70
790.00
0.70
0.70
790.00
0,80
0.80
904.67
0.80
0.80
904.67
0.90
0.90
1001.33
0.90
0.90
1001.33
1.00
1.00
1118.00
1.00
1.00
1118.00
Ethernet
Conmax
Percent
Recall
And Reduction(AR)
Percent
Recall
And Reduction(AR)
0.10
0.11
0.00
0.10
0.10
95.00
0.20
0.19
0.00
0.20
0.20
188.00
0.30
0.28
0.33
0.30
0.30
251.00
0.40
0.38
1.33
0.40
0.40
330.67
0.50
0.48
2.33
0.50
0.50
411.67
0.60
0.56
3.00
0.60
0.59
493.33
0.70
0.65
3.67
0.70
0.69
557.67
0.80
0.75
4.33
0.80
0.78
625.00
0.90
0.89
6.67
0.90
0.90
718.67
1.00
1.00
8.00
1.00
1.00
782.00
20

---

Published as a conference paper at ICLR 2026
Table 9: A detailed description of circuits from the EPFL benchmark. Nodes denotes the sizes of
circuits, and Lev denotes the depths of circuits.
Circuit
Pl
PO
Latch
Nodes
Edge
Cube
Lev
Adder
256
129
1020
2040
1020
255
Barrel shifter
135
128
3336
6672
3336
Divisor
128
128
57247
114494
57247
4372
Hypotenuse
256
128
214335
428670
214335
24801
Log2
32
32
32060
64120
323060
444
Max
512
130
2865
5730
2865
287
Multiplier
128
128
27062
54124
27062
274
Sin
24
25
0
5416
10832
5416
225
Square-root
128
64
0
24618
49236
24618
5058
Square
64
128
18486
36969
18485
250
Round-robin ariter
256
129
11839
23678
11839
87
Alu control unit
7
26
175
348
174
10
Coding-cavle
10
11
693
1386
693
16
Decoder i2c controller
8
256
304
608
304
3
147
142
1357
2698
1356
20
Int to float converter
11
260
520
260
Memory controller
1204
1230
47110
93945
47109
114
Priority encoder
128
978
1956
978
250
Lookahead XY router
60
30
284
514
257
54
Voter
1001
13758
27516
13758
70
Table 10: A detailed description of circuits from the IWLS benchmark. Nodes denotes the sizes of circuits, and Lev denotes the depths of circuits.
Circuit
PI
PO
latch
nodes
edge
cube
lev
aes_core des _area
259
129
530
20797
40645
24444
28
240
64
128
5005
9882
5889
35
des der-
234
64
8808
98463
180542
108666
28
ethernet
98
115
10544
46804
113378
72850
37
i2c mem_ctrl pci bridge32
19
14
128
1147
2299
1375
15
115
152
1083
11508
26436
14603
31
162
207
3359
16897
34607
23130
29
pei_conf_cyee @yyc_addr.de _ec
32
32
0
109
212
128
pei pei_spoci_eto ctrl
25
13
60
1271
2637
1557
19
sasc simple_spi
16
12
117
552
1148
766
10
16
12
132
823
1694
1089
14
spi steppermotordrive
47
45
229
3230
6904
4054
32
4
4
25
228
397
253
11
systemcaes
260
129
670
7961
18236
11648
44
systemedes
132
65
190
3324
6304
3791
33
tv80
14
32
359
7166
16280
9352
50
usb_funer
128
121
1746
12871
27102
16378
25
usb-phy
15
18
98
559
1001
638
12
vga_led
89
109
17079
124050
242332
146201
25
wb_conmax
1130
1416
770
29036
77185
39619
26
wb_dma
217
215
263
3495
7052
4496
26
21


Reviews:
[{"review_id": "nAWPDsBYyM", "reviewer": "Reviewer_L1RN", "summary": "Existing logic optimization tools suffer from high inference costs and limited interpretability. The authors developed HIS, an effective logic optimization model that leverages hierarchical symbolic function representation and a corresponding group reward mechanism.", "questions": "See the 'weakness' part", "limitations": "", "rating": 6, "confidence": 2, "soundness": 3, "presentation": 3, "contribution": 3, "strengths": "* The paper is well written, easy to follow\n* Authors performed various experiments including ablation studies.\n* The problem the authors aimed to address is practical and addresses a real demand in the field.", "weaknesses": "* I haven’t read many AI papers on logic optimization, so I’m not very familiar with the field, but the number of baselines seems rather limited. It would be beneficial to include more general AI models as baselines, even if they were not originally designed for logic optimization, as long as they can be applied to this problem.\n* It appears that the experiments were conducted only once and the performance was reported based on that single run. To ensure that the model’s performance is not dependent on a specific random seed but is statistically meaningful, it is necessary to repeat the experiments multiple times and report the mean and standard deviation of the performance.\n* From Table 3, it can be seen that for the Hyp, Multiplier, Square, and Conmax circuits, the performance difference with or without group optimization is not very large, whereas for DesPerf and Ethernet, the difference is significant. This suggests that while certain components of the model are highly beneficial for some circuits, they contribute little to others. It would be helpful if the authors could provide an explanation of whether this variation is related to the characteristics of the circuits.", "quality": null, "clarity": null, "significance": null, "originality": null, "strengths_and_weaknesses": "", "was_revised": false, "final_justification": "", "rebuttal": "", "claims_and_evidence": "", "methods_and_evaluation_criteria": "", "theoretical_claims": "", "experimental_designs_or_analyses": "", "relation_to_broader_scientific_literature": "", "essential_references_not_discussed": "", "other_strengths_and_weaknesses": "", "other_comments_or_suggestions": "", "questions_for_authors": "", "summary_of_paper": "", "summary_of_recommendation": "", "technical_quality": "", "clarity_of_presentation": "", "potential_impact": "", "robotics_focus": "", "quality_of_limitations": "", "questions_for_rebuttal": "", "reasons_to_accept": "", "reasons_to_reject": "", "questions_to_authors": "", "extra_scores": {}}, {"review_id": "PTfQMcT456", "reviewer": "Reviewer_63LY", "summary": "This paper proposes a novel Hierarchical Circuit Symbolic Discovery Framework (HIS) for efficient logic optimization. HIS aims to address the high inference cost and limited interpretability of existing machine-learning cost-prediction methods, such as GNNs. The framework leverages reinforcement learning to train a structure-aware Transformer model that automatically discovers a lightweight and interpretable symbolic function. This function, represented as a hierarchical tree, mimics the message-passing of GNNs to identify ineffective node-level transformations for pruning. Extensive experiments on two public benchmarks demonstrate that HIS outperforms state-of-the-art methods in prediction accuracy and optimization efficiency. When integrated with the Mfs2 heuristic, HIS significantly reduces runtime while maintaining or even improving optimization quality.", "questions": "1. **Scalability of the Symbolic Tree:** The paper demonstrates the effectiveness of relatively small symbolic trees for integration into existing tools. Could the authors comment on the scalability of their approach? What would be the computational cost and potential performance implications of training a model to discover significantly larger and more complex symbolic expressions?\n2. **Scaling Laws and Potential for a Foundational Model:** A key question for the long-term impact of this methodology is its adherence to scaling laws. Do the model's performance and generalization capability improve predictably with increased model capacity and training data volume? If empirical evidence supported such scaling laws, it would justify the development of a large-scale, pre-trained symbolic model for EDA. Can the authors provide any insight or preliminary results on this front?\n3. **Sensitivity to the Symbolic Library:** The choice of the symbolic library is a strong prior in the discovery process. The results appear sensitive to this choice, as more complex operators (e.g., `log`, `exp`) are available yet absent from the discovered functions in Figure 5. A dedicated ablation study on the composition of the symbolic library is lacking. How do the results change if key operator types (e.g., aggregation functions) are removed? Such a study is crucial for understanding the true expressiveness of the discovered functions and the biases introduced by the library.", "limitations": "", "rating": 6, "confidence": 4, "soundness": 3, "presentation": 2, "contribution": 3, "strengths": "1. **Well-identified the practical problems of GNNs:** The paper correctly pinpoints the critical bottlenecks— **high inference cost and lack of interpretability and** —that prevent state-of-the-art GNNs from being widely deployed in real-world EDA tools. This shows a clear understanding of industrial needs beyond just academic metrics.\n2. **Innovative methodology combining generation and RL:** The core idea of using a **generative model (Transformer) coupled with Reinforcement Learning** to discover an interpretable symbolic tree is highly innovative. It reframes the problem from a black-box prediction task to a structured search for a human-readable function, effectively bridging the gap between performance and interpretability.\n3. **Solid integration with industry tools and demonstrated gains:** The research is grounded in practicality. By seamlessly integrating with a standard EDA framework (ABC) and a critical, time-consuming heuristic (Mfs2), and demonstrating **significant, measurable improvements** (27.22% speedup, 6.95% size reduction), the work is far more **substantial and deployable** compared to many theoretical GNN studies that lack a clear path to real-world application.", "weaknesses": "1. **Misleading figures and poor readability:** The writing and diagrams are currently a significant weakness and hinder understanding.\n    - **Figures:** Figure 1 mentions \"GNNs\" in a way that is confusing and seems disconnected from the HIS methodology. In Figure 2, the flow of \"Generation Process\" and \"Model Training\" are not expressive and hard to understand.\n    - **Writing:** The methodology section requires significant polishing. It needs to guide the reader through the complex pipeline in a simpler, more logical, and step-by-step manner. The current presentation is dense and difficult to follow.\n2. **Omission of training cost:** While the paper justifiably highlights the model's superior **inference efficiency**, it omits any discussion of the **training time and computational resources** required. For a comprehensive cost-benefit analysis, especially for industrial adoption, the substantial computational overhead of training the Transformer with RL must be considered and disclosed.\n3. **Non-actionable interpretability:** The claimed \"interpretability\" is superficial in its current form. While the final symbolic tree is indeed human-readable, the pipeline does **not leverage this interpretability to adjust or improve the model**. It is a one-way, post-hoc explanation. There is no feedback loop where a human expert can correct or guide the symbolic discovery process based on the generated formulas. \n4. **Lack of qualitative analysis:** The authors missed a key opportunity to use interpretability for a compelling **qualitative analysis**. The paper lacks a case study or an in-depth discussion that answers questions like: \"What did we learn from the discovered formulas?\" or \"Can we see a specific example where the symbolic tree correctly identified a complex structural pattern that a human would have missed?\" Including such an analysis would have powerfully demonstrated the unique advantage of their method over pure black-box approaches.", "quality": null, "clarity": null, "significance": null, "originality": null, "strengths_and_weaknesses": "", "was_revised": false, "final_justification": "", "rebuttal": "", "claims_and_evidence": "", "methods_and_evaluation_criteria": "", "theoretical_claims": "", "experimental_designs_or_analyses": "", "relation_to_broader_scientific_literature": "", "essential_references_not_discussed": "", "other_strengths_and_weaknesses": "", "other_comments_or_suggestions": "", "questions_for_authors": "", "summary_of_paper": "", "summary_of_recommendation": "", "technical_quality": "", "clarity_of_presentation": "", "potential_impact": "", "robotics_focus": "", "quality_of_limitations": "", "questions_for_rebuttal": "", "reasons_to_accept": "", "reasons_to_reject": "", "questions_to_authors": "", "extra_scores": {}}, {"review_id": "IGErjYTHnD", "reviewer": "Reviewer_DPdp", "summary": "This paper proposes HIS (Hierarchical Circuit Symbolic Discovery Framework), a novel approach for efficient logic optimization in chip design. The key innovation lies in learning hierarchical symbolic functions that can capture circuit structural information while maintaining interpretability and computational efficiency. The framework uses structure-aware Transformers with reinforcement learning to generate symbolic trees that perform message passing similar to GNNs but with significantly lower inference cost. Experiments on EPFL and IWLS benchmarks demonstrate that HIS achieves runtime improvement and circuit size reduction when integrated with the Mfs2 heuristic, while being faster than GNN-based methods during inference.", "questions": "(1) What is the computational cost of training the hierarchical symbolic trees compared to GNN based symbolic discovery method such as CMO?\n(2) Is the claimed interpretability advantage primarily from the hierarchical learning framework, or do the final, complex symbolic expressions offer more practical insights for domain experts than the simpler, non-hierarchical functions from methods like CMO?\n(3) The paper focuses solely on the Mfs2 heuristic. How does the HIS framework generalize to other critical LO operators with different graph structures and optimization goals, such as Refactor?", "limitations": "", "rating": 6, "confidence": 3, "soundness": 3, "presentation": 3, "contribution": 2, "strengths": "(1) novel problem formulation: First GNN-free work to apply symbolic discovery to circuit graphs for logic optimization.\n(2) Good originality: proposing a hierarchical symbolic tree structure that independently learns to mimic GNN-style message passing.\n(3) Comprehensive Evaluation: The authors conducted a comprehensive empirical evaluation to validate their approach, including inference time, online/offline evaluation, QoR improvement etc.\n(4) Clear and Intuitive Presentation: The paper presents a clear writing style and visual aids.", "weaknesses": "(1) Limited Analysis on Training Overhead: While the paper excellently highlights the inference speed-up, it lacks a analysis of the training time overhead, which can be substantial for reinforcement learning-based methods.\n(2)  Inconsistent Performance Gains: The experimental results do not consistently demonstrate the superiority of HIS over the state-of-the-art CMO. While HIS shows an advantage in some specific settings (e.g., HIS-Mfs2 on 'Hyp' and 'DesPerf'), it underperforms CMO in QoR-focused scenarios (e.g., 2HIS-Mfs2), raising concerns about the stability and real-world benefit of the proposed method.\n(3) The Claim of Interpretability is Not Substantiated by the Final Outputs: While HIS proposes a conceptually novel hierarchical framework, its final symbolic expressions seems are not demonstrably more interpretable than those from CMO.", "quality": null, "clarity": null, "significance": null, "originality": null, "strengths_and_weaknesses": "", "was_revised": false, "final_justification": "", "rebuttal": "", "claims_and_evidence": "", "methods_and_evaluation_criteria": "", "theoretical_claims": "", "experimental_designs_or_analyses": "", "relation_to_broader_scientific_literature": "", "essential_references_not_discussed": "", "other_strengths_and_weaknesses": "", "other_comments_or_suggestions": "", "questions_for_authors": "", "summary_of_paper": "", "summary_of_recommendation": "", "technical_quality": "", "clarity_of_presentation": "", "potential_impact": "", "robotics_focus": "", "quality_of_limitations": "", "questions_for_rebuttal": "", "reasons_to_accept": "", "reasons_to_reject": "", "questions_to_authors": "", "extra_scores": {}}, {"review_id": "YswTb61src", "reviewer": "Reviewer_KPds", "summary": "To address the bottleneck of low efficiency in LO heuristic algorithms for chip design, as well as the issues of high inference cost and poor interpretability in existing GNN-based optimization methods, the researchers propose HIS, a hierarchical circuit symbol discovery framework. This framework leverages a hierarchical symbolic tree structure and a structure-aware Transformer optimized with PPO to generate lightweight, interpretable symbolic functions for identifying invalid subgraphs. Evaluated on the EPFL and IWLS benchmarks, HIS outperforms SOTA methods like COG and CMO in terms of prediction recall. Furthermore, when integrated with Mfs2, it achieves an average runtime reduction of 27.22%, a circuit size reduction of 6.95%, and demonstrates 296x and 254x faster inference speed compared to COG.​", "questions": "1. Please respond to the concerns I have raised in the 'weaknesses' section. If the revision can adequately address most of the critical issues, I would consider raising the score.\n2. In my personal opinion, the contribution of this paper lies more in its solid experimentation and reproducibility than in its theoretical advancement in ML. Considering this, EDA-focused conferences (such as DAC or ISCA, with an upcoming November deadline) would be a more suitable venue for it. Of course, I also believe that if the intention is to submit to DAC or ISCA, experiments related to scalability, as well as validation under advanced process technologies (below 7nm), would need to be supplemented.", "limitations": "", "rating": 4, "confidence": 4, "soundness": 2, "presentation": 2, "contribution": 2, "strengths": "1. The researchers tackle the critical problem of logic optimization in EDA, achieving notable advances on an NP-hard problem through the design of HIS.\n2. The study validates the balance between efficiency, accuracy, and interpretability on industrial-grade benchmarks. The experimental design is solid and demonstrates high reproducibility, achieving a 27.22% reduction in runtime and a 6.95% reduction in circuit size.", "weaknesses": "1. The work lacks a mathematical proof that the hierarchical symbolic tree can equivalently approximate the message-passing capability of a GNN. It relies solely on the experimental observation that its performance with L=2 is comparable to that of a 2-layer GNN. The work lacks a theoretical analysis of the necessity of the operators (e.g., log, exp) included in the symbol library.\n2. The paper does not derive the generalization error bound for the symbolic function, such as how the sensitivity of the $\\beta / \\gamma$ parameters changes as the number of circuit nodes increases. While positioning itself as a paper that emphasizes \"interpretability,\" it provides little theoretical proof or analysis to substantiate this claim.\n3. This paper only validates the Mfs2 heuristic for logic optimization, without testing mainstream pre-mapping heuristics such as Resub and Rewrite. In my view, the practical value of this work in the broader context of LO problems would be significantly strengthened if it included at least three different LO heuristics. Otherwise, there is reasonable doubt that the proposed framework might be effective only for Mfs2.\n4. While the EPFL and IWLS benchmarks cover industrial-scale circuits, they do not include real circuit data from advanced process technologies (e.g., 7nm or 3nm). Therefore, I believe testing on real industrial data would provide more compelling evidence of the method's robustness.\n5. The work fails to investigate the impact of the computation tree depth L (using only L=2) on performance, thus making it impossible to determine if L=3 or L=4 could enhance the structure-capturing capability. It also omits an analysis of how circuit type (e.g., combinational vs. sequential logic) influences the effectiveness of HIS.\n6. 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Author rebuttal:

Decision: Accept (Poster)