CircuitFusion: Multimodal Circuit Representation Learning for Agile Chip Design
Authors: Wenji Fang
Shang Liu
Jing Wang
Zhiyao Xie
Venue: ICLR 2025 Poster (2025)
Keywords: Electronics Design Automation (EDA)
circuit representation learning
multimodal learning
self-supervised learning
hardware circuits
Primary area: infrastructure, software libraries, hardware, systems, etc.
TL;DR: We propose CircuitFusion, the first multimodal and implementation-aware circuit encoder. It encodes multimodal circuits into general representations that support different downstream design tasks.

Abstract: The rapid advancements of AI rely on the support of integrated circuits (ICs). However, the growing complexity of digital ICs makes the traditional IC design process costly and time-consuming. In recent years, AI-assisted IC design methods have demonstrated great potential, but most methods are task-specific or focus solely on the circuit structure in graph format, overlooking other circuit modalities with rich functional information. In this paper, we introduce CircuitFusion, the first multimodal and implementation-aware circuit encoder. It encodes circuits into general representations that support different downstream circuit design tasks. To learn from circuits, we propose to fuse three circuit modalities: hardware code, structural graph, and functionality summary. More importantly, we identify four unique properties of circuits: parallel execution, functional equivalent transformation, multiple design stages, and circuit reusability. Based on these properties, we propose new strategies for both the development and application of CircuitFusion: 1) During circuit preprocessing, utilizing the parallel nature of circuits, we split each circuit into multiple sub-circuits based on sequential-element boundaries, each sub-circuit in three modalities. It enables fine-grained encoding at the sub-circuit level. 2) During CircuitFusion pre-training, we introduce three self-supervised tasks that utilize equivalent transformations both within and across modalities. We further utilize the multi-stage property of circuits to align representation with ultimate circuit implementation. 3) When applying CircuitFusion to downstream tasks, we propose a new retrieval-augmented inference method, which retrieves similar known circuits as a reference for predictions. It improves fine-tuning performance and even enables zero-shot inference. Evaluated on five different circuit design tasks, CircuitFusion consistently outperforms the state-of-the-art supervised method specifically developed for every single task, demonstrating its generalizability and ability to learn circuits' inherent properties.

Published as a conference paper at ICLR 2025
CIRCUITFUSION: MULTIMODAL CIRCUIT REPRESEN- TATION LEARNING FOR AGILE CHIP DESIGN
Wenji Fang Shang Liu Jing Wang Zhiyao Xie
The Hong Kong University of Science and Technology (wfang838, s1 fudx jwang www.://wwcoonnttoooom ust. eezhiyaolust.hit
ABSTRACT
The rapid advancements of AI rely on the support of integrated circuits (ICs). However, the growing complexity of digital ICs makes the traditional IC design process costly and time-consuming. In recent years, Al-assisted IC design meth- ods have demonstrated great potential, but most methods are task-specific or focus solely on the circuit structure in graph format, overlooking other circuit modalities with rich functional information. In this paper, we introduce CircuitFusion the circuit encoder. encodes circuits
first multimodal and implementation-awee into general representations that support different downstream circuit design tasks. To learn from circuits, we propose to fuse three circuit modalities: hardware code, structural graph, and functionality summary. More importantly, we identify four unique properties of circuits: parallel execution, functional equivalent transformation, multiple design stages, and circuit reusability. Based on these properties, we propose new strategies for both the development and application of CircuitFusion: 1) During circuit preprocessing, utilizing the parallel nature of cir- cuits, we split each circuit into multiple sub-circuits based on sequential-elene boundaries, each sub-cireuit in three modalities. enables fine-grate fine-grained encoding at the sub-circuit level. 2) During CircuitFusion pre-training, we introduce three self-supervised tasks that utilize equivalent transformations both within and across modalities. We further utilize the multi-stage stage property of circuits to align repre- sentation with ultimate circuit implementation. 3) When applying CircuitFusion strrival--augmente inference method,
downstream tasks, we propose a which retrieves similar known circuits as a reference for predictions. It improves fine-tuning performance and even enables zero-shot inference. Evaluated on five different circuit design tasks, CircuitFusion consistently outperforms the state- of-the-art supervised method specifically developed for every single task, demon- strating its generalizability and ability to learn circuits' inherent properties'.
INTRODUCTION
The fast advancements of require the support of hardware circuits (e.g., GPU, TPU, NPU). How- ever, the increasing complexity of the digital integrated circuit (IC) has led to skyrocketing IC design costs, challenging traditional IC design methodologies. In recent years, Al-assisted IC design tech- niques have demonstrated unprecedented potential in enabling agile chip design process (Rapp et al., 2021). Existing explorations include automated chip design planning (Mirhoseini et al., 2021; Bai et al., 2023; Yu et al., 2018). early chip quality evaluation (Du et al., 2024; Fang et al., 2024a; Zheng et al., 2023; Wang et al., 2023b), automated chip design assistance (Pei et al., 2024; Liu et al., 2023b;a; Yao et al., 2024), etc. These works are mostly task-specific and trained supervisely with small amount of labeled circuit data. In this work, we target essentially general and multi- multi-tasking Al models for circuits by exploring customized circuit representation learning techniques.
Learning hardware representation. Several recent works have proposed either supervised (Yang al., 2022; Li et al., 2022b; Shi al., 2023; Vasudevan et al., 2021; Yang et al., 2022; Deng et al., 2024) or self-supervised contrastive methods (Wang et al., 2022; Xu et al., 2023; Fang et al.,
"Corresponding Author
'CircuiFFusion is available http://gihuu.com/kuu-- www.://uuuutiiiyyaooCnnuauuuuio

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Published as a conference paper at ICLR 2025
2025) to learn eircuit representations. Most works only focus on the circuit structure by converting circuits into a graph format and learning circuit embeddings based on the graph alone. However, circuit is unique data type and inherently exhibits multimodal characteristics. A register-transfer level (RTL.) circuit can be described with hardware description language (HDL.) code, a graph of operators, or natural-language summary of functionality. Generally, we view each circuit structured implementation of certain finctionality. The graph modality highlights the structure, the functionality summary emphasizes the functionality, while the HDL code incorporates information from both aspects.
Learning multimodal representation. To encode information from diverse modalities, multimodal representation learning has been successfully applied for various modality fusions, such as vision- language (Radford et al., 2021; Li et al., 2021; 2022a; 2023a; Akbari et al., 2021; Bao et al., 2022), graph-language (Yin et al., 2020; Gao et al., 2020), and software-graph (Guo et al., 2022a; Zhang et al., 2024). However, no existing work has ever exploited inherent multi-modalities of RTL. circuits. More importantly, there are significant differences between the mechanisms of circuits and other common data types during multimodal representation learning, as we will summarize later.
To this end, we present AircuitFusion. the first multimodal fused and implementation- encoder to capture informative general circuit representations. Leveraging the multimodal nature of circuits, first encode circuits separately under three modalities (i.e., HDL code, structural graph, and functionality summary) through three independent unimodal encoders. A multimodal encoder then fuses the modalities via cross prossaattention mechanism. Additionally, we enrich CireuitFusion with downstream circuit implementation information using an auxiliary netlist encoder.
circuit
To learn this special multimodal circuit data, we identify four unique circuit properties (P1-4) and propose four corresponding innovative strategies (S1-4), applied to circuit preprocessing (S1), Cir- cuitFusion pre-training (S2,3), and application of CircuitFusion in downstream tasks (S4):
Pl: Parallel execution. Hardware circuit operates with inherent parallelism, where all combina- tional logic calculates simultaneously, and all sequential elements are updated at every clock cycle. S1: Sub-circuit generation. Exploiting this parallel mechanism, we propose to split the entire circuit into multiple sub-cireuits based on sequential element boundaries. This preprocessing step allows for scalable CircuitFusion learning across the entire circuit.
P2: Functional equivalent transformation. The same functionality of a circuit can be imple- mented in various ways, as each logic expression can be equivalently transformed. Therefore, circuits with similar functionality may have entirely different structures. S2: Semantic-structure pre-training on circuit. Leveraging this property, we design three pre-training tasks simulta- neously capture both structural (i.e., masked graph modeling) and semantic (i.e., masked summary modeling, functional contrastive) circuit representations within and across the three modalities. The circuit data for these tasks is further augmented through equivalent transformations, generating circuits that maintain the same functionality but have entirely different structures.
P3: Multiple design stages. In standard digital IC design flow, the functional hehavior is de- scribed with HDI. codes at the RTL stage. Then the RTL circuits will be automatically synthe- sized into gate-level netlists, representing the circuit implementation in connected logic gates. The netlists are then transformed into the chip layout for ultimate manufacturing. This multi-stage de- sign process involves various levels of circuit abstraction, with earlier stages (e.g., RTL) capturing more semantics and later stages (e.g., netlist) introducing more implementation details. S3: Cir- cuit implementation-awaan the RTL circuits with their netlist implementations within a shared latent space during pre-training This alignment integrates implementation information into circuit representations, significantly ben- efiting downstream tasks that predict the eircuit implementation metries at early RTT. stages.
alignment. Based on this multi-stage property, we propose to align
P4: Circuit reusability. In realistic circuit development, circuits exhibit high reusability, with com- panies tending to use intellectual property (IP) blocks rather than designing circuits from scratch. This reusability inspires us to leverage the similarity of circuit embeddings generated by CircuitFu- sion to improve inference. S4: Retrieval-augmente downstream tasks of new circuits, we propose retrieving the most similar known circuits as refer- ences and calibrating the final predictions utilizing these retrieved circuits. This method not only improves the fine-tuning results but also enables zero-shot inference for circuits.
inference. When applying CircuitFusion to
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Published as a conference paper at ICLR 2025
20
WNS
TNS
Power
SOTA baseline
51
w/o S4
only graph
only code
only summary.
CircultFusion
Strategy
Modality
Figure 1: Preview of results on the effectiveness of proposed strategies and circuit modalities.
We evaluate the effectiveness of our proposed method across various tasks, where CircuitFusion's s general solution consistently outperforms state-of-the-ard (SOTA) task-specific models, demonstrat- ing that CircuitFusion learns the truly general circuit embeddings applicable to various tasks. Addi- tionally, as shown in Figure 1, we provide preview results on the impact of cach proposed strategy and circuit modality, with more details provided in Appendix E.3. Specifically, relying on only sin- gle circuit modality also leads to increased error. Similarly, removing any strategy results a notice- able increase in prediction error, highlighting the effectiveness of our proposed multimodal fusion and circuit-specffic strategies. Furthermore, we also evaluate the scalability of CircuitFusion by scal- ing both model size and data size, with details presented in Section 4.5. This suggests the potential for incorporating more diverse circuit datasets and larger models in future work. We believe our scal- able and versatile CircuitFusion holds significant promise for enhancing other circuit-related tasks.
2 RELATED WORKS
Hardware representation learning. Several latest works have started exploring the learning of general circuit representations based on pretrain-fineture paradigms. However, these works (Wang al., 2022; Li et al., 2022b; Xu et al., 2023; Shi et al., 2023) only focus on the circuit's graph format, Moreover, most studies (Wang et al., 2022; Li et al., 2022b; Shi al., 2023) target the functional verification tasks for netlist, a late stage of the design flow. In comparison, we target learning circuit representation at the early RTL stage, when designers design circuit functionality with HDL code. This early stage offers more flexibility for design quality optimization. Additionally, there are also explorations for FPGAs (Sohrabizadeh al., 2023) and analog cireuits (Zhu et al., 2022).
Multimodal representation learning. Multimodal learning has achieved remarkable success in multiple other domains, such as vision-language learning (Radford et al., 2021: Li al., 2021; 2022a; 2023a: Akbari et al., 2021; Bao et al., 2022) and graph-language learning (Yin et al., 2020; Gao et al., 2020). Among all multimodal learning applications, software code is the most similar to hardware circuits. Existing software encoders primarily target the summary and code modali- ties (Feng et al., 2020; Li et al., 2023b; Wang et al., 2023a; Zhang al., 2024), while some (Guo et al., 2022a; Zhang et al., 2024) consider the syntactic graph format. However, multimodal software encoders cannot be directly applied to hardware tasks due clearly different underlying mecha- nisms. For example, all four circuit properties (P1-P4) introduced in the Introduction do not apply to software code. Additionally, most existing software encoders are only validated on short code snippets within 1024 tokens, which are even shorter than the HDL of simple circuit.
3 PROPOSED METHOD: CIRCUITFUSION
In this section, we present our CireuitFuusin encoder framework in detail. We will first outline the circuit preprocessing steps and the model architecture, followed by an illustration of the pre-training process and its applications: 1) Circuit preprocessing (Section 3.1): We first split the entire circuit into multiple sub-circuits according to the parallel execution of sequential registers in circuits. Each sub-circuit is represented in three modalities: HDL. code, circuit graph, and functionality summary. 2) Model architecture (Section 3.2): We encode the three circuit modalities via three unimodal encoders, with multimodal encoder for modality fusion and an auxiliary netlist encoder to integrate implementation information. 3) Pre-training of CircuitFusion (Section 3.3 and Section 3.4): We propose 4 self-supervised pre-training tasks to jointly train CircuitFusion, achieving multimodal fusion and implementation-avwee aware alignment to capture both structural and semantic information from circuits. 4) Application CircuitFusion (Section 3.5): We propose a new retrieval- aatgeeel-augmentedd inference method to improve CircuitFusion to downstream tasks.
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(a) Circuit preprocessing flow
(b) A prompt example on summary
Figure 2: Multimodal and multi-stage circuit preprocessing flow. We split circuits into sub-circuits for fine-grained encoding, representing RTL in three modalities (HDL code, functionality summary, and graph) and netlists as graphs, ensuring data alignment across modalities and design stages.
3.1 PREPROCESSING: MULTIMODAL AND MULTI-STAGE CIRCUIT DATA
Figure 2 illustrates our circuit data preprocessing workflow. For each circuit, we split it into multiple subcircuits, then express each subcircuit in three modalities (i.e., code, graph, summary). Each training circuit data is in both RTL and netlist, two primary circuit design stages. More preprocessing details with a concrete example of the circuit data be found in Appendix B.
Generation of three circuit modalities. (1) HDL code: circuit may be initially designed with different HDL code formats, such Verilog, VHDII, and Chisel. For consistency, all HDL code is automatically converted into Verilog format with open-source tools (Wolf et al., 2013). (2) Circuit graph: To further capture circuit structure, each circuit in HDL code will be converted a graph of logic operators and sequential registers. (3) Functionality summary: To further capture circuit se- mantics, as Figure 2b shows, we prompt GPT-4 summarize the functionality and implementation details of each sub-circuit. We introduce the generation of sub-circuit below.
Sub-cireuit generation. Utilizing the parallel execution mechanism of circuits, we split an entire circuit into multiple sub-circuits, each corresponding to one register. Specifically, for each register, we capture a sub-circuit by backtracing all its combinational input logic operators. This process applies to both RTL and netlist stages, and across all modalities, ensuring that the sub-circuits are consistently split and functionally aligned. The detailed sub-cireuit generation algorithm is in Ap- pendix B. CircuitFusion will encode each sub-cireuit into an embedding, supporting various down- stream tasks.
There several key advantages of splitting circuits based on the register: (1) The sub-circuits for multimodal RTL and the ctoss-stage netlist are strictly aligned and functionally equivalent, ensuring consistency across both modalities and design stages. (2) Each sub-circuit captures the complete state transition of the register within a single clock cycle, including all timing paths and logic com- putations. This serves as a foundation for our model to learn both the combinational and sequential behavior of circuits. (3) The sub-cireuit provides an intermediate level of granularity, bridging the gap between detailed tokens/nodes and the overall circuit. This granularity also enables generating summaries for the state update function of each register, offering a more fine- -ree-grained understanding compared to summarizing the entire circuit.
3.2 CIRCUITFUSION MODEL ARCHITECTURE
Figure shows the model architecture of CircuitFusion. It consists of three unimodal encoders, one for each modality. Then a multimodal fusion encoder integrates the output information from all three unimodal encoders. Additionally, an auxiliary netlist encoder is employed only during pretraining.
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CircuitFusion
Task
Subciauu
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Implementation- Aware Alignment
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Neilit
Enceder
Encoder
CNV
Embbeddinng
RTL-Stage
Setlist-Stage
CircuitFusion pre-training workflow. CircuitFusion includes three unimodal encoders (graph, summary, and code) and multimodal fusion encoder, with auxiliary netlist encoder used only in pre-training. Leveraging the circuit's unique properties, we propose four tasks to capture structural and semantic information, while aligning the netlist stage for implementation awareness.
Figure 3:
Here we introduce each unimodal encoder: (1) Graph encoder: Unlike text or image encoders (De- vlin, 2018; Dosovitskiy, 2020) that benefit from extensive pre-trained models, pre-trained general-purpose graph models are relatively scarce, requiring us to build our graph encoder from scratch. We adopt a 7-layer graph transformer (Ying al., 2021) with graph positional encoding. Each sub-circuit graph is encoded into sequence of graph embeddings {Gels: G....., Gn where is the number of nodes in the graph. (2) Summary encoder: We employ 6-layer transformer to process the functionality summary with m tokens into summary embeddings {Ses. St...., Sm }. initialized using the first 6 layers of BERT base (Devlin, 2018). (3) Code encoder: To handle long HDL code snippets, we use an LLM-based text encoder NV-Embed-VI (Lee et al., 2024), capable of a maximum of 32K input tokens. encodes the HDL code with q tokens into a sequence of code embeddings {Cols. C1...., ......,,G J. We freeze this code encoder to allow integration with various potential LLM-based encoders, including both open-source and commercial models, supporting scalability to larger models in the future. In all three encoders, the [CLS] token represents the embedding of the entire sub-circuit.
As for the fusion encoder, we initialize the multimodal encoder using the last 6 layers of BERT equipped with the widely adopted cross attention mechanism for multimodal fusion (Li et al., 2021; 2022a; 2023a). We propose summary-centric fusion to fuse the three modalities, since the summary provides higher-level semantic insights, while code and graph capture details of the circuit. More details of different fusion strategies discussed in Appendix E.5. Specifically, we first perform a mixup (Zhang, 2017) of the graph node embeddings and code token embed- dings, controlled by interpolation coefficient X. The resulting mixup embedding is defined as X(G,, G2, G.) + (1 (C Cz...., C.),, where the two modality embedding vectors are padded into the same dimension first. The mixup strategy facilitates pre-fusion between the graph and code modality for better fusion with the summary modality. In the fusion encoder, the summary token embeddings are directly fed as queries for cross attention each layer, while the mixup em- beddings serve as the keys and values. Ultimately, the initial RTL sub-cireuit is encoded into fused embeddings {Ras, Ry...., R.
base,
In addition, an auxiliary GNN-based netlist graph encoder is already pre-trained on netlist before being applied to CircuitFusion. This auxiliary encoder encodes each sub-circuit netlist graph with w nodes into node embeddings { [N1, N2...... ... N.,, and graph-level embedding N Npool by mean pooling all node embeddings. Please note that the netlist encoder is discarded during the inference process, as netlist data is unavailable in our RTL-stage downstream tasks. The implementation details of the netlist encoder are provided in Appendix C.3.
3.3 PRE-TRAINING WITHIN CIRCUITFUSION MULTIMODAL FUSION
Figure also shows the pre-training process of CircuitFusion. To learn informative representations utilizing the unique circuit properties, carefully design four pre- pre-training tasks to train CircuitFu- sion: #1 Intra-modal learning on unimodal encoders to extract features within its specific modality. #2 Cross-moda contrastive learning for modality alignment. #3 Masked summary modeling and
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mixup-summary matching the fusion encoder for multimodal fusion. #4 Implementation-aveee aware alignment between CircuitFusion and netlist encoder by cross- gross-design-stee contrastive learning.
Task #1 Intra-modal learning. For the circuit graph modality, first introduce the masked graph modeling pre-training objective. captures the structural information of different circuit operators in relation to their connectivity within the circuit graph. Specifically,
randomly mask the graph nodes (i.e., operators) with the special token [MASK]- Then their operator type (e.g., ADD, OR, MUX, etc.) will be predicted based on surrounding graph node embeddings. Denote the input eircuit masked graph as G. The ground-truth operator type masked nodes is denoted as a one- hot vector makk The predicted operator type of masked nodes is denoted as pm pm>kk (G), where the prediction based on the surrounding graph node embeddings. The objective to minimize the mean squared error (MSE) between ye
makk and pmskkss formulated below:
Tuts misk (G) )
=E (OOND
(I)
MGM
where E(g)~D represents the expectation E over the eircuit graph dataset D.
Additionally, it's crucial capture the functional semantics of each sub-circuit. To achieve this, we employ intra-modal contrastive learning for both the graph and summary encoders. Specifically, we augment each sub-cireuit with positive samples (denoted as +) generated through functionally equivalent transformations, which create new sub-circuits with the same functionality but entirely different structures. All other functionally different sub-circuits in the batch are treated as negative samples ("). A contrastive objective pulls functionally similar circuits closer together in their spective modality embedding space while pushing dissimilar circuits further apart. Specifically, we minimize the InfoNCE (Oord et al., 2018) loss (defined as CL) for sub-circuit embeddings in both the graph (Gels) and summary (Sess) modalities, as formulated below:
CLo [Cc))-(CILLGas G Gou), L (CL)), chs ST.)
(2)
Task #2 Cross-modal alignment. We employ cross- modal contrastive learning to align graph, summary, and code representations. This task aligns representations from different modalities in shared latent space, benefiting the subsequent modality fusion. We formulate the cross-modal contrastive loss as follows:
Cl B(s,G.Cy~D [CL(Sets: C...Gal + CL.(Sass Co. Cail
Task #3 Multimodal fusion. We adopt two pre-training tasks for modality fusion: (1) Mask sum- mary modeling: This objective involves randomly masking parts of the high-level summary tokens with [MASK] and predicting them based on the fusion embeddings R. This helps the model capture the relationship between the modalities and reinforces its understanding of the summary. The model takes the masked summary embeddings as the cross-attention query, and the graph-code mixup embeddings mirge as the key and value. The probability for masked token p mak (R is predicted by the model. This objective minimizes a cross-entropy (CE) loss:
L
#3 MSM
mas pmsss(()) (ft)) y
where yn mask is ground-truth in one-hot vocabulary distribution.
(2) Summary and mixup-embedding matching: We employ a binary classification task that pre- dicts whether pair of given summary- muimary-mixup embeddings is positive (matched) negative (un- matched). This task ensures that the model correctly fuses the summary with the mixup embed- dings. Denote the binary prediction in probability p naathh and its ground-truth value match we formulate the training objective as follows:
#3 match
B(s,G,C)~DDB (y mmatch (Rt, R RT)).
5
3.4 PRE-TRAINING BEYOND CIRCUITFUSION INPLEMENTATION-AWAN ALIGNMENT
Task #4 Implementation-awaar alignment. Besides the above three tasks within CircuitFusion, further pre-train CircuitFusion integrate the later-stage netlist implementation information.

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indexing
sub-iitcat Vecier
Crown circite
Summary
Known circutts
Codo
stoee
CrouttRusion Encoder
Retrieval Inference
Zero-thot
Design Quality
Rerformance
Fuston Embbedeinge
gPO
SP
Area
Power
Figure 4: CireuitFusion retrieval- auggented inference flow. For downstream tasks, CircuitFusion retrieves the most similar known circuits as references to improve fine-tuning and enable zero-shot.
Specifically, we utilize an auxiliary netlist encoder with an implementation- aware contrastive objec- tive, which aligns the embeddings of the whole sub-circuit in both the RTL (i.e., Rak) and netlist (i.e., Npaol) within shared latent space. The contrastive loss is formulated below:
#4 Smpt
ERRNN
CL N pool poot + CL(NNoool pool: Rig Raw))
Before the alignment, the netlist encoder is already pre-trained using masked graph modeling and graph contrastive objectives on netlist, with tasks similar to those employed in the CircuitFusion graph encoder. These objectives help the netlist encoder capture the structure of the netlist graph.
To this end, we formulate the complete self-supervised pre-training objective of CircuitFusion by jointly employing the four tasks:
L = (4 LELC L(ts)
t#2 CLasds
##3 mmatich + L
MSM
3.5 APPLICATION: RETRIEVAL- RETRIEVAL-AUGMENTEE INFERENCE FOR DOWNSTREAM TASKS
When applying CircuitFusion to downstream tasks, we propose eetrieval-augmente inference method", leveraging the circuit reuse property, as illustrated in Figure 4. Given the similarity across different chip product generations and the extensive reuse of IP blocks, there is vast pool of func- tionally similar known circuits that can be used as references. The key idea is to utilize the pre- trained CircuitFusion encoder to retrieve these similar circuits during inference new designs, using their design quality metrics as references for downstream tasks.
Specifically, Figure 4 details the steps: 1) Indexing: This step stores already known circuit? embeddings for future retrieval. The known multimodal circuits are first split into sub-circuits, converted into fusion embeddings by CireuitFusion, and stored a VectorStore, denoted VS 2) Retrieval and inference: For each new sub-circuit, the top-k most similar sub-circuits are retrieved from VS e by measuring their cosine similarity in the embedding space.
During fine-tuning, the retrieved metrics (e.g., timing, power, area) from these similar circuits are concatenated with the fusion embeddings of the target unknown circuit and fed into fine-tuning mod- els, which are trained with task- task-specific labels. These metrics act as additional reference points, al- lowing the fine-tuning model calibrate and improve accuracy. Leveraging the aerreeval-augmented strategy, the pre-trained CircuitFusion is fine-tuned with task labels by adding a simple regression model. Moreover, the retrieved metrics can directly serve as the final prediction, enabling zero-shot inference, where no further model training or task-specific labels are required. We provide more retrieval-ane auggeentd inference implementation details in Appendix C.5.
4 EXPERIMENTS
Circuit dataset. We construct a dataset with 41 RTL designs collected from various representative open-source benchmarks (Corno al., 2000: URL, b; VexRisev, 2022; Amid et al., 2020), with detailed statistics provided Table 1. We provide more introductions on the benchmarks in Ap- pendix A. The original dataset consists of 7, 166 aligned RTL and netlist sub-cireuit pairs, where each
Plecase note this retrieval optional during inference. no similar design exists, omitting this strategy will result in only a slight performance decrease, with more detailed evaluations shown in Figure 9. In practice, known cireuit designs may come from previous version of circuit product, IP libraries, etc.

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Published as a conference paper at ICLR 2025
Table 1: Statisties of Circuit Benchmarks.
Source
#
Circuit Size (Min, Avg. Max}
Sub-circuit Size (Min, Avg. Max)
Original
Benchmarks
Circuit
Node (Graph)
# Token (Code)
Suub-ciruuic
Node (Graph)
Token (Code)
HDL Type
ITC"99
(3,6, 9JK
[30, 70, TORJK
[12. 21,
[12, 106, 252]
[68. 1k. 2K)
VHDL
OpenCores
5
(1.23, 54]K
[12K, IM, 2M)
(12.96 96, 173)
[8. 18, IK]
(74, 2K, 91K]
Verilog
VexRisev
17
(4. 147, 521
{144K. 6M, 20M)
33. 168, 694)
[15. 47, 4K)
[68, 3K. 123K)
SpinalIDL.
Chipyard
12 11, 13, 83|K
{9K. IM. SM)
(28. 461. 23K}
24. 50, IK)
(70, 6K. 109K]
Chisel
RTL sub-cireuit is represented through three modalities. To enable contrastive learning, we perform circuit augmentation using functionally equivalent transformations through open-source tools like Yosys (Wolf et al., 2013) and ABC (Brayton & Mishchenko, 2010), generating positive samples and resulting in total of 57,328 sub-circuits across the dataset. Theoretically, the dataset can be further augmented with an unlimited number of designs. We apply an 80/20 training/test split, ensuring the split is based complete designs, with 33 designs used for training and 8 reserved for testing.
Effectiveness of sub-circuit generation. The effectiveness of our proposed sub-circuit generation demonstrated in Table 1. The original circuit consists of tens of thousands of graph nodes and millions of code tokens, making it extremely challenging for existing graph and text models to handle. In comparison, sub-circuits are approximately 1000x smaller in the number of nodes and code tokens, thus enabling scalable and fine-grained representation learning.
4.1 VISUALIZATION OF CIRCUIT MULTIMODAL FUSION
Before delving into the quantitative experiment results, we first visualize the impact of cross- attention between the centric summary modality and corresponding code and graph modalities, as shown in Figure 5. Specifically, we use the Grad-CAM technique (Selvaraju et al., 2017) to highlight the graph nodes and code tokens with the highest cross-attention scores. For example, in Figure 5a, when the summary describes input signals, cross-attention highlights the correspond- ing signal names in both code and graph modalities. In Figure 5b, for conditional logic, both the relevant operations and signals are highlighted in the code modality, while conditional operations are highlighted in the graph modality. This visualization shows CircuitFusion' 's ability to focus on rele- vant elements across modalities: the graph provides structural information, the code offers semantic details, and the summary guides the fusion, enabling comprehensive representation learning.
Summary
Summary
The design takes two data Inputs: regr (a 32 Input data) and
*Conditional Logk": The circuit uses conditional assignments to perform different operations on values of input signals
(a single-bit input determines current state)
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(b) Cross attention on conditional logics
Figure 5: Visualization of cross attention between summary and code/graph.
4.2 DESIGN QUALITY PREDICTION TASKS AND BASELINE METHODS
CireuitFusion is pre-trained based on our proposed four supe-supe tasks, with implementation details in Appendix C. Then we apply pre-trained CircuitFusion to RTT--ttage circuits, targeting five different prediction tasks about ultimate eircuit qualities. These predictions are critical for designers to receive early feedback on design quality while writing HDL code, without going through time- consuming downstream design processes with EDA tools. These tasks are highly challenging, as the RTL-stage circuit only contains functional information, lacking the implementation details related to design quality. Recently, there have been several task specific explorations (Sengupta et al., 2022; Xu et al., 2023; 2022; Fang et al., 2023; 2024b;a) individual tasks.
Design quality evaluation tasks at RTL stage. We detail the five design quality prediction tasks as follows: (1) Register slack prediction: Predicting the slack for individual registers, which indicates
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the margin by which the register meets misses the timing constraints post-synthesis. This task helps identify critical registers that might cause timing violations. (2) WNS prediction: Estimating the worst negative slack (WNS) for the entire design, which measures the largest timing violation in the circuit. A key metric for determining whether the design meets timing requirements. (3) TNS prediction: Predicting the total negative slack (TNS), which sums up all the negative slack across the circuit. This metric indicates the overall severity of timing violations and helps prioritize timing optimization efforts. (4) Total power prediction: Estimating the total power consumption of the circuit, to assess the energy efficiency. (5) Total area prediction: Evaluating the total silicon area required implement the circuit, which is critical for determining the physical feasibility and cost. Please note that the slack prediction task is directly evaluated at the sub-circuit level, whereas the other four tasks are ultimately evaluated on the entire circuit design. Moreover, we discuss the potential applications of CircuitFusion in multi-clock circuits in Appendix G, as well as optimization tasks and RTL generation in Appendix F, highlighting its adaptability and future research directions.
Evaluation metrics. We evaluate the accuracy with regression metrics including correlation coeffi- cient (R) and mean absolute percentage error (MAPE) between labels and predictions.
Baselines. We comprehensively compare CircuitFusion against SOTA methods from diverse do- mains, including hardware task-specific solutions, general text encoders, and software code en- coders. Hardware solution baselines include task-specific supervised methods RTL-Timer (Fang et al., 2024a) and MasterRTI, (Fang et al., 2024b), as well as the self-supervised pre-trained circuit encoder SNS v2 (Xu et al., 2023). Software solution baselines include recent pre-trained software code encoders, including CodeSage (Zhang et al., 2024), the encoder from CodeT5+ + (Wang et al., 2023a), and UnixCoder (Guo et al., 2022a), multimodal code encoder. These models have an input token limit of 1024, which prevents them from directly processing the longer HDL code, and therefore we crop the imput HDL code to fit this token limit. As for the general text encoders, we use NV-Embed-Ve (Lee et al., 2024), with 32k input token capacity, one of the top perfffrfrriin text encoders on the MTEB LeaderBoard (Muennighoff et al., 2022).
4.3 SUPERVISED FINE-TUNING FOR DESIGN QUALITY TASKS
We first compare CircuitFusion against the aforementioned baselines across the five design quality prediction tasks. The detailed experimental results are demonstrated in Table 2.
Table 2: Comparison between CircuitFusion and baseline methods across all five design quality prediction tasks. CircuitFusion consistently outperforms all baseline methods, including hardware solutions, general LLM-based text encoders, and software code encoders across all tasks.
Slack
WNS
TNS
Power MAPE
Area
Type
Method
R
MAPE
R
MAPE
R
MAPE
R
R
MAPE
RTL.Timer
17%
0.9
16%.
0.9h
25%
N/A
N/A
Hardware
MusterRTL
N/A
0.89
18%
0.94
28%
0.89
26%
0.98
16%
Solution
SNS v2
N/A
0.82
22%
N/A
0.76
28%
0.93
25%
Text Encoder
NV-Embed-vl
N/A
0.49
17%
0.97
55%
0.85
44%
0.86
24%
UnixCoder
N/A
0.46
21%
0.95
44%
0.83
29%
0.85
26%
Software Code
Co Encoder
N/A
0.55
21%
0.63
43%
0.49
0.45
39%
Encoder
CodeSage
N/A
0.23
25%
0.86
45%
0.8
38%
0.77
41%
Ours
CireuitFusion
0.87
12%
0.91
11%
0.99
15%
0.99
13%
0.99
11%
Overall performance summary. CircuitFusion consistently outperforms all the hardware solutions, general text encoders, and software code encoders across all five design quality prediction tasks. Its high correlation and low MAPE demonstrate its effectiveness and reliability in learning HDL code representations. Compared to SOTA baseline methods, CircuitFusiin achieves a MAPE improve- ment of 5% for slack, WNS, and area prediction, 10% for TNS, and 13% for power prediction.
Unlike hardware solutions that often require intensive, task-specific modifications, CireuitFusion serves as a fiexible foundation for multiple tasks, allowing fine-tuning without significant adjust- ments, which enhances its versatility, Moreover, the significant performance gap between CircuitFu- sion and text/software- based models highlights the importance of building hardware-spectee models like CircuitFusion for tasks within the hardware design realm.
We conduct ablation studies to demonstrate the effectiveness of each modality and proposed strategy, as shown in Figure 1, with detailed evaluations provided in Appendix E.3. Furthermore, apply our strategies to baseline methods and assess the improvements in Appendix E.4.

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4.4 ZERO- SHOT RETRIEVAL AND REGRESSION
Compared with the existing hardware solutions, CircuitFusion is the first method to support zero-shot circuit quality prediction due to our innovative retrieval-augmentedd method. We provide a detailed evaluation of how the number of retrievals affects the prediction results, and we also compare with the LLM-based and software code encoders. As shown in Table CircuitFusion consistently performs best at top-1 retrieval for all tasks, achieving the lowest MAPE across the board. According to this result, we set the retrieval number in our retrieval-augmeen to minimize error. Additionally, this result demonstrates that the encoded circuit embeddings contain rich semantic circuit information, enabling effective search and differentiation of functionally simi- lar circuits. In contrast, other general text or software code encoders struggle to identify functionally prop-
inference
similar HDL code snippets. This gap highlights the importance of integrating erties into hardware circuit learning. We also perform detailed few-shot fine-tuning experiments by increasing the training data from 0% (i.e., zero-shot) to 100%, as demonstrated in Appendix E.2.
Table 3: MAPE(%) ) results of the zero-shot top-k similar circuit retrieval.
Slack
Sub-circuit Power
Sub-circuit Area
Method
top-1
top-3
top-5
top-
10p-10
top-1
top-3
top-5
top-10
top-1
top-3
top-5
top-10
LLM Encoder
51
35
33
34
92
90
90
90
90
88
88
88
UnixCoder
56
36
36
36
90
89
90
91
89
88
89
89
CodeTS+ Embedding
57
35
36
88
87
89
90
87
86
87
88
CodeSage
50
36
36
89
87
88
91
88
85
86
87
Ours
21
22
23
26
36
40
42
53
35
40
42
51
4.5
DOWNSTREAM PERFORMANCE SCALING WITH MODEL SIZE AND DATA SIZE
In Figure 6, study how the downstream task per- formance of CircuitFusion scales with both model size and pre-training data size. The plot shows the
Model Size
- Data Size
Avg. MAPE (9%)
25
25%
average performance across all five design quality
50%
prediction tasks after fine-tuning. The results indi- cate that increasing both model size and data size significantly enhances performance. demonstrating the scalability of CircuitFusion. This indicates the potential that further scaling of both model and data size in the future could lead to even greater improve- ments in accuracy and generalization.
20
270M
350M
100%
10
500M
Scaling Up
Figure 6: On the downstream task perfor- mance scaling with pre-trained CireuitFusion model size and data size.
Specifically, when the model size is increased from 270M to 500M parameters, the error decreases from 19% to 12%. This trend shows that larger models are able to capture more complex structural and semantic details from the circuit data, leading to better performance. Similarly, scaling the data size also leads to noticeable reduction in error. Similarly, scaling the pre-training data size from 25% to 100% (i.e., 7k RTL sub-circuits) of the dataset reduces the error from around 24% to 12%, highlighting the importance of using large, diverse circuit dataset for pre- mraitrinn We also provide model size statistics for the baseline methods as comparison in Appendix E.
CONCLUSION AND FUTURE WORK
In this work, we propose CireuitFusion, the first multimodal fusion and implementation-awarc cir- cuit encoder tailored for hardware circuits. We introduce four innovative strategies that leverage the unique properties of circuits, spanning from cireuit preprocessing to CircuitFusion pre-training and application in downstream tasks. CircuitFusion is evaluated across five design quality prediction tasks, where it consistently achieves state-of-the-art performance after fine-tuning and even enables zero-shot inference.
Limitations and future work. While CircuitFusion is already trained in several different bench- marks and outperforms the existing hardware task-specific approaches, the amount of training data used is still limited compared to what would be ideal for a robust circuit foundation model. For future work. we aim to explore circuit data generation techniques and further scale CireuitFusion by pre- pre-trainin training on larger sets of synthetic circuit data. We will also release large-scale CircuitFusion as foundation model support different tasks for other users.
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ACKNOWLEDGEMENT
This work is supported by National Natural Science Foundation of China 62304192, Hong Kong Re- search Grants Council (RGC) CRF Grant C6003-24Y, and ACCESS AI Chip Center for Emerging Smart Systems, sponsored by InnoHK funding, Hong Kong SAR.
REPRODUCIBILITY STATEMENT
We provide references to relevant sections and materials to assist readers and researchers in repli- cating results.
Dataset description: All datasets used our experiments are from open-source benchmarks. A summary of these datasets is available in Appendix A, with demonstration example shown in Ap- pendix B.2. Detailed preprocessing methods are described in Appendix B, including the different circuit modality generation, sub-circuit generation, and downstream task label collection. The cor- responding scripts can be found in our open-source repository.
Open access CircuitFusion code: The source code for CircuitFusion publicly available http://kuuttziiiiiee conouusttzhiii haalllaao///rruuuuaaaaaa iinsion ion. The repository includes
at: https: / scripts with step-by-stee by-step instructions to replicate the primary results presented in this paper.
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A MORE ON CIRCUIT HDL DATASET
This section provides an overview of the various circuit HDL datasets used in our work, includ- ing ITC*99, OpenCores, VexRiscv, and Chipyard. These datasets offer diverse designs that span range of hardware implementations, enabling comprehensive benchmarking of CircuitFusion across different circuit design tasks.
A.0.1 ITC'99
The ITC'99 benchmark suite (Corno et al., 2000) is a widely used collection of hardware circuit designs, primarily designed for logic synthesis and verification. ITC'99 provides diverse designs ranging from simple combinational logic to more complex sequential circuits. VHDL
A.0.2 OPENCORES
The OpenCores repository (URL, b) offers open- source hardware designs. including a wide variety of digital systems, such as CPUs, memory controllers, communication protocols, etc. OpenCores is rich dataset for benchmarking HDL models because of its diverse collection of designs, which range from small, simple circuits to large, complex ones, Its open-source nature allows for flexibility in circuit modification, making it ideal for research and development in hardware design.
A.0.3 VEXRISCV
VexRisev (VexRisev, 2022) is open-source, RISC-V V compliant CPU core designed using Spinal- HDL. This dataset focuses on CPU design and features a highly configurable architecture, allowing for variations in pipeline stages, instruction sets, and optimizations. The VexRiscv dataset is partic- ularly useful for testing the scalability and flexibility of models in handling CPU-level design tasks, making it a valuable resource for benchmarking models like CircuitFusion on processor design tasks.
A.0.4 CHIPYARD
Chipyard (Amid et al., 2020) a comprehensive framework for building RISC- V-bsed system-on- chip (SoC) designs. It includes a collection of CPU cores, accelerators, memory systems, and I/O components, offering a complete design ecosystem for hardware developers. The Chipyard dataset enables testing at the SoC level, providing a broad set of circuits with varying complexities and design objectives.
B
MORE ON CIRCUIT DATA PREPROCESSING
B. DATASET AND FINE-TUNING LABEL COLLECTION
The labels for fine-tuning (i.e., post-synthesis PPA metrics) are generated through an industrial- standard logic synthesis process applied to benchmark RTL designs. In the open-source bench- marks, the HDL code of RTL circuits is provided, where the RTL stage describes the functional behaviors of the circuit. We then use the EDA tool Synopsys Design Compiler automatically synthesize the RTL circuits into gate-level netlists. The netlists represent real circuit implementa- tions, consisting of logie gates (e-g., ADD, INV, AND, etc.) and registers (DFF). The synthesis process is performed with the open-source NanGate 45nm technology library (URL, a). Following the synthesis process in our baseline method (Fang et al., 2023), we use the "compile." e_ultra" command in Design Compiler to ensure that the synthesized netlists achieve high-quality PPA met- rics at the Pareto frontier, with minimal variance across different configurations and optimization objectives. The design quality metrics of netlists are then obtained through Synopsys Prime Time after synthesis, including slack each register and WNS, TNS, total power, and total area for each RTL. design.
B.2 MULTIMODAT. AND MULTI-STAGE CIRCUIT: A CASE STUDY
In this subsection, we provide detailed example demonstrating the three modalities of RTL circuits.
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Figure 7: An example for multimodal circuit
B.2.1 HDL CODE
As shown in Figure 7a, the HDL code for each sub-circuit is directly used as one of the input modalities, capturing the functional description of the circuit's behavior at the RTL stage. In this Verilog HDL code, module represents an entire sub-cireuit, where input and output specify the primary signals, wire connects the internal signals, ass assign represents combinational logic operations, and the always block triggered by clock signal defines the behavior of sequential registers.
B.2.2 STRUCTURAL GRAPH
Each sub-circuit HDL code is parsed into abstract syntax tree (AST), which is then used to con- struct a control data flow graph, following similar process Fang et al. (2023). As demonstrated in Figure 7b, the nodes represent sequential registers and combinational operators (e.g., AND, ADD, EQUAL, MUX), while the wires connecting elements in the HDL code serve as the edges between these nodes.
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B.2.3 FUNCTIONALITY SUMMARY
We employ GPT-4o (Achiam al., 2023) from Open-Al summarize both the functionality and the implementation details of each sub-circuit HDL code. An example generated summary is illustrated in Figure 7c. A sub-cireuit contains only combinational logic for a single register within a single clock cycle, making it simpler for the LLM to analyze without dealing with the complex sequential state transitions of the entire circuit.
B.2.4 NETLIST GRAPH
We follow similar widely adopted method (Wang et al., 2022) to convert netlists into the graph format. Specifically, register flip-flops (FF) and logic gates (e.g., AOI, INV, FA, AND) are treated the nodes, and the wires connecting these gates form the edges of the graph.
B.3 SUB-CIRCUIT GENERATION ALGORITHM
We convert the HDL code into sub-circuit code snippets and the circuit graph into corresponding sub-gree graphs, using the same sub-circuit generation method for both modalities to ensure functional alignment. The detailed splitting algorithm is provided in Algorithm 1. Specifically, for each reg- ister, we apply a breadth-first search starting from that register, backtracking through all connected combinational logic until reaching the related input/output registers. This process is highly paral- lelized within design, ensuring minimal runtime.
Algorithm 1 Sub-circuit generation(s)
1: V {s)
Set of visited nodes > Queue with start node Set registers and inputs
2: Q <- {8)
3: R ++0 0
4: while Q + 0 do
5:
4 dequeue Q for all E u.outgoing do
Current node
6:
7:
if typpe(v) freg, in) then R - (v)
8:
Add register/input to set D Skip to next node
9:
continue
10:
if v & V then
11:
Q QU(
Add unvisited node queue >> Mark node as visited Set parent node
12:
V
v.setParent( v
14:
return R
> Return set of all registers and inputs
C IMPLEMENTATION OF CIRCUITFUSION
C.I MODEL HYPERPARAMETERS
We first detail the hyperparameters for the proposed unimodal encoders: For the Graph encoder, we train a 7-layer graph transformer Graphormer (Ying et al., 2021) from scratch to capture the complex relationships in circuit graph semantics and structure. This encoder uses graph positional encodings supporting up to 256 in-degrees and out-degrees for centrality encoding, a maximum distance of 5 for spatial encoding, and an edge dimension of 12. It produces graph embeddings with a dimension of 768. The node features are represented by one-hot encoding of the node type, and the edge features are based on one-hot encoding of edge types, determined by the types of connected nodes. The encoder has a hidden dimension of 256 and utilizes 3 attention heads. For the Code encoder, we employ frozen LLM-based general text encoder NV-Embed-Vi (Lee et al., 2024), which handles maximum input size of 32K tokens. This model is based Mistral-7B-vol and was ranked No. 1 on the Massive Text Embedding Benchmark (MTEB) as of May 24, 2024. generates embeddings with dimension of 4096, which then linearly projected to 768. As for the Summary encoder, is initialized using the first layers of BERT hase (Devlin, 2018), following the setup in (Li et al., 2021).
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Retrieved Quality Metrics
Regression
concat
Model
Pre-trained CircuitFusion
[
(a) Sub-eircuit-lese level inference.
Retrieved
Quality Metrics
(sum)
SC
SC2
Pre-trained CircuitFusion
[C]
xM (sum)
Regression Model
:
SCu
Circuit Feature
concat
(b) Circuit-leve inference.
Figure 8: Retrival-augmented inference implementation for tasks at different granularities.
For the multimodal fusion encoder, we initialize it with the last 6 layers of BERT base- The fusion encoder equipped with cross-attention mechanisms to enable the effective fusion embeddings generated from the three unimodal encoders.
For the auxiliary netlist encoder, since graph transformers struggle with large and bit- bit-blasted netlist graphs, instead use 3-layer GraphSAGE (Hamilton et al., 2017) GNN with a hidden dimension of 256. encodes the netlist sub-circuit graphs into embeddings 768 dimensions.
C.2 SELF-SUPERVISED PRE- TRAINING TASKS IMPLEMENTATION
For masked graph modeling on both RTL and netlist sub-circuit graphs (used in Task #1 and netlist encoder), adopt approach inspired by GraphMAE (Hou al., 2022). Specifically, 30% of the nodes in both the RTL and netlist graphs are randomly masked and reconstructed during each training epoch. A three-layer MLP with hidden dimension of 256 is used to reconstruct the node types. Mean Squared Error (MSE) loss is applied to minimize the error between the original node type vectors and the reconstructed outputs, with the node types represented using one-hot encoding.
For the contrastive learning tasks (i.e., Task #1, #2, and #4), we utilize the InfoNCE loss function across all contrastive schemes. To balance the contributions of the different contrastive schemes, assign an intra-modal weight of 1.0, while the cross-modal and implementation-awwan aware weights are to 0.2. The InfoNCE loss is formulated follow:
exp (sim(E,
NCE(E,E*,ET)
log exp (sim((E,E))) ΣE- exp (sim(E,E~)/7)
(8)
where 7 is the temperature scaling parameter that controls the sharpness of the similarity scores, E represents the circuit embeddings with positive samples (E+) and negative samples (E-). temperature parameters are set to 0.3.
For the multimodal fusion tasks, including masked summary modeling and mixup embedding- summary matching, we adhere to the widely adopted tasks as described in (Li et al., 2021; 2022a; 2023a).
C.3 NETLIST ENCODER IMPLEMENTATION
The auxiliary netlist encoder is pre-trained using the graph modality gate-level netlists, as these netlists are flattened and contain limited semantics compared to RTL. The models and pre-training tasks are adapted from those in the graph encoder of CircuitFusion, with two key tasks: (1) Masked Graph Modeling: This task reconstructs the gate-level netlist nodes (e.g., logic gates) rather than RTL operators. (2) Graph Contrastive Learning: Positive samples are generated through Boolean equivalent transformations ensuring structural variations retain functionality.
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C.4 TRAINING HYPERPARAMETERS
During the pre-training phase, the four self-supervised tasks are trained simultaneously for 50 epochs, with total training time of approximately 20 hours. We GELU as the activation func- tion and set the batch size to 128. For optimization, we select Adam W, known for its ability to handle large-scale data effectively. The learning rate is warmed up to 1e-4 during the first 1000 iterations, after which it follows cosine decay schedule, gradually reducing to 1e-5. This sched- ule ensures smooth convergence while avoiding abrupt gradient updates that could destabilize the training process.
In the fine-tuning phase, the pre-trained CircuitFusion model frozen to preserve the learned rep- resentations, and lightweight models are applied to adapt to specific downstream tasks. To comple- ment the learned sub-circuit representations, we integrate design-level features, such as the number of different operator types, to capture the overall design scale. Specifically, we explore various lightweight models, including additional MLP layers, GNN layers, and tree-based models like XG- Boost. XGBoost consistently delivers the best performance due to its capability to efficiently handle the concatenation of sub-circuit embeddings with design-level features, treating them as tabular data.
Regarding the model development time, pre-training the model for 50 epochs takes approximately 10 hours using Nvidia A4000 GPUs or around 32 hours on a single A4000 GPU. Fine-tuning is significantly faster, taking only around minutes per task. Fine-tuning runtime efficiency is key advantage of our method compared to task-specific solutions (i.e., our baselines). These task-specific methods often require time-consuming task-related feature engincering or model modifications, and lack generalizability to other tasks. In contrast, our pre-trained model allows developers to efficiently fine-tune for various design quality evaluation tasks, ensuring both flexibility and speed.
C.5 RETRIEVAL- BASED INFERENCE IMPLEMENTATION
Our proposed cetrieval-augmenter inference process for CircuitFusion is illustrated in Figure 4. It designed for two types of downstream tasks: sub-circuit-level and circuit-level.
Sub-cireuit-level inference: For each sub-cireuit, the pre-trained CircuitFusion encoder generates the corresponding multimodal embedding. We employ a retrieval process to fetch the most function- ally similar sub-circuits from vectorstore that contains previously seen circuits. These retrieved sub-circuits provide their design quality metrics, which are directly concatenated with the embed- ding generated by CircuitFusion. The concatenated feature vector is then fed into a regression model to predict the final design quality metric for the sub-circuit.
Cireuit-level inference: At the circuit-level, the entire design is composed of multiple sub-circuits. Each sub-cireuir is individually encoded by the CircuitFusion encoder, producing embeddings. Sim- ilar to the sub-cireuit-leve inference, we retrieve quality metries for each sub-circuit from the vec- torstore. The embeddings and retrieved quality metrics for all sub-circuits are added to generate comprehensive circuit-level feature vector. We also concatenate this with design-level features (e.g., operator counts) to reflect the overall scale of the design. The combined feature vector is then fed into a regression model to predict circuit-level design quality metrics.
C.6 BASELINE METHOD IMPLEMENTATION
For all the baselines, we directly employ the gper-sourced code provided in their papers available. For methods without open-source code, we carefully re-implement their approaches based on their published descriptions to ensure fair comparison. Regarding the comparisons with baseline meth- ods, we use the same pre-trained CircuitFusion model across all tasks, only fine-tuning different task-specific downstream models, following the standard gretrain-finetur paradigm.
D EXPERIMENTAL SETTINGS
Our CicouitEncoder is implemented in Python, utilizing Pytorch and DGL (Wang, 2019) for self- supervised pre-training and model implementation. Experiments conducted on server equipped with a 2.9 GHz Intel Xeon(R) Platinum 8375C CPU and 512 GB RAM, with four NVIDIA A4000 GPUs for model pre-training.
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E
MORE EXPERIMENTAL RESULTS
E. BASELINE MODELS (EXTENDED)
We summarize the baseline model size compared with CircuitFusion in Table 4.
Table 4: Pre-trained baseline model statistics.
Model
Model Size
Embedding Dim.
Max Token
Training Data Source
NV-embed-VI
7B
4096
32768
Various text
UnixCoder
125M
768
1024
Software code
Code T5+ Encoder
110M
768
1024
Software code
CodeSage
1.3B
768
1024
Software code
CircuitFusion
500M (+7B frozen)
768
32768
Hardware circuit
E.2 ZERO-SHOT AND FEW-SHOT INFERENCE (EXTENDED)
Tables to illustrate the performance of CircuitFusion compared to SOTA baselines for zero- shot and few-shot learning on five design quality prediction tasks. The baseline method is selected as the nop-perfomming model from all baselines in Table 2. The x-axis represents the fraction of training data used, ranging from zero-shot (0%) full-shot (100%), while the y-axis shows the MAPE. These results demonstrate CircuitFusion's effectiveness in both zero-shot and few-shot set- tings, making it versatile and reliable model for etrly-stage design quality prediction tasks, where access to large datasets is often restricted.
Zero-shot. Only CircuitFusion supports this zero-shot capability due our innovative retrieval- augmented method. While the baselines do not provide predictions the zero-shot setting, Circuit- Fusion achieves reasonable prediction accuracy without any training data, demonstrating its unique advantage.
Few-shot. CircuitFusion is particularly effective when training data is limited, which is crucial given the data availability challenges in hardware circuit design. As more training data is introduced (from 1/8 to full-shot), CircuitFusion consistently outperforms the baselines across all tasks, show- ing steeper performance improvements. It achieves lower MAPEs in nearly all cases, highlighting its superior ability to generalize and learn with minimal data.
Table 5: Few-shot results (MAPE) slack prediction -Sub-Cirruit-lever
Task: Slack
100%
50%
25%
13%
0%
SOTA (RTL-Timer)
15%
16%
19%
30%
N/A%
CircuitFusion 12%
14%
16%
19%
21 1%
Table 6: Few-shot results (MAPE) on WNS prediction (Circuit-level).
Task: WNS
100%
50%
25%
13%
0%
SOTA (RTL-Tiie Timer)
16%
29%
36%
43%
N/A
CircuitFusion 11%
17%
18%
25%
27%
Table 7: Few-shot results (MAPE)
TNS prediction (Cireuit-level).
Task: TNS
100%
50%
25%
13%
0%
SOTA (RTL-TIE Timer)
25%
35%
49%
74%
N/A
CircuitFusion 15%
24%
41%
52%
59%
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Table 8: Few-shot results (MAPE) on Power prediction (Cireuit-level).
Task: Power
100%
50%
25%
13%
0%
SOTA (MasterRIL) 26%
37%
46%
55%
N/A
CircuitFusion 13%
34%
43%
54%
62%
Table 9: Few-shot results (MAPE) on Area prediction (Circuit-level),
Task: Area
100%
50%
25%
13%
0%
SOTA (MasterRTI)
16%
33%
46%
56%
N/A
CircuitFusion
11%
30%
45%
51%
58%
E.3 ABLATION STUDY
Effectiveness of proposed strategies. Figure shows our ablation study by removing key com- ponents employed in CircuitFusion strategies. Removing the sub-circuit generation severely limits CircuitFusion's ability handle large-scale circuits, leading to the most significant error increases across all tasks. Without this splitting, the model struggles to capture fine-grained circuit details, which is essential for tasks like slack prediction that require sub-circuit-level embeddings. We fur- ther assess the impact of each pre-training objective by selectively removing them. In every case, this leads to clear rise in MAPE, indicating the importance of each pre-training task in enhancing both structural and semantic circuit understanding. Excluding retrieval-augmented inference results in substantial increase in MAPE across all tasks. This highlights the significant role retrieval plays in enhancing fine-tuning performance by utilizing functionally similar existing circuits references.
30
MAPE
20
15
18
19
23
10
15
25
19
N/
Slack
WNS
TNS
70
22
15
Power
Arca
CrcuitFusion
w/o
stoww matching tts
algen
modality
w/o MSM cM2oel
w/o retrivval
Figure 9: Ablation study on the effectiveness of proposed strategies.
Impact of circuit modality. In addition to the ablation study that evaluates the use of each modality individually in Figure 1, we also conduct an extended study on the selective removal each modal- ity. This study aims to further quantify the contribution of each modality (i.e., code, graph, and summary) to the model's overall performance. Specifically, when either the hardware code or graph modality is removed, there is significant rise in prediction error across all tasks, highlighting their critical role in capturing both the structural and functional details of circuits. The graph modality, in particular, contributes more, it contains rich structural information essential for circuit repre- sentation. These results demonstrate the necessity of leveraging modality fusion to fully capture the diverse characteristics of circuits.
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40
MAPE
20
17
14
Slack
WNS
TNS
Power
Area
CircuitFusion
w/ graph modality
w/o code modality
only graph
only code
Il only summary
Figure 10: Ablation study on the impact of circuit modalities.
Table 10: Evaluation results when applying strategy SI and S4 to other pre-trained encoders.
Slack
WNS
TNS
Power
Area
Method
MAPE
R
MAPE
R
MAPE
R
MAPE
MAPE
N/A
0.49
26%
0.97
55%
0.85
44%
0.86
24%
NV-Embed-v1 w/ S1&4
0.85
15%
0.81
17%
0.95
27%
0,99
20%
0.97
17%
CodeSage
or w/ S1&4
N/A
0.23
21%
0.86
45%
0.8
38%
0.77
41%
0.84
14%
0.9
25%
0.95
24%
0.96
18%
0.96
17%
ori CodeTS+ Encoder
N/A
0.55
30%
0.63
43%
0,49
46%
0.45
39%
w/ S1&4
0.83
14%
0.8
21%
0.94
24%
0.95
19%
0.93
21%
UnixCoder
ori w/ S1&4
N/A
0.46
21%
0.95
44%
0.83
29%
0.85
26%
0.84
14%
0.83
20%
0.96
22%
0.96
18%
0.96
16%
CircuitFusinn
0.87
12%
0.91
11%
0.99
15%
0.99
13%
0.99
11%
E.4 APPLYING PROPOSED STRATEGIES TO BASELINE ENCODERS
As shown Table 10, applying the sub-circuit generation (S1) and retrieval-augmented inference (S4) strategies to other pre pre-trained baseline encoders significantly boosts their performance across all tasks. By encoding sub-cireuits instead of the entire circuit, all baseline methods are now able to handle the fine-grained slack prediction task, which they originally could not support.
For example, the LLM-based encoder NV-Embed-v1, despite its ability to process 32k tokens, strug- gles encode entire circuit code sequences. When enhanced with SI and S4, it achieves notable reduction in MAPE for WNS (from 26% to 17%), TNS (from 55% to 27%),, power (from 44% to 20%), and (from 24% to 17%). Similarly, other software code encoders, such as CodeSage, CodcTS+ Encoder, and UnixCoder, also benefit significantly from these strategies. This shows that S1 and S4 not only improve fine-tuning accuracy but also enhance generalization across various design quality prediction tasks. Despite these improvements, CircuitFusion still outperforms all baselines, underscoring the effectiveness of perdware-speciffe pre-training strategies.
E.5 DISCUSSTON ON DIFFERENT MULTIMODAL FUSTON IMPLEMENTATIONS
In CircuitFusion, we propose summary-centric fusion strategy, where graph and code embeddings, capturing detailed structural and semantic information, are first mixed. The Fusion Encoder then combines these mixup embeddings with summary embeddings generate the final circuit represen- tation. To evaluate the effectiveness of this strategy, we implemented multiple variants of CircuitFu- sion, including (1) other modality-centrie (i.e., graph-centric and code-centie cedee--entrc),, (2) summary- partial fusion (i.e., summary+graph and sunmary+code), (3) simple alignment and inference with one modality (i.e., aligned graph, aligned code, and aligned summary), and (4) only single modality (i.c., graph, code, summary).
The experimental results, summarized Table 11, demonstrate the superiority of CircuitFusion's summary-centric fusion strategy. It consistently outperforms other modality-centro partial fusion, simple alignment, and single-modality approaches across all metrics, with significant improvements over SOTA baselines. These findings underscore the effectiveness of combining detailed structural and semantic information (from graph and code) with high-level functional insights (from summary) for comprehensive circuit evaluation.
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Table 11: Evaluation results (MAPE%) for different multimodal fusion implementation variants.
Method
Slack
WNS
TNS
Power
Area
Avg.
Variant Type
CircuitFusion
12
11
15
13
11
12
aligned graph-centric
17
12
22
16
13
13
1. Other modality-centir
aligned code-centric
20
16
11
16
aligned summary+graph
14
13
15
15
2. Partial fusion
aligned summary +code
22
24
22
15
17
20
aligned graph
15
13
17
19
14
16
3. Only modality alignment
aligned code
25
26
27
20
23
aligned summary
16
only graph
16
28
19
16
14
19
4. Single modality
only code
25
26
27
20
17
23
only summary
18
39
22
SOTA Baselines
17
16
25
26
Table 12: Evaluation results on applying CircuitFusion for multi-clock circuit designs.
Test Circuil
Slack
WNS
TNS
Clock
Design
Frequency
R
MAPE
MAPE
MAPE
itel
I,5GHz
0.91
6%
5%
8%
Single-Clock
chipyardl
1.5GHz
0.88
12%
16%
15%
itcl
1,5GHz
0.91
6%
5%
8%
Multi-Clock
chipyard1
IGHz
0.89
13%
155
16%
F APPLING CIRCUITFUSION FOR MORE AGILE CHIP DESIGN PROCESSES
In addition to the various design quality tasks supported by CircuitFusion, here also discuss the application scenario of CircuitFusion for the agile chip design process. Inspired by (Fang et al., 2024a), these predictions can be further applied for early timing optimization, such setting fine- grained timing optimization options for logic synthesis. Our better prediction results can seamlessly support the optimization method in [4] and would enable similar
better optimization results.
Furthermore, a recent trend involves leveraging LLMs for direct RTL code generation and optimiza- tion (Liu et al., 2023b; Yao al., 2024). Combining the multimodal RTL embeddings captured by our CircuitFusion encoder with such code generation decoders opens up a promising future research direction for designing and optimizing RTL code more efficiently.
G APPLING CIRCUITFUSION FOR MULTI-CLOCK CIRCUIT DESIGNS.
Currently, most Al-based timing evaluation methods (Wang al., 2023b; Guo et al., 2022b; Fang et al.. 2024a), including ours, primarily focus on circuits within single clock domain (i.c., syn- chronous circuits). Multi-clock designs were explicitly addressed this work. However, our proposed S1 sub-cireuit generation strategy inherently divides circuits into register cones by back- tracing logic to their driving registers. This process captures state transitions and all timing paths within each register cone. For multi-clock designs, timing predictions can be handled within indi- vidual clock groups by fine-tuning the model with timing labels specific to each group.
To demonstrate this capability, we combine two circuits from separate timing groups into a single design and perform logic synthesis. Then our CircuitFusion fine-tuned with different clock fre- quencies is used to predict the timing metric within each timing group. The prediction results with CircuitFusion are shown in Table 12. CircuitFusion achieves similar timing prediction accuracy to that observed in single-clock scenarios. However, challenges such signal transfers across asyn- chronous clock domains (i.e., clock-domain crossing) are significantly more complex and currently fall beyond the scope of method. This remains promising direction for future exploration.
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Reviews:
[{"review_id": "w2dgHIW8FA", "reviewer": "Reviewer_uzeD", "summary": "This paper introduces a multi-modal representation method for agile digital IC design. \nEvaluations show that the proposed method achieves significant performance improvement over several SOTA methods.", "questions": "Q1: How do you label data for fine-tuning?\n\nQ2: How long does it take for pre-training and fine-tuning the model?\n\nQ3: How are the correlation coefficient (R) and mean absolute percentage error (MAPE)in Table 2 obtained? I.e, Based on a single inference or multiple inferences?", "limitations": "", "rating": 6, "confidence": 5, "soundness": 3, "presentation": 3, "contribution": 3, "strengths": "The paper proposes to use multimodal representations to estimate digital IC performance efficiently. This strategy is novel as compared to previous LLM-based methods.\n\nThe technique details on how to encode each modality and fuse modalities are elaborated clearly.\n\nThe paper comprehensively evaluates multiple tasks and compares them with many SOTA methods to show the impressive performance of the proposed method.\n\nAn ablation study is also performed to show the impact of each individual modality on the estimation error.", "weaknesses": "It is unclear why a summary-centric fusion is used to fuse the three modalities, lacking quantitative support.\n\nIt is unclear how the netlist encoder is pre-trained.\n\nThe comparisons with previous methods are unfair since the reported results are not based on the same number of model parameters across all baselines.", "quality": null, "clarity": null, "significance": null, "originality": null, "strengths_and_weaknesses": "", "was_revised": false, "final_justification": "", "rebuttal": "", "claims_and_evidence": "", "methods_and_evaluation_criteria": "", "theoretical_claims": "", "experimental_designs_or_analyses": "", "relation_to_broader_scientific_literature": "", "essential_references_not_discussed": "", "other_strengths_and_weaknesses": "", "other_comments_or_suggestions": "", "questions_for_authors": "", "summary_of_paper": "", "summary_of_recommendation": "", "technical_quality": "", "clarity_of_presentation": "", "potential_impact": "", "robotics_focus": "", "quality_of_limitations": "", "questions_for_rebuttal": "", "reasons_to_accept": "", "reasons_to_reject": "", "questions_to_authors": "", "extra_scores": {}}, {"review_id": "zoarzBUSry", "reviewer": "Reviewer_kA13", "summary": "This paper introduces an approach to circuit representation learning using multimodal fusion and implementation-aware alignment.", "questions": "* For sequential logic, how well does it handle logics with multiple clocks? Can it optimize such tasks?", "limitations": "", "rating": 6, "confidence": 1, "soundness": 2, "presentation": 3, "contribution": 3, "strengths": "* The paper is structured well and easy to follow. All training steps and the proposed methodology is clearly illustrated with representative figures, these make it easy to follow and understand the proposed approach and results.\n* Evaluations are comprehensive and comparison are done against many recent methods. \n* The approach of this fusion approach that overcomes the hardware unique (P1 to P4) looks novel and interesting.", "weaknesses": "* The dataset contains only 41 RTL designs, this might not be representative of the entire space. It would be nice to demonstrate the effectiveness of the proposed method on a wider range of dataset.", "quality": null, "clarity": null, "significance": null, "originality": null, "strengths_and_weaknesses": "", "was_revised": false, "final_justification": "", "rebuttal": "", "claims_and_evidence": "", "methods_and_evaluation_criteria": "", "theoretical_claims": "", "experimental_designs_or_analyses": "", "relation_to_broader_scientific_literature": "", "essential_references_not_discussed": "", "other_strengths_and_weaknesses": "", "other_comments_or_suggestions": "", "questions_for_authors": "", "summary_of_paper": "", "summary_of_recommendation": "", "technical_quality": "", "clarity_of_presentation": "", "potential_impact": "", "robotics_focus": "", "quality_of_limitations": "", "questions_for_rebuttal": "", "reasons_to_accept": "", "reasons_to_reject": "", "questions_to_authors": "", "extra_scores": {}}, {"review_id": "vUZCgyBKOD", "reviewer": "Reviewer_KB11", "summary": "This paper proposed a multimodal and implementation-aware circuit encoder. It encodes circuits into general representations that support different downstream circuit design tasks with three modalities: hardware code, structural graph, and functionality summary. CircuitFusion demonstrates excellent generalizability and the ability to learn circuits’ inherent properties compared to state-of-the-art supervised methods in the empirical study.", "questions": "Could you provide examples from related work where multimodal models have been successfully used for evaluation tasks, particularly in hardware or software domains? Additionally, could you elaborate on the specific advantages that a multimodal approach offers for circuit evaluation tasks compared to traditional unimodal methods?", "limitations": "", "rating": 6, "confidence": 3, "soundness": 3, "presentation": 3, "contribution": 3, "strengths": "• This paper proposes the first multimodal fused and implementation-aware circuit encoder that fuses three modalities (i.e., HDL code, structural graph, and functionality summary). \n• CircuitFusion outperforms state-of-the-art (SOTA) task-specific supervised models in design quality evaluation task empirically\n• CircuitFusion is able to perform few-shot and zero-show inference.", "weaknesses": "• Most existing multi-modality encoders, such as CLIP, seem to be mainly used as a controller for generation, such as stable diffusion text to image generation. This paper, however, uses it as an evaluator, which I personally feel does not fit the purpose. \n• I feel the argument about scalability is not significant enough to consider as one of the strengths. Since deep learning models are naturally scaled with larger datasets, and such large datasets are not available right now and may not be available in the future due to the IP issue, achieving excellent results with limited data is more important than scalability to large but nonexistent datasets.", "quality": null, "clarity": null, "significance": null, "originality": null, "strengths_and_weaknesses": "", "was_revised": false, "final_justification": "", "rebuttal": "", "claims_and_evidence": "", "methods_and_evaluation_criteria": "", "theoretical_claims": "", "experimental_designs_or_analyses": "", "relation_to_broader_scientific_literature": "", "essential_references_not_discussed": "", "other_strengths_and_weaknesses": "", "other_comments_or_suggestions": "", "questions_for_authors": "", "summary_of_paper": "", "summary_of_recommendation": "", "technical_quality": "", "clarity_of_presentation": "", "potential_impact": "", "robotics_focus": "", "quality_of_limitations": "", "questions_for_rebuttal": "", "reasons_to_accept": "", "reasons_to_reject": "", "questions_to_authors": "", "extra_scores": {}}, {"review_id": "OzqsOlB2Cl", "reviewer": "Reviewer_bMDX", "summary": "This paper designs a CircuitFusion pre-training workflow to achieve an implementation-aware representation of RTL codes. The CircuitFusion aligns three RTL modalities(hardware code, structural graph, and functionality summary) with corresponding netlists and encodes them to an embedding vector for RTL design quality evaluation. The paper also presents a retrieval-augmented inference flow to improve fine-tuning and enable zero-shot.\n\nI read the rebuttals and decided to keep my decision.", "questions": "1. This paper regards the performance of synthesized netlists as the RTL quality metrics. However, one RTL code can be synthesized into many gate-level netlists based on different configurations and optimization objectives, can the authors provide a detailed description on the selection of representative gate-level netlists, to represent the true performance of RTL and guide optimization.\n\n2. In Table 3, please explain why the prediction error of CircuitFusion increases with the number of retrievals. \n\n3. There is an inherent issue of information asymmetry between different circuit modalities, and it can be computationally expensive to calculate the similarity and alignment between these features. Can the authors provide more evidence to demonstrate that the summary-centric approach is more effective compared to simple alignment or using other modalities as the central focus?", "limitations": "", "rating": 8, "confidence": 4, "soundness": 3, "presentation": 3, "contribution": 3, "strengths": "1. The CircuitFusion successfully encodes and aligns the hardware code, structural graph and functionality summary of RTL into an embedding vector and achieves SOTA performance. During pre-training, techniques include masked modeling, contrastive learning and mixup embedding summary matching are employed to enhance the model's understanding of circuit functionality.\n\n2. This paper introduces a register-based circuit splitting method to enable fine-grained encoding and detailed representation with low computational complexity and scalability.\n\n3. This paper proposes a retrival-augmented inference method to enable the model to integrate external knowledge effectively, leading to improvements in both zero-shot and few-shot learning scenarios.\n\n4. Sufficient ablation studies and experimental evaluations are conducted to valitate the necessity of the above arrpoachs.", "weaknesses": "1. Regarding the technical novelty of this work, a related work was published on ICCAD 2024, named RTLRewriter [1]. Many techniques are similar to each other. RTLRewriter is a multimodal one that considers manual, code, and notes and also incorporates graph partitioning techniques, retrieval-augmented inference, etc. \n\n2. During zero-shot inference, it is not reliable to simply average the performance metrics of retrieved similar circuits to make predictions. This issue seems to be reflected in the experimental results in Table 3, where the performance decreases with the increased available retrievals. Meanwhile, sufficient circuit data is required when building a VectorStore with quality metrics, which contradicts the concept of zero-shot inference.\n\n3. The CircuitFusion implements summary-centric fusion to achieve alignment with information from other modalities. However, this approach may result in an underrepresentation of structural information or code-level details, which could be particularly important in timing, power and area performance. Additional experiments and explanations are needed to demonstrate the necessity of the summary mode.\n\n4. The downstream applications should be further elaborated. Specifically, how to adjust the RTL design based on the obtained performance predictions warrants more detailed discussion. Currently, this work shows less relevance to the title's concept of 'agile chip design', as it does not adequately illustrate how CircuitFusion can be effectively applied to the optimization of RTL code. Prior works: [1] uses the encoded different modal RTL for new code reconstruction. [2] can notate detailed timing information on HDL and set fine-grained optimization options in the synthesis script for optimization applications.\n\n5. The uploaded source code for CircuitFusion lacks readability and is hard to run. For example, many of the files mentioned in the README do not exist (data_bench, pretrain_model, pos and others).\n\n[1] RTLRewriter: Methodologies for Large Models aided RTL Code Optimization [ICCAD 2024](https://arxiv.org/abs/2409.11414)\n\n[2] Annotating Slack Directly on Your Verilog: Fine-Grained RTL Timing Evaluation for Early Optimization (https://arxiv.org/abs/2403.18453)", "quality": null, "clarity": null, "significance": null, "originality": null, "strengths_and_weaknesses": "", "was_revised": false, "final_justification": "", "rebuttal": "", "claims_and_evidence": "", "methods_and_evaluation_criteria": "", "theoretical_claims": "", "experimental_designs_or_analyses": "", "relation_to_broader_scientific_literature": "", "essential_references_not_discussed": "", "other_strengths_and_weaknesses": "", "other_comments_or_suggestions": "", "questions_for_authors": "", "summary_of_paper": "", "summary_of_recommendation": "", "technical_quality": "", "clarity_of_presentation": "", "potential_impact": "", "robotics_focus": "", "quality_of_limitations": "", "questions_for_rebuttal": "", "reasons_to_accept": "", "reasons_to_reject": "", "questions_to_authors": "", "extra_scores": {}}]

Author rebuttal:

Decision: Accept (Poster)