AnalogGenie: A Generative Engine for Automatic Discovery of Analog Circuit Topologies
Authors: Jian Gao
Weidong Cao
Junyi Yang
Xuan Zhang
Venue: ICLR 2025 Spotlight (2025)
Keywords: Circuit Generation
Application of Generative Models
Electronic Design Automation
Primary area: applications to physical sciences (physics, chemistry, biology, etc.)
TL;DR: A versatile generative model capable of designing topologies for wide range of analog circuits.

Abstract: The massive and large-scale design of foundational semiconductor integrated circuits (ICs) is crucial to sustaining the advancement of many emerging and future technologies, such as generative AI, 5G/6G, and quantum computing.
Excitingly, recent studies have shown the great capabilities of foundational models in expediting the design of digital ICs.
Yet, applying generative AI techniques to accelerate the design of analog ICs remains a significant challenge due to critical domain-specific issues, such as the lack of a comprehensive dataset and effective representation methods for analog circuits.
This paper proposes, $\textbf{AnalogGenie}$, a $\underline{\textbf{Gen}}$erat$\underline{\textbf{i}}$ve  $\underline{\textbf{e}}$ngine for automatic design/discovery of $\underline{\textbf{Analog}}$ circuit topologies--the most challenging and creative task in the conventional manual design flow of analog ICs.
AnalogGenie addresses two key gaps in the field: building a foundational comprehensive dataset of analog circuit topology and developing a scalable sequence-based graph representation universal to analog circuits.
Experimental results show the remarkable generation performance of AnalogGenie in broadening the variety of analog ICs, increasing the number of devices within a single design, and discovering unseen circuit topologies far beyond any prior arts.
Our work paves the way to transform the longstanding time-consuming manual design flow of analog ICs to an automatic and massive manner powered by generative AI.
Our source code is available at https://github.com/xz-group/AnalogGenie.

Published as a conference paper at ICLR 2025
ANALOGGENIE: A GENERATIVE ENGINE FOR AUTO- MATIC DISCOVERY OF ANALOG CIRCUIT TOPOLOGIES
Jian Gao', Weidong Cao², Junyi Yang', Xuan Zhang'
1 Northeastern University, The George Washington University {gao. jian3, yang. juny, xuan. zhang) (hang) www.oe/etttttttennccco (weidong. cao @ggu.
ABSTRACT
The massive and large-scale design of foundational semiconductor integrated cir- cuits (ICs) is crucial to sustaining the advancement of many emerging and fu- ture technologies, such as generative AI, 5G/6G, and quantum computing. Ex- citingly, recent studies have shown the great capabilities of foundational mod- els in expediting the design of digital ICs. Yet, applying generative Al tech- niques accelerate the design of analog ICs remains a significant challenge due to critical domain-specific issues, such as the lack of a comprehensive dataset and effective representation methods for analog circuits. This paper proposes, AnalogGenie, a Generative engine for automatic design/discovery of Analog cir- cuit topologies- the most challenging and creative task the conventional man- ual design flow of analog ICs. AnalogGenie addresses two key gaps in the field: building a foundational comprehensive dataset of analog circuit topology and developing scalable sequence-based graph representation universal to ana- log circuits. Experimental results show the remarkable generation performance of AnalogGenie in broadening the variety of analog ICs, increasing the num- ber of devices within a single design, and discovering unseen circuit topolo- gies far beyond any prior arts. Our work paves the way to transform the long- standing tone-ccngu manual design flow of analog ICs to an automatic and massive manner powered by generative AI. Our source code is available com xz mozz-group/aaae Ana logGenie
INTRODUCTION
Semiconductor integrated circuits (ICs) are the foundational hardware cornerstone to advance many emerging technologies such generative AI, 5G/6G, and quantum computing. The demand for and the scale of ICs are soaring to unprecedented levels with the ever-increasing information and computing workloads (e.g.. training foundation models with billions of parameters) (Achiam al., 2023). Thus, accelerating the design of advanced ICs is a key to sustaining the development of future technologies. Excitingly, recent breakthroughs in generative Al have presented transformative op- portunities to expedite the conventional design flows of ICs. Domain-specific large language models (LLMs) have been developed to free human designers by automatically generating and correcting Hardware Description Languages (HDL) (Zhong et al.] 2023: Blocklove et al.] 2023)] [023nChang et al.
2023 Thakur al. 2024 2023 Fu al. 2023; Liu al. 2023b: Wu et al.] [202 Liu et al.] (202a)), which can be seamlessly used to synthesize digital ICs with desired functionalities. As an example,
NVIDIA's ChipNeMo (Liu et al. 2023a), a powerful Nomain-adapted LLM, can rapidly generate valuable digital designs with just few prompts. Yer, applying generative AI to speed up the de- sign of analog ICs-essential in ubiquitous electronic systems to bridge the interfaces between physical world and cyberspace, ranging from enhancing performance in computing systems (c.g., high-speed memory interfaces and I/O links) to providing critical functionalities in communication and sensing systems (e.g., 5G/6G and quantum computing) remains significantly understudied.
The fundamental challenge arises from the intricate design complexities of analog ICs. Unlike digital ICs that can be universally and hierarchically abstracted into Boolean logic representations and easily described with high-level hardware description languages (c.g., Verilog and VHDL) or programming languages (e.g., C), analog ICs remain intractable to such abstraction due to their

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lack of systematic hierarchical representation and the heuristic and knowledge-intennsee nature of their design process (Gielen & Rutenbar, 2000). This makes it extremely hard to automate the design of analog ICs by developing programming languages similar to those used for digital ICs. As such, domain experts have followed a longstanding manual flow to design analog ICs. This process involves a number of time-consuming stages, such as selecting/creating topology (i.e., defining the connections between devices), optimizing device parameters based on the topology to achieve desired performance, and designing the physical layout of the optimized circuit for manufacturing. Importantly, the topology generation stage is the foundation and most creative part of the analog IC design process, posing a formidable and perennial challenge to design automation. Addressing it is the key to accelerating the development of analog ICs.
existing (new) circuit
There have been several studies in tackling this problem with generative Al techniques. The early pioneering work, CkIGNN (Dong et al. 2023), formulates the topology design graph generation task, as circuit topologies of analog ICs can be naturally represented as graph structures. uses a graph variational autoencoder (VAE) to generate various circuit topologies for a specific type of analog ICs, i.e., perrational-amllifies (Op-Amps). More recently, foundational models have also been explored for designing analog circuit topologies. LaMAGIC (Chang et al., 2024), fine-tuned masked language model (MLM), has been proposed to generate analog circuits with a fixed number of graph nodes. It shows high success rate in designing specific type of analog ICs, i.e., power converters (with fewer than 4 devices). AnalogCoder (Lai et al.) 2024), another M-based work, uses domain-speciffc prompt engineering to generate analog circuits from well-established LLM models (e.g., GPT-4), Instead of directly generating circuit topologies, it generates PySpice codes that can be converted to a SPICE (Simulation Program with Integrated Circuit Emphasis) netlist-a textual high-level description of device connections used for circuit simulation. AnalogCoder can generate a range of conventional analog circuits that often have a limited number of devices on the order of ten. These methods have demonstrated the potential of applying generative Al to analog IC design. Yet, a vast untapped frontier remains.
This work proposes, AnalogGenie, Generative engine (model) for automatic discovery of analog circuit topologics. In contrast to previous methods (Dong et al. 2023 Chang et al. 2024 Lai eet al. 2024) that are limited to a smaller scale of generation (c.g., generating single type of ana- log ICs, small-size analog ICs, or conventional analog ICs), AnalogGenie addresses the problem of scalable and general design. It can significantly broaden the variety of analog ICs, increase the number of devices within a single design, and discover unseen circuit topologies. A major ob- stacle to advancing generative models for scalable analog circuit design automation is the lack of a comprehensive dataset of analog circuit topologies. We bridge this gap by building a extensive dataset that consists of more than 3000 distinct analog circuit topologies with diverse functionalities (e.g., Op-Amps, Low Dropout Regulator (LDO), Bandgap reference, Comparator, Phase-Lockes Loop (PLL), Low Noise Amplifier (LNA), Power Amplifiers (PA), Mixer, DoltageCController Os- cillator (VCO), etc) from public resources (Razavi. 2000 Razavi & Behzad [ & Martin, 2008 Gray et al. 2009, Allen & Holberg 2011 Camenzind 2005). In addition, we apply data augmentation techniques to expand these circuit topologies by over 70x. To the best of our knowl- edge, this is the largest circuit dataset that effectively incorporates and enhances existing real-world analog circuit topologies to the greatest extent. This enables AnalogGenie to effectively learn var- ious analog topologies and significantly enhance its generation capabilities, surpassing all previous
methods (Dong al. 2023 Chang al. 2024 Lai et al. 2024).
Nonetheless, another key barrier to advancing the scalable design of analog circuits is short of a scalable and unambiguous representation of circuit topologies. AnalogCoder (Lai et al.] (024) relies on high-level text representations that use multiple tokens to describe a single connection between devices, making the generation prone to errors. CkıGNN (Dong al.] 2023) and LaM- AGIC (Chang et al.] 2024) use muuph-baedd representations with a fixed number of nodes, where each node represents a circuit device or subgraph. This ignores the critical low-level details essen- tial in analog circuit design, leading to ambiguous and unscalable circuit generation. We propose a scalable sequence-style data structure that captures fundamental analog circuit design details while efficiently describing large circuit graphs. Specifically, we represent each circuit topology as an undirected graph where each node is a device pin (Figure 3). We then sequentialize it into an Eu- lerian circuit-a trail that visits every edge exactly once and starts and ends at the same node. This unique representation allows AnalogGenie to generate circuit topologies in a scalable, flexible, and efficient manner. These developed dataset and techniques can thus enable AnalogGenie with excep-
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Topology
Graph generation
VOD
PM1
Vout
Vin
NM1
VSS
SPICE
Adding device connection circuit by simply adding edge or node
M2 Vout Vout VDD VDD) pmos4 Vin VSS) nmo54
Graph
Code generation
M2 (Vout Vout VDD VDD) pmos4 vin VSS VSS)
01010101010001100
Adding new device connection circuit requires generating complete sentence where each token can lead error
(a) Typical data repres entation for analog circuit topology
(b) Existing analog circ uit topology generation paradigms
Figure 1: Current states of analog circuit topology generation. (a) Typical data representation for analog circuit topology. (b) Existing analog circuit topology generation paradigms. Graph provides a clear one-to-one mapping between the graph generation process and the circuit design process. PySpice code is high-level representation, making its generation process more prone to error.
tional capabilities to produce diverse, large, and unseen analog circuit topologies. The advancement holds both profound engineering and scientific significance, demonstrating that generative Al can not only meet human expertise but also unlock the possibilities beyond human capability.
The key contributions in this paper are: (1) We propose a generative engine, AnalogGenie, built on GPT model to generate diverse analog circuits by predicting the next device pin to connect in the circuit; (2) We introduce a sequence-basee pin-level graph representation that efficiently and ex- pressively captures large analog circuit topologies; (3) We develop a comprehensive dataset of ana- log circuit topologies to advance research in analog electronic design automation using generative AI and introduce an augmentation scheme to enhance data diversity. (4) Experiment results show that AnalogGenie is capable of automatically generating far more, large-scale, valid, unseen, and nigh-peeformance topologies compared existing graph generation and foundation model work.
2
PRELIMINARIES AND RELATED WORKS
2.1 DESIGN PROCESSES OF ANALOG CIRCUITS
The design process of analog circuits begins with creating the circuit topology, which involves de- termining the device types (i.e., NMOS/PMOS transistor, capacitor, resistor, inductor, etc.) and the number of devices, and defining how they are interconnected. Following this, designers perform device sizing, i.e., optimizing the physical dimensions of devices to achieve desired performance. Finally, the physical layout (i.c., mask design) is developed to prepare for manufacturing. Note that a physical design is the representation of an IC in terms planar geometric shapes corresponding to the different stacked physical layers (e.g., metal, oxide, or semiconductor) during the fabrication process. Of all these stages, topology design demands the most creative effort, as needs to be conceptualized from scratch by human designers. While significant progress has been made in au- tomating device sizing [Wang et al. 2020 Cao et al. 2022 Gao et al. 2023 Cao et al., (024) and layout design (Kunal et al. 2019 Xu et al. 2019), the topology generation remains challenging problem due to its abstract and complex nature. This work aims to address this thorny issue.
2.2 GENERATIVE AI FOR ANALOG CIRCUIT TOPOLOGY GENERATION
An analog circuit topology can be naturally represented as a graph structure, providing a clear one- to-one mapping between graph generation and topology design (Figure a For instance, adding
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node to graph corresponds directly to adding a new device circuit topology, while adding an edge between nodes represents a new connection between devices. This intuitive representation has led most existing topology generation methods to focus graph generation (Figure (Tb),, such as CktGNN (Dong et al. 2023) and LaMagic (Chang et al. 2024). Yet, these approaches are often limited to generating only single type of circuit topology (e.g., Op-Amps or power converters). This is because they rely on one-shot generation by predicting the adjacency matrix directly and pre-define the number of nodes for generation, thereby suffering from low scalability (Zhu et al. 2022). In contrast, our work employs sequential graph generation (Section 3), offering far greater flexibility and more adaptability to various types of circuit designs.
An analog circuit can also be compiled into SPICE (Simulation Program with Integrated Circuit Emphasis) netlist (Figure aa)). A SPICE netlist is a text-based high-level description of the con- nection between devices (i.e., nets) in circuit topology, which is used in the process of circuit performance simulation. Leveraging the powerful code and text generation capabilities of LLMs, recent work, AnalogCoder (Lai al. 2024), applies domain-specific prompt engineering to exist- ing LLMs to generate Python-style SPICE (i.e., PySpice) netlists for analog circuits. However, the availability of publicly accessible SPICE netlist data remains significantly limited compared to the wealth of publicly available analog circuit topologies. This is because analog circuit topologies readablee illustrations commonly found in textbooks and scientific publications, whereas netlists are software-oriented representations often used together with confidential semiconductor technologies to extract circuit performance by simulation tools. Another key challenge faced by code generation approaches is their reliance on high-level text-based circuit topology representa- tions. Specifically, add a new device or connection, autoregressive models must predict multiple tokens to generate a complete line of code (Figure [b)), making them more prone to errors com- pared to graph-
methods, which require only single action per step. AnalogCoder (Lai al.] 2024) shows that even advanced models (e.g., GPT-4) struggle to correctly generate simple circuits with fewer than 10 devices. Thus, our work focuses on graph generation to achieve a more robust and scalable generation.
2.3 OPEN-SOURGE ANALOG CIRCUIT DATASETS
The lack of a comprehensive analog circuit dataset fundamentally hinders the development of gen- erative Al-based methods to automate the design of analog ICs. While some circuit datasets exist in the field, such as those provided by Align (Kunal et al. 2019 CktGNN (Dong et al. 2023), and AMSNet (Tao et al. 2024), they are often limited to specific types of analog circuits (i.e., Amp) without any label ge.g., circuit performance). In addition, most of their topologies are synthesized by permutating pre-defined template, resulting in non-unique designs. To address this fundamental gap, we have created thorough dataset by collecting 3350 distinct analog circuit topologies with di- verse functionalities (c.g., LDO, Bandgap reference, Comparator, PLL, LNA. PA, Mixer, VCO. etc) from public resources (Razavi 2000, Razavi & Behzad, 2012] Johns & Martin 2008; Gray et al. 2009 Allen & Holberg [011] Camenzind 2005). To ensure accurate connections, each schematic is manually drawn in an industry-standary circuit design tool for performance simulation. We also labeled each circuit with its performance metrics.
APPROACH
AnalogGenie is a domain--specife GPT model designed to generate various analog circuit topologies with greatly improved scalability. To achieve this, we first introduce an expressiveness-enieee graph representation that models each device pin as an individual node, ensuring that every connec- tion and interaction between circuit devices is explicitly represented. Next, we develop a sequence- style data structure to effectively handle large-scale analog circuits that can be typically modeled as large and sparse graphs. To further enhance the generation quality of AnalogGenie, we propose a data augmentation technique to address both data scarcity and the permutation invariance issue inherent in sequence data. Building upon these innovations, customize tokenizer to pre- pre-train AnalogGenie and perform finetuning afterward, enabling AnalogGenie to generate specific type of nigh-performance circuits.
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Efficient sequential graph representation (Sec 3.1:3.3)
VDD
Euler circuit
PM1
Vout
NK1
VS5
Augmented by permutating traversa path
diverse analog by predicting pin (Sec 3.4)
AnalogGenle (deceder only transformer)
Lager
Tead
AnalogGenie (decoder only transformer)
Op Amp
Bandgap Reference
Switched Capacitor Sampler
Figure 2:
Overview of AnalogGenie. AnalogGenie represents each topology a sequence and generates all sorts of analog circuit topology from scratch by predicting the device pin to connect.
3.1 EXPRESSIVENESS-ENIANN GRAPH REPRESENTATION FOR TOPOLOGY MODELING
Prior works (Dong al. 2023 Lu et al. 2023) rely on high-level graph representations to generate circuit topologies, where each node represents a device subgraph. This method omits essen- tial low-level device details, leading to the issue of ambiguous generation, i.e., single generated graph can be interpreted as multiple unique topologies. To understand this, consider that an NMOS transistor (NM) has four device
(D), gate (G), source (S), and body (B). When an entire device is abstracted into single node, it becomes challenging to interpret which pin edge connects (Figure 3 a)). Therefore, to ensure a unique one-on-one mapping between the graph and every circuit connection is explicitly represented, analog circuit has to be represented at the pin level (Figure Bb). Furthermore, previous methods restricted the graph representation of analog circuit topologies to directed acyclic graphs (DAGs), greatly limiting the types of circuit topologies that can be learned and generated. In this work, we adopt a more expres- sive and flexible representation of analog circuit topologies. Specifically, we represent the topology of analog circuit as finite connected undirected graph G = (V, E), where V = [V| n and E x V the edge set. For each
the circuit topology-wher
is
the node set representing each device pin with node i in graph G, we let {u V (u, E E} denote the set of neighboring nodes of e.
3.2 SEQUENTIAL GRAPH REPRESENTATION OF SCALABLE ANALOG CIRCUIT TOPOLOGIES
Previous methods (Dong et al. 2023 Lu et al. 2023) use adjacency matrices to represent circuit graphs. Yet, an adjacency matrix requires O n space to store n nodes, regardless of the number of edges, which is inefficient for sparse graphs. Analog circuit topologies are typically sparse because most devices are connected only to their immediate neighbors. As a result, the number of edges far smaller than n², leaving the adjacency matrix filled with zeros and wasting significant space on non-existent edges. For example, the graph in Figure 2 has six nodes and six undirected edges or 12 directed edges. An adjacent matrix will need 6x6 matrices to represent them, wasting 24 elements to store nothing. In contrast, our work represents the graph as an Eulerian circuit that stores only existing edges, making it much more efficient than adjacency matrices, particularly for handling large analog circuit topologies. More examples of the advantages of using the Eulerian circuit to represent large sparse graphs can be found in Appendix A.3
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Definition 3.2.1: Eulerian circuit is graph trail that visits every edge exactly once and starts and ends at the same node.
Theorem 3.2.1: Let G = (V.E) be finite connected undirected graph. Construct a directed graph D = (V, A) by replacing each undirected edge {u, v E E with two directed ares (u, v) and (v, u) in A. Then, the directed graph D contains at least one Eulerian circuit starting from any node.
Proof. Since directed graph D = (V, A) is derived from a finite connected undirected graph g = (V. all of D's node will have even degree and directed graph D is connected. According Euler theorem (Biggs et al. 1986), if a graph is connected and every node has even degree, then it has at least Fulerian circuit. The Fulerian circuits can start at any vertex. Thus, the directed graph D contains at least one Eulerian circuit starting from any vertex.
Theorem 3.2.1 clearly shows that all analog topologies have least one Eulerian circuit once the original finite connected undirected graph G is converted into a finite connected directed graph D. Thus, we know that our Eulerian circuit can represent any analog eircuits as long as they can be represented as finite connected undirected graph (i.e., Eulerian circuit traverse each directed edge exactly once when we convert finite connected undirected graph to finite connected directed graph).
3.3 DATA AUGMENTATION TO PREVENT OVER-FITTING AND REDUCE INDUCTIVE BIAS
Conventional graph-based generation circuit methods (Dong et al. 2023 Chang et al. 2024) rely on synthetic circuit data to mitigate model overfitting by permutating circuit connections under fixed number of nodes. Models trained on such data fail to capture the full complexity and nuances of real-world circuits, limiting their ability to generate only single type of analog circuits. In addition to the overfitting, another critical issue that significantly impacts the model's learning ability is the inherent bias in data representation. Permutation invariance is a fundamental inductive bias of graph-structure data. For a graph with n nodes, there are up to n! different adjacency matrices that are equivalent representations of the same graph. well-designed circuit generative model should assign the same probability to each of these equivalent representations.
To address these limitations, AnalogGenie learns from real-world circuits with diverse circuit types and their augmented representations. Specifically, AnalogGenic learns diverse representations from each analog circuit topology by generating multiple unique Eulerian circuits that represent the same topology. This allows us to generate 70x more data. Eulerian circuits ensure each sequence traverses each directed edge exactly once. To enforce graph-level permutation invariance, AnalogGenie adopt the approach used by GraphRNN (You et al. 2018), employing rithm to assign node orders within each device type, ensuring that each circuit topology has a unique graph representation. To further minimize permutation invariance at the sequence level. AnalogGe- nie manually defines "VSS" (the ground node universal to all analog circuits) as the starting node for all sequences. These techniques let AnalogGenic to learn robust and generalizable representation.
Sreadth-first-sarcch (BFS) algo-
3.4 CUSTOMIZING TOKENIZER TO PRE-TRAIN A DOMAIN- SPECIIIC GPT MODEL
Built the above foundations, customize a tokenizer encode and decode our sequence that represents the circuit topology to train AnalogGenie. Table in Appendix [A.2 shows an example of look-up table used for tokenization, where each token represent device pin. The device type and the maximum number of devices in each device type are determined through a data-driven method by scanning the devices types and number in the training data. To allow AnalogGenie to generate topologies with different numbers of devices, we introduce special "Truncate" token and use padding to ensure that all sequences have the same length.
With this customized tokenizer, we pre-train AnalogGenic to predict the next device pin in the sequence. Unlike traditional pre-training of LLMMs, which often involves randomly cropping se- quences from text documents, AnalogGenie's pre-training ensures that each sequence corresponds to a complete circuit topology. Specifically, given an unsupervised corpus of tokens = (u,..... ., un that represent one circuit topology, we aim to maximize the standard language modeling objec- tive (Radford et al., 2018) to train AnalogGenie. During generation, AnalogGenie begins with a single context token, "VSS" (the starting node for all Eulerian circuits) and completes the rest of the sequence, ensuring it represents a valid circuit topology. The pre-trained AnalogGenic model ca- pable of learning from various circuit topologies without requiring knowledge of their performance

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Non-unique mapping from graph to circuit topology
NM1
NM2
(a) Device level graph representation
AMG
AM2
NM2
(b) Device level graph representation
Figure 3: Comparison between two different circuit graph representations. (a) An example showing the limitation of device level graph representation used by previous graph generation work (Dong et al., [2023 Lu et al. 2023). which oversimplified the analog circuit connection and led to non- unique mapping from graph to circuit topology during generation. (b) Our device pin-level graph representation ensures there is a unique mapping between each graph and circuit topology and is able to explicitly represent every connection a circuit topology.
or specific circuit types. We then can further fine-tune to target high-performancee unseen circuits for particular task following the typical manner of reinforcement learning with human feedback.
RESULTS
4.1 EXPERIMENT SETUP
Dataset and AnalogGenic setup. Our circuit dataset contains 3350 distinct topologies, spanning 11 circuit types: Op-Amps, LDOSs, Bandgap references, Comparators, PI..s, LNAs, PAs, Mixers, VCOs, Power converters, and Switched Capacitor Samplers. The largest circuit comprises 54 de- vices. The performance of circuits has been evaluated with circuit simulator and thus been labeled. A. During training, we first split the topology data set into train and validation sets with a 9 to ratio. Then, we leverage the data augmentation tech- nique in Section 3.3 to generate 70x unique sequences of these circuit topologies. This ensures that all the topologies in the validation set are unseen. Our AnalogGente model is a decoder-only trans- former consisting of hidden layers and 6 attention heads with 11.825 million parameters in total. The vocab size is 1029. The maximum sequence length is 1024.
The detailed statistics are shown in Appendix
Baselines. We compare AnalogGenic with recent approaches for analog circuit generation, i.e., Ck- IGNN (Dong et al. 2023) based on VAE, and LaMAGIC (Chang et al. 2024) and AnalogCoder (Lai al. 2024) built on foundation models. These methods are different from AnalogGenie in circuit representation, generation capability and scalability as introduced in Section 2.2
We follow the
original work to produce the baseline results.
Evaluation task and metrics. We focus on evaluating the generative capabilities of AnalogGenie and baseline models. Specifically, we employ each model to generate topologies for various circuits, including Op-Amps, bandgap references, and power converters, and assess the outcomes based on four key criteria: correctness, scalability, novelty, and performance. (1) Correctness: We use a standard circuit simulator to determine whether the generated circuits are simulatable with default sizing, checking for issues such as floating and shorting nodes (i.e., open and short circuits). Cireuits considered valid. (2) Scalability: We measure scalability by recording the
that are simulatable number of circuit types and the largest valid circuit generated by each model. based on the number of devices. (3) Novelty: We assess the novelty of generated topologies by comparing them existing
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Aratiogfanie tmmn less with unnagmentc calroer (Min: D118)
Arsllig Garie lasa with un unieggmented ditasec (Min 0. 0.7964)
Andlogg Donie train sugmented (Mi 0.0394)
Figure 4: Comparisons between AnalogGenie pretrained with unaugmented data and augmented data. Our augmentation method is able improve validation loss around 8.5x.
ones in the dataset. A topology is deemed novel if it differs from all known topologies in our datasets. (4) Performance: We size each generated topology using a genetic algorithm and use the figure-of-merit (FoM) that considers all major metrics (e.g., gain, bandwidth, power for Op-Amps), as a comprehensive indicator to represent the circuit performance. We compare the best FoM of the circuits generated by each model.
4.2 ENHANCED GENERATION CAPABILITIES WITH DATA AUGMENTATION
We begin by examining the impact of the proposed data augmentation technique on the learning capabilities of AnalogGenic. The unaugmented training dataset consists of only 3015 unique se- quences due to the train and validation split, with each sequence representing distinct circuit topology. Figure 4 compares the training performance of AnalogGenie using unaugmented data (3015 sequences) against augmented data (227766 sequences). The results demonstrate that our augmentation technique reduces validation loss by approximately 8.5x, We also evaluate how this improvement influences the quality of circuit generation. The results indicate that without aug- mentation, AnalogGenic struggled with overfitting, leading to failures in generating valid circuits. In contrast, augmentation significantly enhances generation quality, increasing the number of valid circuits by 73.5x x as shown in Table
Table 1: Performance comparison between AnalogGenie and existing analog circuit topology gen-
eration work.
Bvaluation Metric
Valid circnits (9)
Topalogy scald
Novel circnits (5)
FaM
Topology
Numbeer of devices
Op-Amp
Power Converter
Bandpap
CRIGNN
67.5
22
93.1
10,9
LAMAGIC
68.2
1
12.7
2,2
AndlogCnder
$7.3
7
10
8.9
L.7
Genle comug-pretrainn
1
2:11
$2.1
0
0
AnalogGente (ang-prettaaln)
73.5
>11
63
98,9
19.3
2.5
17.3
AndogGGente cang-ppeeralln-lnneenn)
93.2
211
56
99
36,5
3,3
21.9
4.3 COMPARISONS WITH STATE-OF-TIIE-ARSS
Next, we compare AnalogGenie with existing VAE model (CkIGNN (Dong et al. 2023 ) and foun- dation models (LaMAGIC (Chang et al. 2024) and AnalogCoder (Lai al.) 2024)) addressing the problem of analog circuit topology generation. The comparisons are shown Table [
Correctness: AnalogCoder generates only 57.3% valid circuits, primarily due to the error-prone nature of code generation. CkIGNN and LaMAGIC, which employ graph generation techniques, achieve slightly better results, with 67.5% and 68.2% valid circuits, respectively. They rely on high- level graph representations, which pose interpretability issues (i.e., ambiguous connections between devices), as discussed in Section 3.1 In contrast, AnalogGenic uses an expressive device pin-level representation, where each connection is explicitly defined, eliminating the mapping issues
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with the other models. As such, AnalogGenie demonstrates superior correctness, achieving 73.5% valid circuits after pretraining and an impressive 93.2% after fine-tuning.
Scalability: CkIGNN and LaMAGIC developed for specific types of circuits, such Op-Amps or power converters, which limits their ability to generate beyond those particular types. Analog- Coder is able to design 7 circuit types. AnalogGenie demonstrates zero-shot capability gen- erate circuit types outside its training set, which includes 11 analog circuit types, as shown in Ap- pendix A.4.2
Beyond topology types, LaMAGIC is constrained by its graph representation, which contains only four device nodes, preventing it from generating larger circuits. CktGNN has similar limitation with its fixed-node graph representation, which supports at most 22 devices. AnalogCoder also struggles with scalability, making it capable of generating circuit topologies with a maximum of 10 devices. This restriction arises from its prompt template, which requires users to specify small circuit examples with limited device counts, leading the GPT model to generate circuits of similar size. In contrast, AnalogGenie benefits from comprehensive dataset, which includes topologies with over 50 devices. Its sequential representation efficiently captures these larger designs, enabling AnalogGenie to generate circuits with up to 64 devices after pretraining and 56 devices after fine- tuning, all within a limited sequence length.
Novelty (unseen designs): AnalogCoder generates only 8.9% novel circuits, as it is designed pri- marily for task completion rather than exploring new topologies. LaMAGIC, limited to circuits with just four devices, produces 12.7% novel circuits. CktGNN, with its graph model supporting up to 22 device nodes, achieves 93.1% novel circuit discovery. Remarkably, AnalogGenie generates nearly 100% novel circuits, leveraging its ability design large circuits from scratch. Visualizations of these novel circuits are provided in Appendix 1.441 1
Performance: For Op-Amp design, AnalogCoder achieves low FoM of just 1.7, constrained by the limited design options available through its prompt engineering. CkIGNN performs significantly better with a FoM of 10.9, though it is still restricted by the lack of detailed low-level design con- trol. AnalogGenie, with its expressive graph structure and flexible bottom-up generation method, initially achieves FoM of 19 after pre-training However, following fine-tuning with focus on bigh-performance Op-Amp design, AnalogGenie makes impressive gains, reaching a FoM of 36.5. In power converter design, AnalogGenie performs similarly to LaMAGIC, achieving a FoM of 2.5 compared to LaMAGIC's 2.2. After fine-tuning, AnalogGenie further improves, discovering topolo- gies that achieve FoM of 3.3, thanks to its larger design capacity. Lastly, AnalogGenie stands out as the only model capable of designing bandgap reference circuits. Its pre-trained model achieves FoM of 17.2, while fine-tuning elevates this to an outstanding FoM of 21.9.
In conclusion, AnalogGenie demonstrates unmatched superiority over AnalogCoder, CktGNN, and LaMAGIC across key metrics such as correctness, scalability, novelty, and performance. This ad- vantage stems from its expressive device pin-level graph representation, which ensures precise and accurate circuit generation, combined with its efficient sequential data structure that supports larger, more complex designs. Additionally, its bottom-up generation approach allows for greater flexibility and innovation in circuit topology, enabling AnalogGenie to explore beyond the limitations faced by the other models. These strengths collectively make AnalogGenie highly versatile and powerful tool for analog circuit topology design.
5 CONCLUSION AND FUTURE WORK
In this paper, we have introduced AnalogGenie, generative engine built on a GPT model to generate diverse analog circuits by predicting the next device pin to connect within a circuit. AnalogGenie addresses two key gaps in the field: building a comprehensive dataset of analog circuit topology and developing a scalable sequence-based graph representation universal to analog circuits. Exper- imental results across three types of analog circuit benchmarks demonstrate that our method can efficiently discover previously unseen circuit topologies in a scalable manner. Given the expressive nature of our representation and the bottom-up generative approach, broader applicability beyond analog circuit topology generation and can be generalized to digital design as well. Ultimately, consider our work to pave the way for the integration of generative
believe that our method has
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AI into IC design, fostering mutually beneficial relationship where IC design enhances generative Al capabilities, while generative Al accelerates IC design advancements.
Limitations and future work. AnalogGenie is comprehensive framework that combines domain-specific generative engine for discovering analog circuit topologies with a genetic algo- rithm for optimizing the parameters (e.g., sizing and bias) of the generated topologies. The primary focus of our work is on discovering topologies with a high likelihood of achieving a superior FoM sized. While the current sizing algorithm is effective, its sample efficiency can be improved by exploring more advanced alternatives (Wang el al. 2020). Additionally, for digital circuit develop- ment, we will consider combining AnalogGenie's graph generation approach with code generation work to enhance its ability.
REPRODUCEBILITY STATEMENT
The main theoretical backbone of paper is Theorem 3.2.1. We have already shown its proof in Section 3.2 Furthermore, we discussed our experiment setup and implementation details Sec- tion 4.1 We also provide open-source code supplementary material, including data augmentation, pretraining, and finetuning, The genetic algorithm sizing framework and Ngpsice simulation infras- tructure also provided in the supplementary material. For our open-sourced circuit dataset, provide its statistics in Appendix A.1 We will make our code and dataset public on Github in the future.
7
ACKNOWLEDGEMENTS
This work was partially supported by NSF Award #2416375. We also thank Professor Lei Li of Carnegie Mellon University for valuable discussions graph generation.
REFERENCES
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A APPENDIX
A.1 DATASET STATISTICS
Figure and Figure O are the statisties of our open-source dataset. The total number of topologies is 3350, and all of them are unique.
1318
1200
Unique Tapoloiiss
1000
800
600
200
185
31-40 Number Devicess
21:30
Figure 5: Our analog circuit dataset's device number distribution.
830
657
Topologes
363
000
238
100
10
27
46
Opdeep
LD0
Bandsoo
Comparierr
PLL
Meer
VD0
Pawer cemettr
SC Sampler
Tapeiogy Types
Figure 6: Our analog circuit dataset's circuit topology type distribution.
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A.2 TOKENIZER LOOKUP TABLE
Table 2 shows the tokenizer lookup table we used in our experiment. Specifically, our lookup table does not only describe basic devices (e.g., NMOS, PMOS, etc.) but also describes logic gates (e-g.- INV. XOR, etc.) that consist of multiple devices so it can scale up to describe large digital circuits for constructing mixed- signal circuits.
Table 2: The tokenizer's s look-up table we used in our experiment for device index mapping
Device
Index
Device
Index
Device
Index
Device
Index
NMI
0
NMI_D
NM1_G
2
NMI_S
3
NM1 B
NM2
NM25
124
PM1
125
PM1 D
126
PM1 G
127
PM1 S
128
PMI_B
129
PM2
130
PM25_B
249
NPNI
250
NPNLC
251
NPNI_
252
NPNLE
253
NPN2
254
NPN25 E
349
PNPI
350
PNPI_C
351
PNPI B
352
PNP1LE
353
PNP2
354
PNP25 E
449
RI
450
RI_P
451
RI
452
R2
453
R25
524
C1
525
CI P
526
CI N
527
C2
528
C25.N
599
L1
600
LIP
601
LIN
602
L2
603
L25_N
674
DIO1
675
DIOLP
676
DIOL
677
DIO2
678
DIO25_N
749
XOR1
750
XORI
751
XORI_B
752
XORLVDD
753
XORI
754
XORI_Y
755
XOR2
756
XORS_Y
779
INVI
815
INVIA
816
INVI_Q
817
INVI_VDD
818
INVI_VSS
819
INV2
820
INVIO
864
TGI
865
TGIAA
866
TGLB
867
TGI-C
868
TGI_VDD
869
TGI VSS
870
TG2
871
TG10 VSS
924
VINI
925
VIN2
926
VIN3
927
VIN4
928
VINS
929
INNI
930
IIN2
931
LOGICQBI
1024
LOGICQB2
1025
VDD
1026
VSS
1027
TRUNCATE
1028
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A.3 MORE DETAILS ABOUT EULERIAN CIRCUIT AND DATA AUGMENTATION
As shown in Figure 7 since we need to represent a circuit topology in an expressive way (i.e., device pin level), small circuit with two devices can lead graph with 14 nodes. Using an adjacency matrix to represent it will take 14 x 14 = 256 elements. On the other hand, the Eulerian circuit only needs 43 elements, which is around 5.95x smaller than the adjacency matrix representation. For our data augmentation, we permutate how the DFS algorithm explores its neighbor to generate unique Eulerian circuits. The number of Eulerian eircuits will drastically increase with the number of devices.
VDD
VDD
PM1
VOUT1
VINIO
NM1
NHT
VSS
ANLG
MM1
MMC_B
(a) Topology
(b) Device pin level graph representation
IVSS' "NM1 "NM1_''MM1" S'NM1'NMM D' VOUTI 'PMM''PM1 G' PMUTI G'PM1 D' NM1 D' G'NM1 D PM1 D' PMM1_GG G' PMM1 S' 'VDD' PM1 BB PMM 'P1 B' PM1 S' B'VDDD PMM''MM D' VOUTI' NIMI_G'VIII"" ''VINI" 'MM_G" NMĪI" NM1_B VS5 NM1 NM1_B''MM B'NM1_S" SIM__S'NMM, 'NM_ NMİ' NM1_S'V551
IVSS' NM1 [MMI_B'ME B'NM1 D' VOUUT''PMI D'LLDD''MM'''' 'MM G' VOUT1'PM1 G'PM1 D' NM1 DMP G'NM1 D' PM1 D' PM1 G' PMM 'PM1 S' PM1 B'PM1' 'PM1 PM1 S'PM1 B'VDD' PM1 PMM D' VOUTI NMM]D' DIND'''''''M 'NM1GG G'VINI' WMM_G 'NMI' NM1 VVS'' MMM_5''MM1 S'NMI_S NMII' NM1 VSS]
IVSS 'NMI_S''M S'NM1 B' V'S' NM1, B' 'MMI' NM1 D'VOU PM1 D PPM1'PM1 M'MI_G"WW G'VOUTT' PM1 [01_G'PM1_ D' NMM_ D'PM1 G' 'NNM1_ 'PM1_D DMMM1_ G G'PM1'PM S'VDDD 'PM1 B PMM''PMM B PPM PM1 B' VDD PM1_5'PM1'' PMM_'PM1_D' "'VLDD'VOUT1'NN "NMII D'LD''N'I''' IMMI'NM1_G GVVIG''IIIIIII ('VINN'NM1_ G" N''M1' 'MM_SS NM1 NM1 'NM1_ S'S''
[VSS 'M1 B"NM1 S'VSS' 'MM S' NM1 NM1 V'VOUTI' 'P1 PPM1'PM1 G' G'VOUT1' PM1 G'PM1 D' D'M1 'MN
DM1 G' G'PM1'PM1 S'VDD" 'P11 B 'PM1' PMM PM1 B' VDDD ''MM' D'VOOUT''MM NMM1 D' 'MI 'MM1 V NM1 G NM1'' NM1 NMI NM1_ NNM VSS'
(C) Four Eulerian circuits we found by using DFS
Figure 7: An example of analog circuit topology, its device pin level graph representation, four unique Fulerian circuits we found by using DFS.
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A.4 ANALOGGENIE'S GENERATED CIRCUIT TOPOLOGY VISUALIZATION
In this section, we show some of the novel circuits AnalogGenie generated and demonstrate its zero-shot capability by generating circuits that belong to a type that is not included the dataset. Particularly, to visualize the circuit schematic, we manually draw all the examples in Cadence Vir- tuoso, which is an andustry-standaan analog schematic edit tool.
A.4.1 NOVEL CIRCUITS
203
YOUTI
VIT
Figure 8: A novel Op-Amp circuit generated by AnalogGenie with GBW = 12 MHz, C₁ = 100 pF, Power 32.88 mW, and FoM 36.5.
M8-1
VCONTZ
VSS
Figure 9: A novel DC converter circuit generated by AnalogGenie with Efficiency 0.95, Voltage conversion ratio 2.35, and FoM = 3.3.
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VTD
SIS
VOD
VOLT1
VSS
VDD
1/2
Figure 10: A novel bandgap reference circuit generated by AnalogGenie with TC = ppm/"C, Line
regulation = 0.196 %/V, PSRR = 70 dB, and FoM = 21.9.
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A.4.2 ZERO-SHOP GENERATION
2012
Figure 11: An example showing AnalogGenic's zero-shot ability by generating transconductance amplifier which is circuit type that is not included in our dataset.
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A.5
FAILED EXAMPLES GENERATED BY ANALOGGENIE PRE-TRAINED MODEL
Figure 12: Failed example 1.
150
Figure 13: Failed example
19


Reviews:
[{"review_id": "jy1g1dPN1Z", "reviewer": "Reviewer_sJmh", "summary": "The paper introduces AnalogGenie, a generative tool to create analog circuit topology based on a generative model. The method has two contributions: first, the paper collects a large and complete analog circuit dataset; second, the scalable generation of analog circuits; the paper proposes to transfer the analog circuit into a sequence-based graph, thus enabling the usage of a generative model with token-based generation. With dataset augmentation and pre-training, AnalogGenie can finish 73.5% of problems, outperforming the best baseline with 68.2%.", "questions": "Questions:\n* To ensure the practicality of the designed circuit in real-world circuit design scenarios, the process technology of circuit fabrication should be taken into consideration. How do you think this current work can be extended to incorporate advanced process technologies and further optimize the design for improved performance and efficiency?\n* Based on my understanding, the paper didn't propose methods to optimize circuits's FoM. Therefore, the paper shouldn't compare the FoM, as the benefits may come from your large dataset, and the model may reuse some circuits. This is unfair as previous methods cannot access the large dataset you have collected.\n* The paper tries to tackle a simple task with topology generation, but how can the more critical analog circuit structure selection and sizing problem be solved?\n* For fine-tuning, how do you ensure the validation circuit has no overlapped knowledge in the fine-tuned dataset? More details about fine-tuning datasets should be included. Your fine-tuning significantly improves the accuracy. Is it because some structures are seen during training? Could you show some examples that, without fine-tuning, it fails, but after fine-tuning, it succeeds?\n* Based on the definition of an Eulerian circuit that only visits edge once, but the example in appendix A.7 (Fig.7), the first generated sequence visit VOUT-PMI-G twice. Could you explain on why it is not consistent with your definition?", "limitations": "", "rating": 8, "confidence": 4, "soundness": 3, "presentation": 3, "contribution": 4, "strengths": "Strength:\n* The idea of transferring the analog circuit into a sequence-based graph representing is a novel and interesting idea, enabling the use of a generative model for scalable circuit generation.\n* The collection of large-scale analog circuits. It would be great if the authors can release the dataset.", "weaknesses": "Weakness:\n* The main weakness of this paper is that it only considers generating functional circuits, which limits its effectiveness.  In real-world tasks, analog designers need to optimize the topology based on the design targets, e.g., sizing. Does this work consider performance optimization during the generation process, or is it only considered functional? Have you performed sizing?\n\nMore weaknesses please check the questions:", "quality": null, "clarity": null, "significance": null, "originality": null, "strengths_and_weaknesses": "", "was_revised": false, "final_justification": "", "rebuttal": "", "claims_and_evidence": "", "methods_and_evaluation_criteria": "", "theoretical_claims": "", "experimental_designs_or_analyses": "", "relation_to_broader_scientific_literature": "", "essential_references_not_discussed": "", "other_strengths_and_weaknesses": "", "other_comments_or_suggestions": "", "questions_for_authors": "", "summary_of_paper": "", "summary_of_recommendation": "", "technical_quality": "", "clarity_of_presentation": "", "potential_impact": "", "robotics_focus": "", "quality_of_limitations": "", "questions_for_rebuttal": "", "reasons_to_accept": "", "reasons_to_reject": "", "questions_to_authors": "", "extra_scores": {}}, {"review_id": "3dDlVVy1Ry", "reviewer": "Reviewer_U6NJ", "summary": "The authors introduce a novel methodology for analog circuit design, leveraging the capabilities of generative AI (specifically, GPT-based models) alongside a fine-grained Directed Acyclic Graph (DAG) representation. Additionally, they present a new dataset tailored to this task, developed through data augmentation techniques.", "questions": "1. I am quite confused about the expression of inductive bias in graph-based data. In the paper, the authors pointed out that to address the inductive bias issue, the model learned multiple unique Eulerian circuits that represent the same topology. Do these Eulerian circuits have different or share the same inductive bias? Since I am not a researcher in graph neural networks, I hope the authors could give me detailed and easy-to-understand instructions to explain this issue (better include proofs)\n\n2. To to best of my knowledge, the authors use pin-grained graph representation to describe a typical circuit design. Is this strategy a kind of data augmentation since a graph with more nodes can represent more information? If so, the main innovative point of this work is to change the representation to a lower level. If we apply such a strategy to other methods without using AGI models, will those older methods (Like GNN-based models) perform better as well?\n\n3. In the real world, the demand for RF circuits is high and those devices require very strict performance and electrical parameters (like filters, PLL, etc.). Is this system fully qualified to handle such devices' circuit generation? If so, are the generated circuits' performance as good as or even better than those that already exist?", "limitations": "", "rating": 6, "confidence": 3, "soundness": 3, "presentation": 3, "contribution": 3, "strengths": "1. The authors propose an innovative RAG representation for analog circuits, where each node corresponds to a device pin. This approach enables the model to capture low-level features and generate topologies in a fine-grained way.\n\n2. The authors present a new open-source dataset that comprises LDOs, bandgap references, comparators, PLLs, LNAs, PAs, mixers, and VCOs. Unlike previous datasets, this dataset includes performance metrics for each circuit. To ensure accuracy, the researchers manually implemented each circuit in an industry-standard design tool and conducted simulations, which is a significant manual effort.\n\n3. The authors avoid using adjacency matrices to represent circuit topologies. Instead, they employ an Eulerian graph representation, which effectively reduces the model’s memory requirements.\n\n4. To the best of my knowledge, this is the first work to apply generative AI models to tasks in analog circuit design.\n\n5. The authors employ data augmentation techniques by learning multiple unique Eulerian circuits that represent the same topology. This approach mitigates overfitting and reduces inductive bias, enhancing the model's generalization capability.", "weaknesses": "The experimental part over-emphasized the performance of the model itself. There is no data that shows the performance of the circuits generated by the AGI models. Since the generated circuits are about to be used in the real physical world, I think it is essential to analyze some basic and widely-used analog circuits like OpAmps(including the slew rate, GBW, CMRR, AoI, Ib, Vos, etc.), LDO(including Dropout Voltage, PSRR, etc.)", "quality": null, "clarity": null, "significance": null, "originality": null, "strengths_and_weaknesses": "", "was_revised": false, "final_justification": "", "rebuttal": "", "claims_and_evidence": "", "methods_and_evaluation_criteria": "", "theoretical_claims": "", "experimental_designs_or_analyses": "", "relation_to_broader_scientific_literature": "", "essential_references_not_discussed": "", "other_strengths_and_weaknesses": "", "other_comments_or_suggestions": "", "questions_for_authors": "", "summary_of_paper": "", "summary_of_recommendation": "", "technical_quality": "", "clarity_of_presentation": "", "potential_impact": "", "robotics_focus": "", "quality_of_limitations": "", "questions_for_rebuttal": "", "reasons_to_accept": "", "reasons_to_reject": "", "questions_to_authors": "", "extra_scores": {}}, {"review_id": "OWuMPf3Z8G", "reviewer": "Reviewer_KSXW", "summary": "This paper introduces \"AnalogGenie,\" a new tool designed to automatically discover analog circuit topologies. The authors aim to tackle some of the biggest hurdles in automating analog IC design, like the lack of comprehensive datasets and effective ways to represent analog circuits.\n\nThe main focus here is on automating the design of analog ICs, which is notoriously tricky. Unlike digital ICs, analog circuits don't have a straightforward hierarchical structure and rely heavily on designer intuition and experience. This makes automation a real challenge, and that's exactly what this paper tries to address.", "questions": "The paper mentions the use of a customized tokenizer and a finetuning process for AnalogGenie. How do they help tailor AnalogGenie to the analog circuit design task and improve the generation quality? Additionally, will this custom tokenizer affect its performance on other tasks, potentially reducing the inherent reasoning ability of the language model? Are there any metrics or experimental methods that can be used to verify these issues?", "limitations": "", "rating": 8, "confidence": 3, "soundness": 3, "presentation": 3, "contribution": 3, "strengths": "The authors reference several earlier efforts, like CktGNN, LaMAGIC, and AnalogCoder, that have explored using generative AI for analog circuit design. These prior works show promise, but there's still a lot of unexplored potential in this area.\n\nAnalogGenie takes a novel approach by creating a large dataset of over 3,000 analog circuit topologies and developing a scalable sequence-based graph representation. They also introduce a customized tokenizer and a pre-training method that allows the model to learn from these topologies without needing to know specific performance metrics or circuit types.\n\nWhile the paper doesn't dive into the nitty-gritty of the experiments, it does claim that AnalogGenie can produce a wide range of large-scale, valid, and high-performance analog circuit topologies, outperforming previous methods.\n\nOverall, AnalogGenie seems like a promising step forward in the automation of analog circuit design. However, it would be great to see more detailed discussions on its limitations and how it stacks up against other state-of-the-art methods. More insights on future directions could also help guide further research in this exciting area.", "weaknesses": "One downside is that the paper doesn't really discuss any limitations of AnalogGenie or suggest areas for future research. It hints at a lot of untapped potential in the field of analog IC design automation and suggests that AnalogGenie's approach might even be applicable to digital design.", "quality": null, "clarity": null, "significance": null, "originality": null, "strengths_and_weaknesses": "", "was_revised": false, "final_justification": "", "rebuttal": "", "claims_and_evidence": "", "methods_and_evaluation_criteria": "", "theoretical_claims": "", "experimental_designs_or_analyses": "", "relation_to_broader_scientific_literature": "", "essential_references_not_discussed": "", "other_strengths_and_weaknesses": "", "other_comments_or_suggestions": "", "questions_for_authors": "", "summary_of_paper": "", "summary_of_recommendation": "", "technical_quality": "", "clarity_of_presentation": "", "potential_impact": "", "robotics_focus": "", "quality_of_limitations": "", "questions_for_rebuttal": "", "reasons_to_accept": "", "reasons_to_reject": "", "questions_to_authors": "", "extra_scores": {}}, {"review_id": "0sYwRikU32", "reviewer": "Reviewer_nrPJ", "summary": "This paper makes a substantial contribution to the automation of analog integrated circuit design, an enduringly challenging problem in electronic design automation (EDA). It introduces a novel approach, establishing a unique, one-to-one mapping between a graph and the circuit topology. Here, each circuit connection is explicitly represented, requiring analog circuits to be modeled at the pin level. A key innovation is a method to transform the undirected graph into a sequence format. Following data augmentation, the authors train a GPT model that generates diverse analog circuits by predicting the next device pin connection within a circuit. The evaluation results demonstrate that the proposed GPT model significantly outperforms previous models.\n\nThe work is impressive, presenting AnalogGenie, a powerful GPT-based model capable of generating a much broader range of large-scale, valid, unseen, and high-performance analog circuit topologies than prior models. It also introduces an efficient, sequence-based, pin-level graph representation that effectively captures complex analog circuit structures. Additionally, the paper constructs a comprehensive, large-scale, high-quality dataset of analog circuit topologies, covering nearly all major categories, including RF circuits. This dataset will likely serve as a valuable resource for further advancements in analog circuit design automation.", "questions": "1.The authors are committed to open-sourcing this, correct? It would be valuable if they honor that commitment, as their work, if as described, could greatly benefit the automation of analog circuit design.?\n2.Can the authors explain how the sizing is done?", "limitations": "", "rating": 8, "confidence": 5, "soundness": 4, "presentation": 4, "contribution": 4, "strengths": "This is a remarkable work with several innovative contributions. First, it introduces an efficient and precise pin-level graph representation of analog topologies, enabling a unique one-to-one mapping between the graph and the circuit topology. Second, the authors treat undirected edges as two directed arcs in opposite directions, ensuring that the graph contains at least one Eulerian circuit starting from any vertex. Using this approach, they can sequentialize the graph of an analog circuit into an Eulerian circuit—a trail that visits each edge exactly once and both starts and ends at the \"VSS\" node. Third, the work implements data augmentation by enumerating all possible trails, effectively reducing overfitting and enhancing the model's generalization ability. Fourth, by creatively applying techniques from natural language processing, the paper reframes analog topology generation as a next-device-pin prediction task, with \"VSS\" acting as the starting token.\n\nAdditionally, this work provides a comprehensive, high-quality, large-scale dataset, poised to greatly advance analog design automation. Thanks to these innovative aspects, AnalogGenie achieves state-of-the-art performance. As a reviewer with experience in analog circuit design during undergraduate studies, I find the circuits presented in the Appendix valuable and practically significant.", "weaknesses": "The dataset introduced in this work encompasses various types of analog circuits, though the experiments conducted focus primarily on commonly used analog circuits. While these circuit types—such as operational amplifiers, power converters, and bandgap references—are indeed foundational in analog electronics, I hope the authors will consider expanding their experiments to include additional analog circuit types in future work. Furthermore, I encourage the authors to present these well-designed circuits to senior engineers for evaluation and, if possible, pursue a tape-out to demonstrate real-world feasibility.", "quality": null, "clarity": null, "significance": null, "originality": null, "strengths_and_weaknesses": "", "was_revised": false, "final_justification": "", "rebuttal": "", "claims_and_evidence": "", "methods_and_evaluation_criteria": "", "theoretical_claims": "", "experimental_designs_or_analyses": "", "relation_to_broader_scientific_literature": "", "essential_references_not_discussed": "", "other_strengths_and_weaknesses": "", "other_comments_or_suggestions": "", "questions_for_authors": "", "summary_of_paper": "", "summary_of_recommendation": "", "technical_quality": "", "clarity_of_presentation": "", "potential_impact": "", "robotics_focus": "", "quality_of_limitations": "", "questions_for_rebuttal": "", "reasons_to_accept": "", "reasons_to_reject": "", "questions_to_authors": "", "extra_scores": {}}]

Author rebuttal:

Decision: Accept (Spotlight)