LaMPlace: Learning to Optimize Cross-Stage Metrics in Macro Placement
Authors: Zijie Geng
Jie Wang
Ziyan Liu
Siyuan Xu
Zhentao Tang
Shixiong Kai
Mingxuan Yuan
Jianye HAO
Feng Wu
Venue: ICLR 2025 Oral (2025)
Keywords: Macro placement
Chip design
EDA
Primary area: applications to robotics, autonomy, planning
TL;DR: We propose a learning-based method for optimizing cross-stage metrics in macro placement.

Abstract: Machine learning techniques have shown great potential in enhancing macro placement, a critical stage in modern chip design.
However, existing methods primarily focus on *online* optimization of *intermediate surrogate metrics* that are available at the current placement stage, rather than directly targeting the *cross-stage metrics*---such as the timing performance---that measure the final chip quality.
This is mainly because of the high computational costs associated with performing post-placement stages for evaluating such metrics, making the *online* optimization impractical.
Consequently, these optimizations struggle to align with actual performance improvements and can even lead to severe manufacturing issues.
To bridge this gap, we propose **LaMPlace**, which **L**earns **a** **M**ask for optimizing cross-stage metrics in macro placement.
Specifically, LaMPlace trains a predictor on *offline* data to estimate these *cross-stage metrics* and then leverages the predictor to quickly generate a mask, i.e., a pixel-level feature map that quantifies the impact of placing a macro in each chip grid location on the design metrics.
This mask essentially acts as a fast evaluator, enabling placement decisions based on *cross-stage metrics* rather than *intermediate surrogate metrics*.
Experiments on commonly used benchmarks demonstrate that LaMPlace significantly improves the chip quality across several key design metrics, achieving an average improvement of 9.6\%, notably 43.0\% and 30.4\% in terms of WNS and TNS, respectively, which are two crucial cross-stage metrics that reflect the final chip quality in terms of the timing performance.

Published as a conference paper at ICLR 2025
LAMPLACE: LEARNING TO OPTIMIZE CROSS-STAGE METRICS IN MACRO PLACEMENT
Zijie Geng",, Jie Wang't, Ziyan Liu', Siyuan Xu², Zhentao Tang', Shixiong Kai" Mingxuan Jianye Hao"*, Feng Wu
MoE Key Laboratory of Brain-inspired Intelligent Perception and Cognition, University of Science and Technology of China
{ jiegeng, 1 liuziyyan Hemall uste. wsw..edu.cc..... cn, {jiewangx, fet.s///seeeuuuu/ucuuuuu..
Noah's Ark Lab, Huawei
(xusiyuan520, tangzhentaol, kaishixiong, Yuan. Mingxua, hao wwwawyyyyemwemccmmm Tianjin University
ABSTRACT
Machine learning techniques have shown great potential in enhancing macro placement, critical stage in modern chip design. However, existing methods primarily focus on online optimization of intermediate surrogate metrics that are available at the current placement stage, rather than directly targeting the cross- stage
as the timing performance that measure the final chip qual- ity. This mainly because of the high computational costs associated with per- forming post-placeman stages for evaluating such metrics, making the online op- timization impractical. Consequently, these optimizations struggle to align with actual performance improvements and can even lead to severe manufacturing is- sues. To bridge this gap. we propose LaMPlace, which Learns a Mask for op- timizing cross-stage metrics in macro placement. Specifically, LaMPlace trains a predictor on offline data to estimate these cross-stage metrics and then lever- ages the predictor quickly generate mask, i.e., pixel-level feature map that quantifies the impact of placing a macro each chip grid location on the design metries. This mask essentially acts fast evaluator, enabling placement de- cisions based on cross-stage metrics rather than intermediate surrogate metrics. Experiments on commonly used benchmarks demonstrate that LaMPlace signifi- cantly improves the chip quality across several key design metrics, achieving an average improvement
9.6%, notably 43.0% and 30.4% in terms of WNS and TNS, respectively, which are two crucial cross-stage metrics that reflect the final chip quality in terms of the timing performance.
INTRODUCTION
Electronic Design Automation (EDA) aims to streamline the chip design process through efficient automation techniques (MacMillen al., 2000 Markov et 2012). It involves lengthy workflow that includes several stages such as logic synthesis, floorplanning, placement, clock tree synthesis (CTS), and routing (Wang et al.] 2024a d 2025: 2024c; Bai et al., 2025). The ultimate goal is optimizing the performance, power, and area (PPA) metrics of the final chip product (Rabaey et al.) 2002 Wang et al. [2009). Within this workflow, macro placement is a crucial step. which involves positioning large rectangular circuit modules- such memories, customized IPs, and interfaces on chip canvas. determines the overall chip layout and impacts subsequent stages such as cell placement, CTS, and routing, thus significantly influencing the final PPA objectives (Chen et al.
2023 Xue et al. (025).
Recent advances have shown that machine learning (ML) techniques have promising potential in enhancing macro placement. These techniques are expected to autonomously explore the vast design space and generate chip layouts that are comparable to, superior to, those designed by
"This work was done when Zijie Geng was an intern at Huawei. Corresponding author.

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mHPWL
Wirelength
Metrics:
mCongestion
HPWL
Congestion
Final PPA
Stages:
WNS, TNS,
Macro Placement
Cell Placement
Clock Tree Synthesis
Routing
MaskPlace
LaMPlace can optimize cross- stage metrics
Methods:
ChiPFormer
AlphaChip
Previous works focus on intermediate surogatte metrics, but what matters is how to improve PPA.
WireMask-BBO
DREA MPlace
Illustration of post-placement stages in the EDA workflow, the metries available at each stage, and the optimization objectives of some previous works. Our main contribution is to optimize the cross-stage metrics to improve the final PPA, rather than intermediate surrogate metrics.
Figure 1:
human experts, while significantly reducing the time required for placement and shortening time-to- market. Traditionally, the macro placement task has been viewed as a black-box optimization (BBO) problem, which has been tackled with optimization techniques such simulated annealing (SA) and
evolutionary algorithms (EA) KKirkpatrick et al. 1983 Ho et al. 2004 Murata et al. 1995 Shi et al.) 2023ap. In their work AlphaChip, published on Nature, Mirhoseini et al. (2021) first proposed to model macro placement as Markov decision process (MDP), where the positions of macros are sequentially determined, and they addressed the problem using reinforcement learning (RL). Since
then, there has been surge of research on RL-based methods for macro placement (Cheng & Yan.
2021 Cheng et al. 2022: Lai et al. 2022 2023 Geng et al. 2024).
Despite the achievements, existing methods primarily focus on optimizing intermediate surrogate metrics that are readily available at the current stage (see Figure D. To name few, MaskPlace (Lai et al. 2022). ChiPFormer (Lai et al.] 2023), WireMask-BBo (Shi et al. (023a),, and Efficient- Place Geng et al. 2024) all focus on efficient optimization of the macro half -erf-perimeter wire length (mHPWL), which is available immediately after macro placement, without considering standard cells (the relatively smaller components). AlphaChip (Mirhoseini et al.] 2021) and DREAM- Place (Lin al. 2019: 2020: Gu et al., 2020 Liao al. (022) mainly optimize the full-netlist half-perimeter wire length (HPWL) and congestion, which are available after cell placement but before CTS. Although DeepPR (Cheng & Yan 202I) and PRNet (Cheng et al.. 2022) propose to optimize the wirelength (WL) by integrating placement and routing, they do not consider the CTS stage and often produce infeasible outcomes due to overlaps. These intermediate surrogate met- rics are commonly favored by RL and BBO methods because of their relatively low computational costs. However, as noted by a recent work (Wang et al.] [024b), there exists considerable mis- alignment between the surrogate metrics and the PPA metrics, such as worst negative slack (WNS) and total negative slack (TNS), which actually reflect the final chip quality but have not yet been adequately considered in the AI community (Cheng et al. 2023). Incorporating these design met- rics at the macro placement stage is crucial for aligning with the industry's s ongoing pursuit of the "shift-left" (Chen al., 2024), i.e., advancing key processes earlier in the development cycle to improve outcome predictability and efficiency. The oversight on these essential metrics primarily arises from two reasons. On one hand, RL and BBO methods typically require extensive evalua- tions (i.e., reward computations) during online optimization. On the other hand, the PPA metrics are inherently cross-stage metrics, and evaluating them is highly time-consuming, requiring not only full placement, including macro and cell placement, but also post- pasteplacement stages such as CTS and routing. The substantial time costs make the online optimization of RL and BBO impractical.
To tackle the aforementioned challenge, we propose LaMPlace. a novel method that Learns Mask for optimizing cross-stage metrics in macro placement. LaMPlace offers two principal insights for macro placement. First, to mitigate the high computational costs of online optimization, we adopt a supervised learning paradigm, training a predictor for desired metrics on offline data. This offline setting is practical in industry, as substantial chip data can be collected from chip design projects. The trained predictor serves as a placement simulator, allowing for the estimation of stoss-stage metrics at relatively low computational cost. Second, to facilitate efficient placement, we shift from learning a predictor that outputs a single value for each placement to learning to generate a mask, i.e., a pixel-level feature map that quantifies the incremental objectives as each macro is placed
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sequentially. To achieve this, we model the predictor polynomial function of pair-wise distances between macros, with learnable coefficients. This polynomial formulation allows us to quickly generate mask to guide the placement decisions in real-time. Leveraging this mask, LaMPlace employs a simple yet effective greedy policy, sequentially placing macros while maintaining local optimality each step. We evaluate the effectiveness of our proposed LaMPlace commonly used benchmarks, considering several cross-stage design metrics. The results demonstrate that LaMPlace significantly improves the chip quality across these metrics, achieving an average improvement of 9.6%, notably 43.0% and 30.4% in terms of WNS and TNS, respectively, which are two crucial cross-stage metrics that reflect the final chip quality in terms of the timing performance.
2
PRELIMINARIES
2.1 MACRO PLACEMENT
Chip placement involves strategically arranging a set of chip modules, including macros (large mod- ules such as memories, customized IPs, and interfaces) and cells (small modules like logic gates), on a chip canvas, subject to the non-overlap constraint. As an integral part of the entire EDA workflow, the ultimate goal of macro placement- performance, and area (PPA) metrics of the final chip product. As illustrated in Figure evaluating the final PPA involves several stages and is very coneccnnu.. Therefore, variety of heuristic metrics have been proposed in order to guide the optimization at intermediate stages. In this section, present some important concepts and metries to facilitate a better understanding of the macro placement task (Rabaey et al. 2002 Wang et al. 2009).
indeed, all these related steps-is to optimize the power,
PPA refers to performance, power, and area, which are three key dimensions to assess the quality of chip product. These are not measured by single metric but through a series of critical metrics. They include, but are not limited to, worst negative slack (WNS), total negative slack (TNS), number of violating paths (NVP), and physical area utilization. Optimizing the PPA metrics, as fundamental objective of EDA, has been extensively explored in the industry through expert-designed heuristics. However, in the AI community, the challenge of PPA optimization has not been adequately recog- nized (Wang et al. 2024b). Bridging this gap and enhancing the integration of Al strategies in PPA optimization core aspirations of this paper.
Worst Negative Slack (WNS) and Total Negative Slack (TNS) are crucial metrics to assess the timing performance of a chip circuit. Slack refers to the difference between signal's expected and required arrival times, and negative slack indicates a timing violation. WNS identifies the worst negative slack in circuit, highlighting the most critical timing issue, while TNS sums up all negative slacks, reflecting the overall timing issues. These two metries, as representatives of PPA metrics, are considered evaluation metrics to demonstrate the effectiveness of our method.
Congestion evaluates the density of wires in different chip regions. High congestion in certain areas can pose substantial challenges during the routing stage. While not direct component of the PPA metrics, managing congestion effectively is essential to ensure that the chip can be successfully manufactured. Congestion typically estimated after CTS but before detailed routing, allowing for adjusting macro placement and routing strategies to mitigate potential issues. It is also used as an evaluation metric in this paper.
Wire Length (WL) is the total length of all wires connecting all modules in chip. half-perimeter Wire Length (HPWL) is the sum of half- perf-eerimeters of bounding boxes that encompass all pins in each net. It is widely used as an estimation of WL. and is obtained after cell placement. Macro HPWL (mHPWL) further simplifies HPWL by only considering the macros. It is favored recent studies as it can be immediately obtained after macro placement. These metrics are thought to correlate with the final PPA, but they do not directly reflect the chip quality, this paper, we include HPWL an evaluation metric mainly for better comparison with previous methods, demonstrating the effectiveness of our approach for optimizing cross- stage metrics.
2.2 RELATED WORK
Existing methods for macro placement can be roughly categorized into analytical methods, black- box optimization (BBO)-based methods, and reinforcement learning (RI.)-based methods.
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Analytical methods formulate the optimization objective, such HPWL, analytical func-
tion of module coordinates, which is solvable via quadratic programming (Kahng et al. 2005
Viswanathan al., 2007a bj [Spindler et al.] 2008 Chen al. 2008 Kim et al. [012]] Kim & Markov] 2012: Cheng et al. 2018) or direct gradient descent (Lin et al. 2019 2020 Gu et al. 2020
|
Liao al. 2022). Although efficient, they rely on differentiable surrogate metrics and struggle with complex and black-box PPA metrics.
BBO-based methods view macro placement as BBO problem and solve it using algorithms like SA and EA (Kirkpatrick et al., 1983; Ho et al.) 2004 Murata et al. 1995 Shi et al. 2023a Sher-
wani 2012 Shunmugathamma al. 2020 Vashisht et al. 2020; Murata et al. 1996 Chang al. 2000 Roy et al.) 2006; Khatkhate et al., 2004). They require numerous evaluations, which are
highly time-consuming when considering cross-stage metrics. Notably, WireMask-BBl
(Shi al.)
2023a) introduces
efficient greedy algorithm for optimizing mHPWI. based on the concept of wiremask (Lai et al., 2022). In this work, we develop a learnable mask instead of the wiremask, and adopt the greedy algorithm from (Shi et al. (2023a) for efficient optimization.
RL-based methods have recently emerged, starting from AlphaChip (Mirhoseini et al. 2021 which first modeled macro placement as a Markov Decision Process (MDP). DeepPR (Cheng & Yan 202T) and PRNet (Cheng et al. 2022) integrate placement and routing but do not consider CTS and the non-overlap constraint. MaskPlace (Lai et al. 2022) introduces the wiremask concept, later adopted by Shi et al.] (2023a) and Ging et al. (2024) to significantly improve efficiency. The suc- cessful application of wiremask also motivates to learn a mask for fast macro placement. These methods require extensive online learning steps, making it challenging to directly optimize PPA as rewards. ChiPFormer (Lai et al. (202)) employs offline RL to reduce the online learning costs. How- ever, it relies on a pre-trained expert policy and does not adequately consider the desired metrics. Additionally, achieving optimal performance still requires extensive online fine-tuning steps.
2.3 WIREMASK FOR FAST MHPWL OPTIMIZATION
The concept of wiremask was first introduced by Lai al. 2022) and later adopted by Shi iet al. (2023a) and Geng et al. (2024) for fast optimization of the macro half half-perimeter wire length (mHPWL). Figure illustrates the wire- mask with trivial example. In the left fig- ure, Mi and M2 represent two macros that have already been placed, and M3 represents the next macro to be placed. The red and green solid boxes indicate the bounding boxes of two nets. The current mHPWL is the sum of half- perimeters of these boxes, i.e., mHPWL. = wi h1 w2 h2. When M3 is placed at a specific grid position, we can casily calculate the increment of mHPWL. Here we use the bottom-left corners of macros to denote their positions. As shown in the right figure, the wiremask is a matrix that quantifies the increase in mHPWL result- ing from placing M3 at each specific grid position. The wiremask can be computed quickly because the mHPWL increment is an explicit function of the macro positions. To determine the next macro position, we can first calculate the wiremask and then greedily select a feasible position that results in the smallest mHPWL increase.
MG
M.
Figure 2: An example from Geng al. 2024 to illustrate of the concept of the wiremask.
Motivation of LaMPlace If we learn a predictor with the full placement as input, it can serve as a sparse reward model. However, its black-box nature makes hard to develop an optimization algorithm as efficient as the one with wiremask. This motivates us to explore how to learn mask for more general metries, similar to how wiremask works for mHPWL. We recognize that mHPWL is essentially in the form of combination of (Manhattan) distances between macros, enabling fast calculation of the mHPWL increase at each position and each step. We further observe that the computational principles behind wiremask can be generalized to any polynomial functions with respect to pairwise distances between macros. This motivates us to learn a predictor in the form of polynomials and leverage to generate mask to guide the optimization process.
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3 METHODOLOGY
This section introduces our proposed framework LaMPlace. An overview of LaMPlace is shown in Figure D which outlines two main components. First, we train predictor for the cross- stage metrics using Laurent polynomial approximation. The coefficients of the polynomials are treated learnable flows, which refer to as L-flows. Second, we leverage the trained predic- for to generate a mask, termed as L-mask, to guide the efficient macro placement. We present detailed explanations of these components in Section 3.1 and Section 3.2 respectively. Addi-
tional implementation details can be found in Appendix A
The code is available at https:
7/github. com MIRAAAA- 4EDA- LEMP Lace
3.1
PREDICTING METRICS USING LAURENT POLYNOMIAL APPROXIMATION
Graph Representation A chip netlist consists of various nets representing the interconnections between macros and standard cells. We represent a netlist as graph G(V. E), where V denotes the nodes and E the edges. Given the high number of standard cells-often surpassing 100, 000 in a sin- gle chip-it impractical or inefficient to represent all macros and cells as individual nodes. There- fore, consistent with previous works, in our graph representation, each node represents macro | However, unlike prior approaches that disregard standard cells in the graph representation, we incor- porate standard cell information by introducing edge features that quantify the connectivity between macros, taking into account paths that include standard cells. Specifically, these edge features cap- ture the number of pathways connecting two macros, with paths differentiated by the number of standard cells they traverse. Such a representation enables us to take the standard cells into consid- eration with relatively low computational overhead. More details about the node and edge features can be found in Appendix A.I
Laurent Polynomial Approximation Based on the aforementioned graph representation, we adopt graph neural network (GNN) (Shi et al. 2023b 2025 2024), denoted as GNNg. to ex- tract node features h, for each node v E V. These features are stacked as matrix H = (hr, " h E IV]xxd writing H = GNNo(G). We consider a set of A metrics, which are evaluated using EDA tools. In this work, we consider different stass- metrics, including HPWI., congestion, WNS, and TNS. Each evaluation metric y/a is supposed to be function of the netlist G and the macro positions X = (x1, ... =Iv1) E R | writing yA- = [H, X). where (a()) represents an EDA tool to run the post-placement stages and obtain the final metrics. Notably, this function is translation- -ivtarnnnnvvaiant
P with respect to the macro positions. Therefore, we re-express it as function of the pairwise distances (X) = ||x, æyح12 between every two macros i and j.
We predict each metric yn using Laurent polynomial function of the pair-wise distances:
か> A (H, X)
Σ Σ KEK
(A)))(H)))))))
(A.1) (H) ||æ,, 2z 22.
(1)
ISKiiSIVI
In Formula 1 K' denotes set of integers indicating the exponents in the polynomial, and (A.k) are the coefficients, calculated as:
oi (H)
1 (a hs + h2 M (2.k) (a,)))))) h:)
(H) 2
(2)
where (A,A) E R ddxd are learnable weight matrices. Intuitively, each o. captures the relation- ship between two macros i and j. analogous to the concept of flows in networks. Therefore, we refer to these coefficients as "learnable flows", or "I-floos". Further discussions are in Appendix A.2
(A.k)
Training the Predictor To train the predictor, we construct a dataset D using a collection C chip netlists (G.)C - each represented as graph G.. For each netlist, we generate set of M dif- ferent placements (Xa.m. ) m= by running the available placement tool like DREAMPlace with dif- ferent seeds. Subsequent togges-sucl cell placement, clock tree synthesis (CTS), and routing-
are run with existing EDA tools to yield the cross-stage evaluation metrics yemm GG, X
It is meaningful to consider the clusters of io ports as nodes, which will a feature the future work. Here, "translation-invarr -nvvariiionnnaaiannnn is approximate description, indicating that the target metrics are primarily influenced by the relative positions of macros.
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(a) Training the predictor
Netlist
L-flows
Laurent Polynomial Model
GNN
a.k
ij
82
Σ
(2.1)
r
ij
Following Stages
Tif
HPWL
Congestion
Va
Loss L(Pa.
TNS
Tee.
Dataset
Placement
Labels
(b) Placement
(c) Performance
Netlist
Congestion
Σ
Σ
(2,K) LJ
min
TNS
HPWL
greedy algorithm
LaMPlace
WNS
WIRmast-BBO
L-mask
Chipfomor
Figure 3: Overview of LaMPlace. (a) We construct an offline dataset by executing placement and post post-placement stages to obtain placement solutions and their corresponding cross-stage metrics. predictor in the form of a Laurent polynomial is trained on this dataset. (b) Using the trained predictor, we reformulate the macro placement task as a polynomial optimization problem. We leverage the predictor to generate the L-mask to guide the sequentially greedy algorithm for fast placement. (c) LaMPlace outperforms existing methods across several key design metrics. The results are averaged over 8 chip circuits and then normalized to [0, 1] for a better visualization.
for each À E [A]. Then we obtain dataset:
0={(Ge Xa,, vea (C), (M), [A]].
D
(3)
For each chip G. and placement X Kems we give the prediction g!ul fA(GNNo Xe,m)- We use the MSE loss to train the predictor:
LMSE
Σ
ye.m
Fe.m
(2)
CMA
C,m,A
Additionally, we adopt pair- ranking loss boost the training effectiveness, which is defined as:
LRank = Σ Σ
Ze. log
(1 + exp
(122)
DCAA )):
(5)
(A) Megim, Pyeging
(A)
where
(A) yer.ms
(A)
exp
exp
Yez.ma
Ze 22.
(6)
Σem
exp
youm
(A)
are weighted coefficients detined following previous works (Chen et al. 2023). We use the combi- nation of these loss functions effectively train the predictor:
L = B1 LMSF + B2 LRank,
where 31, 32 are hyperparameters.

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3.2 BARRAABE-MMASKGUUSE GREEDY ALGORITHM FOR EFFICIENT PLACEMENT
Optimization Problem Formulation In the macro placement phase, the chip canvas is discretized N x N grid, and the feasible macro positions are the grid corners, denoted X. With the predictor in hand, the task of macro placement is recast as an optimization problem. Without loss of generality, we assume that, for all metries, a lower value indicates better performance. Formally, the goal is to minimize the predicted metrics subject to no overlap:
arg min XEXIVI
Σ Ox X) dE
(8)
s.t.
Overlap(G, = =0
where (H, X) are polynomial functions defined in Equation and a' are hyperparameters. Unlike wiremask, an advantage of our method the ability to control the weights of every metric, effectively balancing the multi--bjeectvve optimization problem.
Efficient Greedy Policy Despite the simple polynomial formulation, solving the above optimiza- tion problem is still challenging due to the large number of macros and the non-overlap constraint. This highlights the necessity of the polynomial form of the predictor, which enables us design greedy algorithm for fast placement. Specifically, we sequentially determine the position of one macro each step. the t step, the positions of the first place the hhh macro position greedily by solving the following problem:
macros are already determined. We
t-1
arg min mxE
Σ aA
Σ
Σ
a
(A))(H) (H)
(A.8) 1
||=, =x,112
AE(A)
REK f=1
Overlap(G, 21, xx) O.
Generating Learnable Mask In Formula 9 D (zx) represents the increase of the objective func-
tion from Formula 8 when placing the new macro at the grid 24. The matrix A, containing A, (x;,)
values for all xt E X' is analogous to the wiremask used in the previous works (Lai et al.] 2022;
Shi et al. 2023a Geng et al.
2024), which has shown promising potential in improving placement efficiency Shi et al. 2023a). As our (r( is learnable rather than pre-defined by mHPWL, it extends wiremask to any learnable metrics. Therefore, we refer to A, "learnable mask", or an "L-Mask"' Thanks to the polynomial form of the predictor, the L-mask can be computed very
(A. efficiently. Notice that the coefficients di. are position-agnostic and need be computed only once before the placement process:
A (A.A)
= - H (M(AA), + +MAATT HT (A.R) = (A.)) (1.A)
(10)
2
(A.k) as entries, indicating the L-flow between each pair of macros. Here A (A,A) is the matrix with di.j
This approach keeps the computational cost of the GNN module very low. At each step during placement, we only need to calculate the distances between each grid position and the placed macros, which can be efficiently computed through tensor computation. See Algorithm for more details.
L-Mask-Guider Black-Box Optimization The L-mask derives an efficient greedy placement policy, which can be used to boost any sequential placement approach by restricting the solution space. In this paper, we showcase its application within the WireMask-BBa BBO framework proposed by/Shi al. al. (2023a). Specifically, in this framework, the placement task is recast as a BBO problem, with the macro positions as the optimization variables. The genotype solutions are randomly initial- ized and optimized using algorithms such as EA. For each genotype solution, we use the L-mask to record the increment of target metrics and greedily improve the genotype solution by sequentially moving the macros to the nearest optimal grid. See Algorithm 2 for more details.
EXPERIMENTS
4.1 EXPERIMENTAL SETUP
Benchmarks We primarily assess our method on the ICCAD2015 benchmark (Kim et al. 2015
which consists of eight large-scale chip circuits. Notably, some recent works (Cheng & Yan 2021
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Cheng et al. 2022, Lai et al. 2022; 2023 Shi et al. 2023a have commonly used benchmarks from ISPD2005 (Nam et al. 2005 and ICCAD2004 (Adya et al. 2009). However, the circuits in these benchmarks are in simplified BookshelE format, lacking the original LEF /DEF files and miss- ing design information necessary for evaluating PPA in later stages. Consequently, obtaining PPA metrics these benchmarks is infeasible. In contrast, the circuits in the ICCAI22015 benchmarks are from the ICCAD2015 contest for timing-driven placement. They include timing libraries and design constraints, allowing for proper evaluation. More details can be found in Appendix A.4
We compare La with several recent advanced placement methods. DREAM- Place (Lin et al. 2019; 2020, Gu et al. 2020, Liao et al., 2022) is an analytical method initially designed for cell placement. We use its latest version, which integrates timing optimization, to per- form mixed-size placement, moving both macros and standard cells together. WireMask-BBi (Shi et al. 2023a) is recent offte-of-the-ar method for optimizing mHPWL. It implements various BBO algorithms, with WireMask-EE demonstrating the best overall performance, so we use WireMask- EA for comparison. The placement algorithm of LaMPlace operates under the same settings as WireMask-EA but utilizes our learned L-mask instead of the wiremask. ChiPFormer (Lai et al.) 2023 is a representative RL-based method, which has been pre-trained on an offline dataset. We load their pre-trained model and fine-tune it on each circuit for comparison.
Baselines
Evaluations Metries As explained in Section 2.1 we use four key metrics for evaluation: HPWL, congestion (Cong.). WNS, and TNS. These metrics are crucial for improving the final chip quality but are consuminn to evaluate as they involve stages after macro placement. We run DREAM- Place (Liao et al. 2022 for cell placement to report HPWI. and congestion, and OpenTimer (Huang) & Wong 2015) for timing analysis to estimate WNS and TNS. Although the model is not directly trained on the final PPA metries obtained after all stages, our experiments have demonstrated its effectiveness in optimizing cross-stage metrics and ultimately improving the final PPA.
Training and Inference We use the first six circuits in ICCAD2015 for training, i.e., superblue 3, 4, 5, 7, and 10, for training. The last two circuits, superblue /6 and 18, are excluded from the training set to demonstrate generalization to unseen data. This is a default dataset partition just according to the circuit indices. We run DREAMPlace for mixed-size placement to generate 200 layouts for each training circuit and evaluate them to obtain the desired metrics, which serve as training labels. This process results in dataset of 1, 200 placement-label pairs as the offline dataset. Notably, this requires only 1, 200 evaluations in total on all six training circuits, significantly fewer than RL and BBO methods, which typically require tens of thousands of steps for convergence on each circuit. The predictor is trained on this dataset and then tested on all circuits.
As LaMPlace, WireMask-FA, and ChiPFormer share the same Python implementation for the can- vas, we implement them under the same settings, where the chip canvas is divided into an 84 x 84 grid. For LaMPlace and Wiremask-EA, we execute the EA algorithm with 50 initial random rounds followed by 20 evolutionary rounds. For ChiPFormer, we load their pre- mr-itrinee model and fine-tune it for 2, 000 steps. For DREA.MPlace, we run it for mixed-size placement using its default parame- ters, with the timing optimization process enabled. More details can be found in Appendix
A.5 A.5
4.2 MAIN RESULTS
the main evaluation results for macro placement using different approaches. The re- sults show that LaMPlace outperforms other baselines. Specifically, LaMPlace consistently achieves the best average rank and the best timing results (i.e., the best TNS and WNS) across all cases, and achieves the best congestion on almost all cases. For HPWL, achieves comparable performance with DREAMPlace, which directly optimizes HPWL as an analytical objective, and significantly surpasses other methods. LaMPlace achieves an average improvement of 9.6% across the four metrics, compared to the best best-performing methods on each of these metrics. Notably, it achieves improvements of 43.0% and 30.4% on TNS and WNS, respectively. The overall performance is vi- sualized as radar chart in Fig3 We visualize the obtained placement solutions in Appendix(B.8 We report the running time in Appendix B.6 We further conduct experiments on ChiPBench Wang et al. (2024b), which evaluates the post-routing PPA results. We run the placement algorithm of LaMPlace directly on the industrial chips from ChiPBench without any fine-tuning. The results are in Appendix B. which demonstrate that I LaMPlace still outperforms other baselines ChiPBench.
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Table I: Comparisons of HPWL (x3.8 x 10th um), Cong. (x10-2), TNS (x10 ps), and WNS (x (x10 ps) for macro placement derived by different approaches. For HPWL and Cong., lower is better, while for TNS and WNS, higher is better. The results for DREAMPlace, Wiremask-EA and LaMPlace obtained from three independent runs with different random seeds, and report the mean and standard deviations (mea of each metric. Additionally, we report the average rank of these methods each circuit. We mark the best results in bold red, and we mark the second best results in underlined blue.
superbluel
superbluc3
superblue4
superblueS
superblue7
supesblue10
superbiue
superbliee88
HPWI
(#3370)
25.72
(=0.76)
7.42
(+2.38)
11.12
(=1.44)
6.12
(=0.8)
3,26
(#2.24)
17.38
(+0.05)
2.30
(#8.93)
36.07
Cong.
(+0.06)
2.02
(+0.01)
2,92
(+0.22)
L62
(+0.19)
1,92
(-0.09)
1.13
(+0.03)
141
(+001)
2.20
(+0.11)
1,03
DREAMPlace
TNS
(# (=8.899)
-5210.15
(77440.44)
-8029.97 97
(#:417.08)
-3764.22
(4:228.18)
-22321.9
(4:1188.3))
-7374.28
(#:18,47)
.7812.66
(#:3.53)
1126.11
(#249,91)
-751.27
-144.74
-1335.9
.241.24
.3928.92
.14.00
.339.27
107.05
.88.11
WNS
(#18.58)
(1:34677))
(116636)
(1:7700688)
(1:199555)
(1:118.8)
(4:1116
(=10.53)
Rank
3.25
2.75
2.25
85.71
12.68
8.12
34,94
5.39
21.22
11.74
38289.15
HPWI
(#1)32
(4:375)
(#7.47)
(=1.06
(+0.88)
(+1.98)
(16660.46)
Cong.
1.87
2,48
1.79
1.84
1,46
1.19
1.56
1.00
(100.10)
(20.02)
(10.39)
(20000)
(=0.08)
(10002)
(10.41)
(200.04)
WircMask-EA
TNS
(4164.00)
-2524.56
(1:154.44)
-2132.54
(4208.84)
-1966.08
(1:414.32)
-1628.77
(1.109.99)
(=1070.55)
.8370.66
(1: (114555)555
-18343.00 30
( (1000.69)
406.01
-155.00
-293.85
-107,72
-194
-76.86
-290.46
-635.80
-78.25
WNS
(+23.15)
(+34.09)
(+21.13)
(-25.71)
(-388)
(+60.06)
(+601.41)
(+8.65)
Rank
3.25
2.25
2.75
2.50
3,00
2:75
3.25
2.50
HPWL
68.10
33.37
8.36
31.06
7.40
24.47
16.58
3528.80
Cong.
2.05
2.49
1.92
0.98
1.87
1.19
1.28
1.00
ChiPFormer
TNS
2150.53
-2447.33
-1586.05
-3176.20
-1489.84
77822.58
-15426.07
-378.90
WNS
132.74
-229.20
-35.28
-202.47
-68.99
-256. 24
-322.05
-80.57
Rank
2.50
3.00
2.75
2.50
3.00
2:75
2.75
2.75
HPWL
(1177)
49.17
(#2.91)
22.25
(+1,94)
4.47
(26.25)
31.48
(=0229)
3,22
(+:2,66)
22.13
(+0.51)
7.61
(+7.14)
16.94
2.34
1.54
0.74
Cong.
(10.04)
(=0.03)
(1:0.0)
(20.15)
20,04
(1:0.2)
(#00011
(:20.02)
LaMPlace
TNS
(=272.73)
.1422.01
(1:115811
-1797.7
(1663.10)
-1424.31
(2:21.14)
2889.21
(4:201 6)
11885.32
(.1453.81)
-7613.01
(11524.61)
-1514.73
(=52.88
426.9
WNS
(3.233)
-12.331
(+46.00)
-174.94
(+9.61)
-84.01
(-29.39)
-178.18
(-7.28)
-66.02
(+21.05)
-224.34
(+11.04)
-36.87
(+11.62)
-66.93
Rank
1.50
1.50
1.00
1.75
1.25
1.50
1.75
1.25
4.3 ANALYSIS
Case Study We visualize the placement results for the compared methods in Figure In this case, existing methods exhibit excellent mHPWL results, but LaMPlace outperforms them on the actual design metrics. Notably, LaMPlace tends to place macros along the borders of the canvas, reserving the center for standard cells. This is a behavior of experienced designers. because this strategy, though increasing mHPWL, can improve the final results empirically (Chiou et al. 2016 Surprisingly, LaMPlace discovers this optimization technique without any prior knowledge. We further use commercial EDA tool, Cadence Innovus, analyze the final PPA results, demonstrating the efféctiveness of LaMPlace to actually enhance the chip quality. The results are in Appendix B.2
Correlation Analysis We present the correlations between the metries involved in this work in Figure The results are derived by collecting all layouts generated by the tested methods on all circuits. We calculate pair-wise Pearson correlation coefficients, which reflect their linear correla- tions. Figure 5aa) illustrates the correlation coefficients between the four evaluation metrics. The results indicate that HPWL and congestion exhibit a positive correlation, and TNS and WNS also show a positive correlation. However, HPWL and congestion do not significantly correlate with TNS and WNS. This suggests that placement is a complex multi-objective optimization problem, and optimizing single metric alone is insufficient. Figure 5] shows the correlation between the evaluation metrics and different optimization surrogates. The results show that the predicted values positively correlate with the true metrics. In contrast, the commonly used intermediate surrogate

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Published as a conference paper at ICLR 2025
1,30
0.78
400
.021
WSS TNS Cany
0.75
1.0
<:20
10:25
-0.66
-0.00
0.71
15
6.71
1.00
(a) 7:27 x
(b) ChiPFomer: mHPWI. x HPWL 8.36 x 10",, Cong. = 1.92 x TNS = 1586.05 x 10", WNS -85.28 x10
RFWL
Grng
TRS
Whg
HPWL = 11.60 x x00", Cong. 1.78 x
Pair-wise correlation coefficients between four evaluation metrics.
(a)
TNS 1920.33 100", WNS -87.09 x10
WNS TNS Cies EPWE
0.84
4027
4..11
-0.25
0.56
6.56
0.90
0150
0:01
0:31
0.11
NINM prlng grte
(c) DREAMPlace: mHPWL. 10 HPWL 6.59 x10", Cong. 1039x10
LaMPlace: mHPWT.
1
(b) Comelation enefficients between mHPWL, predicted value LaMPlace and four evaluation metries.
HPWL= 2.48 x .onn. = 1.04 x10 = x10?. = x10*
INS= 1NS=-1871.3x100 -N5==107.80x10"
Figure Visualization full-netlist placement results of su- perblue4 using different methods. Macros are marked in red, while standard cells are represented blue.
Fi Figure The Correlation analysis. The prefix 'p" de- notes the predicted values.
metric, mHPW1. fails to positively correlate with the metrics. The metric "Pred" represents the sum of predicted values, serving the optimization objective for placement introduced in Section 3.2 The results demonstrate that "Pred" has a positive correlation with all metrics, highlighting its ef- fectiveness serve an optimization objective. These findings reveal the fundamental reasons for LaMPlace's superiority in multi-objectic optimization compared to previous works.
conduct comparative experiments to demonstrate the effectiveness of the Lau- rent polynomial form. Specifically, in Equation [ define K set of integers indicating the orders terms in the polynomial. In the main experiments, we empirically set K {1, 0, -1, 2 We further investigate the effect of the choice of K, and the results are presented in Table in Ap- pendix [B.] The findings indicate that the Laurent polynomial form, rather than general polynomials, can indeed enhance performance.
Ablation Study
As shown in Equation g the optimization objective during the placement phase is defined as = ExE(s fxfx (H, X), which is the weighted summation of different metrics. We further conduct experiments to investigate the impact of the hyperparameters Appendix
>==>>M
Results are in Table 9 in
We also conduct an ablation study on the number of layers in the GNN architecture. The results are shown in Figure 12 in Appendix B.5) demonstrating that the model performance overall robust against the GNN architecture.
Prediction Error Analysis We analyze the correlation between the placement quality and the prediction error. The results shown in Figure [ Appendix B.7 The results demonstrate the positive correlation between the placement quality and the prediction error, while the placement quality is overall robust against the variations. We also present the training curves of several key metrics regarding the prediction error in Figure 14 in Appendix B.7
5 CONCLUSIONS
In this paper, we propose LaMPlace, novel macro placement method that learns a mask to optimize cross-stage metrics, rather than intermediate surrogate metrics. It introduces predictor, in the form of Laurent polynomial functions, for cross-stage metrics. This formulation derives a sequentially greedy policy for efficient placement. Experiments demonstrate that LaMPlace can significantly improve the chip quality in terms of several key design metrics.
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REPRODUCIBILITY STATEMENT
We provide the following information for the reproducibility of our proposed LaMPlace. method detailed in Section 3
The
The implementation details are provided in Appendix A The
experimental details and results are in Section and further elaborated in Appendix A.5 The code
publicly available at httph:::///// /attpp://github... com http://///AAAAA--STSSAAAAAAAAAA-
ACKNOWLEDGMENTS
The authors would like to thank all the anonymous reviewers for their insightful comments. This work was supported in part by the National Key R&D Program of China under con- tract 20227DD1 19801, National Nature Science Foundations of China grants U23A20388, and 62021001. This work was supported in part by Huawei as well.
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A IMPLEMENTATION DETAILS
A.1 GRAPH REPRESENTATION
2- Z-path
-path
directed 2-
not directed 1-path
path
Figure 6: Illustration of directed and undirected k-paths. The blue rectangles represent macros and orange dots represent cells. the left figure, we do not conside the directions. In the right figure, we consider both directed and undirected paths.
We use a graph & represent each circuit netlist. A eircuit netlist often comprises hundreds of macros and numerous standard cells. We treat macros as nodes and capture the cell information as edge features. As shown in Figure 6 we denote path (which connected by nets) consisting cells between two macros k-path. We refer to k as the depth of such path. Notice that each net consists of both input and output components, i.e., we should consider their directions. Therefore, take directions into consideration by defining both directed k-paths and undirected k--paths. For any two nodes and j, we denote the number of directed k-patts between them as Ar(k) Similarly, kj we denote the number of undirected k- k-paths between them as A/(R) In G, we add an edge between two nodes if there exists directed path with depth not exceeding D between them, there exists an undirected path with depth not exceeding D'. Here and D' represent the maximum depth of directed and undirected paths that consider, respectively.
The dataflow metric is often used in the EDA community to capture the "information closeness" between two macros (Vidal-Obiols al., 2019: 202I). Here, introduce dataflow our edge feature to capture the cell information. For directed paths, we define:
(D)
(11)
USAED
For undirected paths, the corresponding dataflow is then defined as:
(DD')
Σ 2
(12)
OSkED
Formally, we represent netlist as a graph & with node features and edge features E. The node feature consists of five channels:
h = (size_x, x., size.y,, node_area, sqrt_node mode,, num aum_pins,).
(13)
The edge feature consists of de = D+ D'+ +4 channels. Specifically, the feature of the edge between nodes and j is defined as:
(D)) M ei (J .N10 .... .NDD Soj
(D)
ArrlD')
(14)
In our work, we D 9 and D' 1, thus obtaining a 14-channel edge feature.
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A.2 L-MASK
LaMPlace employs a "learnble mask", i.e., L-mask, for the opti- mization of general metrics of chip netlist. In Appendix A.I have introduced the concept of dataflow, which is designed to quantify the connectivity properties between any two macros, tak- ing standard cells into consideration. As shown in Equation 2 the coefficients d (A.8) take similar form as the dataflow. They capture the pair-wise relationships between macros. Therefore, we refer "learnable flow", i.e., L-flow. Compared to dataflow, these L-flows have
As described in Section 2.3
these coefficients stronger representational capacity, as they are learned by predicting general cross-stage metrics and can better correlate with the final design PPA.
L-mask is derived from L-flow and has a similar form with the wiremask. Specifically, it is an pixel-level feature map that represents the increase in the L-flow value maero is placed at specific position. We detail the computation process for the L-mask in Algorithm, | We also visualize the process of L-mask guided placement in Figure 7
Algorithm 1 Calculation of L-Mask
Input: Placed macros P. macro to be placed macro,, L-flow A (A,8)
Parameters: Number of canvas partitions n, weights orx.
Output: L-mask
Initialize L as n grid, with elements of 0
for macro, in P do
(z the grid position of macro,
Initialize Gy as n. X n grids for < to n do
for y f 0 to
do
G. G.[r] f I
G
y
R (G2 23)² (G, yj )2 quantifying the distance from grid cells to (xzz f1)
L L+ Σ, as En A (k.2) R
Return: The L-mask L
L-mask
(b) Legalization- mask
(c) Pre-Placement
(d) Step of Placement
Figure 7: Illustration of L-mask guided macro placement. (a) the L-mask. the blue pixels indicate the local minimum points. (b) A legalization mask is applied to the L-mask to ensure no overlap. The white grids indicate the legal positions for placement. (c) The legal position (no overlap) with the lowest L-mask value is selected to place the next macro, which is represented by the blue macro (d).
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A.3 PLACEMENT ALGORITHM
We formulate the macro placement task as black-box optimization problem. We then follow Shi al. (2023a) and employ an evolutionary algorithm (EA)-where the genotype-phenotype mapping is greedily guided by L-mask- placement. The random initial process records one best solution with the lowest predicted value, and the following evolutionary process improves this solution via random mutation. The mutation operators are implemented by randomly swapping the positions of two macros. More algorithm details are demonstrated Algorithm
Algorithm 2 Placement Algorithm
Input: A netlist G, the L-flow A A (A,k)
Parameters:
Number of initial random turns Ninit, Number of evolutionary turns Nea
Output: Placement P
(2,
For each macro i, compute the sum of its corresponding coefficients, i.e., wy = Ej.n, Order all macros decreasingly, denoted as U1, Um, according to wi;
(4.5
for in Nua do
Randomly initialize the position each macro e4 denoted as pi Initialize placed-macre positions, denoted as P Initialize the best placement p with the best value V for each macro V2 do
Generate L-mask L,, given the placed macros P and L-flow A (A,k) as in Algorithm + the of grids that has the minimum values in L,
Select the grid from Q, which is the closest to the macro initial position
Update the position the macro o; to that of g Generate the predicted value V of the final placement P
if V V then
pa P *++V
for in New do Initialize the position each macro i as p; from Swap the positions of two randomly selected macros in p for each macro do
Generate L-mask L,, given the placed macros P and L-flow A (A.k) Q + the set of grids that has the minimum values in L;
A as in Algorithm
Select the grid g from Q, which is the closest the macro initial position pt
Update the position of the macro to that of Generate the predicted value V of final placement
if V < V then
Pa +- P
V* - V
Return: The best placement P*
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A.4 BENCHMARK DETAILS
Table 2: Statistics of public benchmark circuits.
Circuit
#Macros
#Standard Cells
#Ncts
#Pins
Area Uti((%)
superblue1
424
1215820
1215710
3767494
85
superblue3
565
1219170
1224979
3905321
87
superblue4
300
801968
802513
2497940
90
superblue5
770
1090247
1100825
3246878
85
superblue7
441
1937699
1933945
6372094
90
superblue
1629
984379
1898119
5560506
87
superblue16
985909
999902
3013268
85
superblue18 18
201
771845
771542
2559143
85
Table 2 details the statistics for eight circuits from the TCCAD2015 dataset. Since larger modules generally exhibit greater complexity, modules larger than ten times the average area selected as macros for placement.
A.5 EXPERIMENTAL DETAILS
We report some important hyperparameters and settings in this section. In our work, all the ex- periments are conducted on a single machine with NVidia GeForce GTX 3090 GPUs and Intel(R) Xeon(R) E5-26667 v4 CPUs 3.20GHz.
In the training stage, we used DREAMPlace to generate 200 layouts and the corresponding metrics for each of six training circuits. This involved conducting 200 mixed-size placement runs for each circuit, each run using different seed and the default settings. We use the Adam optimizer to train our model for 400 epochs with a batch size of 60. We select the best model checkpoint based on the Kendall coefficient evaluated on the validation set. The Kendall coefficient is used to evaluate the ranking performance (Chen et al. 2023). The learning rate is initialized to 0.001 and decays exponentially.
In the placement stage, since LaMPlace employs the same EA-search framework as WireMask-B -EA, which is thoroughly discussed in (Shi al. (023a),, EA. The only difference is replacing the mHPWL- WireMask with our L-mask. Both methods perform 50 random search iterations and 20 evolutionary iterations obtain the final macro place- ment results. We fine-tune the pre-trained Chipformer model using its open-source code to generate macro placements for each test case. Since LaMPlace, Wiremask-EA and Chipformer all treat the chip canvas as grid, as proposed by (Lai et al.) (002)). we partition the grid into 84 x 84 across all the cases, aligning with (Lai et al. 2023). The evaluation of macro placement conducted through cell placement using DREAMPlace and timing analysis with OpenTimer. In order to reduce the influence of randomness record the best evaluation result. For DREAMPlace, we obtain the mixed-size placement results with default settings.
the same configurations WireMask-
reasonable way, we pick the five best macro placement layouts and
A.6 MODEL ARCHITECTURE AND HYPERPARAMETERS
We provide the model structure and some apper-paraeeter details of our prediction model in this section. All the MLPs have two layers and use ReLU () as the activation function. We use the graph introduced in as
as the input. The model papre-paraeeters shown in Table 3
The input node and edge features are embedded using two MLP encoders. Next, multiple GNNs employed to extract graph information, generating the node embeddings h,, After embedding h; through the output encoder MLP, pairs of linear layers are used to obtain the Laurent polynomial coefficients between two nodes, shown in Equation 2 Specifically, the message-passing process
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Table Hyper-parameters of prediction model
module
layer
layer size
output size
16 x 256
edge encoder
MLP_1
ReLU ()
(num of edges, 256)
256 x 256
3 x 256
node encoder
MLP 2
ReLU 256 x 256
(num of nodes, 256)
graph encoder
GNN x5
256 x 256 for all MLPs
(num of nodes, 256)
256 256
ouput encoder
MLP 3
ReLU () 256 256
(num of nodes, 256)
L.-flw decoder
Linear Layer x16
256 x 256 for layers
(num of nodes, num of nodes, 16)
in GNN can be represented by the following equations:
mij = tbe (Contac (h)))
m, Σ mji:
(15)
JEN(i)
(1-1) = (n m;),
where (1) is the set of neighbors of node, and des Φn are non-linear mappings implemented by MLP.
A.7 PAIR-WISE RANK LOss
Learning to rank is a machine learning framework that learns to optimize the correlation between predicted values and ground truth metrics. The pair-wise ranking method simplifies this problem into a binary classification task, focusing on distinguishing which candidate in given pair is better. Given a pair of macro placement solutions, (X,, X,), the predictor outputs their corresponding predicted metrics, (0i, 0z). If the true metrics satisfy y; > Yj. denoted as X; > Xj. the predicted probability of X, being better than X, is:
P(X: X,)
(16)
cxpp-(ppp) (Ú: i;}}
The rank loss for this pair is computed using binary cross cross-entropy function, incorporating the difference caused by swapping the ranks of samples and j:
Lij = log [1 exp(-(0 9))H))
(17)
where AZy quantifies the difference in ranking caused by the swap, calculated using the softmax function:
exp(ys)
exp(u;)
A = Ep exp(Up) Σ, exp(Up)
(18)
The total rank loss aggregates the pair-wise losses across all pairs and metrics:
LRank
Σ
Σ
Z ma, log [ exp ( (A)
(19)
Mey.my 2802.mg
where À denotes each metric, and
ymg ) - exp
())
( (2)
exp
Ze 02.
(20)
Eam exp yem
(A)
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B ADDITIONAL RESULTS
B.1 RESULTS ON CHIPBENCH
We conduct experiments on ChiPBench (Wang et al. 2024b). We run the placement algorithm of LaMPlace directly on industrial chips from ChiPBench without further fine-tuning, and follow their proposed workflow to obtain the final PPA metrics. The results are in Table
Table 4: Post-routing PPA results- -Wireleghh (um), Congestion, Power (W), WNS (ps), TNS (ps) and NVP-on ChiPBench. For WNS and TNS, higher is better, and for other metrics, lower better. Additionally, best results in bold red, and we mark the second best results in underline blue. LaMPlace achieves the best overall performance though baselines tuned the dataset while LaMPlace not.
report the average rank of these methods each circuit. We mark the
SWerV wwrppwr
urianc133
bp_fe
bp
bp_be
ariane 136
Wirelength
4525348
6348638
2823861
9347541
3518916
6831531
Congestion
0.366
0.2138
0.5084
0.4088
0.5165
0.2306
Power
0.645674
0.367289
0.2942135
0.2500424
0.458286
0.570734
DREAMPlace
WNS
-1 -1.06067
-0.540441
-1.11661
-2. 12.10779
22 26144
-1.35843
TNS
-780.20
-690.27
473.261
-14.6088
-3648.02
-3269.22
NVP
1608
2307
1849
192
6026
4350
Rank
2.29
2.00
2.14
1.86
3.00
2.14
Wirelength
4854661
6583143
2783740
10002159
3574875
6945252
Congestion
0.41
0.23
0.51
0.44
0.52
0.24
Power
0.67
0.37
0.31
0.25
0.47
0.57
WireMask-EA
WNS
-1.02747
-0.417093
-1.66571
-1,93591
2.14159
-1.72648
TNS
-873.506
-329.353
-777.42
-21.8123
-4093.97
-4268.61
NVP
1518
1970
2628
326
5131
3628
Rank
2.71
2.86
3
3
2.286
Wirelength
5019849
6581086
2073376
8970666
3572070
6869186
Congestion
0.43
0.23
0.38
0.39
0.52
0.24
Power
0.67
0.37
0.30
0.25
0.43
0.57
Chipformer
WNS
-1.19
-0.55
-1.20
-1.75
-2.17
-1.39
TNS
-1282.24
-860.95
-1000.19
-502998
-3541,82
-3603.53
NVP
2139
2703
2714
2179
5100
3609
Rank
2.67
2.50
3.17
3.00
3.33
3.33
Wirelength
4123153
6947307
1874385
9840460
2854486
7051781
Congestion
0.35
0.24
0.34
0.42
Power
0.636157
0.364683
0.294396
0.257111
0,415
0,545532
LaMPlace
WNS
-1.02
-0.19
-1.07
-1.73
-1.97
-1.13
TNS
-740.69
-120330
-880.39
-53.47
2325.43
2806.97
NVP
1424
1533
2676
400
4687
3469
Rank
1.00
2.00
1.83
2.83
1.00
2.00
B.2 CASE STUDY ON PPA METRICS
We further evaluate those methods with the actual post-routing PPA metrics, using the Commercial Tool Innovus. The test metrics include routing wirelength (rWL), horizontal and vertical overflow (rOverflowHl and YOverflow respectively), post-routing timing metrics (TNS, WNS) and number of violations (NVP), i.e., the count of timing violation paths in chip design. The detailed results
are provided in Table 5 6 and 7 The visualization of the placement results are in Figure 3 and
10 Figure displays histogram of the timing slack distribution for violated paths. Compared to other methods, the distribution for LaMPlace placements is more concentrated near zero. These results demonstrate that LaMPlace can significantly enhance the final PPA results.
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Table 5: Post-routing PPA results on superblue4, computed using Innovus.
(WL(x10'um)
|Overflow((%)
rOverflowV(%)
WNS(ps)
TNS(x10'
NVP
DREAMPlace
2.15
71.62
46.67
-105.013
-4.47
45567
Wiremask- EA
1.90
70.90
19.40
-109.103
-2.69
22007
Chipformer 1.84
69.93
17.51
-85,923
-2.17
22627
LaMPlace
1.53
9.93
0.32
-87.170
-1.77
13045
Table 6: Post-routing PPA results on superblue 16, computed using Innovus.
WWL(x0'M) (WL(x10uum)
(OverflowH(())
(DverfloW((%)
WNS(ps)
TNS(x 10"ps)
NVP
WireMask-B EA
1.13
9.21
0.15
-53.04
-2.12
21399
Chipformer
1.17
6.44
0.17
-91.19
-2.73
34606
MPlace
1,41
16.31
1.66
-57.18
-1.90
30737
PolyMaP
1.04
1.26
0.10
-45.06
-1.36
18776
Table 7: Post-routing PPA results on superblue 18, computed using Innovus.
rWL(x10'um) um)
rOverflowH(*)
rOverflowV(CS
WNS(ps)
TNS(x 10"ps)
NVP
WireMask-EA
0.99
20.18
17.38
-61.63
-1.33
33151
Chipformer
0.95
18.41
12.44
-50,227
-0.64
17365
DREAMPlace
1.92
69.31
15.41
-65.014
-1.94
28477
PolyMaP
0.95
9.48
5.79
-88.967
-0.51
11495
(a) WireMask
(b) ChiPFormer
(c) DREAMPlace
(d) LaMPlace
Figure 8: Visualization of post-routing results on superblue4 using Commercial Tool Innorus. The red area denotes the overflow area.
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RAGORAIE 31200157
-0. CMC
(a) WireMask EA
(b) ChiPFormer
(c) DREAMPlace
(d) LaMPlace
Figure 9: Visualization of post-routing results superbluel6 using Commercial Tool Innovus. The red area denotes the overflow area.
(a) WireMask EA
(b) ChiPFormer
(c) DREAMPlace
(d) LaMPlace
Figure 10: Visualization post-routing results on superblue18 using Commercial Tool Innovus. The red area denotes the overflow area.
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800
1350
700
1200
1050
500
400
600
300
200
300
150
115830 019900022900--00 .77220
-90110 -00-000700000 -70330 -00540-50450
40360
30270
20180 80000000000
(a) WireMask-EA
(b) ChiPFormer
900
1200
800
700
900
600
400
600
300
200
300
+12200101430-90160 778890 67620 56350 45080 -3310 -225-02250000 -11270
-96660 45920 (000066440..0
537000 42960
(c) DREAMPlace
(d) LaMPlace
Figure 11: Histogram of post-routing timing slack results on superblue4 using Commercial
Tool Innovus. The x-axis denotes the timing slack, and the y-axis quantifies the number of paths falling within specified timing slack intervals.
B.3 COMPARISON STUDY ON K
Table 8 presents the results of different choices of K, which is defined in Equation I The experi- ments are conducted with the same settings as the main experiments, except for the different choices of K. According to the results, we empirically set K = (1,0, -1, -2 in the main experiments.
Table 8: Comparisons of HPWL (x3.8 10 um), Cong. (x10-2), TNS (x 10 ps), and WNS (x103 ps) for macro placement derived by LaMPlace under different choices of K.
K
superbluel
superbluc3
superblue4
superblue5
superblue7
superblue
superblue16
superblue18
Cong.
1.51
2.34
1.54
1.54
0.87
1.06
2.03
0.74
[1.0, (1,-)
2422.01
-1797.7
11424.11
-8899221
-1585.32
7613.01
-1514.73
WNS
-12.31
-174.94
84.01
-178.18
.6.02
-22.344
-36.87
66.93
HPWL
31.05
18.44
4.49
20.59
4,99
Cong.
1.62
2.41
1.64
1,523
1.31
0.99
2.05
0.78
(0.-1.22)
-2157.98
1764..7
2541..6
-1449.57
-7203.3
-941.28
-378.25
WNS
167.51
-381.78
104.92
-193.88
-51.11
-235.91
-30.89
-69.61
27.11
3.5
25.32
8.46
Cong.
1.8
2.5
1.85
1.98
1.67
1.25
2.12
0.87
(2,1,0,
TNS
-1834442
-1839.52
-1713.99
-6337.1
-3311.24
-7866.22
-1487.49
-375.03
WNS
1140.4
-185.5
108.25
-164.98
447.55
-292.77
-33.96
-50.09
HPWL
38.08
21.57
45.29
4.99
11.6
28.47
Cong.
1.63
2.47
1.58
1.36
1.17
1.02
2.06
0.83
(1,0,-2)
TNS
33100.32
2496.02
-148188
2363.55
11702.37
8591.41
1194.61
250.23
WNS
166.55
402.34
.4.95
-152.54
-6.42
-394228
-36.36
-73.41
B.4 COMPARISON STUDY ON {aAJAEA
We further study how the coefficients {ax bee affect the placement results. To this end, we adjust {ax Faea emphasize each of the metrics on the circuit superblue4. The results show that adjusting the hyperparameters can effectively control the final placement results, In main experiments, we simply set ax for all X.
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Table Results of different weights of metrics. Here the four coefficients correspond HPWL, Cong., TNS, and WNS, respectively. The results are obtained on superblue4. We highlight the best result for each metric in bold, which aligns with our coefficients modification.
fax
HPWL
Cong.
TNS
WNS
11,1,1,1}
5.47
1.63
-1763.62
-123.71
1,,1,
4.734
1.47
-1708.66
-81.45
11,1,5,1]
7.28
1.71
-1579.60
-90.47
11,5,1,1}
4.35
1.41
-1880.33
-84.07
1,,1,1,13
1.83
1.45
-1006.05
-99.03
B.5 COMPARISON STUDY ON GNN LAYERS
We conduct additional ablation study on the number of layers the GNN architecture. The
results are shown in Figure 12 demonstrating that the model performance is overall robust against the GNN architecture.
0.006
Layers
Layers
Ranking Loss
0.005
Layers
0.004
0.003
0.002
0.001
1000
2000
3000
Step
Figure 12: Ablation study on the number of layers GNN. We present the training curves of the ranking loss with different GNN layers. The results robust against the model architecture.
B.6 RUNTIME ANALYSIS
We report the running time of the compared methods in Table TO. Both LaMPlace and Wiremask-EA undergo 50 initial turns followed by 20 evolutionary turns. The runtime for Chipformer is derived from fine-tuning pre-trained model, while DREAMPlace conducts mixed-size placement.
Table 10: Running time (h) of compared methods to obtain the placement results.
superblue!
superblue3
superblue4
superblue5
superblue7
superblue10
superbluc16
superblue18
DREAMPlace
0.28
0.25
0.14
0.34
0.46
0.47
0.20
0.18
Wiremask-EA
0.15
0.34
0.15
0.46
0.25
1.28
0.05
0.15
Chipformer
0.95
0.35
2.09
0.17
LaMPlace
0.22
0.38
0.11
0.72
0.21
3.16
0.01
0.05
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B.7 ANALYSIS ON TRAINING LOss
We analyze the correlation between the placement quality and the prediction error. The results are shown in Figure [3] The results demonstrate the positive correlation between the placement quality and the prediction error, while the placement quality is overall robust against the variations. We also present the training curves of several key metrics regarding the prediction error in Figure 14
Placement Quality
0.6
0.4
0.2
0.00
0.05
0.15
Ranking Loss
Figure 13: The correlation between placement quality and prediction error. We use models from 8 different checkpoints compute ranking loss and perform macro placement superblue 16. The placement quality is evaluated by the average normalized values the four considered metrics, lower indicating better. The results show that placement quality positively correlates with ranking loss, but it is still robust against variations.
1.1
Bocking Loos
MSB Less
0.40
0.9
1000
2000
3000
3000
Stopp
Stegs
Peanson Carceltion Coetleiest
0.6
Kondll's The Chefficent
0.5
0.5
0.4
0.3
0.3
0.2
1000
2000
3000
1000
2000
5000
Stop
Step
Figure 14: Training curves of several key metrics regarding the prediction error. The metrics include MSE loss, pair-wise ranking loss, Pearson and Kendall's Tau correlation coefficient. The results are computed the validation set.
B.8 VISUALIZATION OF PLACEMENT
We include the visualized results of DREAMPlace, WireMask-EA, ChiPFormer and LaMPlace in
Figure 18 16 17 and 15 The visualizations highlight the distinct placement patterns of differ- ent methods. ChiPFormer and WireMask- EA often place macros irregularly toward the center. DREAMPlace places macros and cells densely in the central area, optimizing HPWL but leading
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to suboptimal PPA. In contrast, LaMPlace learns to place macros edges corners. From the view of an expert designer, this usually a preferred practice as benefits the back-end processes.
(a) superblue1
(b) superblue3
(c) superblue4
(d) superblue5
superblue7
( superblue10
(g) superblue16
superblue
Figure 15: Visualization of full-netlist placement results of all circuits in ICCAD2015 using LaMPlace. Macros are marked in red, while standard cells are represented in blue.
superblue1
(b) superblue3
(c) superblue4
(d) superblue5
(e) superblue7
( superblue10
(g) superblue16
(h) superblue
Figure 16: Visualization of full-netlist placement results of all circuits in ICCAD2015 using WireMask-EA. Macros marked in red, while standard cells are represented in blue.
superblue1
(b) superblue3
(c) superblue4
(d) superblue5
(c) superbluc7
(f) superblue10
(g) superblue16
(h) superblue18
Figure 17: Visualization of full-netlist placement results of all circuits in ICCAD2015 using ChiPFormer. Macros are marked in red, while standard cells are represented in blue.
26

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Published as a conference paper at ICLR 2025
(a) superblue1
(b) superblue3
(c) superblue4
(d) superbluc5
(e) superblue7
(1) superblue10
(g) superblue16
(h) superblue
Figure 18: Visualization of full-netlist placement results of all circuits in ICCAD2015 using
DREAMPlace. Macros are marked in red, while standard cells are represented in blue.
B.9 DREAMPLACE RESULTS DISABLING TIMING-DRIVEN OPTION.
We disable the timing-driver option in DREAMPlace, and evaluate timing results using OpenTimer. The results are included in Table I1]
Table 11: Evaluation results HPWL (x3.8 10 um). Cong. (x10- 3), TNS (x10y ps), and WNS (x103 ps)-fof for DREAMPlace (mixed- size with timing liming-driven disabled).
superblue1
superblue3
superbluc4
superblue5
superblue7
superblue
superblue16
superblue18
HPWL 22.8
26.5
8.2
29.02
20.76
1.81
10.5
7.29
Overllow
2.29
1.89
2,26
2.36
144
1.43
2.16
1.92
TNS
-6888.7
2669..75
1640.86
-17115.8
-4233.2
-343.664
-2235.03
-44.233
WNS
-236.96
-327.83
-70.9
-362.18
-248.36
-268.71
-103.83
-73.2
B.10 ABLATION STUDY ON TRAINING DATASET
We conduct an ablation study evaluate the impact of different sizes of the offline training dataset. In the manuscript, we use offline data from circuits superbluel, 3, 4, 5, and 10 for training. In this ablation study, we train our model using the following subsets of circuits: (1) superblue and 3, and (2) superbluel, 3, 4, and 5. We provide the placement evaluation results for each ablation setting in Table 12 The results demonstrate the robustness of our method to varying amounts training data. Also, it demonstrates that using larger training dataset shows some improvement in generalization performance (better placement results for superblue16. 18).
Table 12: Comparisons of HPWL(X3.8 x 10 um), Cong, (x10 2), TNS (x10² ps), and WNS 10 ps) with different training data sizes.
Train circuits
superbluel
superbiue3
superbiued
superbine5
superblue7
superblue
saperblue16
superblue
HPWL
$2.26
13.65
5,31
29.80
2.48
23.41
6.48
14.06
Overflow
1.39
2.28
1.16
1.284
0.89
0.2
2.03
0.89
TNS
-2126.91
-1460.06
1868.52
2561.76
-2122.93
8652.82
-1420.6
-86.32
WNS
-123,28
-212.77
108.27
-165.99
-61.64
266.42
-3.97
-71.44
superbluel
superbluc3
superbine4
superblue5
superbluc?
superbluct0
superbluc16
superbluet8
IPWL
44.29
16.58
6.54
46.54
121
16.71
6.63
33,78
Overllow
0.74
TNS
-1965.00 85
-1882.6
-1671.95
2659.65
.98.51
8944.52
-151 .4
-275.91
WNS
-134.71
-230.69
-77.99
-156.55
-60.66
324.07
46.02
Train on six circuits
superbluel
superbluc3
superbiue4
superbiue5
superblue? 3.41
superbluet0
superbinet6
superbine18
HPWT.
52.56
18.38
3,6
34,35
23.16
5.07
29.84
Overllow
1.43
2.39
1.21
1.39
0.98
2,08
0.75
TNS
.0020.33
1456.38
.3388881
-2719.28
1160.47
7339.67
.98.83
-35.66
27

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Published as a conference paper at ICLR 2025
C DISCUSSIONS
The increasing availability of large datasets in industrial environments highlights the potential of offline training for Al-driven optimization in many scenarios (Geng al. 2025 Liu et al. [025 2024a). In large EDA companies, where substantial chip data has already been accumulated, the focus shifting towards leveraging existing datasets rather than repeatedly collecting new online data. This trend underscores the feasibility and effectiveness of offline pre-training approaches for modern placement tasks.
Our method demonstrates remarkable data efficiency and generalization capabilities. With rela- tively modest dataset of 1, 200 placement datapoints derived from open-source circuits, the model achieves strong performance across unseen chip designs. This modest computational demand for offline pretraining positions our approach as both practical and scalable. In contrast, prior reinforce- ment learning (RL)-based methods often necessitate thousands of online training steps, significantly increasing computational overhead and resource requirements (Yang et al. 2022 Liu et al. 2024b).
Future research directions include exploring innovative data augmentation strategies further hance gencralization (Geng et al. 2023). While directly perturbing chip layouts may inadvertently alter PPA metrics, alternative strategies, such generating placement solutions using diverse place- ment methods or augmenting the dataset with more open-source netlists, hold promise. However, these strategies can be time-intensive and require further investigation. Expanding the dataset and refining augmentation methods are priorities for future work, aiming to strengthen the applicability and robustness of offline-triined models in diverse design environments.
28


Reviews:
[{"review_id": "is6uL26EMw", "reviewer": "Reviewer_wAg4", "summary": "This paper presents LaMPlace, a novel machine learning method aimed at enhancing macro placement in chip design by prioritizing cross-stage metrics, such as timing performance, over intermediate metrics. The approach employs an offline-trained predictor to generate a pixel-level mask that evaluates the impact of macro placements on design metrics, followed by a greedy algorithm for placement optimization. Experimental results demonstrate a noteworthy average improvement of 9.6% in chip quality, with significant enhancements of 43.0% in WNS and 30.4% in TNS.", "questions": "- In Figure 9, related to DREAMPlace, there are blank rectangular areas, and some macros appear to overlap. Could you clarify this observation? Additionally, could you provide visualized results for the baseline method?\n- The timing-driven option in DREAMPlace does not seem to support macros effectively. Can you present results with this option disabled?\n- How does LaMPlace handle macros that are smaller than the grid size?\n- Some tables, such as Table 4 and Table 8, are missing units. Could you rectify this oversight?", "limitations": "", "rating": 6, "confidence": 5, "soundness": 3, "presentation": 3, "contribution": 3, "strengths": "+ The method shows strong zero-shot inference capabilities, allowing for effective generalization to unseen designs without requiring extensive training samples in the offline phase.\n+ It successfully optimizes cross-stage metrics, including HPWL, WNS, and TNS, concurrently, which is a significant advancement in macro placement techniques.", "weaknesses": "- The algorithm struggles with placing macros that are not edge-connected, limiting its effectiveness in scenarios where macros do not have interconnections.", "quality": null, "clarity": null, "significance": null, "originality": null, "strengths_and_weaknesses": "", "was_revised": false, "final_justification": "", "rebuttal": "", "claims_and_evidence": "", "methods_and_evaluation_criteria": "", "theoretical_claims": "", "experimental_designs_or_analyses": "", "relation_to_broader_scientific_literature": "", "essential_references_not_discussed": "", "other_strengths_and_weaknesses": "", "other_comments_or_suggestions": "", "questions_for_authors": "", "summary_of_paper": "", "summary_of_recommendation": "", "technical_quality": "", "clarity_of_presentation": "", "potential_impact": "", "robotics_focus": "", "quality_of_limitations": "", "questions_for_rebuttal": "", "reasons_to_accept": "", "reasons_to_reject": "", "questions_to_authors": "", "extra_scores": {}}, {"review_id": "zC2xkkF26z", "reviewer": "Reviewer_cJoe", "summary": "This paper introduces LaMPlace, a machine learning-based approach to optimize macro placement in EDA by focusing on cross-stage metrics that impact the final quality of chip designs. Traditional methods often optimize surrogate metrics, which are simpler to compute but do not directly correlate with final chip performance. LaMPlace tackles this by training a predictor to estimate these cross-stage metrics offline and generating a pixel-level mask to inform placement decisions efficiently. This work improved timing performance metrics like WNS and TNS, etc. Experimental results demonstrate that LaMPlace achieves significant improvements, with an average increase of 9.6% across key metrics.", "questions": "None", "limitations": "", "rating": 8, "confidence": 4, "soundness": 3, "presentation": 3, "contribution": 4, "strengths": "Focus on final metrics and thus improved results: LaMPlace addresses a critical gap by targeting final chip quality metrics rather than intermediate surrogate metrics.\n\nEfficiency: By using a pre-trained predictor, the proposed method reduces the high computational cost associated with evaluating cross-stage metrics during placement.\n\nZero-shot Generalization: The method demonstrates strong generalization on unseen benchmarks, showing adaptability without extensive fine-tuning.", "weaknesses": "Computational Complexity: Despite its efficiency improvements, the approach still relies on a complex training phase that may limit its practical applications in resource-constrained environments.\n\nPotential Overhead in Prediction: Generating the placement mask may still introduce additional computational overhead, particularly when applied to larger, more complex designs.", "quality": null, "clarity": null, "significance": null, "originality": null, "strengths_and_weaknesses": "", "was_revised": false, "final_justification": "", "rebuttal": "", "claims_and_evidence": "", "methods_and_evaluation_criteria": "", "theoretical_claims": "", "experimental_designs_or_analyses": "", "relation_to_broader_scientific_literature": "", "essential_references_not_discussed": "", "other_strengths_and_weaknesses": "", "other_comments_or_suggestions": "", "questions_for_authors": "", "summary_of_paper": "", "summary_of_recommendation": "", "technical_quality": "", "clarity_of_presentation": "", "potential_impact": "", "robotics_focus": "", "quality_of_limitations": "", "questions_for_rebuttal": "", "reasons_to_accept": "", "reasons_to_reject": "", "questions_to_authors": "", "extra_scores": {}}, {"review_id": "LczYwoqEZR", "reviewer": "Reviewer_pziW", "summary": "This work proposes a novel learning-based macro placement algorithm which learn a mask to optimize multiple cross-stage metrics. The performance of this algorithm is significant especially as the timing metrics, i.e., TNS and WNS.", "questions": "Thanks to the authors’ contributions for proposing this novel macro placement algorithm and performing comprehensive experiments. Meanwhile, this paper is well-written and easy to read.\n\nI still have some questions about the technical contents and experimental settings.\n\n1. “Notably, this function is translation-invariant with respect to the macro positions.“ Even if the relative positions of two macros remain unchanged for chip placement, the final design metrics (e.g., congestion and timing) will still change. This is because the macros' positions relative to the chip boundary affect the placement of other standard cells. Therefore, I wonder if there is a more detailed explanation of “translation-invariant”.\n2. More explanation about pair-wise ranking could be included in the paper.\n3. The final metric \"HPWL\" often serves as a surrogate metric in the design flow. \"Wirelength\" is a common final metric, that most people are concerned with, to replace \"HPWL\".", "limitations": "", "rating": 8, "confidence": 4, "soundness": 4, "presentation": 4, "contribution": 3, "strengths": "1. The idea of L-flow and L-mask is novel and the improvement is significant.\n2. Comprehensive experiment and analysis.", "weaknesses": "Some parts of technical contents and experimental settings should be explained.", "quality": null, "clarity": null, "significance": null, "originality": null, "strengths_and_weaknesses": "", "was_revised": false, "final_justification": "", "rebuttal": "", "claims_and_evidence": "", "methods_and_evaluation_criteria": "", "theoretical_claims": "", "experimental_designs_or_analyses": "", "relation_to_broader_scientific_literature": "", "essential_references_not_discussed": "", "other_strengths_and_weaknesses": "", "other_comments_or_suggestions": "", "questions_for_authors": "", "summary_of_paper": "", "summary_of_recommendation": "", "technical_quality": "", "clarity_of_presentation": "", "potential_impact": "", "robotics_focus": "", "quality_of_limitations": "", "questions_for_rebuttal": "", "reasons_to_accept": "", "reasons_to_reject": "", "questions_to_authors": "", "extra_scores": {}}, {"review_id": "xXUalUCrq1", "reviewer": "Reviewer_xPKq", "summary": "The paper introduces LaMPlace, a novel method for macro placement in chip design that focuses on optimizing cross-stage metrics, such as timing performance, which are crucial for the final chip quality. LaMPlace addresses this by learning a mask that guides the placement process based on cross-stage metrics. The proposed method involves (1) training a predictor on offline data to estimate cross-stage metrics, and (2) using this predictor to generate a mask, which is a pixel-level feature map that quantifies the impact of placing a macro in each chip grid location on the design metrics. This mask enables placement decisions based on cross-stage metrics rather than intermediate surrogate metrics. The paper demonstrates the effectiveness of LaMPlace on commonly used benchmarks, showing improvements in chip quality across several key design metrics, including WNS and TNS.", "questions": "1. Ablation study on the size of the offline dataset. What are the results with different sizes of offline dataset?\n2. The authors claim that they will release the code once the paper is accepted. Is it possible to discuss more implementation details or release the code for review?", "limitations": "", "rating": 8, "confidence": 4, "soundness": 3, "presentation": 3, "contribution": 3, "strengths": "1. The paper introduces a unique approach to macro placement that directly addresses the optimization of cross-stage metrics, crucial for the final chip quality. Existing methods often focus on optimizing intermediate surrogate metrics, which can lead to sub-optimal chip quality.\n2. The proposed method, LaMPlace, has been demonstrated to be effective in improving chip quality across several key design metrics, including WNS and TNS, which are crucial for timing performance. The paper provides great empirical results on commonly used benchmarks, showing significant improvements in chip quality.\n3. The use of a mask for placement optimization allows for efficient placement decisions based on cross-stage metrics. It enables the optimization of cross-stage metrics without incurring the high computational costs associated with existing methods.\n4. The paper acknowledges the practicality of its approach for industry applications. It emphasizes that the offline setting for training the predictor is feasible due to the availability of substantial chip data from design projects.", "weaknesses": "1. Reliance on Offline Data. The paper's approach relies on the availability of substantial offline chip data for training the predictor. While the paper argues that this is practical in the industry, it may limit the applicability of the method in scenarios where such data is scarce or unavailable. Addressing this limitation, either through data augmentation techniques or alternative training strategies, would enhance the paper's broader impact.\n\n2. Black-Box Nature of the Predictor. The predictor used in LaMPlace is a black box, meaning its internal workings and decision-making processes are not transparent. This lack of interpretability may make it difficult to understand why certain placement decisions are made, potentially hindering further improvements or debugging of the method. Specifically, did authors find strange examples, which are difficult for human experts to understand?\n\n3. Limited Discussion of Scalability. The paper does not explicitly discuss the scalability of LaMPlace to very large-scale designs with millions of cells. While the method shows promising results on the tested benchmarks, further analysis of its computational complexity and memory requirements for larger designs would be beneficial.", "quality": null, "clarity": null, "significance": null, "originality": null, "strengths_and_weaknesses": "", "was_revised": false, "final_justification": "", "rebuttal": "", "claims_and_evidence": "", "methods_and_evaluation_criteria": "", "theoretical_claims": "", "experimental_designs_or_analyses": "", "relation_to_broader_scientific_literature": "", "essential_references_not_discussed": "", "other_strengths_and_weaknesses": "", "other_comments_or_suggestions": "", "questions_for_authors": "", "summary_of_paper": "", "summary_of_recommendation": "", "technical_quality": "", "clarity_of_presentation": "", "potential_impact": "", "robotics_focus": "", "quality_of_limitations": "", "questions_for_rebuttal": "", "reasons_to_accept": "", "reasons_to_reject": "", "questions_to_authors": "", "extra_scores": {}}]

Author rebuttal:

Decision: Accept (Oral)