Evolving Graph Structured Programs for Circuit Generation with Large Language Models
Authors: Yinqi Bai
Jie Wang
Lei Chen
Zhihai Wang
Yumeng Li
Mingxuan Yuan
Jianye HAO
Defu Lian
Enhong Chen
Venue: ICLR 2026 Poster (2026)
Keywords: Electronic Design Automation; Logic Synthesis; Large Language Models;
Primary area: applications to computer vision, audio, language, and other modalities
TL;DR: A Graph Structured Program Evolution Framework for Circuit Generation with Large Language Models

Abstract: Logic synthesis (LS), which aims to generate a *compact* logic circuit graph with minimized size while *accurately* satisfying a given functionality, plays an important role in chip design. However, existing LS methods struggle to balance circuit structure compactness and functional accuracy, often leading to suboptimal generation. To address this problem, we propose a novel *Circuit Program Evolution* framework, namely CircuitEvo, which iteratively leverages large language models (LLMs) to evolve circuit programs towards improved compactness while preserving functional accuracy. Specifically, CircuitEvo models the circuit graph as a structured program and leverages the strong generative capabilities of LLMs — guided by domain-specific evolutionary prompt strategies — to generate promising circuit candidates in each iteration. Moreover, a structure-aware circuit optimization module is introduced to correct functional discrepancies by appending necessary substructures to the generated circuits.  To the best of our knowledge, CircuitEvo is *the first* LLM-based LS approach that can iteratively improve a circuit's compactness while ensuring functional accuracy.  Experiments on several widely used benchmarks demonstrate that CircuitEvo can efficiently generate accurate circuits with up to 16 input number and 69 output number. Moreover, our method significantly outperforms state-of-the-art methods in terms of circuit size, achieving an average improvement of 6.74%.

Published as a conference paper at ICLR 2026
EVOLVING GRAPH STRUCTURED PROGRAMS FOR CIR- CUIT GENERATION WITH LARGE LANGUAGE MODELS
Yinqi Bai', Jie Wang'1, Lei Chen', Zhihai Wang', Yumeng Li', Mingxuan Yuan²,
Jianye Hao", Defu Lian', Enhong Chen', I 'MoE Key Laboratory of brain-inspired Intelligent Perception and Cognition,
University of Science and Technology of China
HHuawei Technologies Co., Ltd.
*College of Intelligence and Computing, Tianjin University byg000. 0yg00032440 22224442000 @ma 1. ustc. edu. cn,
ABSTRACT
Logic synthesis (LS), which aims to generate compact logic circuit graph with minimized size while accurately satisfying given functionality, plays an im- portant role in chip design. However, existing LS methods struggle to balance circuit structure compactness and functional accuracy. often leading to subopti- mal generation. To address this problem, we propose novel Circuit Program Evolution framework, namely CircuitEvo, which iteratively leverages the large lan- guage models (LLMs)) to evolve circuit programs towards improved compactness while preserving functional accuracy. Specifically, CircuitEvo models the circuit graph structured program and leverages the strong generative capabilities of LLMs guided by the domain-specnt promising circuit candidates in each iteration. Moreover, structure-aware circuit optimization module is introduced to correct functional discrepancies by appending necessary substructures to the generated circuits. To the best of our knowledge, CircuitEvo is the first L..M-based L. approach that can iteratively improve the circuit's compactness while ensuring functional accuracy. Experiments on several widely used benchmarks demonstrate that our CircuitEvo can efficiently generate accurate circuits with up to 16 input number and 69 output number. Moreover, method significantly outperforms offe--of-theaate art methods in terms of the cir- cuit size, achieving an average improvement of 6.74%. The code is available at hntpp:://iithus com www../o.../MMaa.. USCC/
L
evolutionary prompt strategies to generate
INTRODUCTION
Complex integrated circuits (ICs) can contain billions of transistors, making manual design impractical (Huang et al. (02T). Consequently, the IC industry depends on electronic design automation (EDA) tools (Wang et 2009p. which systematically transform high-level hardware descriptions into layouts ready for IC fabrication. A crucial step in this process is logic synthesis (LS) (Devadas et al.) 1994, Rudell 1989.. which aims to transform behavioral-level description, i.e., truth table, into an optimized gate-level circuit to minimize its delay and area. Since LS is the first step in the EDA process that leads to the final IC layout, the quality of its output has a significant impact on the area, power, and performance of the resulting IC (De Abreu et al. 2021 Berndt et al. (022)).
LS is a challenging Ahr-hard combinatorial optimization problem (Micheli 1994 Farrahi Sar rafzadeh 1994). To address this task, existing LS approaches typically follow generate-then: optimize framework: they first generate a circuit from the truth table, then apply various operators for circuit optimization (Wang al. 2024b; Li et al. 2025 Cheng et al. 2024). Since the quality of the initial generated circuit heavily influences the final result after optimization (Rai et al. 2021 Alanminko 2024), the central problem in LS lies in generating compact circuit graph that exactly satisfies the functionality constraints defined by the truth table. Both commercial and academic LS tools use sophisticated human-designed heuristics (Nabulsi al. 2017
Lai al. 1993) solve
1 Corresponding author. Email: jiewangx @ustc.cdu.cn

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this task, often resulting in suboptimal solutions. Recently, thaming-bbseed approaches (Wang et al. 2024b A'scoli et al. [023] Rai et al.] [021] et al. 2025) have emerged as a promising alternative for circuit generation. These methods aim to explore the circuit design space to identify graph structures that meet strict function constraints. However, they struggle to balance circuit structure compactness and functional accuracy, often resulting in limited circuit quality.
To address this challenge, we propose a novel Circuit Program Evolution framework, namely CircuitEvo, which iteratively leverages large language models (LLMs) to evolve eircuit programs toward improved compactness while preserving functional accuracy. Specifically, CircuitEvo first introduces an innovative graph-structured circuit program formulation (see Figure I to model the circuit graph as an LLM-friendly textual format. The key advantage of the circuit program over traditional sequence-
textual representation (d' Ascoli et al., 2023; Li et al.) (025) lies in its graph-structured design, which effectively encodes hierarchical structural information to facilitate LLM's graph comprehension and generation. To effectively explore the complex program space for accurate and compact circuits, CircuitEvo integrates an evolutionary program generator and structure-aware function optimizer into an iterative framework. In each iteration, CircuitEvo utilizes an LLM-based generator generate diverse and promising circuit programs. The key innovation of this generator is a domain-specific evolutionary prompting strategy that combines domain know ledge with the explorative power of evolutionary methods to enhance the LLM's generative capabilities.
However, due to the stochastic nature of evolutionary generation and the inherent limitations of L.MMs in exactly understanding graph functionality (Dai et al. (024)) the generated circuits cannot always guarantee functional correctness. To address this problem, we introduce a structure-aware functioon optimizer. Specifically, the optimizer utilizes existing LS tools to efficiently generate two essential substructures, which are then appended to the incomplete circuit to correct functional discrepancies based on the circuit functionality completion theory. Moreover, to ensure the compactness of the optimized circuits, we introduce a local program search method to identify key structures of the generated circuits before functional optimization. By integrating the structure generator with the function optimizer, CircuitEvo effectively explores the space of circuit programs, enabling the generation of both functionally accurate and compact circuits.
We evaluate CircuitEvo using two open-source models Dessss---eeeee-... and Sween.55-B-IInstrue and a proprietary model-GPP GPT-3.5-turbe as the backbone large language model. Experiments on several widely used benchmarks demonstrate that CircuitEvo can efficiently generate accurate circuits with up to 16 input number and 69 output number, and significantly achieves an average improvement of 6. 7.7%% in terms of the circuit size over state-of-the-art methods. Additionally, through thorough analysis of CircuitEvo, we observed two key factors contributing to circuit compactness, which can offer valuable insights for the development of future circuit generation approaches.
We summarize our contributions as follows. (1) To the best of our knowledge, CircuitEvo is the first LS method that integrates LLM into an evolutionary framework iteratively improve the circuit's compactness while ensuring functional accuracy. (2) We propose novel graph-structure circuit program formulation that enables large language models to effectively understand and evolve circuit graphs. (3) Experiments on several widely used benchmarks demonstrate that CircuitEvo can efficiently generate accurate circuits and significantly outperforms the state-of-the-art methods in terms of the circuit size. (4) The thorough analysis of our CircuitEvo provides valuable insights into the key factors that contribute to achieving compact circuits.
2 BACKGROUND
Logic Synthesis (LS) from 10 examples Logic synthesis aims to convert a behavioral level descrip- tion, i.e., truth table, into an optimized gate-level circuit as shown in Figure 5 in Appendix B A truth table a tabular data in which each row corresponds to an input-output pair (x;: y:). Given a truth table T with n inputs and m outputs, the set of input-output pairs D = (X, Y)
{(x, ) defines a Boolean function f B" - BmT where BB = {0, 1]. Thus, the goal of LS is to find a circuit with minimized size while accurately satisfying the given Boolean function f. However, directly generating the optimal circuit is challenging due to its Ahrd nature (Farrahi & Sarrafzadeh 1994). Consequently, LS is divided into two stages Circuit Generation and Circuit Optimization. The Circuit Generation stage focuses the given truth table. Since the quality of the initial circuit has a significant impact on the quality of the optimized circuits, this stage aims generate circuits that are both functionally correct and
generating an initial circuit that accurately implements
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structurally compact. Following this, the Circuit Optimization stage applies subsequent optimization operators (Mishchenko et al. 2011 Brayton 2006 to further improve circuit quality.
RELATED WORK
Machine Learning for Logic Synthesis (LS) Traditional LS methods synthesize a circuit from given truth table via manually designed heuristics, such as sum-of-product (SOP) (Nabulsi et al.
2017) and binary decision diagrams (BDD) (Lai al.) 1993). Recently, many researchers have
investigated machine learning for LS RRai et al. 2021 Belcak & Wattenhofer) 2022a Schmitt et al.
202T 2023
Wang et al. 2024a Bai et al. 2025b 2026), which offers promising approaches to
generating compact circuits with smaller sizes. Existing learning-base based approaches can be broadly classified into two categories based on their underlying circuit representations, (1) In the early stages of the International Workshop on Logic & Synthesis (IWLS) competition (Rai et al.] 2021), researchers represent the circuit as sequence-basee based or tree-based Boolean expressions and formulate LS as a symbolic regression problem, i.e., learning accurate and compact Boolean functions given the input-output pairs. Within this formulation, a variety of symbolic regression techniques (Rai et al. 2021: d Ascoli et al. 2023) have been explored for Boolean function discovery. (2) In recent IWLS competitions (Alanminko 2024). researchers represent the circuit as a logic gate network, such as Inverer Graphs (AIGs), and have proposed using deep machine learning methods (Wang et al.,
2024b
Li et al. 2025) to generate circuits.
Large Language Models for Algorithm Design In recent years, the capabilities of large language
models (LLMs) have advanced substantially (Liang et al. 2025 2026 Ni et al. 2026 ?). A growing
body of research has explored the use of LLMs as automated algorithm designers, capable of generating novel algorithms through in-context learning. Given that circuit generation can be framed as algorithm design task, where each circuit represents a functionally constrained graph-based algorithm, we propose to leverage LLMs for the discovery of circuit algorithms. Recent studies have adopted a program-centre approach, representing algorithms as programs and employing LLMs to iteratively optimize them Chomera-Paredee et al., 2024 Liu et al. 2024b). This iterative program generation and refinement process presents a promising direction for discovering new and effective algorithms.
4 THE CIRCUITEVO FRAMEWORK
In this section, we provide a comprehensive description of the proposed Circuit Program Evolution framework (CircuitEvo), as illustrated in Figure 2 The structure of the section is as follows: in Section 4.1]] we introduce the novel graph-structured circuit program representation and problem formulation. Then, we introduce the two main components of CircuitEvo: Evolutionary Program Generation in Section 4.2 and Structure-aware Function Optimization in Section
4.1 THE CIRCUIT PROGRAM REPRESENTATION AND PROBLEM FORMULATION
Graph Structured Circuit Program Existing
Input= X2 X2
works usually employ expression trees (d Ascoli
3
Output =Y, Y2
jt al. 2023 Bai et al. 2025a (uun et al.; 2022)
nodel =x, X2
and And-Inverter Inverter Graphs (Li et al. 2025 Wang
2
node2 = X, X
et al. 2024b) to model the circuit. However, these non-textual representations present signif- icant challenges for LLM- understanding and generation. To address this problem, we propose an innovative strph-structure circuit program, which encodes both the circuit's topo- logical structure and functional information into a textual representation as shown in Figure [ Specifically, the program consists of three parts:
Inverter
node3 -model* -node2
node4 = -model node2
nodeš -mode3 model
-node5
X
Yz
node4
3
And Inverter Graph (AIG)
Graph Structured Program
Figure 1: An Illustration of our novel graph- structured circuit program formulation.
1. 10 Definition: Specify the name and number of input and output variables for the eircuit.
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2. Structure Description: The topological structure of circuit is inherently defined by its nodes and the directed edges that connect them. In our program representation, we employ hierarchical, bottom-up modeling approach, where each line specifies a circuit node along with its input dependencies. This formulation explicitly encodes the connectivity among nodes in textual format, facilitating LLM'' comprehension of the eircuit's structure.
3. Function Definition: Since our program explicitly defines the connectivity between nodes, the Boolean function of each node can be systematically constructed. Therefore, we define the functionality of our circuit program as the Boolean functions of the primary output nodes, which are required to satisfy the specified truth table.
Overall, our graph-structured circuit program formulation bridges the gap between circuit graph representations and language-based reasoning, thereby unlocking the significant potential of LLMs for addressing LS tasks through their powerful generative capabilities.
Problem Formulation Building on the circuit program representation, the LS problem is defined as: Given truth table T, CircuitEvo aims generate a circuit program P that exactly satisfies the given functionality while minimizing the number of structure lines (circuit nodes). To achieve this goal, CircuitEvo incorporates an evolutionary program generator and structure-aware function optimizer into an iterative framework. Specifically, it maintains a population of functionally correct programs, denoted by P .P...... PN }. In each iteration, the structure generator generates diverse set of candidate programs, which are subsequently optimized to ensure functional correctness. The top-performing optimized programs are then added to the population for the next iteration. The overall procedure of Cir is outlined in Algorithm|] [ and the core components of the circuit generator and optimizer are discussed in detail in the following sections.
4.2 EVOLUTIONARY PROGRAM GENERATION
Recently, the generative capabilities of large language models (LLMs) have ad- vanced significantly, enabling their appli- cation in various complex tasks. There- fore, CircuitEvo utilizes LLMs as the pro- gram generator explore the space of cir- cuit programs. However, we observe that standalone LLMs with zero-shot prompt- ing often struggle to generate high-quality programs. To address this challenge, Cir- cuitEvo integrates LLMs within an evo- lutionary framework, leveraging domain- specific evolutionary prompting strategies and high-quality circuit examples to effec- tively guide the exploration of LLMs. The evolutionary generation process is as fol- lows:
Algorithm 1: Pseudo Code for CircuitEvo
Input :LLM me, Truth table T, Population size
N, I iterations, M strategies
Output :A compact and accurate eircuit program P < InitPop((N) for
to I do for m <- to M do for j 6 1 to N do
parents + Sample(P)
Pg < LLMGGnnrrator(pareetss m)
P < LocalSearch (P3)
Popt & FunctionOptimiizer(( (Pk, T)
Sopt Fitness (Popt)
P -- PU ((P Sopt))
end
end
P - GetBest N)
Initialization To guide the LLM in effec- tively exploring the circuit search space, we first construct an initial population of circuit programs that are diverse and ac- curate. To this end, CircuitEvo adopts a circuit decomposition strategy inspired by the Shannon decomposition theorem (Gdanskiy et al., 2020)). Specifically, given the original truth table T with n input variables, we select decomposition variable X; and partition T into two sub-tables, Ti and Tz. corresponding to X, = and X; = 0, respectively:
end return GetBest 1)
T(X,, X2, ......, X,) = X, Ti(X, = 1) X T2(X; = 0).
(1)
We then use heuristic methods in existing LS tools to synthesize two sub- programs P. and P2 from Ti and Tz, and combine them into functionally correct program P based on Equation [] By varying the choice of decomposition variable X,, this approach yields a diverse set of accurate mitial solutions.
More implementation details of our initialization process provided in Appendix E.1
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Evolutionary Program G eneration
Population M anaggement
Demain-specific Prompts
Evolutionary Generation
Problem Specification:
Crossover er-based Exploration a
Compact Exact
Sample Sampled Programs:
P
#P-
PI. P2.
P2 Mutation-a basedd Refinement
CrOSSOVGE
Evolutionary Strategies:
Exploration, Reflnement
+/
Function Constraints:
mntaiion
InvOul
Stracture
Function
V f(X
Optimized
Generated Programs
Programs
Structure-awars Function Optimization
Function Completion
Local Program Search
PPR
#
Size:
P
Program Fusion
Ciruil Function Completion Theory
Aor: Size:
appt.
Acr: Size:
Eusion
Ar:: Size:
Size: 3
Aoc:
Figure 2: Overview of the CircuitEvo framework. The CircuitEvo comprises evolutionary program generator and a structure-awant function optimizer for function completion.
Generation of Programs At each generation step, we sample batch of N programs (P.) from the LLM Ty based on carefully designed prompt Tú i.e., Pt ~ (T;).. To fully leverage the LLM's generative capabilities for creative circuit programs generation, we construct the domain-specific evolutionary prompt as follows (see Figure TT:: Problem Specification A detailed description of the circuit generation problem, including the program format and compactness objective. Few-shot Learning To stimulate the generative potential of LLMs, we adopt a few-shot learning strategy by sampling several representative circuit programs from the current population in-context examples. To balance quality and diversity, programs are sampled with probability prob(P.) = rank( P,)+ 1+)+++++++ I+ where rank(P.) indicates the fitness-based rank of P. within the population. These examples offer structural and functional priors that guide the LLM toward generating comprehensive and diverse candidate programs. Evolutionary Prompt Strategies To effectively leverage the sampled programs, we design four evolutionary prompt strategies to guide the LLM's generation process. These strategies grouped into two categories: Exploration (E1, E2) and Refinement (R1, R2). The exploration strategies aim to broaden the structural search space by performing crossover-inspired transformations between pairs of parent programs. contrast, the refinement strategies focus improving individual programs by altering Boolean operators and variable configurations. Domain-Specific Function Constraints Since the cireuit search space grows exponentially with the number of inputs, it is challenging to generate accurate circuit programs. To mitigate this, we incorporate domain- knowledge to improve generation accuracy. Specifically, we observe that the outputs of multi- output circuits often exhibit simple yet meaningful logical relationships, typically expressed as Ym = (Y......... Y mI).. For instance, a two-output circuit, the outputs Y and Y₂ may satisfy relation such Y2 -Y,, where denotes the logical NOT operator. By pre-identifying inter-output dependencies and embedding them as function constraints in the prompt, the generator significantly reduces the search space. Detailed prompts provided in Appendix E.I
Fitness and Population Management In each generation, we apply all four prompt strategics N times, resulting in a total of 4N newly generated circuit programs. These candidates then optimized (see Section 4.3), and the feasible ones are incorporated into the current population. From according their fitness scores-are selected to form the population for the next generation. Since all circuit programs in the population are functionally correct, we adopt circuit compactness (i.e., size) as the fitness metric.
this updated population, the top N individuals-
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4.3 STRUCTURE-AWAEE FUNCTION OPTIMIZATION
Although CircuitEvo can continuously generate new circuit programs, the stochastic nature of evolutionary generation and the limited graph-level reasoning capabilities of large language models (LLMs) make it difficult to ensure their functional correctness. To address this problem, we present the following remark, which provides a theoretical foundation for augmenting generated programs with auxiliary substructures to ensure functional accuracy:
Remark (Circuit Functionality Completion). Let F= [F denote the set of target Boolean functions defined by a truth table T with m oulput bits. Let F. (Fg represent the functionality
of the generated circuit programs Pg. Then, for each i {1, (1,...., m), there exist Boolean functions Fg. and F such that:
+F
9a where and denote the logical OR and AND operations, respectively.
The detailed proofs are in Appendix A Based on Remark 1 we can easily get and translate the auxiliary Boolean functions g. = (F
9a im and Fa = { 2s im into their corresponding truth tables Ta and To- Subsequently, traditional heuristics
applied to generate accurate circuit programs Pa and P. from these truth tables. These programs are then integrated into the initially generated program Pg to complete its functionality. The program fusion process involves both structural and functional aspects. Structurally, the programs are merged with common subgraphs eliminated through structural hashing. Functionally, the completed circuit's functionality is defined by Equation 2
Local Program Search Although the completion process guarantees functional correctness, it may introduce redundant logic that compromises circuit compactness. To mitigate this, we propose local program searcher that identifies a key substructure P& within the initial program Pg to guide the completion process. This approach is motivated by the observation that initial programs with higher functional accuracy and smaller sizes tend to yield more compact results after function complction, as illustrated in Figure / Specifically, given eircuit program comprising Rp nodes, the Local Program Searcher generates "p candidate subprograms, where the i-th candidate consists of the first nodes of the original program. Each candidate represents local subgraph that structurally more compact than the full program. To identify the most promising candidate, a greedy selection strategy is applied to choose the subprogram with the highest accuracy. This localized refinement effectively eliminates redundant components, yielding more compact and functionally accurate initial program for the function optimization. Finally, after identifying the key substructure Pk. traditional heuristics are employed to generate the corresponding circuit programs 'Px and Pa,, for the final functionally optimized program Popt- Due to limited space, we provide more implementation details about the program search and function completion process in Appendix
E.2 E.2
EXPERIMENTS
In this section, we conduct extensive experiments to evaluate CircuitEvo, which have four main parts: Experiment 1. To demonstrate the superior performance of our CircuitEvo in generating accurate and compact circuits, Experiment 2. To demonstrate that our method explores the circuit design space more efficiently than other learning- based approaches. Experiment 3. Perform carefully designed ablation studies to provide further insights into CircuitEvo. Experiment 4. Perform visualization and analysis of the inherent compact structures discovered by our method compared to the baselines.
Benchmarks We evaluate our method on four widely used benchmarks: Arithmetic (Alanminko) 2024), Random (Alanminko 2024). LogicNets (He al., 2021), and Espresso (Boucher & King 2010 Specifically, we select 16 diverse benchmark circuits for evaluation, including very challenging cases with up to 16 inputs and 69 outputs, which corresponds to a search space of 269x2 possible solutions. Moreover, the size of the selected circuits, depending on the number of nodes synthesized by the traditional heuristic method SOP, ranges widely from 39 to 3302. Due to limited space, please refer to Appendix C.I for more details about the benchmarks.
Experimental Setup Throughout all experiments, we use two open-source moddlls-Deepseek. V3 (Liu et al.) 2024a) and Qwen2.5-7BB 7 and a proprietary model-GPPM GPT-3.5-turbo as the backbone large language models. Although more powerful proprietary models such GPT-4o could be used as the base model, we adopt GPT-3.5-turbe to balance generation performance with resource efficiency (see Table in the Appendix). Moreover, we employ ABC (Brayton al. 2010) as the

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backend LS tool. ABC is state-of off-the-art art open-source LS tool and is widely used in research of
machine learning for LS (Pasandi et al. [2023 Wang et al. 2024b). All experiments are conducted on
single machine that contains 32 Intel Xeonk E5-2667 v4 CPUs and 8 NVIDIA GeForce RTX 3090
GPUs. Additional implementation details can be found in Appendix C
Table 1: The results demonstrate that CircuitEvo can generate accurate circuits for all benchmarks
Benchmurk
Boolformer
SPL
DSR
ICSR
DNAS
CircuitEvo (Ours)
Circuit
Acc(S))
Acc(16) 1
Acc(S)) 1
Acc(9))
Acc(S) f
Qwen2.5-7B
Deepseek-V V3
GPT-3,5-turb
Arithmetic
89.2
92.0
89.1
73.9
100.0
100.0
100.0
100.0
LogicNets
97.9
97.9
96.8
88.1
99.9
100.0
100.0
100.0
Espresso
92.7
90.3
87.4
87.2
99.9
100.0
100.0
100.0
Random
87.7
89.0
87.4
83.7
100.0
100.0
100.0
100.0
Average 91.1
91.5
89.5
83.5
99.9
100.0
100.0
100.0
Table 2: The results demonstrate that CircuitEvo significantly outperforms all competitive baselines in terms of the initial size, with an average improvement of 6.74% over state-of- ofate-of-the-arr methods.
Bootformer
Cirrsitaan
Cirest
F1
P0
Init Nosk
Isit Ntde
Inst Ntode
Tsst. Nodi
Lest Nock:
Iasi Nesk:
Issl Node
QQen225-BB
Despockk-V3
CDPT-3.5-uroo
Impe//00
Arthaeticl
10
185
163
47
222
17
77
81
71
74
3,90
Mithneik3
1590
1250
LogkNess
159
339
183
149
139
Logkhes2
13
95
09
95
127
102
11.5
134
74
74
74
22.11
L
15
273
268
199
324
214
242
334
212
211
211
.6.8
Peprosost
140
77
83
71
71
7.79
Popeoest
3968
357L
3220
3154
Pyprosst
2008
2186
3122
920
944
1157
365
645
6.92
Randon
47
52
64
42
42
41
42
41
0.00
Rundont
51
44
30
37
44
36
36
2.70
Bondoms
10
94
63
60
20,00
Randend
155
190
105
105
Rundoms
15
1987
1806
1622
15.0
1529
1514
1236
1163
1098
11:0
12.58
Avernge
660.58
700.63
634.81
736.75
539.38
545.81
532.88
479.80
471.13
471.44
6.74
Evaluation Metries In our experiments, we use the pre-mapping performance (accuracy and size)
and post-mapping performance (area and delay) as the evaluation metries to assess the accuracy and compactness of the generated circuits, respectively. (1) Accuracy is defined as the proportion of correctly predicted output bits the total number of output bits. Specifically, it is computed as 2m EE Ej=1 [0t = Vr.l]. where n is the input number, m is the output number, Di.j is the predicted output bit, Vt., is the ground truth, and 1[:] denotes the indicator function. An accuracy of 100% indicates that the generated eircuit fully satisfies the truth table; otherwise, the circuit does not match the truth table exactly. (2) Size is defined as the node numbers of the generated circuits. During the L.S stage, reducing circuit size significantly improves the final design's PPA (Power, Performance, and Area) (Rai et al.) 202T: Alanminko 2024 Li et al. 2025). Therefore, we use the circuit size to evaluate the quality of the generated circuits. (3) Area is defined as the total physical silicon area occupied by the mapped circuit, typically measured in square micrometers, which reflects the hardware resource consumption. Delay is defined as the longest signal propagation time from any primary input to any primary output in the mapped circuit, which reflects the circuit's maximum operating speed. Smaller area and shorter delay generally indicate better hardware efficiency, so these metrics are used assess the practical performance of the generated circuits on target technology.
Baselines Our baselines fall into two categories: traditional methods and learning- based methods. For traditional methods, we employ two widely used heuristics: SOP (Nabulsi et 2017) and BDD (La et al. 1993). For learning-based methods, we utilize the state-of-the-art (SOTA) machine learning technique DNAS (Wang et al. 2024b) Chu et al.). Moreover, we employ four Boolean function learning methods, including a pre-trained method, two search-based techniques, and an -ased method. Specifically: (1) Boolformer (d' Ascoli al.) (023) is a pre-trained model designed for Boolean function learning in circuit generation; (2) SPL (Sun et al. 2022) is a SOTA
Monte Carlo Tree dearch-based function learning method; (3) DSR (Petersen et al. 2019) is a
search-based function learning method with reinforcement learning: (4) ICSR (Merler et al. (024) is an LLM-based function learning approach. More details about the basclines are presented in Appendix D
Experiment 1. Generation performance analysis In this subsection, we compare CircuitEvo with seven competitive baselines in terms of pre-mapping metrics (accuracy and size), and post-mapping metrics (area and delay). The evaluation is conducted on four widely used circuit benchmarks. Results in Table I show that our CircuitEvo outperforms all learning-based methods in terms of
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Table The results demonstrate that CircuitEvo significantly outperforms baselines in terms of the circuit area and delay after technology mapping four benchmarks.
Benchmark
Boolformer
SPI.
DSR
ICSR
SOP
BDD
DNAS
CireuitEvo
Area J
Area
Area 4
Area 4
Area J
Area
Area 4
Area 4
Arithmetic
1232.67
1037.67
878.67
1131.67
915.33
940.00
928.00
789.67
Espresso
2266.00
2410.00
2553.50
2504.50
1894.25
1912.75
2035.50
1818.25
LogicNets
323.00
303.67
259.67
364.33
274.00
287.33
403.67
251.33
Random
749.67
717.67
642.50
623.17
590.17
572.33
511.67
431.33
Delay +
Delay 4
Delay 4
Delay 4
Delay
Delay 4
Delay +
Delay +
Arithmetic
17.73
16.57
15.23
15.30
15.60
15.90
14.07
13.67
Espresso
14.55
15.18
15.98
16.25
15.45
15.48
14.58
14.15
LogicNets
12.27
12.70
12.43
12.43
12.30
12.37
13.10
12.23
Random 13.22
13.27
12.63
12.62
13.17
12.93
11.67
10.80
Table 4: The ablation results show that each component plays an important role our CireuitEvo.
Renchmark
CimmitFees
Program
Fxolution
Ch-Cooplizion
Inii Nodz
Acc
Node
Inil
Acc/933
Node
Acc130
Node
Edit Node
Arthmeticl
100,0
74
100.0
75.
100,0
100.0
75
100,0
79
100.0
74
Ariimeticc
100.0
1206
163.0
1229
100.0
1220
101L0
1233
136.0
1178
67.3
27
Espresso3
100.0
3184
100.0
3220
100.0
3377
101LE
3184
130.0
3337
$2.6
200
Espresso4
100.0
545
10000
940
100.0
940
100.0
911
190.0
911
36.4
LogicNets]
100,0
139
10000
140
100.0
145
100.0
150
150.0
140
70.1
LogeNeetz2
100,0
74
100.0
90
100.0
74
100.0
75
100.0
75
60.6
Randoms
100,0
138
100.0
147
100.0
146
100.0
151
100.0
146
86.5
20
RandemS
100.0
105
10000
110
100.0
106
100.0
106
100.0
105
833
49
accuracy. Specifically, CircuitEvo achieves an average improvement of 16.5% compared to the LLM- based baseline, ICSR. Additionally, all circuits generated by CircuitEvo achieve 100% accuracy, demonstrating the effectiveness of our structure-awar function optimizer. To fairly compare circuit sizes, first apply the rule-based legalization method from (Wang et al.] (024b) ensure that circuits generated by baseline methods are functionally correct, i.e., 100% accuracy. Building upon that, the results in Table[]show that our CircuitEvo significantly outperforms all baselines in terms of the generated circuit size. Specifically, CircuitEvo achieves an average reduction of 6.74% in size compared the SOTA baselines. Furthermore, demonstrate that the circuits produced by our method provide better initial solutions for optimization, we apply three optimization heuristics resyn2, de2, and compress2 achieves average reduction of 1 1.09% in the optimized circuit size compared to the SOTA baselines under the resyn2, indicating the superiority of our method.
the generated circuits. Results in Table show that our method
Moreover, to assess the practical efficiency of the generated circuits after technology mapping, we evaluate their post-mapping performance in terms of area and delay. Specifically, we use ABC's map operator to map each circuit onto mene. genginnlli ii, widely used standard cell library with 23 different gates in logic synthesis, and measure the resulting area and delay. As shown in Table 3 CircuitEvo consistently achieves smaller area and shorter delay than all baselines across the four benchmarks, indicating that our method not only generates functionally correct and compact circuits but also produces designs that translate into more efficient hardware implementations. Overall, these comparative results demonstrate that CircuitEvo surpasses existing methods in generating accurate and compact circuits. More comparative results are provided Appendix F.1
Experiment 2. Efficiency analysis In this sub- section, we compare the search efficiency of our method with three competitive search- search-based base- lines across circuits from four benchmarks. For fair comparison, we adopt convergence time as the metrie for evaluating efficiency. The results Table 5 demonsttat that CircuitEvo consistently outperforms all baselines in terms of search effi- ciency, demonstrating its ability to effectively igate the search space by leveraging the powerful search capability of LLMs. Overall, the results demonstrate the superior efficacy of our CircuitEvo.
Table 5: The efficiency comparative results.
Benchmark
CircuitEvo
DSR
SPL
DNAS
Circuit
Timeth)
Timeth) 4 Timeth)
Timoch)
Arithmeticl
1.21
2.02
3,88
7.69
LogicNets
1.34
3.73
3.99
32.16
Espressol
2.04
4.01
3,54
18.03
Randoms
1.32
2.38
4.25
9.75
Average
1.48
3.91
3,03
16.91
Experiment Ablation Study In this subsection, we conduct an ablation study on eight circuits us- ing GPT-3.55ttubo the LLM backbone understand the individual contribution of each component
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of our CircuitEvo (see T)) The 'w/o LLM' variant, which removes the use of LLM and instead employs a rule- based genetic algorithm gegorrthmm-linarr genetic program (Oltean & Grosan 2003) to evolve the cireuits, led to considerable size expansion. This highlights the importance of incorporating the strong generation ability and prior knowledge of L.LM our CircuitEvo. The 'w/o Program' variant, which formulates the circuit substantial increase in size. This highlights that our proposed graph-structured program captures more structural and functional information than other textual representations. The 'w/o Evolution' variant, which doesn't 't use the exploration and refinement evolutionary strategies for circuit generation, also exhibits a negative impact on size. This demonstrates the effectiveness of incorporating LLM in an evolutionary framework. The 'w/o Local' variant, which completes the originally generated circuits without applying local program search, results in a significant increase in size. This demonstrates the necessity of local search in eliminating redundant structures. The 'w/o Completion variant, which removes the function completion approach and directly uses the size the LLM's generated circuits as the fitness metric, results in a substantial drop in accuracy. This underscores the critical role of our proposed function optimizer in ensuring the functional correctness of the final generated circuits.
Boolean function rather than circuit program, led to
Experiment 4. Visualization of compact structures In this subsection, aim to provide insights into the compact structural patterns captured by our method. By visualizing the generated circuit structures, we observe that the compactness achieved by our approach primarily manifests in two aspects: increased logic sharing and the emergence of triangular circuit structures. Due to limited space, we provide more visualization results in Appendix F3
Logic sharing is defined as the logic nodes or sub- expressions that are shared by multiple logical com- ponents. For example, X2 is a logic sharing that appears twice in the expression X2-33 * (X2X3 + X4) and can be shared as a node in the final circuit. By analyzing the generated circuits, we found that creased logic sharing always leads to reduced circuit size. Specifically, the results in Figure 3 show that method, which generates more compact circuits, achieves a significantly larger number of logic shar- ing than all Boolean function learning baselines on four benchmarks. This observation underscores the importance of logic sharing in reducing circuit size and suggests that future methods should explicitly promote exploitation in circuit generation.
Insight for Logic Sharing
Normalized Sharing Number
ICSI
0.3
0.2
0.1
0.0
Espresso
Random
LogieNets
Artthmetic
Benchmarks
Figure 3: Logic Sharing significantly matters with the circuit compactness.
Triangle structure refers to a circuit where the num- ber of lower-level nodes consistently exceeds that of higher-level nodes. The current logic network learn- ing methods necessitate the definition of an initial circuit structure to guide the search (Belcak & Wat- tenhofer 2022b Wang et al. 2024b). Nevertheless, a principled methodology for designing these initial structures remains lacking. Through the analysis of generated circuits, we have observed that com- pact circuits consistently exhibit a triangle structure. Specifically, Figure 4sowss shows that the number of nodes decreases as the circuit level increases on five bench- mark circuits, confirming the presence of a triangular structure. Therefore. it is suggested that triangular networks should be prioritized in the initial network design, which can lead to better circuit generation.
Insight for Triangle strucutre
Espresso1
Normallzed Node Number
Arthhmetict
0.8
Logichets!
Logictetsk
Randomd
0.6
0.4
0.2
0.0
11
14
Lev Number
Figure 4: Triangle Structures play a signifi- cant role in circuit compactness.
6 CONCLUSION
Logic synthesis aims to generate compact and accurate logic circuit. which plays an important role in chip design. However, existing LS methods struggle to balance circuit structure compactness and functional accuracy, often leading to suboptimal generation. To address this problem, propose

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novel Circuit Program Evolution framework, namely CireuitEvo. This framework models the circuit graph as a structured program and integrates an LLM- program generator and structure aware function optimizer to explore the circuit program space. An appealing feature of this framework lies in its ability to enable iterative improvement of circuit compactness while preserving functional accuracy. Experiments several benchmarks demonstrate that CircuitEvo efficiently generate accurate circuits and significantly outperforms the state-of-the-ar methods in terms of the circuit size.
ETHICS STATEMENT
This research does not involve any personally identifiable information. All datasets used publicly available and widely adopted in the community, and we have verified that their licenses permit research use. In accordance with the ICLR Code of Ethics (https://icl) wwt.cl...cc.....eeeeeeeeeoo cw/ppc/ppll.cc.cccc ic/ CodeOfRthico cs), we ensure that our work adheres to principles of fairness, transparency, and responsible Al research. We also disclose that LLMs were used for text polishing, while all conceptual contributions and validation remain the responsibility of the authors in Appendix
REPRODUCIBILITY STATEMENT
We will provide open access to all source code, configuration files, and preprocessing scripts, together with detailed instructions to reproduce the main experimental results. All datasets employed publicly available, and we specify the exact versions and preprocessing steps. We report all hyperparameters, model versions, and API parameters in full, and we deseribe the computational environment (hardware type, GPU model, and software dependencies) in the supplemental material. We also include ablation studies and negative results to ensure transparency. Collectively, these resources and specifications enable reliable and faithful reproduction of our results.
ACKNOWLEDGGENNTS
This work was supported in part by National Key R&D Program of China under contract 2022ZD01 19801, National Nature Science Foundations of China grants U23A20388 and 62021001. This work was supported in part by Huawei as well. We would like to thank all the anonymous reviewers for their insightful comments.
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A PROOF OF CIRCUIT FUNCTIONALITY COMPLETION (REMARK 1)
Before proceeding with the proof, we briefly recall the key symbols and definitions involved. Through- this section, we use +. and to denote the logical OR, AND, and NOT operations, respectively, m denotes the set of target Boolean functions defined by the truth table 'T with m output F = [FF) Ti
bits. Fg { g represent the functionality of the generated circuit programs Pg. Our goal is to prove that for each i m... there exist Boolean functions F and Fii such that:
9n. gb.
From Boolean algebra, know that Boolean functions have the following properties. Let F, G and H be Boolean functions, we have:
A sssociativity of AND: ==
Associativity of OR:
F GF+
Commutativity of AND: F+
Commutativity of OR:
F+G=G+F
Distributivity of AND over OR: F* (P)
Identity for AND:
F+1=F
Identity for OR:
F+0 #+0=+ =
Annihilator for AND: F=0=0)
Annihilator for OR: F+1=1
Idempotence of AND:
F+F=F
Idempotence of OR: F+F==F
Complementation of AND: F F* (-F)=
Complementation of OR: (- =1
Proof. For each E {l....,,,) m.) we define Fi Da
and Fi as
( and
9s =
(3)
respectively. Thus, according to the distributivity of AND over OR, the expression can rewritten as
(F+F + = (F+ (-F g.
F +
(-F))
(-Fi)) and (Fi * (-F;)) * (-F to Fi (-F Substituting this result back into the original expression, we have
According to the above properties, we can simplify to ())
(F) g
= F
*
gu
F +>F)
FFF
= =F*(FF+(FFF))
=1
=F.
which completes our proof.
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Truth Table
And Inverter Graph (AIG)
Optimized A AIG
Input:
Output
Pls
Eliminated Node
X1
X2
X3
Y
Circuit Generation
Node
Inverter
Circuit Optimization
Inverter
Edge
Edge
POs X1
X1
X3
X1
X3
Figure 5: The illustration of two stages in LS: Circuit Generation and Circuit Optimization.
B MORE DETAILS FOR BACKGROUND AND RELATED WORK
Circuit Graph Representation In the LS stage, circuits are typically represented using And-Inverter Graphs (AIGs) (Berndt et al. 2022). An AIG is directed acyclic graph where each node represents Boolean function and each edge corresponds to a wire connecting these functions. AIGs include four types of nodes: constants, primary inputs (PIs), primary outputs (POs), and two-input AND gates (And2 nodes). The graph edge is either inverted or not, with a complemented edge indicating that the signal is inverted. Given truth table with imputs and outputs, the AIG contains Pls and m POs. The size of a circuit denotes the number And2 nodes the AIG, while the depth/level signifies the longest path from Pl PO.
Symbolic Regression (SR) for Learning Boolean Functions Symbolic Regression (SR) aims to discover a mathematical expression that best fits given dataset D. To achieve this, many existing SR approaches represent mathematical expressions as algebraic expression trees, where internal nodes are operators (e.g., +, x, sin) and terminal nodes are input variables constants. We denote by (T..... Tx the pre-order traversal of such an expression tree. Notably, there exists one-to-one correspondence between an expression tree and pre-order traversal. Each is an operator, input variable, or constant selected from a predefined library of tokens, such as [+, -, X, sin, cos, exp. log, xr). In Logic Synthesis (LS), Boolean functions can be learned from truth tables using SR methods. To adapt existing SR techniques for Boolean function learning, we redefine the operator set as and, or, not, and the token library at each step becomes Once these functions are learned, they can be directly mapped into logic
land, or, not, 21...., r... circuits for further synthesis or optimization.
LLM with Evolutionary methods Evolutionary Computation (EC), inspired by the fundamental mechanisms of natural selection and biological evolution, has emerged as a powerful and flexible optimization paradigm (Katoch al. 2021 Gen & Lin 2023). Recent advancements demonstrate the significant potential of incorporating EC into the prompt engineering of large language models
(LLMs), leading to notable performance improvements across diverse tasks, including code generation, natural language understanding, and the automated design of heuristics (Hemberg et al. [024]] Romera- Paredes al. 2024 Liu al., 2024b; Yao al., 2024 Morris et al. 2024). By synergizing EC with prompt engineering, it becomes possible to effectively navigate and exploit the vast and complex search space inherent to M.-M-driven tasks. This integration not only facilitates more efficient exploration and exploitation strategies but also enhances the model's ability to uncover higher-quality solutions that may be difficult to identify through conventional optimization approaches.
C IMPLEMENTATION DETAILS OF EXPERIMENTAL SETUP
C.1 DETAILS ON THE BENCHMARKS
We provide the detailed information of the circuits used in our paper follows.
Arithmetic I, 2, 3: Arithmetic functions with permuted inputs / dropped outputs.
Espresso 1, 3, 4: Selected Espresso benchmarks with permuted inputs.
LogicNets 1, 2, 3: Three-output neurons from the LogieNets (He et al. 2021 project.
Random 2, 6: Random and modified random functions.
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Random 3, 4: Known random-looking functions.
C.2 HYPERPARAMETERS
In our experiments, we implemented the CircuitEvo framework using GPT-3.5-TURBO and DEEPSEEK- V3 the base LLM generators (πT²), with population size of N 10 and 10 iterations to balance exploration and computational efficiency. The evolutionary process employed M = 4 distinct strategies: two crossover-based exploration methods (E1, E2) for generating novel circuit designs by combining parent solutions, and two mutation-based refinement techniques (RI R2) for fine-tuning individual circuits through local modifications. Moreover, for the learning-based baseline methods, we use the same default hyperparameters as reported in the corresponding paper.
C.3 USE OF LS TOOLS
In our paper. we leverage the Logic Synthesis (LS) tool ABC Brayton al. (2010) in two key aspects. First, we adopt ABC's traditional heuristic methods Loridd--uu--ooe Num-of-Producce (SOP) and Binary Decision Diagrams (BDD) baselines and functional optimizers. These heuristics are applied to the Randoml circuit using the following operator sequences:
SOP: peaad_tuthha -xf Randoml .truth; collapse; sop; strash
BDD: read_Iruth -xf Random I. I.ruth; bdd; strash
Second, during the cireuit optimization stage, employ three widely used ABC opera- tors rors-resyn2, dc2, and compress2-to refine the initial synthesized circuits. The specific optimization sequences are:
resyn2: read Randoml.aig strash; resyn2
dc2: read Randomi. aig; strash; de2;
compress2: read fandoml.aigr strash; compress2;
Here, aig denotes the file format of the generated And-Inverter Graph (AIG) circuits.
D IMPLEMENTATION DETAILS OF THE BASELINES
Below, we provide short descriptions of the five learning-based methods and two manually designed heuristics.
DNAS: DNAS (Wang et al. 2024b) is a differentiable neural architecture search method designed to synthesize circuits from input-output examples. It begins by constructing logic network architecture and then employs gradient descent to train the network. After training, DNAS prunes unnecessary nodes and outputs the remaining structure as the circuit network. However, the search quality heavily depends on the initial network. An inappropriate initial network always hinders the learning- based methods from discovering compact structures. In logic synthesis, traditional neural architecture search methods (Wang et al. [024b] [Pteeseen et al. 2022) often use square structures, which introduce significant structural bias compared to the inherent circuit structure, leading to inefficient search processes.
Boolformer:
Boolformer (d d''Acooli al. 2023) is pioneering method that introduces the Transformer framework to learn compact Boolean functions for logic synthesis. This innovative approach significantly advances the field by combining the strengths of pre- trained model and symbolic reasoning.
DSR: DSR Petersen et al. (2019) is search-based method that combines reinforcement learning with a recurrent neural network to generate highly expressive mathematical ex- pressions. By leveraging the strengths of reinforcement learning, DSR efficiently explores the space of possible expressions, while the recurrent neural network enables the model to capture complex patterns and dependencies within the data.
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SPL: SPL et al. (2022) is state-of-the search-based method that utilizes Monte Carlo Tree Search (MCTS) agent to systematically explore and identify optimal expression trees from measurement data. By leveraging the strategic exploration capabilities of MCTS, SPL. efficienty navigates the vast search space of potential expressions, ensuring a balance between exploration and exploitation.
ICSR Merler et al. 2024) is an LLM--ased symbolic regression method that utilizes large language models search for optimal expressions. A key strength of ICSR lies in its ability to itcratively refine generated expressions using off-the-shelf optimizers. This approach effectively combines the exploratory power of LLMs with the domain-speeific expertise of external tools.
ICSR:
SOP: SOP (Nabulsi al. 2017) a heuristic method integrated into the widely used logic synthesis framework ABC. This method achieves precise logic synthesis by representing truth tables sums of products.
BDD: BDD (Lai et al. 1993) is another heuristic method included in the ABC logic synthesis framework. It achieves precise logic synthesis by applying the Shannon decomposition theorem and representing the truth table as a binary decision diagram (Bryant 1992 1978 Drechsler Becker 2013).
Akers
E IMPLEMENTATION DETAILS OF OUR CIRCUITEVO
E.1 MORE DETAILS OF THE EVOLUTIONARY PROGRAM GENERATION FRAMEWORK
Initialization process In the initialization phase, we adopt a circuit decomposition strategy to generate diverse and accurate initial population. Specifically, the original truth table T decomposed into two sub-truth tables, Ti and T2. according to Equation [ Each sub-truth table is then converted into circuit graph using the traditional heuristic Nabulsi et al. (2017), and subsequently converted into programs Pi and Pz. These two programs are then fused into an accurate program P (see Section E.2 for the fusion method). To ensure diversity in the initial population, we vary the decomposition variable and repeat the process N times, resulting in N candidate programs. Each sample corresponds different decomposition variable, enabling the generation of a diverse set of circuit programs.
The domain-specific evolutionary prompts We present the detailed prompts in Figure 11, Specifi- cally, the prompts are structured into four main components: Problem Specification, which defines the task and objectives; Circuit Program Example, which offers concrete example to guide the generation process; Evolutionary Generation Strategies, which describe the methods for generating and evolving candidate solutions; and Domain Domain-Specifie Function Constraints, which incorporate domain knowledge to effectively reduce the search space.
X X2 X22 Output -Y
model =x, X₃
Input X2 X, X,
Tnguit Xxput=Xx> X; X,
nods2 =X, + Xs
node3 = nodel "mode2
Output -Y;
Output= =Y
X
mode3
Functionality rule: F. = Fg + Fp
nodel Xs X
node2 XX,- x
Sharing part
Strest
nodel N,,
=X, +X,
structure
strashed
Ingut Progrem
node3 nodel -odde2
node3 = reode] reodl2
Input X, Xs
node2 X, x,
nodel =X,
Sharing part
noded nodel node2
Output =Y;
node3 nodel mode?
nodel =X X2
nodes
functon fusion
-ooda noded function fusion
node2 xX X
node3 = nodel * node?
Output Program
Strashed Program
= node3 Input Program
Figure 6: An illustration of the program fusion process. Two input programs are fused to get new program based on a given functionality rule and structure hashed.
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E.2 MORE DETAILS OF THE STRUCTURE- AWARE FUNCTION OPTIMIZATION FRAMEWORK
Program Fusion The circuit program fusion process, as illustrated in Figure 6 can be clearly divided into two complementary dimensions: structural fusion and functional fusion. Structurally, the fusion begins by directly stacking the logic structures from both input programs. At this stage, all nodes from both programs are combined into single unified representation without any simplification. This forms an intermediate circuit that contains potentially duplicated logic patterns across the two input structures. To optimize this intermediate structure, we employ the strash operator from existing LS tools, which performs structural hashing. This operation identifies and merges shared subgraphs logic nodes that compute the same Boolean functions therrbyy removing redundancy and yielding compact and efficient circuit. In the figure, such redundant substructures (e.g., Xi X2. X1 * X3) are merged to form the structure of the final program. Functionally, the fusion proceeds by combining the output functionalities the input programs according predefined rule. In the given example, the functional rule is Fe F. Fb. indicating that the final circuit should output the logical conjunction of the functionalities of two input programs. This combination is implemented by constructing new output expression based on the original outputs (-node3 from Program a and node3 from Program b). The fused functional output is thus defined as Y1 -node3 * node4. In summary, the fusion process simultaneously operates the structural and functional levels: the structure stacked and then optimized through strash, while the function is fused directly based on given rule. This two-step design ensures both correctness and compactness in the resulting program.
Motivations for Local Program Search Although the circuit functionality completion theory ensures the accuracy of the circuit programs, it often leads to increase in circuit size. Therefore, key challenge is to identify an initial circuit program that minimizes this size overhead after function optimization. To address this issue, propose local program search method that explores the neighborhood of the initially generated program to discover candidates with higher accuracy and smaller size. This approach motivated by our empirical observation, illustrated in Figure 7 that initial circuits with higher functional accuracy and more compact structure result in better circuits.
Motivations for Local Program Search
Normallzed Post-completion Size
1.0
Size=1000
1.0
Accuracy=0.99
Size=1500
Accuracy=0.30
Size=2000
Accuracy=0.80
0.6
0.6
In
0.2
0.2
0.0
0.3
0.4
0.5
0.6
0.7
0.0
0.2
0.4
0.5
0.8
1.0
Accuracy
Normalized Size
Figure 7: Motivations for Local Program Search. Experimental results show that, with fixed accuracy, larger pre-completion circuits lead to larger final circuits, while with fixed pre-complction size, higher accuracy results smaller final circuits. These insights motivate us to generate smaller and more accurate pre-completion circuits.
ADDITIONAL RESULTS
F.1 MORE RESULTS FOR COMPARATIVE EVALUATION
In this subsection, we provide more comparative results. Specifically, we evaluate our method on sixteen circuits from four widely used benchmarks. In terms of the accuracy of the generated circuit, Table 7 demonstrates that all circuits generated by CircuitEvo achieve 100% accuracy. In terms of the initial size, Table shows that CircuitEvo significantly outperforms all competitive baselines in terms of the initial size, with an average improvement of 6. 6.74% over state-of-the-art methods. In terms of the optimized size, the results in Table Table and Table 10 demonstrate that
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CircuitEvo achieves average improvement of 11.09%, 9.91%, and 10.79% in optimized circuit size compared to the state-of-the-ar methods when using resyn2, dc2 and compress2 optimization operator, respectively. Overall, the comparative results demonstrate that CircuitEvo can effectively generate more accurate and compact circuits than the baseline methods.
F.2 THE EVOLUTION TRAJECTORY RESULTS OF OUR CIRCUITEVO
In this subsection, present the evolution trajectory results of our method on two circuits. As shown in Figure g CircuitEvo can iteratively improve both the average and best performance of the population over iterations, indicating the effectiveness of our method.
Evolution of Circuit LogicNets2
Evolution of Circuit Random4
population (Average)
population (Average) population (Best)
100
popubation (Best)
Performance (Size)
Performance (Size)
155
90
150
85
145
140
1
6
9
10
4
6
8
10
Number of Iterations
Number of Iterations
Figure 8: From left to right: (a) The evolutionary trajectory of Circuit LogicTNets2, (b) The evolutionary trajectory of Circuit Random4. The blue line indicates the average performance of the population at each iteration, while the red line represents the performance of the best individual.
F.3 MORE VISCALIZATION RESULTS OF OUR CIRCUITEVO
In this subsection, we visualize the generated circuit programs and present additional analysis on two key factors that contribute to circuit compactness: logic sharing and triangular structures.
Logic Sharing As shown in Figure 9 logic sharing defined the logic nodes sub- expressions that are shared by multiple logical components. The detailed results in Table demonstrate that our method, which generates more compact circuits, captures significantly larger number of logic sharing than all func- tion learning baselines. Therefore, we can con- clude that increased logic sharing corresponds to reduced circuit size. To further illustrate this, visualize the Random3 circuit program and graph generated by CircuitEvo in Figure TO The visualization reveals that approximately one-third of the nodes are shared across different parts of the circuit, providing evidence of the compactness enabled by logic sharing.
Node=5
Node=1
X1
X2
X3
X4
X
X2
X3
X
No logical sharing
logical sharing Figure 9; Illustration of logic sharing.
Triangular Structures In this subsection, we provide additional results to support the presence of triangular structures in our generated circuits. Specifically, the detailed results in Table [2 and Table 1 consistently demonstrate this structural pattern across all test circuits. Furthermore, visualization results shown in Figure 10 offer intuitive evidence for the existence of the triangular structure.
G THE USE OF LARGE LANGUAGE MODEL
In accordance with ICLR 2026 policy, disclose the of Large Language Models (LLMs) an assistive tool in the preparation of this manuscript. The primary application of LLMs was to aid in improving the clarity and quality of the writing.
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Published as a conference paper at ICLR 2026
Our process involved using an LLM to perform the following specific tasks:
Grammar Correction:
Identifying and correcting grammatical errors and spelling mistakes.
Clarity and Readability Enhancement: Rephrasing sentences and suggesting alternative phrasings improve the overall readability and flow of the text.
Conciseness: Assisting in shortening sentences and paragraphs to make the writing more direct and concise.
The core scientific contributions, analyses, and claims presented in this paper are the work of the human authors. We have ensured that the use of LLMs in the writing process was conducted responsibly and in line with academic and ethical standards.
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Published as a conference paper at ICLR 2026
INPUT=x 1x,
21, 2x,
Sharing nodes
Triangular structure
OUIPUI 2v_
mele 14 =x x
axk 15, 7x
=>,
11 uode
rdd Ri, <x
mak 19 =x,2"
mdd 3) =*.2"" made R)
ude 2. =*.5" made 1
rode 22 --mvl 20 mode 21
ank N. = =
M
mede 25
-oode 27 mode 2: --nde
made 27. maae 17, made 26
mode 21 = =-nde 17 rando 26
mode 29 =x 1a mach 27;
uxde 30 = uude 28 made 29,
mede 31
maal 15
12
14
=-node
-uod
ande 36 =axle 23
padee 35
modn 37. --nde 23, -odd 31,
mnd 3t = -udh 36,
"adde 37,
33
16
mode 3) = --ode 31 mode 81
male, 40. =adee 31 -aod W
41
-rode 31;
y. ym1=mode
* (2;
x.2--x4
X3
X5
Xg
X1
Y 6
The generaled circuit program
The corresponding circuit graph
Figure 10: Visualization of the generated circuit program and its corresponding AIG graph for the Random3 eircuit. The logic sharing and triangular structure are visualized.
Problem Specification
Evolutionary Strategies
In logic synthesis, a key task is find an And-Inverter Graph (AIG) that satisfies a given functionality while minimizing the number nodes. We use the following program format to represent AIG network. For example.
Exploration
El: Please help me create program that has tolally different program structure from the given ones but can be motivated from them. You generate program structure by mixing parts of the program structures from the given progrums, similar genetic algorithms.
for Bookean (unction poO piO pil pi2, the corresponding program follows:
INORDER pio pil pi2;
crossover operation
OUUTORDER pol:
new n4 -pi0 pil;
Please help me create new program crossover operation that has totally different program structure from the given ones should as complex as possible. Refinement
nnw noow p4_ pi2:
ppo0 - new niew_ns_:
program consists two parts:
II.nppu and Output Declarations: These lines include INORDER and OUTORDER, which specify the input and output variables.
R1: Please assist me in creating new program that different program stracture but be modified version
Program Structure: This section demonstrates how the output is derived step by step using intermediate variables (denoted as new) and input variables (denoted pi). Each intermediate variable corresponds mode in the AIG network.
of the program provided. You can modify the program by
selectively adding removing the NOT operator (-)
before some variables, changing some AND operatees (*) vice
OR in genetic algorithms.
similar the mutation process
AIG network, each node has inputs, and intermedinte variables computed using Boolcan operaions such as AND (*), OR (+), and NOT (!).
Picase identify the program structures and
program constructed derive through sequence of intermediate steps.
output (i.c., functionality)
me in creating new program by mutation operation that
a different structure the program provided using
main stractures.
Domain-speeifle Function Constraints
Sampled Programs
Now we want to discover an network finput number) inputs and [output number) ourputs. There are some prior function construints on the AIG network:
have 4 circuit programs with their codes as follows:
No.1 program: No.2 program: No.3 program: No.4 program:
(constraints)
Generation Instruction
The generated progrum adhere to the specified format mentioned above. It is important note that the number of nodes in AIG network comesponds the lines number the program strncture. Moreower, ensuring the functional equivalence of the progrmm to the provided program crucial. Do give additional explanations.
Figure 11: The prompts of CircutiEov. Specifically, the prompts consist of four main parts: Problem Specification, Circuit Program Examples, Evolutionary strategies (including exploration and refine- ment), and Domain-specific function constraints.
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Table compare the circuit size and inference cost between our GPT-3.5-turbo and GPT-4o based approaches the Random circuit benchmark. The results show that although GPT-3.5-turbo
incurs a slight increase in size compared to GPT-4o, its cost is five times lower.
Benchmark
SOTA Baseline
(GPT-3.5-turbo)
Ours (GPT-3.5-turoo)
(GPT-40)
Ours (GPT-40)
Circuit
Init Node +
Init Node +
Cost (S)
Init Node +
Cost ($) !
Randoml
41
41
0.14
38
0.38
Random2
37
36
0.11
33
0.41
Random3
75
60
0.08
60
0.69
Random4
152
138
0.18
140
0.52
RandomS
117
105
0.21
105
0,86
Random6
1256
1110
0.11
1072
1.63
Averuge
279.67
248.33
0.15
241.33
0.75
Table 7: The results demonstrate that CircuitEvo generate accurate circuits for all of the selected circuits from four widely used benchmarks.
Benchmark
Boollormer
SPL
DSR
ICSR
DNAS
CircuitEvo (Ours)
Circuit
P1
PO
Acc(56) f
Acc(S6)
Acc(56)
Acc(S() f
Acc(%)
Qwen2.5.7R
Deepseek-VV V3
GPT-3.5-turb
Arithmeticl
100.0
100.0
Arithmetic2
16
6
75.3
83.5
77.4
55.7
100.0
100.0
100.0
100.0
Arithmetic
16
97.5
97.6
97.2
77.0
100.0
100.0
100.0
100.0
LogieNetst
13
6
96.5
96.5
94.2
87.4
99.9
100.0
100.0
100.0
LngicNets2
13
99.2
99.2
99.2
85.0
100.0
100.0
100.0
100.0
LogicNets3
15
98.0
98.0
97.1
91.8
100.0
100.0
100.0
100.0
Espressol
11
94,9
94.5
94.0
100.0
100,0
100.0
100.0
Espresso2
11
91.4
84.5
85.4
100.0
100.0
100.0
Espresso3
12
17
$8.4
88.5
88.5
87.9
99.9
100.0
100.0
100.0
Espresso4
Randoml
7
2
87.5
87.5
87.5
82.8
100.0
100.0
100.0
100.0
Randem2
7
87.5
100.0
Random3
10
87.5
90.0
86.5
86.7
100.0
100.0
100.0
100.0
Randem4
10
87.9
100.0
Random5
12
86.2
88.4
86.8
86.3
100.0
100.0
100.0
100.0
Random6
15
88.6
88.1
75.5
100.0
100.0
100.0
100.0
Average
91.1
91.5
89.5
83.5
100.0
100.0
100.0
100.0
Table 8: The optimization results (using resyn2 operator for optimization) show that CircuitEvo achieves average improvement of 11 11.0% in optimized circuit size over state of oftte-of-theaan tet-hhe-rt art baselines.
Renchmark
Boolformer
SPI.
DSR
ICSR
RDD
DNAS
Circuifvve (Ours)
Cheuit
Opt Node.
Opt Node
Opr Node
Opt Node
Ope
Ope
Oge Node
Oye Node
Impe(1))
Arthmetiel
5
150
122
67
117
65
72
65
0,00
Arthmetic2
16
6
243
157
70
230
51
55
105
44
13.73
Arthmetic3
7
1171
1108
1254
1234
116]
973
12.18
LogicNets
LogieNet22
75
75
95
92
36.00
LogicNets3
15
7
196
207
154
190
184
199
227
186
-20.78
Papressol
11
114
95
180
54
54
55
54
0,00
Pspressa2
220
170
121
29.75
Espressaã
Espressoó
69
623
1443
1456
1469
611
619
820
572
6.38
Randoml
2
42
38
39
11
38
39
37
35
5.41
Random2
2
34
34
35
34
39
34
-9.88
Random3
Random4
135
Randoms
218
283
171
168
156
106
105
76
27.62
Randomó
15
1695
1571
1405
1338
1290
1287
897
868
3.23
$32.00
517.38
504.44
$17.50
426.19
427.50
4J6.13
360.81
11.09
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Table 9: The optimization results (using de2 operator for optimization) show that CircuitEvo achieves an average improvement of 9.91% % in optimized circuit size over state-of- fate--ofthhe-rt baselines.
Benchmark
Boolformer
SPL
DSR
ICSR
SOP
BDD
DNAS
Circuitvve (Ours)
Opt Node.
Opt Node
Opt Node
Opt
Ope
Oge
Oge Node
Ope Impe(5)
Arihmeticl
5
137
113
62
112
73
-1.61
Arihmetic2
16
6
242
176
74
204
48
45
101
43
10.42
Arihmetic3
1145
1081
1217
1140
1191
1132
955
11.66
LogicNets
113
160
LogicNets2
62
24.59
Netis
195
199
155
183
178
202
218
176
-13.55
Espressol
11
3
108
86
89
53
53
54
55
.3.77
Esgresso2
201
219
162
138
121
33,06
Espressaã
Espressof
69
1376
1908
1388
377
820
354
3,99
Randoml
2
41
38
41
40
35
38
37
35
0.00
Random?
2
34
33
29
31
35
31
30
32
-10.34
Random3
87
$2.46
Random4
126
Random5
199
271
165
163
145
99
103
67
Random6
15
4
1641
1536
13:18
1289
1238
1256
854
368
-1.64
Average
513.31
503.69
487.75
198.38
111.75
415.38
407.13
352.44
9.91
Table 10: The optimization results (using compress2 operator for optimization) show that CircuitEvo achieves an average improvement of 10.79% in optimized circuit size over state-of of-the-art baselines.
Benchmark
BoolTommer
SPL
DSR
ICSR
BDD
DNAS
CirentEve (Ouns
Cincuit
P1
PO
Opt Node
Opt Node
Opt Node 1
Opt Node
Opt Node
Opt Node
Ogt Node
Oyt Node L Impr.(9)
Arilmneticl
150
120
67
117
65
72
66
-1.54
Arihmetic2
151
105
0,00
Arthmetici
LogicNetst
6
146
113
110
211
120
117
100
103
6.36
LogicNets2
13
6
75
75
75
78
83
94
93
48
36.00
LogicNets.
7
199
206
154
190
197
227
185
-0.13
Espressol
Eaprose22
220
174
131
Pspressa
17
3195
2523
2860
2677
2570
2576
2564
2484
1.55
Espressa4
16
69
631
1432
1444
1468
611
613
816
573
6.22
Randomi
38
39
39
37
35
2.78
Randon3
68
91
61
53.13
Random4
10
133
146
133
141
133
131
138
115
12.21
Randoms
12
215
284
171
165
152
105
104
72
30.77
Random6
1403
894
2.91
Average
501.38
Table 11: The logic sharing results demonstrate that CircuitEvo significantly outperforms all Boolean function learning baselines in terms of the number of shared logic components.
Benchmark
Boolformer
SPL
DSR
ICSR
CircuitEvo (Ours)
Circuit
P[
PO
Sharing
Sharing
Sharing
Sharing
Sharing
Arithmetic
10
5
22
8
39
Arithmetic2
16
6
13
13
13
14
42
Arithmetic3
16
7
52
51
35
LogicNetsl
13
6
126
125
118
92
62
LogicNets2
13
6
2
8
2
6
31
LogicNets3
15
7
89
59
70
57
282
Espressol
11
3
58
79
67
69
109
Espresso2
11
9
4
5
19
40
70
Espresso3
12
17
2221
1556
1663
2384
Espresso4
16
69
265
439
449
423
3998
Random1
7
2
0
0
0
2
Random2
7
2
0
1
Random3
10
3
0
0
20
Random4
10
3
9
14
5
7
9
Random5
12
98
75
59
79
275
Random6
15
4
28
33
23
29
15
Average
185.75
59.44
152.56
157.56
463.44
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Table 12:
The results show that the number of nodes in five circuits decreases as the circuit level increases, illustrating the triangular structure of the circuits generated by our method.
Circuits
Arithmetic
LogicNets
LogicNets3
Espressol
Random4
Lev
Node
Rate
Node
Rate
Node
Rate
Node
Rate
Node
Rate
1
14
0.19
31
0.22
44
0.21
8
0.11
29
0.21
2
13
0.18
25
0.18
41
0.19
10
0.14
30
0.22
3
10
0.14
17
0.12
30
0.14
10
0.14
19
0.14
4
9
0.12
13
0.09
24
0.11
5
0.07
18
0.13
5
0.09
10
0.07
18
0.09
0.06
13
0.09
6
6
0.08
0.06
13
0.06
4
0.06
10
0.07
7
0.05 4
0.05
0.05
10
0.05
4
0.06
5
0.04
8
0.04
9
0.04
4
0.06
4
0.03
9
0.01
0.04
7
0.03
4
0.06
3
0.02
10
0.01
0.03
0.02
4
0.06
3
0.02
11
0.01
0.02
0.02
4
0.06
0.01
12
0.01
0.02
0.01
4
0.06
0.01
13
2
0.03
2
0.01
2
0.01
3
0.04
0.01
14
0.01
0.02
0.00
0.01
0.01
15
0.00
0.01
0.00
I
0.01
0
0.00
16
0.00
0.01
0.00
0.01
0.00
Table 13: This table provides further evidence of the triangular structure in our generated circuits. Specifically, the level rate, defined as half the ratio of the number of nodes at the bottom level to those at the top level, exceeds in all cases, indicating greater concentration of nodes the bottom.
Benchmark
CircuitEvo (Ours)
Benchmark
CircuitEvo (Ours)
Circuit
PO
Lev
Lev rale
Circuit
PI
PO
Lev
Lev rate
Arithmeticl
10
5
14
5.73
Espresso3
12
17
21
9.66
Arithmetic2
16
6
12
4.37
Espresso4
16
69
21
11.75
Arithmetic3
7
24
18.45
Random1
7
2
3.00
LogicNets
13
6
16
5.36
Random2
7
2
9
3,00
LogicNets2
13
6
17
2.57
Random3
10
3
9
5.00
LogicNets3
15
7
15
5.81
Random4
10
3
14
8,86
Espressol
11
3
16
2.23
Random5
12
3
11
5.18
Espresso2
11
9
10
2.28
Random6
15
4
23
15.32
Table 14: The Computation cost per circuit when using the GPT-3.5-turbo API as the backbone.
Benchmark
CircuitEvo (Ours)
Benchmark
CircuitEvo (Ours)
Circuit
PI
PO
Cost (S)
Circuit
Pl
PO
Cost ($)
Arithmetic1
10
5
0.09
Espresso3
12
17
0.45
Arithmetic2
0.16
Espresso4
16
69
0.43
Arithmetic3
16
7
0.27
Randoml
7
2
0.08
LogicNets
13
6
0.12
Random2
7
2
0.11
LogicNets2
0.20
Random3
10
3
0.14
LogicNets3
15
7
0.14
Random4
10
3
0.11
Espressol
11
3
0.11
Random5
12
3
0.18
Espresso2
9
0.12
Randomó
15
4
0.21
24


Reviews:
[{"review_id": "VFiqHzi3bt", "reviewer": "Reviewer_XHWa", "summary": "CircuitEvo proposes an LLM-based framework for logic synthesis that iteratively evolves circuit programs toward improved compactness while preserving functional accuracy. The key innovation is a graph-structured circuit program representation that enables LLMs to understand and generate circuits through evolutionary prompting strategies. A structure-aware function optimizer ensures correctness by appending substructures based on circuit functionality completion theory. Experiments show 6.74% improvement in circuit size over state-of-the-art methods while achieving 100% accuracy across benchmarks with up to 16 inputs and 69 outputs.", "questions": "See Weakness", "limitations": "", "rating": 4, "confidence": 3, "soundness": 2, "presentation": 3, "contribution": 3, "strengths": "1. The graph-structured program formulation (Figure 1) is genuinely clever - it encodes topological structure in a hierarchical, textual format that preserves connectivity information while being LLM-compatible. This bridges the gap between graph-based circuit representations and language-based reasoning.\n2. Comprehensive evaluation across 16 circuits, 7 baselines, 3 different LLM backbones (GPT-3.5, Deepseek-V3, Qwen2.5-7B), and multiple optimization operators demonstrates robustness. The ablation study (Table 4) clearly shows each component contributes.", "weaknesses": "1. The \"structure-aware function optimizer\" uses existing LS tool (ABC) to generate subprograms Pa and Pb when the LLM-generated circuit is incorrect. This raises fundamental questions:\n\nIf ABC can generate correct subprograms, why not use ABC for the entire circuit?\nHow much of the final circuit comes from LLM vs. ABC?\nBaselines don't receive this \"rescue\" mechanism - is the comparison fair?\nTable 4 shows w/o Completion drops accuracy to 67-86%, suggesting LLMs contribute incomplete circuits that ABC must fix\n\n2. Severe scalability limitations with no path forward:\n\nLimited to 16 inputs, 69 outputs.\nShannon decomposition (Equation 1) has exponential complexity O(2^(n-1)).\nAuthors acknowledge \"computational constraints limit... to 12-15 components\" but provide no solution.\nNo analysis of asymptotic complexity or scaling behavior.", "quality": null, "clarity": null, "significance": null, "originality": null, "strengths_and_weaknesses": "", "was_revised": false, "final_justification": "", "rebuttal": "", "claims_and_evidence": "", "methods_and_evaluation_criteria": "", "theoretical_claims": "", "experimental_designs_or_analyses": "", "relation_to_broader_scientific_literature": "", "essential_references_not_discussed": "", "other_strengths_and_weaknesses": "", "other_comments_or_suggestions": "", "questions_for_authors": "", "summary_of_paper": "", "summary_of_recommendation": "", "technical_quality": "", "clarity_of_presentation": "", "potential_impact": "", "robotics_focus": "", "quality_of_limitations": "", "questions_for_rebuttal": "", "reasons_to_accept": "", "reasons_to_reject": "", "questions_to_authors": "", "extra_scores": {}}, {"review_id": "17EPuRKHoY", "reviewer": "Reviewer_LswG", "summary": "The paper proposes a framework for logic synthesis, CircuitEvo, which employs LLMs within an evolutionary loop to improve final circuit compactness while preserving functional accuracy. The framework is carefully designed to account for the specific characteristics of circuit synthesis and introduces several domain-tailored operations, such as population initialization via the Shannon decomposition theorem and domain-specific function constraints. These components appear both reasonable and effective in ensuring a diverse set of accurate initial solutions, or enhancing optimization efficiency under an exponentially large search space. Experiments conducted on multi-benchmarks, in comparison with multiple baselines, demonstrate the effectiveness and efficiency of CircuitEvo. Moreover, the authors report an interesting additional finding: triangular structures play a significant role in circuit compactness.", "questions": "1. It seems hard to believe that the involvement of LLMs results in such a low convergence time of only 1.48 hours. I am curious whether the reported runtime excludes the LLM inference time between inputting prompt and generating output.\n2. Could the authors provide a breakdown of the time consumption for each operation within the evolutionary program generation process in each iteration — for example, the proportions spent on crossover, mutation, and functionality completion?\n3. There are some cases where CircuitEvo underperforms the baselines in terms of circuit compactness. Could the authors provide a clear explanation for these results?\n4. I look forward to the clarifications that address the above weaknesses.", "limitations": "", "rating": 8, "confidence": 2, "soundness": 3, "presentation": 4, "contribution": 3, "strengths": "1. Although integrating LLMs into a circuit-design loop is not entirely novel, the authors propose several domain-specific operations to enhance how inherently uncertain LLMs can correctly and efficiently generate the desired circuit structures in this domain — which is commendable.\n2. The paper is clearly written, with well-designed figures that aid understanding.\n3, I think the authors have conducted comprehensive experiments (although I am not very familiar with experimental design in this field). The benchmarks and baselines appear sufficiently chosen, and the experimental results look impressive.", "weaknesses": "1. The experimental results are based on single-run evaluation. This limits the statistical significance of the findings, especially considering that LLMs can be highly sensitive to random factors such as initialization and prompt variations, whose influences on the experiments are not  discussed in the paper.\n\n2.Several highly relevant off-the-shelf baselines were not included in the experimental comparison, such as DARTS- [1] and T-Net [2].\n\n[1] Xiangxiang Chu, Xiaoxing Wang, Bo Zhang, Shun Lu, Xiaolin Wei, and Junchi Yan. Darts-: robustly stepping out of performance collapse without indicators. arXiv preprint arXiv:2009.01027, 2020.\n\n[2]  Zhihai Wang, Jie Wang, Qingyue Yang, Yinqi Bai, Xing Li, Lei Chen, Jianye HAO, Mingxuan Yuan, Bin Li, Yongdong Zhang, and Feng Wu. Towards next-generation logic synthesis: A scalable neural circuit generation framework. In The Thirty-eighth Annual Conference on Neural Information Processing Systems, 2024.", "quality": null, "clarity": null, "significance": null, "originality": null, "strengths_and_weaknesses": "", "was_revised": false, "final_justification": "", "rebuttal": "", "claims_and_evidence": "", "methods_and_evaluation_criteria": "", "theoretical_claims": "", "experimental_designs_or_analyses": "", "relation_to_broader_scientific_literature": "", "essential_references_not_discussed": "", "other_strengths_and_weaknesses": "", "other_comments_or_suggestions": "", "questions_for_authors": "", "summary_of_paper": "", "summary_of_recommendation": "", "technical_quality": "", "clarity_of_presentation": "", "potential_impact": "", "robotics_focus": "", "quality_of_limitations": "", "questions_for_rebuttal": "", "reasons_to_accept": "", "reasons_to_reject": "", "questions_to_authors": "", "extra_scores": {}}, {"review_id": "o4CTPCzdIU", "reviewer": "Reviewer_8gZq", "summary": "This paper introduces CircuitEvo, an LLM-based evolutionary framework for circuit programs, to tackle the difficulty in balancing compactness and accuracy in LS. By leveraging a graph-based program representation alongside LLM-driven evolution and structure-aware optimization, it iteratively optimizes sequential circuits. Results show 100% generation accuracy, an average 6.74% reduction in circuit size, and significantly better search efficiency versus baseline methods.", "questions": "1. Please respond to the concerns I have raised in the 'weaknesses' section. If the revision can adequately address most of the critical issues, I would consider raising the score.\n2. In my personal opinion, the contribution of this paper lies more in its solid experimentation and significant performance improvements, rather than in its theoretical advancement in AI. Considering this, EDA-focused conferences (such as DAC or ISCA, with an upcoming November deadline) would be a more suitable venue for it.", "limitations": "", "rating": 4, "confidence": 4, "soundness": 2, "presentation": 3, "contribution": 2, "strengths": "1. This paper addresses the important problem of automated sequential circuit design, offering well-defined practical value.\n2. The experimental results significantly outperform existing baseline methods, demonstrating clear advantages in terms of accuracy, scale, and efficiency.  \n3. The theoretical derivations are logically rigorous, with proofs provided for the relevant remarks.", "weaknesses": "1. The paper has a deficiency in terms of innovation. The core techniques—LLM generation, evolutionary algorithms, and circuit function completion—constitute an integration of existing methods, and no novel model architecture or theoretical framework is proposed. Furthermore, the local program search is essentially an incremental improvement of a greedy strategy, lacking a breakthrough in algorithmic originality.\n2. The experimental evaluation in the paper is limited to synchronous sequential circuits and combinational circuits. It does not demonstrate the framework's applicability to asynchronous sequential circuits or circuits with complex feedback loops.\n3. The paper lacks comprehensive ablation studies. It only examines the impact of variants like removing the LLM or the evolutionary algorithm, but fails to evaluate the individual contribution of different evolutionary strategies (E1/E2/R1/R2). For instance, how much would circuit diversity decrease if the E1 exploration strategy were removed?\n4. Validation on extreme scales is missing. The framework was not tested on very large-scale circuits (e.g., with inputs >16 and outputs >70), leaving its scalability unverified.\n5. The comparative analysis of LLMs is brief. It merely lists results from models like GPT-3.5-turbo and Deepseek-V3 without analyzing the impact of LLM parameter scale (e.g., 7B vs. 13B) on generation quality.", "quality": null, "clarity": null, "significance": null, "originality": null, "strengths_and_weaknesses": "", "was_revised": false, "final_justification": "", "rebuttal": "", "claims_and_evidence": "", "methods_and_evaluation_criteria": "", "theoretical_claims": "", "experimental_designs_or_analyses": "", "relation_to_broader_scientific_literature": "", "essential_references_not_discussed": "", "other_strengths_and_weaknesses": "", "other_comments_or_suggestions": "", "questions_for_authors": "", "summary_of_paper": "", "summary_of_recommendation": "", "technical_quality": "", "clarity_of_presentation": "", "potential_impact": "", "robotics_focus": "", "quality_of_limitations": "", "questions_for_rebuttal": "", "reasons_to_accept": "", "reasons_to_reject": "", "questions_to_authors": "", "extra_scores": {}}, {"review_id": "IrSgQ51acl", "reviewer": "Reviewer_m5UB", "summary": "CircuitEvo is a novel framework that utilizes large language models (LLMs) to iteratively evolve circuit programs, enhancing compactness while ensuring functional accuracy. ​\n\nThe paper introduces CircuitEvo, the first LLM-based logic synthesis method that improves circuit compactness and functional accuracy. ​It employs a graph-structured circuit program representation to facilitate LLM comprehension and generation. ​It integrates an evolutionary program generator and a structure-aware function optimizer in an iterative framework. ​Empirical studies show  an average improvement of 6.74% in circuit size over state-of-the-art methods. \n\n\nTask:  Given a truth table T , CircuitEvo aims to generate a circuit program P that exactly satisfies the given functionality while minimizing the number of structure lines (circuit nodes).", "questions": "1. please address the choice of baselines\n2. please carefully focus on ablation regarding which aspect of your approach provides the real benefit (see comments about choice of baseline)", "limitations": "", "rating": 6, "confidence": 4, "soundness": 3, "presentation": 4, "contribution": 2, "strengths": "The proposed graph-structured circuit program effectively encodes circuit topology and functionality in a textual format. ​\n\nThe program consists of three parts: IO definition, structure description, and function definition.\nThis representation bridges the gap between circuit graphs and language-based reasoning, enhancing LLM capabilities. ​\nThe LS problem is formulated to generate a circuit program that satisfies functionality while minimizing the number of nodes. ​\n\nEvolutionary Program Generation Process\nCircuitEvo employs an evolutionary framework to generate diverse and promising circuit programs using LLMs. ​\n\nInitializes a diverse population of accurate circuit programs through a decomposition strategy.\nUtilizes domain-specific evolutionary prompting strategies to guide LLMs in generating high-quality programs. ​\nIncorporates fitness-based population management to select the top-performing programs for subsequent iterations.", "weaknesses": "The LS summary uses very dated algorithms: existing LS approaches typically follow a generate-then optimize framework: they first generate a circuit from the truth table, then apply various operators for circuit optimization. Please update the references to show that topology-driven modern methods exist.\n\nIn terms of baselines I am curious to understand why you selected BDD (quite outdated---1993), and SOP (2017, also not SoA).\nFurther, since you use evolutionary methods, why not compare against one of the many evolutionary SoA methods; some very recent references are below. The failure to compare against existing evolutionary SoA methods means that we can't evaluate ablation techniques well, i.e., is it the evolutionary part that makes the difference, the graph part, or what?\n\n\nChen, Yu, and Shao-Yun Fang. \"Optimizing Analog Circuit Design Through a Machine Learning‐Assisted Evolutionary Algorithm.\" Electronics Letters 61, no. 1 (2025): e70331.\n\nCampilho-Gomes, Miguel, Rui Tavares, and João Goes. \"Analog flat-level circuit synthesis with genetic algorithms.\" IEEE Access (2024).\n\nSrikanth, V., P. Aswini, Rakesh Chandrashekar, N. Sirisha, Manish Kumar, and K. Adnan. \"Machine Learning-Based Analogue Circuit Design for Stage Categorization and Evolutionary Optimization.\" In 2024 Second International Conference Computational and Characterization Techniques in Engineering & Sciences (IC3TES), pp. 1-6. IEEE, 2024.", "quality": null, "clarity": null, "significance": null, "originality": null, "strengths_and_weaknesses": "", "was_revised": false, "final_justification": "", "rebuttal": "", "claims_and_evidence": "", "methods_and_evaluation_criteria": "", "theoretical_claims": "", "experimental_designs_or_analyses": "", "relation_to_broader_scientific_literature": "", "essential_references_not_discussed": "", "other_strengths_and_weaknesses": "", "other_comments_or_suggestions": "", "questions_for_authors": "", "summary_of_paper": "", "summary_of_recommendation": "", "technical_quality": "", "clarity_of_presentation": "", "potential_impact": "", "robotics_focus": "", "quality_of_limitations": "", "questions_for_rebuttal": "", "reasons_to_accept": "", "reasons_to_reject": "", "questions_to_authors": "", "extra_scores": {}}]

Author rebuttal:

Decision: Accept (Poster)