CktGNN:  Circuit Graph Neural Network for Electronic Design Automation
Authors: Zehao Dong
Weidong Cao
Muhan Zhang
Dacheng Tao
Yixin Chen
Xuan Zhang
Venue: ICLR 2023 poster (2023)
Keywords: Graph Neural Networks
Electronic Design Automation
Benchmark Graph Dataset

Abstract: The electronic design automation of analog circuits has been a longstanding challenge in the integrated circuit field due to the huge design space and complex design trade-offs among circuit specifications. In the past decades, intensive research efforts have only been paid to automate the transistor sizing with a given circuit topology. By recognizing the graph nature of circuits, this paper presents a Circuit Graph Neural Network (CktGNN) that simultaneously automates the circuit topology generation and device sizing based on the encoder-dependent optimization subroutines. Particularly, CktGNN encodes circuit graphs using a two-level GNN framework (of nested GNN) where circuits are represented as combinations of subgraphs in a known subgraph basis. In this way, it significantly improves efficiency by reducing the number of subgraphs to perform message passing.

Nonetheless, another critical roadblock to advancing learning-assisted circuit design automation is a lack of public benchmarks to perform canonical assessment and reproducible research. To tackle the challenge, we introduce Open Circuit Benchmark (OCB), an open-sourced dataset that contains $10$K distinct operational amplifiers with carefully-extracted circuit specifications from physical implementations. OCB also equips with communicative circuit generation and evaluation capabilities such that it can be used to generalize the applicability of CktGNN to design various analog circuits by efficiently producing corresponding datasets. Experiments on OCB show the extraordinary advantages of CktGNN through representation-based optimization frameworks over other recent powerful GNN baselines and manual design from human experts. Our work paves the way toward a learning-based open-sourced design automation flow for analog circuits.

Published as a conference paper at ICLR 2023
CKTGNN: CIRCUIT GRAPH NEURAL NETWORK FOR ELECTRONIC DESIGN AUTOMATION
Zehao Dong!. Weidong Cao Muhan Zhang* Dacheng Tao Yixin Chen Xuan Zhang
(zehao. dong, we dong. cao, xuan. zhang) ( @wsstl.wsllllle chenêcse wust. edu & muhanêpku edu. en & dacheng taoesydney edu.
ABSTRACT
The electronic design automation of analog circuits has been a longstanding chal- lenge in the integrated circuit field due to the huge design space and complex design trade-offs among circuit specifications. In the past decades, intensive re- search efforts have mostly been paid automate the transistor sizing with given circuit topology. By recognizing the graph nature of circuits, this paper presents a Circuit Graph Neural Network (CktGNN) that simultaneously automates the circuit topology generation and device sizing based on the encoder-depender tion subroutines. Particularly, CkiGNN encodes circuit graphs using a two-level GNN framework (of nested GNN) where circuits are represented combinations subgraphs in a known subgraph basis. In this way, significantly improves design efficiency by reducing the number of subgraphs to perform message pass- ing. Nonetheless, another critical roadblock to advancing learning-assioe assisted circuit design automation is lack of public benchmarks to perform canonical assessment and reproducible research. To tackle the challenge, we introduce Open Circuit Benchmark (OCB), an open-sourced dataset that contains 10K distinct operational amplifiers with carefully-extracted circuit specifications. OCB is also equipped with communicative circuit generation and evaluation capabilities such that can help generalize CktGNN to design various analog circuits by producing corresponding datasets. Experiments on OCB show the extraordinary advantages of CkiGNN through representation-bun based optimization frameworks over other recent powerful GNN baselines and human experts' manual designs. Our work paves the way toward learning-based open-sourced design automation for analog circuits. Our source code is available at
optimiza-
INTRODUCTION
Graphs are ubiquitous to model relational data across disciplines (Gimmer et al., 2017 Duvenaud et al.
Dong et al.) (021). Graph neural networks (GNNs) (Kipf & Welling 2016 Xu et al.) 2019 Velickovic et al., 2018, You et al. 20188] Scarselli et al. 2008 have been the de facto standard for representation learning over graph-structure data due to the superior expressiveness and flexibility.
In contrast to heuristics using hand-crafted node features (Kriege et al. 2020) and non- non-parameterizee graph kernels (Vishwanathan et al. [2010: Shervashidze et al. 2009 Borgwardt & Kriegel 2005). GNNs incorporate both graph topologies and node features to produce the mode/graph-leve em- beddings by leveraging inductive bias in graphs, which have been extensively used for node/graph
classification (Hamilton et al. 2017 Zhang et al. 2018), graph decoding (Dong et al. 2022 Li et al.) 2018), link prediction (Zhang & Chen 2018), and etc. Recent successes GNNs have boosted the requirement for benchmarks to properly evaluate and compare the performance of different GNN architectures. Numerous efforts have been made to produce benchmarks of various graph graph-structio structured data. Open Graph Benchmark (OGB) (Hu et al. (2020) introduces a collection of realistic and diverse graph datasets for real-world applications including molecular networks, citation networks,
Department of Computer Science & Engineering, Washington University in St. Louis. 2 Department of Electrical & Systems Engineering, Washington University in St. Louis. Institute for Artificial Intelli- gence, Peking University. School of Computer Science, The University of Sydney. Equal contribution. Corresponding authors.

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source code networks, user-product networks, etc. NAS-Bench-101 (Ying et al. 2019 and NAS-
Bench-301 (Zela et al. 2022) create directed acyclic graph datasets for surrogate neural architecture search (Elsken et al. 2011: Wen et al. 2020). These benchmarks efficiently facilitate substantial and reproducible research, thereby advancing the study of graph representation learning.
Analog circuits, an important type of integrated circuit (IC), are another essential graph modality (directed acyclic graphs, i.e., DAGs). However, since the advent of ICs, labor-intensive manual efforts dominate the analog circuit design process, which is quite time-consuming and cost-ineffective. This problem is further exacerbated by continuous technology scaling where the feature size of transistor devices keeps shrinking and invalidates designs built with older technology. Automated analog circuit design frameworks are thus highly in demand. Dominant representation-bent based approaches (Liu et al. 2021 Wang et al. 2020, Cao et al.
alla|a222220 2022a b) Zhang et al. 2019a) have recently been developed for analog circuit design automation. Specifically, they optimize device parameters to fulfill desired circuit specifications with a given circuit topology. Typically, GNNs are applied to encode nodes' embeddings from circuit device features based on the fixed topology, where black-box optimization techniques such as reinforcement learning (Zoph & Le 2016) and Bayesian Optimization (Kandasamy et al.) 2018) are used to optimize parameterized networks for automated searching of device parameters. While these methods promisingly outperform traditional heuristics (Liu et al. 2017) in node feature sizing (i.e., device sizing), they are not targeting the circuit topology optimization//enerationn which, however, constitutes the most critical and challenging task in analog circuit design.
In analogy to neural architecture search (NAS), we propose encode analog circuits into continuous vectorial space to optimize both the topology and node features. Due to the DAG essence of analog circuits, recent DAG encoders for computation graph optimization tasks are applicable to circuit encoding. However, GRU-based DAG encoders (D-VAE (Zhang et al. 2019b) and DAGNN (Thost & Chen 202I ) use shallow layers to encode computation defined by DAGs, which is insufficient to capture contextualized information in circuits. Transformer-based DAG encoder (Dong et al. [2022] however, encodes DAG structures instead of computations. Consequently, we introduce Circuit Graph neural Network (CKIGNN) to address the above issues. Particularly, CkIGNN follows the nested GNN (NGNN) framework (Zhang & Li| 202I). 1). which represents a graph with rooted subgraphs around nodes and implements message passing between nodes with each node representation encoding the subgraph around it. The core difference is that CkIGNN does not extract subgraphs around each node. Instead, a subgraph basis is formulated in advance, and each circuit is modeled DAG G' where each node represents a subgraph in the basis. Then CkIGNN uses two-level GNNs to encode a circuit: the inner GNNs independently learn the representation of each subgraph as node embedding, and the outer GNN further performs directed message passing with learned node embeddings to learn a representation for the entire graph. The inner GNNs enable CktGNN to stack multiple message passing iterations to increase the expressiveness and parallelizability. while the outer directed message passing operation empowers CkIGNN to encode computation of circuits (i.e. circuit performance).
Nonetheless, another critical barrier to advancing automated circuit design is the lack of public benchmarks for sound empirical evaluations. Researches in the area are hard to be reproduced due to the non-unique simulation processes on different circuit simulators and different search space design. To ameliorate the issue, we introduce Open Circuit Benchmark (OCB), the first open graph dataset for optimizing both analog circuit topologies and device parameters, which is good supplement to the growing open- soen-souree research in the electronic design automation (EDA) community for IC (Chai al. [2022] Hakhamaneshi et al. 2022). OCB contains 10K distinct operational amplifiers (circuits) whose topologies are modeled as graphs and performance metrics are carefully extracted from circuit simulators. Therefore, the EDA research can be conducted via querying OCB without notoriously tedious circuit reconstructions and simulation processes on the simulator. In addition, we will open-source codes of the communicative circuit generation and evaluation processes to facilitate further research by producing datasets with arbitrary sizes and various analog circuits. The OCB dataset is also going to be uploaded to OGB to augment the graph machine learning research.
The key contributions in this paper are: 1) we propose a novel two-level GNN, CkIGNN, to encode circuits with deep contextualized information, and show that our GNN framework with a pre-designed subgraph basis can effectively increase the expressiveness and reduce the design space of a very challenging problem- groblem-eircuit topology generation; 2) we introduce the first circuit benchmark dataset OCB with open-source codes, which can serve as an indispensable tool to advance research in EDA; 3) experimental results on OCB show that CkiGNN not only outperforms competitive GNN baselines but also produces high-competitive operational amplifiers compared to human experts' designs.
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2 RELATED WORKS
2.1 GRAPH NEURAL NETWORKS
GNNs for DAGs Directed acyclic graphs (DAGs) are another ubiquitous graph modality in the real world. Instead of implementing message passing across all nodes simultaneously, DAG GNNs (encoders) such as D-VAE (Zhang et al. 2019b) and DAGNN (Thost & Chen [ sequentially encode nodes following the topologiaal order. Message passing order thus respects the computation dependency defined by DAGs, Similarly, S-VAE (Bowman et al. (016) represents DAGs as sequences of node strings of the node type and adjaceney vector of each node and then applies GRU-based RNN to the topologically sorted sequence to learn the DAG representation. To improve the encoding efficiency, PACE (Dong et al. (022) encodes the node orders in the positional encoding and processes nodes simultaneously under Transformer (Vaswani et al. 2017) architecture.
2.2 AUTOMATED ANALOG CIRCUIT DESIGN
Design Automation Methods for Device Sizing Intensive research efforts have been paid in the past decades to automate the analog circuit design at the pre-layout level, i.e., finding the optimal device pa- rameters to achieve the desired circuit specifications. Early explorations focus pptimization-basee
methods, including Bayesian Optimization (Lyu et al. 2018). Geometric Programming (Colleran) al. 2003), and Genetic Algorithms (Liu al. 2009). Recently, learning-based methods such as supervised learning methods (Zhang et al. (2019)) and reinforcement learning methods (Wang et al. Cao et al. [202aa b) have emerged as promising alternatives. Supervised learning methods aim to learn the underlying static mapping relationship between the device parameters and circuit specifications. Reinforcement learning methods, on the other hand, endeavor to find a dynamic programming policy to update device parameters in an action space according to the observations from the state space of the given circuit. Despite their great promise, all these prior arts have been limited to optimizing the device parameters with a given analog circuit topology. There are only few efforts (c.g., Genetic Algorithms (Das & Vemuri (007)) to tackle another very challenging yet more important problem, i.e, circuit topology synthesis. These works leverage genetic operations such as crossover and mutation to randomly generate circuit topologies and do not sufficiently incorporate practical constraints from feasible circuit topologies into the generation process. Therefore, most of the generated topologies are often non- con-functional and ill- ill-posed. Conventionally, a newly useful analog circuit topology is manually invented by human experts who have rich domain knowledge within several weeks or months. Our work focuses on efficiently and accurately automating circuit topology generation, based on which the device parameters for the circuit topology are further optimized.
2020 Li et al. 202 |
Graph Learning for Analog Circuit Design Automation With the increasing popularity of GNNs in various domains, researchers have recently applied GNNs to model circuit structures as a circuit topology resembles graph very much. Given a circuit structure, the devices in the circuit can be treated as graph vertices, and the electrical connections between devices can be abstracted as edges between vertices. Inspired by this homogeneity between the circuit topology and graph, several prior arts have explored GNNs to automate the device sizing for analog circuits. A supervised learning method (Zhang et al., 2019a) is applied to learn the geometric parameters of passive devices with customized circuit- circuit-topology based GNN. And reinforcement learning-base based methods (Wang et al. 2020 Cao al. 2022b) propose circuit- ropology-basee policy networks to search for optimal device parameters to fulfill desired circuit specifications. Distinctive from these prior arts, our work harnesses two-level GNN encoder simultaneously optimize circuit topologies and device features.
3 CIRCUIT GRAPH NEURAL NETWORK
In this section, we introduce the proposed CkIGNN model constructed upon a two-level GNN framework with a subgraph basis to reduce the topology search space for the downstream optimization algorithm. We consider the graph-level learning task. Given graph g (V, E). where V = {1, 2...... n is the node set with [V| = n and E E V x V is the edge set. For each node in graph g, we let ((v) {u E V( v) E F) denote the set of neighboring nodes of v.
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basis
Subgraphe
Inner GNNNs
Message Passing
Outer
A Impolt graph
Figure 1: Illustraionn of the two-level GNN framework with a pre-designed subgraph basis. It first represents input graph g as combination of subgraphs in the subgraph basis and then learns representations of subgraphs with inner GNNs. The subgraph representations are used as input features to the outer message passing operation, where the message passing can be directed/undirected.
3.1 TWO-LEVEL GNN FRAMEWORK WITH A SUBGRAPH BASIS
Most undirected GNNs follow the message passing framework that iteratively updates the nodes' representation by propagating information from the neighborhood into the center node. Let h denote the representation of time stamp f, the message passing framework is given by:
de ++ A((halu,, v) E E)) he* U(h a. d
Here, A is an aggregation function on the multiset of representations of nodes in in.(() (w)). and / an update function. Given undirected graph G, GNNs perform the message passing over all nodes simultaneously. For a DAG G, the message passing progresses following the dependency of nodes in DAG G. That is, node v's representation is not updated until all of its predecessors are processed.
has been shown that the message passing scheme mimics the 1-dimensional Weisfeiler-Lehhme (I-WL) algorithm (Leman Weisfeiler 1968). Then, the learned node representation encodes rooted subtree around each node. And GNNs exploit the homophily as a strong inductive bias in graph learning tasks, where graphs with common substructures will have similar predictions. However, encoding rooted subtrees limits the representation ability, and the expressive power of GNNs is upper-bounded by the 1-WL test (Xu al., 2019). For instance, message passing GNNs fail to differentiate d-regular graphs (Chen et al. 2019 Murphy et al. 2019).
To improve the expressive ability, Zhang & (021)) introduces two-level GNN framework, NGNN, that encodes the general local rooted subgraph around each node instead of subtree. Concretely, given a graph G, h-hopp rooted subgraph d around each node is extracted. Then, inner GNNs are independently applied to these subgraphs {g y E G} and the learned graph representation of d is used as the input embedding of node v to the outer GNN. After that, the outer GNN applies graph pooling get graph representation. The NGNN framework is strietly more powerful than 1-WL and can distinguish almost all d-regular graphs. However, the two-level GNN framework can not be applied to DAG encoders (GNNs).
Hence, we introduce a two-level GNN framework with an (ordered) subgraph basis, to restrict subgraphs for inner message passing in the given subgraph basis and apply to the circuit (DAG) encoding problems in order to reduce the topology search space and increase the expressive ability.
Definition 3.1 (Ordered subgraph basis) An ordered subgraph basis B [91 92, ..., gk} is of subgraphs with a total order o. For Vg1, 92 E B, 91 < 92 if and only if o(g)) < o(g2).
Figure ] Tillustrates the two-level GNN framework. Given graph G and an ordered subgraph basis B. the rules to extract subgraphs for inner GNNs to learn representations are as follows: 1) For node E G. suppose it belongs to multiple subgraphs 9f ...g" g E IB, then the selected subgraph to perform (inner) message passing is 9h = argmax,- 2...... m o(g.") ). 2) If connected nodes v and u select the same subgraph 9h. B. merge e and u and use the representation of subgraph gı. the feature of the merged node when performing the outer message passing. We show that two-level GNNs can be more powerful than 1-WL. in Appendix B
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Fiod 1002
Ben
Rrd
Grd
CHIGNN:
Graphilteer
R. and
Undirected Inner GNha
Graphs
Representation leaming
Directed outer
Feedback path
Node
Node
Stage Main feedfoowwrd path
Shage
S
"oodo
Subgraph
Circult simulators
CiroutCloud
GND
SPICE
Performance
ate
Circults: operational amplifier
evaluation
Exact cirpuit structure
Behavioral
Figure Illustration of the overall framework. The performance evaluation of circuits is implemented on the circuit simulator. In the representation learning process, we formulate a subgraph basis for operational amplifiers implement the CktGNN model.
3.2 THE CKTGNN MODEL
Next, we introduce the CkıGNN model for the circuit (i.e. DAGs) automation problem which requires optimizing the circuit topology and node features the same time. Given circuit G (V, F)), each node E V has a node type It and node features Ia. where Ie denotes the device type in circuit (i.e., resistor, capacitor, and etc.), and v, are the categorical continuous features of the corresponding device.
Due to the similarity between the circuit automation problem and neural architecture search (NAS), potential solutions naturally come from advancements in neural architecture search, where two gradient-hased frameworks have achieved impressive results in DAG architecture learning: 1) The VAE framework (Dong et al.) 2022,,hanm et 2019bb) uses GRU-based (or Transformer-basse coder to map DAGs into vectorial space and then trains the model with VAE loss. 2) NAS-subroutine- based framework develops DAG encoders and implements encoding-dependent subroutines such as perturb-architecture subroutines (Real et al. 2019; White et al. 2020) and train prain-predictor-modee subroutines (Wen al. 2020; Shi et al. 2019). As the NAS-subroutine baased framework usually requires a relatively large-size training dataset, yet the large-scale performance simulation of circuits can be time-consuming, we resort to the VAE framework.
en-
Due to the complexity of circuit (DAG) structures and the huge size of the circuit design space (see Appendix A), the circuit automation problem is typically highly non-convex, challenging optimization problem. Thus, the GRU-based encoders that use shallow layers to encode complex DAG architectures are sufficient to capture complicated contextualized information of node features and topologies.
To address these limitations, we introduce the CkIGNN model. Figure 2 illustrates the architecture of CkIGNN. The key idea is to decompose the input circuit as combinations of non-overlapping subgraphs in the subgraph basis B. After the graph transformation process (i.e. graphlizer f), each node the transformed DAG G' (V', EE') represents subgraph in the input graph (circuit). Then, the representation of circuit is learned in the two-level GNN framework.
Each node v' E V' in the transformed DAG G' corresponds to a subgraph g,' in the input graph. CkIGNN treats g. as an undirected graph and uses inner GNNs to learn the subgraph representation h,, and each inner GNN consists of multiple undirected message passing layers followed by graph pooling layer to summarize a subgraph representation. Such technique enables inner GNNs to capture the contextualized information within each subgraph, thereby increasing the representation ability. In addition, undirected message passing also provides better parallelizability than directed message passing, which increases encoding efficiency.
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In the outer level GNN, CktGNN performs directed message passing where the aggregation function A uses a gated summation and the update function uses gated recurrent unit (GRU):
a A(tzy/lú E EN(('))) Ev (E) m(z,);
(2)
Rv/ U(conca(x. hh),,,))))) ).)))))))))))))
(3)
Here, 2, is the hidden representation of node v in the transformed DAG G', m is a mapping network and g is a gating network. In the GRU, x is the one-hot encoding of the subgraph type, and h, is the corresponding subgraph representation learned by inner GNNs. The outer level GNN processes nodes in transformed DAG G' following the topological order, and uses the hidden representation of the output node as the graph representation.
3.3 DISCUSSIONS
The Injectivity of Graph Transformation Process Since CkiGNN is constructed upon a graphlizer f: G G G' that converts imput circuits G to DAGs G' whose nodes v represent non-overlapping subgraphs in G, it's worth discussing the injectivity of f. If f(G) is not unique, CkIGNN will map the same input circuit (DAG G) to different transformed G', thereby learning different representations for the same input G.
Theorem 3.2 Let subgraph basis B contain every subgraph of size There exists an injective graph transformation if each subgraph 9v' IB has only one node be the head (tail) of a directed edge whose tail (head) is outside the subgraph 9,'
We prove Theorem 3.2 in Appendix C The theorem implies that f exists when subgraph basis IB contains every subgraph of size 1 and characterizes conditions when the injectivity concern is satisfied. The proof shows that an injective ff can be constructed based on the order function o over the basis IB. The condition in the Theorem holds in various real- world applications including circuit automation and neural architecture search. For instance, Figure presents an ordered subgraph basis that satisfies the condition for the general operational amplifiers (circuits), and introduce operational amplifiers and the corresponding subgraph basis in Appendix
Drgure2peeeentts
Comparison to Related Works. The proposed CkıGNN model extends the NGNN technique (i.e., two-level GNN framework) (Zhang & Li [022]) to the directed message passing framework for DAG encoding problem. In contrast NGNN which extracts a rooted subgraph structure around each node within which inner GNNs perform message passing to learn the subgraph representation, CktGNN only uses inner GNNs to learn representations of non-overlapping subgraphs in a known ordered subgraph basis IB. Two main advantages come from the framework over GRU-based DAG encoders (i.e. D- D-V and DAGNN). 1) The topology within subgraphs is automatically embedded once the subgraph type is encoded in CkGGNN, which significantly reduces the size of the topology search space. 2) The inner GNNs in CkIGNN help to capture the contextualized information within each subgraph, while GNNs in GRU-based DAG encoders are usually too shallow to provide sufficient representative ability.
4 OPEN CIRCUIT BENCHMARK
We take operational amplifiers (Op-Amps to build our open circuit benchmark as they are not only one of the most difficult analog circuits design in the world. but also are the common benchmarks used by prior arts (Wang et al. 2020 Li et al. 2021 Cao et al. (022b) to evaluate the performance of the proposed methods. Our benchmark equips with communicative circuit generation and evaluation capabilities such that it can also be applied to incorporate broad range of analog circuits for the evaluations various design automation methods. To enable such great capabilities, two notable features are proposed and introduced below.
Converting Circuits into Graphs We leverage an acyclic graph mapping method by abstracting a complex circuit structure to several simple low-level functional sub-structures, which is similar the standard synthesis of modern digital circuits. Such a conversion method is thus scalable to large-scale analog circuits with thousands of devices while effectively avoiding cycles in graph converting. To

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Table 1: Predictive performance and topology reconstruction accuracy.
Clain
BW
PM
FrM
Recun
Fudhation Metric
RMSF
Pesmon'sr
RMSR
Porson's
RMSF
Proson'kr
RMSF.
Prsnuri's x
Acc 1
CRIGNN
0.077 0,003
0.791 0.002
0.873 1: 0,005
0,479
00001
0.973 0.002
0.217 0.001
0.54
(U083
[1,99]
6.002
0.397
PACE
0.0003
0.762
0.002
0,886 0,001
0:442
0,889 0.003
0.423 00000
0.451
0,777
D-VAE
0.739 0.001
0.002
0.002
0.005
0.374 0.000
GCN
0.972 0.003
0,140 + 0.002
0.970 + 0.003
0.236 0.001
0.993 0.002
0.171
0.0001
0.974 0.005
0.217 + 0.001
0.658
GEN
0,850 0.003
0,352 2: 0.001
0.926 0.002
0.251
0.001
0.985 0.004
0.167
000022
0.910 = 0.033
0.264 5: 0.000
0.051
NGNN
08832 2 0.005
0.633
-: 0.002
0,933
8: 0.003
0.247
0091
0,984 0000
0.899
9 0.002
0.926 = 0.002
0.267
8 0.001
0130
Pathioemerr
08816 0.003
0,589 :: 0.001
0,805 6 0/002
0,410 - 0.00
0,967 8 0.002
0.797
8 0.001
0.387 - 0.002
0.391 1 0.001
0.881
illustrate this general mapping idea, we take the Op-Amps in our benchmark as example (see the left upper corner in Figure 2) For an N-stage Op-Amp (N = 2, 2), it consists of N single-stage Op-Amps in the main feedforward path (i.e., from the input direction to the output direction) and several feedback paths (i.e., vice versa) with different sub-circuit modules. We encode all single-stage Op-Amps and sub-eireuit modules as functional sub-structures by using their behavioral models (Lu) it al., (02T). In this way, each functional sub-structures can be significantly simplified without using its exact yet complex circuit structure. For instance, a single-stage Op-Amp with tens of transistors can be modeled as a voltage-controlles current source (VCCS, 9m) with a pair of parasitic capacitor C' and resistor R. Instead of using these functional sub-structures as graph vertices, we leverage them as our graph edges while the connection point (e.g., node 1 and node 2) between these sub-structures is taken as vertices. Meanwhile, we unify both feedforward and feedback directions as feedforward directions but distinguish them by adding polarity (e.g.. '+' for feedforward and '-' for feedback) on device parameters (e.g.. Im + or 9m -). In this way, an arbitrary Op-Amp can be efficiently converted into acyclic graph as shown in Figure 2 Inversely, newly-generated circuit topology from graph sampling can be converted back into the corresponding Op-Amp by using a conversion- back process from the graph and functional sub-structures to real circuits.
Interacting with Circuit Simulators Another important feature of our circuit benchmark is that it can directly interact with a circuit simulator evaluate the performance of generated Op-Amp in real-time. Once a circuit topology is generated from our graph sampling, a tailored Python script can translate it into a circuit netlist. A circuit netlist is standard hardware description of a circuit, based on which the circuit simulator can perform a simulation (evaluation) to extract the circuit specifications, e.g., gain, phase margin, and bandwidth for Op-Amps. This process can be inherently integrated into Python environment as both open-sourced and commercial circuit simulators support command-line operations. We leverage this loop to generate 10, 000 different Op-Amps with detailed circuit specifications. Note that in our dataset, the topologies of Op-Amps are not always distinct from each other. Some Op-Amps have the same topology but with different device parameters. However, benchmark is friendly augment other analog circuits such as filters if corresponding cireuit-graph mapping methods are built.
EXPERIMENTS
5.1 DATASET, BASELINES, AND TASKS
Dataset Our circuit dataset contains 10,000 operational amplifiers (circuits) obtained from the circuit generation process of OCB. Nodes in a circuit (graph) are sampled from C' (capacitor). R (resistor), and single-stage Op-Amps with different polarities (positive or negative) and directions (feedforward or feedback). Node features are then determined based on the node type: resistor R has a specification from 10 to 10? Ohm, capacitor C has a specification from 10- 14 to 10-12 F, and the single-stage Op-Amp has a specification (transconductance,, 9m) from 10-4 to 10 2 S. For each circuit, the circuit simulator of OCB performs careful simulations to get the graph properties (circuit specifications): DC gain (Gain), bandwidth (BW). and phase margin (PM), which characterize the circuit performance from different perspectives. Then the Figure of Merit (FoM) which is an indicator of the circuit's overall performance is computed from Gain, BW, and PM. Details are available in Appendix B
Baselines We compare CkiGNN with GNN baselines including: 1) widely adopted (undirected) GNNs: GCN (Kipf & Welling 2016), GIN (Xu et al. 2019), NGNN ZZhang & Li 2021) and
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675
CoGMR NEW DANN
Ave. informnce time (secondi))
COSAN
5GG Nix
Ave traiiing tinelpach
100
16
13
Training Efficiency
Inference Efficiency
Figure 3: Comparison of training/inference efficiency.
Graphormer (Ying et al.
2021); 2) dominant DAG encoders (directed GNNs): D-VAE (Zhang et al.
2019b), DAGNN (Thost & Chen 202T and PACE (Dong et al. 2022). Baseline settings provided
in Appendix D
Tasks We compare CkIGNN against baselines on the following three tasks evaluate the expres- siveness, efficiency, and real-world impact: (1) Predictive performance and topology reconstruction accuracy: We test how well the learned graph representation encodes information to predict the graph properties (i.e., Gain, BW, PM, FoM) and reconstruct the input circuit topology. (2) Circuit encoding efficiency: This task compares the training/inference time to characterize the efficiency the circuit (DAG) encoders. (3) Effectiveness in real-world electronic circuit design automation: For the purpose of circuit generation, we test the proportion that the decoder the VAF architecture can generate valid DAGs, circuits, and new circuits that are purpose automated circuit design, we also perform Bayesian Optimization and compare the overall performance (i.e. FoM) of the detected circuit topology and specifications.
seen in the training set. Furthermore, for the
5.2 PREDICTIVE PERFORMANCE AND TOPOLOGY RECONSTRUCTION ACCURACY
In the experiment, we test the expressive ability of circuit encoders by evaluating the predictivity of the learned graph representation. As the encoder with more expressive ability can better distinguish circuits (graphs) with different topologies and specifications, circuits with similar properties (Gain, BW, PM. or FoM) can mapped close representations. Following experimental settings of D-VAE (so DAGNN and PACE), we train sparse Gaussian Process (SGP) regression models (Snelson & Ghahramani 2005) to predict circuit properties based on learned representations. In addition, we also characterize the complexity of topology space to encode by measuring the reconstruction accuracy of the circuit topology.
We show our results in Table I Experimental results illustrate that CkıGNN consistently achieves state-of-art performance predicting circuit properties. In analogy to D-VAE, we find CkIGNN encodes computation (i.c., circuit performance) instead of graph structures when the map between subgraph structure and their defined computation injective for subgraphs in the basis B. Compared to DAG encoders D-VAE and DAGNN that encodes circuit, inner GNNs in CkiGNN enables more message passing iterations to better encode the complicated contextualized information circuits. On the other hand, PACE, undirected GNNs, and graph Transformers inherently encode graph structures, hence, the latent graph representation space of CkIGNN is smoother w.r.t the circuit performance. Furthermore, we also find that CkIGNN significantly improves the topology reconstruction accuracy. Such an observation is consistent with the purpose of CktGNN (see Section 3.2) b to reduce the topology search space.
5.3 CIRCUIT ENCODING EFFICIENCY
Besides the representation learning ability, efficiency and scalability play critical roles in the model design due to the potential heavy traffic coming into the circuit design automation problem in the real world. In the experiment, we compare the average training time per epoch to validate the efficiency of the VAE framework that includes a circuit encoding process and a circuit generation process, while the encoding efficiency itself is tested using the average inference time. Figure iillustrats the results. Compared to bRUsddded computation encoders (i.e., D- VAE and DAGNN), since CktGNN utilizes simultaneous message passing within each subgraph, it significantly reduces the training/inference
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time. In addition, we also find that the extra computation time of CktGNN to fully parallelize encoders (i.e., undirected GNNs like GCN) is marginal.
5.4 EFFECTIVENESS IN REAL- WORLD ELECTRONIC CIRCUIT DESIGN
Next, we test the real-world performance of different circuit encoders from two aspects. 1) In real-world automation process, the circuit generator (i.e., decoder in the VAE framework) is required be effective generate proper and novel circuits. Hence, we compare the proportion of valid DAGs, valid circuits, and novel circuits of different methods. 2) We also perform batch Bayesian Optimization (BO) with batch size 50 using the expected improvement heuristic (Jones et al. 1998) and compute the FoM of the detected circuits after 10 iterations.
Table 2: Effectiveness in real-world electronic circuit design.
Methods
Valid (%)
Valid circuits
Novel circuits
CkIGNN
98.92
98.92
92.29
33,436447
PACE
83.12
75.52
97.14
33,274162
DAGNN
83.10
74:21
97. 19
33,274162
D-VAE
82.12
73.93
97.15
32,377778
GCN
81.02
72.03
01
31,624473
GIN
80.92
73.17
96.88
31,624473
NGNN
82.17
73.22
95.29
32,282656
Graphormer
Table iillustrates the results. We find that the proportion valid circuits generated by the CkIGNN- related decoder is significantly higher than other decoders. One potential reason is that CkIGNN has an easier topology space to encode and the corresponding decoder can thus better learn the circuit generation rules. We also find that CktGNN has the best circuit design (generation) ability in the generation process. These observations are significant for real-world applications as the automation tools can perform fewer simulations be cost-effective and time-efficient. In the end, we find that CkIGNN-based VAE can find the best circuits with the highest FoM, and we visualize detected circuits in Appendix D
CONCLUSION AND DISCUSSIONS
In this paper, we have presented CkIGNN, a two-level GNN model with a pre-designed subgraph basis for the circuit (DAG) encoding problem. Inspired by previous VAE-based neural architecture search routines, we applied CkIGNN based on a VAE framework for the challenging analog circuit design automation task. Experiments on the proposed open circuit benchmark (OCB) show that our automation tool can address this long-standing challenging problem in a predictivity-effecti time-efficient way. To the best of our knowledge, the proposed CkIGNN-based automation framework methods to simultaneously optimize the circuit topology
and
pioneers the exploration of learning-bard and device parameters to achieve the best cireuit performance. In addition, the proposed OCB is also the first open- open-source benchmark in the field of analog circuit topology generation and device parameter optimization. Last but not the least, both our method and benchmark can be generalized to other types of analog circuits with excellent scalability and compatibility.
With the increasing popularity of applying deep learning methods to design industrial digital circuits such as Google TPU (Mirhoseini et al. 2021) and Nvidia GPU (Khailany et al., 2020), the attention paid to analog circuit design automation will be unprecedented as analog circuits are critical type of ICs to connect our physical analog world and modern digital information world. In a nutshell, we believe that deep learning (especially graph learning)- based analog circuit design automation is an important rising field, which is worthy of extensive explorations and interdisciplinary collaborations.
7 ACKNOWLEDGEMENT
This work is supported in part by NSF CCF # #1942900 and NSF CBET 2225809.

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8 REPRODUCIBILITY STATEMENT
The main theoretical contribution of our paper comes from Theorem 3.2 and the complete proof of the Theorem available Appendix C Furthermore, our proposed circuit encoder, CkIGNN, is constructed upon the two-level GNN framework with pre-designed subgraph basis, hence we compare with general two-level GNN in Section [.2] and discuss the expressive ability in Appendix B For our open circuit benchmark (OCB), we provide detailed instructions in Appendix and provide open-source code in supplementary material, including the circuit generation code and the simulation file for the circuit simulator. Our source code to implement experiments is also provided in the supplementary materials, and we will make it public on Github in the future.
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A OPERATIONAL AMPLIFIERS (CIRCUITS) AND THE CORRESPONDING SUBGRAPH BASIS
In this work, we take one type of the most classical analog circuits, i.e., operational amplifiers (Op-Amps), as example to present our graph beannng-basee automation framework. In this paper, the question we are interested in is that given a group of Op-Amp circuit specifications that are required by particular application, how do a proper Op-Amp topology and the corresponding optimal device parameters to achieve the desired circuit specifications? However, ultimate goal is generalize this method to design various analog circuits and even radio-frequency and millimeter-wave circuits.
graph caaming-based automation method find
For Op-Amp, it has many circuit specifications. We pick up four main specifications, i.e., DC gain (A), bandwidth (BW), phase margin (PM), and power consumption (P) in this project. All these specifications can be simulated by using circuit simulators or derived by using simplified behavioral model of Op-Amps.
Feedforward
Feedback
path1
pathl
A1
A2
A3
Input
Output
Stage
Stage
Stage
Main path
Figure 4: The conceptual illustration of a three-stage op-amp.
Figure 4 shows the conceptual illustration of three-stage Op-Amp, which consists of the main path, several feed-forward paths (e.g.. feed-forward path 1), and several feedback paths (e.g.. feedback path1). In the main path, there three single-stage Op-Amps, i.e., A1, A2, and A3. The total gain of the three-stage Op-Amp is the product of the gain of each single-stage Op-Amp. To make the Op-Amp more stable, the feed-forward and feedback paths are used to realize the compensation schemes. Each of these paths is implemented with electronic circuits, e.g., single-stage Op-Amps, resistor, and capacitor circuits. Note that, the forward and feedback paths are versatile. Figure. just shows very simple example. In addition, each single-stage Op-Amp could have many different topologies. For example, Figure 5 shows some single-stage Op-Amps with various topologies.
VIS
Vo
VN
Veus
(a)
(b)
Figure 5: Different topologies single-stage Op-Amps. (a) A differential Op-Amp. (b) A single-end Op-Amp.
Due to the different topologies of single-stage Op-Amps and various compensation schemes, the design space (e.g., topology space and device parameter space) of three-stage Op-Amps is thus very large. The manual process adopted by human designer is very time-consuming. That is why graph learning-bast based methods come here. We can formulate the design of three-stage Op-Amps as a graph generation and optimization problem. In this way, the first step is to model the circuit as a graph. Figure[]]show the basic idea. We map the topology of three-stage Op-Amp into graph with five nodes: input node, node node 2, output node, and
automate the design process. Therefore,
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GND node. The edge connecting two nodes can be single-stage Op-Amp (i.e., transconductance stage, 9ms), resistor (R) or capacitor (C), or a combination them, which are discussed below.
mm
Feedback path
Node
Node 2
ml
9m²
gma
Input
Output node
node
Stage
Stage 2
S tage 3
Main feedforward path
R:
Figure 6: Graph mapping of a stree-stage Op-Amp.
From the perspective of designing a three-stage Op-Amp. there are 24 types of (existing) connections
between every two nodes in the eircuit graph shown in Figure 6
Only single C or R connection (Figure 7a), 2 types)
C and connected in parallel serial (Figure bb), 2 types)
A single-stage Op-Amp (gm) with different polarities (positive, - negative, -9m)
and directions (feedforward or feedback) (Figure ( ,), types);
A single-stage Op-Amp (gm) with or R connected in parallel or serial (Figure dd) 16
types); note that here only take the single-stage Op-Amp with feedforward direction and positive polarities as an example
C
C
-
(a)
R
-
||
(b)
C
W
|| -
9m
9m
Feedforward
Backward
(c)
(c)
Figure 7: Subgraph basis for operational amplifiers.
To simplify the graph learning process, we convert the role of nodes and edges (except for the input node and output node) in Figure 6 then the Figure which illustrates the edge types in the original graph, now presents a subgraph basis B for the operational amplifier.
Given the pre-designed subgraph basis G. we also need to define total order subgraphs in B to guarantee that circuits are injectively represented as DAGs G'. Basically, for subgraphs of size 1, we set o(gm) > o(R) > oC), and 9m with feedforward direction and positive polarity as a prior order than 9m with backward direction and negative polarity. For subgraphs of size larger than 1. the order of subgraphs is firstly dependent on the number nodes in the subgraph. Then, for subgraphs of the same size, the with parallel connection prior that with series connection. In the end,
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if the connection type is also the same, the order of subgraphs is determined by lexicographically sorting the order of nodes in subgraphs.
Expressiveness and total order on nodes Various node orderings have been adopted in encoders for the DAG encoding problem, and node ordering is especially important for auto-regressive models. For instance, S-VAF, D-VAE and DAGNN use topological ordering, PACE and GRAN Liao et al. (2019) use canonical ordering, and graphRNN You et al. (2018) uses BFS ordering. The key of developing powerful DAG encoders is to make sure that node-order dependent encoding process can injectively map non-isomorphic DAGs (or different computation of DAGs) to different embeddings in the vectorial space, and experimental results in prior works (PACE, D-VAE, DAGNN) have confirmed the claim on general DAG encoding tasks, such as NAS (neural architecture search) and Bayesian network structure learning. In summary, PACE can injectively encode the structure of DAGs by linearizing DAGs as sequences according to the canonical ordering, while D-VAE and DAGNN can injectively encode computation of DAGs following an RNN-based directed message passing. Compared with these methods, S- VAE and GraphRNN-lin like encoder (GraphRNN is originally designed as pure generative model, yet it can be extended to a BFS-order based DAG encoder following the idea of S-VAE, and details are available in the ablation study section in paper of PACE) fail to injectively encode structure nor computation of DAGs as both topological ordering and BFS ordering are not unique. As result, PACE, D-VAE, and DAGNN significantly outperforms S-VAE and GraphRNN.
Following the above analysis, we find that the expressive ability of CkıGNN is independent of the domain specific total ordering of nodes. Basically, total ordering of nodes only determines the order of subgraphs (i.e. o) in the subgraph basis IB (plases see the last paragraph in Appendix A). When basis B satisfies the conditions in Theorem 3.2, there exists an injective graphlizer f, and f can be formulated as Appendix C suggests. Hence, for any given order o, the input graph G is injectively mapped to f fG), based on which CkIGNN performs the two-level GNNs. Then, if both the inner GNNs and outer directed message passing are injective, CkIGNN can injectively map ((G) to embeddings in the vectorial space, as injective functions follow the transitive property. Hence, for any order o on subgraph basis B, the overall encoding process can injectively map G to embeddings.
Although the expressive ability is not affected by the node ordering. the complexity of topology search space is dependent on it. When we use different orders: 0₁ and 02, the graphlizer f will map G to different transformed graphs fo, (G) and (G), where for (G) and foz (G) may contain different numbers of subgraphs. Hence, the numbers of connections between subgraphs to encode in the outer message passing are different.
In the studied op-amp circuits automation problem, we find that the order of subgraphs in basis B will not affect the transformation from circuits G to transformed graphs (G) (though it is not true for the general problems) due to the property of op-amp circuits. For instance, when we reverse the order of C and R (i.e from o(R)= > o(C) to o(C') > o(R), the order of subgraphs 'C parallel gm' and 'R parallel gm' will also be reversed (i.e from of R parallel gm') > o(*C parallel gm') to o('C' parallel gm')= > o( parallel gm')). However, when the reversed subgraph order affects the transformation from G to fG), we find that the gm, C, and R should be connected in parallel, which means that they formulate another subgraph 'gm parallel R parallel C' of larger size in the basis TB which means that the graphlizer I should choose subgraph 'gm parallel R parallel C' instead of decomposing it to smaller subgraphs. We also empirically evaluate the effect of domain specific total ordering of nodes on our dataset, and we find 0 of 10000 circuits G have different transformed graphs f(G) when we reverse the order of C and R.
B EXPRESSIVE ABILITY OF TWO-LEVEL GNN WITH A SUBGRAPH BSIS
Though various GNN models have been proposed, (Atwood & Towsley 2016 Verma & Zhang 2018; Niepert et al. 2016), most follow the message passing scheme (Gilmer et al. 2017). Message passing GNNs (MPGNNs) implicitly leverage the inductive bias in the graph topology by iteratively passing messages between each node and its neighbors to extract a node embedding that encodes the local substructure. The message passing scheme shows impressive graph representation learning ability to extract highly expressive features representing the local structure information in a graph. MPGNNs show close relationship with the WI. test, and (Xu et al. 2018) has proven that they
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most powerful as the WL test for distinguishing graph structures, which limits the expressive power of message passing GNNs. To improve the expressiveness of message passing GNNs, plug-and-play framework, NGNN (Zhang & Li 202I), is proposed to learn substructures where standard message passing scheme fails to discriminate. NGNN uses a two-level GNN framework that uses an inner GNN learn the representation of extracted subgraphs around each node embed the substructures, instead of rooted subtrees, thereby efficiently distinguishing almost all d-regular graphs.
Corollary B.1 By selecting proper subgraph basis and order function o, the expressiveness of the two-level GNN framework with subgraph basis B can be: 1) strictly more powerfil than message passing GNNs; 2) as powerful as nested GNN in distinguishing n-sized r-regular graphs.
When the subgraph basis contains all subgraphs of depth the two-level GNN with B equivalent to general message passing framework. If we add rooted subgraphs with height larger than 1, message passing in inner GNNs will be applied added rooted subgraphs to extract additional distance features (Li et al. 2020) to provide further distinction ability. On the other hand, when the subgraph basis contains all height-k: rooted subgraphs and the order function o defines a partial order dependent on the root node v, then the two-level GNN with subgraph basis IB is essentially NGNN framework.
The Corollary indicates that we can manipulate the subgraph basis to balance the trade-off between the complexity and the expressiveness of the two-level GNN framework. We leave the problem in the future to incorporate the subgraph selection progress into the end-to-end learning framework for the general graph learning tasks. In this work, we focus on the circuit (DAG) optimization problem, where the ordered subgraph basis is known, and we show that it can be used to reduce the (topology) search space size of the optimization problem.
C PROOF OF THEOREM 3.2
It's straightforward that the f can convert input DAG to some transformed DAGs Gj.... Gm basis B contains every of size 1. Then we can identify the unique f by following two rules:
(1) Then the output of f should minimize the number of nodes (subgraphs used in the basis BB) in the transformed graph G'. That is. f(G) = G = arg min |G/|-
(2) If there exists two transformed subgraphs G. and G' such that |c|| =IG] arg mign G = K, then both Gú and Gjj are represented as K subgraphs in basis IB. - We denote these K subgraphs as G',,, G'.g... G¹,x and G3 Gz.2.... Gj.K- then we can sort o(G o( o(G',k)
to provide G. ordered tuple t, of size K, and sort oGG),), ol o(G oGG to provide Gj, ordered tuple I of size K. Then the output of f is given by:
C' 4>4
f(G) =
G 4>4
where > denotes the lexicographical sorting operation.
The above rules ensure that the graphitized can injectively select subgraphs in the basis B to formulate the transformed DAG G' Then, since each subgraph in B only has single node one node to be the head (tail) of a directed edge whose tail (head) is outside the subgraph, the connections between subgraphs are uniquely dependent on the input DAG G. Furthermore, as connections between nodes within each subgraph in B are fixed, the order of nodes in input DAG is uniformly encoded in the transformed DAG G'.
D EXPERIMENT DETAILS AND ADDITIONAL RESULTS
Model Configurations In the experiment, message passing GNNs (i.e. GCN and GIN) contain 3 graph convolution layers and use mean pooling read out graph-level representation. NGNN uses rooted subgraph height h = 3 and takes GIN with / = 3 layers as the base GNN. In Transformer- based models (i.e., Graphormer and PACH), the number of Transformer encoder layers is 5 and it.
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V/8
VB
nm
V up
Vun
1p
V8
-4
FoM 33.436447
FoM -33.274162
Encoder: CkGGNN
Encoder: PACE & DAGNN
Figure 8: Exemplary optimal circuits detected by Bayesian Optimization.
plays multi-hee heali- attention with 6 heads. DAGNN uses two-layer directed graph convolutions. We implement experiments on 12G TeslaP100 and GeForce GTX 1080 Ti, and 5 independent trials are implemented when the mean and standard deviation reported.
Bayesian Optinization Results In the experiment, we take the Bayesian optimization Approach and optimize the FoM score the (latent) vectorial space generated by the DAG encoder. Figure illustrates the results. Optimization on the latent space by CkIGNN yields a circuit with the largest FoM score than competitive DAG encoders (or GNN for undirected graphs).
E MORE DETAILS ABOUT TRAINING AND EVALUATION
Training Methodology The proposed CkIGNN can be trained in a supervised fashion, in the VAE framework. When trained with supervised learning, the loss function is formulated with the target value and the output representation of CkIGNN. On the other hand, CkıGNN can also be trained in a VAE framework such as D- D-VA,, DAGNN, and PACE. In the VAE architecture, we take CkIGNN as the DAG encoder. Two fully connected (FC) layers take the output representation of CkiGNN as inputs to predict the mean and variance of the approximated posterior distribution in the evidence lower bound (ELBO) (Kingma Welling 2013). The decoder is formulated as the decoder of D-VEE to generate transformed DAGs from the latent space. That is, the decoder uses the same undirected message passing CktGNN to learn intermediate node and graph states z./ For the zth generated node vi in G', MLPs are used predict the subgraph type in the basis and the existence of directed edges (u). v2)) for vi E G' = 1, ...,, 1. In addition, given the predicted subgraph type, the topology within the subgraph is known. Therefore, the decoder only needs to use MLPs to predict the node features within the subgraph based on the current graph state 2./-
In the training methodology, reconstruction loss + a KL. divergence, where a set to be 0.005 as prior works (i.e. Grammer variational autoencoder Kusner al. (2017). D-VAE, PACE). the training process, we perform mini-batch stochastic gradient descent with batch size of 64. We train models for 200 epochs. The initial learning rate set as IB-4, and we use schedule to modulate the changes of the learning rate over time such that the learning rate will shrink by a factor of 0.1 if the training loss is not decreased for 20 epochs.
resort VAE architecture, and the VAE loss is formulated as
When evaluating the circuit design ability in section 5.4 we use two metrics: Valid circuits and Novel circuits, to measure the circuit design (generation) effectiveness. To calculate these values, we randomly sample 1000 random points in the latent vectorial space from a (prior) standard normal distribution, and decode each point for 10 times. Then we compute the proportion valid circuits and novel circuits not seen in the training sets. A generated circuit is valid if it satisfies following three criteria: (1) It has only one input node and one output node; (2) The generated circuit (directed graph) is DAG (i.e. there is cycle); (3) In the main path, there no R node nor C node. The last criterion is consistent with the design rules operational amplifiers (Op-Amps), and more details are available in the Appendix A
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Published as a conference paper at ICLR 2023
F MORE DETAILS ABOUT DECODER
Basically, the decoder is also based on the CkIGNN framework where the GRU-based directed message passing (introduced in D-VAE) is used the outer GNN. Given point in the latent vectorial space, an MLP is used to map 2 to ho as the initial hidden state. Next, the decoder constructs the circuits subgraph by subgraph, where subgraphs are from the known subgraph basis B. Specifically, for the ith subgraph 2/, we use an MLP sabb (h= to compute the subgraph type
distribution, and sample the subgraph type v.. Then we can update the hidden state representation bej using the CkIGNN framework based current circuit (DAG). Given the predicted subgraph
type, the topology within the subgraph is known, thus the decoder only needs to use MLPs to predict the node features within the subgraph based on hu.... In the end, for previous subgraph 1/ such that
j < i, we use an MLP Sedge (huj; h:;))
to predict the probability of connection between uj and vj.
These steps are repeated until the generated subgraph type is an output type.
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Reviews:
[{"review_id": "c44MfcvZaq", "reviewer": "Reviewer_nGNe", "summary": "", "questions": "", "limitations": "", "rating": 6, "confidence": 2, "soundness": null, "presentation": null, "contribution": null, "strengths": "", "weaknesses": "", "quality": null, "clarity": null, "significance": null, "originality": null, "strengths_and_weaknesses": "", "was_revised": false, "final_justification": "", "rebuttal": "", "claims_and_evidence": "", "methods_and_evaluation_criteria": "", "theoretical_claims": "", "experimental_designs_or_analyses": "", "relation_to_broader_scientific_literature": "", "essential_references_not_discussed": "", "other_strengths_and_weaknesses": "", "other_comments_or_suggestions": "", "questions_for_authors": "", "summary_of_paper": "", "summary_of_recommendation": "", "technical_quality": "", "clarity_of_presentation": "", "potential_impact": "", "robotics_focus": "", "quality_of_limitations": "", "questions_for_rebuttal": "", "reasons_to_accept": "", "reasons_to_reject": "", "questions_to_authors": "", "main_review": "", "summary_of_the_paper": "This work proposes a Graph Neural Network (CktGNN) to automate the design for both the device parameters (device sizing) and the circuit topology.\nFurthermore, the paper also proposes an open source dataset, Open Circuit Benchmark (OCB), which consists of 10k operational amplifiers with detailed circuit specifications. \n\nThe proposed CktGNN, shows promising results in three different domain: \n- the ability to predict the graph properties (i.e., Gain, BW, PM, FoM)\n- Circuit encoding efficiency (training/inference time)\n- new circuit generation\n", "summary_of_the_review": "As mentioned before, this paper does not fall into my area of expertise. Hence, my decision is going to heavily rely on other reviewers' evaluation. ", "strength_and_weaknesses": "Strength: \n- Paper is well written and easy to follow\n- The idea to simultaneously automate the circuit topology generation and device sizing is novel.\n\nWeaknesses:\n\nAdmittedly, this paper does not fall into my area of expertise. So I cannot write a proper critical review. Though, I have several questions regarding the statements in the paper:\n\n- In the paper it says: \"previous work, inherently fail to optimize the circuit topology\". This claim needs justification which I could not find in the paper. \n- In the paper it says: \"However, these methods often lead to the generation of many useless circuit topologies\". Again, This claim is provided with no justification.\n- Regarding the OCB dataset, who has designed the 10k operational amplifiers? Basically, the question is: where do they come from?\n- In the paper it says: \"We also find that CktGNN can achieve the highest novelty in the generation process\". However, in Table 2, CktGNN  is not the one with the highest novelty score! \n- There are some spelling errors in the text\n", "limitations_and_societal_impact": "", "review_text": "", "extra_scores": {"correctness": "3: Some of the paper’s claims have minor issues. A few statements are not well-supported, or require small changes to be made correct.", "technical_novelty_and_significance": "4: The contributions are significant, and do not exist in prior works.", "empirical_novelty_and_significance": "4: The contributions are significant, and do not exist in prior works."}, "extra_text": {}}, {"review_id": "UDot14DzzQ", "reviewer": "Reviewer_uYkn", "summary": "", "questions": "", "limitations": "", "rating": 6, "confidence": 3, "soundness": null, "presentation": null, "contribution": null, "strengths": "", "weaknesses": "", "quality": null, "clarity": null, "significance": null, "originality": null, "strengths_and_weaknesses": "", "was_revised": false, "final_justification": "", "rebuttal": "", "claims_and_evidence": "", "methods_and_evaluation_criteria": "", "theoretical_claims": "", "experimental_designs_or_analyses": "", "relation_to_broader_scientific_literature": "", "essential_references_not_discussed": "", "other_strengths_and_weaknesses": "", "other_comments_or_suggestions": "", "questions_for_authors": "", "summary_of_paper": "", "summary_of_recommendation": "", "technical_quality": "", "clarity_of_presentation": "", "potential_impact": "", "robotics_focus": "", "quality_of_limitations": "", "questions_for_rebuttal": "", "reasons_to_accept": "", "reasons_to_reject": "", "questions_to_authors": "", "main_review": "", "summary_of_the_paper": "This paper designs a circuit GNN (CktGNN) to facilitate the learning of circuit graphs and electronic design automation. CktGNN is a generation of the nested GNN structure to DAGs. The paper also presents a circuit benchmark dataset OCB with open-source code for automated circuit design methods evaluation.", "summary_of_the_review": "The benchmark dataset provided has an unneglectable contribution to the field. However, the method itself doesn't offer much novelty. It's barely an application of the nested GNN.", "strength_and_weaknesses": "Strength:\n1. The benchmark dataset has an empirical contribution to the field.\n2. CktGNN is empirically proven to achieve SOTA performance.\n\nWeakness:\n1. The discussion on the decoder (circuit design/generation) is too little.\n2. The method is an incremental development upon the nested GNN.\n3. The figures are hard to read due to the font size.\n4. The ability to design circuits automatically is not evaluated adequately in the experiments.", "limitations_and_societal_impact": "", "review_text": "", "extra_scores": {"correctness": "3: Some of the paper’s claims have minor issues. A few statements are not well-supported, or require small changes to be made correct.", "technical_novelty_and_significance": "2: The contributions are only marginally significant or novel.", "empirical_novelty_and_significance": "4: The contributions are significant, and do not exist in prior works."}, "extra_text": {}}, {"review_id": "OS0x4YW2l-", "reviewer": "Reviewer_ESXP", "summary": "", "questions": "", "limitations": "", "rating": 8, "confidence": 4, "soundness": null, "presentation": null, "contribution": null, "strengths": "", "weaknesses": "", "quality": null, "clarity": null, "significance": null, "originality": null, "strengths_and_weaknesses": "", "was_revised": false, "final_justification": "", "rebuttal": "", "claims_and_evidence": "", "methods_and_evaluation_criteria": "", "theoretical_claims": "", "experimental_designs_or_analyses": "", "relation_to_broader_scientific_literature": "", "essential_references_not_discussed": "", "other_strengths_and_weaknesses": "", "other_comments_or_suggestions": "", "questions_for_authors": "", "summary_of_paper": "", "summary_of_recommendation": "", "technical_quality": "", "clarity_of_presentation": "", "potential_impact": "", "robotics_focus": "", "quality_of_limitations": "", "questions_for_rebuttal": "", "reasons_to_accept": "", "reasons_to_reject": "", "questions_to_authors": "", "main_review": "", "summary_of_the_paper": "The paper presents a modification of the NGNN framework of Zhang & Li which uses the embeddings of subgraphs around each node as node embeddings for an outer global message passing loop to DAGs (by defining a total ordering of possible subgraphs and  selecting the largest for each node) in order to apply the architecture to EDA tasks. The expressiveness of the architecture is analysed showing that the method is more expressive than standard MPGNNs and a new dataset is proposed on which the method and related work are evaluated.\n\nContributions:\n\n1. domain knowledge dependent subgraph extraction for DAGs to extend NGNN\n2. expressivty analysis\n3. dataset + generation codes\n4. empirical evaluation", "summary_of_the_review": "Overall this is a fine paper. I would not call it ground breaking, but the dataset + code generation takes considerate amount of work to accomplish and will be valuable for the community, the method improves on prior art (not a lot but noticably) and the modification is well justified and analysed.", "strength_and_weaknesses": "Strengths:\n\n- the paper is well written and easy to understand\n- the architecture achieves decent gains against most competing models\n- the architecture should be useful for other DAG centric tasks as well\n\nWeaknesses\n\n- an author claim that this is the \"first open source dataset for analog eda\" should be made more nuanced, given the existence of e.g. https://arxiv.org/abs/2208.01040 and https://arxiv.org/abs/2203.15913 and their accompanying datasets\n- the method relies on domain specific total ordering which needs to be handcrafted, similar to the node ordering methods used by GraphRNN and GRAN. The relation and impact of these should maybe be discussed, and if there is time, and ablation over the sensitivity towards ordering choice (e.g.  setting o(C)>o(R))  would strengthen the paper\n- either I missed them or the experimental details (optimiser choice, number of seeds etc) are missing and should be added, although they are in the supplementary code", "limitations_and_societal_impact": "", "review_text": "", "extra_scores": {"correctness": "3: Some of the paper’s claims have minor issues. A few statements are not well-supported, or require small changes to be made correct.", "technical_novelty_and_significance": "3: The contributions are significant and somewhat new. Aspects of the contributions exist in prior work.", "empirical_novelty_and_significance": "3: The contributions are significant and somewhat new. Aspects of the contributions exist in prior work."}, "extra_text": {}}, {"review_id": "0ztzqxKYn58", "reviewer": "Reviewer_F1jP", "summary": "", "questions": "", "limitations": "", "rating": 6, "confidence": 5, "soundness": null, "presentation": null, "contribution": null, "strengths": "", "weaknesses": "", "quality": null, "clarity": null, "significance": null, "originality": null, "strengths_and_weaknesses": "", "was_revised": false, "final_justification": "", "rebuttal": "", "claims_and_evidence": "", "methods_and_evaluation_criteria": "", "theoretical_claims": "", "experimental_designs_or_analyses": "", "relation_to_broader_scientific_literature": "", "essential_references_not_discussed": "", "other_strengths_and_weaknesses": "", "other_comments_or_suggestions": "", "questions_for_authors": "", "summary_of_paper": "", "summary_of_recommendation": "", "technical_quality": "", "clarity_of_presentation": "", "potential_impact": "", "robotics_focus": "", "quality_of_limitations": "", "questions_for_rebuttal": "", "reasons_to_accept": "", "reasons_to_reject": "", "questions_to_authors": "", "main_review": "", "summary_of_the_paper": "The paper studies the problem of representation learning of the analog circuit. It propose a two-level GNN model, in which the outer graph is composed with multiple non overlapping subgraphs. The representation can be used to perform different tasks. Then it also present a dataset called Open Circuit Benchmark which contains 10K OpAmp to benefit future projects.", "summary_of_the_review": "A new representation learning for analog circuit which leverages human knowledge to construct the high level graph with low level subgraphs. A circuit dataset is released containing 10K Opamp circuits.\n\nThanks for the response. I would like to increase the score to 8 and i would encourage the authors to add more circuit to the dataset. ", "strength_and_weaknesses": "Strength:\nThe two-level GNN is natural for the analog circuit problem as the circuit needs to be constructed with some basic blocks instead of random circuit components.\nThe proposed benchmark is important for future study in this field\n\nWeakness:\nThe OCB dataset only contains the operational amplifiers, though Opamp is a widely used units, it would be good to include other important circuit such as LDO, comparators, etc.\nIt is unclear that whether the two-level circuit representation can be used to other circuit since the subgraph basis may not be generally applied to all kinds of circuit.\n\nComments:\nHow can this method benefit the layout design of analog circuits? is that possible to design a layout for each subgraph basis?\n\n", "limitations_and_societal_impact": "", "review_text": "", "extra_scores": {"correctness": "4: All of the claims and statements are well-supported and correct.", "technical_novelty_and_significance": "3: The contributions are significant and somewhat new. Aspects of the contributions exist in prior work.", "empirical_novelty_and_significance": "3: The contributions are significant and somewhat new. Aspects of the contributions exist in prior work."}, "extra_text": {}}]

Author rebuttal:

Decision: Accept: poster