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  <title>MINSD—Return Minimum Scalar Double-Precision Floating-Point Value </title></head>
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  <h1>MINSD—Return Minimum Scalar Double-Precision Floating-Point Value</h1>
  <table>
  <tr>
  <th>Opcode/Instruction</th>
  <th>Op/En</th>
  <th>64/32-bit Mode</th>
  <th>CPUID Feature Flag</th>
  <th>Description</th></tr>
  <tr>
  <td>
  <p>F2 0F 5D /<em>r</em></p>
  <p>MINSD <em>xmm1</em>, <em>xmm2/m64</em></p></td>
  <td>RM</td>
  <td>V/V</td>
  <td>SSE2</td>
  <td>Return the minimum scalar double-precision floating-point value between <em>xmm2/mem64 </em>and<em> xmm1</em>.</td></tr>
  <tr>
  <td>
  <p>VEX.NDS.LIG.F2.0F.WIG 5D /r</p>
  <p>VMINSD <em>xmm1, xmm2, xmm3/m64</em></p></td>
  <td>RVM</td>
  <td>V/V</td>
  <td>AVX</td>
  <td>Return the minimum scalar double precision floating-point value between <em>xmm3/mem64 </em>and <em>xmm2</em>.</td></tr></table>
  <h3>Instruction Operand Encoding</h3>
  <table>
  <tr>
  <td>Op/En</td>
  <td>Operand 1</td>
  <td>Operand 2</td>
  <td>Operand 3</td>
  <td>Operand 4</td></tr>
  <tr>
  <td>RM</td>
  <td>ModRM:reg (r, w)</td>
  <td>ModRM:r/m (r)</td>
  <td>NA</td>
  <td>NA</td></tr>
  <tr>
  <td>RVM</td>
  <td>ModRM:reg (w)</td>
  <td>VEX.vvvv (r)</td>
  <td>ModRM:r/m (r)</td>
  <td>NA</td></tr></table>
  <h2>Description</h2>
  <p>Compares the low double-precision floating-point values in the first source operand and the second source operand, and returns the minimum value to the low quadword of the destination operand. When the source operand is a memory operand, only the 64 bits are accessed. The high quadword of the destination operand is copied from the same bits in the first source operand.</p>
  <p>If the values being compared are both 0.0s (of either sign), the value in the second source operand is returned. If a value in the second source operand is an SNaN, that SNaN is returned unchanged to the destination (that is, a QNaN version of the SNaN is not returned).</p>
  <p>If only one value is a NaN (SNaN or QNaN) for this instruction, the second source operand, either a NaN or a valid floating-point value, is written to the result. If instead of this behavior, it is required that the NaN source operand (from either the first or second source) be returned, the action of MINSD can be emulated using a sequence of instructions, such as, a comparison followed by AND, ANDN and OR.</p>
  <p>The second source operand can be an XMM register or a 64-bit memory location. The first source and destination operands are XMM registers.</p>
  <p>In 64-bit mode, use of the REX.R prefix permits this instruction to access additional registers (XMM8-XMM15).</p>
  <p>128-bit Legacy SSE version: The destination and first source operand are the same. Bits (VLMAX-1:64) of the corresponding YMM destination register remain unchanged.</p>
  <p>VEX.128 encoded version: Bits (127:64) of the XMM register destination are copied from corresponding bits in the first source operand. Bits (VLMAX-1:128) of the destination YMM register are zeroed.</p>
  <h2>Operation</h2>
  <p><strong>MIN(SRC1, SRC2)</strong></p>
  <pre>{
      IF ((SRC1 = 0.0) and (SRC2 = 0.0)) THEN DEST ← SRC2;
           ELSE IF (SRC1 = SNaN) THEN DEST ← SRC2; FI;
           ELSE IF SRC2 = SNaN) THEN DEST ← SRC2; FI;
           ELSE IF (SRC1 &lt; SRC2) THEN DEST ← SRC1;
           ELSE DEST ← SRC2;
      FI;
  }</pre>
  <p><strong>MINSD (128-bit Legacy SSE version)</strong></p>
  <pre>DEST[63:0] ← MIN(SRC1[63:0], SRC2[63:0])
  DEST[VLMAX-1:64] (Unmodified)</pre>
  <p><strong>MINSD (VEX.128 encoded version)</strong></p>
  <pre>DEST[63:0] ← MIN(SRC1[63:0], SRC2[63:0])
  DEST[127:64] ← SRC1[127:64]
  DEST[VLMAX-1:128] ← 0</pre>
  <h2>Intel C/C++ Compiler Intrinsic Equivalent</h2>
  <p>MINSD:</p>
  <p> __m128d _mm_min_sd(__m128d a, __m128d b)</p>
  <h2>SIMD Floating-Point Exceptions</h2>
  <p>Invalid (including QNaN source operand), Denormal.</p>
  <h2>Other Exceptions</h2>
  <p>See Exceptions Type 3.</p></body></html>