text: .nh
  .TH "X86-VFMADDSUB132PD-VFMADDSUB213PD-VFMADDSUB231PD" "7" "May 2019" "TTMO" "Intel x86-64 ISA Manual"
  .SH NAME
  VFMADDSUB132PD-VFMADDSUB213PD-VFMADDSUB231PD - FUSED MULTIPLY-ALTERNATING ADD-SUBTRACT OF PACKED DOUBLE-PRECISION FLOATING-POINT VALUES
  .TS
  allbox;
  l l l l l 
  l l l l l .
  \fB\fCOpcode/Instruction\fR	\fB\fCOp/En\fR	\fB\fC64/32 bit Mode Support\fR	\fB\fCCPUID Feature Flag\fR	\fB\fCDescription\fR
  T{
  VEX.128.66.0F38.W1 96 /r VFMADDSUB132PD xmm1, xmm2, xmm3/m128
  T}
  	A	V/V	FMA	T{
  Multiply packed double\-precision floating\-point values from xmm1 and xmm3/mem, add/subtract elements in xmm2 and put result in xmm1.
  T}
  T{
  VEX.128.66.0F38.W1 A6 /r VFMADDSUB213PD xmm1, xmm2, xmm3/m128
  T}
  	A	V/V	FMA	T{
  Multiply packed double\-precision floating\-point values from xmm1 and xmm2, add/subtract elements in xmm3/mem and put result in xmm1.
  T}
  T{
  VEX.128.66.0F38.W1 B6 /r VFMADDSUB231PD xmm1, xmm2, xmm3/m128
  T}
  	A	V/V	FMA	T{
  Multiply packed double\-precision floating\-point values from xmm2 and xmm3/mem, add/subtract elements in xmm1 and put result in xmm1.
  T}
  T{
  VEX.256.66.0F38.W1 96 /r VFMADDSUB132PD ymm1, ymm2, ymm3/m256
  T}
  	A	V/V	FMA	T{
  Multiply packed double\-precision floating\-point values from ymm1 and ymm3/mem, add/subtract elements in ymm2 and put result in ymm1.
  T}
  T{
  VEX.256.66.0F38.W1 A6 /r VFMADDSUB213PD ymm1, ymm2, ymm3/m256
  T}
  	A	V/V	FMA	T{
  Multiply packed double\-precision floating\-point values from ymm1 and ymm2, add/subtract elements in ymm3/mem and put result in ymm1.
  T}
  T{
  VEX.256.66.0F38.W1 B6 /r VFMADDSUB231PD ymm1, ymm2, ymm3/m256
  T}
  	A	V/V	FMA	T{
  Multiply packed double\-precision floating\-point values from ymm2 and ymm3/mem, add/subtract elements in ymm1 and put result in ymm1.
  T}
  T{
  EVEX.128.66.0F38.W1 A6 /r VFMADDSUB213PD xmm1 {k1}{z}, xmm2, xmm3/m128/m64bcst
  T}
  	B	V/V	AVX512VL AVX512F	T{
  Multiply packed double\-precision floating\-point values from xmm1 and xmm2, add/subtract elements in xmm3/m128/m64bcst and put result in xmm1 subject to writemask k1.
  T}
  T{
  EVEX.128.66.0F38.W1 B6 /r VFMADDSUB231PD xmm1 {k1}{z}, xmm2, xmm3/m128/m64bcst
  T}
  	B	V/V	AVX512VL AVX512F	T{
  Multiply packed double\-precision floating\-point values from xmm2 and xmm3/m128/m64bcst, add/subtract elements in xmm1 and put result in xmm1 subject to writemask k1.
  T}
  T{
  EVEX.128.66.0F38.W1 96 /r VFMADDSUB132PD xmm1 {k1}{z}, xmm2, xmm3/m128/m64bcst
  T}
  	B	V/V	AVX512VL AVX512F	T{
  Multiply packed double\-precision floating\-point values from xmm1 and xmm3/m128/m64bcst, add/subtract elements in xmm2 and put result in xmm1 subject to writemask k1.
  T}
  T{
  EVEX.256.66.0F38.W1 A6 /r VFMADDSUB213PD ymm1 {k1}{z}, ymm2, ymm3/m256/m64bcst
  T}
  	B	V/V	AVX512VL AVX512F	T{
  Multiply packed double\-precision floating\-point values from ymm1 and ymm2, add/subtract elements in ymm3/m256/m64bcst and put result in ymm1 subject to writemask k1.
  T}
  T{
  EVEX.256.66.0F38.W1 B6 /r VFMADDSUB231PD ymm1 {k1}{z}, ymm2, ymm3/m256/m64bcst
  T}
  	B	V/V	AVX512VL AVX512F	T{
  Multiply packed double\-precision floating\-point values from ymm2 and ymm3/m256/m64bcst, add/subtract elements in ymm1 and put result in ymm1 subject to writemask k1.
  T}
  T{
  EVEX.256.66.0F38.W1 96 /r VFMADDSUB132PD ymm1 {k1}{z}, ymm2, ymm3/m256/m64bcst
  T}
  	B	V/V	AVX512VL AVX512F	T{
  Multiply packed double\-precision floating\-point values from ymm1 and ymm3/m256/m64bcst, add/subtract elements in ymm2 and put result in ymm1 subject to writemask k1.
  T}
  T{
  EVEX.512.66.0F38.W1 A6 /r VFMADDSUB213PD zmm1 {k1}{z}, zmm2, zmm3/m512/m64bcst{er}
  T}
  	B	V/V	AVX512F	T{
  Multiply packed double\-precision floating\-point values from zmm1and zmm2, add/subtract elements in zmm3/m512/m64bcst and put result in zmm1 subject to writemask k1.
  T}
  T{
  EVEX.512.66.0F38.W1 B6 /r VFMADDSUB231PD zmm1 {k1}{z}, zmm2, zmm3/m512/m64bcst{er}
  T}
  	B	V/V	AVX512F	T{
  Multiply packed double\-precision floating\-point values from zmm2 and zmm3/m512/m64bcst, add/subtract elements in zmm1 and put result in zmm1 subject to writemask k1.
  T}
  T{
  EVEX.512.66.0F38.W1 96 /r VFMADDSUB132PD zmm1 {k1}{z}, zmm2, zmm3/m512/m64bcst{er}
  T}
  	B	V/V	AVX512F	T{
  Multiply packed double\-precision floating\-point values from zmm1 and zmm3/m512/m64bcst, add/subtract elements in zmm2 and put result in zmm1 subject to writemask k1.
  T}
  .TE
  
  .SH INSTRUCTION OPERAND ENCODING
  .TS
  allbox;
  l l l l l l 
  l l l l l l .
  Op/En	Tuple Type	Operand 1	Operand 2	Operand 3	Operand 4
  A	NA	ModRM:reg (r, w)	VEX.vvvv (r)	ModRM:r/m (r)	NA
  B	Full	ModRM:reg (r, w)	EVEX.vvvv (r)	ModRM:r/m (r)	NA
  .TE
  
  .SS Description
  .PP
  VFMADDSUB132PD: Multiplies the two, four, or eight packed
  double\-precision floating\-point values from the first source operand to
  the two or four packed double\-precision floating\-point values in the
  third source operand. From the infinite precision intermediate result,
  adds the odd double\-precision floating\-point elements and subtracts the
  even double\-precision floating\-point values in the second source
  operand, performs rounding and stores the resulting two or four packed
  double\-precision floating\-point values to the destination operand (first
  source operand).
  
  .PP
  VFMADDSUB213PD: Multiplies the two, four, or eight packed
  double\-precision floating\-point values from the second source operand to
  the two or four packed double\-precision floating\-point values in the
  first source operand. From the infinite precision intermediate result,
  adds the odd double\-precision floating\-point elements and subtracts the
  even double\-precision floating\-point values in the third source operand,
  performs rounding and stores the resulting two or four packed
  double\-precision floating\-point values to the destination operand (first
  source operand).
  
  .PP
  VFMADDSUB231PD: Multiplies the two, four, or eight packed
  double\-precision floating\-point values from the second source operand to
  the two or four packed double\-precision floating\-point values in the
  third source operand. From the infinite precision intermediate result,
  adds the odd double\-precision floating\-point elements and subtracts the
  even double\-precision floating\-point values in the first source operand,
  performs rounding and stores the resulting two or four packed
  double\-precision floating\-point values to the destination operand (first
  source operand).
  
  .PP
  EVEX encoded versions: The destination operand (also first source
  operand) and the second source operand are ZMM/YMM/XMM register. The
  third source operand is a ZMM/YMM/XMM register, a 512/256/128\-bit memory
  location or a 512/256/128\-bit vector broadcasted from a 64\-bit memory
  location. The destination operand is conditionally updated with write
  mask k1.
  
  .PP
  VEX.256 encoded version: The destination operand (also first source
  operand) is a YMM register and encoded in reg\_field. The second source
  operand is a YMM register and encoded in VEX.vvvv. The third source
  operand is a YMM register or a 256\-bit memory location and encoded in
  rm\_field.
  
  .PP
  VEX.128 encoded version: The destination operand (also first source
  operand) is a XMM register and encoded in reg\_field. The second source
  operand is a XMM register and encoded in VEX.vvvv. The third source
  operand is a XMM register or a 128\-bit memory location and encoded in
  rm\_field. The upper 128 bits of the YMM destination register are
  zeroed.
  
  .PP
  Compiler tools may optionally support a complementary mnemonic for each
  instruction mnemonic listed in the opcode/instruction column of the
  summary table. The behavior of the complementary mnemonic in situations
  involving NANs are governed by the definition of the instruction
  mnemonic defined in the opcode/instruction column.
  
  .SS Operation
  .PP
  .RS
  
  .nf
  In the operations below, “*” and “\-” symbols represent multiplication and subtraction with infinite precision inputs and outputs (no
  rounding).
  
  .fi
  .RE
  
  .SS VFMADDSUB132PD DEST, SRC2, SRC3
  .PP
  .RS
  
  .nf
  IF (VEX.128) THEN
      DEST[63:0]←RoundFPControl\_MXCSR(DEST[63:0]*SRC3[63:0] \- SRC2[63:0])
      DEST[127:64]←RoundFPControl\_MXCSR(DEST[127:64]*SRC3[127:64] + SRC2[127:64])
      DEST[MAXVL\-1:128] ←0
  ELSEIF (VEX.256)
      DEST[63:0]←RoundFPControl\_MXCSR(DEST[63:0]*SRC3[63:0] \- SRC2[63:0])
      DEST[127:64]←RoundFPControl\_MXCSR(DEST[127:64]*SRC3[127:64] + SRC2[127:64])
      DEST[191:128]←RoundFPControl\_MXCSR(DEST[191:128]*SRC3[191:128] \- SRC2[191:128])
      DEST[255:192]←RoundFPControl\_MXCSR(DEST[255:192]*SRC3[255:192] + SRC2[255:192]
  FI
  
  .fi
  .RE
  
  .SS VFMADDSUB213PD DEST, SRC2, SRC3
  .PP
  .RS
  
  .nf
  IF (VEX.128) THEN
      DEST[63:0]←RoundFPControl\_MXCSR(SRC2[63:0]*DEST[63:0] \- SRC3[63:0])
      DEST[127:64]←RoundFPControl\_MXCSR(SRC2[127:64]*DEST[127:64] + SRC3[127:64])
      DEST[MAXVL\-1:128] ←0
  ELSEIF (VEX.256)
      DEST[63:0]←RoundFPControl\_MXCSR(SRC2[63:0]*DEST[63:0] \- SRC3[63:0])
      DEST[127:64]←RoundFPControl\_MXCSR(SRC2[127:64]*DEST[127:64] + SRC3[127:64])
      DEST[191:128]←RoundFPControl\_MXCSR(SRC2[191:128]*DEST[191:128] \- SRC3[191:128])
      DEST[255:192]←RoundFPControl\_MXCSR(SRC2[255:192]*DEST[255:192] + SRC3[255:192]
  FI
  
  .fi
  .RE
  
  .SS VFMADDSUB231PD DEST, SRC2, SRC3
  .PP
  .RS
  
  .nf
  IF (VEX.128) THEN
      DEST[63:0]←RoundFPControl\_MXCSR(SRC2[63:0]*SRC3[63:0] \- DEST[63:0])
      DEST[127:64]←RoundFPControl\_MXCSR(SRC2[127:64]*SRC3[127:64] + DEST[127:64])
      DEST[MAXVL\-1:128] ←0
  ELSEIF (VEX.256)
      DEST[63:0]←RoundFPControl\_MXCSR(SRC2[63:0]*SRC3[63:0] \- DEST[63:0])
      DEST[127:64]←RoundFPControl\_MXCSR(SRC2[127:64]*SRC3[127:64] + DEST[127:64])
      DEST[191:128]←RoundFPControl\_MXCSR(SRC2[191:128]*SRC3[191:128] \- DEST[191:128])
      DEST[255:192]←RoundFPControl\_MXCSR(SRC2[255:192]*SRC3[255:192] + DEST[255:192]
  FI
  
  .fi
  .RE
  
  .SS VFMADDSUB132PD DEST, SRC2, SRC3 (EVEX encoded version, when src3 operand is a register)
  .PP
  .RS
  
  .nf
  (KL, VL) = (2, 128), (4, 256), (8, 512)
  IF (VL = 512) AND (EVEX.b = 1)
      THEN
          SET\_RM(EVEX.RC);
      ELSE
          SET\_RM(MXCSR.RM);
  FI;
  FOR j←0 TO KL\-1
      i←j * 64
      IF k1[j] OR *no writemask*
          THEN
              IF j *is even*
                  THEN DEST[i+63:i]←
                      RoundFPControl(DEST[i+63:i]*SRC3[i+63:i] \- SRC2[i+63:i])
                  ELSE DEST[i+63:i]←
                      RoundFPControl(DEST[i+63:i]*SRC3[i+63:i] + SRC2[i+63:i])
              FI
          ELSE
              IF *merging\-masking* ; merging\-masking
                  THEN *DEST[i+63:i] remains unchanged*
                  ELSE ; zeroing\-masking
                      DEST[i+63:i] ← 0
              FI
      FI;
  ENDFOR
  DEST[MAXVL\-1:VL] ← 0
  
  .fi
  .RE
  
  .SS VFMADDSUB132PD DEST, SRC2, SRC3 (EVEX encoded version, when src3 operand is a memory source)
  .PP
  .RS
  
  .nf
  (KL, VL) = (2, 128), (4, 256), (8, 512)
  FOR j←0 TO KL\-1
      i←j * 64
      IF k1[j] OR *no writemask*
          THEN
              IF j *is even*
                  THEN
                      IF (EVEX.b = 1)
                          THEN
                              DEST[i+63:i] ←
                      RoundFPControl\_MXCSR(DEST[i+63:i]*SRC3[63:0] \- SRC2[i+63:i])
                          ELSE
                              DEST[i+63:i] ←
                      RoundFPControl\_MXCSR(DEST[i+63:i]*SRC3[i+63:i] \- SRC2[i+63:i])
                  FI;
                  ELSE
                      IF (EVEX.b = 1)
                          THEN
                              DEST[i+63:i] ←
                      RoundFPControl\_MXCSR(DEST[i+63:i]*SRC3[63:0] + SRC2[i+63:i])
                          ELSE
                              DEST[i+63:i] ←
                      RoundFPControl\_MXCSR(DEST[i+63:i]*SRC3[i+63:i] + SRC2[i+63:i])
                  FI;
              FI
          ELSE
              IF *merging\-masking* ; merging\-masking
                  THEN *DEST[i+63:i] remains unchanged*
                  ELSE ; zeroing\-masking
                      DEST[i+63:i] ← 0
              FI
      FI;
  ENDFOR
  DEST[MAXVL\-1:VL] ← 0
  
  .fi
  .RE
  
  .SS VFMADDSUB213PD DEST, SRC2, SRC3 (EVEX encoded version, when src3 operand is a register)
  .PP
  .RS
  
  .nf
  (KL, VL) = (2, 128), (4, 256), (8, 512)
  IF (VL = 512) AND (EVEX.b = 1)
      THEN
          SET\_RM(EVEX.RC);
      ELSE
          SET\_RM(MXCSR.RM);
  FI;
  FOR j←0 TO KL\-1
      i←j * 64
      IF k1[j] OR *no writemask*
          THEN
              IF j *is even*
                  THEN DEST[i+63:i]←
                      RoundFPControl(SRC2[i+63:i]*DEST[i+63:i] \- SRC3[i+63:i])
                  ELSE DEST[i+63:i]←
                      RoundFPControl(SRC2[i+63:i]*DEST[i+63:i] + SRC3[i+63:i])
              FI
          ELSE
              IF *merging\-masking* ; merging\-masking
                  THEN *DEST[i+63:i] remains unchanged*
                  ELSE ; zeroing\-masking
                      DEST[i+63:i] ← 0
              FI
      FI;
  ENDFOR
  DEST[MAXVL\-1:VL] ← 0
  
  .fi
  .RE
  
  .SS VFMADDSUB213PD DEST, SRC2, SRC3 (EVEX encoded version, when src3 operand is a memory source)
  .PP
  .RS
  
  .nf
  (KL, VL) = (2, 128), (4, 256), (8, 512)
  FOR j←0 TO KL\-1
      i←j * 64
      IF k1[j] OR *no writemask*
          THEN
              IF j *is even*
                  THEN
                      IF (EVEX.b = 1)
                          THEN
                              DEST[i+63:i] ←
                      RoundFPControl\_MXCSR(SRC2[i+63:i]*DEST[i+63:i] \- SRC3[63:0])
                          ELSE
                              DEST[i+63:i] ←
                      RoundFPControl\_MXCSR(SRC2[i+63:i]*DEST[i+63:i] \- SRC3[i+63:i])
                      FI;
                  ELSE
                      IF (EVEX.b = 1)
                          THEN
                              DEST[i+63:i] ←
                      RoundFPControl\_MXCSR(SRC2[i+63:i]*DEST[i+63:i] + SRC3[63:0])
                          ELSE
                              DEST[i+63:i] ←
                      RoundFPControl\_MXCSR(SRC2[i+63:i]*DEST[i+63:i] + SRC3[i+63:i])
                      FI;
              FI
          ELSE
              IF *merging\-masking* ; merging\-masking
                  THEN *DEST[i+63:i] remains unchanged*
                  ELSE ; zeroing\-masking
                      DEST[i+63:i] ← 0
              FI
      FI;
  ENDFOR
  DEST[MAXVL\-1:VL] ← 0
  
  .fi
  .RE
  
  .SS VFMADDSUB231PD DEST, SRC2, SRC3 (EVEX encoded version, when src3 operand is a register)
  .PP
  .RS
  
  .nf
  (KL, VL) = (2, 128), (4, 256), (8, 512)
  IF (VL = 512) AND (EVEX.b = 1)
      THEN
          SET\_RM(EVEX.RC);
      ELSE
          SET\_RM(MXCSR.RM);
  FI;
  FOR j←0 TO KL\-1
      i←j * 64
      IF k1[j] OR *no writemask*
          THEN
              IF j *is even*
                  THEN DEST[i+63:i]←
                      RoundFPControl(SRC2[i+63:i]*SRC3[i+63:i] \- DEST[i+63:i])
                  ELSE DEST[i+63:i]←
                      RoundFPControl(SRC2[i+63:i]*SRC3[i+63:i] + DEST[i+63:i])
              FI
          ELSE
              IF *merging\-masking* ; merging\-masking
                  THEN *DEST[i+63:i] remains unchanged*
                  ELSE ; zeroing\-masking
                      DEST[i+63:i] ← 0
              FI
      FI;
  ENDFOR
  DEST[MAXVL\-1:VL] ← 0
  
  .fi
  .RE
  
  .SS VFMADDSUB231PD DEST, SRC2, SRC3 (EVEX encoded version, when src3 operand is a memory source)
  .PP
  .RS
  
  .nf
  (KL, VL) = (2, 128), (4, 256), (8, 512)
  FOR j←0 TO KL\-1
      i←j * 64
      IF k1[j] OR *no writemask*
          THEN
              IF j *is even*
                  THEN
                      IF (EVEX.b = 1)
                          THEN
                              DEST[i+63:i] ←
                          RoundFPControl\_MXCSR(SRC2[i+63:i]*SRC3[63:0] \- DEST[i+63:i])
                          ELSE
                              DEST[i+63:i] ←
                          RoundFPControl\_MXCSR(SRC2[i+63:i]*SRC3[i+63:i] \- DEST[i+63:i])
                      FI;
                  ELSE
                      IF (EVEX.b = 1)
                          THEN
                              DEST[i+63:i] ←
                          RoundFPControl\_MXCSR(SRC2[i+63:i]*SRC3[63:0] + DEST[i+63:i])
                          ELSE
                              DEST[i+63:i] ←
                          RoundFPControl\_MXCSR(SRC2[i+63:i]*SRC3[i+63:i] + DEST[i+63:i])
                      FI;
              FI
          ELSE
              IF *merging\-masking* ; merging\-masking
                  THEN *DEST[i+63:i] remains unchanged*
                  ELSE ; zeroing\-masking
                      DEST[i+63:i] ← 0
              FI
      FI;
  ENDFOR
  DEST[MAXVL\-1:VL] ← 0
  
  .fi
  .RE
  
  .SS Intel C/C++ Compiler Intrinsic Equivalent
  .PP
  .RS
  
  .nf
  VFMADDSUBxxxPD \_\_m512d \_mm512\_fmaddsub\_pd(\_\_m512d a, \_\_m512d b, \_\_m512d c);
  
  VFMADDSUBxxxPD \_\_m512d \_mm512\_fmaddsub\_round\_pd(\_\_m512d a, \_\_m512d b, \_\_m512d c, int r);
  
  VFMADDSUBxxxPD \_\_m512d \_mm512\_mask\_fmaddsub\_pd(\_\_m512d a, \_\_mmask8 k, \_\_m512d b, \_\_m512d c);
  
  VFMADDSUBxxxPD \_\_m512d \_mm512\_maskz\_fmaddsub\_pd(\_\_mmask8 k, \_\_m512d a, \_\_m512d b, \_\_m512d c);
  
  VFMADDSUBxxxPD \_\_m512d \_mm512\_mask3\_fmaddsub\_pd(\_\_m512d a, \_\_m512d b, \_\_m512d c, \_\_mmask8 k);
  
  VFMADDSUBxxxPD \_\_m512d \_mm512\_mask\_fmaddsub\_round\_pd(\_\_m512d a, \_\_mmask8 k, \_\_m512d b, \_\_m512d c, int r);
  
  VFMADDSUBxxxPD \_\_m512d \_mm512\_maskz\_fmaddsub\_round\_pd(\_\_mmask8 k, \_\_m512d a, \_\_m512d b, \_\_m512d c, int r);
  
  VFMADDSUBxxxPD \_\_m512d \_mm512\_mask3\_fmaddsub\_round\_pd(\_\_m512d a, \_\_m512d b, \_\_m512d c, \_\_mmask8 k, int r);
  
  VFMADDSUBxxxPD \_\_m256d \_mm256\_mask\_fmaddsub\_pd(\_\_m256d a, \_\_mmask8 k, \_\_m256d b, \_\_m256d c);
  
  VFMADDSUBxxxPD \_\_m256d \_mm256\_maskz\_fmaddsub\_pd(\_\_mmask8 k, \_\_m256d a, \_\_m256d b, \_\_m256d c);
  
  VFMADDSUBxxxPD \_\_m256d \_mm256\_mask3\_fmaddsub\_pd(\_\_m256d a, \_\_m256d b, \_\_m256d c, \_\_mmask8 k);
  
  VFMADDSUBxxxPD \_\_m128d \_mm\_mask\_fmaddsub\_pd(\_\_m128d a, \_\_mmask8 k, \_\_m128d b, \_\_m128d c);
  
  VFMADDSUBxxxPD \_\_m128d \_mm\_maskz\_fmaddsub\_pd(\_\_mmask8 k, \_\_m128d a, \_\_m128d b, \_\_m128d c);
  
  VFMADDSUBxxxPD \_\_m128d \_mm\_mask3\_fmaddsub\_pd(\_\_m128d a, \_\_m128d b, \_\_m128d c, \_\_mmask8 k);
  
  VFMADDSUBxxxPD \_\_m128d \_mm\_fmaddsub\_pd (\_\_m128d a, \_\_m128d b, \_\_m128d c);
  
  VFMADDSUBxxxPD \_\_m256d \_mm256\_fmaddsub\_pd (\_\_m256d a, \_\_m256d b, \_\_m256d c);
  
  .fi
  .RE
  
  .SS SIMD Floating\-Point Exceptions
  .PP
  Overflow, Underflow, Invalid, Precision, Denormal
  
  .SS Other Exceptions
  .PP
  VEX\-encoded instructions, see Exceptions Type 2.
  
  .PP
  EVEX\-encoded instructions, see Exceptions Type E2.
  
  .SH SEE ALSO
  .PP
  x86\-manpages(7) for a list of other x86\-64 man pages.
  
  .SH COLOPHON
  .PP
  This UNOFFICIAL, mechanically\-separated, non\-verified reference is
  provided for convenience, but it may be incomplete or broken in
  various obvious or non\-obvious ways. Refer to Intel® 64 and IA\-32
  Architectures Software Developer’s Manual for anything serious.
  
  .br
  This page is generated by scripts; therefore may contain visual or semantical bugs. Please report them (or better, fix them) on https://github.com/ttmo-O/x86-manpages.
  
  .br
  MIT licensed by TTMO 2020 (Turkish Unofficial Chamber of Reverse Engineers - https://ttmo.re).
  