text: `timescale 1ns / 1ps
  //////////////////////////////////////////////////////////////////////////////////
  // Company: Xilinx
  // Engineer: Parimal Patel
  // Module Name: pulse_gen
  // Project Name: 
  // Target Devices: 
  // Tool Versions: 
  // Description: This module takes multi-cycle pulse (generated by GPIO writes) and 
  //              outputs synchronized one clock wide pulse
  //////////////////////////////////////////////////////////////////////////////////
  
  
  module pulse_gen(
      input async_in,
      input sync_clk,
      output reg pulsed_out
      );
      
      reg edge_detect;
      always @(posedge async_in or posedge pulsed_out)
          if(pulsed_out)
              edge_detect <= 0;
          else
              edge_detect <= 1;
  
      always @(posedge sync_clk)
               pulsed_out <= edge_detect;
       
  endmodule
  