text: 
  ///////////////////////////////////////////////////////////
  ///////////////   Welcome to Cello   //////////////////////
  ///////////////////////////////////////////////////////////
  
  JobID by date: 0x68
  
  [ -dateID 0x68 -figures false -external_directory true -assignment_algorithm abstract_only  -verilog /Users/peng/cello/resources/verilog/3-input/0x68.v  -output_or false]
  
  ///////////////////////////////////////////////////////////
  ///////////////   Logic synthesis, Wiring diagram   ///////
  ///////////////////////////////////////////////////////////
  
  fin_ver /Users/peng/cello/resources/verilog/3-input/0x68.v
  Input gates  = 3
  Logic gates  = 8
    NOR gates  = 8
    AND gates  = 0
  Output gates = 1
  
  ----- Logic Circuit #0 -----
  OUTPUT      01101000          out               0  (1)         
  NOR         01101000          ~|                1  (3,2)       
  NOR         10010000          ~|                3  (4,9)       
  NOR         00010111          ~|                2  (4,5)       
  NOR         01100000          ~|                4  (6,5)       
  NOR         00011111          ~|                6  (8,7)       
  NOR         10001000          ~|                5  (10,11)     
  NOR         10100000          ~|                7  (9,11)      
  NOR         11000000          ~|                8  (9,10)      
  INPUT       00001111          in1               9              
  INPUT       00110011          in2               10             
  INPUT       01010101          in3               11             
  
  
  
  Cello finished playing.  Abstract circuit only.
  