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  <p style="position:absolute;top:1103px;left:68px;white-space:nowrap" class="ft00">VFMSUB132SD/VFMSUB213SD/VFMSUB231SD—Fused&#160;Multiply-Subtract of Scalar Double-Precision Floating-Point Values</p>
  <p style="position:absolute;top:47px;left:637px;white-space:nowrap" class="ft01">INSTRUCTION SET REFERENCE, V-Z</p>
  <p style="position:absolute;top:1103px;left:764px;white-space:nowrap" class="ft00">Vol. 2C&#160;5-177</p>
  <p style="position:absolute;top:100px;left:69px;white-space:nowrap" class="ft03">VFMSUB231SD DEST,&#160;SRC2, SRC3&#160;(EVEX encoded&#160;version)<br/>IF (EVEX.b&#160;= 1)&#160;and SRC3&#160;*is a register*</p>
  <p style="position:absolute;top:136px;left:89px;white-space:nowrap" class="ft02">THEN</p>
  <p style="position:absolute;top:154px;left:116px;white-space:nowrap" class="ft02">SET_RM(EVEX.RC);</p>
  <p style="position:absolute;top:172px;left:89px;white-space:nowrap" class="ft02">ELSE&#160;</p>
  <p style="position:absolute;top:190px;left:116px;white-space:nowrap" class="ft02">SET_RM(MXCSR.RM);</p>
  <p style="position:absolute;top:208px;left:69px;white-space:nowrap" class="ft03">FI;<br/>IF k1[0] or *no writemask*</p>
  <p style="position:absolute;top:244px;left:89px;white-space:nowrap" class="ft02">THEN</p>
  <p style="position:absolute;top:244px;left:143px;white-space:nowrap" class="ft02">DEST[63:0]&#160;&#160;RoundFPControl(SRC2[63:0]*SRC3[63:0] - DEST[63:0])</p>
  <p style="position:absolute;top:262px;left:89px;white-space:nowrap" class="ft02">ELSE&#160;</p>
  <p style="position:absolute;top:280px;left:116px;white-space:nowrap" class="ft02">IF&#160;*merging-masking*</p>
  <p style="position:absolute;top:280px;left:332px;white-space:nowrap" class="ft02">;&#160;merging-masking</p>
  <p style="position:absolute;top:298px;left:143px;white-space:nowrap" class="ft03">THEN *DEST[63:0] remains unchanged*<br/>ELSE&#160;;&#160;</p>
  <p style="position:absolute;top:316px;left:338px;white-space:nowrap" class="ft02">zeroing-masking</p>
  <p style="position:absolute;top:334px;left:170px;white-space:nowrap" class="ft02">THEN DEST[63:0]&#160;&#160;0</p>
  <p style="position:absolute;top:352px;left:116px;white-space:nowrap" class="ft02">FI;</p>
  <p style="position:absolute;top:370px;left:69px;white-space:nowrap" class="ft03">FI;<br/>DEST[127:64]&#160;&#160;DEST[127:64]<br/>DEST[MAX_VL-1:128]&#160;&#160;0</p>
  <p style="position:absolute;top:442px;left:69px;white-space:nowrap" class="ft03">VFMSUB132SD DEST,&#160;SRC2, SRC3&#160;(VEX&#160;encoded&#160;version)<br/>DEST[63:0]&#160;RoundFPControl_MXCSR(DEST[63:0]*SRC3[63:0] - SRC2[63:0])<br/>DEST[127:64]&#160;DEST[127:64]<br/>DEST[MAX_VL-1:128]&#160;0</p>
  <p style="position:absolute;top:532px;left:69px;white-space:nowrap" class="ft03">VFMSUB213SD DEST,&#160;SRC2, SRC3&#160;(VEX&#160;encoded&#160;version)<br/>DEST[63:0]&#160;RoundFPControl_MXCSR(SRC2[63:0]*DEST[63:0] - SRC3[63:0])<br/>DEST[127:64]&#160;DEST[127:64]<br/>DEST[MAX_VL-1:128]&#160;0</p>
  <p style="position:absolute;top:622px;left:69px;white-space:nowrap" class="ft03">VFMSUB231SD DEST,&#160;SRC2, SRC3&#160;(VEX&#160;encoded&#160;version)<br/>DEST[63:0]&#160;RoundFPControl_MXCSR(SRC2[63:0]*SRC3[63:0] - DEST[63:0])<br/>DEST[127:64]&#160;DEST[127:64]<br/>DEST[MAX_VL-1:128]&#160;0</p>
  <p style="position:absolute;top:710px;left:69px;white-space:nowrap" class="ft01">Intel C/C++&#160;Compiler&#160;Intrinsic Equivalent</p>
  <p style="position:absolute;top:733px;left:69px;white-space:nowrap" class="ft03">VFMSUBxxxSD __m128d _mm_fmsub_round_sd(__m128d&#160;a, __m128d b,&#160;__m128d c, int r);<br/>VFMSUBxxxSD __m128d _mm_mask_fmsub_sd(__m128d a,&#160;__mmask8 k, __m128d&#160;b, __m128d c);<br/>VFMSUBxxxSD __m128d _mm_maskz_fmsub_sd(__mmask8&#160;k, __m128d a, __m128d&#160;b, __m128d&#160;c);<br/>VFMSUBxxxSD __m128d _mm_mask3_fmsub_sd(__m128d&#160;a, __m128d b, __m128d c, __mmask8&#160;k);<br/>VFMSUBxxxSD __m128d _mm_mask_fmsub_round_sd(__m128d&#160;a, __mmask8&#160;k, __m128d b,&#160;__m128d&#160;c, int r);<br/>VFMSUBxxxSD __m128d _mm_maskz_fmsub_round_sd(__mmask8 k, __m128d&#160;a, __m128d&#160;b, __m128d c, int r);<br/>VFMSUBxxxSD __m128d _mm_mask3_fmsub_round_sd(__m128d a, __m128d&#160;b, __m128d&#160;c, __mmask8 k, int r);<br/>VFMSUBxxxSD __m128d _mm_fmsub_sd&#160;(__m128d a,&#160;__m128d&#160;b, __m128d&#160;c);</p>
  <p style="position:absolute;top:894px;left:69px;white-space:nowrap" class="ft01">SIMD Floating-Point&#160;Exceptions</p>
  <p style="position:absolute;top:916px;left:69px;white-space:nowrap" class="ft02">Overflow, Underflow,&#160;Invalid, Precision, Denormal</p>
  <p style="position:absolute;top:951px;left:69px;white-space:nowrap" class="ft01">Other Exceptions</p>
  <p style="position:absolute;top:973px;left:69px;white-space:nowrap" class="ft04">VEX-encoded&#160;instructions, see Exceptions Type 3.<br/>EVEX-encoded&#160;instructions, see Exceptions Type&#160;E3.</p>
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