text: /* TREZORv1 firmware linker script */
  
  ENTRY(reset_handler)
  
  MEMORY {
    FLASH  (rx)  : ORIGIN = 0x08010000, LENGTH = 1024K - 64K
    SRAM   (wal) : ORIGIN = 0x20000000, LENGTH = 128K
  }
  
  main_stack_base = ORIGIN(SRAM) + LENGTH(SRAM); /* 8-byte aligned full descending stack */
  _estack = main_stack_base;
  
  /* used by the startup code to populate variables used by the C code */
  data_lma = LOADADDR(.data);
  data_vma = ADDR(.data);
  data_size = SIZEOF(.data);
  
  /* used by the startup code to wipe memory */
  /* we have no CCMRAM, so erase the first word of SRAM as hack */
  ccmram_start = ORIGIN(SRAM);
  ccmram_end = ORIGIN(SRAM) + 4;
  
  /* used by the startup code to wipe memory */
  sram_start = ORIGIN(SRAM);
  sram_end = ORIGIN(SRAM) + LENGTH(SRAM);
  _ram_start = sram_start;
  _ram_end = sram_end;
  
  _codelen = LENGTH(FLASH);
  _flash_start = ORIGIN(FLASH);
  _flash_end = ORIGIN(FLASH) + LENGTH(FLASH);
  _heap_start = ADDR(.heap);
  _heap_end = ADDR(.heap) + SIZEOF(.heap);
  
  SECTIONS {
    .flash : ALIGN(512) {
      KEEP(*(.vector_table));
      . = ALIGN(4);
      *(.text*);
      . = ALIGN(4);
      *(.rodata*);
      . = ALIGN(512);
    } >FLASH AT>FLASH
  
    .data : ALIGN(4) {
      *(.data*);
      . = ALIGN(512);
    } >SRAM AT>FLASH
  
    .bss : ALIGN(4) {
      *(.bss*);
      . = ALIGN(4);
    } >SRAM
  
    .heap : ALIGN(4) {
      . = 37K; /* this acts as a build time assertion that at least this much memory is available for heap use */
      . = ABSOLUTE(sram_end - 16K); /* this explicitly sets the end of the heap effectively giving the stack at most 16K */
    } >SRAM
  
    .stack : ALIGN(8) {
      . = 4K; /* this acts as a build time assertion that at least this much memory is available for stack use */
    } >SRAM
  }
  