text: /* ---------------------------------------------------------------------------- */
  /*                  Atmel Microcontroller Software Support                      */
  /*                       SAM Software Package License                           */
  /* ---------------------------------------------------------------------------- */
  /* Copyright (c) 2015, Atmel Corporation                                        */
  /*                                                                              */
  /* All rights reserved.                                                         */
  /*                                                                              */
  /* Redistribution and use in source and binary forms, with or without           */
  /* modification, are permitted provided that the following condition is met:    */
  /*                                                                              */
  /* - Redistributions of source code must retain the above copyright notice,     */
  /* this list of conditions and the disclaimer below.                            */
  /*                                                                              */
  /* Atmel's name may not be used to endorse or promote products derived from     */
  /* this software without specific prior written permission.                     */
  /*                                                                              */
  /* DISCLAIMER:  THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR   */
  /* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */
  /* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE   */
  /* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,      */
  /* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */
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  /* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */
  /* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.                           */
  /* ---------------------------------------------------------------------------- */
  
  #ifndef _SAMA5D2_RSTC_COMPONENT_
  #define _SAMA5D2_RSTC_COMPONENT_
  
  /* ============================================================================= */
  /**  SOFTWARE API DEFINITION FOR Reset Controller */
  /* ============================================================================= */
  /** \addtogroup SAMA5D2_RSTC Reset Controller */
  /*@{*/
  
  #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
  /** \brief Rstc hardware registers */
  typedef struct {
    __O  uint32_t RSTC_CR; /**< \brief (Rstc Offset: 0x00) Control Register */
    __I  uint32_t RSTC_SR; /**< \brief (Rstc Offset: 0x04) Status Register */
    __IO uint32_t RSTC_MR; /**< \brief (Rstc Offset: 0x08) Mode Register */
  } Rstc;
  #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
  /* -------- RSTC_CR : (RSTC Offset: 0x00) Control Register -------- */
  #define RSTC_CR_PROCRST (0x1u << 0) /**< \brief (RSTC_CR) Processor Reset */
  #define RSTC_CR_PERRST (0x1u << 2) /**< \brief (RSTC_CR) Peripheral Reset */
  #define RSTC_CR_KEY_Pos 24
  #define RSTC_CR_KEY_Msk (0xffu << RSTC_CR_KEY_Pos) /**< \brief (RSTC_CR) Write Access Password */
  #define RSTC_CR_KEY(value) ((RSTC_CR_KEY_Msk & ((value) << RSTC_CR_KEY_Pos)))
  #define   RSTC_CR_KEY_PASSWD (0xA5u << 24) /**< \brief (RSTC_CR) Writing any other value in this field aborts the write operation.Always reads as 0. */
  /* -------- RSTC_SR : (RSTC Offset: 0x04) Status Register -------- */
  #define RSTC_SR_URSTS (0x1u << 0) /**< \brief (RSTC_SR) User Reset Status */
  #define RSTC_SR_RSTTYP_Pos 8
  #define RSTC_SR_RSTTYP_Msk (0x7u << RSTC_SR_RSTTYP_Pos) /**< \brief (RSTC_SR) Reset Type */
  #define   RSTC_SR_RSTTYP_GENERAL_RST (0x0u << 8) /**< \brief (RSTC_SR) Both VDDCORE and VDDBU rising */
  #define   RSTC_SR_RSTTYP_WKUP_RST (0x1u << 8) /**< \brief (RSTC_SR) VDDCORE rising */
  #define   RSTC_SR_RSTTYP_WDT_RST (0x2u << 8) /**< \brief (RSTC_SR) Watchdog fault occurred */
  #define   RSTC_SR_RSTTYP_SOFT_RST (0x3u << 8) /**< \brief (RSTC_SR) Processor reset required by the software */
  #define   RSTC_SR_RSTTYP_USER_RST (0x4u << 8) /**< \brief (RSTC_SR) NRST pin detected low */
  #define RSTC_SR_NRSTL (0x1u << 16) /**< \brief (RSTC_SR) NRST Pin Level */
  #define RSTC_SR_SRCMP (0x1u << 17) /**< \brief (RSTC_SR) Software Reset Command in Progress */
  /* -------- RSTC_MR : (RSTC Offset: 0x08) Mode Register -------- */
  #define RSTC_MR_URSTEN (0x1u << 0) /**< \brief (RSTC_MR) User Reset Enable */
  #define RSTC_MR_URSTIEN (0x1u << 4) /**< \brief (RSTC_MR) User Reset Interrupt Enable */
  #define RSTC_MR_KEY_Pos 24
  #define RSTC_MR_KEY_Msk (0xffu << RSTC_MR_KEY_Pos) /**< \brief (RSTC_MR) Write Access Password */
  #define RSTC_MR_KEY(value) ((RSTC_MR_KEY_Msk & ((value) << RSTC_MR_KEY_Pos)))
  #define   RSTC_MR_KEY_PASSWD (0xA5u << 24) /**< \brief (RSTC_MR) Writing any other value in this field aborts the write operation.Always reads as 0. */
  
  /*@}*/
  
  
  #endif /* _SAMA5D2_RSTC_COMPONENT_ */
  