text: //
  // Generated by Microsoft (R) HLSL Shader Compiler 10.1
  //
  //
  // Buffer Definitions: 
  //
  // cbuffer XeTextureLoadConstants
  // {
  //
  //   uint xe_texture_load_guest_base;   // Offset:    0 Size:     4
  //   uint xe_texture_load_guest_pitch;  // Offset:    4 Size:     4
  //   uint2 xe_texture_load_guest_storage_width_height;// Offset:    8 Size:     8
  //   uint3 xe_texture_load_size_blocks; // Offset:   16 Size:    12
  //   uint xe_texture_load_is_3d_endian; // Offset:   28 Size:     4
  //   uint xe_texture_load_host_base;    // Offset:   32 Size:     4
  //   uint xe_texture_load_host_pitch;   // Offset:   36 Size:     4
  //   uint xe_texture_load_height_texels;// Offset:   40 Size:     4 [unused]
  //
  // }
  //
  //
  // Resource Bindings:
  //
  // Name                                 Type  Format         Dim      ID      HLSL Bind  Count
  // ------------------------------ ---------- ------- ----------- ------- -------------- ------
  // xe_texture_load_source            texture   uint4         buf      T0             t0      1 
  // xe_texture_load_dest                  UAV   uint4         buf      U0             u0      1 
  // XeTextureLoadConstants            cbuffer      NA          NA     CB0            cb0      1 
  //
  //
  //
  // Input signature:
  //
  // Name                 Index   Mask Register SysValue  Format   Used
  // -------------------- ----- ------ -------- -------- ------- ------
  // no Input
  //
  // Output signature:
  //
  // Name                 Index   Mask Register SysValue  Format   Used
  // -------------------- ----- ------ -------- -------- ------- ------
  // no Output
  cs_5_1
  dcl_globalFlags refactoringAllowed
  dcl_constantbuffer CB0[0:0][3], immediateIndexed, space=0
  dcl_resource_buffer (uint,uint,uint,uint) T0[0:0], space=0
  dcl_uav_typed_buffer (uint,uint,uint,uint) U0[0:0], space=0
  dcl_input vThreadID.xyz
  dcl_temps 8
  dcl_thread_group 2, 32, 1
  ishl r0.x, vThreadID.x, l(4)
  mov r0.yz, vThreadID.yyzy
  uge r1.xyz, r0.xyzx, CB0[0][1].xyzx
  or r0.z, r1.y, r1.x
  or r0.z, r1.z, r0.z
  if_nz r0.z
    ret 
  endif 
  ishl r0.yz, r0.xxyx, l(0, 1, 1, 0)
  ishl r0.w, CB0[0][1].y, l(1)
  ishl r0.y, r0.y, l(1)
  imad r0.z, vThreadID.z, r0.w, r0.z
  imad r0.y, r0.z, CB0[0][2].y, r0.y
  iadd r0.y, r0.y, CB0[0][2].x
  ushr r0.z, CB0[0][2].y, l(4)
  ieq r0.w, CB0[0][0].y, l(-1)
  if_nz r0.w
    and r1.x, CB0[0][1].w, l(1)
    if_nz r1.x
      iadd r1.xy, CB0[0][0].wzww, l(31, 31, 0, 0)
      ishr r2.xyz, vThreadID.yzyy, l(4, 2, 3, 0)
      ushr r1.xy, r1.xyxx, l(4, 5, 0, 0)
      and r1.x, r1.x, l(0x0ffffffe)
      imad r1.x, r2.y, r1.x, r2.x
      ibfe r1.z, l(27), l(1), vThreadID.x
      imad r1.x, r1.x, r1.y, r1.z
      ishl r1.y, vThreadID.y, l(9)
      ishr r1.y, r1.y, l(6)
      iadd r1.z, r2.y, r2.z
      and r1.yw, r1.yyyz, l(0, 48, 0, 1)
      ishr r2.x, r0.x, l(3)
      bfi r1.z, l(1), l(1), r1.z, l(0)
      iadd r1.z, r1.z, r2.x
      bfi r1.z, l(2), l(1), r1.z, l(0)
      iadd r1.z, r1.z, r1.w
      bfi r1.xw, l(21, 0, 0, 21), l(9, 0, 0, 12), r1.xxxx, l(0, 0, 0, 0)
      imad r1.xy, r1.yyyy, l(2, 16, 0, 0), r1.xwxx
      bfi r1.xy, l(2, 2, 0, 0), l(7, 10, 0, 0), vThreadID.zzzz, r1.xyxx
      bfi r1.w, l(1), l(4), vThreadID.y, l(0)
      ubfe r2.x, l(3), l(6), r1.x
      and r2.y, r1.z, l(4)
      bfi r1.z, l(2), l(8), r1.z, l(0)
      imad r1.z, r2.x, l(32), r1.z
      imad r1.z, r2.y, l(4), r1.z
      bfi r1.xy, l(5, 5, 0, 0), l(0, 3, 0, 0), r1.wwww, r1.xyxx
      bfi r1.y, l(9), l(3), r1.z, r1.y
      bfi r1.x, l(6), l(0), r1.x, r1.y
    else 
      ibfe r1.y, l(27), l(1), vThreadID.x
      ishr r1.zw, vThreadID.yyyy, l(0, 0, 5, 2)
      iadd r2.x, CB0[0][0].z, l(31)
      ushr r2.x, r2.x, l(5)
      imad r1.y, r1.z, r2.x, r1.y
      bfi r2.xyz, l(4, 4, 4, 0), l(4, 7, 6, 0), vThreadID.yyyy, l(0, 0, 0, 0)
      bfi r2.xyz, l(24, 24, 24, 0), l(8, 11, 10, 0), r1.yyyy, r2.xyzx
      ishl r1.y, vThreadID.y, l(7)
      and r1.y, r1.y, l(2048)
      bfi r1.y, l(12), l(0), r1.y, r2.y
      and r1.z, r2.z, l(1792)
      iadd r1.y, r1.y, r1.z
      and r1.z, r1.w, l(2)
      ishr r1.w, r0.x, l(3)
      iadd r1.z, r1.w, r1.z
      bfi r1.z, l(2), l(6), r1.z, l(0)
      iadd r1.y, r1.y, r1.z
      bfi r1.x, l(6), l(0), r2.x, r1.y
    endif 
  else 
    ishl r0.x, r0.x, l(1)
    iadd r1.y, CB0[0][1].y, l(31)
    and r1.y, r1.y, l(-32)
    imad r1.y, vThreadID.z, r1.y, vThreadID.y
    imad r1.x, r1.y, CB0[0][0].y, r0.x
  endif 
  iadd r0.x, r1.x, CB0[0][0].x
  ushr r0.xy, r0.xyxx, l(2, 4, 0, 0)
  ushr r1.x, CB0[0][1].w, l(1)
  ld r2.xyzw, r0.xxxx, T0[0].ywxz
  ieq r1.x, r1.x, l(1)
  if_nz r1.x
    ishl r3.xyzw, r2.zxwy, l(8, 8, 8, 8)
    and r3.xyzw, r3.xyzw, l(0xff00ff00, 0xff00ff00, 0xff00ff00, 0xff00ff00)
    ushr r4.xyzw, r2.zxwy, l(8, 8, 8, 8)
    and r4.xyzw, r4.xyzw, l(0x00ff00ff, 0x00ff00ff, 0x00ff00ff, 0x00ff00ff)
    iadd r2.xyzw, r3.ywxz, r4.ywxz
    mov r3.xy, r2.zwzz
  else 
    mov r3.xy, r2.zwzz
  endif 
  iadd r1.yzw, r0.xxxx, l(0, 1, 2, 3)
  ld r4.xyzw, r1.yyyy, T0[0].xyzw
  if_nz r1.x
    ishl r5.xyzw, r4.xyzw, l(8, 8, 8, 8)
    and r5.xyzw, r5.xyzw, l(0xff00ff00, 0xff00ff00, 0xff00ff00, 0xff00ff00)
    ushr r6.xyzw, r4.xyzw, l(8, 8, 8, 8)
    and r6.xyzw, r6.xyzw, l(0x00ff00ff, 0x00ff00ff, 0x00ff00ff, 0x00ff00ff)
    iadd r5.xyzw, r5.xyzw, r6.xyzw
    mov r3.zw, r5.xxxz
    mov r2.zw, r5.yyyw
  else 
    mov r3.zw, r4.xxxz
    mov r2.zw, r4.yyyw
  endif 
  and r4.xyzw, r3.xyzw, l(0xf0f0f0f0, 0xf0f0f0f0, 0xf0f0f0f0, 0xf0f0f0f0)
  ishl r5.xyzw, r3.xyzw, l(8, 8, 8, 8)
  and r5.xyzw, r5.xyzw, l(0x0f000f00, 0x0f000f00, 0x0f000f00, 0x0f000f00)
  iadd r4.xyzw, r4.xyzw, r5.xyzw
  ushr r3.xyzw, r3.xyzw, l(8, 8, 8, 8)
  and r3.xyzw, r3.xyzw, l(0x000f000f, 0x000f000f, 0x000f000f, 0x000f000f)
  iadd r3.xyzw, r3.xyzw, r4.xyzw
  store_uav_typed U0[0].xyzw, r0.yyyy, r3.xyzw
  iadd r1.y, r0.z, r0.y
  and r3.xyzw, r2.xyzw, l(0xf0f0f0f0, 0xf0f0f0f0, 0xf0f0f0f0, 0xf0f0f0f0)
  ishl r4.xyzw, r2.xyzw, l(8, 8, 8, 8)
  and r4.xyzw, r4.xyzw, l(0x0f000f00, 0x0f000f00, 0x0f000f00, 0x0f000f00)
  iadd r3.xyzw, r3.xyzw, r4.xyzw
  ushr r2.xyzw, r2.xyzw, l(8, 8, 8, 8)
  and r2.xyzw, r2.xyzw, l(0x000f000f, 0x000f000f, 0x000f000f, 0x000f000f)
  iadd r2.xyzw, r2.xyzw, r3.xyzw
  store_uav_typed U0[0].xyzw, r1.yyyy, r2.xyzw
  iadd r2.xyz, r0.yyyy, l(1, 2, 3, 0)
  ld r3.xyzw, r1.zzzz, T0[0].ywxz
  if_nz r1.x
    ishl r4.xyzw, r3.zxwy, l(8, 8, 8, 8)
    and r4.xyzw, r4.xyzw, l(0xff00ff00, 0xff00ff00, 0xff00ff00, 0xff00ff00)
    ushr r5.xyzw, r3.zxwy, l(8, 8, 8, 8)
    and r5.xyzw, r5.xyzw, l(0x00ff00ff, 0x00ff00ff, 0x00ff00ff, 0x00ff00ff)
    iadd r3.xyzw, r4.ywxz, r5.ywxz
    mov r4.xy, r3.zwzz
  else 
    mov r4.xy, r3.zwzz
  endif 
  ld r5.xyzw, r1.wwww, T0[0].xyzw
  if_nz r1.x
    ishl r6.xyzw, r5.xyzw, l(8, 8, 8, 8)
    and r6.xyzw, r6.xyzw, l(0xff00ff00, 0xff00ff00, 0xff00ff00, 0xff00ff00)
    ushr r7.xyzw, r5.xyzw, l(8, 8, 8, 8)
    and r7.xyzw, r7.xyzw, l(0x00ff00ff, 0x00ff00ff, 0x00ff00ff, 0x00ff00ff)
    iadd r6.xyzw, r6.xyzw, r7.xyzw
    mov r4.zw, r6.xxxz
    mov r3.zw, r6.yyyw
  else 
    mov r4.zw, r5.xxxz
    mov r3.zw, r5.yyyw
  endif 
  and r5.xyzw, r4.xyzw, l(0xf0f0f0f0, 0xf0f0f0f0, 0xf0f0f0f0, 0xf0f0f0f0)
  ishl r6.xyzw, r4.xyzw, l(8, 8, 8, 8)
  and r6.xyzw, r6.xyzw, l(0x0f000f00, 0x0f000f00, 0x0f000f00, 0x0f000f00)
  iadd r5.xyzw, r5.xyzw, r6.xyzw
  ushr r4.xyzw, r4.xyzw, l(8, 8, 8, 8)
  and r4.xyzw, r4.xyzw, l(0x000f000f, 0x000f000f, 0x000f000f, 0x000f000f)
  iadd r4.xyzw, r4.xyzw, r5.xyzw
  store_uav_typed U0[0].xyzw, r2.xxxx, r4.xyzw
  iadd r1.yzw, r0.zzzz, r2.xxyz
  and r4.xyzw, r3.xyzw, l(0xf0f0f0f0, 0xf0f0f0f0, 0xf0f0f0f0, 0xf0f0f0f0)
  ishl r5.xyzw, r3.xyzw, l(8, 8, 8, 8)
  and r5.xyzw, r5.xyzw, l(0x0f000f00, 0x0f000f00, 0x0f000f00, 0x0f000f00)
  iadd r4.xyzw, r4.xyzw, r5.xyzw
  ushr r3.xyzw, r3.xyzw, l(8, 8, 8, 8)
  and r3.xyzw, r3.xyzw, l(0x000f000f, 0x000f000f, 0x000f000f, 0x000f000f)
  iadd r3.xyzw, r3.xyzw, r4.xyzw
  store_uav_typed U0[0].xyzw, r1.yyyy, r3.xyzw
  if_nz r0.w
    iadd r0.y, r0.x, l(16)
  else 
    iadd r0.y, r0.x, l(4)
  endif 
  ld r3.xyzw, r0.yyyy, T0[0].ywxz
  if_nz r1.x
    ishl r4.xyzw, r3.zxwy, l(8, 8, 8, 8)
    and r4.xyzw, r4.xyzw, l(0xff00ff00, 0xff00ff00, 0xff00ff00, 0xff00ff00)
    ushr r5.xyzw, r3.zxwy, l(8, 8, 8, 8)
    and r5.xyzw, r5.xyzw, l(0x00ff00ff, 0x00ff00ff, 0x00ff00ff, 0x00ff00ff)
    iadd r3.xyzw, r4.ywxz, r5.ywxz
    mov r4.xy, r3.zwzz
  else 
    mov r4.xy, r3.zwzz
  endif 
  iadd r0.xyz, r0.yyyy, l(1, 2, 3, 0)
  ld r5.xyzw, r0.xxxx, T0[0].xyzw
  if_nz r1.x
    ishl r6.xyzw, r5.xyzw, l(8, 8, 8, 8)
    and r6.xyzw, r6.xyzw, l(0xff00ff00, 0xff00ff00, 0xff00ff00, 0xff00ff00)
    ushr r7.xyzw, r5.xyzw, l(8, 8, 8, 8)
    and r7.xyzw, r7.xyzw, l(0x00ff00ff, 0x00ff00ff, 0x00ff00ff, 0x00ff00ff)
    iadd r6.xyzw, r6.xyzw, r7.xyzw
    mov r4.zw, r6.xxxz
    mov r3.zw, r6.yyyw
  else 
    mov r4.zw, r5.xxxz
    mov r3.zw, r5.yyyw
  endif 
  and r5.xyzw, r4.xyzw, l(0xf0f0f0f0, 0xf0f0f0f0, 0xf0f0f0f0, 0xf0f0f0f0)
  ishl r6.xyzw, r4.xyzw, l(8, 8, 8, 8)
  and r6.xyzw, r6.xyzw, l(0x0f000f00, 0x0f000f00, 0x0f000f00, 0x0f000f00)
  iadd r5.xyzw, r5.xyzw, r6.xyzw
  ushr r4.xyzw, r4.xyzw, l(8, 8, 8, 8)
  and r4.xyzw, r4.xyzw, l(0x000f000f, 0x000f000f, 0x000f000f, 0x000f000f)
  iadd r4.xyzw, r4.xyzw, r5.xyzw
  store_uav_typed U0[0].xyzw, r2.yyyy, r4.xyzw
  and r4.xyzw, r3.xyzw, l(0xf0f0f0f0, 0xf0f0f0f0, 0xf0f0f0f0, 0xf0f0f0f0)
  ishl r5.xyzw, r3.xyzw, l(8, 8, 8, 8)
  and r5.xyzw, r5.xyzw, l(0x0f000f00, 0x0f000f00, 0x0f000f00, 0x0f000f00)
  iadd r4.xyzw, r4.xyzw, r5.xyzw
  ushr r3.xyzw, r3.xyzw, l(8, 8, 8, 8)
  and r3.xyzw, r3.xyzw, l(0x000f000f, 0x000f000f, 0x000f000f, 0x000f000f)
  iadd r3.xyzw, r3.xyzw, r4.xyzw
  store_uav_typed U0[0].xyzw, r1.zzzz, r3.xyzw
  ld r3.xyzw, r0.yyyy, T0[0].ywxz
  if_nz r1.x
    ishl r4.xyzw, r3.zxwy, l(8, 8, 8, 8)
    and r4.xyzw, r4.xyzw, l(0xff00ff00, 0xff00ff00, 0xff00ff00, 0xff00ff00)
    ushr r5.xyzw, r3.zxwy, l(8, 8, 8, 8)
    and r5.xyzw, r5.xyzw, l(0x00ff00ff, 0x00ff00ff, 0x00ff00ff, 0x00ff00ff)
    iadd r3.xyzw, r4.ywxz, r5.ywxz
    mov r4.xy, r3.zwzz
  else 
    mov r4.xy, r3.zwzz
  endif 
  ld r0.xyzw, r0.zzzz, T0[0].xyzw
  if_nz r1.x
    ishl r5.xyzw, r0.xyzw, l(8, 8, 8, 8)
    and r5.xyzw, r5.xyzw, l(0xff00ff00, 0xff00ff00, 0xff00ff00, 0xff00ff00)
    ushr r6.xyzw, r0.xyzw, l(8, 8, 8, 8)
    and r6.xyzw, r6.xyzw, l(0x00ff00ff, 0x00ff00ff, 0x00ff00ff, 0x00ff00ff)
    iadd r5.xyzw, r5.xyzw, r6.xyzw
    mov r4.zw, r5.xxxz
    mov r3.zw, r5.yyyw
  else 
    mov r4.zw, r0.xxxz
    mov r3.zw, r0.yyyw
  endif 
  and r0.xyzw, r4.xyzw, l(0xf0f0f0f0, 0xf0f0f0f0, 0xf0f0f0f0, 0xf0f0f0f0)
  ishl r5.xyzw, r4.xyzw, l(8, 8, 8, 8)
  and r5.xyzw, r5.xyzw, l(0x0f000f00, 0x0f000f00, 0x0f000f00, 0x0f000f00)
  iadd r0.xyzw, r0.xyzw, r5.xyzw
  ushr r4.xyzw, r4.xyzw, l(8, 8, 8, 8)
  and r4.xyzw, r4.xyzw, l(0x000f000f, 0x000f000f, 0x000f000f, 0x000f000f)
  iadd r0.xyzw, r0.xyzw, r4.xyzw
  store_uav_typed U0[0].xyzw, r2.zzzz, r0.xyzw
  and r0.xyzw, r3.xyzw, l(0xf0f0f0f0, 0xf0f0f0f0, 0xf0f0f0f0, 0xf0f0f0f0)
  ishl r2.xyzw, r3.xyzw, l(8, 8, 8, 8)
  and r2.xyzw, r2.xyzw, l(0x0f000f00, 0x0f000f00, 0x0f000f00, 0x0f000f00)
  iadd r0.xyzw, r0.xyzw, r2.xyzw
  ushr r2.xyzw, r3.xyzw, l(8, 8, 8, 8)
  and r2.xyzw, r2.xyzw, l(0x000f000f, 0x000f000f, 0x000f000f, 0x000f000f)
  iadd r0.xyzw, r0.xyzw, r2.xyzw
  store_uav_typed U0[0].xyzw, r1.wwww, r0.xyzw
  ret 
  // Approximately 249 instruction slots used
  