text: //===-- XCore.td - Describe the XCore Target Machine -------*- tablegen -*-===//
  //
  // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
  // See https://llvm.org/LICENSE.txt for license information.
  // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
  //
  //===----------------------------------------------------------------------===//
  //
  // This is the top level entry point for the XCore target.
  //
  //===----------------------------------------------------------------------===//
  
  //===----------------------------------------------------------------------===//
  // Target-independent interfaces which we are implementing
  //===----------------------------------------------------------------------===//
  
  include "llvm/Target/Target.td"
  
  //===----------------------------------------------------------------------===//
  // Descriptions
  //===----------------------------------------------------------------------===//
  
  include "XCoreRegisterInfo.td"
  include "XCoreInstrInfo.td"
  include "XCoreCallingConv.td"
  
  def XCoreInstrInfo : InstrInfo;
  
  //===----------------------------------------------------------------------===//
  // XCore processors supported.
  //===----------------------------------------------------------------------===//
  
  class Proc<string Name, list<SubtargetFeature> Features>
   : Processor<Name, NoItineraries, Features>;
  
  def : Proc<"generic",      []>;
  def : Proc<"xs1b-generic", []>;
  
  //===----------------------------------------------------------------------===//
  // Declare the target which we are implementing
  //===----------------------------------------------------------------------===//
  
  def XCore : Target {
    // Pull in Instruction Info:
    let InstructionSet = XCoreInstrInfo;
  }
  