Scalable RF, N x M switching matrix architecture

Abstract: A scalable N x M switching matrix architecture is characterized by a readily calculable number of crossover locations and comprises one or more single pole, N throw ("SPNT") switches (10A-10F) and, for each such switch, an N state impedance converter/amplitude compensation network.

Description: The present invention relates generally to RF circuit switching architectures and, more particularly, to non-blocking, N x M switching matrices. A conventional approach to realizing a non-blocking N x M switching matrix in RF frequency applications is shown in FIG. 1 of the accompanying drawings. As seen in FIG. 1, each of the power dividers D 1 , D 2 , D 3 , and D N is configured to receive a corresponding RF signal input at input ports designated RF in 1, RF in 2, RF in N-1, and RF in N, respectively. At each power divider, the RF input signal is directed to output paths 1-M. These paths are then switched in and out using 1 x N switches, indicated generally at S 1 , S 2 , S 3 , and S N , disposed at the outputs, indicated generally at RF out 1, RF out 2, RF out N-1, and RF out N. A principal disadvantage of the arrangement shown in FIG. 1 is that the power dividers are frequency limited. Additionally, routing every RF input signal over plural paths to reach the corresponding switch simultaneously establishes multiple leakage paths for each input. This opportunity for isolation degradation is, consequently, multiplied by the number of splits on each input. Moreover, as a consequence of this multiple stage architecture, the input paths must be routed in a fashion which creates numerous cross over points, only some of these being identified by reference numeral CO in FIG. 1. The inability to provide adequate isolation between the input signal lines has made the above-described approach wholly impractical and unsuited to implementation as a discrete IC. While it might be possible to construct a multiple layer printed circuit board (PCB) with shielded ground planes between layers to minimize cross talk and achieve acceptable isolation between signal paths, given the complexity of routing the paths in such a device, it is presently not possible to simulate or predict what level of isolation will be achieved until such a device is actually constructed and tested. In any event, it is believed that adapting the above-described matrix architecture to the ever-increasing numbers of inputs and outputs demanded by modern applications would pose substantial reliability concerns. US-A 5 510 757 discloses a non-blocking 2 x 2 switching matrix architecture comprising two SPDT-switches. The aforementioned deficiencies are addressed, and an advance is made in the art, by a switching architecture having the advantages of broad bandwidth, high isolation, and an ability to be implemented at the IC level due to a systematic approach taken to ensure isolation. The scalable N x M switching matrix architecture of the present invention is characterized by a readily calculable number of cross over locations so that leakage can be accurately modeled and predicted. A scalable N x M switching matrix architecture is characterized by a readily calculable number of crossover locations and comprises one or more single pole, N throw ("SPNT") switches and, for each such switch, an N state impedance converter/amplitude compensation network. In accordance with the present invention, each SPNT switch network selects the output to any of the N inputs in any combination with up to all N inputs being selected. Collectively, the individual 1 x N networks formed by each combination of SPNT switch and its corresponding impedance converter/amplitude compensation network comprises the N x M network. In all switch conditions, the impedance and insertion loss of each SPNT switch is maintained by an impedance converter/amplitude compensation network. The number of output ports determines the number (M) of 1 x N networks in the matrix. The number of input ports is set by the number of legs (N) in the SPNT switch. By placing the SPNT switch as the last element before the output, the number of cross over points is maintained at a number which can be readily calculated based on the number of inputs and outputs. Illustrative embodiments of the invention will now be described, by way of example, with reference to the accompanying drawings in which like numerals refer to like parts and further and in which: FIG. 1 is a block diagram depicting a conventional non-blocking N x M switching matrix suitable for only a relatively small number of RF signal inputs and not adaptable for implementation as an integrated circuit; FIG. 2 is a block diagram schematic of a novel individual 1 x N switch network element for use with the present invention; FIGS. 3A-3D are circuit schematics depicting various topologies for obtaining impedance and gain compensation in the present invention; FIGS. 4A-4C are block diagrams respectively depicting illustrative configurations of non-blocking 2 x 2, 4 x 4, and 4 x 6 switch matrix architectures and FIG. 5 depicts a non-blocking N x M switching matrix architecture constructed in accordance with the present invention and in which each switch element is aligned such that the inputs are directed towards each other and interconnected in a grid fashion. With initial reference to FIG. 2, there is shown a 1 x N switch network 10, for use in an N x M switching matrix architecture according to the present invention, which provides not only 1 x N switching connectivity, but also impedance and gain compensation regardless of the number of ports selected to be output. Each switch, S 1 through S N , is directly controlled by embedded control logic 12 located on the same integrated circuit chip (IC) as the other components of the network 10. Impedance and/or gain compensation, which may, as in the illustrative embodiment depicted in FIGS. 2-3D, be variable to permit multiple ports to be selected to a single output simultaneously, is performed by discrete impedance and gain compensation circuit modules indicated generally at G in 1 through G in N and G out . Initially, it should be noted that conventional 1 x N switches have several limitations which make them unsuitable for the non-blocking architecture contemplated by the inventors herein. First, such devices require many control lines, leading to complex routing requirements and user interface. Second, if multiple ports are switched to the same port simultaneously, the impedance seen at the ports gets lower and lower, proportional to the number of ports selected. Not only does the port impedance vary dramatically, the insertion gain varies significantly as well. Needless to say, it is undesirable to have such variations. Current switch matrix solutions also require multiple die and driver integrated circuits within a complex and costly package. As well, they are limited in their ability to maintain constant insertion and return loss through different switch states. Heretofore, switches have been designed to operate in a single system impedance environment, requiring multiple versions of the switch and external components to operate with proper impedance in systems of variable impedance. The present invention, on the other hand, utilizes switched impedance circuitry to maintain constant, wide band port impedance and insertion gain. External driver circuitry is not needed because all of the logic is preferably incorporated on a single IC. Advantageously, the IC uses different combinations of internal impedance blocks to maintain constant match and gain. Several illustrative topologies, in which the impedance blocks are arranged to achieve the flexibility and functionality required to implement a non-blocking N x M switch architecture in accordance with the present invention, are shown in FIGS. 3A-3D. Preferably, each of these topologies uses a parallel path method for creating the attenuation steps. That is, instead of "daisy chaining" multiple attenuators, each with a bypass transistor for use when that stage is not desired, a "PI", "T" or other equivalent structure as shown in FIGS. 3A-3D is made with parallel resistive elements. This results in superior return loss and lower reference insertion loss as compared to conventional multi-step attenuator design approaches. Note that an ideal multistep attenuator would have no reference insertion loss. For example, a 5 dB multistep attenuator would be expected to have steps between 0 and 5 dB attenuation. In reality, there is loss in each bypass stage, so the conventional approach using bypass transistors would typically have been characterized by a reference insertion loss of 1.5 dB. The parallel method is therefore especially preferred for use in conjunction with implementing 1 x N switch networks in accordance with the present invention since the reference loss is significantly reduced in comparison to the conventional bypass transistor approach. As will be readily appreciated by those skilled in the art, the effect of switching multiple impedance in parallel or in series gives a varied overall input and output impedance, as well as varied insertion gain. The individual impedance are chosen so that appropriate lumped impedance are acquired for each desired state. These can be any combination of resistance, capacitance and inductance to get the requisite values. By varying these impedances and gains, it is possible to offset the variation that would otherwise exist in a switch without this impedance/gain control. With such offsets, the device can maintain a constant input and output impedance and overall port to port gain. In any event, and with continued reference to FIGS. 3A-3D, it will be appreciated that the illustrative topologies may be used individually or in any combination as required for the specific system impedance of a particular application. That is, the precise topology used will be based upon the particular impedance and loss requirements of each application. For each port or combination of ports selected by SPNT switch SW under the direction of embedded logic control 12 (FIG. 2), a specific combination of impedance is used. Accordingly, the invention permits operation with more than one system impedance without degradation of performance. An external control word may be used to specify the system impedance so that the embedded control logic 12 (FIG. 2) can implement multiple sets of impedance combinations. As such, a single component as network 10 may be used to function in a wide variety of impedance networks. Preferably, a serial control interface is used to reduce the number of needed control lines. The device can be implemented in an addressable configuration, so that multiple serial devices can be on the same serial bus yet maintain individual device control, greatly simplifying the higher level assembly of the IC. In any event, and with particular reference now to FIGS. 4A-4C, several non-blocking configurations employing the above-described 1 x N switching network element 10 will now be described. In FIG. 4A, for example, there is shown a 2 x 2 non-blocking switch matrix architecture comprising two 1 x N switching networks indicated generally at 10a and 10b. This embodiment is not claimed. In FIG. 4B, a 4 x 4 non-blocking switch matrix architecture is depicted, the structure using four 1 x N switching networks indicated generally at 10a, 10b, 10c and 10d. In FIG. 4C, there is shown yet another example of a non-blocking switch matrix architecture constructed in accordance with the present invention, this time employing six 1 x N switching networks indicated generally at 10a, 10b, 10c, 10d, 10e and 10f. Under the control of embedded control logic 12 (FIG. 2), the SPNT switch SW of each 1 x N network, as network 10a, can select the output to any of the N inputs in any combination with up to all N inputs being selected . In the preceding embodiments depicted in FIGS. 4A-4C, N would be 2, 4 and 4, respectively. In all switch conditions, the impedance and the insertion loss of the switch is maintained by the impedance converter/amplitude compensation network comprising gain modules G in -1 through G in -N and G out (FIG 2). A generalized case, i.e., an N x M architecture is depicted in FIG. 5 with each switch element 10a-10f being aligned such that the inputs are directed towards each other and interconnected in a grid fashion. The RF portion of each switch element is identical, but the input port selected for any given control word can be controlled by a control logic block. Hence, the layout of the matrix is optimized such that the number of crossovers is minimized to maximize the overall isolation performance of the matrix. For a symmetrical switch matrix in which the number of inputs is equal to the number of outputs (i.e., N=M, N ≠ 2), the minimum number of crossovers (CX) in the matrix is given by the relation: CX = N 2- -N For a matrix which is not symmetrical, the number of crossovers depends on the configuration but can be easily calculated. By placing the 1 x N switches across the X and Y directions as shown in FIG. 5, the calculation of the number of crossovers is: CX=(N*SE x )*((N-1)*SE y ) where SE x is the number of switch elements in the X direction and SE y is the number of switch elements in the Y direction (see FIG. 5). For example, a 4 x 6 switch matrix configured as shown in FIG. 4 C would be: CX = (4*1)*((4-1)*2) = 24 Just as important as the total number of crossovers is the number of crossovers associated with each switch leg. Preferably, the number of crossovers is kept constant for each input. By designing the architecture such that each associated input has the same number of crossovers, it is possible to ensure that each input is equally loaded. Advantageously, the predictability of the RF matrix of the present invention enables it to be accurately simulated using a variety of ubiquitous commercial RF CAD tools so that the operating performance can be readily simulated and characterized.

Claims: A scalable, non-blocking N x M switching matrix architecture having a minimum number of crossovers CX in the matrix represented by the following equation: CX=(N*SE x )*((N-1)*SE y ) wherein N is the number of inputs in the matrix, whereby N > 2 , M is the number of outputs in the matrix, whereby M > 2; SE x is the number of switch elements in the X direction; and SE y is the number of switch elements.in the Y direction with the proviso that when N = M , CX = N 2 -N; and wherein each switch element in the matrix comprises a single pole, N-throw switch (S 1 - S N ). The switching matrix architecture of claim 1, comprising an N state impedance converter/amplitude compensation network for each switch. The switching matrix architecture of claim 2, wherein the N state impedance converter/ amplitude compensation network comprises impedance and gain compensation circuit modules (G in 1- G in N, G out ). The switching matrix architecture of claim 3, wherein the modules are arranged in a topology that utilizes a parallel path method for creating attenuation steps. The switching matrix architecture of claim 3 or 4, wherein the modules are selected and arranged to maintain constant input and output impedance and overall port-to-port gain. The switching matrix architecture of claim 2, 3, 4 or 5, wherein each switch (S 1 -S N ) selects the output to any of the N inputs in any combination with up to all N inputs being selected. The switching matrix architecture of any preceding claim 2 to 6, wherein each switch is directly controlled by embedded control logic (12). The switching matrix architecture of claim 1, wherein the number of crossovers for each input is kept constant.

Inventors: FREESTON ANDREW KENNETH, SCHWAB PAUL JOHN, FREESTON, ANDREW KENNETH, SCHWAB, PAUL JOHN
Applicants: TYCO ELECTRONICS CORP, TYCO ELECTRONICS CORPORATION
Application year: 2001
Main classification: H01P1
IPC codes: H01P1