Method and circuit for synchronizing parallel voltage source inverters

Abstract: An inverter circuit (10) has a plurality of voltage source inverters (VSI) coupled in parallel. Each of the voltage source inverters are coupled to a load (14). A synch signal source (12) generates a square wave from a fundamental operating frequency. The square wave generated by the synch signal source (12) is coupled to each voltage source inverter (VSI). Each voltage source inverter VSI has a timer counter (22), a microprocessor (26), and an inverter (32). The timer counter (22) is preferably a triangle wave generator that corresponds to the time since a rising edge of a synch signal (18). The microprocessor (26) samples the cyclic output signal (24) and determines a phase angle for the voltage source inverter. The phase angle and the voltage magnitude are provided to the inverter (32). The inverter (32) provides an output signal to the load that has the same phase angle as the outputs of the other phase inverters.

Description: The present invention relates generally to voltage source inverters, and more specifically, to a synchronization circuit for synchronizing the output of parallel voltage source inverters. To generate high power outputs for an AC source, it is common to place a number of electronic voltage source inverters in parallel. Each of the voltage source inverters has an associated phase angle. One known problem with placing voltage source inverters in parallel is that if the phase angles are not the same in each of the parallel voltage source inverters, circulating real power between the voltage sources may be developed. Circulating real power reduces the capability and efficiency of the voltage sources. Further, circulating real power may also cause the malfunctioning of the voltage source inverter. One solution disclosed in US 4 171 517 involves the adding of a synchronization signal to the output of a common reference oscillator. Another solution disclosed in US 3 832 622 involves the controlling of the operating rate of static inverter flip-flops. It is therefore one object of the invention to provide a voltage inverter circuit having the phase angles synchronized to minimize real power circulation. It is therefore one object of the invention to provide a circuit having parallel voltage source inverters that are configured to minimize circulating real power among the inverters. The parallel voltage source inverters essentially become electrically equivalent by the present invention to eliminate the circulating real power. In one aspect of the invention an inverter circuit comprises a synchronization signal source having a frequency and a phase. A first voltage source inverter circuit is coupled to a load and the synchronization source. The first voltage source inverter circuit comprises a cycle time counter generating a cyclic output signal and a first sampling circuit receiving the cyclic output signal and sampling said cyclic output signal. The first sampling circuit generates a magnitude signal and a phase signal in response to said cyclic output signal. The first inverter circuit generates an output signal having a first phase in response to the magnitude signal and the phase signal. A second voltage source inverter circuit is coupled to the load in parallel with the first voltage source inverter and to the synchronization signal source. The second voltage source inverter circuit has a second cycle time counter generating a second cyclic output signal. The second sampling circuit receives the second cyclic output signal and samples the second cyclic output signal. The second sampling circuit generates a second magnitude signal and a second phase signal in response to the cyclic output signal. The second phase signal and the first phase signal are substantially synchronised. In a further aspect of the invention, a method for generating a voltage signal using a first inverter circuit in parallel with the second inverter circuit comprises the steps of: generating a synchronization signal having a frequency and a phase; continuously counting cycle times of the synch signal in a first inverter circuit; sampling a first cycle time from the cycle times at a first sample moment; calculating a first phase angle in response to the first cycle time; generating an output signal from a first inverter circuit having the first phase angle; counting cycle times of the synchronization signal in a second inverter circuit; sampling a second cycle time at a second sampling moment; calculating a second phase angle in response to said second cycle time; generating a second output signal from said second inverter circuit having a second phase wherein said second phase angle is substantially equal to said first phase angle. One advantage of the invention is that a sawtooth generator may be used to generate the cyclic output signal that represents the phase angle. This eliminates the usually strict requirement that the updating rate of each of the voltage source inverters must be the same and that the updating cycle must be synchronized for the phase angle synchronization among the voltage source inverters. Another advantage of the invention is that the fundamental operating frequency and the sampling frequency of the microprocessor do not need strict synchronization. Another advantage of the invention is that no analog-to-digital conversion is required between the microcontroller and the sawtooth wave generator. Yet another advantage of the invention is that the synchronous signal source is digital which has much better noise immunity than analog signals. Also, the digital signal is based on a relatively low frequency and thus the bandwidth requirements for transmission among the parallel voltage source inverters is low. In combination, the advantages result in increased reliability, robustness and better performance of the voltage source. The invention will now be described further, by way of example, with reference to the accompanying drawings, in which: Figure 1 is a block diagrammatic view of an inverter circuit according to the present invention, and Figure 2 is a block diagrammatic view of a sawtooth triangle wave generator included in the circuit of Figure 1. In the following figures the same reference numeral is used to identify the same component in the two views. The present invention is particularly suited for applications requiring parallel voltage sources including power sources. However, those skilled in the art will recognize that the present invention may be applicable to other areas including motor controls. Referring now to Figure 1, an inverter circuit 10 has a synchronization (synch) signal source 12 coupled to a plurality of voltage source inverter circuits (VSI 1, VSI n-1, and VSI n). Although three voltage source inverter circuits (VSI) are illustrated, various numbers of voltage source inverter circuits may be used depending on the output power to be provided as would be evident to those skilled in the art. The output of each voltage source inverter circuit VSI 1, VSI n-1, and VSI n is coupled to a common load 14. Synch signal source 12 is illustrated as a square wave generator. However, those skilled in the art would recognize that other types of synch signal sources may be used. Synch signal source 12 has a fundamental operating frequency input 16. A suitable fundamental operating frequency is a relatively low frequency, e.g., preferably about 50 or 60 Hz. The preferred fundamental operating frequency is the frequency provided through the connection to the mains power companies. The synch signal source 12 generates a synch signal represented by reference numeral 18 through an output 20. The synch signal 18 has a first frequency corresponding to the fundamental operating frequency input and a phase also corresponding to the fundamental operating frequency input. As mentioned above, a square wave generator is used as the synch signal source. The square wave is a digital signal and is consequently less susceptible to noise during transmission to the VSIs. The VSIs are configured in a similar manner and therefore the operation and components of only one will be described. Each VSI has a timer counter 22 such as a sawtooth wave generator. Timer counter 22 generates a cyclic output signal 24 which has a magnitude corresponding to a count of the cycle time of the square wave. For example, the cyclic output signal 24 may, for example, correspond to the time since the last rising edge of the synch signal square waves. The timer counter 22 converts the square wave synch signal 18 into cyclic output signal 24, which is a sawtooth wave. The frequency of the sawtooth wave is the same as the synch signal. The sawtooth cyclic output signal 24 also has the same phase as the square wave signal. A microprocessor 26 is used to sample the cyclic output signal 24. The sampling frequency should be much higher than the synchronization signal frequency of 50 to 60 Hz. A suitable range of the sampling frequency is between about 2,000 and 20,000 Hz. The sample by the microprocessor of the cyclic output signal 24 corresponds to a time elapsed from the previous rising edge of the phase synch signal. Using the elapsed time, the phase angle at the sampling moment may be calculated by the following equation:  k =t s ·f e ·360° where t s is the elapsed time from the rising edge at the sampling moment, f e is the fundamental operating frequency (50 or 60 Hz) of the VSI. The microprocessor has two outputs; a magnitude output 28 and a phase angle output 30. The phase angle and the magnitude are coupled to an inverter 32. Inverter 32 provides a synchronized signal to load 14 corresponding to V m *Sin. Thus, the phase angles of the outputs of each VSI may be synchronized. Referring now to Figure 2, timer counter circuit 22 is illustrated in further detail. Timer counter 22 has a time counter 34 that is coupled to a time source such as a clock 36 and to square wave generator 10 for receiving synch signal 18. The output of time counter 34, as mentioned above, is a measurement of time from the last rising edge of the synch signal 18. Thus, the cyclic output signal 24 starts at zero upon a rising edge of the synch signal and increases until a new rising edge is presented. Clear logic circuit 35 monitors the synch signal 18 and resets time counter 34 upon the rising edge. Of course, other triggers such as a falling edge may be used for resetting. As long as a consistent portion of synch signal 18 is monitored, the phase of the cyclic output signal 24 is the same as the phase of synch signal 18. The microprocessor 26 is coupled to gate 40 for receiving cyclic output signal 24. Gate 40 is coupled to a sampling line 42 of microprocessor 26 to control the sampling of the cyclic output signal 24. Because the magnitude of the cyclic output signal 24 corresponds to the time since the last rising edge, the phase angle of the signal may be calculated by microprocessor 26 using the equation above. Thus, the inverter may then output a common phase angle signal for each of the VSIs. In operation, the synch signal 18 is derived from a fundamental operating frequency. The square wave signal has a first frequency and a first phase angle. The time counting circuit 22 calculates the time since the last rising edge of the synch signal. Because this signal directly corresponds to the time since the last rising edge, the phase angle may be derived therefrom. The microprocessor 26 samples the cyclic output signal 24 that corresponds to the time and thus the phase of the output of the microprocessor 26 may be set to provide the inverter with the same signal as the other microprocessors provide to the other inverters. Thus, the output of each of the inverters is synchronized in terms of phase angle and thus real power will not be circulated through the inverter circuit 10.

Claims: An inverter circuit comprising: a synchronization signal source (12) having a frequency and a phase; a first voltage source inverter circuit coupled to a load (14) and said synchronization signal source (12), said first voltage source inverter circuit comprising a cycle time counter (22) generating a first cyclic output signal (24) having a frequency and a phase corresponding to the frequency and the phase of the synchronization signal, a first sampling circuit (26,40) receiving and sampling said first cyclic output signal (24) said first sampling circuit (26,40) generating a magnitude signal (28) and a first phase angle signal (30) in response to said first cyclic output signal; a second voltage source inverter circuit coupled to said load (14) and said synchronization signal source (12) in parallel with said first voltage source circuit, said second voltage source inverter circuit comprising a second cycle time counter (22) generating a second cyclic output signal (24) having a frequency and a phase corresponding to the frequency and the phase of the synchronisation signal, a second sampling circuit (26,40) receiving and sampling said second cyclic output signal (24) said second sampling circuit (26,40) generating a magnitude signal (28) and a second phase angle signal (30) corresponding to said second cyclic output signal, said second phase angle signal having a phase substantially synchronised with said first phase angle signal. An inverter circuit as claimed in claim 1 wherein said first sampling circuit (26,40) comprises a first microprocessor (26) and said second sampling circuit comprises a second microprocessor (26). An inverter circuit as claimed in claim 1 wherein each said cycle time counter (22) comprises a triangle wave generator. An inverter circuit as claimed in claim 1 wherein each said cycle time counter (22) is coupled to a clock source (36) and said synchronization signal source (12). An inverter circuit as claimed in claim 1 wherein each said time counter (22) generates a sawtooth wave signal having a phase corresponding to said synch signal source. An inverter circuit as claimed in claim 1 wherein said first sampling circuit (26,40) has a sampling frequency substantially greater than said first frequency. An inverter circuit as claimed in claim 1 wherein said sampling frequency is between 2,000 and 20,000 Hz. An inverter circuit as claimed in claim 1 wherein said cycle time counter (22) comprises a time counter (34) and a clear logic circuit (35) coupled to said time counter. An inverter circuit as claimed in claim 8, further comprising a clock (36) coupled to the time counter (34) , said time counter (34) counting the clock pulses since a clear logic signal from said clear logic circuit (35). A method for generating a voltage signal using a first inverter circuit in parallel with a second inverter circuit comprising the steps of: generating a synchronization signal having a frequency and a phase; in a first inverter circuit generating a first cyclic output signal having a frequency and a phase corresponding to the frequency and phase of the synchronization signal; sampling the first cyclic output signal; calculating a magnitude signal and a first phase angle in response to the first cyclic output signal ; generating an output signal from the first inverter circuit having the first phase angle; in a second inverter circuit generating a second cyclic output signal having a frequency and a phase corresponding to the frequency and phase of the synchronization signal ; sampling the second cyclic output signal ; calculating a magnitude signal and a second phase angle in response to said second cyclic output signal ; generating a second output signal from said second inverter circuit having the second phase angle wherein said second phase angle is substantially synchronised with said first phase angle. A method as claimed in claim 10 wherein said step of generating a synchronization signal comprises a step of generating a square wave signal. A method as claimed in claim 10 wherein said step of generating a first cyclic output signal comprises the steps of generating a triangle wave having a frequency and a phase corresponding to the frequency and the phase of the synchronization signal. A method as claimed in claim10 wherein said step of generating a triangle wave comprises counting the time since a rising edge of the synchronization signal. A method as claimed in claim 10 further comprising the step of clearing a time counter in response to a rising edge of the synchronization signal.

Inventors: BHAVARAJU VIJAY, DENG DOUG D, WANG KON-KING, BHAVARAJU, VIJAY, DENG, DOUG D., WANG, KON-KING
Applicants: BALLARD POWER SYSTEMS, BALLARD POWER SYSTEMS CORPORATION
Application year: 2001
Main classification: H02M7
IPC codes: H02M7