VOLTAGE STABILIZED LOW LEVEL DRIVER

Abstract: The invention provides a voltage stabilized low level driver. The driver includes a switched op-amp that controls the output of the driver to match an internal reference voltage when it is switched on. When it is switched off, the op-amp turns off the output of the driver and allows the output to be pulled up by an external device. The driver also includes a slew rate control circuit for limiting the slew rate of the high-to-low transition at the output. The driver may be used for I<2>C applications.

Description: Voltage stabilized low level driver BACKGROUND OF THE INVENTION The invention generally relates to voltage drivers, and more particularly to voltage stabilized low level drivers for a variety of applications. Voltage drivers have been used for providing a voltage level to drive loads for various applications. Different applications require different types of voltage drivers. Many conventional voltage drivers are not stable. Some of them are temperature or Vcc dependent, while others are load current or load capacitance dependent. As a result, these conventional voltage drivers have their limitations in their applications. In a particular application relating an Inter Integrated Circuits (I C) bus interfaces, unstable voltage drivers adversely affect the circuit performance. Therefore, there is a need for a stable voltage driver that is independent of temperature, Vcc, load current and load capacitance. SUMMARY OF THE INVENTION The present invention provides a voltage stabilized low level driver that outputs a low level independent of temperature, Vcc, load current, and load capacitance. According to one embodiment of the invention, a voltage driver having an output node is provided. The driver comprises a switching circuit and an operational amplifier. The switching circuit has a control terminal and an output terminal coupled to the output node. The amplifier has a first input terminal connected to the output node, a second input terminal connected to an input reference voltage, and an output terminal connected to the control terminal of the switching circuit. The amplifier is controlled by an external disable signal for switching on and off the amplifier. The amplifier, upon being switched on, drives the control terminal of the switching circuit to cause the output node to match the reference voltage. The amplifier, upon being switched off, drives the control terminal of the switching circuit to cause the output node to have a high impedance. The high impedance allows the output node to be pulled up by an external device to a predetermined level. In a specific embodiment, the switching circuit is a transistor, and the control terminal is a gate terminal of the transistor. According to another embodiment of the invention, a voltage driver having an output node is provided. The driver comprises a switching circuit having a control terminal and an output terminal; an operational amplifier having a first input terminal, a second input terminal, and an output terminal that is connected to the control terminal of the switching circuit, the amplifier being controlled by an external disable signal for switching on and off the amplifier; an output protection circuit coupled between the output node and the output terminal of the switching circuit; a first input protection circuit coupled between the first input terminal of the amplifier and the output node; and a second input protection circuit coupled between the second input terminal of the amplifier and an input reference voltage. The amplifier, upon being switched on, drives the control terminal of the switching circuit to cause the output node to match the reference voltage. The amplifier, upon being switched off, drives the control terminal of the switching circuit to cause the output node to have a high impedance. The high impedance allows the output node to be pulled up by an external device to a predetermined level. In another embodiment, the driver further comprises a slew rate control circuit coupled between the output node and the control terminal of the switching circuit. According to a third embodiment of the invention, a repeater incorporating a voltage driver of the invention is provided for use in an I 2 C bus interface. Other objects and attainments together with a fuller understanding of the invention will become apparent and appreciated by referring to the following description and claims taken in conjunction with the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS The invention is explained in further detail, and by way of example, with reference to the accompanying drawings wherein: FIG. 1 shows a voltage stabilized low level driver according to a first embodiment of the invention; FIG. 2 shows a voltage stabilized low level driver according to a second embodiment of the invention; FIG. 3 shows the schematics of the circuit in FIG. 2; and FIG. 4 shows a repeater according to a third embodiment of the invention. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The principles of the invention are described with reference to the embodiment in FIG. 1. FIG. 1 shows a voltage stabilized low level driver 10 according to a first embodiment of the invention. Driver 10 comprises an operational amplifier (op-amp) 12 and a switching circuit, e.g., an output NMOS transistor 22 having an open-drain output Vout. Op- amp 12 has its positive input terminal connected to an output node 24, forming a feedback loop and its negative input terminal connected to a reference voltage, Vref. Op-amp 12 also has its output connected to the gate of transistor 22. When it is enabled, op-amp 12 drives transistor 22 such that the feedback mechanism causes the output voltage Vout to match the reference voltage, Vref. When op-amp 12 is disabled by a disable signal, the op-amp turns off transistor 22 to allow output node 24 to have a high impedance. Therefore, the output voltage Vout can be pulled up to approximately the digital supply voltage level Vcc by an external resistor or current source (not shown). FIG. 2 shows a voltage stabilized low level driver 30 according to a second embodiment of the invention. Driver 30 is a variation of driver 10 in FIG. 1. In addition to op-amp 12 and NMOS transistor 22, driver 30 includes an output protection circuit 32, input protection circuits 34 and 36, and a slew rate control circuit 38. Output protection circuit 32 is placed in series with transistor 22. Two input protection circuits 34 and 36 are placed in series with the two input terminals of op-amp 12, respectively, to maintain symmetry and noise rejection. In addition, slew rate control circuit 38 is connected between output node 24 and the gate of transistor 22. In FIG. 2, when op-amp 12 is enabled, it acts as a feedback mechanism driving the gate of transistor 22 high to turn the transistor on. Slew rate control circuit 38 limits how quickly transistor 22 can be turned on. As the voltage Vout at output node 24 falls to the reference voltage Vref, op-amp 12 reduces the gate voltage of transistor 22 to the point that transistor 22 sinks just enough current from output node 24 to make the output voltage Vout match the reference voltage Vref. For convenience, an industry standard type band-gap reference is used to generate the reference voltage, Vref. In specific example, Vref is 0.52 V. The band-gap is also used to generate a reference current Iin (shown in FIG. 3) to set the tail current in the op-amp. Other types of reference voltage and current may also be used with little or no effect on the circuit behavior. The voltage stabilized low level driver according to the invention provides 100 mV stability of output low level independent of temperature, Vcc, load current and load capacitance. FIG. 3 shows the schematics of driver 30 in FIG. 2. In FIG. 3, an input reference current Iin is reflected using a current mirror comprised of transistors M138 and M139 to provide the tail current for the input pair of transistors M140 and M141. Resistor R150 and NMOS transistor M154 comprise the secondary input gate protection in addition to primary ESD (electrostatic discharge) protection circuit (not shown). R150 and Ml 54 are matched with resistor R149 and transistor Ml 53 for noise immunity considerations. The output currents from the input pair M140, M141 flow through diode wired transistors M158 and M159 and are mirrored onto transistors M160 and M161, respectively. The current through Ml 60 is reflected through a current mirror comprised of transistors M142 and M143 to become the pull-up current which is summed against the pull-down current of M161 for the gate drive of transistor M157, which is the output NMOS transistor. The op-amp frequency compensation is provided by capacitor 1146 and resistor R148. Transistors M144, M145, M162, and M156 are used to disable the pull-up current . mirror M142 and M143 and to pull the gate of the output NMOS transistor M157 down when the output NMOS transistor M157 is switched off. Diode wired transistors M182 and M155 along with capacitor 1147 and resistor R151 comprise the slew rate control circuit which limits the slew rate of the output high-to-low transition as transistor Ml 57 turns on. FIG. 4 shows a repeater 50 according to a third embodiment of the present invention. It illustrates the use of the voltage stabilized low level driver of the present invention in an I 2 C bus interface application. An I 2 C bus is an industry standard bus interface developed by Philips Corporation which allows integrated circuits to communicated directly with each other via a simple bi-directional 2-wire bus. Interfacing devices in a I 2 C based system can be achieved by directly connecting them to the two bus lines: a serial data line (SDA) and a serial clock line (SCL). In FIG. 4, repeater 50 comprises four identical I O cells, 52A, 52B, 52C, and 52D. Cells 52A and 52B are connected to each other on the SDA line between I/O pads 54A and 54B. Similarly, cells 52C and 52D are connected on the SCL line between I/O pads 54C and 54D. Each cell includes a voltage stabilized low level driver and a low level comparator. For example, cell 52A includes a voltage stabilized low level driver 58A and a low level comparator 60A. A bandgap reference block 56 is connected to the blocks in each I/O cell. Bandgap reference block 56 generates bandgap reference derived voltages Vref and VR, as well as a reference current (not shown) for the op-amps in drivers 58A, 58B, 58C and 58D. When a low signal Li (e.g., a voltage less than 0.4 V) is supplied at pad 54A via SDA line, for example, low level comparator 60A compares it with a bandgap reference derived voltage, VR (e.g., 0.45 V). After determining that Li is less than VR, comparator 60A outputs a low signal Li to voltage stabilized low level driver 58B. The low signal Li from comparator 60 A causes driver 58B to turn on by enabling the op-amp in driver 58B, which in turn pulls pad 54B to a low level L2 to match Vref (e.g., 0.52 V). Vref, which is also a bandgap reference derived voltage, is higher than Li received at pad 54A and is thus treated as a high signal by comparator 60B. As a result, after determining that L2 from pad 54B is greater than VR, comparator 60B outputs an internal high signal Hint (approximately equal to a digital supply voltage Vcc) to driver 58A. High signal Hint causes driver 58A to remain off. Thus, the output of driver 58 A is off. Therefore, the voltage at pad 54A remains at Li. This allows latch-up free I O pads to be achieved. When an external high signal Hext (e.g., a voltage greater than 0.45 V) caused by an external pull-up resistor or current source appears at pad 54A, comparator 60A sends a high signal Hint to driver 58B after comparing Hext with VR. The high signal Hint causes driver 58B to turn off. Therefore, the output of driver 58B and pad 54B are pulled up to Hext by an external pull-up resistor or current source (assuming the pad is not otherwise pulled down by other circuits). Comparator 60B compares Hext at pad 54B with VR and outputs an internal high signal Hint to driver 58A. The internal high signal Hint causes driver 58A to stay off. Thus, the output of driver 58 A remains off. Therefore, the voltage at pad 54A remains at Hext caused by the external pull-up resistor or current source. This allows latch-up free I/O pads to be achieved. The operations of cells 52C and 52D on the SCL line are similar to the operations of 52A and 52B on the SDA line described above and the description is therefore omitted. By using the repeater of the present invention, additional capacitive loads are allowed to be added to the I 2 C bus interface (which has a limitation on the total allowed capacitive loads). This is achieved by splitting the capacitive loads on the SDA and SCL lines so that the total capacitive loads may be doubled. While the invention has been described in conjunction with specific embodiments, it is evident that many alternatives, modifications and variations will be apparent to those skilled in the art in light of the foregoing description. Accordingly, it is intended to embrace all such alternatives, modifications and variations as fall within the spirit and scope of the appended claims.

Claims: CLAIMS: 1. A voltage driver having an output node, comprising: a switching circuit (22) having a control terminal and an output terminal coupled to the output node; and an operational amplifier (12) having a first input terminal connected to the output node, a second input terminal connected to an input reference voltage, and an output terminal connected to the control terminal of the switching circuit, the amplifier being controlled by an external disable signal for switching on and off the amplifier; wherein the amplifier, upon being switched on, drives the control terminal of the switching circuit to cause the output node to match the reference voltage; wherein the amplifier, upon being switched off, drives the control terminal of the switching circuit to cause the output node to have a high impedance. 2. The driver of claim 1, wherein the switching circuit is a transistor, and the control terminal is a gate terminal of the transistor. 3. The driver of claim 1, wherein the high impedance of the output node allows the output node to be pulled up by an external device to a predetermined level. 4. The driver of claim 1, further comprising a slew rate circuit (38) coupled between the output node and the control terminal of the switching circuit. 5. A voltage driver having an output node, comprising: a switching circuit (22) having a control terminal and an output terminal; an operational amplifier (12) having a first input terminal, a second input terminal, and an output terminal that is connected to the control terminal of the switching circuit, the amplifier being controlled by an external disable signal for switching on and off the amplifier; an output protection circuit (32) coupled between the output node and the output terminal of the switching circuit; a first input protection circuit (36) coupled between the first input terminal of the amplifier and the output node; and a second input protection circuit (34) coupled between the second input terminal of the amplifier and an input reference voltage; wherein the amplifier, upon being switched on, drives the control terminal of the switching circuit to cause the output node to match the reference voltage; wherein the amplifier, upon being switched off, drives the control terminal of the switching circuit to cause the output node to have a high impedance. 6. The driver of claim 5, further comprising a slew rate control circuit (38) coupled between the output node and the control terminal of the switching circuit. 7. The driver of claim 6, wherein the switching circuit is a transistor, and the control terminal is a gate terminal of the transistor. 8. The driver of claim 5, wherein the high impedance of the output node allows the output node to be pulled up by an external device to a predetermined level. 9. The driver of claim 7, wherein the first and second input protection circuits maintain symmetry and noise rejection. 10. A repeater (50) having first and second ends, comprising: a first I/O cell (52A) including: a first voltage driver (58A) having a first input terminal, a second input terminal connected to a first reference voltage and an output terminal coupled to the first end, and a first comparator (60A) having its first input terminal coupled to the first end and its second input terminal coupled to the second reference voltage less than the first reference voltage, the first comparator receiving an input signal via the first end and outputting a first result signal at its output terminal based on comparison of the input signal with the second reference voltage; and a second I/O cell (52B) including: a second voltage driver (58B) having its first input terminal coupled to the output terminal of the first comparator, its second input terminal coupled to the first reference voltage, and its output terminal coupled to the second end, the second voltage driver receiving the first result signal and outputting a second driving signal, via its output terminal, to the second end, and a second comparator (60B) having its first input terminal coupled to the second end, its second input terminal coupled to the second reference voltage, and its output terminal coupled to the first input terminal of the first voltage driver, the second comparator receiving the first driving signal and outputting a second result signal, via its output terminal, to the first voltage driver based on comparison of the first driving signal and the second reference voltage; wherein the first voltage driver receives the second result signal and outputs a first driving signal, via its output terminal, to the first end. 11. The repeater of claim 10, further comprising: a third I O cell (52C) identical with the first I/O cell; and a fourth I/O cell (52D) identical with the second I/O cell and connected to the third I/O cell in the same way as the first and second I/O cells are connected. 12. The repeater of claim 11, wherein the first and second VO cells are used on a SDA line of an I2C bus interface. 13. The repeater of claim 12, wherein the third and fourth I/O cells are used on a SCL line of an I2C bus interface.

Inventors: ANDERSON ALMA, ANDREWS HOWARD, ANDERSON, ALMA, ANDREWS, HOWARD
Applicants: KONINKL PHILIPS ELECTRONICS NV, KONINKLIJKE PHILIPS ELECTRONICS N.V.
Application year: 2001
Main classification: H03K17
IPC codes: H03K5, H03K17, H03K19