SECONDARY REORDER BUFFER MICROPROCESSOR

Abstract: A method, processor, and data processing system for enabling maximum instruction issue despite the presence of complex instructions that require multiple rename registers is disclosed. The method includes allocating a first rename register from a first reorder buffer for storing the contents of a first register affected by the complex instruction. A second rename register from a second reorder buffer is then allocated for storing the contents of a second register affected by the complex instruction. In an embodiment in which the first reorder buffer supports a maximum number of allocations per cycle, the allocation of the second register using the second reorder buffer prevents the complex instruction from requiring multiple allocation slots in the first reorder buffer. The method may further include issuing a second instruction that contains a dependency on a register that is allocated in the secondary reorder buffer. In one embodiment, reorder buffer information indicating the second instruction's dependence on a register allocated in the secondary reorder buffer is associated with the second instruction such that, when the second instruction is issued subsequently, the reorder buffer information is used to restrict the issue unit to checking only the secondary reorder buffer for dependencies.

Description: SECONDARY REORDER BUFFER MICROPROCESSOR BACKGROUND Field of the Invention The present invention generally relates to the field of microprocessors ana more particularly to a microprocessor utilizing a secondary reorder buffer for instructions with multiple targets. Background of the Invention The use of reorder buffers in microprocessors to enable out-of-order execution is well known. See, e.g., Hennessy & Patterson, Compu ter Archi tect ure a Quan ti ta tive Approach, pp. 309-317 (Morgan Kaufmann 2d ed. 1996) . Reorder buffers are used to store results of executed instructions until an instruction s finally committed. Many superscalar processors allow multiple instructions to issue in a single cycle. To achieve maximum performance, rename register allocation for each issued instruction should occur in the cycle m which tne instruction is issued. Typically, each issued instruction affects the contents of a single register in tne microprocessor and therefore requires ust a single rename register entry. In other cases, however, an instruction (referred to herein as a complex instruction) affects the contents of two or more registers. Register renaming for these complex instructions should also occur in tne issue cycle if optimum performance is to be achieved. Unfortunately, the renaming buffers employed in conventional microprocessors are limited in the number of allocations they can perrorm in a single cycle. This limitation on the number of rename allocations that can occur in a single cycle coupled with the existence of instructions requiring multiple allocations complicates the issue unit and can result m the issue unit being unable to issue the maximum number of instructions in a particular cycle if one of the instructions is a complex instruction. DISCLOSURE OF THE INVENTION Accordingly tne invention provides a method of executing instructions n a microprocessor, comprising: issuing an instruction affecting the contents of multiple registers; allocating a first rename register from a first reorder buffer for storing the contents of a first register affected py tne instruction; allocating a second rename register from a second reorder buffer for storing the contents of a second register affected by the instruction; wherein the allocation of the second rename register using the second reorder buffer prevents the instruction from consuming multiple allocation slots m the first reorder buffer. The invention further provides a processor comprising: an issue unit configured to receive instructions from an instruction cache and adapted to issue instructions for execution; a first reorder buffer dedicated for allocating rename registers for a primary register of an instruction; and a second reorder buffer dedicated for allocating rename registers for a secondary register of an instruction; wherein the issue unit is configured to allocate, upon issuing a complex instruction affecting the contents of at least two registers, a rename register in the first reorder buffer for a primary register of the instruction and a rename register in the second reorder buffer for a secondary register of the instruction. The invention yet further provides a data processing system comprising: system memory; input means; a display; and the processor described above. Preferably the invention provides a microprocessor capable of issuing the maximum number of instructions per cycle regardless of whether the instructions include simple instructions, complex instructions, or a combination of both. In an embodiment in which the first reorder buffer supports a maximum number of allocations per cycle, the allocation of the second register using the second reorder buffer prevents a complex instruction from requiring multiple allocation slots in the first reorder buffer. The method may further include issuing a second instruction that contains a dependency on a register that is allocated in the secondary reorαer buffer. In one embodiment, reorder buffer information indicating the second instruction' s dependence on a register allocated in the secondary reorder buffer is associated with the second instruction such that, when the second instruction is issued subsequently, the reorder buffer information is used to restrict the issue unit to checking only the secondary reorder buffer for dependencies. BRIEF DESCRIPTION OF THE DRAWINGS Embodiments of tne prf sent invention will now be described in detail, by way of example only, and with reference to the following drawings : FIG 1 is a block diagram of a data processing system; FIG 2 is a block diagram of a processor suitable for use in the data processing system of FIG 1; FIG 3 .s a block diagram of a reorder burfer including a primary reorder buffer and a secondary reorder suffer according to one embodiment of tne present invention; and FIG 4 is a flow diagram illustrating the operation of one embodiment of the invention. DETAILED DESCRIPTION OF THE INVENTION Referring now to FIG 1, an embodiment of a data processing system 100 according to tne present invention is deoicted. System 100 has one or more centra, processing units (processors) 101a, 101b, 101c, etc. (collectively or generically referred to as processor (s) 101. In one embodiment, each processor 101 comprises a reduced instruction set computer (RISC) microprocessor. Additional information concerning RISC processors m general is available in C. May et al . Ed., PowerPC Archi tecture : A Specifica tion for a New Fam±ly of RISC Processors, (Morgan Kaufmann, 1994 2d edition) . Processors 101 are coupled to system memory (RAM) 250 and various other components via system bus 113. Read only memory (ROM) 102 is coupled to the system bus 113 and includes a basic input/output system (BIOS), wh ^ ch controls certain basic functions or system 100. FIG 1 further depicts an I/O adapter 107 and a network or communications adapter 106 coupled to the system bus 113. I/O adapter 107 is, for example, a small computer system interface (SCSI) adapter that communicates with a hard disk 103 and/or tape storage drive 105. I/O adapter 107, hard disk 103, and tape storage device 105 are collectively referred tc Herein as mass storage 104 (see figure 2) . The network adapter 106 interconnects bus 113 with an outside network enaol ^ ng data processing system 100 to communicate with otner sucn systems. Display monitor 136 is connected to system DUS 113 oy display adapter 112, which may include a graphics adapter to improve the performance of graphics intensive applications and a video controller (both not shown) . In one embodiment, adapters 107, 106, and 112 are connected to one or more I/O busses tnat are connected to system bus 113 via an intermediate bus bridge (not shown) . Suitable I/O busses for connecting peripheral devices such as hard disk controllers, network adapters, and grapnics adapters include tne Peripheral Components Interface (PCI) bus according to PCI Local Bus Specification Rev. 2.2 available from the PCI Special Interest Group, Hillsboro OR, and incorporated by reference herein. Additional input/output devices are shown as connected to system bus 113 via user interface adapter 108 and display adapter 112. A Keyboard 109, mouse 110, and speaker 111 all interconnected to cus 113 /ιa user irterface adapter 108, which may include, for example, a Superl/O ch_.p integrating multiple device adapters into a single integrated circuit. For additional information concerning one such chip, the reader is referred to the PC87338/ τ=C97338 ACPI 1 . 0 and PC98/99 Compl ian t Superl/O data sheet from National Semiconductor Corporation (Novemoer 1998) at www.national.com. Thus, as configured in FIG 1, system 100 includes processing means n the form of processors 101, storage means including system memory 250 and mass storage 104, input means sucn as keyboard 109 and mouse 110, and output means including speaker 111 and display 136. In one embodiment a portion of system memory 250 and mass storage 104 collectively store an operating system, such as tie IX'S) operating system from IBM Corporation, to coordinate the functions of the various components shown .n FIG 1. Additional detail concerning the AIX operating system is available in A IX Version 4 . 3 Technica l Reference : Base Opera ting Sys tem and Ex tensions , Vol umes 1 and 2 (order numbers SC23-4159 and SC23-4160); AIX Versi on 4 . 3 Sys tem User ' s Guide : Communica tions and Networks (order numoer SC23-4122); and AIX Version 4 . 3 System User ' s Guide : Opera ting Sys tem and Devices (order numϋer SC23-4121) from IBM Corporation at www.ibm.com and incorporated oy reference nerein. Turn_ng now to FIG 2, a simplified Dlock diagram of an embodiment of processor 101 suitaole for jse m system 100 is presented. In the depicted embodiment, processor 101 comprises an integrated circuit superscalar microprocessor fabricated on a monolithic semiconductor substrate. Processor 101 includes various execution units, registers, buffers, memories, anc other functional units as discussed in greater detail below. As illustrated in FIG 2, processor 101 is coupled to system bus 113 v a bus interface unit (BIU) 212 and processor bus 213, which like system DUS 113 includes address, data, and control buses. BIU 212 controls the transfer of information between processor 101 and other devices coupled to system PUS 113, such as system memory 250 and mass storage 104. It w ll be appreciated that processor 101 may include other devices coupled to system bus 113 that are not necessary for an understanding of the following description and are accordingly omitted for the sake of simplicity. BIU 212 is connected to instruction cache and memory management unit (MMU) 214 and data cache and memory management unit 216 within processor 101. High-speed caches, such as those witnm instruction cache 214 and data cacne 216, enaole processor 101 to acnieve relatively fast access times to a subset of data or instructions previously transferred from system memory 250, thus improving the speed of operation of data processing system 100. Data and instructions stored within data cache 216 and instruction cache 214, respectively, are identified and accessed by address tags, whicn each comprise a selected number of bits (typically the high-order bits) of the system memory physical address n whicn the data or instructions reside. Sequential fetch unit 217 retrieves instructions for execution from instruction cache 214 during each clock cycle. In one embodiment, if sequential fetch un t 217 retrieves a branch instruction from instruction cacne 214 the branch instruction is forwarded to branch processing unit (BPU) 218 for execution. Sequential fetcn unit 217 forwards non-branch instructions to an instruction queue 219, where the instructions are stored temporarily pending execution by other functional units of processor 101. A dispatch unit 220 s responsible for retrieving stored instructions from queue 219 and forwarding the instructions to an issue unit (ISU) 221. Dispatch unit 220 scnedules dispatch of instructions to issue unit 221 based, in part, on instruction completion information received from a completion unit 240. The depicted embodiment of ISU 221 includes one or more issue queues 222a, 222b, 222c, etc. (collectively or geneπcally referred to issues queue(s) 222). ISU 221 is responsible for maintaining fully loaded pipelines by issuing new instructions m each cycle to the execution un ts whenever possible. In one embodiment, instructions are issued from ISU 221 out-of-order. In the depicted embodiment, the execution circuitry of processor 101, _n addition to BPU 218, includes multiple functional units for executing sequential instructions, including flxed-pomt-unit (FXU) 223, load/store unit (LSU) 228, ana floating-point unit (FPU) 230. Each c: execution units 223, 228 and 230 typically executes one or more instructions of a particular type during each processor cycle in a pipelined fasnion. For example, FXU 223 performs f xed-pomt mathematical and logical operations such as addition, suotraction, ANDing, ORmg, and XORing, utilizing source operands received from specified general purpose registers (GPRs) 232. E'ollowmg the execution of a fixed-point instruction, FXU 223 outputs the data results of the instruction to GPR buffers 232, which provide storage for the result received on result ous 262. The FPU 230 typically performs single and double-precision floatmg-DOint arithmetic and logical operations, sucn as floating-point multiplication and division, on source operands received from floating-point registers (FPRs) 236. FPU 230 outputs data resulting rrom the execution of floating-point instructions to selected F?R Duffers 236, which store tne result data. As its name implies, LSU 228 typically executes floating-point and fixed-point load instructions, which oac data from data cache 216, a lower level cache memory (not depicted), or system memory 250 into selected GPRs 232 or FPRs 236 or and floating-point and fixed-oomt store instructions, which store data from a selected one of GPRs 232 or FPRs 236 to data cache 216 and, ultimately, to system memory 250. In the preferred embodiment, processor 101 employs out-of-order instruction execution to further improve tne performance of its superscalar architecture. Accordingly, instructions can oe executed oγ FXU 223, LSU 228, and FPU 230 in an order that varies from the oπαi"ai program order of the instructions as long as data dependencies ar^ observed. As indicated previously, instructions are processed oy eacn or FXU 223, LSU 228, and FPU 230 as a sequence of pipeline stages. I >~ one embodiment, processor 101 includes five distinct pipeline stages, namery, fetch, αecode/dispatch, execute, finisn, and completion. Curing tne fetch stage, sequential fetch unit 217 retrieves one or more non-brancn instructions from instruction cache 214 and stores tne fetched instructions within instruction αueue 219. In contrast, sequential fetch unit 217 forwards any branch instructions from the instruction stream to BPU 218 for execution. BPU 218 includes a brancn prediction mecnanism that includes, in one emoodiment, a dynamic prediction mecnanism sucn as a branch history table that enaoles BPU 218 to speculatively execute unresolved conditional branch instructions by predicting wnetner or not the brarch will be taken. During the decode/d Lspatch stage, dispatch un t 220 and ISU 221 decode and issue one or morr> instructions from issue queues 222 to execution units 223, 228, and 230, typically in program order. ISU 221 may allocate one or more rename buffers within GPR rename buffers 233 or FPR rename Duffers 237 for temporarily storing the result (or results) of an instruction prior to committing the result or results to GPRs 232 and FPRs 237. In addition, instructions (or instructions identifiers or tags representative of the instructions) may be stored within a multiple-slot completion ouffer (the completion table) of completion unit 240 as a means of tracking which instructions have completed. During the execute stage, execution units 223, 228, and 230 execute instructions issued from ISU 220 opportun_stιcally as operands and execution resources for the indicated operations become available. In one embodiment, each of execution units 223, 228, and 230 are equipped with a reservation station that stores instructions dispatched to that execution unit until operands or execution resources become available. After execution of an instruction has terminated, execution units 223, 228, and 230 store data results, if any, within either GPRs or FPRs, depending upon the instruction type. In the depicted embodiment, execution units 223, 228, and 230 notify completion un_.t 240 which instructions have finisned execution. Finally, instructions are completed in program order out of the completion table of completion unit 240. Instructions executed by FXU 223 and FPU 230 are completed oγ transferring data results of the instructions from GPR rename buffers 233 and FPR rename buffers 237 to GPRs 232 and FPRs 236, respectively. Processor 101 preferably supports out-of-order speculative instruction execution. Instructions may be speculative on a predicted brancn direction or speculative beyond an instruction tnat may cause an interrupt condition. In the event of a branch misprediction or an interrupt, hardware automatically flushes undesired instructions from the pipelines and discards undesired results, presenting the effect of precise exceptions and sequentially executed instructions down the appropriate branch patns . Incorrect speculative results are selectively flusned from all units m one clock cycle, and instruction issue can resume the following c_ock cycle. Processor 101 may include multiple load units and a single store unit. However, it should oe clear to one skilled m the art that processor 101 coulc comprise other configurations such as a single load/store unit, etc. When an instruction is issued, the ISU 221 tags the instruction in such a manner that relative age between any two instructions can be easily determined. In one embodiment, sequential instructions are tagged with integer values ( ITAGs ;. In addition to providing a mecnanism for determining the issue order and relative age of issued instructions, ITAGs provide a shorthand representation of their corresponding instructions. The ITAG value of each instruction is associated with queue entries and pipeline stages n wnich it resides. The use of ITAGs fac.litates an instruction flush mechanism (in response to a processor-generated flush instruction) m which a magnitude comparison between the ITAG associated with the flush instruction and tne ITAG associated with a particular queue entry or functional unit stage is performed and the entry invalidated if it s for an instruction which is as young or younger than (i.e., issued s multaneously or after) tne f±usneα instruction. All remnants o c the flushed instruction (and all suϋsequent instructions) are "flushed" from the machine and the fetcn unit is redirected to the fetch starting at tne address of the "flushed" instruction. One embodiment of the present invention contemplates a metnod of handling instruction issue and register ren ming for instructions requiring multiple rename entries. In many instruction sets, such as the PowerPC® instruction set, tne majority of mstruct_ons upcate the contents of just a single register. (Detailed in orma ion regarding tne PowerPC? instruction set is available m the PowerPC 6PC RISC Mi croprocessor User ' s Man ua l available from Motorola, Inc. (Order Mo. MPC620UM/AD) , wnich is incorporated by reference nerei' , . Such instructions, thererore, require only a single rename register entry + ■ o store the instruction's result temporarily until the result is committed t GPR 232. In superscalar machines employing multiple, paralle. execution units and enaoled to issue multiple instructions per cycie, tne one-to-one correspondence between ar instruction and tne rename register allocated for its res .: simpliries the issue and rename allocation process. If a processor is capaole of issuing four instructions per cyc_e, for example, register rename control logic is designed to allocate up to four rename registers per cycle. The issue/rename mecnanism becomes mere complicated, nowever, f the instruction set also includes one or more instructions that require tne allocation of multiple rename registers. In the PowerPC-?' instruction set, for example, some instructions affect the contents of two registers (tne result registers). For purposes of this disclosure, instructions affecting tne contents of multiple registers are referred to as comp ex instructions. If tne processor is to fully support out-of-order execution, each of the result registers must be a_locateo a rename register in the cycle when a complex instruction is issued. Conventionally, the multiple rename registers required for complex instructions prevented other instructions from issuing m the cycle when the complex instruction issued. The issue logic was required to determine whether the total number of rename registers required to be allocated during a given cyc.e exceeded a specified maximum. If, for example, a processor was capable of issuing four "simple" instructions (i.e., instructions that affect the contents of just a single register) per cycle (and allocating four rename registers in that cycle) and the processor's issue unit issued a complex instruction, the issue unit would be required to prevent the other three issue slots from all issuing instruction n the same cycle. In other words, the processor would have to prevent one of the three remaining issue slots from issuing an instruction and would further have to ensure that the two remaining issue slots did not issue complex instructions themselves. Thus, the presence of complex instructions in a multiple issue superscalar microprocessor increased the complexity of the issue __ogιc and negatively affected performance by preventing the maximum number of instructions from issuing n a single cycle . Turning now to FIG 3, a reorder buffer 300 according to one emoodiment of the present invention is depicted. Reorder buffer 300 includes a primary reorder buffer 302 and a secondary reorder buffer 303. The primary reorder puffer 302 contains primary rename GPRs 304 while the secondary reorder bufter 303 contains secondary rename GPRs 306. The combination of primary rename GPRs 302 and secondary rename GPRs 304 comprise the rename GPRs indicated by reference numeral 233 in FIG 2. (Although tne depicted embodiment of reorder buffer 300 is specific to rename GPRs 233, reorder buffer 300 may include rename FPRs 237 instead or in addition to the rename GPRs 233) . In the preferred emoodiment, all rename registers for simple instructions are allocated m primary reorder buffer 302. In addition, the primary reorder buffer 302 is also used to allocate a primary rename register 304 for a primary register associated with eacn complex instruction. The secondary reorder buffer 303, on the other hand, is not useo when a simple instruction is issued but is used to allocate a secondary rename register 306 for a secondary register of a complex instruction. If, as an example using the PowerPC instruction set, a simple load instruction LOAD RT, RA, RB is issued, a rename register 304 is allocateα when the instruction issues to hold the result of the instruction until the instruction is ultimately committed (i.e., wnen the result is written to tne target register RT m GPR (register file) 232) . Because the load instruction ..n this example affects the contents of ust a single register, only a single rename register is required to be allocated. In a second example, a complex instruction sucn as Load with Update (LU) instruction is issued (e.g., LU RT, RA, RB) . The load with update instruction calculates an effective address cased on the contents of registers RA and RB and loads the target register RT with the contents of the memory location with the calculated effective address. In addition, the instruction updates the contents of RA witn the value of the calculated effective address. The LU instruction is useful m a variety of circumstances including the implementation of software loops by providing a single instruction that automatically increments the source memory address each time the instruction is executed. The LU instruction is a complex instruction because _t affects the contents of two registers and therefore requires two rename registers to be allocated when issued. In the depicted embodiment, the operand information in registers A and B is read from a dual ported register file 232. In this example, however, a primary rename register 304 m primary reorαer buffer 302 is allocated for the target register RT whiie a seconαary rename register 306 is allocated in secondary reorder bufrer 303 for tne secondary register (RA) va.ue. In comparison, a conventionally designed processor would be forced to allocate registers for ootn the RT and RA registers in the (Single) reorder buffer wnen the instruction issues. Because the processor is only able to allocate a specified number of registers per cycle, and because the LU instruction consumes two of tnese allocation s ots, the conventional processor wouxd undesirably oe torced to issue fewer tnan the maximum allowable number of instructions C ring tne cycle .n which tne LL instruction issued. Although the example uses an LU instruction, 'nose familiar with t^e PowerPC instruction set and other instruction sets tnsi contain one or more complex instructions wιl_. appreciate that any instruction affecting toe contents of two registers would benefit from t h e inclusion of a secondary reorder buffer as α.sclosed herein. The incorporation of an additional resource m the form of secondary reorder buffer 303 for register renaming beneficially enables processor 101 to issue tne maximum allowable number of instructions in eacn cycle (assuming the maximum number of instructions are ready to issue;, without regard to whether the instructions are simple, complex, or a combination thereof. In tne aosence of tne resource provided oy secondary reorder buffer 303, the issue of a complex instruction would require al Location or multiple rename registers m the processor's (single) reorder bufrer. Because the numoer of rename registers that a single reorder buffer can allocate m a single cycle is architectura ly limited, the complex instruction would prevent the processor rrcrr issuing the maximum numoer of instructions in the cycle in wnich a complex instruction is issued. Moreover, the intelligence necessary to determine what number of instructions, in the presen e of complex instructions, is permitted to issue m any given cycle significantly increases the complexity required of tne issue logic. The presence of secondary reorder buffer 303 necessitates a mechanism by which instructions determine whether any of their operand registers are currently allocated n tne secondary reorder buffer 303. In one embodiment, processor 101 simply requires each instruction that is issued while a complex instruction is m-flight to search both reorder buffers to determine any dependencies. While this embodiment enjoys the advantage of simplicity, it undesirably increases the number of reorder buffer entrres that are searched during the issue cycle. As the number of instructions that can issue m any given cycle increases, it becomes increasingly desirable to minimize tne number or reorder buffer entries that must be examined to determine instruction dependencies. To address tnis problem, one embodiment of the invention contemplates a mechanism by which reorder buffer information is recorded during the first execution of an instruction. The reorder buffer information is then used during suosequent executions of tne instruction to determine which of the reorders buffers tne instruction must examine. Turning to FIG 4, a flow diagram illustrative of th s eiruoodiment is described with respect to the following code segment example: LQ Rd, R25, R26 ADD R7, R5, R2 Block 400 represents issuing tne LQ (load quad) instruction. The LQ instruction s a complex instruction in the PowerPC® instruction set that affects the contents of the indicated target register (Rl) as well as the next sequential register (R5 . Because the ADD instruction includes an R5 source operand, the ADD instruction is dependent upon tne LQ instruction. During a first execution of th_s code segment, the issue unit preferaoly forces all instructions following the LQ instruction (i.e., all instructions that are issued after the LQ instruction is issued but oerore the LQ instruction is committed) to search both reorder buffers to detect any deDendenc_.es . Thus, m olock 402, the issue unit detects the ADD instruction's dependency on R5, which is allocated ^ n a secondary rename register 306 of the secondary reorder buffer 303. Upon detecting a dependency m secondary buffer between the ADD instruction and the LQ instruction, issue unit 221 is configured to record (block 404) , reorder buffer information that indicates that the ADD instruction' s dependency was found m secondary reorder buffer 303. In one embodiment, tnis reorder buffer information is stored in a dedicated pit or set of bits m the instruction cache entry containing tne ADD instruction. When tne ADD instruction is subsequently executed (blocκ 406) , the reorder buffer information corresponding to the ADD instruction informs issue unit 221 that the ADD instruction's dependency is found in the secondary reorder buffer (as it was during the first execution) . In this manner, issue un_t 221 can advantageously restrict its search of reorder buffer 300 to secondary reorder oufrer 303. Although the example is described with respect to a LQ instruction, the mechanism is used in conjunction witn other complex instructions sucn as the PowerPC® LU instruction. Thus, by incorporating a secondary issue buffer m con j unction with a mechanism for selectively enabling and disabling tne secondary reorder buffer, the present invention oeneficially provides means tor enabling maximum instruction issue per cycle hi-st min-.mizj.rg t n e oerfor ance penal or the issue unit. It will ce apoarent to those skilled ±n the art having the oerefrt of this disclosure that the present invention, ^ n accordance with a preferred embodiment, contemplates simplified and improved performance of tne issue/rename techanism in a microprocessor periormarce oy implementing an additional rename facility to allocate secondary regj≤ters m a secondary rename scheme.

Claims: 1^ CLAIMS 1. A method of executing instructions in a microprocessor, comprising: issuing an instruction affecting tne contents of multiple registers; allocating a first rename register from a first reorder buffer for storing tne contents of a first register affected by the instruction; allocating a second rename register from a second reorder Duffer for storing the contents of a second register affected by the instruction; wherein the allocation of the second rename register using the second reorder ouffer prevents tne instruction from consuming multiple allocation slots m the first reorder buffer. 2. The method of claim 1, wherein the issued instruction comprises a complex instruction and wherein first reorder buffer supports a maximum number of allocations per cycle and wherein the issuing of the complex instruction comprises issuing a set of instructions including the complex instruction m a single cycle, wnerein tjhe number of instructions m tne set of instructions equals the maximum numoer of allocations per cycle supported by the first reorder ouffer. 3. The method of claim 2, wherein tne set of instructions may comprise any combination of complex instructions and simple instructions that affect the contents of a single register. 4. The method of claim 1 or claim 2, wnerein the issued instruction comprises a complex instruction and further comprising, sunsequent to issuing tne complex instruction, issuing a second instruction, wherein the second instruction is dependent upon the second rename register and, responsive thereto, associating reorder buffer information with the second instruction, wherein the reorder buffer information is indicative of the second instruction's dependence on a register allocated in the seconαary buffer . 5. The method of claim 4, further compr.sing, upon issuing the second instruction after recording the reorder ouffer information, using the reorder bufrer information to restrict tne seconα instruction's reorder lookup to the secondary reorder buffer. 6. The method of claim 2, wherein the allocation of the second rename register preserves first reorder buffer slots such that tne maximum number of instructions the processor can issue is independent of the instruction type. 7. A processor comprising: an issue unit configured to receive instructions from an instruction cache and adapted to issue instructions for execution; a first reorder buffer dedicated for allocating rename registers for a primary register of an instruction; and a second reorder bufter dedicated for allocating rename registers for a secondary register of an instruction; wnerein the issue unit is configured to allocate, upon issuing a complex instruction affecting the contents of at least two registers, a rename register in the first reorder buffer for a primary register of tne instruction and a rename register in tne second reorder buffer for a secondary register of the instruction. 8. The processor of claim 7, wherein the issue unit is further configured to check the primary ana second reorder buffers upon issuing = second instruction to determine whether the second instruction is dependent en the first instruction. 9. The processor of claim 8, wherein, upon detecting that the . ^ nα instruction is dependent upon a register allocated m the secondary reorder buffer, the issue unit records reorder buffer information in an instruction cache entry corresponding to tne second instruction, wherein the reorder ouffer information is indicative of tne second instruction' s dependence en an entry m the secondary reorder buffer. 10. The processor of claim 9, wherein tne issue unit is configured, upon subsequently issuing tne second instruction after recording tne reorder buffer information and responsive to the reorder buffer information, to check only tne secondary reorder buffer for dependencies. 11. A data processing system comprising: system memory; input means; a display; and a processor as claimed in any of claims 7 to 10.

Inventors: KAHLE JAMES ALLAN, KAHLE, JAMES, ALLAN
Applicants: IBM, IBM UK, IBM UNITED KINGDOM LIMITED, INTERNATIONAL BUSINESS MACHINES CORPORATION
Application year: 2001
Main classification: G06F9
IPC codes: G06F9