METHOD AND APPARATUS FOR ADJUSTING THE PHASE OF INPUT/OUTPUT CIRCUITRY

Abstract: Input/output clockphase adjustment circuitry for use with input/output circuitry of an integrated circuit chip. In one embodiment, an integrated circuit chip includes a phase adjustment circuit coupled to receive a system clock. The phase adjustment circuit generates an input/output clock coupled to be received by an input/output circuit of an integrated circuit chip for input/output data transfers in a system. The phase adjustment circuit includes a phase locked loop circuit coupled to receive the system clock through a first delay circuit. The input/output clock generated by the phase locked loop circuit is received through a second delay circuit at a feedback clock input of the phase locked loop circuit. The first and second delay circuits are used to control the phase of the input/output clock generated by the phase locked loo circuit relative to the system clock. In one embodiment, a third delay circuit is included in an input/output data path of the input/output circuit of the integrated circuit. The third delay circuit enables input and output data transmission from the integrated circuit to be clocked out of phase with the system clock.

Description: METHOD AND APPARATUS FOR ADJUSTING THE PHASE OF INPUT/OUTPUT CIRCUITRY BACKGROUND OF THE INVENTION Field of the Invention The present invention relates generally to the field integrated circuits and, more specifically, the present invention relates to input/output between integrated circuit chips. Background Information Currently, input/output (I/O) timing test of integrated circuit chips, such as central processing units (CPUs), are performed using testers. By using a carefully calibrated multi-channel tester, one measures I/O timing for all pins, where the testers and the on-die phase lock loop (PLL) share the same clock. The specification specified I/O timings are acquired by exercising different "worst-case" patterns, which are programmed during the tester setup. Furthermore, the tester environment is designed to mimic real system situations whenever possible. There are several drawbacks to measuring I/O timings in the tester environment. In order to get very accurate reading, all tester channels require extremely tight timing and careful calibration, adding to tester cost. Even then, a guard band must be added to the measured timings to guarantee specification numbers. This is to account for the uncertainties of strobe edges and clock skew introduced by the testers. The added guard- band in the specification numbers result in more stringent requirements for both circuit designers and system designers in order to avoid unqualified defects. Another problem associated with guard-band is that additional guard-band must be added to account for the difference between the tester and the real system environment because the measurements from the testers may not emulate the real system behavior effect on the I/O timing. Thus, the circuit designers, in many cases, are burdened with the additional challenges stemming from the tester requirements. When an integrated circuit chip, such as a CPU, fails I/O timing tests, the part is generally discarded. In many instances, all other functionality of the part is within the specification requirements. In addition, it has been observed that a significant portion of the parts that fail I/O timing tests fail by a relatively small margin. BRIEF DESCRIPTION OF THE DRAWINGS The present invention is illustrated by way of example and not limitation in the accompanying figures. Figure 1 is a block diagram illustrating one embodiment of a phase adjustment circuit and I/O buffer circuit in accordance with the teachings of the present invention. Figure 2 is a block diagram illustrating one embodiment ofa delay circuit in accordance with the teachings of the present invention. Figure 3 is a schematic illustrating one embodiment ofa delay chain circuit in accordance with the teachings of the present invention. Figure 4 is a block diagram illustrating another embodiment ofa delay circuit in accordance with the teachings of the present invention. Figure 5 is one embodiment of a timing diagram illustrating a clock to output characteristic of an output signal being tested in accordance with the teachings of the present invention. Figure 6 is a timing diagram of another embodiment of a clock to output characteristic of an output signal being tested in accordance with the teachings of the present invention. Figure 7 is a timing diagram illustrating one embodiment of a hold time of an output signal being tested in accordance with the teachings of the present invention. Figure 8 is a timing diagram illustrating one embodiment of a set up time of an output signal being tested in accordance with the teachings of the present invention. Figure 9 is a timing diagram illustrating one embodiment of overcoming a speed related I/O defect in accordance with the teachings of the present invention. Figure 10 is a timing diagram illustrating overcoming an 1/0 defect in an output signal in accordance with the teachings of the present invention. Figure 11 is a timing diagram illustrating yet another embodiment of overcoming a speed related defect in an output signal in accordance with the teachings of the present invention. Figure 12 is a timing diagram illustrating still another embodiment of overcoming a speed related I/O defect in an output signal in accordance with the teachings of the present invention. DETAILED DESCRIPTION Methods and apparatuses for using calibrated delay elements in I/O circuitry are disclosed. In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present invention. It will be apparent, however, to one having ordinary skill in the art that the specific detail need not be employed to practice the present invention. In other instances, well known materials or methods have not been described in detail in order to avoid obscuring the present invention. In an example embodiment, the clock driver is used to generate a system clock to clock I/O data transmissions between integrated circuit chips in the system. Integrated circuit chips in [the?] [this?] system receive the system clock and generate internal I/O clocks to clock I/O circuitry in the respective integrated circuit chips. In one embodiment, at least one of the integrated circuit chips in the system includes a phase adjustment circuit coupled to receive the system clock and generate an internal I/O clock having a selectable phase difference from the system clock. That is, in one embodiment of the present invention, the phase adjustment circuit adjusts the I/O clock to be out of phase with the system clock by a selectable amount. In the example embodiment, other chips in the system generate their own respective I/O clocks, which are in phase with the system clock. In an example embodiment, the phase adjustment circuit introduces the phase difference in the generated I/O clock from the system clock using calibrated delay elements. For instance, a calibrated delay element is coupled to a reference clock input of a phase lock loop circuit of the phase adjustment circuit and another calibrated delay element is coupled to a feedback clock input of the phase lock loop circuit. Using the calibrated delay elements coupled to the reference clock input and feedback clock input of the phase lock loop circuit, the phase difference can be selectively introduced into the I/O clock generated by the phase adjustment circuit. In one embodiment, the I/O buffer circuit of the integrated circuit chip also includes a calibrated delay circuit in an I/O data path of the I/O buffer circuit. In one embodiment, the calibrated delay element is included in an output data path of the I/O data buffer circuit. In another embodiment, the calibrated delay element may be included in an input data path of the 1 0 buffer circuit. In one embodiment, the phase adjustment circuit is used to shift the I/O clock of the integrated circuit from the system clock. Thus, the I/O buffer circuit of the integrated circuit is clocked out of phase relative to the I/O buffer circuits of other integrated circuit chips in the system by a selectable amount. In one embodiment, the calibrated delay element in the I/O data path of the I/O buffer circuit of the integrated circuit provides the effect of input data transmissions to the integrated circuit to be clocked out of phase with output data transmissions from the integrated circuit. Using the phase adjustment circuit and the delay circuit in the I/O buffer circuit of the integrated circuit chip in accordance with the teachings of the present invention, control of the phase of input and output data transmissions of the integrated circuit chip are provided. By adjusting the phase of the I/O data transmissions, I/O timing tests of the integrated circuit chip may be performed. In addition, the ability to adjust the timing of I/O operations in the integrated circuit chip enable the integrated circuit chip to be fine tuned to meet timing specification requirements of systems in which the integrated circuit chip would otherwise fail to meet. To illustrate, Fig. 1 is a block diagram of one embodiment ofa system 101 in accordance with the teachings of the present invention. In one embodiment, system 101 includes a motherboard, systemboard or the like including a plurality of integrated circuit chips 103 and 105. In an example embodiment, integrated circuit chip 103 is a central processing unit (CPU) and integrated circuit chip 105 is a chip of chip set. As shown in Fig. 1, system 101 includes a clock driver 107, which generates a system clock 109 that is coupled to be received by integrated circuit chips 103 and 105 of system 101. In the example embodiment of Fig. 1, integrated circuit chip 103 includes an I/O buffer circuit 113 and integrated circuit chip 105 includes an I/O buffer circuit 115. I/O buffer circuits 113 and 115 are coupled to one another to provide I/O data transmissions between integrated circuit chips 103 and 105 of system 101. In the example embodiment, I/O buffer circuit 115 is clocked in response to I/O clock 149, which is generated by phase lock loop circuit 147. In the example embodiment, I/O clock 149 of integrated circuit chip 105 is in phase with system clock 109. In an example embodiment of the present invention, I/O buffer circuit 113 is clocked in response to I/O clock 129. In the example embodiment, I/O clock 129 is generated by phase adjustment circuit 111. In one embodiment, I/O clock 129 may be generated by phase adjustment circuit 111 to be out of phase with the system clock 109 by a selectable amount responsive to phase control information 117. Therefore, I/O clock 129 may be out of phase with the other 1/0 clocks of system 101, including I/O clock 149 in accordance with the teachings of the present invention. As illustrated in Fig. 1, one embodiment of phase adjustment circuit 111 includes a phase lock loop circuit 123 coupled to receive system clock 109 through delay circuit 125 at a reference clock input of phase lock loop circuit 123. Phase lock loop circuit 123 generates I/O clock 129, which is coupled to be received at a feedback clock input of phase lock loop circuit 123 through delay circuit 127. In the illustrated embodiment, delay circuits 125 and 127 control the phase of I/O clock 129 in response to phase control information 117. In one embodiment, phase control information 117 includes a forward delay control signal 119, which is coupled to be received by delay circuit 125, and a feedback delay control signal 121, which is coupled to be received by delay circuit 127. As shown in the illustrator's embodiment, I/O buffer circuit 113 includes an input data path from which input data 143 is received from input buffer 137 through latch 131. In the illustrated embodiment, the output data path of I/O buffer circuit 113 includes an output buffer 135, which is coupled to receive output data 145 through latch 133. As illustrated, latches 131 and 133 are clocked in response to I/O clock 129. In one embodiment, a delay circuit 139 is included in an I/O data path of I/O buffer circuit 113. For example, in the embodiment illustrated in Fig. 1, delay circuit 139 is coupled between latch 133 and output buffer 135 of the output data path. In the illustrated embodiment, delay circuit 139 provides a delay in the output data path in response to output delay control signal 141. In another embodiment, (not shown) delay circuit 139 may be included in an input data path of I/O buffer circuit 113. In the illustrated embodiment, phase lock loop circuit 147 receives system clock 109 at a reference clock input and I/O clock 149 is generated in phase with the system clock 109 and is received at a feedback input of phase lock loop circuit 147. I/O buffer circuit 115 of integrated circuit chip 105 includes an output buffer 157 coupled to receive output data 161 through latch 153. I/O buffer circuit 115 includes an input buffer 155 through which input data 159 is received through latch 151. As illustrated, latches 151 and 153 are clocked in response to I/O clock 149. It is appreciated that buffer circuits 135, 137, 155, and 157 are illustrated in Fig. 1 as driver circuits. It is appreciated however that buffer circuits 135, 137, 155 and 157 may be implemented as other circuits, such as for example inverters or the like in accordance with the teachings of the present invention. Fig. 2 is a block diagram illustrating one embodiment of a delay circuit 225 in accordance with the teachings of the present invention. In one embodiment, delay circuit 225 of Fig. 2 may be used in place of delay circuits 125 and/or 127 of Fig. 1 in accordance with the teachings of the present invention. Referring back to Fig. 2, delay circuit 225 generates a calibrated delayed output 229 in response to input 209 and delayed control 219. In particular, delay circuit 225 includes a phase lock loop circuit 265 receiving input 209 at a reference clock input of phase lock loop circuit 265. As illustrated, phase lock loop circuit 265 also receives delayed output 229 at a feedback clock input of phase lock loop circuit 265. In one embodiment, input 209 is received at the reference clock input of phase lock loop circuit 265 through impedance matching circuitry 263. Impedance matching circuitry 263 is utilized such that the input impedance of the reference clock input of phase lock loop circuit 265 is matched with the input impedance of the feedback clock input of phase lock loop circuit 265. In the embodiment illustrated in Fig. 2, phase lock loop circuit 265 generates an oscillating signal in phase with input signal 209. The oscillating signal generated by phase lock loop circuit 265 is coupled to be received by one input of a phase detector 267 as well as an input ofa delay chain circuit 275. As illustrated in the depicted embodiment, delay chain circuit 275 generates a plurality of at least [n?] outputs 279. As will be discussed, delay chain circuit 275 includes a chain of delay circuits. The output of each delay circuit in the chain is one of the plurality of outputs 279. In one embodiment, each delay circuit in delay chain circuit 275 introduces an additional Δt delay in the oscillating signal received at the input of delay chain circuit 275. Accordingly, the first one of the plurality of outputs 279 introduces a Δt delay, the second output of the plurality of outputs 279 introduces a 2Δt delay, ..., and an n th one of the plurality of outputs 279 introduces an nΔt delay to the oscillating signal received at the input of delay chain circuit 275. In one embodiment of the present invention, a second input of phase detector 267 is coupled to receive an n th output of one of the at least n plurality of outputs 279 of delay chain circuit. In one embodiment, the n th output is calibrated such that the n th output is the oscillating signal generated by phase lock loop circuit 265 delayed by one clock period. For example, if the oscillating signal generated by phase lock loop circuit 265 has a frequency off, then a clock period of the oscillating signal generated by phase lock loop circuit 265 is equal to 1/f. Thus, if for example the oscillating signal generated by phase lock loop circuit 265 is equal to 200 megahertz, then a clock period of that signal is equal to 5 nanoseconds. In the illustrated embodiment, an output of phase detector 267 is received by an up/down counter 269. In one embodiment, up/down counter 269 is configured to be adjusted in response to an output of phase detector 267. Therefore, when the oscillating signal generated by phase lock loop circuit 265 is out of phase with the n th output of delay chain circuit 275, which is calibrated to be delayed by one clock period, then up/down counter is incremented or decremented accordingly. In one embodiment, calibration control signal 271 is output by up/down counter 269 and is coupled to be received by calibration controller 273. In one embodiment, calibration controller 273 generates a bias control signals 277 which are coupled to received by the delay circuit elements of delay chain circuit 275. The Δt delay of each one of the delay circuit elements in delay chain circuits 275 is adjusted in response to the bias control signals 277. Accordingly, when the n th output of delay chain circuit 275 has been calibrated to be delayed by one clock period of the oscillating signal generated by phase lock loop circuit 265, up/down counter 269 will have stabilized and calibration control signal 271 will control calibration controller 273 to maintain the bias control signals 277. Therefore, delay chain circuit 275 is calibrated in accordance with the teachings of the present invention. It is appreciated that the delay provided by delay chain circuit 275 is independent over variations in process-voltage-temperature. In one embodiment, delay control signal 219 is utilized to control or select the amount of delay generated in delayed output 229. For instance, in one embodiment, delay controller 281 is coupled to receive delay control signal 219 and generates the appropriate select signals used to control a selection circuit 285, which is coupled to receive the plurality of at least n outputs 279 of delay chain circuit 275. In one embodiment, selection circuit 285 is a multiplexer type circuit used to select one of the plurality of at least n outputs 279 [????????] delayed output 229. In one embodiment, increased resolution may be provided for delayed output 229 with the use of an interpolator 283, which is coupled to receive a plurality of outputs from selection circuit 285 in response to delay controller 281. In one embodiment, interpolator 283 generates delayed output 229 by dividing the Δt delay increments of delay chain circuit 275 into finer delay increments. In one embodiment, the interpolation provided by interpolator 283 is provided by shorting the input taps and output taps of a delay element with a programmed combination of tap driver weights or strengths. The calibrated delay elements and interpolator provide capability to produce fine delay adjustments within a core phase magnitude. It is appreciated that the total amount of calibrated delay can be increased in integer multiples of core phases by adding latches in the clock generation paths. Fig. 3 is a schematic illustrating one embodiment ofa delay chain circuit 375 in accordance with the teachings of the present invention. In one embodiment, delay chain circuit 375 of Fig. 3 may be used in place of delay chain circuit 275 of Fig. 2 in accordance with the teachings of the present invention. As illustrated in the embodiment depicted in Fig. 3, delay chain circuit 375 includes a plurality of at least n delay circuit elements, illustrated as 389A, 389B and 389C coupled in sequence. As illustrated, delay circuit element 389 A receives input 387 and generates a delayed output 379 A. Delayed output 379A is coupled to be received by delay circuit element 389B, which generates delayed output 379B, ..., etc. The n th delay circuit element 389C generates delayed output 379C. It is appreciated that in one embodiment, delay chain circuit 375 may include more than n delay circuit elements. As mentioned earlier, in one embodiment, the delayed output 379C of the n th delay circuit element 389C is the signal received at input 387 delayed by one clock period, t. In one embodiment, each delay circuit element 389A, 389B and 389C in the delay chain circuit 375 introduces a Δt delay. Therefore, the output 379A of delay circuit element 389A is delayed lt/n, the output 379B of delay circuit element 389B introduces a 2t/n delay, etc., and the delayed output 379C of delay circuit element 389C is delayed nt/n or t. As illustrated in Fig. 3, delay circuit element 389A includes a buffer 391 coupled to receive input 387. It is appreciated that in the embodiment illustrated in Fig. 3, buffer 391 is illustrated as a driver circuit. However, buffer 391 may be implemented using other types of circuits, such as for example inverter circuits or the like. As illustrated in the depicted embodiment, the output of buffer 391 is coupled through switches 393A and 393B to capacitor 395, which is coupled to ground. In one embodiment, switches 393A and 393B are Pchannel and Nchannel transistors which provide a variable resistive connection to capacitor 395. In one embodiment, the variable resistance provided by switches 393A and 393B are controlled in response to bias signals VBIASP 377A and VBIASN 377B, respectively. In operation, increased delay may be provided by delay circuit element 389A by decreasing the resistance provided by switches 393 A and 393B. Conversely, decreased delay may be provided by delay circuit element 389A by increasing the resistance provided by switches 393A and 393B, in response to bias control signals VBIASP 377A and VBIASN 377B, respectively. As illustrated in Fig. 3, the schematics for the other circuit delay elements 389B and 389C of delay chain circuit 375 are substantially similar to the schematic of delay circuit element 389 A. Fig. 4 is a block diagram of one embodiment ofa delay circuit 439 in accordance with the teachings of the present invention. In one embodiment, delay circuit 439 of Fig. 4 may be used in place of delay circuit 139 in Fig. 1. As will be appreciated, one embodiment of delay circuit 439 shares a number of similarities with the embodiment of delay circuit 225 of Fig. 2. Referring back to Fig. 4, delay circuit 439 receives an input 409 at an input of delay chain circuit 475. Delay chain circuit 475 generates a plurality of at least n delayed outputs, illustrated as 479A, 479B and 479B. Similar to delay chain circuit 275 of Fig. 2 or delay chain circuit 375 of Fig. 3 an n th one of the plurality of outputs 479C delays input 409 by one clock period, t. In one embodiment, delayed chain circuit 375 of Fig. 3 may be used in place of delay chain circuit 475 of Fig. 4. As illustrated in the depicted embodiment, a calibration control signal 471 is received by calibration controller 473, which generates bias control signals 477A and 477B, which are coupled to be received by delay chain circuit 475. In one embodiment, bias control signals 477A and 477B are used to calibrate the plurality of at least 10 outputs 479 A, 479B, and 479C such that the n th output 479C delays input 409 by one clock period t. In one embodiment, calibration control signal 471 is calibration control signal 271, which is generated by up/down counter 269 of Fig. 2. Referring back to Fig. 4, a delay control signal 441 is received by a delay controller 481 which generates the appropriate control signals for a selection circuit 485 and an interpolator 483. In one embodiment, selection circuit 485 is coupled to receive the plurality of at least n outputs 479A, 479B and 479C of delay chain circuit 475. In one embodiment, interpolator 483 is not included and selection circuit 485 is used to select the appropriated one of the plurality of at least n outputs 479 A, 479B or 479C as delayed output 429. In another embodiment, interpolator 483 is coupled to receive a pair of outputs from selection circuit 485. In this embodiment, interpolator 483 adds additional resolution to delayed output 429 by dividing the Δt delay between outputs of delay chain circuit 475 into finer delay increments. Embodiments of the phase adjustment circuitry for I/O circuitry in accordance with the teachings of the present invention may be used in a variety of applications including for example I/O timing tests of integrated circuit chips such as CPUs or adjusting or fine tuning the timing of I/O operations of integrated circuit chips such that the chips function within specification requirements. To illustrate, assume for example that integrated circuit chip 103 of Fig. 1 is a CPU and that integrated circuit chip 105 is a chip of a chip set and that system 101 is a motherboard on which integrated circuit 103 and integrated circuit 105 and clock driver 107 are mounted. Embodiments of the present invention may be used to test timing parameters such as minimum and maximum clock to output times, hold times or set up times. Referring briefly back to Fig. 1 clock to output times refer to the amount of time required for output data to appear at the output of driver 135 after a rising clock edge of I/O clock 129 of integrated circuit chip 103. To illustrate, assume that integrated circuit chip 103 is a CPU and that integrated circuit chip 105 is a chip set. Fig. 5 is an illustration of timing diagrams of one embodiment of the present invention in which minimum clock to output times (TCO-MIN) may be tested in accordance with the teachings of the present invention. In particular, waveform 529A illustrates a CPU clock and waveform 535 A illustrates corresponding output data cycles that appear at the output of buffer circuit 135. As shown, rising edge 597A of CPU clock 529A corresponds to the transition of cycle and -1 to cycle n of CPU output data waveform 535A. Waveform 549 illustrates the chip set clock. As shown, rising edge 599 of chip set clock 549 occurs during cycle n of the CPU output data 535 A. The minimum clock to output parameter TCO-MIN 502A is illustrated in Fig. 5, which is the amount of time between the rising edge 599 of chip set clock 549 and the time in which cycle n transitions to cycle n+1 in the CPU output data 535 A. The minimum clock to output timing parameter may be tested by shifting the phase of the CPU clock 529A in accordance with the teachings of the present invention. For example, waveform 529B illustrates the CPU clock being shifted out of phase with chip set clock 549 by Δt. In one embodiment, CPU clock 529B is shifted in phase or pulled back relative to chip set clock 549 as shown by adjusting the forward delay control signal 119 to add more delay than feedback delay control signal 121. In one embodiment, feedback delay control signal 121 is configured to add no delay in this situation. Referring back to Fig. 5, rising clock edge 597B of CPU clock 529B results in the corresponding transition between cycle n-1 and cycle n of the new CPU output data 535B. As illustrated, rising clock edge 599 of chip set clock 549 still occurs within cycle n of CPU output data 535B. However, the minimum clock to output timing parameter new TCO- MIN 502B is now less than the original TCO-MIN 502A. In one embodiment, the minimum clock to output timing parameter may be stressed to cause system failures in order to test the CPU I/O timing paths in accordance with the teachings of the present invention. Fig. 6 illustrates timing diagrams showing the maximum clock to output timing parameters being tested in accordance with the teachings of the present invention. In particular, CPU clock 629A is illustrated having a rising clock edge 697A resulting in a transition from cycle n-1 to cycle n of the CPU output data 635 A. As shown, rising clock edge 699 of chip set clock 649 occurs during cycle n of CPU output data 635 A, and therefore output data may be latched properly by the chip set. The maximum clock to output timing parameter is illustrated in Fig. 6 as TCO-MAX 602A, which is the amount of time between a rising clock edge of chip set clock 649 and a corresponding transition between cycles on CPU output data 635 A. In the embodiment illustrated, the maximum clock to output timing parameter is tested by shifting the CPU clock 629B to be out of phase with chip set clock 649. In the example illustrated, CPU clock 629B is pushed out relative to chip set clock 649 by Δt by increasing the forward delay control signal 119 relative to the feedback delay control signal 121. In one embodiment, feedback delay control signal 121 is set to add no delay in this situation. Accordingly, rising clock edge 697B of CPU clock 629B results in the transition from cycle n-1 to cycle n of CPU output data 635B. Accordingly, the updated maximum clock to output timing parameter, TCO-MAX 602B is illustrated in Fig. 6 as shown. In one embodiment, TCO-MAX 602B is stressed to cause a system failure to test the CPU timing path in accordance with the teachings of the present invention. In one embodiment, the system will fail when rising clock edge 699 of chip set clock 649 does not occur within cycle n of CPU output data 635B. Fig. 7 is a timing diagram illustrating one embodiment of hold-time timing parameters of data being sent from a chip set to a CPU in accordance with the teachings of the present invention. In particular, Fig. 7 shows rising clock edge 797 of chip set clock 749 resulting in a corresponding transition from cycle n-1 to cycle n of chip set output data 757. As shown, rising clock edge 799A of original CPU clock 729A occurs during cycle n of chip set output data 757. Thus, data may be latched properly by the CPU. The hold-time timing parameter is illustrated in Fig. 7 as T-HOLD 702A, which is the time between rising clock edge 799A of original CPU clock 729A and the time at which chip set output data 757 transitions from cycle n to cycle n+1. In order to test the hold-time timing parameter, the CPU clock is pushed out relative to the chip set clock 749 by increasing the forward delay signal 119 relative to the feedback delay control signal 121. In one embodiment, feedback delay control signal 121 is set to add no delay in this situation. Accordingly, new CPU clock 729B shows that the rising clock edges of the CPU clock are pushed out an additional Δt relative to chip set clock 749. Rising clock edge 799B of new CPU clock 729B is shown to occur during cycle n of output data 757, and therefore data may be latched properly by the CPU from the chip set. The new hold- time timing parameter is shown in Fig. 7 as NEW T-HOLD 702B, which is the amount of time between rising clock edge 799B of new CPU clock 729B and the transition of chip set output data 757 from cycle n to cycle n+1. In one embodiment, the NEW T- HOLD 702B timing parameter can be stressed to cause system failures to test the CPU I/O timing paths. In one embodiment, a system failure will occur if rising clock edge 799B of new CPU clock 729B does not occur within cycle n of chip set output data 757. Fig. 8 is an illustration of timing diagrams showing set up time timing parameters of data being transferred from a chip set to a CPU being tested in accordance with the teachings of the present invention. As shown, rising clock edge 897 of chip set clock 849 results in the transition of chip set output data 857 from cycle n-1 to cycle n. At this time, both the forward delay control signal 119 and the feedback delay control signal 121 are set to zero. As illustrated in Fig. 8, rising clock edge 899A of original CPU clock 829A occurs during cycle n of chip set output data 857. Accordingly, there is not a system failure at this time. Divisional set up timing parameter is shown in Fig. 8 as ORIGINAL T-SETUP 802A, which is the amount of time from a transition between cycles of chip set output data 857 and a subsequent corresponding rising clock edge of the CPU clock. In one embodiment, the setup time parameter may be tested in accordance with the teachings of the present invention by shifting the phase of the CPU clock to be out of phase with the chip set clock 849. In Fig. 8, new CPU clock 829B is pulled in relative to chip set clock 849 by Δt by increasing the feedback delay control signal 121 relative to the forward delay control signal 119. In one embodiment, forward delay control signal 119 is set to zero in this situation. The new setup time timing parameter is illustrated in Fig. 8 as NEW T-SETUP 802B, which is the amount of time from a transition between cycles of chip set output data 857 and a subsequent corresponding rising clock edge 899B of new CPU clock 829B. In one embodiment, the NEW T-SETUP parameter 802B can be stressed to cause a system failure to test the CPU I/O timing paths in accordance with the teachings of the present invention. In one embodiment, a system failure can be triggered by a rising clock edge 899B not occurring within a cycle n of chip set output data 857. Fig. 9 is a timing diagram illustrating an integrated circuit chip including phase adjustment circuitry in association with I/O circuitry being adjusted to allow the integrated circuit chip to function properly in the system with I/O timing path defects. For instance, assume that the integrated circuit chip is a CPU and that data is transferred between the CPU and the chip set on a motherboard in accordance with the teachings of the present invention. For instance, Fig. 9 shows a rising clock edge 997A of an original CPU clock 929 A resulting in a corresponding transition of CPU output data 935 A from cycle n- 1 to cycle n. In this example, forward delay control signal 119 and feedback delay control signal 121 are set to equal zero at this time. In this example, it is assumed that there is a timing defect in the system in which the CPU and chip set are mounted. Consequently, chip set clock 949 is out of phase with original CPU clock 929A, as illustrated in Fig. 9. Accordingly, the rising clock edge of chip set clock set 949 does not occur within cycle n of original CPU output data 935 A. In one embodiment, rising clock edge 999 not occurring during cycle n of original CPU output data 935 A would result in a system failure. Prior to the present invention, a system exhibiting such timing characteristics would be discarded because of such a system failure. In order to remedy this situation, this phase of the CPU clock can be adjusted in accordance with the teachings of the present invention such that the system no longer fails. In particular, Fig. 9 shows new CPU clock 929B having a clock edge 997B that is pushed out relative to chip set clock 949 by adding Δt with forward delay control signal 119. In one embodiment, feedback delay control signal 121 is set at zero at this time. As a result, rising clock edge 997B, which results in the transition of new CPU output data 935B from cycle n-1 to cycle n is also pushed out. As a result, rising clock edge 999 of chip set clock 949 now occurs within cycle n of new CPU output data 935B, thereby resulting in the system no longer failing during the I/O transmission. In one embodiment, the phase of the CPU clock is adjusted an amount small enough such that data communications in the opposite direction are still within I/O timing tolerances. Therefore, a system including a integrated circuit chip having phase adjustment circuitry in association with I/O circuitry in accordance with the teachings of the present invention no longer must be discarded. In another example, Fig. 10 illustrates a rising clock edge 1097A of a CPU clock 1029A resulting in a transition of CPU output data 1035A from cycle n-1 to cycle n. In the example illustrated in Fig. 10, chip set clock 1049 is in phase with the original CPU clock 1029 A, but rising clock edge 1099 of chip set clock 1049 does not occur within cycle n of CPU output data 1035 A. In the illustrated embodiment, the phase of new CPU clock 1029B is adjusted by Δt such that Δt is added by feedback delay control signal 121 to pull in the CPU clock 1029B relative to chip set clock 1049 by Δt. In one embodiment, forward delay control signal 119 is set to be zero at this time. By pulling in new CPU clock 1029B by Δt as illustrated, new CPU output data 1035B is pulled in correspondingly. As a result, the rising clock edge 1099 now occurs within cycle n of new CPU output data 1035B, thereby correcting the system failure described earlier. In one embodiment, new CPU clock 1029B is shifted by an amount Δt small enough such that data communications from other chips in the system to the CPU are still within timing tolerances, and thereby do not result in system failures. Fig. 11 is a timing diagram illustrating a rising clock edge 1197 of chip set clock 1149 resulting in a transition of chip set output data 1157 from cycle n-1 to cycle n. In the embodiment illustrated in Fig. 11, original CPU clock 1129A is in phase with chip set clock 1149, but since rising clock edge 1199A of original CPU clock 1129A does not occur within cycle n of chip set output data 1157, there is a system failure. In order to correct this system failure, new CPU clock 1129B is shifted to be out of phase with chip set clock 1149 by Δt. In one embodiment, new CPU clock 1129B is shifted by adding a Δt delay to forward delay control signal 119. In one embodiment, feedback delay control signal 121 is set to zero at this time. As a result, new CPU clock 1129B is pushed out Δt relative to chip set clock 1149, resulting in rising clock edge 1199B of new CPU clock 1129B occurring within cycle n of chip set output data 1157. As a result, the system failure described earlier has been corrected in accordance with the teachings of the present invention. In one embodiment, new CPU clock 1129B is shifted by an amount Δt small enough such that data communications from the CPU to the chip set remain within timing tolerances such that a system failure does not occur. Fig. 12 is a timing diagram illustrating another situation in which a chip set clock 1249 is out of phase with an original CPU clock 1229 A, with forward delay control signal 119 and feedback delay control signal 121 both being set to zero. In one embodiment, the phase difference between chip set clock 1249 and original CPU clock 1229A may occur as a result of a defect in the clock timing paths of the system. As shown, rising clock edge 1297 of chip set clock 1249 results in a transition of chip set output data 1257 from cycle n-1 to cycle n. Since original CPU clock 1229A is out of phase with chip set clock 1249, rising clock edge 1299A of original CPU clock 1229 A does not occur within cycle n of chip set output data 1257, consequently resulting in a system failure for input data transmissions from the chip set to the CPU. In order to correct the system failures for CPU data inputs from the chip sets, the phase of new CPU input clock 1229B is adjusted by Δt 1202 A in accordance with the teachings of the present invention. In one embodiment, new CPU clock 1229B is pulled in relative to chip set clock 1249 by adding Δt to feedback delay control signal 121. In one embodiment, forward delay control signal 119 is set to be zero at this time. As a result of the phase of new CPU clock 1229B being phase shifted by Δt 1202A, rising clock edge 1229B of new CPU clock 1229B now occurs within cycle n of chip set output data 1257. Accordingly, inputs to the CPU to the chip set are now possible and do not result in system failures as described previously. In one embodiment, the phase of data outputs from the CPU are also adjusted by Δt 1202C such that there are no system failures when transmitting data from the CPU to other chips in the system. For instance, there may be a situation in which pulling the CPU clock in by Δt 1202A as shown in new CPU clock 1229B for CPU inputs would result in system failures for CPU outputs. Accordingly, the effective CPU clock for data outputs from the CPU is shown as effective CPU clock 1229C. In one embodiment, the phase of the effective CPU clock 1229C is adjusted by Δt 1202C by adding Δt 1202C delay to the output delay control signal 141 in the I/O circuitry 113, as illustrated in Fig. 1. In the embodiment illustrated, delay circuit 139 delays data output by output buffer 135 Δt 1202C, as controlled by output delay control signal 141. In the embodiment illustrated in Fig. 12, the effective CPU clock 1229C for CPU outputs has been adjusted to be in phase with the original CPU clock 1229A. Accordingly, the phase of CPU data outputs are effectively unchanged, even though the phase of new CPU clock 1229B has been pulled back by Δt 1202A in accordance with the teachings of the present invention. In the foregoing detailed description, the method and apparatus of the present invention have been described with reference to exemplary embodiments thereof. It will, however, be evident that there is modifications and changes thereto without departing from the broader spirit and scope of the present invention. The present specification are accordingly to be regarded as illustrative rather than restrictive.

Claims: CLAIMS What is claimed is: 1. An apparatus, comprising: a phase adjustment circuit coupled to receive a system clock and phase control information, the phase adjustment circuit to generate a first input/output (I/O) clock having a selectable phase difference from the system clock; an I/O buffer circuit clocked in response to the first I/O clock to latch I/O data of the apparatus, the I/O buffer circuit coupled to latch the I/O data to and from a remote I/O buffer circuit ofa remote apparatus, the remote I/O buffer circuit clocked in response to a remote I/O clock substantially in phase with the system clock. 2. The apparatus of claim 1 wherein the phase adjustment circuit comprises: a first phase locked loop circuit to generate the first I/O clock; a first delay circuit coupled to a reference clock input of the first phase locked loop circuit, the first delay circuit coupled to receive the system clock and coupled to delay the system clock in response to the phase control information; and a second delay circuit coupled to a feedback clock input of the first phase locked loop circuit, the second delay circuit coupled to receive the first I/O clock and coupled to delay the first I/O clock in response to the phase control information. 3. The apparatus of claim 2 wherein the phase control information comprises: a first delay control signal coupled to be received by the first delay circuit; and a second delay control signal coupled be received by the second delay circuit. 4. The apparatus of claim 1 wherein the I/O buffer circuit includes a third delay circuit coupled in an I/O data path of the I/O buffer circuit, the third delay circuit coupled to receive a third delay control signal, the third delay circuit coupled to delay an I/O data of the I/O buffer circuit in response to the third delay control signal. 5. The apparatus of claim 4 wherein the I/O data path comprises an output data path of the I/O buffer circuit including an output buffer and an output data latch clocked in response to the first I/O clock. 6. The apparatus of claim 4 wherein the I/O data path comprises an input data path of the I/O buffer circuit including an input buffer and an input data latch clocked in response to the first I/O clock. 7. The apparatus of claim 2 wherein at least one of the first and second delay circuits comprises: a second phase locked loop circuit coupled to receive an input clock signal at a reference clock input of the second phase locked loop circuit, the second phase locked loop circuit to generate an oscillating signal having a period of T and in phase with the input clock signal; a first delay chain circuit coupled to receive the oscillating signal from the second phase locked loop circuit, the first delay chain circuit including a chain of at least N outputs, each successive one of the chain N outputs coupled to output the oscillating signal with an additional (l/N) x T delay relative to a neighboring upstream output of the chain of N outputs; a first selection circuit coupled to receive the chain of at least N outputs of the first delay chain circuit, the first selection circuit coupled to select at least one of the chain of at least N outputs in response to a delay control signal, wherein a feedback clock input is coupled to receive a delayed clock signal responsive to the selected at least one of the chain of at least N outputs of the first delay chain circuit. 8. The apparatus of claim 7 further comprising an interpolator circuit coupled to receive a pair of the at least N outputs of the first delay chain circuit from the first selection circuit, the interpolator circuit coupled to output the delayed clock signal responsive to the delay control signal. 9. The apparatus of claim 7 further comprising calibration circuitry coupled to receive the oscillating signal and coupled to the first delay chain circuit and coupled to calibrate the first delay chain circuit. 10. The apparatus of claim 9 wherein the calibration circuitry comprises: a phase detector coupled to receive the oscillating signal from the second phase locked loop circuit and coupled to receive a delayed oscillating signal from an Nth one of the chain of at least N outputs of the first delay chain circuit; an up/down counter coupled to an output of the phase detector; and a calibration controller coupled to receive a calibration control signal from the up/down counter and coupled to generate a calibration bias information coupled to be received by the first delay chain circuit. 11. The apparatus of claim 7 wherein the first delay chain circuit comprises a chain of at least N variable resistor-capacitor (RC) circuits coupled in series to output the chain of at least N outputs of the first delay chain circuit. 12. The apparatus of claim 4 wherein the third delay circuit comprises: a second delay chain circuit coupled to receive an input signal, the second delay chain circuit including a chain ofa plurality of outputs, each successive one of the chain the plurality of outputs coupled to output a delayed input signal with an additional incremental delay relative to a neighboring upstream output of the chain of the plurality outputs; a second selection circuit coupled to receive the chain of the plurality of outputs of the second delay chain circuit, the second selection circuit coupled to select at least one of the chain of the plurality of outputs in response to the third delay control signal, wherein a delayed output signal is generated in response to the selected at least one of the chain of the plurality of outputs of the second delay chain circuit. 13. The apparatus of claim 12 further comprising a second interpolator circuit coupled to receive a pair of the plurality of outputs of the second delay chain circuit from the second selection circuit, the second interpolator circuit coupled to output the delayed output signal responsive to the third delay control signal. 14. The apparatus of claim 12 further comprising second calibration circuitry coupled to calibrate the second delay chain circuit in response to a calibration control signal. 15. A system, comprising: a clock driver circuit coupled to generate a system clock; a first chip including a first input/output (I/O) buffer circuit and a first phase locked loop circuit coupled receive the system clock and coupled to generate a first I/O clock coupled to clock the first I/O buffer circuit, the first I/O clock substantially in phase with the system clock; and a second chip including a second I/O buffer circuit coupled to the first I/O buffer circuit to transfer I/O data between the first and second chips, the second chip including a phase adjustment circuit coupled receive the system clock and coupled to generate a second I/O clock coupled to clock the second I/O buffer circuit, the second I/O clock having a selectable phase difference from the system clock. 16. The system of claim 15 wherein the second chip further includes a delay circuit in an I/O data path of the second I/O buffer circuit, the delay circuit coupled to receive a delay control signal, the delay circuit coupled to delay an I/O data transfer between the first and second chips in response to the delay control signal. 17. The system of claim 16 wherein the delay circuit includes a calibration controller responsive to a counter output to provide the delay of the I/O data transfer substantially independent of process-voltage-temperature variations. 18. The system of claim 15 wherein the phase adjustment circuit comprises: a phase locked loop circuit coupled to generate second I/O clock; a forward delay circuit coupled to a reference clock input of the phase locked loop circuit and coupled to receive the system clock, the forward delay circuit coupled to delay the reference clock input from receiving the system clock in response to a forward delay control signal; and a feedback delay circuit coupled to a feedback clock input of the phase locked loop circuit and coupled to receive the second I/O clock, the feedback delay circuit coupled to delay the feedback clock input from receiving the second I/O clock in response to a feedback delay control signal. 19. The system of claim 18 wherein both the forward and feedback delay circuits include a calibration controller responsive to a counter output to provide the delay of respective clock signals substantially independent of process-voltage-temperature variations. 20. The system of claim 18 wherein at least one of the forward and feedback delay circuits include a counter coupled to an output ofa phase detector, the phase detector coupled to detect a phase difference between an oscillating signal and a delayed oscillating signal, delayed oscillating signal generated by a delay chain circuit coupled delay the oscillating signal by at least one period of the oscillating signal. 21. A method, comprising: generating a first input/output (I/O) clock in response to a system clock to clock a first I/O buffer ofa first chip; adjusting a phase of the first I/O clock to be out of phase with the system clock; transmitting I/O data between the first I/O buffer of the first chip and a second I/O buffer ofa second chip, the second I/O buffer clocked in response to a second I/O clock substantially in phase with the system clock. 22. The method of claim 21 further comprising calibrating delay circuitry with respect to the system clock. 23. The method of claim 22 wherein calibrating the delay circuitry comprises: delaying the system clock at least one clock period with the delay circuitry; measuring a phase difference between the system clock and the delayed system clock; and adjusting the delay circuitry such that a the delayed system clock is substantially in phase with the system clock. 24. The method of claim 21 further comprising adjusting a delay of an I/O data path of the first I/O buffer of the first chip such that the transmission of I/O data through the I/O data path of the first I/O buffer is out of phase with the first I/O clock. 25. The method of claim 24 wherein the I/O data path of the first I/O buffer comprises an output data path of the first I/O buffer. 26. The method of claim 24 wherein the I/O data path of the first I/O buffer comprises an input data path of the first I/O buffer. 27. The method of claim 21 further comprising testing for a speed-related I/O defect in a system including the first and second chips by adjusting the phase of the first I/O clock to be out of phase with the system clock and transmitting the I/O data between the first and second I/O buffers until there is an I/O data transmission failure. 28. The method of claim 21 further comprising overcoming a speed-related I/O defect in a system including the first and second chips by adjusting the phase of the first I/O clock to be out of phase with the system clock until there is a successful I/O data transmission between the first and second chips. 29. An apparatus, comprising: phase adjustment means coupled to receive a system clock and phase control information, the phase adjustment means for generating a first input/output (I/O) clock having a selectable phase difference from the system clock; I/O buffer means clocked in response to the first I/O clock to latch I/O data of the apparatus, the I/O buffer means for latching the I/O data to and from a remote I/O buffer means of a remote apparatus, the remote I/O buffer means clocked in response to a remote I/O clock substantially in phase with the system clock. 30. The apparatus of claim 29 wherein the phase adjustment means comprises: first phase locked loop means for generating the first I/O clock; first delay means coupled to a reference clock input of the first phase locked loop means and coupled to receive the system clock, the first delay means for delaying the system clock in response to the phase control information; and second delay means coupled to a feedback clock input of the first phase locked loop means and coupled to receive the first I/O clock, the second delay means for delaying the first I/O clock in response to the phase control information.

Inventors: CHAO CHI-YEU, KIM SONGMIN, LIM CHEE, TAYLOR GREGORY, WONG KENG, CHAO, CHI-YEU, KIM, SONGMIN, LIM, CHEE, TAYLOR, GREGORY, WONG, KENG
Applicants: CHAO CHI YEU, INTEL CORP, KIM SONGMIN, LIM CHEE, TAYLOR GREGORY, WONG KENG, CHAO, CHI-YEU, INTEL CORPORATION, KIM, SONGMIN, LIM, CHEE, TAYLOR, GREGORY, WONG, KENG
Application year: 2001
Main classification: G01R19
IPC codes: G01R31