BOTTOM GATE TYPE THIN FILM TRANSISTOR, ITS MANUFACTURING METHOD AND LIQUID CRYSTAL DISPLAY DEVICE USING THE SAME

Abstract: The object of the invention is to provide a bottom gate type thin film transistor and a manufacturing method of it, which can reduce a burden of TFT manufacturing process and thereby a less manufacturing cost is required. A bottom gate type thin film transistor is provided, in which a base layer (1), a gate electrode (2), a gate isolation film (3), and source and drain electrodes (4, 5) are located in this order. The transistor comprises a semiconductor channel layer (6) which is in contact with a portion of the gate isolation film exposed between the source and drain electrodes (4, 5) while being in contact with respective inter-opposite ends of the source and drain electrodes (4,5) and being formed in association with the gate electrode (2). The channel layer (6) is bridged from one of the inter-opposite ends to the other on the upper face side of the source and drain electrodes (4, 5). Contact portions (6c) of the channel layer (6) with the source and drain electrodes (4, 5) form ohmic contact surface layers.

Description: Bottom gate type thin film transistor, its manufacturing method and liquid crystal display device using the same BACKGROUND OF THE rNVENTION Field of the invention The invention relates to a thin film transistor (TFT) and a method for manufacturing such a TFT. In particular, the invention relates to a bottom gate type TFT that is well applied to active matrix type liquid crystal display devices and to a method of manufacturing such a TFT. The invention also relates to a liquid crystal display device comprising such bottom gate type TFTs. DESCRIPTION OF THE PRIOR ART Thin film transistors are commonly used in electronic devices such as liquid crystal display (LCD) devices and image sensors. In particular, the liquid crystal display panel of an active matrix type uses TFTs each of which comprises a source electrode, a drain electrode and a channel region as elements for supplying an appropriate voltage to pixel electrodes in accordance with the pixel information. Some transmissive active matrix type LCDs may be provided with a light-shield film for each TFT so as to cut off the light that may possibly enter the TFT, especially the channel region thereof from a backlight etc. located on the rear side of the LCD panel. For example, if the light enters the channel region when the TFT is controlled so as to keep its complete "off" state, the degree of insulation between the source and drain electrodes may decrease, whereby leakage current may be occurred. This may further lead to unnecessary variation in an electrical potential of the pixel electrode that is connected to the drain electrode, which may further deteriorate the quality of images to be displayed. In order to prevent such leakage current, there has been one conventional solution that is to provide a light-shield film to cover the channel region on the side of the backlight of the LCD panel for preventing the channel region from being struck by the light. The TFT manufacturing method disclosed in Japanese Patent Application Laid-Open No. 131021/95 comprises depositing over a glass substrate a phosphorus-doped silicon film which is to serve as a light-shied film, and forming a silicon oxide film on the upper surface of that silicon film. Then, an amorphous silicon film is formed on the upper surface of that silicon oxide film, which will form a source electrode, a drain electrode and a channel region in the later step. After that, over the amorphous silicon film, another silicon oxide film and an aluminum film is deposited in this sequence. Thereafter a stack-layered position is formed, which is in a shape of a smaller island than the other layers, and which consists of an aluminum film, silicon oxide film and an amorphous silicon film, by means of a resist treatment (masking process) and a patterning process with an etching process. After that, nitrogen ions are implanted into parts of the silicon oxide film's area located out of the stack-layered portion and the phosphorus-doped silicon film. Thus the method performs an anneal process only upon the ion-implanted parts of the silicon oxide film and the phosphorus-doped silicon film so as to nitride the parts and give them optically transparent. Thus, the above-referenced, known method performs a transparentizing process upon the desired portion and gives a function as a light-shield film to the phosphorus- doped silicon film below the stack-layered portion. Subsequently, a silicon oxide film is formed as a gate insulator on the amorphous silicon film, and a patterned gate electrode and an oxide layer surrounding that gate electrode are further formed on the gate insulator. After having formed the gate portion, phosphorus ions are implanted into the amorphous film using the gate portion as a mask so as to form n-type source and drain regions. As a result, the amorphous portion overlaying the gate portion forms a channel forming region and the other amorphous portion forms n-type source and drain regions. Because the light going to enter at the source, drain and channel region from the outer surface side of the glass substrate can be cut off by means of the light-shield film, it is possible to prevent the light of the backlight system from entering the finished channel region and thereby causing such leakage current described above. However, such a conventional method needs an expensive ion implanting equipment since an ion implantation process is used to form final source and drain electrodes. Since the amorphous silicon film for forming source, drain and channel regions is formed on the substrate using the plasma CVD equipment before the ion implantation process, the conventional method also needs a transportation of the processed assembly substrate from the plasma CVD equipment to the ion implanting equipment; that is, a transfer between the process chambers is required. Accordingly, the conventional method has drawbacks that its process is complicated, that its processing environments are discrete and that the assembly substrates should be too carefully handled against dusts, damages and so on. As a result, the trend has been to have a heavy burden on its TFT manufacturing process, and to lead to an expensive manufacturing cost. Furthermore, in the conventional method there is disclosed only so-called top gate type TFTs in which the light-shield film is disposed on the bottom side of the channel region (on the far side from the liquid crystal medium, namely on the rear side of the LCD panel or on the backlight side) and the gate electrode is disposed on the upper side of the channel region. However, bottom gate type TFTs (in which a gate electrode is disposed on the bottom side of the channel region), can be more advantageously applied to transmissive liquid crystal display devices. That is because the gate electrode disposed on the bottom side of the channel region in the bottom gate type TFT also can serve as another function of a light-shield film for that channel region in the transmissive LCD device. Accordingly, the transimissive LCD device does not need the dedicated light-shield film and does not require its manufacturing step, and also decreases the burden on the TFT manufacturing process. Therefore, improvements in the structure, performance and manufacturing process of the bottom gate type TFT can significantly contribute to reducing the price and improving the capability of the transmissive liquid crystal display device. SUMMARY OF THE INVENTION In view of the above-described background, it is an object of the invention to provide a good bottom gate type thin film transistor and its manufacturing method whereby burden on the manufacturing process and the manufacturing cost can be reduced. It is another object of the invention to provide a bottom gate type thin film transistor and its manufacturing method which is suitable for a transmissive liquid crystal display device. In order to achieve the above-described objects, the invention provides a bottom gate type thin film transistor in which a base layer, a gate electrode, a gate isolation film, and source and drain electrodes are located in this order, the transistor comprising a semiconductor channel layer which is in contact with a portion of the gate isolation film exposed between the source and drain electrodes while being in contact with respective inter- opposite ends of the source and drain electrodes and being formed in association with the gate electrode, the channel layer being bridged from one of the inter-opposite ends to the other on the upper face side of the source and drain electrodes, contact portions of the channel layer with the source and drain electrodes forming ohmic contact surface layers. With this structure, after the said source and drain electrodes have been formed, the same plasma CVD equipment can be consistently used not only for the process for forming the channel layer but also for the process for making ohmic contact between the source and drain electrodes and the channel layer, so that a simplified process requiring no transfer between processing chambers could be obtained. Additionally, a desirable source/drain current path could be advantageously formed under the bottom gate type structure. Moreover, in the transistor, a channel formed at a bottom of the channel layer forms a straight line-shaped current path on the sectional view together with the source and drain electrodes. Besides, the gate electrode may be formed from a light-shield material that is capable of cutting off the light that may possibly enter into the channel layer. In this case, the gate electrode can be also utilized as a light-shield film, which is very preferable for the transmissive liquid crystal display device. The invention also contributes to enhancement of the transmissive liquid crystal display devices in which a light irradiation system is disposed on the rear side of the base layer and their pixels are driven by the bottom gate type thin film transistors. The invention further provides a method of manufacturing a thin film transistor. The said method comprises: a pre-step of forming a gate electrode, a gate isolation film, and source and drain electrodes on a base layer in this order; a phosphor treatment step of plasma-doping surface layers of the source and drain electrodes with phosphorus; and a channel layer forming step of subsequently making a semiconductor channel layer which is in contact with a portion of the gate isolation film exposed between the source and drain electrodes while being in contact with respective inter-opposite ends of the source and drain electrodes and being formed in association with the gate electrode, the channel layer being bridged from one of the inter-opposite ends to the other on the upper face side of the source and drain electrodes, by means of a plasma-doping process. It is particularly preferable that the phosphor treatment step and the channel layer forming step in the inventive method are performed with the same plasma CVD equipment. These and other aspects of the invention will be apparent from and elucidated with reference to the embodiments described herein after. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a cross-sectional view of a part of a display panel substrate assembly, showing a structure of the TFT of the first embodiment according to the invention. Fig. 2 is a first flow chart showing the first half of the manufacturing procedure for the TFT of Fig. 1. Fig. 3 is a second flow chart showing the second half of the manufacturing procedure for the TFT of Fig. 1. Fig. 4 is a cross-sectional view illustrating a part of the intermediate structure of the TFT in process in the first manufacturing stage of the flow shown in Figs. 2 and 3. Fig. 5 is a schematic cross-sectional view illustrating a part of the intermediate structure of the TFT in process in the second manufacturing stage of the flow shown in Figs. 2 and 3. Fig. 6 is a cross-sectional view illustrating a part of the intermediate structure of the TFT in process in the third manufacturing stage of the flow shown in Figs. 2 and 3. Fig. 7 is a cross-sectional, magnified view of a part of the TFT, showing the phosphor treatment process . Fig. 8 is a cross-sectional view illustrating a part of the intermediate structure of the TFT in process in the fourth manufacturing stage of the flow shown in Figs. 2 and 3. Fig. 9 is a cross-sectional view illustrating a part of the intermediate structure of the TFT in process in the fifth manufacturing stage of the flow shown in Figs. 2 and 3. Fig. 10 is a cross-sectional view illustrating a part of the intermediate structure of the TFT in process in the sixth manufacturing stage of the flow shown in Figs. 2 and 3. Fig. 11 is a cross-section of a part of a display panel substrate assembly, showing a structure of the TFT of the second embodiment according to the invention. Fig. 12 is a cross-sectional view of a part of the TFT according to the first and second embodiments, illustrating the current path between the source and drain electrodes of such TFT. Fig. 13 is a schematic cross-sectional view of a part of the TFT according to a different example than the first and second embodiments, illustrating the current path between the source and drain electrodes of such TFT. DESCRIPTION OF THE PREFERRED EMBODIMENT(S) Fig. 1 illustrates a schematic cross-sectional structure of the TFT (thin film transistor) in accordance with one embodiment of the invention. The TFT shown in Fig. 1 is used in a display panel of an active matrix type transmissive liquid crystal display device. The liquid crystal medium LC for performing an optical modulation to display images is sealed in between two plates of the assemblies 100, 200 each using a glass substrate as a base layer, and the TFT is formed on a glass substrate 1 of one assembly 100. The backlight BL from the light irradiation system disposed on the rear side of the glass substrate 1 enters into the liquid crystal medium through the glass substrate 1, a part of the TFT formed on the upper face side of the substrate and the pixel electrode, is subjected to the optical modulation and is led to the external display screen through the other assembly 200. The gate electrode 2 formed from a light-shield material, which also serves as a light-shield film, is disposed on the upper face side of the glass substrate 1, namely on the liquid crystal medium LC side of the substrate. However, it may be possible to form an isolation film, e.g., a film comprising silicon oxide SiOx as a foundation layer between the substrate 1 and the gate 2 all over the upper surface of the substrate 1. Besides, over the substrate 1, a gate insulator film 3 consisting of e.g., SiNx is formed covering the gate electrode 2. Then, on the upper face of the gate insulator film 3, source and drain electrodes 4, 5 are formed by stacking transparent conductive films 4t, 5t and metal layers 4m, 5m (or by single metal layers). In this embodiment in which the stacked layers are used, the metal layers 4m and 5m are formed for the purpose of reducing the resistance of the source electrode and the drain electrode. In this embodiment, the metal layers are utilized based on the consideration that the resistances of the source and drain electrodes 4, 5, which are designed to extend vertically and horizontally in the LCD panel, are not allowed to be ignored when driving the transistors. Such metal layers can be often eliminated in case of small size display devices. Furthermore, between the source and drain electrodes and correspondingly to the gate electrode 2, an amorphous silicon a-Si film 6 as a semiconductor layer for forming a channel forming region and an isolation film 7 consisting of silicon nitride SiNx are stacked in this sequence in an island shape. With this structure, it is possible to make the a-Si film thinner because the a-Si film is not etched in the later process whereas it is etched in a back channel etching type. This feature can contribute to reducing the leakage current when the transistor is in an "off" state. The isolation layer 7 serves as a protection layer to prevent the top surface of the a-Si film 6 from becoming rough. Notably, in order to reduce the contact resistance of the a-Si film 6 with the source electrode 4 and the drain electrode 5, an n-type semiconductor n + a-Si surface layer portion 6c in the contact a-Si portion of which phosphorus (P) is diffused is formed. With this surface layer portion 6c, a desirable ohmic contact can be obtained between the source and drain electrodes 4, 5 and the a-Si film 6 so that a resistance between the source and drain electrodes (an "on" resistance in the transistor) can be reduced. The process for forming this surface layer portion will be described later. Furthermore, an isolation layer 8 consisting of e.g. silicon nitride SiNx is formed on the upper face side of the a-Si film 6 and the isolation film 7 so as to cover these films. The isolation layer 8 is provided with a contact hole 80, by which the drain electrode 5 is allowed to be exposed as shown in Fig. 1. For the exposed portion, a pixel electrode 9 is formed so as to extend along the upper face of the isolation layer 8 through the wall portion of the contact hole 80 so that the pixel electrode 9 can be in contact with the drain electrode 5. A portion of the isolation layer 8 corresponding to the gate terminal (not shown) is also removed so as to form a contact hole for contacting that gate terminal with the gate electrode 2. In this embodiment of the transmissive display device, the pixel electrode 9 is a transparent conductive film consisting of ITO (indium tin oxide) for example. It should be noted that: the source electrode 4 (the metal layer 4m) serves as a source bus-line that extends vertically in the effective display region of the display panel but it has not been shown herein; and the gate electrode 2 serves as a gate bus-line that extends horizontally in the effective display region of the display panel. Also, the pixel electrode 9 is designed to more extend rightward in Fig. 1 but it has not been shown. The extended area is dedicated to a pixel region or a voltage-applying region for the liquid crystal layer LC. Although a LC alignment layer or more is provided on the further upper layer side of the pixel electrode 9, such a layer is not described herein for the sake of clarity for the description of the invention. Now, the way to manufacture the thin film transistor having the structure illustrated in Fig. 1 will be described. Figs. 2 and 3 illustrate a procedure of the manufacturing method in a flow chart form, and Figs. 4-10 illustrate respective cross- sectional structures of the TFT being processed at the respective manufacturing stages. With reference to Fig. 2, a glass substrate 1 is at first prepared (step SI), and then a material containing, e.g., aluminum or alloys of aluminum for the gate electrode is deposited evenly over the substrate 1 by means of a sputtering process (step S2). Then the deposited film is patterned in a shape as shown in Fig. 4 to form the gate region 2 (step S3). Alternatively, the gate 2 may be a stack-layered structure consisting of at least one layer of some low-resistive material. The patterning process in step S3 includes a masking process with a photo resist, an exposure and development process, and an etching and removing process. Furthermore, the gate insulator film 3 is formed by depositing a material of e.g. SiNx evenly all over the upper surface of the substrate 1 by means of a sputtering process so that the gate 2 is buried as shown in Fig. 5 (step S4). Thereafter, a material consisting of e.g. ITO for the transparent conductive film 4t and then a material consisting of e.g. molybdenum alloy for the metal film 4m are deposited evenly over the isolation film 3 by e.g. a sputtering process in this order (steps S5 and S6). Then the same kind of patterning process is performed on the deposited transparent conductive film and metal film so that the deposited films are partially removed with respect to the portion substantially corresponding to the gate 2 (step S7). Thus, as illustrated in Fig. 6, the transparent conductive film 4t and the metal film 4m serving as the source 4 and the transparent conductive film 5t and the metal film 5m serving as the drain region 5 are formed. The source and drain are located with a space between them while having their respective ends facing to each other in the space. On the other hand, the surface of the gate isolation film 3 is exposed at the space, corresponding to the gate 2. After the patterning process on the source and drain, a phosphorus (P) diffusion process is performed (step S8). More specifically, using a plasma CVD equipment based on a plasma CVD (a chemical vapor phase epitaxial (evaporation) method), while the assembly substrate 1 having the gate 2, the gate isolation film 3, the source 4 and the drain 5 is kept at a predetermined temperature, e.g. 200-300 degrees centigrade, a dilution mixture gas containing phosphorus, for example, a gas obtained by diluting a PH 3 (phosphine) gas with an argon gas at 5000 ppm is applied to the assembly substrate at the speed of 10 cc/minute and plasma irradiation of high frequency of about 10mW/cm 2 is applied to the substrate continuously for a few minutes in an atmosphere of pressure of about 100 Torr so that the phosphorus doping is done. As a result, phosphorus is diffused or bonded with a predefined density and with a predefined depth from the exposed surface (including the stripped surface on the gate 2 side) of the transparent conductive film 4t, 5t and the metal film 4m, 5m. It should be noted that the portion, corresponding to the gate 2, of the gate isolation 3 between the source 4 and the drain 5 is exposed during the phosphorus diffusion process, but the phosphorus is little diffused in this exposed portion. So, the gate isolation film 3 may not substantially contain phosphorus. This is because the atoms of P basically tends to combine with electrically conductive substances but not with electrically insulating substances. Thus, the diffused phosphorus may be distributed over the surface-layered portion of the source and the drain as shown with dots in Fig. 7 that is a magnified view of Fig. 6. Now, getting back to the process flow with reference to Figure 3, a semiconductor material consisting of e.g. amorphous silicon a-Si for a channel region 6 and an insulation material consisting of e.g. SiNx for the isolation film 7 are deposited evenly all over the upper surfaces of the source 4 and the drain 5 in this order (steps S9 and S10). This depositing process is performed using the same plasma CVD equipment as described above. Then, the same kind of patterning process is performed on these deposited films so that a channel forming region comprising a semiconductor film 6 and an isolation film 7 in an island shape is formed approximately correspondingly to and over the gate 2 as illustrated in Fig. 8 (step s 11). Here, some of the phosphors that have been diffused to the source 4 and the drain 5 diffusely moves into the conductor film 6 from their contact surfaces due to the effect of the plasma and the atmosphere of high temperature in the CVD equipment, so that an n- type semiconductor n + a-Si film, which is very thin, can be formed at the contact portion of the semiconductor film 6 with the source and drain 4, 5. This n + a-Si thin film becomes the above-described ohmic contact layer 6c. Notably, most of the phosphors that have existed in the exposed portion of the source 4 and the drain 5 may disappear during the patterning (dry- etching) process for the semiconductor film 6 and the isolation film 7. After step S 11, a material consisting of e.g. SiNx is deposited all over the source 4 and the drain 5 so as to completely cover the island-shaped channel forming region (step S12), and the same kind of patterning process is performed (step S13). The patterning causes the protection film 8 is formed as shown in Fig. 9, which is removed with respect to e.g. a contact hole 80 for exposing only a necessary potion of the drain metal layer 5m (step S13). After that, a transparent conductive material consisting of e.g. ITO (indium tin oxide) for forming the pixel electrode corresponding to the pixel of the display panel is deposited evenly over the bottom and the wall of the contact hole 80 as well as over the upper surface of the isolation film 8 (step S 14). Then the same kind of patterning process is performed on the deposited ITO film so as to form the pixel electrode with its appropriate shape and position (step S15). As a result, as illustrated in Fig. 10, the pixel electrode 9 is formed, which is in contact with the drain electrode 5 and extends over the protection film 8 with a predefined area, for the contact hole 80. In the above-described method for manufacturing thin film transistors, it is possible to use an easy sputtering process for the prepositive stages for the gate 2 through the source 4 and the drain 5. Also, the plasma CVD equipment can be used to form the semiconductor film 6. Therefore, such expensive processing equipment as an ion implanting system is not required in forming these films. Additionally, after the source and drain have been formed, the same processing chamber in the plasma CVD equipment can be consistently used not only for the process for forming the semiconductor film but also for the phosphor diffusion process for making the ohmic contact. Accordingly, the above-mentioned conventional inter-chamber transfer is not required, whereby a simple process and a continuous process in terms of processing environments are achieved. Hence, it can contribute to the reduction of the burden on a manufacturing process for the TFT and the reduction of the manufacturing cost. Besides, since the embodiment is to improve the bottom gate type TFT and its manufacturing method wherein an additional function of a light-shield film is given to the gate 2 at the lower side of the channel region, it also significantly contributes to the reduction of the price of the transmissive liquid crystal display device as well as the improvement of its performance. Although the above description has referred to a thin film transistor that is intended to form one pixel driving circuit, a plurality of the thin film transistors each of which comprises an independent channel region may be formed in a matrix arrangement so as to correspond to each of the pixels in the liquid crystal display device. Now, with reference to Figure 11, a second embodiment of the invention will be explained. The same components in Fig. 11 as those in the first embodiment shown in Fig. 1 are given the same reference numerals. The difference in Fig. 11 from Fig. 1 is that it is not required to form a layer corresponding to the transparent conductive film 9 in the first embodiment because the drain 5' itself serves as a pixel electrode. In this case, the drain electrode 5' comprises only a transparent conductive film so as to pass through the backlight toward the liquid crystal side. The other features are basically the same as in the first embodiment, so that this embodiment has the same advantages as in the first embodiment. The second embodiment can further advantageously reduce the number of patterning processes to four due to no transparent conductive film 9. Furthermore, the structure of the thin film transistor in accordance with the invention has a unique and significant advantage other than the above-described advantages, and it will be mentioned as follows. Fig. 12 illustrates the states of the current flowing through the channel region in the fist and second embodiments. When the concerned thin film transistor is in an "on" state, the current "i" flowing from the source electrode 4 to the drain electrode 5 flows in the gate side surface the resistance value of which has eventually become the lowest in the semiconductor film 6 constituting the channel region due to the gate electric potential. In this situation, the source and drain electrodes 4, 5 are in contact directly with the bottom of the semiconductor film 6 at both ends of the bottom of the semiconductor film 6 as illustrated in Fig. 12, and the contact portion is subjected to the ohmic contact. As a result of this, when the semiconductor film 6 is in an "on" sate, the current path (channel) can be formed between the source electrode 4 and the drain electrode 5 in form of a straight line and with the shortest distance. In contrast to this, in the conventional structure of the thin film transistor as illustrated in Fig. 13, the semiconductor film 26 for forming the channel region extends on the gate isolation film 23 above the gate 22, and the source electrode 24 and the drain electrode 25 are formed on the semiconductor film 26 in association with the gate 22. With this conventional structure, the current "i" flowing from the source electrode 24 to the drain electrode 25 may take the following rout (channel). It is directed from the source electrode 24 toward the gate side surface of the semiconductor film 26 (downwardly in the Figure) through the inside of the semiconductor 26, and then toward the drain electrode side along the bottom of the semiconductor film 26, and finally upwardly toward the drain electrode 25 (upwardly in the Figure) again through the inside of the semiconductor 26. According to the current path as illustrated in Fig. 13, there are caused serial connection resistances R due to the thickness of the semiconductor film 26 on either side of the source electrode 24 and the drain electrode 25. Therefore, the resistance between the source and the drain and the "on" resistance for the thin film transistor may become higher. Such a situation that the resistance R is high is disadvantageous in respect of the reduction of the power consumption and/or the measures against the high temperature. Referring back to Figure 12, in the embodiment of the invention, the current from the source electrode 4 to the drain electrode 5 does not flow into the inside of the semiconductor film 6 in its thickness direction but flows linearly along the gate side surface of the semiconductor film 6. Thus, the resistance between the source and the drain and the "on" resistance for the thin film transistor can be made low. Consequently, the invention can contribute to improving the efficiency of driving pixel electrodes, reducing the power consumption and suppressing the heat of the thin film transistor. Although the transmissive liquid crystal display device has been referred to in the above description, the invention is not intended to limit to this type. The invention may be basically applied to a reflective type liquid crystal display device as well. In this case, the substrate 1 may be not required to be transparent, the pixel electrode 9 and/or the drain electrode 5' may be formed from some optical reflective material, and even some dedicated reflection layer, rather than such electrodes, can be used. Besides, although the above description has referred to a structure in which the substrate having TFTs is located on the rear side of the display panel, the substrate may be disposed on the front side of the display panel. Preferred embodiments described herein are therefore illustrative and not restrictive, the scope of the invention being indicated by the appended claims and all variations which come within the meaning of the claims are intended to be embraced therein. Translation of the drawing and elements Fig. 2 SI: Provision of glass substrate S2: Lamination of metal film S3: Patterning of gate S4: Lamination of isolation film S5: Lamination of transparent conductive layer S6: Lamination of metal film S7: Patterning of source and drain S8: P-diffusion Fig. 3 S9: Lamination of a Si film S10: Lamination of isolation film Sll: Patterning of channel forming portion S12: Lamination of protective film S13 Patterning of protective film S14: Lamination of pixel electrode S15: Patterning of pixel electrodes

Claims: CLAIMS: 1. A bottom gate type thin film transistor in which a base layer, a gate electrode, a gate isolation film, and source and drain electrodes are located in this order, the transistor comprising a semiconductor channel layer which is in contact with a portion of the gate isolation film exposed between the source and drain electrodes while being in contact with respective inter-opposite ends of the source and drain electrodes and being formed in association with the gate electrode, the channel layer being bridged from one of the inter-opposite ends to the other on the upper face side of the source and drain electrodes, contact portions of the channel layer with the source and drain electrodes forming ohmic contact surface layers. 2. A transistor as defined in Claim 1, characterized in that a channel formed at a bottom of the channel layer forms a straight line-shaped current path on the sectional view together with the source and drain electrodes. 3. A transistor as defined in Claim 1 or 2, characterized in that the gate electrode is formed from a light-shield material cutting off light possibly entering into the channel layer. 4. A transmissive liquid crystal display device whose pixels are driven by the bottom gate type thin film transistors according to any one of Claims 1-3, comprising a light irradiation system on the rear side of the base layer. 5. A method of manufacturing a thin film transistor, comprising: a pre-step of forming a gate electrode, a gate isolation film, and source and drain electrodes on a base layer in this order; a phosphor treatment step of plasma-doping surface layers of the source and drain electrodes with phosphorus; and a channel layer forming step of subsequently making a semiconductor channel layer which is in contact with a portion of the gate isolation film exposed between the source and drain electrodes while being in contact with respective inter-opposite ends of the source and drain electrodes and being formed in association with the gate electrode, the channel layer being bridged from one of the inter-opposite ends to the other on the upper face side of the source and drain electrodes, by means of a plasma-doping process. 6. A method as defined in Claim 5, characterized in that the phosphor treatment step and the channel layer forming step are performed by the same plasma CVD equipment.

Inventors: YUKAWA TEIZO, YUKAWA, TEIZO
Applicants: KONINKL PHILIPS ELECTRONICS NV, YUKAWA TEIZO, KONINKLIJKE PHILIPS ELECTRONICS N.V., YUKAWA, TEIZO
Application year: 2001
Main classification: H01L
IPC codes: G02F1, G09F9, H01L21, H01L29