INGRATED RF POWER SENSOR THAT COMPENSATES FOR BIAS CHANGES

Abstract: A system for controlling a bias circuit by sensing RF amplifier output power and compensating for a dominating quiescent bias current includes an amplifier transistor and two sampling transistors. The two sampling transistors are physically smaller than the amplifier transistor, and are preferably the same size. The first sampling transistor is configured to sample the same RF input signal that is amplified by the amplifier transistor. The second sampling transistor is configured to receive and amplify only a bias network signal. The bias network associated with the transistors includes a selection of components based upon operating parameters as well as actual physical sizes of the transistors. The selection of component values in association with transistor sizes is used to enable generation of a current sensing signal that is proportional to the power level of the RF output signal generated by the amplifier transistor. The bias current to the amplifier transistor is controlled by an operational amplifier that is fed with a reference voltage and the dc bias detected by the second small transistor.

Description: INTEGRATED RF POWER SENSOR THAT COMPENSATES FOR BIAS CHANGES Background of the Invention (1) Field of the Invention The present invention generally relates to radio f equency (RF) power amplifier output power detection techniques and, more particularly, to a system and method for sensing power consumed by a RF power amplifier and compensating for bias changes. (2) Description of the Prior Art Portable wireless transmitter systems generally require that a specified radio frequency (RF) output power be delivered to the radiating antenna. Further, many such systems are required to back-off or reduce the transmitted power to achieve a specific level depending upon signal strength. To meet the aforesaid requirements, the system architecture generally incorporates a closed-loop power control scheme. Typically, this scheme requires a "sampling" of the RF power amplifier output power that is subsequently fed back to predetermined control circuitry which generates a control signal that adjusts the output power until it is within the specified power level. Such sampling of the output power is disadvantageous in that it increases the insertion loss between the output of the power amplifier and the radiating antenna. Therefore, sampling of the output power decreases the available output power from the power amplifier and reduces the overall talk time. Talk time is a measure of the time a portable transceiver can be in the "talk" mode before the battery is fully depleted. The power amplifier consumes the majority of the current and therefore dominates in the calculation of talk time. A common technique for sampling the output power includes the use of a directional coupler on the output of the power amplifier. The power coupled from the main signal path is diode detected to generate a video signal proportional to the amplitude of the RF voltage delivered to the antenna. Use of directional couplers, however, adds loss to the system, forcing the power amplifier to consume more power thereby reducing the talk time of the associated radio unit. In typical applications, the aforesaid loss is often 5-10% of the power amplifier output power and relates to a direct loss in available talk time. Another common technique for detecting the output power includes measurement of the current consumed by the power amplifier. This current is directly related to the output power generated by- the power amplifier and is also fed back to predetermined power control leveling circuitry. This technique is also disadvantageous due to the loss associated with the current measurement. This current measurement generally requires that a series "dropping" element be added between the associated battery and the power amplifier bias input. The voltage across this element will determine the current entering the power amplifier (for a known resistance across the element). In typical applications, the voltage across the dropping element will be about 3% of the total battery voltage. Because this is a loss in the dc input power to the power amplifier, the loss of talk time will be even higher than 3% due to the less than 100% dc-rf conversion efficiency of the power amplifier. For example, if the power amplifier efficiency is 60%, then the talk time loss will be 3/0.6 or 5%. Thus, there remains a need for a new and improved technique for current sensing associated with RF amplifier power detection. Summary of the Invention The present invention is directed to a system and method relating to current sensing to detect RF amplifier output power and controlling a bias circuit to ensure that a bias current is set to a desired value. A small current sensing transistor is added in parallel with a large transistor that delivers the high power to the antenna. The current in this sensing - transistor is proportional to the current in the large transistor. The current in the large transistor is directly related to the output power generated by the power amplifier. By using . a small current sensing transistor, talk time loss is reduced by less than 1%. This small transistor is dc biased and RF driven proportionally to the large output transistor. The small transistor (sampling transistor) is about 1/250 the size of the larger output transistor which results in a scaling factor such that the additional current required for sensing is about 0.4% of the total current consumed by the power amplifier. In order to compensate for a dominating quiescent bias current at low power levels, an embodiment of the present invention incorporates a second small current sensing transistor that is in parallel with the large transistor and the first small current sensing transistor. However, the second small current sensing transistor does not receive the RF signal driving the large transistor and the first small current sensing transistor. Rather, the second small current sensing transistor only receives a bias current. Preferably, the second small transistor is the same physical size as the first small transistor. This configuration allows the power sensed by the first small current sensing transistor to be corrected for bias current effects and bias current shifts. In a further embodiment of the present invention, an operational amplifier is used in a feedback loop to precisely set the amplifier bias point for the large transistor. More specifically, the operational amplifier is input with a reference voltage proportional to a desired bias current in the large transistor and the detected dc bias of the second small transistor. The output of the operational amplifier is fed back to the large transistor. Accordingly, one feature of the present invention includes a technique for measurement of RF amplifier output power that reduces talk time by less than 1%. Another feature of the present invention includes a technique for measurement of RF amplifier output power that is more efficient than known measurement techniques. Still another feature of the present invention includes a technique for measurement of RF amplifier output power which consumes about an order of magnitude less power than that consumed by using known techniques. Yet another feature of the present invention includes a technique for measurement of RF amplifier output power that compensates for bias current effects and bias current shifts. A further feature of the present invention includes a technique for controlling the total bias current to an RF amplifier transistor by sensing the output power and the bias. These and other features of the present invention will become apparent to those skilled in the art after a reading of the following description of the preferred embodiment when considered with the drawings. Brief Description of the Drawings Figure 1 is a simplified schematic diagram illustrating a traditional method of RF power sensing known in the art. Figure 2 is a simplified schematic diagram illustrating a current sensing system constructed according to one embodiment of the present invention. Figure 3 is a more detailed schematic diagram illustrating a current sensing system according to another embodiment of the present invention. Figure 4 is a simplified schematic diagram illustrating a current sensing system that compensates for bias changes according to another embodiment of the present invention. Figure 5 is a simplified schematic diagram illustrating a current sensing system that compensates for bias changes and controls a bias circuit. Description of the Preferred Embodiments In the following description, like reference characters designate like or corresponding parts throughout the several views. Referring now to the drawings in general and Figure 1 in particular, it will be understood that the illustrations are for the purpose of describing a preferred embodiment of the invention and are not intended to limit the invention thereto. In Figure 1, a simplified schematic diagram illustrates a traditional RF power sensing system known in the art, generally designated 100. As stated herein, many RF systems need to know how much power is being supplied. The classical solution is to obtain samples of the RF energy being supplied via a coupling scheme, rectify the samples and use the resulting voltage as an indication of the power being supplied. A pair of coupled transmission lines 102 are used as the directional coupler. The power coupled from the main signal path 104 is detected via a diode 106, i.e. Schottky diode to generate a video signal, e.g. PWR_Sense 1.08, proportional to the amplitude of the RF output voltage delivered to the antenna (not shown). As stated above, such directional couplers 102 add loss to the system 100, forcing the power amplifier 110 to deliver more power, thus reducing the valuable talk time of the associated radio (not shown). Figure 2 illustrates a simplified schematic diagram showing a current sensing system 200 constructed according to one embodiment of the present invention. A radio frequency signal is received by the system 200 at the rf-in signal port 202 where it is coupled to a RF amplifier transistor 204 via coupling capacitor 206. An output matching and bias network 208 provides the necessary dc power and antenna matching to provide efficient transmission of the amplified RF signal to the associated antenna 210. The output matching and bias network 208 details are not important to the present invention and are not discussed herein to preserve brevity and enhance clarity associated with the present discussion of the invention. It is sufficient to state that a typical output matching network generally consists of a combination of inductors and capacitors configured to provide an impedance match between the RF amplifier transistor 204 output impedance and the antenna 210 input impedance. Figure 2 also illustrates an implementation of RF output power sensing that is accomplished in part via a small RF signal sensing (sampling) transistor 212. The small RF sampling transistor 212 is deployed in parallel with the RF amplifier transistor 204 that is physically much larger than the small sampling transistor 212. Coupling a small amount of the drive energy from the output stage into a small parallel device provides an integrated approach for indicating the power supplied by an amplifier. The small sampling transistor 212 is dc biased via a dedicated bias network 214. Details of the dc bias network 214 are not central to the present invention and so will not be discussed herein except to state that such bias schemes are well known to those skilled in the art and may consist of nothing more than a voltage source coupled to the small sampling transistor 212 via a resistor (not shown). In one embodiment, the size of the small sampling transistor 212 is about l/250 ft the size of the RF amplifier transistor 204. The present invention is not so limited however, and it shall be understood that other ratios associated with sizing of the RF amplifier transistor 204 and the small sampling transistor 212 will also be effective to practice the present invention. For example, the aforesaid ratio could just as well be any number between 1 and 500 or larger. Larger ratios could also be used in association with dedicated applications and processing technologies. With a scaling factor of 250, the additional current required for sensing is only about 0.4% of the total current consumed by the current sensing system 200 RF amplifier transistor 204. This is an order of magnitude less than the loss incurred by power measurement and sensing systems known in the art. For example, directional couplers reduce a typical transmitter's total efficiency by about 5% or more. Figure 3 illustrates a more detailed schematic diagram of a current sensing system 300 according to another embodiment of the present invention. With reference to the foregoing discussion above regarding ratio sizes, a typical ratio of device sizes for RF amplifier transistor 302 and sampling transistor 304 can be 224 to 1. In this case, the RF signal coupling capacitors 306, 308 will employ a similar ratio while the bias resistors 310, 312 will optimally employ a ratio of 1 to 224. The values for coupling the capacitor 306 and bias resistor 310 will be set by the design value associated with the specific application • parameters. In operation, the RF drive signal through capacitor 306 and capacitor 308 turns on the RF amplifier transistor 302 and the sampling transistor 304 proportional to the RF signal amplitude. The current flowing through the sampling transistor 304 then flows through bias resistor R2 and reduces the voltage across capacitor C2. The output power can then be determined by sensing the bias current flowing through bias resistor R2 at the PWR_Sense junction 314 using techniques familiar to those skilled iri the art of voltage/current transformations. As illustrated in Figure 2, it can be seen that the varying voltage across capacitor C2 (now hidden inside bias network 214) can also be used in a feedback loop to change the gain of the RF amplifier transistor 204. A differential amplifier 218 compares a reference voltage 220 with the changing voltage across capacitor C2 and changes the DC quiescent bias current to affect a change in the RF amplifier transistor 204 gain characteristics. The output power can thus be increased or decreased as desired. Most preferably, the RF signal coupling capacitors 306, 308, bias resistors 310, 312 and transistors 302, 304 are integrated on the same die, leaving the connections to transistor collectors open to maximize flexibility in configuring the power sense option desired. While the embodiments illustrated in Figures 2 and 3 provide an improved technique for current sensing associated with RF amplifier power detection, there is one disadvantage of the approach. The Q2a collector current (304 Figure 3) is composed of the DC quiescent current and the induced RF current. Therefore, at low power levels, the quiescent bias current is the dominating current. If the PWR_Sense voltage across C2 is used to control the RF power level, any change in the bias current introduces an error. Such a change in the bias current could result from a change in the temperature or power supply. Figure 4 illustrates a simplified schematic diagram showing a current sensing system 400 that compensates for erroneous contributions of a bias current according to another embodiment of the present invention. A RF signal is received by the system 400 at the RF- in signal port 402 where it is coupled to a RF amplifier transistor 404 via coupling capacitor 406. An output matching and bias network 408 provides the necessary dc power and antenna matching to provide efficient transmission of the amplified RF signal to the associated antenna (not shown). A small RF sampling transistor 412 is deployed in parallel with the RF amplifier transistor 404, which is physically much larger than the small sampling transistor 412. The small sampling transistor 412 is dc biased via a dedicated bias network 414. As noted above, the size of the small sampling transistor 412 may be about 1/250 the size of the RF amplifier transistor 404. The present invention is not so limited, however, and it shall be understood that other ratios associated with sizing of the RF amplifier transistor 404 and the small sampling transistor 412 will also be effective to practice the present invention. In order to compensate for a dominating quiescent bias current at low power levels, the system 400 includes a second small sampling transistor 416. This second small sampling transistor 416 is also physically much smaller than the RF amplifier transistor 404 and is optionally the same physical size as the first small sampling transistor 412. The second small RF sampling transistor 416 is deployed in parallel with the first small sampling transistor 412, however, it does not receive any of the RF drive energy from the input stage. Rather, the second small sampling transistor 416 amplifies and receives only the bias current from the bias networking 414. As a result of this configuration, the predicted power can be corrected for bias current effects and bias current shifts. More specifically, a simple differential amplifier 418 connected between the PWR_Sense and PWR_Sense _Reference can be used to cancel erroneous contributions of the bias current to the predicted power. Similar to the embodiment illustrated in Figure 2, and as illustrated in Figure 5, the varying dc bias of the first sampling transistor 512 can be used in a feed back loop to control a bias circuit and ensure that the bias current to the amplifying transistor 504 is set to a desired value. More specifically, an external operational amplifier 520 may be fed with a reference voltage proportional to the desired bias current in the amplifying transistor 504. The dc bias of the second sampling transistor 516 may also be fed back to the operational amplifier 520. This configuration allows the amplifier bias point to be precisely set by compensating for process or temperature variations which could otherwise cause the bias point to vary from the desired value. Further, when the output power is reduced to low levels, the bias current can be reduced to improve the efficiency of the amplifier. Certain modifications and improvements will occur to those skilled in the art upon a reading of the foregoing description. By way of example, the embodiments described herein above are based upon specific circuit architectures. The present invention is not so limited, however. It shall be understood that those skilled in the art can use a wide variety of circuit architectures including electronic and electromechanical components, either integrated or discrete or combinations thereof to practice the present invention so long as the transistor ratio functionality described herein is retained. Also, it shall be understood that the present invention is not limited to use of a particular processing technology, e.g. HBT, Silicon BJT, CMOS, and the like. It should be understood that all such modifications and improvements have been deleted herein for the sake of conciseness and readability but are properly within the scope of the following claims.

Claims: I Claim: 1. A system for sensing RF amplifier output power and controlling a bias circuit comprising a RF amplifier transistor configured to receive and amplify a RF signal; a first sampling transistor configured to receive and amplify the RF signal, wherein the first sampling transistor is physically smaller than the RP amplifier transistor such that the first sampling transistor is capable of producing a proportionally smaller amplified RF signal than that capable of being produced by the RF amplifier transistor for a RF input signal common to both the RF amplifier transistor and the first sampling transistor; a second sampling transistor configured to receive and amplify a bias circuit signal, wherein the second sampling transistor is physically smaller than the RF amplifying transistor; a first current sensing circuit configured to receive a RF signal amplified by the first sampling transistor and generate a RF current proportional to a RF signal amplified by the RF amplifier transistor; a second current sensing circuit configured to receive a bias circuit signal amplified by the second sampling transistor and generate a bias network current; and a feedback configured to be responsive to the bias circuit current and generate the bias circuit signal. 2. The system according to claim 1 wherein the first and second sampling transistors are of equal size. 3. The system according to claim 1 wherein the second sampling transistor is configured to not receive the RF signal. 4. The system according to claim 1 wherein the bias circuit signal generated by the feedback establishes a quiescent operating point for the RF amplifier transistor, the first sampling transistor, and the second sampling transistor. 5. The system according to claim 1 wherein the feedback is an operational amplifier. 6. The system according to claim 1 further comprising a first bias resistor associated with the RF amplifier transistor. 7. The system according to claim 6 further comprising a second bias resistor associated with the first sampling transistor and a third bias resistor associated with the second sampling transistor. 8. The system according to claim 7 wherein a ratio of resistor values between the first bias resistor and the second bias resistor are substantially equal to a ratio of physical sizes between the first sampling transistor and the RF amplifier transistor. 9. The system according to claim 7 wherein a ratio of resistor values between the first bias resistor and the third bias resistor are substantially equal to a ratio of physical sizes between the second sampling transistor and the RF amplifier transistor. 10. The system according to claim 1 further comprising a first RF signal coupling capacitor configured to pass the RF signal to the RF amplifier transistor. 11. The system according to claim 10 further comprising a second RF signal coupling capacitor configured to pass the RF signal to the first sampling transistor. 12. The system according to claim 11 wherein a ratio of capacitor values between the first RF signal coupling capacitor and the second RF signal coupling capacitor are substantially equal to a ratio of physical sizes between the RF amplifier transistor and the first sampling transistor. 13. A system for sensing RF amplifier output power and controlling a bias circuit comprising: a RF amplifier having a amplifier transistor and further having a first RF signal input port and a first RF signal output port; a first sampling amplifier having a first sampling transistor, a second RF signal input port coupled to the first RF signal input port, and a second RF signal output port, wherein the first sampling transistor is physically smaller than the amplifier transistor; a second sampling amplifier having a second amplifying transistor, a first bias circuit input port, and a first bias circuit output port, wherein the second sampling transistor is physically smaller than the amplifying transistor; a first current sensing network having a third RF signal input port and a first voltage input port, wherein the third RF signal input port is coupled to the second RF signal output port; a second current sensing network having a second bias circuit input port and a second voltage input port, wherein the second bias circuit input port is coupled to the first bias circuit output port; and a feedback configured to be responsive to the second current sensing network and generate a bias circuit signal. 14. The system according to claim 13 wherein the first and second sampling transistors are of equal size. 15. The system according to claim 13 wherein the second sampling transistor does not include an RF signal input port. 16. The system according to claim 13 wherein the bias circuit signal generated by the feedback establishes a quiescent operating point for the first RF amplifier fransistor, the sampling transistor, and the second sampling transistor. 17: The system according to claim 13 wherein the feedback is an operational amplifier. 18. The system according to claim 13 further comprising a first bias resistor coupled at one end to the amplifier transistor and coupled at an opposite end to the feedback. 19. The system according to claim 18 further comprising a second bias resistor coupled at one end to the first sampling transistor and coupled at an opposite end to the feedback. 20. The system according to claim 19, wherein a ratio of resistor values between the first bias resistor and the second bias resistor is substantially equal to a ratio of physical sizes between the first sampling transistor and the amplifier transistor. 21. The system according to claim 19 further comprising a third bias resistor coupled at one end to the second sampling transistor and coupled at an opposite end to the feedback. 22. The system according to claim 21, wherein a ratio of resistor values between the first bias resistor and the third bias resistor is substantially equal to a ratio of physical sizes between the second sampling transistor and the amplifier transistor. 23. The system according to claim 13 further comprising a first RF signal coupling capacitor coupled at one end to the first and second RF signal input port and coupled at an opposite end to the amplifier transistor. 24. The system according to claim 23 further comprising a second RF signal coupling capacitor coupled at one end to the first and second RF signal input port and coupled at an opposite end to the first sampling transistor. 25. The system according to claim 24 wherein a ratio of capacitor values between the first RF signal coupling capacitor and the second RF signal coupling capacitor is substantially equal to a ratio of physical sizes between the amplifier transistor and the first sampling transistor. 26. A system for sensing RF amplifier output power and controlling a bias circuit comprising: amplifying means for amplifying a RF input signal and generating a RF output signal therefrom; first sampling means for sampling the RF input signal that is associated with the amplifying means and generating a sampled RF signal therefrom; second sampling means for sampling a bias circuit signal and generating a sampled bias circuit signal therefrom; first sensing means for sensing the sampled RF signal and generating a current sensing signal therefrom proportional to a power amplitude associated with the RF output signal; second sensing means for sensing the sampled bias circuit signal and generating a bias sensing signal therefrom; and feedback means for responding to the bias sensing signal and generating the bias circuit signal. 27. The system according to claim 26 wherein the bias circuit signal generated by the feedback means establishes a quiescent operating point for the amplifying means, the first samplings means, and the second samplings means. 28. The system according to claim 26 wherein the amplifying means comprises a first transistor. 29. The system according to claim 28 wherein the first sampling means comprises a second transistor, the second transistor being configured to be physically smaller than the first transistor such that a ratio of currents associated with the amplifying means and the first sampling means is equal to a ratio of physical sizes associated with the first and second transistors. 30. The system according to claim 29 wherein the second sampling means comprises a third transistor, the third transistor being configured to be physically smaller than the first transistor such that a ratio of currents associated with the amplifying means and the second sampling means is equal to a ratio of physical sizes associated with the first and third transistors. 31. The system according to claim 30 wherein the second and third transistors are of equal physical size. 32. A method for sensing RF signal power amplitude and controlling a bias circuit, the method comprising the steps of: (a) providing a RF signal amplifier comprising a first transistor having a first predetermined size; (b) providing a first sampling amplifier comprising a second transistor having a second predetermined size that is smaller than the first predetermined size; (c) providing a second sampling amplifier comprising a third transistor having a third predetermined size that is smaller than the first predetermined size; (d) amplifying a RF input signal to produce a first RF output signal; (e) sampling the RF input signal to produce a second RF output signal proportional to the first RF output signal, wherein the proportion is associated with a ratio determined by the first and second predetermined sizes; (f) sampling a bias circuit signal to produce a bias circuit qutput signal; and (g) controlling a bias circuit by responding to the bias circuit output signal and generating the bias circuit signal. 33. A system for sensing RF amplifier output power comprising: a RF amplifier transistor configured to receive and amplify a RF signal; a first sampling transistor configured to receive and amplify the RF signal, wherein the first sampling transistor is physically smaller than the RF amplifier transistor such that the first sampling transistor is capable of producing a proportionally smaller amplified RF signal than that capable of being produced by the RF amplifier transistor for a RF input signal common to both the RF amplifier fransistor and the first sampling transistor; a second sampling transistor configured to receive and amplify a bias circuit signal, wherein the second sampling fransistor is physically smaller than the RF amplifier fransistor; a first current sensing circuit configured to receive a RF signal amplified by the first sampling fransistor and generate a current proportional to a power amplitude associated with the RF signal amplified by the RF amplifier transistor; a second current sensing circuit configured to receive a bias circuit signal amplified by the second sampling transistor and generate a sampled bias circuit current; a feedback configured to be responsive to the sampled bias circuit current and generate the bias circuit signal to establish a quiescent operating point for the RF amplifier fransistor, the first sampling transistor, and the second sampling transistor; a first bias resistor associated with the RF amplifier fransistor; and a second bias resistor associated with the first sampling fransistor; and a third bias resistor associated with the second sampling fransistor; wherein a ratio of resistor values between the first bias resistor and the second bias resistor is substantially equal to a ratio of physical sizes between the first sampling transistor and the RF amplifier fransistor and wherein a ratio of resistor values between the first bias resistor and the third bias resistor is substantially equal to a ratio of physical sizes between the second sampling transistor and the RF amplifier transistor.

Inventors: AUGUSTINE PAUL J, DENING DAVID C, AUGUSTINE, PAUL, J., DENING, DAVID, C.
Applicants: RF MICRO DEVICES INC, RF MICRO DEVICES, INC.
Application year: 2001
Main classification: H04B1
IPC codes: H03F1