HIGH NOISE REJECTION VOLTAGE-CONTROLLED RING OSCILLATOR ARCHITECTURE

Abstract: A ring oscillator circuit, such as a VCO, with a relatively high level of noise rejection for noise originating from both the voltage supply and ground. The ring oscillator circuit is composed of a plurality of differential delay circuits, each differential delay circuit generating a differential ouput signal that is a delayed (and preferably inverted) version of a differential input signal. Each differential delay circuit includes first and second input transistors for receiving the differential input signal. Each differential delay circuit also includes first and second load transistors coupled in parallel with the respective first and second input transistors. Each differential delay circuit further includes a first current source coupled between the first input transistor and a first power supply terminal (e.g., a voltage supply terminal), a second current source coupled between the second input transistor and the first power supply terminal and a third current source coupled between the first and second input transistors and a second power supply terminal (e.g., a ground terminal). The first and second current sources (525, 526) reduce the coupling of noise from the first power supply terminal to the output. The third current source reduces the coupling of noise from the second power supply terminal VDO to the output. The third current source (527) reduces the coupling of noise from the second power supply terminal GNO to the output.

Description: HIGH NOISE P .EJECTION VOLTAGE-CONTROLLED RING ( iSCILLATOR ARCHITECTURE BACKGROUND OF THE INVENTION Field of the Invention This invention relates generally to ring oscillator circuits and. in particular, to a ring oscillator or VCO circuit that provides an improved level of noise rejection for noise originating from both the voltage supply and ground. Description of the Related Art High-speed digital circuits such as microprocessors and memories often employ a phase- locked loop ( PLL) circuit to suppress timing skews between the on-chip clock and the system clock. PLL circuits typically include a voltage-controlled oscillator (VCO) circuit to generate a periodic digital signal. Figure 1 shows a conventional VCO circuit 100. The VCO 100. which is a type of ring oscillator, and consists of N stages of differential inverters 1 10 with the output of the Nth stage connected back to the input of the first stage. The VCO circuit 100 generates an output signal VCO out. which is a periodic digital signal having a frequency that is adjustable by varying the voltage of the frequency control signal Vctrl. The PLL circuit is typically fabricated on the same integrated circuit as the digital circuit and as a result, the switching noise generated by the digital circuit is coupled to the PLL, including the VCO 100. The switching noise is coupled to the PLL circuit through various sources, including the voltage supply VDD, the ground GND and the substrate. The coupling of noise to the VCO 100 causes the output signal VCO out to suffer from jitter (i.e., rapid variations in phase). A conventional approach to reducing the effect of switching noise is to construct the VCO 100 with differential, rather than single-ended, inverters 1 10 so hat the switching noise is rejected by the inverters as common-mode noise. However, under the large-signal conditions under which most VCOs operate, the differential inverters of the VCO may function as a mixer so as to combine the common-mode noise with the differential signal. Consequently, despite its differential operation, the VCO 100 at least partially couples the switching noise to its output. Another conventional approach is to isolate the inverters from the noise source by placing a high-impedance current source between the noise source and the inverter, as shown in Figures 2 and 3. Figure 2 shows a differential inverter 210 including n-type MOSFET input transistors 21 1 and 212 and p-type MOSFET load transistors 21 3 and 214 connected in a conventional differential inverter configuration. The load transistors 213 and 214 are diode-connected with the gate of the transistor connected to the drain. The differential inverter 210 also includes a current source 216 placed between ground and the input transistoi s 21 1 and 212. The current source 216 reduces the coupling of noise from ground becaus.* of ts high impedance relative to the impedance of the ground. Similarl . F igui e 3 shows a differential mvertei 3 10 including PMOS input transistors 31 1 and 312 and n-type MOSFET load transistors 313 and 314 Fhe differential inverter 3 10 also includes a current souice 3 1 5 placed between the voltage supply VDD and the input transistors 3 1 1 and 312. The current source 315 reduces the coupling of noise from the \ oltage supplv VDD because of its high impedance relative to the impedance of VDD. A antage of the differential inverters 210 and 310 is that they are capable of ι c)cctmg noise Irom onlv one of the potential switching noise sources VDD and ground, but not both. Consequently, sw itching noises onginating from the other supplv (I c, VDD lor the differential inv erter 21 0 and ground lor the differential inverter 3 1 ) can still affect the output of the di f ferential inverter, thereby causing jitter in the output signal VC()_out. In view of the shortcomings of these approaches, ii is an ob]ect of the present invention to pi ov ide a VCO circuit w ith an improv ed level of noise I election for noise originating from both the v oltage supplv and ground, I e . an improv ed powei supply i election ratio ( PSRR) SUMMARY Ol I HE INVENTION I he pi esent inv ention comprises a ring oseillutoi ciicuit. such as a VCO. ith a l elativclv high lev el of noise ιc)ectιon for noise onginating liom both the voltage supplv and giound The πng oscillatoi cn cuit is composed ot a plurality of dif ferential delav circuits, each dif ferential delav circuit generating a dif ferential output signal that is a delav cd (and preferably inverted) version ol a dif f erential input signal Lach dif ferential delay circuit includes fust and second input transistoi s f or receiving the dif ferential input signal Each differential delav circuit also includes first and second load transistors coupled in parallel with the respective first and second input transistoi s Lach differential delav circuit f urther includes a first current source coupled between the fu st input transistor and a first power supply terminal, a second current source coupled between the second input transistor and the first po ei supplv tei minal and a third current source coupled between the fu st and second input tiansistors and a second power supplv terminal In a prelerred embodiment ol the invention, the f u st powei supply terminal consists ol a voltage supplv terminal and the second power supply tei minal consists of a ground tei minal In other embodiments, hovvev ei . the fu st and second power supplv tei minals may be reversed I he πng oscillator circuit ol the present invention provides an improv ed lev el of noise rc|ectιon over prior art VCO circuits because the inventive differential delay circuit rc|ects noise originating from both the voltage supply and ground. Specifically, the first and second current sources reduce the coupling oi noise horn the fust power supplv terminal to the output, w hile the third current source reduces the coupling of noise from the second power supply terminal to the output These and other features and advantages of the invention will be better appreciated from the following detailed description of the invention together with the appended drawings. BRIEr DESCRIPTION OF THE DRAW INGS figure 1 is a cncuit diagram ot a conventional VCO circuit figures 2 and 3 aie circuit diagiams ot con entional differential inv eiteis used in the VCO circuit of Tiguie 1 I igure 4 is a circuit diagram of a VCO circuit in accoi dance with an embodiment of the present mvention 1 iguie 5 is a cncuit diagram of the differential delav circuit used in the VC O circuit of I iguie 4 DEI ΛILL D Dl SC RIP I ION OI TI IF PRCITRRCD LMBOD1MI N I S 1 he piesent invention comprises a i mg oscillator cncuit such as a VC () w ith an impro ed level of noise i election foi noise onginating Irom both the v ltage supplv and giound I e an improved PSRR \s a result the output signal generated bv theπngoscillatoi cncuit sulieis fiom less |itteι than conventional ring oscillator or VCO circuits in the piesence ol stich noise Consequentlv the ring oscillator ol the present invention is especiallv suitable loi use as a VCO in integrated cncuits that include digital cncuits such as micropioccssors oi digital signal processois (DSPs) I he following descnption is presented to enable Λ\ \ puson skilled in the ait to make and use the invention, and is piovided in the context of a particulai application and its lequiiements Various modifications to the prefciied embodiment will be ieadilv uppaient to those skilled in the ait and the genciic piinciples delined heiein mav be applied to other embodiments and applications without departing fiom the spint and scope of the invention Moieovei, the following description numeious details are set forth lor purpose of explanation However one ol ordinaiv skill in the art would reah/e that the invention mav be piacticed without the use ol these specific details In other instances well-known stiuctures and devices aie shown in block diagram foim in older not to obscure the descnption of the invention with unnecessaiv detail I hus the piesent invention is not intended to be limited to the embodiment shown but is to be accoided the widest scope consistent ith the piinciples and leatuics disclosed herein I igure 4 shows a iing oscillator oi more specillcallv a VC 0400 in accoi dance with a preferred embodiment ol the invention 1 he oveiall stiuctuie and function ot the VC O 400 is similar to that ot the conventional VCO 100 described in the background section except foi those features pertaining to voltage supply and ground noise The VCO 400 includes N stages ol differential delav cncuits or cells 410 where N is an odd number In the paiticular embodiment shown in the figure N = 3 Lach diffeiential delav circuit 410 generates an output signal that is an inverted and delayed version ot the input signal Ihe output signal is delavcd fiom the input signal bv a phase delav of AF The output ot each diffeiential delav cncuit 41 is connected to the input of the subsequent diffeiential delav cncuit stage except for the Nth stage 1 or the Nth stage, the output is connected back to the input of the fist diffeiential delav circuit stage The VCO 400 generates a periodic digital output signal VCO_out The frequencv f of the output signal VCO_out is a function of the phase delav A T of the differential delav cncuit 410 Specificallv t = 1 ' (2 * N * Δ f) The VCO 400 receives a frequencv contiol signal Vctrl for adiusting the fiequencv t of the output signal VCO_out The VCO 400 pro ides a relatively high level of ιc|ectιon of noise onginating liom the voltage supplv VDD and giound As a result, the output signal VCO_out does not suffer significantlv from jitter e\ en in the presence of substantial amounts ol voltage supplv or ground noise I ach dilteiential delav cncuit 410 in a preferred embodiment leceives and transmits the lollowing signals ( 1 ) Diffeiential input signal \ in Ihe differential input signal Vin is received from the output ol the pieceding dilteiential delav circuit 410 Ihe diifetcntial input signal Vin is a diffeiential signal comprising a first differential input signal component Vin-t- and a second dilteiential input signal component Vin- The first and second differential input signal comp i nts Vιn+ and Vin- are input to lust and second input teiminals of the differential delav _ιιcuιt410 lespectivelv (2) Dilteiential output signal Vout The differential delay cncuit 410 generates the dilteiential output signal Vout which is an inverted and delavcd version of the differential input signal Vin 1 he dif erential output signal Vout lags the differential input signal Vin in phase by the phase delav \ 1 I he differential output signal Vout is used as the dilteiential input signal Vin tor the succeeding differential delav cncuit 410 The differential output signal Vout is a dilteiential signal comprising a first differential output signal component Vout-and a second dilteiential output signal component Vout+ The first and second differential output signal components Vout- and Vout+ are output on first and second output terminals ot the differential delay cncuit 410 lespectivelv Ihe differential output signal Vout also has a common-mode voltage Vem As is known in the art the common-mode voltage Vein is the voltage that appears in common at the fust and second output teiminals with lespect to a leference voltage (e g , ground) (3) Releience voltage signal Vref The reference voltage signal Vref is used to adjust the common-mode voltage \ cm ol the diffeiential output signal Vout The reference voltage signal Vrel is received from a reference voltage circuit 460 explained below (4) frequencv control signal Vctil The frequencv control signal Vctrl is used to adjust the phase delav A I ot the differential delav circuit 410 and thus the frequencv 1 of the output signal VCO out The liequencv control signal Vctil is generated bv a source external to the VCO 400 such as a phase-detectoi circuit (not shown) which is a circuit well-known in the ait, contained within the same PLL circuit as the VCO 400 The VCO 400 also includes an output buffer 450 The output buffei 450 converts the differential output signal Vout geneiatcd bv the Nth differential delav circuit 410 mto the digital output signal VCO_out The VCO 400 fuithei includes a leference voltage circuit 460 The leterence voltage circuit 460 generates the reference voltage signal Vief that is supplied to each of the differential delav circuits 410 ot the VCO 400 The reference voltage signal Vief is used to adjust the common-mode voltage Vem ot the differential output signal Vout to the desired level In this embodiment the leterence voltage signal Viet equals the desired common-mode voltage Vem of the diffeiential output signal Vout The reference v ltage circuit 460 is a tvpe of circuit that is well-known in the ait and thus will not be described further 1 he differential delav circuits 41 and the leterence voltage cncuit 460 of the VCO 400 aie connected to sepaiate voltage supplies and giounds I he diffeiential delav circuits 410 arc connected to a voltage supplv teiminal VDD and a giound terminal GND Ihe voltage supplv teiminal VDD and ground teiminal are tvpicallv connected to manv other cncuits and mav contain significant amounts of switching noise especiallv if connected to oi touted near noise- geneiating digital circuits 1 he ielcrence voltage circuit 460 is connected to a reference-voltage voltage supplv teiminal VDD_rel and a leterence-voltage giound terminal GND_ιet VDD rel and GND i ei aie usuallv relativelv noise-hee because thev aie tvpicallv connected to lelativclv tew other cncuits and aie routed awav Irom digital cncuits and othei noise souices I igure 5 shows the details ol a diff rential delav circuit 410 ot the VC () circuit 400 in accoidance with a pieteired embodiment of the invention Ihe diffeiential delav cncuit 410 provides a ldativelv high level of isolation from noise onginating liom both the voltage supply and giound C onsequentlv, the VCO output signal VC 0_out has a i educed amount ol jittci in the presence ol such noise In this embodiment the dilfcrential delav cncuit 410 is implemented using CMOS technologv In alternative embodiments of the invention however the diffeiential delay cncuit 410 mav be implemented using other technologies such as silicon bipolar and GaAs HBT Ihe differential dela> circuit 410 comprises a differential mveitcr 520 and a common- mode feedback (CMIB) cncuit 540 Ihe dilfcrential mveitei 520 generates the diffeiential output signal Vout that is an inverted and delayed vei ion ol the diffeiential input signal Vin Ihe CMTB cncuit 540 is connected in a teedback loop with the differential mveitei ~>20 to adjust the common-mode voltage Vem ol the diffeiential output signal Vout geneiated bv the diffeiential delav cncuit as explained further below The diffeiential inverter 520 is essentially a modification of a conventional differential inverter, such as the inverter 210 ot 1 igure 2 Using the differential mveitcr 210 as an example the first and second folded load tiansistors ~>23 and 524 are formed bv, changing the load transistois 213 and 214 fiom p-tvpe MOSTETs to n-tvpe MOSrETs and 'folding them over so that thev are no longer connected to the oltage supplv teiminal VDD but rather aie connected in paiallel with the respective input tiansistors 321 and 522 Two cuπent souices 525 and 526 are then inserted between the folded load transistors 523 a id 524 and the v oltage supplv terminal VDD Ihe diffeiential output signal Vout of the ditf renth 1 mvertei 520 is thus isolated from noise originating from both the vo tage supplv VDD and giound bv the cuirent sources 525, 526 and 527 In a preleired embodiment if the invention the dilfcrential inveiter 520 includes fust and second input tiansistois 521 and ' 22 ist and second folded load tiansistors 523 and 524 and fust second and third cuirent sources 525526 and 527 In this embodiment the in stand second input transistois 521 and 522 and the first and second folded load tiansistois 523 and 524 each compπse an n-tv pe MOSFET The fust and second cuπent souices 525 and 526 each consist of a p-tv pe MOS1 FT and the third current source 527 consists ot an n-tv pe MOSTET In alternative embodiments of the invention the dilteiential mvertei 520 may be implemented using othei logicaliv-equivalent device configurations lorexample the first and second input tiansistois 521 and 522 and the first and second iolded load transistors 523 and 524 mav each compπse a p-tvpe iathei than an n-t pe MOSTTT In this embodiment the diffeiential mveitei 520 would include one cuirent souice consisting ol a p-tv pe MOS1 TT connected to the voltage supplv teiminal VDD and two cuirent souices each consisting ot ΛI n-t pe MOSTFT connected to the mound teiminal I he lust and second input tiansistois 521 and 522 ieceive the lespective fust and second diffeiential input signal components Vm+and Vin- so as to control the diffeiential output signal Vout Ihe gates ol the fust and second input transistois 521 and 522 aie connected to the icspective tlist and second input teiminals (indicated bv Vm+ and Vin- lespectivelv) Ihe lust and second folded load tiansistors 523 and 524 aie diode-connected and thus function as icsistive loads tor the differential mvertei 520 Unlike conventional lesistive loads, however the fust and second folded load tiansistois 523 and 524 aie "folded" back on the lespective fust and second input tiansistois 521 and 522 to accommodate the respective fust and second cuirent sources 525 and 526 I he gates of the first and second folded load tiansistors 523 and 524 are each connected to thediains ol the respective tiansistors to foim resistive loads The first iolded load tiansistoi 523 is connected in parallel with the fust input tiansistor 521 Specificallv the diain/gate of the lust folded load transistoi 523 mav be connected to the diain ol the fust input tiansistor 521 and the souice ol the lust folded load tiansistor may be connected to the source ot the fust input tiansistor Similailv the second folded load tiansistor 524 is connected in paiallel with the second input transistoi 522 Specificallv the diain/gate of the second Iolded load transistoi 524 mav be connected to the diainot the second input transistor 522 and the source ot the second folded load transistor mav be connected to the source of the second input transistor Fhe first and second current souices 525 and 526 aie current sources connected between the voltage suppl} teiminal VDD and the respective input and folded load tiansistors Specifically the first current souice 525 is connected between the oltage suppl) terminal VDD and the drains of the fust input tiansistoi 521 and the first folded load tiansistoi 523 The first differential output signal component Vout- is generated at the point where the first current source 525 connects to the drains of the first input transistor 521 and the first folded load transistor 523. Similarly, the second current source 526 is connected between the voltage supply terminal VDD and the drains of the second input transistor 522 and the second folded load transistor 524. The second differential output signal component Vout+ is generated at the point where the second current source 526 connects to the drains of the second input transistor 522 and the second folded load transistor 524. The first and second current sources 525 and 526 supply current to and bias the transistors 521 and 522 to the proper region of operation. The first and second current sources 525 and 526 also reduce the coupling of noise from the voltage supply terminal VDD to the output because the impedances of the current sources are higher than the impedance at the voltage supply terminal VDD. The first and second current sources 525 and 526 each receive the frequency control signal Vctrl to control the amount of current generated by the current sources, thereby varying the phase delay Δ ' f of the differential delay circuit 410. In the embodiment where the first and second current sources 525 and 526 comprise p-type MOSFETs. the frequency control signal Vctrl is input to the gates of the transistors. The third current source 527 is a current source connected between the input and folded load transistors and the ground terminal. Specifically, the third current source 527 is connected between the sources of the input transistors 521 and 522 and the folded load transistors 523 and 524 and the ground terminal. The third current source 527 drains current from and biases the transistors 521 and 522 to the proper region of operation. In a preferred embodiment of the invention, the average current produced by the third current source 527 is approximately twice that produced by each of the first and second current sources 525 and 526. The third current source 527 also reduces the coupling of noise from the ground terminal to the output because the impedance of the third current source is higher than the impedance at the ground terminal. The third current source 527 receives the frequency control signal Vctrl to control the amount of current generated by the current source, thereby varying the phase delay Δ ' f of the differential delay circuit 410. In addition, the third current source 527 receives the feedback signal Vcmfb from the CMFB circuit 540 to further adjust the level of generated current. The feedback signal Vcmfb adjusts the current to set the common-mode voltage Vem of the differential output signal Vout at a level appropriate for the proper operation of the differential inverter 520. In the embodiment where the third current source 527 comprises an n-type MOSFET. the frequency control signal Vctrl and the feedback signal are combined in a manner appropriate for the proper operation of the differential inverter 520. as can be performed by one skilled in the art. In the preferred embodiment just described the frequencv contiol signal Vctrl is applied to all thiee cuπent souices 525.526 and 527 and the leedback signal Vcmfb is applied to the third cuπent source 527 onlv In alternati e embodiments of the invention the fiequencv contiol signal Veti 1 and the feedback signal V cmfb mav be applied to the current sources in a different manner In a fust alternativ e embodiment the frequencv control signal Vctrl is applied to the first. second and thu d cuirent sources 525.526 and 527 and the feedback signal Vcmfb is applied to the fu st and second current sources 525 and 526 In a second alternativ e embodiment, the li equenev conti ol signal Vcti l is applied to the first and second current sources 525 and 526 and the leedback signal Vcmfb is applied to the third current source 527 In a third alternative embodiment the f iequencv control signal Vctrl is applied to the third current source 527 and the leedback signal \ cmtb is applied to the fu st and second current sources 525 and 526 More genei allv the pai ticulai connections and voltage lev els appropriate for the frequencv control signal Vctrl and the f eedback signal Vcmlb depend upon the implementation of the diffeiential inv c" *' 520 and can be determined bv one skilled in the ai t As show n in 1 igui e ;> a v ii tual giound node VG is formed at the point where the sources of the input tiansistois ">21 and 522 the sources of the folded load tiansistors 523 and 524 and the thud cui rent soui ce 527 connect Vntual gi ound nodes aie well-known in the art of dif feiential cncuit design and thus will not be explained further 1 he common-mode feedback (C MI B) circuit 540 ot the differential delav circuit 410 is used to ensuie the proper operation of the dif feiential inverter 520 T he CMTB cncuit 540 compares the common-mode v oltage V em of the differential output signal Vout with the releience v oltage signal Vief and based on this comparison generates a feedback signal Vcmfb Thus Vcmfb = Vem - Vref I he leedback signal Vcmlb is used to control the common-mode voltage Vem ol the differential output signal Vout produced bv the differential inverter 520 such that Vein iemains at a level appropriate tor the proper operation of the differential inverter 520 In a preteπcd embodiment ol the invention, the feedback signal Vcmfb controls the output current ol the third cui rent source 527 w hich in turn controls the common-mode voltage Vem ol the dif feiential output signal Vout 1 he CMI B circuit 540 is a t> pe ot feedback circuit that is well-known in the ai t and thus need not b descπbed in detail I he operation of the dilfcrential delay circuit 410 w ill now be described As mentioned earlier, the dif ferential delav cncuit 410 inveits and delays the differential input signal Vin to produce the dif ferential output signal Vout When the diffeiential input signal Vin is set to a logic value ol "1" the fu t input terminal (indicated bv Vιn+) assumes a differentially high voltage and the second input terminal (indicated bv Vin-) assumes a differentially low voltage The differentially high v oltage at the fust input terminal turns the first input tiansistor 521 "on" (l e , the conducting state) therebv steering a bias current awav from the fu st load tiansistor 523 As a result, the first output terminal (indicated b> Vout-) is pulled low bv the third current source 527 to a diffeientiallv low voltage The differentialh low voltage at the second input terminal turns the second input transistor 522 "off (i.e., the non-conducting state), thereby steering the bias current through the second load transistor 524. As a result, the second output terminal (indicated by Vout+) is pulled high by the second current source 526 to a differentially high voltage. Consequently, when the differential input signal Vin assumes the logic value of "I", the differential output signal Vout switches to the logic value of "0" after the phase delay ΔT. Conversely, when the differential input signal Vin is set to the logic value of "0". the first input terminal assumes a differentially low voltage and the second input terminal assumes a differentially high voltage. The differentially low voltage at the first input terminal turns the first input transistor 521 otϊ. thereby steering a bias current through the first load transistor 523. As a result, the first output terminal is pulled high by the first current source 525 to a differentially high voltage. The differentially high voltage at the second input terminal turns the second input transistor 522 on. thereby steering the bias current away from the second load transistor 524. As a result, the second output terminal is pulled low by the third current source 527 to a differentially low voltage. Consequently, when the differential input signal Vin assumes the logic value of "0", the differential output signal Vout switches to the logic value of "I" after the phase delay ΔT. The phase delay AT between the differential input signal Vin and the differential output signal Vout can be adjusted by varying the voltage of the frequency control signal Vctrl. The frequency control signal Vctrl varies the current produced by the first, second and third current sources 525. 526 and 527. thereby varying the phase delay ΔT of the differential delay circuit 410. The particular voltage levels appropriate for the frequency control signal Vctrl depend upon the implementation of the differential inverter 520 and can be determined by one skilled in the art. In a preferred embodiment of the invention, the differential delay circuit 410 is implemented on an integrated circuit that includes guard rings or substrate taps (not shown) connected to the ground terminal. The guard rings or substrate taps, which are physical structures that consist of highly-doped regions of the substrate as is known in the art. are placed adjacent to and surrounding the transistors 521. 522. 523 and 524 of the diff erential delay circuit. The guard rings or substrate taps are connected to the ground terminal so that any noise coupled through the substrate, such as from adjacent digital circuits, is shunted to ground, rather than being coupled to the transistors 521. 522. 523 and 524 and possibly coupled to the differential output signal Vout. The noise originating from the ground terminal is prevented from entering the differential delay circuit 410 by the third current source 527. as described earlier. Consequently, in addition to rejecting voltage supply and ground noise, the differential delay circuit 410 in this embodiment also rejects substrate noise. To verify the operation of the differential delay circuit 410. computer simulations of both the conventional VCO 100 and the VCO 400 of the present invention were performed using SPICE. The conventional VCO 100 includes the differential inverter 210 shown in Figure 2. The VCO 400 includes the differential delav circuit 41 0 snown in Fitiure 5. The simulation results show that the level of noise rejection from both the voltage supply VDD and ground provided by the VCO 400 is about 8 dB hit her than that of the conventional VCO 100. While specific embodiments of the invention have been described and illustrated, it will be appreciated that modifications can be made to these embodiments without departing from the spirit of the invention. Therefore, it ,s intended that the scope of the invention be defined by the following claims and their equivalents.

Claims: CLAIMS 1 . A ring oscillator circuit, comprising: a plurality of differential delay circuits interconnected in a ring configuration, wherein each differential delay circuit is coupled to first and second power supply terminals and comprises: first and second input transistors for receiving a differential input signal; first and second load transistors coupled in parallel with the first and second input transistors, respectively: a first current source coupled between the first input transistor and the first power supply terminal; a second current source coupled between the second input transistor and the first power supply terminal; and a third current source coupled between the first and second input transistors and the second power supply terminal. 2. Fhe ring oscillator circuit of Claim 1 . w herein: the first power supply terminal comprises a voltage supply terminal; and the second power supply terminal comprises a ground terminal. 3. The ring oscillator circuit of Claim 1 , wherein: the first power supply terminal comprises a ground terminal; and the second power supply terminal comprises a voltage supply terminal. 4. The ring oscillator circuit of Claim 1. wherein the first and second load transistors of each differential delay circuit are each diode-connected. 5. fhe ring oscillatot circuit of Claim 1. w herein the first and second load transistors of each differential delay circuit each comprise a folded load transistor. 6. The ring oscillator circuit of Claim 1. wherein the third current source of each differential delay circuit operatively generates a current that is about twice as large as a current operatively generated by the first or second current sources. 7. The ring oscillator circuit of Claim 1 , wherein each differential delay circuit further comprises a common-mode feedback circuit for comparing a common-mode voltage of the differential output signal to a reference voltage signal generated by a reference voltage circuit and for generating a feedback signal based upon the comparison. 8. The ring oscillator circuit of Claim 7. wherein: at least one of the first, second and third current sources of each differential delay circuit includes a control input for receiving the feedback signal: and the at least one current source of each differential delay circuit generates a current that is responsive to the feedback signal. 9. The ring oscillator circuit of Claim 1. wherein: at least one of the first, second and third current sources of each differential delay circuit includes a control input for receiving a frequency control signal; and the at least one current source of each differential delay circuit generates a current that is responsive to the frequency control signal; the ring oscillator circuit thereby comprising a voltage-controlled oscillator circuit. I :) The ring oscillator circuit of Claim 1 , wherein the first and second input transistors of each differential delay circuit each comprise a MOSFET. 1 1 . I he ring oscillator circuit of Claim 1 , wherein the first and second load transistors of each differential delay circuit each comprise a MOSFET. 12. 1 " he ring oscillator circuit of Claim 1. wherein the first, second and third current sources of each differential delay circuit each comprise a MOSFET. 1 3. A ring oscillator circuit, comprising: a pluralitv- of differential delay cells interconnected in a ring configuration, wherein each differential delav- cell is connected to a voltage supply and to a ground and comprises: first and second input transistors for receiving a differential input signal; a first current source connected between the first input transistor and the voltage supply: a second current source connected between the second input transistor and the voltage supply; a third current source connected between the first and second input transistors and the ground; a first load device connected between the first and third current sources; and a second load device connected between the second and third current sources. 4. A voltage-controlled oscillator circuit, comprising: a plurality of differential delay circuits interconnected in a ring configuration, wherein each differential delay circuit is coupled to first and second power supply terminals and comprises: first and second input transistors for receiving a differential input signal; first and second load transistors coupled in parallel with the first and second input transistors, respectively; a first current source coupled between the first input transistor and the first power supply terminal; a second current source coupled between the second input transistor and the first power supply terminal: and a third current source coupled between the first and second input transistors and the second power supply terminal. 15. The voltage-controlled oscillator circuit of Claim 14. wherein: the first power supply terminal comprises a voltage supply terminal; and the second power supply terminal comprises a ground terminal. 16. The voltage-controlled oscillator circuit of Claim 14, wherein: the first power supply terminal comprises a ground terminal; and the second power supply terminal comprises a voltage supply terminal. 17. The voltage-controlled oscillator circuit of Claim 14, wherein the first and second load transistors of each differential delay circuit are each diode-connected. 18. The voltage-controlled oscillator circuit of Claim 14. wherein the first and second load transistors of each differential delay circuit each comprise a folded load transistor. 19. The voltage-controlled oscillator circuit of Claim 14. wherein the thud current source of each difTerential delay circuit operatively generates a current that is about twice as large as a current operatively generated by the first or second current sources. 20. The voltage-controlled oscillator circuit of Claim 14, wherein each differential delay circuit further comprises a common-mode feedback circuit for comparing a common-mode voltage of the differential output signal to a reference voltage signal generated by a reference voltage circuit and for generating a feedback signal based upon the comparison. 21. The voltage-controlled oscillator circuit of Claim 20. wherein: at least one of the first, sec md and third current sources of each differential delay circuit includes a control input for recen ing the feedback signal, and the at least one current sou ce of each differential delay circuit generates a current that is responsive to the feedback signal 22 The voltage-controlled oscillator circuit of Claim 14. wherein at least one of the fu st, second and third cui rent sources of each dif ferential delay circuit includes a contiol input foi receiving a f iequencv control signal, and the at least one current source ol each dif ferential delay circuit generates a current that is lesponsive to the frequencv control signal 23 I he voltage-contiolled oscillatoi circuit of Claim 14. wheiein the first and second input transistoi s ol each dil fcrential delav cncuit each compπse a MOSFET 24 I he v oltage-controlled oscillator circuit ot C laun 14 wherein the fu t and second load ti ansistoi s ol each dif ferential delav circuit each comprise a MOSFET 25 I he voltage-contiolled oscillatoi circuit ol Claim 14, wheiein the fu st, second and third current sources ol each dilfcrential delay circuit each comprise a MOSFET 26 A voltage-controlled oscillator circuit, comprising a pluralitv of differential delay cells interconnected in a ring configuration, wherein each differential delav cell is connected to a v oltage supply and to a ground and comprises lii st and second input transistois lor receiving a diffeiential input signal, a first current souice connected between the first input tiansistor and the voltage supplv a second cui ient soui ce connected between the second input transistor and the voltage suppl) , a third cui ient source connected between the fust and second input transistors and the ground. a first load dev ice connected between the first and third current sources, and a second load dev ice connected between the second and third current sources 27 A differential delav circuit coupled to first and second power supply terminals, comprising first and second input transistors for receiving a differential input signal. first and second load transistors coupled in parallel with the first and second input transistors, respectively; a first current source coupled between the first input transistor and the first power supply terminal; a second current source coupled between the second input transistor and the first power supply terminal: and a third current source coupled between the first and second input transistors and the second power supply terminal. 28. I he differential delay circuit of Claim 27. wherein: the first power supply terminal comprises a voltage supply terminal: and the second power supply terminal comprises a ground terminal. 29. The differential delay circuit of Claim 27, wherein: the first power supply terminal comprises a ground terminal; and the second power supply terminal comprises a voltage supply terminal. 30. The differential delay circuit of Claim 27, wherein the first and second load transistois are each diode-connected. 3 1 . The differential delay circuit of Claim 27. wherein the first and second load transistors each comprise a folded load transistor. 32. The differential delay circuit of Claim 27, further comprising a common-mode feedback circuit for comparing a common-mode voltage of the differential output signal to a reference voltage signal generated by a reference voltage circuit and for generating a feedback signal based upon the comparison. 33. The differential delay circuit of Claim 32. wherein: al least one of the first, second and third current sources includes a control input for receiving the feedback signal: and the at least one current source generates a current that is responsive to the feedback signal. 34. The differential delay circuit of Claim 27. wherein: at least one of the first, second and third current sources includes a control input for receiving a frequency control signal; and the at least one current source generates a current that is responsive to the frequency control signal. 35. The differential delay circuit of Claim 27, wherein the third current source operatively generates a current that is about twice as large as a current operatively generated by the first or second current sources. 36. The differential delay circuit of Claim 27, wherein the first and second input transistors each comprise a MOSFET. 37. The differential delay circuit of Claim 27, wherein the first and second load transistors each comprise a MOSFET. 38. The differential delay circuit of Claim 27. wherein the first, second and third current sources each comprise a MOSFET. "9. A differential delay circuit connected to a voltage supply and to a ground. comprising: first and second input transistors for receiving a differential input signal; a first current source connected between the first input transistor and the voltage supply; a second current source connected between the second input transistor and the voltage supply; a third current source connected between the first and second input transistors and the ground; a first load device connected between the first and third current sources: and a second load device connected between the second and third current sources. 40. A method of minimizing the coupling of noise sources from voltage and ground lines to a differential delay circuit, comprising the steps of: supplying power to first and second current sources from a first power supply terminal; supplying power to a third current source from a second power supply terminal; generating first, second and third currents from respective first, second and third current sources; sinking a current from the first current source to a first terminal of a first input transistor; sinking a current from the first current source to a first terminal of a first load transistor; sinking a current from the second current source to a first terminal of a second input transistor; sinking a current from the second current source to a first terminal of a second load transistor, and sinking a plurality of currents from the third current source to a second terminal of each of the plurality of first and second input and load transistors. 41. The method of claim 30. wherein the first power supply terminal comprises a voltage supply terminal and the second power supply terminal comprises a ground terminal. 42. The method of claim 30, wherein the first power supply terminal comprises a ground terminal and the second power supply terminal comprises a voltage supply terminal.

Inventors: LIU BIN, LIU, BIN
Applicants: BROADCOM CORP, LIU BIN, BROADCOM CORPORATION, LIU, BIN
Application year: 2001
Main classification: H03K3
IPC codes: H03F3, H03K3, H03K5, H03L7