Clock signal generator and communication device using the same

Abstract: An edge detector circuit 103 detects the edge of an original clock signal S102 generated by the clock signal generator circuit 102. A counter 104 counts the number of edges of the original clock signal S102. The counter 104 is reset when the preset counter value S101 is reached, and repeats counting operation. A clock signal modification circuit 105 masks the original clock signal S102 when the counter value has reached the preset counter value to generate a baud rate control clock signal S105. An input circuit 107 latches input data S106 per predetermined rising edge of the clock signal with the band rate control clock signal S105 and outputs an output signal S107.

Description: BACKGROUND OF THE INVENTION The present invention relates to a clock signal generator for generating a desired clock signal by adding a peripheral circuit to clock signal generating means and communications apparatus using the clock signal generator. Asynchronous communications such as RS-232C are widely known and used in a variety of fields. Asynchronous communications are an essential feature for personal computers. A precise clock signal is required also in asynchronous communications. A variety of clock signal generators have been developed and added to a library. In case asynchronous communications are carried out by using a conventional clock signal generator that has been added to a library, a desired clock signal thus a correct baud rate may not be obtained by frequency division. For example, according to the RS-232C specifications (EIA/TIA-22-E), a maximum transfer rate is 20 kbps although the transfer rate exceeds this limit in practice. This may cause problems such as a communication error thus requesting re-design of the entire communications apparatus. While re-designing a clock signal generator can customize the frequency division feature of the clock signal and a precise baud rate can be obtained, a considerable increase in the number of development man-hours and another trouble may be caused by a new design. The article "Build A Cycle-Stealing Ratio Divider" by Bundgard T (Electronic Design, Penton Publishing, Cleveland, OH, US, vol. 47, no. 11, May 31, 1999), pages 72-73, shows a cycle-stealing ratio divider, which is used to produce multiple individual frequencies from a base frequency f. The document shows a simple technique using standard digital components, such as the counter IC Intel 8254 to produce discrete frequencies with jitter and accuracy comparable to those of a typical phase-locked-loop implementation using standard digital components. SUMMARY OF THE INVENTION The invention, in view of the aforementioned problems, aims at reducing the number of man-hours required for custom design of a clock signal generator, by having a configuration where an additional circuit is incorporated into an existing highly reliable clock signal generator circuit and an intermittent clock signal is generated to obtain a baud rate, instead of making a design by customizing a clock signal generator circuit for generating a clock signal whose frequency is constant. In order to solve the aforementioned problems, a cycle stealing ratio divider is provided as defined in the appended claims. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a block diagram of communications apparatus according to embodiment 1 of the invention. Fig. 2 is a first timing chart explaining the operation of the communications apparatus shown in Fig. 1. Fig. 3 is a second timing chart explaining the operation of the communications apparatus shown in Fig. 1. Fig. 4 is a third timing chart explaining the operation of the communications apparatus shown in Fig. 1. Fig. 5 is a block diagram of communications apparatus according to embodiment 2 of the invention. Fig. 6 is a timing chart explaining the operation of the communications apparatus shown in Fig. 5. Fig. 7 is a block diagram of communications apparatus according to embodiment 3 of the invention. Fig. 8 is a timing chart explaining the operation of the communications apparatus shown in Fig. 7. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of the invention will be described referring to the drawings. (Embodiment 1) A clock signal generator and communications apparatus using the cycle stealing ratio divider according to embodiment 1 regenerates a baud rate clock signal by correcting a clock output by an existing clock generator circuit in generating a clock signal. Thus, the number of man-hours required for custom design of a clock signal generator is reduced in designing communications apparatus. A clock signal generator and communications apparatus using the clock signal generator according to embodiment 1 will be described referring to Figs. 1 through 4. Fig. 1 is a block diagram of a clock signal generator and communications apparatus using the clock signal generator according to embodiment 1 of the invention. The communications apparatus 100 is composed of a preset counter value input terminal 101, a clock signal generator circuit 102, an edge detector circuit 103, a counter 104, a clock signal modification circuit 105, an input terminal 106, an input circuit 107, and an output terminal 108. Operation of the clock signal generator and the communications apparatus using the clock signal generator will be described. As shown in Fig. 2, the edge detector circuit 103, on detecting the rising edge of an original clock signal S102 generated by the clock signal generator circuit 102, outputs a High signal as an edge signal to the counter 104. The counter 104 is incremented when an edge signal S103 is input. The counter 104 is zero-cleared when the counter value S104 becomes identical with the preset counter value S101. The clock signal modification circuit 105 masks the original clock signal S102 in case the counter value S104 is identical with the preset counter value S101. Otherwise, the clock signal modification circuit 105 outputs a baud rate control clock signal S105 to the input circuit 107 without masking the original clock signal S102. With the timing shown in Fig. 3, the input circuit 107 latches input data S106 per predetermined rising edge of the baud rate control clock signal S105 and sequentially outputs the input data S106 to an external data output terminal 108. In this embodiment, a baud rate is realized via accuracy of the baud rate clock signal alone by generating an intermittent baud rate clock signal, instead of using a 4/3-times clock signal. Fig. 4 is a timing chart comparing the case where the input signal S106 is captured via a precision clock signal S400 (S401) and the case where the input signal S106 is captured via a baud rate control clock signal S105 (107) in case the precision clock signal S400 as a 4/3-times clock signal is generated with a clock signal generator circuit customized. As understood from comparison between S107 and S401, capture timing completely matches at 12 cycles for the output baud rate control clock signal and the precision clock signal. This eliminates the effects of capturing jitter caused by an intermittent signal. As mentioned earlier, a desired baud rate is realized by performing communications via a baud rate clock signal regenerated using an intermittent clock signal even when conventional communications apparatus whose baud rate clock signal is less accurate. Such a configuration uses only a circuit that generates an intermittent clock signal for compensation. Thus the number of man-hours required for designing a customized clock signal generator circuit is drastically reduced. While data input from the baud rate clock signal is specified as shown in Figs. 3 and 4, this invention is not limited to this configuration. While the clock signal modification circuit processes a delayed input baud rate control clock signal, the delay amount is variable and it is possible to process an input baud rate control clock signal without delay. (Embodiment 2) A clock signal generator and communications apparatus using the cycle stealing ratio divider according to embodiment 2 of the invention is characterized in that the frequency range where a baud rate clock signal can be corrected is extended without substantially enhancing the circuit scale. A clock signal generator and communications apparatus using the cycle stealing ratio divider according to embodiment 2 will be described referring to Figs. 5 and 6. Fig. 5 is a block diagram of a clock signal generator and communications apparatus using the clock signal generator according to embodiment 2 of the invention. In Fig. 5, the same reference numerals correspond to those in Fig. 1. Configuration in Fig. 5 differs from that in Fig. 1 in that a clock signal modification terminal 501 is additionally provided and that the clock modification circuit 105 is replaced with a clock signal modification circuit 502. The clock signal modification circuit 502 generates the baud rate control clock signal S502 by masking the rising edge of the original clock signal S102 when the counter value S104 has reached a clock signal modification value S502. Fig. 6 shows the operation of the clock signal generator and the communications apparatus using the clock signal generator. Assume that 10 is input as a preset counter value S101 and 4 and 9 are input as clock signal modification values S501. The clock signal modification circuit 502 masks the original clock signal S102 in the case of counter values 4 and 9 and generates the baud rate control clock signal S502. The input circuit 107 sequentially captures input data S106 every three cycles of the rising edge of the baud rate control clock signal S502, then outputs the captured data as output data S107. In this embodiment, a baud rate is realized via accuracy of the baud rate clock signal alone by generating an intermittent baud rate clock signal from a clock generator circuit, instead of using a 9/11 time clock signal. As mentioned earlier, an existing clock signal generator circuit is used to generate a baud rate clock signal thus reducing the number of man-hours required for customizing a clock signal generator circuit. Interval of intermittence of a clock signal is externally input so that the baud rate compensation range can be substantially extended, compared with the case in embodiment 1. (Embodiment 3) A clock signal generator and communications apparatus using the clock signal generator according to embodiment 3 of the invention modulates a clock signal output by an existing clock generator circuit in generating a clock signal for controlling the baud rate. Fig. 7 is a block diagram of the clock signal generator and the communications apparatus using the clock signal generator according to embodiment 3 of the invention. In Fig. 7, communications apparatus 700 comprises a frequency division value input terminal 701, a modulation indication value input terminal 702, and a modulation circuit 703. The remaining sections correspond to those having the same signs in embodiment 1. Fig. 8 is a timing chart explaining the operation of the clock signal generator and the communications apparatus using the clock signal generator shown in Fig. 7. The frequency division circuit divides the frequency of an original clock signal S102 generated in the clock signal generator circuit 102 based on the frequency division value S701. The modulation circuit 703, on obtaining the modulation indication value S702, for example information (frequency, degree of modulation)=(3, 1), outputs a baud rate clock signal whose signal cycles are incremented by one once in three times, as shown in Fig. 8. The input circuit 107 captures input data S106 via the baud rate clock signal S703. While the modulation indication value is (frequency, degree of modulation) in embodiment 3, the invention is not limited to this but either or both of the frequency and the degree of modulation may be limited to a predetermined amount and external input may not be required. The degree of modulation can be realized via the falling edge or plus or minus level of a reference clock signal, or via another clock signal. While communications apparatus in embodiments 1 through 3 assumes reception only, communications apparatus that performs transmission and reception may be implemented. The same advantage is obtained in case the clock signal frequency of the reference clock signal and that of a clock signal for controlling the baud rate are known, even when both signals are not synchronized. As mentioned earlier, a clock signal generator and communications apparatus using the clock signal generator according to the invention has a configuration where an intermittent clock signal having a desired frequency is obtained by adding a peripheral circuit to an existing clock signal generator. This eliminates the need for designing a dedicated clock signal generator for generating a frequency required per communications apparatus, thus reducing the number of man-hours required for design of communications apparatus.

Claims: A cycle stealing ratio divider to generate an output signal (S502) of predetermined frequency, comprising: a clock signal generation means (102) for generating a dock signal (S102) of consecutive docks at a predetermined frequency, a counting means (104) for outputting a counter value (S104) counting the clocks of said clock signal (S102), wherein said counter value (S104) is reset upon reaching a preset counter value (S101), a masking means (105) connected to said counting means (104) for receiving said counter value (S104) and for outputting said output signal (S502), wherein said masking means (105) is adapted to receive said dock signal (S102) from said dock signal generation means (102) and to receive a plurality of clock signal modification values (S501), wherein a dock of said clock signal (S102) is masked by said masking means (105) in case one of said clock signal modification values (S501) equals the current counter value (S104). A communication apparatus adapted to perform data input/output using a signal generated by a cycle stealing ratio divider according to claim 1.

Inventors: KAU STEFAN, KIEFNER MARCUS, NISHIO TAKATOSHI, TABIRA YOSHIHIRO, KAU, STEFAN, KIEFNER, MARCUS, NISHIO, TAKATOSHI, TABIRA, YOSHIHIRO, Kau, Stefan,
Applicants: MATSUSHITA ELECTRIC IND CO LTD, MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.
Application year: 2001
Main classification: H03L7
IPC codes: H03K5, H04L7, H03K17, G06F1