COPPER ALLOY INTERCONNECTIONS FOR INTEGRATED CIRCUITS AND METHODS OF MAKING SAME

Abstract: Formation of copper alloy interconnected lines on integrated circuits includes electroplating copper onto a seed layer wherein the concentration of the doping element or elements in the copper is controlled such that the core portion of the copper interconnect line has a low concentration of the doping element or elements, while surface portions of the copper interconnect line have higher concentrations of the doping element or elements. Copper alloys are plated at different current densities to provide doping element rich interfaces. In this way, electromigration resistance can be improved by having relatively higher doping concentrations at surface portions of an interconnect line while the desired low electrical resistivity of the interconnect is maintained by keeping the interior portions of the interconnect with a substantially lower doping concentration.

Description: COPPER ALLOY INTERCONNECTIONS FOR INTEGRATED CIRCUITS AND METHODS OF MAKING SAME Background of the Invention Field of the Invention The present invention relates generally to the field of integrated circuit manufacturing, and more specifically, to copper alloy interconnections and their formation. Background Advances in semiconductor manufacturing technology have led to the development of integrated circuits having multiple levels of interconnect. In such an integrated circuit, patterned conductive material on one interconnect level is electrically insulated from patterned conductive material on another interconnect level by films of material such as, for example, silicon dioxide. These conductive materials are typically a metal or metal alloy. Connections between the conductive material at the various interconnect levels are made by forming openings in the insulating layers and providing an electrically conductive structure such that the patterned conductive material from different interconnect levels are brought into electrical contact with each other. These electrically conductive structures are often referred to as contacts or vias. Other advances in semiconductor manufacturing technology have led to the integration of millions of transistors, each capable of switching at high speed. A consequence of incorporating so many fast switching transistors into an integrated circuit is an increase in power consumption during operation. One technique for increasing speed while reducing power consumption is to replace the traditional aluminum and aluminum alloy interconnects found on integrated circuits with a metal such as copper, which offers lower electrical resistance. Those skilled in the electrical arts will appreciate that by reducing resistance, electrical signals may propagate more quickly through the interconnect pathways on an integrated circuit. Furthermore, because the resistance of copper is significantly less than that of aluminum, the cross-sectional area of a copper interconnect line, as compared to an aluminum interconnect line, may be made smaller without incurring increased signal propagation delays based on the resistance of the interconnect. Additionally, because the capacitance between two electrical nodes is a function of the overlap area between those nodes, using a smaller copper interconnect line results in a decrease in parasitic capacitance. In this way, replacing aluminum-based interconnects with copper-based interconnects provides, depending on the dimensions chosen, reduced resistance, reduced capacitance, or both. As noted above, copper has electrical advantages, such as lower resistance per cross- sectional area, the ability to provide for reduced parasitic capacitance, and greater immunity to electromigration. For all these reasons, manufacturers of integrated circuits find it desirable to include copper in their products. While copper is electrically advantageous as compared to aluminum for interconnect lines in integrated circuits, pure copper interconnect lines may still suffer from electromigration related defects. Accordingly, there is a need for providing copper-based interconnections on integrated circuits that have improved levels of electromigration resistance. Brief Description of the Drawings Fig. 1 is a schematic cross-sectional view of an electroplated damascene structure illustrating an indirect encapsulation scheme in accordance with the present invention wherein the dopant is concentrated in the top surface of the etai film. Fig. 2 is a schematic cross-sectional view of an electroplated damascene structure illustrating an indirect encapsulation scheme in accordance with the present invention wherein the dopant has diffused sufficiently such that it remains on the top surface of the metal film. Fig. 3 is a schematic cross-sectional view of an electroplated damascene structure illustrating an indirect encapsulation scheme in accordance with the present invention showing the dopant concentration at the Cu interfaces. Fig. 4 is a schematic cross-sectional view of an electroplated damascene structure illustrating a direct encapsulation scheme in accordance with the present invention wherein the dopant is concentrated in the bottom, side and top surfaces of the metal film. Fig. 5 is a schematic cross-sectional view of an electroplated damascene structure illustrating a direct encapsulation scheme in accordance with the present invention wherein the dopant has diffused sufficiently such that it remains on the top surface of the metal film. Fig. 6 is a schematic cross-sectional view of an electroplated damascene structure illustrating a direct encapsulation scheme in accordance with the present invention showing the dopant concentration at the Cu interfaces. Fig. 7 is a schematic cross-sectional view of an interconnect structure with copper alloy elements preferentially formed on the interface portions of the interconnect structure. Fig. 8 is a schematic cross-sectional view of an interconnect structure with Cu alloy elements preferentially formed on the top surfaces of the interconnect structures. Fig. 9 is a flowchart showing the operations in a process in accordance with the present invention. Fig. 10 is a flowchart showing the operations in a process in accordance with the present invention. Detailed Description It has been demonstrated that by adding small amounts of a second metallic species to copper interconnect lines, the electromigration lifetime of those Cu interconnects is significantly improved. However, a typical consequence of introducing such a second metallic species is a reduction in conductivity compared to pure Cu. In one embodiment of the present invention, a benzenesulfonic acid based Cu-Sn plating bath enables the control of the percentage of Sn in the Cu in a real-time manner during the electrodepostion process. In this way, a second metallic species, such as Sn, can be placed in regions known to be more susceptible to electromigration (e.g., the surface of a copper interconnect line), while very little Sn is placed in the regions of interconnect lines (e.g., inside metal trenches) where reduction in conductivity is undesirable. Such an electroplating process in accordance with the present invention enables the deposition of precise and very small amounts (e.g., ppm level) of Sn (or other doping elements) in the bulk of the copper. Sn is mainly accumulated at the grain boundaries after annealing, or room temperature grain growth. Sn on the grain boundaries of copper suppresses Cu grain boundary diffusion and increases the electromigration activation energy to about 1.3 eV. In addition to Sn, other doping elements can be used including, but not limited to, In, Cd, Zn, Bi, Sb, Mn, g, Co, Cr, Ni, Pb, Re, Ru, Rh, Pd, Pt, Os, W, S, C. An illustrative plating bath in accordance with the present invention includes low concentrations of sulfuric acid to "superfill" and sulfonic acids to deposit doping elements from the copper plating solution containing ions of the doping elements. Use of sulfonic acids facilitates the incorporation of carbon into plated films. Since carbon has a low solubility in copper, it can subsequently be driven into interface regions by using an annealing operation. Furthermore, the concentration the doping element(s) in the alloy can be regulated, in accordance with the present invention, by changing the current density in real-time during the electroplating process. That is, interconnect lines can be made from copper wherein the bulk of the interior portion has a doping concentration <0.5%, while the interface, or surface portions, of the interconnect can have a doping concentration >0.5%. The current density can be changed by changing the applied voltages. For example, if the substrate is made to appear more negative, than it will more strongly attract positively charged ions to the substrate. Terminology The terms, chip, integrated circuit, monolithic device, semiconductor device or component, microelectronic device or component, and similar terms and expressions, are often used interchangeably in this field. The present invention is applicable to all the above as they are generally understood in the field. The terms metal line, trace, wire, conductor, signal path and signaling medium are all related. The related terms listed above, are generally interchangeable, and appear in order from specific to general. In this field, metal lines are sometimes referred to as traces, wires, lines, interconnects or simply metal. The terms contact and via, both refer to structures for electrical connection of conductors from different interconnect levels. These terms are sometimes used in the art to describe both an opening in an insulator in which the structure will be completed, and the completed structure itself. For purposes of this disclosure contact and via refer to the completed structure. NHE refers to a normalized hydrogen electrode. The acronym ppm stands for parts per million. A substrate may also be referred to as a wafer. Wafers, may be made of semiconducting, non-semiconducting, or combinations of semiconducting and non-semiconducting materials. Silicon wafers may have thin films of various materials formed upon them. Other materials such as GaAs, silicon-on-sapphire, or silicon on insulator (SOI) may be used to form wafers. The term vertical, as used herein, means substantially perpendicular to the surface of a substrate. Embodiments of the present invention provide a bath to deposit Cu alloys onto a Cu or Cu alloy seed layer. Electroplated Cu alloys include, but are not limited to, CuSn, CuC, CuS, Culn, CuCd, CuCr, CuZn, CuBi, CuSb, CuPb, CuMn, CuMg, CuCo, CuNi, CuRe, CuRu, CuW, CuPt, CuPd, CuRh, CuOs. The Cu alloy seed layer includes, but is not limited to, CuSn, CuMg, CuAI, CuTi, CuTa, CuW, Culn, CuSb, CuZn, CuPd, CuMn, CuCr, CuNi, CuRu, CuRh, CuAu, CuBi, CuCd, CuPt, Culr, CuOs, CuRe, CuMo, CuZr, CuW. For purposes of the present invention, the seed layer, whether a Cu or Cu alloy, can be deposited by physical vapor deposition (PVD), chemical vapor deposition (CVD), atomic layer deposition (ALD), or any other suitable manner of forming the seed layer. Cu alloy seed layers can be used with or without a barrier layer. Copper diffusion barrier layers include, but are not limited to, Ta, TaN, TaSiN, W, WN, WSiN, Ti, TiN, TiSiN, Co. A barrier layer can be deposited by PVD, CVD or ALD. Embodiments of the present invention include an electroplating deposition process. An illustrative embodiment of an electroplating bath in accordance with the present invention may be formed by combining: Cu ions in the concentration range of 5-100 g/l; sulfuric acid in the concentration range from 1 to 50 g/l (<10 wt% in the plating bath); Cl ions in the concentration range from 10 to 100 mg/l; one or more sulfonic acids; and Sn(ll) ions. One or more doping elements can be co-deposited with Cu including Sn, In, Cd, Cr, Zn, Bi, Sb, Pb, Mn, Mg, Co, Ni, Re, W, Ru, Pt, Rh, Pd, C, S, Os. The selected doping element(s) are included in the electroplating bath. Additionally, organic additives, including but not limited to, an anti- suppressor such as mercapto alkylsulfonates, a suppressor such as polyethers (e.g., polyethylene glycoi (PEG), polypropylene glycol (PPG)), and a leveler such as polyimines, or polyamids, may be used in the electroplating bath. Complexing agents such as, but not limited to, citrate, tartrate, ethylenediaminetetra acetic acid (EDTA), and acetate may also be included in the electroplating bath to provide a more negative deposition potential for copper which facilitates co-deposition of elements having a large difference in electrode potential with Cu (NHE +0.34 V) for example Cr, Mg, Mn (NHE -1.18 V), Co (NHE -0.8 V), Zn (NHE - 0.76 V), In (NHE - 0.35 V), Ni (NHE -0.25 V). Complexing agents are also used to provide a more negative electrode potential for noble metals such as Pd (NHE +0.99 V), Rh (NHE +0.8 V), and Pt (NHE + 0.73 V). In the illustrative electroplating bath described above, the Cu ions may be supplied from starting materials including, but not limited to, copper sulfate, copper nitrate, copper chloride, copper methanesulfonate, copper ethanesulfonate, copper propanesulfonate, copper benzenesulfonate, and copper triflate. The Cl ions may be supplied from a starting material such as, but not limited to, HCI. Sulfonic acids such as, but not limited to, methanesulfonic acid (MSA), ethanesulfonic acid (ESA), propanesulfonic acid (PSA), benzenesulfonic acid (BSA), and trifluoromethane sulfonic acid (triflic acid - TFA) in the concentration range from 0.005 mole/1 to 2.5 mole/1 may be used. Sn(ll) ions may be supplied from starting materials including, but not limited to, tin(ll) sulfate, tin(ll) acetate, tin(ll) bromide, tin(ll) chloride, tin(ll) fluoride, tin(ll) iodide, and tin(ll) oxide in the concentration range from 0.1 to 200 g/l. Fabricating alloy structures In illustrative embodiments of the present invention, current densities are varied during the electroplating process because varying the current densities in an electroplating bath in accordance with the present invention controls the concentration of doping elements being deposited along with the copper. In this way, Cu alloys rich in one or more doping elements can be formed at specific regions within the interconnect structure. In particular, copper- based interconnects having alloys at the outer, or interface, portions of the interconnects are formed. The current densities referred to above may be high (e.g., in a range from 30 to 100 mA/cm 2 ) at the initial deposition phase and at the terminal deposition phase to allow deposition of Cu with higher concentrations of doping elements (e.g., >0.5 wt%). Conversely, low deposition current densities (e.g., from 0.5 to 30 mA/cm 2 ) allow deposition of Cu with low concentrations of doping elements (e.g., <0.5 wt%). An anneal operation may be performed shortly, if not immediately, after deposition in the same plating tool to form and stabilize the Cu alloy microstructure. This anneal operation may also drive doping elements to the interface and grain boundaries. The anneal temperature can vary from a low anneal temperature of less than 250°C during the first operation to increase Cu grain size and drive impurities to the interface, and a high anneal temperature (>250 C C) during a second operation to form a Cu alloy preferentially at the interface. In another embodiment of present invention, annealing is performed after chemical mechanical polishing (CMP) so that doping elements can diffuse to the interfaces and form encapsulated structures. This post-CMP anneal operation can be done with different temperatures (low and high) in an integrated anneal chamber in the plating tool, in a stand alone furnace or in Rapid Thermal Processing (RTP) equipment. The post-CMP anneal operation can also be performed during or before an etch stop/I LD deposition. Cu interconnect with Cu alloys on top interface. One interconnect structure in accordance with an embodiment of the present invention is formed by co-depositing one or more doping elements with Cu preferentially during the terminal phase of the deposition operation with high current densities being used, while the bulk of the deposition is done with relatively lower current densities to allow the deposition of Cu with a low concentration of one or more doping elements (<0.5%). After the deposition by electroplating is completed, an anneal operation is performed to allow the one or more doping elements to diffuse toward the top of the Cu filled trenches while a very low concentration of Sn (i.e., <100 ppm) remains within the bulk copper at the grain boundaries. Figs. 1-3 illustrate this structure and process in more detail. Fig. 1 shows a cross- section of a portion of a partially processed wafer. More particularly, Fig. 1 shows an interlayer dielectric (ILD) 102 that has been patterned to form trenches 101 and vias 103 therein. The partially processed wafer is placed in an electroplating bath that contains Cu ions, as well as ions of one or more doping elements. A layer of copper 104 is then electroplated over ILD 102 such that trenches 101 and vias 103 are filled, and the top surface of ILD 102 is also covered with copper 104. While still in the electroplating bath that was used to plate copper 104, the current density is increased so that one or more doping elements present in the electroplating bath are co-deposited with copper to form copper alloy layer 106. The current densities are selected so that the amount of doping atoms in copper layer 104 is less than 0.5 wt.% and the amount of doping atoms in layer copper alloy layer 106 is greater than 0.5 wt.%. Referring to Fig. 2, the structure of Fig. 1 is shown after an annealing operation is performed. In this embodiment, an anneal operation is done at a temperature less than 450 °C for a period of time between 0.5 and 180 minutes in an N 2 , Ar, or N 2 +H 2 (i.e., forming gas) environment. In an alternative embodiment, an anneal operation is performed in two steps: first an anneal at a temperature between 100 °C and 250° C for a period of time between 0.5 and 180 minutes in an N 2 , Ar, or N 2 +H 2 (i.e., forming gas) environment; and a second anneal at a temperature between 250 °C and 450 °C for a period of time between 0.5 and 180 minutes in an N 2 , Ar, or N 2 +H 2 (i.e., forming gas) environment. The annealing operation drives the doping element(s) from copper alloy layer 106 through a top portion of copper layer 104. Some of these doping atoms are also driven toward interface surfaces of copper layer 104 to form copper alloy layer 108 as shown in Fig. 2. Fig. 3 shows the structure of Fig. 2 after a chemical mechanical polishing (CMP) operation is performed. This CMP operation removes the metal overlying the top surface of ILD 102 thereby creating individual interconnect lines that have a copper portion 104 and a copper alloy portion 108 as shown in Fig. 3. The copper alloy portion that resides at the top surface of the interconnect structure has a shape that is generally thin near the vertical sidewalls of the trench and gets thicker towards the middle of the interconnect structure. Cu interconnect structure encapsulated with Cu alloys. In one embodiment of the present invention a copper-based interconnect structure is formed by co-depositing Cu with one or more doping elements followed by an in-situ anneal of the plated Cu-dopant material to drive one or more low solubility doping elements to the interface portions of the interconnect structure. Such an interconnect structure can be also formed by the co-plating of copper with a higher concentration of doping elements by using higher current density (>30 mA/cm 2 ) at the initial deposition step followed by plating Cu at low current densities (<30 mA/cm 2 ) to achieve a relatively low concentration of doping elements in the bulk interior portions of the interconnect structure followed by plating Cu at high current densities (>30 mA/cm 2 ) to achieve a relatively high concentration of doping elements in the top portion, i.e., later deposited portion, of the interconnect structure. Subsequent to completion of the electroplating operations, an anneal operation is performed to allow diffusion of doping elements to the top of the Cu filled trenches. Figs. 4-6 illustrate this structure and process in more detail. Fig. 4 shows a cross- section of a portion of a partially processed wafer. More particularly, Fig. 4 shows an interlayer dielectric (ILD) 402 that has been patterned to form trenches 401 and vias 403 therein. The partially processed wafer is placed in an electroplating bath that contains Cu ions and ions of one or more doping elements. A layer of copper alloy 404 is then electroplated over ILD 402 such that surfaces of trenches 401 and vias 403 are covered, and the top surface of ILD 402 is also covered with copper alloy 404. In the illustrated embodiment, Sn is co-deposited with copper to form copper alloy 404, and this layer is deposited to a thickness of approximately 100 to 500 angstroms. Copper alloy 404 is formed by the co-deposition of one or more doping elements along with copper from the electroplating bath. While still in the electroplating bath that was used to plate copper alloy 404, the current density is decreased so that doping elements present in the electroplating bath are not co-deposited with copper to form copper layer 406. Copper layer 406, as shown in Fig, 4, fills the portions of trenches 401 and vias 403 not occupied by copper alloy layer 404. The current densities are selected so that the amount of doping atoms in copper alloy layer 404 is greater than 0.5 wt.% and the amount of doping atoms in layer copper layer 406 is less than 0.5 wt.%. After layer 406 is formed, the current density is increased to again co-deposit atoms of one or more doping elements with copper from the electroplating bath thereby forming copper alloy layer 408. Referring to Fig. 5, the structure of Fig. 4 is shown after an annealing operation is performed. In this embodiment, an anneal operation is done at a temperature less than 450 °C for a period of time between 0.5 and 180 minutes in an N 2 , Ar, or N 2 +H 2 (i.e., forming gas) environment. In an alternative embodiment, an anneal operation is performed in two steps: first an anneal at a temperature between 100 °C and 250° C for a period of time between 0.5 and 180 minutes in an N 2 , Ar, or N 2 +H 2 (i.e., forming gas) environment; and a second anneal at a temperature between 250 °C and 450 °C for a period of time between 0.5 and 180 minutes in an N 2 , Ar, or N 2 +H 2 (i.e., forming gas) environment. The annealing operation drives the doping element(s) from copper alloy layers 404, 408 through a portions of copper layer 406 as indicated in Fig. 4. By driving these doping atoms toward interface surfaces of copper layer 406 a self-encapsulated copper region is formed. That is, copper 406 is surrounded by post-anneal copper alloy 410. Fig. 6 shows the structure of Fig. 5 after a chemical mechanical polishing operation is performed. This CMP operation removes the metal overlying the top surface of ILD 402 thereby creating individual interconnect lines that have a copper portion 406 and a copper alloy portion 410 as shown in Fig. 6. The copper alloy portion that resides at the top surface of the interconnect structure has a shape that is generally thin near the vertical sidewalls of the trench and gets thicker towards the middle of the interconnect structure. In an alternative embodiment of present invention, the anneal operation is performed after excess metal is removed by CMP. Such a post-CMP anneal operation can be done with different temperatures (low and high) in an integrated anneal chamber in the plater tool, in a stand-alone furnace, or in a rapid thermal processing (RTP) tool. Further, in accordance with the present invention, the anneal operation can be performed during or before the deposition of an etch stop or ILD layer. Fig. 7 shows a cross-section of a portion of a wafer having copper interconnect lines and vias surrounded by an ILD layer. More particularly, the copper interconnect lines and vias have a self-encapsulating layer surrounding their core regions. These self- encapsulating layers are formed of copper alloys. Copper alloys may be used, not only as described above for the improvement of electromigration properties, but also to eliminate the need for separately formed copper diffusion barriers as are found in conventional copper interconnect lines. Fig. 8 is similar to Fig. 7, but illustrates an embodiment of the present invention in which the copper alloy layer is formed on the top portion of the copper interconnect lines. Fig. 9 illustrates a method in accordance with the present invention. As shown at block 902, copper is electroplated onto a substrate from an electroplating bath containing sulfuric acid, a sulfonic acid, copper ions and doping ions, at a first current density. Subsequently, as shown at block 904 the current density is changed to a second value, and a copper alloy is electroplated onto the previously deposited copper from the same electroplating bath. Fig. 10 illustrates an embodiment of the present invention in which encapsulated copper interconnect structures are formed. By encapsulated, it is meant that a core or interior portion of the copper interconnect structure is surrounded by a region of copper alloy. As shown in Fig. 10 at block 1002, a copper alloy is electroplated onto a substrate from an electroplating bath containing sulfuric acid, a sulfonic acid, copper ions and doping ions, at a first current density. This current density is chosen such that a doping element present in the electroplating bath is co-deposited along with copper. This copper alloy layer is typically formed over a previously formed seed layer. At block 1004, copper is electroplated onto the copper alloy from the same electroplating bath containing sulfuric acid, a sulfonic acid, copper ions and doping ions, at a second, lower, current density. At block 1006, another layer of copper alloy is electroplated from the same bath, onto the copper layer. This copper alloy deposition is performed at a third current density which is higher than the second current density. The first and third current densities may be, but are not required to be equal. As shown at block 1008, the substrate is annealed so that the doping atoms in the copper alloy regions are driven into portions of the copper layer including the interface portions, thereby forming a self-encapsulating region around the core portion of the copper interconnect structure. Conclusion Embodiments of the present invention provide copper-based interconnect structures and methods and chemistries for their formation. More particularly, damascene copper-based interconnects are formed through the use of a plating bath in which the mixture of sulfuric acid at low concentration (<50 g/l) with sulfonic acids allows "superfill" and co-plating of doping elements. The concentration of doping elements can be regulated by changing the current density during electroplating to create higher concentrations of doping elements at the interfaces of the interconnect structures in order to improve electromigration resistance without substantially sacrificing the electrical resistivity of undoped Cu lines. By annealing after electroplating, without any significant intervening delay, for example, in a plating tool with an integrated annealing chamber, allows doping elements to diffuse to the interface thereby forming an alloy at the interface. Annealing temperatures can vary from low (e.g., <250°C) to high (>250°C) to form alloys preferentially at the interface. Forming copper- based interconnects in accordance with the present invention produces interconnects that are encapsulated with doping element alloys. Forming Cu lines encapsulated with Re, Ru or W produces a built-in barrier layer. In other words, by forming copper lines with Re, Ru, or W, a doping element alloy at the outer, i.e., interface, portions of the interconnect lines is formed which act to reduce or prevent the diffusion of copper atoms into the surrounding dielectric layers. Cu interconnect structures in accordance with the present invention can also be formed with the top interface or bottom interface containing the Cu alloys. With respect to CuSn plating, combinations such as: (a)having a substantially uniformly average, very low Sn content through the electroplated metal films with Sn mainly on the grain boundaries; (b) having a higher CuSn concentration at the bottom of lines and vias; (c) having a higher CuSn concentration at the top of lines and vias; and (d) having a higher CuSn concentration at the top and bottom of lines and vias. It should also be noted that, with respect to annealing, this can be done after Cu plating, after CMP of the deposited copper layer, or after both Cu plating and CMP. An advantage of some embodiments of the present invention is that adhesion of silicon nitride to copper interconnect lines is improved. An advantage of some embodiments of the present invention is that a silicon nitride etch stop layer is rendered unnecessary. An advantage of some embodiments of the present invention is that the wear resistance of copper-based interconnects is improved. An advantage of some embodiments of the present invention is that hillock formation during an anneal operation is reduced. An advantage of some embodiments of the present invention is that the adhesion between the copper alloys and the barrier layer is improved relative to that of pure copper, because the doping constituents of the copper alloy can form an intermetallic compound with the barrier layer (e.g., Sn alloy of copper and Ta-based barrier layer). An advantage of some embodiments of the present invention is that encapsulation of copper interconnect lines with copper alloys provides a mechanical framework to support the copper lines. This is particularly useful when Si0 2 based interlayer dielectric materials are replaced with the less rigid low-k and ultra low-k dielectric materials. Other modifications from the specifically described apparatus, cleaning solutions, and processes will be apparent to those skilled in the art and having the benefit of this disclosure. Accordingly, it is intended that all such modifications and alterations be considered as within the spirit and scope of the invention as defined by the subjoined Claims.

Claims: What is claimed is: 1. An electroplating bath comprising a mixture formed from: sulfuric acid, a sulfonic acid, a copper containing compound, a chlorine containing compound, and at least one doping element. 2. The electroplating bath of Claim 1 , wherein the copper containing compound is selected from the group consisting of copper sulfate, copper nitrate, copper chloride, copper methanesulfonate, copper ethanesulfonate, copper propanesulfonate, copper benzenesulfonate, and copper triflate. 3. The electroplating bath of Claim 2, further comprising at least one organic additive. 4. The electroplating bath of Claim 3, wherein the at least one organic additive is selected from the group consisting of mercapto alkylsulfonates, polyethers, polyimines, and polyamids. 5. The electroplating bath of Claim 4, further comprising at least one complexing agent. 6. The electroplating bath of Claim 5, wherein the at least one complexing agent is selected from the group consisting of acetates, citrates, tartrates, and EDTA. 7. The electroplating bath of Claim 2, wherein the sulfonic acid is selected from the group consisting of methanesulfonic acid, ethanesulfonic acid, propanesulfonic acid, benzenesulfonic acid, and trifluormethanesulfonic acid; and the concentration range of the sulfonic acid is between 0.005 moles/liter and 2.5 moles/liter. 8. The electroplating bath of Claim 1 , wherein the at least one doping element is selected from the group consisting of Sn, In, Cd, Cr, Zn, Bi, Sb, Pb, Mn, Mg, Co, Ni, Re, W, Ru, Pt, Rh, Pd, C, S, Os. 9. The electroplating bath of Claim 8, wherein the sulfuric acid has a concentration in the range from 1 to 50 g/l; and wherein the concentration of Cl ions from the chlorine containing compound is in the concentration range from 10 to 100 mg/l. 10. The electroplating bath of Claim 3, wherein the sulfuric acid is less than 10 wt% of the plating bath. 11. The electroplating bath of Claim 6, wherein the at least one doping element is Sn; and a source material for Sn in the electroplating bath is selected from the group consisting of tin(ll) sulfate, tin(ll) acetate, tin(ll) bromide, tin(ll) chloride, tin(ll) fluoride, tin(ll) iodide, and tin(ll) oxide. 12. The electroplating bath of Claim 6, wherein the chlorine containing compound is HCI. 13. A method of forming a copper-based interconnect line on an integrated circuit, comprising: providing a substrate having a dielectric layer thereon, the dielectric layer having trenches therein, and the dielectric layer and trenches having a seed layer disposed thereover; placing the substrate into an electroplating bath mixture formed from sulfuric acid, a sulfonic acid, a copper containing compound, a chlorine containing compound, and at least one doping element; forming a layer of copper over the seed layer, the copper layer having a non-uniform distribution of doping elements therein; annealing the substrate; and removing a top portion of the copper layer by chemical mechanical polishing. 14. The method of Claim 13, wherein forming the layer of copper comprises: applying a first voltage to the wafer to force a first current density; and applying a second voltage to the wafer to force a second current density. 15. The method of Claim 14, wherein the first current density is less than 30 mA/cm 2 . 16. The method of Claim 14, wherein the second current density is greater than 30 mA/cm 2 . 17. The method of Claim 14, wherein the doping element is selected from the group consisting of Sn, In, Cd, Cr, Zn, Bi, Sb, Pb, Mn, Mg, Co, Ni, Re, W, Ru, Pt, Rh, Pd, C, S, Os. 18. The method of Claim 14, wherein the doping element is Sn, the first current density is less than 30 mA/cm 2 and second current density is greater than 30 mA/cm 2 . 19. The method of Claim 13, wherein forming the layer of copper comprises: applying a first voltage to the wafer to force a first current density; applying a second voltage to the wafer to force a second current density; and applying a third voltage to the wafer to force a third current density. 20. The method of Claim 19, wherein the second current density is less than the first current density, and the second current density is less the third current density. 21. An interconnect structure in an integrated circuit, comprising: an interlayer dielectric layer having at least one trench therein, the trench having spaced apart vertical sidewalls; a metallic conductor disposed in the at least one trench; wherein the metallic conductor has an interior portion comprising copper with less than 0.5 wt.% doping elements therein, the metallic conductor has a top portion, including a top surface thereof, comprising copper with greater than 0.5 wt.% doping elements therein, and the top portion has a thickness that varies according to a distance from the trench vertical sidewalls. 22. The interconnect structure of Claim 21 , wherein the top portion is a CuSn alloy, and the top portion is thickest midway between the vertical sidewalls of the at least one trench.

Inventors: DUBIN VALERY M, THOMAS CHRISTOPHER D, DUBIN, VALERY, M., THOMAS, CHRISTOPHER, D.
Applicants: DUBIN VALERY M, INTEL CORP, THOMAS CHRISTOPHER D, DUBIN, VALERY, M., INTEL CORPORATION, THOMAS, CHRISTOPHER, D.
Application year: 2001
Main classification: H01L21
IPC codes: H01L21, H01L23