METHOD OF PERFORMING PLASMA WARM-UP ON SEMICONDUCTOR WAFERS

Abstract: A method for stabilizing the temperature of a semiconductor wafer. In one embodiment, the present invention introduces a semiconductor wafer into an processing environment. Prior to subjecting said semiconductor wafer to a conventional semiconductor process, the present invention performs a plasma warm-up step. The aforementioned plasma warm-up step of the present invention is comprised of the following steps. First, the present invention subjects the semiconductor wafer to an inert gas plasma within the processing environment. Next, the present invention continues to subject the semiconductor wafer to the inert gas plasma until the semiconductor wafer achieves a desired temperature.

Description: METHOD OF PERFORMING PLASMA WARM-UP ON SEMICONDUCTOR WAFERS TECHNICAL FIELD The present disclosure relates to the field of semiconductor manufacturing. More specifically, the present disclosure relates to semiconductor wafer temperature, and to the use of inert gas plasma for stabilizing wafer temperature prior to plasma processing. In particular, a method for performing plasma warm-up on semiconductor wafers is disclosed. BACKGROUND ART Wafer temperature is one of the most important variables for a plasma etch or deposition process. It can affect the rate at which the process progress and can also affect other parameters such as etch selectivity, profile control, and film quality. But the plasma itself heats the wafer surface above the setpoint of the temperature-controlled chuck on which the wafer sits. Even a state-of-the-art electrostatic chuck with He backside cooling cannot prevent this heating. Thus, any wafer that is conventionally plasma processed experiences temperatures ranging from the initial chuck temperature to the final equilibrium temperature. When the plasma is first ignited, the suddenly increasing wafer temperature makes it difficult to control process performance. For example, shallow sihcon trench etch is typically performed by assuming a constant etch rate and then etching for a set amount of time to reach a When the plasma is first ignited, the suddenly increasing wafer temperature makes it difficult to control process performance. For example, shallow silicon trench etch is typically performed by assuming a constant etch rate and then etching for a set amount of time to reach a desired depth. However, the assumption of a fixed etch rate is not correct since the wafer temperature itself is not fixed throughout the etch. As the wafer is initially heated by the plasma, the etch rate can vary, resulting in an off-target trench depth. Another example where wafer temperature control is critical is the etching of materials (such as Cu or Pt) where the etch products have low volatility. To evolve low volatility products requires the wafer temperature to be relatively high. If etching begins at a lower than desired temperature, for a period of time there can be blocked etch and surface roughening that might affect the final result even after the wafer temperature stabilizes. Temperature control during plasma-assisted film deposition is also important. Film deposited during the initial stages of the deposition, when the wafer is cooler than its equilibrium temperature, will not have the same properties as the remainder of the film. Thus, a need exists for a method to reduce wafer temperature variability during semiconductor process steps. A further need exists for a method which reduces the difficulty in controlling process conditions due to initial heating of the semiconductor wafer. DISCLOSURE OF THE INVENTION The present invention provides a method to reduce wafer temperature variability during semiconductor process steps. The present invention further provides a method which reduces the difficulty in controlling process conditions due to initial heating of the semiconductor wafer. Specifically, in one embodiment, the present invention introduces a semiconductor wafer into an processing environment. Prior to subjecting the semiconductor wafer to a conventional semiconductor process, the present invention performs a plasma warm-up step. The aforementioned plasma warm-up step of the present invention is comprised of the following steps. First, the present invention subjects the semiconductor wafer to an inert gas plasma within the processing environment. Next, the present invention continues to subject the semiconductor wafer to the inert gas plasma until the semiconductor wafer achieves a desired temperature. In one embodiment, the present invention includes the steps of the above-described embodiment, and further recites that the inert gas is selected from the group consisting of He, Ne, Ar, Kr, and Xe. In yet another embodiment, the present invention includes the steps of the first of the above-described embodiments, and further recites that the semiconductor wafer is subjected to the inert gas plasma until the semiconductor wafer approaches the maximum temperature to which the semiconductor wafer would be heated during a subsequent conventional semiconductor process step. These and other objects and advantages of the present invention will no doubt become obvious to those of ordinary skill in the art after having read the following detailed description of the preferred embodiments which are illustrated in the various drawing figures. BRIEF DESCRIPTION OF THE DRAWINGS The accompanying drawings, which are incorporated in and form a part of this specification, illustrate embodiments of the invention and, together with the description, serve to explain the principles of the invention: FIGURE 1 is a flow chart of steps performed in accordance with one embodiment of the present claimed invention. FIGURE 2 is a schematic illustration of semiconductor wafer in an processing environment adapted to perform a plasma warm-up step in accordance with one embodiment of the present claimed invention. FIGURE 3 is a graph of semiconductor wafer temperature vs. time (includ ng deviation from stable temperature) during a plasma warm-up step in accordance with one embodiment of the present claimed invention. The drawings referred to in this description should be understood as ot being drawn to scale except if specifically noted. BEST MODE FOR CARRYING OUT THE INVENTION Reference will now be made in detail to the preferred embodiments of the invention, examples of which are illustrated in the accompanying drawings. While the invention will be described in conjunction with the preferred embodiments, it will be understood that they are not intended to limit the invention to these embodiments. On the contrary, the invention is intended to cover alternatives, modifications and equivalents, which may be included within the spirit and scope of the invention as defined by the appended claims. Furthermore, in the following detailed description of the present invention, numerous specific details are set forth in order to provide a thorough understanding of the present invention. However, it will be obvious to one of ordinary skill in the art that the present invention may be practiced without these specific details. In other instances, well known methods, procedures, components, and circuits have not been described in detail as not to unnecessarily obscure aspects of the present invention. With reference now to Figure 1, a flow chart of steps performed in accordance with one embodiment of the present invention is shown. The steps of Figure 1 will be described in conjunction with the schematic illustration of Figure 2. As mentioned above, semiconductor wafer temperature is one of the hidden parameters in plasma processing that significantly impacts process results and can cause variation between presumably identical process tools. Understanding and controlling the actual wafer temperature, as opposed to simply controlling the temperature setpoint of the wafer chuck, is critical for preventing resist burning; controlling vertical and lateral etch rates of temperature-sensitive films, such as AlCu or organic polymers; and minimizing the effect of charging damage on gate oxide. The present invention, as will be described in detail below, reduces the variability associated with uncontrolled semiconductor wafer heating. That is, as will be set forth in detail below, the present embodiment provides a method for stabilizing the temperature of a semiconductor wafer. Such a stabilization can be used, for example, to reduce variability in an etching process, or to selectively pre-heat a semiconductor wafer to a desired temperature. Additionally, although the following discussion will repeatedly refer to a "semiconductor wafer", for purposes of the present application, the term semiconductor wafer will refer to a semiconductor substrate alone, and also to a semiconductor substrate having additional materials disposed thereon. Such materials include, but are not limited to, oxides, dielectrics, passivation materials, metals, and the like. Referring now to step 102 of Figure 1, the present embodiment, introduces a semiconductor wafer 202 into an processing environment 200, both of Figure 2. It will be understood that numerous well-known features of an processing environment are not shown in Figure 2 for purposes of clarity. Referring next to step 104, in the present embodiment, prior to subjecting semiconductor wafer 202 to a conventional semiconductor process (e.g. an etching process), the present embodiment performs a plasma warm-up step. More specifically, in the present embodiment, the plasma warm-up step comprises subjecting semiconductor wafer 202 to an inert gas plasma 204 generated within processing environment 200. In one embodiment of the present invention, the inert gas used to create the inert gas plasma is selected from the group consisting of He, Ne, Ar, Kr, and Xe. Furthermore, for purposes of the present application, the term "inert gas plasma" is intended to refer to a plasma which does not deleteriously affect, to a significant extent, semiconductor wafer 200 (or various materials disposed thereon) during the plasma warm-up step. That is, the present invention is not limited to use solely with the "inert" elements (i.e. the noble elements) of the periodic table. Referring still to step 104, during the plasma warm-up step, the present embodiment continues to subject semiconductor wafer 202 to inert gas plasma 202 until a desired condition is met. In one embodiment, the plasma warm-up step is continued until semiconductor wafer 202 approaches the maximum temperature to which semiconductor wafer 202 would be heated during a subsequent conventional semiconductor process. For example, when semiconductor wafer 202 is subsequently going to be subjected to an etching process which will heat semiconductor wafer to a temperature of 70 degrees Celsius, the present embodiment continues the aforementioned plasma warm-up step until semiconductor wafer 202 reaches 70 degrees Celsius. With reference still to step 104, in still another embodiment, rather than basing the length of the plasma warm-up step solely on the measured temperature semiconductor wafer, the plasma warm-up step is continued for a duration of approximately 10-30 seconds. Still referring to step 104, the plasma warm-up step of the present invention is performed under flow rates and parameters which tire easily obtained in a standard processing environment. For example, in one embodiment, the aforementioned plasma warm-up step is performed in an processing environment wherein the inert gas introduced at a flow rate of approximately 50-5000 standard cubic centimeters per minute (SCCM); wherein the processing environment is at a pressure in the range of 50 mTorr to 5 Torr; wherein the processing environment is at a power in the range of 100 Watts to 3000 Watts; wherein the plasma warm-up step is performed for a duration in the range of 5 seconds to 150 seconds; and wherein the low electrode setpoint is at a temperature in the range of -60 degrees Celsius to 600 degrees Celsius. Although such parameters are recited in the present embodiment, the present invention is well suited to varying the parameters, conditions, and components of the plasma warm- up step processing environment. With reference next to Figure 3, a graph 300 of semiconductor wafer temperature vs. time (including deviation from stable temperature) during the plasma warm-up step 104 of Figure 1 is shown. As shown in graph 300 of Figure 3, using the plasma warm-up step of the present invention, the temperature of semiconductor wafer 202 of the present embodiment is almost completely stabilized after approximately 20 seconds. Hence, by performing the plasma warm-up step of the present invention, the present invention accurately controls one of the hidden parameters in plasma processing that significantly impacts process results and causes variation between presumably identical process tools. Also, by stabilizing the temperature of semiconductor wafer 200, the present invention minimizes variation, allows for a wider process window for other parameters, and improves process control. Thus, the present invention provides a method to reduce wafer temperature variability during semiconductor process steps. The present invention further provides a method which reduces the difficulty in controlling process conditions due to initial heating of the semiconductor wafer. The foregoing descriptions of specific embodiments of the present invention have been presented for purposes of illustration and description. They are not intended to be exhaustive or to limit the invention to the precise forms disclosed, and obviously many modifications and variations are possible in light of the above teaching. The embodiments were chosen and described in order to best explain the principles of the invention and its practical application, to thereby enable others skilled in the art to best utilize the invention and various embodiments with various modifications as are suited to the particular use contemplated. It is intended that the scope of the invention be defined by the Claims appended hereto and their equivalents.

Claims: CLAIMS: 1. A method comprising the steps of: a) introducing a semiconductor wafer into a processing environment; and b) prior to subjecting said semiconductor wafer to a conventional semiconductor process, performing a plasma warm-up step, said plasma warm-up step comprising the steps of: bl) subjecting said semiconductor wafer to an inert gas plasma within said processing environment, and b2) continuing to subject said semiconductor wafer to said inert gas plasma until said semiconductor wafer achieves a desired temperature. 2. The method as recited in Claim 1, wherein said method is for stabilizing the temperature of a semiconductor wafer. 3. The method as recited in Claim 1, wherein said method is for reducing variability in an etching process. 4. The method as recited in Claim 1, wherein said method is for selectively pre-heating a semiconductor wafer to a desired temperature. 5. The method as recited in any one of Claims 1-4 wherein said semiconductor wafer has other material disposed thereover. 6. The method as recited in any one of Claims 1-5 wherein said conventional semiconductor process is an etching process. 7. The method as recited in any one of Claims 1-6 wherein said inert gas is selected from the group consisting of He, Ne, Ar, Kr, and Xe. 8. The method as recited in any one of Claims 1-6 wherein said inert gas is comprised of a gas which does not deleteriously affect, to a significant extent, said semiconductor wafer during said step b). 9. The method as recited in any one of Claims 1-8 wherein step b2) is continued until said semiconductor wafer approaches the maximum temperature to which said semiconductor wafer would be heated during subsequent said conventional semiconductor process. 10. The method as recited in any one of Claims 1-8 wherein step b2) is continued until said semiconductor wafer reaches a temperature of approximately 70 degrees Celsius. 11. The method for stabilizing the temperature of a semiconductor wafer as recited in any one of Claims 1-8 wherein step b2) is continued for approximately 10- 30 seconds.

Inventors: GABRIEL CALVIN TODD, YEH EDWARD K, GABRIEL, CALVIN, TODD, YEH, EDWARD, K.
Applicants: KONINKL PHILIPS ELECTRONICS NV, PHILIPS SEMICONDUCTORS INC, KONINKLIJKE PHILIPS ELECTRONICS N.V., PHILIPS SEMICONDUCTORS, INC.
Application year: 2001
Main classification: H01L21
IPC codes: C23C16, H01L21