SEMICONDUCTOR MEMORY HAVING SEGMENTED ROW REPAIR

Abstract: A memory device having a segmented row repair architecture that provides the benefits of single bit repair, thereby efficiently utilizing redundant rows of the memory device, is disclosed. The rows of a memory device are segmented into four segments and segmented row repair is provided by selectively disabling a wordline driver for only one segment of the primary row in which a defective memory cell is located and enabling a redundant wordline driver with a redundant term signal provided by the redundancy matching circuit, thereby substituting a redundant row segment for only a specific segment of the entire row length. By selectively disabling only the wordline driver associated with the defective memory cell and dividing the primary and redundant rows into four segments, localized or single bit repair can be performed, thereby efficiently utilizing the redundant rows of the memory device.

Description: SEMICONDUCTOR MEMORY HAVING SEGMENTED ROW REPAIR BACKGROUND OF THE INVENTION 1. Field ofthe Invention The present invention relates generally to integrated circuit memory devices, and more particularly to a memory device having segmented row repair. 2. Description ofthe Related Art Memory tests on semiconductor devices, such as random access memory (RAM) integrated circuits, e.g., DRAMs, SRAMs and the like, are typically performed by the manufacturer during production and fabrication to locate defects and failures in such devices that can occur during the manufacturing process ofthe semiconductor devices. Defects may be caused by a number of factors, including particle defects such as broken or shorted out columns and rows, particle contamination, or bit defects. The testing is typically performed by a memory controller or processor (or a designated processor in a multi-processor machine) which runs a testing program, often before a die containing the semiconductor device is packaged into a chip. Random access memories are usually subjected to data retention tests and/or data march tests. In data retention tests, every cell of the memory is written and checked after a pre-specified interval to determine if leakage current has occurred that has affected the stored logic state. In a march test, a sequence of read and/or write operations is applied to each cell, either in increasing or decreasing address order. Such testing ensures that hidden defects will not be first discovered during operational use, thereby rendering end-products unreliable. Many semiconductor devices, particularly memory devices, include redundant circuitry on the semiconductor device that can be employed to replace malfunctioning circuits found during testing. During the initial testing of a memory device, defective elements are repaired by replacing them with non-defective elements referred to as redundant elements. By enabling such redundant circuitry, the device need not be discarded even if it fails a particular test. Fig. 1 illustrates in block diagram form a 256Mbit DRAM 20. DRAM 20 includes eight memory banks or arrays 22a-22h, labeled BANK<0> to BANK<7>. Each memory bank 22a-h is a 32Mbit array map 24 as illustrated in Fig. 2. The architecture of array map 24 illustrated in Fig. 2 divides array map 24 into a plurality of 256K blocks 30 (only one labeled for clarity). As shown, array map 24 includes eight vertical strips 26a-26h ofthe 256K blocks 30 across, labeled DQ<0> to DQ<7>, and is sixteen strips of the 256K blocks 30 high. Memory cells (not shown) in each 256K block 30 are arranged in a plurality of primary rows and redundant rows. For example, typically 512 primary rows and 4 redundant rows are provided. Sense amplifiers 32 are provided between each row of 256K blocks 30 for sensing data stored in the memory cells therein. Wordline drivers 34 are provided on each side of each vertical strip of 256K blocks 30 for firing a wordline in each 256K block 30 associated with a specified row address. Accordingly, there will be an associated wordline and wordline driver for each row of memory cells in a 256K block 30. Thus, it should be understood that wordline driver 34 actually comprises a plurality of wordline drivers, one for each wordline. Within each 256K block 30, the rows are designated as either an even row or an odd row. Accordingly, each wordline driver 34 will fire either a wordline associated with an odd row or an even row. Fig. 3 illustrates a single horizontal strip of 256K blocks 30 from Fig. 2. Wordline drivers 34a, 34c, 34e, 34g and 34i will fire even row wordlines, while drivers 34b, 34d, 34f and 34h will fire odd row wordlines. Thus, wordline driver 34a will fire even rows 40 in block 26a, wordline driver 34c will fire even rows 40 in blocks 26b and 26c, wordline driver 34e will fire even rows 40 in blocks 26d and 26e, wordline driver 34g will fire even rows 40 in blocks 26f and 26g, and wordline driver 34i will fire even rows 40 in block 26h. Conversely, wordline driver 34b will fire odd rows 42 in blocks 26a and 26b, wordline driver 34d will fire odd rows 42 in blocks 26c and 26d, wordline driver 34f will fire odd rows 42 in blocks 26e and 26f, and wordline driver 34h will fire odd rows 42 in blocks 26g and 26h. A memory cell is accessed by applying a specific row address to the wordline drivers 34. A local wordline driver is driven by application ofthe address and a phase term provided from a global wordline driver (not shown) to activate the selected cell row via one of the row lines, while a column decoder (not shown) will activate the column select circuits to access specified memory cells on an open row. Accordingly, the selected row will be activated across all eight vertical strips 26a-26h. As noted above, memory devices typically employ redundant rows and columns of memory cells so that if a memory cell in a column or row o the primary memory array is defective, then an entire column or row of redundant memory cells can be substituted therefore. Substitution of one or more ofthe spare rows or columns is conventionally accomplished by opening a specific combination of fuses (not shown) or closing antifuses in one of several fuse banks (not shown) on the die. A selected combination of fuses are blown to provide an address equal to the address ofthe defective cell. For example, if the defective cell has an eight- bit binary address of 11011011, then the third and sixth fuses in a set of eight fuses within one of several fuse banks will be blown, thereby storing this address. A compare circuit (not shown) compares each incoming address to the blown fuse addresses stored in the fuse banks to determine whether the incoming address matches with one ofthe blown fuse addresses. If the compare circuit determines a match, then it outputs a match signal (typically one bit). In response thereto, the wordline drivers 34 of a redundant row will be activated to access the redundant row in substitution for the row with the defective memory cell. There are drawbacks, however, with the redundant row substitution approach described above. The redundant rows of memory cells necessarily occupy space on the die. Therefore, it is desirable to obtain the maximum number of repairs using a minimum number of spare rows by utilizing a single bit repair method. This is not possible, however, when a complete redundant row must be substituted for a primary row that has only a single defective memory cell, as a substantial amount of non- defective memory cells will also necessarily be replaced by the redundant row. For example, if vertical strip 26d of Fig. 3 has a defective memory cell, when a redundant row is used to replace the row in which the defective memory cell is located, the entire redundant row will be utilized across all strips 26a-26h, even though there may be no defects in the corresponding row in the other seven strips 26a-26c and 26e- 26h. Thus, there exists a need for a memory device in which efficient use of a redundant circuit to replace a defective primary circuit is provided, thereby minimizing die space required for the redundant circuit. SUMMARY OF THE INVENTION The present invention overcomes the problems associated with the prior art and provides a memory device having a segmented row repair architecture that provides the benefits of localized or single bit repair, thereby efficiently utilizing redundant rows ofthe memory device. In accordance with the present invention, the rows of a memory bank are segmented into four segments and segmented row repair is provided by selectively disabling a wordline driver for only one segment in which a defective memory cell is located and enabling a redundant wordline driver with a redundant term signal provided by the redundancy matching circuit, thereby selecting a redundant row segment for only a specific portion ofthe entire row length. By selectively disabling only the wordline driver associated with the defective memory cell and dividing the primary and redundant rows into four segments, localized or single bit repair can be performed, thereby efficiently utilizing the redundant rows of the memory device. These and other advantages and features ofthe invention will become more readily apparent from the following detailed description ofthe invention which is provided in connection with the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS FIGURE 1 illustrates in block diagram form a conventional memory device; FIGURE 2 illustrates one bank ofthe memory device of Fig. 1; FIGURE 3 illustrates a portion ofthe memory bank from Fig. 2; FIGURE 4 illustrates a portion of a memory device in accordance with the present invention; FIGURE 5 illustrates a memory bank in accordance with the present invention; FIGURE 6 illustrates the segmentation ofthe rows in accordance with the present invention; and FIGURE 7 illustrates in block diagram form a processor system in which a memory device in accordance with the present invention can be used. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described as set forth in the preferred embodiments illustrated in Figs. 4-7. Other embodiments may be utilized and structural or logical changes may be made without departing from the spirit or scope ofthe present invention. Like items are referred to by like reference numerals. In accordance with the present invention, segmented row repair is provided by selectively disabling a wordline driver for a row segment containing a defective memory cell and enabling a redundant wordline driver for a redundant row segment with a redundant term signal provided by the redundancy matching circuit, thereby substituting a redundant row segment for only a specific segment ofthe entire row length which contains a defective memory cell. Fig. 4 illustrates a portion of a memory device having segmented row repair in accordance with the present invention. Specifically, Fig. 4 illustrates the area between two vertical strips ofthe 256K blocks 30 where the wordline drivers 34 are located. In accordance with the present invention, the wordline drivers 34 for the segment ofthe row that includes a defective memory cell can be disabled, and one of the redundant wordline drivers 34 enabled, to replace the defective memory cell, as will be described further below. A global wordline driver 52 activates a desired row by providing an address term and four phase signals, as is known in the art. The use ofthe four phase signals reduces the number of address terms required for each 256K block 30. Thus, for example, if there are 512 rows in the 256K block 30, the number of address terms can be reduced to 128 by using the four phase signals (128x4=512). The four phase signals are global phase signal (GPH) <0> 60, GPH<1> 62, GPH<2> 64 and GPH<3> 66. Similar phase signals are also provided to activate the redundant row included in each 256K block 30. Specifically, the signals for the redundant rows include redundant phase signal (RPH)<0> 70, RPH<1> 72, RPH<2> 74 and RPH<3> 76. In accordance with the present invention, a plurality of AND gates 50a- 5 Oh are provided. A first input of each AND gate 50a-50d is connected to one ofthe four global phase (GPH) signals 60-66 from the global driver 52, and a first input of each AND gate 50e-50h is connected to one ofthe four redundant phase (RPH) signals 70-76. Specifically, AND gate 50a has a first input connected to the signal GPH<1> 62, AND gate 50b has a first input connected to the signal GPH<0> 60, AND gate 50c has a first input connected to the signal GPH<3> 66, AND gate 50d has a first input connected to the signal GPH<2> 64, AND gate 50e has a first input connected to the signal RPH<1> 72, AND gate 50f has a first input connected to the signal RPH<0> 70, AND gate 50g has a first input connected to the signal RPH<3> 76, and AND gate 50h has a first input connected to the signal RPH<2> 74. The output from each AND gate 50a-50d is connected to the wordline drivers 34 for the primary rows of 256K blocks 30, while the output from each AND gate 50e-50h is connected to a redundant wordline drive 34 for the redundant rows of 256K blocks 30. Thus, the output from the AND gates 50a-50h, in conjunction with the address terms from global driver 52 on bus line 80, will drive the desired wordline driver 34 or redundant wordline driver 34 to activate a selected primary row (labeled WL<0:256>) or a redundant row (labeled RWL<0:1> and RWL<2:3>) in the 256K blocks 30. The selective disabling of a wordline driver and enabling of a redundant wordline driver according to the present invention is as follows. In accordance with the present invention, a pair of complementary redundant matching signals, RED 58 and RED* 56, are provided from a matching circuit 82. Signal RED 58 is input to a second input of each AND gate 50e-50h. Signal RED* 56 is input to a second input of each AND gate 50a-50d. Matching circuit 82 compares each mcoming address to addresses of defective memory cells, typically designated by blown fuse addresses stored in fuse banks (not shown), as is known in the art and described with respect to Figs. 1 and 2, to determine whether the mcoming address matches with one ofthe blown fuse addresses, i.e., a defective memory cell. If matching circuit 82 determines there is not a match, i.e., the address for the desired memory cell does not match the address of a defective memory cell, it is not necessary to substitute one ofthe redundant wordlines and the appropriate primary wordline can be activated. The redundant match signal RED 58 output from matching circuit 82 will be low, and accordingly signal RED* 56 will be high. The low input of signal RED 58 to AND gates 50e-50h will cause a low output from AND gates 50e-50h, regardless ofthe state ofthe RPH signals 70-76 being input to AND gates 50e-50h. The low outputs from AND gates 50e-50h will effectively disable the redundant wordline drivers 34 by not driving the redundant wordline, drivers 34. Conversely, the high signal RED* 56 output from matching circuit 82 being input to the second input of AND gates 50a-50d will cause the output of one ofthe AND gates 50a-50d to be high, depending on the state ofthe GPH signals 60-66. Global driver 52 will output a high signal on one phase of signals GPH 60-66, and a high signal on the corresponding signal RPH 70-76, depending on the address ofthe memory cell selected for access and an address specified by match circuit 82 via line 83, respectively, and a low signal on the other three global and other three redundant phase signals. For example, if the address ofthe cell for access requires that phase <1> be high, then both GPH<1> 62 and, for example, RPH<1> 72 will be high, while the remaining phase signals will be low. It should be noted, however, that any one ofthe redundant phase signals RPH 70-76 could be high depending on which programmed fuse bank matched the incoming address. The high signal GPH<1> 62 and the high signal RED* 56 input to AND gate 50a will cause a high output from AND gate 50a, which, along with the address term on bus line 80, will activate the appropriate wordline driver 34 to drive its associated wordline of a primary row ofthe 256K blocks 30 associated with that wordline driver 34. Now suppose, for example, matching circuit 82 determines the address ofthe cell to be accessed matches a defective address, requiring substitution of a redundant element. Matching circuit 82 will output a high match signal RED 58 and accordingly signal RED* 56 will be low. The low input of signal RED* 56 to AND gates 50a-50d will cause a low output from AND gates 50a-50d, regardless ofthe state ofthe GPH signals 60-66 being input to AND gates 50a-50d. The low outputs from AND gates 50a-50d will effectively disable the wordline drivers 34 for the primary rows ofthe 256K blocks 30. Conversely, the high signal RED 58 output from matching circuit 82 being input to the second input of AND gates 50e-50h will cause the output of one ofthe AND gates 5 Oe- 5 Oh to be high, depending on the state ofthe RPH signals 70-76. As noted above, global driver 52 will output a high signal on one phase of signals GPH 60-66, and a high signal on the corresponding signal RPH 70-76, depending on the address ofthe memory cell selected for access and an address specified by match circuit 82 via line 83, respectively, and a low signal on the other three global and other three redundant phase signals. For example, if the address ofthe cell for access requires that phase <1> be high, then both GPH<1> 62 and, for example, RPH<1> 72 will be high, while the remaining phase signals will be low. It should be noted, however, that any one ofthe redundant phase signals RPH 70-76 could be high depending on which programmed fuse bank matched the mcoming address. The high signal RPH<1> 72 and the high signal RED 58 input to AND gate 50e will cause a high output from AND gate 50e, which, along with the address term on line 80, will activate the appropriate redundant wordline driver 34 to drive its associated redundant wordline of a redundant row of its associated 256K blocks 30, such as for example RWL<0>. Thus, by utilizing AND gates 50a-50h in conjunction with the phase signals GPH 60-66 and RPH 70-76, and the redundant matching signals RED 58 and RED* 56, it is possible to disable a wordline driver 34 associated with a defective cell in only a portion of a primary row of 256K block and enable a redundant wordline driver 34 associated with a portion of a redundant row to replace the defective cell. Fig. 5 illustrates how only a portion of a primary row can be selectively disable and replaced with a corresponding portion of a redundant row according to the present invention. Fig. 5 illustrates in block diagram form a 32 Mbit bank 124 in accordance with the present invention. As shown in Fig. 5, matching circuit 82 includes a logic portion 84. Alternatively, the logic portion 84 could be separate from matching circuit 82. The matching signals RED 58 and RED* 56 run between each vertical strip 26a-26h ofthe bank 124 and on the outer edge of strips 26a and 26h. Phase signals GPH 60-66 and RPH 70-76 run between each horizontal strip and on the outer edge ofthe horizontal strips (not shown in Fig. 5 for clarity). The circuitry illustrated in Fig. 4, including the wordline and redundant wordline drivers 34 and AND gates 50a- 5 Oh, is also provided between each vertical strip 26a-26h and on the outer edges of strips 26a and 26h, and in the gap cells 92, i.e., the area of intersection ofthe wordline drivers 34 and sense amplifiers 32 between each vertical strip 26a-26h and each horizontal strip. Logic 84 selectively controls the application ofthe match signals RED 58 and RED* 56 to the vertical strip 26a-26h based on the address of the cell being accessed. Suppose for example there is a defective element 90 in an odd row of 256K block 30 located in the first horizontal strip in vertical strip 26d. The incoming cell address will be compared with the defective cell addresses, and a match determined. Accordingly, the defective element must be replaced by a redundant element. Matching circuit 82 will provide a high match signal RED 58 and low match signal RED* 56 to logic 84. Logic 84, based on the cell address, will provide these signals only on the signal lines 56, 58 located between vertical strips 26c and 26d to disable the primary wordline drivers 34 and enable the redundant wordline drivers 34, as described with respect to Fig. 4, for only the 256K blocks 30 in vertical strips 26c and 26d. The other vertical strips will receive a low match signal RED 58, thereby enabling the worldine drivers 34 associated with the primary rows in the other vertical strips. Accordingly, only a single segment will be replaced by redundant elements. The segmentation ofthe rows according to the present invention is illustrated in Fig. 6. As shown in Fig. 6, each row across a bank of memory is segmented into four segments, labeled Segment<0> to Segment<3>. For odd rows 42, Segment<0> includes the 256K blocks 30 DQ<0> and DQ<1>, Segment<l> includes the 256K blocks 30 DQ<2> and DQ<3>, Segmen <2> includes the 256K blocks 30 DQ<4> and DQ<5>, and Segment<3> includes the 256K blocks 30 DQ<6> and DQ<7>. For the even rows 40, Segment<0> includes the 256K blocks 30 DQ<0> and DQ<7>, Segment<l> includes the 256K blocks 30 DQ<1> and DQ<2>, Segment<2> includes the 256K blocks 30 DQ<3> and DQ<4>, and Segment<3> includes the 256K blocks 30 DQ<5> and DQ<6>. Thus, when only a single segment, such as for example Segment<l> from the above example which includes the odd rows in vertical strip 26d (DQ<3>) is disabled, the remaining segments ofthe redundant row can still be used to repair additional defective cells within the other 256K blocks 30 within this strip. It should be understood that more than one segment can be repaired within each row, i.e., the logic 84 can provide a high match signal RED 58 to more than one segment if necessary. In the case of a cluster failure, in which several defective elements are located within an area, it is still possible to replace an entire row if necessary utilizing the redundant row across the same horizontal strip or to borrow an entire redundant row from other horizontal strips to replace an entire row, or only a portion of an entire row by selectively applying the high redundancy match signal RED 58 to one or more segments. Thus, in accordance with the present invention, the rows of a memory bank are segmented into four segments and segmented row repair is provided by selectively disabling a wordline driver for only one segment in which a defective memory cell is located and enabling a redundant wordline driver with a redundant term signal, thereby selecting a redundant row segment for only a specific portion of the entire row length. By selectively disabling only the wordline driver associated with the defective memory cell and dividing the primary and redundant rows into four segments, localized or single bit repair can be performed, thereby efficiently utilizing the redundant rows ofthe memory device. A typical processor based system which includes a memory device according to the present invention is illustrated generally at 200 in FIG. 7. A computer system is exemplary of a system having digital circuits which include memory devices. Most conventional computers include memory devices permitting storage of significant amounts of data. The data is accessed during operation ofthe computers. Other types of dedicated processing systems, e.g., radio systems, television systems, GPS receiver systems, telephones and telephone systems also contain memory devices which can utilize the present invention. A processor based system, such as a computer system, for example, generally comprises a central processing unit (CPU) 210, for example, a microprocessor, that communicates with one or more input/output (I/O) devices 240 over a bus 270. The computer system 200 also includes random access memory (RAM) such as DRAM 260, and, in the case of a computer system may include peripheral devices such as a floppy disk drive 220 and a compact disk (CD) ROM drive 230 which also communicate with CPU 210 over the bus 270. RAM 260 is preferably constructed as an integrated circuit which includes circuitry to allow for segmented row repair as previously described with respect to Figs. 4-6. It may also be desirable to integrate the processor 210 and memory 260 on a single IC chip. It should be noted that while the preferred embodiment ofthe invention is described as applied to a 256 Mbit memory DRAM device having typical row addressable architecture, the invention is not so limited and may be applied to memory devices having other architectures or sizes as well. Additionally, while the invention has been described with reference to segmenting the rows into four segments, the invention is not so limited and any number of segments can be used. While preferred embodiments ofthe invention have been described and illustrated above, it should be understood that these are exemplary ofthe invention and are not to be considered as limiting. Additions, deletions, substitutions, and other modifications can be made without departing from the spirit or scope ofthe present invention. Accordingly, the invention is not to be considered as limited by the foregoing description but is only limited by the scope ofthe appended claims.

Claims: What is claimed is: 1. A memory device comprising: a first memory bank including a plurality of memory blocks arranged in horizontal and vertical strips, each of said horizontal strips of memory blocks being divided into a plurality of segments, each of said plurality of memory blocks including a plurality of rows of primary memory cells and at least one row of redundant memory cells; a plurality of wordlines for accessing said primary and redundant memory cells of said memory blocks, each of said plurality of wordlines being driven by a respective one of a plurality of drivers; and circuitry for selectively disabling a respective driver for a wordline associated with a row of primary memory cells in which a defective memory cell is located in one of said segments and enabling a respective driver for a wordline associated with a row of redundant memory cells to substitute said row of redundant memory cells for said row of primary memory cells in only said one segment in which said defective memory cell is located. 2. The memory device according to claim 1, wherein at least one of said segments spans at least two adjacent vertical strips of said memory blocks. 3. The memory device according to claim 1, wherein said circuitry further comprises: a plurality of logic gates, each of said plurality of logic gates having an output coupled to an associated wordline driver, wherein said respective driver for a wordline associated with a row of primary memory cells is disabled based on said output of one of said plurality of logic gates, and said respective driver for a wordline associated with a row of redundant memory cells is enabled based on said output of another of said plurality of logic gates. 4. The memory device according to claim 3, wherein said respective driver for said wordline associated with said row of redundant memory cells is enabled and said respective driver for said wordline associated with said row of primary memory cells in which said defective memory cell is located is disabled is further based on a portion of an address of said defective memory cell. 5. The memory device according to claim 3, wherein each of said plurality of logic gates is an AND gate having a first input coupled to one of a plurality of first control signals and a second input coupled to one of a plurality of second control signals. 6. The memory device according to claim 5, wherein said plurality of first control signals are respective phase signals. . 7. The memory device according to claim 6, further comprising: a global driver circuit to provide said respective phase signals. 8. The memory device according to claim 6, wherein said respective phase signals are determined based on an address of a memory cell being accessed. 9. The memory device according to claim 6, wherein said plurality of second control signals includes a redundant match signal and a signal complementary to said redundant match signal. 10. The memory circuit according to claim 9, further comprising: a matching circuit to compare an input memory cell address to an address of said defective memory cell, and if said input memory cell address matches said address of said defective memory cell, outputting a high signal for said redundant match signal and a low signal for said signal complementary to said redundant match signal. 11. The memory device according to claim 10, wherein said high signal for said redundant match signal will enable said respective driver for said wordline associated with said row of redundant memory cells and said low signal for said signal complementary to said redundant match signal will disable said respective driver for said wordline associated with said row of primary memory cells in which said defective memory cell is located. 12. The memory device according to claim 11, further comprising: logic circuitry to provide said high signal and said low signal to only wordline drivers in said segment in which said defective memory cell is located. 13. The memory device according to claim 10, wherein said matching circuit further comprises: a plurality of programmable elements to store said address of said defective memory cell. 14. The memory device according to claim 13, wherein said programmable elements are fuses. 15. The memory device according to claim 1, wherein said circuitry further selectively disables a respective driver for a wordline associated with a row of primary cells in which a second defective memory cell is located in a second of said segments and enables a respective driver for a wordline associated with a row of redundant memory cells in said second segment to substitute a portion of said row of redundant memory cells in said second segment for said row of primary memory cells in said second segment in which said second defective memory cell is located. 16. A memory circuit for repairing a portion of a row of memory blocks of a semiconductor memory device, each of said plurality of memory blocks having a corresponding plurality of rows of primary memory cells and at least one row of redundant memory cells, each of said plurality of rows of primary memory cells and said at least one row of redundant memory cells having an associated wordline driven by a respective one of a plurality of drivers, said memory circuit comprising: a first circuit to compare an input address of a memory cell to be accessed in said memory device with addresses of defective memory cells in said memory device and output a pair of complementary control signals based on said comparison; a second circuit to provide a plurality of phase signals based on said input address of said memory cell to be accessed; and a plurality of logic gates, each of said plurality of logic gates having an output connected to one of said plurality of drivers, a first input connected to a respective one of said plurality of phase signals, and a second input connected to one of said pair of complementary control signals, wherein if said input address of said memory cell to be accessed matches an address of a defective memory cell, said pair of complementary control signals and said plurality of phase signals cause said plurality of logic gates to selectively disable a driver for a respective row of primary memory cells of a memory block in said row of memory blocks in which said defective memory cell is located and enable a driver for said at least one row of redundant memory cells in said memory block to substitute said at least one row of redundant memory cells for said row of primary memory cells in said memory block, without substituting for a corresponding row of primary cells in at least one other of said plurality of memory blocks. 17. The semiconductor memory according to claim 16, wherein said plurality of logic gates are AND gates. 18. The semiconductor memory according to claim 16, wherein said pluraHty of phase signals includes four phase signals. 19. A memory device comprising: a memory array comprising at least one row of primary memory cells; at least one primary row wordline for accessing said primary memory cells, said at least one primary row wordline being divided into a plurality of segments, each of which accesses a respective portion of said primary memory cells; at least one row of redundant memory cells; at least one redundant row wordline for accessing said redundant memory cells, said at least one redundant row wordline being divided into a plurality of segments, each of which accesses a portion of said redundant memory cells; and a programmable logic circuit which can be selectively programmed to replace at least one of said primary row wordline segments associated with a defective memory cell with a redundant row wordline segment during memory access operation. 20. The memory device according to claim 19, wherein said programmable logic circuit further comprises: a plurality of AND gates, each of said plurality of AND gates having a first input coupled to receive one of a plurality of first control signals, a second input coupled to receive on of a plurality of second control signals, and an output coupled to a driver associated with a respective one of said at least one primary row wordline and said at least one redundant row wordline. 21. The memory device according to claim 20, wherein said plurality of first control signals are respective phase signals. 22. The memory device according to claim 20, further comprising: a matching circuit to compare an input memory cell address to an address of said defective memory cell and output said plurality of second control signals based on said comparison. 23. A processor system comprising: a central processing unit; and a memory device connected to said processing unit to receive data from and supply data to said central processing unit, said memory device comprising: a first memory bank including a plurality of memory blocks arranged in horizontal and vertical strips, each of said horizontal strips of memory blocks being divided into a plurality of segments, each of said plurality of memory blocks including a plurality of rows of primary memory cells and at least one row of redundant memory cells; a pluraHty of wordlines for accessing said primary and redundant memory cells of said memory blocks, each of said pluraHty of wordlines being driven by a respective one of a pluraHty of drivers; and circuitry for selectively disabling a respective driver for a wordline associated with a row of primary memory ceUs in which a defective memory ceU is located in one of said segments and enabling a respective driver for a wordline associated with a row of redundant memory ceUs to substitute said row of redundant memory ceUs for said row of primary memory ceUs in only said one segment in which said defective memory ceU is located. 24. The processor system according to claim 23, wherein at least one of said segments spans at least two adjacent vertical strips of said memory blocks. 25. The processor system according to claim 23, wherein said circuitry further comprises: a pluraHty of logic gates, each of said pluraHty of logic gates having an output coupled to an associated wordline driver, wherein said respective driver for a wordHne associated with a row of primary memory cells is disabled based on said output of one of said pluraHty of logic gates, and said respective driver for a wordHne associated with a row of redundant memory ceUs is enabled based on said output of another of said pluraHty of logic gates. 26. The processor system according to claim 25, wherein said respective driver for said wordHne associated with said row of redundant memory ceUs is enabled and said respective driver for said wordline associated with said row of primary memory ceUs in which said defective memory ceU is located is disabled is further based on a portion of an address of said defective memory ceU. 27. The processor system according to claim 26, wherein each of said pluraHty of logic gates is an AND gate having a first input coupled to one of a pluraHty of first control signals and a second input coupled to one of a pluraHty of second control signals. 28. The processor system according to claim 27, wherein said pluraHty of first control signals are respective phase signals. 29. The processor system according to claim 28, further comprising: a global driver circuit to provide said respective phase signals. 30. The processor system according to claim 28, wherein said respective phase signals are determined based on an address of a memory ceU being accessed. 31. The processor system according to claim 28 wherein said pluraHty of second control signals includes a redundant match signal and a signal complementary to said redundant match signal. 32. The processor system according to claim 31, further comprising: a matching circuit to compare an input memory ceU address to an address of said defective memory ceU, and if said input memory ceU address matches said address of said defective memory ceU, outputting a high signal for said redundant match signal and a low signal for said signal complementary to said redundant match signal. 33. The processor system according to claim 32, wherein said high signal for said redundant match signal wiU enable said respective driver for said wordHne associated with said row of redundant memory ceUs and said low signal for said signal complementary to said redundant match signal wiU disable said respective driver for said wordHne associated with said row of primary memory ceUs in which said defective memory ceU is located. 34. The processor system according to claim 33, further comprising: logic circuitry to provide said high signal and said low signal to only wordHne drivers in said segment in which said defective memory ceU is located. 35. The processor system according to claim 32, wherein said matching circuit further comprises: a pluraHty of programmable elements to store said address of said defective memory ceH. 36. The processor system according to claim 35, wherein said programmable elements are fuses. 37. The processor according to claim 23, wherein said circuitry further selectively disables a respective driver for a wordHne associated with a row of primary cells in which a second defective memory ceU is located in a second of said segments and enables a respective driver for a wordHne associated with a row of redundant memory ceUs in said second segment to substitute a portion of said row of redundant memory ceUs in said second segment for said row of primary memory ceUs in said second segment in which said second defective memory ceU is located. 38. The processor system according to claim 23, wherein said central processing unit and said memory device are on a same chip. 39. A processor system comprising: a central processing unit; and a memory device connected to said central processing unit to receive data from and supply data to said central processing unit, said memory device comprising: a pluraHty of memory blocks each having a pluraHty of rows of primary memory ceUs and at least one row of redundant memory ceUs, each of said plurality of rows of primary memory ceHs and said at least one row of redundant memory ceUs having an associated wordHne driven by a respective one of a pluraHty of drivers; and a memory circuit for repairing a portion of a row of said pluraHty of memory blocks, said memory circuit comprising: a first circuit to compare an input address of a memory ceU to be accessed in said memory device with addresses of defective memory ceUs in said memory device and output a pair of complementary control signals based on said comparison; a second circuit to provide a pluraHty of phase signals based on said input address of said memory ceU to be accessed; and a pluraHty of logic gates, each of said pluraHty of logic gates having an output connected to one of said pluraHty of drivers, a first input connected to a respective one of said pluraHty of phase signals, and a second input connected to one of said pair of complementary control signals, wherein if said input address of said memory ceH to be accessed matches an address of a defective memory ceU, said pair of complementary control signals and said pluraHty of phase signals cause said pluraHty of logic gates to selectively disable a driver for a respective row of primary memory ceUs of a memory block in said row of memory blocks in which said defective memory ceU is located and enable a driver for said at least one row of redundant memory ceUs in said memory block to substitute said at least one row of redundant memory ceUs for said row of primary memory ceUs in said memory block, without substituting for a corresponding row of primary ceUs in at least one other of said pluraHty of memory blocks. 40. The processor system according to claim 39, wherein said pluraHty of logic gates are AND gates. 41. The processor system according to claim 39, wherein said pluraHty of phase signals includes four phase signals. 42. The processor system according to claim 39, wherein said central processing unit and said memory device are on a same chip. 43. A processor system comprising: a central processing unit; and a memory device connected to said central processing unit to receive data from and supply data to said central processing unit, said memory device comprising: a memory array comprising at least one row of primary memory ceUs; at least one primary row wordHne for accessing said primary memory ceUs, said at least one primary row wordHne being divided into a pluraHty of segments, each of which accesses a respective portion of said primary memory ceHs; at least one row of redundant memory ceUs; at least one redundant row wordHne for accessing said redundant memory ceUs, said at least one redundant row wordHne being divided into a pluraHty of segments, each of which accesses a portion of said redundant memory ceUs; and a programmable logic circuit which can be selectively programmed to replace at least one of said primary row wordHne segments associated with a defective memory ceU with a redundant row wordHne segment during memory access operation. 44. The processor system according to claim 43, wherein said programmable logic circuit further comprises: a pluraHty of AND gates, each of said pluraHty of AND gates having a first input coupled to receive one of a pluraHty of first control signals, a second input coupled to receive on of a pluraHty of second control signals, and an output coupled to a driver associated with a respective one of said at least one primary row wordHne and said at least one redundant row wordHne. 45. The processor system according to claim 44, wherein said pluraHty of first control signals are respective phase signals. 46. The processor system according to claim 44, further comprising: a matching circuit to compare an input memory ceU address to an address of said defective memory ceU and output said pluraHty of second control signals based on said comparison. 47. A method for repairing out at least one defective memory ceU in a memory device, said method comprising: segmenting a each of a pluraHty of rows of primary memory ceU rows and at least one redundant memory ceU row into a pluraHty of segments such that each segment corresponds to at least two row blocks of said memory device; disabling a primary memory ceU row in only a segment in which said at least one defective memory ceU is located; enabling said at least one redundant memory ceU row in said segment; and repairing out said primary memory ceU row with said at least one redundant memory ceH row in only said segment in which said at least one defective memory ceU is located. 48. The method according to claim 47, wherein said steps of segmenting further comprises: segmenting each of a pluraHty of rows of primary memory ceU rows and at least one redundant memory ceH row into a pluraHty of segments such that each segment corresponds to at least two adjacent row blocks of said memory device. 49. The method according to claim 47, wherein said step of disabling further comprises: comparing an input address of a memory ceU to an address of said at least one defective memory ceU; and if said input address of a memory ceU matches said address of said at least one defective memory ceU, providing a first control signal to a first logic circuit, wherein an output of said first logic circuit disables said primary memory ceU row in only said segment in which said at least one defective memory ceU is located. 50. The method according to claim 49 wherein said first logic circuit is an AND gate, said method further comprising: inputting said first control signal to a first input of said AND gate; inputting a first phase signal to a second input of said AND gate, said first phase signal being based in part on said input address; and providing said output of said AND gate to disable said primary memory ceU row in only said segment Hi which said at least one defective memory ceH is located. 51. The method according to claim 50, wherein said step of enabling further comprises: providing a second control signal to a second logic circuit, said second control signal being complementary to said first control signal, wherein an output of said second logic circuit enables said at least one redundant memory ceU row in said segment. 52. The method according to claim 51 wherein said second logic circuit is a second AND gate, said method further comprising: inputting said second control signal to a first input of said second AND gate; inputting a second phase signal to a second input of said second AND gate, said second phase signal being based H part on said input address; and providing said output of said second AND gate to enable said at least one redundant memory ceH row in said segment. 53. A method for repairing out a defective memory ceH in a memory device, said method comprising: locating said defective memory ceU in said memory device; identifying a segment of a row of memory blocks in which said defective memory ceU is located; disabling a driver associated with a primary memory ceU row in which said defective memory ceU is located in only said identified segment; enabling a driver associated with a redundant memory ceU row in only said identified segment; and repairing out said defective memory ceH with said redundant memory ceH row in only said identified segment.

Inventors: KEETH BRENT, KEETH, BRENT
Applicants: MICRON TECHNOLOGY INC, MICRON TECHNOLOGY, INC.
Application year: 2001
Main classification: G11C
IPC codes: G11C11, G11C29