METHOD AND ARRANGEMENT FOR REGULATING LOW OUTPUT VOLTAGES IN MULTIPLE OUTPUT FLYBACK DC/DC CONVERTERS

Abstract: To generate, in addition to a main output DC voltage (U1), at least one additional output DC voltage (U2) in a flyback DC/DC converter having a transformer (TR) with a primary winding connected in series with a primary switch (T1), a first secondary winding (N1+N2) connected in series with a first rectifier (D1) to a first output capacitor (C1) for generating said main output DC voltage (U1), and a second secondary winding (N2) connected in series with a synchronous rectifier (T2) to a second output capacitor (C2) for generating said additional output DC voltage (U2), an error amplifier (3) is provided to compare the actual value of said additional output DC voltage (U2) with a desired value, and a control circuit (C4, R4, R3, T5) is interconnected between the error amplifier (3) and the synchronous rectifier (T2) to adjust the turn-off time of the synchronous rectifier (T2) in response to the ratio between the actual value of said additional output DC voltage (U2) and the desired value to adjust the actual value to the desired value.

Description: METHOD AND ARRANGEMENT FOR REGULATING LOW OUTPUT VOLTAGES IN MULTILE OUTPUT FLYBACK DC/DC CONVERTERS TECHNICAL FIELD The invention relates generally to multiple output flyback DC/DC converters and more specifically to a method and an arrangement for regulating low output voltages to tight tolerances in multiple output flyback DC/DC converters. BACKGROUND OF THE INVENTION There is a demand for converters supplying in addition to a main output DC voltage, at least one additional output DC voltage lower than the main output voltage. If diodes are used for generating the additional output DC voltages, the voltage drop across the diodes can be as high as 0.5 V. This means that for low output voltages, e.g. < 3.3 V, the efficiency will be low. When high efficiency is needed, synchronized rectification has to be used since the voltage drop across synchronous rectifiers, i.e. MOSFETs, is much lower than across diodes. In multiple output converters, the main output voltage is regulated in a manner known per se by regulating the duty cycle of the primary switch. However, additional output voltages can not be regulated in multiple output converters by regulating the duty cycle of the primary switch but have to be separately regulated, e.g. by means of complicated switched series-regulators. SUMMARY OF THE INVENTION The object of the invention is to bring about a method and an arrangement for controlling a MOSFET used as synchronous rectifier to regulate low output voltages to tight tolerances. This is attained in accordance with the invention by controlling the switch-off time of the MOSFET to vary its on-period. Hereby, the output voltage can be controlled between the voltage drop in the body diode of the MOSFET and the saturation voltage of the MOSFET. This voltage difference is only about 0.3 to 0.4 V but large enough for regulating a 3.3 V output voltage to tight tolerances. BRIEF DESCRIPTION OF THE DRAWING The invention will be described more in detail below with reference to the appended drawing on which Fig. 1 shows an embodiment of a multiple output flyback DC/DC converter in accordance with the invention, and Figs. 2A-2F are diagrams illustrating different signals in the embodiment in Fig. 1. DESCRIPTION OF THE INVENTION Fig. 1 shows an embodiment of a multiple output flyback DC/DC converter in accordance with the invention. In the embodiment in Fig. 1, in addition to a main output voltage Ul, a single additional output voltage U2 is generated. It is however to be understood that it is possible to generate more than one additional output voltage. In such a case, for every additional output voltage to be generated, there has to be an arrangement corresponding to the arrangement for generating the additional output voltage U2 to be described below. The converter in Fig. 1 comprises in a manner known per se, a transformer TR having a primary winding connected in series with a primary switch Tl to a schematically illustrated DC voltage source VI, and a secondary winding N1+N2 connected in series with a diode Dl to an output capacitor Cl for generating the main output DC voltage Ul . The on and off periods of the primary switch Tl, i.e. its duty cycle, is controlled by a switch duty cycle regulator or switch control unit 1 in response to output signals αf an error amplifier 2 connected with its input terminals across the capacitor Cl for generating output signals in response to differences between the actual value of the output voltage Ul and a desired value set within the error amplifier 2. To generate the additional output DC voltage U2 in accordance with the invention, in the embodiment in Fig. 1, a part N2 of the secondary winding of the transformer TR is connected in series with a synchronous rectifier in the form of a MOSFET T2 to an output capacitor C2. Instead of a common secondary winding N1+N2, it is to be understood that separate secondary windings (not shown) can be used for generating the main and the additional output DC voltages Ul and U2, respectively. In a manner known per se, the MOSFET T2 comprises a source S, a drain D, and a gate G as well as a body diode D2 connected with its anode to the source S and with its cathode to the drain D of the MOSFET T2. In the embodiment shown in Fig. 1, the drain D of the MOSFET T2 is connected to the source S of the MOSFET T2 via a resistor Rl in series with a diode D3 and a capacitor C3. The interconnection point between the diode D3 and the capacitor C3 is connected to the collector of a transistor T3. The emitter of the transistor T3 is connected to the gate G of the MOSFET T2 and to the emitter of a transistor T4 whose collector is connected to the source S of the MOSFET T2. The transistors T3 and T4 are two emitter-followers that quickly can charge/discharge the gate G of the MOSFET T2. The bases of the transistors T3 and T4 are interconnected and connected via a resistor R2 to the collector of the transistor T3. . The interconnected bases of the transistors T3 and T4 are also connected to the collector of a transistor T5 whose emitter is connected to the source S of the MOSFET T2. The base of the transistor T5 is connected via resistor R3 in series with a capacitor C4 to the drain D of the MOSFET T2. In accordance with the invention, the interconnection point between the resistor R3 and the capacitor C4 is connected via a resistor R4 to an output terminal of an error amplifier 3. The error amplifier 3 is connected with its input terminals across the capacitor C2 for generating output signals in response to differences between the actual value of the additional output voltage U2 and a desired value set within the error amplifier 3 to control the MOSFET T2. As mentioned above, the switch Tl is the primary switch of the flyback converter. When the switch Tl is on, magnetic energy is stored in the transformer TR and the voltage across the secondary winding of the transformer TR is assumed to be negative. When the primary switch Tl turns off, the voltage across the secondary winding of the transformer TR goes positive and a current ID1 will flow through the diode Dl to charge the capacitor Cl, and a current IT2 will flow through the MOSFET T2 to charge the capacitor C2. With reference to the diagrams in Figs. 2A-2F, the operation of the converter illustrated in Fig. 1 during one off-period of the primary switch Tl will now be described in more detail. It should be pointed out that the diagrams in Figs. 2A-2F are essentially theoretical, i.e. more or less idealized. The primary switch Tl is supposed to be on from the beginning and is supposed to be turned off at time tl and turned on again at time t4 as illustrated in Fig. 2 A. , • When the primary switch Tl is on, the voltage across the winding N2 is negative and the capacitor C3 is charged via the resistor Rl in series with the diode D3. At time tl when the primary switch Tl turns off, the body diode D2 of the MOSFET T2 begins to conduct to charge the output capacitor C2. In Fig. 2B, the source-drain voltage U S . D T2 of the MOSFET T2 is illustrated. Base current will be supplied to the transistor T3 via the resistor R2. The gate G of the MOSFET T2 will be charged causing the MOSFET T2 to become saturated. Fig. 2C illustrates the gate-source voltage Uo- s T2 of the MOSFET T2. In the following description, it is assumed that, at time tl, the output voltage U2 is higher than the desired value set within the error amplifier 3. The error amplifier 3 senses that the output voltage U2 is higher than the desired value and starts to discharge the capacitor C4 via the resistor R4. This causes the transistor T5 to start to conduct at time t2 as apparent from Fig. 2D that illustrates the base-emitter voltage U B - E T5 of the transistor T5. When the transistor T5 starts to conduct at time t2, the gate charge of the gate G of the MOSFET T2 will begin to be discharged via the transistor T4 as illustrated in Fig. 2C. The gate charge of the gate G is supposed to have been fully discharged at time t3. Thus, at time t3, the MOSFET T2 turns off. When the MOSFET T2 turns off at time t3, the current IT2 through it will drop as illustrated in Fig. 2E. However, due to imperfections of the transformer TR and the existence of the body diode D2 in the MOSFET T2, the current IT2 will not drop to zero. The drop of the current IT2 will cause a corresponding jump of the current IDl through the diode Dl as illustrated in Fig. 2F. This jump of the current IDl tends to increase the main output voltage Ul . The error amplifier 2 will sense this increase of the main output voltage Ul and in response hereto control the duty cycle regulator 1 to adjust the duty cycle of the primary switch Tl in such a manner that the main output voltage Ul is decreased to the desired value. Between time t3 when the MOSFET T2 turns off, and time t4 when the primary switch Tl turns on again, the currents IT2 and IDl decrease due to the fact that the energy stored in the transformer TR decreases. By controlling the MOSFET T2 in this manner, i.e. by adjusting its turn-off time in response to that the actual value of the additional voltage U2 exceeds the desired value, it is possible to regulate low additional output DC voltages in the interval between the voltage drop of the body diode D2 and the saturation voltage of the MOSFET T2 to tight tolerances.

Claims: CLAIMS 1. A method of generating, in addition to a main output DC voltage, at least one additional output DC voltage in a flyback DC/DC converter having a transformer with a primary winding connected in series with a primary switch to an input DC voltage source, a first secondary winding connected in series with a first rectifier to a first output capacitor for generating said main output DC voltage across said first output capacitor, and a second secondary winding connected in series with a second rectifier to a second output capacitor for generating said additional output DC voltage across said second output capacitor, characterized by - selecting a synchronous rectifier as said second rectifier, - comparing the actual value of said additional output DC voltage with a desired value, and - adjusting the turn-off time of the synchronous rectifier in response to the ratio between the actual value and the desired value to adjust the actual value to the desired value. 2. An arrangement for generating, in addition to a main output DC voltage (Ul), at least one additional output DC voltage (U2) in a flyback DC/DC converter having a transformer (TR) with a primary winding connected in series with a primary switch (Tl) to an input DC voltage source (VI), a first secondary winding (N1+N2) connected in series with a first rectifier (Dl) to an first output capacitor (Cl) for generating said main output DC voltage (Ul) across said first output capacitor (Cl), and a second secondary winding (N2) connected in series with a second rectifier (T2) to a second output capacitor (C2) for generating said additional output DC voltage (U2) across said second output capacitor (C2), characterized in - that said second rectifier (T2) is a synchronous rectifier, - that an error amplifier (3) is provided to compare the actual value of said additional output DC voltage (U2) with a desired value, and - that a control circuit (C4, R4, R3, T5) is interconnected between the error amplifier (3) and the synchronous rectifier (T2) to adjust the turn-off time of the synchronous rectifier (T2) in response to the ratio between the actual value of said additional output DC voltage (U2) and the desired value to adjust the actual value to the desired value.

Inventors: ASSOW BENGT, ASSOW, BENGT
Applicants: ERICSSON TELEFON AB L M, TELEFONAKTIEBOLAGET LM ERICSSON (PUBL)
Application year: 2001
Main classification: H02M3
IPC codes: H02M3