MEMORY CELL WITH VERTICAL FLOATING GATE TRANSISTOR

Abstract: A semiconductor device (8) includes a substrate (10) having a trench (18) formed therein. A gate structure for a vertical transistor is formed adjacent to a sidewall of the trench. The gate structure includes a floating gate conductor (52) formed in contact with sidewalls of the trench. The floating gate forms a void in a center portion of the floating gate conductor, and the center portion has vertically disposed surfaces. A dielectric layer (46) lines the void in the center portion of the floating gate conductor, and a control gate (48) conductor is formed in contact with the dielectric layer. The control gate conductor fills the void in the center portion of the floating gate conductor. Methods for fabricating the semiconductor device are also disclosed.

Description: MEMORY CELL WITH VERTICAL FLOATING GATE TRANSISTOR BACKGROUND 1. Technical Field This disclosure relates to semiconductor structures and fabrication methods, and more particularly, to memory cells and methods for fabrication of memory cells with floating gates which are independent of lithographic scaling. 2. Description of the Related Art Semiconductor memories, such as flash memories include lithographically patterned features. In many cases, the current lithographic processes dictate the smallest feature size (F) possible for line structures formed in the semiconductor fabrication process. The desire to shrink chip sizes and increases in layout density have caused improved lithographic resolution. This lithographic resolution improvement has lead to smaller structural components, which are formed on a semiconductor device. In some instances smaller features led to other problems. For example, shorter channels are subject to short channel effects. One solution for conserving layout area on a chip may include the formation of vertical devices, e.g., transistors. The length of the transistor channel, for example, can extend deep into a semiconductor substrate. For flash memory devices, a floating gate activates transistors. The floating gate is capacitively coupled to a wordline so that when the wordline is activated, the floating gate can cause conduction through a channel of the transistor. The floating gate and the wordline function as capacitor plates. It is advantageous to have the largest possible cross-sectional area between the plates of a capacitor to ensure the best possible capacitive coupling. However, due to lithographic processing limitations less than desirable capacitive coupling is experienced since the cross-sectional area is limited. Therefore, a need exists for a memory cell and a method for fabrication of a memory device, which provide a structure where the floating gate is independent of lithographic scaling. A further need exists for a flash memory cell with a floating gate, which includes a 4F 2 memory cell area. SUMMARY OF THE INVENTION In accordance with the invention, a method for fabricating a semiconductor device includes forming a trench in a semiconductor substrate and depositing a first conductive material in the trench. The first conductive material is etched in the trench to remove a portion of the first conductive material such that the first conductive material includes vertically disposed interior surfaces and remains in contact with sidewalls of the trench to form a floating gate conductor. A dielectric layer is deposited over the interior surfaces of the first conductive material, and a second conductive material is deposited over the dielectric layer to fill the trench to form a control gate conductor for capacitively coupling to the floating gate conductor. In other methods, the interior surfaces of the first conductive material may include a circular cross-section or a rectangular cross-section in a plane parallel to a major surface of the substrate. The step of etching may include performing a spacer etch to remove the portion of the first conductive material. The step of depositing a dielectric layer may include depositing a dielectric layer including ONO . The method preferably includes the step of forming a gate oxide on the sidewalls of the trench. A vertical transistor channel is preferably formed in the substrate adjacent to the trench and the method preferably includes the step of forming a gate oxide on the sidewalls of the trench such that when the floating gate is activated conduction occurs through the channel . The method may include the step of forming a wordline in electrical contact with the control gate conductor. A semiconductor device of the present invention includes a substrate having a trench formed therein and a gate structure for a vertical transistor formed adjacent to a sidewall of the trench. The gate structure includes a floating gate conductor formed in contact with sidewalls of the trench and forming a void in a center portion of the floating gate conductor, the center portion having vertically disposed surfaces. A dielectric layer lines the void in the center portion of the floating gate conductor, and a control gate conductor is formed in contact with the dielectric layer and fills the void in the center portion of the floating gate conductor. In other embodiments, the trench preferably includes a gate dielectric formed on the sidewalls thereof. The vertical transistor may include a vertical channel disposed adjacent to the trench, the vertical channel conducting when activated by the floating gate conductor. The vertical channel preferably connects a source region to a vertically offset drain region when activated by the floating gate conductor. One of the source region and the drain region are connected to a bit line by a contact . The source region or the drain region, and the contact are shared by two adjacent vertical transistors. The control gate conductor is preferably electrically connected to a wordline. The floating gate conductor may include a circular cross-section or a rectangular cross-section in a plane parallel to a major surface of the substrate. Another semiconductor device of the present invention includes a substrate having a trench formed therein and a gate structure for a vertical transistor formed adjacent to a sidewall of the trench. The gate structure occupies a layout area including one of a length or width of a groundrule size, F. The gate structure further includes a floating gate conductor formed in the trench in contact with sidewalls of the trench and forming a void in a center portion of the floating gate conductor, the center portion having vertically disposed surfaces. A dielectric layer lines the void in the center portion of the floating gate conductor, and a control gate conductor is formed in contact with the dielectric layer and fills the void in the center portion of the floating gate conductor such that a surface area between the control gate and the floating gate is greater than F 2 . In other embodiments, the trench preferably includes a gate dielectric formed on the sidewalls thereof. The vertical transistor may include a vertical channel disposed adjacent to the trench, the vertical channel conducting when activated by the floating gate conductor. The vertical channel preferably connects a source region to a vertically offset drain region when activated by the floating gate conductor. The source region or the drain region is connected to a bit line by a contact . The source region or the drain region and the contact are shared by two adjacent vertical transistors. The control gate conductor is preferably electrically connected to a wordline. The floating gate conductor may include a rectangular cross-section or a circular cross-section in a plane parallel to a major surface of the substrate. The gate structure occupies a layout area including both a length and width of about a groundrule size, F. The gate structure occupies a layout area equal to the layout area occupied by the trench; however the contact gate and the floating gate have a common surface area of greater than F 2 . A memory cell, which includes the gate structure, may occupy a layout area of about 4F 2 . These and other objects, features and advantages of the present invention will become apparent from the following detailed description of illustrative embodiments thereof, which is to be read in connection with the accompanying drawings . BRIEF DESCRIPTION OF DRAWINGS This disclosure will present in detail the following description of preferred embodiments with reference to the following figures wherein: FIG. 1 is a top schematic view showing the orientation and position of diffusion regions formed in a substrate of a semiconductor device in accordance with one embodiment of the present invention; FIG. 2 is a cross-sectional view taken at section line 2- 2 of FIG. 1 showing trenches filled after forming the diffusion regions in accordance with the present invention; FIG. 3 is a cross-sectional view taken at section line 3- 3 of FIG. 1 showing trenches filled after forming the diffusion regions in accordance with the present invention; FIG. 4 is a cross-sectional view taken at section line 4- 4 of FIG. 5 showing of the semiconductor device of FIG. 2 after isolation regions are formed in accordance with the present invention; FIG. 5 is a top layout view showing the isolation regions formed in accordance with one embodiment of the present invention; FIG. 6 is a cross-sectional view taken at section line 6- 6 of FIG. 5 after isolation regions are formed in accordance with the present invention; FIG. 7 is a magnified cross-sectional view of the semiconductor device of FIG. 4 showing the formation of a gate dielectric and a trench top dielectric in accordance with the present invention; FIG. 8 is a magnified cross-sectional view of the semiconductor device of FIG. 7 showing the formation of a floating gate conductor by a spacer etch process in accordance with the present invention; FIG. 9A is a cross-sectional view of the semiconductor device of FIG. 8 showing the formation of a control gate conductor in accordance with the present invention; FIG. 9B is a magnified cross-sectional view of the semiconductor device of FIG. 9A showing the formation of a control gate conductor in accordance with the present invention; FIG. 10 is a cross-sectional view taken at section line 10-10 of FIG. 9A showing a memory array in a top view in accordance with the present invention; FIG. 11 is a cross-sectional view taken along the plane section line 11-11 of FIG. 10 in accordance with the present inven ion; FIG. 12 is a cross-sectional view taken at section line 12-12 of FIG. 13 after a gate stack, contacts and a bitline are formed in accordance with the present invention; FIG. 13 is a top layout view with layers removed so that gate stacks may be viewed in accordance with the present invention; FIG. 14 is a cross-sectional view taken at section line 14-14 of FIG. 13 in accordance with the present invention; FIG. 15 is a top schematic view showing the orientation and position of diffusion regions formed in a substrate of a semiconductor device in accordance with another embodiment of the present invention; FIG. 16 is a cross-sectional view taken at section line 16-16 of FIG. 15 showing trenches and diffusion regions formed in accordance with the present invention; FIG. 17 is a cross-sectional view taken at section line 17-17 of FIG. 15 showing trenches and diffusion regions formed in accordance with the present invention; FIG. 18 is a cross-sectional view taken at section line 18-18 of FIG. 19 showing of the semiconductor device of FIG. 16 after formation of floating and control gate conductors in accordance with the present invention; FIG. 19 is a top layout view showing floating and control gate structures extending longitudinally down along the semiconductor device in accordance with the present invention; FIG. 20 is a cross-sectional view taken at section line 20-20 of FIG. 19 showing a control gate formed in accordance with the present invention; FIG. 21 is a top layout view showing isolation regions formed perpendicularly to the gate structures of FIG. 19 in accordance with the present invention; FIG. 22 is a cross-sectional view taken at section line 22-22 of FIG. 21 gate structures formed in accordance with the present invention; FIG. 23 is a cross-sectional view taken at section line 23-23 of FIG. 21 showing isolation regions in accordance with the present invention; FIG. 24 is a cross-sectional view taken at section line 24-24 of FIG. 25 after a gate stack, contacts and a bitline are formed in accordance with the present invention; FIG. 25 is a top layout view with layers removed so that gate structures may be viewed in accordance with the present invention; and FIG. 26 is a cross-sectional view taken at section line 26-26 of FIG. 25 showing isolation regions formed in accordance with the present invention. DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS The present invention includes memory cells and methods for fabrication wherein a floating gate is independent of lithographic scaling. The present invention will be illustratively described in terms of flash memory cells and fabrication methods. However, the present invention is broader and is applicable to any semiconductor device, which can benefit from reduced layout area and increased channel length for transistors formed thereon. As will become apparent from the following description, the present invention may include bitline contacts shared between every 2 cells for lower bitline capacitance. In one embodiment, a very high capacitive coupling between a control (e.g., wordline) and a floating gate is achieved. In another embodiment, a more uniform cell structure is provided where the gate structures are formed in a trench, which extends across the memory array. Referring now in specific detail to the drawings in which like reference numerals identify similar or identical elements throughout the several views, and initially to FIG. 1, a top view of a substrate 10 is shown indicating diffusion regions 12. Diffusion regions 12 are shown to illustrate their orientation and to indicate cross-sectional directions for FIGS. 2 and 3. Substrate 10 is preferably a semiconductor substrate, such as, for example, a doped monocrystalline silicon, although other substrate materials may be employed. Substrate 10 is preferably part of a memory array for a memory device 8. Memory device 8 may be any memory device having a floating gate structure. In a preferred embodiment, device 8 includes a flash memory device, such as for example, an electrically erasable nonvolatile memory. Other programmable memories are also contemplated. The fabrication of a 4F 2 area memory cell will be illustratively described to demonstrate one aspect of the present invention. Dimension arrows "D" will be indicated throughout the views to illustratively demonstrate a groundrule dimension or minimum feature size dimension F. Each double-headed arrow D will illustratively indicate F. Of course, other memory cell areas may be realized in accordance with the present invention. Referring to FIGS. 2 and 3, before the formation of diffusion regions 12 of FIG. 1, substrate 10 is subjected to an oxidation process to form a pad oxide layer 14. Pad oxide 14 is covered by a dielectric layer 16, such as for example, a nitride layer (e.g., pad nitride) . A hardmask layer (not shown) is formed on layer 16, followed by the patterning of a lithographic mask (not shown) . The lithographic mask is employed to pattern the hardmask by known etching methods. Hardmask is then employed to etch dielectric layer 16, pad oxide 14 and substrate 10 to form trenches 18. Diffusion regions 12 are formed by a known implanting process (e.g., N- type dopant implant) . Diffusion regions 12 form source lines for vertical transistors, which will be described in greater detail below. The hardmask is removed, and a buffer oxidation process is performed to form an oxide 20 on surfaces within trenches 18. Trenches 18 are filled with a material 22, preferably polysilicon, by a deposition process. Material 22 is planarized by, for example, a chemical-mechanical polishing process to provide top surface 24. Dielectric layer 14 is now removed . Referring to FIG. 4, a dielectric layer 26, for example a nitride layer, is deposited and patterned (See FIG. 5) by employing a hardmask (e.g., a TEOS hardmask) and a lithographic process (not shown) . Isolation trenches 28 are etched in accordance with the hardmask employed to pattern layer 26. Isolation trenches 28 are preferable etched by an anisotropic etching process, such as for example, reactive ion etching. The hardmask is removed, and a dielectric material 30 is deposited to fill trenches 28. Dielectric material 30 may include an oxide, and more preferably, a high density plasma (HDP) deposited oxide. A chemical-mechanical polish (CMP) process is performed to planarize dielectric material 30 down to dielectric layer 26, and trench isolation regions 32 are formed . Referring to FIGS. 5 and 6, a top view (FIG. 5) of the memory array of device 8 is shown after planarization of material 30 to form isolation regions 32. FIG. 6 shows a cross-sectional view of a section indicated in FIG. 5, which is perpendicular to the section of FIG. 4. Dielectric layer 26 is now removed. Referring to FIG. 7, active area doping is now performed to form diffusion regions 34. A doping mask layer (not shown) is formed over device 8 and pattered to permit doping of substrate 10 between trenches 18. One or more known implantation processes may be employed to form diffusion regions 34, which will function as a drain for a vertical transistor as will be explained below. The doping mask layer is now removed and material 22 is removed from trenches 18. A dielectric layer 38 is formed on horizontal surfaces, preferably an oxide formed by a high density plasma (HDP) oxidation process. Layer 38 may be referred to as a trench top oxide (TTO) . Vertical sidewalls of trenches 18 are oxidized to form a gate oxide 40 thereon. Referring to FIG. 8, a conductive material 42, such as a polysilicon film, is conformally deposited in trenches 18. A spacer etch process is performed to leave a spacer from material 42, which lines sidewalls of trench 18. A center .region 44 does not include material 42. The spacer etch process includes an anisotropic etch process, such as reactive ion etching (RIE) . RIE is tuned to etch the thickness of the layer of conductive material 42 to thereby leave spacers 42. Other processes may also be employed to form conductive material, which lines the sidewalls of trench 18. Referring to FIGS. 9A and 9B, a dielectric layer 46 is deposited over exposed surfaces of material 42. Layer 46 will function as a capacitor dielectric between material 42 (which forms a floating gate in accordance with the invention) and a control gate 48. Layer 46 may include a nitride, such as silicon nitride and preferably a layer of 0N0 (silicon oxide, silicon nitride, silicon oxide) . If ONO is employed, a thickness for layer 46 may be between 10 to 20 nm. A conductive material 50 is deposited over layer 46. Material 50 preferably includes polysilicon. Material 50 is planarized (e.g., by CMP) down to layer 46 (or layer 38). Material 50 forms control gate 48. Control gate 48 and floating gate 52 function as capacitor plates separated by layer 46. In one illustrative embodiment, the memory array is processed along with a support region (not shown) . A silicon nitride liner 54 is formed over device 8. The array region and support region are masked. The support region mask is opened and liner 54 is etched in the support region followed by support processing (e.g., sacrificial oxidation, implants, gate oxidation, polysilicon deposition and/or other known processes) . After processing the support region, the polysilicon layer employed in processing the support region is removed from the array region followed by deglazing liner 54 and the removal of liner 54 from the array region. Referring to FIGS. 10 and 11, FIG. 10 is a cross- sectional view taken at section line 10-10 of FIG. 9A. FIG. 10 shows floating gate 52 and control gate 48 having layer 46 disposed therebetween. The surface area between gates 48 and 52 is increased by at least one order of magnitude over conventional floating gates, which typically occupy IF 2 in area. Advantageously, the surface area between gates 48 and 52 occupies a three dimensional space in a conical or cylindrical configuration. This configuration can extend deep into substrate 10 and is virtually unlimited in terms of surface area between gates 48 and 52. FIG. 11 shows a cross- section taken along the direction of section line 11-11 in FIG. 10. Referring to FIG. 12, gate stacks 60 are formed by depositing and patterning a conductive layer or conductive layers in electrical contact with control gate 48. A layer 62 may include polysilicon (e.g., heavily doped) and a high conductivity layer 64 (e.g., Tungsten, Tungsten suicide, or other highly conductive material) . A dielectric cap 66 and spacers 68, preferably formed from silicon nitride, are provided to isolate gate stack 60 from contacts 70. Contacts 70 are formed through a dielectric layer 72, which may be formed from silicon dioxide. Holes for contacts 70 need to be formed through dielectric layer 72, layer 46 and layer 38 to make contact to diffusion region 34. A conductive line 74 is formed to provide access to vertical transistors 76. When gate stack 60 (wordline) is activated conduction is achieved through transistor 76 between diffusion region 12 and line 74. This process provides a high capacitive coupling between control gate 48 and a vertical floating gate 52. Transistors 76 are created along the side of trench 18 in substrate 10. In the illustrative embodiment described, the source junction (12) is implanted through the trench bottom and creates a buried conductive path across the array. Overlap of a source junction 12 and a vertical floating gate 46 provides an interface for electrical erasing (e.g., when a source erase is employed) . The floating gate 52 is created by deposition and a spacer etch, forming a spacer structure in the trench. The control gate 48 is deposited after dielectric layer 46 deposition on floating gate 52 and provides electrical contact to the wordline (gate stack 60) . The drain junction (34) is formed by an implantation step at the active area surface and is connected to line 74 (e.g., bit line) through contacts 74. Advantageously, each contact 74 (and drain region 34) services two adjacent memory cells. It is to be understood that the source and drain regions may be reversed, or may include conductive regions such as storage nodes, conductive lines or other devices or structures. Referring to FIGS. 13 and 14, a top layout of device 8 is schematically shown with an outline of layer 46 for reference. Note that arrows " D" indicate a 4F 2 or less area memory cell in accordance with the invention. The present invention provides a substantial increases in floating gate to control gate surface area while maintaining a small (e.g., 4F 2 or less) memory cell area. FIG. 14 shows a cross-section taken along the direction of section line 14-14 in FIG. 13. Another illustrative embodiment will now be described. Referring to FIG. 15, a top view of substrate 10 is shown indicating diffusion regions 13. Diffusion regions 13 are shown to illustrate their orientation and to indicate cross- sectional directions for FIGS. 16 and 17. Substrate 10 is preferably a semiconductor substrate, such as, for example, a doped monocrystalline silicon, although other substrate materials may be employed. Substrate 10 is preferably part of a memory array for a memory device 9. Memory device 9 may be any memory device having a floating gate structure. In a preferred embodiment, device 9 includes a flash memory device, such as for example, an electrically erasable nonvolatile memory. Other programmable memories are also contemplated. The fabrication of a 4F 2 area memory cell will be illustratively described to demonstrate one aspect of the present invention. Dimension arrows " D" will be indicated throughout the views to illustratively demonstrate a groundrule dimension or minimum feature size dimension F. Each double-headed arrow D will indicate F. Of course, other memory cell areas may be realized in accordance with the present invention. Referring to FIGS. 16 and 17, before the formation of diffusion regions 13 of FIG. 15, substrate 10 is subjected to an oxidation process to form a pad oxide layer 14. Pad oxide 14 is covered by a dielectric layer 16, such as for example, a nitride layer (e.g., pad nitride) . A hardmask layer 15 is formed on layer 16 and patterned by lithography. Hardmask 15 is then employed to etch dielectric layer 16, pad oxide 14 and substrate 10 to form trenches 18, which extend longitudinally across at least a portion of device 9. Diffusion regions 13 are formed by a known implanting process (e.g., N-type dopant implant) . Diffusion regions 13 form source lines for vertical transistors, which extend longitudinally in accordance with trenches 18. The hardmask 15 is removed, and a buffer oxidation process is performed to form an oxide 20 on surfaces within trenches 18. Hardmask 15 and dielectric layer 14 are now removed. Referring to FIG. 18, active area doping is now performed to form diffusion regions 34. A doping mask layer (not shown) is formed over device 9 and pattered to permit doping of substrate 10 between trenches 18. One or more known implantation processes may be employed to form diffusion regions 34, which will function as a drain for a vertical transistor as will be explained below. The doping mask layer is now removed. A dielectric layer 38 is formed on horizontal surfaces, preferably an oxide formed by a high density plasma (HDP) oxidation process, which preferentially forms on horizontal surfaces. Layer 38 may be referred to as a trench top oxide (TTO) . Vertical sidewalls of trenches 18 are oxidized to form a gate oxide 40 thereon. Trenches 18 are lined with a conductive material 42, preferably polysilicon, by a deposition process. A spacer etch process is performed to leave a spacer from material 42, which lines sidewalls of trench 18. A center region 44 does not include material 42. The spacer etch process includes an anisotropic etch process, such as reactive ion etching (RIE) . RIE is tuned to etch the thickness of the layer of conductive material 42 to thereby leave spacers (floating gate 52) . A dielectric layer 46 is deposited over exposed surfaces of material 42. Layer 46 will function as a capacitor dielectric between material 42 (which forms a floating gate in accordance with the invention) and a control gate 48. Layer 46 may include a nitride, such as silicon nitride and preferably a layer of ONO (silicon oxide, silicon nitride, silicon oxide) . If ONO is employed, a thickness for layer 46 may be between 10 to 20 nm. A conductive material 50' is deposited over layer 46. Material 50 preferably includes polysilicon. Material 50 is planarized (e.g., by CMP) down to layer 38 (or layer 46) . Material 50 forms a control gate 48. Control gate 48 and floating gate 52 function as capacitor plates separated by layer 46. Referring to FIGS. 19 and 20, a top view of the memory array of device 9 is shown in FIG. 19 after planarization of material 50. Floating gates 52 and control gates 48 extend longitudinally along direction "A" on device 9. FIG. 20 shows a cross-sectional view of a section indicated in FIG. 19, which is perpendicular to the section of FIG. 18. Referring to FIGS. 21, 22 and 23, a dielectric layer 26, for example a nitride layer, is deposited and patterned by employing a hardmask (e.g., a TEOS hardmask) and a lithographic process (not shown) . Layer 26 is not shown in FIG. 21, for clarity. Isolation trenches 28 are etched in accordance with the hardmask employed to pattern layer 26. Isolation trenches 28 are preferably etched by an anisotropic etching process, such as for example, reactive ion etching. The hardmask is removed, and a dielectric material 30 is deposited to fill trenches 28. Dielectric material 30 may include an oxide, and preferably, a high density plasma (HDP) deposited oxide. A CMP process is performed to planarize dielectric material 30 down to dielectric layer 26, and trench isolation regions 32 are formed. In one illustrative embodiment, the memory array is processed along with a support region (not shown) . A silicon nitride liner (not shown) is formed over device 9. The array region and support region are masked. The support region mask is opened followed by support processing (e.g., sacrificial oxidation, implants, gate oxidation, polysilicon deposition and/or other known processes) . After processing the support region, the polysilicon layer employed in processing the support region is removed from the array region followed by deglazing liner 54 (see e.g., FIG. 9A) and the removal of liner 54 from the array region. Referring to FIG. 24, a gate stack 60 is formed by depositing and patterning a conductive layer or conductive layers in electrical contact with control gate 48. A layer 62 may include polysilicon (e.g., heavily doped) and a high conductivity layer 64 (e.g., Tungsten, Tungsten suicide, or other highly conductive material) . A dielectric cap 66 and spacers 68, preferably formed from silicon nitride, are provided to isolate gate stack 60 from contacts 70. Contacts 70 are formed through a dielectric layer 72, which may be formed from silicon dioxide. Holes for contacts 70 need to be formed through dielectric layer 72, layer 46 and layer 38 to make contact to diffusion region 34. A conductive line 74 is formed to provide access to a vertical transistor 76. When gate stack 60 (wordline) is activated conduction is achieved through transistor 76 between diffusion region 13 and line 74. This process provides a high capacitive coupling between control gate 48 and a vertical floating gate 52, and provides a more uniform gate structure across device 9. Transistor 76 is created along the side of trenches 18 in substrate 10. In the illustrative embodiment described, the source junction (13) is implanted through the trench bottom and creates a buried conductive path across the array. The floating gate 52 is created by deposition and a spacer etch, forming a spacer structure in the trench. The control gate 48 is deposited after dielectric layer 46 deposition on floating gate 52 and provides electrical contact to the wordline (gate stack 60) . The drain junction (34) is formed by an implantation step at the active area surface and is connected to line 74 (e.g., bit line) through contacts 70. Advantageously, in the illustrative embodiment, each contact 70 (and drain region 34) services two adjacent memory cells. The surface area between gates 48 and 52 is increased by at least one order of magnitude over conventional floating gates, which typically occupy IF 2 in area. Advantageously, the surface area between gates 48 and 52 occupies a three dimensional space in a conical or cylindrical configuration. This configuration can extend deep into substrate 10 and is virtually unlimited in terms of surface area between gates 48 and 52. Referring to FIGS. 25 and 26, a top layout (FIG. 25) of device 9 is schematically shown with layer 72 and line 74 not shown for clarity. Note that arrows "D" indicate a 4F 2 or less area memory cell in accordance with the invention. The present invention provides a substantial increase in floating gate to control gate surface area while maintaining a small (e.g., 4F 2 or less) memory cell area. The gate structure occupies a layout area equal to the layout area occupied by the trench; however, the contact gate and the floating gate have a common surface area of greater than about F 2 . FIG. 26 shows a cross- section taken along the direction of section line 26-26 in FIG. 25. Having described preferred embodiments for memory cell with vertical floating gate transistor (which are intended to be illustrative and not limiting) , it, is noted that modifications and variations can be made by persons skilled in the art in light of the above teachings. It is therefore to be understood that changes may be made in the particular embodiments of the invention disclosed which are within the scope and spirit of the invention as outlined by the appended claims. Having thus described the invention with the details and particularity required by the patent laws, what is claimed and desired protected by Letters Patent is set forth in the appended claims.

Claims: WHAT IS CLAIMED IS: 1. A method for fabricating a semiconductor device, comprising the steps of: forming a trench in a semiconductor substrate; depositing a first conductive material in the trench; etching the first conductive material in the trench to remove a portion of the first conductive material such that the first conductive material includes vertically disposed interior surfaces and remains in contact with sidewalls of the trench to form a floating gate conductor; depositing a dielectric layer over the interior surfaces of the first conductive material; and depositing a second conductive material over the dielectric layer to fill the trench to form a control gate conductor for capacitively coupling to the floating gate conductor. 2. The method as recited in claim 1, wherein the interior surfaces of the first conductive material include a circular cross-section in a plane parallel to a major surface of the substrate. 3. The method as recited in claim 1, wherein the interior surfaces of the first conductive material include a rectangular cross-section in a plane parallel to a major surface of the substrate . 4. The method as recited in claim 1, wherein the step of etching includes performing a spacer etch to remove the portion of the first conductive material . 5. The method as recited in claim 1, wherein the step of depositing a dielectric layer includes depositing a dielectric layer including ONO. 6. The method as recited in claim 1, further comprising the step of forming a gate oxide on the sidewalls of the trench. 7. The method as recited in claim 1, wherein a vertical transistor channel is formed in the substrate adjacent to the trench and further comprising the step of forming a gate oxide on the sidewalls of the trench such that when the floating gate is activated conduction occurs through the channel . 8. The method as recited in claim 1, further comprising the step of forming a wordline in electrical contact with the control gate conductor. 9. A semiconductor device, comprising: a substrate having a trench formed therein; a gate structure for a vertical transistor formed adjacent to a sidewall of the trench, further including: a floating gate conductor formed in contact with sidewalls of the trench and forming a void in a center portion of the floating gate conductor, the center portion having vertically disposed surfaces; a dielectric layer lining the void in the center portion of the floating gate conductor; and a control gate conductor formed in contact with the dielectric layer and filling the void in the center portion of the floating gate conductor. 10. The device as recited in claim 9, wherein the trench includes a gate dielectric formed on the sidewalls thereof. 11. The device as recited in claim 9, wherein the vertical transistor includes a vertical channel disposed adjacent to the trench, the vertical channel conducting when activated by the floating gate conductor. 12. The device as recited in claim 11, wherein the vertical channel connects a source region to a vertically offset drain region when activated by the floating gate conductor. 13. The device as recited in claim 12, wherein one of the source region and the drain region are connected to a bit line by a contact. 14. The device as recited in claim 13, wherein the one of the source region and the drain region and the contact are shared by two adjacent vertical transistors. 15. The device as recited in claim 9, wherein the control gate conductor is electrically connected to a wordline . 16. The device as recited in claim 9, wherein the floating gate conductor includes a circular cross-section in a plane parallel to a major surface of the substrate. _17. The device as recited in claim 9, wherein the floating gate conductor includes a rectangular cross-section in a plane parallel to a major surface of the substrate. 18. A semiconductor device, comprising: a substrate having a trench formed therein; a gate structure for a vertical transistor formed adjacent to a sidewall of the trench, the gate structure occupying a layout area including one of a length or width of a groundrule size, F, the gate structure further including: a floating gate conductor formed in the trench in contact with sidewalls of the trench and forming a void in a center portion of the floating gate conductor, the center portion having vertically disposed surfaces; a dielectric layer lining the void in the center portion of the floating gate conductor; and a control gate conductor formed in contact with the dielectric layer and filling the void in the center portion of the floating gate conductor such that a surface area between the control gate and the floating gate is greater than F 2 . 19. The device as recited in claim 18, wherein the trench includes a gate dielectric formed on the sidewalls thereof . 20. The device as recited in claim 18, wherein the vertical transistor includes a vertical channel disposed adjacent to the trench, the vertical channel conducting when activated by the floating gate conductor. 21. The device as recited in claim 20, wherein the vertical channel connects a source region to a vertically offset drain region when activated by the floating gate conductor. 22. The device as recited in claim 21, wherein one of the source region and the drain region are connected to a bit line by a contact. 23. The device as recited in claim 22, wherein the one of the source region and the drain region and the contact are shared by two adjacent vertical transistors. 24. The device as recited in claim 18, wherein the control gate conductor is electrically connected to a wordline. 25. The device as recited in claim 18, wherein the floating gate conductor includes a circular cross-section in a plane parallel to a major surface of the substrate. 26. The device as recited in claim 18, wherein the floating gate conductor includes a rectangular cross-section in a plane parallel to a major surface of the substrate. 27. The device as recited in claim 18, wherein the gate structure occupies a layout area including both a length and width of a groundrule size, F. 28. The device as recited in claim 18, wherein a memory cell, which includes the gate structure, occupies a layout area of 4F 2 . 29. The device as recited in claim 18, wherein the gate structure occupies a layout area equal to a layout area occupied by the trench such that the contact gate and the floating gate have a common surface area of greater than about F 2 .

Inventors: CASAROTTO DANIELE, CASAROTTO, DANIELE
Applicants: INFINEON TECHNOLOGIES CORP, INFINEON TECHNOLOGIES NORTH AMERICA CORP.
Application year: 2001
Main classification: H01L21
IPC codes: H01L21, H01L27, H01L29