MULTIPATH PARAMETER ESTIMATION IN SPREAD-SPECTRUM COMMUNICATIONS SYSTEMS

Abstract: A training circuit includes resources for processing magnitude and phase information received in a main propagation path signal with magnitude and phase information concurrently received in a secondary propagation path signal to determine values for magnitude, phase, and time offset of the secondary propagation path signal relative to the main propagation path signal. Differential decoding circuitry within the training circuit provides a correlation circuit, also in the training circuit, with differentially decoded sequences of symbol phase values derived from concurrent main and secondary signal propagation path symbol phase value sequences provided to the training circuit by an associated communications receiver. Operating on these phase value sequences, the correlation circuit determines the time offset between the main and secondary propagation path signals based on determining he correspondence between symbol phase values received via the main propagation path signal and those concurrently received via the secondary propagation path signal. The training circuit can identify time offsets less than or greater than a symbol period, for either leading or lagging secondary path time offsets. A phase difference circuit, further included in the training circuit, determines a phase offset for the secondary propagation path signal relative to the main propagation path signal using main and secondary propagation path symbol phase values in combination with the time offset information. The relative magnitude, phase, and time information represents a characterization of the secondary propagation path with respect to the main propagation path. This characterization information may be used to improve reception performance or cancel multipath interference.

Description: MULTIPATH PARAMETER ESTIMATION IN SPREAD-SPECTRUM COMMUNICATIONS SYSTEMS Field of the Invention The present invention generally relates to direct-sequence spread spectrum (DSSS) communications systems, and particularly relates to characterizing multipath propagation characteristics in DSSS receivers. Background of the Invention In wireless communications systems, successfully extracting transmitted information from a received signal oftentimes requires overcoming significant levels of interference. Multipath interference represents one type of received signal interference that can be particularly problematic in certain types of wireless communications systems. For example, wireless LANs are typically employed in indoor environments that commonly include partitioned walls, furniture, and multiple doorways, along with various metallic and non-metallic building features. In these environments, transmitted signals follow multiple transmission paths of differing lengths and attenuation. Consequently, a receiver in such an environment receives multiple, time-offset signals of differing signal strengths. These multiple versions of the same transmit signal are termed "multipath signals." The effect of multipath signals on DSSS receiver performance depends upon the particulars of the communications system in question. For example, in certain types of DSSS communications systems, multipath signals can actually improve receiver signal- to-noise ratio. To understand this phenomenon, it is helpful to highlight a few basic aspects of DSSS commumcations. DSSS transmitters essentially multiply an information signal by a pseudo-noise (PN) signal — a repeating, pseudo-random digital sequence. Initially, the information signal is spread with the PN signal, and the resultant spread signal is multiplied with the RF carrier, creating a wide bandwidth transmit signal. In the general case, a receiver de-spreads the received signal by multiplying (mixing) the incoming signal with the same PN-spread carrier signal. The receiver's output signal has a maximum magnitude when the PN-spread signal exactly matches the mcoming received signal. In DSSS systems, "matching" is evaluated based on correlating the incoming PN-sequenced signal with the receiver's locally generated PN-sequenced signal. The spreading code (PN code) used by the transmitter to spread the information signal significantly influences the effects of multipath signals on receiver performance. DSSS transmissions based on a single spreading code with good autocorrelation properties (or on a small set of orthogonal spreading codes) allow the receiver to selectively de-correlate individual signals within a multipath signal relatively free of interference from the other signals within the multipath signal. By adjusting the PN- sequence offset used to generate its local PN despreading signal, the receiver can time- align (code phase) its despreading circuitry with any one of the multipath signals it is receiving. If the spreading/despreading PN code has good autocorrelation and cross- correlation properties, the receiver can recover the transmitted data from any one of these multipath signals without undue interference. Of course, it may be preferable to use only the strongest multipath signal(s) for information recovery. Indeed, conventional RAKE receivers used in Code-Division Multiple Access (CDMA) digital cellular telephone systems exploit the above situation. CDMA transmissions use a relatively long, fixed spreading code for a given receiver and transmitter pair, which results in very favorable auto- and cross-correlation characteristics. RAKE receivers are well known in the art of digital cellular receiver design. A RAKE receiver includes multiple, parallel 'TtAKE fingers." Each RAKE finger can independently synchronize with and de-spread a received signal. By synchronizing the multiple RAKE fingers to the sfrongest received multipath signals (those with the highest correlation values), the RAKE fingers lock on to the sfrongest multipath signals. Because of the excellent correlation properties of the CDMA spreading codes, each RAKE finger synchronizes with and de-spreads one of the multipath signals relatively free from interference associated with the other multipath signals. Thus, each RAKE finger de-spreads a relatively clean signal and this allows the overall RAKE receiver to coherently combine (with time/phase alignment) the signals to form a combined output signal that represents the addition of the multipath signals. Coherently combining the multipath signals allows the RAKE receiver to achieve an improvement in signal-to-noise ratio (SNR), essentially meaning that multipath signals can actually improve reception performance in certain types of spread spectrum systems. Unfortunately, the characteristics of many other types of spread spectrum communications systems greatly complicate how a receiver deals with multipath signals. Some types of DSSS systems use spreading codes with poor correlation properties. The IEEE standard for high data-rate wireless LANs, known as 802.1 lb, is a primary example of such a system. Standard IEEE 802.11 transmissions use a single spreading code combined with binary phase-shift keying (BPSK) or quadrature phase-shift keying (QPSK) to transmit data at 1 or 2 Mbps, respectively. The 802.1 lb extensions provide higher data rates by defining 5.5 and 11 Mbps transmission rates. These higher data rates use a modulation format known as Complimentary Code Keying (CCK). 802.1 lb CCK- mode fransmissions use multiple spreading codes, and the spreading codes change across symbols. While providing the ability to achieve high data transfer rates and still maintain compatibility with the standard 802.11 1 and 2 Mbps channelization scheme, CCK modulation does include the drawback of making it more difficult for receivers to cleanly despread individual multipath signals. Indeed, due to the relatively poor correlation properties of the spreading codes used in 802.1 lb, the various multipath signals can interfere with each other and result in inter-symbol interference (ISI) at the receiver. Thus, in contrast to the CDMA digital cellular scenario, multipath signals can significantly degrade receiver performance in systems operating under 802.1 lb standards. Of course, multipath signals may be problematic in any type of DSSS system that uses less-than-ideal spreading codes, so the problem is not limited to wireless LAN applications. Multipath interference in DSSS systems arises from both inter-chip interference (ICI) and ISI. For the purposes of this disclosure the term ISI is understood to include both ICI and ISI. From the perspective of a DSSS receiver, each transmitted symbol results in the reception of multiple symbols arriving with relative time offsets from each other, due to the multiple signal propagation paths between receiver and transmitter. ISI, as used herein, describes multipath interference arising from these multiple received symbols and can include interference arising from multipath signal delay spreads exceeding one symbol period. In DSSS systems where the spreading code(s) do not allow multipath signals to be individually despread without interference, RAKE receiver techniques are not applicable. The basis of RAKE receiver operation assumes that each RAKE finger can cleanly despread a selected multipath signal, which is subsequently combined with the output from other RAKE fingers to form an overall RAKE receiver output signal. If the output from the individual RAKE fingers is corrupted by multipath interference, the combined signal will be compromised and RAKE receiver performance suffers. Channel equalization offers a potential opportunity for improving receiver performance in a multipath channel. Unfortunately, conventional channel equalization techniques are not suitable for DSSS transmissions due to complexity. For any radio frequency channel, the term "channel-coherent bandwidth" describes the portion of a given channel's available bandwidth where a relatively flat frequency response may be observed. Typically, only a small portion of a wideband DSSS channel may exhibit a flat frequency response. Consequently, existing equalizers exploiting conventional digital filtering techniques are inappropriate for compensating a wideband DSSS channel for multipath interference. This inappropriateness results from the sheer complexity associated with implementing and training a conventional digital filter having a finite number of filter taps and corresponding filter coefficients that is capable of compensating the received signal for the complex frequency response of a wideband DSSS radio channel. Existing approaches to DSSS receiver design do not adequately address multipath interference in systems where individual multipath signals cannot be despread relatively free of interference. As noted, these types of systems are typically based on less-than- ideal spreading codes, with IEEE 802.11b representing an example of such systems. Without the ability to handle multipath interference, such systems cannot reHably operate in environments with significant multipath interference. Existing approaches, including the use of RAKE receivers or conventional channel equalizers are either inappropriate or impractical. Effective handling of multipath signals, whether for the purpose of interference compensation, such as in 802.11b environments, or for the purpose of coherent multipath signal combination, such as in RAKE receiver operations, depends upon developing accurate estimates of propagation path characteristics for one or more of the secondary propagation path signals included in the received signal. Under many real world conditions, the delay spread among the individual propagation path signals comprising a received multipath signal exceeds one symbol time, meaning that, at any one instant in time, the various propagation path signals may represent different information values (symbol values), making it potentially difficult to relate one propagation path signal to another. Without this ability, only multipath signals with propagation path delay spreads less than a symbol time may be processed substantially free from interference. Thus, there remains a need for a method a d supporting apparatus for identifying and characterizing secondary signal propagation paths relative to a main signal propagation path that accommodates a wide range of propagation path delay spreads, including delay spreads that exceed one symbol time. With the ability to determine time offsets between main and secondary signals over a range of less than to more than one symbol time, a communications receiver can accurately characterize secondary signal propagation paths relative to a main signal propagation path in variety of environments, even those with severe multipath conditions. Such a characterization method would allow for compensation of a received multipath signal in a broad range of radio signal propagation environments, even those with severe multipath conditions, thus enhancing communications receiver performance. This method and supporting apparatus would be particularly valuable in any type of DSSS communications system that relies on spreading techniques that do not intrinsically provide multipath interference rejection, but would also be valuable in any DSSS communications system subject to multipath signal reception. Summary of the Invention The present invention includes an apparatus, referred to as a training circuit, for characterizing one or more secondary signal propagation paths relative to a main signal propagation path. Preferably, the training circuit of the present invention is included in an associated communications receiver that provides it with signals received via the main signal propagation path concurrently with a signal received via one of the secondary signal propagation paths. The training circuit accumulates magnitude samples from the main and secondary signals and uses them to compute a relative magnitude for the secondary signal. The training circuit also includes circuit resources for differentially decoding symbol values (phase values) received via the main and secondary signals, and correlation circuitry for determining secondary-to-main signal time offset using the differentially decoded symbol information. Additional resources within the training circuit compute possible phase offsets for the secondary signal relative to the main signal based on current and delayed symbol values, and supporting logic to identify a one of these possible phase offsets as being the closest-to-actual phase offset based on the time offset information. Thus, the training circuit provides time offset, magnitude, and phase information for a secondary propagation path signal relative to a main propagation path signal. The associated communications receiver may use information developed by the fraining circuit to improve multipath signal reception performance or cancel selected multipath interference arising from one or more of the secondary propagation path signals. By adopting the main path signal as the reference, an information symbol or fransmitted data item received through the main path signal may be considered to have an arrival time of t 0 , a phase of 0, and a magnitude of 1. A selected secondary path signal may then be concurrently compared to the main path signal to determine relative magnitude, phase, and arrival time, thereby characterizing the secondary signal propagation path parameters with respect to the main signal propagation path. Indeed, in exemplary embodiments, the associated communications receiver provides the training circuit with sequences of magmtude and phase values from the main path signal and a selected secondary path signal for a period of time sufficient to allow characterization of the selected secondary path signal. The communications receiver may repeat this operation for one or more additional secondary path signals. Preferably, the training circuit includes integrators that integrate several successive magnitude samples from the main path signal and the currently selected secondary path signal. A comparison function uses these integrated magnitudes to determine a ratio for the magmtude of the secondary path signal relative to the main path signal. Since the main path signal is, preferably, the strongest signal, this relative magnitude is a fractional value. Other embodiments of the fraining circuit may implement other techniques for accumulating magmtude samples, and the number of magnitude samples accumulated will vary with design and performance requirements. There is a two-fold problem associated with determining the time and phase offset for the secondary signal relative to the main path signal: (1) the secondary signal has some unknown phase shift relative to the main signal; and (2) the secondary signal may be offset from the main signal by more or less than one symbol period, in either a leading or lagging fashion. To ehminate the secondary signal phase shift, the training circuit includes differential decoders for the main and secondary signals. Differentially decoded symbol values (phase values) are processed by correlation circuitry included in the fraining circuit. Correlation operations identify the correspondence between symbols in a sequence of symbols received via the main path and symbols in a sequence of symbols concurrently received via the secondary path. Corresponding main and secondary path symbols values will have a minimum phase difference and, thus, a maximum correlation. Once the symbol correspondence is known, the fraining circuit can infer the time offset between the main and secondary path signal. Additional circuitry within the training circuit, disposed in advance of the aforementioned differential decoding circuitry, supports determining the phase offset or difference between the main and secondary signals. This circuitry computes the phase difference as the difference between current and delayed samples of the main and secondary signal symbol phase values. Since the secondary signal symbol phase values corresponding to the main signal symbol phase values may be offset by more or less than one symbol period, in either a leading or lagging fashion, the training circuit computes the phase difference between current and delayed main and secondary signal symbol phase values. The previously determined time offset value is used to select the appropriate phase difference value. Brief Description of Drawings Figure 1 illustrates a wireless commumcations environment subject to multipath signal reception. Figure 2A illustrates the influence of multiple propagation paths on a received signal. Figure 2B illustrates the problem of inter-symbol interference in a sequence of received symbols. Figure 3 illustrates an exemplary wireless networking system in which the present invention may be advantageously practiced. Figure 4 is a generahzed block diagram of an exemplary communications receiver used in the system of Figure 3. Figure 5 is a more detailed functional block diagram of the communications receiver of Figure 4. Figure 6 illustrates the structure of an IEEE 802.1 lb wireless LAN data packet. Figure 7A depicts time-offset main and secondary path received signal symbol sequences. Figure 7B provides exemplary details for a portion of the main and secondary path signal processing operations associated with the training method associated with the present invention. Figure 7C illustrates how an unknown secondary signal phase shift may be determined based on the operations shown in Figure 7B. Figure 8 is a simplified logic flow diagram for an exemplary embodiment of the training method associated with the present invention. Figure 9 A is a simplified block diagram of an exemplary embodiment of the training circuit of the present invention. Figure 9B is a more detailed diagram of the fraining circuit introduced in Figure 9A. Figure 10 is a generalized block diagram of an exemplary embodiment of a radio channel equalizer that may be advantageously used in conjunction with the present invention. Figure 11 is an alternate exemplary embodiment of the equalizer of Figure 10. Detailed Description of the Invention Figure 1 illustrates a wireless commumcations environment 10 subject to multipath interference. While Figure 1 depicts two PCs 20 in wireless communications with each other, as might be expected in a wireless LAN environment, the present invention may be advantageously applied in any DSSS communications systems subject to multipath interference. As illustrated, multipath signals arise from intervening obstacles between a fransmitter and a receiver — in this case, a transmitting PC 20 and a receiving PC 20. While not explicitly illustrated in Figure 1, it will be readily appreciated that the multipath signals received by the receiving PC 20 may be subject to differing levels of attenuation and phase shifting based on the specific signal path followed by each signal. In the context of this disclosure, the main path signal is not necessarily the signal following the most direct route to the receiver; rather it is the strongest of the received multipath signals. Because the multipath signals follow different signal paths of differing lengths, the various signals received by the receiver are subject to time dispersion. That is, the multipath signals are offset from one another by an amount of time proportionate to the difference in signal path length. Figure 2A illustrates this time dispersion phenomenon. In Figure 2A, the upper and lower horizontal time axes are aligned. An ideahzed impulse signal represents the transmitted data. Although the transmitter outputs a single clean impulse, the receiver actually receives multiple impulses at different times, with different amplitudes and phase due to multipath. The received signal with the largest amplitude is deemed the main path signal, denoted by "M" in Figure 2A. The remaining, weaker signals are deemed echo or secondary multipath signals, and are denoted as Eι..E 3 . Exemplary fraining method embodiments provide support characterization and subsequent cancellation for the two strongest secondary signals, while ignoring the weaker, remaining echo signals. In the context of Figure 2 A, the two sfrongest echo signals are E 2 and Ei. Note that the training method may be varied to characterize any number of secondary signals. Reception performance requirements and processing time limitations are considerations in choosing the number of secondary signals (echo signals) that will be characterized. In DSSS systems, information is transmitted from a transmitter to a receiver as a series of chips, with a defined number of chips forming a symbol. Each symbol corresponds to one or more known binary values. Thus, by decoding the received symbols, the receiver can re-create the binary data sent by the transmitter. Of course, to -■• successfully decode these symbols, the receiver must synchronize with the transmitter's chip and symbol timing. Figure 2B illustrates a sequence of received signals over at least two symbol times (Ts). What is not immediately apparent from Figure 2B is whether one or more multipath events (echo signals) within a given symbol's time slot arises from the current symbol's transmission or from transmission of the previous symbol. Without the ability to make this determination, ISI cannot be effectively mitigated. The apparatus and associated fraining method of the present invention enables identifying and characterizing multipath events with time offsets that may exceed one or more symbol times and, thus, provides methods for identifying and compensating for ISI. Figure 3 depicts an exemplary PC-based wireless LAN environment in which the various aspects of the present invention may be advantageously practiced. PCs 20 communicate with one another via wireless signaling, transmitting and receiving signals through antennae 26. Each PC 20 includes an exemplary communications receiver 100 supporting the multipath propagation parameter training operations of the present invention, a compatible transmitter 24, and supporting circuitry 22. Figure 3 is not meant as a depiction of actual structure for the inter-organization of PC 20; rather, Figure 3 provides a functional depiction for the inclusion of the communications receiver 100 within a typical wireless LAN environment. The PCs 20 send and receive information via transmitters 24 and communications receivers 100, respectively. Such communications may be peer-to-peer (between PCs), or may be routed through a hub or server equipped with a wireless interface. The actual network organization and hierarchical structure used in a given appHcation is not important with respect to understanding the present invention. Ideally, the communications receiver 100 is implemented as single integrated circuit, including portions supporting programmed operation, but may be implemented as a cooperative collection of integrated circuit devices collectively supporting the same functionahty. Exemplary embodiments of the communications receiver 100 support the training operations of the present invention and the channel equaUzation (multipath interference cancellation) methods detailed herein. Figure 4 provides a more detailed illustration of the communications receiver 100 introduced in Figure 3. The communications receiver 100 includes a conditioning and conversion circuit 110, a carrier recovery circuit 120, an equalizer 130, a despreading circuit 140, a baseband processing circuit 170 including a fraining circuit 200 (shown in Figure 5), and additional supporting logic 160. Signals received through antenna 26 pass through the conditioning and conversion circuit 110, where they are filtered, optionally amphfied, and converted from analog to digital format. Digital information then passes to the carrier recovery circuit 120. The carrier recovery circuit 120 maps received symbols in the main path signal to one of the ideal constellation points defined by the transmit signal modulation scheme. For example, QPSK-modulated symbols map to one of the 4 defined constellation points, namely +/-1 and +/- j. Output from the carrier recovery circuit 120 passes to the equahzer 130 that is preferably included in the communications receiver 100. In order for the equalizer 130 to effectively cancel selected multipath interference from the received multipath signal, the communications receiver 100 must properly configure the equalizer 130 based on multipath propagation parameter fraining. This configuration entails providing the equalizer 130 with a complex coefficient and corresponding delay information for each secondary path to be canceled from the received signal. The complex path coefficient represents a learned model of propagation path parameters for a given secondary path, while the delay information represents the arrival delay of the given secondary path relative to the main path signal arrival time. The training circuit 200 of the present invention, shown within baseband processor 170 (Figure 5), and discussed in detail later, represents an exemplary circuit for practicing the fraining method of the present invention. Some types of communication systems may implement different fraining circuit architectures, depending upon signal characteristics and design requirements. Once configured, the equahzer 130 compensates the main path signal for multipath interference caused by the secondary signals. The compensated output from the equalizer 130 then passes to the despreading circuit 140, where signal correlation operations provide the baseband processor 170 with despread, received signal samples. Baseband processor 170 extracts the received data from these received signal samples. Figure 5 provides more details of the communications receiver 100 shown in Figure 4. The conditioning/conversion block 110 includes a receiver front-end circuit, analog-to-digital converter, and a digital low-pass filter. The despreading circuit 140 includes four sets of despreading circuits, including a "main path" despreading circuit that includes a multiplier 142B, an integrator 144B, a coordinate translator 146B, and a phase sheer 148. Additional multipliers 142A and 142C in combination with integrators 144A and 144C and coordinate translators 146A and 146C, comprise "early" and "late" despreading circuits, respectively. Multiplier 142D, integrator 144D, and coordinate translator 146D combine to form a "secondary path" despreading circuit. The supporting logic circuit 160 includes amodulo-N counter 162, a set of offset adders 164A..D and a corresponding set of PN sequence look-up tables (LUTs) 166A..D. The supporting logic 160 also includes additional logic resources 168. A baseband processor 170 includes a fraining circuit 200 that is used to determine the secondary path propagation parameters that permit the equahzer 130 to cancel multipath interference in the received signal. Generally, the received signal coming into the conditioning/conversion circuit 110 comprises both in-phase (I) and quadrature (Q) signals. These signals may be filtered and/or buffered in a front-end circuit before being converted from analog format into digitized I and Q sample streams by analog-to-digital converters. Subsequent to digital conversion, the I and Q samples may be low-pass filtered before leaving the conditioning/conversion circuit 110. The carrier recovery circuit 120 corrects for carrier frequency error, as previously described, and passes the digitized samples on to the equalizer 130. As will be discussed in more detail later, the equalizer 130 compensates the received signal samples for multipath interference once it has been properly configured. In learning secondary path parameters, exemplary embodiments of the training circuit 200 operate on the main path received signal and selected secondary path signals. Thus, the despreading circuit 140 is required to provide the training circuit 200 with one despread signal that is synchronized with the phase of the main path signal and one despread signal that is synchronized to the phase, of a selected secondary path signal. These input signals represent successive sample values of magnitude and phase for the main path and selected secondary path signal. Therefore, while not critical to practicing the present invention, an understanding of the exemplary despreading circuit 140 illustrated in Figure 5 is helpful in understanding how the secondary path propagation parameters are learned using training circuit 200. Note that the fraining circuit 200 of the present invention may be practiced with any type of supporting circuit or system capable of providing magnitude and phase information for a main and secondary path signal. As explained earlier, DSSS receivers despread received signals using the same PN sequence that was used by a corresponding transmitter to spread the original narrowband information signal. For maximum correlation, the receiver's progression through the PN sequence must be exactly synchronized with the transmitter's PN sequence progression. That is, the instantaneous PN sequence value at the receiver must exactly match that of the transmitter for maximum correlation response. The modulo-N counter 162 — hich is a Modulo-44 counter in exemplary embodiments — included in supporting logic 160 '* provides a repeating count sequence used to sequentially select values from memory- based PN sequence look-up-tables (LUTs) 166A..166D. The output PN sequences (PNE, PN M , PN L , and PNs) provided to the despreadmg circuit 140 are all based on a commonly selected PN sequence, but may have differing sequence offsets based on their respective index offset values (OFFSET E , OFFSET M , OFFSET L , and OFFSET* ? ) signals feeding the offset multipHers 164A..164D. With the above information in mind, the set of four multipliers (correlators) 142A..142D in the despreading circuit 140 are capable of despreading the received signal with up to four different despreading phases. In operation, the communications receiver 100 configures the supporting logic 1 0 such that OFFSET M sets the sequence offset of the "on-time" or main path sequence (PN M ) supplied to the multipHer 142B such that it is synchronized with the main path signal. This allows the despreading circuit 140 to provide the training circuit 200 with magmtude samples ΓM and phase samples ΘM corresponding to the main path signal. The communications receiver 100 adjusts the PN sequence offsets of PN E and PN L (OFFSET E and OFFSET L ) such that mult phers 142A and 142C despread the received signal with PN sequences adjusted to have a phase slightly earlier and " slightly later than the main path PN sequence phase, respectively. However, these operations relate to maintaining synchronization with the main path signal, rather than to practicing the present invention and are not further detailed herein. In estimating secondary propagation path parameters for each of the secondary path signal of interest, the OFFSETs value is adjusted to synchronize the secondary path despreading circuitry in the despreading circuit 140 with selected ones of the secondary propagation path signals. This allows the communications receiver 100 to control the despreading circuit 140 to provide the fraining circuit 200 with magnitude and phase samples of the received signal synchronized, at different times during training, to each one of the secondary path signals for which cancellation is desired. In 802.11b applications, the commumcations receiver 100 uses the training circuit 200 of the present invention and equalizer 130 to provide multipath interference cancellation in CCK-modulated received signals conforming to IEEE 802.1 lb standards. Understanding the structure of an 802.1 lb data packet is helpful in understanding exemplary fraining and cancellation operations. Figure 6 illustrates the structure of an 802.1 lb data packet. 802.1 lb data packets comprise a preamble, a header, and .a data payload. In standard 802.11 data packets, the preamble is transmitted at 1 Mbps using BPSK, while the header and payload may be transmitted at either 1 Mbps or 2 Mbps. At 2 Mbps, QPSK is used rather than BPSK. In 802.1 lb, modulation of the header and preamble remain the same, but the data payload is transmitted at 5.5 Mbps or 11 Mbps, with CCK modulation used in both cases. In general, channel estimation may be supervised (both transmitted data and spreading code are known), blind (both transmitting data and spreading code are unknown), or semi-blind (spreading code is known but data is unknown). As one might guess, blind estimation represents the most difficult approach, while supervised estimation is the most straightforward. For 802.11b applications, the present invention adopts semi-blind fraining techniques (based on the known spreading code apphed to 802.1 lb preambles and headers) to develop appropriate coefficients for the equalizer 130. The fixed spreading sequence appHed to the preamble and header has good correlation properties that allow conventional 802.11 receivers to despread one or more path signals within a multipath signal arising from the transmission of the preamble and header without substantial interference from the other multipath signals, regardless of whether 802.11 or 802.1 lb is being used. This means that multipath cancellation (channel equalization) is typically not required during reception of the preamble and header portion of an 802.1 lb data packet. This allows the communications receiver 100 to characterize the secondary propagation paths' influence on the transmitted signal during the 802.1 lb preamble and header. This information is then used to configure the equahzer 130 to provide channel equalization during the CCK-modulated 802.11b payload, where multipath signal cancellation becomes necessary to avoid interference. In other words, the communications receiver 100 uses the fraining circuit 200 and associated method during the preamble and header portion of each 802. l ib data packet, taking advantage of the good correlation properties of the known spreading code appHed to the preamble and header, to learn the multipath channel conditions prevailing for the current 802.1 lb data packet. During the preamble and header, the equalizer 130 is turned off - set to a flat frequency response - and then updated with the newly learned parameters for the current 802.1 lb packet. As applied in 802.1 lb systems, training is such that path parameters for the major secondary path signals can be learned based on processing a relatively small number of received symbols — fewer than are contained in the standardized preamble and header. This allows the communications receiver 100 to determine the required path parameters and configure and then enable the equalizer 130 for active cancellation before the start of the high data rate 802.1 lb payload portion of the data packet. The information provided to equalizer 130 for secondary signal cancellation is derived and updated during fraining, and then held fixed during the 802.1 lb packet payload. In short, the equahzer 130 is disabled during the preamble and header (while fraining is active) and then updated and enabled prior to the payload, and this action is repeated for each successive 802.1 lb data packet. In communications systems, equalizers function essentially as filters that are tuned to the response of the radio channel. In a preferred system, the equalizer 130 produces estimates of the significant multipath reflections (secondary signals) of the main path signal based on learned propagation characteristics (magnitude, phase, and delay) for the secondary propagation paths associated with the radio channel. These reflection estimates are subtracted from the received signal, thereby providing cancellation of selected multipath signals included in received signal. The fraining method detailed herein provides an advantageous technique for developing these secondary propagation path characteristics. Ideally, a radio channel has a flat frequency response, meaning that it passes all frequencies of interest with uniform attenuation and phase shift. In reality, radio channels seldom exhibit this ideal behavior. Before fraining, equalizer 130 is simply turned off — or, equivalently, set to a flat frequency response. After synchronizing the main path circuitry (carrier recovery circuit 120 and the main path despreading correlator included in despreading circuitry 140) with the main path signal, the communications receiver 100 individually synchronizes its secondary path circuitry (including the secondary path correlator of the despreading circuitry 140) with the secondary path signals in the accommodated delay spread range, extending both before and after the arrival of the main path signal, to determine the strongest secondary path signals. Preferably, the communications receiver 100 incorporates circuit resources supporting the operation introduced in Figures 7A through 7C, and more greatly detailed in Figure 8. Figure 7A depicts a sequence of symbols (S-...SN) arriving at the commumcations receiver 100 via a main signal propagation path and a secondary signal propagation path. Each symbol block represents one symbol time or period, and the sequence of symbols received through the secondary path has an unknown delay relative to the sequence of symbols received via the main path. Secondary path delays may be less or more than one symbol period. In an actual multipath signal, some secondary signals will likely have delays falling within one symbol time of a given main path received symbol, while other secondary signals will have delays falling outside one symbol time. Figure 7B generally outlines fraining for a given secondary signal. In PSK transmission, symbols are conveyed using phase modulation. Thus, the numbers within the blocks comprising sequence 700 represents an exemplary sequence of ideally transmitted symbols (phase values). Note that these phase values are for illustration and may not correspond to phase values used in any actual PSK modulation scheme. The fransmitted sequence 700 is received by the communications receiver 100 through a main signal path as a main sequence 710, and through a secondary signal path as a secondary sequence 720. For convenience, the secondary sequence 720 is illustrated offset from the main sequence 710 by one symbol period, but may take on any offset value in practice. As received, the sequences 710 and 720 do not perfectly reflect the symbol phase values in transmitted sequence 700. While the main path symbols in sequence 710 are relatively close to the transmitted values in sequence 700, they exhibit some noise- induced differences. The secondary path symbols exhibit noise problems as well, but further exhibit a phase shift with respect to the main path symbols. As an example, sequence 720 is illustrated with a phase shift of approximately 30° with respect to sequence 710. So, for example, a transmitted symbol phase of 45° becomes 43° through the main path — due to noise — and, relative to the main path, becomes 76° through the secondary path — due to noise plus secondary path phase shift. For a given secondary signal path, this phase shift is essentially constant unless signal transmission conditions change. To determine the correspondence and, hence, the time offset between the main and secondary signal, the main path symbol phase values are first sliced or adjusted to their corresponding nominal phase values to form sequence 730, while the secondary path values are not modified. This removes phase noise from the individual main path samples. Since the phase values in the received secondary sequence 720 have an . unknown phase shift compared to the values in the received main path sequence 710, they are not yet shced. To remove this unknown phase shift, the secondary sequence 720 is differentially decoded to form the differential secondary sequence 750, and the sliced main sequence 730 is, for consistency, also differentially decoded to form the sliced, differential sequence 740. Once the unknown offset is removed, sequence 750 may be shced to remove individual sample phase noise to form the differential, shced secondary sequence 760. At this point, individual phase sample values in sequence 740 may be compared with phase samples in sequence 760 to identify which phase sample in the secondary sequence 760 corresponds with which phase sample in the main sequence 740. As illustrated, corresponding values are shown in bold. Based on identifying this correspondence, training may then determine the path delay and phase shift for the secondary signal being processed. As shown, current main sequence values are compared to current and preceding secondary sequence values, and current secondary sequence values are compared with preceding main sequence values. As shown, these correlation operations are limited to adjacent symbols, but may be extended across additional symbols. Once main and secondary path symbol correspondence is determined, as explained above, the unknown phase shift of the secondary path relative to the main path may be determined. Here, differential decoding is not used, so that the secondary path phase shift is preserved. Operating on sliced received main path symbol phase values and un-sliced secondary path symbol phase values (sequences 730 and 720, respectively, in Figure 7B), the training method subtracts a preceding secondary phase value from a current main phase value, a current secondary phase value from the current main phase value, and the current secondary phase value from a preceding main phase value. Only one of these differences represents the actual phase shift of the secondary signal relative to the main signal. In the example outlined in Figure 7B, the current secondary phase value corresponds with the preceding main phase value. Figure 7C illustrates that the difference between the preceding main phase value and the current secondary phase values represents an estimate of the actual secondary-to-main phase shift. Of course, the range of main and secondary symbols used in the operations outlined in Figures 7B and 7C may be varied as needed to cover a broader range of delays. Figure 8 broadly presents an exemplary embodiment of the fraining method. The general process includes identifying the main propagation path signal and major (strongest) secondary propagation path signals, and learning propagation path characteristics for the secondary signals of interest, relative to the main propagation path signal. In the context of the communications receiver 100, this assumes the carrier recovery circuit 120 and despreading circuits 140 have performed initial synchronization with transmitted symbols received via the main path signal and continue tracking the main path signal during operation. Synchronization and tracking may be accomplished in a number of ways, and the specifics of how these are accomplished are not critical to understanding the fraining process. In this sense, however, Figure 8 may be a simplification of the overall operating logic implemented in the communications receiver 100. Indeed, the communications receiver 100 may execute the logic outlined in Figure 8 in the context of larger, more complex operating algorithms, and may represent operating logic executed concurrently with other operations. Processing begins (block 810) with the assumption that a received signal sample stream synchronized with the main propagation path symbol timing and phase is available, this is referred to as the main path signal. Further, a received signal sample stream that may be selectively synchronized with individual secondary propagation path signals is also assumed available, and this is referred to as the secondary path signal. In exemplary embodiments, the secondary path signal is adjusted to "scan" over an entire spreading code phase range to identify secondary path signals — this process may be thought of as a "course" search. This may be done at various resolutions, with an exemplary embodiment adopting a secondary path phase step equal to 1/2 chip resolution. Thus, in exemplary embodiments, circuitry supporting the despreading of secondary path signals is adjusted to an initial PN code phase offset index (block 812). The secondary path signal magmtude and PN code phase offset index for this initial setting are stored (block 814), and the PN code phase offset index is checked to insure that the code phase offset adjustment has not reached a maximum offset index value (block 816). The PN code phase offset is then adjusted such that secondary path despreading circuitry adopts the next PN code phase offset setting (block 818) and the secondary signal magnitude and PN code phase offset are stored for this phase setting. Blocks 814 to 818 are repeated for each PN code phase offset setting, until the maximum code phase offset setting is reached (block 816), at which point processing advances to a point where the N strongest secondary path signals are identified, where the sfrongest multipath signal is the main path signal (block 820). At this point, a set of multipath signal magnitudes exists, one for each corresponding phase offset index in the despreading PN sequence. These magnitude values correspond to individual signals contained in the received multipath signal, with each one representing the multipath signal being despread with a different phase index offset setting. In exemplary embodiments, the magnitude values are evaluated to identify the magmtude samples having the greatest and next-greatest magnitudes. The greatest magnitude value corresponds to the strongest of the multipath signals in the received multipath signal, deemed the main path signal, while the next-greatest magnitudes correspond to the significant secondary signals in the received multipath signal. In exemplary embodiments, only the two sfrongest secondary path signals are characterized for cancellation (e.g., N = 2), as these two secondary signals represent the main source of multipath interference in the received signal. Other embodiments may provide cancellation for fewer or greater numbers of secondary (echo) signals. Essentially any number of secondary path signals may be selected and subsequently characterized with this method, but characterizing and canceling very weak secondary signals may provide little additional benefit. With the N secondary path signals of interest identified, processing advances to the characterization portion of the training method of the present invention. In exemplary embodiments of this method adapted to work in the context of multipath interference cancellation in 802.1 lb data packets, propagation path parameters for the selected secondary path signals are learned at the beginning (preamble/header) of each 802.1 lb data packet, and are characterized with respect to the main propagation path signal. The main propagation path signal may be considered to have a magnitude of 1, and a phase of 0. Thus, learning the parameters of the selected secondary path signals entails determining a complex coefficient that expresses the relative magnitude and phase of a given secondary path signal with respect to the normalized main path signal. Parameterization of the secondary path signals additionally entails identifying the propagation path delay of each selected secondary path with respect to the main propagation path. Based on the previously saved phase offset index value corresponding to the first secondary path of interest, the secondary path despreading circuit is synchronized with the first of the secondary path signals of interest (block 822). Received signal magmtude and phase samples for both the main path signal and the selected secondary path signal are accumulated over K symbols (blocks 824 and 828, respectively). While simultaneous acquisition of magnitude and phase sample information is depicted, some embodiments may employ non-simultaneous magnitude and phase processing. With respect to magnitude, the accumulated samples are integrated to form rs and Γ M , representing the secondary path signal magnitude integrated over M symbols and the main path signal magnitude integrated over the same M symbols, respectively. Using these values, the relative magnitude of the currently selected secondary path signal may be computed with respect to the main path signal, providing the value r_ (block 826), which is stored for subsequent use. Based on correlating differentially decoded phase values from previous, current, and succeeding main path and secondary path symbols, the method of the present invention identifies whether the current secondary path symbol arises from the current main path symbol, or if it is associated with a different main path symbol (block 830). With this information, the appropriate phase of the currently selected secondary path signal may be determined with respect to the main path signal (block 832), and the delay offset of the currently selected secondary propagation path may be determined with respect to the main path signal (block 834). Thus, for the currently selected secondary path signal, the relative magmtude r., the relative phase θ_, and the path delay ( .are now estimated. The magmtude and phase information are combined to form a complex coefficient C { that represents the magnitude and phase changes experienced by a signal transmitted via the currently selected secondary propagation path with respect to the main propagation path transmission (block 836). Exemplary embodiments of the method of the present invention assume that the radio channel propagation path characteristics are constant over the duration of a single 802.1 lb data packet. Thus, this complex coefficient may be used in the cancellation of the currently selected secondary path signal in the payload portion of the current 802.1 lb data packet, and then updated at beginning of the next data packet. Of course, in other embodiments, the method of the present invention may be readily adapted to complement the requirements of other protocols or system configurations. The learned parameters ( τ ) for the currently selected secondary path signal are stored for subsequent use in other system operations (block 838). In an exemplary implementation, the communications receiver 100 provides these learned parameters to the equalizer 130 for use in its multipath interference cancellation operations, but this represents only one of many possible uses. For example, in other types of systems, such as previously discussed CD1VIA cellular telephone systems, the learned secondary path channel parameters may be advantageously used by a RAKE receiver to synchronize one of its RAKE fingers with the currently selected secondary path. -The secondary path parameters further provide path delay information necessary to coherently combine individual RAKE fingers signals to form the RAKE receiver output. Once the currently selected secondary path signal has been fully characterized, processing checks if there are any remaining secondary path signals of interest (block 840). If there are not, processing ends (block 844), otherwise the secondary path despreading circuitry is adjusted to synchronize with the next secondary path signal of interest (block 842), so that its path parameters may be similarly learned (blocks 824 through 838). Figure 9A provides a simplified diagram of an exemplary embodiment of the training circuit 200 of the present invention. As noted, fraining circuit 200 is preferably integrated with the communications receiver 100. The fraining circuit includes main and secondary signal magnitude processing circuitry comprising a magnitude comparator 250, and further includes main and secondary signal phase value processing circuitry including delay elements 206A and 206B, differential decoders 208 and 210, a phase comparator 260, an optional phase sheer 212, additional delay elements 222A and 222B, and a correlator 270. The correlator 270 operates on both current and delayed values from differentially decoded symbol sequences received via the main and secondary signals to determine the time offset between the main and the currently selected secondary signal. For clarity, delay elements 222A and 222B are shown apart from the correlator 270, but may considered be included within the correlation circuit 270. The phase comparator 260 operates on both current and delayed values in symbol sequences received via the main and secondary signals in advance of the differential decoders 208 and 210 to determine a relative phase between the secondary signal and the main signal. Note that the delay elements 206A and 206B have symmetrical delays, as do delay elements 222A and 222B. The associated delays may be set depending upon design requirements and signal characteristics. Exemplary operations of the training circuit 200 are detailed in following discussion. Referring now to the more detailed depiction of an exemplary fraining circuit 200 shown in Figure 9B, integrators 202A and 202B, along with a comparator circuit 204, form the magnitude comparator 250. Differential decoder 208 is implemented as a summing node 208 and outputs a differentially decoded symbol phase value based on subtracting a delayed symbol phase value from a current symbol phase value for main path signal symbol phase values. Differential decoder 210 is implemented as a summing node 210 and outputs a differentially decoded symbol phase value based on subtracting a delayed symbol phase value from a current symbol phase value for secondary path signal symbol phase values. Decoders 208 and 210 receive delayed symbol phase values from delay elements 206 A and 206B for the main and secondary signals, respectively. Summing nodes 214, 216, and 218, in combination with the phase selector circuit 220, combine to form the phase comparator 260. The phase comparator 260 receives current symbol phase values from the main and secondary signal inputs and delayed main and secondary signal symbol phase values from the delay elements 206 A and 206B. Note that additional summing nodes may be included in the fraining circuit 200 to compute any number of phase differences between current and delayed main and secondary symbol values for input to the phase selector circuit 200. An optional sheer 212 operates on the differentially decoded output from decoder 210 to remove noise from the secondary signal symbol phase values. Digital delay elements 222A and 222B combine with summing nodes 224, 226, and 228, and associated integrators 230, 232, 234, along with a minimum picker circuit 236, to form the correlator 270. In operation, the fraining circuit 200 receives a main path signal that remains synchronized to the sfrongest of the multipath signals, and a secondary path signal that is synchronized at different times with different ones of the secondary path signals. For reference in the subsequent discussion, variables associated with the main path signal will have an "M" subscript, while variables associated with the secondary path signals will have an "S" subscript. The communications receiver 100 adjusts the offset index (OFFSET M ) of the PN M sequence using adder 164B, which changes the code phase of the PN sequence provided to multipHer 142B, allowing it to synchronize with and despread the main path signal. Thus, Γ M and Θ M represent magnitude and phase sample values, respectively, of the main path signal. Secondary propagation path parameter estimation requires the commumcations receiver 100 to characterize a select number of secondary path signals with respect to the main path signal. The number of secondary path signals that are characterized during training depends upon specific design and operating requirements. Those skilled in the art will readily appreciate that the fraining method of the present invention may be varied in this and in other respects without departing from the scope of the present invention. Exemplary embodiments process the secondary path signals to identify the two strongest secondary path signals, with these strongest signals referred to as the secondary path signals of interest. The communications receiver 100 varies the offset index (OFFSETs) of the secondary path PN sequence (PNs) using adder 164D, which changes the code phase of the PN sequence provided to the secondary signal despreading circuitry (including multiplier 142D) in the despreading circuit 140. This allows the despreading circuit 140 to selectively synchronize with each secondary signal. Each offset change in the P s sequence supplied to the despreading circuit 140 effectively results in despreading the received signal with a different time delay relative to the main path signal timing. Essentially, the communications receiver 100 sets the offset of the PNs sequence and monitors the magnitude of rs. In exemplary embodiments, it performs this operation at half-chip resolution over an entire PN code phase cycle relative to the main path symbol timing. By recording the phase settings (index offsets) that result in the greatest magnitudes for rs, the communications receiver 100 identifies the main path signal and the sfrongest secondary signals. After performing this course search for the main path signal and major secondary path signals, it is necessary to estimate the propagation path parameters and delay for each secondary path of interest. The fraining circuit 200 provides an economical and processing-efficient manner of accompHshing this goal. Essentially, the fraining circuit 200 may be thought of as comprising an upper branch, fed by Θ M (main path received symbol phase modulation sample values) and including the summing node 208, and a lower branch fed by θg (secondary path received sy bol phase modulation sample values) and including the summing node 210. The upper branch operates on the despread main path signal, while the lower branch operates on the selected despread secondary signal to which the despreading circuitry 140 is currently synchronized. The combined operation of the upper and lower branches of fraining circuit 200 provides estimations for magnitude r, phase θ, and delay d, for each secondary path signal of interest relative to the main path signal. The following operations are repeated for each secondary signal of interest. The PNs sequence offset is set such that the despreading circuitry 140 de-spreads the desired secondary path signal — each of the required PNs sequence offsets corresponding to the secondary signals of interest were identified during the course search. The symbol magnitudes for Tu and rs are accumulated for K symbols and then compared in the relative magnitude circuit 204. For example, main and secondary path symbols may be accumulated or integrated in integrators 202A and 202B, respectively. The magnitude for the current secondary signal of interest relative to the main path signal is estimated based on dividing the K-sum of rs over ΓM. The fraining circuit 200 provides this estimated relative magnitude "r" as an output value that is used in estimating the secondary propagation path coefficient associated with the current secondary signal. At this point, the relative magmtude for the current secondary signal of interest has been estimated. The hard-slicer 148, preferably included in the despreading circuit 140, shces the main path signal phase samples according to the modulation constellation involved before they are input to the upper branch of the framing circuit 200 as Θ M . Hard-slicing entails adjusting or changing the actual phase value to the closest matching one of a defined set of nominal phase values — essentiaUy, this removes noise from the phase sample. To provide differential decoding for the main path phase samples Θ , the training circuit 200 includes the delay element 206A, which provides the shced main path phase sample of the preceding symbol to the inverting input of the summing node 208. In communications systems lacking the hard-slicer 148, it may be optionally integrated into the training circuit 200. The summing node 208 outputs the difference between the current and previous main path symbols' shced phase values. The shced phase of the main path signal is the phase modulation value of the current data symbol subject to possible decision error (the slicing operation). Because the secondary path imposes an unknown phase change on the phase of the current secondary path data symbol (θs), the θs phase values are differentially decoded using the delay element 206B and the summing node 210 before hard slicing. The summing node 210 outputs the difference between the current secondary path data symbol's phase and that of the previous symbol. The received phase of the secondary signal consists of the phase modulation value of the current secondary path data symbol and the channel phase delay of the secondary propagation path. Therefore, the phase delay of the secondary path relative to the main path can be estimated by subtracting the shced phase of the main path from the received phase of the secondary path. For near post-cursor (within a symbol time), the subtraction of phase values Θ and θs is performed immediately on the current main and secondary path data symbols using summing node 216, with the result labeled θi. For pre-cursor delay, the phase delay between the main path signal and the current secondary path signal is estimated based on subtracting the current main path symbol's phase value from the phase value of the preceding secondary path symbol using summing node 214, with the result labeled θ 0 . For far post-cursor delay (delay exceeding one symbol time), the phase delay between the main path and the current secondary path is estimated based on subtracting the phase value of the preceding main path symbol from the phase value of the current secondary path symbol using summing node 218, with the result labeled θ 2 . In order to determine which main-to-secondary path relative phase value to use (θ 0 , θ \ , or θ ), the communications receiver 100 must know whether the current secondary signal arises from pre-cursor, or near or far post-cursor echo signal interference. The fraining circuit 200 provides this information by evaluating the cross-correlation between the main path symbol decision and the current secondary path symbol decision (the hard- shced, differentially decoded values of ΘM and θs) using a sequence of R received symbols. The cross-correlation is performed, in this exemplary embodiment, with relative lags of-1, 0, and +1 symbols, corresponding to pre-cursor, near post-cursor, and far post-cursor delays, respectively. Note that the correlator 270 may be modified to perform correlation operations on any number of leading and lagging main and secondary symbols, thus enabling the correlator 270 to identify a symbol correspondence between main and secondary symbols offset by time offsets equaling any number of symbol times. Differentially decoding the secondary path symbols substantially removes any phase shift relative to the main path induced in the transmitted symbols received through the currently selected secondary propagation path. This results from the secondary path phase shift being an essentially constant value that can be removed through subtraction. The main path symbols are differentially decoded for consistency of operations in the main-to-secondary path symbol processing. The siunming node 224 provides as its output the difference between the differentially decoded, hard-sHced phase value of the current main path symbol and the differentially decoded, hard-sliced phase value of the previous secondary path symbol. The integrator 230 integrates the absolute value of this signal over R symbols. The summing node 226 provides as its output the difference between the differentially decoded, hard-sliced phase value of the current main path symbol and the differentially decoded, hard-sliced phase value of the current secondary path symbol. The integrator 232 integrates the absolute value of this signal over R symbols. The summing node 228 provides as its output the difference between the differentially decoded, hard-sliced phase value of the previous main path symbol and the differentially decoded, hard-sliced phase value of the current secondary path symbol. The integrator 234 integrates the absolute value of this signal over R symbols. As a result of the phase-domain operations, the maximum correlation of symbols translates to a rninimum value (ideally zero) of phase — minimum phase corresponds to a maximum real component. The minimum picker circuit 236 operates on the output from each of the integrators 230, 232, and 234 to determine which of the integrated signals exhibits the lowest value. The earlier, so-called course search identified the time offset (PN code phase offset index) of each secondary path signals of interest within a symbol time with respect to the main path signal, but could not provide information about actual secondary path time offset (potentially more than a symbol time) without pre/post-cursor information. Correlation results from the minimum picker circuit 236 identify corresponding main and secondary symbols. The number of symbols times by which corresponding main and secondary path symbols are offset may be expressed as a relative time offset based on the known symbol timing of the received multipath signal. Thus, the output of the nύnimum picker circuit 236 may be used to set the appropriate equalizer shift register tap offset value (f in Figures 10 and 11), and is further used to set the phase select circuit 220 such that it provides the appropriate phase output (θo, θi, or θ 2 ). Providing the appropriate phase output means selecting the phase difference computed for corresponding main and secondary symbol values, as the phase shift of the secondary path signal relative to the main path signal may only be accurately determined from main and secondary symbol values that actually correspond to one another — result from the same transmitted symbol value. Upon completion of these operations, the communications receiver 100, based on practicing an exemplary embodiment of the fraining method, has determined the required magmtude, phase, and time offset information necessary to configure the equalizer 130 to provide cancellation of the currently selected secondary path signal. More specifically, the communications receiver 100 has the information necessary to estimate the complex coefficient ( C ) for the current secondary propagation path. The above process is repeated for each secondary path of interest. In operation, the equalizer 130 maintains a running buffer of the last N most-recent hard-sliced multipath signal phase samples corresponding to the past N received multipath signal samples. Since each successive stage (tap) in shift register 330 (buffer) corresponds to a successively longer sample time offset delay with respect to the current received signal sample, a secondary path time offset value τ is set for a given secondary path coefficient C such that the corresponding shift register 330 tap delay matches or substantially matches the calculated secondary propagation path time offset relative to the main propagation path. Figure 10 illustrates a generahzed exemplary embodiment for the equalizer 130 included in the communications receiver 100. Operating on chip or sub-chip resolution input samples u(t), the equalizer 130 provides pre-cursor and/or post-cursor multipath signal cancellation. Once propagation path parameters are determined — the appropriate estimated delay register tap values (τ 2l ..f 2L an n .. 1N ) and complex estimated coefficients (C^C-^ and C n ..C 1N ) must be set first — the equalizer 130 compensates received signal samples output from the carrier recovery circuit 120 by canceling out interfering secondary signals caused by multipath phenomena. These compensated received signal samples are output from the equahzer 130 and serve as the input samples to the despreading circuits 140. Thus, once the equalizer 130 is set and activated, the despreading circuits 140 and subsequent baseband processing circuits 170 operate on received signal samples from which equahzerl30 has canceled the major multipath interference. As illustrated in Figure 10, the equalizer 130 includes a sample shift register 320, a shced sample shift register 330, a hard sheer 310, a post-cursor cancellation summing node 302, a pre-cursor cancellation summing node 304, a post-cursor estimated multipath signal summing node 308, a pre-cursor estimated multipath signal summing node 306, and memory elements 312 and 314 for storing post- and pre-cursor estimated secondary propagation path coefficients C u ..C m and C 2] ..C 2L , respectively. The equalizer 130 provides cancellation for up to N post-cursor multipath signals and up to L pre-cursor multipath signals. Of course, these capabilities may be varied based on specific design needs. Indeed, the equalizer 130 may be implemented with just pre-cursor multipath cancellation, or with just post-cursor multipath cancellation. Note also that the maximum delay offsets between pre- and post-cursor multipath signals and the main path signal which can be handled by the equalizer 130 are limited only by the lengths of shift register 320 (length d) and shift register 330 (length D), respectively. Thus, the multipath offset delay capability of the equalizer 130 may be easily adjusted in a given design without changing its structure or operation. The input signal u(t) represents the output from the carrier recovery circuit 120. The signal u(t) comprises multi-bit complex values (real and imaginary) representing discrete, synchronized samples of the received signal taken at chip or sub-chip resolution. The u(t) samples include multipath interference. The equahzer 130 provides multipath interference cancellation based on applying hard-decision logic to the phase value of each sample of u(t) (chip or sub-chip). For example, in DSSS using QPSK, or in 802.1 lb payload data using CCK, each received symbol or chip takes a symbol value on a QPSK constellation, and the hard-decision may be made by hard-slicing the phase of the received sample in u(t). To cancel post-cursor multipath interference, the hard-sliced chip (or sub-chip) decision(s) is fed back with the proper delay(s) (e.g., τu) and multiplicand coefficient(s) (e.g., Cu) for subtraction from u(t) in summing node 302. This aspect of operation is conceptually similar to more conventional Decision Feedback Equalizers DFE), which are well understood in the art. Looking specifically at post-cursor multipath interference, we can represent the received samples (chip or sub-chip resolution) in u(t) as the sum of the main path signal s(t), which is defined as the signal with the greatest magnitude, and post-cursor secondary path signals with delays τi. and corresponding complex coefficients Cu (with [ Cu I <= 1). From this perspective, we may represent the received signal samples comprising u(t) as r(t) = s(t) + ∑ ' ι C u s(t - τ u ) Thus, the output y(t) from the post-cursor cancellation summing node 302 may be represented as u(t) minus the estimated post-cursor multipath signals as follows, y(t) = r(t) -∑C u s(t ~τ ) i Where C lt and τ u are the estimated complex secondary path coefficients and corresponding secondary propagation path delay estimates, respectively, developed during fraining, and where s(t) is the hard-shced sample decision given by s(t) = j/zce[y( ] • Note that the slicer 310 performs its hard-decision slicing operation after cancellation of post-cursor multipath signals. Note that the number of shift register stages comprising the sliced sample shift register 330 combined with the input sample resolution (chip or sub-chip) determines the maximum multipath signal delay accommodated by the structure of equahzer 130. As illustrated, shift register 330 has D stages. This provides the equalizer 130 with the abiHty to cancel post-cursor multipath signals offset from the main path signal by up to D/x chip times, where x represents the sample resolution of u(t) — that is, the number of samples per chip in u(t). As an example, assume that u(t) is at half-chip resolution, or two samples per received DSSS chip, and further assume D — 32 stages. With these values, the equalizer 130 accommodates multipath delays up to 32/2 or 16 chip times. In 802.11b CCK-mode transmissions, this equates to two symbol periods of multipath delay capability (CCK modulation uses 8 chips per symbol in 802.1 lb). Pre-cursor multipath delay cancellation requires sample shift register 320 and the corresponding pre-cursor multipath cancellation summing node 304. In pre-cursor multipath interference, the echo signal arrives before the main path signal, thus the x 21 values are negative. The length d of shift register 320 determines the maximum precursor multipath delay accommodated by the equalizer 130, in a manner similar to that explained for post-cursor delay capabihty. With depth d = 8 and at 2 samples-per-chip input resolution, the equahzer 130 provides multipath cancellation for pre-cursor signals delayed from the main path signal by up to 8/2 or 4 chip times. Of course, pre- and post- cursor delay handling capabihty may be easily adjusted to suit the needs of a specific application simply by altering the length of either or both the shift registers 320 and 330. Focusing now on an expression for the input signal y(t-d) only in the context of pre-cursor multipath interference — ignoring any post-cursor cancellation operation performed on u(t) to form y(t) — we can express y(t-d) as, y(t -d) = s(t -d) + ∑ C 2i s(t - (τ 2l + d)) i Thus, the output z(t) from the pre-cursor cancellation summing node 304 may be represented as y(t-d) minus the estimated pre-cursor multipath signals as follows, z(t) = y(t - d) - X C 2i s(t - (τ 2i - d)) i Where C and τ 2i are the complex coefficient estimates and delay estimates developed during equalizer fraining, and s(t) is the hard-sliced sample decision, s(t) = slice[y(t)]. The equalizer 130 advantageously avoids complex multiplications regarding the hard-sliced samples s(t) held in shift register 330 and the estimated complex coefficients C H and C 2i . Rather than multiplying the s(t) sample held in a particular shift register stage by one of the estimated coefficients (C n or C 2i ) , the hard-sliced value of s(t) is used to simply "rotate" the phase of the complex coefficient. This action works because the complex coefficient (C ι; or C 2i ) represents, in part, the essentially constant phase shift of a particular secondary path signal relative to the main path signal, and the particular hard- sliced value of s(t) represents the nominal phase value of the multipath signal sample at a point in time offset from the current multipath signal sample by an amount equal to the time offset of the particular secondary path signal relative to the main path. Thus, the secondary path coefficient represents relative phase shift and the hard-shced sample serves as a reference for this relative phase shift. Hard-slicing the y(t) samples with sheer 310 produces shced samples s(t) from which the noise is removed. The operation of sheer 310 produces output samples having one of a defined set of values corresponding to the constellation points defined by the communications system modulation scheme. For example, in an 802.1 lb CCK scheme, the sheer 310 operates as a QPSK sheer, processing (hsy(t) samples to produce s(t) output samples having the closest matching ideal QPSK constellation values (namely, ±1, or ±j). Thus, the feedback (feedforward) signals for post-cursor (pre-cursor) multipath signal cancellation represent the ideal estimated multipath signal rather than the estimated multipath signal + sample noise. This avoids adding noise in the feedback or feedforward signals with the instantaneous noise in the current u(t) oτy(t-d) sample values. Figure 11 illustrates an exemplary implementation of the equalizer 130 designed for multipath signal cancellation in an 802.1 lb environment. In exemplary embodiments of the communications receiver 100, the received DSSS/PSK signal is converted from analog-to-digital format at 5 bits of resolution, but the particular resolution used is not critical to practicing the present invention. Continuing the 802.1 lb example, the input to the equalizer 130 comprises complex digital values representing quarter chip samples of QPSK-modulated chips at 8 chips per symbol. (This corresponds to the CCK-modulated payload data of an 802.1 lb data packet and assumes that the equalizer 130 has already been trained — configured using the fraining method of the present invention, as described earlier herein — during the lower data rate header/preamble portions of the 802.1 lb packet.) Thus, u(t) represents a stream of 5-bit complex signal samples, that, in an exemplary embodiment, are taken at quarter-chip resolution (4 samples per received QPSK-modulated chip) and represent a sampling rate of 44 MHz. As shown in Figure 11, the equalizer 130 includes an optional decimation block 301 on its input to adjust its sampling rate to be compatible with a wide range of sub-chip input sample resolutions. The decimation block 301 may be configured to decimate the input signal u(t) as required to provide u(t) ' having the desired sample resolution (chip or sub-chip). As iUusfrated, decimation block 301 decimates the quarter-chip resolution input signal u(t) by a factor of two to form the half-chip resolution input signal u(t) ' with a sample rate of 22 MHz. Note that the equahzer 130, as depicted in Figure 10, provides multipath signal compensation for two post-cursor echo signals or one post- and one precursor echo signals. Operation of the equalizer 130 depicted in Figure 11 is consistent with the discussion relating to Figure 10. The equalizer 130 uses the sliced sample register 330 in combination with the summing circuit 302 to provide post-cursor multipath signal cancellation. As illusfrated, the feedback paths including complex coefficients Ci and C 2 provide for cancellation of up to two post-cursor multipath signals. The post-cursor delay offsets %\ and τ 2 correspond to the delay offsets between main path and post-cursor multipath signals as determined during equalizer fraining. Figure 11 also illustrates cancellation capability for one pre-cursor multipath signal, based on using the sample shift register 320 and the corresponding summing node 304. As illustrated, the feed-forward path including the complex coefficient C 3 provides for cancellation of a single pre-cursor multipath signal. (The novel structure of the equalizer 130 allows deletion of pre-cursor multipath cancellation by eHminating the shift register 320 and the summing circuit 304 without interfering with the basic post-cursor cancellation structure.) The half-chip resolution complex samples u(t) ' are compensated for post-cursor multipath interference in summing circuit 302. For example, assume that equahzer fraining identified a post-cursor multipath signal offset from the main path signal by one- and-a-half (1.5) chip times as the secondary event, and further identified a pre-cursor multipath signal offset by two-and-a-half (2.5) chip times from the main path signal as the tertiary event. With a 2-chips per sample shift rate, f 3 = 4 - 9 = -5 , which represents the offset (4) into the sliced sample register 330 minus the depth (9) of the delayed sample register 320 required to provide 2.5 chip times of precursor delay. Continuing the example, the supporting logic 160 in conjunction with the baseband processor 170 sets the estimated complex coefficients C-. and C 3 and estimated offset delays τ and τ 3 by methods earlier described — C 2 and 2 would not be used in this specific example. For the i* u(t) ' input sample, the (i th - 3) delayed sample (f x = 3) is "subtracted" from the input sample, thereby canceling the secondary multipath event corresponding to this secondary propagation path delay. As earlier explained, the complex coefficients are phase rotated based on the hard-sliced sample value contained in the shift register stage corresponding to delays ( ) associated with the coefficients, and then subtracted from u(t) ' oτy(t-d). Actual radio channel characteristics, required bit rates, and communications system requirements determine the optimal structure of the equalizer 130 in specific designs. Figure 10 illustrates a generalized realization of the equalizer 130 preferably included within the communications receiver 100, while Figure 11 provides a more specific example in the context of 802. l ib CCK-mode multipath signal interference cancellation. Figure 11 corresponds to an embodiment of the training method wherein only the two strongest multipath signals are canceled — either two post-cursor or one precursor and one post-cursor echo signal. Note that operating with a greater number of samples per chip provides better multipath delay resolution, but requires greater shift register depth to provide the same multipath signal delay spread capabihty. Those skilled in the art will recognize that shift register depth must be balanced against multipath event time resolution based on individual design requirements. The equahzer 130 easily accommodates such design- specific changes without requiring structural changes. More specifically, the need for increased or decreased multipath signal delay capability may be handled by simply adjusting the length of shift registers 320 and 330. Because post-cursor multipath delay ranges can be much longer than pre-cursor multipath delay ranges, there is a real advantage in extending the length of the post- cursor cancellation shift register 330 well beyond that of the pre-cursor cancellation shift register 320. If the full bit resolution of the individual complex samples (sub-chip or chip samples) was used for the post-cursor cancellation shift register 330, an extended length shift register, as is required for spanning multi-symbol delays, would consume considerable circuit resources because of the need to store full-resolution samples (e.g., 12 bits) rather than reduced-resolution samples. For example, hard-slicing the y(t) samples to produce the s(t) samples reduces the required width of shift register 330 to just • two bits for QPSK signals, to represent the l-of-4 nominal phase values used in QPSK modulation. (In general, hard-shcing reduces the shced samples to n bits where 2 n = M in M-ary modulation schemes.) The fraining method of the present invention offers substantial oppoiτunity for variation without departing from the spirit and scope of the invention. For example, details regarding the communications receiver 100 are not critical to practicing the fraining method. Virtually any combination of methods and supporting apparatus for despreading and synchronizing with the main path signal and selectable ones of the secondary path signals is compatible with the fraining method disclosed herein. Thus, operations associated with the fraining method of the present invention may be implemented in a variety of communications receiver architectures, and in a variety of communications system types. Further, while the disclosed training circuit 200 represents an exemplary apparatus for practicing the fraining method, other circuit implementations are possible and perhaps even desirable, depending upon the requirements of a given communications system. With regard to its implementation details, the fraining circuit and associated fraining method offer significant opportunity for variation. Understandably, substantial variation potentially arises with regard to the particular communications receiver architecture used to implement or support the fraining method. It should be understood that the commumcations receiver 100 illustrated and described herein represents only an exemplary platform for practicing the multipath propagation parameter fraining operations of the present invention. Other architectures are possible, or even preferred, depending upon design and system requirements. Thus, ancillary operations associated with mscriminating (despreading or selectively receiving) secondary and main signals may vary as a function of associated receiver circuitry. Further, the training circuit itself may be varied in a number of ways. For example, the magnitude comparator 250 may be simplified to simply compare main and secondary signal magnitudes, at the potential expense of accuracy in the relative magnitude comparison. Conversely, the magnitude comparator 250 may be increased in terms of sophistication, both in the number of samples accumulated, and in the integrating or accumulating operations themselves. Similar variation is possible with regard to the number of phase values samples used in correlation and phase comparison operations. Additionally, while shown in the context of an exemplary commumcations receiver 100, the training circuit 200 may be implemented in a variety of configurations, and may operate as a stand-alone device, or be integrated within other architectures. Further, as the number of secondary signals characterized may vary, so too the range of time offset between main and secondary signals accommodated by the fraining circuit may vary. Thus, variations on the extent of multipath delay (either pre- or post- cursor) are well within the scope of the present invention. Correlation operations may be modified to cover a desired range of current, preceding, and succeeding ones in concurrent sequences of main and secondary signal symbols. With the ability to determine secondary signal time offsets extending beyond one symbol time relative to the main signal and, therefore, accurately determine secondary signal phase shift relative to the main signal, the fraining operations of the present invention, supported by the training circuit 200 and associated method, provide an advantageous approach to characterizing secondary signals in a multipath reception environment without limitations regarding secondary signal delay spread. Training, as outlined herein in exemplary fashion, provides advantages to a broad range of communications systems subject to multipath signals. The fraining circuit 200 and fraining method are particularly advantageous for use as the basis of multipath signal interference cancellation in spread spectrum systems utilizing spreading codes with poor auto- and cross-correlation characteristics, as conventional RAKE receiver techmques works poorly in such applications. As such, the present invention may be used to significant advantage in 802.1 lb wireless LAN systems. However, the present invention may also be advantageously apphed in RAKE receiver architectures, or, indeed, applied in any DSSS communications system for which multipath signal characterization and/or cancellation benefits receiver performance. The foregoing details should, in all respects, be considered as exemplary rather than as limiting. The present invention allows significant flexibility in terms of implementation and operation. Examples of such variation are discussed in some detail above; however, such examples should not be construed as limiting the range of variations falling within the scope of the present invention. The scope of the present invention is limited only by the claims appended hereto, and all embodiments falling within the meaning and equivalency of those claims are embraced herein.

Claims: Claims What is claimed is: 1. An apparatus for characterizing a secondary path signal relative to a main path signal received in a multipath radio signal, said apparatus comprising: main and secondary magnitude inputs adapted to receive main and secondary magnitude values from the main and secondary path signals; a magnitude comparator adapted to receive the main and secondary magnitude values and to determine a magnitude of the secondary path signal relative to the main path signal; main and secondary phase inputs adapted to receive main and secondary symbol values from the main and secondary path signals; first main and secondary delay elements adapted to receive the main and secondary symbol values and to output delayed main and secondary symbol values; main and secondary differential decoders adapted to receive the main and secondary symbol values and the delayed main and secondary values and to output differentially decoded main and secondary symbol values; second main and secondary delay elements adapted to receive the differentially decoded main and secondary symbol values and to output delayed differentially decoded main and secondary symbol values; a correlator adapted to receive the differentially decoded main and secondary symbol values and the delayed differentially decoded main and secondary symbol values, and to determine a time offset of the secondary path signal relative to the main path signal based on identifying a symbol correspondence between the differentially decoded main and secondary symbol values; and a phase comparator adapted to received the main and secondary symbol values and the delayed main and secondary symbol values and to determine a phase difference between corresponding main and secondary symbol values based, in part, on said symbol correspondence. 2. The apparatus of claim 1 wherein said magnitude comparator comprises main and secondary magnitude value accumulators and an associated comparator circuit adapted to output a relative magnitude value based on comparing accumulated main and secondary magnitude values. 3. The apparatus of claim 2 wherein said comparator circuit is adapted to compute a ratio between an accumulated secondary magnitude value and an accumulated main magnitude value. 4. The apparatus of claim 2 wherein said main and secondary magnitude value accumulators provide an accumulated main magnitude value and an accumulated secondary magnitude value based on integrating a number of received main and secondary magnitude values. 5. The apparatus of claim 1 wherein said correlator comprises: a plurality of input circuits adapted to receive selected combinations of the differentially decoded main and secondary symbol values and the delayed differentiaUy decoded main and secondary symbol values and to output a corresponding plurality of difference values; a plurality of accumulators adapted to receive said difference values and to output a corresponding plurality of accumulated difference values; and a correlation circuit adapted to receive said accumulated difference values and to identify one of said accumulated difference values as a minimum difference value, and further adapted to identify said symbol correspondence between main symbol values and secondary symbol values based on said minimum difference value. 6. The apparatus of claim 5 wherein said plurality of input circuits comprise: a first input circuit adapted to receive a differentially decoded main symbol value and a delayed differentially decoded secondary symbol value, and further adapted to output a first difference value indicating a difference between the differentially decoded main symbol values and the delayed differentially decoded secondary symbol value; a second input circuit adapted to receive the differentiaUy decoded main symbol value and a differentially decoded secondary symbol value and further adapted to output a second difference value indicating a difference between the differentiaUy decoded main and secondary symbol values; and a third input circuit adapted to receive a delayed differentially decoded main symbol value and the differentiaUy decoded secondary symbol value and further adapted to output a third difference value indicating a difference between the delayed differentiaUy decoded main symbol value and the differentially decoded secondary symbol value. 7. The apparatus of claim 6 wherein respective ones of said plurality of accumulators accumulate respective ones of said first, second, and third difference values to form first, second, and third accumulated difference values, and wherein one of said accumulated difference values will be a minimum accumulated difference value indicating a maximum main and secondary symbol value correlation associated with one of said selected combinations of the differentially decoded main and secondary symbol values and the delayed differentially decoded main and secondary symbol values received by said plurality of input circuits. 8. The apparatus of claim 7 wherein said maximum main and secondary symbol value correlation indicates whether a given secondary symbol value corresponds to a concurrently received main symbol value, to a main symbol value received more than one symbol time before said given received secondary symbol, or to a main symbol value received more than one symbol time after said given secondary symbol. 9. The apparatus of claim 1 wherein said phase comparator comprises: a plurahty of input circuits adapted to receive selected combinations of the main and secondary symbol values and the delayed main and secondary symbol values and to output a corresponding plurality of difference values; and a phase selection circuit adapted to select one of said plurality of difference values for output as a phase offset value for the secondary path signal relative to the main path signal based on said symbol correspondence identified by said correlator. 10. The apparatus of claim 9 wherein said plurality of input circuits comprise: a first input circuit adapted to receive a main symbol value and a delayed secondary symbol value, and further adapted to output a first difference value indicating a difference between the main symbol value and the delayed secondary symbol value; a second input circuit adapted to receive the main symbol value and a secondary symbol value, and further adapted to output a second difference value indicating a difference between the main and secondary symbol values; and a third input circuit adapted to receive a delayed main symbol value and the secondary symbol value, and further adapted to output a third difference value indicating a difference between the delayed main symbol value and the secondary symbol value. 11. The apparatus of claim 10 wherein said phase selection circuit outputs said phase offset value by selecting one of said first, second, and third difference values as representing a phase difference between corresponding main and secondary symbol values, wherein said corresponding main and secondary symbols are selected based on said symbol correspondence. 12. The apparatus of claim 1 further comprising a phase sheer adapted to receive main symbol values from the main path signal and to output sliced main symbol values for input to said main phase input, whereby said apparatus receives sliced main symbol values from the main path signal via said main phase input, and further wherein said phase sheer changes received main symbol values to closest matching nominal symbol values, wherein the possible nominal symbol values are defined by a modulation scheme associated with the main and secondary path signals. 13. The apparatus of claim 1 further comprising a phase sheer adapted to receive differentially decoded secondary symbol values and to output shced differentially decoded secondary symbol values, whereby said second secondary delay element and said correlator receive shced differentially decoded secondary symbol values, and whereby said correlator additionally receives delayed sliced differentially decoded secondary symbol values output from said second secondary delay element, wherein said phase sheer changes differentially decoded secondary symbol values to closest matching nominal symbol values, and wherein the possible nominal symbol values are defined by a modulation scheme associated with the main and secondary path signals. 14. An apparatus for characterizing a secondary path signal relative to a main path signal received in a multipath radio signal, said apparatus comprising: a correlation circuit adapted to concurrently receive sequences of differentially decoded main and secondary symbol values from the main and secondary path signals, and further adapted to determine a time offset of the secondary path signal relative to the main path signal based on identifying a symbol correspondence between main and secondary symbol values by cross-correlating selected ones in the sequence of differentially decoded main symbol values with selected ones in the sequence of differentially decoded secondary symbol values; a phase comparison circuit adapted to concurrently receive one or more main and secondary symbol values from the main and secondary path signals, and further adapted to determine a phase offset of the secondary path signal relative to the main path signal based on computing a number of phase differences between selected ones of the main symbol values and selected ones of the secondary symbol values, and further based on selecting one of said number of phase differences as said phase offset based on said time offset determined by said correlation circuit; and a magnitude comparison circuit adapted to concurrently receive one or more main and secondary magnitude values from the main and secondary path signals, and further adapted to determine a relative magmtude of the secondary path signal relative to the main path signal based on comparing the one or more secondary magnitude values with the one or more main magnitude values; said characterization of the secondary path signal provided based on said 1 apparatus outputting said time offset, said phase offset, and said relative magnitude. 15. The apparatus of claim 14 wherein said correlation circuit includes main and secondary delay elements adapted to receive the concurrent sequences of differentially decoded main and secondary symbol values, said main and secondary delay elements further adapted to output delayed sequences of differentially decoded main and secondary symbol values for use in said cross-correlating selected ones in the sequence of differentially decoded main symbol values with selected ones in the sequence of differentially decoded secondary symbol values. 16. The apparatus of claim 15 wherein said correlation circuit performs said cross-correlating selected ones in the sequence of differentially decoded main symbol values with selected ones in the sequence of differentially decoded secondary symbol values by correlating selected ones in the delayed sequence of differentially decoded secondary symbol values with selected ones in the sequence of differentially decoded main symbol values to form a first correlation value, correlating respective ones in the sequences of differentially decoded main and secondary symbol values to form a second correlation value, and correlating selected ones in the sequence of differentiaUy decoded secondary symbol values with selected ones in the sequence of delayed differentially decoded main symbol values to form a third correlation value. 17. The apparatus of claim 16 wherein said correlation circuit determines said- time offset based on identifying one of said first, second, and third correlation values as representing a maximum symbol correlation, wherein said maximum symbol correlation indicates whether secondary path signal leads the main path signal by a time offset in the range of one to two symbol times, lags the main path signal by a time offset in the range of one to two symbol times, or is aligned within one symbol time of the main path signal. 18. The apparatus of claim 17 wherein said phase comparison circuit determines said phase offset based on computing leading, lagging, and concurrent phase ' differences between the one or more main and secondary symbol values to form said number of phase differences, with said phase offset selected as one of said number of phase differences based on said time offset. 19. The apparatus of claim 15 wherein said correlation circuit performs said cross-correlating selected ones in the sequence of differentially decoded main symbol values with selected ones in the sequence of differentiaUy decoded secondary symbol values by correlating selected ones in the delayed sequence of differentially decoded secondary symbol values with selected ones in the sequence of differentially decoded main symbol values to form a number of leading correlation values, correlating respective ones in the main and secondary symbol sequences to form a concurrent correlation value, and by correlating selected ones in the sequence of differentially decoded secondary symbol values with selected ones in the delayed sequence of differentially decoded main symbol values to form a number of lagging correlation values. 20. The apparatus of claim 19 wherein said correlation circuit identifies said symbol correspondence and determines said time offset based on identifying one of said leading, lagging, and concurrent correlation values as representing a maximum symbol correlation, wherein said maximum symbol correlation indicates the number of symbol times by which the secondary path signal leads or lags the main path signal, or indicates that the secondary path signal is aHgned within one symbol time of the main path signal. 21. The apparatus of claim 20 wherein said phase comparison circuit determines said phase offset based on computing leading, lagging, and concurrent phase differences between the one or more main and secondary symbol values to form said number of phase differences, with said phase offset selected as one of said number of phase differences based on said time offset. 22. The apparatus of claim 14 wherein said magnitude comparison circuit comprises main and secondary magnitude value accumulators adapted to accumulate one or more magmtude values from the main and secondary path signals to form accumulated main and secondary magmtudes, and further comprising a magnitude comparator adapted to output said relative magmtude based on comparing the accumulated main and secondary magnitudes. 23. The apparatus of claim 22 wherein said main and secondary magmtude value accumulators function as integrators and wherein said accumulated main and secondary magnitudes represent an integration of a number of main and secondary magmtude values. 24. An apparatus for characterizing a secondary path signal relative to a main path signal received in a multipath radio signal, said apparatus comprising: a means for receiving sequences of main and secondary symbol values concurrently extracted from the main and secondary path signals; a means for generating sequences of differentially decoded main and secondary symbol values based on differentially decoding the sequences of main and secondary symbol values; a means for determining a symbol offset based on identifying corresponding symbol values between the sequences of differentially decoded secondary symbol values and differentially decoded main symbol values; a means for determining a time offset between the main and secondary path signals based on said symbol offset and a known symbol period; a means for deterrrining a number of phase differences between selected ones in the sequences of main and secondary symbols values; a means for selecting one of said number of phase differences as a relative phase offset based on said symbol offset; a means for receiving sequences of main and secondary symbol magnitudes concurrently extracted from the received main and secondary path signals; a means for accumulating main and secondary symbol magnitudes; and a means for comparing accumulated main and secondary symbol magnitudes to determine a relative magnitude for the secondary path signal to the main path signal; and means of outputting a set of characterization values including said relative magmtude, said relative phase offset, and said time offset.

Inventors: KING ERIC J, SHAN PEIJUN, KING, ERIC, J., SHAN, PEIJUN
Applicants: RF MICRO DEVICES INC, RF MICRO DEVICES, INC.
Application year: 2001
Main classification: H04B
IPC codes: H04B1