Resonant power converter

Abstract: A resonant power converter includes a DC power source 1, a pair of MOS-FETs 1 and 2 which are connected in series to the DC power source, a transformer Tr1 which is arranged at the subsequent stage of the MOS-FETs 1 and 2 and includes a primary coil and a secondary coil, a capacitor C4 is arranged in parallel with the secondary coil of the transformer Tr1 so that series resonance occurs between the leakage inductance of the transformer Tr1 and the capacitor C4. A current doubler rectifier circuit may be arranged in the subsequent stage of the capacitor C4. Further, a pair of switching elements for synchronous rectification may be provided in the subsequent stage of the capacitor C4 so that these switching elements are driven by drive signals responsive to a voltage generated across the resonance capacitor C4.

Description: BACKGROUND OF THE INVENTION Field of the Invention This invention relates to a DC power converter (DC power supply), and more particularly to a resonant power converter which is capable of performing zero voltage switching (ZVS) with reduced noise. A power converter of the kind defined by the precharacterizing portion of claim 1 is known from the JP 6 141 514. Description of the Prior Art In general, a 5 to 10 volt DC power converter is required to operate the semiconductor integrated circuits used in electrical and electronic equipment such as personal computers and AV equipment. In the prior art, as for such DC power converters, power converters using a switching regulator are employed. Such DC power converter using the switching regulator can be formed into a compact size rather than other types of DC power converters using series regulators and shunt regulators and the like. Further, such DC power converters have advantages in that power loss is small and energy conversion efficiency is high. Recently, in order to achieve even greater reductions in power loss, resonant switching converters which are capable of zero voltage switching (ZVS) have been proposed and put to practical use. In this connection, Fig. 16 is a schematic view of the structure of a prior art resonant power converter which is formed into a full bridge type. As shown in the drawing, this resonant power converter 20 is equipped with a DC power source E21, a bridge circuit composed of four MOS-FETs 21 to 24, and a transformer Tr21 which is arranged at the output side of such bridge circuit. In this structure, one end of a primary coil (winding) L21 of the transformer Tr21 is connected to the junction between the MOS-FETs 23, 24, and the other end thereof is connected to the junction between of the MOS-FETs 21, 22 via a resonance capacitor C21 and a resonance coil L24. Further, the both ends of a secondary coil (winding) L22 of the transformer Tr21 are respectively connected to the anodes of diodes D21, D22, and the cathodes of the diodes D21, D22 are connected to a center tap of the secondary coil L22 via a choke coil L23 and a capacitor C22. Further, both ends of the capacitor C22 form output terminals for connection to a load RL. In this arrangement, the MOS-FETs 21 to 24 are driven by drive pulses having roughly the same resonance frequency as the resonance circuit constituted from the resonance capacitor C21, the resonance coil L24 and the primary coil L21 of the transformer Tr21, so that alternate switching between a state in which the MOS-FETs 21, 24 are turned on and a state in which the MOS-FETs 22, 23 are turned on is carried out to generate a resonance current in the primary coil L21 of the transformer Tr21. With this result, the resonance current induces a current in the secondary coil L22 of the transformer Tr21, and therefore a regulated output voltage Vo is generated across the ends of the capacitor C22. Further, because the resonance current flows with a substantially sinusoidal waveform, zero voltage switching can be carried out, and this makes it possible to greatly reduce switching loss and generation of noise. However, in the prior art resonant power converter, since the resonance caused between the resonance capacitor C21 and resonance coil L24 and the primary coil L21 of the transformer Tr21 is utilized, there is a problem in that the energizing current for the transformer Tr21 becomes too large, which results in large energy loss and an increased size of the transformer Tr21. Further, there is another problem in that this arrangement requires to have the center tap in the secondary coil L2 of the transformer Tr21, which results in complicated structure of the transformer Tr21. In addition, in the prior art resonant power converter, since the diodes D21, D22 are used as the rectifying means, a large voltage drop occurs in these elements. Therefore, when such a power converter is configured into a large current and low voltage type power converter which is a trend of the current power converters, the energy loss caused in the diodes becomes considerably large, which results in the factors that cause increased heat generation and decreased conversion efficiency of the circuit of the power converter. Namely, the prior art circuit configuration involves a problem which can not be applied to large current and low voltage type power converters. SUMMARY OF THE INVENTION The present invention has been made in view of the problems in the prior art described above, and therefore an object of the present invention is to provide a resonant power converter which does not need to provide a center tap in a transformer and has high energy conversion efficiency. Another object of the present invention is to provide a resonant power converter utilizing synchronous rectification which can reduce energy loss in the rectifying means to improve energy conversion efficiency of the power converter. These objects are attained by the features of claim 1. Advantageous developments of the invention are defined in the subclaims. In the resonant power converter described above, because a resonance current flows between the resonance capacitor arranged on the secondary side of the resonant transformer and the leakage inductances of the resonant transformer, a resonance current will not flow through the primary coil of the transformer, and as a result, it is possible to reduce the excitation current of the transformer. Further, because zero voltage switching can be carried out, it becomes possible to reduce power loss. Furthermore, because the switching timing of the primary side is not synchronized with the switching timing of the secondary side, the switching noise generated at the primary side and the switching noise generated at the secondary side are not superposed with each other, and this makes it possible to diffuse noise. In the present invention, it is preferred that the resonant transformer is constructed from an ideal transformer and a resonant coil arranged in the primary side of the ideal transformer, so that the series resonance occurs between the resonant coil and the resonance capacitor. Further, it is also preferred that the resonant transformer has a leakage inductance, and the series resonance of the current occurs between the leakage inductance and the resonance capacitor. In the present invention, it is also preferred that the resonant power converter further comprises a current doubler circuit for making the current flowing through the secondary side double, said current doubler circuit being provided in the secondary side and coupled to the both ends of the resonance capacitor. In this case the current doubler circuit includes a pair of circuits each having a rectifying means and an inductance, in which these circuits are connected in parallel with each other so that a junction between the rectifying means and inductance of one circuit and a junction between the rectifying means and the inductances are respectively connected to the both ends of the secondary coil of the transformer. In the present invention, it is particularly preferred that the resonant power converter further comprises means for performing synchronous rectification for the current flowing the secondary side, said means including switching elements for synchronous rectification provided in the secondary side so as to be driven by drive signals responsive to the voltage generated across the resonance capacitor and having a sinusoidal waveform. In this case, it is preferred that said switching means includes a pair of switching elements, and these switching elements are driven by the drive signals. According to this arrangement, since the voltage signal in the form of sinusoidal wave generated across the resonance capacitor is used to drive the switching elements for synchronous rectification to rectify the current flowing through the secondary side of the circuit, a voltage drop can be drastically reduced as compared with the conventional circuit using diodes and thereby it is possible to improve the energy conversion efficiency of the power converter remarkably. Further, there is no need to provide a separate drive circuit for driving the switching elements, the circuit configuration can be made simple and therefore manufacturing cost can be lowered. In this arrangement, it is preferred that the resonant power converter further comprises a pair of auxiliary coils which are connected to the both ends of the secondary coil, respectively, and the drive signals are obtained from the opposite ends of the respective auxiliary coils which are not connected to the secondary coil. This makes it possible to amplify the drive signals generated at the resonance capacitor. Further, it is also possible to further comprises waveform processing means for producing pulse waves by processing and shaping the voltage drive signals to be supplied to the switching elements. In this waveform processing means, the voltage drive signals in the form of sinusoidal wave are compared with a predetermined reference value to produce the plus signals. Moreover, it is also preferred that the resonant transformer is composed of an ideal transformer and a resonant coil connected to the primary coil of the transformer, so that the series resonance occurs between the resonant coil and the resonance capacitor. In the arrangements described above, a MOS-FET is preferably used as each of the switching elements. These and other objects, structure and advantages of the present invention will be apparent from the following description of the preferred embodiments in conjunction with the appended drawings. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a circuit diagram which shows a first embodiment of a resonant power converter according to the present invention. Figs. 2(a) and 2(b) are an equivalent circuit of the circuit shown in Fig. 1, in which Fig. 2(a) shows the flow of the current at the interval between time t0 and time t1, and Fig. 2(b) shows the flow of the current at the interval between time t1 and time t2. Fig. 3(a) shows the flow of the current at the interval between time t2 and time t3, and Fig. 3(b) shows the flow of the current at the interval between time t3 and time t4. Fig. 4(a) shows the flows of the current at the interval between time t4 and time t5, and Fig. 4(b) shows the flow of the current at the interval between time t5 and time t0. Fig. 5 is a timing chart showing the operation of the circuit of this embodiment, in which (a) shows ON/OFF states of MOS-FET 1, (b) shows ON/OFF states of MOS-FET 2, (c) shows the voltage across the MOS-FET 2, (d) shows a waveform of the current in the primary side, and (e) shows a waveform of the voltage in the secondary side. Figs. 6(a) and 6(b) are a circuit diagram for explaining the flows of the current in the current doubler circuit in the resonant power converter of this embodiment, in which (a) shows a state of (+) input and (b) shows a state of (-) input. Fig. 7 is a circuit diagram of a modification of the resonant power converter shown in Fig. 1. Fig. 8 is a circuit diagram of a second embodiment of the resonant power converter according to the present invention. Fig. 9 is a circuit diagram which shows the flow of the current in a current doubler circuit of the second embodiment when one end P1 of the resonance capacitor C4 is positive voltage. Fig. 10 is a circuit diagram which shows the flow of the current in the current doubler circuit when the other end P2 of the resonance capacitor C4 is positive voltage. Fig. 11 is a timing chart which shows voltages in the form of sinusoidal wave which are generated across the resonance capacitor C4 and the timings of ON and OFF of each of the MOS-FETs 3 and 4. Fig. 12 is a circuit diagram which shows a first modification of the second embodiment of the present invention. Fig. 13 is a second modification of the second embodiment of the present invention. Fig. 14 is a timing chart which shows pulse voltages generated in the waveform processing circuit of the second modification. Fig, 15 is a circuit diagram which shows a third modification of the second embodiment of the present invention. Fig. 16 is a circuit diagram of the prior art resonant power converter. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, preferred embodiments of the present invention will be described with reference to the appended drawings. First, Fig. 1 is a circuit diagram showing the circuit configuration of a first embodiment of a resonant power converter according to the present invention. As shown in this circuit diagram, a resonant power converter 10 is equipped with a DC power source E1. two MOS-FETs 1, 2 (switching means) connected in series with respect to the DC power source E1, a voltage controlled oscillator (hereinafter, referred to as a VCO) 30 for controlling the frequency of the driving signals supplied to the MOS-FETs 1, 2, a capacitor C1 connected'in parallel with the MOS-FET 1, a capacitor C2 connected in parallel with the MOS-FET 2, and a transformer (resonant transformer) Tr1 which includes a primary coil (winding) L1 and a secondary coil (winding) L2. In this arrangement, one end of the primary coil L1 of the transformer Tr1 is connected to the junction between the MOS-FETs 1, 2, and the other end is connected to the negative side of the DC power source E1 via a capacitor C3. The VCO 30 turns the two MOS-FETs 1, 2 on and off by means of drive signals adjustably outputted with the same frequency as or a higher frequency than the resonance frequency of a resonance circuit constituted from leakage inductances (L11, L12) and a resonance capacitor (C4) described below. The resonance capacitor C4 is arranged at both ends of the secondary coil L2 of the transformer Tr1, and a current doubler circuit (current doubling circuit) which includes two diodes (rectifying means) D3, D4 and two choke coils L3, L4 (inductors) is also coupled to the ends of the secondary coil L2. The current doubler circuit is constructed from a first series circuit which includes the diode D3 and the choke coil L3, and a second series circuit which includes the diode D4 and the choke coil L4, wherein these two series circuits are connected in a parallel arrangement. In this arrangement, the junction between the diode D3 and the choke coil L3 is connected to one end of the secondary coil L2 of the transformer Tr1, and the junction between the diode D4 and the choke coil L4 is connected to the other end of the secondary coil L2. Further. a capacitor C5 is arranged between the junction of the diodes D3, D4 and the junction of the choke coils L3, L4, and both ends of the capacitor C5 form output terminals for connection to a load RL. In this arrangement, the voltage signals generated at the capacitor C5 are supplied to the VCO 30 via an amplifier 31. Next, the operation of the present embodiment will be described with reference to Figs. 2 to 4 which respectively show an equivalent circuit diagram of the circuit configuration of the power converter shown in Fig. 1 (In this regard, because a constant-current circuit is formed on the secondary side of the transformer Tr1 by the provision of the choke coils L3, L4, only a portion of the circuit in the left-side of the capacitor C4 need to be considered), and Fig. 5 which shows a timing chart showing the operation of the circuit of this embodiment. Now, if the transformer Tr1 shown in Fig. 1 has a coupling coefficient K and a conversion is carried out for the primary side, then the transformer Tr1 can be represented by two leakage inductances L11, L12 (L11, L12 = (1 - K) × L1) and a main inductance L13 (L13 = K × L1) connected in a T-shaped arrangement. Further, the resonance capacitor C4 shown in Fig. 1 can be represented by the capacitor C11 (C11 = C4/N 2 , where N is the winding ratio of the transformer Tr1). Furthermore, in Figs. 2 to 4, D1 is a body diode for the MOS-FET 1 and D2 is a body diode for the MOS-FET 2. In this connection, Fig. 5(a) shows the ON - OFF states of the MOS-FET 1, Fig. 5(b) shows the ON - OFF states of the MOS-FET 2, Fig. 5(c) shows the voltage across the MOS-FET 2, Fig. 5(d) shows a waveform of the current in the primary side, and Fig. 5(e) shows a waveform of the voltage in the secondary side. As shown in Fig. 5, under the control by the VCO 30, drive signals like those shown in Fig. 5(a) and (b), namely, drive signals which switch the MOS-FET 1 to an OFF state after the MOS-FET 1 has been in an ON state for a prescribed time, and drive signals which switch the MOS-FET 2 to an ON state after a predetermined delay from the time of point that the MOS-FET 1 has been in the OFF state are generated and outputted. (That is, the two MOS-FETs 1, 2 are never in an ON state at the same time). When these drive signals are given, the MOS-FET 1 is turned on at time t0 (at which time the MOS-FET 2 is in an OFF state), so that a resonance current i1 will flow from the positive side of the DC power supply E1 (where the voltage is V in ) to the negative side thereof via the MOS-FET 1, the leakage inductances L11, L12 and the capacitors C11, C3 as shown in Fig. 2(a). At this time, the capacitor C2 is charged by the resonant current to establish a voltage V in thereon, and as shown in Fig. 5(c), the voltage V ds (drain-to-source voltage) of the MOS-FET 2 is V in volts. Then, since the MOS-FET 1 is turned off at time t1 (and at this time the MOS-FET 2 is also in an OFF state), the discharge current i3 of the capacitor C2 and the charging current i2 of the capacitor C1 flow as a resonance current as shown in Fig. 2(b). Then, when the voltage of the capacitor C2 becomes 0 at time t2, a resonance current i4 begins to flow via the body diode D2 as shown in Fig. 3(a). At this time, the voltage V ds of the MOS-FET 2 has become 0 volts. Therefore, if the MOS-FET 2 is switched to an ON state within the time interval between time t2 and time t3, it becomes possible to carry out zero voltage switching, and this makes it possible to reduce power loss. Next, when the MOS-FET 2 is turned on at time t3, charge stored in the capacitor C3 is discharged, so that a resonance current i5 begins to flow via the MOS-FET 2, as shown in Fig. 3(b), in a direction opposite to those currents that flowed up to time t3. At this time, the capacitor C1 is charged by the resonance current to establish a voltage V in thereon. Then, when the MOS-FET 2 is turned off at time t4, the charge stored in the capacitor C1 is discharged, and this causes currents 16, i7 to flow as shown in Fig. 4(a), whereby the capacitor C2 is charged to establish a voltage V in thereon. Further, as shown in Fig. 5(c), when the drain-to-source voltage V ds of the MOS-FET 2 becomes V in volts, a resonance current i8 begins to flow via the body diode D1 as shown in Fig. 4(b). At this time, because the voltage V ds of the MOS-FET 1 becomes 0 volts, it becomes possible to carry out zero voltage switching if the MOS-FET 1 is turned on within the time interval between time t5 and time t6(t0). Then, when the MOS-FET 1 is switched to an ON state again, the operations described above with reference to Figs. 2 to 4 are repeated, and this makes it possible to obtain a primary current having a sinusoidal waveform like that shown in Fig. 5(d), and a secondary voltage having a sinusoidal waveform like that shown in Fig. 5(e). As can be understood from these drawings, because the timing of the primary side switching is not synchronized with the timing of the secondary side switching, the switching noise generated at the primary side and the switching noise generated at the secondary side will not be superposed with each other, and this makes it possible to diffuse noise. Further, because a resonance current continues to flow without interruption via the leakage inductances L11, L12, it is possible to prevent the generation of ringing noise in the secondary voltage waveform. Figs. 6(a) and (b) are circuit diagrams which show the operation of the current doubler circuit. Hereinbelow, the operation of a portion of the circuit which is the right side of the capacitor C4 shown in Fig. 1 will be described with reference to Figs. 6(a) and 6(b). Now, in the case where the voltage of the capacitor C4 is positive, a current i11 flows via the choke coil L3, the capacitor C5 and the diode D4, and a loop current i12 flows via the capacitor C5, the diode D4 and the choke coil L4 as shown in Fig. 6 (a). As a result, the current (i11 + i12) flows through the load RL, whereby the value of the current is doubled. Further, in the case where the voltage of the capacitor C4 is negative, a current i13 flows via the choke coil L4, the capacitor C5 and the diode D3, and a loop current i14 flows via the capacitor C5, the diode D3 and the choke coil L3 as shown in Fig. 6(b). As a result, the current (i13 + i14) flows through the load RL, whereby the value of the current is doubled. At this time, because the current i13 and the current i14 have mutually symmetrical waveforms, the current (i13 + i14) obtained by the addition of such currents creates a flat DC voltage. Namely, it is possible to achieve zero ripple. In this way, the capacity of the output capacitor C5 can be made small. In the resonant power converter 10, the frequency of the drive signals supplied to each of the MOS-FETs 1, 2 can be changed under the control by the VCO 30. Then, by adjusting the frequency of the drive signals, it is possible to adjust the output voltage. For example, in the case where the frequency of the drive signals is raised, the impedance of the resonance circuit is increased, so that the voltage generated at the secondary side is reduced. In this way, it becomes possible to supply a regulated output voltage. In the example described above, the diodes D3 and D4 are used as rectifying means, but it is also possible to use other means to carry out synchronous rectification of the current. For example, switching elements such as transistors (including MOS-FET) or thyristors can be used for carrying out synchronous rectification of the current. As described above, in the resonant power converter according to the present embodiment, the resonance capacitor C4 is provided in the secondary side of the transformer Tr1 so that a resonance current is generated by utilizing the resonance phenomenon between the capacitor C4 and the leakage inductances (L11, L12) of the transformer Tr1. Therefore, the resonance current does not flow through the main inductance L13 (see Fig. 2), and thereby the excitation current of the transformer Tr1 does not increase. Accordingly, the transformer Tr1 can be made more compact, and this makes it possible to lower manufacturing costs. Further, a sinusoidal waveform voltage is generated across the resonance capacitor C4 provided in the secondary side. Therefore, if this voltage is utilized to drive switching elements (such as MOS-FETs, thyristors or the like which are used as rectifying means), it is possible to easily carry out synchronous rectification for the current flowing through the switching elements. Namely, when the voltage waveform (sinusoidal wave) generated across the capacitor C4 is used as drive signals, it is possible to drive the MOS-FETs using the drive signals. As a result, it is not necessary to provide a separate drive circuit for driving the MOS-FETs, thereby enabling to simplify the overall circuit structure. This will be discussed in more details with reference to the second embodiment described below. Furthermore, because it is possible to achieve zero ripple, the capacity of the output capacitor C5 can be made small. Further, because the current flowing through the choke coils L3 and L4 is the same DC current, the magnetic fluxes passing (current flowing) through the central pole portion of the EI-core of each of the choke coils L3, L4 is reduced. This makes it possible to use an EI-core having a smaller central pole portion, thereby enabling to reduce the size of the choke coils. Further, because the resonance current of the secondary side is supplied as a load current, it is possible to regulate the current value regardless of the load. Namely, even when the load fluctuates, a current larger than such resonance current does not flow. Therefore, even in the case where an overload happens at the output side, an excessive current flow will not occur, and operations are carried out to lower the power source voltage, thereby enabling to protect the circuit of the power converter. Next, Fig. 7 is a circuit diagram showing a modified structure of the resonant power converter 10 described above. In comparison with the resonant power converter 10 shown in Fig. 1, the resonant power converter 20 shown in Fig. 7 has an ideal transformer Tr2 (i.e., a transformer which does not have leakage inductance) in place of the transformer Tr1 which has leakage inductance, and the primary winding of this ideal transformer Tr2 is connected to a resonance coil L31. Further, because the equivalent circuit for this structure is the same as the circuit shown in Figs. 2 to 4 (in which the combined inductance of the inductances L11 and L12 correspond to the inductance of the resonance coil L31), a current flowing through the secondary side of the transformer Tr2 can be made series resonance between the resonance coil L31 and the resonance capacitor C4. Accordingly, this structure also makes it possible to achieve the same results as those described above for the structure shown in Fig. 1. Now, in the embodiment and its modification described above, two MOS-FETs 1, 2 are used as switching means, and a half bridge circuit is used, but it should be noted that the present invention is not limited to such structure, and it is possible to use other elements such as an IGBT as switching means. Further, it is also possible to use four switching means to form a full bridge circuit. Hereinbelow, a description will be made with regard to the second embodiment of the present invention based on Fig. 8 to Fig. 15. In this connection, it is to be noted that the same or corresponding components or parts as those of the first embodiment are designated with the same reference numerals. Fig. 8 is a circuit diagram which shows the second embodiment of the resonant power converter of the present invention. As is the same with the first embodiment shown in Fig. 1, the resonant power converter 100 is equipped with a DC power source E1, two MOS-FETs 1, 2 (switching means) connected in series with respect to the DC power source E1, a voltage controlled oscillator (hereinafter, referred to as a VCO) 30 for controlling the frequency of the driving signals supplied to the MOS-FETs 1, 2, a capacitor C1 connected in parallel with the MOS-FET 1, a capacitor C2 connected in parallel with the MOS-FET 2, and a transformer (resonance transformer) Tr1 which includes a primary coil (winding) L1 and a secondary coil (winding) L2. In this arrangement, one end of the primary coil L1 of the transformer Tr1 is connected to the junction between the MOS-FETs 1, 2, and the other end is connected to the negative side of the DC power source E1 via a capacitor C3. In the secondary side of the circuit, a resonance capacitor C4 is coupled to the both ends of the secondary coil L2 of the transformer Tr1 so as to form parallel connection with respect to the secondary coil L2. Further, a pair of MOS-FETs for synchronous rectification (switching means for synchronous rectification) 3, 4 which are serially connected with each other are also connected to the both ends of the secondary coil L2. Furthermore, a pair of choke coils L3 and L4 which are serially connected are also connected to the both ends of the secondary coil L2. In addition, a capacitor C5 is arranged between the junction between the MOS-FETs 3, 4 and the junction between the choke coils L2, L3. The opposite ends of the capacitor C5 form output terminals for connection with a load RL. Moreover, one end P1 of the resonance capacitor C4 is connected to a gate of the MOS-FET 4 and the other end P2 of the resonance capacitor C5 is connected to a gate of the MOS-FET 3 for providing drive signals for synchronous rectification. An output voltage (a voltage applied to the load RL) is also supplied to a VOC 30 via an amplifier 7. The VCO 30 turns the two MOS-FETs 1, 2 ON and OFF by means of drive signals adjustably outputted with the same frequency as or a higher frequency than the resonance frequency of a resonance circuit constituted from leakage inductances (L11, L12) and the resonance capacitor (C4) described below. The frequency is adjusted in response to the voltage to be applied to the load RL to regulate an output voltage. In this regard, it is to be noted that the circuit shown in Fig. 8 can be represented with the same equivalent circuit as that of the circuit 1 shown in Fig. 1. Therefore, the operations of the circuit (that is, a portion of the circuit in the left side of the capacitor C4) shown in Fig. 8 can be represented by the equivalent circuit shown in Fig. 2 to Fig. 4 described above, and the timing chart shown in Fig. 5 is also applicable to this circuit configuration. Accordingly, as see from Fig. 5, a voltage in the form of the sinusoidal waveform is generated across the resonance capacitor C4, and in this embodiment the voltage is utilized as drive signals for the MOS-FETs 3, 4 for synchronous rectification. Fig. 9 and Fig. 10 respectively show the operations of the doubler current rectification circuit of this embodiment, and Fig. 11 is a timing chart which shows ON/OFF states of the MOS-FETs 3, 4 and the sinusoidal waveform voltage generated across the resonance capacitor C4. Hereinbelow, the operations of a portion of the circuit in the right side of the capacitor C4 will be explained with reference to these drawings. When the voltage at one end P1 of the resonance capacitor C4 is a positive voltage, a drive signal is supplied to the gate of the MOS-FET 4 within the time interval between time t11 and time t 12 (corresponding to a half-wave part of the sinusoidal waveform voltage), the MOS-FET 4 is turned on (at this time, MOS-FET 3 is in an off state). As a result, as shown in Fig. 9, a current i11 flows via the choke coil L3, the load RL (capacitor C5) and the MOS-FET 4, and a loop current i12 also flows via the capacitor C5, the MOS-FET 4 and the choke coil 4. Therefore, an added (combined) current (i11 + i12) flows through the load RL, so that the current value becomes double to achieve a doubler current. At this time, since a voltage drop in the current flowing through the MOS-FET 4 is very small, it is possible to reduce switching loss. Further, since the current i11 and the current i12 have symmetrical waveforms with each other, the added current (i11 + i12) generates a flat direct voltage. That is, zero ripple can be achieved. In this way, the capacity of the output capacitor C5 can be made small. Further, when the other end P2 of the resonance capacitor C4 is a positive voltage, a drive signal is supplied to the gate of the MOS-FET 3 within the time interval between time t12 and time t13, as shown in Fig. 11, so that the MOS-FET 3 is turned on (at this time, the MOS-FET 4 is in OFF state). As a result, as shown in Fig. 10, a current i13 flows via the choke coil L4, the load RL (capacitor C5) and the MOS-FET 3, while a loop current i14 flows via the capacitor C5, the MOS-FET 3, and the choke coil L3. As a result, an added (combined) current (i13 + i14) flows through the load RL, the current value becomes double. At this time, since a voltage drop in the current flowing through the MOS-FET 3 is very small, it is possible to reduce switching loss. As described above, in the resonant power converter 100 using the synchronous rectification according to this embodiment, the resonance capacitor C4 is arranged at the secondary side of the transformer Tr1 (that is, the resonance capacitor C4 is connected in parallel with the secondary coil L2 of the transformer Tr1) so that a resonance current is generated by using the resonance phenomenon occurring between the resonance capacitor C4 and the leakage inductances (L11, L12) of the transformer Tr1. Further, since the MOS-FETs 3, 4 are driven using the sinusoidal voltage waveform generated across the capacitor C4 to perform synchronous rectification, the current flowing through the secondary side of the transformer Tr1 can be rectified without providing a separate drive circuit. In this regard, it is to be noted that since the MOS-FETs 3, 4 have a smaller switching resistance and therefore a voltage drop is small, it is possible to improve conversion efficiency of the power converter drastically. Further, since zero ripple is achieved, a capacity of the output capacitor can be made small. Fig. 12 is a circuit diagram which shows a circuit configuration of a resonant power converter 110 using synchronous rectification which is a first modification of the resonant power converter 100 of the second embodiment. As shown in this figure, in this modification a pair of auxiliary coils (windings) L5, L6 are respectively connected to the both ends of the secondary coil L2 of the transformer (resonant transformer) Tr1, and voltage signals generated at each of the ends of these coils which are opposite to their connecting ends to the secondary coil L2 are supplied to the gates of the MOS-FETs 3, 4, respectively. Since other structure of the circuit is the same as that of the circuit shown in Fig. 8, a detailed description thereof has been omitted. According to the circuit configuration of this first modification, the voltage generated across the opposite ends of the two auxiliary coils L5, L6 corresponds to a voltage which is obtained by amplifying the voltage generated across the resonance capacitor C4. Therefore, by using this voltage, it is also possible to drive the MOS-FETs 3, 4 reliably even in the case where the voltage value generated across the capacitor C4 is small. Fig. 13 is a circuit diagram which shows a resonant power converter 120 using synchronous rectification which is a second modification of the resonant power converter 100 of the second embodiment shown in Fig. 8. As shown in this figure, in this second modification, the both ends of the resonance capacitor C4 are connected to a waveform processing circuit (waveform processing means) 6, and other structure is the same as that of the circuit shown in Fig. 8. In this regard, Fig. 14 is a timing chart which shows a waveform of an input voltage and a waveform of an output voltage to and from the waveform processing circuit 6. The waveform processing circuit 6 has a comparing means which compares the sinusoidal voltage obtained across the capacitor C4 with a predetermined reference voltage V ref . When the obtained voltage value is higher than the reference voltage V ref , a high level signal "H" is outputted, while when the obtained voltage value is lower than the reference voltage V ref , a low level signal "L" is outputted. Specifically, as shown in the timing chart (a) of Fig. 14, the voltage signal S1 obtained at one end P1 of the capacitor C4 is compared with the reference voltage V ref and thereby a high level pulse signal "H" is obtained when the equation S1 > V ref is satisfied. With this result, as shown in (b) of the figure, a voltage signal S2 in the form of a pulse wave is obtained. In this pulse wave S2. each pulse has a leading edge which is raised slightly later than the leading edge of the voltage signal S1 and a trailing edge which is lowered slightly earlier than the trailing edge of the voltage signal S1. The MOS-FET 4 is driven by this voltage signal S2. As is the same with the above, the voltage signal S3 (see Fig. 13 (c)) obtained at the other end P2 of the capacitor C4 is compared with the reference voltage V ref and thereby a high level signal "H" is obtained when the equation S3 > V ref is satisfied. With this result, as shown in (d) of the figure. a voltage signal S4 in the form of a pulse wave is obtained. In this pulse wave S4, each pulse has a leading edge which is raised slightly later than the leading edge of the voltage signal S3 and a trailing edge which is lowered slightly earlier than the trailing edge of the voltage signal S3. The MOS-FET 3 is driven by this voltage signal S4. As described above, since the pulse signal S4 for driving the MOS-FET 3 is raised at a point time tp slightly after S2 has become zero ("L" level) and the pulse signal S2 for driving the MOS-FET 4 is raised at a point of time tp slightly after S2 has become zero ("L" level), it is possible to avoid the case where the two MOS-FETs 3, 4 are turned on at the same time, thus enabling to prevent generation of cross-conduction. Further, a MOS-FET needs a high gate voltage for turning it on. Therefore, if such MOS-FET is used as a switching element, it is possible to obtain the result as shown in Fig. 14. Fig. 15 is a circuit diagram which shows a resonant power converter 130 using synchronous rectification which is a third modification of the resonant power converter 100 of the first embodiment shown in Fig. 8. As shown in this figure, this resonant power converter 130 is composed of an ideal transformer Tr11 (a transformer having no leakage inductance) and a resonant coil L21 which is connected to a primary coil of the ideal transformer Tr11. Other structure of this circuit is the same as that of the circuit shown in Fig .8. While the circuit configuration shown in Fig. 8 has the structure in which a current flowing through the secondary side of the transformer Tr1 performs series resonance between the leakage inductance of the transformer Tr1 and the resonance capacitor C4, the circuit configuration shown in Fig. 15 has a structure in which a current flowing through the secondary side of the transformer Tr1 performs series resonance between the resonance coil L21 and the resonance capacitor C4. Since an equivalent circuit of this circuit configuration is the same as that shown in Figs. 2 to 4, the same results as those described above with reference to the second embodiment and its modifications can be obtained. In the above embodiment and modifications thereof, MOS-FETs 3, 4 are used as switching elements for synchronous rectification, the present invention is not limited thereto, and it is also possible to use transistors or thyristors other than MOS-FETs. Further, although the first modification of the second embodiment shown in Fig. 12 uses the auxiliary coils L5, L6 and the second modification shown in Fig. 13 uses the waveform processing circuit 6, it is possible to use combination of these coils L5, L6 and the waveform processing circuit 6. That is, the present invention includes the case that such auxiliary coils L5, L6 and the waveform processing circuit 6 are incorporated into a single circuit. As described above, according to the second embodiment of the present invention, since the voltage signal in the form of sinusoidal wave generated across the resonance capacitor arranged at the secondary side of the transformer is used to drive the switching elements for synchronous rectification to rectify the current flowing the doubler current circuit at the secondary side of the circuit, a voltage drop can be drastically reduced as compared with the conventional circuit using diodes and thereby it is possible to improve the conversion efficiency of the power converter remarkably. Further, there is no need to provide a separate drive circuit for driving the switching elements, the circuit configuration can be made simple and therefore manufacturing cost can be lowered. Further, in the case where the two auxiliary coils are respectively connected to the opposite ends of the secondary coil as the second modification, the voltage generated across the resonance capacitor can be amplified. Therefore, even in the case where the voltage across the capacitor is small, it is possible to drive the switching elements for synchronous rectification reliably. Furthermore, in the case where the waveform processing means is arranged at the subsequent stage of the resonance capacitor to produce pulse wave for driving the two switching elements for synchronous rectification by using the waveform processing means as the second modification, a very short delay is produced between the OFF-timing of one switching element and the ON-timing of the other switching element, so that it is possible to reliably turn on the other switching element after the one switching element has been turned off, thus resulting in reducing generation of cross-conduction. Finally, it is also to be noted that the present invention is not limited to the embodiments and modifications thereof as described above, and many changes and additions may be made without departing from the scope of the present invention which will be determined by the following claims.

Claims: A resonant DC power converter (10, 20, 100, 110, 120, 130) having a primary side and a secondary side, comprising: an input power source (E1) provided in the primary side; switching means (1, 2) provided in the primary side and connected to the input power source (E1), the switching means comprised of a first MOS-FET (1) and a second MOS-FET (2) which are connected in series with respect to the input power source (E1); means (30) for driving the first and second MOS-FETs (1) (2) for providing drive signals to each of the first and second MOS-FETs (1) (2) so that the first and second MOS-FETs (1) (2) are never in an ON state at the same time in a switching period; a resonant transformer (Tr1, Tr2) having a primary coil (L1) and a secondary coil (L2); and a resonance capacitor (C4) which is provided in the secondary side and is connected in parallel to the secondary coil (L2) of the resonant transformer (Tr1, Tr2) so that series resonance occurs in a current flowing through the secondary side of the power converter (10, 20, 100, 110, 120, 130), characterized in that , the primary side of the power converter (10, 20, 100, 110, 120, 130) comprises first to third capacitors (C1 to C3), in which the first capacitor (C1) is connected in parallel with the MOS-FET (1), the second capacitor (C2) is connected in parallel with the MOS-FET (2) and the third capacitor (C3) is connected between one end of the primary coil (L1) and the input power source (E1), and the other end of the primary coil (L1) is connected to a junction between the MOS-FETs (1, 2) and a junction between the first and second capacitors (C1 and C2), so that the series resonance occurs throughout the switching period in cooperation with these capacitors (C1 to C4). The power converter (20) as claimed in claim 1, wherein the resonant transformer is constructed from an ideal transformer (Tr2) and a resonant coil (L31) arranged in the primary side of the ideal transformer Tr2), so that the series resonance occurs between the resonant coil (L31) and the resonance capacitor (C4). The power converter (10, 100, 110, 120, 130) as claimed in claim 1, wherein the resonant transformer (Tr1) has leakage inductances, and the series resonance of the current occurs between the leakage inductances and the resonance capacitor (C4). The power converter (10, 20) as claimed in claim 1, further comprises a current doubler circuit for making the current flowing through the secondary side double, said current doubler circuit being provided in the secondary side and coupled to the both ends of the resonance capacitor (C4). The power converter (10, 20) as claimed in claim 4, wherein the current doubler circuit includes a pair of circuits each having a rectifying means (D3, D4) and an inductance (L3, L4), in which these circuits are connected in parallel with each other so that a junction between the rectifying means (D3) and inductance (L3) of one circuit and a junction between the rectifying means (D4) and inductance of the other circuit are respectively connected to the both ends of the secondary coil (L2). The power converter (10, 20, 100, 110, 120, 130) as claimed in claim 1, wherein the switching means is formed into a bridge type comprised of the first and second MOS-FETs (1,2). The power converter (100, 110, 120, 130) as claimed in claim 1, further comprises means for performing synchronous rectification for the current flowing the secondary side, said means including switching elements (3, 4) provided in the secondary side so as to be driven by drive signals responsive to the voltage generated across the resonance capacitor (C4) and having a sinusoidal waveform. The power converter (100, 110, 120, 130) as claimed in claim 7, wherein said synchronous rectification performing means includes a pair of switching elements (3, 4) for synchronous rectification, and these switching elements (3, 4) are driven by the drive signals. The power converter (110) as claimed in claim 8, further comprises a pair of auxiliary coils (L5, L6) which are connected to the both ends of the secondary coil (L2), respectively, and the drive signals are obtained from the opposite ends of the respective auxiliary coils (L5, L6) which are not connected to the secondary coil (L2). The power converter (120) as claimed in claim 8, further comprises waveform processing means (6) for producing pulse waves by processing and shaping the voltage drive signals to be supplied to the switching elements (3, 4). The power converter (120) as claimed in claim 10, wherein the waveform processing means (6) compares the voltage drive signals in the form of sinusoidal wave with a predetermined reference value to produce the plus signals. The power converter (130) as claimed in claim 8, wherein the resonant transformer is composed of an ideal transformer (Tr11) and a resonant coil (121) connected to the primary coil of the transformer (Tr11), in which the series resonance occurs between the resonant coil (121) and the resonance capacitor (C4). The power converter as claimed in claim 8, wherein each of the switching elements (3, 4) includes a MOS-FET.

Inventors: TERASHI HIROTO, TERASHI, HIROTO, Terashi, Hiroto Densei-Lambda Kabusiki Kaisha
Applicants: DENSEI LAMBDA K K, DENSEI-LAMBDA K.K.
Application year: 2001
Main classification: H02M7
IPC codes: H02M3