SYSTEM WITH MICROCODE MULTI-WAY BRANCHING CAPABILITY

Abstract: An apparatus for and method of accommodating branching (10) within an instruction processor having a microprogrammed and pipelined architecture. The technique involves defining instructions as either normal mode or xway mode (Fig. 2). A single bit position (112) within each microinstruction defines the mode for that microinstruction. The complex xway mode is reserved for complex branches and particular conditional branches which are likely to benefit from permitting branching on each clock cycle. A Look Up Table (LUT) (102) is utilized to limit the number of required microcode bit positions.

Description: SYSTEM WITH MICROCODE MULTI-WAY BRANCHING CAPABILITY CROSS REFERENCE TO CO-PENDING APPLICATIONS None. BACKGROUND OF THE INVENTION 1. Field of the Invention - The present invention generally relates to methods and apparatus for implementing branching within an instruction processor and more particularly relates to branching in an instruction processor which employs a microprogrammed and pipelined architecture. 2. Description of the Prior Art - It is known in the prior art to develop instruction processors having a microprogrammed architecture. Using this technique, the basic instruction set of the instruction processor, which -is available for , software development, is provided by a microprogrammed processor. The instruction set of the microprogrammed processor is much more basic than that made available for software development. The execution of each software instruction is accomplished through the execution of a set of microprogrammed instructions . This architectural technique can provide instruction processors having a number of different software environments from microprogrammed processors of a common design. This approach can reduce recurring costs and instruction processor development times, as well as improving maintenance and reliability. A common practice in the design of instruction processors employing microprogrammed architectures is "" " " pipelining". This is a technique wherein a number of sequential instructions are processed simultaneously. If, for example, instruction processing requires three distinct operations (e.g., instruction fetch, operand fetch, and operand arithmetic operation) , a first instruction may be involved in step three (i.e., operand arithmetic operation), while a second instruction is involved in step two (i.e., operand fetch) , and while a third instruction is involved in step one (i.e., instruction fetch). When the machine instructions are sequential, a three way pipeline as suggested in the example above can operate three times faster than a non-pipelined machine having the same clock speed. This occurs because a new instruction fetch is performed each new clock cycle. Similarly, an operand fetch occurs each clock cycle, and an operand arithmetic operation occurs each clock cycle. Therefore, even though a single given instruction requires three complete clock cycles, the equivalent of three instructions are performed during those three clock cycles . Unfortunately, the optimum performance of the pipelined architecture is only available for sequential instructions. Most commonly, whenever a branch occurs, the instructions are executed in a non-sequential fashion, by definition. Most problematic for highly pipelined architectures are conditional branches or jumps. A conditional branch is an instruction which cause a branch if and only if a particular arithmetic, logical, or status condition is met. The difficulty with conditional branches is that the later stages of the conditional branch instruction pipeline (e.g., the operand fetch and operand arithmetic operation) must be performed before it can be determined whether the branch is to occur. Most commonly, branches are accommodated within pipelined architectures by the " " " " de-piping," of subsequent and therefore not to be executed instructions . This wastes the time associated with reestablishing the pipeline at the branched to instructions. Thus, if branches could be known earlier within the pipelined execution of the branch instruction, some of the de-piping time could be saved. SUMMARY OF THE INVENTION The present invention overcomes many of the disadvantages associated with the prior art by providing a method of and apparatus for branching within an instruction processor employing a microprogrammed and pipelined architecture. The preferred mode of the present invention provides branch control information one cycle earlier than found in the prior art. This overcomes the latency involved in reading the control information from the microcode RAM. Thus, the system can branch on every machine cycle rather than on every other machine cycle. The number of bits required of the microcode is limited through the use of a Look Up Table (LUT) . The present invention utilizes a technique of microprocessed control which divides all instructions into "" ^ normal 11 and ^ xway' 1 modes. A single microcode bit within each microinstruction indicates which mode is associated with that particular microinstruction. Most instructions (including branching instructions) are handled under ~ " normal" mode of the microcode control. Normal mode may be capable of branch operations such as call/return operations; GOTO (conditional or unconditional) ; and 2way, 4way, 8way, etc. branching where the control is from the ucode address 2 cycles before. " """ Xway" mode is reserved for instructions (or parts of instructions) that require considerable conditional branching and that can gain performance by being able to branch in an xway form on each cycle . The present invention requires two features to enable branching on eve'ry cycle: l. All branching in the " "^ xway" mode is to b e defined in the form ^ goto target, xway" . The system can be defined to handle all branching as 8way branches, with 4way, 2way, and plain GOTO's being considered simplified 8way branches. 2. All information on the branching to be done is contained in the ucode or pointed to by that ucode in the address one cycle earlier than would be indicated by a functional flowchart of the instruction branching. In accordance with the present invention, the prior art technique of not permitting branches on every clock cycle to improve efficiency by limiting latency, is superceded by permitting branching on any clock cycle without an increase in latency. BRIEF DESCRIPTION OF THE DRAWINGS Other objects of the present invention and many of the attendant advantages of the present invention will be readily appreciated as the same becomes better understood by reference to the following detailed description when considered in connection with the accompanying drawings, in which like reference numerals designate like parts throughout the figures thereof and wherein: FIG. 1 is a functional block diagram including up to 8way branching; FIG. 2 is a functional block diagram of the preferred embodiment; FIG. 3 is a table showing ucode control fields and associated LUT hardware; and FIG. 4 is a timing diagram. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The detailed descriptions which follow are presented largely in terms of algorithms and symbolic representations of operations on data bits within a computer memory. These algorithmic descriptions and representations are the means used by those skilled in the data processing arts to most effectively convey the substance of their -work to others skilled in the art. An algorithm is here, generally, conceived to be a self- consistent sequence of steps leading to a desired result. These steps are those requiring physical manipulations of physical quantities. Usually, though not necessarily, these quantities take ' the form of electrical or magnetic signals capable of being stored, transferred, combined, compared, and otherwise manipulated. It proves convenient at times, principally for reasons of common usage, to refer to these signals as bits, values, elements, symbols, characters, terms, numbers or the like. It should be kept in mind, however, that all of these and similar terms are to be associated with the appropriate physical quantities and are merely convenient labels applied to these quantities. Furthermore, the manipulations performed are often referred to in terms, such as adding or comparing, which are commonly associated with mental operations performed by a human operator. No such capability of a human operator is necessary, or desirable in most cases, in any of the operations described herein which form part of the present invention; the operations are machine operations. Useful machines for performing the operations of the present invention include general purpose digital computers or other similar devices. In all cases, it should be kept in mind the distinction between the method operations in operating a computer and the method of computation itself. The present invention related to method steps for operating a computer in processing electrical or other (e.g., mechanical, chemical) physical signals to generate other desired physical signals. The present invention also relates to apparatus for performing these operations . This apparatus may be specially constructed for the required purposes or it may comprise a general purpose computer as selectively activated or reconfigured by a computer program stored in the computer. The algorithms present herein are not inherently related to a particular computer system or other apparatus. In particular, various general purpose computer systems may be used with computer programs written in accordance with the teachings of the present invention, or it may prove more convenient to construct more specialized apparatus, to perform the required method steps. The required structure for such machines will be apparent from the description given below. FIG. 1 is a functional block diagram 10 showing up to 8way branching. The GOTO instruction is presented to function code element 14 for decoding at path 12.. The ""E" decoder, consisting of EO 18, El 20, E2 22, and E3 24, performs the initial routing. EO 18 routes an 8way to BO 58 of the ""B" decoder. El 20 routes to A0 26 of the "A" decoder. E2 22 routes to A5, and E3 24 reroutes to the input of the ""E" decoder. The ""A" decoder consists of A0 26, Al 28, A230, A3 32, A4 34, A5 36, A6 38, and A740. The ""B" decoder contains B0 58, Bl 60, B2 62, B3 64, B4 66 , B5 68, B6 70, and B7 72. The "C" decoder contains CO 74, Cl 76, C2 78, C3 80, C4 82, C5 84, C6 86, and C7 88. The ""D" consists of DO 42, Dl 44, D2 46, D3 48, D4 50, D5 52, D6 54, and D7 56. The decoder elements are linked as shown. The END decode signal is presented on path 90. FIG. 2 is a functional diagram of the preferred mode of the present invention. Shown are the pathways associated with branching in the ""xway" mode. However, not shown are all of the paths needed to operate in the ""normal" mode. The encoded data is retrieved from the branch LUT 102 and presented to multiplexer 94 via path 92. The selection made from multiplexer 94 is controlled by the output of multiplexer 96 via path 98. This selection comes from the eight pointer inputs to multiplexer 96 received via path 100. Selection is made from output 144 of flip-flop 140. The nine bit address selected by multiplexer 94 is presented as an input to multiplexers 104, 114, and 116. Gate 126 switches the output of multiplexer 104 via path 106 to register 130. Gate 126 responds to the output of multiplexer 120 via path 138. Multiplexer 120 selects one of the targets received from the conditional branching logic 118 based upon the output of multiplexer 116 received via path 124. The output of register 130 is transferred via path 132 to the microcode storage 134. The selected data is buffered by flip-flop 136 and output on paths 146 and 148. Similarly, multiplexer 122 selects the branch type based upon the output of multiplexer 116. The selected data are transferred to register 140 for output via paths 142 and 144. Fig 3 is ,a table showing ucodes and associated LUT hardware. Subtable 150 shows the 4way branch from the function code to the LUT pointers for each of the four possible targets of the branch (see also Fig. 1, references 12, 14, 16, 18, 20, 22, and 24) . The pointers indicate the addresses in the LUT that contain target, branch type, and branch variables which are used to exit each of the function codes possible targets . Subtable 152 shows the output from El 20 to A026. This eight way branch contains pointers into the LUT for each of the eight possible targets of the branch. The pointers indicate the addresses in the LUT that contain target, branch type, and branch variables which are used to exit each of El 20' s possible targets. Al 28 and A2 30 decodes are found in subtable 154. From both Al 28 and A2 30 an 8way branch is made to BO 58 (see also Fig. 1) . Each microcode address (label) contains ""Look Ahead One ' ' branch pointers . The operation of the Look Up Table (LUT) is shown in subtable 156 containing columns 158, 160, and 162. The LUT contains information associated with each microcode address (label) , which functions as a branch target (8way, 4way, 2way or GOTO) . The LUT information describes how each target is accessed. A target may be accessed from multiple locations, but each access for a particular target must employ identical branch functionality (see also Figs. 1 and 2) . FIG. 4 is a' self-explanatory timing diagram for the above described logic. Having thus described the preferred embodiments of the present invention, those of skill in the art will readily appreciate that the teachings found herein may be applied to yet other embodiments within the scope of the claims hereto attached. WE CLAIM;

Claims: 1. In a data processing system having an instruction processor which is implemented using a microprogrammed and pipelined architecture, the improvement comprising: a. A normal mode; b. An xway mode; and c. A microprogramming bit which defines between said normal mode and said xway mode. 2. The improvement according to claim 1 further comprising a Look Up Table (LUT) . 3. The improvement according to claim 2 wherein said xway mode is reserved for instructions requiring considerable conditional branching. 4. The improvement according to claim 3 wherein said normal mode allows unconditional branching. 5. The improvement according to claim 4 wherein said LUT decreases the number of microcode bits. 6. An apparatus comprising: a. An instruction processor for executing software instructions ; b. A pipelined microprocessor within said instruction processor for emulating said software instructions by executing microinstructions; and c. A bit position within said microinstructions for indicating whether any particular microinstruction is normal mode or xway mode. 7. An apparatus according to claim 6 further comprising an LUT within said pipelined microprocessor. 8. An apparatus according to claim 7 wherein all microinstructions in said xway mode are defined in the form goto target, xway. 9. An apparatus according to claim 8 wherein said LUT is associated with target addresses rather than come from addresses . 10. An apparatus according to claim 9 wherein said branches within said xway mode are defined as 8way. 11. A method of processing a branch instruction within a pipelined, microprogrammed instruction processor comprising: a. Determining whether said branch instruction is a normal mode instruction or an xway mode instruction; and b. Permitting a branch at any clock cycle when said determining step determines that said branch instruction is an xway mode instruction. 12. A method according to claim 11 further comprising: d. Defining a bit position to identify xway mode instructions . 13. A method according to claim 12 further comprising utilizing a Look Up Table to execute said branch instruction. 14. A method according to claim 13 wherein said utilizing step further comprises looking up information associated with each microcode address. 15. A method according to claim 13 wherein said looking up step further comprises accessing a branch target. 16. An apparatus comprising: a. Means for providing a branch instruction; b. Means responsively coupled to said providing means for determining whether said branch instruction is an xway mode instruction; and c. Means responsively coupled to said providing means and said determining means for branching on any clock cycle if said determining means determines that said branch instruction is said xway mode instruction. 17. An apparatus according to claim 16 further comprising means located within said branch instruction for indicating whether said branch instruction is said xway instruction. 18. An apparatus according to claim 17 wherein said branching means further comprises means for storing look up tabular information. 1 . An apparatus according to claim 18 wherein said storing means further comprises means for identifying a branch target. 20. An apparatus according to claim 19 wherein said storing means further comprises a microcode address.

Inventors: CRISWELL PETER B, PETERSON EDWARD R, CRISWELL, PETER, B., PETERSON, EDWARD, R.
Applicants: UNISYS CORP, UNISYS CORPORATION
Application year: 2001
Main classification: G06F9
IPC codes: G06F9