ETHERNET ADAPTING APPARATUS

Abstract: An Ethernet adapting apparatus for data transfer between a standard Ethernet data pump and an Ethernet medium access controller via telecommunication medium (4), comprising: (a) a dual mode media independent interface (9) which emulates in a PHY mode the standard Ethernet data pump and which emulates in a MAC mode the Ethernet medium access controller; (b) a data pump (10) connected to the telecommunication medium (4); (c) a data buffer (11) for storing at least one Ethernet data package to be transferred between the standard Ethernet data pump and the Ethernet medium access controller.

Description: Ethernet Adapting Apparatus The present invention refers to an Ethernet adapting apparatus for data transfer between a standard Ethernet data pump and an Ethernet medium access controller (MAC) via a telecommunication medium, and in particular via a telephone line. Ethernet began as a shared media network architecture. Line- cards of a PC are connected to an Ethernet data transfer cable as shown in Fig. 1. In the architecture shown in Fig. 1, only half duplex data transfer is possible. Further, no auto-negotiation procedures between the different line-cards can be performed. Fig. 2 shows a further Ethernet architecture with a HUB device. A HUB is a component that serves as a common termination point for multiple nodes and can relay signals along appropriate signal paths. A HUB connects nodes that have a common architecture, such as Ethernet. In the architecture shown in Fig. 2, all data coming from one line- card are sent to all other line-cards comprising a physical layer PHY and a MAC layer (MAC) . In the architecture shown in Fig. 2, only half duplex data transmission is possible. Further auto-negotiation procedures can be performed. Fig. 3 shows an Ethernet architecture with a switch known in the state of the art. An Ethernet switch is a device that can direct network traffic among several Ethernet networks or PCs. The switch has multiple ports to connect the subnetworks, and it generally has multiple processors to handle the data traffic through the switch. Two types of Ethernet switches are common. The store-and-forward switch checks each data packet for errors before directing it to the appropriate network. In contrast, a cross-point switch directs packets without checking for errors. This type of switch is generally much faster than a store-and-forward switch, because no time-consuming error check is performed. In the architecture shown in Fig 3, full duplex data transmission is possible as well as auto-negotiation procedures . Fig. 4 shows a bridge connecting two local area networks (LAN) . The bridge is a hardware device that can pass data packets from one local area network to the other local area network. The bridge makes the networks look like a single network to higher level protocols or programs. Depending on the architecture of the local area network, full duplex data transmission and auto-negotiation is possible. In many applications, it is necessary to connect an Ethernet network to a remote Ethernet network. Fig. 5 shows an example connecting the first Ethernet local area network (LANA) in a first building A to a remote second Ethernet network (LANB) in a building B. Since the maximum distance between two PCs or switches in an Ethernet network is about 100 meters, it is necessary to connect both LANs via two bridges A, B and a telecommunication channel, e.g. a telephone line. The maximum distance between two computers within an Ethernet network is about 100 meters, because the resistance and accordingly the attenuation of an Ethernet cable connecting two Ethernet devices can be intolerable for higher distances. The standard Ethernet networks LANA, LANB have the following characteristics. The Ethernet network operates at the two lowest layers in the OSI reference model, i.e. as a physical and data link layer. The Ethernet networks use a bus topology. Nodes are attached to a trunk segment which is a main piece of cable in an Ethernet network. lOBaseT, a variant architecture based on the IEEE 802.3 standard, can also use a star topology. 100BaseT networks must use a star topology according to IEEE 802.3 U specifications. Ethernet networks operate usually at speeds of up to 10 Mbps. Several variants of the Ethernet network operate at slower speeds, and new variants of Ethernet networks operate even at 100 Mbps and 1 Gbps, respectively. Ethernet networks use CSMA/CD, i.e. immediate access method based on collision detection. This access method is specified as part of the IEEE 802.3 standard. An Ethernet network broadcasts transmissions, so that each node receives the transmission at the same time. Further, Ethernet networks use Manchester encoding, which is a self-clocking encoding method that includes a voltage transition in the middle of each bit interval. Normally, 50 Ω coaxial cables are used in an Ethernet network, however, variant networks can also use 75 Ω coaxial cables, twisted pair and fiber optic cables. The frame sizes vary between 64 and 15/8 data bytes. Variants of the Ethernet networks are the 10Base5 (thick Ethernet) , the 10Base2 (thin Ethernet) , the lOBaseT (twisted pair Ethernet) , the lOBaseF (fiber optic Ethernet) , the 10Broad3β and the 100 Base T. The lOBaseT Ethernet uses UTP cables. This configuration was adopted as the 802.3 I standard in 1990 and is becoming increasingly popular, because UTP is inexpensive and easy to install and work with. The maximum cable segment length is about 100 meters. A disadvantage of the system shown in Fig. 5 resides in that there is only one data transmission channel between the two local area networks LANA, LANB. This significates that only one Ethernet data frame can be sent from one local area network to the other local area network at a time via the telephone line. Conseguently, the data transfer speed for data transfer from one local area network to the other local area network is very slow. A further disadvantage is that two bridge devices are necessary to connect both local area networks. Accordingly, it is the object of the present invention to provide an Ethernet adapting apparatus for data transfer which makes it possible to extend an Ethernet local area network to remote locations without reducing the data transfer speed. This object is solved by an Ethernet adapting apparatus for data transfer having the features of main claim 1. The present invention provides an Ethernet adapting apparatus for data transfer between a standard Ethernet data pump and a Ethernet medium access controller via telecommunication medium, comprising a dual-mode media independent interface (Mil) which emulates in a PHY mode the standard Ethernet data pump and which emulates in a MAC mode the Ethernet medium access controller (MAC) , a data pump connected to the telecommunication medium, and a data buffer for storing at least one Ethernet data package to be transferred between the standard Ethernet data pump and the Ethernet medium access controller. According to a preferred embodiment, the telecommunication medium is a telephone line. The data pump is preferably a lOBases data modem. In a preferred embodiment of the Ethernet adapting apparatus according to the present invention, the dual-mode media independent interface is set to the PHY mode or to the MAC mode by means of a switching device. The dual-mode media independent interface comprises in a preferred embodiment a serial management interface (SMI) connectable via a SMI data line to an Ethernet medium access controller (MAC) or to a standard Ethernet data pump for the exchange of SMI data frames including SMI messages, and a data flow interface (DFI) connectable via a data bus to an Ethernet medium access controller (MAC) or to a standard Ethernet data pump for the exchange of Ethernet data packages . The serial management interface (SMI) comprises in a preferred embodiment a deframing circuit for deframing the SMI-data frames supplied via the SMI-data line, a decoder for decoding the SMI messages, and a set of SMI-registers. These SMI-registers are in a preferred embodiment a command register, a status register, an identification code register, a negotiation advertisement register and an auto- negotiation partner ability register. In an alternative embodiment the SMI comprises an encoder for encoding SMI messages and a framing circuit for framing SMI data frames to be supplied through the SMP data line to an Ethernet data pump. The serial management interface (SMI) is in a preferred embodiment connected to a central processing unit (CPU) of the Ethernet adapting apparatus. The data-flow interface (DFI) is connected in a preferred embodiment via control lines to a data buffer control circuit for controlling the data buffer. In an alternative embodiment, the telecommunication medium is a wireless telecommunication channel. In a further alternative embodiment, the telecommunication medium is an optical telecommunication channel. In a preferred embodiment of the Ethernet adapting apparatus for data transfer between a standard Ethernet data pump and an Ethernet medium access controller are described with reference to the enclosed Figures which show: Fig. 1 a first Ethernet architecture according to the state of the art; Fig. 2 a second Ethernet architecture according to the state of the art; Fig. 3 a third Ethernet architecture according to the state of the art; Fig. 4 a fourth Ethernet architecture according to the state of the art; Fig. 5 the connection between two Ethernet local area networks according to the state of the art showing the problem underlying the present invention; Fig. 6 the extension of an Ethernet local area network using several Ethernet adapting apparatuses according to the present invention; Fig. 7 the connection of a medium access controller (MAC) and a standard Ethernet data pump by means of two Ethernet adapting apparatuses and a telephone line according to the present invention; Fig. 8 a block diagram of an Ethernet adapting apparatus according to the present invention; Fig. 9 a more detailed block diagram showing details of the Mil interface within the Ethernet adapting apparatus according to the present invention; Fig. 10 a flow chart of a first mode of the dual-mode media independent interface (Mil); Fig. 11 a second mode of the dual-mode media independent interface (Mil) of the Ethernet adapting apparatus according to the present invention; Fig. 12a, 12b, 12c different data frame formats according to the present invention; Fig. 13 a block diagram of the transmitting side of the data pump within a preferred embodiment of the Ethernet adapting apparatus according to the present invention; Fig. 14a, 14b block diagrams of the receiving side of a data pump within a preferred embodiment of the Ethernet adapting apparatus according to the present invention. As can be seen from Fig. 6, an- Ethernet local area network 1 including, for example, a switch and several PCs within a building A is connected via lines 2-1, 2-2, 2-3 to the Ethernet adapting apparatuses 3-la, 3-2a, 3-3a within the same building. Each Ethernet adapting apparatus is connected via a corresponding telephone line 4-1, 4-2, 4-3 to a remote Ethernet adapting apparatus 3-lb, 3-2b, 3-3b in a different building B. In the example shown in Fig. 6, each remote Ethernet adapting apparatus 3-lb, 3-2b, 3-3b of a computer 5-1, 5-2, 5-3 is connected by means of a line 6-1, 6-2, 6-3. The Ethernet adapting apparatuses 3-la, 3-2a, 3-3a within building A are set in a physical PHY mode to emulate the standard Ethernet data pump, whereas the remote Ethernet adapting apparatuses 3-lb, 3-2b, 3-3b within building B are set to a MAC mode for emulating an Ethernet medium access controller. Two Ethernet adapting apparatuses according to the present invention connected via a telecommunication medium such as a telephone line are set in different operating modes. The operating mode of an Ethernet adapting apparatus 3 according to the present invention is preferably set by a switching device of the Ethernet adapting apparatus, such as a hardware pin. In an alternative embodiment, the Ethernet adapting apparatus 3 of the present invention is switched between two modes by a control signal applied via control line from a remote control unit or by Ethernet commands . Fig. 7 shows the connection of an Ethernet medium access controller, such as a switch, a bridge or a HUB device 7 to a standard Ethernet data pump 8 by means of two Ethernet adapting apparatuses 3a, 3b and a telephone line 4 in more detail. Each Ethernet adapting apparatus 3 comprises an Mil interface 9, a data pump 10, a data buffer 11, a buffer control circuit 12 and a central processing unit 13. The two data pumps 10a, 10b of the Ethernet adapting apparatus 3a, 3b are connected to each other via the telephone line 4. The first Ethernet adapting apparatus 3a shown in Fig. 7 is set to the physical mode by means of a switching device 14a, and the other Ethernet adapting apparatus 3b is set to the MAC mode by means of a switching device 14b. The first Ethernet adapting apparatus 3a emulates the standard Ethernet data pump and is connected via control and data lines to the medium access controlling device 7, such as a switch, a bridge or a HUB. On the other side, the second Ethernet adapting apparatus 3b operates in the MAC mode and emulates an Ethernet medium access controller. The Mil interface 9b of the second Ethernet adapting apparatus 3b is connected via data and control lines to a standard Ethernet data pump 8. From the view point of the medium access controller 7, the two Ethernet adapting apparatuses 3a, 3b connected to the LO ω N3 M > > Lπ o Cπ o Lπ o Cπ Ό CΛ O TJ H- rt CL Ω rt rt CΛ a a Ω μ- CU CU ^ μ- cr ι-3 cu T fu Ω LO s ^ 173 o 3 M O H s: Hi H 3 O Cu 3 J Φ Φ d Cu Cu d O 3 a TJ μ- 3 Φ - Ω 0 TJ o OJ > H rt Hi o rt rt O H- O a rt cu H 1 Ω rt rt cu 3 rt u TJ ιQ TJ tr Φ Ω CΛ TJ 3 • o. o τr rt " Cu O rr rt Ω Φ rt 0) 3 Φ Φ tf u Cu rt Φ TJ Cu . u φ CΛ CU rt 3 φ d Φ 3 Φ Ω t Φ TJ 3" 3 Ω Ω 1 μ> H rt H Φ CΛ <i Ω CΛ μ- l-i H LO Ω H TJ l-i H 3 J Φ CΛ Φ Φ Φ O O CU T Cu 3 o Hi μ- Cu oo 3 Φ O CΛ tr C O cr O rt 3 ro 3 CU CΛ H- CΛ 3 H- 3 3 CΛ d 3 o Cu 3 rt φ 3 rt 3 3 ^ Φ rt 0J Φ H - 3 α p. a CL 3 • 3 Ω ιQ d ω 3 TJ Ω Φ d " cr rt Φ rt o -> rt 3 ua e 3 Φ Cu Φ d C CU T Φ Ω Φ CO 3 ^ rt μ- d O CΛ φ Φ H μ- tQ α> ιQ 3 rt CΛ ι-3 3 3 Ω μ- Cu o Φ ? rt 3 rt Φ H & O <l a μ 1 N a M α rt Cu 3 J μ- μ- rt o 3 H ιχ> TJ L0 ≤ a φ Φ rt O CΛ a> H 1 μ- OJ Φ J rt d Φ 1 d Φ Ω Ω φ o 3 Φ Ω TJ ω H H <j Φ rt- 3 rt- 3" 3 3 3 μ- CT cπ Cu CU rt d C CU μ- o CΛ O 0) LO > Φ Φ s: OJ μ- rt OJ Φ H- H- 0 H- 3 C 3 rt rt φ μ- μ- μ- Cu H Ω cu 3 h H Ω cu Ω 3 * l-i rt Ω α rr rt Hi rt Φ μ- μ- T CΛ O u rt fu Ω a ( l H 3- Ω H TJ TJ ro OJ TJ 3 Φ Φ Φ Hi O a o o 3 J rt O cr cr μ- 1 Φ μ- O μ- -J o d rt- d Φ μ> > H Φ H- 3 3 O Ω μ- μ> CU d l-i d 3 H Φ LO H μ- 3 μ- 3 rt ω 3 ω Hi H rt d 3 o 3 M rt CΛ a 0 μ- u <l cr Φ Cu 3 TJ CΛ OJ TJ .£» φ Cu \-y 3 Ω 3 Φ 3 μ- a Cu μ- Ω H -J Φ μ- 3 rt -> a H- a <! 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Φ d 3 Φ μ- μ- rt Ω CΛ CJ0 CΛ a φ OJ a H H- ω 3 rt 3 μ- Hi x H w oo d rt μ- Φ φ " rt a Cu CΛ Φ øJ øJ ^ " « ι-3 cu Hi φ 3 • 3 3 CΛ CΛ OJ O H CΛ - > μ- Φ ^ φ 3 Φ μ- CΛ rt 3 Φ a en cu Φ i-i rt rt CΛ 3 J Ω CΛ 00 Φ Φ to the data pump 10 which is connected via data lines 19 to the data buffer 11. Fig. 9 shows a preferred embodiment of the Ethernet adapting apparatus 3 according to the present invention in more detail. The media independent interface 9 provides simple easy-to- imple ent interconnection between media access control (MAC) sublayers and physical layers for data transfer at 10 Mb/sec and 100 Mb/sec. The Mil interface 9 is capable of supporting up to 100 Mb/sec rates for data transfer and of supporting management functions for physical layer devices. The data and delimiters are synchronous to clock references. Any kind of Mil interface 9 can be used, such as a RMII or a SMII. The Mil interface 9 provides for full duplex operation, if necessary. The media independent interface is described in detail in the IEEE standard 802.3. The Mil interface receives Ethernet data frames via data lines 20 which are converted by a converting unit 21 into data bytes. The converting unit 21 is connected via lines 22 to a write control unit 23 which checks whether sufficient memory space for at least one Ethernet data frame is in the data buffer 11. In case that there is enough memory space in the data buffer 11, the data bytes of the received data frame are stored in the data buffer 11 via lines 24. The write control unit 23 is enabled via a control line 25. If there is not sufficient memory space in the data buffer 11, the data buffer control circuit 12 sends a control signal via a control line 26 to the flow control circuit 27 within the Mil interface 9. The flow control circuit 27 sends an indicating signal to the sending device indicating that the transmission medium is not available at the moment. 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Φ Ω Cu ro Ω CΛ ro > ; rt CΛ rt ^ 0J cu μ- rt H l-i rt s 1 KQ o CL Φ 3 Φ CΛ rt- O hi TJ O Hi if rt- PIQ OJ α> μ- CD Hi μ- l-i ro • ro Φ l-i 0 3 rt if OJ CL 3 CU φ 3 " rt hi μ- 3 ro cr Ω S ' 3 TJ o Ω o 3 Φ OJ CL Ω CO cr o o OJ 3 cr o O O Φ H o OJ O d o Φ ø TJ OJ 3 ro l-i ιQ Hi 3 μ» CO OJ 0J φ o . cr rt OJ h- 1 Φ 3 CΛ rt Hi 3 H OJ TJ Cu μ- 3 H o LO φ Hi 3 3 CL L rt 3 d ø 3 Φ μ- φ rt rt Ω CΛ Hi rt Hi l-f rt CO ØJ OJ -• GO O μ- if Hi < S" μ- <i : rt φ H μ- 1 μ- OJ μ- h- 1 ro TJ 3 ro hj d CL μ- 3 Φ μ- H) TJ rt Φ Φ 3 fJJ OJ Ω o l-i o O 3 rt 3 * L PI ¬ TJ μ- 3 ØJ CL 3 Φ 3 φ 3 φ d < 0 μ- M H hi h- 1 ≤ CL d ιQ S' 0J 3 3 U CO 3 H hi 3 μ- Hi 3 hi rt μ- μ- ro 1 μ- CΛ μ- CL Φ l-i KQ CL rt- 3 J μ- a rt Φ τι TJ ø H d φ Φ if H L o CL (-> O Ω 3 0J 0J OJ μ- <! . ^ 3 μ- - 1 ro hi 3 Φ Φ * * • μ- O ØJ LO rt rt rt OJ Φ Φ CΛ o iQ μ 1 ØJ C rt (!> O CO μ- 3 3 rt o fu d pi3 μ-- n rt rt- o Φ if rt- CL CΛ rh 3 Hi φ rt μ- CΛ s' O 3- ro CU -> μ- Φ rt ro OJ if 3' H 3 μ- PI ¬ ω CL Φ Φ 3 μ- < hj O rt- O Φ rt Φ t\) O KQ rt S' CO Φ CL CL 3 Φ OJ Hi if 00 h- 1 Φ 3 • φ ro is checked whether the receive data line 30 is ready for data transmission. In case that a data transmission is possible, the data are read out of the data buffer 11 via data lines 31 to a reading unit 32 which is enabled by the flow control circuit 27 via control line 32. On the output side of the reading unit 32, the read-out data are supplied via lines 34 to a converting unit 35. If the receiving data line 30 is not ready for data transmission, the flow control circuit 27 generates dummy data which are supplied to the converting unit 35 in a data line 36. The reading unit 32 delivers an RX-valid signal via line 37. The flow control circuit 27 is further connected to a carrier sense (CRS) line 38, a collision signal line (COL) 39, a transmission error (TX-ER) line 40 and a receive error (RX-ER) line 41. Ethernet physical devices generate a carrier sense signal (CRS) to indicate activity on the Ethernet medium. The MAC layer uses this CRS to validate receptions and to avoid a concurrent transmission in shared media configurations. The CRS is generated by the Mil interface to indicate to the MAC device by the physical device that there is a legal signal on the transmission medium. The Ethernet physical device may generate a collision signal (COL) while transmitting and when it detects another simultaneous transmission on the transmission medium. The collision signal indicates to the MAC device that the current transmission has collided with that of another station and will not be correctly received by any station. The collision signal is a signal of the Mil interface 9 that indicates to the MAC device in half duplex that an incoming message collides with an outgoing message. The transmit error signal (TX-ER) is generated by a MAC device to request that a physical device deliberately corrupt the data contents of a frame in such a manner that a receiver will detect the corruption with the highest degree of probability. The received error signal (RX-ER) is generated by an Ethernet physical device, if a coding error or any other error that the physical device is capable of detecting was detected somewhere in the data frame presently being transferred from the physical device. The media independent interface 9 shown in Fig. 9 is constituted by a data flow interface (DFI) comprising the converting units 21, 35, the read-and-write units 23, 32 and the data flow control circuit- 27. The media independent interface 9 further comprises a serial management interface (SMI) . The serial management interface is constituted by a framing circuit 42 for deframing SMI data frames supplied to the Mil interface 9 via the SMI data line 43. The framing circuit 42 is further connected to a SMI clock line 44. The serial management interface (SMI) does further comprise a decoder 45 connected to the framing circuit 42 via lines 46. The serial management interface includes further a set of serial management interface registers 47 connected to the decoder 45 via lines 48 and to the central processing unit 13 via lines 49. The central processing unit 13 controls the data flow control circuit 27 within the data flow interface via control line 50 to switch between a half duplex mode (HDX) and a full duplex mode (FDX) . In the half duplex mode (HDX) , the data flow control circuit 27 creates dummy data as back pressure data which are sent via the receiving data line 30 back to the data origin which might be a medium access controller or a standard Ethernet data pump, in case that the data buffer 11 is recognized to be full. In case that the full duplex mode (FDX) is set by the central processing unit 13 via the control line 50, no dummy data are generated, but a special pause and continue frame is generated and sent back to the data origin. The procedure is based on pause/continue data packets with special source address. Pause/continue data pockets are described in the IEEE 802.3x standard. Fig. 10 shows a flow chart of an Ethernet adapting apparatus 3 working in the physical mode (PHY-MODE) set by the mode switching device 14. In the physical layer mode shown in Fig. 10, the Ethernet adapting apparatus 3 according to the present invention emulates a standard Ethernet data pump. After the start in step SO, it is checked in step SI by the Mil-interface 9 whether an SMI data frame has been transmitted via the SMI data line 43. In case that no SMI data frame has been received by the decoder 42 of the SMI interface, it is checked in step S2 whether a status change message has been received. Contrary, if it is detected in step SI that an SMI data frame has been received by the deframer 42, the SMI data frame is analyzed in step S4 by the decoder 45. Fig. 12b shows the structure of an SMI data frame. The SMI data frame comprises a start of frame delimiter (SFD) and a five-bit address of the physical device attended by the MAC controller. A MAC controller (MAC) can attend up to 32 physical devices simultaneously. Further, the SMI data frame contains 5 bits of a register address in the physical device, such as BMCR, BMSR. Further, the SMI data frame contains 1 bit which indicates whether the MAC controller wants to write data or wants to read data. Further, there is a turn-around bit TT and 16 bits of data read by the MAC controller if the SMI data frame is a read data frame and set by the physical device if the SMI data frame is a write data frame. As can be seen from Fig. 10, it is checked in the physical mode in step S5 whether the received SMI data frame contains a read-or-write command by checking the read/write bit included in the SMI data frame. If the write bit of the SMI data frame is high, it is checked in step S6 whether the SMI data frame includes an ordinary write command or not. In case that it is an ordinary write command, a write message is sent in step S7 from the CPU 13 to the remote CPU 13. The format of the message ,is shown in Fig. 12c. The message data frame comprises a header indicating the message type and the length of the message. Further, the message data frame comprises message data and a validity check sum. There are three types of message data frames, i.e. lOBaseS link control messages, general write-or-read messages and special SMI messages. In step S7, a general write/read message is sent from the CPU 13 to the remote CPU 13 of the remote Ethernet adapting apparatus 3. In case that it is recognized in step S6 that no ordinary write command has been included in the received SMI date frame, it is checked in step S8 whether the command was a force write command. In case that the write command is a force write command, the procedure proceeds to step S9 and a force message is sent to the remote CPU 13. In the contrary case, an auto-negotiation message is sent in step S10. In step Sll, the local SMI interface is set to no link, and in step S12 it is checked whether a status change message has been received. When a status change message has been received, the local speed and the duplex mode bits of the BMCR are set according to the configuration command included in the status change message in step S13. Further, in step S14, an ordinary write message is sent from the CPU 13 to the remote CPU 13 to set a speed and duplex mode of the registers of the remote Ethernet adapting apparatus to the new configuration set in step S13. Further, the content of the registers in the register bank 47 of the Ethernet adapting apparatus 3 is mirrored to the corresponding register bank 47 of the remote Ethernet adapting apparatus 3 on the other side of the telephone line 4. In case that in step S5 it is detected that the decoded and analyzed command is a read command, the SMI interface sends in step S15 the SMI data frame back to the data source with the data content of a register within the register bank 47 as requested. The register bank 47 within the Mil interface 9 comprises at least 5 obligatory registers. These registers are a command register, a status register and an identification code register, a negotiation advertisement register and auto- negotiation partner ability register. The command register (BMCR) comprises 5 bits. The first bit sets the speed to 100 Mbps or 10 Mpbs, the second bit sets the duplex mode to half duplex or full duplex, the third bit is a reset command, the fourth bit enables or disables the auto-negotiation procedure and the fifth bit restarts the auto-negotiation procedure. The status register comprises 4 bits, wherein the first bit indicates the actual data transfer speed, the second bit indicates the actual duplex mode, the third bit indicates the link status and the fourth bit indicates whether the auto- negotiation procedure is complete or not. In the identification code register, an identification code is stored being unique identifies for a particular type of Ethernet. In the negotiation advertisement register, it is indicated whether the physical device is capable to work in 10 Mbpshalf duplex, 100 mbs half duplex, 10 mbs full duplex, 100 Mbpsfull duplex, and whether the physical device supports the pause/continue procedure according to IEEE 802.3x. The auto-negotiation partner ability register is similar to the negotiation advertisement register and reflects the partner abilities as advertised by the communication partner device. If in step S2 it is detected that no status change message has been received, it is checked in step S15 whether auto- negotiation has been enabled or not. If the auto-negotiation has been enabled, the procedure continues with step S10. The auto-negotiation procedure between two Ethernet physical layer devices aims to find the highest available mode of operation that can be supported by those Ethernet physical layer devices. The auto-negotiation procedure provides a link device with the capability to detect the modes of operation supported by the device at the other end of the data link, determine common abilities and to configure for joint operation. The auto-negotiatiόn procedure instructs the Ethernet physical device to perform auto-negotiation and then calibrates all data path operations and data procedures. The auto-negotiation procedure can be disabled by the MAC layer device. When the auto-negotiation procedure is disabled, the Ethernet physical layer device is forced to the configuration indicated by the MAC layer. Fig. 11 shows a further flow chart of an Ethernet adapting apparatus 3 according to the present invention working in the medium access control mode (MAC-mode) . After a start step S17, it is checked in step S18 whether a message from the physical layer device has been received or not. If the answer is yes, the received message is analyzed in step S19. In step S20, it is checked whether the message is an ordinary write message or not. In case that it is an ordinary write message, an SMI data frame including the write command is generated and sent in step S21. In the contrary case, it is detected whether the analyzed message is a force message or not in step S22. If the received message is a force message, an SMI data frame is generated including the force command and sent in step S23. Otherwise, it is decided in step S22 that the received message is an auto-negotiation message, and a corresponding SMI data frame including an auto-negotiation command is generated and sent in step S24. In step S25, it is detected whether an Ethernet link is provided or not. If yes, proprietary information data is read from aa register of the Ethernet physical device in step S26, and the local Ethernet adapting apparatus 3 is set in step S27 to support the data transfer speed, the duplex mode according to the proprietary duplex mode data read in step S26. In a further step S28, a status change message is sent from the MAC-mode device to the central processing unit of the remote device. In case that in step S18 it is detected that no message has been received, it is checked in step S29 whether a status change has occurred. In case that a status change is detected in step S29, a status change message is sent in step S30 to the new status stored in the registers. In a preferred embodiment, the Ethernet adapting apparatus 3 according to the present invention as shown in Fig. 8 comprises a lOBaseS data modem 10 as a data pump. The lOBaseS data modem 10 comprises a modem transmitter as shown in Fig. 13 and a modem receiver as shown in Fig. 14a, 14b. The data source feeding the modem 10 supplies a transmit data signal and a transmit enable signal to a transmitter interface 51 of the lOBaseS data modem. The transmit interface inputs digital data to a FIFO device 52. The FIFO functions to adjust the rate of data transfer between the data source and the data modem itself. The FIFO device 52 compensates the differences in the data rates between the two devices. The signal output of the FIFO device 52 is input to a sync generator 53, a header generator 54 and a randomizer 54. The sync generator 53 generates and outputs two sync bytes to a frame formatter 56. The header generator 54 generates header information spanning a plurality of bytes. The header information is then randomized or scrambled by a randomizer 57 and subsequently encoded by an encoder 58. The output signal of the encoder 58 is input to the frame formatter 56. The data from the frame FIFO device 52 is further input to a scrambler or randomizer 55 which scrambles the data. The output of the randomizer 55 is connected to an encoder 59 which encodes the data stream. An encoded data stream is output to an interleaver 60 which in combination with a Reed Solomon encoding shuffles the data to overcome impulse type noise thus resulting in improved error recovery. The output of the interleaver 60 is input to the frame formatter 56. The frame formatter 56 samples a complete data frame comprising sync, the header data and the data stream output from the interleaver 60. The frame formatter 56 is connected to a symbol encoder 61. The symbol encoder 61 generates an in-band I and a quadrature Q digital output signal from the basis of the input digital data stream. The I and Q channels are input to an in-phase filter 62 and a quadrature filter 63. The output of the quadrature filter 63 is subtracted from the output of the in-band filter 62 by means of the subtracting device 64. The output signal of the subtracting device is converted by means of a digital analogue converter 65, the output of which is connected to a line interface 66. The line interface 66 transmits the output signal via a twisted pair telephone line 4. Fig. 14a, 14b show the modem receiver side of the lOBaseS data modem 10 used in a preferred embodiment of the Ethernet adapting apparatus 3 according to the present invention. The twisted pair wire 4 is coupled to an analogue front end 67 which is provided to interface the data modem 10 to the telephone line 4 and to amplify the received analogue signal. The output of the analogue front end 67 is connected to an analogue digital converter 68. The output of the analogue digital converter 68 is input to an automatic gain control 69. The output of the digital converter 68 is further coupled to a multiplexer 70, a notch filter 71 and a narrowband interference detector 72. The output of the notch filter 32 is connected to the second input of the multiplexer 70. The narrowband interference detector 72 detects the presence of an amateur radio signal which lies in the frequency range of 1,82 MHz. If sufficient signal levels in the amateur radio band are detected in the received signal, the multiplexer 70 is set to switch the output of the notch filter 71 through. The center frequency and the bandwidth of the notch filter 71 is set to cover the amateur radio band. The output of the multiplexer 70 is input to an in-phase filter 73, a quadrature filter 74 and a timing control circuit 75. The in- phase and quadrature signals output via the in-phase and quadrature filters 73, 74 are input to an adaptive equalizer 76. The in-phase and quadrature signals output by the adaptive equalizer 76 are input through a slicer 77 which generates a feedback signal to control the adaptive equalizer 76 and the timing control circuit 75. The timing control circuit 75 outputs a signal to a voltage controlled crystal oscillator/phase locked loop 78. The output of the phase- locked loop 78 input to a clock-generating circuitry 79 which generates clock signals used internally by the modem 10. The I and Q output signals of the slicer 77 are input to a symbol decoder 80. The symbol decoder 80 makes a best determination from among the constellation points according to the I and Q input signals. The data bits represented the detected symbol are output by the symbol decoder 80 and input to a frame deformatter 81 shown in Fig. 14b. The frame deformatter 81 is coupled to a deinterleaver 82, a decoder 83 and a sync detector 84. The sync detector 84 matches the sync pattern and searches for multiple sync occurrences in the input data stream. Once a sync signal is detected, the header data is read from the frame by the frame deformatter 81 and input to the decoder 83. The output of the decoder 83 is input to a LO CO ro NJ 1 μ» Cπ o Cπ O Cπ o cπ μ- 3 M M øJ M O ι-3 Φ CD Λ rt CU PIΩ μ- ι-3 rt- PIι-3 μ- ι-3 rt Φ rt pi ¬ rt 3 OJ s; O O CL ι-3 OJ if ex ex < if 3 rt μ- 0 S' O 3 if O S' if 3 if o CL Φ if d d φ if CL Φ Φ Φ C 3' s' 3 3' Φ φ d ø) KQ μ- Φ 3 <l φ Φ ro pi- Φ CL l_I. hi μ- rt rt μ- φ CL cu hj hi μ- CΛ Φ ro Φ Φ H 3 3 ro 3 φ TJ ro Φ d OJ o J J 3 H 01 co 0J hi H hi ex Cu 3 01 CL OJ 3 ro M d 3 M hi hi rt- 3 hi o 3 CO 3 3" d d rt- Hi Φ Φ 3 3 Q 3 3 3 OJ μ- OJ if PIrt 3 rt- PIO o ro Hi d rt- rt rt- ro H CΛ H TJ μ- Φ φ Φ ex ex hi ro hi 0J S' if μ- μ- S' - <! Ω Cu rt μ> co o CL h OJ CO o o o 3 rt rt Φ rt hi CL OJ 3 Φ Φ Ω O ro μ- ro Φ o TJ o 3 Φ O O - 1 ØJ 3 μ- CO ex tQ H μ- o 3 3 3 Ω H hi cu 3 H CL 3 μ- ro d Hi μ- CΛ Hi Hi Φ φ 3 cu μ- μ- CO ex 3 φ TJ 3 hi 3 K CL ro 3 3 rt 3 φ <J rt OJ o N Ω OJ iQ li ¬ N N μ- TJ OJ φ Ω 3 * ? μ- PIΦ Φ μ- μ- φ μ* Φ Ω 3 hi Φ hi rt rt <j CL eu Φ Φ cr h rt CL O • 3 M S' rt TJ rt rt 0 Cfl rt- OJ o μ- o α H 0 ) if s- ro Φ Hi hi H μ- o øJ μ- 3 CΛ 3 ιQ PI ¬ Φ if ro 3 Ω H Hi pi3 Φ Φ hi Hi d μ- Φ rt d μ- OJ S' hi Φ hi rt CΛ cu OJ Ω μ- μ- Ω rt s' 00 cr 0 3 Cfl 00 00 O TJ 3 d Ω J o φ. 3 Hi o rt OJ 3 CL o o d PI ¬ 3 * φ 00 M CL α CO H Ω Cπ cπ rt Ω d 3 OJ Φ Hi hi Φ o o o 01 3 OJ O Ω μ- S' Φ φ ro Φ M 3 rt- OJ . O O 3 cu μ- CΛ 3 rt o hi 3 ex φ TJ Ω μ- ?τ rt Φ CL μ- CΛ Ω μ- OJ μ- 3 μ- -> TJ Ω Ω rt Φ t-ι 3 CΛ α <! rt ?f 3 Ω μ- CΛ o 3 rt o Cu Cfl ι-3 O CO Ω 0J h- 1 μ- if rt CL 0J OJ OJ rt- μ- TJ ιQ KΩ Hi O l- PIL ri- if rt 3 h-" 3- 3' O Φ rt OJ rt φ ø ) CΛ 3 CO hi ro 3 CΛ d Φ o hi Hi μ- S' ro ro μ- Φ CO ^ O Φ OJ o 3 CO μ- ^< 3 rt μ- Ω d ex Hi 3 ιQ μ- rt 3 OJ § φ 3 φ H H Ω H " ^ N d H <! CΛ o Φ TJ hi Φ ø ιQ Φ Ω μ- CL KQ φ € 3 d hi TJ if φ TJ O Φ Φ PI ¬ 3 hi O Φ CL 3 if hj μ- OJ 3 rt hi if Φ 3 φ d hi 00 φ CO φ α TJ d H S ' Ω CΛ KQ μ- TJ OJ O 1-3 CΛ 3 TJ ØJ O CU μ- μ- 3 rt- Φ -J OJ μ 1 rt rt μ- Φ o 3 O CΛ μ- d d H" Hi OJ if rt iQ TJ ti ¬ Ω •^ Ω Ω Ω <l ro Ω rt μ- TJ 3 PI3 φ TJ μ- Λ 3 3 CO Φ øJ PIro if 0J Φ rt Φ μ- φ CΛ O . o Φ d Hi S' O rt CL Φ cr rt- TJ OJ cr CL H Hi S' CL •^ rt CO o μ- CΛ hi if d CL rt O Φ PIH μ- H μ- 1 ro ØJ hi d O M 0J ro 0J O ro o o μ- <! d rt H S' O d OJ Φ hi Ω μ- Φ Hi O PI• <J rt- H cr d o O PIφ CΛ 00 Hi TJ Φ rt O 3 3 Φ 3 ti- Ω 3 Hi t 1 S' Φ μ- d ' H ' rt α 3 Hi S' CL d N> Hi d rt- O Hi OJ Φ H CD rt Ω Φ μ- Φ *• Φ K Ω O rt φ TJ Φ ro TJ -> rt- ro rt ^^ .&. o o CΛ PI3 H hi ro if Ω rt d < CL PICL TJ μ- ro cn Ω OJ PIμ- CΛ S 3 3 CΛ S' μ- o. 3 O LO φ Φ if rt μ- φ S' Hi OJ μ-- Λ CΛ rt S' O rt μ- μ- O h- 1 rt- Φ rt 0 ) t) Φ Hi cr μ- φ Cfl Ω <! φ hi rt μ- Hi if ro 3 Φ O Λ hj φ ro Ω 0J 3 Λ rt ro OJ hi < φ μ- Cu PJ φ μ- rt d 3 ro μ- Φ — 3 rt 3 o TJ rt- CL Ω rt Ω Φ Φ CL rt Ω CL 3 • CL 3 3- hi μ- OJ ex CΛ Φ • TJ ØJ rt 3 if ro 0J øJ O s: Ω Ω ØJ 3 " 00 φ cu ro TJ ro rt co ex Φ d Ω O H H rt CΛ rt ■ < α CL rt . 3 Φ O Φ μ- rt ro & rt- ι-3 rt d 3 " O Φ Ω Ω O ro 3 o i-> if H CΛ U Ø g Φ hi μ- 3 0J Ω OJ •^ i o rt hi Φ μ- H o if 3 > < < "< Φ o o μ- rt- rt- rt TJ d 3 α < ti ¬ H μ- o H φ ro hi 3 ex 3 PIμ- Hi Ω o Cu 3 * rt 3 μ- ro ro CL Φ C0 3 hi **1 cu rt Ω KQ ex Φ OJ d d S ' D. s: S H-" 0J Φ μ- μ- øJ 3 i ro Ω 3 0J o o O φ OJ OJ hi CΛ 3 CD Φ ro μ- PI ¬ Φ μ- ro Hi 3 Ω ιQ α Hi <1 Φ μ- Φ t-i- d CL μ- Hi rt μ- μ- PIo S' H 3 μ- CO KQ 01 CO 0J 01 μ- μ- 3 Ω ro CL rt- φ OJ <! CL H OJ 00 Ω 3 O S' φ 3 d O Φ rt Φ rt li ¬ Ω Ω < TJ rt- CΛ φ TJ hj Φ OJ OJ LO O OJ KQ 3 cr o μ- o l- 1 Ω OJ μ- Ω O eu ro φ Φ d ro <! d ØJ α CL rt- 3 Cu 0J rt Φ ro d OJ CΛ 3 L OJ • O TJ o O rt CL cr μ- rt 3 φ OJ Φ 3 CU CL μ- CΛ rt rt ^ !2 φ rt- 3 TJ 3 3 rt OJ Ω CL ro Ω CL Ω CL CO ØJ 3 o TJ CO s; Φ H piro h3 CL 0J if 3 o OJ rt rt- rt φ O O O 0J CΛ - h- 1 ex cr s ro μ- CD 3 hi s' u if H cu Φ α 3 rt- o o s; Hi 3 CL rt rt > 0J Ω C ro o μ- φ 3 piφ h- 1 øJ Ω 3 OJ ro OO μ- φ CU hi TJ N pi¬ H 3 μ- Φ 3 rt 0J 3 CL s' 0J rt Ω ø) TJ Hi ro OJ rt Φ • rr N hi • Φ φ φ s' 0J Φ OJ μ- 3 rt S ro o • <: d O •< h{ d Ω CO if 3 if φ OJ hi hi φ s ex μ- OJ PIΩ CL Φ rt in Φ CΛ hi φ Φ 3 rt- μ- hi Φ Φ hi oo Hi 3 Hi Ω μ- 3 S ' Φ hi O o ω hi a hi CO Ω ro iQ Φ pi3- -~J if O CO Φ d CL Φ PI ¬ Hi LO μ- φ rt CL 3 Ω 3 s' μ- 00 " φ r hi en 3 rt S' OJ 3 O 3 O 3 μ- OJ ro o Φ Ω 00 0 3 • rt if Φ Ω o μ- d vQ Hi rt- o rt M μ- CL if ι-3 ω 3' OJ Φ ex CL CΛ 3 o < φ if PIι-3 S • Φ rt- Φ φ Φ rt CΛ ro 3 φ S' if H • CO O Φ φ activities, auto-negotiation, data link, speed duplex mode, etc.. Auto-recognition of the Ethernet physical layer device makes it possible to use its proprietary speed detector. The new telecommunication medium 4 may be used for other applications simultaneously.

Claims: Patent Claims 1. An Ethernet adapting apparatus for data transfer between a standard Ethernet data pump (8) and an Ethernet medium access controller (7) via telecommunication medium (4) , comprising: (a) a dual mode media independent interface (9) which emulates in a PHY mode the standard Ethernet data pump and which emulates in a MAC mode the Ethernet medium access controller; (b) a data pump (10) connected to the telecommunication medium (4) ; (c) a data buffer (11) for storing at least one Ethernet data package to be transferred between the standard Ethernet data pump (8) and the Ethernet medium access controller (7) . 2. The Ethernet adapting apparatus according to claim 1, wherein the telecommunication medium (4) is a telephone line. 3. The Ethernet adapting apparatus according to claim 1 or 2, wherein the data pump (10) is a lOBaseS data modem. 4. The Ethernet adapting apparatus according to one of the preceding claims, wherein the dual mode media independent interface (9) is set in the PHY mode or the MAC mode by means of a switching device (14). 5. The Ethernet adapting apparatus according to one of the preceding claims, wherein the dual mode media independent interface (9) comprises: a serial management interface (42, 45, 47) connectable via a SMI-data line (43) to an Ethernet medium access controller or a standard Ethernet data pump for the exchange of SMI data frames including SMI messages, and a data flow interface (21, 23, 27, 32, 35) connectable via a data bus to an Ethernet medium access controller or a standard Ethernet data pump for the exchange of Ethernet data packages . 6. The Ethernet adapting apparatus according to one of the preceding claims, wherein the serial management interface circuit (42, 45, 47) comprises a deframing circuit (42) for deframing the SMI data frames supplied via the SMI data line (43) , a decoder (45) for decoding the SMI messages, and a set of SMI registers (47) . 7. The Ethernet adapting apparatus according to claim 6, wherein the SMI registers comprise at least: a command register, a status register, an identification code register, a negotiation advertisement register, and an auto-negotiation partner ability register. 8. The Ethernet adapting apparatus according to one of the preceding claims, wherein the serial management interface (9) is connected to a central processing unit (13) . 9. The Ethernet adapting apparatus according to one of the preceding claims, wherein the data flow interface circuit (21, 23, 27, 32, 35) is connected via control lines (26) to a data buffer control circuit (12) . 10. The Ethernet adapting apparatus according to claim 1, wherein the telecommunication medium (4) is a wireless telecommunication channel. 11. The Ethernet adapting apparatus according to claim 1, wherein the telecommunication medium (4) is an optical telecommunication channel. 12. The Ethernet adapting apparatus according to claims 1-11, wherein the register content of any SMI-register is mirrored.

Inventors: ARONSON SIMCHA, HARPAK AMNON, LAZMI SHAI, ARONSON, SIMCHA, HARPAK, AMNON, LAZMI, SHAI
Applicants: INFINEON TECHNOLOGIES AG
Application year: 2001
Main classification: H04L29
IPC codes: H04L12