FIELD EMISSION DISPLAY AND METHOD

Abstract: Method for operating a field emission display (10) and a field emission display (10) that has a plurality of column conductors (17, 18, 19) on which electron emitter structures (24) are disposed. Column conductor driver circuits (47, 48, 49) are coupled to respective column conductors (17, 18, 19) and row conductor driver circuits (37, 38, 39) are coupled to respective row conductors (27, 28, 29) to form sub-pixels (50, 57, 58, 60, 67, 68, 70, 77, 78). The column conductor driver circuits (47, 48, 49) and the row conductor driver circuits (37, 38, 39) cooperate to cause the electron emitter structures (24) to emit electrons. The column conductor driver circuits (47, 48, 49) measure a signal change on at least one of the column conductors and thereby adjusts the operating state of the electron emitter structures (24) are adjusted in accordance with the comparison results.

Description: FIELD EMISSION DISPLAY AND METHOD Field of the Invention The present invention relates, in general, to field emission displays and, more particularly, to methods and circuits for controlling emission current in field emission displays. Background of the Invention Field emission displays (FED's) are well known in the art. A field emission display includes an anode plate and a cathode plate that define a thin envelope. The cathode plate * includes a matrix of column conductors and row conductors, which are used to cause electron emission from electron emitter structures such as, Spindt tips. FED's further include ballast resistors between the electron emitter structures and the cathode plate for controlling the electron emission current. Typically, the ballast resistors have resistance values greater than ten megohms . Because of the high resistance values, the ballast resistors are difficult to fabricate and are highly temperature sensitive, which results in uneven current emission from the electron emitter structures over temperature. Another drawback encountered with field emission displays is differential aging of the electron emission structures. Accordingly, there exists a need for a method and means for controlling the emission current in a field emission display, which overcome at least some of these shortcomings . Brief Description of the Drawings FIG. 1 is a partially cut-away isometric view and circuit schematic representation of a field emission display in accordance with an embodiment of the present invention; FIG. 2 is an equivalent circuit representation of the field emission display of FIG. 1; FIG. 3 is a circuit diagram of a column conductor driver circuit of FIG. 1 in accordance with the present invention; and FIG. 4 is a timing diagram for the operation of the field emission display of FIG. 1. For simplicity and clarity of illustration, elements in the drawings are not necessarily drawn to scale, and the same reference numerals in different figures denote the same elements . Detailed Description of the Drawings Generally, the present invention includes a method and a field emission display for maintaining a uniform emission current over the operating lifetime of the display. The method includes using column conductor driver circuits to drive the column conductors of an FED and row conductor driver circuits to drive the row conductors of the FED, wherein the column conductor driver circuits place a high voltage, or a low voltage, or a high impedance state on the column conductors. In addition, when the column conductor driver circuit is in a high impedance state it monitors the voltage on the column conductor to which it is coupled. When the column conductor driver circuits and the row conductor driver circuits output approximately zero volts, the FED is off. When the column conductor driver circuit is in a high impedance state and a row conductor is at a high voltage level the sub-pixel associated with that row conductor and column conductor transmit an emission current. The voltage at which a particular row conductor turns on the sub-pixel is referred to as a row select voltage. As charge is emitted, the voltage on the column conductor associated with the electron emitter structures that are emitting electrons rises. This voltage rise or change is monitored by the column conductor driver circuit and compared with a predetermined voltage. This predetermined voltage is also referred to as an intensity voltage value and may be determined when the display is started. Once the desired voltage rise is achieved, i.e., the desired luminance is achieved, the column conductor driver output is switched from a high impedance state to a high voltage state to adjust the operating state of the electron emitter structures. For example, the electron emitter structures and therefore the sub-pixels are turned off. Preferably, the turning on and off of the pixels occurs in a single frame time. The column conductor driver circuit is capable of operating in both an amplitude modulation (AM) mode and a dynamic pulse width modulation (PWM) mode. In the amplitude modulation mode, the capacitances associated with the column conductors are charged and discharged to pre-selected levels. In the AM mode, a column with a strong sub-pixel is discharged to a positive voltage thereby reducing the emitted current over a full discharge range whereas a column with a weak sub-pixel is discharged to zero volts. In the PWM mode, stronger emitting sub-pixels have pulse widths that are shorter than a nominal pulse width and weaker emitting sub- pixels have pulse widths that are longer. FIG. 1 is a partially cut-away isometric view and circuit schematic representation of a field emission display (FED) 10 in accordance with an embodiment of the present invention. FED 10 includes an FED device 11 and control circuitry 12 for controlling emission current in FED device 11. FED device 11 includes a cathode plate 13 and an anode plate 14. Cathode plate 13 includes a substrate 16, which can be made from glass, silicon, and the like. A first column conductor 17, a second column conductor 18, and a third column conductor 19 are disposed on substrate 16. A dielectric layer 21 is disposed upon column conductors 17, 18, and 19, and further defines a plurality of wells 22. An electron emitter structure 24 such as, for example, a Spindt tip, is disposed in each of wells 22. Row conductors 27, 28, and 29 are formed on dielectric layer 21. Row conductors 27, 28, and 29 are spaced apart from and proximate to electron emitter structures 24. Row conductors 27, 28, and 29 include a plurality of apertures 30 which cooperate with corresponding wells 22 and electron emitter structures 24 to form current emission regions 31. Column conductors 17, 18, and 19 and row conductors 27, 28, and 29 are used to selectively address electron emitter structures 24. To facilitate understanding of the present invention, FIG. 1 depicts only three row and column conductors. However, it is desired to be understood that any number of row and column conductors can be employed. An exemplary number of row conductors for an FED device is 240 and an exemplary number of column conductors is 960. Methods for fabricating cathode plates for matrix-addressable field emission displays are known to one of ordinary skill in the art. Anode plate 14 is disposed to receive an emission current 32, which is defined by the electrons emitted by electron emitter structures 24. Anode plate 14 includes a transparent substrate 33 made from, for example, glass. An anode 34 is disposed on transparent substrate 33. Anode 34 is preferably made from a transparent conductive material, such as indium tin oxide. In the preferred embodiment, anode 34 is a continuous layer that opposes the entire emissive area of cathode plate 13. That is, anode 34 preferably opposes the entirety of electron emitter structures 24. A plurality of phosphors 36 is disposed upon anode 34. Phosphors 36 are cathodoluminescent . Thus, phosphors 36 emit light upon activation by emission current 32. Methods for fabricating anode plates for matrix-addressable field emission displays are also known to one of ordinary skill in the art. In accordance with one embodiment of the present invention, control circuitry 12 comprises row conductor driver circuits 37, 38, and 39 and column conductor driver circuits 47, 48, and 49. Row conductor driver circuits 37, 38, and 39 are coupled to row conductors 27, 28, and 29, respectively, and column conductor driver circuits 47, 48, and 49 are coupled to column conductors 17, 18, and 19, respectively. FIG. 2 is a schematic diagram of FED 10. What is shown in FIG. 2 is a schematic representation of column conductors 17, 18, and 19, column conductor driver circuits 47, 48, and 49, row conductors 27, 28, and 29, and row conductor driver circuits 37, 38, and 39. It should be understood that although only three row conductor driver circuits and three column conductor driver circuits are shown, there may be more or fewer row conductor driver circuits and more or fewer column conductor driver circuits. FIG. 2 further illustrates electron emitter structures, sub-pixel capacitances, and ballast resistors associated with each row and column conductor of FED 10. More particularly, sub-pixel capacitance 51, sub-pixel ballast resistor 52, an electron emitter structure 24 (2717) associated with sub-pixel 50 are shown as being coupled to row conductor 27 and column conductor 17. Electron emitter structure 24 <27ιl7) is shown as a lumped element representing all the electron emitter structures associated with sub-pixel 50. It should be understood that the reference number 24 has been used to identify electron emitter structures in general. To help explain the embodiment shown in FIG. 2, the electron emitter structures have been further defined by appending subscripts to reference number 24. For example, the electron emitter structures associated with row conductor 27 and column conductor 17 have been identified by reference number 24 (27|17) the electron emitter structures associated with row conductor 28 and column conductor 17 have been identified by reference number 24 (2817) , the electron emitter structures associated with row conductor 27 and column conductor 18 have been identified by reference number 24 (2718) , etc. Sub-pixel capacitance 53, sub-pixel ballast resistor 54, and electron emitter structure 24 (28 associated with sub-pixel 57 are shown as being coupled to row conductor 28 and column conductor 17. Electron emitter structure 24 (2817) is shown as a lumped element representing all the electron emitter structures associated with sub-pixel 57. Sub-pixel capacitance 55, sub-pixel ballast resistor 56, and electron emitter structure 24 (2 . (17) associated with sub-pixel 58 are shown as being coupled to row conductor 29 and column conductor 17. Electron emitter structure 24 (2917) is shown as a lumped element representing all the electron emitter structures associated with sub-pixel 58. Sub-pixel capacitance ' 61, sub-pixel ballast resistor 62, and electron emitter structure 24 (2718) associated with sub-pixel 60 are shown as being coupled to row conductor 27 and column conductor 18. Electron emitter structure 24 (2718) is shown as a lumped element representing all the electron emitter structures associated with sub-pixel 60. Sub-pixel capacitance 63, sub-pixel ballast resistor 64, and electron emitter structure 24 (28 8) associated with sub-pixel 67 are shown as being coupled to row conductor 28 and column conductor 18. Electron emitter structure 24 (2818) is shown as a lumped element representing all the electron emitter structures associated with sub-pixel 67. Sub-pixel capacitance 65, sub-pixel ballast resistor 66, and electron emitter structure 24 ( 8) associated with sub-pixel 68 are shown as being coupled to row conductor 29 and column conductor 18. Electron emitter structure 24 (2918) is shown as a lumped element representing all the electron emitter structures associated with sub-pixel 68. Sub-pixel capacitance 71, sub-pixel ballast resistor 72, and electron emitter structure 24 (27 _ 19) associated with sub-pixel 70 are shown as being coupled to row conductor 27 and column conductor 19. Electron emitter structure 24 (2719) is shown as a lumped element representing all the electron emitter structures associated with sub-pixel 70. Sub-pixel capacitance 73, sub-pixel ballast resistor 74, and electron emitter structure 24 (28Λ9) associated with sub-pixel 77 are shown as being coupled to row conductor 28 and column conductor 19. Electron emitter structure 24 (2819) , is shown as a lumped element representing all the electron emitter structures associated with sub-pixel 77. Sub-pixel capacitance 75, sub-pixel ballast resistor 76, and electron emitter structure 24 (29ιl9) associated with sub-pixel 78 are shown as being coupled to row conductor 29 and column conductor 19. Electron emitter structure 24 (2919) is shown as a lumped element representing all the electron emitter structures associated with sub-pixel 78. Briefly referring to FIG. 3, what is shown is an embodiment of each column conductor driver circuit 47, 48, and 49 in accordance with the present invention. In other words, each circuit block 47, 48, and 49 comprises the circuit structure shown in- FIG. 3. Column conductor driver circuits 47, 48, and 49 each include a sample and hold circuit 80, a comparator 81, a driver control circuit 82, a tri-state driver 83, a one-stage serial-to-parallel converter 87, and a calibration circuit 88. In particular, an input terminal 84 is coupled for receiving an analog video signal, VID A . An output terminal 85 of sample and hold circuit 80 is coupled to a non-inverting input terminal 86 of comparator 81. An output terminal 87 of comparator 81 is coupled to an input terminal 111 of driver control circuit 82. Driver control circuit 82 includes an amplitude modulation portion 93 and a pulse width modulation portion 94. An output terminal 89 of driver control circuit 82 is coupled to an input terminal 90 of tri-state driver 83. An output terminal 91 is commonly coupled to inverting input terminal 92 of comparator 81 and to the column conductors as shown in FIG. 2. An input terminal 95 of calibration circuit 88 is coupled for receiving a start signal and an output terminal 96 of calibration circuit 88 is coupled to a control terminal 97 of comparator 81. An output terminal 98 of calibration circuit 88 is coupled to an input terminal 99 of one-stage serial-to-parallel converter 87. Another input terminal 101 of one-stage serial-to-parallel converter 87 is coupled for receiving a serial input from channel n-1. An output terminal 102 of one-stage serial-to-parallel converter 87 is coupled to an input terminal 103 of driver control circuit 82 and as a serial output for coupling to channel n+1. An output terminal 110 of one-stage serial-to-parallel converter 87 is connected to input terminal 111 of driver control circuit 82. In operation, when display 10 is powered up, calibration circuit 88 transmits a reference signal to comparator 81 via control ■ terminal 97. In addition, calibration circuit 88 cycles display 10 to display a full white screen. In particular, the rows of display 10 are sequentially selected by sequentially activating row conductor driver circuits 37, 38, and 39. When row conductor driver circuit 37 is selected, it activates row conductor 27, while calibration circuit 88 enables driver control circuit 82 to turn on the sub-pixels coupled to row conductor 27. For example, row conductor driver circuit 37 places about eighty volts on row conductor 27 and column conductor driver circuits 47, 48, and 49 place about zero volts on column conductors 17, 18, and 19, respectively, thereby causing sub-pixels 50, 60, and 70 to conduct current. Ideally, each sub-pixel emits a sufficient current to create a white signal . For sub-pixels that are strong emitters, the voltage appearing at the output of the column driver circuit is greater than the reference voltage V REF causing the comparator to trip. Thus, for that sub-pixel, a logic high or one voltage level is stored in serial-to-parallel converter 87. If the comparator does not trip, a logic low or zero voltage level is stored in serial-to-parallel converter 87 for that sub-pixel. At the end of a line time, this serial information is streamed out of the column driver register and stored in external memory (not shown) . For example, at the end of the line time, the intensity or luminance information of sub-pixels 50, 60, and 70 is streamed into register 87. The information is then transmitted to the external memory. The next row is then selected and the process continues until all the sub-pixels have been characterized as a strong pixel or a weak pixel. In this way, the entire display is mapped one line at a time, with one bit being output for each sub-pixel. This mapping takes one frame time, i.e., one-sixtieth of one second. Once the display is mapped, the data stored in memory is appended to the proper digital video byte data as it streams into the display. The column driver circuits know, for each row scanned, whether the sub-pixel to be displayed is a strong or a weak sub-pixel. For example, if a logic one is appended to the digital video byte, the sub-pixel is a strong emitting sub-pixel, whereas if a logic zero is appended to the digital video byte, the sub-pixel is a weak emitting sub-pixel. Once display has been mapped, calibration circuit 88 is inactivated. FIG. 4 is a timing diagram 100 illustrating a method for operating FED 10 in a display mode. The display mode is characterized by the creation of a display image at anode 14. It should be understood that timing diagram 100 shown in FIG. 4 will be described together with FIGS. 1, 2, and 3. Represented in FIG. 4 is the selective addressing and activation of sub-pixels 50, 57, and 58. It should be understood that subpixels 60, 67, 68, 70, 77, and 78 can be selected in a similar fashion by activating row conductor driver circuits 48 and 49. At time t 0 , all of the display capacitances are discharged to zero volts by driving the output voltage of column conductor driver circuits 47, 48, and 49 and row conductor driver circuits 37, 38, and 39 to a voltage lower than the threshold voltage of the corresponding electron emitter structures. By way of example, the output voltages of column conductor driver circuits 47, 48, and 49 and the output voltages of row conductor driver circuits 37, 38, and 39 are driven to zero volts. Moreover, nodes 101, 102, 103, 104, 105, 106, 107, 108, and 109 are driven to zero volts. Thus, capacitances 51, 53, 55, 61, 63, 65, 71, 73, and 75 each are at a voltage of substantially zero volts. At time t x , column conductor driver circuits 47, 48, and 49 are placed in a high impedance state and are, therefore, electrically disconnected from FED 10. It should be noted that timing diagram 100 only shows column conductor driver circuit 47 being placed in high impedance state. Row conductor driver circuits 37, 38, and 39 are then sequentially activated as indicated in timing diagram 100 shown in FIG. 4. At time t x , row conductor driver circuits 37, 38, and 39 are outputting, for example, zero volts. This places zero volts on row conductors 27, 28, and 29, respectively. The outputs of column conductor driver circuits 47, 48, and 49 remain in a high impedance state. At time t 2 , row conductor driver circuit 37 is activated and places a voltage greater than the -, threshold voltage of the electron emitter structures on row conductor 27. By way of example, the voltage placed on row conductor 27 is eighty volts. Row conductor driver circuits 38 and 39 continue to maintain row conductors 28 and 29, respectively, at zero volts . It should be understood that capacitances 53 and 55 are effectively in parallel and have an effective capacitance denoted by C effl7 . In a typical FED, there are more than just three row conductors. Thus, the capacitance value of effective capacitance C effl7 is typically much larger than that of capacitance 51. Moreover, the ballast resistors 54 and 56 are effectively in parallel and have an effective resistance value denoted R effl7 , which is typically much less than that of resistance value 52. More particularly, the effective capacitance and the effective resistance values C e£fl7 and R effl7 , respectively, are given by: C e£fl7 = (n-l ) *C actl7 R e « 17 = ι/ ( n-D *R actl7 where C e££17 represents the lumped capacitance associated with the (n-1) row conductors coupled to column conductor 17 that are at zero volts; C actl7 represents the capacitance associated with a single activated row conductor coupled to column conductor 17 ; R e££17 represents the lumped ballast resistance associated with the (n-1) row conductors coupled to column conductor 17 that are at zero volts; R act i 7 represents the ballast resistance associated with a single activated row conductor coupled to column conductor 17; and n is the number of row conductors of FED 10. It should be understood that each column conductor has a similar effective capacitance and effective ballast resistance associated therewith. For example, the effective capacitance and effective ballast resistance associated with column conductor 18 when all but one of the row conductors is activated is given by: c βfflβ = (n-D *c actl8 where C e££18 represents the lumped capacitance associated with the (n-1) row conductors coupled to column conductor 18 that are at zero volts; C actl8 represents the capacitance associated with a single activated row conductor coupled to column conductor 18; R e£fl8 represents the lumped ballast resistance associated with the (n-1) row conductors coupled to column conductor 18 that are at zero volts; R actl8 represents the ballast resistance associated with a single activated row conductor coupled to column conductor 18; and n is the number of row conductors of FED 10. The effective capacitance and effective ballast resistance associated with column conductor 19 is given by: C e££19 = (n-l ) *C actl9 R e££19 = l / (n-l ) *R actl9 where C e£fl9 represents the lumped capacitance associated with the (n-1) row conductors coupled to column conductor 19 that are at zero volts; C actl9 represents the capacitance associated with a single activated row conductor coupled to column conductor 19; R ef£ i 9 represents the lumped ballast resistance associated with the (n-1) row conductors coupled to column conductor 19 that are at zero volts; R e££19 represents the ballast resistance associated with a single activated row conductor coupled to column conductor 19; and n is the number of row conductors of FED 10. Returning to the description of the operation of a sub-pixel such as, for example, sub-pixel 50, capacitances 51 and C e££17 form a capacitive voltage divider network. Because the capacitance value of capacitance C e££17 is much larger than that of capacitance 51, the voltage at node 101 remains at about zero volts and essentially all of the voltage from row conductor driver circuit 37 appears across capacitance 51. If the voltage on the row conductor is greater than the threshold voltage of electron emitter structure 24 (2717) , electron emitter structure 24 (2717) emits electrons, thereby discharging capacitance 51 and charging effective capacitance C a££17 . Therefore, the voltage at node 101 increases, reducing the voltage across electron emitter structure 24 (27ιl7) . When the voltage across electron emitter structure 24 (2717) decreases to a value less than the threshold voltage, it stops emitting electrons, i.e., turns off. Comparator circuit 81 (shown in FIG. 3) cooperates with output terminal 91 to monitor the voltage on the column conductors when the column conductor driver circuits are in a high impedance state and the electron emitter structures are emitting current. The change in voltage measured on the column conductor is proportional to the charge emitted by the electron emitter structures. For example, column conductor driver circuit 47 compares the' measured change in voltage on column conductor 17 to a voltage proportional to the desired intensity of sub-pixel 50, which proportional voltage was previously determined as described with reference to FIG. 2. Column conductor driver circuit 47 shuts off sub-pixel 50 after the proper amount of charge has been emitted. For sub-pixel 50, -when electron emitter structure 24 (2717) is emitting current, the change in charge at node 101 is given by the relationship: q= *c a r ΔV. where q is the total charge emitted by electron emitter structure 24 (2717) ; C actl7 is the capacitance associated with an activated row conductor coupled to column conductor 17; and ΔV 101 is the change in voltage at node 101. Column conductor driver circuit 47 includes an amplitude modulation portion 93 so that capacitance 51 is discharged to a pre-selected voltage rather than zero volts. Thus, a column conductor with a strong sub-pixel, i.e., a strong electron emitter structure, •' • is discharged to a positive voltage, reducing the emitted current that is discharged compared to the amount discharged when capacitance 51 is at a discharge voltage of zero volts. A column conductor with a weak emitting sub-pixel, i.e., a weak electron emitter structure, is discharged to zero volts. Determination of which electron emitter structures are strong or weak may be performed when powering FED 10 by, for example, displaying a single frame of full white and determining which electron emitter structures switch or trip the comparator circuit. Those that do are strong electron emitter structures and those that do not are weak electron emitter structures. The locations of the strong and weak electron emitting structures may be stored in a memory location. After the electron emitter structure 24 (2717) has emitted the desired current, it is turned off by switching column conductor driver circuit 47 from the high impedance state to a high voltage state. This is shown as time t 3 in FIG. 4. During this time, the voltage at node 101 increases because capacitance C effl7 begins charging when the output voltage of column conductor driver circuit 47 is switched to the high voltage state. At time t 4 , the output voltage of row conductor driver circuit 37 is switched from a high voltage, e.g., eighty volts, to a low voltage, e.g., zero volts; thereby discharging capacitances 51, 53, and 55 associated with column conductor 17. At time t 5 , column conductor driver circuit 47 is placed in a high impedance state and the output voltage of row conductor driver circuit 38 transitions from a low voltage state, e.g., zero volts, to a high voltage state, e.g., eighty volts. Column conductor driver circuit 47 monitors the voltage on column conductor 17 and electron emitter structure 24 (2817) emits current. Column conductor driver circuit 47 compares the measured change in voltage on column conductor 17 to a voltage proportional to the desired intensity of sub- pixel 57, which proportional voltage was previously determined as described with reference to FIG. 2. Column conductor driver circuit 48 shuts off sub-pixel 57 after the proper amount of charge has been emitted. For sub-pixel 57, when electron emitter structure 24 (2817) is emitting current, the change in charge at node 104 is given by the relationship: q= *C act ι 7 *ΔVι 04 where q is the total charge emitted by electron emitter structure 24 (2817) ; C actl7 is the capacitance associated with an activated row conductor coupled to column conductor 17; and ΔVι 0 is the change in voltage at node 104. After the electron emitter structure 24 (2817) has emitted the desired current, it is turned off by switching column conductor driver circuit 47 from the high impedance state to a high voltage state. This is shown as time t 6 in FIG. 4. At time t 7 , the output voltage of row conductor driver circuit 38 switches from a high voltage, e.g. eighty volts, to a low voltage, e.g., zero volts; thereby discharging capacitances 51, 53, and 55 associated with column conductor 17. At time t 8 , column conductor driver circuit 47 is placed in a high impedance state and the output voltage of row conductor driver circuit 39 transitions from a low voltage state, e.g., zero volts, to a high voltage state, e.g., eighty volts. Column conductor driver circuit 47 monitors the voltage on column conductor 17 and electron emitter structure 24 (2917) emits current. Column conductor driver circuit 47 compares the measured change in voltage on column conductor 17 to a voltage proportional to the desired intensity of sub- pixel 58, which proportional voltage was previously determined as described hereinbefore. Column conductor driver circuit 47 shuts off sub-pixel 58 after the proper amount of charge has been emitted. For sub- pixel 58, when electron emitter structure 24 (2917) is emitting current, the change in charge at node 107 is given by the relationship: q= *C act ι 7 *ΔVι 07 where q is the total charge emitted by electron emitter structure 24 (2917) ; C actl7 is the capacitance associated with an activated row conductor coupled to column conductor 17 ; and ΔV 107 is the change in voltage at node 107. After the electron emitter structure 24 (29 _ 17) has emitted the desired current, it is turned off by switching column conductor driver circuit 47 from the high impedance state to a high voltage state. This is shown at time t 9 in FIG. 4. It should also be noted that at time t 9 , the output voltage of row conductor driver circuit 39 switches from a high voltage, e.g. eighty volts, to a low voltage, e.g., zero volts; thereby discharging capacitances 51, 53, and 55 associated with column conductor 17. As can be seen from timing diagram 100, another benefit of the present invention is that in addition to using amplitude modulation to control the emission current, pulse width modulation portion 94 of each column conductor driver circuit performs pulse width modulation. For example, assume the timing and variable pulse widths shown in timing diagram 100 and that the desired intensity of sub-pixels 50, 57, and 58 are the same. The amount of time that column conductor driver circuit 47 is in a high impedance state is the least for the time interval between times t s and t 6 and the most for the time interval between times t 8 and t 9 . Thus, electron emitter structure 24 (2817) is a stronger emission structure than electron emitter structure 24 (29>17) . In other words, sub-pixel 57 is a stronger emitting sub-pixel than sub-pixel 58. Sub-pixel 51 is intermediate sub-pixels 57 and 58 in emission strength. Accordingly, the column conductor drivers operate in a pulse width modulation mode to help improve, the luminance uniformity of FED 10. Although only the operation of sub-pixels 50, 57, and 58 have been described, it should be understood the change in voltage at the other sub-pixel emitter nodes of FED 10, i.e., nodes 104, 105, 106, 107, 108, and 109, is directly proportional to the total charge emitted by the electron emitter structure associated with that particular node, i.e., 24, 2817) , 24 (2818) , 24 (2819) , 24 (29ιl7)/ 24 (29jl8) , 24 (29ιl9) , respectively, and that the operation is similar to that described for sub-pixels 60, 67, 68, 70, 77, and 78. By now it should be appreciated that a field emission display that employs both amplitude modulation and pulse width modulation to control its luminance has been provided. The FED comprises a control circuit that includes a tri-state driver that monitors the voltage on the column conductor and uses pulse width modulation to control the current emitted from the electron emitter structures. In addition, the control circuit includes an amplitude modulation portion that controls the charging level on the capacitances associated with the column conductors. While specific embodiments of the present invention have been shown and described, further modifications and improvements will occur to those skilled in the art. It is understood that the invention is not limited to the particular forms shown and it is intended for the appended claims to cover all modifications which do not depart from the spirit and scope of this invention. For example, the row and column conductor driver circuits can be implemented using a microprocessor. In addition, the column conductor driver circuit can be designed to use the rate of change of voltage to control the uniformity of the luminance.

Claims: CLAIMS 1. A method for operating a field emission display having a plurality of column conductors on which electron emitter structures are disposed and a plurality of row conductors having apertures formed therein, wherein a column conductor driver circuit is coupled to a first column conductor of the plurality of column conductors, and wherein the plurality of column conductors and the plurality of row conductors cooperate to form sub-pixels, the method comprising: causing a portion of the electron emitter structures to emit electrons, thereby defining an emission current ; measuring a signal change on at least one of the column conductors of the plurality of column conductors, thereby defining a measured voltage change; comparing the measured voltage change with an intensity voltage value, thereby defining an adjustment voltage value; and adjusting an operating state of the portion of the electron emitter structures that are emitting electrons in accordance with the adjustment voltage value. 2. The method of claim 1, wherein causing the portion of the electron emitter structures to emit electrons comprises applying a row select voltage to a row conductor of the plurality of row conductors. 3. The method of claim 1, wherein causing a portion of the electron emitter structures to emit electrons comprises placing the column conductor driver circuit in a high impedance state. 4. The method of claim 1, wherein measuring the signal change on the at least one of the column conductors of the plurality of column conductors includes measuring a column conductor voltage change. 5. The method of claim 4, wherein adjusting the operating state includes inactivating at least one electron emitter structure. 6. The method of claim 1, wherein adjusting includes using amplitude modulation to change the emission of electrons from predetermined electron emitter structures. 7. The method of claim 6, wherein adjusting includes using pulse width modulation to increase the emission of electrons from the predetermined electron emitter structures. 8. The method of claim 7, wherein adjusting is performed during a single signal frame time. 9. The method of claim 1, wherein adjusting includes using pulse width modulation to increase the emission of electrons from the predetermined electron emitter structures . 10. A method for operating a field emission display having a first conductor coupled to a second conductor via a first capacitance and to a third conductor via a second capacitance, wherein a first conductor driving circuit is coupled to the first conductor and a plurality of electron emitter structures are disposed on the first conductor and a second conductor driver circuit is coupled to the second conductor, the method comprising: causing the plurality of electron emitter structures to emit electrons, thereby defining an emission current; and stopping the plurality of electron emitter structures from emitting electrons when the emission current has emitted a predetermined amount of current . 11. A field emission display, comprising: a first conductor; a first conductor driver circuit coupled to the first conductor, the first conductor driver circuit capable of operating in a high impedance state; a second conductor, the second conductor coupled to the first conductor via a first capacitance; a second conductor driver circuit coupled to the second conductor; a third conductor, the third conductor coupled to the first conductor via a second capacitance; a third conductor driver circuit coupled to the third conductor; and a plurality of electron emitter structures disposed on the first conductor.

Inventors: SMITH ROBERT T, SMITH, ROBERT, T.
Applicants: MOTOROLA INC, MOTOROLA, INC.
Application year: 2001
Main classification: G09G3
IPC codes: G09G3