Method for driving plasma display panel

Abstract: There is provided a method for driving a plasma display panel having front and rear substrates opposed to and facing each other, X and Y electrode lines and orthogonal address electrode lines. The X and Y electrode lines are divided into a plurality of groups (X G1 , X G2 ..; Y G1 , Y G2 ,..) such that no two adjacent pairs of adjacent X and Y electrode lines belong to the same pair of X and Y groups, and the X and Y electrode lines of the respective groups are commonly connected to be driven. At least first and second subfields (SF) are driven in an overlapping manner for displaying gray scales during a unit display period. The method includes the steps of a scan step, an address step, a display step, a second driving step and a repetition step. A reduction in the number of driving devices can be obtained by an AND-logic driving method as a result of the overlap of subfields, and the luminance of light emitted from the plasma display panel can be enhanced by an address-while-display driving method.

Description: The present invention relates to a method for driving a plasma display panel, and more particularly, to a method for driving a three-electrode surface-discharge plasma display panel. FIG. 1 shows a structure of a general three-electrode surface-discharge plasma display panel, and FIG. 2 shows an electrode line pattern of the panel shown in FIG. 1. Referring to FIGS. 1 and 2, address electrode lines A R1 , A G1 , ..., A Gm , A Bm , dielectric layers 11 and 15, Y electrode lines Y 1 , Y 2 ,... Y n , X electrode lines X 1 , X 2 ,..., and X n , phosphors 16, partition walls 17 and a MgO protective film 12 are provided between front and rear glass substrates 10 and 13 of a general surface-discharge plasma display panel 1. The address electrode lines A R1 , A G1 , ..., A Gm , A Bm are coated over the front surface of the rear glass substrate 13 in a predetermined pattern. The lower dielectric layer 15 is entirely coated over the front surface of the address electrode lines A R1 , A G1 , ..., A Gm , A Bm . The partition walls 17 are formed on the front surface of the lower dielectric layer 15 to be parallel to the address electrode lines A R1 , A G1 , ..., A Gm , A Bm . The partition walls 17 define discharge areas of the respective pixels and prevent optical crosstalk among pixels. The phosphors 17 are coated between partition walls 17. The X electrode lines X 1 X 2 ,... X n and the Y electrode lines Y 1 Y 2 ,... Y n are arranged on the rear surface of the front glass substrate 10 so as to be orthogonal to the address electrode lines A R1 , A G1 , ..., A Gm , A Bm in a predetermined pattern. The respective intersections define corresponding pixels. The X electrode lines X 1 , X 2 ,... and X n and the Y electrode lines Y 1 , Y 2 ,... Y n are each comprised of conductive indium tin oxide (ITO) electrode lines (X na and Y na of FIG. 2) and metal bus electrode lines (X nb and Y nb of FIG. 2). The upper dielectric layer 11 is entirely coated over the rear surface of the X electrode lines X 1 , X 2 ,... X n and the Y electrode lines Y 1 , Y 2 ,... Y n . The MgO protective film 12 for protecting the panel 1 against strong electrical fields is entirely coated over the rear surface of the upper dielectric layer 11. A gas for forming plasma is hermetically sealed in a discharge space 14. The above-described plasma display panel is basically driven such that a reset step, an address step and a display step are sequentially performed in a unit subfield. In the reset step, wall charges remaining in the previous subfield are erased and space charges are evenly formed. In the address step, the wall charges are formed in a selected pixel area. Also, in the display step, light is produced at the pixel at which the wall charges are formed in the address step. In other words, if alternating pulses of a relatively high voltage are applied between the X electrode lines X 1 , X 2 ,... X n and the Y electrode lines Y 1 , Y 2 ,... Y n , a surface discharge occurs at the pixels at which the wall charges are formed. Here, plasma is formed at the gas layer of the discharge space 14 and the phosphors 16 are excited by ultraviolet rays to thus emit light. In the above-described driving method, in order to perform gray scale display on a plasma display panel, a time-divisional driving method in which a frame, which is a unit display period, is divided into subfields each having different display times to display gray scales, is employed. For example, in the case of displaying 256 gray scales by 8-bit image data in units of frames, 8 subfields are set to each frame (in the case of a sequential driving method) or field (in the case of a non-interlaced driving method). Here, according to the method of arranging the respective subfields on a unit display period, there are an address-display separation driving method and an address-while-display driving method. According to the address-display separation driving method, since the time regions of the respective subfields are separated in a unit display period, the time regions of an address period and a display period are also separated in each subfield. Thus, in an address period, a pair of X and Y electrode lines must wait until the other pairs of X and Y electrode lines are all addressed even after the pertinent pair of X and Y electrode lines are addressed. Thus, the time for the address period increases for each subfield, which relatively reduces the time for a display period. Although the address-display separation driving method is advantageous in that the driving circuit and algorithm are simple, the luminance of a plasma display panel driven based on this method is disadvantageously low. According to the address-while-display driving method, since the time regions of the respective subfields overlap in a unit display period, the time regions of the address and display periods in the respective subfields also overlap. Thus, immediately after addressing of each pair of X and Y electrode lines is performed in an address period, a display discharge step is performed. Since the time for the address period of each subfield is reduced, the display period is relatively increased. Although the address-while-display driving method is disadvantageous in that the driving circuit and algorithm are complex, the luminance of light emitted from a plasma display panel driven based on this method is advantageously increased. The applicant of the present invention proposed an AND-logic driving method in which X electrode lines X 1 , X 2 ,... X n are divided into a plurality of X groups and Y electrode lines Y 1 , Y 2 ,... Y n are divided into a plurality of Y groups such that no two adjacent pairs of adjacent X and Y electrode lines belong to the same pair of X and Y groups, and the X and Y electrode lines are driven by being connected by a common line in units of X and Y groups (U.S. Patent Application No. 09/081,827). According to this driving method, the number of driving devices of X and Y riving circuits can be reduced by applying the AND-logic driving method to the address-display separation driving method. However, since the address-while-display driving method is not used, the luminance of light emitted from a plasma display panel cannot be enhanced. "1998 SID International Symposium Digest of Technical Papers", Anheim, Ca: SID, US (1998), 29, pages 283-286 discloses a method for driving a plasma display panel in which the number of scan drivers can be reduced by an order of magnitude using gas-discharge AND logic. EP 0938073 discloses a circuit and method for driving a plasma display panel in which an occurrence of flicker is prevented by making interfaces between driving blocks continuous with respect to time. According to the invention, there is provided a method for driving a plasma display panel according to the wording of claim 1. The invention thus provides a method for driving a plasma display panel having front and rear substrates opposed to and facing each other, X and Y electrode lines formed between the front and rear substrates to be parallel to each other, and address electrode lines formed to be orthogonal to the X and Y electrode lines, to define corresponding pixels at interconnections. In the driving method, the X electrode lines are divided into a plurality of X groups and the Y electrode lines are divided into a plurality of Y groups such that no two adjacent pairs of adjacent X and Y electrode lines belong to the same pair of X and Y groups, and the X and Y electrode lines of the respective groups are commonly connected to be driven, and at least first and second subfields are driven in an overlapping manner for displaying gray scales during a unit display period. The method includes the steps of a scan step, an address step, a display step, a second driving step and a repetition step. In the scan step, a Y scan pulse of a first polarity is applied to Y electrode lines of a pair of X and Y groups to which a pair of X and Y electrode lines of the first subfield belong, and an X scan pulse of a second polarity opposite to the first polarity is applied to X electrode lines, to form wall charges in the discharge space around the pair of X and Y electrode lines. In the address step, a data signal corresponding to the pair of X and Y electrode lines of the first subfield is applied to all address electrode lines to erase the wall charges formed at unselected discharge cells. In the display step, display pulses are alternately applied to electrode lines of a pair of X and Y groups to which the pair of the X and Y electrode lines belong, to cause a display discharge at discharge cells where wall charges are formed. In the second driving step, the scan, address and display steps are performed for the pair of X and Y groups to which a pair of X and Y electrode lines of the second subfield belong, the address step being performed at different timing points. Also, in the repetition step, the scan, address, display steps and the second driving step are repeatedly performed for pairs of X and Y groups to which the remaining pairs of X and Y electrode lines of the first and second subfields belong. This method enables a reduction in the number of driving devices of X and Y driving circuits and can enhance the luminance of light emitted from the plasma display panel by using an address-while-display driving method. Since the respective pairs of X and Y electrode lines are driven by pairs of X and Y groups to which they belong, AND-logic driving is performed. Also, the respective subfields are driven in an overlapping manner by repeatedly performing the scan, address, display and second driving steps. Accordingly, the number of driving devices of X and Y driving circuits can be reduced by an AND-logic driving method, and the luminance of light emitted from the plasma display panel can be enhanced by an address-while-display driving method. Examples of the invention will now be described in detail with reference to the accompanying drawings, in which: FIG. 1 shows an internal perspective view illustrating a structure of a general three-electrode surface-discharge plasma display panel; FIG. 2 is a cross section of an example of a pixel of the panel shown in FIG. 1; FIG. 3 is a connection diagram of electrode lines of a plasma display panel based on a driving method according to the present invention; FIG. 4 is a timing diagram showing the structure of a unit display period based on an address-while-display driving method employed in the driving method according to the present invention; FIG. 5 is a waveform diagram of driving signals applied to pairs of X and Y electrode groups X G1 and Y G1 to which a first pair of X and Y electrode lines X 1 and Y 1 shown in FIG. 3 belong, according to a first embodiment of the present invention; FIG. 6 is a waveform diagram of driving signals applied to pairs of X and Y electrode groups X G1 and Y G1 to which a first pair of X and Y electrode lines X 1 and Y 1 shown in FIG. 3 belong, according to a second embodiment of the present invention; FIG. 7 is a timing diagram illustrating the procedure of driving a first pair of X and Y electrode lines X 1 and Y 1 of a first subfield, a second pair of X and Y electrode lines X 2 and Y 2 of the first subfield and a first pair of X and Y electrode lines X 1 and Y 1 of a second subfield, by the driving waveforms shown in FIG. 6; FIG. 8 is a timing diagram illustrating the state in which polarities of display pulses shown in FIG. 7 are converted into positive polarities; FIG. 9 is a waveform diagram of driving signals applied to pairs of X and Y electrode groups X G1 and Y G1 to which a first pair of X and Y electrode lines X 1 and Y 1 shown in FIG. 3 belong, according to a third embodiment of the present invention; FIG. 10 is a timing diagram illustrating the procedure of driving a first pair of X and Y electrode lines X 1 and Y 1 of a first subfield, a second pair of X and Y electrode lines X 2 and Y 2 of the first subfield and a first pair of X and Y electrode lines X 1 and Y 1 of a second subfield, by the driving waveforms shown in FIG. 9; FIG. 11 is a diagram illustrating the state of discharge cells at various timing points shown in FIG. 9; FIG. 12 is a timing diagram illustrating the procedure of driving a first pair of X and Y electrode lines X 1 and Y 1 of a first subfield, a second pair of X and Y electrode lines X 2 and Y 2 of the first subfield and a first pair of X and Y electrode lines X 1 and Y 1 of a second subfield, according to a fourth embodiment of the present invention; FIG. 13 is a timing diagram illustrating the procedure of driving a first pair of X and Y electrode lines X 1 and Y 1 of a first subfield, a second pair of X and Y electrode lines X 2 and Y 2 of the first subfield and a first pair of X and Y electrode lines X 1 and Y 1 of a second subfield, according to a fifth embodiment of the present invention; FIG. 14 is a timing diagram illustrating the procedure of driving a first pair of X and Y electrode lines X 1 and Y 1 of a first subfield and a second pair of X and Y electrode lines X 2 and Y 2 of the first subfield, according to a sixth embodiment of the present invention; FIG. 15 is a timing diagram illustrating the procedure of driving a first pair of X and Y electrode lines X 1 and Y 1 of a first subfield and a second pair of X and Y electrode lines X 2 and Y 2 of the first subfield, according to a seventh embodiment of the present invention; and FIG. 16 is a timing diagram illustrating the procedure of driving a first pair of X and Y electrode lines X 1 and Y 1 of a first subfield, a second pair of X and Y electrode lines X 2 and Y 2 of the first subfield and a third pair of X and Y electrode lines X 3 and Y 3 of the first subfield, according to an eighth embodiment of the present invention. FIG. 3 is a connection diagram of electrode lines of a plasma display panel based on a driving method according to the present invention. Referring to FIG. 3, X electrode lines X 1 , X 2 ,... X n are divided into n/3 X groups X G1 , X G2 ,... X Gn/3 (Here, n is the number of pairs of X and Y electrode lines.) and the Y electrode lines Y 1 and Y 2 ,... Y n are also divided into n/3 X groups Y G1 and Y G2 ,... Y Gn/3 . Also, the electrode lines of the respective groups are commonly connected to be driven. Here, the respective pairs of X and Y groups to which the respective pairs of adjacent X and Y electrode lines X 1 Y 1 , X 2 Y 2 ,... X n Y n belong, i.e., X G1 Y G1 , X G1 Y G2 , X G1 Y G3 , X G2 Y G1 , X G2 Y G2 , X G2 Y G3 , X G3 Y G1 , X G3 Y G2 , X G3 Y G3 ,..., are all different. In a state in which the X and Y electrode lines are connected in such a manner, an AND-logic driving method, which will be described below, and an address-while-display driving method, are performed, thereby reducing the numbers of output driving devices of X and Y drivers 31 and 32 to 1/3, respectively, and enhancing the luminance of light emitted from a plasma display panel 1. In FIG. 3, reference numeral 33 denotes an address driver for driving address electrode lines A R1 , A G1 , A B1 ,... A Rm , A Gm , A Bm. FIG. 4 is a timing diagram showing the structure of a unit display period based on an address-while-display driving method employed in the driving method according to the present invention. Referring to FIG. 4, display pulses are continuously applied to electrode lines belonging to all the X and Y groups, and scan and address pulses are applied between each of the display pulses. In other words, in a unit subfield, scan and address steps are sequentially performed with respect to electrode lines of a pair of X and Y groups to which individual pairs of X and Y electrode lines belong, and a display step is performed for the remaining time. Here, the order of pairs of X and Y electrode lines for scanning and addressing is determined by the driving order of subfields. For example, after electrode lines of a pair of X and Y groups to which a pair of X and Y electrode lines of a first subfield SF 1 belong are driven, electrode lines of a pair of X and Y groups to which a pair of X and Y electrode lines of a second subfield SF 2 belong are then driven. Likewise, if electrode lines of a pair of X and Y groups to which a pair of X and Y electrode lines of an eighth subfield SF 8 belong are driven, electrode lines of a pair of X and Y groups to which another pair of X and Y electrode lines of a first subfield SF 1 belong are driven. Referring to FIG. 4, a unit field or frame is divided into 8 subfields SF 1 , SF 2 ,... SF 8 for achieving a time-divisional gray scale display. Also, in each subfield, reset, address and sustain-discharge steps are performed, and the time allocated to each sub-field is determined by the display discharge time corresponding to gray scales. For example, in the case of displaying 256 gray scales by 8-bit image data in units of frames, assuming that a unit frame, generally 1/60 sec, consists of 255 unit times, the first subfield SF 1 driven by the image data of the least significant bit has 1 (2 0 ) unit time, the second subfield SF 2 2 (2 1 ) unit times, the third subfield SF 3 4 (2 2 ) unit times, the fourth subfield SF 4 8 (2 3 ) unit times, the fifth subfield SF 5 16 (2 4 ) unit times, the sixth subfield SF 6 32 (2 5 ) unit times, the seventh subfield SF 7 64 (2 6 ) unit times, and the eighth subfield SF 8 driven by the image data of the most significant bit 128 (2 7 ) unit time, respectively. In other words, since the sum of the unit times allocated to the respective subfields is 255 unit times, it is possible to achieve 255 gray scale display, and 256 gray scale display inclusive of one gray scale in which a no display discharge occurs in any subfield. Here, the time for a unit subfield is equal to the time for a unit frame. However, the respective unit subfields overlap based on a pair of driven X and Y electrode lines to form a unit frame. The numbers of output driving devices for the X and Y drivers 31 and 32 can be reduced to 1/3, respectively, by employing the address-while-display driving method to the connection method shown in FIG. 3. Also, the luminance of light emitted from the plasma display panel 1 can be enhanced. Now, the address-while-display driving method and the AND-logic driving method will be described in more detail. FIG. 5 is a waveform diagram of driving signals applied to a pair of X and Y electrode groups X G1 and Y G1 to which a first pair of X and Y electrode lines X 1 and Y 1 shown in FIG. 3 belong, according to a first embodiment of the present invention. In FIG. 5, reference mark S YG1 denotes a driving signal of a first Y group Y G1 , reference mark S XG1 denotes a driving signal of a first X group X G1 , and reference mark S AR1...ABM denotes data signals applied to all address electrode lines (A R1 , A G1 , A B1 ,... A Rm , A Gm , A Bm of FIG. 3), respectively. Referring to FIG. 5, Y display pulses P DY1 , P DY2 ,... and X display pulses P DX1 , P DX2 ,... are alternately applied to the first pair of X and Y groups X G1 and Y G1 . A scan period T S1 and an address period T A1 for the first pair of X and Y electrode lines X 1 and Y 1 of a subfield (one of subfields SF 1 , SF 2 ,... SF 8 of FIG. 4) are set during the time between a Y display pulse P DY0 and a first Y display pulse P DY1 . Reference mark T D1 denotes a display period for the first pair of X and Y electrode lines X 1 and Y 1 of the pertinent subfield. During a scan period T S1 for a pair of X and Y electrode lines, e.g., the first pair of X and Y electrode lines X 1 and Y 1 , a negative-polarity Y scan pulse P SY1 is applied to the Y electrode lines (Y 1 , Y 4 and Y 7 of FIG. 3) of the pair of X and Y groups X G1 and Y G1 to which the pair of the X and Y electrode lines X 1 and Y 1 belong, and a positive-polarity X scan pulse P SX1 is applied to the X electrode lines (X 1 , X 2 and X 3 of FIG. 3). Accordingly, positive-polarity wall charges are formed in the discharge space around the first Y electrode line Y 1 , and negative-polarity wall charges are formed in the discharge space around the first X electrode line X 1 . At the time when application of the scan pulses P SY1 and P SX1 is terminated, a voltage is applied between the first pair of X and Y electrode lines X 1 and Y 1 due to wall charges. Thus, a discharge is performed between the pair of X and Y electrode lines X 1 and Y 1 by the negative-polarity display pulse P DX1 applied to the first X group X G1 , so that negative-polarity wall charges are formed in the discharge space around the first Y electrode line Y 1 and positive-polarity wall charges are formed in the discharge space around the first X electrode line X 1 . During a subsequent address period T A1 , data signals S AR1..ABm are applied to all address electrode lines A R1 , A G1 , A B1 ,... A Rm , A Gm , A Bm , so that wall charges formed at unselected discharge cells are erased. In other words, as a negative-polarity data pulse P A1 is applied to the address electrode lines of unselected discharge cells, the wall charges formed at unselected discharge cells are erased. During a subsequent display period T D1 , display pulses P DY1 , P DX2 , P DY2 , P DX3 , P DY3 , P DX4 ,... are alternately applied to the electrode lines of the pair of X and Y groups X G1 and Y G1 to which the first pair of X and Y electrode lines X 1 and Y 1 belong, so that a display discharge occurs at discharge cells where wall charges are formed. The driving procedure of the scan and address periods T S1 and T A1 is consistently performed with respect to the pair of X and Y groups to which a pair of X and Y electrode lines of another subfield belong. For example, during the time between first and second Y display pulse P DY1 and P DY2 , scan and address steps are performed with respect to a pair of X and Y electrode lines of another subfield. Also, during the time between second and third Y display pulse P DY2 and P DY3 , scan and address steps are performed with respect to a pair of X and Y electrode lines of another subfield. FIG. 6 is a waveform diagram of driving signals applied to a pair of X and Y electrode groups X G1 and Y G1 to which a first pair of X and Y electrode lines X 1 and Y 1 shown in FIG. 3 belong, according to a second embodiment of the present invention. In FIG. 6, the same reference marks as those in FIG. 5 denote the same functional elements. Referring to FIG. 6, in an address period T A1 , while the data pulse P A1 of an address signal for erasing wall charges of unselected discharge cells is applied, bias pulses P BX1 and P BY1 having the same polarity with the data pulse P A1 of the address signal are applied to the electrode lines of X and Y electrode groups X G1 and Y G1 to which the first pair of X and Y electrode lines X 1 and Y 1 belong. Accordingly, much more wall charges of unselected discharge cells can be erased. FIG. 7 is a timing diagram illustrating the procedure of driving a first pair of X and Y electrode lines (Y 1 and X 1 of FIG. 3) of a first subfield (SF 1 of FIG. 4), a second pair of X and Y electrode lines (Y 2 and X 2 of FIG. 3) of the first subfield SF, and a first pair of X and Y electrode lines (Y 1 and X 1 of FIG. 3) of a second subfield (SF 2 of FIG. 4), by the driving waveforms shown in FIG. 6. In FIG. 7, the same reference marks as those in FIG. 6 denote the same functional elements. Reference mark S YG1 denotes a driving signal of a first Y group Y G1 , reference mark S YG2 denotes a driving signal of a second Y group (Y G2 of FIG. 3), reference mark S YG3 denotes a driving signal of a third Y group (Y G3 of FIG. 3), reference mark S XG2 denotes a driving signal of a second X group (X G2 of FIG. 3), and reference mark S XG3 denotes a driving signal of a third X group (X G3 of FIG. 3), respectively. Referring to FIG. 7, scan and address periods for the first pair of X and Y electrode lines X 1 and Y 1 of the first subfield SF 1 are performed at the starting time of a first unit driving period ranging from 0H to 1H. Next, scan and address periods for a pair of X and Y electrode lines of a second SF 2 are performed during the time between first and second Y display pulses P DY1 and P DY2 (not shown). Then, scan and address periods for a pair of X and Y electrode lines of a third SF 3 are performed during the time between second and third Y display pulses P DY2 and P DY3 (not shown). Thus, scan and address periods for a pair of X and Y electrode lines of an eighth subfield (SF 8 of FIG. 4) are performed immediately before application of an eighth Y display pulse P DY8 (not shown). Next, scan and address periods for the second pair of X and Y electrode lines X 2 and Y 2 of the first subfield SF 1 are performed at the starting time of a second unit driving period ranging from 1H. Also, scan and address periods for a first pair of X and Y electrode lines X 1 and Y 1 of the second SF 2 are performed during the time between ninth and tenth Y display pulses P DY9 and P DY10 (not shown). Next, scan and address periods for a pair of X and Y electrode lines of a third SF 3 are performed during the time between tenth and eleventh Y display pulses P DY10 and P DY11 (not shown). Likewise, scan and address periods for a pair of X and Y electrode lines of a fourth SF 4 are performed during the time between eleventh and twelfth Y display pulses P DY11 and P DY12 (not shown). FIG. 8 is a timing diagram illustrating the state in which polarities of display pulses shown in FIG. 7 are converted into positive polarities. In FIG. 8, the same reference marks as those in FIG. 7 denote the same functional elements. Referring to FIG. 8, scan and address periods for the first pair of X and Y electrode lines X 1 and Y 1 of the first subfield (SF 1 of FIG. 4) are performed at the starting time of a first unit driving period ranging from 0H to 1H, which will now be described in detail. A positive-polarity Y scan pulse P SY1 is applied to the Y electrode lines (Y 1 , Y 4 and Y 7 of FIG. 3) of the pair of X and Y groups X G1 and Y G1 to which a pair of the X and Y electrode lines of the first subfield SF 1 , e.g., the first pair of X and Y electrode lines X 1 and Y 1 belong, and a negative-polarity X scan pulse P SX1 is applied to the X electrode lines (X 1 , X 2 and X 3 of FIG. 3). Accordingly, negative-polarity wall charges are formed in the discharge space around the first Y electrode line Y 1 , and positive-polarity wall charges are formed in the discharge space around the first X electrode line X 1 . At the time when application of the scan pulses P SY1 and P SX1 is terminated, a voltage due to the wall charges is applied between the first pair of X and Y electrode lines X 1 and Y 1 . Thus, a discharge is performed between the pair of X and Y electrode lines X 1 and Y 1 by the positive-polarity display pulse P DX1 applied to the first X group X G1 , so that positive-polarity wall charges are formed in the discharge space around the first Y electrode line Y 1 and negative-polarity wall charges are formed in the discharge space around the first X electrode line X 1 . Next, data signals S AR1...ABm corresponding to the first pair of X and Y electrode lines X 1 and Y 1 are applied to all address electrode lines A R1 , A G1 , A B1 ,... A Rm , A Gm , A Bm , so that wall charges formed at unselected discharges are erased. In other words, as a positive-polarity data pulse P A1 is applied to the address electrode lines of unselected discharge cells, the wall charged formed at unselected discharge cells are erased. While the data pulse P A1 of an address signal is applied, bias pulses P BX1 and P BY1 having the opposite polarity with the data pulse P A1 of the address signal are applied to the electrode lines of X and Y electrode groups X G1 and Y G1 to which the first pair of X and Y electrode lines X 1 and Y 1 belong. Accordingly, much more wall charges of unselected discharge cells can be erased. Next, until the first unit driving period ranging from 0H to 1H is terminated, display pulses P DY1 , P DX2 , P DY2 , P DX3, P DY3, P DX4 ,... are alternately applied to the electrode lines of the pair of X and Y groups X G1 and Y G1 to which the first pair of X and Y electrode lines X 1 and Y 1 belong, so that a display discharge occurs at discharge cells where wall charges are formed. Here, scan and address periods for a pair of X and Y electrode lines of a second SF 2 are performed during the time between first and second Y display pulses P DY1 and P DY2 (not shown). Next, scan and address periods for a pair of X and Y electrode lines of a third SF 3 are performed during the time between second and third Y display pulses P DY2 and P DY3 (not shown). Thus, scan and address periods for a pair of X and Y electrode lines of an eighth subfield (SF 8 of FIG. 4) are performed immediately before application of an eighth Y display pulse P DY8 (not shown). Next, scan and address periods for the second pair of X and Y electrode lines X 2 and Y 2 of the first subfield SF 1 are performed at the starting time of a second unit driving period ranging from 1H. Also, scan and address periods for a first pair of X and Y electrode lines X 1 and Y 1 of the second SF 2 are performed during the time between ninth and tenth Y display pulses P DY9 and P DY10 (not shown). Next, scan and address periods for a pair of X and Y electrode lines of a third SF 3 are performed during the time between tenth and eleventh Y display pulses P DY10 and P DY11 (not shown). Likewise, scan and address periods for a pair of X and Y electrode lines of a fourth SF 4 are performed during the time between eleventh and twelfth Y display pulses P DY11 and P DY12 (not shown). FIG. 9 is a waveform diagram of driving signals applied to a pair of X and Y electrode groups X G1 and Y G1 to which a first pair of X and Y electrode lines X 1 and Y 1 shown in FIG. 3 belong, according to a third embodiment of the present invention. FIG. 10 is a timing diagram illustrating the procedure of driving a first pair of X and Y electrode lines X 1 and Y 1 of a first subfield, a second pair of X and Y electrode lines X 2 and Y 2 of the first subfield and a first pair of X and Y electrode lines X 1 and Y 1 of a second subfield, by the driving waveforms shown in FIG. 9. FIG. 11 is a diagram illustrating the state of discharge cells at various timing points shown in FIG. 9. In FIGS. 9, 10 and 11, the same reference marks as those of FIGS. 7 and 8 denote the same functional elements. In FIG. 11, reference mark X denotes an X electrode of a discharge cell, reference mark Y denotes a Y electrode of a discharge cell, and reference mark D denotes an address electrode of a discharge cell, respectively. Referring to FIGS. 9, 10 and 11, scan and address periods for the first pair of X and Y electrode lines X 1 and Y 1 of the first subfield (SF 1 of FIG. 4) are performed at the starting time of a first unit driving period ranging from 0H to 1H, which will now be described in detail. During a scan period T S1 for the first pair of X and Y electrode lines X 1 and Y 1 , a negative-polarity Y reset pulse P RY1 is applied to the Y electrode lines (Y 1 , Y 4 and Y 7 of FIG. 3) of the pair of X and Y groups X G1 and Y G1 to which the pair of the X and Y electrode lines X 1 and Y 1 belong, and a positive-polarity X reset pulse P RX1 is applied to the X electrode lines (X 1 , X 2 and X 3 of FIG. 3). Accordingly, wall charges existing in the discharge space around the first pair of X and Y electrode line X 1 and Y 1 are erased (at the timing point t1). The above-described erasing operation is performed for the purpose of increasing the accuracy of scan and address driving steps (at the subsequent timing points t2 and t3). Next, a positive-polarity Y scan pulse P SY1 is applied to the Y electrode lines Y 1 , Y 4 and Y 7 of the pair of X and Y groups X G1 and Y G1 to which the first pair of the X and Y electrode lines X 1 and Y 1 belong, and a negative-polarity X scan pulse P SX1 is applied to the X electrode lines X 1 , X 2 and X 3 . Accordingly, negative-polarity wall charges are formed in the discharge space around the first Y electrode line Y 1 , and positive-polarity wall charges are formed in the discharge space around the first X electrode line X 1 (at the timing point t2). At the time when application of the scan pulses P SY1 and P SX1 is terminated, a voltage due to the wall charges is applied between the first pair of X and Y electrode lines X 1 and Y 1 . During a subsequent address period T A1 , data signals S AR1...ABm corresponding to the first pair of X and Y electrode lines X 1 and Y 1 are applied to all address electrode lines A R1 , A G1 , A B1 ,... A Rm , A Gm , A Bm , so that wall charges formed at unselected discharges are erased. In other words, as a positive-polarity data pulse P A1 is applied to the address electrode lines of unselected discharge cells, the wall charged formed at unselected discharge cells are erased. While the data pulse P A1 of an address signal is applied, bias pulses P BX1 and P BY1 having the opposite polarity with the data pulse P A1 of the address signal are applied to the electrode lines of X and Y electrode groups X G1 and Y G1 to which the first pair of X and Y electrode lines X 1 and Y 1 belong. Accordingly, much more wall charges of unselected discharge cells can be erased (at the timing point t3). Next, until the first unit driving period ranging from 0H to 1H is terminated (T D1 ), negative-polarity display pulses P DY1 , P DX2 , P DY2 , P DX3 , P DY3 , P DX4 ,... are alternately applied to the electrode lines of the pair of X and Y groups X G1 and Y G1 to which the first pair of X and Y electrode lines X 1 and Y 1 belong, so that a display discharge occurs at discharge cells where wall charges are formed (at the timing point t4). Here, scan and address periods for a pair of X and Y electrode lines of a second SF 2 are performed during the time between first and second Y display pulses P DY1 and P DY2 (not shown). Next, scan and address periods for a pair of X and Y electrode lines of a third SF 3 are performed during the time between second and third Y display pulses P DY2 and P DY3 (not shown). Thus, scan and address periods for a pair of X and Y electrode lines of an eighth subfield (SF 8 of FIG. 4) are performed immediately before application of an eighth Y display pulse P DY8 (not shown). Next, scan and address periods for the second pair of X and Y electrode lines X 2 and Y 2 of the first subfield SF 1 are performed at the starting time of a second unit driving period ranging from 1H. Also, scan and address periods for a first pair of X and Y electrode lines X 1 and Y 1 of the second SF 2 are performed during the time between ninth and tenth Y display pulses P DY9 and P DY10 (not shown). Next, scan and address periods for a pair of X and Y electrode lines of a third SF 3 are performed during the time between tenth and eleventh Y display pulses P DY10 and P DY11 (not shown). Likewise, scan and address periods for a pair of X and Y electrode lines of a fourth SF 4 are performed during the time between eleventh and twelfth Y display pulses P DY11 and P DY12 (not shown). FIG. 12 is a timing diagram illustrating the procedure of driving a first pair of X and Y electrode lines X 1 and Y 1 of a first subfield, a second pair of X and Y electrode lines X 2 and Y 2 of the first subfield and a first pair of X and Y electrode lines X 1 and Y 1 of a second subfield, according to a fourth embodiment of the present invention. In FIG. 12, the same reference marks as those in FIG. 10 denote the same functional elements. The driving waveforms shown in FIG. 12 further include periodically appearing bias pulses P BY1 , P BX1 ,..., P BY9 , P BX9 , P BY10 , P BX10 ,... in addition to those shown in FIG. 10. In other words, before the respective display pulses P DY0 , P DX1 ..., P DY12 , P DX13 ... are applied to the electrode lines of all X and Y groups (Y G1 ,..., Y Gn/3 , X G1 ,..., X Gn/3 of FIG. 3), bias pulses having the same polarities with those of bias pulses P BY1 , P BX1 , P BY9 , P BX9 , P BY10 and P BX10 applied in the address step. Therefore, driving errors due to a time difference can be reduced. FIG. 13 is a timing diagram illustrating the procedure of driving a first pair of X and Y electrode lines X 1 and Y 1 of a first subfield, a second pair of X and Y electrode lines X 2 and Y 2 of the first subfield and a first pair of X and Y electrode lines X 1 and Y 1 of a second subfield, according to a fifth embodiment of the present invention. In FIG. 13, the same reference marks as those in FIG. 12 denote the same functional elements. The driving waveforms shown in FIG. 13 further include periodically appearing auxiliary pulses P SY1 ,..., P SX1 ,.... in addition to those shown in FIG. 12. In other words, before the respective display pulses P DY0 , P DX1 ,..., P DY12 , P DX13 ... are applied to the electrode lines of all X and Y groups (Y G1 ,..., Y Gn/3 , X G1 ,... X Gn/3 of FIG. 3), bias pulses P BY1 , P BX1 ,..., P BY9 , P BX9 ,..., P BY10 , P BX10 ,... are applied. Also, before these bias pulses are applied, auxiliary pulses having the same polarities with the scan pulses P SY1 , P SX1 , P SY9 , P SX9 , P SY10 and P SX10 applied in the address step. Therefore, driving errors due to a time difference can be further reduced. FIG. 14 is a timing diagram illustrating the procedure of driving a first pair of X and Y electrode lines X 1 and Y 1 of a first subfield and a second pair of X and Y electrode lines X 2 and Y 2 of the first subfield, according to a sixth embodiment of the present invention. In FIG. 14, the same reference marks as those in FIG. 10 denote the same functional elements. The driving method shown in FIG. 14 further includes cease periods between each of the respective scan and address steps, compared to the driving method shown in FIG. 10. Referring to FIG. 14, after scan pulses P SX1 and P SY1 are applied to the first pair of X and Y groups (X G1 and Y G1 of FIG. 3) and before a data pulse P A9 is applied, there is a first cease period corresponding to the time for the first unit driving time ranging from 0H to 1H. During the first cease period, in order to appropriately erase space charges due to a scan discharge between the first pair of X and Y electrode lines (X 1 and Y 1 of FIG. 3), cease pulses P PY1 , P PX1 ,... P PY8 are applied to electrode lines of the first pair of X and Y groups X G1 and Y G1 to which the first pair of X and Y electrode lines X 1 and Y 1 belong. Accordingly, excess space charges do not form in the discharge space around the first pair of X and Y electrode lines X 1 and Y 1 , thereby attaining a stable state of the space charges. During the time between first and second Y cease pulses P PY1 and P PY2 , a scan discharge occurs at a pair of X and Y electrode lines of a second subfield. Thus, during the time between seventh and eighth Y cease pulses P PY7 and P PY8 , a scan discharge occurs at a pair of X and Y electrode lines of an eighth subfield. At the starting time of a second unit driving period ranging from 1H to 2H, after scan pulses P SX9 and P SY9 are applied to the second pair of X and Y groups (X G2 and Y G2 of FIG. 3) and before a data pulse P A17 is applied, there is a ninth cease period corresponding to the time for the second unit driving time ranging from 0H to 1H. During the time between ninth and tenth Y cease pulses P PY9 and P PY10 , a scan discharge occurs at a pair of X and Y electrode lines of a second subfield. Thus, during the time between fifteenth and sixteenth Y cease pulses P PY15 and P PY16 , a scan discharge occurs at a pair of X and Y electrode lines of an eighth subfield. At the starting time of a third unit driving period ranging from 2H to 3H, a scan discharge occurs at a third pair of X and Y electrode lines X 3 and Y 3 of the first subfield (see P SX17 and P SY17 ). Also, there is a seventeenth cease period corresponding to the time for the third unit driving period ranging from 2H to 3H before a data pulse (not shown) is applied. Immediately before and after an eighth X cease pulse P PX18 , the first pair of X and Y electrode lines X 1 and Y 1 of the second subfield are scanned (see P RX18 , P RY18 , P SX18 and P SY18 ). FIG. 15 is a timing diagram illustrating the procedure of driving a first pair of X and Y electrode lines X 1 and Y 1 of a first subfield and a second pair of X and Y electrode lines X 2 and Y 2 of the first subfield, according to a seventh embodiment of the present invention. In FIG. 15; the same reference marks as those in FIG. 14 denote the same functional elements. Referring to FIG. 15, after reset pulses P RX18 and P RY18 are applied to the first pair of X and Y groups (X G1 and Y G1 of FIG. 3) and before scan pulses P SX9 and P SY9 are applied, there is a first cease period corresponding to the time for a unit driving time ranging from 0H to 1H. During the first cease period, in order to appropriately erase space charges due to a reset discharge between the first pair of X and Y electrode lines (X 1 and Y 1 of FIG. 3), cease pulses P PY1 , P PX1 ,... P PY8 are applied to electrode lines of the first pair of X and Y groups X G1 and Y G1 to which the first pair of X and Y electrode lines X 1 and Y 1 belong. Accordingly, excess space charges do not form in the discharge space around the first pair of X and Y electrode lines X 1 and Y 1 , thereby attaining a stable state of the space charges. During the time between first and second Y cease pulses P PY1 and P PY2 , a reset discharge occurs at a pair of X and Y electrode lines of a second subfield (not shown). Thus, during the time between seventh and eighth Y cease pulses P PY7 and P PY8 , a reset discharge occurs at a pair of X and Y electrode lines of an eighth subfield (not shown). At the starting time of a second unit driving period ranging from 1H to 2H, after reset pulses P RX9 and P RY9 are applied to the second pair of X and Y groups (X G1 and Y G2 of FIG. 3) and before scan pulses P SX17 and P SY17 are applied, there is a ninth cease period corresponding to the time for the second unit driving time ranging from 0H to 1H. During the time between ninth and tenth Y cease pulses P PY9 and P PY10 , a reset discharge occurs at a pair of X and Y electrode lines of a second subfield (not shown). Thus, during the time between fifteenth and sixteenth Y cease pulses P PY15 and P PY16 , a reset discharge occurs at a pair of X and Y electrode lines of an eighth subfield (not shown). At the starting time of a third unit driving period ranging from 2H to 3H, a reset discharge occurs at a third pair of X and Y electrode lines X 3 and Y 3 of the first subfield (see P RX17 and P RY17 ). Also, there is a seventeenth cease period corresponding to the time for the third unit driving period ranging from 2H to 3H before a scan pulse (not shown) is applied. After the reset discharge (see P RX17 and P RY17 ), a reset discharge occurs at the first pair of X and Y electrode lines X 1 and Y 1 of the second subfield (see P RX18 and P RY18 )· FIG. 16 is a timing diagram illustrating the procedure of driving a first pair of X and Y electrode lines X 1 and Y 1 of a first subfield, a second pair of X and Y electrode lines X 2 and Y 2 of the first subfield and a third pair of X and Y electrode lines X 3 and Y 3 of the first subfield, according to an eighth embodiment of the present invention. In FIG. 16, the same reference marks as those in FIG. 15 denote the same functional elements. Referring to FIG. 16, after reset pulses P RX1 and P RY1 are applied to the first pair of X and Y groups (X G1 and Y G1 of FIG. 3) and before scan pulses P SX9 and P SY9 are applied, there is a first cease period corresponding to the time for a unit driving time ranging from 0H to 1H. Also, after a data pulse P A1 is applied to address electrode lines which are not to be displayed and before display pulses P DX17 ,... are applied, there is a second cease period corresponding to the time for a unit driving time ranging from 1H to 2H. During the first and second cease period, in order to appropriately erase space charges due to a reset or address discharge between the first pair of X and Y electrode lines (X 1 and Y 1 of FIG. 3), cease pulses P PY1 ,... are applied to electrode lines of the first pair of X and Y groups X G1 and Y G1 to which the first pair of X and Y electrode lines X 1 and Y 1 belong. Accordingly, excess space charges do not form in the discharge space around the first pair of X and Y electrode lines X 1 and Y 1 , thereby attaining a stable state of the space charges. During the time between first and second Y cease pulses P PY1 and P PY2 , a reset discharge occurs at a pair of X and Y electrode lines of a second subfield (not shown). Thus, during the time between seventh and eighth Y cease pulses P PY7 and P PY8 , a reset discharge occurs at a pair of X and Y electrode lines of an eighth subfield (not shown). During a subsequent second unit driving period ranging from 1H to 2H, at the time between eighth and ninth Y cease pulses P PY8 and P PY9 , an address discharge occurs at the first pair of X and Y electrode lines X 1 and Y 1 of the first subfield (see P BX9 , P BY9 and P A9 ). Thus, during the time between fifteenth and sixteenth Y cease pulses P PY15 and P PY16 , an address discharge occurs at a pair of X and Y electrode lines of an eighth subfield (not shown). During the time between eighth and ninth Y cease pulses P PY8 and P PY9 , after reset pulses P RX9 and P RY9 are applied to the second pairof X and Y groups X G1 and Y G2 and before scan pulses P SX17 and P SY17 are applied, there is a first cease period corresponding to the time for a unit driving time ranging from 1H to 2H. Also, after a data pulse P A17 is applied to address electrode lines which are not to be displayed and before display pulses are applied, there is a second cease period corresponding to the time for a unit driving time. During the time between ninth and tenth Y cease pulses, a reset discharge occurs at a pair of X and Y electrode lines of a second subfield (not shown). Thus, during the time between fifteenth and sixteenth Y cease pulses, a reset discharge occurs at a pair of X and Y electrode lines of an eighth subfield (not shown). During a subsequent third unit driving period ranging from 2H to 3H, at the time between sixteenth and seventh Y cease pulses, an address discharge occurs at a second pair of X and Y electrode lines of the first subfield (see P BX17 , P BY17 and P A17 ). Thus, during the time between twenty-third and twenty-fourth Y cease pulses, an address discharge occurs at a pair of X and Y electrode lines of an eighth subfield (not shown). Likewise, during the time between sixteenth and seventh Y cease pulses, after reset pulses P RX17 and P RY17 are applied to a third pair of X and Y groups X G1 and Y G3 and before scan pulses P SX25 and P SY25 are applied, there is a first cease period corresponding to the time for a unit driving time ranging from 2H to 3H. Also, after a data pulse P A25 is applied to address electrode lines which are not to be displayed and before display pulses are applied, there is a second cease period corresponding to the time for a unit driving time. During the time between seventeenth and eighteenth Y cease pulses, a reset discharge occurs at a pair of X and Y electrode lines of a second subfield (not shown). Thus, during the time between twenty-third and twenty-fourth Y cease pulses, a reset discharge occurs at a pair of X arid Y electrode lines of an eighth subfield (not shown). During a subsequent fourth unit driving period ranging from 3H to 4H, at the time between twenty-fourth and twenty-fifth Y cease pulses, an address discharge occurs at a third pair of X and Y electrode lines X 3 and Y 3 of the first subfield (see P BX25 , P BY25 and P A25 ). During the time between twenty-fourth and twenty-fifth Y cease pulses, a reset discharge occurs at the first pair of X and Y electrode lines X 1 and Y 1 of the second subfield (see P RX26 and P RX27 ). As described above, in the method for driving a plasma display panel method according to the present invention, the respective pairs of X and Y electrode lines are driven by pairs of X and Y groups to which they belong, that is, an AND-logic driving method is performed. Also, since the scan, address and display steps and the second driving step are repeatedly performed, the respective subfields are driven in an overlapping manner. Accordingly, the number of driving devices of X and Y driving circuits can be reduced by an AND-logic driving method, and the luminance of light emitted from the plasma display panel can be enhanced by an address-while-display driving method. Although the invention has been described with respect to a preferred embodiment, it is not to be so limited as changes and modifications can be made which are within the full intended scope of the invention as defined by the appended claims.

Claims: A method for driving a plasma display panel (1) having front and rear substrates (10, 13) opposed to and facing each other, X and Y electrode lines (X n , Y n ) formed between the front and rear substrates to be parallel to each other, and address electrode lines (AGm, ABm) formed to be orthogonal to the X and Y electrode lines, to define corresponding pixels at interconnections, wherein the X electrode lines are divided into a plurality of X groups and the Y electrode lines are divided into a plurality of Y groups such that no two adjacent pairs of adjacent X and Y electrode lines belong to the same pair of X and Y groups, and the X and Y electrode lines of the respective groups are commonly connected to be driven, and wherein at least first and second subfields are driven in an overlapping manner for displaying gray scales during a unit display period, the method comprising the steps of: in a scan step, applying a Y scan pulse of a first polarity to said Y electrode lines and a X scan pulse of a second polarity, opposite to said first polarity, to said X electrode lines to form wall charges in the discharge space around the X and Y electrode lines, said X and Y electrode lines belonging to a first group of XY line pairs which is to be selected in a said first subfield; in an address step, applying a data signal corresponding to the pair of X and Y electrode lines which are to be addressed in said first subfield to all address electrode lines so as to erase the wall charges formed at unselected discharge cells; in a display step, alternately applying display pulses to electrode lines of a pair of X and Y groups to which the pair of X and Y lines belong, to cause a display discharge at discharge cells where wall charges are formed; a driving step of performing the scan, address and display steps for the pair of X and Y groups to which a pair of X and Y electrode lines, which have to be activated in said second subfield, belong; a repetition step of repeatedly performing said scan, address, display and driving step for pairs of X and Y groups to which the remaining pairs of X and Y electrode lines, which have to be activated in said first and second subfield, belong, characterized by comprising the step of: during said address step, applying a pulse to said address electrodes while applying bias pulses of the same polarity to the electrode lines of the pair of said X and Y groups to which the pair of X and Y electrode lines belong, so as to erase the wall charges of the unselected discharge cells. The method according to claim 1, wherein, in the display step, before the respective display pulses are applied to the electrode lines of the pair of X and Y groups, bias pulses having the same polarity and voltage, respectively, of the bias pulses applied in the address step, are applied to the electrode lines of the pair of X and Y groups. The method according to claim 1, wherein, in the scan step, before the scan pulses are applied to the electrode lines of the pair of X and Y groups, a reset pulse of said second polarity is applied to the Y electrode lines of the pair of X and Y groups and a reset pulse of said first polarity is applied to the X electrode lines, to erase the wall charges. The method according to claim 3 wherein, in the scan step, first pulses for appropriately erasing the space discharges are applied to the electrode lines of the pair of X and Y groups to which the pair of X and Y electrode lines belong, so as to define a first period between the application of the reset pulses and the scan pulses, to prevent excess space charges from being formed in the discharge space around the pair of X and Y electrode lines and to allow a stable state of the space charges. The method according to claim 1, wherein, in the display step, before the respective display pulses are applied to the electrode lines of the pair of X and Y groups, auxiliary pulses having the same polarity and voltage as those of the scan pulses applied in the scan step are applied to the electrode lines of the pair of X and Y groups, respectively. The method according to claim 1 wherein second pulses for appropriately erasing the space discharges are applied to the electrode lines of the pair of X and Y groups to which the pair of X and Y electrode lines belong, so as to define a second period after the scan step is terminated and before the address step starts, to prevent excess space charges from being formed in the discharge space around the pair of X and Y electrode lines and to allow a stable state of the space charges. The method according to claim 1 wherein third pulses for appropriately erasing the space discharges are applied to the electrode lines of the pair of X and Y groups to which the pair of X and Y electrode lines belong, so as to define a third period after the address step is terminated and before the display step starts, to prevent excess space charges from being formed in the discharge space around the pair of X and Y electrode lines and to allow a stable state of the space charges.

Inventors: IGARASHI KIYOSHI, ISHII MAKOTO, JUNG NAM-SUNG, KANG KYOUNG-HO, KIM HEE-HWAN, LEE JOO-YUL, LEE SEONG-CHARN, MIKOSHIBA SHIGEO, SHIGA TOMOKAZU, IGARASHI, KIYOSHI, ISHII, MAKOTO., JUNG, NAM-SUNG, KANG, KYOUNG-HO, KIM, HEE-HWAN., LEE, JOO-YUL, LEE, SEONG-CHARN, MIKOSHIBA, SHIGEO, SHIGA, TOMOKAZU, Jung, Nam-sung 502-204 Samsung 5cha Apt., Kim, Hee-hwan. c/o Samsung SDI, Lee, Joo-yul 304 Daepyung-ri, Lee, Seong-charn 301 Samyong Villa
Applicants: MIKOSHIBA SHIGEO, SAMSUNG SDI CO LTD, MIKOSHIBA, SHIGEO, SAMSUNG SDI CO., LTD.
Application year: 2001
Main classification: G09G3
IPC codes: H04N5, G09G3