APPARATUS AND METHODS FOR SAMPLE SELECTION AND REUSE OF RAKE FINGERS IN SPREAD SPECTRUM SYSTEMS

Abstract: An apparatus for reducing storage requirements and for allowing reuse of multiple rake fingers in a spread spectrum system includes a decimation circuit (302) having an associated decimation factor, a memory (304) coupled to the decimation circuit (302), and an interpolation circuit (306) having an interpolation factor coupled to the memory (304). The decimation circuit (302) decimates the sampling rate of received data to produce a decimated rate. The received data is stored in the memory (304) at the decimated rate. The decimated rate is later increased by the interpolation circuit (306) by the interpolation factor when the stored data is retrieved from the memory (304). The memory is a circular buffer or a single port RAM that is accessible by multiple rake fingers substantially simultaneously via selector circuits.

Description: APPARATUS AND METHODS FOR SAMPLE SELECTION AND REUSE OF RAKE FINGERS IN SPREAD SPECTRUM SYSTEMS PRIORITY DATA This application claims priority from the following Provisional Applications: (1) "Method and Apparatus for Decimation-Inteφolation Applied to CDMA Systems," bearing U.S. Serial No. 60/222,027, filed on July 31, 2000; (2) "Apparatus and Method for Concurrent Sample Selection and Reuse of Rake Fingers," bearing U.S. Serial No. 60/222,008, filed on July 31, 2000; (3) "Concurrent Sample Selection, Segmented-Cache for CDMA Rake Fingers," bearing U.S. Serial No. 60/222,025, filed on July 31, 2000; and (4) "Apparatus and Method for Concurrent Sample Selection in a CDMA System," bearing U.S. Serial No. 60/222,029, filed on July 31, 2000. CROSS REFERENCE TO RELATED APPLICATIONS Related applications are: "Flexible CDMA System Architecture", Serial No. ; "Generic Data Path Processor for W-CDMA Applications, Serial No. ; "Generic Finger Architecture for W-CDMA Applications, Serial No. . Each of these applications is filed concurrently herewith and is incoφorated herein by reference. BACKGROUND OF THE INVENTION This invention relates generally to wireless communication systems. Wireless communication has many applications in consumer and business markets. Among the many applications are: mobile wireless, fixed wireless, unlicensed Federal Communications Commission (FCC) wireless, local area network (LAN), cordless telephony, personal base station, telemetry, and others. Generally, each of these applications utilizes unique and frequently incompatible modulation techniques and protocols. Wireless communication devices, such as cellular handsets, typically need to acquire certain cell specific information and characteristics before negotiating a service with a base station. For this piupose, each base station transmits certain cell specific information necessary for a user to acquire services such as paging or cellular telephony from the base station. For example, in CDMA systems, the cell specific information is contained in pilot and/or synchronization channels. The pilot and/or synchronization channels are spread and scrambled with cell specific pseudo-random noise or gold code sequences, which form the basis for frame, slot, and bit timing synchronization for a handset. Multiple users are typically in communication with a single base station. Although such users operate on the same frequency at the same time, various techniques allow multiple users to be distinguished from one another. In CDMA systems, each handset user is assigned a different orthogonal code that is used to spread the data transmitted from the base station so as to distinguish it from the data transmitted to other handset users. Figure 1 illustrates a prior art communication device 100. The communication device 100 includes an antenna 102, a front-end processor 104, a base band processor 106, a microprocessor/controller 108, and a bus for interconnecting the front-end processor 104, the base based processor, and a microprocessor/controller 108. The microprocessor 108 supports the exchange of data and/or instructions to the other components of the communication device 100. The base band processor 106 is coupled to the front-end processor 104 to receive and transmit data. The communication device 100 maybe a mobile handset, a test platform, an embedded modem, a base station or other communication devices in other code-dependent applications. The front-end processor 104 is coupled to the antenna 102 to receive data. The front-end processor 104 includes components and performs functions that are known to those skilled in the art. These components are not shown in the front-end processor 104 for pmrposes of clarity. After data has been processed by the front-end processor, the processed data is supplied to the base band processor 106. In spread spectrum systems, the base band processor has to be able to identify, despread, and decode the data. Despreading (i.e., multiplication of the process data by the same binary spreading waveform as was used to spread the data at the transmitter) and removal of the carrier modulation restore the original baseband data waveform. In practice, multiple copies of the same signal are typically received at communications device 100 within a short time of each other. These copies, which are sometimes called multipath components arise because the signals take different paths of different length from the transmitter antenna to the receiver antenna. In the case of a CDMA system, it is feasible and advantageous to despread and decode several of the multipath components, realign them so that they are also in phase and combine them to produce a stronger signal. To do this, the base band processor in a CDMA system typically takes the form of a rake receiver that has several fingers, each one of which is a receiver that despreads and decodes one of the multipath components. General information about rake receivers can be found at pages 972-982 of J. S. Lee, L. E. Miller, CDMA Systems Engineering Handbook (Artech House 1998). Generally, received data is sampled at a rate known as the chipping rate. In the IS-95 and 3 GPP CDMA standards, the chipping rates are 1.2288 MHz and 3.84 MHz, respectively, which correspond to sampling periods of 0.814 microseconds and 0.2604 microseconds. The sampling period is known as a chip. Data is usually processed in pairs, commonly referred to as "In-Phase" (1) and "Quadrature" (Q) data. A rake finger is supplied with three samples, typically labeled Early, On-Time, and Late, where each sample includes a pair of data (i.e., I and Q data). The On-Time sample contains the data to be decoded. The Early and Late samples are used in tracking tools to ensure that the On-Time sample represents the center of the chip. Two examples of chipping rate are 1.2288 MHz and 3.84 MHz which correspond to sampling periods of 0.814 microseconds and 0.2604 microseconds. These are used in IS95 and 3GPP CDMA systems, respectively. Data arriving at the base band processor 106 is typically over-sampled at an over-sampling rate (e.g., 4x or 8x over-sampling rate) measured with respect to the chipping rate. For example: if the chipping rate is 1.2288 MHz and the over-sampling rate is 4x then the samples will be at 4.9152 MHz. Directly passing received over- sampled data to the base band processor 106 is generally inefficient because the sampling rate of the data may not be at the optimal rate for processing by the base band processor 106 rate. Thus, some type of front-end storage is required. Because the over-sampling rate is typically very fast, such front-end storage is likely to be very expensive, and more memory storage capacity is required as the sampling rate increases. Thus, a need arises for apparatus and methods that provide fast storage of raw data at the front end of the baseband processor without requiring excessive memory space. Further, data is typically despread by multiple rake fingers. A need arises for apparatus and methods that allow reuse of multiple rake fingers to conserve physical silicon space and allow the multiple rake fingers to access the data storage substantially concurrently to achieve faster processing. SUMMARY In an exemplary embodiment of the present invention, the sampling rate of received data is decimated by a factor of D and the received data is stored in memory at the decimated rate. By storing received data at the decimated rate, storage requirements are reduced by a factor of D. This can be done because the data, prior to sampling, has been filtered such that all information at sampling rates greater than twice the filter cut-off frequency has been removed. The stored data is subsequently inteφolated by a factor of IR to restore it to a faster rate, a multiple of the chipping rate. In an exemplary embodiment, decimation and inteφolation operations occur at the beginning of the signal processing chain, thus providing the benefit of reduced storage requirements at the front end of the processing chain. However, decimation and inteφolation operations can occur anywhere in the signal processing chain and therefore are not limited to implementations at the front end. In an exemplary embodiment, the memory is a circular buffer comprising a set of registers. Each register is divided into two parts for storing in-phase and quadrature (I and Q) data, respectively. Once data has been stored into memory (at a decimated rate), a despreading circuit (e.g., a rake receiver), which includes multiple rake fingers, can access the data. The multiple rake fingers can substantially simultaneously access data in the memory via a selector circuit for each rake finger. Each selector circuit includes multiple multiplexers controlled by a set of select lines. The select lines are controlled by an external controller. In another exemplary embodiment, the memory is a single port RAM that is divided into blocks based on the applicable chipping rate and the round-trip distance between serviceable mobile terminals and a base station. If the memory is divided into three blocks, for example, during each pass by a virtual or physical rake finger, two blocks in the memory are in a Read mode while the third block is in a Write mode These blocks are further divided into segments based on a performance area trade-off. In this context, each block of RAM is in effect a stand-alone single port RAM. In another exemplary embodiment, the memory can contain enough storage locations to store data from multiple antennas and store enough data from each antenna to allow the alignment of the signals received from the multipaths. Each block of data may contain data from a plurality of CDMA encoded channels each with possible multipaths. By reprocessing the data multiple times the memory and the rake fingers are effectively used many times per chip (or block of chips) thus significantly reducing the amount of hardware required for a given number of (logical) fingers, and combiners. To avoid having to use a multiport read/write RAM, a time-sharing method may be used. One (or more) cycle can be dedicated to write operations and many cycles can be dedicated to read operations. BRIEF DESCRIPTION OF THE DRAWINGS Figure 1 illustrates a prior art communication device. Figure 2 illustrates an exemplary communication device in accordance with an embodiment of the invention. Figure 3 illustrates an exemplary decimation-inteφolation circuit in accordance with an embodiment of the invention. Figure 4 illustrates an exemplary decimation circuit in accordance with an embodiment of the invention. Figure 5 illustrates an exemplary inteφolation circuit in accordance with an embodiment of the invention. Figure 6 illustrates an exemplary despreading circuit in a base band processor in accordance with an embodiment of the invention. Figure 7 illustrates an exemplary memory in accordance with an embodiment of the invention. Figure 8 illustrates an exemplary despreading circuit coupled to a memory in accordance with an embodiment of the invention. Figure 9 illustrates another exemplary memory in accordance with an embodiment of the invention. Figure 10 illustrates another exemplary despreading circuit coupled to a memory in accordance with an embodiment of the invention. Figure 11 illustrates an exemplary process in accordance with an embodiment of the invention. Figure 12 illustrates an implementation of a single port memory that is functionally a multiport memory. Figure 13 illustrates how the memory in Figure 12 can access a contiguous series of addresses starting at any address. DETAILED DESCRIPTION Reference will now be made in detail to the various embodiments of the invention. In the following detailed description of the present invention, numerous specific details are set forth in order to provide a thorough understanding of the present invention. However, it will be apparent to one of ordinary skill in the art that the present invention may be practiced without these specific details. I i other instances, well-known methods, procedures, components, and circuits have not been described in detail so as not to unnecessarily obscure aspects of the present invention. Figure 2 illustrates an exemplary communication device 200 in accordance with an embodiment of the invention. The communication device 200 includes an antenna 102, a front-end processor 104, a decimation-inteφolation circuit 202, a base band processor 204, a microprocessor 108, and a bus 110 for interconnecting the above components. The decimation-inteφolation circuit 202 receives data from the front-end processor 104, stores the data (the amount of data stored will depend on details of the embodiment chosen), and converts the sampling rate into a rate more advantageous for processing by the other processing units, such as the baseband processor 204. The baseband processor 204 includes mechanisms that allow multiple despreaders (e.g., rake fingers) to substantially simultaneously retrieve data from a memory in the decimation-inteφolation circuit 202. Exemplary embodiments of such mechanisms are described in Figures 8 and 10 below. Figure 3 illustrates an exemplary decimation-inteφolation circuit 202 in accordance with an embodiment of the invention. The decimation-inteφolation circuit 202 includes a decimation circuit 302, a memory 304, and an inteφolation circuit 306. In an exemplary embodiment, the memory 304 is a single-port RAM. In another exemplary embodiment, the memory 304 is a FIFO RAM, a set of registers, or other suitable memory devices. Exemplary embodiments of the memory 304 are described in Figures 7, 9, 12 and 13, below. Data received from the front-end processor 104 is decimated by the decimation circuit 302 by a factor of D to reduce the sampling rate (R) to a minimum sampling rate (e.g., R/D) more efficient for storage in the memory 304. Data retrieved from the memory 304 is inteφolated by the inteφolation circuit 306 by a factor of JR to increase its speed to a rate of R*IR/D before being outputted into the base band processor 204. In an exemplary embodiment, the decimation factor (D) and the inteφolation factor (JR) are independently determined depending on the surrounding infrastructure. For example, the decimation factor may be configured to decimate the sampling rate by a factor of four while the inteφolation factor may be configured to increase the sampling rate by a factor of two. When the decimation factor and the inteφolation factor are the same, the decimation and the inteφolation factors cancel each other exactly and the final output data rate is the same as the received data rate (i.e., sampling rate). hi one embodiment, the decimation factor and the inteφolation factor are hard- coded into the decimation-inteφolation circuit 202. In another embodiment, the decimation factor and the inteφolation factor are dynamically configurable to adapt to multiple communication protocols by making the filter coefficients programmable. Figure 4 illustrates an exemplary decimation circuit 302 in accordance with an embodiment of the invention. The decimation circuit 302 includes a low pass filter 402 and a down-sampler circuit 404. The low pass filter 402 and the down-sampler circuit 404 are designed using well known principles for designing decimation circuits. For example, assume a signal x(n) with a spectrum X(ω) is to be downsampled by an integer factor D. The input sequence x(n) is first passed through the lowpass filter 402 that is characterized by the impulse response h(n) and a frequency response H D (ω). hi an exemplary embodiment, H D (ω) is equal to 1 when |ω|≤ π/D and is equal to 0 otherwise. The lowpass filter 402 eliminates the spectrum of X(ω) in the range of π/D < ω < π. The output of the lowpass filter 402 is a sequence v(n): v(n) = ∑h(k)x(n-k) k=0 The sequence v(n) is down sampled in the down-sampler circuit 404 by a factor D to produce y(m): y(m) = v(mD) = oo I (k)x(mD-k) k=0 A person skilled in the art will know specific gate structures necessary to construct a decimation circuit to serve the puφoses of the decimation circuit 302 based on the above described principles. An increase in the sampling rate by an integer factor of IR can be accomplished by inteφolating IR-1 new samples between successive values of the signal. As generally known in the art, the inteφolation process can be accomplished in a variety of ways. In an exemplary embodiment, a process that preserves the spectral shape of the signal sequence x(n) is used. Figure 5 illustrates an exemplary inteφolation circuit 306 in accordance with an embodiment of the invention. The inteφolation circuit 306 includes an up-sampler circuit 502 coupled to a lowpass filter 504. In an exemplary embodiment, v(m) denotes a sequence that is obtained from x(n) by adding IR-1 zeros between successive values of x(n). hi an exemplary embodiment, the sampling rate of v(m) is equal to the rate of y(m) above. Further, v(m) is equal to x(m/LR), when m = 0, ±LR, ±2IR, .... and equal to zero otherwise. A z-transform is performed on v(m) in the up-sampler circuit 502. Subsequent to the z- transform, the sampling rate increase obtained by the addition of IR-1 zero samples between successive values of x(n) results in a signal whose spectrum V(ω y ) is an 1R- fold periodic repetition of the input signal spectrum X(ω x ). Because only the frequency components of x(n) in the range of 0 ≤ ω y ≤ π/LR are unique, the images of X(ω) above ω y = π/IR are rejected by passing the sequence v(m) through the lowpass filter 504 that has a frequency response of H τ (ω y ). hi an exemplary embodiment, H,(ω y ) is equal to C when 0 ≤ |ω y | < π/LR and equal to 0 otherwise. C is a scale factor that is required to properly normalize the output sequence y(m). In an exemplary embodiment, C is selected so that the output y(m) is equal to x(m/ R) for m = 0, ±LR, ±2IR, etc. In an exemplary embodiment, the output sequence y(m) may be expressed as a convolution of the sequence v(n) (see Figure 4) with the unit sample response h(n) of the lowpass filter 504. A person skilled in the art will know specific gate structures necessary to construct an inteφolation circuit to serve the puφoses of the inteφolation circuit 306 based on the above described principles. Additional information regarding decimation and inteφolation can be found at pages 549-555 of A. V. Oppenheim et al., Signals & Systems (Prentice Hall, 2d edition 1997). This reference is hereby incoφorated for all puφoses. Figure 6 illustrates an exemplary despreading circuit 600 in the base band processor 204 of the invention. The despreading circuit 600 includes a selector circuit 602 coupled to multiple rake fingers 604a-604c. The number of rake fingers shown is for illustration puφoses only. In a despreading circuit, the number of rake fingers may be more or less depending on system design requirements. The selector circuit 602 selectively couples the multiple rake fingers 604 at substantially the same time to the memory 304 to allow the rake fingers 604 to retrieve data stored in the memory 304. In an exemplary embodiment, rather than using a different rake finger 604 to process the data of each different multipath, circuits in the individual rake fingers 604 can be reused. Each reuse of the hardware of a finger to process a different multipath or a path of a different data channel is referred to as using a virtual finger. Figure 7 illustrates an exemplary memory 304 in accordance with an embodiment of the invention. The memory 304 includes multiple registers 702a-702p. Each register 702 is divided into two halves: one half for storing In-Phase (I) data and another half for storing Quadrature (Q) data. Decimated samples from the decimation circuit 302 are sequentially written into the multiple registers 702 in a circular manner, one sample being stored in each register. Thus, when all the registers 702 have been initially written into, the next sample is written into the least recently written register and so forth. For example, if there are 16 registers and the samples are stored in numerical order starting with sample 0, then sample 16 is stored by overwriting sample 0, sample 17 is stored by overwriting sample 1, etc. as shown in Figure 7. This way, the memory 304 contains the most recent samples from the decimation circuit 302. The number of registers shown in memory 304 of Figure 7 is arbitrary and can be increased or decreased depending on system requirements. In an exemplary embodiment, the memory 304 stores only samples from one antenna. When multiple antennas are providing samples (e.g., at a base station), multiple memories 304 should be implemented, one per antenna. Figure 8 illustrates an exemplary despreading circuit 600 coupled to the memory 304 as shown in Figure 7 above. For ease of explanation, the despreading circuit 600 includes only one rake finger 802. The rake finger 802 is configured to access the memory 304 substantially simultaneously with other rake fingers or virtual fingers (not shown) via the selector circuit 602. The rake finger 802 includes rake finger circuits known in the art for performing rake finger functions. The selector circuit 602 includes multiple multiplexers 804a-804c for providing three types of JJI- Phase data (i.e., Early, On-Time, and Late) and multiple multiplexers 806a-806c for providing three types of Quadrature data (i.e., Early, On-Time, and Late) to the rake finger 802, respectively. The selector circuit 602 also includes a Late sample select line 808, an On-Time sample select line 810, and an Early sample select line 812 for selecting various types of I or Q data. Advantageously, each multiplexer has an input from each register of memory 304 and control signals are applied to the multiplexer to allow selection of any of these inputs as the output from the multiplexer. As shown, memory 304 stores 16 samples and each select line 808-812 has four bits for identifying the sample to be selected by the multiplexer to which it is connected. In an exemplary embodiment, the sample select lines 808-812 are controlled by an external controller (not shown). When more than one physical rake finger is implemented in the base band processor 204, the rake finger 802 and the select circuit 602 are replicated for each physical rake finger. Each physical rake finger requires its own set of select lines 808- 812. In an exemplary embodiment, rather than using a different rake finger 802 to process the data of each different multipath, circuits in the rake finger 802 can be reused. In one embodiment, if three virtual fingers are implemented in a single physical rake finger 802, the select lines 808-812 will cycle through three sets of sample select operations, one per virtual finger, so that each virtual finger is given access to all the samples retrieved from the memory 304. In an exemplary embodiment, the memory 304 is accessible substantially simultaneously by multiple physical or virtual rake fingers 802. For example, if samples are stored in the memory 304 at an 8x over sampling rate, during access by the rake finger 802, sixteen sets of I data (or words) are received by the I multiplexers 804 and sixteen sets of Q data (or words) are received by the Q multiplexers 806. That is, for the I multiplexers 804, the same sixteen sets of I data are available to the Early, On-Time, and Late multiplexers. Similarly, for the Q multiplexers 806, the same sixteen sets of Q data are available to the Early, On-Time, and Late multiplexers. Figure 9 illustrates another exemplary memory 304 in accordance with an embodiment of the invention. The memory 304 is divided into three blocks 902a- 902c. Each block 902 can store up to 256 words or chips worth of samples. Generally, two types of data per sample (fri-Phase and Quadrature) are stored per chip. In an exemplary embodiment, at a given pass, one block is in a Write mode and the remaining blocks are in a Read mode. Thus, as shown in Figure 9, in Pass 1 data is being written to block 902c and read from blocks 902a and 902b and in Pass 2 data is being written to block 902a and read from blocks 902b and 902c. The blocks in Read mode allow multiple rake fingers with different offsets to read out data sequentially. The size of the blocks 902 is determined based on several factors, including: the chipping rate of the processing system and the maximum (serviceable) round-trip distance between a mobile terminal and a base station. The chipping rate is dependent on applicable standards (e.g., IS-95, 3GPP, etc.). Generally, the higher the chipping rate, the bigger the memory block 902 should be. Further, the longer the maximum round-trip distance, the bigger the memory block 902 should be. For example, if the maximum round-trip distance is about 10 kilometers, each block in the memory 304 should be able to store about 256 chips. A person skilled in the art knows how to calculate the memory block size based on the maximum round-trip distance and the chipping rate. Figure 10 illustrates another exemplary despreading circuit 600 coupled to the memory 304 as shown in Figure 9 above. In Figure 10, each memory block 902 in the memory 304 is further divided into segments 1002a-1002h. In an exemplary embodiment, the size of the segments 1002 is dependent on area minimization. For example, for a memory block of 256 word (or chip) size, a 16 or 32 word segment 1002 is a good performance trade-off. A person skilled in the art knows how to calculate a performance area trade-off and determine an optimum size for the segments 1002 based on the memory block size. Each memory segment 1002 is coupled to a separate bussing element 1004a- 1004h via multiple signal lines 1006a- 1006h. In general, each signal line 1006 carries an I and Q data pair onto the bussing element 1004. Each bussing element 1004 sequentially reads out data from its respective segment 1002. Multiple despreading circuits 600a-600b are connected to the memory segments 1002 via a bus 1010. Each despreading circuit 600 includes a selector circuit 602 and a rake finger 1008. The selector circuit 602 includes a block multiplexer 1012, three sample multiplxers 1014a-1014c, and a cache 1016. The rake finger 1008 includes hardware known in the art. The block multiplexer 1012 selects one of the bussing elements 1004 to read data from one of the segments 1002. The sample multiplexers 1014 selects the Early, On-time, and Late samples among the I and Q data pairs read from a segment 1002, which was selected by the block multiplexer 1012. The I and Q data pairs selected by the sample multiplexers 1014 are stored into the cache 1016 to be processed by the rake finger 1008. In an exemplary embodiment, the cache 1016 is a FIFO cache that begins storing samples when the first chip to be processed is presented to the FIFO. In an exemplary embodiment, each selector circuit 602 is coupled to an independent inteφolation circuit (not shown) to inteφolate samples retrieved from the memory 304. Figure 11 illustrates an exemplary process in accordance with an embodiment of the invention. At step 1102, data is received at an antenna and sampled at a sampling rate R. The sampling rate of the received data is decimated by a factor of D by the decimation circuit 302 (step 1104). Next, data is stored into the memory 304 at the decimated rate (step 1106). Stored data is read from the memory 304 as needed and provided to the inteφolation circuit 306 (step 1108). In an exemplary embodiment, the memory 304 is read and controlled by a micro-processor (e.g., microprocessor 108) or a dedicated controller. The memory can be accessed by multiple physical and virtual rake fingers substantially simultaneously via a selector circuit. In one embodiment, the memory is a circular buffer comprised of multiple registers. In another embodiment, the memory is a single-port RAM. The inteφolation circuit 306 inteφolates the rate of the data read from the memory 304 (step 1110) then outputs the data at an inteφolated rate (e.g., a predetermined multiple of the chipping rate (i.e., Ix, 2x, 4x, 8x, etc.)) into the next processing module, such as the base band processor 204 (step 1112). In an exemplary embodiment, the decimation and inteφolation factors are hard-coded into the decimation-inteφolation circuit 202. In another exemplary embodiment, the decimation and inteφolation factors are dynamically re- programmable to accommodate various cornmunication protocols depending on the surrounding infrastructure either by utilizing a scan chain (which is a technique known to one skilled in the art) or by accessing registers controlling the operation by the microprocessor, or by other means. Data is stored into the memory 304 at a minimum speed to reduce the required memory size. Later, data retrieved from the memory 304 is inteφolated to an increased rate. As a result, memory space requirements at the memory 304 are small while efficiency during the next processing stages (such as at the base band processor 204) is not compromised. Figure 12 illustrates the use of a wide RAM structure that behaves in a manner analogous to a multi-port RAM. The RAM structure comprises a register 1201, a memory 1202, a register 1203 and a multiplexer 1204. The output of multiplexer 1204 is provided to one rake finger. Register 1201 is segmented into n segments, each being capable of being written independently and each storing one sample. If n is a power of 2 the operation is simpler. Successive samples are stored into successive segments in register 1201. When n samples have been assembled they are written into one memory location in memory 1202. Each finger has its own register 1203 and multiplexer 1204. Figure 13 illustrates more detail of memory 1202 and depicts how data can be read from memory 1202 on any address boundary. For puφoses of illustration, it is assumed that 8 samples are stored at each memory address 1301, that the samples are numbered consecutively as shown and that it is desired to read out 8 consecutive samples starting at any sample address (and not necessarily at a memory address). The memory is addressed by address circuitry that comprises a plurality of multiplexers 1302-0 through 1302-7, address lines A_LOW and A_LOW+l and select lines 0 through 7. Each multiplexer selects an address from either A_LOW or A_LOW+l depending on the value on the select line connected to the multiplexer. The number of multiplexers (and select lines) is equal to the number of samples stored at each address 1301 in memory. The memory address on address line A_LOW is formed by dividing the sample address by the number of samples stored at each memory address. The memory address on address line A_LOW+l is one more than the memory address on address line A_LOW. The remainder that results from the division of the sample address by the number of samples stored controls the value on each select line. If the remainder is equal to or less than the number of the select line, the signal supplied by the select line to the multiplexer is such that the memory address on line A_LOW is selected. If the remainder is greater than the number of the select line, the signal supplied by the select line to this multiplexer is such that the memory address on line A_LOW+l is selected. Thus, if it is desired to read out 8 samples starting with same address 5, Select5, Select6, and Select7 will steer the multiplexer 1302 to supply AJ OW and the remaining Selects will steer their multiplexers 1302 to supply AJLOW+1. The multiplexer 1204 will supply data in the order 5, 6, 7, 8, 9, 10, 11, 12. In the apparatus of Figures 12 and 13 cycles are dedicated to a particular operation. A request-arbitration scheme will accomplish the same goals. When a memory such as shown in Figures 9, 10 or 12 or similar the possibilities exist of finger reuse and multiple antenna support. Memory 1202, if n samples wide, can support up to n-1 fingers if operated at chipping rate. If the memory 1202 is operated at some higher frequency than the chipping rate, a multiple, plus possibly some overhead for context switching, then data from the same block of memory can be fed more than once to the same finger hardware thus providing finger reuse. A block of data, for example 256 chips, can be processed by a finger, then a second block (probably with different starting point) can be processed by the same finger hardware. As each finger is not processing a continuous data stream, cycles may be required for context switching, possibly including the initialization of inteφolation filters. If the memory 1202 is operated at some higher frequency than the chipping rate, a multiple, plus possibly some overhead for context switching, or if less than n-1 fingers are supplied, and the size of the memory is increased by a multiple A (new memory size = previous memory size x A), then data from A antennas can be supplied to the rake fingers. The memory block, with its addressable access is inherently a multiplexor. The foregoing examples illustrate certain exemplary embodiments of the invention from which other embodiments, variations, and modifications will be apparent to those skilled in the art. The invention should therefore not be limited to the particular embodiments discussed above, but rather is defined by the claims.

Claims: LN THE CLAIMS: 1. An apparatus for processing data in a spread spectrum system, comprising: a decimation circuit having an associated decimation factor; a memory coupled to said decimation circuit; and an inteφolation circuit coupled to said memory, said inteφolation circuit having an associated inteφolation factor; wherein said decimation circuit decimates a data rate of received data by said decimation factor to a decimated rate and stores said received data into said memory at said decimated rate; and wherein said inteφolation circuit inteφolates said decimated rate by said inteφolation factor to an inteφolated rate and retrieves said received data from said memory at said inteφolated rate. 2. The apparatus of claim 1, further comprising: a communication processor coupled to said inteφolation circuit for receiving data from said memory at said inteφolated rate. 3. The apparatus of claim 1, further comprising: a dedicated controller for controlling data retrieval from said memory. 4. The apparatus of claim 1, further comprising: a micro-processor for controlling data retrieval from said memory. 5. The apparatus of claim 1 , wherein said decimation factor is programmable by configuring said decimation circuit. 6. The apparatus of claim 1 , wherein said decimation factor is hard-coded into said decimation circuit. 7. The apparatus of claim 1, wherein said inteφolation factor is programmable by configuring said inteφolation circuit. 8. The apparatus of claim 1, wherein said inteφolation factor is hard-coded into said inteφolation circuit. 9. The apparatus of claim 1, wherein said memory is a single port RAM. 10. The apparatus of claim 9, wherein said memory is divided into memory blocks such that during processing a first subset of memory blocks is in a Read mode and a second subset of memory blocks is in a Write mode. 11. The apparatus of claim 10, further comprising a plurality of despreaders. 12. The apparatus of claim 11, wherein each of said plurality of despreaders includes: a selector circuit; and a rake finger. 13. The apparatus of claim 12, wherein each of said memory blocks are divided into segments such that data stored in each segment is read out sequentially onto a bussing element accessible by multiple rake fingers via selector circuits in said plurality of despreaders. 14. The apparatus of claim 12, wherein said selector circuit includes a block multiplexer, a plurality of sample multiplexers, and a cache coupled to each rake finger. 15. The apparatus of claim 1 , wherein said memory is a circular buffer. 16. The apparatus of claim 15, wherein said circular buffer includes multiple registers. 17. The apparatus of claim 16, further comprising a plurality of despreaders. 18. The apparatus of claim 17, wherein each of said plurality of despreaders includes: a selector circuit; and a rake finger. 19. The apparatus of claim 18, wherein data stored in said multiple registers are accessible by multiple rake fingers via selector circuits in said plurality of despreaders. 20. The apparatus of claim 18, wherein said selector circuit includes a first set of multiplexers for selecting in-phase data, a second set of multiplexers for selecting quadrature data, and multiple sample select lines coupled to each rake finger. 21. A method for processing data in a spread spectrum system, comprising the steps of: receiving data at a sampling rate; decimating said sampling rate by a decimation factor to obtain a decimated rate; storing said data into a memory at said decimated rate; inteφolating said decimated rate to obtain an inteφolated rate; and outputting said data from said memory at said inteφolated rate to a communication processor. 22. The method of claim 21 , further comprising the step of: retrieving data from said memory in accordance with instructions from a micro-processor. 23. The method of claim 21 , further comprising the step of: retrieving data from said memory in accordance with instructions from a dedicated controller. 24. An apparatus for processing data, comprising: a plurality of rake fingers; a memory for storing data at the input to said plurality of rake fingers; and a selector circuit positioned between said memory and each of said plurality of rake fingers; wherein said plurality of rake fingers can access said memory substantially simultaneously via a respective selector circuit. 25. The apparatus of claim 24, wherein said memory is a circular buffer including a plurality of registers. 26. The apparatus of claim 24, wherein said selector circuit includes a first plurality of multiplexers for selecting in-phase data from said memory, a second plurality of multiplexers for selecting quadratrue data from said memory, and a set of select lines for controlling data being selected by said first plurality of multiplexers and said second plurality of multiplexers. 27. The apparatus of claim 24, wherein said memory is a single-port RAM. 28. The apparatus of claim 27, wherein said memory is divided into memory blocks such that, during each processing cycle, a first subset of said memory blocks is in a Read mode and a second subset of said memory blocks is in a Write mode. 29. The apparatus of claim 28, wherein each of said memory blocks is divided into segments, such that data stored in each segment is read out sequentially onto a bussing element. 30. The apparatus of claim 29, wherein said selector circuit includes a block multiplexer, a plurality of sample multiplexers, and a cache coupled to each rake finger. 31. The apparatus of claim 30, wherein said block multiplexer selects a bussing element to receive data from a segment. 32. The apparatus of claim 31 , wherein said sample multiplexers selects data received from said block multiplexer and stores said data into said cache. 33. An apparatus for processing data in spread spectrum systems, comprising: a memory coupled to a set of despreaders via a bus; each of said set of despreaders including: a block multiplexer coupled to said bus; a set of sample multiplexers coupled to said block multiplexer; a cache coupled to said sample multiplexers; and a rake finger coupled to said cache; and wherein said set of despreaders can access samples stored in said memory substantially simultaneously via said bus. 34. The apparatus of claim 33, wherein said memory is divided into blocks such that during a processing cycle by a despreader, a first subset of said blocks is in a Read mode and a second subset of said blocks is in a Write mode. 35. The apparatus of claim 34, wherein said blocks are divided into segments such that samples stored in each of said segments are read out sequentially onto a bussing element coupled to said bus. 36. The apparatus of claim 35, wherein said block multiplexer in each of said despreaders selects samples from one bussing element. 37. The apparatus of claim 36, wherein said sample multiplexers in each of said despreaders select appropriate Early, On-Time, and Late samples among samples received from said block multiplexer to be stored into said cache.

Inventors: HOLMES DAVID M, MEDLOCK JOEL D, RIEKEN KEITH, HOLMES, DAVID, M., MEDLOCK, JOEL, D., RIEKEN, KEITH
Applicants: MORPHICS TECH INC, MORPHICS TECHNOLOGY, INC.
Application year: 2001
Main classification: H04L27
IPC codes: H04L27