SEMICONDUCTOR DEVICE FOR LOW VOLTAGE PROTECTION WITH LOW CAPACITANCE

Abstract: A semiconductor thyristor device (110) that incorporates buried regions (112) spaced around an emitter region (114). By spacing the buried regions (112) around the emitter region (114), current carriers emitted from the buried regions are distributed over a large area of the emitter region (114), thereby providing a high current capability during initial turn on of the device. In order to achieve low breakover voltage devices, the buried regions (112) are offset laterally with respect to the respective emitter regions (114). The low voltage thyristor device exhibits a low capacitance for operating with high speed, low voltage signals. The device capacitance is reduced by utilizing a plurality of buried regions (112), each formed having a relatively small area junction with the base region (118).

Description: SEMICONDUCTOR DEVICE FOR LOW NOLTAGE PROTECTION WITH LOW CAPACITANCE TECHNICAL FIELD OF THE INVENTION The present invention relates in general to thyristors and other four-layer devices, and more particularly to the fabrication of thyristor devices having low breakover voltages. RELATED APPLICATIONS This application is a continuation-in-part of pending U.S. application Serial No. 09/504,224, filed February 15, 2000, entitled "Very Low Noltage Actuated Thyristor With Centrally-Located Offset Buried Region" , which is a continuation-in-part patent application of U.S. Pat. No. 6,084,253, issued July 4, 2000, the entire subject matter of the application and patent of which is incorporated herein by reference. BACKGROUND OF THE INVENTION Thyristors, SIDACtor® overvoltage devices and other four-layer devices are commonly used to provide overvoltage protection to circuits requiring the same. The SIDACtor® overvoltage devices are two-terminal thyristors that have bidirectional current carrying capability. Such devices are obtainable from Teccor Electronics at many different breakover voltage values. When used in conjunction with telephone lines, for example, of the type in which 220-volt ringing signals are carried, a 250-volt breakover voltage SIDACtor® overvoltage device can be used to allow normal operation of the telephone line, but operate at 250 volts, or greater, in response to lightning strikes or power line crosses to thereby safely clamp the line to a very low voltage. This type of a device provides high surge current capabilities for protecting equipment from damage due to the extraneous voltages that may be coupled to the telephone line. Five-pin telephone line protection modules utilizing these high voltage devices have typically been commercially available. Many telephone circuits and equipment operate on a 48-volt supply voltage. To that end, SIDACtor® overvoltage devices that operate at a nominal 64 volts are often used to protect such type of circuits. A nominally operating 30 volt SIDACtor® device can be advantageously used to protect many 24 volt circuits, such as fire alarm and other systems, that are susceptible to extraneous voltages. It can be appreciated that the lines that generally require protection from damage due to extraneous voltages are often in environments where energy from lightning strikes can be induced into the lines, where high voltage AC circuits are in close proximity thereto, and for a host of other reasons. While low-voltage digital lines, such as those driven by 5-volt TTL drivers are extensively employed in computerized and other equipment, such lines have not yet found a large application in outside installations. However, in view of the fact that computer networks and communications are increasing at a substantial rate, such low-voltage lines are being used in environments where overvoltage protection is required. Such overvoltage protection need not be due solely to lightning and power line crosses, but can be due to other standard voltages that are commonly found in indoor equipment. It is well known in the thyristor and SIDACtor® overvoltage device field that the impurity level of a semiconductor wafer can be adjusted to thereby achieve a desired breakover voltage. It is commonly known that lightly-doped silicon substrates are characterized by high breakover voltages. As the doping or impurity level of the substrate is increased, the breakover voltage is reduced. It is also well known that the impurity level of a semiconductor material is inversely proportional to the resistivity thereof. It has also been found that the use of buried regions in the semiconductor substrate facilitates the operational characteristics of a SIDACtor® overvoltage device. See, for example, U.S. Pat. No. 5,479,031 by Webb. Referring to Fig. 1, if the SIDACtor® device is constructed so as to have an N-type emitter 18, a P-type base 16 and an N-type substrate 12 or mid-region, a heavily doped P-type buried region 14 can be implanted between the base region 16 and the silicon substrate 12 to thereby reduce the breakover voltage. Important advantages are achieved when the buried region 14 is directly beneath the emitter region 18, with the base region 16 material therebetween. Without significantly changing the impurity levels of the emitter 18, base 16 and substrate 12, the breakover voltage can be changed by simply changing the impurity level of the buried region 14. Moreover, in achieving breakover voltages from 250 volts down to 64 volts, the buried region need only be more heavily doped. In like manner, to achieve 30-volt breakover voltage devices, the buried region is required to be even more heavily doped. As the impurity level of the buried region 14 increases, the junctions 20-26 formed between the buried region 14 and the base region 16 are displaced upwardly toward the emitter region 18. Indeed, as the doping level of the buried region 14 increases, the distance between the buried region-base junction 20 and the base-emitter junction becomes smaller and smaller. The reason for this is that the junction 20 is formed at a location in the semiconductor material where the donor states of one impurity are cancelled by the acceptor states of the opposite impurity. Stated another way, the junction of two semiconductor materials exists where the impurity concentration of one region is equal to the impurity concentration of the other region. The formation of a low breakover voltage SIDACtor® overvoltage device is not an elementary task. It has been found that to fabricate nominal 10-volt breakover voltage SIDACtor® devices, the impurity level of the buried region must be so high that the buried region can often be effectively short circuited to the emitter region. In any event, even after fine tuning the processes so as to prevent short circuiting between the buried region and the emitter, the yield of workable devices is low, and thus such devices become costly. Another problem attendant with upward migration of the junction of the buried region is that the base region under the emitter becomes thinner. The distance in the base region between the emitter junction and the buried region junction defines, in part, a holding current (I h ) parameter. The holding current is that current required to maintain an on-state of the device. A thinner base region adversely affects the ability to control a desired holding current. Various other attempts have been made to make low breakover voltage thyristors. One endeavor involves a semiconductor design in which the breakover voltage occurs at the surface of the device. In other words, the concentration of the impurities at the surface of the device is controlled to achieve a low breakdown voltage. Standard twisted pair telephone lines are protected by various circuits from hazardous voltages and currents that may be imposed on the lines. It is a standard practice to provide primary protection by the use of five-pin protection modules in the central offices and other high density conductor applications. Such modules have a standard pin configuration so that the modules of many different suppliers can be inserted into the same type of socket. The basic protection to telephone lines includes primary protection modules and secondary protection modules. The primary protection module provides overvoltage protection against lightning strikes and power line crosses to the telephone lines. Such primary protectors may include gas discharge tubes and other semiconductor devices that can withstand high voltages. Secondary protection circuits often include semiconductor devices, resistors, positive temperature coefficient devices and other components to provide lower voltage protection to the customer side equipment. A family of overvoltage protection SIDACtor® devices providing the secondary protection is available from Teccor Electronics, Irving, Texas. The primary protection module is effective to limit the hazardous line voltages to approximately 300 volts. The secondary protection circuits, for example in line cards, provide additional protection to the telephone lines at levels below 300 volts. While numerous five-pin primary protection modules are commercially available to provide primary protection, there is a limited selection of five-pin secondary protection modules providing secondary protection. Recent changes in regulatory requirements suggest the use of DC isolation as well as overvoltage protection in secondary protection circuits of certain types of equipment. This imposes additional constraints not currently satisfied by currently available devices and circuits. From the foregoing, it can be seen that a need exists for a method and technique to fabricate low breakover voltage thyristor devices. Another need exists for a technique to fabricate low voltage thyristor devices where the breakover voltage is independent of the holding current. Yet another need exists for a thyristor device which can be reliably made with high yields, thereby reducing the cost of the devices. Another need exists for a five-pin communication line protection module for use with low voltage communication lines. A further need exists for a low voltage thyristor device that exhibits a low voltage overshoot in response to fast rise time transients, and that exhibits a low device capacitance. SUMMARY OF THE INVENTION In accordance with the principles and concepts of the invention, there is disclosed a technique for fabricating low-voltage thyristor devices, which technique overcomes the disadvantages and shortcomings of the prior art. In accordance with an edge-fired embodiment of the invention, the buried region is laterally offset from the emitter region. The upward movement of the buried region junction as a function of the impurity level does not thereby interfere or otherwise become too close to the emitter junction. In addition, because of the lateral displacement of the buried region from the emitter, the base region underlying the emitter does not vary in thickness as a function of the location of the buried region junction. This essentially makes the breakover voltage independent of the holding current value of the device. In accordance with another feature of the invention, a deep base is provided to thereby make the mid-region of the substrate thinner. The mid-region of the substrate functions in the four-layer device as a base of one of the regenerative-connected transistors of the thyristor device. With a thinner transistor base, the gain of the device is higher, thereby allowing the thyristor device to remain in an on state with a lower holding current. In another embodiment, a four-layer thyristor is fabricated utilizing a pair of spaced- apart emitters with the buried region disposed therebetween. In yet another embodiment, a low voltage thyristor device is formed as a center-fired device in which the buried region is formed offset from the emitter, but generally centered in the chip. This arrangement not only allows an increased device current to flow, but also facilitates assembly of the packaged device. By placing the buried region in the center of the semiconductor chip and utilizing two symmetrically oriented metal contacts, the chip self centers itself to a lead frame when reflow soldered thereto. In yet another embodiment, a five-pin communication line protection module uses the low-voltage thyristor to provide low voltage line protection to other circuits, such as data systems. According to another embodiment, high impurity concentration buried regions are used to not only achieve a low breakdown voltage, but the buried regions are constructed utilizing cross-sectionally small areas to reduce device capacitance. The device can thus be used for protecting lines carrying high speed digital signals. An additional feature of this embodiment is that the buried regions are formed at various locations with respect to the emitter region, such that full conduction over the entire emitter area is achieved faster, thereby reducing the voltage overshoot of the device. In accordance with a described embodiment, the emitter of the device is fabricated with a peripheral edge or perimeter having indentions or cutouts formed therein. Formed below such cutouts are corresponding buried regions. The location of the buried regions with respect to the emitter allow carriers emitted from the buried regions to flow to essentially the entire, if not all, of the emitter area, thereby providing full turn on of the emitter. This allows high current densities to be accommodated during turn on of the device without causing "bottle-neck" locations of the current. BRIEF DESCRIPTION OF THE DRAWINGS Further features and advantages will become apparent from the following description of the drawings, in which like referenced characteristics generally refer to the same parts, elements or functions throughout the views, and in which: Fig. 1 is a cross-sectional view of a low breakover voltage SIDACtor® device constructed in accordance with the prior art; Fig. 2 is a cross-sectional view of a low voltage SIDACtor® device constructed in accordance with one embodiment of the invention; Figs. 3 and 4 are respective cross-sectional and top views of yet another embodiment of a low voltage SIDACtor® device having a deep base region to effectively make the mid- region of the substrate thinner, thereby reducing the holding current characteristics of the device; Figs. 5 and 6 are respective cross-sectional views of a low voltage SIDACtor® device utilizing a buried region disposed between emitter regions; Fig. 7 is a cross-sectional view of a low voltage SIDACtor® device utilizing a base region that has a portion thereof that is lightly doped for improved turn-on performance, and a more heavily doped portion of the base region to control the breakover voltage; Figs. 8 and 9a are respective top and sectional views of yet another embodiment of the invention, in which the device is considered a "center- fired" device in that the buried region is centrally located in the semiconductor chip; Fig. 9b is a cross-sectional view of another embodiment of the invention with semiconductor areas formed so that the entire device functions as a low voltage Zener diode; Fig. 10 is a side view of a thyristor device soldered to lead frame members; Figs. 11 and 12 are respective circuit diagrams of low voltage communication line protection circuits; Figs. 13 and 14 are five-pin protection modules embodying the respective low voltage protection circuits shown in Figs. 11 and 12; Fig. 15 is an isometric view of a five-pin protection module utilizing low-voltage protection circuits; Fig. 16 is a top view of another embodiment of the invention, showing the features of the individual buried regions, as well as the location of the buried regions with respect to the emitter; Fig. 17 is a cross-sectional view of the device of Fig. 16, taken along line 17-17 thereof; Fig. 18 is a cross-sectional view of the device of Fig. 16, taken along line 18-18 thereof; Fig. 19 is a top view of the device of Fig. 16 subsequent to a metalization of the chip; Fig. 20 is a top layout view of the device of Figs. 16-19, showing the pattern of carriers emanating from each buried region; Fig. 21 is a top layout view of another embodiment similar to that of Fig. 16, but employing a larger emitter and thus more buried regions for providing carriers thereto; Fig.22 is a cross-sectional view of the device of Fig.21 , taken along line 22-22 thereof; Fig. 23 is a cross-sectional view of the device of Fig.21 , taken along line 23-23 thereof; Fig 24 is a top layout view of the device of Fig. 21, showing the pattern of carriers emanating from each buried region; Fig. 25 is a top view of another embodiment of the invention where the buried regions are located under coπesponding openings in the emitter region; Fig. 26 is a sectional view of the device of Fig. 25, taken along line 26-26 thereof; and Fig. 27 is a top view similar to that of Fig. 25, but with broken lines showing the emanation of carriers from the buried regions. DETAILED DESCRIPTION OF THE INVENTION Fig. 2 illustrates the principles and concepts of one embodiment of the invention. A single four-layer unidirectional device 30 is illustrated. Two such devices (a top surface and bottom surface device) can be formed in the semiconductor substrate to provide bidirectional current flow capabilities. The device 30 is formed in the top surface of a starting silicon substrate 32 of the P-type. Region 32 defines both the mid-region of the four-layer thyristor, and a base of a PNP transistor. An N-type base region 34 for one device is formed in the top surface of the wafer, and a second N-type base region 36 for a second device (not shown) is formed in the bottom surface of the wafer. A heavily doped buried region 38 is formed in the substrate 32, preferably by standard semiconductor diffusion techniques and before either base region 34 or 36 is formed. The buried region 38 is formed by depositing boron ions for about three days, resulting in a surface concentration of about 10 19 atoms per cm 3 , and at a depth of 80 microns. This impurity concentration at the top of the buried region 38 is effective to provide a breakover voltage in the range of 8-12 volts. The wafer undergoes the diffusion process at a temperature of about 1275 ° centigrade for about three days to activate the ions. After activation, a buried region junction 40 is formed in the base region 34. A P-type emitter region 42 is formed in the base region 34, but offset laterally from the buried region 38. A metal emitter contact 44 is formed in electrical contact with both the emitter region 42 and the base region 34. On the semiconductor wafer overlying the buried region 38, there is formed a dielectric layer 46 of glass, oxide or other electrically insulating material. As can be seen from Fig. 2, the buried region 38 does not underlie the emitter region 42. Rather, the buried region 38 is offset so that the junction 40 with the base region 34 does not come into close vertical proximity to the emitter-base junction, even when the buried region junction 40 becomes increasingly shallow as the buried region 38 becomes more heavily doped. Any upward movement of the buried region junction 40 is due to the application of high processing temperatures (1275 °C) to activate the P-type ions. Indeed, even when the buried region junction 40 becomes extremely shallow due to the heavy doping of the buried region 38, there is no possibility that it would short circuit with the emitter-base junction. The arrangement of the semiconductor regions of Fig. 2 defines an edge fired thyristor device, in that the buried region 38 is located near the edge of the chip. The buried region associated with the companion unidirectional device (not shown) in Fig. 2 would be located near the bottom left of the chip, much like the positions of the buried regions shown in the prior art device of Fig. 1. The holding current I h of the device 30 is a function of the distance 52 between the emitter-base junction 48 and the base and mid-region junction 50. As can be appreciated, the distance 52 is independent of the location of the buried region junction 40. The breakover voltage (N B0 ) of the device 30 is primarily a function of the distance 54 between the buried region junction 40 and the upper surface 56 of the semiconductor wafer. In addition, and as noted above, the impurity concentration of the buried regions 38 also determines the breakover voltage characteristics of the device 30. In accordance with an important feature of the invention, the breakover voltage of the device 30 is determined, in part, by the distance 54, which is independent of the holding current characteristics. The holding current characteristics are determined primarily by the distance 52. Not only can a high impurity concentration buried region 38 be used without the attendant problem of short circuiting with the emitter-base junction 48, but the device made according to the invention renders the breakover voltage characteristics independent of the holding current characteristics. As noted above, an insulating dielectric 46 overlies the buried region 38. The reason for this is that when the device is subjected to an overvoltage, initial breakdown occurs as current flows from the bottom base region 36 to the emitter 42, via the buried region 38. With multiple buried regions, multiple current paths are initially formed, thereby providing a high surge current capability. To force the initial current during breakdown to pass through the emitter region 48 and through the emitter contact 44, the base region above the buried region 38 is covered with the insulator 46. Otherwise, if the metal contact 44 extended over the buried region 38, current would bypass the emitter region 42 and pass directly to the emitter contact 44. Once the current through the device 30 reaches the switching cuπent (I s ), the on-state of the device is maintained and current flow need not pass through the buried region 38. It can be appreciated from the foregoing that the lateral distance between the emitter region 42 and the buried region 38 should be small to increase the turn-on speed of the device, as well as to reduce the initial overshoot during turn on. In the fabrication of a bidirectional SIDACtor® device, two devices (one shown in Fig. 2) can be used, one formed in the top surface of the substrate, and the other device formed in the bottom surface. Fig. 3 illustrates another embodiment 60 of the invention having double base regions formed on the top surface of the substrate, and double base regions formed on the bottom surface of the substrate. In the example shown, the substrate or mid-region 62 is employed, and one or more buried regions 64 are formed therein in the manner noted above with reference to Fig. 2. A first thick base region 65 is formed in the top surface of the substrate, and doped with an N-type impurity to achieve an 80 ohm per square resistivity. A second thinner base region 66 is formed in the first base region 65. The base region thicknesses are not shown to scale in the drawings. The second base region 66 is formed at a higher N-type impurity level at the surface of about 3 x 10 19 atoms per cubic centimeter. The heavily doped N-type base region 66 and the heavily doped P-type buried region 64 allow a junction to be formed therebetween. In the top base 66 there is formed a P-type emitter 68. Again, the buried region 64 is laterally offset with respect to the emitter region 68, thereby making the breakover voltage characteristics independent of the holding current characteristics. In addition, by utilizing a double base region in the top and bottom surfaces of the substrate 62, the mid-region 62 is thereby effectively narrowed. The P-type mid-region 62 corresponds to the base of an NPN transistor which forms one-half of the thyristor device. By making the mid-region 62 thinner, and thus the base region of the NPN transistor thinner, the gain of the device is improved and the initial breakover characteristic is improved to reduce the overshoot. Overshoot is considered to be a positive current/voltage slope of the device once breakover (V B o) begins to occur. Fig. 4 is a top view of the device 60, taken along line 4-4 of Fig. 3. Figs. 5 and 6 illustrate another embodiment of a thyristor device 70 in which the emitter configuration is modified. Here, a pair of spaced-apart P-type emitters 72 and 74 are formed in the N-type base region 76. Indeed, each emitter region 72 and 74 is spaced on each side of the buried region 78. As noted in the next step of the process shown in Fig. 6, additional P-type impurities are diffused into the top surface of the base region to form a bridge 80 that thereby short circuits the emitters 72 and 74 together. The bridge 80 should be sufficiently thin to maintain a separation with the junction 86 of the buried region 78. The bottom surface of the junction 82 of each emitter region 72 and 74 can thus be formed as close to the junction 84 as necessary, to improve the gain and turn-on characteristics of the device. Again, the distance between the junction 82 and the junction 84 is independent of the location of the junction 86 formed at the top of the buried region 78. With reference now to Fig. 7 there is illustrated another embodiment 90 of the invention. Here, there is shown a P-type mid-region 92, an N-type base region 94 and a P-type emitter 96 formed therein. The first base region 94 is highly doped and underlies the emitter region 96. Disposed laterally at the side of the emitter 96 is a more heavily doped second base region 98. A buried region 100 forms a junction 102 in the heavily doped second region 98. Since the more heavily doped base region 98 does not underlie the emitter 96, the turn on characteristics of the device are not substantially affected. With this arrangement, the breakover voltage can be reduced further, thus providing overvoltage protection to low voltage communication lines. Another embodiment of the invention is shown in Figs. 8 and 9a. This thyristor device 110 also includes a buried region 112 that is laterally offset with respect to an emitter region 114. Rather than placing the buried region 112 near an edge of the chip, the buried region 112 is located generally in the central portion of the chip. As will be described in more detail below, the center-fired design allows the metal contact areas to be larger, thereby providing a larger current-carrying capability. Two symmetrically-oriented surface contacts are located on each side of the wafer, thereby allowing easier centering of the device within a lead frame during assembly of the packaged device. The thyristor device 110 shown in Figs. 8 and 9 includes a first base region 116 and a second base region 118, providing the same advantages noted above in connection with the embodiment of Fig. 3. A metal cathode contact 120, such as solder, is formed in electrical contact with the emitter region 114. The solder contact 120 is bounded by silicon oxide 122. Formed at the same time as the central buried region 112 is another buried region 124 formed at the edge of the chip. The buried region 124 functions to terminate the junction of the two base regions 116 and 118. An insulating material, such as glass 126, formed in a trench serves to prevent the edge-located buried region 124 from initiating conduction of carriers toward the emitter 114. Rather, electron conduction is initiated through the central buried region 112. One unidirectional device of the thyristor involves the central buried region 112, the emitter 114, the upper two base regions 116 and 118, the mid-region 127, as well as the lower two base regions 128 and 130. A lower contact 132 functions as the anode to the first unidirectional device of the thyristor 110. Assuming the thyristor 110 is biased so that the cathode contact 120 is positive with respect to the anode contact 132, electron current flows from the anode 132 through the bottom base regions 128 and 130, through the mid-region 127 and into the central buried region 112. Initial electron current does not flow directly through the upper base regions 116 and 118, but first through the central buried region 112. From the top junction 134 of the buried region 112, electrons flow into the upper N2 base region 118 and into the emitter region 114, whereupon thyristor conduction begins. Current flows from the emitter region 114 and out of the cathode contact 120. Once conduction is initiated by way of the central buried region 134, current thereafter flows directly from the mid-region 127 through the upper Nl and N2 base regions 116 and 118 into the emitter 114. The glass-filled trench insulation regions 126 and 136 function to prevent initiation of current flow, except through the central buried region junction 134 to the emitter 114. The glass-filled trench 136 prevents initial electron current from flowing through the central buried region 112 into a metal anode contact 137 formed in the top surface. This is because the breakdown voltage of the top junction 134 of the central buried region 112 is lower than the breakdown voltage at the side junction indicated by reference numeral 138. The breakdown voltage of the side junction 138 of the buried region 112 under the glass 136 is greater than that of the top junction 134. The reason for the difference in breakdown voltages is that the impurity concentration of the buried region 112 at the side junction 138 is less than that at the top junction 134. As noted above, the heavily doped central buried region 112 is formed by a long-term diffusion process which naturally results in an impurity concentration gradient between the upper and lower portions of the central buried region 112. According to the diffusion process, the impurity concentration of the upper part of the central buried region 112 is greater than the impurity concentration located therebelow. With a lower impurity concentration at the side junction 138, the breakdown voltage is naturally higher than that at the top junction 134. As a result, the top junction 134 of the central buried region 112 reaches breakdown first, whereupon initial electron current flow is through the top of the central buried region 112 to the emitter 114. The same principle operates in conjunction with the edge buried region 124 and the glass-filled trench 126. It is noted that the depth of the glass-filled trench boundaries 126 and 136 are formed at the same depth. Indeed, the insulating glass 126 and 136 are formed about the periphery of the device, and formed at the same time in a single peripheral trench. In the event it is desired that a higher switching current be achieved in the device, the depth of the glass 136 can be less, thereby raising the upper edge of the side junction 138, thus reducing the breakdown voltage at that location. With a lower breakdown voltage, some current tends to pass from the central buried region 112 into the left N2 region 148 and out the metal anode contact 136. As will be described more fully below, the top metal contacts 120 and 137 are short circuited together by a lead frame, and the lower contacts 132 and 140 are short circuited together by another lead frame. The other bidirectional device of the thyristor 110 includes a bottom emitter 142 in contact with the bottom cathode contact 140. The two lower base regions 144 and 146 are associated electrically with the emitter 142. The upper two base regions 148 and 150 are associated with the anode contact 137. Current flow in the second bidirectional device is from the anode contact 137 to the cathode contact 140. As with the other unidirectional device described above, initial electron current flows from the anode contact 137 through the two upper base regions 148 and 150, through the mid-region 127 and into the lower, central buried region 152. Electron current flows out of the bottom-most junction 154 of the buried region 152, through the heavily doped lower base region 144 and into the emitter 142. Once conduction is initiated, current does not pass through the buried region 152, but rather through the lower base regions 144 and 146 into the emitter 142 and out of the cathode contact 140. The various insulator glass and silicon oxide regions shown formed in the bottom of the semiconductor chip 110 provide the same function as those described above in connection with the top of the semiconductor chip 110. As can be appreciated, if the overvoltage to which the thyristor device 110 is subjected is an AC signal, then the unidirectional devices will conduct alternately based on the positive and negative cycles of the AC signal. Fig. 9b illustrates an embodiment of the invention that functions in a manner similar to a low voltage Zener diode. The semiconductor regions formed in the right-most part of the semiconductor chip 156 function in the same manner noted above to produce an overvoltage protection device when a negative voltage is applied to the bottom contact 158 and a more positive voltage is applied to the top contact 120. When the voltage applied across the device is reversed, the semiconductor regions on the left function as a diode bridged across the other unidirectional device. The N-type regions 148 and 150 together with the P-type regions 127 and 142 define the diode. In this embodiment, only a single bottom contact 158 is necessary. Fig. 10 is a side view of the thyristor device 110 as assembled in connection with a first lead frame 160 and a metal preform 162. As can be seen, the top cathode contact 120 and top anode contact 137 are soldered to the top preform 162, and thus short circuited together. In like manner, the bottom anode contact 132 and bottom cathode contact 140 are soldered to the bottom lead frame 160 and are thereby short circuited together. The top preform 162 is soldered to an up-turned end 164 of a second lead frame 166. The joint 168 between the second lead frame 166 and the preform 162 is reflow soldered at the same time as the solder contacts of the thyristor device 110 are reflow soldered to the respective preform 162 and first lead frame 160. Due to the surface tension inherent in the liquified solder, the edge 170 of the first lead frame 160 tends to become self-aligned with the edge of the bottom anode contact 132. Similarly, the edge 172 of the preform 162 tends to become self aligned with the edge of the soldered anode contact 137. This self centering of the thyristor device with respect to the first lead frame 160 and the preform 162 helps prevent misalignment of the device with respect to the lead frames and thus increases assembly yield of the resulting semiconductor structure. Were it not for the symmetry between the edges of the various solder contacts of the thyristor device 110 and the lead frames, registration of the components would be more difficult. In the event that the thyristor device 110 becomes misaligned with the lead frames, the assembly will not correctly fit into the mold for final packaging and encapsulation of the device. As noted above, another advantage of the symmetry between the top solder contacts 120 and 137 and the bottom solder contacts 132 and 140 is that larger area contacts can be formed to thereby facilitate increased current capability of the device. This symmetry can be achieved because the buried regions 112 and 152 are formed in vertical alignment. In practice, it has been found that the effective conduction area of the metallized emitter of Fig. 2 was about 883 square mils (.57 mm 2 ), whereas the corresponding area of both top contacts of the embodiment shown in Fig. 8 is about 1111 square mils (.72 mm 2 ). Fig. 11 illustrates a five-pin, low voltage communication line protection circuit for providing twenty volt protection to circuits (not shown) connected to the customer tip and ring conductors. The protection circuit is useful in providing low voltage protection to telephone signaling lines that are typically employed to report alarms and the status of banks or series of printed circuit cards. These signaling lines constitute private communication channels used to communicate between a central office and remotely located terminals or cabinets. Such lines are not powered by the standard 48 volt supply but rather are low voltage operating circuits. The tip conductor 179 is connected in series with a positive temperature coefficient (PTC) element 180 to the customer tip conductor 185. The PTC element 180 produces about 4-10 ohms resistance up to about 300 ma flowing therethrough. Should the tip line current increase, the resistance of PTC element 180 increases to provide overcurrent protection to the customer side circuits. When the tip line current is reduced, the resistance of the PTC element 180 returns to its original value. Bridged between the customer tip conductor 185 and ground 181 is a twenty-volt Zener diode 182. A small value capacitor (470 pF) 184 functions to filter, condition and stabilize the signal line. The outside ring conductor 183 is similarly situated, in that it is connected in series with a PTC element 186 to the customer ring conductor 187. A second Zener diode 188 provides twenty volt protection to the customer ring equipment. The Zener diodes 182 and 188 can be of the type shown above in conjunction with Fig. 9b. A capacitor 190 provides the same function to the ring conductor 183 as capacitor 184 provides to the tip conductor 179. While the low voltage protection circuit of Fig. 11 uses Zener diodes 182, 188, the four- layer devices described above in connection with Figs. l-9a can be used with equal effectiveness in place of the Zener diodes 182, 188. Zener diodes can be fabricated by maintaining only a single unidirectional device as described above in connection with Fig. 9b, and replacing the other unidirectional device with an effective PN junction. Those skilled in the art can readily appreciate the manner in which the various semiconductor regions can be modified by masking and diffusion techniques to provide a diode in parallel with the other unidirectional thyristor device. When packaging or otherwise implementing the circuit of Fig. 11 in a module, it is not necessary to use the entire circuit. Rather, when it is desired to protect only the customer tip conductor 185 from hazardous voltages appearing on the outside tip conductor 179, then the capacitor 190 and Zener diode 188 can be omitted. Only a three-pin module may be necessary in this instance to provide protection to one line or conductor. The converse is also true if hazardous voltage protection is necessary to only the customer ring conductor 187. Fig. 12 illustrates yet another embodiment of a low voltage protection circuit that uses a transformer 196. Such an aπangement can be employed for connection to standard TI or El digital transmission, or many other types of lines. In this embodiment, the tip conductor 191 is connected through a PTC element 192 through the primary 194 of the transformer 196. The other terminal of the transformer primary 194 is coupled through another PTC element 198 to the ring conductor 193. The transformer secondary 200 has one terminal connected to a customer tip conductor 195, and another terminal connected to a customer ring conductor 197. Connected between the customer tip conductor 195 and ground 201 is a back-to-back Zener diode arrangement 202 providing bidirectional protection in the neighborhood of about 6.8 volts to the customer tip conductor 195. A second bidirectional Zener diode arrangement 204 is coupled between the customer ring conductor 197 and ground 201 to provide bidirectional protection to the customer ring conductor 197. The transformer 196 is effective to block any DC voltage that may exist on the tip and ring conductors from entering the customer circuits. Some TI and El transmission lines can be powered by 130 volt or 48 volt supplies. The transformer prevents such DC voltages from being coupled to the lower operating voltage equipment of the customer. However, any AC voice, pulse or other similar types of signals are able to be transfeπed from the transformer primary 194 to the transformer secondary 200 and coupled to the customer circuits. The electrical isolation and other parameters provided by the transformer 196 may be of the type satisfying the recognized standards of UL 497A, CSA C22.2 NO. 950-95 and UL 1950 (3rd edition). The line conditioning and protection circuit of Fig. 12 is well adapted for those situations where the outside line conditions are not well identified or known, and where the protection of the inside or customer circuits is important. For example, where there may be numerous lines incoming from various destinations and different applications where the electrical properties, operating conditions and characteristics of the lines may not be known, the protection module or circuit of Fig. 12 can be used to isolate all external DC voltages from the customer circuits but still allow the AC information to be transferred. The interfacing of the many outside lines to the customer circuits can be achieved by utilizing a bank of five-pin sockets, where each socket has pins connected to the outside lines, the customer lines, and a ground connection. A module with a protection circuit such as described above can be plugged into the socket to provide the type of protection desired. If different lines require different types of electrical protection, then a module with a different circuit therein can be used. The modules can be color coded or otherwise visually distinguished to identify the different circuits therein. The modularized line conditioning and protection circuits can facilitate compliance with new or modified standards and specifications. In those situations where there already exists the primary and secondary protection circuits, the circuits shown in Figs. 11 and 12, and yet other circuits, can be incorporated with the existing protection circuits to establish compliance with the new standards or specifications. The integration of the new protection circuits can be facilitated by incorporating the same into modular form adapted for plugging into standardized sockets. The adaptation of the new circuits can even be achieved in these instances by incorporating the standard secondary protection circuits with the new conditioning and protection circuits into the same module, and plug such module into the socket that previously held the standard secondary protection module. This feature allows the incorporation of the new protection scheme without having to wire, rewire or make connections to the existing communication lines. The low voltage protection circuits of Figs. 11 and 12 can be incorporated into five-pin modules for easy use and plugability into customer communication interface equipment. With reference to Fig. 13, there is illustrated the telephone line protection circuit of Fig. 11 assembled in a five-pin module structure 206. The five pins 210 of the module are aπanged in a standard configuration well known in the art. The pins 210 are fixed within a plastic molded base 212. A first printed circuit board 214 has conductive paths soldered to the respective pins 210. A second printed circuit board 216 is fabricated to hold the electrical components shown in Fig. 11. Various wire conductors 218 and 220 serve to connect the various conductors of the second printed circuit board 216 to the first printed circuit board 214 so that the circuit configuration operates electrically as shown in Fig. 11. The conductors 220 also support the second printed circuit board 216 vertically with respect to the first printed circuit board 214. A plastic molded cover 222 (Fig. 15) is molded to snap fit to the base 212 by way of the small openings 224 formed in the cover. The openings 224 are snap fit around corresponding bosses 216 extending from sides of the module base 212. As noted above, the Zener diodes 182 and 188 can be used as the low voltage thyristor devices described above, and packaged in diode-shaped packages. Other package configurations, including the well-known TO style packages can be easily soldered to the printed circuit boards. With reference now to Fig. 14, there is illustrated a five-pin module 228 incorporating the components of the low voltage protection circuit of Fig. 12. Again, there is a standard configuration five-pin molded base 230 to which the five pins 232 are fixed. A first printed circuit board 234 has conductive paths soldered to the respective pins 232. A second upright printed circuit board 236 is wired to the first printed circuit board 234 by a number of wire conductors 238 and 239. One terminal of each PTC element 192 and 198 is connected to the respective conductive paths of the second printed circuit board 236, while the other respective terminals 238 and 240 are connected directly to the first printed circuit board 234. The various printed circuit board conductive paths and components shown in Fig. 14 are arranged to provide the functions of the electrical circuit shown in Fig. 12. Fig. 15 illustrates a completed low voltage five-pin protection module 206 that may house the components of either circuit shown in Fig. 13 or Fig. 14. A finger-grip handle 242 molded as part of the cover 222 permits easy installation or replacement of the low voltage protection circuits in the customer equipment racks. The standard five-pin module configuration can be used to provide low voltage protection to various types of customer equipment that operates with low voltage signals carried on the lines. Indeed, the low voltage protection circuits and devices described above need not provide protection to voltages to which standard twisted pair telephone lines may be exposed, but rather to other digital and low- level signal lines that may never be exposed to lightning or power line voltages. Rather, many types of digital and analog communication lines may require protection from inside power sources, such as DC or AC power supplies which may be inadvertently coupled to the customer equipment, or where other circuits fail and allow damaging voltages between 5-50 volts to be coupled to the customer equipment. The various devices, circuits, modules and combinations thereof can be adapted for use with these and many other applications. Figs. 16-20 illustrate yet another embodiment of the invention, where plural buried regions are selectively located at different sites in the overvoltage protection device 250, thereby allowing current carriers to quickly migrate to substantially the entire surface area of the emitter region 258 during initial turn on of the device 250. In the fabrication of the device 250 according to this embodiment, a silicon wafer uniformly doped with a P-type impurity is used as the starting semiconductor material. The starting silicon material forms a mid-region 252 of the device 250. Those skilled in the art may prefer to use a starting silicon wafer of an N-type, in which event the polarities of the various semiconductor regions described below would be reversed. The P-type silicon mid-region 252 is then masked to define circular openings for forming the various buried regions deep into the mid-region 252. In accordance with an important feature of the invention, the number of buried regions formed within the silicon material corresponds generally to the area of the emitter region 258. For larger emitter regions in terms of lateral area, either larger area buried regions or more buried regions may be used. While the use of many buried regions may increase the turn-on speed of the device, the overall capacitance of the device is also increased. A compromise must generally be made between the turn-on speed of the device, and the capacitance of the device. In one embodiment, the device 250 is formed on a square semiconductor chip having an area of about 75.0 mils square. The area of the emitter region 258 is about half the area of the device 250. In any event, each current-carrying device on the chip using this configuration is fabricated with four buried regions. Two buried regions 254 and 256 are formed somewhat adjacent to each other, close to the outside edge of the chip, adjacent to and laterally offset with respect to the emitter region 258. Importantly, the breakdown junction of each buried region is formed laterally offset from the emitter region. The breakdown junction of the buried regions means the portion of the junction that generally defines the breakover voltage of the overvoltage protection device. Two other buried regions 260 and 262 are formed further apart, adjacent the opposite edge of the emitter region 258. The buried regions 260 and 262 are formed adjacent two respective corners of the emitter region 258. As will be described more thoroughly below, this pattern or location of buried regions enhances the turn-on speed of the device 250 and thus lowers the voltage overshoot. This is critically important in the fabrication of overvoltage protection devices having low breakover voltage characteristics, namely fifty volts and below. As noted above, such type of overvoltage protection devices are useful in protecting digital or other low-voltage telecommunication lines or conductors. The openings in the mask for forming the buried regions 254, 256 and 260, 262 are circular in shape and located in the positions shown in Fig. 16. In the processing of a wafer having many chip areas thereon, the various masking and deposition steps are carried out on both sides of the wafer at the same time. The mask opening forming each buried region has a radius of about 2.0 mils. A P-type impurity is deposited on the wafer, in the openings, with a concentration sufficient to achieve the desired breakdown voltage suitable for protecting lines on which digital signals are transmitted. In order to achieve a breakover voltage of about ten volts, a P-type impurity, such as boron, is deposited to substantially a saturation level. Next, the boron atoms are driven deeply into the wafer from both sides thereof to a depth of about 3.0-3.5 mils, as shown in Figs. 17 and 18. The deep buried regions are formed by subjecting the wafer to a temperature of about 1275° C for about 72 hours. It can be appreciated that both sides of the wafer are processed at the same time to form buried regions in the shape and location as noted in Figs. 16-18. The device 250 has formed therein one overvoltage protection device (with four buried regions) for conducting current in one direction, and a counterpart overvoltage protection device (with four other buried regions) for conducting cuπent in the opposite direction. The processing steps and the geometry of each overvoltage protection are substantially identical. A bidirectional overvoltage protection device 250 for protecting circuits from overvoltages of either polarity is thus provided. With reference now to Figs. 17 and 18, the wafer is masked on both sides thereof to form openings in which a well or tub of N-type impurities are diffused. N-type impurities such as phosphorus can be used. The n-wells 264 and 266 are formed directly underlying surface locations at which the respective emitter regions will be formed. The respective top and bottom wells 264 and 266 function to reduce the effective thickness of the mid-region 252 and increase the switching speed of the device 250. With a thinner mid-region, the forward turn-on voltage of the device is reduced. Subsequent to the formation of the n-wells 264 and 266, the wafer is prepared to form a pair of first base regions 268 and 272 in respective sides of the wafer. The wafer is not masked when forming the base regions. The first base region 268 is lightly doped to form an 80-ohm N-type layer, and is formed so as to be contiguous with the n-well 264. The first base region 268 is formed by depositing an N-type impurity (such as phosphorus) into the surface and diffusing the impurity atoms to a depth substantially as shown in Figs. 17 and 18. Because of the inherent characteristics of the high temperature diffusion process, an impurity gradient is formed in the first base region 268. The gradient of the N-type impurities in the first base region 268, together with the heavily doped P-type buried regions, define a frustoconical- shaped junction 270 around a portion of each buried region. A similar first base region 272 is formed in the opposite side of the wafer contiguous with the respective n-well 266. The lightly- doped first base region 272 also forms a frustoconical-shaped junction 274 with respect to the buried regions 257 associated with the counterpart overvoltage protection device. In the next step of the process in fabricating the device 250, a second, or upper, base region 276 is formed over the first base region 268. A second base region 278 is also formed on the opposite side of the wafer, over the other corresponding first base region 272. In particular, the second base regions 276 and 278 are formed with a high concentration of N-type impurities. The second base regions 276 and 278 have sufficiently high concentrations such that the upper sections of the respective buried regions 256 and 257 become inverted, thereby resulting in a layer of N-type impurities in the second base regions 276 and 278. While only two buried regions are illustrated for each overvoltage protection device in Figs. 17 and 18, all four buried regions of each device undergo the same processing. As a result of such processing, a breakdown junction 280 is formed at the interface between the top lateral surface of the buried region 256 and the second heavily doped base region 276. A similar breakdown junction 282 is formed with respect to the buried region 257 and the second base region 278 formed in the opposite side of the device 250. These junctions of the buried regions define the breakover voltage of the overvoltage protection devices. Importantly, these breakdown junctions are formed laterally offset from respective portions of the emitter region. It is generally inconsequential if other portions of the buried regions forming respective high breakdown voltage junctions with the lightly doped base regions are formed under the emitter regions. The heavily doped second base regions 276 and 278 effectively "bury" the respective buried regions 256 and 274, as well as the other buried regions (not shown) formed in the top and bottom surfaces of the wafer. Respective emitter regions 258 and 286 for each overvoltage protection device are next formed in the opposing sides of the device 250. As shown in Fig. 17, the top emitter region 258 is formed laterally with respect to the buried region 256. In like manner, the bottom emitter region 286 is formed laterally with respect to the corresponding buried region 257. Each buried region is similarly offset with respect to the associated emitter regions. The offset nature of the breakdown junctions of the buried regions, and the respective emitter regions provide the same advantages as noted above in connection with the other embodiments of the invention. Importantly, as illustrated in Fig. 16, the emitter region 258 is formed around at least a portion of each circular-shaped buried region. With this arrangement, no portion of the emitter region 258 overlies any of the coπesponding breakdown junctions of buried regions 254, 256, 260 or 262. As noted above, the buried regions and the emitter region of the counterpart overvoltage protection device are similarly constructed. In the subsequent processing stages of the device 250, a trench 290 is formed through the second base region 276 for electrically isolating the buried region 260 from the adjacent portion of the second base region 276. The shape of the trench 290 is a partial circular shape, concentric with the frustoconical-shaped buried region, such as shown in Fig. 16. A similar trench 292 is formed through the second base region 276 for providing electrical isolation from the respective buried region 262. The trenches 290 and 292 are then filled with a standard leadaluminoborosilicate glass insulating material. The function of the glass-filled trenches 290 and 292 is for forcing the conduction of carriers from the buried regions 260 and 262 to the emitter 258, rather than to a metal contact (not shown) via the second base region 276. With this construction, the carriers generated by the buried region 260 favor a conduction path in the heavily-doped portion of the second base region 276 located adjacent to the emitter 258, rather than through the lightly-doped first base region 268 under the glass-filled trenches 290 and 292 to the second base region 276. Stated another way, were it not for the glass-filled trenches 290 and 292 located as shown, the carriers emitted from the buried regions 260 and 262 would be short circuited directly through the second base region 276 to the corresponding contact (not shown), rather than be carried to the emitter 258. The glass-filled trench 293 formed on the opposite side of the device 250 function to provide the same advantage for the other overvoltage protection device. The devices 250 formed on the semiconductor wafer are separated from each other by a grid network formed in the opposing sides of the semiconductor material. The grid network is filled with the glass insulating material, which provides a protective passivation layer to the side edges of the chip. Before being scribed and broken into the individual devices 250, the wafer is masked to define metal contact areas. The overvoltage protection devices of the invention have only a cathode contact on one side, and an anode contact on the other side. Once masked, a metal is deposited so as to form a contact on each side of the chip. The shape of the contacts on one side of the chip is shown in Fig. 19. Illustrated is a top contact 300 coated with a solder material. A corresponding bottom contact is formed in a mirror image of that shown in Fig. 19. The contacts 300 do not overlie the buried regions, and the peripheral grid network is shown providing electrical isolation between the center buried regions 260 and 262 and the second base region (not shown). A device formed according to the foregoing provides an overvoltage protection device characterized by a breakover voltage (V B0 ) of aboutlO volts and a device capacitance of about 60 pf. Fig 20. shows in diagrammatic form the patterns of carriers as emanating from each of the buried regions during initial turn on of one overvoltage protection device, it being realized that the same type of action occurs with the counterpart overvoltage protection device. The circular-shaped buried regions influence corresponding circular areas where carriers travel outwardly to the surface of the emitter 258. As can be seen, a major portion of the surface of the emitter 258 receives the carriers and is thus involved during the turn on of the overvoltage protection device. With a larger surface area of the emitter active during turn on, a higher surge current can be handled, and thus less voltage overshoot reaches the circuits to be protected. A more detailed discussion of the advantages of the plural buried regions spaced around the emitter region is set forth below in conjunction with Fig. 24. Figs. 21-24 illustrate yet another embodiment of the invention. Here, the device 310 is formed on a square semiconductor chip having an area of 105 mils square. The larger area device has a higher current carrying capability. With this increased semiconductor area (as compared to the Figs. 16-20 embodiment), an additional buried region is employed. Three buried regions 312, 314 and 316 are formed near the edge of the device 310, while two other buried regions 318 and 320 are formed near the center of the chip. Corresponding buried regions (not shown) are formed in mirror image locations on the bottom side of the chip. The buried regions are located at the apexes of respective imaginary triangles. In other words, buried regions 312, 314 and 318 are formed at the apexes of a first triangle; buried regions 318, 314 and 320 are formed at the apexes of a second triangle; and buried regions 314, 316 and 320 are located at the apexes of a third triangle. The breakdown junctions of the buried regions 312 and 316 are laterally offset from respective corners of the emitter region 332. As will be described below, this positioning of the buried regions with respect to the emitter region 332 facilitates a high-speed turn-on characteristic of the device 310. The various semiconductor regions of the device 310 are otherwise formed in a manner substantially the same as that described above in connection with Figs. 16-20. The mid-region of the device 310 is identified as reference numeral 322 in the cross-sectional view of Figs. 22 and 23. The buried regions of the device 310 are identified in Fig. 22 as reference numerals 314 for a top buried region and 324 for a bottom buried region. The device 310 of Fig. 23, when viewed along a cross-sectional view of line 23-23 of Fig. 21, illustrates a top buried region 320 and a bottom buried region 326. The first base region formed of a lightly doped N- type material is identified as reference numeral 328. The first base region formed in the bottom surface of the chip and associated with the counterpart overvoltage protection device is identified as reference numeral 330. The n-wells are identified as reference numerals 333 and 334. The more heavily doped second base regions are identified as reference numerals 326 and 328. The top P-type emitter is identified by reference numeral 332, and the bottom P-type emitter is identified by reference numeral 334. The electrically isolating glass-filled trenches are shown as reference characters 336 and 338. While the embodiments of the invention shown in Figs. 16-24 are illustrated with plural buried regions spaced around the peripheral edge of the respective emitter regions, additional buried regions could also be formed under central circular openings formed through the emitters. Also, while it has been found that circular-shaped buried regions of a specified diameter exhibit less device capacitance, as compared to cross-sectionally square-shaped buried regions of comparable widths, other shapes of the buried regions can be used. Indeed, the device can be fabricated using some buried regions of one cross-sectional shape, and other buried regions located at other areas (such as corners) can be fabricated with different cross- sectional shapes. While the utilization of square or rectangular-shaped buried regions may provide a better coverage of the emitter area with carriers, with fewer areas void of carriers during initial turn on, the use of such shape is believed to represent only a nominal increase in the tum-on speed of the device, with a corresponding disadvantage of higher device capacitance. As will be set forth more fully below, the pattern by which carriers are emitted from the buried regions is generally similar to the cross-sectional shape of the buried regions employed. As noted above, the function of the buried regions is to facilitate the initial turn on of a low breakover voltage device, while yet maintaining a low capacitance. In order to accomplish this, and to reduce or eliminate "bottle-necking" of the current during turn on, it is desirable to form the buried regions in a spaced-apart manner so that the carriers emitted therefrom are distributed over a wide area, thereby allowing a large area of the emitter to become quickly functional and effect a high current turn on of the device. As is well known, turn on of the overvoltage protection device is initiated by the current carriers flowing from the highly conductive buried regions to the emitter region, whereupon the emitter j unction b ecomes forward biased and thereafter device conduction occurs in the semiconductor regions outside of the buried regions. A high current turn on is achieved by forming the buried regions in a specified shape, and by positioning the buried regions around the emitter region. In other words, and as shown in Fig. 24, the buried regions 312-320 are formed in a cross-sectionally circular shape to provide corresponding circular patterns or areas in which the carriers migrate during turn on. The buried region 312 is formed adjacent and laterally offset from a comer portion of the emitter region 332. In like manner, the buried region 316 is formed adjacent another comer of the emitter region 332, and laterally offset therefrom. The buried region 314 is formed in a location intermediate the comer buried regions 312 and 316. The pattern by which carriers are emitted from the buried region 312 are shown by broken lines 340. As can be seen, the upper right comer portion of the emitter region 332 is provided with carriers for initiating turn off of the device. The middle buried region 314 produces a pattern in a semi- circular area identified by broken lines 342. Much like the pattern 340 generated by the comer- located buried region 312, the buried region 316 generates a quarter-circle pattern 344. The carrier patterns 340 and 342, and the carrier patterns 342 and 344, each overlap somewhat. The remaining two buried regions 318 and 320 generate corresponding semi-circular patterns 346 and 348 which also overlap somewhat. The peripheral areas of carrier patterns 346 and 348 are generally contiguous with the other carrier patterns 340, 342 and 344. As can be appreciated, the concentration of carriers decreases as a function of distance from the buried regions. While there may exist a few areas under the emitter region 332, such as area 350, that receive fewer carriers than the other emitter areas, substantially the entire area of the emitter region 332 is provided with carriers generated from the various buried regions. Full turn on of the device 310 can thus be initiated in a high speed manner. This substantially reduces bottle-necking of the cuπent and allows high transient currents to be accommodated by the device 310. Figs.25 and 26 depict yet another embodiment of the overvoltage protection device 360 constructed according to the principles and concepts of the invention. This device is preferably constructed on a chip having an area of 75 mils square. The device is formed with a P-type mid- region 362. Formed in both surfaces of the chip are a pair of P-type buried regions. The overvoltage protection device formed in the top surface of the chip is formed with two buried regions 364 and 366. The overvoltage protection device formed in the bottom surface of the chip also has two buried regions, one shown as reference numeral 368. Diffused in both the top and bottom surfaces of the chip are respective lightly-doped N-type first base regions 370 and 372, and corresponding n-wells 373 and 376. The heavily doped N-type second base regions 378 and 380 are formed in the respective lightly doped first base regions 370 and 372. A top surface emitter region 382 is formed in the second base region 378, and a bottom surface emitter 384 is formed in the coπesponding second base region 380. The various processing steps described above in connection with the embodiments of Figs. 16-24 can be used in forming the device of Figs. 25-27. In accordance with an important feature of the invention, the emitter region 382 has formed therein a pair of circular-shaped openings 386 and388. Formed adjacent to and laterally offset from the annular edges of the openings 386 and 388 are the respective breakdown junctions 390 and 392. Each buried region 366 and 368 is formed so as to be centered about an axis extending through the respective emitter region openings 386 and 388. Moreover, the buried regions 366 and 368 are formed with circular-shaped breakdown junctions 390 and 392. The buried regions are formed in the other surface of the chip in a similar manner with respect to openings in the emitter region 384. As noted above, the circular-shaped breakdown junctions of the buried regions permits the device to be constructed with a small capacitance. As can be seen from Fig. 25, each buried region 366 and 366 is formed generally centered in a half section of the emitter region 382. The carriers emitted from the breakdown junctions 390 and 392 thus allow a large surface area of the emitter region to become forward biased during initial turn on of the device 360. The emanation of the carriers from the breakdown junctions 390 and 392 is illustrated in Fig. 27. It can be seen that with this construction of the overvoltage protection device 360, the overall capacitance is small due to the use of only two buried regions per overvoltage protection device, and a high-speed turn on is achieved. While Figs. 25-27 illustrate an embodiment where the emitter region is formed with plural openings therein, those skilled in the art may find that the principles of the invention can be employed in constructing a similar device having an emitter with a centrally-located emitter opening. A buried region would be located under the central opening to provide carriers to a wide area of the emitter. As noted above, a low capacitance overvoltage protection device can be used for protecting lines carrying high speed signals. Because the buried regions necessarily involve the use of heavily doped regions to achieve a low breakdown voltage, such a structure also involves a larger capacitance. This is because with high concentration P-type and N-type junctions, the depletion region therebetween is small, thus presenting a high capacitance structure. The high concentration buried regions together with the high concentration second base regions form respective breakdown junctions characterized with a relatively high capacitance. In order to minimize the overall capacitance of the device, a small-area junction is formed in connection with each buried region, and plural buried regions are used. This structure not only reduces capacitance, but also provides a mechanism for distributing carriers to a large surface area of the emitter region during turn on. From the foregoing, numerous embodiments of the invention have been disclosed. In any of the embodiments, a breakover voltage of the device can be achieved sufficiently low for protecting TTL digital or other low voltage analog or digital lines, and the like. In addition, other equipment susceptible to extraneous high voltages can be protected with the described overvoltage protection devices. A common characteristic of each of the devices is that the buried region is laterally offset and adjacent to the emitter region so that the position of the breakdown junction of the buried region is independent of the distance between the emitter-base junction and the base-mid-region junction. Stated another way, with these designs, the breakover voltage is independent of the holding current of the device. By utilizing buried regions one over the other in bidirectional overvoltage protection devices, an economy of semiconductor area is realized. The utilization of metal contact area placement in conjunction with the lead frames allows self-registration between the elements during the reflow solder assembly process. While the preferred and other embodiments of the invention have been disclosed with reference to specific semiconductor techniques and methods of operation, it is to be understood that changes in detail may be made as a matter of design choices, without departing from the spirit and scope of the invention, as defined by the appended claims. For example, the devices may be fabricated utilizing impurities of the opposite type, other than those disclosed above.

Claims: WHAT IS CLAIMED IS: 1. A bidirectional overvoltage protection device, comprising: a first group of semiconductor regions formed in a semiconductor chip for carrying cuπent in response to a positive polarity voltage applied across the device; a second group of semiconductor regions formed in the semiconductor chip for carrying current in response to a negative polarity voltage applied across the device; and at least one buried region formed in association with each said first and second group of semiconductor regions, said buried regions being formed to define a breakover voltage for said overvoltage protection device, and formed centrally and laterally between two opposite sides of said semiconductor chip. 2. The bidirectional overvoltage protection device of Claim 1 , further including an emitter region associated with each said first and second group of semiconductor regions, and wherein said buried regions are formed laterally offset from the respective emitter regions. 3. The bidirectional overvoltage protection device of Claim 1 or 2, wherein said semiconductor chip is formed with an anode and cathode contact for said first group of semiconductor regions, and a different anode and cathode contact for said second group of semiconductor regions. 4. The bidirectional overvoltage protection device of Claim 3, wherein said semiconductor chip is formed having an anode and contact cathode on one surface thereof, and the different anode and contact cathode on an opposite side surface of the semiconductor chip. 5. The bidirectional overvoltage protection device of Claim 4, wherein the anode and cathode contacts on one side of said semiconductor chip define different contacts that are short circuited together by a lead frame. 6. The bidirectional overvoltage protection device of Claim 3 , further including in combination a top lead frame soldered to a top pair of contacts defining a first set of anode and cathode contacts, and a bottom lead frame soldered to a pair of contacts defining a second set of anode and cathode contacts. 7. The bidirectional overvoltage protection device of Claim 1 , 2 or 3 , wherein there is formed in one surface of said semiconductor chip at least one first base region and said emitter formed thereover, at least one second base region laterally spaced from said first base region, and a buried region formed between said first and second base regions. 8. The bidirectional overvoltage protection device of Claim 7, further including a PN junction between said buried region and said second base region, and including an electrically isolating material formed down into said junction to prevent cuπent flow between said buried region and said second base region. 9. The bidirectional overvoltage protection device of Claim 1 , wherein said second group of semiconductor regions are formed substantially identical to said first group of semiconductor regions, said first and second groups of semiconductor regions being formed in opposite faces of said semiconductor chip. 10. The bidirectional overvoltage protection device of Claim 7, further including a first metal contact electrically connected to said emitter, and a second metal contact electrically connected to said first base region, said first and second metal contacts being of substantially the same area when viewed from a top view. 11. The bidirectional overvoltage protection device of Claim 1 or 2, further including: a buried region formed in one surface of said semiconductor chip, and a second buried region formed in an opposing surface of said semiconductor chip, and wherein said first and second buried regions are formed vertically aligned with each other. 12. An overvoltage protection device, comprising: at least one base region formed in a semiconductor material; an emitter region formed in said base region such that a base-emitter junction is formed, said emitter region defined by a peripheral lateral boundary; a plurality of buried regions for promoting cuπent flow through said device during turn on, said buried regions formed with a breakdown junction for establishing a breakover voltage of said device; and at least a portion of said buried regions each being laterally offset from said emitter region. 13. The overvoltage protection device of Claim 12, wherein said buried regions include buried regions spaced around the peripheral lateral boundary of said emitter region so that carriers emitted from said buried regions are collected by substantially an entire surface of said emitter region. 14. The overvoltage protection device of Claim 12 or 13 , wherein said emitter region includes at least one opening therein, said opening bounded by a circular edge, and one said buried region is axially registered with said opening in said emitter region. 15. The overvoltage protection device of Claim 12 or 13, wherein said emitter region is formed with at least two comers, and further including at least two said buried regions formed laterally adjacent respective said comers of said emitter region. 16. The overvoltage protection device of Claim 12, 13 or 14, wherein said buried regions are formed using a mask having generally circular openings therein such that said buried regions have a generally circular profile. 17. The overvoltage protection device of Claim 12, 13, 14, 15 or 16, wherein said emitter region is formed with at least one indented area formed laterally in said peripheral boundary, and one said buried region is located so as to be laterally adjacent said indented area. 18. The overvoltage protection device of Claim 14, wherein said indented area has a shape substantially the same as a shape of a portion of said buried region located adjacent thereto. 19. The overvoltage protection device of Claim 12, further including an electrical isolation disposed between at least a portion of said base region and one said buried region to prevent cuπent flow between a portion of said base region and said buried region. 20. The overvoltage protection device of Claim 19, wherein said electrical isolation comprises a trench formed in said base region and filled with an electrical insulating material. 21. The overvoltage protection device of Claim 12, wherein said base region comprises a first base region having an impurity concentration of a specified level having an impurity concentration greater than that of said first base region. 22. The overvoltage protection device of Claim 21, wherein said first base region is formed having a well with a lateral shape that is generally the same as a lateral shape of said emitter region. 23. The overvoltage protection device of Claim 12, further including an electrical isolation isolating at least a portion of one said buried region from at least a portion of said base region. 24. An overvoltage protection device, comprising: at least one base region formed in a semiconductor material; an emitter region formed in said base region such that a base-emitter junction is formed, said emitter region having at least one opening therein bounded by a closed peripheral edge; at least one buried region forming a breakdown junction with said base region, said breakdown junction being axially registered within said opening in said emitter region, and said breakdown junction being laterally offset from said closed peripheral edge. 25. The overvoltage protection device of Claim 24, further including plural said openings, and further including a plurality of said buried regions, each buried region having a breakdown junction axially aligned and laterally offset with a respective said emitter opening.

Inventors: CASEY KELLY C, TURNER ELMER L JR, CASEY, KELLY, C., TURNER, ELMER, L., JR.
Applicants: CASEY KELLY C, TECCOR ELECTRONICS LP, TURNER ELMER L JR, CASEY, KELLY, C., TECCOR ELECTRONICS, LP, TURNER, ELMER, L., JR.
Application year: 2001
Main classification: H01L29
IPC codes: H01L27, H01L29