INSITU DIFFUSION BARRIER AND COPPER METALLIZATION FOR IMPROVING RELIABILITY OF SEMICONDUCTOR DEVICES

Abstract: A method for forming metallizations for semiconductor devices, in accordance with the present invention, includes forming trenches (107) in a dielectric layer (104), depositing a single layer diffusion barrier (116) in the trenches, and without an air-brake, depositing a seed layer (118) of metal on the surface of the diffusion barrier. The trenches are then filled with metal (120). The metal adheres to the seed layer, which adheres to the diffusion barrier to provide many improvements in electrical characteristics as well as to reduce failures in the semiconductor devices.

Description: INSITU DIFFUSION BARRIER AND COPPER METALLIZATION FOR IMPROVING RELIABILITY OF SEMICONDUCTOR DEVICES BACKGROUND 1. Technical Field This disclosure relates to semiconductor fabrication and more particularly, to a method for reducing failures while employing copper metallizations in semiconductor devices. 2. Description of the Related Art Semiconductor devices employ metal layers for connecting electronic devices . Metal layers for semiconductors are electrically isolated from other metal lines and layers by employing dielectric layers. In one example, a dielectric layer is deposited on a semiconductor device and then is patterned to form trenches or holes therein. The trenches or hole's are then filled with metal to provide interlevel connections or same level connections to various electrical components . Metal lines formed in such trenches typically include Aluminum. Aluminum although sufficient for many applications, other materials, such as copper, provide higher conductivity. Further, for logic applications, aluminum may be unsuitable especially in smaller groundrule designs. Higher conductivity is particularly useful in semiconductor devices with smaller line widths. As the line width decreases, resistance increases. Providing a material, like copper, which has a higher conductivity, may compensate for this. Copper also has several shortcomings, however. The dielectric layers employed for isolating copper often include oxygen, for example, silicon oxides. Electrical properties of copper degrade significantly when oxidized. Diffusion barriers employed between the dielectric layer and the copper, especially for smaller linewidths, reduce the cross-sectional area of the copper in the trench since these diffusion barrier layers occupy space. This increases the resistance of the metal line for a given linewidth. Therefore, a need exists for a method for employing copper metallizations without the drawbacks associated with copper. A further need exists for reducing barrier diffusion layer thicknesses to permit a greater amount of metal in metal lines . SUMMARY OF THE INVENTION A method for forming metallizations for semiconductor devices, in accordance with the present invention, includes forming trenches in a dielectric layer, depositing a single layer diffusion barrier in the trenches, and without an air-brake, depositing a seed layer of metal on the surface of the diffusion barrier. The trenches are then filled with metal. The metal adheres to the seed layer, which adheres to the diffusion barrier to provide many improvements to electrical characteristics as well as to reduce failures in the semiconductor devices. In the past, it was not possible to perform a chemical vapor barrier deposition without an air-brake before the metal (e.g., copper) deposition. The present invention avoids this air-brake and overcomes, among other things, problems due to adhesion problems. Another method for forming metallizations for semiconductor devices includes the steps of forming trenches in a dielectric, depositing a single layer diffusion barrier in the trenches, without an air-brake, depositing a seed layer of metal on the surface of the diffusion barrier, filling the trenches with metal, and planarizing a top surface down to the dielectric layer in a single polishing step to remove the metal and the diffusion barrier. Yet another method for forming copper metallizations for semiconductor devices includes the steps of forming trenches in a dielectric layer including an oxide, chemical vapor depositing a single layer diffusion barrier comprised of Ti or TiN in the trenches, without an air-brake after the chemical vapor depositing of the single layer diffusion barrier, chemical vapor depositing a seed layer of copper on the surface of the diffusion barrier, and filling the trenches with copper. In other methods, the step of without an air-brake, depositing a seed layer preferably includes the step of without an air-brake, chemical vapor depositing a seed layer of metal on the surface of the diffusion barrier. The steps of depositing a single layer diffusion barrier in the trenches and without an airbrake, depositing a seed layer of metal are performed in a same processing chamber. The seed layer and the metal preferably include copper. The trenches may include dual damascene trenches. The diffusion barrier may include one of Ti, TiN, WN, or TaN. The diffusion barrier is preferably less than or equal to 5 nm. The step of filling the trenches with metal may include the step of electroplating the metal to fill the trenches with the metal . The step of depositing a single layer diffusion barrier may include the step of chemical vapor depositing the diffusion barrier. The step of without an air-brake, depositing a seed layer may include the step of without an air-brake, ionized sputtering a seed layer of metal on the surface of the diffusion barrier. The step of filling the trenches with metal may include the step of sputtering to fill the trenches with the metal. These and other objects, features and advantages of the present invention will become apparent from the following detailed description of illustrative embodiments thereof, which is to be read in connection with the accompanying drawings. BRIEF DESCRIPTION OF DRAWINGS This disclosure will present in detail the following description of preferred embodiments with reference to the following figures wherein: FIG. 1 is a cross-sectional view of a dual damascene trench formed in a dielectric layer for applying the present invention; FIG. 2 is a cross-sectional view of a via, trench or single damascene structure formed in a dielectric layer for applying the present invention; FIG. 3 is a cross-sectional view of the dual damascene trench of FIG. 1, with a single layer diffusion barrier formed therein in accordance with the present invention; FIG. 4 is a cross-sectional view of the trench of FIG. 2, with a single layer diffusion barrier formed therein in accordance with the present invention; FIG. 5 is a cross-sectional view of the dual damascene trench of FIG. 3, with an in-situ seed layer of metal formed on the diffusion barrier in accordance with the present invention; FIG. 6 is a cross-sectional view of the trench of FIG. 4, with an in-situ seed layer of metal formed on the diffusion barrier in accordance with the present invention; FIG. 7 is a cross-sectional view of the dual damascene trench of FIG. 5, filled with metal in accordance with the present invention; FIG. 8 is a cross-sectional view of the trench of FIG. 6, filled with metal in accordance with the present invention; FIG. 9 is a cross-sectional view of the dual damascene trench of FIG. 7, planarized down to the dielectric layer in a single step polish process in accordance with the present invention; and FIG. 10 is a cross-sectional view of the trench of FIG. 8, planarized down to the dielectric layer in a single step polish process in accordance with the present invention. DETAILED DESCRIPTION OF PREFERRED EMBODIMENT The present invention relates to semiconductor fabrication processing and more particularly, to a method for reducing failures while employing copper metallizations in semiconductor devices. Attempts by the inventors to employ copper metallizations in semiconductor devices included employing a conformal chemical vapor deposited (CVD) TiN diffusion barrier for a Cu metallization scheme. The diffusion barrier may also include other CVD materials, such as, for example, TaN, WN, etc. It was necessary to have an additional layer, for example Ta or TaN, in between the TiN and a Cu seed layer. This was discovered to cause major problems while shrinking dimensions due to the area limitation of the additional layer in the trenches. The additional layer reduced the effective current carrying cross- section of Cu. The inventors have discovered new methods for employing metallizations for semiconductor devices with surprising results. Using an in-situ deposition process for depositing a diffusion barrier, for example, a titanium nitride (TiN) barrier, by chemical vapor deposition (CVD) without an air-brake after this deposition, a seed layer for a metal may be deposited with superior adhesion to the diffusion barrier. This provides excellent test results in chain resistance, and contact resistance, while reducing failures due to electromigration or other mechanisms. Since, the diffusion barrier may be made conformally, thin diffusion barriers are provided, and metal seed layers may advantageously be deposited directly on the chemical vapor deposited diffusion barrier. By an in-situ CVD TiN without an air-brake, an improvement in metal stack depositions and planarization removal are achieved. No additional bi-layer is necessary to achieve good adhesion between CVD layer and the seed layer . Referring now in specific detail to the drawings in which like reference numerals identify similar or identical elements throughout the several views, and initially to FIG. 1, a cross-sectional view of a partially fabricated semiconductor device 100 is shown. Device 100 may include a memory device, a logic device or a combination of both. Device 100 may include an application specific device or any other semiconductor device, which employs metal lines. A target layer 102 includes a conductive material, such as a metal line, a contact and/or a diffusion region formed in a substrate. A dielectric layer 104 is formed on target layer 102. Dielectric layer 104 may include a silicate glass or an oxide, such as silicon dioxide. Other dielectric materials may be employed as well. Dielectric layer 104 is patterned, in this case, to form a dual damascene structure. The dual damascene structures includes vias or holes 106 extending to target layer 102 and a trench 108 extending into and/or out of the plane of the page. A resist layer 112 is shown for patterning trenches 108. Vias 106 may be formed prior to trenches 108 using a different resist layer (not shown) which is patterned to etch open vias 106. Referring to FIG. 2, dielectric layer 104 may also be patterned using a resist layer 114 to etch holes 107 which may include vias, contact holes or single damascene structures. The structures shown in FIGS. 1 and 2 are illustrative only and should not be construed as limiting the invention. Referring to FIGS. 3 and 4, resist layers 112 and 114 are removed from dielectric layer 104. A diffusion barrier 116 is deposited over dielectric layer 104 and over an exposed portion of target layer 102. Diffusion barrier 116 is advantageously conformally deposited. This conformal deposition of diffusion barrier 116 is preferably performed in an evacuated chamber by a chemical vapor deposition process. A physical vapor deposition process, such as sputtering may also be employed. Diffusion barrier 116 preferably includes Ti, TiN or equivalent materials. Diffusion barrier 116 is preferably as thin as possible, for example less than or equal to 5 nm, or more preferably less than or equal to 3 nm. In some cases, the thickness of diffusion barrier 116 is at least 1 nm. Referring to FIGS. 5 and 6, a seed layer 118 is deposited or flashed onto diffusion barrier. One important aspect of the present invention is that seed layer 118 is formed without an air-brake between the deposition of diffusion barrier 116 and the deposition of seed layer 118. Eliminating the air-brake which is typically performed after a diffusion barrier deposition may be performed by employing a same tool to deposit both diffusion barrier 116 and seed layer 118. A different tool may be employed if the environment around device 100 is maintained in an inert or evacuated state. Eliminating the air-brake after diffusion barrier deposition has demonstrated surprising results as will be described in greater detail below. Seed layer 118 is preferably copper, although other metals, such as aluminum may be employed. Seed layer 118 provides nucleation sites on diffusion barrier 116 such that when the structures are filled better adhesion is provided and voids are eliminated or significantly reduced. Seed layer 118 may be formed by a physical vapor deposition (PVD) process, such as, an ionized sputtering process or by a CVD process. The CVD process is preferred. Seed layer 118 need only be about 0.03 nm in thickness although other thicknesses may also be useful . Referring to FIGS. 7 and 8, holes 106 and trenches 108 (FIG. 7) and holes 107 (FIG. 8) , are filled with a conductive material 120 which is preferably the same material as seed layer 118. Conductive material is preferably copper, although benefits for aluminum and other metals may be obtained in accordance with the present invention. Conductive material 120 may be performed in a different tool other than the tool for the deposition of diffusion barrier 116 and/or seed layer 118 deposition. Conventional tools may be employed as are known to those skilled in the art. A CVD process, a PVD process or a combination of both processes may be employed to provide conductive material 120. Alternately, an electro-chemical deposition (ECD) process may be used to deposited conductive material. Advantageously, conductive material 120 nucleates on seed layer 118 and significantly greater adhesion to diffusion barrier 116 is achieved. The following illustrative options are possible for a reliable Cu metallization scheme: 1) CVD TiN/ionized sputter Cu flash (seed layer)/ CVD Cu/ECD Cu (electroplating) 2) CVD TiN /ionized sputter Cu/ECD Cu 3) CVD TiN/CVD Cu/ECD Cu 4) CVD TiN/ionized sputter Cu flash/CVD Cu/PVD Cu 5) CVD TiN/ionized sputter Cu /PVD Cu 6) CVD TiN/CVD Cu/ PVD Cu. Other methods may also be employed with in-situ deposition of diffusion barrier 116 and seed layer 118. Advantageously, a phase II copper metallization is provided. A phase II cooper includes a copper metallization, which is extendable at least down to 0.1 microns ! Referring to FIGS. 9 and 10, another benefit of employing an in-situ TiN diffusion barrier includes the capability of a 1-step polish process, for example, a chemical-mechanical polish (CMP) process to remove conductive material 120. Where multiple diffusion barrier layers are employed, such as those including an additional Ta/TaN barrier, the additional layers have to be removed in an additional CMP step after conductive material removal . This reduces the CMP throughput dramatically and therefore the cost of operations is very high. In accordance with the present invention, a planarized surface 122 is provided by a one-step CMP process. Testing by the inventors has shown that dishing of conductive material 120 in a trench or hole due to overpolishing is reduced by using the fast one-step process instead of a more expensive two step polish. Interconnect shorts and opens are at least equivalent if not better for the cheaper 1- step CMP process as opposed to the expensive 2-step CMP process. The present invention is particularly useful for sub- micron groundrules, for example, less than 0.3 microns, although the invention may be practiced with larger groundrules. The present invention is also particularly useful for structures (trenches or holes) with aspect ratios of 4:1 or greater. Surprisingly, contact resistance between metal lines of a first layer and contacts to metal lines of a second layer was at least 2.5 times better than for copper metallizations in accordance with the present invention (in-situ diffusion barrier and seed layer) as opposed to copper metallizations with a bi- layer diffusion barrier and air-brake. Similarly, sheet resistance is improved slightly for the present invention. However, chain resistance tests showed results of at least about 10 times better for the present invention as opposed to copper metallizations with a bi-layer diffusion barrier and air-brake. Chain resistance for 0.175 micron structures with 100,000 chains was tested by known testing techniques . If copper is employed about 1000 times fewer electromigration failures occur due to in- situ CVD TiN diffusion barrier and copper metal. At the bottom of contacts, copper diffuses into Si0 2 during test conditions. This causes a void to form, which creates an open failure (e.g., open circuit), in conventional devices. The CVD barrier, in accordance with the invention, provides higher conformity and therefore prevents significant diffusion resulting in fewer failures. The advantages of the present invention include : 1) copper metallizations may be used instead of aluminum (although aluminum sees improvements as well if used) which improves conductivity of metal lines and contacts; 2) improved electrical characteristics are achieved; 3) only one diffusion barrier layer is employed for copper; 4) a single polish step reduces costs (e.g., by about 40%) ; and 5) fewer failures are encountered as a result of the present methods thereby improving reliability of the devices. Having described preferred embodiments for in-situ diffusion barrier and copper metallization for improving reliability of semiconductor devices (which are intended to be illustrative and not limiting) , it is noted that modifications and variations can be made by persons skilled in the art in light of the above teachings. It is therefore to be understood that changes may be made in the particular embodiments of the invention disclosed which are within the scope and spirit of the invention as outlined by the appended claims. Having thus described the invention with the details and particularity required by the patent laws, what is claimed and desired protected by Letters Patent is set forth in the appended claims.

Claims: WHAT IS CLAIMED IS; 1. A method for forming metallizations for semiconductor devices comprising the steps of : forming trenches in a dielectric layer; depositing a single layer diffusion barrier in the trenches ; without an air-brake, depositing a seed layer of metal on the surface of the diffusion barrier; and filling the trenches with metal. 2. The method as recited in claim 1, wherein the step of without an air-brake, depositing a seed layer includes the step of without an air-brake, chemical vapor depositing a seed layer of metal on the surface of the diffusion barrier. 3. The method as recited in claim 1, wherein the steps of depositing a single layer diffusion barrier in the trenches and without an air-brake, depositing a seed layer of metal are performed in a same processing chamber. 4. The method as recited in claim 1, wherein the seed layer and the metal include copper. 5. The method as recited in claim 1, wherein the trenches include dual damascene trenches . 6. The method as recited in claim 1, wherein the diffusion barrier includes one of Ti and TiN. 7. The method as recited in claim 1, wherein the diffusion barrier is less than or equal to 5 nm. 8. The method as recited in claim 1, wherein the step of filling the trenches with metal includes the step of electroplating to fill the trenches with the metal. 9. The method as recited in claim 1, wherein the step of depositing a single layer diffusion barrier includes the step of chemical vapor depositing the diffusion barrier. 10. The method as recited in claim 1, wherein the step of without an air-brake, depositing a seed layer includes the step of without an air-brake, ionized sputtering a seed layer of metal on the surface of the diffusion barrier. 11. The method as recited in claim 1, wherein the step of filling the trenches with metal includes the step of sputtering to fill the trenches with the metal. 12. A method for forming metallizations for semiconductor devices comprising the steps of: forming trenches in a dielectric- depositing a single layer diffusion barrier in the trenches; without an air-brake, depositing a seed layer of metal on the surface of the diffusion barrier; filling the trenches with metal; and planarizing a top surface down to the dielectric layer in a single polishing step to remove the metal and the diffusion barrier. 13. The method as recited in claim 12, wherein the step of without an air-brake, depositing a seed layer of metal on the surface of the diffusion barrier includes the step of without an air-brake, chemical vapor depositing a seed layer of metal on the surface of the diffusion barrier. 14. The method as recited in claim 12, wherein the steps of depositing a single layer diffusion barrier in the trenches and without an air-brake, depositing a seed layer of metal are performed in a same processing chamber. 15. The method as recited in claim 12, wherein the seed layer and the metal include copper. 16. The method as recited in claim 12, wherein the trenches include dual damascene trenches . 17. The method as recited in claim 12, wherein the diffusion barrier includes one of Ti and TiN. 18. The method as recited in claim 12, wherein the diffusion barrier is less than or equal to 5 nm. 19. The method as recited in claim 12, wherein the step of filling the trenches with metal includes the steps of electroplating to fill the trenches with the metal. 20. The method as recited in claim 12, wherein the step of depositing a single layer diffusion barrier includes the step of chemical vapor depositing the diffusion barrier. 21. The method as recited in claim 12, wherein the step of without an air-brake, depositing a seed layer includes the step of without an air-brake, ionized sputtering a seed layer of metal on the surface of the diffusion barrier. 22. The method as recited in claim 12, wherein the step of filling the trenches with metal includes the- step of sputtering to fill the trenches with the metal. 23. A method for forming copper metallizations for semiconductor devices comprising the steps of: forming trenches in a dielectric layer including an oxide; chemical vapor depositing a single layer diffusion barrier comprised of Ti or TiN in the trenches; without an air-brake after the chemical vapor depositing of the single layer diffusion barrier, chemical vapor depositing a seed layer of copper on the surface of the diffusion barrier; and filling the trenches with copper. 24. The method as recited in claim 23, wherein the steps of chemical vapor depositing a single layer diffusion barrier in the trenches and without an air-brake, chemical vapor depositing a seed layer of metal are performed in a same processing chamber. 25. The method as recited in claim 23, wherein the trenches include dual damascene trenches. 26. The method as recited in claim 23, wherein the diffusion barrier is less than or equal to 5 nm. 27. The method as recited in claim 23, wherein the step of filling the trenches with copper includes the step of electroplating copper to fill the trenches with the metal. 28. The method as recited in claim 23, wherein the step of without an air-brake, depositing a seed layer includes the step of without an air-brake, ionized sputtering a seed layer of copper on the surface of the diffusion barrier. 29. The method as recited in claim 23, wherein the step of filling the trenches with copper includes the step of sputtering to fill the trenches with copper.

Inventors: KNORR ANDREAS, LIN CHENTING, RUF ALEXANDER, WEBER STEFAN, KNORR, ANDREAS, LIN, CHENTING, RUF, ALEXANDER, WEBER, STEFAN
Applicants: INFINEON TECHNOLOGIES CORP, INFINEON TECHNOLOGIES NORTH AMERICA CORP.
Application year: 2001
Main classification: H01L21
IPC codes: H01L21