FREQUENCY SYNTHESIZER

Abstract: Frequency synthesizer including a phase accumulator (200), a most significant bit selector (250) and a jitter adjusting circuit (260). The most significant bit selector passes the most significant bit of the output of the phase accumulator to a jitter adjusting circuit to remove jitter before outputting a square wave. The jitter adjusting circuit may be, for example, a phase locked loop or a bandpass filter.

Description: FREQUENCY SYNTHESIZER I. BACKGROUND OF THE INVENTION This invention relates generally to the field of frequency synthesizers, and more specifically to the field of frequency synthesizers that generate square wave signals having a frequency greater than a reference frequency. Phase locked loops (PLL) have been used to generate a clock pulse based on an input or reference signal, whereby the output clock pulse has a frequency which is a multiple of the input signal frequency. In particular, the reference signal is divided by a conventional divider circuit and supplied to the PLL. The divider circuit often divides the reference signal by an integer M. If M is small, the output clock frequency has less granularity and cannot be finely tuned. If M is large, however, the signal supplied from the divider circuit has a relatively long period and the PLL has a slow response time, during which the output of the PLL is susceptible to noise. Phase accumulators (PA) have been used in alternative frequency synthesizer circuits. For example, U.S. Patent No. 5,931,891 entitled "A Digital Frequency Synthesizer", incorporated herein by reference, discloses a relatively complicated frequency synthesizer that includes, PA, discrete digital synthesizer, and a look-up table. A simplified frequency synthesizer, however, is needed that allows for a finely tuned frequency output with minimal noise. II. SUMMARY OF THE INVENTION The present invention provides a simplified frequency synthesizer circuit that uses the most significant bit output from a phase accumulator for input to a phase locked loop or bandwidth filter to generate a square wave having a precisely tuned frequency. A frequency synthesizer consistent with the present invention includes a phase accumulator, a most significant bit selector for selecting a most significant bit (MSB) from an output of the phase accumulator, and a jitter adjusting circuit for processing the selected MSB. Another frequency synthesizer consistent with the present invention includes a phase accumulator, and a phase locked loop for removing jitter from a signal processed by the phase accumulator. Another frequency synthesizer consistent with the present invention includes a phase accumulator, and a bandpass filter for removing jitter from a signal processed by the phase accumulator. III. BRIEF DESCRIPTION OF THE DRAWINGS The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate the invention and, together with the description, serve to explain the principles of the invention. In the drawings: Fig. 1 is a block diagram of a frequency synthesizer according to the present invention including a PLL; Fig. 2 is a circuit diagram of a frequency synthesizer as shown in Fig. 1 ; and Fig. 3 is a block diagram of a frequency synthesizer according to the present invention including a bandpass filter. IV. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Reference will now be made in detail to embodiments consistent with this invention that are illustrated in the accompanying drawings. The same reference numbers in different drawings generally refer to the same or like parts. Consistent with the present invention, a synthesizer circuit generates a square wave for use as a clock signal, for example, based on the most significant bit (MSB) output from a phase accumulator circuit. The MSB output, however, often has jitter (a time varying phase fluctuation), which can be eliminated with a jitter adjustment circuit, such as a PLL or narrow bandpass filter. An MSB selector circuit is used to select and supply the MSB to the jitter adjustment circuit. Fig. 1 is a block diagram of the present invention including a phase locked loop (PLL) 160 as the jitter adjusting circuit. As shown, a phase accumulator section (PAS) 100 generates a signal that is output to a most significant bit (MSB) selector 150. MSB selector 150 selects the most significant bit from the output of the PAS 100. The MSB is input to PLL 160 which, using a series of received bits, generates a square wave 175 without significant jitter. MSB 150 may be a bus or other connection coupling the MSB of PAS 100 with PLL 160. Fig. 2 is a more detailed circuit diagram of the system in Fig. 1 showing the frequency synthesizer of the present invention including a phase accumulator section and a phase locked loop. As seen in Fig. 2, reference clock f r 140 causes register 130 (including a DQ flip-flop, for example) to latch the value of adder circuit 120, which adds an N-byte (N being an integer) integer phase increment value X 110 to the previous output value (the phase value) of register 30. In this manner, each reference clock period causes the phase value output from register 130 to increase linearly, creating a phase ramp. The rate of increase in the phase accumulator value is determined by X. The output of register 130 will increase until a maximum value is reached, at which point the phase value output will rollover to a minimum value. With each rollover, the MSB toggles. An MSB selector circuit, such as a bus or other connection, is coupled to an appropriate output of register 130, and outputs the MSB. Since the MSB is changes between a logic level "1" and "0", the resulting output from the MSB selector circuit constitutes a train of square wave pulses shown as signal 135 in Fig. 2, and having a frequency/ defined as equation (1) follows: PA 100 and resulting signal 135 typically cannot be used alone as a digital synthesizer because signal 135 may contain jitter, a time-varying phase fluctuation. Accordingly, PLL 160 can be provided to reduce jitter and generate a stable output. PLL 160 includes an optional frequency divider circuit 162, a phase detector circuit 164, filter circuit 166, voltage control oscillator (VCO) circuit 168 and an optional loop frequency divider circuit 170. Although not required, signal divider circuit 162 and loop divider circuit 170 advantageously expand the range of frequencies that can be output from PLL 160 so that even frequencies greater than reference frequency f r can be output from PLL 160. MSB 155 is input to signal divider 162 which divides the frequency of signal 155 by an integer M. Phase detector 164 compares the output from divider 162 and a feed back signal output from divider circuit 170, and outputs a signal that is a measure of the phase difference. Filter 166 typically includes a low pass filter circuit that filters the signal output by the phase detector 164. In particular, filter 166 typically has a cutoff frequency lower than expected jitter components in the signal supplied from phase detector 164. The filtered signal is input to VCO 168, which then outputs a square wave signal 175 having frequency/, defined by equation (2) as: KX / = /, (2) M PLL 160 outputs a stable square wave 175, which is also fed back to phase detector 164 via optional divide-by-K (K is an integer) circuit 170. As indicated in formula (2), the granularity of output 175 is determined, at least in part, by phase increment X 110. Moreover, by appropriately choosing K, X and M, the frequency output from the PLL can have a magnitude greater than frequency ... Fig. 3 illustrates an alternative embodiment of the present invention similar to Fig. 1. In Fig. 3, however, the MSB is supplied via selector 150 to bandpass filter circuit 300 instead of PLL 160. Bandpass filter circuit 300 advantageously has a relatively narrow bandwidth of about 1 kHz to thereby significantly reduce jitter. In the embodiment shown in Fig. 3, the signal output from bandpass filter circuit 300 has a frequency defined by equation 3, below: There are many variations that may be made consistent with the present invention. For example, different types of PA and PLL circuits may be used. The foregoing description is presented for purposes of illustration and description. It is not exhaustive and does not limit the invention to the precise form disclosed. Modifications and variations are possible in light of the above teachings or may be acquired from practicing the invention. The scope of the invention is defined by the claims and their equivalents.

Claims: WHAT IS CLAIMED IS: 1. A frequency synthesizer circuit being configured to generate an output signal having desired frequency comprising: a phase accumulator circuit being configured to receive a phase increment value, and output a plurality of bits in response to said phase increment value; a most significant bit selector circuit being configured to select a most significant bit (MSB) from said plurality of bits; and a jitter adjusting circuit being configured to process said MSB, and supply said output signal. 2. The frequency synthesizer of claim 1 wherein said jitter adjusting circuit is a phase locked loop. 3. The frequency synthesizer of claim 2 wherein the phase locked loop includes: a phase detector circuit being configured to receive the MSB and a feedback signal; a filter circuit being configured to receive an output of the phase detector; and a voltage controlled oscillator being configured to receive an output of said filter circuit. 4. The frequency synthesizer of claim 3 wherein the filter has a cutoff frequency lower than expected jitter components in a received signal. 5. The frequency synthesizer of claim 3 wherein said phase locked loop further includes: a first divider circuit being coupled to said phase accumulator and being configured to generate a first output signal having a first frequency equal to a frequency associated with said MSB divided by M, said first divider circuit supplying said first output signal to said phase detector circuit; and a second divider divider circuit being coupled to an output of said frequency synthesizer and being configured to generate a second output signal having a second frequency equal to said desired frequency divided by K, said second divider circuit supplying said second output signal to said phase detector circuit. 6. The frequency synthesizer of claim 1 wherein said jitter adjusting circuit is a bandpass filter. 7. The frequency synthesizer of claim 6 wherein the bandpass filter has a bandwidth approximately equal to 1kHz. 8. The frequency synthesizer of claim 1 wherein the phase accumulator includes: an adder circuit being configured to add said phase increment increment value with an output of said phase accumulator circuit to thereby generate a sum signal; and a register receiving a sum signal from said adder circuit and a reference clock. 9. The frequency synthesizer of claim 1 wherein the MSB selector is a bus.

Inventors: CHIANG TING-KUANG, CHIANG, TING-KUANG
Applicants: CIENA CORP, CIENA CORPORATION
Application year: 2001
Main classification: H03L7
IPC codes: G06F1, H03L7