MULTI-GENERATOR, PARTIAL ARRAY Vt, TRACKING SYSTEM TO IMPROVE ARRAY RETENTION TIME

Abstract: Improved transistor array device performance is obtained by use of bias voltage regulation which tracks with a fraction of a monitor transistor threshold voltage. The circuitry and methods are especially useful for improving the performance of transistor array devices such as DRAM and embedded DRAM. These benefits are obtained especially when at least two bias voltages normally supplied to the array are regulated by tracking with a fraction of an actual threshold voltage of at least one monitor transistor. Performance improvements include improved reliability, wider operational bias conditions, reduced power consumption and (in the case of memory cells) improved retention time.

Description: Multi-Generator, Partial Array V t Tracking System to Improve Array Retention Time Background of the Invention High density dynamic random access memory (DRAM) products and integrated circuit products typically employ transistor arrays. The reliable management of the electrical environment of these arrays becomes increasingly challenging with the increase in number and density (decreased channel length and channel width) of memory array devices. The electrical environment of the array devices is naturally important to the ability of the devices to be operated for their intended purpose, e.g., in the case of a memory array, writing, reading and retaining data in the individual cells of the array. As shown in Figure 1 , a typical DRAM memory cell of a memory array contains an FET transfer transistor 10 which interfaces with a charge storage device (capacitor) 60 which stores the data state of the cell. The array transfer transistor 10 typically has a gate 40 (in the case of DRAM connected to a word line) which is passivated by a dielectric insulator 70. The drain 20 of array transfer transistor 10 acts as a path to charge storage device 60. Source 30 of array transfer transistor 10 acts as a bit line contact path (e.g., a path to allow sensing of the voltage in capacitor 60). Drain 20 and source 30 are separated by well (or body) 50. A primary consideration in the cell transistor operating environment (e.g., range of conditions where the cell is reliable) is leakage current. Leakage may result in cell or product fails, excess power consumption, and/or constrained operating conditions (e.g., need for tight voltage regulation, wider spacing of components, increased redundancy, etc.). In the cell of Figure 1 , the leakage current may occur along several paths. For example, transistor off-state (subthreshold) leakage current A may occur between drain 20 and source 30 along the channel. Junction leakage current B may occur between drain 20 and substrate (body or well) 50 induced by the substrate (body or well) bias. Gate-Induced-Drain- Leakage (GIDL) current C may also occur between drain 20 and the substrate (body or well) 50 induced by the gate bias. The performance of the DRAM array cells may thus be adversely affected if the electrical environment is not effectively controlled. Unfortunately, this control becomes more problematic with decreasing device dimensions, i.e., when channel lengthen is further reduced. Generally, the electrical operating environment of the cell is defined by bias conditions of the transfer transistors which are selected to establish the operating window for the processes to be performed reliably by the chip circuitry during normal operation (e.g., the read, write and other operations). For example, to achieve certain word-line access speed, the word-line boost level (or V pp ) is set to have sufficient gate overdrive. On the other hand, too much overdrive will damage the gate dielectric and cause reliability concern. Also, in order to reduce the cell leakage, the negative word-line level is set properly below ground so that the transfer transistors are turned off more hardly for those non-selected word-lines. However, if biased too much, then the GIDL leakage will dominate the leakage mechanism and result in poor retention situation. Similarly, the body bias, V b , is also implemented to cut down the subthreshold leakage. Excessive body bias will cause junction leakage to increase and would result in unsatisfied retention. Largely for economic reasons, the bias conditions are set during design stage and can be slightly adjusted at the wafer-level burn-in. With an array containing thousands of cells, selecting the appropriate bias conditions may be difficult due to lack of uniformity of cells across the wafer, from wafer to wafer and from lot to lot. In other words, a single set of bias conditions will be difficult to cope with non-uniform threshold voltage distribution across the wafer. The nominal bias conditions for the cell array are typically selected based on the intended cell geometry and performance characteristics assuming all cells act the same; this assumption breaks down as arrays become larger and cell sizes (ground rules) become smaller. Thus, slight variations in the geometry or manufacturing condition across the array on the chip and/or across the wafer will cause increasingly wider variations in the electrical characteristics (e.g. threshold voltage (V t ) of array transfer transistor) among the cells of the array. For example, variations in the planarity of adjacent shallow trench isolation (STI) can cause array V t variations as large as 200mV across a wafer. Variations in array V t may directly translate into degradation of the retention time for the DRAM circuit due to certain array transistors having significant transistor off-state leakage current. The increasingly wide variations in the array V t , make it difficult to obtain a robust design with a fixed bias set, such as a fixed V b (body bias), V pp (word line boost voltage), or Vnwii (negative word line low). Thus, the yield of DRAM chips from the wafer and/or the performance of those chips may be compromised. In the past, this problem has been addressed to some extent by various bias correction techniques to improve the retention time of memory array by optimizing the critical operating voltage conditions. Earlier approaches include tuning the body bias at the end of the product development stage, or by holding the gate of the non- active transfer devices below ground. These approaches tend to over adjust the voltage conditions, and therefore lead to negative impact to the device performance and circuit power consumption. For example, the over-correction of the substrate bias may result in failure of other cells due to increases in junction leakage at high substrate biases. Another example is that the over-adjustment of the gate bias of the non-active transfer devices below ground can also lead to fails in other cells due to increases in gate-induced drain leakage (GIDL) at high off-state gate biases as has mentioned above. Also, the monitor devices used in the past have typically provided wrongful and misleading information regarding the real product array due to mismatch between the dimensions of monitor devices used and those of the real product array. Thus, there is a need for improved bias correction techniques and on-chip support circuits which enable improved bias control and correction to achieve improved chip operation and yield even for memory arrays on the order of 1 giga byte or higher. It would be especially desirable to provide such improvements to enable proper biasing of the chip which can be trimmed at the wafer level burn-in. Summary of the Invention The invention provides methods and circuitry for improved bias condition selection and control for on-chip transistor arrays. The invention also provides transistor arrays devices (or cores) having improved performance using control circuitry of the invention. The invention can potentially lead to significant yield improvement for memory products employing transistor arrays. In one aspect, the invention encompasses methods involving the use of array bias voltage correction where the amount of correction for a given bias voltage for a memory array is based on the threshold voltage of a monitor transistor, but is only a fraction of the monitor transistor threshold voltage. In another aspect, the invention encompasses a method of regulating at least one bias voltage supplied to a transistor array, the method comprising: (a) providing at least one monitor transistor, (b) biasing the monitor transistor(s) provided in step (a) to determine a first monitor threshold voltage, and (c) adjusting a first bias voltage by a first fraction of the first monitor threshold voltage, the first fraction being less than one. Preferably, the transistor array is part of an array of memory cells, more preferably an array of random access memory cells (especially DRAM). Preferably, at least two bias voltages are regulated. The bias voltage(s) are preferably selected from the group consisting of Vbb, V pp , V n iι, bi h (bitline high voltage), and Vbieq (bitline equalization voltage). The monitor transistor(s) is preferably part of a monitor cell located in the transistor array or in a monitor array adjacent to the transistor array. In another aspect, the invention encompasses a transistor array device comprising: (a) an array of transistors, (b) a first power supply to supply a first bias voltage to the array, (c) a first voltage regulator circuit to control the first bias voltage, (d) circuits for communicating to and from the array, and (e) a first monitor cell comprising a first monitor cell transistor, the first monitor cell transistor forming part of the first voltage regulator circuit whereby the first bias voltage is modulated by a fraction of a threshold voltage of the first monitor cell transistor, the fraction being less than one. In another aspect, the invention provides a monitor and voltage control circuit for determining a threshold voltage of at least one monitor transistor and regulating at least one bias voltage (to be supplied to a transistor array) in response to the monitor transistor threshold voltage. The bias voltage(s) to be regulated are preferably selected from the group consisting of Vb b , V pp , V nw ιι- Vbi h , and V b | Θq . The monitor transistor is preferably located in a monitor cell located in the transistor array or in an array adjacent to the transistor array. The invention further encompasses a voltage regulator circuit for regulating a voltage supplied to a transistor array, the circuit comprising: (a) a power supply, (b) a first monitor transistor having a gate and a drain node which are connected to the power supply, (c) a first resistor having a first node connected to a source node of the first monitor transistor, (d) a differential amplifier having a first input connected to a second node of the first resistor, (e) a reference voltage source connected to a second input of the differential amplifier, (f) a charge pump having an input node connected to an output node of the differential amplifier, (g) a second monitor transistor having a gate and a drain node which are connected to the second node of the first resistor, (h) a second resistor having a first node connected to a source node of the second monitor transistor, (i) an output node connecting an output of the charge pump and a second node of the second resistor, whereby a feedback loop is formed from the output of the differential amplifier to the first input of the differential amplifier, the feedback loop including the charge pump, second resistor and second monitor transistor, and (j) an output connection from the output node to the transistor array. These and other aspects of the invention are described in further detail below. Brief Description of the Drawings Fig. 1 is a schematic cross section view of a memory cell transistor. Fig. 2 shows a control circuit for adjusting an array bias voltage in response to a threshold voltage of a monitor array transistor. Fig. 3 is a schematic illustration of a layout of a monitor array adjacent to a memory cell array. Fig. 4 is a schematic illustration of a layout of a monitor cell in a monitor array according to the invention useful in implementing the control circuit of Fig. 2. Detailed Description of the Invention The invention encompasses methods involving the use of array bias voltage correction where a given bias voltage for a transistor array is adjusted fractionally in response to an actual threshold voltage of a monitor device transistor. More preferably, the methods of the invention involve the use of this type of bias correction for at least two array bias voltages. The invention also encompasses voltage regulation circuits for use with power supplies to transistor arrays where the voltage regulation circuit includes at least one monitor cell transistor such that the output voltage is regulated as a function of a fraction of the monitor cell threshold voltage. The invention also encompasses transistor array devices using a power supply regulated using the methods of the invention. The invention enables the achievement of improved array transistor performance, increased operating bias condition ranges, and improved product yield for devices employing transistor arrays. Broadly, the methods of the invention involve setting a bias condition for a transistor array by the following steps: (a) providing at least one monitor transistor, (b) biasing the monitor transistor(s) provided in step (a) to determine a first monitor threshold voltage, and (c) adjusting a first bias voltage by a first fraction of the first monitor threshold voltage, the first fraction being less than one. More preferably, the methods of the invention involve the setting of at least two bias voltage conditions where the methods include the additional step: (d) adjusting a second array bias voltage by a second fraction of at least one monitor threshold voltage. The transistor array may be any array containing numerous transistor devices operating in a similar environment. Preferably, the transistor array is an array such as would be typically used in a dynamic random access memory (DRAM) device chip or in a so-called embedded DRAM (eDRAM) device - e.g. where the memory array is incorporated as a macro to a core logic device chip. The invention is not limited to DRAM or eDRAM devices, but rather may be used wherever a transistor array device, especially any memory array is desired, for example, it can be a flash memory. A typical memory array might have on the order of at least one million transistors, more typically, about tens of millions to billions of transistors. The invention is not limited to any specific memory array configuration or method of making. For example, the invention is illustrated further below in connection with memory cells using trench capacitors, however, the invention is also useful with memory cells using stacked capacitor designs. Apart from incorporation of the structures and circuitry needed to implement the invention, methods known in the art for forming the transistor array(s) and associated devices may be used as known in the art. It should also be understood that the invention may be applied to a plurality of transistor arrays if desired. Accurate monitoring of the device V t is important to successfully implementing the tracking scheme of the invention. Therefore, the monitor cell transistor(s) of the invention is preferably a transistor which is of similar (if not identical) construction as the transistors of the memory array. More preferably, the monitor transistor(s) are located in an environment which is similar (if not identical) to the environment of the transistors of the memory array. For example, in the case of a memory array that functions as part of a DRAM memory array, the monitor cell transistors are preferably constructed as part of DRAM memory cells in a DRAM memory cell array. If desired, the monitor cells may be placed in the actual memory array or may be placed in a monitor array adjacent to the memory array. Preferably, the monitor transistors are located in monitor cells which are in one or more monitor arrays adjacent to the memory array. The monitor transistor will have its gate and body biased substantially identically as those of the transistors in the product transistor array. Therefore, the threshold voltage monitored from the monitor transistor will reflect the threshold voltage of the transistor in the product array. The monitor array must also slightly modified so that its threshold voltage can be physically measured. Preferably, a plurality of monitor cell transistors are provided such that at least two (or two groups of) monitor cell transistors form part of a voltage regulation circuit for a given power supply (bias) to the memory array. In this manner, the actual threshold voltages of the monitor cell transistors is used to adjust the actual power supply to the memory array. The manner in which the voltage regulation circuit is configured is preferably such that the output bias voltage as a result of application of the regulation circuit adjusts (tracks) the output voltage by a fraction (<1) of the actual monitor transistor voltage. Thus, for example, if the desired fraction were 0.5, for both bias voltages V bb and V n ι, then the adjustment for a change of monitor transistor threshold voltage of 200 mV would be 100 mV correction from the V bb adjustment, and 100mV correction from the V nw ι adjustment. The exact fraction of the monitor transistor threshold voltage contributed to the voltage regulation process can be adjusted by the configuration of resistors within the circuit or by other means apparent to those of ordinary skill in the art from the contents of the present application. The desired adjustment fraction can be modified depending on the bias voltage to be supplied, the history of the product incorporating the memory array, or to achieve some other objective. For memory cell memory arrays, the fraction(s) are preferably selected to provide an improved operating range of bias conditions, reduced power consumption, reduced device stress, improved the overall retention time of the memory cells in the array, or other desirable benefits. Preferably, the gate of at least one of the monitor cell transistor(s) is connected to the internal power supply (Vm t ) or to another suitable power source. The invention is not limited to a specific voltage regulator circuit configuration. A preferred voltage regulator circuit layout is shown in Figure 2. In the circuit layout of Fig. 2, a power source (V int ) 102 is connected to gate 104 and drain 106 of the first monitor transistor 108. The other source 110 of monitor cell 108 is connected to the first node of a first resistor (R*ι)112. The second node of resistor 112 is connected 114 is connected to the first input 122 of a differential amplifier 124 and also to drain 116 and gate 118 of the second monitor transistor 120. A second input 126 of differential amplifier 124 120. A second input 126 of differential amplifier 124 is supplied with a reference voltage 126 (V ref ). Preferably, the reference voltage is insensitive to the voltage supply and the chip temperature. The reference voltage can be generated from a conventional band-gap reference circuit or constant voltage source. Source 127 of the second monitor device 118 is connected to the first node of a second resistor (R 2 ) 128. The second node of the second resistor 128 is connected to the output 134 from a voltage generator 130. Node 134 is also connected to a internal voltage supply of the memory array. The voltage generator is controlled by the output of the differential amplifier 124. Thus, a feed back control loop is formed from the output of differential amplifier 124 to generator 130 and back to the input of the differential amplifier 126 through the voltage regulator circuit. Using the above circuit, the bias voltage (generically represented as V b ) supplied to the array would be according to equation (1) below, assuming that the transistors of the first and second monitor cells have approximately equal threshold voltages: V b = Vref [(R2/R1) + 1] + V t [(R2/R1) - 1] + (R /Rι)V in t (1) where V t is the actual threshold voltage of the monitor transistors. R1, R 2 and V ref can be selected based on initial design parameters and/or target values for the bias voltage (e.g., Vbb, V pp , V nw ιι- Vbi , and V | eq etc.) to be supplied. For example, in the case of V bb , if V ref is kept constant, values of R-i, and R 2 can be adjusted according to α [ or R 2 /R*i-1] , so that V b will vary proportionally to α V int , where α is the fraction. In this example, for V iπ t=2.1V, array device's nominal threshold voltage is 1.0V, and the target V b b is -0.5V. In order to get 1/2 V t (actual) tracking, we can set V ref = 0.95V. HSPICE simulation software (available from Meta-Soft, Inc., Campbell, Calif.) was used to generate simulations indicating that V bb can track array V t to a different degree. With a modification of the resistor ratio, V variation corresponding to different fractions of V t variation can be achieved. It is most preferable that the tracking of the bias voltage to be supplied be a function of some fraction (less than one) times the actual threshold voltage of the monitor transistor, also referred to as "partial tracking" to avoid over-correction. The advantages of partial tracking are especially apparent where at least two bias voltages are being adjusted. In order to get dual bias voltages and partial tracking, two regulator circuits as shown in figure 2 are needed. The first circuit is used for the first generator to adjust the first bias against the first fraction of a first monitor transistor V t . Similarly, the second circuit is used for the second generator to adjust the second bias against the second fraction of a second monitor transistor V t . For example, V nw ιι can be adjusted in a manner similar to the adjustment of Vbb described above. The table below illustrates the advantages of improved retention time (i.e., reduced degradation relative to the nominal retention time of the device as designed) associated with partial tracking of at least two bias voltages (e.g., V b b and Vnwii) for two different values of deviation (ΔV t ) from the nominal threshold voltage. The nominal Vt for the array transistors in the example below is 1 V. Thus the invention enables: (1) accurate monitoring of the array Vt (from the corresponding monitor cell transistor V t) and (2) flexibility in adjusting the critical array operating bias conditions such as the substrate bias (V bb ) and the negative word line low level (V nw n). In this way, the low fliers (failing or performance-limiting transistors/cells) due to the across-wafer or across-lot V t variations can be minimized. Retention yield on actual product can therefore be significantly improved. The invention provides monitor and voltage control circuits for determining a threshold voltage of at least one monitor transistor and regulating at least one bias voltage (to be supplied to a transistor array) in response to the monitor transistor threshold voltage. The bias voltage(s) to be regulated are preferably selected from the group consisting of V bb , V pp , V n ιι, V b i h , and V b | eq . The monitor transistor is preferably located in a monitor cell located in the transistor array or in an array adjacent to the transistor array. As with the preferred circuit of Figure 2, preferably at least two monitor transistors are incorporated into the circuit, where one of the monitor transistors forms part of a feedback loop to the differential amplifier. Also, preferably at least two resistors are used as the resistive load where the ratio of resistance of the two resistors controls the fraction of monitor threshold voltage by which the output voltage from the circuit is controlled. While the voltage regulator circuit of the invention has been shown in a basic layout, it should be understood that the invention also encompasses more complicated layouts which basically perform the same partial tracking voltage regulation function. Thus, the voltage regulator circuit for regulating a voltage supplied to a transistor array may be a circuit comprising: (a) a power supply, (b) a first monitor transistor having a gate and a drain node which are connected to the power supply, (c) a first resistor having a first node connected to a source node of the first monitor transistor, (d) a differential amplifier having a first input connected to a second node of the first resistor, (e) a reference voltage source connected to a second input of the differential amplifier, (f) a charge pump having an input node connected to an output node of the differential amplifier, (g) a second monitor transistor having a gate and a drain node which are connected to the second node of the first resistor, (h) a second resistor having a first node connected to a source node of the second monitor transistor, (i) an output node connecting an output of the charge pump and a second node of the second resistor, whereby a feedback loop is formed from the output of the differential amplifier to the first input of the differential amplifier, the feedback loop including the charge pump, second resistor and second monitor transistor, and (j) an output connection from the output node to the transistor array. The invention encompasses transistor array devices comprising: (a) an array of transistors, (b) a first power supply to supply a first bias voltage to the array, (c) a first voltage regulator circuit to control the first bias voltage, (d) circuits for communicating to and from the array, and (e) a first monitor cell comprising a first monitor cell transistor, the first monitor cell transistor forming part of the first voltage regulator circuit whereby the first bias voltage is modulated by a fraction of a threshold voltage of the first monitor cell transistor, the fraction being less than one. More preferably, the device includes multiple power supplies each for providing a separate bias voltage to the transistor array. Also, preferably, the device preferably includes voltage regulation circuits for at least two of the power supplies each regulation circuits preferably including at least two monitor cell transistors which enable partial tracking of the supplied voltage based on the monitor transistor threshold voltage. Referring to Figure 3, a transistor array 200 is provided with one or more monitor transistors located in a monitor array 210 adjacent to the transistor array. In a region 250 of the chip. Also provided in region 250 are power generators which supply powers 220, 230 and 240 to provide bias voltages to array 200. The circuitry of at least one, more preferably at least two of the bias voltage supplies include connections (not shown) to transistors in monitor array 210. If desired, a plurality of monitor arrays may be employed. Also, the monitor array(s) may be located at any convenient position relative to the other design elements of the chip to manage the available chip area. It may be possible to locate the monitor cell transistors in the actual device transistor array, however, this is generally less preferable since it might force an extra design constraint on the transistor array layout. Referring to Figure 4, a portion of monitor array 210 is shown. Preferably, the environment of the transistors in the monitor array is as similar as possible to the transistors of the device transistor array. Thus, where the array is a bank of trench capacitor DRAM memory cells, monitor array 210 preferably contains active areas 410, word lines 457, 459, 480 and trench capacitors 420 similar to those which would be found in a trench capacitor cell DRAM memory array. If desired, monitor array 210 could also contain bit lines (not shown) and other features of a memory array as long as they did not impair the ability of the monitor transistors to function. A monitor cell transistor 300 is formed by joining two active areas 410 to form a longer active area 411. Transistor 300 has a source/drain contact 426, gate 455 and second source/drain contact 450. Contact 450 would not be the normal location for a source/drain contact relative to gate 455 (e.g., if gate 455 were part of a DRAM memory cell), however, it becomes an effective source/drain by biasing of word lines 480 whereby gate 460 effectively becomes a conductor and the portion between gate 455 and contact 450 can be represented as an equivalent resistance 480a shown in the equivalent circuit representation at the bottom of Figure 4. Generally, equivalent resistance 480a is considered as negligible relative to the operation of monitor transistor 300 and relative to resistors such as R-i and R 2 of the Figure 2 circuit. In operation as a monitor cell such as cell 108 of Figure 2, gate 455 and a source/drain contact 426 could be biased by connection to Vint or other appropriate voltage source. Contact 450 would then be connected a resistor R-i not shown in Figure 4. An additional monitor cell could be configured in the monitor array to serve as monitor cell 120 of the Figure 2 circuit. Additionally, monitor array 210 could contain additional monitor cells to act as part of the voltage regulation circuits for other bias voltage supplies to the memory array 200. As noted previously, the invention is not limited to any specific device configuration apart from presence of the monitor transistors with suitable connection to the appropriate voltage regulation circuitry to accomplish the partial tracking of the invention.

Claims: Claims What is claimed is: 1. A method of regulating at least one bias voltage supplied to a transistor array, said method comprising: (a) providing at least one monitor transistor, (b) biasing the monitor transistor(s) provided in step (a) to determine a first monitor threshold voltage, and (c) adjusting a first bias voltage by a first fraction of said first monitor threshold voltage, said first fraction being less than one. 2. The method of claim 1 wherein a first plurality of monitor transistors is supplied in step (a). 3. The method of claim 1 further comprising: (d) providing at least one additional monitor transistor, (e) biasing the additional monitor transistor(s) provided in step (d) to determine a second monitor threshold voltage, and (f) adjusting a second bias voltage by a second fraction of said second monitor threshold voltage, said second fraction being less than one. 4. The method of claim 1 wherein said first fraction is about 0.4 to 0.6. 5. The method of claim 4 wherein said first fraction is about 0.5. 6. The method of claim 3 wherein said first and second fractions total to about 0.9 to 1.1. 7. The method of claim 6 wherein said fractions total to about 1.0. 8. The method of claim 1 wherein said first fraction is determined by a ratio of two resistor values. 9. The method of claim 1 wherein said bias voltage is selected from the group consisting of a body bias, boost word-line bias, negative-word-line-low bias, the bit-line high bias, and bit-line low bias. 10. The method of claim 1 wherein said adjusting step (c) includes: providing a voltage regulation circuit for supplying said first bias voltage to said array, said circuit including a differential amplifier and a charge pump, wherein said differential amplifier receives said first monitor threshold voltage as an input and controls the operation of said charge pump. 11. The method of claim 10 wherein said adjusting step (c) further comprises providing a reference voltage as a second input to said differential amplifier. 12. The method of claim 11 wherein said reference voltage is provided from a a band-gap reference circuit. 13. The method of claim 1 wherein said transistor array is a DRAM array. 14. The method of claim 1 wherein transistor array is an embedded DRAM array. 15. A transistor array device comprising: (a) an array of transistors, (b) a first power supply to supply a first bias voltage to said array, (c) a first voltage regulator circuit to control said first bias voltage, (d) circuits for communicating to and from said array, and (e) a first monitor cell comprising a first monitor cell transistor, said first monitor cell transistor forming part of said first voltage regulator circuit whereby said first bias voltage is modulated by a fraction of a threshold voltage of said first monitor cell transistor, said fraction being less than one. 16. The transistor array device of claim 15 comprising a first plurality of monitor transistors including said first monitor cell transistor wherein at least two of said first plurality of monitor transistors form part of first said voltage regulator circuit. 17. The transistor array device of claim 15 further comprising: (f) a second voltage regulator circuit to control a second bias voltage to be supplied to said array, and (g) a second monitor cell comprising a second monitor cell transistor, said second monitor cell transistor forming part of said second voltage regulator circuit whereby said second bias voltage is modulated by a second fraction of a threshold voltage of said second monitor cell transistor, said second fraction being less than one. 18. The transistor array device of claim 17 comprising first and second pluralities of monitor transistors said pluralities respectively including said first and second monitor cell transistors wherein at least two of said first plurality of monitor transistors form part of said first voltage regulator circuit, and at least two of said second plurality of monitor transistors form part of said second voltage regulator circuit. 19. The transistor array device of claim 15 wherein said transistors of said array are part of a memory cell array. 20. The transistor array device of claim 15 wherein said first monitor transistor has a threshold voltage which is representative of a threshold voltage of said transistors of said array. 21. The transistor array device of claim 19 wherein said first monitor transistor is connected to at least one storage capacitor. 22. The transistor array device of claim 15 wherein said first monitor transistor is located in said transistor array. 23. The transistor array device of claim 15 wherein said first monitor transistor is located in a monitor array adjacent to said transistor array. 24. A voltage regulator circuit for regulating a voltage supplied to a transistor array, said regulator circuit comprising: (a) a power supply, (b) a first monitor transistor having a gate and a drain node which are connected to said power supply, (c) a first resistor having a first node connected to a source node of said first monitor transistor, (d) a differential amplifier having a first input connected to a second node of said first resistor, (e) a reference voltage source connected to a second input of said differential amplifier, (f) a charge pump having an input node connected to an output node of said differential amplifier, (g) a second monitor transistor having a gate and a drain node which are connected to said second node of said first resistor, (h) a second resistor having a first node connected to a source node of said second monitor transistor, (i) an output node connecting an output of said charge pump and a second node of said second resistor, whereby a feedback loop is formed from the output of said differential amplifier to said first input of said differential amplifier, said feedback loop including said charge pump, second resistor and second monitor transistor, and (j) an output connection from said output node to said transistor array. 25. The voltage regulator circuit of claim 24 wherein said monitor transistors are located in a memory cell array. 26. The voltage regulator circuit of claim 24 wherein said monitor transistors have a threshold voltage which is representative of a threshold voltage of said transistors of said array. 27. The voltage regulator circuit of claim 24 wherein each of said monitor transistors is connected to at least one storage capacitor. 28. The voltage regulator circuit of claim 24 wherein said monitor transistors are located in said transistor array. 29. The voltage regulator circuit of claim 24 wherein said monitor transistors are located in a monitor array adjacent to said transistor array.

Inventors: ELLIS WAYNE F, HSU LOUIS L, JI BRIAN L, LI YUJUN, WEINFURTNER OLIVER, ELLIS, WAYNE F., HSU, LOUIS, L., JI, BRIAN, L., LI, YUJUN, WEINFURTNER, OLIVER
Applicants: IBM, INFINEON TECHNOLOGIES CORP, INFINEON TECHNOLOGIES NORTH AMERICA CORP., INTERNATIONAL BUSINESS MACHINES CORPORATION
Application year: 2001
Main classification: G11C5
IPC codes: G11C5, G11C8, G11C11