Method and apparatus for retiming an asynchronous clock

Abstract: A time-to-digital converter is used to determine which edge of the higher-frequency clock (oversampling clock) is farther away from the edge of the lower-frequency timing signal. At the same time, the oversampling clock performs sampling of the timing signal by two registers: one on the rising edge and the other on the falling edge. Then, the register of "better quality" retiming, as determined by the fractional phase detector decision, is selected to provide the retimed output.

Description: TECHNICAL FIELD OF THE INVENTION This invention relates in general to the field of electronics and more specifically to a method for asynchronous clock retiming. DESCRIPTION OF THE RELATED ART Retiming a lower frequency timing signal (or clock) by a higher frequency clock, when both signals are asynchronous to each other, is typically done by passing the lower frequency signal through a series of registers (e.g., flip-flops) that are clocked using the higher frequency clock. There is however, a certain probability of a metastability condition per register stage and the overall probability of metastability at the system output increases exponentially with each register stage used. The number of registers is established such that the Mean Time Between Failures (MTBF) rate is acceptably small. Unfortunately, the metastability condition brings the timing uncertainty of one high-speed clock (or possibly higher) since, during metastability, the output could be resolved at a given clock or at the next. Although the output levels are defined, this timing error is unacceptable in some applications. A need thus exist in the art for a method for asynchronous clock retiming that can overcome some of the problems mentioned above. BRIEF DESCRIPTION OF THE DRAWINGS For a more complete understanding of the present invention, and the advantages thereof, reference is now made to the following detailed description of certain particular and illustrative embodiments and the features and aspects thereof, by way of example only, and with reference to the figures of the accompanying drawings in which: Fig. 1 shows a block diagram of a phase-domain all-digital synchronous PLL synthesizer; FIG. 2 shows a time-to-digital converter (TDC) and period normalization block, forming a fractional phase detector; FIG. 3 shows a timing diagram highlighting a negative fractional phase error condition; FIG. 4 shows a timing diagram highlighting a positive fractional phase error condition; FIG. 5 shows a circuit that is used to determine the "raw" digital fractional phase; FIG. 6 shows a timing diagram for the circuit shown in FIG. 5; FIG. 7 shows a TDC and period normalization block that provide for edge skipping; FIG. 8 shows a timing diagram for the circuit shown in FIG.7 FIG. 9 shows a DCO clock retiming circuit; FIG. 10 shows a timing diagram for the circuit in FIG. 9; FIG. 11 shows the selection of the rising-edge-retimed FREF signal or the falling-edge-retimed FREF; and FIG. 12 shows details of the DCO clock retiming. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT The method described herein is a general solution to the problem of retiming a lower frequency timing signal (or clock) by a higher frequency clock when both signals are asynchronous to each other. In the following described embodiment, the timing signal is a Frequency-Reference clock (FREF), the oversampling clock is a Digitally-Controlled Oscillator (DCO) clock output. Obviously, both of these signals are completely asynchronous to each other. The preferred embodiment will illustratively describe the invention in association with a frequency synthesizer based on a phase-domain All-Digital-Phase-Lock-Loop (ADPLL) structure although the invention can be used in any application where an asynchronous clock retiming is required. A block diagram of an ADPLL synthesizer 100 that can use the present invention is shown in FIG. 1. The PLL loop is a fixed-point phase-domain architecture whose purpose is to generate an RF frequency in the 2.4 GHz Bluetooth band. The central element in synthesizer 100 is a digitally-controlled oscillator (DCO) and the PLL loop used is a fully digital and of type I (i.e., only one integrating pole due to the DCO frequency-to-phase conversion). The PLL loop arithmetically compares the accumulated frequency control word (FCW) in the reference phase accumulator R R (k) in order to arrive at the phase error correction. The FCW input to the reference accumulator is used to establish the operating frequency of the desired channel, and it is expressed in a fixed-point format such that 1 LSB of its integer part corresponds to the f R reference frequency. A more detailed discussion of the synthesizer section can be found in a U.S. patent application entitled "Digital Phase-Domain PLL Frequency Synthesizer", by Staszewski, et al., having serial number 09/603,023, filed on 06/26/2000 and now issued as US Patent 6,326,851. A more detailed discussion of the fractional phase detector used in synthesizer 100 can be found in a U.S. patent application entitled "Digital Fractional Phase Detector", by Staszewski, et al., having serial number 09/608,317, filed on 06/30/2000 and now issued as US Patent 6,429,693. In the ADPLL 100 the reference phase, variable (DCO) phase, phase error, and all other phase signals need to be represented as fixed-point digital word signals that are synchronous to each other and cannot be corrupted by noise. If this is accomplished, then the phase error can be simply an output of a synchronous arithmetic subtractor used as a phase detector. Thus retimed FREF clock (CKR) is used as a synchronous clock. The ADPLL 100 uses a selection control circuit such as a time-to-digital converter (TDC) 202 to measure the fractional (sub-T v ) delay difference between both edges of the DCO clock and the reference clock with a time quantization and resolution of Δt res . This difference is represented by a digital word, the timing diagram for a negative phase error are shown in FIG. 3, while the timing diagram for a positive phase error are shown in FIG. 4. The digital fractional phase is determined by passing the DCO clock through a chain of inverters as shown in FIG. 5, such that each inverter output produces a clock signal slightly delayed than from the previous inverter. The staggered clock phases are then sampled by the same reference clock. Position of the detected transition from a logic 1 to a logic 0 indicates that a quantized time delay Δt r between the FREF sampling edge and the rising edge of the DCO clock, CKV, in Δt res multiples. Similarly, the position of the detected transistion from a logic 0 to a 1 indicates a quantized time delay Δt f between the FREF sampling edge and the falling edge of the DCO clock, CKV. Because of the time-casual nature of this operation, both delay values must be interpreted as positive. This is fine if Δt r is smaller than Δt f . This corresponds to the negative phase error of the classical PLL loop in which the DCO edge is ahead of the reference edge and, therefore, the phase sign has to be negated. However, it is not so straightforward if Δt r is greater than Δt f , which correponds to the positive phase error of the classical PLL loop. The time lag between the reference edge and the following rising edge of the CKV must be calculated based on the available information of the delay between the preceeding rising edge of CKV and the reference edge and the clock half-period, which is the difference T v /2 = Δt r - Δt f . In general, T v /2 = Δt r - Δt f if Δt r ≥ Δt f , otherwise Δt f - Δt r . The above analysis can be summarized in equation in the following equation, where Δt frac is the digital fractional phase detector output: Δt frac = - Δt r if Δt r ≥ Δt f , otherwise Δt r - 2Δt f . . The period-normalized fractional phase is described by:  F = Δ t frac T v In this implementation, the fractional phase is not needed. Instead, Δt r is used as the ε(k) correction that is positive and ε ∈ (0, 1), in the following equation:  r (k) = kN +  0 + ε(k), where  r (k) is the reference phase, k is an index, the  v (k) is the high-rate DCO phase, and ε(k) = Δt r (k)/T v . In practice, it is preferred to obtain the clock period through longer-term averaging in order to ease the calculation burden and linearize the transfer function of 1/T v . The averaging time constant can be as slow as the expected drift of the inverter delay. The actual fractional output of the error correction "ε" needs one extra bit due to the fact that the whole CKV cycle has to be skipped, if the rising edge of FREF transitions is too close before the rising edge of CKV and, as a safety precaution, the falling CKV edge has to be used. This scenario is illustrated in FIGs 7 and 8. Output PHF_I 702 is of the integer least-significant-bit (LSB) weight. The clock retiming solution in accordance with the invention uses the previously-described TDC circuit to determine which edge of the higher-frequency clock (oversampling clock) is farther away, or far enough based on the design criteria, from the edge of the lower-frequency timing signal. Alternatively, in another design, the circuit only needs to find an edge that is far enough to guarantee a low probability of metastability. In this case, it could well be that either edge meets a "far enough" threshold. This predetermined threshold can be determined on a design by design case, and it is usually acceptable for timing values larger than several inverter delays. At the same time, the oversampling clock performs sampling of the timing signal by two registers, one on the rising edge and the other on the falling edge. Then the register of "better quality" retiming, as determined by the fractional phase detector decision, is selected to provide the retimed output. In FIG. 9, there is shown a circuit that allows for the ADPLL 100 to synchronize the reference and variable clock signals in accordance with the invention. Both of the retimed signal paths are provided to a selection circuit such as a multiplexer (mux). In FIG. 10, there is shown the potential metastability of the falling-edge-retimed FREF and the potential metastability of the rising-edge-retimed FREF. The sole purpose is to resample the reference clock with a variable DCO clock as required in order to avoid metastability. It does so by resampling the FREF by both edges of CKV and choosing the one that has the larger clock separation. The select decision is based on the existing TDC output, thus little additional cost is incurred. In case of FREF resampling with the falling edge of CKV, an additional rising-edge CKV retiming is required. A high degree of redundancy in the thermometer-encoded TDC output vector could be exploited to obtain extra error correction and metastability resolution. However, in the preferred embodiment we have chosen a simple extraction of the selection control. In FIG. 11 there is shown a timing diagram highlighting the selection of the rising-edge-retimed FREF signal and the selection of the falling-edge-retimed FREF signal. FIG. 12 highlights how a certain single TDC register output can be used for the edge selection. It is also shown in FIGs 7-12 that it is necessary to skip the whole CKV clock cycle if the FREF rising edge is close to the CKV rising edge. Consequently, an extra bit of information is sent to the phase detector. Several additional pairs of rising/falling reclocking stages are inserted to allow extra time (in multiple of CKV clock cycles) for the SEL_EDGE selection signal to resolve its metastability. The asynchronous retiming method of the present invention begins by sampling the frequency reference clock (FREF) using both edges of an oversampling clock (CKV) that is derived from a controllable oscillator, such as a DCO. The sampling is preferably performed by a pair of clocked memory elements, such as flip-flops or registers, one operating on the positive or rising transition of the CKV clock, and the other operating on the negative or falling transition of the CKV clock. The effect of sampling the FREF clock by the CKV clock is to retime the FREF to either the rising or falling edge of the CKV clock. By using a circuit like a time-to-digital converter to determine which edge of a higher frequency clock (e.g., oversampling clock) is farther away from the significant edge of the lower frequency timing signal, provides for improved asynchronous clock retiming. When the retiming method of the present invention is used in an all-digital PLL synthesizer, as one example, the retimed FREF can be used as a synchronous clock for the synthesizer. The retimed frequency reference (CKR) can be generated using a digitally-controlled oscillator (DCO) output as the oversampling clock. Thus providing for an improved and lower cost design.

Claims: A method for asynchronous retiming comprising: sampling a clock signal (FREF) using both the rising and falling edges of an oversampling clock signal (CKV) to produce both rising and falling edge retimed clock signals; determining which one of the rising or falling oversampling clock signal (CKV) edges lies farther away from a rising or falling edge of the clock signal (FREF); selecting, based on said determination, from either the rising or falling edge clock signal (FREF), the signal edge that provides the larger clock separation; whereby the clock signal (FREF) is retimed to either the rising or the falling edge of the oversampling clock(CKV). A method as defined in claim 1, wherein the sampling step comprises: sampling the rising edges of the oversampling clock signal (CKV) using a first clocked memory element and sampling the falling edges of the oversampling clock signal (CKV) using a second clocked memory element. A method as defined in claim 2, wherein the first and second clocked memory elements comprise registers or flip-flops. A method as defined in claim 2 or claim 3, comprising the step of: providing both the rising and falling edge retimed signal paths to a selection circuit. A method as defined in claim 4, further comprising the step of: delaying both the rising and falling edge retimed signal paths by a controllable amount. A method as defined in claim 5, wherein the delaying step is performed by introducing a predetermined number of shift register stages that are clocked by the oversampling clock signal (CKV) or a clock signal derived from the oversampling clock signal (CKV). The method as defined in any of claims 4 to 6, wherein the selection circuit comprises a multiplexer. The method as defined in claim 7, wherein the multiplexer has an output that is resampled by the oversampling clock signal (CKV). The method of claim any preceding where in said choosing step is performed by a mid-edge detector including a time-to-digital converter (TDC) that is clocked by the frequency clock signal (FREF). The method of any preceding claim, further comprising the steps of: delaying the oversampling clock signal (CKV); sampling the delayed oversampling clock signal (CKV) using the frequency clock signal (FREF) such that the selected retimed signal is away from a metastability condition. The method of any preceding claim, including providing the oversampling clock signal (CKV) from an oscillator output; the lower frequency clock signal (FREF) being a frequency reference signal. A circuit for asynchronous retiming comprising: a sampling circuit for sampling a clock signal (FREF) using both rising and falling edges of an oversampling clock signal (CKV) and producing both rising and falling edge retimed signals; and a selection control circuit coupled to the sampling circuit for determining which of the rising or falling edge of the oversampling clock signal (CKV) lies farther away from an edge of the clock signal (FREF) and for selecting, based on said determination, from the rising or falling edge clock signal (FREF), the signal edge that provides the larger clock separation; whereby the clock signal (FREF) is retimed to either the rising or the falling edge of the oversampling clock (CKV). A circuit as defined in claim 12, wherein the sampling circuit comprises a pair of clocked memory elements. A circuit as defined in claim 12 or claim 13, wherein the selection control circuit comprises a time-to-digital converter (TDC). A circuit as defined in any of claims 12 to 14 further comprising: a delay circuit coupled to the selection circuit for delaying the first and second retimed signals. A circuit as defined in claim 15, wherein the delay circuit comprises at least one shift register. A circuit as defined in any of claims 12 to 16 further comprising a multiplexer coupled to the selection control circuit.

Inventors: LEIPOLD DIRK D, MAGGIO KENNETH J, STASZEWSKI ROBERT B, LEIPOLD, DIRK D., MAGGIO, KENNETH J., STASZEWSKI, ROBERT. B
Applicants: TEXAS INSTRUMENTS INC, TEXAS INSTRUMENTS INCORPORATED
Application year: 2001
Main classification: H03L7
IPC codes: H03L7