INDEPENDENT ASYNCHRONOUS BOOT BLOCK FOR SYNCHRONOUS NON-VOLATILE MEMORY DEVICES

Abstract: A non-volatile memory device (20) having a main memory (23) that operates synchronously with the system clock and an asynchronous boot block (25). The boot block (25) can be activated to operate asynchronously upon initial power up or can be switched from synchronous to asynchronous mode upon receipt of a command signal by control logic circuitry within the device.

Description: Description INDEPENDENT ASYNCHRONOUS BOOT BLOCK FOR SYNCHRONOUS NON-VOLATILE MEMORY DEVICES TECHNICAL FIELD The present invention relates to the filed of non-volatile semiconductor memory devices, and more particularly to a synchronous non-volatile memory device having an independent asynchronous boot block. BACKGROUND ART Non-volatile memory devices include a variety of semiconductor memory devices which have cells that maintain their data when the power is removed from the chip. Types of non-volatile memory devices include flash memory and electrically erasable programmable read only memory (EEPROM) , as well as a variety of other device constructions. Typically, these types of memories oper- ate synchronously with a device system clock in order to read data from the memory array and to program/write data into the memory array. Often times, non-volatile devices include a boot block, which is dedicated area of the memory which is used to store special programs such as an operating system, a BIOS (Basic Input Output System), and the like. Generally, the data in these boot blocks are accessed synchronously with the clock used for the rest of the memory array. The disadvantage to this is that the clock signal and read commands need to be established before the data from the boot block can be accessed. It would be advantageous to be able to access the data from the boot block right away after power up without having to set up the clock or read commands. To do so the boot block would need to operate a synchronously with the regular synchronous main memory portion of the memory device . U.S. Patent No. 5,197,034 to Andrich et al . discloses a non-volatile memory including a main block and a boot block. Circuitry means are coupled to receive a control signal as a control input for allowing the boot block to be updated when the control signal is in a first voltage state and for generating a power off signal to switch the memory into a substantially powered off state when the control signal is in another voltage state. U.S. Patent No. 5,402,383 to Akaogi discloses an electrically erasable non-volatile semiconductor memory device for selective use in boot block type or normal type flash memory devices . The device has a memory cell array, a first erase unit, a second erase unit, and an operation establish unit. When a first operation mode is established, the erasing operation of the memory cell array is carried out by a first erase unit only. When a second operation mode is established the erasing operation of the first erase unit is disabled and the second erase unit is activated to carry out the erase operation. Therefore, the change between the boot block flash memory and a normal-type flash memory can be realized by changing an established value of the operation mode unit. U.S. Patent No. 5,502,835 to Le et al . describes a method for synchronously accessing memory in which an integrated circuit microprocessor reads data from an external memory device through early overlapping memory access cycles, thus allowing efficient accesses to slower speed memory. The circuitry includes a boot region that stores the boot routine. The boot region is part of the chip select generation unit shown in Fig. 13 of the Le et al . patent, and appears to be synchronous. It is an object of the present invention to provide a non-volatile memory device having a boot block that can be accessed asynchronously and can still be programmed/erased in a synchronous operation. It is a further object of the present invention to provide a non-volatile memory device that can either allow the asynchronous boot block to be active after the device is initially powered up or allow switching from synchronous operation to activate the asynchronous boot block upon the assertion of a regular synchronous memory operational command. SUMMARY OF THE INVENTION The above objects have been achieved by a nonvolatile memory device having a main memory block that operates synchronously with the system clock and an inde- pendent asynchronous boot block. This device construction can be used for configuration of the microprocessor/memory controller, in which the device is used, upon initial power up and system reset operations. The nonvolatile memory device includes control logic circuit which can allow the asynchronous boot block to be active after initial power up or can allow the boot block to be activated in synchronous mode and then be switched to asynchronous mode. This allows data to be read immediately from the boot block without having to wait for the clock or read command signals to be established. Additionally, since many microprocessor/memory controllers operate asynchronously, this allows for the non-volatile memory device to be compatible with asynchronous microprocessors . BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a block diagram of the non-volatile memory device of the present invention. Fig. 2 is a block diagram of the asynchronous boot block. Fig. 3 is a circuit diagram of an x-decoder circuit block in the asynchronous boot block. Fig. 4 is a circuit diagram of an x-decoder circuit in the main memory block. Fig. 5 is a circuit diagram of the output buffers of the boot block and main memory block. BEST MODE FOR CARRYING OUT THE INVENTION With reference to Fig. 1, the non-volatile memory device of the present invention is shown. The memory device is made up of a regular synchronous non- volatile memory block 23 and a asynchronous boot block 25. Both the regular synchronous non-volatile memory block 23 and the asynchronous boot block 25 are blocks of memory circuits which may include address inputs, x and y decoders, column selects for read, program and erase, non-volatile memory arrays, sense amplifiers, and output buffers. The memory device 20 includes a plurality of input pins 21 and output pins 27 for receiving commands and outputting commands to and from the memory device. Signal lines 31 and 33 transmit commands between the main memory block 23 and the asynchronous boot block 25. A boot block enable signal 32 is input into the asynchronous boot block 25 and is inverted 35 before being input into the regular main memory block. With reference to Fig. 2, the asynchronous boot block 25 receives a signal 41 to the address portion of the block 49 and x-decoder 47 and y-decoder 48 along with column select 44 and program/erase select 42 determine which block in the memory area 43 will be selected for read, program, and erase operations . The boot block also includes sense amplifiers and output buffers which are used to buffer the output signal 50. The asynchronous boot block can be activated in at least two ways. One way is to issue a "mode register set command, which is a regular synchronous memory opera- tional command, to activate the asynchronous boot block and to disable the regular synchronous non-volatile memory block. In this case, the boot block would be operating in synchronous mode, and the mode register set would switch the boot block to operate in asynchronous mode. This would allow most of the functional operations such as read, program and erase, to be accessible to the asynchronous boot block instead of the regular main memory block. A second way to activate the asynchronous boot block is to have the asynchronous boot block be active, instead of the synchronous non-volatile memory block, upon power up of the chip. A mode register set command can be issued to deactivate the asynchronous boot block at such a time as when it is desired to enable the synchronous main memory block. The mode register set command is normally a synchronous chip operation. Since one would be entering this command in the asynchronous boot block mode of operation, some of the input pins functions such as clock, row access (RAS#) , and column access (CAS#) , etc. cannot be disabled but can be set to their respective non-active states at VIL or VIH at the inputs until they are used for input commands. In this way, while the chip is in asynchronous boot block mode of operation, the synchronous command sequence of programming and erasing can still be issued and functional. This can save a large effort needed to design a set of asynchronous logic for programming and erasing the asynchronous boot block. With reference to Fig. 3, some control logic circuitry is shown which is used to enable and disable the asynchronous boot block. The circuit is Fig. 3, is an x-decoder in the asynchronous food block, while the circuit of Fig. 4 is an x-decoder in the synchronous main memory block. With reference to Fig. 3, the x-decoder logic circuit 60 includes a NAND gate 65 having a plurality of inputs 61, 69 including a boot block enable signal 67. The output of the NAND gate 65 is inverted by inverter 66 producing an output 68. Similarly in Fig. 4, a NAND gate 75 receives a plurality of input signal 71, 79 including a boot block enable signal 77. However, the boot block enable signal 77 is inverted before entering the NAND gate 75. The output of the NAND gate 75 is inverted by inverter 76 producing an output 78. The boot block enable signal can be made active or logically high with the mode register set command or can be made high after power up in order to indicate that the asynchronous boot block is activated. If the asynchronous boot block is not activated, the boot block enable signal will be at a logical low state. In Fig. 3, the output signal will follow the logic combination of the input a-0 to a-n 61, 69 only if the boot block enable signal 67 is at a logic high state. Otherwise, the output 68 will stay at a logic low state as long as the boot block enable signal 67 stays at a logic low state, which indicates that the asynchronous boot block is not activated. With reference to Fig. 4, in the x-decoder circuit block 70 of the syn- chronous main memory block, the output signal 78 will follow the logic combination of the input signals a-0 to a-n 71, 79 if the boot block enable signal 77 is at a logic low state, indicating that the asynchronous boot block is not activated and that the regular synchronous main memory block is enabled. With reference to Fig. 5, the output buffers of the boot block and main memory block are shown. The output buffer control logic circuitry 80 of the asynchronous boot block is combined with the output buffer 90 of the synchronous main memory block has the outputs of each of the buffers provide an output signal 99 at output pad 100. The first logic block 80 which is the output buffer of the asynchronous boot block, consists of a first inverter 83 which receives the boot block enable signal 87 on one input terminal and produces an intermediate control signal on an output terminal of the inverter 83. A NOR gate 84 has a first input terminal coupled to the output terminal of the first inverter 83 and receives the intermediate control signal at that terminal. The NOR gate receives the first input signal 81 at the second input terminal of the NOR gate. The NOR gate produces a first gate signal at a NOR output . The NAND gate 82 receives the boot block enable signal 87 at a first terminal and receives a input signal 81 at the second terminal. The output of the NAND gate 82 is a second gate signal. The two gates signals are input the gates of CMOS inverter consisting of a PMOS transistor and an NMOS transistor 86. The PMOS transistor receives the signal of the output of the NAND gate 82 and the NMOS transistor 86 receives a signal of the output of the NOR gate 84. The output of the inverter formed by the PMOS 85 and the NMOS transistor 86 produces a signal 88 which is sent to the output signal 99 of the output pad 100. The circuit 90 of the synchronous non-volatile memory device block has a inverter 93 receiving the boot block enable signal on an input terminal and producing an intermediate control signal on its output terminal. A NAND gate 92 has a first input terminal coupled to the output terminal of the first inverter 93 and receives the first input signal 91 at the second input terminal producing a first gate signal at the NAND output. The NOR gate 94 receives the boot block enable signal 97 at the first terminal and receives the input signal 91 at a second terminal and produces a second gate control signal at its output. The first gate control signal goes to the PMOS transistor 95 and the second gate control signal goes to the gate of a NMOS transistor 96. The PMOS transistor 95 and the NMOS transistor 96 form an inverter which produces an output 98 which goes to the output pin 100. When the synchronous boot block is activated, the boot block enable signal will be at a logic high and will allow the input signals to control the logic cir- cuitry to drive the output 100 at the same time the boot block enable signal at logic high will turn off logic circuit 90 so that the output buffer and the synchronous main memory block is disabled. When the synchronous boot block is not activated, the boot block enable signal will be at a logic low value such that the output buffer of the asynchronous boot block 80 will be disabled and the low signal to the output buffer 90 of the synchronous main memory block will be enabled. Therefore, even though the output pad 100 is driven by both output buff- ers, only one output buffer will be allowed to drive the pad at any one time and the other buffer will be in a tristate mode. This allows for the enabling and dis- abling of the asynchronous boot block even after the synchronous memory block has been operating.

Claims: Claims 1. A non-volatile memory, comprising: a memory array including a synchronous main memory block and an asynchronous boot block; a plurality of input pins and a plurality of output pins coupled to the memory array; control logic circuitry for receiving address signals, asynchronous control signals, and synchronous control signals including a clock signal; and means for activating and deactivating the asynchronous boot block. 2. The non-volatile memory of claim 1 wherein the means for activating and deactivating the asynchronous boot block includes applying a first control signal to a first input pin coupled to the control logic circuitry, the control logic circuitry providing an output that indicates whether the asynchronous boot block is activated or deactivated. 3. The non-volatile memory of claim 1 wherein the control logic circuitry includes a first x-decoder circuit block in the asynchronous boot block and a second x-decoder circuit block in the synchronous main memory block, said first and second x-decoder receiving a first control signal and each providing an output that is indicative of whether the respective asynchronous or synchronous block is enabled. 4. The non-volatile memory of claim 3 wherein the output of the first x-decoder block is always in an opposite logic state than the output of the second x-decoder block. 5. The non-volatile memory of claim 1 wherein the asynchronous boot block is activated upon receipt of a power-up signal by one of the input pins . 6. The non-volatile memory of claim 5 wherein the asynchronous boot block is deactivated and the synchronous main memory block is activated upon receipt of a mode register set signal by one of the input pins. 7. The non-volatile memory of claim 1 wherein the control logic circuitry includes a first logic block in an output buffer in the synchronous main memory block and a second logic block in an output buffer in the asynchronous boot block, said first and signal logic blocks receiving a first control signal and a first input signal and producing an output on one of the output pins . 8. The non-volatile memory of claim 1 wherein each of the first logic blocks includes: a first inverter receiving the first control signal on an input terminal producing an intermediate control signal on an output terminal; an NAND gate having a first input terminal coupled to the output terminal of the first inverter and receiving the intermediate control signal at the first input terminal, and said NAND gate receiving the first input signal at a second input terminal and producing a first gate signal at a NAND output; a NOR gate receiving the first control signal at a first input and receiving the first input signal at a second input and producing a second gate signal at a NOR output; and a CMOS inverter including a PMOS transistor having a gate coupled to the NAND output, a drain coupled to a voltage supply and a source coupled to the one of -li¬ the said output pins, and an NMOS transistor having a gate coupled to the NOR output, a drain coupled to the one of said output pins and a source connected to a ground potential, said gate of said PMOS transistor receiving said first gate signal and said gate of said NMOS transistor receiving said second gate signal, said output being produced on the one of said output pins . 9. The non- olatile memory of claim 7 wherein each of the second logic blocks includes: a first inverter receiving the first control signal on an input terminal and producing an intermediate control signal on an output terminal; a NOR gate having a first input terminal coupled to the output terminal of the first inverter and receiving the intermediate control signal at the first input terminal, and said NOR gate receiving the first input signal at a second terminal and producing a first gate signal at a NOR output; a NAND gate receiving the first control signal at a first input and receiving the first input signal at a second input and producing a second gate signal at a NAND output; and a CMOS inverter including a PMOS transistor having a gate coupled to the NAND output, a drain coupled to a voltage supply and a source coupled to the one of said output pins, and an NMOS transistor having a gate coupled to the NOR output, a drain coupled to the one of said output pins and a source connected to a ground potential, said gate of said PMOS transistor receiving said first gate signal and said gate of said NMOS transistor receiving said second gate signal, said output being produced on the one of said output pins . 10. The non-volatile memory of claim 1 wherein the memory array is a flash memory type.

Inventors: FRANKLIN DIRK R, HUI EDWARD S, FRANKLIN, DIRK, R., HUI, EDWARD, S.
Applicants: ATMEL CORP, ATMEL CORPORATION
Application year: 2001
Main classification: G11L
IPC codes: G11C7, G11C16