METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE

Abstract: A method of manufacturing a semiconductor device including a PMOS transistor (6) and an NMOS transistor (5) comprises the steps of: (a) providing a semiconductor substrate (1) having a P-well region (3), which is to be provided with the NMOS transistor (5), and an N-well region (2), which is to be provided with the PMOS transistor (6); (b) forming gate electrodes (8) on the P-well region (3) and the N-well region (2); (c) applying a hard mask (10), which covers either the P-well region (3) or the N-well region (2); (d) implanting a source and a drain in the region that is not covered by the hard mask (10), followed by heat activation; (e) implanting pocket implants in the region that is not covered by the hard mask (10), followed by heat activation; (f) removing the hard mask (10).

Description: Method of manufactuπng a semiconductor device The present invention relates to the manufacture of semiconductor devices, and especially to the provision of tools for the reduction of the minimum feature size of Metal Oxide Semiconductor Field Effect Transistors (MOSFETs) in integrated circuits (ICs). More in particular, the present invention relates to a technology enabling the separate formation of source/drain (S/D) junction and pocket counterdoping regions in MOS transistors without the need of extra masking steps. The semiconductor industry continuously stπves to reduce the minimum feature sizes of MOSFETs in integrated circuits. These attempts are essentially dπven by the need to produce ICs at lower costs, while retaining or improving circuit functionality and speed. This downscahng can for instance be achieved by reducing the characteπstic dimensions of the transistors present on these ICs, and especially the gate lengths, the gate oxide thickness and the junction depths, and by increasing the channel doping levels. Short MOS transistors generally suffer from the so-called short-channel effect (SCE): the source and dram regions will approach each other when the gate length is reduced. This has an adverse effect on the switching of the transistors in the sense that the switching is less controlled by the gate electrode, which leads to an undesired decrease m the threshold voltage. This adverse effect can be explained by a mechanism which causes the depletion regions around the source and the drain to occupy an increasingly large fraction of the channel region, so that a lower potential on the gate is needed to achieve inversion in the channel. In the conventional MOSFET scaling scenaπos, SCE has been kept within acceptable limits by reducing the junction depths and increasing the channel dopant concentration. These conventional scenaπos, however, no longer work for sub-0.18 micron devices, because in these devices the suppression of SCE requires too high a doping level in the channel, which gives πse to junction breakdown. A proposed solution to this problem is the use of pocket or halo counterdoping implants. Phosphorus, arsenic or antimony ions are used for pockets in PMOS transistors, while boron or indium ions are used for pockets in NMOS transistors. The pocket implants serve to raise the channel doping level in the immediate vicinity of the S/D regions. This leads to a net increase in the channel doping regions when the gate length is reduced, thereby suppressing the influence of the S/D depletion regions for short-channel devices. In standard MOS processing, and especially in conventional Complementary MOS processing, the pocket implantation step, which is also referred to as the halo implantation step, is combined with the S/D (extension) implantation step. During this combined implantation step, certain areas of the silicon wafers are covered with a patterned resist layer in order to avoid undesired implantation of these areas. For instance, PMOS transistors are covered during formation of NMOS transistors and vice versa. These pocket implants and S/D implants are activated in a single annealing step after removal of the said resist layer. The dopant diffusion during this annealing step determines the distribution of both the pocket dopants and the S/D dopants. An example of a process wherein the size of a first diffusion region of a primary dopant and a halo diffusion region are adjusted by annealing is given in US-A- 5,227,321. A disadvantage of this approach, wherein one annealing step is used to diffuse the dopants, is that the doping profiles of the pocket and the S/D regions cannot be independently tailored in order to improve the device performance. Thus the possibility should be created to implant and anneal the pocket region and the S/D region separately and independently. This would provide the possibility to optimize the dopant distribution and thereby the short-channel performance. A problem lies, however, in the fact that resist layers that cover part of the wafer during implantation cannot be subjected to temperatures above 250°C. This means that fully separating pocket and S/D formation would require the use of extra resist masking steps. For a CMOS process, this would mean that two additional lithography steps are needed. The method of the present invention should not require additional masking or lithography steps, because such steps would extend and complicate the manufacturing process and thus significantly raise the costs of manufacture. The present invention intends to overcome the problems as sketched for the conventional MOS transistor technology. This object is achieved by using hard masking layers enabling the independent formation of pocket and S/D regions. More in detail, the present invention relates to a method of manufacturing a semiconductor device including a PMOS transistor and an NMOS transistor comprising the steps of: (a) providing a semiconductor substrate having a P-well region, which is to be provided with the NMOS transistor, and an N-well region, which is to be provided with the PMOS transistor, (b) forming gate electrodes on the P-well region and the N-well region, (c) applying a hard mask, which covers either the P-well region or the N-well region, (d) implanting a source and a drain in the region that is not covered by the hard mask, followed by heat activation, (e) implanting pocket implants in the region that is not covered by the hard mask, followed by heat activation, (f) removing the hard mask Preferably, step (c) is effected by applying a hard mask layer, coveπng the hard mask layer with a resist layer, patterning this resist layer, and using the patterned resist layer as a mask for patterning the hard mask layer to form the hard mask The hard mask should be sufficiently thick to avoid penetration of the implanted dopants, and therefore advantageously has a thickness of at least 0 05 micron The upper limit of the thickness of the hard mask is less cπtical Sometimes the thickness is determined by economical considerations, as a result of the hard mask will not be very thick In general, the thickness required for the hard mask depends on the chemical composition of the layer used to form the hard mask This determines the penetration depth of the implanted ions. The use of a hard mask that is not too thick, for example a SiGe-hard mask having a thickness below 0 25 micron, preferably below 0 20 micron, has the additional advantage that the effect of ion shadowing that may occur duπng tilted pocket implants is reduced Very good results are obtained by using for example a SiGe-hard mask having a thickness of about 0 15 micron Although several mateπals, especially several oxides, nitπdes and oxynitπdes, can be used for the hard mask, the hard mask advantageously compπses Ge-doped silicon, especially Ge-doped polycrystalhne silicon (poly-Sii x Ge x , which mateπal can be deposited at temperatures of about 450°C for x>0 3, and can withstand rapid thermal annealing conditions), Si-πch SiN or polycrystalhne Ge These mateπals can be applied by, for example, chemical vapour deposition and can be patterned by, for example, plasma etching These mateπals can be removed very selectively from oxides and silicon by, for example, conventional wet etching The present invention will be descπbed in more detail with reference to Figs 1 to 5, which illustrate a suitable method according to the invention In Fig 1 a silicon substrate 1 is shown, provided with an N-well region 2 and a P-well region 3, separated by a field isolation 4 The P-well region 3 is to be provided with an NMOS transistor 5, whereas the N-well region 2 is to be provided with a PMOS transistor 6 Both the P-well region 3 and the N-well region 2 are provided with a gate oxide 7 on which polysihcon gate electrodes 8 are formed After formation of the polysihcon gate electrodes 8, a short oxidation step equivalent to a few nanometers of oxide growth is advantageously earned out to cover the silicon substrate and the polysihcon gate electrodes 8 with an oxide layer 9 Then, a hard mask layer 10 (Fig 2) of Ge-doped polycrystalhne (poly- Sι 0 65 Geo 35 ) is applied by chemical vapour deposition at 450°C The layer is applied in a thickness of about 0 15 micron A customaπly used photoresist layer 11 (thickness about 0 5 micron) is applied on top of the hard mask layer 10 and patterned using conventional lithography The patterned resist layer 11 is used as a mask for patterning the hard mask layer 10 by means of plasma etching, the ultimate result of which is shown in Fig. 3 Fig 4 shows the step wherein arsenic ions are implanted into the P-well region 3 at an energy in the range from 5 to 15 KeV and a dose in the range between 1E15 and 5E15 cm , preferably between 3E14 and 1E15 cm , which implantation step is followed by conventional annealing, thereby forming a source and a dram 12 Fig 5 shows the pocket implantation using boron ions (15-30 KeV, 1E13-1E14 cm 2 ) at a tilt angle of 20-40°, followed by an annealing step The steps shown in Figs 4 and 5 can optionally be reversed, so that first a pocket implant/annealing is earned out followed by a source/dram implant/annealing Subsequently, the hard mask 10 is selectively removed from the wafer (not shown) If desired, the same steps as depicted in Figs 2 to 5 can be earned out for the N-well region 2, using B or BF 2 ions for the source/drain implant and As or P ions for the pocket implant Following the steps descπbed heremabove as part of the present invention, the selectively implanted structure is subjected to conventional further processing to complete the semiconductor device compnsmg the PMOS transistor and the NMOS transistor More in particular, side wall spacers, generally of oxides or nitndes, are formed on the sides of the gate electrodes Subsequently the NMOS area is selectively doped with, generally, arsenic, while using conventional mask technologies, and the PMOS area is selectively doped with, generally, boron The NMOS and PMOS doping steps can be earned out in any order Then, an annealing step is earned out to activate the doped regions Finally, conventional silicidation and metallisation steps are earned out, which ultimately provide the desired semiconductor device

Claims: WO 01/80310 , PCT/EPOl/03749 o CLAIMS 1 A method of manufactuπng a semiconductor device including a PMOS transistor and an NMOS transistor compnses the steps of (a) providing a semiconductor substrate having a P-well region, which is to be provided with the NMOS transistor, and an N-well region, which is to be provided with the PMOS transistor, (b) forming gate electrodes on the P-well region and the N-well region, (c) applying a hard mask, which covers either the P-well region or the N-well region, (d) implanting a source and a drain in the region that is not covered by the hard mask, followed by heat activation, (e) implanting pocket implants in the region that is not covered by the hard mask, followed by heat activation, (f) removing the hard mask 2 A method as claimed in claim 1, wherein, pπor to the application of the hard mask, a dielectnc layer is applied covenng the semiconductor substrate and the gate electrodes 3 A method as claimed in claim 1 or 2, wherein step (c) is effected by applying a hard mask layer, covenng the hard mask layer with a resist layer, patterning this resist layer, and using the patterned resist layer as a mask for patterning the hard mask layer to form the hard mask 4 A method as claimed in claim 1, 2 or 3, wherein the hard mask is applied in a thickness of at least 0 05 micron 5 A method as claimed in claim 4, wherein the hard mask is applied in a thickness below 0 25 micron η 6. A method as claimed in any one of the preceding claims, wherein the hard mask applied compnses Ge-doped silicon, Si-nch SiN or polycrystalhne Ge.

Inventors: KNITEL MATHIJS J, STOLK PETER A, VAN BRANDENBURG ANJA C M C, WOERLEE PIERRE H, KNITEL, MATHIJS, J., STOLK, PETER, A., VAN BRANDENBURG, ANJA, C., M., C., WOERLEE, PIERRE, H.
Applicants: KONINKL PHILIPS ELECTRONICS NV, KONINKLIJKE PHILIPS ELECTRONICS N.V.
Application year: 2001
Main classification: H01L21
IPC codes: H01L21, H01L27, H01L29