Display apparatus comprising two display regions and portable electronic apparatus that can reduce power consumption, and method of driving the same

Abstract: A display apparatus includes a plurality of scanning lines (G) to which a plurality of scanning signals (VG) are inputted, respectively and a plurality of signal lines (S) to which a plurality of display signals (VS) are inputted, respectively and a plurality of capacitance sections (22) respectively provided through a plurality of switching elements (20) at a plurality of intersections of the plurality of scanning lines (G) and the plurality of signal lines (S), and a display section (30) including the plurality of capacitance sections (22). The display section (30) is divided into first and second display regions (31, 32) by a virtual line parallel to at least one of the plurality of scanning lines (G). The plurality of scanning signals (VG1∼VGn-1) are inputted at first intervals to a first group of the scanning lines (G1∼Gn-1) corresponding to the first display region (31) of the plurality of scanning lines (G). The plurality of scanning signals (VGn, VGn+1···) are inputted at second intervals different from the first intervals to a second group of the scanning lines (Gn, Gn+1···) corresponding to the second display region (32) of the plurality of scanning lines (G).

Description: Background of the Invention 1. Field of the Invention The present invention relates to an active matrix liquid crystal display apparatus and a method of driving an active matrix liquid crystal display apparatus according to the preamble of claims 1 and 14. Portable electronic apparatusses recently begin to employ an active matrix drive method represented by a TFT (Thin-Film-Transistor) method suitable for a display apparatus of a color dynamic picture. The portable electronic apparatus requires that a consumptive power is especially reduced since large restriction is put on battery capacity. Conventionally, in a passive matrix drive type of a portable electronic apparatus represented by the STN type, techniques for reducing the consumptive power at the section which do not require the usual indication on the liquid crystal display panel are known. Since the passive matrix driving method is different, these techniques can-not be applied to the active matrix driving method. It is desirable to attain a low consumptive power manner optimal for the driving method of the active matrix drive type. EP 0 974 952 A1, EP 0 852 371 A1 and EP 0 655 725 A1 disclose an active matrix liquid crystal display apparatus and a method for driving such display according to the preamble of claims 1 and 14, respectively. EP 0 651 367 A1, EP 0 750 288 A2, NL 1 002 584 C and WO 98 21707 A disclose further liquid crystal displays. EP 0 607 778 A1 discloses an active matrix liquid crystal display apparatus with switches mounted in a shift register circuit being part of a scan line driving circuit. EP 0 797 182 A1 and NEC Data sheet MOS integrated circuit µPD16654, May 1998, disclose active matrix liquid crystal display circuits with an AND circuit connected between a shift register circuit and the LCD panel. Summary of the Invention The object of the present invention is to provide an active matrix liquid crystal display apparatus that does not suffer from bad influence caused by application of direct current voltage and can reduce consumptive power. The invention solves this object with the features of independent claims 1 and 14. According to another aspect of the present invention, the display section is divided into first, second and third display regions by two virtual lines parallel to at least one of the plurality of scanning lines, wherein a third portion of the plurality of scanning signals are inputted at a third refresh rate to a third group of the scanning lines corresponding to the third display region of the plurality of scanning lines, and wherein at least one of the first, second and third refresh rates is different from a remaining one in a case that the at least one is withdrawn from the first, second and third refresh rates. According to another aspect of the present invention, a portable electronic apparatus has a display apparatus according to one of the display apparatus claims. The display apparatus of the present invention is based on the active matrix drive method, and has a plurality of regions having different refresh rates (a display rate, a write frequency and an gate-on period) on a single screen. The active method is used to control the voltages applied to a scanning line of a second display region, a signal line, an opposite common electrode and a liquid crystal. Thus, it is possible to reduce consumptive power and also to carry out picture display (a middle between a static picture and a first display region) in which picture change is smaller than that of a dynamic picture of the first display region (Since an accumulation voltage is dropped with elapsing time, the contrast of a picture may be dropped). Brief Description of the Drawings Fig. 1A is a circuit diagram showing a schematic circuit configuration of a typical TFT type LCD panel; Fig. 1B is a view when the LCD panel of Fig. 1A is divided into two sections; Fig. 2A is a timing chart showing the voltage of a display signal sent to a signal line in a method of driving a typical TFT type LCD panel; Fig. 2B is a timing chart showing an opposite common voltage commonly sent to all pixel capacities in a method of driving a typical TFT type LCD panel; Fig. 2C is a timing chart showing a voltage of a scanning signal VG1 sent to a scanning line G1 in a method of driving a typical TFT type LCD panel; Fig. 2D is a timing chart showing a voltage of a scanning signal VG2 sent to a scanning line G2 in a method of driving a typical TFT type LCD panel; Fig. 2E is a timing chart showing a voltage of a scanning signal VGn sent to a scanning line Gn in a method of driving a typical TFT type LCD panel; Fig. 2F is a timing chart showing a voltage of a scanning signal VGn+1 sent to a scanning line Gn+1 in a method of driving a typical TFT type LCD panel; Fig. 3A is a timing chart showing the voltage of a display signal sent to a signal line in a method of driving a TFT type LCD panel of an embodiment of a display apparatus of the present invention; Fig. 3B is a timing chart showing an opposite common voltage commonly sent to all pixel capacities in a method of driving a TFT type LCD panel of an embodiment of a display apparatus of the present invention; Fig. 3C is a timing chart showing the voltage of a scanning signal VG1 sent to a scanning line G1 in a method of driving a TFT type LCD panel of an embodiment of a display apparatus of the present invention; Fig. 3D is a timing chart showing the voltage of a scanning signal VG2 sent to a scanning line G2 in a method of driving a TFT type LCD panel of an embodiment of a display apparatus of the present invention; Fig. 3E is a timing chart showing the voltage of a scanning signal VGn sent to a scanning line Gn in a method of driving a TFT type LCD panel of an embodiment of a display apparatus of the present invention; Fig. 3F is a timing chart showing the voltage of a scanning signal VGn+1 sent to a scanning line Gn+1 in a method of driving a TFT type LCD panel of an embodiment of a display apparatus of the present invention; Fig. 4 is a view showing a connection example between a shift register and an LCD panel used in this embodiment; Fig. 5 is a view showing a configuration of a shift register in this embodiment; Fig. 6 is a view showing a connection example between a shift register and a three-division LCD panel; Fig. 7 is a view showing a configuration of a shift register of Fig. 6; Fig. 8 is a view showing a circuit configuration of a pixel portion of a TFT type LCD at an ideal state; Fig. 9 is a view showing an actual equivalent circuit when TFT is at an off-state; Figs. 10A to 10F are timing charts analogous to those of Figs. 3A to 3F in another method of driving a TFT type LCD panel of an embodiment of a display apparatus of the present invention; Figs. 11A to 11F are timing charts analogous to those of Figs. 3A to 3F in still another method of driving a TFT type LCD. Figs. 12A to 12F are timing charts analogous to those of Figs. 3A to 3F in yet another method of driving a TFT type LCD panel of an embodiment of a display apparatus of the present invention; Figs. 13A to 13F are timing charts analogous to those of Figs. 3A to 3F in yet another method of driving a TFT type LCD panel of an embodiment of a display apparatus of the present invention. Description of the Preferred Embodiments An embodiment of the present invention will be described below with reference to the attached drawings. At first, a three-terminal device matrix drive method is described for using TFT as a conventionally typical switching device. An operational principle of LCD (Liquid Crystal Display) based on an active matrix drive using a three-terminal device is described with reference to Figs. 1, 2A~2F. As shown in Fig. 1A, TFTs 20 are positioned at the intersections of matrix lines composed of scanning lines G1, G2, ··· Gn, Gn+1 ··· and signal lines S1, S2 ···. Gate electrodes of the TFTs 20 are connected to the scanning lines G1, G2, ··· Gn, Gn+1 ···. Their source electrodes are connected to the signal lines S1, S2 ···. And, their drain electrodes D are connected to pixel electrodes. If the electrode is made of transparent metal, this is a transparent liquid crystal display using a light of a back light. If it is a reflective electrode, this is a reflective liquid crystal display using an external light. By the way, n is any integer equal to or greater than 2. If a direct current voltage is applied to a liquid crystal for a long time, a deterioration phenomenon is induced such as a change in a material property and a drop of a specific resistance and the like. Thus, an alternating current drive is required from the viewpoint of the life of an LCD panel. So,the polarity of drive voltage is inverted. For this reason, the polarity of the drive voltage is inverted for each frame (refresh). As shown in Figs. 1A, 2C~2F, a scanning signal is sent to the scanning lines G1, G2, ··· Gn, Gn+1 ··· by using a line sequence drive method. As shown in Fig. 2A, a parallel display signal (picture signal) whose polarity is inverted for each frame FT is sent to each of the signal lines S1, S2 ···. Symbol VS of Fig. 2A denotes a voltage of a display signal sent to any one of the plurality of signal lines S1, S2 ··· (hereafter, one of them is described as the signal line S1). Symbol VCOM of Fig. 2B denotes an opposite common voltage that is commonly sent from an opposite common electrode COM to all pixel capacities 22 of the LCD panel, as shown in Fig. 1A. As shown in Figs. 2A and 2B, each of the display signal and an opposite common signal (corresponding to the opposite common voltage VCOM) is driven at an alternating current. As shown in Fig. 2B, the opposite common signal whose polarity is inverted for each frame FT is sent to the opposite common electrode COM. The display signal is written to the capacity 22 of each pixel (the capacity 22 includes both a liquid crystal capacity and an accumulation capacity) through a TFT switch 20 that is controlled to be turned on and off, in accordance with the scanning signal. A liquid crystal on each pixel electrode is operated on the basis of a potential difference between a pixel electrode voltage VD corresponding to the display signal and the opposite common voltage VCOM at that time. The operation for writing the display signal to the pixel electrode (capacity 22) is carried out by using a method of sampling a parallel display signal to be simultaneously sent to the signal lines S1, S2 ··· by using a scanning signal to be sequentially sent to the plurality of scanning lines G1, G2, ··· Gn, Gn+1 ··· (Line Sequence Drive). As for the display signal written to the pixel electrode, a next scanning signal is inputted after one frame FT from the execution of its write operation. Until a display signal whose polarity (with the opposite common voltage VCOM as a standard) is written to an already written display signal in response to the input scanning signal,the potential of the already written display signal is maintained. So, the liquid crystal is driven at a semi-static state. The polarity of the display signal sent to a signal line S1 is inverted for each frame FT. As shown in Fig. 2A, as for a pixel electrode voltage VD corresponding to a voltage of the display signal sent to the signal line S1, at its lead (a voltage applied to a capacity 22 connected through the TFT switch 20 to the scanning line G1 at a highest order), a positive write is performed on a first frame FT, a negative write is performed on a second frame FT, a positive write is performed on a third frame FT, and a negative write is performed on a fourth frame FT. Hereafter, it is similarly done. As shown in Fig. 1B, an LCD panel 30 is divided into an upper half (first display region) 31 and a lower half (second display region) 32, and it is driven. The first display region 31 is in a range between the scanning lines G1, G2, ···, Gn-1. The second display region 32 is in a range between the scanning lines Gn, Gn+1 ···. If it is desired to display a picture having a small picture change on the first display region 31 and display a usual picture on the second display region 32 and accordingly reduce a consumptive power, the second display region 32 is intermittently driven to thereby reduce the consumptive power. For example, let us suppose that a date and hour and a battery remaining amount are usually displayed on the first display region 31 having a narrow area, and on the other hand, let us suppose that an antenna indication or a white screen indication is displayed on the second display region 32 having a wide area, at a wait time except the usual usage time. Accordingly, the intermittent drive of the second display region 32 at the wait time enables the consumptive power to be reduced. The time band, in which the picture of the second display region 32 is not changed in picture, does not require that the scanning signal is sent to the scanning lines Gn, Gn+1 ··· of the second display region 32. In the time band, a display signal when a scanning signal is sent to the scanning lines Gn, Gn+1 ··· immediately before the time band is held in a capacity section 22 of the second display region 32. For example, if the voltage of the display signal when the scanning signal is sent to the scanning lines Gn, Gn+1 ··· is equal to or less than a threshold and immediately after its supply, the scanning signal is not sent to the scanning lines Gn, Gn+1 ···, the screen of the second display region 32 is kept white when a liquid crystal of each pixel is a normally white type. As mentioned above, according to the method in which the scanning signal is not sent to the second display region 32 (scanning lines Gn, Gn+1 ···), the consumptive power can surely be reduced. However, as described below in detail, the fact has been found that the continuation of the condition in which the scanning signal is not merely inputted to the scanning line may cause a direct current voltage to be applied to the liquid crystal and result in the deterioration phenomenon such as the change of the material property and the drop of the specific resistance and the like. A TFT type LCD has a parasitic resistance, and a leak current is induced from a pixel potential. Thus, the pixel potential is not always attenuated in a direction of a zero volt, in both the positive write and the negative write such as a field through voltage and the like. It may occur that an unexpected direct current voltage is applied to the liquid crystal, and this case leads to a factor of a deterioration. For this reason, even in the second display region 32 in which the consumptive power is reduced, it is not desirable to stop the supply of the scanning signal for a long time. It is necessary that the scanning signal is sent even if the write period is long. The pixel section of the TFT type LCD may be ideally illustrated as shown in Fig. 8. Thus, if it is at the ideal state, when the TFT 20 is at an off-state, the TFT 20 serving as a switch is made at an open state. Hence, a liquid crystal voltage VLC is held which is written to a liquid crystal capacity CLC and an accumulation capacity CST. Here, the liquid crystal voltage VLC corresponds to a potential difference between the pixel electrode voltage VD and the opposite common voltage VCOM. However, an off-resistance RTFT of the TFT 20 is not infinite. Moreover, the capacity section of the liquid crystal also has a finite resistor value RLC. An actual equivalent circuit when the TFT 20 is at the off-state is illustrated as shown in Fig. 9. Thus, charges written to the liquid crystal capacity CLC and the accumulation capacity CST are discharged through the resistor RLC. Also, they are discharged or charged through the resistance RTFT (since the potential of the signal line is changed on the basis of the picture (display) signal that is momentarily changed, both the discharging and charging actions are done in the resistance RTFT). Here, when the pixel section is observed (except the TFT 20), a discharge time constant τ can be represented by the following equation: τ = RLC × (CLC + CST). If the influence from only the resistor value RLC of the liquid crystal capacity section is considered, it suffices to increase the value of the accumulation capacity CST. However, as the accumulation capacity CST is made greater, load on the TFT 20 is made greater. Thus, it is necessary to improve current supply ability of the TFT 20, in proportion to the load. This results in the drop of the off resistance RTFT in the TFT 20. As a result, the suppression of the discharging/charging phenomenon can not be expected at the RTFT section. Also, it may occur that the off resistance RTFT of the TFT 20 does not exhibit a merely linear resistive property because of a fluctuation of a process for manufacturing the TFT 20 and exhibits a non-linear property in which the property is changed depending on a voltage and a polarity. Thus, it is impossible to expect the simply discharging/charging property. As a result, the continuation of the off-state of the TFT 20 causes the voltages written to the liquid crystal capacity CLC and the accumulation capacity CST to be gradually changed. The direction of the change is not uniform. The continuation of this changed state causes the direct current voltage to be continuously applied to the liquid crystal. Thus, fear may occur that the molecules of the liquid crystal within the liquid crystal panel and the related material are dissolved to thereby bring about the aging deterioration. In the conventional method of using the TFT type LCD (for example, the write at 60 Hz), both the resistor value RLC of the liquid crystal capacity and the off resistance RTFT of the TFT 20 are sufficiently large. Thus, there is no problem with regard to the discharging/charging action. However, in order to reduce the consumptive power, only keeping the TFT 20 at the off-state may have bad influence on the liquid crystal. Thus, this embodiment uses the feature of the hold device for holding the voltage at which the TFT type LCD is written, and makes the write period longer and drives it, and accordingly attains both the maintenance of the original reliability and the reduction in the consumptive power. In this case, the fact that the liquid crystal driven at the long write period needs to be driven at the alternating current is similar to that of the liquid crystal driven at the usual write period. The operational principle in this embodiment is described with reference to Figs. 3A ~ 3F. Figs. 3A~3F show a case in which a picture of the second display region 32 is not changed in picture (including a case that the entire surface of the second display region 32 is still kept white). Instead of the above-mentioned case, it may occur that a picture corresponding to a lengthened write period (this picture has the picture change smaller than that of the picture of the first display region 31 of the usual write period) is displayed on the second display region 32. In Figs. 3A and 3B, each of the display signal and the opposite common signal is driven at the alternating current, similarly to Figs. 2A and 2B. The polarity of each pixel is inverted for each refresh. At first, a first frame FT is described. As shown in Fig. 3E, in the first frame FT, a scanning signal VGn is sent to the scanning line Gn of the second display region 32 at the usual timing (the timing equal to that of Fig. 2). Similarly, as shown in Fig. 3F, in the first frame FT, a scanning signal VGn+1 is sent to the scanning line Gn+1 of the second display region 32 at the usual timing (the timing equal to that of Fig. 2). That is, in the first frame FT, the scanning signals are sequentially inputted to all the scanning lines G1, G2, ··· Gn, Gn+1 ··· of the LCD panel 30. Thus, not only the first display region 31 but also the second display region 32 is driven. In Figs. 3A, 3E and 3F, a voltage VS of a display signal sent to a liquid crystal capacity 22 connected through the TFT 20 to the scanning line Gn when the scanning signal VGn is sent to the scanning line Gn and a voltage VS of a display signal sent to a liquid crystal capacity 22 connected through the TFT 20 to the scanning line Gn+1 when the scanning signal VGn+1 is sent to the scanning line Gn+1 are different from each other in polarity and equal to each other in amplitude. When the scanning signal VGn is sent to the scanning line Gn and when the scanning signal VGn+1 is sent to the scanning line Gn+1, the values of the voltages applied to the respective capacities 22 are equal to each other (an absolute value of a potential difference between the VD and the VCOM). If voltage at each pixel is equal to or smaller than a threshold of the liquid crystal, each pixel is white when the liquid crystal of each pixel is a normally white type. Moreover, its gradation is the same. The above-mentioned explanation is described with regard to the scanning lines Gn, Gn+1. The operation in the above-mentioned explanation is repeated for the scanning lines Gn+2, Gn+3, ···. That is, the scanning signals VGn+2, VGn+3, ··· are sent to the scanning lines Gn+2, Gn+3, ···, by using the line sequence drive method, similarly to Figs. 2E and 2F. Voltage VS of a display signal sent to a liquid crystal capacity 22 connected through the TFT 20 to the scanning line Gn+2 when the scanning signal VGn+2 is sent to the scanning line Gn+2 and a voltage VS of a display signal sent to a liquid crystal capacity 22 connected through the TFT 20 to the scanning line Gn+3 when the scanning signal VGn+3 is sent to the scanning line Gn+3 are different from each other in polarity and equal to each other in amplitude. Here, voltage VS of the display signal sent to the liquid crystal capacity 22 connected through the TFT 20 to the scanning line Gn+2 when the scanning signal VGn+2 is sent to the scanning line Gn+2 and voltage VS of the display signal sent to the liquid crystal capacity 22 connected through the TFT 20 to the scanning line Gn+1 when the scanning signal VGn+1 is sent to the scanning line Gn+1 are different from each other in polarity and equal to each other in amplitude. When the scanning signal VGn+1 is sent to the scanning line Gn+1, when the scanning signal VGn+2 is sent to the scanning line Gn+2 and when the scanning signal VGn+3 is sent to the scanning line Gn+3, the values of the voltages applied to the respective capacities 22 are equal to each other (the absolute value of the potential difference between the VD and the VCOM). They are equal to or less than the threshold of the liquid crystal of each pixel. Thus, each pixel becomes white in the same graduation. The above-mentioned display signal VS shown in Fig. 3A corresponds to any one of the plurality of signal lines S1, S2 ··· (here, it is assumed to be the signal line S1). As for the other signal lines (here, they are assumed to be the signal lines S2, S3···), when the scanning signals VGn, VGn+1 ··· are sent to the scanning lines Gn, Gn+1 ···, the value of the display signal sent to each of the liquid crystal capacities 22 connected through the TFTs 20 to the scanning lines Gn, Gn+1 ··· is equal to any one of the above-mentioned signal lines (signal line S1). From the above-mentioned explanation, the whole of the second display region 32 is white in the same gradation. The second frame FT will be described below. As shown in Figs. 3C and 3D, in the second frame FT, the scanning signal VG1, VG2, ··· VGn-1 ··· are sent to the scanning lines G1, G2, ··· Gn-1 of the first display region 31, similarly to Figs. 2C and 2D. On the other hand, in the second frame FT, the pulses for turning the TFTs on, such as the scanning signals VGn, VGn+1 ···, are not sent to the scanning lines Gn, Gn+1 ··· of the second display region 32, differently from Figs. 2E and 2F. Thus, in the second frame FT, all the TFTs 20 of the second display region 32 are at the off-state (the second display region 32 is not driven). Hence, a new voltage (the potential difference between the VD and the VCOM) is never applied to each of the liquid crystal capacities 22 of the second display region 32. In the second frame FT, the voltage applied in the first frame FT is held in each of the liquid crystal capacities 22 of the second display region 32. Thus, the respective pixels of the second display region 32 are white in the same graduation. In the second frame FT, the charges accumulated in the respective liquid crystal capacities 22 of the second display region 32 may be slightly discharged with an elapse of a time, as compared with the first frame FT. However, if the discharge amount is equal to or less than the threshold voltage of the liquid crystal, no problem on the actual usage occurs. In the second frame FT, all the TFTs 20 of the second display region 32 are at the off-state (not driven). Thus, each of the voltage VS of the display signal and the opposite common voltage VCOM, which correspond to each liquid crystal capacity 22 (the scanning lines Gn, Gn+1 ···) of the second display region 32 has no relation to the picture (color) of the second display region 32. In this embodiment, the liquid crystal voltage VLC of each pixel of each liquid crystal capacity 22 of the second display region 32 in the second frame FT is equal to the liquid crystal voltage VLC of each pixel corresponding to each liquid crystal capacity 22 of the second display region 32 in the first frame FT (fixed from the first frame FT). The third frame FT will be described below. In the third frame FT, the second display region 32 is not driven similarly to the second frame FT. The operation with regard to the second display region 32 is equal to that of the second frame FT. The condition of the second display region 32 is equal to that of the second frame FT. In the third frame FT, the charges accumulated in the respective liquid crystal capacities 22 of the second display region 32 may be slightly discharged with an elapse of a time, as compared with the second frame FT. However, if the discharge amount is equal to or less than the threshold voltage of the liquid crystal, no problem on the actual usage occurs. The fourth frame FT will be described below. In the fourth frame FT, the second display region 32 is driven similarly to the first frame FT. The operation with regard to the second display region 32 is equal to that of the first frame FT except the following points. As shown in Figs. 3A, 3E and 3F, in the first frame FT, the voltage VS of the display signal sent to the liquid crystal capacity 22 connected through the TFT 20 to the scanning line Gn when the scanning signal VGn is sent to the scanning line Gn is the positive potential (with the opposite common voltage VCOM as the standard). The voltage VS of the display signal sent to the liquid crystal capacity 22 connected through the TFT 20 to the scanning line Gn+1 when the scanning signal VGn+1 is sent to the scanning line Gn+1 is the negative potential (with the opposite common voltage VCOM as the standard). On the contrary, the polarity of each voltage VS of the fourth frame FT is opposite to that of the first frame FT. That is, in the fourth frame FT, the voltage VS of the display signal sent to the liquid crystal capacity 22 connected through the TFT 20 to the scanning line Gn when the scanning signal VGn is sent to the scanning line Gn is the negative potential (with the opposite common voltage VCOM as the standard). The voltage VS of the display signal sent to the liquid crystal capacity 22 connected through the TFT 20 to the scanning line Gn+1 when the scanning signal VGn+1 is sent to the scanning line Gn+1 is the positive potential (with the opposite common voltage VCOM as the standard). From the above-mentioned explanation, the liquid crystal of each pixel in the second display region 32 is driven at the alternating current between the first frame FT and the fourth frame FT. In the fourth frame FT, the voltage VS of the display signal sent to the liquid crystal capacity 22 connected through the TFT 20 to the scanning line Gn when the scanning signal VGn is sent to the scanning line Gn and the voltage VS of the display signal sent to the liquid crystal capacity 22 connected through the TFT 20 to the scanning line Gn+1 when the scanning signal VGn+1 is sent to the scanning line Gn+1 are different from each other in polarity and equal to each other in amplitude, similarly to the first frame FT. When the scanning signal VGn is sent to the scanning line Gn and when the scanning signal VGn+1 is sent to the scanning line Gn+1, the values of the voltages applied to the respective capacities 22 are equal to each other (the absolute value of the potential difference between the VD and the VCOM). Each of the values is equal to or less than the threshold of the liquid crystal of each pixel. The above-mentioned explanation is described with regard to the scanning lines Gn, Gn+1. The operation in the above-mentioned explanation is repeated for the scanning lines Gn+2, Gn+3, ···. Thus, the respective liquid crystal capacities 22 of the second display region 32 are only different from each other in polarity. So, they are driven similarly to the first frame FT. Each pixel of the second display region 32 is white in the same graduation as the first frame FT. The fifth frame FT (not shown) will be described below. The operation with regard to the second display region 32 in the fifth frame FT is equal to that of the second frame FT. The liquid crystal voltage VLC of each pixel corresponding to each liquid crystal capacity 22 of the second display region 32 in the fifth frame FT is assumed to be equal to the liquid crystal voltage VLC of each pixel corresponding to each liquid crystal capacity 22 of the second display region 32 in the fourth frame FT (fixed from the fourth frame FT). The operation with regard to a second display region 32 in a sixth frame FT (not shown) is equal to that of the third frame FT. The operation with regard to a second display region 32 in a seventh frame FT (not shown) is equal to that of the first frame FT. And, the operations on and after an eighth frame FT (not shown) are also similar to those of the above-mentioned frames FT. In the above-mentioned embodiment, the second display region 32 is driven in the fourth frame FT after the first frame FT. Therefore, the liquid crystal of each pixel of the second display region 32 is driven at the alternating current between the first frame FT and the fourth frame FT. If the liquid crystal of each pixel of the second display region 32 can be driven at the alternating current, the frame FT in which the second display region 32 is driven can be replaced by the above-mentioned frame FT. For example, in Figs. 3A, 3E and 3F, the second display region 32 can be driven in the fourth frame FT and the sixth frame FT after the first frame FT and the third frame FT. According to this manner, in the first and third frames FT, the voltage VS of the display signal sent to the liquid crystal capacity 22 connected through the TFT 20 to the scanning line Gn when the scanning signal VGn is sent to the scanning line Gn is the positive potential (with the opposite common voltage VCOM as the standard). The voltage VS of the display signal sent to the liquid crystal capacity 22 connected through the TFT 20 to the scanning line Gn+1 when the scanning signal VGn+1 is sent to the scanning line Gn+1 is the negative potential (with the opposite common voltage VCOM as the standard). On the contrary, the polarities of the respective voltages VS of the fourth and sixth frames FT are opposite to those of the first and third frames FT. That is, in the fourth frame FT, the voltage VS of the display signal sent to the liquid crystal capacity 22 connected through the TFT 20 to the scanning line Gn when the scanning signal VGn is sent to the scanning line Gn is the negative potential (with the opposite common voltage VCOM as the standard). The voltage VS of the display signal sent to the liquid crystal capacity 22 connected through the TFT 20 to the scanning line Gn+1 when the scanning signal VGn+1 is sent to the scanning line Gn+1 is the positive potential (with the opposite common voltage VCOM as the standard). Thus, From the above-mentioned explanation, the liquid crystals of the respective pixels in the second display regions 32 are driven at the alternating current between the first and third frames FT and between the fourth and sixth frames FT. As mentioned above, in this embodiment, the write periods on and after the scanning signal VGn (VGn, VGn+1 ···) in the second display region 32 are longer (a display rate is lower) than those of Figs. 2E and 2F. Thus, the consumptive power can be reduced correspondingly to it. The write period of the second display region 32 shown in Figs. 3E and 3F is equal to three times that of Figs. 2E and 2F. In the TFT type LCD, the charges accumulated in the liquid crystal capacity 22 are held until a next write timing. Thus, if the low display rate is allowable such as the second display region 32, it can be driven in the write period in which the alternating current drive can be attained, on the basis of the display rate. In the above-mentioned embodiment, as for the voltages VS of the display signals applied to the respective signal lines S1, S2 ··· at the time of the drive of the second display region 32, their amplitudes are set to be equal to each other so that the uniform voltage having the positive and negative polarities are applied to the respective liquid crystal capacities 22 between the respective scanning lines Gn, Gn+1 ···, together with the opposite common voltages VCOM. This is because the respective pixels are made white (or, black or the like) in the same graduation. If the graduation is not severely considered, instead of the above-mentioned case, the voltages VS of the display signals applied to the respective signal lines S1, S2 ··· at the time of the drive of the second display region 32 may be the voltages of the original picture (display) signals which are not always equal to each other in amplitude. In the above-mentioned embodiment, when the second display region 32 is not driven (for example, in the second and third frames FT), the signal voltages VS sent to the TFTs 20 connected to the scan electrodes on and after the scan electrode Gn (Gn, Gn+1 ···) are set to be equal (fixed) to those when the second display region 32 is driven (for example, the first frame FT). Instead, when the second display region 32 is not driven, the potentials of the signal lines S1, S2 ··· can be removed or set at a floating state (a high impedance state) at a timing when they are sent to the second display region 32. That is, it is possible to transiently stop the supply of a power supply to a driver IC for driving the signal lines S1, S2 ··· or mount an on/off switching switch at former stages of the signal lines S1, S2 ···. In the above-mentioned embodiments, it is assumed that the scanning lines Gn, Gn+1 ··· at the time of the drive of the second display region 32 are scanned by using the line sequence scan manner. Instead of this manner, the number of interlaced scanning lines may be plural. Also, on the side of the scanning line, when the second display region 32 is not driven, the potentials corresponding to the scanning lines Gn, Gn+1 ··· may be removed. In the second display region 32, the consumptive power can be further reduced when the voltage VS of the display signal is not changed if possible. In view hereof, if the liquid crystal of each pixel of the second display region 32 is the normally white type, and the voltage equal to or less than the threshold is applied to each pixel, and it is made white, the amplitude can be made further lower than that of the example of Fig. 3A, as shown in Fig. 10A. Moreover, as shown in Fig. 11A, the consumptive power can be further reduced by setting the amplitude of the voltage VS of the display signal at zero, in the second display region 32. Furthermore, as shown in Fig. 12B, the further reduction in the consumptive power can be attained by setting the amplitude of the opposite common voltage VCOM at zero, in the period in which the scanning signals VGn, VGn+1 ··· are not sent to the scanning lines Gn, Gn+1 ··· of the second display region 32. In the embodiment of Figs. 3A~3F, both the first display region 31 and the second display region 32 employ the row line inversion drive for inverting a signal voltage VS of a next row scanning line to any scanning line within one frame screen. Figs. 13A to 13F show another embodiment. In this embodiment, the first display region 31 employs the row line inversion drive, and the second display region 32 employs the frame inversion drive. In this case, each pixel voltage in the first display region 31 is operated similarly to the embodiment of Figs. 3A~3F. However, as for each pixel voltage in the second display region 32, the positive potential (the VCOM standard) is charged in the first frame FT. The TFT is not driven in the second and third frames FT, such as VGn, VGn+1 ···. And, the negative potential (the VCOM standard) is charged in the fourth frame FT. In this way, even the inversion drive operation different for each display region can attain the reduction in the consumptive power. The configuration for inputting the scanning signals VG1, VG2, ···, VGn-1, VGn, VGn+1 ··· to each of a plurality of scanning lines G1, G2, ··· Gn-1, Gn, Gn+1 ···, at the timing shown in Fig. 3 will be described below with reference to Figs. 4, 5. In Figs. 4, 5, symbol 40 denotes a shift register. As shown in Fig. 4, the shift register 40 is connected to all the scanning lines G1, G2, ··· Gn-1, Gn, Gn+1 ··· of the LCD panel 30. As shown in Fig. 5, a shift pulse is inputted from an input 41 to the shift register 40, and its shift pulse is transferred in a direction of an arrow Y1, in response to a shift clock (not shown). That is, the shift register 40 outputs the scanning signals VG1, VG2, ···, VGn-1, VGn, VGn+1 ··· to the respective scanning lines G1, G2, ··· Gn-1, Gn, Gn+1 ··· at a predetermined timing. As shown in Fig. 5, a switch 42 is mounted between the two scanning lines Gn-1, Gn corresponding to a boundary between the first display region 31 and the second display region 32, in the shift register 40. When the switch 42 is turned off, the shift pulse transferred in the direction of the arrow Y1 from the input 41 is not transferred on and after the scanning lines Gn, Gn+1 ···. A controller (not shown) is mounted in the shift register 40. This controller counts the predetermined timings (shift clocks), and detects the number of frames FT at this time (which number of frame FT) in accordance with the count result. In the example shown in Fig. 3, the controller turns the switch 42 on, in the first and fourth frames FT. Thus, the scanning signals VG1, VG2, ···, VGn-1, VGn, VGn+1 ··· are outputted to each of all the scanning lines G1, G2, ··· Gn-1, Gn, Gn+1 ··· at a predetermined timing. The controller turns the switch 42 off, in the second and third frames FT. Hence, the scanning signals VG1, VG2, ···, VGn-1 are outputted to each of the scanning lines G1, G2, ··· Gn-1 at a predetermined timing. The scanning signals VGn, VGn+1··· are not outputted to each of the scanning lines Gn, Gn+1 ···. The case in which the second display region 32 is driven in the usual write period and the first display region 31 is driven in the write period longer than that of the second display region 32 will be described below. As shown in Fig. 5, a second input 43 is mounted at a position corresponding to the scanning line Gn, in the shift register 40. The controller receives a shift pulse from the second input 43, when it does not drive the first display region 31, in accordance with the count result. Its shift pulse is transferred in the direction of the arrow Y1 to thereby drive only the second display region 32. The controller receives a shift pulse from the input 41, when driving the first display region 31, in accordance with the count result. Its shift pulse is transferred in the direction of the arrow Y1 to thereby drive the first and second display regions 31, 32. The variation in this embodiment will be described below with reference to Figs. 6, 7. In Figs. 1A, 4, the LCD panel 30 is divided into the first display region 31 and the second display region 32. Instead of this division, the LCD panel 30 can be divided into a first display region 31, a second display region 32 and a third display region 33, as shown in Fig. 6. Fig. 7 shows a shift register 50 for driving the LCD panel 30 shown in Fig. 6. A switch 52 and a switch 53 are mounted in the shift register 50, in addition to the switch 42. The switch 52 is mounted between two scanning lines Gm-1, Gm corresponding to a boundary between the second display region 32 and the third display region 33. And, the switch 53 is mounted between two scanning lines Gn-1, Gm. When the switch 52 is turned off, the shift pulse transferred in the direction of the arrow Y1 from the input 41 is not transferred on and after the scanning lines Gm, Gm+1 ···. When the switch 42 is turned off and the switch 53 is turned on, the shift pulse transferred in the direction of the arrow Y1 from the input 41 is not transferred to the scanning lines Gn, Gn+1 ···, Gm-1. When the switch 42 and the switch 53 are turned off, the shift pulse transferred in the direction of the arrow Y1 from the input 41 is not transferred to the scanning lines Gn, Gn+1···. A third input 54 is mounted in the shift register 50, in addition to the input 41 and the second input 43. The controller mounted in the shift register 50 receives the shift pulse from any of the input 41, the second input 43 and the third input 54, in accordance with the count result. By the way, in Figs. 4 and 6, the output of the shift register or the AND circuit and directly connected to the LCD panel. However, an amplifying circuit or a voltage level converting circuit may be mounted at the output of the shift register or the AND circuit, in order to sufficiently drive the TFT. The following case may be considered as a case that only the second display region 32 among the first, second and third display regions 31, 32 and 33 are driven at the usual write period, and the first and third display regions 31, 33 are driven at the write periods longer than that of the second display region 32. This is the case if a record medium such as a television broadcast, a movie or the like is reproduced, a difference of an aspect ratio on a screen (4:3 and 16:9) and the like cause black portions to be induced in a top and a bottom of the screen, and a dynamic picture can-not be displayed on the black portions. This embodiment is not limited to the above-mentioned portable electronic apparatus, and it can be applied to various displays including television. In the above-mentioned explanations, the case that the picture of the second display region 32 is not changed in picture as shown in Figs. 3E and 3F is described (including the case that the entire surface of the second display region 32 is held in its white color). This may be happen instead of the above-mentioned case, a picture corresponding to the lengthened write period (the picture change is slighter as compared with the picture of the first display region 31 based on the usual write period) being displayed on the second display region 32. The above-mentioned embodiments are described with regard to the LCD based on the active matrix drive method using the three-terminal device. However, the present invention is not limited thereto. The present invention can be applied to an apparatus based on a two-terminal device matrix drive method represented by an MIM type. In case of the STN type LCD, because of its driving method, the division into the first and second display regions, in which the write periods are different from each other, causes a write time of each pulse to be longer, in the usual write period. Thus, the consumptive power can not be sufficiently reduced. Moreover, the STN type LCD further requires a circuit for changing a bias voltage. Hence, the circuit configuration becomes complex. In the TFT type LCD of the above-mentioned embodiment, since a gate voltage is not applied to the TFT, its operation is stopped. Thus, the consumptive power can be sufficiently reduced. The TFT type LCD does not require the circuit for changing the bias voltage and the like. Hence, the circuit configuration is simple. According to the present invention, it is possible to reduce the consumptive power.

Claims: Active matrix liquid crystal display apparatus, comprising: a plurality of scanning lines (G) to which a plurality of scanning signals (VG) are inputted, respectively; a plurality of signal lines (S) to which a plurality of display signals (VS) are inputted, respectively; a plurality of pixels each comprising a capacitance section (22) including a liquid crystal, a pixel electrode, and a common electrode (COM) and a switching element (20), at intersections of said plurality of scanning lines (G) and said plurality of signal lines (S) such that the display signal (VS) is written to the capacitance section (22) through the switching element (20) controlled in accordance with the scanning signal using a line sequence drive method; and a display section (30) including said plurality of capacitance sections (22), wherein said display section (30) is divided into a first display region (31) and a second display region (32), by a virtual line parallel to at least one of said plurality of scanning lines (G), and wherein a first portion (VG1~VGn-1) of said plurality of scanning signals (VG) are repeatedly inputted at a first refresh rate, namely every n-th frame, with n being a positive integer, to a first group of the scanning lines (G1~Gn-1) corresponding to said first display region (31), characterized by a shift register (40, 50) for supplying said plurality of scanning signals (VG) to said plurality of scanning lines (G) by transferring an input signal one by one, and wherein said shift register (40, 50) has a switch (42), which is mounted between the two scanning lines (Gn-1, Gn) corresponding to the boundary between the first and second display regions (31, 32) and is controlled by a controller, for enabling, when periodically closed every m-th frame, with m being an integer greater than n, the transfer of the input signal from the shift register circuit corresponding to the last scanning line (Gn-1) of the first display region (31) to the shift register circuit corresponding to the first scanning line (Gn) of the second display region (32), in order to output a second portion (VGn, VGn+1, ...) of said scanning signals (VG) only every m-th frame to each of a second group of said scanning lines (Gn, Gn+1, ...) corresponding to said second display region (32), and for stopping said transfer when periodically opened in any other frame in order to stop output of the second scanning signals (VGn, VGn+1, ...) to each of said second group of scanning lines (Gn, Gn+1,...), such that said second portion (VGn, VGn+1,...) of said plurality of scanning signals (VG) are repeatedly inputted at a second refresh rate lower than said first refresh rate to said second group of the scanning lines (Gn, Gn+1···). The display apparatus according to Claim 1, wherein said first refresh rate is selected such that said plurality of capacitance sections (22) of said first display region (31) are driven at alternating currents, and wherein said second refresh rate is selected such that said plurality of capacitance sections (22) of said second display region (32) are driven at alternating currents. The display apparatus according to Claim 1 or 2, wherein during a refresh frame period of the second display region (32), the display signals (VS) inputted to the capacitance sections (22) of said second display region (32) have amplitudes substantially identical with each other. The display apparatus according to any one of Claims 1 to 3, wherein in frames other than said every m-th frame, specific display signals (VS) having amplitudes substantially identical with the amplitudes of the display signals (VS) inputted to the capacitance sections (22) of said second display region (32) in said every m-th frame are outputted to said plurality of signal lines (S) at the same timings as within said every m-th frame. The display apparatus according to Claim 4, wherein the amplitudes of said specific display signals (VS) are substantially zero. The display apparatus according to any one of Claims 1 to 4, wherein in frames other than said every m-th frame, potentials of said signal lines (5) are dropped at the same timings as within said every m-th frame. The display apparatus according to any one of Claims 1 to 4, wherein in frames other than said every m-th frame, said signal lines (S) are in floating states at the same timings as within said every m-th frame. The display apparatus according to any one of Claims 1 to 7, wherein in other than said every m-th frame, potentials of said second group of the scanning linens (Gn, Gn+1···) are dropped at the same timings as within said every m-th frame. The display apparatus according to any one of Claims 1 to 8, further comprising: a first shift register supplying said first portion (VG1~VGn-1) of said plurality of scanning signals (VG) to said first group of the scanning lines (G1~Gn-1) by transferring a first input signal one by one; and a second shift register supplying said second portion (VGn, VGn+1, ...) of said plurality of scanning signals (VG) to said second group of the scanning lines (Gn, Gn+1 ···) by transferring a second input signal one by one. The display apparatus according to Claim 1, wherein said input signal is transferred in a predetermined direction (Y1) in said shift register (40), and wherein a first input section (41) inputting said input signal is provided in the most upstream in said predetermined direction (Y1) of said first group of the scanning lines (G1~Gn-1) in said shift register (40), and wherein a second input section (43) inputting said input signal is provided in the most upstream in said predetermined direction (Y1) of said second group of the scanning lines (Gn, Gn+1···) in said shift register (40). The display apparatus according to Claim 1 or 10, wherein each of first and second intervals of said first and second refresh rates corresponds to a multiple of a period (FT) of a frame when a single image is displayed in said display section (30), and wherein said display apparatus further comprises: a control section detecting the number of said frames to switch between an ON state and an OFF state of said switch (42) based on the detected result. The display apparatus according to any one of Claims 1 to 11, wherein said switching element (20) is one of a TFT (Thin-Film-Transistor) type and an MIM (Metal-Insulator-Metal) type. The display apparatus according to any one of Claims 1 to 12, wherein said display apparatus is provided on a single substrate. A driving method of an active matrix liquid crystal display apparatus, comprising: (a) providing a plurality of scanning lines (G) to which a plurality of scanning signals (VG) are inputted, respectively; (b) providing a plurality of signal lines (S) to which a plurality of display signals (VS) are inputted, respectively; (c) providing a plurality of pixels each comprising a capacitance section (22) including a liquid crystal, a pixel electrode, and a common electrode (COM), and a switching element (20), at intersections of said plurality of scanning lines (G) and said plurality of signal lines (S) such that the display signal (VS) is written to the capacitance section (22) through the switching element (20) controlled in accordance with the scanning signal using a line sequence drive method; (d) providing a display section (30) including said plurality of capacitance sections (22); (e) dividing said display section (30) into first and second display regions (31, 32) by a virtual line parallel to at least one of said plurality of scanning lines (G); (f) repeatedly inputting a first portion (VG1~VGn-1) of said plurality of scanning signals at a first refresh rate, namely every n-th frame, with n being a positive integer, to a first group of the scanning lines (G1~Gn-1) corresponding to said first display region (31); characterized by (g) providing a shift register (40, 50) for supplying said plurality of scanning signals (VG) to said plurality of scanning lines (G) by transferring an input signal one by one, providing a switch (42) mounted in said shift register (40, 50) between the two scanning lines (Gn-1, Gn) corresponding to the boundary between the first and second display regions (31, 32) and controlling said switch (42), for enabling, when periodically closed every m-th frame, with m being an integer greater than n, the transfer of the input signal from the shift register circuit corresponding to the last scanning line (Gn-1) of the first display region (31) to the shift register circuit corresponding to the first scanning line (Gn) of the second display region (32), in order to output a second portion (VGn, VGn+1, ...) of said scanning signals (VG) only every m-th frame to each of a second group of said scanning lines (Gn, Gn+1, ...) corresponding to said second display region (32), and for stopping said transfer when periodically opened in any other frame in order to stop output of the second scanning signals (VGn, VGn+1, ...) to each of said second group of scanning lines (Gn, Gn+1,...), thereby repeatedly inputting said second portion (VGn, VGn+1, ...) of said plurality of scanning signals at a second refresh rate lower than said first refresh rate to said second group of the scanning lines (Gn, Gn+1···). A driving method of a display apparatus according to Claim 14, wherein said first refresh rate is selected such that said plurality of capacitance sections (22) of said first display region (31) are driven at alternating currents, and wherein said second refresh rate is selected such that said plurality of capacitance sections (22) of said second display region (32) are driven at alternating currents. A driving method of a display apparatus according to Claim 14 or 15, wherein in said every m-th frame, said display signals (VS) inputted to said plurality of capacitance sections (22) of said second display region (32) have amplitudes substantially identical with each other. A driving method of a display apparatus according to any one of Claims 14 to 16, wherein in frames other than said every m-th frame, specific display signals (VS) having amplitudes substantially identical with the amplitudes of said display signals (VS) inputted to the capacitance sections (22) of said second display region (32) in said every m-th frame are outputted to said plurality of signal lines (S) at the same timings as within said every m-th frame.

Inventors: MORIYAMA HIROAKI, MORIYAMA, HIROAKI
Applicants: NEC LCD TECHNOLOGIES LTD, NEC LCD TECHNOLOGIES, LTD.
Application year: 2001
Main classification: G09G3
IPC codes: G09G3, G09F9, G02F1