Differential amplifier, semiconductor device, power supply circuit and electronic equipment using the same

Abstract: A differential amplifier comprises first and second differential amplifier circuits. The first differential amplifier circuit includes a first N-type transistor and a second N-type transistor for constituting a differential pair, and operates based on a first input voltage (V IN1 ). The second differential amplifier circuit includes a first P-type transistor and a second P-type transistor making up a differential pair, and operates based on a second input voltage (V IN2 ). There is also provided a third P-type transistor operable based on a first signal (S 1 ) coming from the first differential amplifier circuit and a third N-type transistor operable based on a second signal (S2) from the second differential amplifier circuit, wherein a voltage between these third P- and N-type transistors becomes an output voltage (V OUT ). The differential amplifier further comprises a first voltage control circuit which includes a fourth N-type transistor which rapidly changes the gate voltage of the third P-type transistor based on a third signal (S 3 ) from the second differential amplifier circuit. There is also provided a second voltage control circuit which includes a fourth P-type transistor which early changes the gate voltage of the third N-type transistor based on a fourth signal (S 4 ) from the first differential amplifier circuit.

Description: BACKGROUND OF THE INVENTION Field of the Invention The present invention relates to a differential amplifier having two sets of differential amplifier circuits, a semiconductor device, a power supply circuit, and electronic equipment using the same. Description of Related Art One prior known differential amplifier is shown in Fig. 8, which device has two, first and second differential amplifier circuits 210, 230. The first and second differential amplifier circuits 210, 230 are designed to receive first and second input voltages V IN1 , V IN2 which have an offset therebetween. A P-type MOS transistor 250 is provided at the rear stage of the first differential amplifier circuit 210, which transistor is driven by a first signal S 1 coming from the first differential amplifier circuit 210. Similarly, an N-type MOS transistor 252 is provided at the rear stage of the second differential amplifier circuit 230, which transistor is driven by a second signal S 2 from the second differential amplifier circuit 230. These PMOS transistor 250 and NMOS transistor 252 are operable to pull together thus defining an output voltage V OUT . As shown in Fig. 8 the first differential amplifier circuit 210 includes a P-type MOS transistor 212 and a P-type MOS transistor 214 that constitutes a current-mirror circuit together with the PMOS transistor 212. The second differential amplifier circuit 230 includes an N-type MOS transistor 232 and an N-type MOS transistor 234 that makes up a current-mirror circuit together with the NMOS transistor 232. The first differential amplifier circuit 210 further has an NMOS transistor 216 that is serially connected to the PMOS transistor 212 between power supply voltages V DD , V SS , and an NMOS transistor 218 as connected in series to the PMOS transistor 214 between the power supply voltages V DD , V SS . Additionally the NMOS transistors 216, 218 are coupled through a constant current source 220 to the power supply voltage V SS . These NMOS transistors 216, 218 are the same as each other both in size and in ability, and thus constitute a differential pair. Similarly the second differential amplifier circuit 230 has a PMOS transistor 236 that is serially connected to the NMOS transistor 232 between the power supply voltages V DD , V SS and a PMOS transistor 238 as series-connected to the NMOS transistor 234 between power supply voltages V DD , V SS . The PMOS transistors 236, 238 are coupled to power supply voltage V DD via a constant current source 240. These PMOS transistors 236, 238 are the same in size and ability as each other, thus making up a differential pair. Here, the approach to stabilizing the output voltage V OUT shown in Fig. 8 at a specified potential level typically includes two cases: increasing the output voltage V OUT from a certain potential level lower than the target voltage to be stabilized, and reducing the output voltage V OUT from a potential level higher than the stabilization voltage. In the former case, it is required to let a more significant current flow at the PMOS transistor 250 of Fig. 8 while at the same time causing a less current to flow in the NMOS transistor 252. In the latter case the reversed operation thereof is required to be done. Unfortunately the prior art is encountered with a problem that in the process of the output voltage V OUT 's becoming potentially stable, the PMOS transistor 250 and NMOS transistor 252 are low in speed of potential rise-up or drop-down of gate voltages thereof, which in turn makes slow or "decelerates" any intended changes in currents flowing in the PMOS transistor 250 and NMOS transistor 252. A differential amplifier according to the pre-characterizing portion of claim 1 is known from JP-A-11-088076 and intended to rapidly provide a rising or falling output signal of an operational amplifier without increasing consumption current. SUMMARY OF THE INVENTION It is an objective of the present invention to provide a differential amplifier, a semiconductor device and power supply circuit capable of operating for letting an output voltage rapidly approach its stable state, and also electronic equipment using the same. This objective is achieved by a differential amplifier as claimed in claim 1, a semiconductor device and power supply circuit as claimed in claims 7 and 8, and an electronic equipment as claimed in claim 9. Preferred embodiments of the invention are subject-matter of the dependent claims. The claimed structure makes it possible to permit acceleration of an operation of the third transistor of the secondary conductivity type, enabling the output voltage to rapidly shift to its stable state. With the first capacitor and the second capacitor which prevent oscillation of the output voltage and the first and the second resistors that prevent static electricity this arrangement is effective. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a schematic circuit diagram showing a circuit configuration of a differential amplifier in accordance with a first embodiment of the present invention. Fig. 2 is a detailed circuit diagram of the differential amplifier shown in Fig. 1. Fig. 3 illustrates an output voltage V OUT of the differential amplifier of Fig. 2. Fig. 4 is a waveform chart showing a process of stabilization of V OUT of the differential amplifier of Fig. 2. Fig. 5 schematically shows a liquid crystal display in accordance with a second embodiment of the present invention. Fig. 6 is a waveform chart showing drive waveforms of the liquid crystal display of Fig. 5. Fig. 7 is a circuit diagram of a power supply circuit for use in the liquid crystal display of Fig. 5. Fig. 8 is a circuit diagram of a conventional differential amplifier. DETAILED DESCRIPTION OF THE EMBODIMENTS The embodiments of the present invention will now be described in detail with reference to the accompanying drawings. 1. First Embodiment An arrangement and operation of the differential amplifier in accordance with one embodiment of the present invention will be described with reference to Figs. 1 to 4. 1.1 Arrangement of Differential Amplifier Referring to Fig. 1, there is shown a circuit configuration of the differential amplifier in accordance with this embodiment. This differential amplifier shown herein has a first differential amplifier circuit 10 of the voltage follower type which is operable based on a first input voltage V IN1 and a second differential amplifier circuit 30 of the voltage follower type operable based on a second input voltage V IN2 . As shown in Fig. 2 the first differential amplifier circuit 10 includes a P-type MOS transistor 12 and a P-type MOS transistor 14 that constitutes a current mirror circuit together with the P-type MOS transistor 12. These PMOS transistors 12, 14 are the same both in size and in ability as each other, thus making up a current mirror circuit. The second differential amplifier circuit 30 includes an N-type MOS transistor 32 and an N-type MOS transistor 34 that makes up a current mirror circuit together with the N-type MOS transistor 32. These NMOS transistors 32, 34 also are the same in size and ability as each other to thereby make up a current mirror circuit. The first differential amplifier circuit 10 further has a MOS transistor 16 of the primary conductivity type that is for example N type (first transistor of the primary conductivity type) which is serially connected to the PMOS transistor 12 between power supply voltages V DD , V SS , and an N-type MOS transistor 18 (second transistor of the primary conductivity type) which is connected in series to the PMOS transistor 14 between the power supply voltages V DD , V SS . Note here that these NMOS transistors 16, 18 are connected through a constant current source 20 to the power supply voltage V SS . These NMOS transistors 16, 18 are the same in size and ability as each other so that these make up a differential pair. Similarly the second differential amplifier circuit 30 has a MOS transistor 36 of the secondary conductivity type that is for example P type (first transistor of the secondary conductivity type) as serially connected to the NMOS transistor 32 between the power supply voltages V DD , V SS , and a P-type MOS transistor 38 (second transistor of the secondary conductivity type) which is series-connected to the N-type MOS transistor 34 between the power supply voltages V DD , V SS . Note that the PMOS transistors 36, 38 are connected via a constant current source 40 to the power supply voltage V DD . These PMOS transistors 36, 38 are the same in size and ability as each other so that they make up a differential pair. As shown in Figs. 1 and 2, there are provided a P-type MOS transistor (third transistor of the secondary conductivity type) 50 operable based on a first signal S 1 from the first differential amplifier circuit 10 and an N-type MOS transistor (third transistor of the primary conductivity type) 52 operable based on a second signal S 2 from the second differential amplifier circuit 30. These PMOS transistor 50 and NMOS transistor 52 are serially connected together between the power supply voltages V DD , V SS whereby a voltage between the PMOS transistor 50 and NMOS transistor 52 becomes an output voltage V OUT of the illustrative differential amplifier. Note that the PMOS transistor 50 is formed to have a large size in view of the fact that its load is significant when the output voltage V OUT potentially drops down, resulting in an increase in gate capacitance thereof. Also note that as shown in Fig. 2, the first and second differential amplifier circuits 10, 30 are provided with oscillation preventing capacitors C 1 , C 2 and static electricity preventing resistors R 1 , R 2 . The first differential amplifier circuit 10 has a first voltage control circuit 60 which includes an N-type MOS transistor (fourth transistor of the primary conductivity type) 62 as provided in parallel to the constant current source 20. This NMOS transistor 62 has its gate to which a third signal S 3 from the second differential amplifier circuit 30 is input. As a result, an operation of the first voltage control circuit 60 for controlling the first signal S 1 leads to achievement of control of the gate voltage of the PMOS transistor 50. Similarly the second differential amplifier circuit 30 has a second voltage control circuit 70 which includes a P-type MOS transistor (fourth transistor of the secondary conductivity type) 72 as provided in parallel to the constant current source 40. This PMOS transistor 72 has a gate to which a fourth signal S 4 from the first differential amplifier circuit 10 is input. As a result, an operation of the second voltage control circuit 70 to control the second signal S 2 leads to achievement of control of the gate voltage of NMOS transistor 52. It should be noted that the NMOS transistor 62 and PMOS transistor 72 are set in the turn-off state while the output voltage V OUT of the differential amplifier is stable, causing any current to hardly flow therein. 1.2 Operation of Differential Amplifier The output voltage V OUT of the differential amplifier operable based on the first and second input voltages V IN1 , V IN2 is such that as shown in Fig. 3, it is potentially stabilized at an intermediate voltage potential level (V IN1 -V IN2 )/2 in the stable state or alternatively becomes a voltage potentially variable between the voltage V IN1 and voltage V IN2 with its intermediate voltage being as a boundary. The differential amplifier of the embodiment is capable of rapidly setting the output voltage V OUT at a voltage of the stable state. Its operation will be described below respectively in a case of rapidly increasing the output voltage V OUT and a case of reducing the output voltage toward the stable state. (1) Letting Output Voltage V OUT Rapidly Rise Up Toward Stable State Voltage As shown in Fig. 4, suppose that a voltage in the stable state is V 1 . Assume that prior to a timing "t o ," an output line of the output voltage V OUT is electrically short-circuited to another voltage line(s) by way of example, resulting in that it is lower than the voltage V 1 . In this case the gate voltages of the NMOS transistor 18 and PMOS transistor 38 become lower than their inherent stable state voltages. Note here that since in the first differential amplifier circuit 10 a constant current flows at the constant current source 20 while the NMOS transistor 18 decreases in its gate voltage, a current I 18 flowing in the NMOS transistor 18 decreases resulting in a current I 16 increasing accordingly. Due to this, in the first differential amplifier circuit 10, such increase of current I 16 results in a likewise decrease in gate voltage S 1 of the PMOS transistor 50, thereby causing a change for letting a more current flow at the PMOS transistor 50. On the contrary, in the second differential amplifier circuit 30, a constant current flows at the constant current source 40 with the PMOS transistors 36, 38 making up the differential pair; accordingly, currents I 36 , I 38 flowing in PMOS transistors 36, 38 are such that I 36 + I 38 = constant. And, in view of the fact that the PMOS transistor 38 decreases in its gate voltage in the way stated supra, the current I 38 flowing in the PMOS transistor 38 increases resulting in the current I 36 decreasing by a degree corresponding to such current increase. Due to this, at the second differential amplifier circuit 30, such decrease of current I 36 results in a likewise decrease in gate potential of the NMOS transistor 52, causing a change for letting a less current flow in NMOS transistor 52. In this way, as a result of the flow of a more current at the PMOS transistor 50 while at the same time letting a less current flow in the NMOS transistor 52, these PMOS transistor 50 and NMOS transistor 52 operate to push and pull each other causing the output voltage V OUT of the push-pull type differential amplifier to potentially go high toward the stable voltage V 1 of Fig. 4. The process of the output voltage V OUT 's potential riseup as explained above is a change as indicated by thin line 80 in Fig. 4, which calls for a relatively long time period of time (t 3 - t 0 ). The reason of this is that with the above-stated operation only, the PMOS transistor 50 and NMOS transistor 52 stay slow in potential riseup or dropdown of gate voltages thereof, resulting in that any available changes in currents flowing at PMOS transistor 50 and NMOS transistor 52 stay slow. More specifically, the gate voltage of the PMOS transistor 50 is given as a voltage that is charged at the oscillation preventing capacitor C 1 and a gate capacitance of the PMOS transistor 50 and also the parasitic lead capacitance of a gate line L 1 shown in Fig. 2. Its charge-up time is determinable by the gate line L 1 's lead capacitance and the ability of constant current source 20. Similarly the gate voltage of the NMOS transistor 52 is represented by a voltage that is charged up at the oscillation prevention capacitor C 2 and a gate capacitance of the NMOS transistor 52 plus the parasitic lead capacitance of a gate line L 2 as shown in Fig. 2. Its charge time is determinable by the gate line L 2 's lead capacitance and the ability of constant current source 40. Then, with the illustrative embodiment, the first and second voltage control circuits 60, 70 are used to cause the PMOS transistor 50 and NMOS transistor 52 to rapidly change in gate voltages thereof. More specifically, in the second differential amplifier circuit 30, a decrease in current I 36 results in a likewise decrease in voltage of the third signal S 3 (this voltage is equal to a voltage on the gate line L 2 of NMOS transistor 52). As a result, the gate voltage of the NMOS transistor 62 as provided in the first differential amplifier circuit 10 gets lower causing a current I 62 flowing in NMOS transistor 62 to decrease accordingly. At this time an operation of the PMOS transistor 50 will be determined by such current flowing in the constant current source 20. On the other hand, in the first differential amplifier circuit 10, the gate line L 1 goes low in potential resulting in a decrease in voltage of the fourth signal S 4 , which is equal to the voltage on the gate line L 1 . This would result in a decrease in gate voltage of the PMOS transistor 72 as provided in the second differential amplifier circuit 30 causing a current I 72 flowing in PMOS transistor 72 to increase accordingly. Thus a current flowing in the differential pair and current mirror of the second differential amplifier circuit 30 becomes greater. At this time an operation of the NMOS transistor 52 is accelerated because of the fact that the current I 72 of PMOS transistor 72 is added to the constant current source 40 although the total value of capacitance components parasitically associated with the gate line L 2 is kept unchanged. The process of potential riseup of the output voltage V OUT based on this additional operation is indicated by solid line 82 in Fig. 4. As shown in Fig. 4, with this embodiment, it is possible to shorten a time as taken to reach the intended stable state at (t 2 -t 0 ) due to an increase in riseup rate of the output voltage V OUT at the timing t 1 whereat the NMOS transistor 72 turns on, thereby enabling the output voltage V OUT to rapidly become stabled at increased speeds. (2) Letting Output Voltage V OUT Rapidly Drop Down To Stable State Voltage In this case the gate voltages of the NMOS transistor 18 and PMOS transistor 38 become higher than their inherent stable state voltages. Accordingly the current I 18 flowing in the NMOS transistor 18 increases with an increase in its gate voltage whereas the current I 16 flowing in the NMOS transistor 16 decreases by a degree corresponding thereto. Due to this, in the first differential amplifier circuit 10, such reduction of the current I 16 results in an increase in gate potential of the PMOS transistor 50, thus causing a less current to flow at the PMOS transistor 50. On the other hand, in the second differential amplifier circuit 30, the current I 38 flowing in the PMOS transistor 38 decreases with an increase in gate voltage thereof, causing the current I 36 flowing in PMOS transistor 36 to increase by a degree corresponding thereto. Due to this, at the second differential amplifier circuit 30, an increase in current I 36 results in an increase in gate potential of the NMOS transistor 52 causing a more current to flow in NMOS transistor 52. Furthermore, in the first differential amplifier circuit 10, the decrease of current I 16 results in the fourth signal S 4 going high in potential, which is equal to the voltage on the gate line L 1 . As a result the PMOS transistor 72 as provided in the second differential amplifier circuit 30 potentially increases in gate voltage causing the current I 72 flowing in PMOS transistor 72 to decrease accordingly. At this time an operation of the NMOS transistor 52 is to be determined by a current of the constant current source 40. On the other hand, in the second differential amplifier circuit 30, the voltage on the gate line L 2 of NMOS transistor 52 potentially goes high causing the third signal S 3 to likewise increase (this voltage is equal to the voltage on gate line L 2 of NMOS transistor 52). As a result the NMOS transistor 62 as provided in the first differential amplifier circuit 10 gets higher in gate voltage resulting in an increase in current I 62 flowing in NMOS transistor 62. Consequently a current flowing through the differential pair and current mirror circuit of the first differential amplifier circuit 10 increases. This finally serves to accelerate the operation of PMOS transistor 50 because of the fact that the current I 62 flowing in NMOS transistor 62 is added to the current of the constant current source 20 although the total value of capacitances parasitically associated with the gate line L 1 remains unchanged. In this way, as a result of the flow of a less current at the PMOS transistor 50 while simultaneously allowing a more current to flow in the NMOS transistor 52, these PMOS transistor 50 and NMOS transistor 52 pull up together forcing the output voltage V OUT to potentially go low toward the intended stable voltage. It must be noted that one possible reason for slow down of the stabilization of the output voltage V OUT is the presence of the oscillation prevention capacitors C 1 , C 2 shown in Fig. 2. Thus, the above-stated measures can be done for differential amplifier circuitry with capacitors of this type added thereto. If one of the first and second differential amplifier circuits 10 and 30 has no capacitor such an oscillation preventing capacitor, it will not always necessary to implement these measures for the differential amplifier circuit with no such capacitors. As a consequence, there must be a case where only one of the first and second differential amplifier circuits 60, 70 is disposed. 2. Second Embodiment The description will next be given of a power supply circuit of a liquid crystal display device in accordance with a second embodiment of the present invention with reference to Figs. 5 to 7 also. 2.1 Arrangement and Operation of Liquid Crystal Display Device Fig. 5 shows a configuration of main part of the liquid crystal display device. In Fig. 5, a liquid crystal display unit, e.g. simple matrix type liquid crystal display unit 100, is arranged to include a first substrate with common electrodes C o to C m formed thereon, a second substrate with segment electrodes S o to S n formed thereon, and a layer of liquid crystal material as sealed and interposed between the first and second substrates. A single one of the common electrodes and one of the segment electrodes cross over each other at an intersection, which becomes a pixel. The liquid crystal display unit 100 has (m + 1) × (n + 1) pixels. Note that the liquid crystal display device in accordance with the second embodiment may also employ other liquid crystal display units such as an active-matrix liquid crystal display device or else in place of the simple-matrix liquid crystal display unit 100. The common electrodes C o to C m are connected with a common driver 102 whereas the segment electrodes S o to S n are with a segment driver 104. These common driver 102 and segment driver 104 receive specified voltages as supplied from a power supply circuit 106 for selectively supplying, based on signals from a drive control circuit 108, such specified voltages to the common electrodes C o to C m or segment electrodes S o to S n . Here, there is shown in Fig. 6 one example of drive waveforms within a frame period for selection of a common electrode C 3 of the liquid crystal display unit 100 shown in Fig. 5. In Fig. 6, thick or "fat" line is used to designate a drive waveform as supplied from the common driver 102 to respective common electrodes C o to C m whereas thin line indicates a drive waveform being supplied from the segment driver 104 to a respective one of the segment electrodes S o to S n . As shown in Fig. 6 the drive waveform as supplied from the common driver 102 changes among voltages V 0 , V 1 , V 4 and V 5 . On the other hand the drive waveform supplied from the segment driver 104 varies among voltages V 0 , V 2 , V 3 and V 5 . 2.2 Arrangement of Power Supply Circuit Fig. 7 shows details of the power supply circuit 106 shown in Fig. 5. As shown in Fig. 7, letting any two of switches SW 1 to SW 6 turn on makes it possible to select one of the voltages V 0 , V 1 , V 4 , V 5 being supplied to the common driver 102 and one of the voltages V 0 , V 2 , V 3 , V 5 as supplied to the segment driver 104. Here, the power supply voltage V DD is used as the voltage V 5 ; power supply voltage V SS is used as the voltage V 0 ; and, the voltages V 4 to V 1 are generated by resistive voltage division of a voltage (V 5 - V 0 ). To this end, the power supply circuit 106 has a resistance type potential divider circuit 110 and four separate differential amplifiers 120, 122, 124, 126. The four differential amplifiers 120-126 receive first and second input voltages V IN1 , V IN2 as input thereto via the resistance divider circuit 110 respectively and then output as their output voltages respective one of V 4 , V 3 , V 2 and V 1 . And these four differential amplifiers 120 to 126 each have the arrangement of Fig. 2. Additionally the power supply circuit 106 shown in Fig. 7 is configurable as a discrete or "stand-alone" component or, alternatively, into the form of a one-chip IC with the common driver 102 and segment driver 104 shown in Fig. 5 being integrated together. 2.3 Operation of Power Supply Circuit The operation of the differential amplifier as has been explained previously by using Figs. 2 and 4 is directly applied to an operation of the differential amplifier 126 shown in Fig. 7 with the voltage V 1 being as its output voltage V OUT , which leads to improvements in waveform at part "A" shown in Fig. 6. More specifically, when the switch SW 3 of Fig. 7 turns on, an output line of the differential amplifier 126 is electrically shorted via the common driver 102 to the common electrode C 3 of the liquid crystal display unit 100. At this time a voltage of the common electrode has been the voltage V 5 due to polarity inversion driving as shown in Fig. 6, such shorting results in the output voltage V OUT of differential amplifier 126 potentially dropping down below the voltage V 1 . In order to permit this output voltage V OUT to rapidly become stable in such a way as to follow or "trace" its riseup process indicated by fat line 182 in Fig. 4, the first and second voltage control circuits 60, 70 of Fig. 2 will be rendered operative. Here, the waveform of the part "A" of Fig. 6 becomes rounded upon influence of parasitic capacitance components of the common electrodes also. This waveform rounding at the part "A" causes contrast reduction and so-called "stringiness" phenomena to appreciably increase at the liquid crystal display unit 100: these problems become more serious with a decrease in length of a selection time period T SEC of Fig. 6. The greater the pixel number, the shorter the selection period T SEC , causing the image quality degradation that is more serious in high-precision display units. As in the illustrative embodiment, onscreen display images may be improved in quality by reducing or suppressing any possible waveform rounding at voltage change points such as the part "A" shown in Fig. 6 or the like. Here, the differential amplifiers 120 to 126 are such that in case stabilization is established after letting the output-voltage V OUT of each device have increased in potential, it is effective to cause the NMOS transistor 62 of the first voltage control circuit 60 to turn on to thereby quickly make higher the gate voltage of PMOS transistor 50 for acceleration of the operation thereof. Adversely the differential amplifiers 120 to 126 are such that in case stabilization is done after letting the output voltage V OUT of each device have dropped down in potential, it is effective to lessen the current I 72 flowing in the PMOS transistor 72 of the second voltage control circuit 70 to thereby rapidly make higher the gate voltage of NMOS transistor 52 for acceleration of its operation. Incidentally it is apparent by referring to Fig. 6 that arrival at the voltage V 1 takes place only when rising up from the voltage V 4 or V 5 and also that arrival at the voltage V 4 occurs only when dropping down from the voltage V 0 or V 1 . It can also be seen that arrival at voltage V 2 occurs with increased frequency when dropping down from the voltage V 0 whereas arrival at voltage V 3 occurs in most cases when rising up from voltage V 5 . Accordingly the differential amplifiers 120, 124 of Fig. 7 that output the voltages V 4 , V 2 will not always require the use of the first voltage control circuit 60 and may be designed to have the second voltage control circuit 70 alone. On the other hand the differential amplifiers 122, 126 of Fig. 7 for outputting the voltages V 3 , V 1 will not always require the use of the second voltage control circuit 70 and may be modified to have the first voltage control circuit 60 only. Additionally the above-described differential amplifiers and power supply circuit are applicable not only to various items of electronic equipment including liquid crystal display devices such as portable telephones, game machines and personal computers, but also applicable to other types of electronic equipment operable upon receipt of stable voltages supplied thereto.

Claims: A differential amplifier comprising: a first differential amplifier circuit which operates based on a first input voltage (V IN1 ) and includes a first transistor (16) of a primary conductivity type and a second transistor (18) of the primary conductivity type which makes up a differential pair with the first transistor (16) of the primary conductivity type; a second differential amplifier circuit which operates based on a second input voltage (V IN2 ) and includes a first transistor of a secondary conductivity type (36) and a second transistor (38) of the secondary conductivity type which makes up a differential pair with the first transistor (36) of the secondary conductivity type; a third transistor (50) of the secondary conductivity type which operates based on a control signal applied from the first differential amplifier circuit; and a third transistor (52) of the primary conductivity type which is serially connected to the third transistor (50) of the secondary conductivity type and operates based on a control signal applied from the second differential amplifier circuit; and a voltage control circuit (60; 70) which controls the voltage of a control terminal of at least one of said third transistors (50, 52), based on a voltage control signal from the other one of said differential amplifier circuits than the one that applies the control signal to that third transistor (50, 52), wherein the voltage between the third transistor (50) of the secondary conductivity type and the third transistor (52) of the primary conductivity type is used as an output voltage, characterized in that: a first capacitor (C1) which prevents oscillation of the output voltage is connected between the control terminal of the third transistor (50) of the secondary conductivity type and the control terminal of the second transistor (18) of the first conductivity type, a first resistor (R1) is connected between the node between the third transistor (50) of the secondary conductivity type and the third transistor (52) of the first conductivity type on the one hand and the control terminal of the second transistor (18) of the first conductivity type on the other hand, a second capacitor (C2) which prevents oscillation of the output voltage is connected between the control terminal of the third transistor (52) of the primary conductivity type and the control terminal of the second transistor (38) of the second conductivity type, and a second resistor (R2) is connected between the node between the third transistor (50) of the secondary conductivity type and the third transistor (52) of the first conductivity type on the one hand and the control terminal of the second transistor (38) of the second conductivity type on the other hand. The differential amplifier as defined in claim 1, wherein the voltage control circuit (60, 70) comprises: a first voltage control circuit (60) which controls the voltage of the control terminal of the third transistor (50) of the secondary conductivity type based on a first voltage control signal from the second differential amplifier circuit, and a second voltage control circuit (70) which controls the voltage of the control terminal of the third transistor (52) of the first conductivity type based on a second voltage control signal from the first differential amplifier circuit. The differential amplifier as defined in claim 1 or 2, wherein the voltage control circuit (60, 70) comprises a first voltage control circuit (60) which controls the voltage of the control terminal of the third transistor (50) of the secondary conductivity type, based on a first voltage control signal from the second differential amplifier circuit and includes a fourth transistor (62) of the primary conductivity type which is connected in parallel with a constant current source (20) of the first differential amplifier circuit; and wherein the first voltage control signal is supplied to the control terminal of the fourth transistor (62) of the primary conductivity type. The differential amplifier as defined in claim 3, wherein the first voltage control signal is identical to the signal which is supplied to a control terminal of the third transistor (52) of the primary conductivity type. The differential amplifier as defined in any one of claims 1 to 4, wherein the voltage control circuit (60, 70) comprises a second voltage control circuit (70) which controls the voltage of the control terminal of the third transistor (52) of the first conductivity type, based on a second voltage control signal from the first differential amplifier circuit and includes a fourth transistor of the secondary conductivity type (72) which is connected in parallel with a constant current source (40) of the second differential amplifier circuit; and wherein the second voltage control signal is supplied to a control terminal of the fourth transistor (72) of the secondary conductivity type. The differential amplifier as defined in claim 5, wherein the second voltage control signal is identical to the signal which is supplied to a control terminal of the third transistor (50) of the secondary conductivity type. A semiconductor device comprising the differential amplifier as defined in any of claims 1 to 6. A power supply circuit comprising the differential amplifier as defined in any of claims 1 to 6. Electronic equipment comprising the power supply circuit as defined in claim 8.

Inventors: TSUCHIYA MASAHIKO, TSUCHIYA, MASAHIKO
Applicants: SEIKO EPSON CORP, SEIKO EPSON CORPORATION
Application year: 2001
Main classification: H03F3
IPC codes: H03F3