A TRACK AND HOLD AMPLIFIER

Abstract: A track and hold amplifier for use in adc-converters comprises in succession an input buffer, a pn-junction switch and a hold capacitor. A feedback is provided between the hold capacitor and the input buffer and means are provided to disable the feedback during the hold mode.

Description: A track and hold amplifier The invention relates to a track and hold amplifier comprising an input buffer for receiving an input signal and for transferring the received input signal to a first terminal of a pn-junction switch a second terminal of which is connected to a hold capacitor, and means to supply a switching signal to said first terminal of the pn-junction switch for translating the buffered input signal through the switching pn-junction to the hold capacitor during a track mode and for blocking this transfer during a hold mode. A track and hold amplifier of this kind is known from the article "A 12-b, 60-Msample/s Cascaded Folding and Interpolating ADC", by P. Norenkamp and R. Roovers in IEEE Journal of Solid State Circuits, Nol 32, No 12, December 1997, Pages 1876-1886. A track and hold amplifier is often used in the input of an analog to digital converter to separate the sampling operation from the quantization operation. Present day multistep AD-architecture has a number of comparators, which do not operate simultaneously. However, it is necessary that all the comparators see the same analog signal value. The function of the track and hold amplifier is to determine the voltage level of the input signal at the sampling instant of the track and hold amplifier, and to maintain this value during a certain time period, so as to ensure that all comparators see the same analog input value. Moreover, each comparator has input capacitance which causes the input signal level to be compared to reach its correct level only after some delay. Therefore, without a track and hold amplifier, the comparator would compare an incorrect signal level, especially at higher signal frequencies. The track and hold amplifier samples the input signal at the correct value and maintains this value during the hold mode, so that the comparator-input has enough time to reach its correct signal level for subsequent quantization. A drawback of the abovementioned prior art track and hold amplifier is that during the track mode larger currents flow into the hold capacitor, especially at higher signal frequencies. These larger currents flow into the holding capacitance through the pn-junction switch. This results in large non linear signal distortion and consequently in incorrect signal sampling. The signal distortion, caused by the pn-junction, may easily reach values of some tens of millivolts, which is too large for modern applications, where the total signal amplitude is not more than 1 Volt. The present invention has for its object to overcome this drawback of the prior art track and hold amplifier and the track and hold amplifier of the present invention is therefore characterized by a feedback connection from the second terminal of the pn-junction switch to the input buffer and means to enable the feedback during the track mode and to disable the feedback during the hold mode. The feedback from the second terminal of the pn- junction switch to the input buffer reduces the signal distortion at this second terminal and shifts the distortion to the first terminal of the pn-junction switch, where it does not harm. However, this feedback has a detrimental effect on the hold feedthrough of the amplifier because the input signal could reach the holding capacitance through this feedback path. Therefore the feedback is disabled during the hold mode. The feedback may for instance be disabled during the hold mode by cutting off the current through the input buffer. This however has inter alia the drawback that the input impedance of the amplifier varies with the track and hold switching signal. A preferred arrangement according to the invention is therefore characterized in that said means to enable the feedback during the track mode and to disable the feedback during the hold mode comprises a second pn-junction switch within said feedback connection and second means to supply the switching signal to the second pn- junction switch. The said second means to supply the switching signal to the second pn- junction switch may cause a large voltage jump on the part of the feedback connection between the input buffer and the second pn-junction switch. This voltage jump may cause interference of the voltage of the hold capacitor through the junction capacitance of the second pn-junction switch. It is a further object of the invention to limit this interference and the track and hold amplifier of the invention may be further characterized by clamping means connected to the part of the feedback connection between the input buffer and the second pn- junction switch. It is another object of the invention to provide a track and hold amplifier which is characterized by resistive means between the second terminal of the first pn-junction switch and the hold capacitor for increasing the stability of the feedback path. These and other aspects of the invention will be further explained with reference to the attached Figures. Herein shows: Figure 1 an embodiment of a track and hold amplifier which is known in the art, Figure 2 a first embodiment of a track and hold amplifier according to the invention and Figure 3 a second embodiment of a track and hold amplifier according to the invention. The prior art track and hold amplifier of Figure 1 comprises an input buffer I B with a first emitter-coupled transistor pair T]-T 2 and a common emitter current source Si. The transistor T 2 has its collector- and base-electrodes interconnected and a collector load current source S 2 . This well known arrangement transfers an input signal voltage N;, applied to the base electrode of transistor to a substantially identical voltage at the base electrode of transistor T 2 , especially when the current of the source Si is twice the current of source S 2 . The output of the input buffer is coupled, through a connection point P to the base electrode of a switching emitter follower transistor T 3 . The emitter electrode of this transistor T 3 is connected to a hold capacitor C H and to the input of an output buffer Oβ. This output buffer comprises a second emitter-coupled transistor pair T 4 -T 5 with a common emitter current source S 3 . The transistor T 5 has its collector- and base-electrodes interconnected and a collector load current source S 4 . Moreover a DC-shift transistor T 6 with interconnected collector and base electrode, is inserted between the collector electrode of transistor T 5 and the current source S 4 . The interconnection between the current source S 4 and the DC-shift transistor T 6 constitutes the output O of the track and hold amplifier. The arrangement further comprises a third emitter-coupled transistor-pair T - T 8 with common emitter-current-source S 5 . The collector-electrode of transistor T is connected to the base-electrode of the emitter follower transistor T 3 and the collector electrode of transistor T 8 is connected to the emitter electrode of transistor T 3 . The base electrodes of the transistors T and T 8 receive a track and hold switching puls T/H which makes the base electrode of the transistor T 8 high and the base electrode of the transistor T 7 low during the track mode and, inversely, the base electrode of transistor T low and that of transistor T high during the hold mode. In operation, during the track mode the current of current source S 5 flows through the transistor T 8 into the emitter electrode of the emitter follower transistor T 3 . Consequently, the signal voltage Nj, which is applied through the input buffer to the base electrode of transistor T 3 , appears at low impedance and one N De junction voltage shift lower at the hold capacitor C H and at the input of the output buffer Oβ. Equally as with the input buffer, especially when the current of source S 3 is twice the current of source S , the currents through the transistors T and T 5 are equal, so that the base (and collector) voltage of transistor T 5 is equal to the base voltage of transistor T 4 . The buffered signal is shifted upwardly one N De junction voltage by transistor T 6 in order to compensate for the downward voltage shift caused by the emitter follower transistor T 3 , and thereafter applied to the output O of the amplifier. Consequently, during the track mode, the output signal of the track and hold amplifier is substantially equal to the input signal. During the hold mode, the current of source S 5 flows through the transistor T 7 and pulls the voltage of point P down. Now the transistor T 3 is switched off and the base voltage of transistor T 4 and consequently the output voltage at terminal O is determined by the voltage of the hold capacitor at the level which it had at the end of the track mode. It may be noted,, that the voltage drop at point P biases the emitter-base junction of transistor T 2 in cutoff direction. Therefore the function of the input buffer, apart from lowering the impedance level at the input during the track mode, is also to isolate point P from the input signal source during the hold mode, so that the voltage of point P is allowed to be pulled downwardly. The arrangement of Figure 1 additionally has a clamping transistor T , whose base electrode is connected to the output terminal O and whose emitter electrode is connected to point P. During the track mode the voltage at point P and the voltage at the output terminal O are substantially equal so that the clamping transistor T is cut off and inoperative. During the hold mode, however, if point P is pulled down more than one N be junction voltage, the transistor T becomes conducting thereby limiting the voltage drop at point P to one N be junction voltage. This measure is taken because a too large voltage drop at point P would result, through the parasitic base-emitter capacitance of transistor T 3 , in a too large transient pulse in the output voltage. A drawback of the prior art arrangement of Figure 1 is that during the track mode the signal variations cause large currents flowing into the hold capacitor C H , especially at the higher signal frequencies of e.g. 20 Mhz. These large currents flow into the hold capacitor through the emitter follower transistor T 3 and thereby cause, across the non-linear base-emitter junction of this transistor large and non-linear voltage variations, so that the track and hold amplifier actually samples and holds a distorted signal level. The arrangement of Figure 2, in which corresponding circuit elements as in Figure 1 have the same reference numerals, seeks to avoid the above described distortion. In this arrangement the base electrode of transistor T 2 , in stead of being coupled to the collector electrode of this transistor, is coupled, through a transistor Tio, to the emitter electrode of transistor T , so that a feedback loop is constituted from the collector electrode of transistor T 2 through the base-emitter junction of transistor T 3 and through the transistor T lυ to the base electrode of transistor T 2 . While the input buffer seeks to make the base voltage of T substantially equal to the input voltage, this feedback loop seeks to make the emitter voltage of transistor T 3 substantially equal to the base voltage of transistor T 2 , so that, as a result, the emitter voltage of transistor T 3 represents the input voltage substantially without distortion. In fact, the distortion which is caused by the emitter-base junction of transistor T appears now at the base electrode of his transistor in stead of at the emitter electrode. When the base electrode of transistor T 2 and the emitter electrode of transistor T 3 would be directly connected to each other, a problem arises during the hold mode. During this mode the transistor T 3 is cut off so that the base electrode of T 2 now follows the hold voltage of the hold capacitor C H - When the input voltage Nj rises during the hold mode the base emitter junction of transistor T blocks, however when the input voltage decreases the base emitter junction of transistor T 2 conducts a large current which (de)charges the hold capacitor so that the hold voltage is distorted. This undesired hold mode feedthrough is prevented by the insertion of a pn-junction switch in the feedback path between the emitter electrode of T 3 and the base electrode of T 2 . In the arrangement of Figure 2 this switch is implemented by the transistor Tio, which has interconnected base- and collector electrodes and therefore operates as a diode. To operate this switch the arrangement of Figure 2 further comprises a current source S 6 connected to the collector base of transistor Tio and a fourth emitter coupled transistor pair Tιι-T ]2 with an emitter current source S 7 , with the collector of transistor Tn connected to the base electrode of transistor Tio and the collector electrode of transistor Tι 2 connected to the emitter electrode of transistor T^. Equally as in the case of the transistor pair T -T 8 , the base electrodes of the transistors Ti ι and T 12 receive a track and hold switching pulse T/H. During the track mode, the current of source S 6 flows through the transistors Tio and Tι , so that the base emitter junction of transistor Tio is conductive. On the other hand, during the hold mode and provided the current of source S is larger than the current of source S 6 , the current of source S 6 flows through the transistor Ti j, the base-emitter junction of transistor Tι 0 is cut off and the aforementioned undesired hold mode feedthrough is prevented. It may be observed that the original track mode distortion by the conductive base-emitter junction of transistor T 3 in the arrangement of Figure 1, is not replaced in the arrangement of Figure 2 by a similar distortion due to the conductive base-emitter junction of Tio. This is because through the conductive base-emitter junction of Tio substantially only DC current flows and the AC signal-current flowing through this junction is negligible. It is further observed, that, during the hold mode, the conductive transistor Ti i pulls down the voltage of point Q, i.e. the interconnection of the base electrodes of the transistors T 2 and Tio- This pull down may be limited by a further clamping transistor Tι 3 which has its base electrode connected to the output terminal O and its emitter electrode to point Q. This voltage pull down of point Q does not only cut off the transistor Tj 0 but also the transistor T , which gives a further reduction of the hold mode feedthrough. If the voltage pull down at point Q is not sufficiently large to cutoff the transistor T 2 for all values of the input voltage Ni, this pull down can be increased by inserting a resistor (R \ ) of appropriate value in the emitter lead of clamping transistor Tι 3 . A further resistor R is included between the emitter electrode of the switched emitter follower transistor T 3 and the hold capacitor C H - The function of this resistor is threefold: - The emitter of transistor T 3 represents an inductive impedance which, with the large hold capacitor C H constitutes an LC-loop. The resistor R 2 damps out undesired ringing of this LC-loop. - The resistor R 2 filters KT/C noise from reaching the hold capacitor C H - - The resistor R 2 separates the hold capacitor C H from the feedback loop T 3 , Tio, T 2 . This improves the stability of this feedback loop. An alternative arrangement is shown in Figure 3, in which again corresponding elements as in Figure 1 and 2 have the same reference numerals. As in the arrangement of Figure 2, this has also a feedback connection from the emitter electrode of transistor T 3 to the base electrode of transistor T , however in this arrangement the switching transistor Tio fails. In order to disable the feedback during the hold mode, the current source Si of the input buffer has been replaced by an emitter-coupled transistor pair T ] -Tι with common emitter source S 8 . The collector electrode of transistor Tι 5 is connected to the common emitter electrodes of transistor pair T T 2 and the collector electrode of transistor Tι 4 is connected to the positive supply. A further current source S 9 is connected between the positive supply and the common emitters of Ti and T 2 . The base electrodes of transistor pair Tι -Ti 5 receive the track and hold switching pulse T/H, which makes the base electrode of Tis high during the track mode and which makes the base electrode of Tj 4 high during the hold mode. In operation, during the track mode, with the transistor T 15 conducting and the transistor Tj 4 cut off, the coupled emitter electrodes of Tj and T 2 carry the current of source S 8 minus the current of source S . With the current of S 8 greater than the current of S 9 , the difference current has the same function as the current of source Si in the arrangements of Figures 1 and 2 and the transistors Ti and T 2 operate as usual for buffering the input signal. During the hold mode, the transistor Tι 5 is cut off and the transistor Tι 4 conducts the current of the source S 8 . The current of the source S now lifts the potential of the two emitter electrodes of Ti and T 2 , thereby cutting off these two transistors. With the transistor T cut off, the feedback from the emitter electrode of transistor T 3 to the transistor T is disabled and the hold mode feedthrough through this connection is largely prevented. Therefore, in the arrangement of Figure 3 the transistor T has taken over the function of the transistor Tio in the arrangement of Figure 2. The simultaneous cut off of the transistor Tj assists in the reduction of the hold mode feedthrough. In order to reduce the amplitude of the voltage pulse at the common emitter electrodes of the transistor pair Tι-T 2 , a clamping transistor (diode) T ]6 with interconnected base- and collector electrodes, is connected between the common emitters of the input buffer Tι-T 2 and the common emitters of the output buffer T 4 -T 5 . During the track mode, both common emitters have substantially the same potential, namely the input signal voltage N, minus one Nt, e junction voltage. The clamping transistor Tι conducts during the hold mode and prevents that the voltage of the emitters of Ti and T 2 rises above the input signal voltage N,. In the arrangement of Figure 3 the output terminal O is connected between the transistors T 5 and T , because in this arrangement, due to the absence of a transistor Tio, the voltage at the input of the output buffer is one N e junction voltage shift higher than in the arrangement of Figure 2. In practice, the arrangement of Figure 2 may be preferred over the arrangement of Figure 3 because the latter consumes less energy from the dc supply. Moreover a disadvantage of the arrangement of Figure 3 is that the input impedance of the arrangement changes with the track and hold switching because the transistor Tj is conducting during the track mode and cut off during the hold mode.

Claims: CLAIMS: 1. A track and hold amplifier comprising an input buffer (I B ) for receiving an input signal and for transferring the received input signal to a first terminal (P) of a pn- junction switch (T 3 ) a second terminal of which is connected to a hold capacitor (C H ), and means (T 7 , T 8 ) to supply a switching signal to said first terminal (P) of the pn-junction switch for translating the buffered input signal through the switching pn-junction to the hold capacitor during a track mode and for blocking this transfer during a hold mode, characterized by a feedback connection from the second terminal of the pn-junction switch (T ) to the input buffer (I B ) and means to enable the feedback during the track mode and to disable the feedback during the hold mode. 2. A track and hold amplifier as claimed in claim 1, characterized in that said means to enable the feedback during the track mode and to disable the feedback during the hold mode comprise a second pn-junction switch (Tio) within said feedback connection and second means (Tn, T] 2 ) to supply the switching signal to the second pn-junction switch (Tio). 3. A track and hold amplifier as claimed in claim 2, characterized by clamping means (Tπ, Rj) connected to the part of the feedback connection between the input buffer (I B ) and the second pn-junction switch (Tio). 4. A track and hold amplifier as claimed in claim 1, characterized by resistive means (R 2 ) between the second terminal of the first pn-junction switch (T 3 ) and the hold capacitor (C H ) for increasing the stability of the feedback path.

Inventors: DIJKMANS EISE C, HOOGZAAD GIAN, ROOVERS RAF L J, DIJKMANS, EISE, C., HOOGZAAD, GIAN, ROOVERS, RAF, L., J.
Applicants: KONINKL PHILIPS ELECTRONICS NV, KONINKLIJKE PHILIPS ELECTRONICS N.V.
Application year: 2001
Main classification: G11C27
IPC codes: G11C27, H03F3