APPARATUS AND METHOD FOR PERFORMING A CRYPTOGRAPHIC ALGORITHM

Abstract: An apparatus for performing a cryptographic algorithm which can be AES algorithm according to Rijndael includes a CPU (12) and a coprocessor (14). One step of the cryptographic algorithm is a mix columns transformation on mix columns input data. The CPU (12) is arranged for providing the mix columns input data. The coprocessor (14) is arranged for performing at least a part of the mix columns transformation on the mix columns transformation with an arithmetic unit which conducts calculations for a number of data units in parallel, said number being equal to or greater than the number of data units of a column. By performing the mix columns transformation using CPU and a coprocessor having a long integer arithmetic unit, the execution time and the required memory space RAM can be reduced. Additionally, security is enhanced, since timing or power analysis related attacks are harder to perform.

Description: Description Apparatus and method for performing a cryptographic algorithm The present invention relates to cryptographic algorithms and, in particular, to an apparatus and method for efficiently performing the AES algorithm according to Rijndael. Recently, the Rijndael algorithm has been declared to be the new Advanced Encryption Standard (AES) algorithm. The algorithm is described in federal information standards publication draft Advanced Encryption Standard (AES) , National Institute of Standards and Technology (NIST) , published 2001. This document can be downloaded using the following link: http: //csrc. nist.gov/publications/drafts/dfips-AES.pdf. The AES algorithm, which is also called the "Rijndael" algorithm is a symmetric block cypher that processes data in blocks of e.g. 128 bits using cypher keys with lengths of 128, 192 and 256 bits. Additional block sizes are generally possible, but are not adopted in the standard. At the start of the encryption operation, input data to be encrypted are copied to the so-called state array. Reference is made to Fig. 3. The to encrypted data are called input bytes 300. The input bytes represent data to be encrypted and are, as it is shown in Fig. 3, ordered in an array having rows and columns. The input bytes 300 are copied in the state array 302. As it is explained later, the state array is processed using key information in order to generate output bytes 304, which are the encrypted representation of the input bytes. Generally, the AES algorithm is performed in so-called rounds. An AES round is illustrated in Fig. 2. Before the first round starts, there has to be performed a so-called add round key operation, which is described later on. The original state array 302 (Fig. 3) is, therefore, transformed into another state array having a round key added. This state array, which is indicated by 200 in Fig. 2 is processed by means of a so- called AES round 202 which consists of several consecutive transformations. These are the byte substitution 204, the shift rows operation 206, the mixed columns operation 208 and an add round key operation 210. For ease of illustration, also the data between blocks 204 to 210 are termed the state, although it is clear that the state bytes are state data output by, for example, the byte substitution operation 204 are different from the state bytes input into the byte substitution operation. As specified by the AES standard, a predetermined number of AES rounds is performed, wherein, for each round, another round key is derived from key information. After the specified number of AES rounds is processed, a final AES round consists of a byte substitution operation followed by a shift rows operation which again is followed by a final add round key operation. The output of the final add round key operation are the output bytes 304 illustrated in Fig. 3. The byte substitution operation shown at 204 in Fig. 2 is a non-linear byte substitution that operates independently on each byte of the state using a substitution table which is also called S-box. This S-box, which is invertible, is constructed by composing two transformations, wherein the first of the two transformations is the multiplicative inverse in the finite field GF(2 8 ). The other of the two transformations is the affine (over GF(2)) transformation. The shift rows transformation 206 is a transformation in which the bytes in the last three rows of the state are cyclically shifted over different numbers of bytes (offsets) wherein the first row, i.e. row 0, is not shifted. The shift value depends on the row number such that bytes in an input row are shifted to lower positions in the row, i.e. lower values of c in a given row, while the "lowest" bytes wrap around into the "top" of the row, i.e. higher values of c in a given row. The mixed columns transformation 208 is further illustrated with respect to Figs. 4a, 4b, 4c and 5. The mixed columns transformation operates on the state column-by-column, treating each column as a four-term polynomial. The columns are considered as polynomials over GF(2 8 ) and multiplied modulo x:4+l with a fixed polynomial a(x) which is shown in Fig. 4a. Since the polynomial a (x) is a fixed polynomial, this multiplication modulo x:4+l can be written as a matrix multiplication which is illustrated in Fig. 4b. As a result of this multiplication, the four bytes in a column of the state (note that this state consists of the array of bytes output by the preceding shift rows transformation 206 in Fig. 2) are replaced by the following s'i j . This is indicated in Fig. 4c. With respect to the notations "01", "02" and "03", it is to be noted that this notation is the usual hexadecimal representation of bit patterns. "00" represents the four bit pattern "0000". "01" represents the four bit pattern "0001". "03" represents the four bit pattern "0010". Since each power of x in Fig. 4a has two such hexadecimal numbers as coefficient, it becomes clear that the coefficients of each power of x consist of 8 bits, i.e. 1 byte, each, which is the reason for considering the columns as several polynomials over GF(2 8 ). Fig. 5 illustrates the mix columns transformation to show that from one column of the state, one column of the transformed state is calculated. With respect to the notation in Fig. 4c, it has to be remarked that the multiplication symbol indicates a multiplication in GF(2 8 ), which corresponds with the multiplication of polynomials modulo an irreducible polynomial of a degree of 8. The addition of two elements in the finite field is achieved by "adding" the coefficients for the corresponding powers in the polynomials for the two elements. The addition is performed with the XOR operation (denoted by the circled plus sign), i.e. modulo 2, so that 1 + 1 = 0, 1 + 0 = 1 and 0 + 0 = 0. Consequently, the subtraction of polynomials is identical to the addition of polynomials. The add round key transformation 210 (Fig. 2) serves to add a round key to the state by a simple bit-wise XOR operation. Each round key consists of a number of words from a key schedule, the number being equal to the number of bytes of the state. In the encryption algorithm, the initial round key addition occurs prior to the application of the first AES round. The AES algorithm, which is a symmetric encryption algorithm takes the key for encryption, i.e. the cypher key, and performs a key expansion routine to generate the key schedule. The key expansion generates a certain amount of words. The algorithm requires an initial set of words, and each of the rounds requires another number of words of key data. The resulting key schedule consists of a linear array of 4-byte words . The AES decryption algorithm, i.e. the inverse cypher, works in a reverse order. The individual transformation used in the inverse cyphers are inverse shift rows, inverse byte substitution, inverse mix columns and add round key. These individual transformations process the state and are performed as described in the AES standard draft cited above. The AES algorithm has been designed to be fully compatible with an 8-bit CPU. The operations occurring in the AES algorithms are operations defined in the finite field GF(2 8 ). Therefore, these operations are suitable for standard 8-bit micro-controllers. When, for example, Fig. 4c is considered, an 8-bit CPU would perform, for example, the multiplications in the first row of Fig. 4c serially and, then, XORing the results of the two multiplications and the remaining state bytes. It has been found out that such an 8-bit implementation needs about 12000 clock cycles to encrypt a 128 bits data block. Additionally, about 48 bytes of a directly addressable internal RAM (RAM = Random Access Memory) are used. It is believed that a decryption algorithm will take about 30% more time than the encryption algorithm and at least the same number of bytes of internal RAM or even more. This is due to the fact that the software implementation of the inverse mix columns transformation for an 8-bit CPU is less efficient than the mix column transformation used for encryption. When, for example, the AES algorithm has to be performed by a controller on a smart card, the computational power of the smart card is not as excessive as on a personal computer. Additionally, the memory resources are very scarce on the smart card. Performing the AES algorithm using an 8-bit micro-controller on a smart card results, therefore, in long computation times and in the need for memory which. This is not favourable for a customer who has to wait very long for the results of the decyphering operation and which, on the other hand, increases the costs of the smart card because of more required memory cells on the smart card. It is the object of the present invention to provide an improved concept for performing a cryptographic algorithm having a mix column transformation which is appreciated by the customers and, at the same time, less costly. This object is achieved by an apparatus for performing a cryptographic algorithm in accordance with claim 1, an apparatus for performing decryption in accordance with claim 16, a method for performing a cryptographic algorithm in accordance with claim 23 and a method for performing decryption in accordance with claim 24. The present invention is based on the finding that, although the AES algorithm is specially defined for 8-bit CPUs, the mix columns transformation is especially suited for being at least partly performed by a coprocessor having an arithmetic unit arranged for conducting calculations for a number of data units, for example, bits in parallel, the number of data units being equal to or greater than the number of data units of a column of the mix column input data which are the state bytes in case of the AES algorithm. The long integer arithmetic unit included in the coprocessor is used to perform the mix column transformation. The long integer arithmetic unit included in the coprocessor can be designed for calculating one data group, for example one byte, of the mix columns transformation output data, i.e., the state after the mix column transformation, in parallel, when it has registers and calculation units for processing a number of bit in parallel, the number of bits being equal to the number of bits in one column. Then, one data group of the mix columns output data can be calculated after the other which is a so-called serial-parallel or hybrid mode. Preferably, the long arithmetic unit is designed for processing a number of bits in parallel which is equal to the number of bits of the whole state. In this case, a fully parallel calculation of the mix columns transformation can be obtained. Both embodiments are made possible by interpreting the polynomials involved with the mix columns transformation that have coefficients in GF(2 8 ) as polynomials in the field GF(2 32 ), in case four bytes are in one column, and treating the coefficients as binary coefficients in GF(2). Then, a standard long integer arithmetic unit designed for handling binary coefficients in GF(2) is suited for carrying out the calculations in GF(2 32 ) or, when the whole mix columns transformation is performed in parallel, in GF(2 128, Preferred embodiments of the present invention are explained in detail with reference to the enclosed drawings, in which Fig. 1 shows a schematic of an inventive apparatus for performing a cryptographic algorithm including a mix column transformation; Fig. 2 illustrates one round of the AES algorithm according to Rijndael; Fig. 3 illustrates how to be encrypted input bytes becomes bytes of the state array and become encrypted output bytes; Fig. 4a illustrates the fixed polynomial standardized in the AES standard having coefficients in GF(2 8 ); Fig. 4b illustrates how a mix columns operation can be described as a matrix multiplication; Fig. 4c illustrates an expanded representation of the matrix multiplication; Fig. 5 illustrates an overview of the mixed columns transformation; Fig. 6a shows the Xtime operation on the state which is used for performing a fully parallel calculation of the mix columns operation; Fig. 6b illustrates a flow chart to perform the Xtime operation shown in Fig. 6a; Fig. 7 illustrates a sequence of steps to perform a fully parallel mix columns transformation; Fig. 8 shows a sequence of steps to perform a fully parallel inverse mix columns transformation; Fig. 9a illustrates other Xtime operations which can be used for carrying out a fully parallel inverse mix columns transformation in accordance with another embodiment of the present invention; Fig. 9b illustrates a sequence of steps for performing a fully parallel inverse mix columns transformation using Xtime operations shown in Fig. 9a; Fig. 10 illustrates a sequence of steps to perform a fully parallel key expansion; Fig. 11 shows a step how to perform fully parallel add round key operation; and Fig. 12 illustrates the inventive apparatus arranged for performing the key expansion transformation in the CPU and the mix columns transformation in the coprocessor, in accordance with another embodiment of the present invention. Fig. 1 shows a block chart of an inventive apparatus for performing a cryptographic algorithm. As it has been outlined with respect to Fig. 2, the cryptographic algorithm includes a sequence of steps, one step including a mix columns transformation 208 (Fig. 2) on mix columns input data, i.e., with respect to Fig. 2, the state output data received after the shift rows step 206. The mix columns operations operates to obtain mix columns output data. The mix columns input data includes an array of data groups, e.g. bytes, the array having a predetermined number, e.g. 4, of columns, wherein one column has a plurality, e.g. 4, of data groups, and wherein one data group includes a number, e.g. 8, of data units, e.g. bits. The inventive apparatus 10 shown in Fig. 1 includes a CPU 12 which is an 8-bit CPU in accordance with a preferred embodiment of the present invention. The cryptographic apparatus 10 further comprises a coprocessor 14 for performing at least a part of the mix columns transformation on the mix columns input data. The coprocessor 14 includes an arithmetic unit arranged for conducting calculations for a number of data units in parallel. The number of data units being equal to or greater than the number of data units of a column. In a preferred embodiment in which the cryptographic apparatus performs an encryption according to the AES algorithm, the arithmetic unit in the coprocessor is designed for parallel computation of at least 32 bits in parallel in order to parallely compute one element of the output vector on the left side of Fig. 4b, i.e. s' 0/C , at a time. Preferably, however, the arithmetic unit is designed for performing the complete mix columns transformation in parallel. In this case, the arithmetic unit is arranged for performing calculations on a number of bits, the number of bits being equal to the number of bits or data units included in the state. When, therefore, the length of the cypher key in the AES algorithm is 128, the arithmetic unit is designed for parallely processing 128 bits. When, however, the key length is 192 bits or 256 bits, the arithmetic unit is designed to parallely process 192 or 256 bits, respectively. In accordance with the first embodiment of the present invention in which the arithmetic unit is arranged for conducting calculations for a number of data units in parallel, the number of data units being equal or greater than the number of data units of a column, one line of the calculations shown in Fig. 4c is calculated substantially in parallel such that this embodiment can be regarded as a kind of hybrid concept, in which one data group of the mix columns output data is calculated in parallel and the data groups themselves are calculated one after the other. In contrast thereto, for calculating s'o, c , an 8-bit CPU has to calculate the first term of the right side in Fig. 4c, then the second term and, then, load the third and the fourth term to XOR the results to get s'o, c - In accordance with the present invention, the mix columns transformation which multiplies a 4-byte variable polynomial by a constant polynomial r(x) modulo x 4 +l and in which all polynomials are coefficient in GF(2 8 ), the use of the long integer arithmetic unit allows to work directly on the 4-byte polynomials by converting them into 32-bit polynomials with coefficients in GF(2) and performing the multiplication on the field GF(2 32 ) . In the following, the second embodiment of the present invention will be described in which the arithmetic unit of the coprocessor is arranged for conducting calculations for a number of data units in parallel, the number of data units being equal to the number of data units included in the mix columns input data. The second embodiment provides for a fully parallel implementation of the mix columns transformation. Preferably, the Xtime (state) operation is used. The Xtime operation is defined in the AES specification. It multiplies one byte of the state by two modulo the irreducible polynomial x 8 +x 4 +x 3 +x+l. This operation is performed inside the coprocessor on the, for example, 16 bytes of the state in parallel with the formula shown in Fig. 6a. (state) indicates the mix columns input data, i.e. the data output by the shift rows transformation 206. In Fig. 6a, the meanings of the symbols in the Xtime operation are summarized, ml, m2 and m3 are fixed numbers in the well-known hexadecimal representation. The star indicates the multiplication operation in GF(2 d ) . Dependent on the key length, d is 128, 192 or 256, when the inventive apparatus is used for performing the AES algorithm. However, other values for d are possible for other key sizes. The + sign indicates addition modulo 2, while the AND sign (&) indicates the logical AND operation. Finally, the « or » signs indicate left and right shift operations in a register. Fig. 6b shows a sequence of steps that are controlled by a sequencer included in the CPU or the coprocessor to calculate the Xtime operation on the state, i.e. the mix columns input data. To this end, the coprocessor has two temporary registers Tmpl and Tmp2 as well as one register for the state. The state can also be a temporary register in the coprocessor, but it can alternatively be a CPU register. Then, the state bits have to be loaded into the processor when needed. In a first step 601, the first temporary register Tmpl receives the result of logical ANDing of the state and the fixed number ml. In a second step 602 the input of the first temporary register is shifted to the right by 7 digits, which are e. g. bits. In a third step 603 the new input of the first temporary register is multiplied in GF(2 d ) by the fixed number m3. In the fourth step 604 the second temporary register Tmp2 receives the result of logically ANDing of the state and the fixed number m2. In the fifth step 605, the input of the second temporary register Tmp2 is left-shifted by 1 digit. In the last step, the input of the first and second temporary registers are added modulo 2 such that, in the first temporary register, the result of the Xtime operation on the state is contained. Preferably, all operations needed for the sequence of steps shown in Fig. 6b are supported by the coprocessor. When, however, the AND operation is not supported by the coprocessor, it can be done in the CPU before loading the state into the coprocessor's register. Then, the result of the AND operation is loaded in the first and second temporary registers Tmpl and Tmp2. Based on the Fig. 6a and Fig. 6b definition of the Xtime operation, the whole mix columns transformation is defined to operate on the 16 bytes of the state in parallel. Referring to Fig. 7, a sequence of steps controlled by a sequencer included in the inventive apparatus, describes a fully parallel mix columns transformation. The total number of registers needed for the implementation of the mix column transformation in accordance with the preferred embodiment shown in Fig. 7 is 3 wherein two temporary registers serve to hold the intermediate results and the third register is used for storing the state bits. In the first step 701, the output of Fig. 6b is loaded into the first temporary register. In a second step 702, the input of the first temporary register "is added modulo 2 to the state. In a third step 703, the input of the second temporary register is processed by a RotWord operation. The RotWord operation performs a word rotation and is defined in the AES specification. This operation has to be performed by the CPU on the data stored in the coprocessor registers, if it is not supported by the coprocessor itself. The RotWord ( ) operation provides an output word by rotating bytes in the input word. This means that, for example, (b0,bl,b2,b3) is transformed into (bl,b2,b3,b0) wherein the bi is a data group, e.g. a byte, which consists of a number of data units, e.g. bits. In a fourth step 704, the temporary register receives the results of an addition modulo 2 of the old value stored in the first temporary register and the value stored in the second temporary register. In a step 705, a RotWord operation is performed on the state, and the result is stored in the second temporary register. In step 706, a RotWord operation is performed on the previous result. In step 707, the contents of both temporary registers are added modulo 2 and loaded into the first temporary register. In step 708, a RotWord operation is performed on the contents of the second temporary register. Finally, in a step 709, the contents of both registers are added modulo 2 and loaded into the state register. After the step 709, the mix columns transformation is completed and the ' state bytes, i.e., the mix columns output data can be input in the add round key operation 210 in Fig. 2. The inventive apparatus shown in Fig. 1 can also be used for performing an inverse mix columns transformation in an efficient manner. As for the mix columns transformation, the inverse mix columns transformation which is needed for decryption can also be defined to operate on the 16 bytes of the state in parallel. The preferred implementation is based on the definition of the Xtime operation given in Figs. 6a and 6b. For performing the fully parallel inverse mix columns transformation shown in Fig. 8, the coprocessor needs four temporary registers Tmpl, Tmp2, Tmp3 and Tmp4 for the intermediate results and another register for the state. A sequencer included in the inventive apparatus controls the CPU and the coprocessor to perform the sequence of the steps shown in Fig. 8. In a first step 801, the result of the Xtime operation on the state is loaded into the first temporary register. In a second step 802, the Xtime operation is performed on the content of the first temporary register. In a third step 803, a Xtime operation is performed on the content of the second temporary register. In the fourth step 804, the contents of the three temporary registers 1 to 3 are added modulo 2 and loaded into the fourth temporary register. In a fifth step 805, the contents of the state register of the second temporary register and the third registers are added modulo 2. In a sixth step 806, the contents of the state, the first and the third temporary registers are added modulo 2. In the seventh step 807, the third temporary register and the state register are added modulo 2 and the result is loaded into the third temporary register. In an eighth step 808, a RotWord operation is performed on the first temporary register. In the ninth step 809, a RotWord operation is performed on the second temporary register. On the result of the RotWord operation, another RotWord operation is performed, and the result of the other RotWord operation is loaded into the second temporary register. In a step 810, a first RotWord operation is performed on the contents of the third temporary register. The result of this first RotWord operation is used as an input into another RotWord operation. The result of the other RotWord operation is again used as an input into a third RotWord operation. The result of the third RotWord operation is loaded into the third temporary register. Finally, in a step 811, the contents of the four temporary registers are added modulo 2 and loaded into the state. As it is known in the art, a decryption round of the AES algorithm firstly performs an inverse shift rows operation, then an inverse byte substitution operation, then an add round key operation and finally an inverse mix columns operation. Therefore, the inverse mix columns input data are the data output by the add round key operation preceding the inverse mix columns transformation. Analogously, the content of the state after the step 811 as shown in Fig. 8 is the input in an inverse shift rows operation for the next decryption round of the AES algorithm. Referring to Figs. 9a and 9b, another way to implement the inverse mix columns transformation is illustrated. To this end, the two Xtime4 and Xtime8 operations are introduced as auxiliary operations. These operations are based on the fixed numbers m4, m5, m6, m7 and, again, m3. Based on the definitions given in Fig. 9, another preferred implementation of the inverse mix columns transformation is shown in Fig. 9b. In a first step 901, a second step 902 and a third step 903, the first, second and third temporary registers are loaded with the three Xtime operations shown in Fig. 9a and Fig. 6a, respectively. In a fourth step 904, the fourth temporary register receives the result of an addition of the first, two, and third temporary registers. In a fifth step 905, the second temporary registers receives the result of an addition of the state and the contents of the second and third temporary registers. In a sixth step 906, the first temporary register receives the result of an addition of the state, the first and the third temporary registers. In a seventh step 907, the third temporary registers receives the result of an addition of the state and the third temporary register. The steps 908, 909, 910 and 911 are identical to the steps 808, 809, 810 and 811 which have been explained in connection with Fig. 8. The advantage of the inverse mix columns transformation shown in Fig. 9b compared to the implementation shown in Fig. 8 is that the Xtime, Xtime4 and Xtimeδ operations can be calculated in parallel from the state which avoids the sequence of the first to third steps 801 to 803 of the implementation shown in Fig. 8. Additionally, in the case that the AND operation is not available in the coprocessor, the second implementation as shown in Fig. 9b allows to precompute all the AND values in the CPU before loading the state into the coprocessor. In accordance with another preferred embodiment, also the key expansion operation can be implemented in the coprocessor. The 16 bytes of the key are loaded into a register of the coprocessor. Then, the new round key is calculated using a sequence of operations, which is shown in Fig. 10. In a first step 1001, a RotWord operation is performed on the four rightmost bytes of the key data. Then, a byte substitution as defined in the AES standard is performed on the result of the RotWord operation. The result of the byte substitution is added modulo 2 to the so-called Rcon constant which is described in the AES standard and has the following value: Rcon = [x i_1 , {00}, {00}, {00}] where i is the round number, and x = {02} in the field GF(2 ) . The result is put into the 4 leftmost bytes of the first temporary register, whereupon the twelve rightmost bytes are cleared, i.e., set to zero. The RotWord, SubByte and λ + Rcon' operations are preferably done by the main CPU. In a second step, a key register is loaded with the original key value added to the contents of the first temporary register. In a third step 1003, the input of the first temporary register is shifted by 32 digits to the right. In a fourth step 1004, the contents of the key register and the first temporary register are added modulo 2. In a fifth step 1005, the contents of the first temporary register is shifted by 32 digits to the right. In a sixth step 1006, the key value added modulo 2 to the first temporary register is loaded into the key register. In a seventh step 1007, the input of the first temporary register is shifted by 32 digits to the right, and in a final step 1008, the key register contents and the contents of the first temporary register are added modulo 2 to result in a new round key which is placed in the key register. It is to be noted that the RotWord operation and the byte substitution operation (SubByte) are performed by the 8-bit CPU on the four right most bytes of the key, and the result is put into the 4 leftmost bytes of the first temporary register. Then, the twelve right most bytes are cleared, i.e. set to 0. As it has been outlined above, Rcon is the 4-byte constant defined in the AES specification. The total number of registers for the implementation of the key expansion transformation in the coprocessor is 2. One temporary register is needed for the intermediate results, while the other temporary register is needed for the key. The coprocessor is also useful for performing the add round key transformation. This transformation is performed by simply adding modulo 2 state and the key inside the coprocessor. To this end, step 1100 shown in Fig. 11 is used. The coprocessor does not need any temporary register for this operation. In the following, reference is made to Fig. 12 which shows the inventive apparatus for performing the AES algorithm in accordance with another embodiment of the present invention. The coprocessor includes data registers for holding necessary data for the arithmetic unit of the coprocessor performing a mix columns transformation. The arithmetic unit is termed mix columns and has the reference number 1202. In the internal RAM of the CPU, key data 1204 are stored. The CPU, which is preferably an 8-bit CPU is arranged for performing the add round key transformation, the byte substitution operation and the shift rows operation. Additionally, in accordance with the embodiment shown in Fig. 12, the CPU is further arranged to perform the key expansion operation. This has the advantage that, since key expansion and mixed columns are independent from each other, key expansion and mixed columns can be performed by the CPU and the coprocessor in parallel. This alone can reduce the number of cycles from 1200 up to 6800 or less and the bytes of the internal RAM required from 48 to 16. This saving is very important because it leaves more directly addressable RAM (a very scarce resource) space to the customer's application. Another advantage when the mix columns transformation is performed in the arithmetic unit 1202 of the coprocessor is an improved balance of the performance of the encryption and decryption algorithm. When an 8-bit CPU alone is used for performing the AES algorithm, the decryption calculations will take about 30% more time than the encryption operations. This is due to the fact that the software implementation of the inverse mix columns transformation used for decryption is less efficient than the mix columns transformation used for encryption. When the inventive apparatus is used for performing the AES algorithm, an improved balance is obtained, since encryption and decryption operations take about the same time. Since the coprocessor performs the multiplication of columns or key words, these operations are protected against timing attacks. Moreover, the parallel execution of the mix columns and the key expansion transformations makes more difficult power consumption analysis. Additionally, the security can be further enhanced by random masking in the CPU during the key expansion and in the coprocessor during the mix columns operation. The mask is removed during the add round key transformation. To this end, an additional register in the coprocessor is needed to store a random mask value. Preferably, the coprocessor includes two calculation units, wherein one calculation unit is used for performing the masking, while the other calculation unit in the coprocessor is used for carrying out AES steps. The main advantages are, however, that the parallel implementation of the AES algorithm as outlined above is about two times faster than an implementation in an 8-bit CPU. Additionally, the parallel implementation requires about 3 times less user memory. In fact, an implementation of the AES encryption algorithm on a CPU together with a coprocessor having a long integer arithmetic unit requires only 20 bytes of internal RAM memory. It is to be noted that because the only multiplication operations on GF(2 8 ) are performed by a constant value m3 = Oxlb (Ox means hexadecimal representation), without any reduction to the irreducible polynomial described in the AES specification, the implementation described here is not susceptible to timing attacks. Also the long arithmetic coprocessor can be used to logically random mask the algorithm' s state to make more difficult power consumption related attacks, but in that case, an additional long register is needed to store the random mask value. A coprocessor suited to perform all operations given above, thus, needs a minimum of 6 long register, wherein four registers are for temporary storage, and two registers are for storage of the "state" and the key. Additionally, the coprocessor can have one or more registers Ci to store the constants ml to m7 used in the Xtime, Xtime4 and Xtimeδ operations. Preferably, the ALU of the coprocessor is able to perform all operations needed to do the mix columns and inverse mix columns operations, but it is also possible to perform the AND and RotWord operations in the main CPU. List of reference numbers 10 cryptographic apparatus 12 CPU 14 coprocessor 200 sequence of steps 202 AES round 204 Byte Substitution 206 ShiftRow Transformation 208 MixColumns transformation 210 AddRoundKey transformation 300 algorithm input data array 302 State Array 304 algorithm output data array 601 to 606 Steps for calculating Xtime (state) 701 to 709 Steps for Calculating MixColumns transformation 801 to 811 Steps for Calculating Inverse MixColumns transformation 901 to 911 Steps for Calculating Inverse MixColumns transformation 1001 to 1008 Steps for calculating Key Expansion 1100 Step for Calculating AddRoundKey transformation 1200 coprocessor register 1202 long arithmetic unit for performing MixColumns transformation 1204 CPU memory

Claims: Claims 1. Apparatus (10) for performing a cryptographic algorithm including a sequence of steps, one step including a mix column transformation (208) on mix columns input data to obtain mix columns output data, the mix columns input data having an array of data groups, the array having a predetermined number of columns, a column having a plurality of data groups and a data group including a number of data units, comprising: a CPU (12) for providing the mix columns input data; and a coprocessor (14) for performing at least a part of the mix columns transformation on the mix columns input data, the coprocessor having an arithmetic unit arranged for conducting calculations for a number of data units in parallel, the number of data units being equal to or greater than the number of data units of a column. 2. Apparatus in accordance with claim 1 in which the cryptographic algorithm is the AES algorithm according to Rijndael, and the sequence of step is one round of the AES algorithm. 3. Apparatus in accordance with claim 1 or 2, in which the mix columns transformation is defined by a modular multiplication of a matrix derived from a fixed polynomial by a column of the mix columns input data to obtain a column of the mixed column output data, in which the multiplications of matrix elements of a row of the matrix by the data groups of one column are performed by the coprocessor in parallel, wherein a column is interpreted as a polynomial in a finite field having a number of data units of one column and having coefficients in the finite field GF(2) . 4. Apparatus in accordance with claim 3, in which the CPU (12) is arranged to load one column of the mix columns input data to the coprocessor (14) at a time until all columns of the mix columns input data have been loaded into the coprocessor, wherein, in response to receiving a column of the mix columns input data, the coprocessor (14) is arranged for performing the multiplication in parallel and summing the results to obtain a data group of the mixed columns output data, and wherein, in response to receiving another column of the mix columns input data, the coprocessor (14) is arranged to use another row of the matrix for multiplication and summing results. 5. Apparatus in accordance with claims 3 or 4 in which the data units are bits, and the matrix is defined as follows: wherein 01 is the binary number 0001, 02 is the binary number 0010, 03 is the binary number 0011, and wherein one row of the matrix is regarded as a polynomial in GF(2 32 ). 6. Apparatus in accordance with claims 1 or 2 in which the coprocessor (14) is arranged for performing calculations on another number of data units in parallel, the other number being greater than or equal to the number of data units in the mix columns input data. 7. Apparatus as claimed in claim 6, which is arranged for performing an operation during the mix columns transformation, the operation being described by multiplying a data group of the mix columns input data by two modulo the following irreducible polynomial: x 8 + x 4 + x 3 + x + 1. 8. Apparatus as claimed in claim 7, in which the operation is the Xtime operation which is defined by the following equation: Xtime (state) = ( (state&m2)« 1) + (((state &ml)»7)*m3, wherein state is an array of data to be processed by the Xtime operation, ml = 0x8080...80, m2 = 0x7f7f...7f, m3 = Oxlb, * is the multiplication operation in GF(2 d ), + is the addition modulo 2, & is the AND operation, « is a left shift of a register content, and » is a right shift of a register content, and wherein the coprocessor additionally includes three registers having a length equal to or greater than the number of data units in the mix columns input data and wherein the arithmetic unit is adapted to perform an addition modulo 2 of the units of the two temporary registers; perform a right and/or left shift in a register by a specified number of data units; and perform a multiplication in the finite field having an order equal to or greater than the number of data units in the mix columns input data. 9. Apparatus as claimed in claim 8, wherein the coprocessor is arranged for performing an AND operation on the contents of the two registers. 10. Apparatus as claimed in claim 9, wherein the coprocessor (14) further comprises control means for controlling the arithmetic unit to perform the following steps in sequence to conduct the Xtime operation: Tmpl = state & ml Tmpl = Tmpl » 7 Tmpl = Tmpl * m3 Tmp2 = state & m2 Tmp2 = Tmp2 « 1 Tmpl = Tmpl + Tmp2 wherein Tmpl is a contents of a first temporal register, Tmp2 is a contents of a second temporal register, state is a contents of a third register, and RotWord is a word rotation function. 11. Apparatus as claimed in claim 10, which further comprises a sequencer for controlling the following sequence of operations : Tmpl = Xtime (state) Tmp2 = Tmpl + state Tmp2 = RotWord (Tmp2) Tmpl = Tmpl + Tmp2 Tmp2 = RotWord (state) Tmp2 = RotWord (Tmp2) Tmpl = Tmpl + Tmp2 Tmp2 = RotWord (Tmp2) State = Tmpl + Tmp2 wherein Tmpl is a contents of a first temporal register, Tmp2 is a contents of a second temporal register, state is a contents of a third register, and RotWord is a word rotation function wherein at least additions included in the sequence are performed by the arithmetic unit of coprocessor 14. 12. Apparatus as claimed by one of claims 1 to 11, in which another step in the sequence of step is a key expansion step for calculating an expanded key to be used for an actual sequence of steps, from a key from the cryptographic algorithm, and wherein the CPU (12) is arranged to work on the key expansion step, while the coprocessor works on the mix columns step. 13. Apparatus as claimed in one of claims 1 to 11, in which another step in the sequence of step is a key expansion step for calculating an expanded key to be used for an actual sequence of steps from a key from the cryptographic algorithm, and wherein the apparatus comprises a key expansion sequencer for controlling the following sequence of steps: Tmpl = Rcon + SubByte (RotWord (Key) ) * Key = Key + Tmpl Tmpl = Tmpl » 32 Key = Key + Tmpl Tmpl = Tmpl » 32 Key = Key + Tmpl Tmpl = Tmpl » 32 Key = Key + Tmpl wherein Tmpl is a contents of a first temporal register, key is a contents of a second temporal register, Rcon is a constant value, RotWord is a word rotation function, SubByte is a byte substitution function, + is an addition modulo 2, » is a right shift of a register contents, « is a left shift of a register contents, wherein the additions are conducted by the arithmetic unit of the coprocessor (14), and wherein the coprocessor has the first temporal register and the second temporal register. 14. Apparatus as claimed in one of claims 1 to 13, in which another step in the sequence of steps is in add round key step wherein the apparatus comprises an add round key sequencer for controlling the following steps: State = Key + state, wherein Key is a contents of a key register and state is the contents of state data of the algorithm. 15. Apparatus as claimed in one of claims 1 to 14, further comprising a masking unit for masking data units before being loaded from the CPU into the coprocessor and/or before being loaded from the coprocessor to the CPU. 16. Apparatus for performing decryption in accordance with a cryptographic algorithm including a sequence of steps, one step including an inverse mix columns transformation on inverse mix columns input data to obtain inverse mix columns output data, the inverse mix columns input data having an array of data groups, the array having a predetermined number of columns, a column having a plurality of data groups, and a data group including a number of data units, comprising: a CPU (12) for providing the inverse mix columns input data; and a coprocessor (14) for performing at least a part of the inverse mix column transformation on the inverse mix columns input data, the coprocessor having an arithmetic unit arranged for conducting calculations for a number of data units in parallel, the number of data units being equal to or greater than the number of data units of a column. 17. Apparatus as claimed in claim 16, in which the cryptographic algorithm is the AES algorithm according to Rijndael and the sequence of step is one round of the AES algorithm for decryption. 18. Apparatus according to claim 16 or 17, further comprising an inverse mix columns sequencer for controlling the following steps : Tmpl = Xtime (state) Tmp2 = Xtime (Tmpl) Tmp3 = Xtime (Tmp2) Tmp4 = Tmpl+Tmp2+Tmp3 Tmp2 = state+Tmp2+Tmp3 Tmpl = state+Tmpl+Tmp3 Tmp3 = state+Tmp3 Tmpl = RotWord (Tmpl) Tmp2 = RotWord (RotWord (Tmp2 ) ) Tmp3 = RotWord (RotWord (RotWord (Tmp3) ) ) State = Tmpl + Tmp2 + Tmp3 + Tmp4 wherein Xtime is an operation defined as follows: Xtime (state) = ( (state&m2)« 1) + (((state &ml)»7)*m3, wherein state is an array of data to be processed by the Xtime operation, ml = 0x8080...80, m2 = 0x7f7f...7f, m3 = Oxlb, * is the multiplication operation in GF(2 d ), + is the addition modulo 2, & is the AND operation, « is a left shift of a register content, and » is a right shift of a register content, wherein Tmpl, Tmp2, Tmp3, and Tmp4 is a content of a first, second, third, and fourth temporal register, respectively, state is a content of a state data register, and RotWord is a word rotation function, and wherein the coprocessor is arranged for performing at least additions, and includes at least five registers, each one having a length equal to or greater than the number of data units in the array for, the at least five registers including registers including the first, second, third, fourth, and state data register. 19. Apparatus as claimed in claim 18, wherein the RotWord operation is performed in the coprocessor (14). 20. Apparatus as claimed in claim 16 or 17, in which the following subsidiary functions are calculated: Xtime4 (state) = ((state & m5) « 2) + (((state & m4) » 6) * m3) Xtimeδ (state) = ((state & 7) « 3) + (((state & m6) » 5) * m3) , wherein m4 = 0xc0c0...c0 (16 bytes), m5 =0x3f3f...3f (16 bytes), m6 = 0xe0e0...e0 (16 bytes), m7 = OxlfIf... If (16 bytes) , state is an array of data to be processed by the Xtime operation, * is the multiplication operation in GF(2 d ), + is the addition modulo 2, & is the AND operation, « is a left shift of a register content, and » is a right shift of a register content. 21. Apparatus as claimed in claim 20, wherein the apparatus further comprises an inverse mix columns sequencer for controlling the following steps: Tmpl = Xtime (state) Tmp2 = Xtime4 (state) Tmp3 = Xtime8 (state) Tmp4 = Tmpl+Tmp2+Tmp3 Tmp2 = state+Tmp2+Tmp3 Tmpl = state+Tmpl+Tmp3 Tmp3 = state+tmp3 Tmpl = RotWord (Tmpl) Tmp2 = RotWord (RotWord (Tmp2) ) Tmp3= RotWord (RotWord (RotWord (Tmp3) ) State = Tmpl + Tmp2 + Tmp3 + Tmp4. wherein Tmpl, Tmp2, Tmp3, and Tmp4 is a content of a first, second, third, and fourth temporal register, respectively, state is a content of a state data register, RotWord is a word rotation function, and Xtime is an operation defined as follows : Xtime (state) = ( (state&m2)« 1) + (((state &ml)»7)*m3, wherein ml = 0x8080...80, m2 = 0x7f7f...7f, and m3 = Oxlb. 22. Apparatus as claimed in claim 21, in which AND operations are performed by the CPU 12. 23. Method for performing a cryptographic algorithm including a sequence of steps, one step including a mix column transformation (208) on mix columns input data to obtain mix columns output data, the mix columns input data having an array of data groups, the array having a predetermined number of columns, a column having a plurality of data groups and a data group including a number of data units, comprising the following steps: providing the mix columns input data; and performing at least a part of the mix columns transformation on the mix columns input data, using an arithmetic unit arranged for conducting calculations for a number of data units in parallel, the number of data units being equal to or greater than the number of data units of a column. 24. Method for performing decryption in accordance with a cryptographic algorithm including a sequence of steps, one step including an inverse mix columns transformation on inverse mix columns input data to obtain inverse mix columns output data, the inverse mix columns input data having an array of data groups, the array having a predetermined number of columns, a column having a plurality of data groups, and a data group including a number of data units, comprising the following steps: providing the inverse mix columns input data; and performing at least a part of the inverse mix column transformation on the inverse mix columns input data using an arithmetic unit arranged for conducting calculations for a number of data units in parallel, the number of data units being equal to or greater than the number of data units of a column.

Inventors: SEIFERT JEAN-PIERRE, VALVERDE ANTONIO, SEIFERT, JEAN-PIERRE, VALVERDE, ANTONIO
Applicants: INFINEON TECHNOLOGIES AG, SEIFERT JEAN-PIERRE, VALVERDE ANTONIO, SEIFERT, JEAN-PIERRE, VALVERDE, ANTONIO
Application year: 2001
Main classification: G06F9
IPC codes: G06F9, H04L9