DUAL-CONFIGURABLE PRINT HEAD ADDRESSING

Abstract: An ink jet print head (20) is controllable based at least in part on q number of first control signals and p number of second control signals. The print head (20) includes a print head integrated circuit chip (22) having ink-heating resistors for generating heat when activated. The print head chip (22) also has a switching circuit for receiving the first and second control signals, and for selectively activating the resistors by allowing electrical current to flow through selected resistors based at least in part on the first and second control signals. The switching circuit is operable in either a first operating mode or a second operating mode, where q is equivalent to q1 in the first operating mode, and is equivalent to q2 in the second operating mode, where q1 is twice q2. In the first operating mode, p is equivalent to p1, and in the second operating mode, p is equivalent to p2, where p2 is twice p1. The product of q1 multiplied by p1 is equivalent to the product of q2 multiplied by p2. The print head (20) also includes an operating mode selection circuit connected to the print head integrated circuit (20). The configuration of the operating mode selection circuit determines whether the switching circuit operates in the first operating mode or second operating mode.

Description: DUAL-CONFIGURABLE PRINT HEAD ADDRESSING FIELD OF THE INVENTION The present invention is generally directed to ink jet printers. More particularly, the invention is directed to an ink jet print head integrated circuit chip that supports two different drive schemes to provide two different levels of performance at two different printer costs. BACKGROUND OF THE INVENTION Ink jet printers form images on a print medium by ejecting droplets of ink from nozzles in a print head as the print head translates across the print medium. The nozzles are generally arranged in one or more columns that are aligned orthogonal to the direction of translation of the print head. Ink is ejected from a selected nozzle when an ink-heating resistor associated with the selected nozzle is activated based on print control signals. Generally, in a three-dimensional nozzle addressing scheme, nozzle selection is based upon a combination of three sets of control signals. These control signals are typically carried from printer controller electronics to contacts on the print head by way of a flexible wiring harness. These signals are carried from the print head contacts to the print head integrated circuit chip by way of a tape automated bonding (TAB) circuit, with each control signal in the three sets of signals being carried by a separate metal conductor in the TAB circuit. These metal conductors in the TAB circuit and the corresponding conductors in the flexible wiring harness represent a significant portion of the total cost of an ink j et printer. In the past, print head integrated circuit designs have supported a single print head drive scheme which provided a single print resolution and print speed as determined by the layout of the integrated circuit chip. This limits the usefulness of the chip design to a narrow performance range. Since conventional print head integrated circuit chip designs have been limited to a single drive scheme, the number of control lines that connect the chip to the printer electronics have also been limited to a particular number. Thus, achieving a different printer cost by changing the number of control lines has in the past required a completely different print head chip design. Therefore, a single print head integrated circuit chip that supports more than one cost/performance design point is needed. SUMMARY OF THE INVENTION The foregoing and other needs are met by an ink jet print head which is controllable based at least in part on q number of first control signals and p number of second control signals. The print head includes a print head integrated circuit chip having ink-heating resistors for generating heat when activated. The print head chip also has a switching circuit for receiving the first and second control signals, and for selectively activating the ink-heating resistors by allowing electrical current to flow through selected ink-heating resistors based at least in part on the first and second control signals. The switching circuit is operable in either a first operating mode or a second operating mode, where q is equivalent to q in the first operating mode, and is equivalent to qi in the second operating mode, and where q \ is greater than q 2 . In a most preferred embodiment, q \ is twice # 2 . In the first operating mode, p is equivalent to p \ , and in the second operating ode,ρ is equivalent to j p 2 , where ρ 2 is greater than p \ . Most preferably P 2 is twice pi. In the most preferred embodiment, the product of q \ multiplied by p \ in the first operating mode is equivalent to the product of # 2 multiplied by p 2 in the second operating mode. The print head also includes an operating mode selection circuit connected to the print head integrated circuit. The operating mode selection circuit determines, based on a configuration of the operating mode selection circuit, whether the switching circuit operates in the first operating mode or the second operating mode. In the first operating mode, the print head requires four passes across a print medium to completely print an image, while in the second operating mode, the print head requires only two passes. Thus, a print head implemented according to the second operating mode offers a higher performance design point. However, a print head implemented according to the first operating mode is less expensive to manufacture. Therefore, the invention provides a single print head integrated circuit chip which may be used for two different cost/performance design points, the selection of which depends upon the configuration of the operating mode selection circuit. BRIEF DESCRIPTION OF THE DRAWINGS Further advantages of the invention will become apparent by reference to the detailed description of preferred embodiments when considered in conjunction with the drawings, which are not to scale, wherein like reference characters designate like or similar elements throughout the several drawings as follows: Fig. 1 is a functional block diagram of an ink jet printer according to a preferred embodiment of the invention; Fig. 2 depicts an ink jet print head according to a preferred embodiment of the invention; Figs. 3A and 3B depict TAB circuit conductor configurations according to a preferred embodiment of the invention; Figs. 4A and 4B depict a configuration of ink-heating resistors on a print head chip according to a preferred embodiment of the invention; Figs. 5A-5H are schematic diagrams that collectively show ink-heating resistors and resistor selection circuitry on a print head chip according to a preferred embodiment of the invention; and Figs. 6A and 6B depict control signal timing diagrams according to a preferred embodiment of the invention. DETAILED DESCRIPTION OF THE INVENTION Shown in Fig. 1 is a functional block diagram of an ink jet printer 10 for printing an image 12 on a print medium 14. The printer 10 includes a printer controller 16, such as a digital microprocessor, that receives image data from a host computer 18. Generally, the image data generated by the host computer 18 describes the image 12 in a bit-map format. Such a format represents the image 12 as a collection of pixels, or picture elements, in a two-dimensional rectangular coordinate system. For each pixel, the image data indicates the rectangular coordinates of the pixel on the print medium 14 and whether the pixel is on or off (printed or not printed). Typically, the host computer 18 "rasterizes" the image data by dividing the image 12 into horizontal rows of pixels, stepping from pixel-to-pixel across each row, and writing out the image data for each pixel according to each pixel's order in the row. Based on the image data from the host computer 18, the printer controller 16 generates print control signals. In the preferred three-dimensional addressing system of the present invention, these control signals include first, second, and third control signals. The first, second, and third control signals are also referred to herein as quad select signals, address signals, and primitive signals. As shown in Figs. 1 and 2, the printer 10 includes a print head 20 that receives the print control signals from the printer controller 1 . On the print head 20 is a thermal ink jet integrated circuit chip 22 covered by a nozzle plate. Within the nozzle plate are nozzles situated in a dual-columnar nozzle array. Based on the print control signals from the printer controller 16, ink droplets are ejected from selected nozzles to form dots on the print medium 14 corresponding to the pixels in the image 12. Ink is selectively ejected from a nozzle when a corresponding ink-heating resistor on the chip 22 is activated by the print control signals from the controller 16. With reference to Fig. 1, the printer 10 includes a print head scanning mechanism 24 for scanning the print head 20 across the print medium 14 in a scanning direction as indicated by the arrow 26. Preferably, the print head scanning mechanism 24 consists of a carriage which slides horizontally on one or more rails, a belt attached to the carriage, and a motor that engages the belt to cause the carriage to move along the rails. The motor is driven in response to the scan commands generated by the printer controller 16. The printer 10 also includes a print medium advance mechanism 28. Based on print medium advance commands generated by the controller 16, the print medium advance mechanism 28 causes the print medium 14 to advance in a paper advance direction, as indicated by the arrow 30, between consecutive scans of the print head 20. Thus, the image 12 is formed on the print medium 14 by printing multiple adjacent swaths as the print medium 14 is advanced in the advance direction between swaths. In a preferred embodiment of the invention, the print medium advance mechanism 28 is a stepper motor rotating a platen which is in contact with the print medium 14. As shown in Fig. 1, the print control signals are preferably communicated to the print head 20 by way of three sets of control lines, Q, P, and A, included in a wiring harness 31. A first set of control lines (designated by Q) communicate q number of quad select signals, a second set of control lines (designated by A) communicate n number of address signals, and a third set of control lines (designated by P) communicate p number of primitive signals. As described in more detail herein, the values of q, n, andp, and the corresponding number of control lines in each set depends upon the selected performance/cost design point of the printer 10. Attached to the print head 20 is a tape automated bonding (TAB) circuit 32, preferably formed on a flexible substrate of polyimide tape. The print head integrated circuit chip 22 is attached within a window of the TAB circuit 32. The flexible nature of the TAB circuit 32 provides for bending the TAB circuit 32 around a corner 34 of the print head 20, as shown in Fig. 2. Electrical connection between the TAB circuit 32 and the control lines Q, P, and A in the printer 10 is provided by a set of TAB contacts 36 on the TAB circuit 32. Electrical connection between the TAB contacts 36 and the chip 22 is provided by a set of conductors that are formed on the substrate material of the TAB circuit 32. The position of the conductors is represented in Fig. 2 by the dotted outline region 38. Generally, there is a separate conductor electrically connecting each TAB contact 36 to a corresponding contact on the chip 22. As described in more detail hereinafter, the number of these conductors on the TAB circuit 32 and in the wiring harness 31 depends upon the selected performance/cost design point of the printer 10. Figs. 3 A and 3B depict a preferred layout of the print head chip 22. Along the two longest edges of the chip 22 are electrical contacts 40 that provide connection points for the conductors on the TAB circuit 32. Preferably, these chip contacts 40 include q number of first electrical contacts, also referred to herein as quad select contacts CQ1- CQ4, n number third electrical contacts, also referred to herein as of address contacts CA1-CA10, and p 2 number of second electrical contacts, also referred to herein as primitive contacts CP1-CP16. In the preferred embodiment of the invention, q\ is four, n is ten, and j_> is sixteen. Preferably, an ink via 42 is situated near the center of the chip 22. On either side of the ink via 42 are chip regions 44a and 44b in which are located the ink-heating resistors and selection logic devices. Fig. 3 A further depicts a configuration of conductors connected to the contacts 40 to implement a first operating mode of the printer 10, and the Fig. 3B further depicts a configuration of conductors connected to the contacts 40 to implement a second operating mode. These conductors on the TAB circuit 32 comprise an operating mode selection circuit, the configuration of which determines the operating mode in which the print head chip 22 will function and the performance/cost point of the printer 10. Possible configurations of these conductors, and their effect on the operation of the printer 10, are described in more detail hereinafter. The preferred embodiment of the invention includes three-hundred-twenty (320) ink-heating resistors R1-R320. As depicted in Fig. 4, the resistors R1-R320 are preferably thin-film resistors arranged on the chip 22 in two main columns 46a and 46b, with each column 46a and 46b having eight sets of twenty resistors per set. Fig. 4A depicts the bottom half and Fig. 4B depicts the top half of the columns 46a and 46b. The column 46a, which includes the resistors R1-R160, is disposed within the region 44a (see Figs. 3A-B), and the column 46b, which includes the resistors R161-R320, is disposed within the region 44b. Preferably, the column 46a is vertically offset from the column 46b by one-half the vertical spacing between resistors. In the preferred embodiment, this vertical offset is Vβoo inch. The sixteen sets of resistors are each divided into two horizontally-separated sub- columns, with ten resistors in each sub-column. In the preferred embodiment, the horizontal offset between sub-columns within a set is V 120 o inch. Preferably, the ten resistors within each sub-column are vertically aligned and separated by 15 0 inch. As shown in Figs. 4A and 4B, the two sub-columns within each set are vertically offset from one another by one-half the spacing between heaters within a sub-column. In the preferred embodiment, this vertical offset is V 300 inch. Preferably, vertically-adjacent sets are horizontally offset from one another by twice the horizontal spacing between sub-columns. In the preferred embodiment, this horizontal offset is Vβoo inch. Thus, as shown in Figs. 4A and 4B, alternating sets within each column 46a and 46b are vertically aligned. Figs. 5A-5H collectively depict a schematic diagram of the preferred embodiment of circuitry on the print head chip 22. This circuitry includes the ink-heating resistors R1-R320 and switching circuits which provide for selection and activation of individual resistors R1-R320 based on the quad select signals on the quad select signal lines Q1-Q4, address signals on the address signal lines A1-A10, and primitive signals on the primitive signal lines PI -PI 6. The switching circuits include first, second, and third switching devices, also referred to herein as pass-gate devices PG1-PG320, power driver devices D1-D320, and pull-down devices PD1-PD320, respectively. Preferably, the pass-gate devices PG1-PG320 and the pull-down devices PD1-PD320 are JFETs, and the power driver devices D1-D320 are NMOS power transistors. Each of the ink-heating resistors R1-R320 has a high side that is connected to one of the primitive signal lines PI -PI 6 and a low side that is connected to a second high- side input, preferably the drain, of an associated one of the power driver devices Dl- D320. Each of the power driver devices D1-D320 has a second low-side output, preferably the source, which is connected to a common ground return. The gate of each of the power driver devices D1-D320 serves as a second control input. In the preferred embodiment, when a control signal on the gate of a power driver D1-D320 is high, the power driver D1-D320 is "on", acting like a closed switch. Thus, when a power driver D1-D320 is "on", the low side of the associated ink-heating resistor R1-R320 is grounded. When the primitive signal goes high on the associated one of the primitive signal lines P1-P16 while the associated power driver D1-D320 is "on", current flows through the associated ink-heating resistor Rl -R320. This current causes the resistor Rl - R320 to dissipate energy in the form of heat that is transferred to ink that is adjacent the surface of the resistor R1-R320. Whether the gate of a power driver D1-D320 is high, and thus whether the power driver D1-D320 is "on", depends on the states of the quad select signal on the associated quad select signal line Q1-Q4 and the address signal on the associated address signal line A1-A10. As shown in Figs. 5A-5H, one of the quad select signal lines Q1-Q4 is connected to a first control input, preferably the gate, of each of the pass-gate devices PG1-PG320. When the quad select signal on the gate is high, the pass-gate device PG1- PG320 is "on" and thus acts like a closed switch. One of the address lines A1-A10 is connected to a first high-side input, preferably the drain, of each of the pass-gate devices PG1-PG320. The pass-gate devices PG1-PG320 each have a first low-side output, preferably the source, that is connected to the gate of the associated power driver Dl- D320. When a pass-gate device PG1-PG320 is "on" (quad select signal is high), the address signal on the drain of the pass-gate device PG1-PG320 passes to the gate of the associated power driver D1-D320. Therefore, in the preferred embodiment, when the quad select signal at the gate and the address signal at the drain of a pass-gate device PG1-PG320 are both high, the associated power driver D1-D320 is "on". As shown in Figs. 5A-5H, associated with each power driver D1-D320 is a pulldown device PD1-PD320. The high-side input, preferably the drain, of each pull-down device PD1-PD320 is connected to the gate of a corresponding power driver D1-D320, and the low-side output, preferably the source, of each pull-down device PD1-PD320 is connected to the common ground return. Thus, when a pull-down device PD1-PD320 is "on", the gate of the corresponding power driver D1-D320 is grounded. Therefore, when a pull-down device PD1-PD320 is "on", the corresponding power driver D1-D320 is "off. The purpose and function of the pull-down devices PD1-PD320 according to one of the operational modes of the print head chip 22 is described in more detail hereinafter. As shown in Fig. 5 A, the resistors R1-R20 are connected to the primitive line PI, and the resistors R161-R180 are connected to the primitive line P2. For convenience of discussion, all of the devices that are connected to the primitive line PI are referred to as a first primitive group, and all of the devices that are connected to the primitive line P2 are referred to as a second primitive group. The primitive lines PI and P2 are connected to the primitive contacts CP1 and CP2, respectively. The gates of the odd-numbered pass-gate devices PG1-PG19 and PG161-PG179 are connected to the quad select line Ql, and the gates of the even-numbered pass-gate devices PG2-PG20 and PG162-PG180 are connected to the quad select line Q2. For convenience of discussion, all of the devices that are connected to the quad select line Ql are referred to as a first quad group, and all of the devices that are connected to the quad select line Q2 are referred to as a second quad group. The gates of the odd-numbered pull-down devices PD1-PG19 and PD161-PG179 are connected to the pull-down signal line Q2P, and the gates of the even-numbered pulldown devices PD2-PD20 and PD162-PD180 are connected to the pull-down signal line Q1P. As shown in Fig. 5B, the resistors R21-R40 are connected to the primitive line P3, and the resistors R181-R200 are connected to the primitive line P4. For convenience of discussion, all of the devices that are connected to the primitive line P3 are referred to as a third primitive group, and all of the devices that are connected to the primitive line P4 are referred to as a fourth primitive group. The primitive lines P3 and P4 are connected to the primitive contacts CP3 and CP4, respectively. The gates of the odd-numbered pass-gate devices PG21-PG39 and PG181-PG199 are connected to the quad select line Q3, and the gates of the even-numbered pass-gate devices PG22-PG40 and PG182-PG200 are connected to the quad select line Q4. For convenience of discussion, all of the devices that are connected to the quad select line Q3 are referred to as a third quad group, and all of the devices that are connected to the quad select line Q4 are referred to as a fourth quad group. The gates of the odd-numbered pull-down devices PD21-PG39 and PD181- PG199 are connected to the pull-down signal line Q4P, and the gates of the even- numbered pull-down devices PD22-PD40 and PD182-PD200 are connected to the pull- down signal line Q3P. Preferably, each of the ten address lines A1-A10 in the address bus A is connected to the drain of one odd-numbered and one even-numbered pass-gate device in each primitive group. The pattern of device connections shown in Figs. 5A and 5B, and described above, continue for the remaining primitive groups, as depicted in Figs. 5C-5H. For each of the remaining primitive groups, the primitive lines P5-P16 are connected to the primitive contacts CP5-CP16, respectively. As shown in Figs. 5G and 5H, the quad select signal lines Q1-Q4 are connected to the quad select contacts CQ1-CQ4, the pulldown signal lines Q1P-Q4P are connected to the pull-down contacts CQ1P-CQ4P, and the address signal lines A1-A10 are connected to the address contacts CA1-CA10. Tables I, II, III, and IN below correlate resistor numbers to quad select, primitive, and address signal lines. Table I. Table II. Table III. Table IN. As indicated by Figs. 5A-5H, each of the sixteen (p 2 ) primitive groups of twenty (q 2 x n = 2 x 10) ink-heating resistors is connected to a distinct one of the sixteen primitive lines LP1-LP16, which are brought out to sixteen corresponding primitive contacts CP1-CP16 on the chip 22. Thus, each of the sixteen primitive groups on the chip 22 is independently addressable by a primitive signal from the printer controller 16. Similarly, each of the four ( q ) quad select groups of eighty (pi x n = 8 x 10) ink-heating resistors is connected to a distinct one of the four quad select lines LQ1-LQ4, which are brought out to four corresponding quad select contacts CQ1-CQ4 on the chip 22. Therefore, each of the four quad select groups on the chip 22 is independently addressable by a quad select signal from the printer controller 16. In other words, each primitive group on the chip 22 may be addressed independently of any other primitive group, and each quad select group may be addressed independently of any other quad select group. One skilled in the art will appreciate, that the chip 22 provides more independently-addressable primitive groups and quad select groups than are necessary to address 320 resistors. In fact, 640 resistors could be addressed with the sixteen primitive lines, four quad select lines, and ten address lines provided on the chip 22. However, as described in greater detail below, these extra signal lines are provided so that the printer 10 maybe manufactured to operate at either one of two different cost/performance design points using a single print head chip design. Referring again to Fig. 3 A, a first configuration of conductors on the TAB circuit 32 is shown for selecting the first operating mode of the print head chip 22. In this first configuration, quad select conductors LQ1, LQ2, LQ3, and LQ4 on the TAB circuit 32 are connected to the corresponding quad select contacts CQ1, CQ2, CQ3, and CQ4 on the chip 22, primitive conductors LP3, LP4, LP7, LP8, LP11, LP12, LP15, and LP16 on the TAB circuit 32 are connected to the corresponding primitive contacts CP3, CP4, CP7, CP8, CPU, CP12, CP15, and CP16 on the chip 22, and address conductors LA1- LA10 on the TAB circuit 32 are connected to the corresponding address contacts CA1- CA10 on the chip 22. Pull-down jumper conductors JQ1P, JQ2P, JQ3P, and JQ4P on the TAB circuit 32 short the quad select conductors LQ1, LQ2, LQ3, and LQ4 to the corresponding pull-down contacts CQ1P, CQ2P, CQ3P, and CQ4P on the chip 22. Primitive jumper conductors JP1, JP2, JP5, JP6, JP9, JP10, JP13, and JP14 on the TAB circuit 32 short the primitive contacts CP1, CP2, CP5, CP6, CP9, CP10, CP13, and CP14 to the primitive conductors LP3, LP4, LP7, LP8, LP11, LP12, LP15, and LP16, respectively. Thus, the configuration of TAB circuit conductors shown in Fig. 3A shorts primitive signal lines PI to P3, P2 to P4, P5 to P7, P6 to P8, P9 to PI 1, P10 to P12, P13 to PI 5, and P14 to P16. In this manner, the number of independently-addressable primitive groups is reduced from sixteen to eight, with forty (q \ x n = 4 x 10) of the ink- heating resistors R1-R320 in each of the eight primitive groups. This provides an addressing scheme of eight primitive signals (p =p\ = 8), four quad select signals (q = q\ = 4), and ten address signals (n = 10), for a total of twenty-two control signals that must be communicated from the printer controller 16 to the chip 22. Thus, in the first implementation of the TAB circuit 32, only twenty-two control signal conductors are needed in the wiring harness 31 and only twenty-two control signal contacts 36 are needed on the TAB circuit 32. Therefore, this first implementation significantly reduces the cost of the printer 10. Fig. 6A is a timing diagram depicting the preferred signal timing scheme when the print head chip 22 is addressed in the first operating mode. As shown in Fig. 6A, the quad select signals on the quad select lines Q1-Q4 are high during sequential quad select windows 46a-46d. Preferably, each quad select window 46a-46d endures for approximately 31.245 μs. During each quad select window 46a-46d, each of the address signals on the address lines A1-A10 go high within sequential address windows 48 of approximately 2.6 μs duration. During any address window 48, the printer controller 16 may drive any or all of the primitive signals high on the eight primitive lines PI, P2, P5, P6, P9, P10, PI 3, and P14 as determined by the image data. Thus, in this first operating mode, there are forty (qϊ n = 4 x 10) groups of resistors that are enabled sequentially as the print head 20 scans across the print medium 14, and the eight (pi = 8) resistors in any one of these forty groups may be activated simultaneously when the group is enabled. Since the quad select signal conductor LQ1 on the TAB circuit 32 is shorted to the pull-down contact CQ1P, the gates of all of the even-numbered pull-down devices PD2-PD20 and PD162-PD180 are high during the quad select window 46a. Thus, the power drivers PD2-PD20 and PD162-PD180 in the second quad group are "off during the quad select window 46a. Also, since the quad select signal conductor LQ2 on the TAB circuit 32 is shorted to the pull-down contact CQ2P, the gates of all of the odd- numbered pull-down devices PD1-PD19 and PD161-PD179 are high during the quad select window 46b. Thus, the power drivers PD1-PD19 and PD161-PD179 in the first quad group are "off during the quad select window 46b. Although not shown in the schematic, Ql and Q2 may be connected to additional pull down devices such that the power devices PD21-PD40 and PD181-PD200 are "off during quad select windows 46a and 46b. Similarly, because the quad select signal conductor LQ3 is shorted to the pulldown contact CQ3P, the gates of all of the even-numbered pull-down devices PD22- PD40 and PD182-PD200 are high during the quad select window 46c. Thus, the power drivers PD22-PD40 and PD182-PD200 in the third quad group are "off during the quad select window 46c. Further, since the quad select signal conductor LQ4 is shorted to the pull-down contact CQ4P, the gates of all of the odd-numbered pull-down devices PD21- PD39 and PD181-PD199 are high during the quad select window 46d. Thus, the power drivers PD21-PD39 and PD181-PD199 in the fourth quad group are "off during the quad select window 46d. Although not shown in the schematic, Q3 and Q4 may be connected to additional pull down devices such that the power devices PD1-PD20 and PD161-PD180 are "off during quad select windows 46c and 46d. The signal transitions shown in Fig. 6A occur as the print head scanning mechanism 24 scans the print head 20 across the print medium 14 from right to left. As the print head 20 scans from left to right, the order of the quad select window transitions is reversed: first Q4 is high, then Q3, Q2, and Ql. In the preferred embodiment of the invention, the scan speed of the print head 20 in the first operating mode is approximately 26.67 inch/second. Thus, during one address window 48, the print head 20 travels approximately 6.93 x 10 "5 inch in the scan direction. During one quad select window 46a-46d, the print head 20 travels approximately 8.33 x 10 "4 (V 120 o) inch. This means that the print head 20 travels 4 / 1200 (V 300 ) inch during the time required to address all of the resistors R1-R320. Preferably, in the first operating mode, the ink droplets are deposited on the print medium 14 in a checkerboard pattern to allow for the fastest possible drying of the ink. Preferably, the invention uses two ink droplets to fill a V 6 o 0 inch diameter spot on the print medium 14. This is referred to as a four-pass implementation, since four passes of the print head 20 across the print medium 14 are required to fill all possible print positions in a print swath. Shown in Fig. 3B is a second configuration of conductors on the TAB circuit 32 for implementing the second operating mode of the print head chip 22. In this second configuration, the quad select conductors LQ1 and LQ2 on the TAB circuit 32 are connected to the corresponding quad select contacts CQ1 and CQ2 on the chip 22, the primitive conductors LP1-LP16 on the TAB circuit 32 are connected to the corresponding primitive contacts CP1-CP16 on the chip 22, and the address conductors LAI -LA 10 on the TAB circuit 32 are connected to the corresponding address contacts CA1-CA10 on the chip 22. The pull-down contacts CQ1P, CQ2P, CQ3P, and CQ4P on the chip 22 are connected to the common ground return. Quad select jumper conductors JQ3 and JQ4 on the TAB circuit 32 short the quad select contacts CQ3 and CQ4 to the quad select conductors LQ1 and LQ2, respectively. Thus, the configuration of TAB circuit conductors shown in Fig. 3B shorts quad select signal lines Ql to Q3 and Q2 to Q4. In this manner, the number of independently- addressable quad select groups is reduced from four to two, with 160 (p x n = 16 x 10) of the ink-heating resistors R1-R320 in each of the eight quad select groups. This provides an addressing scheme of sixteen primitive signals (p =p 2 = 16), two quad select signals (q = q 2 = 2), and ten address signals (n = 10), for a total of twenty-eight control signals communicated from the printer controller 16 to the chip 22. Fig. 6B is a timing diagram depicting the preferred signal timing scheme when the print head chip 22 is addressed in the second operating mode. As shown in Fig. 6B, the quad select signals on the quad select lines Ql and Q3 are high simultaneously during quad select windows 50a. Subsequently, the quad select signals on the quad select lines Q2 and Q4 are high simultaneously during quad select windows 50b. Preferably, each quad select window 50a-50b endures for approximately 41.67 μs. During each quad select window 50a-50b, each of the address signals on the address lines A1-A10 go high within sequential address windows 52 of approximately 3.47 μs duration. During any address window 52, the printer controller 16 may drive any or all of the primitive signals high on the sixteen primitive lines PI -PI 6 as determined by the image data. Thus, in this second operating mode, there are twenty (q 2 x n = 2 x 10) groups of resistors that are enabled sequentially as the print head 20 scans across the print medium 14, and the sixteen resistors in any one of these twenty groups may be activated simultaneously when the group is enabled. hi the preferred embodiment of the invention, the scan speed of the print head 20 in the second operating mode is approximately 20.0 inch/second. Thus, during one address window 52, the print head 20 travels approximately 6.93 x 10 "5 inch in the scan direction. During one quad select window 50a-50b in the second operating mode, the print head 12 travels approximately the same distance (V 12 o 0 inch) as during one quad select window 46a-46d in the first operating mode. However, in the second operating mode, all of the resistors R1-R320 may be addressed in during the time required for the print head 20 to travels 2 / 1200 (or βoo ) inch. Thus, the second operating mode requires only two passes of the print head 20 across the print medium 14 to fill all possible print positions in a print swath. Therefore, the invention operating in the second operating mode prints much faster than when operating in the first mode. However, the second implementation is more expensive to manufacture due to the larger number of primitive lines PI -PI 6. It is contemplated, and will be apparent to those skilled in the art from the preceding description and the accompanying drawings that modifications and/or changes may be made in the embodiments of the invention. Accordingly, it is expressly intended that the foregoing description and the accompanying drawings are illustrative of preferred embodiments only, not limiting thereto, and that the true spirit and scope of the present invention be determined by reference to the appended claims.

Claims: CLAIMS 1. An ink jet print head for use in an ink jet printing device, the print head controllable based at least in part on q number of first control signals and p number of second control signals, the print head comprising: a print head integrated circuit chip having: ink-heating resistors for generating heat when activated; and a switching circuit for receiving the first and second control signals, and for selectively activating the ink-heating resistors by allowing electrical current to flow through selected ink-heating resistors based at least in part on the first and second control signals, the switching circuit operable in either a first operating mode or a second operating mode, where q is equivalent to q \ in the first operating mode, where q is equivalent to q 2 in the second operating mode, where q \ is equivalent to twice q , where p is equivalent to p \ in the first operating mode, where p is equivalent top 2 in the second operating mode, where p 2 is equivalent to twice p \ , and where the product of q \ multiplied by p \ in the first operating mode is equivalent to the product of q 2 multiplied by p 2 in the second operating mode; and operating mode selection means connected to the print head integrated circuit for determining, based on a configuration of the operating mode selection means, whether the switching circuit operates in the first operating mode or the second operating mode. 2. The ink jet print head of claim 1 further controllable based at least in part on n number of third control signals, wherein the print head integrated circuit chip further comprises: at least q \ multiplied by p \ multiplied by n number of the ink-heating resistors; and the switching circuit further for receiving the third control signals, and for selectively activating the ink-heating resistors by allowing electrical current to flow through selected ink-heating resistors based at least in part on the third control signals, where the value of n in the first operating mode is equivalent to the value of n in the second operating mode. 3. The ink j et print head of claim 2 wherein: the ink-heating resistors further comprise q\ x n number of groups of ink-heating resistors, each group including p \ number of ink-heating resistors that may be simultaneously activated; and the switching circuit is operable in the first operating mode to sequentially enable activation of each of the q\ x n number of groups based on the first and third control signals, and for activating any one of the ink-heating resistors within an enabled group based on the second control signal. 4. The ink j et print head of claim 2 wherein: the ink-heating resistors further comprise q 2 x n number of groups of ink-heating resistors, each group including p 2 number of ink-heating resistors that may be simultaneously activated; and the switching circuit is operable in the second operating mode to sequentially enable activation of each of the q 2 x n number of groups based on the first and third control signals, and for activating any one of the ink-heating resistors within an enabled group based on the second control signal. 5. The ink jet print head of claim 2, wherein the switching circuit further comprises: q \ number of first electrical contacts for receiving the first control signals; p number of second electrical contacts for receiving the second control signals; and n number of third electrical contacts for receiving the third control signals. 6. The ink jet print head of claim 5, wherein the operating mode selection means fiirther comprise an interconnection circuit for providing electrical connections between the ink jet printing device and the switching circuit on the print head integrated circuit, the interconnection circuit having: 5 first conductive lines for providing electrical connection between the ink jet printing device and at least some of first electrical contacts; second conductive lines for providing electrical connection between the ink jet printing device and at least some of the second electrical contacts; jumper lines for shorting some of the second electrical contacts together in the 0 first operating mode; and at least n number of third conductive lines for providing electrical connection between the ink jet printing device and the at least n number of third electrical contacts. 7. The ink jet print head of claim 5, wherein the operating mode selection means further comprise an interconnection circuit for providing electrical connections between the ink jet printing device and the switching circuit on the print head integrated circuit, the interconnection circuit having: s first conductive lines for providing electrical connection between the ink jet printing device and at least some of first electrical contacts; second conductive lines for providing electrical connection between the ink jet printing device and at least some of the second electrical contacts; jumper lines for shorting some of the first electrical contacts together in the o second operating mode; and at least n number of third conductive lines for providing electrical connection between the ink jet printing device and the at least n number of third electrical contacts. 8. The ink jet print head of claim 6, wherein the interconnection circuit further comprises: at least q \ number of the first conductive lines for providing electrical connection between the ink jet printing device and the at least q\ number of the first electrical 5 contacts; at least p \ number of the second conductive lines for providing electrical connection between the ink jet printing device and a first half of the p 2 number of the second electrical contacts; and at least j?! number of the jumper lines for shorting the at least p \ number of the 0 second conductive lines to a second half of the p 2 number of the second electrical contacts. 9. The ink jet print head of claim 7, wherein the interconnection circuit further comprises: at least p 2 number of the second conductive lines for providing electrical connection between the ink jet printing device and the at least p number of the first s electrical contacts; at least q 2 number of the first conductive lines for providing electrical connection between the ink jet printing device and a first half of the q \ number of the first electrical contacts; and at least q number of the jumper lines for shorting at least q number of the first o conductive lines to a second half of the q\ number of the first electrical contacts. 10. The ink jet print head of claim 6, wherein the interconnection circuit further comprises a flexible tape automated bonding (TAB) circuit, and the first, second, third, and jumper conductive lines further comprise conductive metal traces in the TAB circuit. 11. The ink jet print head of claim 7, wherein the interconnection circuit further comprises a flexible tape automated bonding (TAB) circuit, and the first, second, third, and jumper conductive lines further comprise conductive metal traces in the TAB circuit. 12. The ink jet print head of claim 2, where q\ is four, p\ is eight, and n is ten in the first operating mode. 13. The ink jet print head of claim 2, where q 2 is two, p 2 is sixteen, and n is ten in the second operating mode. 14. The ink j et print head of claim 5 further comprising: at least q \ multiplied by p \ multiplied by n number of the ink-heating resistors, each ink-heating resistor having a high side for receiving one of the second control signals, and a low side; and the switching circuit having: at least qι multiplied by p\ multiplied by n number of first switching devices, each first switching device associated with a corresponding one of the ink- heating resistors, each first switching device having a first control input for receiving one of the first control signals, a first high-side input for receiving one of the third control signals, and a first low-side output; and at least q \ multiplied by p\ multiplied by n number of second switching devices, each second switching device associated with a corresponding one of the first switching devices and associated with a corresponding one of the ink-heating resistors, each second switching device having a second high-side input connected to the low side of an associated ink-heating resistor, a second control input connected to the first low- side output of an associated first switching device, and a second low-side output connected to a common ground return. 15. The ink j et print head of claim 14 wherein: the first switching devices are field effect transistors having a first gate, a first source, and a first drain, the first gate being the first control input, the first drain being the first high-side input, and the first source being the first low-side output; and the second switching devices are power field effect transistors having a second gate, a second source, and a second drain, the second gate being the second control input, the second drain being the second high-side input, and the second source being the second low-side output. 16. The ink jet print head of claim 15 wherein any one of the ink-heating resistors is activated by an electrical current flowing through the resistor when the first control signal is high on the first gate of the corresponding first switching device, the second control signal is high on the high side of the resistor, and the third control signal is high on the first drain of the first switching device. 17. The ink jet print head of claim 6 wherein the print head integrated circuit further comprises: q \ number of select groups of ink-heating resistors corresponding to the q\ number of first electrical contacts, each select group consisting x n number of ink- heating resistors, each select group being independently addressable by one of the q \ number of first control signals; and p 2 number of primitive groups corresponding to the p number of second electrical contacts, each primitive group consisting of q 2 x n number of ink-heating resistors, each primitive group being independently addressable by one of Haap 2 number of second control signals. 16. The ink jet print head of claim 15 wherein the operating mode selection means have p\ number of jumper conductors when in the first operating mode for shorting a first half of the p 2 number of the second electrical contacts to a second half of the ? 2 number of the second electrical contacts, thereby reducing the number of primitive groups to p and increasing the number of ink-heating resistors in each of the primitive groups to q\ x n, each of the p\ number of primitive groups being independently addressable byj_> ! number of the second control signals. 17. The ink jet print head of claim 15 wherein the operating mode selection means have q number of jumper conductors when in the second operating mode for shorting a first half of the q \ number of the first electrical contacts to a second half of the qx number of the first electrical contacts, thereby reducing the number of select groups to q and increasing the number of ink-heating resistors in each of the select groups to p x n, each of the q 2 number of select groups being independently addressable by q 2 number of the first control signals. 18. An ink jet print head for use in an ink jet printing device, the print head controllable based at least in part on q number of first control signals and p number of second control signals, the print head comprising: a print head integrated circuit chip having: ink-heating resistors for generating heat when activated; and a switching circuit for receiving the first and second control signals, and for selectively activating the ink-heating resistors by allowing electrical current to flow through selected ink-heating resistors based at least in part on the first and second control signals, the switching circuit operable in either a first operating mode or a second operating mode, where q is equivalent to q \ in the first operating mode, where q is equivalent to q 2 in the second operating mode, where q \ is greater than q 2 , where p is equivalent topi in the first operating mode, where ? is equivalent to p 2 in the second operating mode, and where p 2 is greater than p\ and operating mode selection means connected to the print head integrated circuit for determining, based on a configuration of the operating mode selection means, whether the switching circuit operates in the first operating mode or the second operating mode.

Inventors: ANDERSON FRANK EDWARD, PARISH GEORGE KEITH, ANDERSON, FRANK, EDWARD, PARISH, GEORGE, KEITH
Applicants: LEXMARK INT INC, LEXMARK INTERNATIONAL, INC.
Application year: 2001
Main classification: B41J29
IPC codes: B41J2