METHOD FOR REMOVING RESIDUES WITH REDUCED ETCHING OF OXIDE

Abstract: A method for removing plasma etching-induced residues. In one embodiment, after a portion of photoresist has been used to form a polysilicon gate, the present invention provides a novel and advantageous plasma ashing environment. Specifically, in this embodiment, the present invention introduces CF4 into the plasma ashing environment. Next, the present embodiment introduces H20 vapor into the plasma ashing environment. In this embodiment, the ratio by volume of the CF4 to the H20 is in the range of from 0.1:1 to 10:1. Next, the present embodiment uses the plasma ashing environment to substantially remove polysilicon etch-induced residues without requiring an aggressive chemical strip. In so doing, the etching of the gate oxide is significantly suppressed such that a sufficient amount of the gate oxide layer remains above the underlying semiconductor substrate. Additionally, in the present invention, after the removal of the plasma etching-induced residues, the gate oxide layer is clean and enough gate oxide remains such that the thickness of the remaining gate oxide layer can be accurately and reliably measured.

Description: METHOD FOR REMOVING RESIDUES WITH REDUCED ETCHING OF OXIDE TECHNICAL FIELD The present disclosure relates to the field of semiconductor device fabrication. More specifically, the present disclosure relates to the removal or ashing of sidewall polymer material. In particular, a method for removing residues with reduced etching of oxide after gate etch using H 2 0 and CF 4 chemistries is disclosed. BACKGROUND ART During conventional semiconductor manufacturing processes, unwanted materials are formed on the semiconductor wafer and on features formed on the semiconductor wafer. Usually, these unwanted materials must be removed or etched from the semiconductor wafer. Unfortunately-, not all unwanted materials are easily removed or etched from the semiconductor wafer or the features formed on the semiconductor wafer. Referring now to Prior Art Figure 1A, a side sectional view of a semiconductor substrate 100 having a gate oxide layer 102, a polysilicon layer 104, and a portion of photoresist 106 disposed thereover is shown. In the structure of Prior Art Figure 1A, portion of photoresist 106 defines the location at which a polysilicon gate will be formed. With reference now to Prior Art Figure IB, in the prior art, polysilicon layer 104 is subjected to a plasma etch process. The plasma etch process removes polysilicon layer 104, except for the portion of polysilicon layer 104 which is covered, and, hence protected from the plasma etching proces s, by portion of photoresist 106. Although such a process is useful in forming a polysilicon gate, such a conventional process has severe drawbacks associated therewith. For example, as shown in Prior Art Figure IB, residues (e.g. residual polymer materials), typically shown as 108, are formed on portion of photoresist 106, the remaining regions of polysilicon layer 104, and the surface of gate oxide layer 102. In one prior art approach,, the structure of Prior Art Figure IB is subjected to an aggressive chemical strip (e.g. a wet acid dip such as an HF acid dip) to remove residues 108. However, plasma-exposed gate oxide, such as gate oxide layer 102, etches rapidly in HF acid. Specifically, plasma-exposed gate oxide can etch 20-40 Angstroms or more during even a brief dip in dilute HF acid. Such a problem is further exacerbated by the fact that some present fabrication processes now form gate oxides with -thicknesses of 30 Angstroms or less. In order to ensure that a requisite amount of gate oxide layer 102 is left on semiconductor substrate 100, the thickness of gate oxide.layer 102 is measured after residues 108 and portion of photoresist 106 have been removed. Referring now to Prior Art Figure 1C, a side sectional view illustrates an example wherein, after an HF dip, gate oxide layer 102 has been deleteriously etched. In Prior Art Figure 1C, due to overetching of gate oxide layer 102, portions of semiconductor substrate 100 are no longer covered by gate oxide layer 102. Hence, regions of semiconductor substrate 100 are not adequately protected during subsequent process steps. Thus, the need has arisen for a method which effectively removes plasma etching-induced residues without deleteriously and substantially attacking gate oxide. DISCLOSURE OF THE INVENTION The present invention provides a method which effectively removes plasma etching-induced residues without deleteriously and substantially attacking gate oxide. More specifically, in one embodiment, after a portion of photoresist has been used to form a polysilicon gate, the present invention provides a novel and advantageous plasma ashing environment. Specifically, in this embodiment, the present invention introduces CF4 into the plasma ashing environment. Next, the present embodiment introduces H2O vapor into the plasma ashing environment. In this embodiment, the ratio by volume of the CF4 to the H2O is in the range of from 0.1:1 to 10:1. Next, the present embodiment uses the plasma ashing environment to substantially remove polysilicon etch-induced residues without requiring an aggressive chemical strip. In so doing, the etching of the gate oxide is significantly suppressed such that a sufficient amount of the gate oxide layer remains above the underlying semiconductor substrate. Additionally, in the present invention, after the removal of the plasma etching-induced residues, the gate oxide layer is clean and enough gate oxide remains such that the thickness of the remaining gate oxide layer can be accurately and reliably measured and the silicon substrate is not exposed to environments that might attack or contaminate it. In another embodiment, the present invention provides a method for concurrently removing photoresist and residual polymers after a plasma etch of polysilicon. In this embodiment, after a portion of photoresist has been used to form a polysilicon gate, the present invention provides a novel and advantageous plasma ashing environment. Specifically, in this embodiment, the present invention introduces CF4 into the plasma ashing environment. Next, the present embodiment introduces H2O vapor into the plasma ashing environment. In this embodiment, the ratio by volume of the CF4 to the H2O is in the range of from 0.1:1 to 10:1. Then, the present embodiment introduces O2 into the plasma ashing environment. Next, the present embodiment uses the plasma ashing environment to both substantially remove polysilicon etch-induced residues and to remove remaining portions of photoresist without requiring an aggressive chemical strip. In so doing, the etching of the gate oxide is significantly suppressed such that a sufficient amount of the gate oxide layer remains above the underlying semiconductor substrate. Additionally, in the present invention, after t e removal of the plasma etching-induced residues, the gate oxide layer is clean and enough gate oxide remains such that the thickness of the remaining gate oxide layer can be accurately and reliably measured and the silicon substrate is not exposed to environments that might attack or contaminate it. Furthermore, all remaining regions of photoresist have already been removed. These and other objects and advantages of the present invention will no doubt become obvious to those of ordinary skill in the art after having read the following detailed description of the preferred embodiments which are illustrated in the various drawing figures. BRIEF DESCRIPTION OF THE DRAWINGS The accompanying drawings, which are incorporated in and form a part of this specification, illustrate embodiments of the invention and, together with the description, serve to explain the principles of the invention: PRIOR ART FIGURES 1A-1C are cross sectional views illustrating steps associated with prior art polysilicon gate formation and residue removal methods. FIGURES 2A-2D are cross sectional views illustrating a residue removal process in accordance with one embodiment of the present claimed invention. FIGURE 3 is a flow chart of steps performed in accordance with one embodiment of the present claimed invention. FIGURE 4 is a flow chart of steps performed in accordance with one embodiment of the present claimed invention. FIGURES 5A-5C are cross sectional views illustrating a residue removal process in accordance with another embodiment of the present claimed invention. FIGURE 6 is a flow chart of steps performed in accordance with one embodiment of the present claimed invention.. FIGURE 7 is a flow chart of steps performed in accordance with one embodiment of the present claimed invention. FIGURE 8 is a table of CF4/H2O and O2 plasma ashing recipes in accordance with one embodiment of the present claimed invention. It will be understood by those of ordinary skill in the art that other features and elements may be present on the semiconductor substrate but are not shown for the purpose of clarity. Additionally, the drawings referred to in this description should be understood as not being drawn to scale except if specifically noted. BEST MODE FOR CARRYING OUT THE INVENTION Reference will now be made in detail to the preferred embodiments of the invention, examples of which are illustrated in the accompanying drawings. While the invention will be described in conjunction with the preferred embodiments, it will be understood that they are not intended to limit the invention to these embodiments. On the contrary, the invention is intended to cover alternatives, modifications and equivalents, which may be included within the spirit and scope of the invention as defined by the appended claims. With reference now to Figure 2A, a cross sectional view of a semiconductor substrate 200 haying a gate oxide layer 202, a polysilicon layer 204, and a portion of photoresist 206 disposed thereover is shown. In the structure of Figure 2A, portion of photoresist 206 defines the location at which a polysilicon gate will be formed. With reference now to Figure 2B, in the present embodiment, polysilicon layer 204 is subjected to a plasma etch process. The plasma etch process removes polysilicon layer 204, except for that portion of polysilicon layer 204 which is covered, and, hence protected from the plasma etching process, by portion of photoresist 206. As shown in Figure 2B, residues (e.g. residual polymer materials), typically shown as 208, are formed on portions of photoresist 206, the remaining regions of polysilicon layer 204, and the surface of gate oxide layer 202. Referring now to Figure 2C, a side sectional view illustrates an example of the present embodiment wherein residues 208 of Figure 2C have been removed without the removal of gate oxide layer 202. Additionally, unlike the prior art, the present embodiment removes residues 208 without the need for subjecting the gate oxide layer 202 to an aggressive chemical strip. The process used in the present embodiment to remove residues 208 will be described in detail below in conjunction with Figures 3 and 4. Referring now to Figure 2D, a side sectional view illustrates an example of the present embodiment after the removal of residues 208 of Figure 2C and after the removal of portion of photoresist 206 of Figure 2C. In the present embodiment, only polysilicon gate region 204 and, gate oxide layer 202 remain disposed above semiconductor substrate 200. Furthermore, gate oxide layer 202 is now clean and can be measured to verify that gate oxide layer 202 is of a requisite thickness. With reference now to Figure 3, a flow chart 300 of steps performed in accordance with one embodiment of the present invention is shown. In the present embodiment, at step 302, a plasma etch of a polysilicon layer is performed to define the location of the polysilicon gate. As mentioned above, this process results in the formation of residues on the portion of photoresist, the remaining regions of the polysilicon layer, and the surface of gate oxide layer all of which reside above the semiconductor substrate. Additionally, as mentioned previously, conventional processes employ an aggressive chemical strip in an attempt to remove these residues. This prior art aggressive chemical strip deleteriously attacks and significantly etches the gate oxide layer. Referring next to step 304, unlike the prior art, the present embodiment then subjects the semiconductor substrate and overlying features to a plasma ashing environment to remove the residues which resulted from the plasma etching of the polysilicon layer. Hence, the present embodiment eliminates the need to subject the semiconductor substrate and overlying features (including the gate oxide layer) to a deleterious aggressive chemical strip. The precise chemistry of the ashing environment used in the step 304 of the present embodiment to remove residues 208 will be described in detail below in conjunction with Figure 4. In the present emibodiment, after the removal of the residues at step 304, the present invention proceeds to step 306. At step 306, the present embodiment removes remaining portions of photoresist (e.g. the photoresist residing above the polysilicon gate). This photoresist removal process insures that the gate oxide layer is now clean and easily measured. Referring now to step 308, after the performance of steps 302, 304, and 306, the present embodiment enables an accurate and reliable measurement of the thickness of the gate oxide layer. That is, in the present embodiment, it is possible to measure the thickness of the gate oxide layer without obtaining substantially flawed measurements associated with measuring prior to strip (because residues may be falsely measured as oxide by the measurement tool) or the use of an aggressive chemical strip (which removes a significant amount of oxide). With reference now to Figure 4, a flow chart 400 of steps performed to generate the plasma ashing environment recited in step 304 of Figure 3 is shown. After the performance of step 302 and in accordance with step 402 of Figure 4, the present embodiment generates a plasma ashing environment. More particularly, in one embodiment, the present invention introduces CF4 into a plasma ashing environment. At step 404, present embodiment, introduces H2O vapor into the plasma ashing environment such that the ratio by volume of the CF4 to the H2O is in the range of from 0.1:1 to 10:1. At step 304 of Figure 3, the present embodiment uses this plasma ashing environment to substantially remove polysilicon etch-induced residues without requiring an aggressive chemical strip. Hence, the present embodiment eliminates the need for the deleterious aggressive chemical strip of the prior art. Additionally, in one embodiment of the present invention, the aforementioned plasma ashing environment is created by introducing the CF4 at a flow rate of approximately 5-5000 standard cubic centimeters per minute (SCCM). In this embodiment, the H2O is introduced into the plasma ashing environment at a flow rate of approximately 5-5000 standard cubic centimeters per minute (SCCM). Furthermore, in this embodiment, the plasma ashing environment used to substantially remove polysilicon etch-induced residues without requiring the aggressive chemical strip is at a pressure in the range of 50 mTorr to 5 Torr; is at a power in the range of 50 Watts to 5000 Watts; is performed for a duration in the range of 3 seconds to 300 seconds; and is performed at a temperature in the range of 20 degrees Celsius to 350 degrees Celsius. Although such parameters are recited in the present embodiment, the present invention is well suited to varying the parameters, conditions, and components of the plasma ashing environment. In the present embodiment, the presence of the CF4 is used to remove residues, while the presence of H2O is used to suppress etching of the gate oxide layer. As an example of the benefits of the present embodiment, conventional prior art processes which expose the gate oxide layer to an aggressive chemical strip, often show a loss of more than 40 Angstroms in the thickness of the oxide layer. The present embodiment however, limits the loss of thickness in the gate oxide layer to less than 10 Angstroms. Upon the completion of step 404, the present embodiment returns to step 306 of Figure 3. With reference now to Figure 5A, a cross sectional view of a semiconductor substrate 500 having a gate oxide layer 502, a polysilicon layer 504, and a portion of photoresist 506 disposed thereover is shown. In the structure of Figure 5A, portion of photoresist 506 defines the location at which a polysilicon gate will be formed. With reference now to Figure 5B, in the present embodiment, polysilicon layer 504 is subjected to a plasma etch process. The plasma etch process removes polysilicon layer 504, except for that portion of polysilicon layer 504 which is covered, and, hence protected from the plasma etching process, by portion of photoresist 506. As shown in Figure 5B, residues (e.g. residual polymer materials), typically shown as 508, are formed on portion of photoresist 506, the remaining regions of polysilicon layer 504, and the surface of gate oxide layer 502. Referring now to Figure 5C, a side sectional view illustrates an example of the present embodiment wherein both residues 508 of Figure 5C and the remaining portions of photoresist 506 of Figure 5C have been removed. Additionally, unlike the prior art, the present embodiment removes residues 508 without subjecting gate oxide layer 502 to an aggressive chemical strip. The process used in the present embodiment to remove both residues 508 and photoresist 506 will be described in detail below in conjunction with Figures 6 and 7. Furthermore, gate oxide layer 502 is now clean and can be measured to verify that gate oxide layer 502 is of a requisite thickness. With reference now to Figure .6, a flow chart 600 of steps performed in accordance with one embodiment of the present invention is shown. In the present embodiment, at step 602, a plasma etch of a polysilicon layer is performed to define the location of the polysilicon gate. As mentioned above, this process results in the formation of residues on the photoresist, the remaining regions of the polysilicon layer, and the surface of gate oxide layer all of which reside above the semiconductor substrate. Additionally, as mentioned previously, conventional processes employ an aggressive chemical strip in an attempt to remove these residues. This prior art aggressive chemical strip deleteriously attacks and significantly etches the gate oxide layer. Referring next to step 604, unlike the prior art, the present embodiment then subjects the semiconductor substrate and overlying features to a plasma ashing environment to remove both the residues which resulted from the plasma etching of the polysilicon layer and the remaining portions of photoresist. Hence, the present embodiment eliminates the need to subject the semiconductor substrate and overlying features (including the gate oxide layer) to a deleterious aggressive chemical strip. The precise chemistry of the ashing environment used in the step 604 of the present embodiment to remove residues 508 will be described in detail below in conjunction with Figure 7. This residue and photoresist removal process ensures that the gate oxide layer is now clean and easily measured. In the present embodiment, after the removal of both the residues and the remaining portion of photoresist at step 604, the present disclosure proceeds to step 606. Referring now to step 606, after the performance of steps 602 and 604, the present embodiment enables an accurate and reliable measurement of the thickness of the gate oxide layer. With reference now to Figure 7, a flow chart 700 of steps performed to generate the plasma ashing environment recited in step 604 of Figure 6 is shown. After the performance of step 602 and in accordance with step 702 of Figure 7, the present embodiment generates a plasma ashing environment. More particularly, in one embodiment, the present disclosure introduces CF 4 into a plasma ashing environment. At step 704, present embodiment, introduces H2O vapor iή£o the plasma ashing environment such that the ratio by volume of the CF4 to the H2O is in the range of from 0.1:1 to 10:1. At step 706, present embodiment, introduces O2 vapor into the plasma ashing environment. At step 706 of Figure 7, the present embodiment uses this plasma ashing environment to substantially remove both polysilicon etch-induced residues and photoresist without requiring an aggressive chemical strip. Hence, the present embodiment eliminates the need for the deleterious aggressive chemical strip of the prior art. Additionally, in one embodiment of the present invention, the aforementioned plasma ashing environment is created by introducing the CF4 at a flow rate of approximately 5-5000 standard cubic centimeters per minute (SCCM). In this embodiment, the H2O is introduced into the plasma ashing environment at a flow rate of approximately 5-5000 standard cubic centimeters per minute (SCCM). In this embodiment, the O2 is introduced into the plasma ashing environment at a flow rate of . approximately 10-10,000 standard cubic centimeters per minute (SCCM). Furthermore, in this embodiment, the plasma ashing environment used to substantially remove both polysilicon etch-induced residues and remaining portions of photoresist without requiring the aggressive chemical strip is at a pressure in the range of 5 mTorr to 5 Torr; is at a power in the range of 50 Watts to 5000 Watts; is performed for a duration in the range of 3 seconds to 300 seconds; and is performed at a temperature in the range of 20 degrees Celsius to 350 degrees Celsius. Although such parameters are recited in the present embodiment, the present invention is well suited to varying the parameters, conditions, and components of the plasma ashing environment. In the present embodiment, the presence of the CF4 is used to remove residues, while the presence of H2O is used to suppress etching of the gate oxide layer, and the presence of 02 is used to remove remaining portions of photoresist material. As an example of the benefits of the present embodiment, conventional prior art processes which expose the gate oxide layer to an aggressive chemical strip, often show a loss of more than 40 Angstroms in the thickness of the oxide layer. The present embodiment however, limits the loss of thickness in the gate oxide layer to less than 10 Angstroms. Upon the completion of step 706, the present embodiment returns to step 606 of Figure 6. Referring now to Figure 8, a table 800 reciting CF4 H2O and O2 plasma ashing recipes in accordance with one embodiment of the present claimed invention. Although such parameters are recited in table 800, the present invention is well suited to varying the parameters, conditions, and components of the plasma ashing environment. Thus, the present invention provides a method which effectively removes plasma etching-induced residues without deleteriously and substantially attacking gate oxide. The foregoing descriptions of specific embodiments of the present invention have been presented for purposes of illustration and description. They are not intended to be exhaustive or to limit the invention to the precise forms disclosed, and obviously many modifications and variations are possible in light of the above teaching. The embodiments were chosen and described in order to best explain the principles of the invention and its practical application, to thereby enable others skilled in the art to best utilize the invention and various embodiments with various modifications as are suited to the particular use contemplated. It is intended that the scope of the invention be defined by the Claims appended herfeto and their equivalents.

Claims: CLAIMS: 1. A method comprising the steps of: a) introducing CF 4 into a plasma ashing environment; and b) introducing H 2 0 vapor into said plasma ashing environment such that the ratio by volume of said CF 4 to said H 2 0 is in the range of from 0.1:1 to 10:1. 2. The method of Claim 1, wherein said method is for enhancing residue removal after a plasma etch of polysilicon, the method further comprising the step of: c) using said plasma ashing environment to substantially remove polysilicon etch-induced residues without requiring an aggressive chemical strip. 3. The method of Claim 1, wherein said method is for accurately determining the remaining thickness of a gate oxide layer after the performance of a plasma etch of polysilicon, the method further comprising the steps of: c) using said plasma ashing environment to substantially remove polysilicon etch-induced residues without requiring an aggressive chemical strip; and d) measuring the thickness of said gate oxide layer after said step c). 4. The method as recited in any one of Claims 1-3 wherein said step a) of introducing CF 4 into said plasma ashing environment comprises the step of: introducing said CF 4 at a flow rate of approximately 360 standard cubic centimeters per minute (SCCM). 5. The method as recited in any one of Claims 1-4 wherein said step b) of introducing H 2 0 into said plasma ashing environment comprises the step of: introducing said H 2 0 at a flow rate of approximately 600 standard cubic centimeters per minute (SCCM). 6. The method as recited in any one of Claims 2-5 wherein said step c) of using said plasma ashing environment to substantially remove said polysilicon etch-induced residues further comprises the step of: using said plasma ashing environment to substantially remove said polysilicon etch- induced residues without requiring said aggressive chemical strip wherein said plasma ashing environment is at a pressure in the range of 50 mTorr to 5 Torr. 7. The method as recited in any one of Claims 2-5 wherein said step c) of using said plasma ashing environment to substantially remove said polysilicon etch-induced residues further comprises the step of: using said plasma ashing environment to substantially remove said polysilicon etch- induced residues without requiring said aggressive chemical strip wherein said plasma ashing environment is at a power in the range of 100 Watts to 3000 Watts. 8. The method as recited in any one of Claims 2-5 wherein said step c) of using said plasma ashing environment to substantially remove said polysilicon etch-induced residues fiirther comprises the step of: using said plasma ashing environment to substantially remove said, polysilicon etch- induced residues without requiring said aggressive chemical strip wherein said plasma ashing environment is for a duration in the range of 5 seconds to 300 seconds. 9. The method as recited in any one of Claims 2-5 wherein said step c) of using said plasma ashing environment to substantially remove said polysilicon etch-induced residues further comprises the step of: using said plasma ashing environment to substantially remove said polysilicon etch- induced residues without requiring said aggressive chemical strip wherein said plasma ashing environment is at a temperature in the range of 50 degrees Celsius to 350 degrees Celsius. 10. The method as recited in Claim 3 wherein said step d) of measuring the thickness of said gate oxide layer after said step c) further comprises the step of: measuring said thickness of said gate oxide layer without obtaining substantially flawed measurements resulting from the Use of said aggressive chemical strip. 11. The method of Claim 1 , wherein said method is for concurrently removing photoresist and residual polymers after a plasma etch of polysilicon, the method further comprising the steps of: c) introducing O 2 into said plasma ashing environment; and d) using said plasma ashing environment to both substantially remove polysilicon etch- induced residues and to remove remaimng portions of photoresist without requiring an aggressive chemical strip. 12. The method as recited in Claim 11 wherein said step a) of introducing CF 4 into said plasma ashing environment comprises the step of: introducing said CF 4 at a flow rate of approximately 5-5000 standard cubic centimeters per minute (SCCM). 13. The method as recited in Claim 11 wherein said step b) of introducing H 2 0 into said plasma ashing environment comprises the step of: introducing said H 2 0 at a flow rate of approximately 5-5000 standard cubic centimeters per minute (SCCM). 14. The method as recited in Claim 11 wherein said step c) of introducing 0 2 into said plasma ashing environment comprises the step of: introducing said 0 2 at a low rate of approximately 10-10,000 standard cubic centimeters per minute (SCCM). 15. The method as recited in Claim 11 wherein said step d) of using said plasma ashing environment to substantially remove said polysilicon etch-induced residues further comprises the step of: using said plasma ashing environment to both substantially remove said polysilicon etch- induced residues and to remove said remaining portions of said photoresist without requiring said aggressive chemical strip wherein said plasma ashing environment is at a pressure in the range of 5 mTorr to 5 Torr. 16. The method as recited in Claim 11 wherein said step d) of using said plasma ashing environment to substantially remove said polysilicon etch-induced residues further comprises the step of: using said plasma ashing environment to both substantially remove said polysilicon etch- induced residues and to remove said remaining portions of said photoresist without requiring said aggressive chemical strip wherein said plasma ashing environment is at a power in the range of 50 Watts to 5000 Watts. 17. The method as recited in Claim 11 wherein said step d) of using said plasma ashing environment to substantially remove said polysilicon etch-induced residues further comprises the step of: using said plasma ashing environment to both substantially remove said polysilicon etch- induced residues and to remove said remaining portions of said photoresist without requiring said aggressive chemical strip wherein said plasma ashing environment is for a duration in the range of 3 seconds to 300 seconds. 18. The method as recited in Claim 11 wherein said step d) of using said plasma ashing environment to substantially remove said polysilicon etch-induced residues further comprises the step of: using said plasma ashing environment to both substantially remove said polysilicon etch- induced residues and to remove said remaining portions of said photoresist without requinng said aggressive chemical strip wherein said plasma ashing environment is at a temperature in the range of 20 degrees Celsius to 350 degrees Celsius.

Inventors: GABRIEL CALVIN TODD, LEARD LINDA, YEH EDWARD K, ZHENG TAMMY, GABRIEL, CALVIN, TODD, LEARD, LINDA, YEH, EDWARD, K., ZHENG, TAMMY
Applicants: KONINKL PHILIPS ELECTRONICS NV, PHILIPS SEMICONDUCTORS INC, KONINKLIJKE PHILIPS ELECTRONICS N.V., PHILIPS SEMICONDUCTORS, INC.
Application year: 2001
Main classification: H01L21
IPC codes: G03F7, H01L21