A/D CONVERTER BACKGROUND CALIBRATION

Abstract: A background calibrated A/D converter includes a random time interval generator (18) for increasing the spurious-free dynamic range of the A/D converter by initiating background calibration at randomly selected time instants.

Description: A/D CONVERTER BACKGROUND CALIBRATION TECHNICAL FIELD The present invention relates to a background calibrated A/D converter and an A/D converter background calibration method. BACKGROUND This invention relates to analog-to-digital converters, and in particular how to reduce the distortion caused by background calibration of such converters. The maximum achievable accuracy-speed performance of any A/D- converter is limited by non-ideal effects associated with its building blocks. Typically, the performance is limited by settling time, finite amplifier gain and/ or analog component mismatch. When designing high-speed, high- accuracy A/D converters, these limitations impose very stringent demands on the building blocks, leading to prolonged design time. It also requires the use of manufacturing processes that are optimized for component matching and performance, thus increasing the manufacturing cost. Many non-ideal effects can however be compensated for by calibration [ 1]. The problem is that the efficiency of the calibration may be degraded by drift and aging. Therefore it is desirable to be able to continuously calibrate the A/D converter during normal operation. Many calibration schemes rely on some form of skip-and-fill method [2, 3]. In such methods, widely separated samples are skipped in the conversion and replaced by a fill sample usually calculated from interpolation of neighboring samples. At each skip, a calibration operation is performed. The error of the fill sample is seen as an increase in noise and/ or spurious tones or frequency components in the output frequency spectrum. When the skip-rate is high, the fill-sample error is mainly repre- sented by spurious tones, which is highly undesirable in, for example, telecommunications systems. Nevertheless it may sometimes be desirable to have a short re-calibration cycle (high skip-rate) in order to track more rapid changes in the operating conditions. Another method to create a calibration time-slot is found in [4], where an input sample queue is formed by a cascade of sample-and-hold circuits. By emptying the queue slightly faster than it is filled, a calibration time- slot is occasionally available. Thus, this "input-queue" method has the benefit of creating a time-slot for calibration without the need to discard any samples. The main drawback of this method is that each extra sample-and-hold stage adds distortion and noise. Therefore this approach is not optimal for highspeed, high-resolution A/D converters. Thus, the key idea in most prior-art solutions is to replace every k^ 1 sample with a fill sample of slightly less quality. This is not a problem in most cases, if k is a large number. However, sometimes a shorter re-calibration cycle is desirable, as noted above. A short re-calibration cycle (small k) will, however, reduce the spurious-free dynamic range (SFDR) of the A/D converter. In some applications, for example telecommunication applications, it is usually preferred that errors degrade the signal-to-noise ratio (SNR) rather than the spurious-free dynamic range. Thus, if there is a need for background calibration with a short re-calibration cycle, it is necessary to find a better solution than to skip and fill every k* sample. SUMMARY An object of the present invention is to allow frequent background calibration of an A/D converter without significant degradation of the spurious-free dynamic range. This object is achieved in accordance with the attached claims. Briefly, the present invention achieves this object by using random skip intervals. This makes it possible to have a high average skip-rate, while maintaining a large spurious free dynamic range. BRIEF DESCRIPTION OF THE DRAWINGS The invention, together with further objects and advantages thereof, may best be understood by making reference to the following description taken together with the accompanying drawings, in which: Fig. 1 is a block diagram of a conventional A/D converter with an interpolator; Fig. 2 is a time diagram illustrating sampling with the A/D converter of fig. i ; Fig. 3 is a simplified diagram illustrating the spectrum of a signal that has been digitized by the A/D converter in fig. 1; Fig. 4 is a block diagram of an A/D converter with an interpolator configured in accordance with the present invention; Fig. 5 is a time diagram illustrating sampling with the A/D converter of fig. 4; Fig. 6 is a simplified diagram illustrating the spectrum of a signal that has been digitized by the A/D converter in fig. 4; Fig. 7 is a block diagram of an exemplary embodiment of an A/D converter in accordance with the present invention; Fig. 8 is a block diagram of another exemplary embodiment of an A/D converter in accordance with the present invention; Fig. 9 is a block diagram of another exemplary embodiment of an A/D converter in accordance with the present invention; Fig. 10 is a block diagram of another exemplary embodiment of an A/D converter in accordance with the present invention; Fig. 1 1 is a block diagram of an exemplary embodiment of a random time interval generator suitable for use in an A/D converter in accordance with the present invention; Fig. 12 is a block diagram of another exemplary embodiment of a random time interval generator suitable for use in an A/D converter in accordance with the present invention; Fig. 13-14 are block diagrams of another exemplary embodiment of a random time interval generator suitable for use in an A/D converter in accordance with the present invention; Fig. 15 is a diagram illustrating the improvement obtained by the present invention; and Fig. 16 is a flow chart illustrating an exemplary embodiment of the method in accordance with the present invention. DETAILED DESCRIPTION In the following description the same reference designations will be used throughout the figures of the drawing for elements performing the same or similar functions. One of the more popular approaches to background calibration is to use the "skip-and-fill" approach, as illustrated in fig. 1. An analog signal is forwarded to an A/D converter 10. The digital samples are forwarded to an interpolator 12 and a delay element 14. A switch 16 is normally in the indicated upper position, in which the digital samples from delay element 14 are outputted at a sampling interval T. Every c* sample switch 16 is forced to its lower position, in which a sample is skipped and an interpolated digital sample from interpo- lator 12 is outputted instead. Thereafter switch 16 returns to its upper position. Calibration, or a part of a complete calibration of A/D converter 10 is performed during the interpolation. The A/D converter output signal is illustrated in fig. 2, where the interpolated samples have been indicated by solid lines. It can be shown that the fill error (due to the interpolation) appears at multiples of the frequency /s/ fc, where fs is the sampling rate. When k is large, the error is spread out over a large number of frequencies. Therefore it appears more or less as noise. However, when k is small, e.g. k = 10, the error is concentrated to a small number of frequency components. Consequently, each of these spurious frequency components becomes more dominant. The simulated output spectrum of an ideal 14-b ADC having every 10 th sample replaced by a fill sample with 10-b resolution is shown in fig. 3. The spurious components or tones at s/ 10 are obvious (fs = 50 MHz). Fig. 4 is a block diagram of an A/D converter with an interpolator configured in accordance with the present invention. In this case switch 16 is not actu- ated at regularly spaced time instants. Instead switch 16 is controlled by a random time interval generator 18, which actuates the switch at randomly selected time instants. Fig. 5 is a time diagram illustrating sampling with the A/D converter of fig. 4. It is evident from the figure that the interpolated values represented by the solid lines are not regularly spaced as in fig. 2. Fig. 6 is a diagram illustrating the spectrum of a signal that has been digitized by the A/D converter in fig. 4. The spurious tones have been removed at the cost of a slightly raised noise floor. However, the spurious-free dynamic range (SFDR) has been increased by approximately 25 dB. (The expression "skipping conversion cycles randomly" seems to be accidentally disclosed in [3], but no implementation has been shown or otherwise indicated. On the contrary, as far as can be understood from the text, equidistant skip cycles were used for the presented experimental results. In fact the problem underlying the present invention has not been mentioned at all.) Having described the basic problem addressed by the present invention and its general solution, it is now time to describe how to efficiently implement random time interval generators for controlling background calibration of A/ D-converters. The random spacing between consecutive skip-and-fills can be generated in a large number of ways. In the example given above, each calibration time ιj can be written as: ij = r j + ij_ λ where η is a random integer value ranging from rmin to rmax. A straightforward implementation of this random timing-generator is shown in fig. 7. A (pseudo) random word generator 20 provides an integer value η to an inter- val counter 22 used to trigger a calibration skip-and-fill. When the counter has counted up to (or down from) η, a trig-pulse SKIP_TRIG is sent to a calibration control unit 24 which initiates a single-step calibration cycle or a step of a multi-step calibration cycle. A look-up table with a sequence of predefined skip-intervals can be used instead of a random word generator. This is illustrated in the embodiment of fig. 8. The "randomness" of the fixed sequence of skip intervals can be examined beforehand, and a sequence with acceptable spectral properties is then chosen. Interval counter 22 in fig. 8 can be excluded if a fixed 1-bit sequence representing the SKIP_TRIG signal itself is stored in a long 1-bit/word memory, as shown in fig. 9. Again, the randomness of the occurrences of SKIP_TRIG = 1 is studied, and a suitable sequence of ones and zeros is chosen. This direct look-up table approach can be suitable for very dense background calibration schemes, although its drawback is that a very long memory is usually needed. If, for example a sequence cannot be repeated more often than every 8 k sample, an 8 kbit memory is required. A presently preferred embodiment is to use a linear feedback shift register (LFSR) to generate pseudo-random time intervals, as indicated in fig. 10. This use is different from known earlier uses of LFSRs, which are pseudo- random noise generators (1-bit sequences) and generation of several fixed- time periods [5]. The use of LFSRs as pseudo-random noise generators is exemplified in [6] with scrambling of data to increase randomness, and in [7] with noise generation for calibrating a magnetic read channel. LFSRs are also used in spread- spectrum (including CDMA) communications and ranging systems for generating spreading codes, i.e., "long" codes and codes with special autocorrelation properties, as well as in cryptography [8]. The main requirements for the skip intervals are that they appear to be ran- dom within a relatively short signal segment, i.e., up to several thousand samples. Preferably a minimum time interval can be set in which a skip is not generated. This feature allows generation of a sufficient number of samples after a skip to permit interpolation. The basic idea in using a LFSR to generate pseudo-random intervals is illustrated in fig. 1 1. The idea is to use a short (shorter than register 20) detection mask 22 on a part of register 20, and generate a skip signal when the contents in the part of the register matches the detection mask. In the present invention, the register consists of either a serial connection of one-bit storage elements, e.g. D-latches, or a fixed length memory. The contents of the storage elements are shifted from one element to the next each clock period (in a fixed length memory implementation the reference point is shifted instead of the data). A feedback is provided from the last storage element and at least one other storage element, the outputs of which are combined in an XOR or XNOR gate 26. The output bit-sequences provided by this type of register, with n storage elements, can be up to 2 n - l bits long, if the proper feedback connections are used [9]. If other connections are used, shorter sequence lengths can be ob- tained. The different sequence lengths possible with a specific connection pattern are related to each other in that the register contents (words) that the LFSR walks through during different sequences are mutually exclusive. This means that the same word can not belong to two different sequences. In the case of maximum-length sequences, one sequence contains all words except all zeros or all ones, and the other contains only the all-zeros word (or all-ones). In non-maximum length LFSRs, several sequences of different or equal lengths can be produced, depending on the contents of the register at startup. Smaller parts of the register return to the same code several times during one long cycle. Statistically, all shorter codes of a given number of bits m appear equally in an arbitrarily chosen subset of a maximum-length LFSR, ex- cept for the all-zeros code which appears one time less. Non-maximum but long sequences also have a good statistical distribution of shorter codes. This can be used favorably in some cases, since some register sizes require more than two feedback connections in order to produce maximum-length sequences. A non-maximum length LFSR can then instead be produced with only two feedback connections, for ease of implementation [9]. This can produce a sequence that is long enough to give a good statistical distribution of intervals between the used detection codes. The detection of the smaller parts is done by matching the contents of cho- sen elements of the register with the detection code mask. The register positions which are used for matching can be continuous or split into several parts, and can also start at different positions. In order to increase the length of the cycle before the sequence of skip inter- vals repeats, a new detection code can be used for each long cycle of the LFSR. This effectively increases the length of the pseudo-random sequence of skip intervals by 2 m times, where m is the number of bits in the detection mask. In order to increase the randomness it is possible to change one or several bits of the detection mask between each m-sequence under the influ- ence of some external analog or digital process, for example analog noise on the chip. Other schemes can also be devised, by for example changing the register positions that are compared with the detection code. The provision of a minimum interval between sample skips can be arranged in several ways. One way is to let the circuitry responsible for providing the skip sample also generate an inhibit signal to the random interval circuit, or let this circuitry just ignore new skip signals during the time it is working. The inhibit signal could, for example, disable the detection circuitry over an AND gate 28 by providing a SKIP_ENABLE signal, as shown in fig. 11. Another embodiment for obtaining a minimum interval between sample skips is illustrated in fig. 12. In this embodiment an ENABLE_LFSR signal is forwarded to an AND gate 30 and controls the clocking of the register. Another way to obtain a minimum interval is to have a counter start counting a predetermined interval starting at the generation of a skip signal, disabling the LFSR or detection circuitry during this interval. This counter could also be made using a smaller LFSR generating a fixed interval, similar to [5]. Such an embodiment is illustrated in fig. 13- 14. A convenient way is to let a part of the LFSR be reconfigured into a counter of a smaller LFSR (fig. 14), for generation of the minimum interval. This embodiment could use the same detection code or part thereof as the regular detection code, the smaller LFSR counting back to the same code. The smaller register could be a maximum or non-maximum length LFSR for getting different minimum intervals. Different minimum intervals could also be obtained by initializing the small register or counter to different states. The statistical distribution of skip intervals can be modified in several ways. By doing this, the skip intervals can be confined to be shorter than a predetermined length, and other statistics of the skip intervals can also be changed. The easiest way to modify the distribution of skip intervals is to simply use a different detection code or detection arrangement. Other varie- ties include detecting several codes, generating a skip signal at the first detected code. This procedure, which shortens the mean interval, can also be used in combination with detecting codes of different parts of the LFSR. Detecting multiple codes one after the other also changes the distribution of skip intervals, and can also be used to increase the mean interval. Changing the statistical distribution of skip intervals is a feature that may be used to dynamically change the average calibration rate. By sensing one or several external parameters, such as temperature, humidity, etc., it is possible to control and adapt the average calibration rate to changing operating conditions. For example, the average calibration rate may be temporarily increased during time periods of rapidly changing temperature. The specific problem of having an upper limit for the skip intervals can be solved with the techniques previously discussed, but also by having a dedicated counter that generates a skip signal after a predetermined time period. When using only the detection code to ensure that the maximum interval is within bounds, the whole cycle distribution of -bit detection codes can be studied beforehand, to determine which detection code has the best statis- tics. A way of reducing statistically the possibility of occasional very long skip intervals, without trying out the code in advance, is to detect multiple codes, where one code is longer than the other. This does not alter the statistical distribution much (the number of skips in a given time period stays about the same) but the possibility of a very long interval is reduced. There are further useful techniques to reduce the power consumption of the skip interval circuit and generate longer skip intervals. One technique is to clock the LFSR at a lower clock rate than the sample clock, possibly a sub- multiple fs/x. This must be accompanied by a suitable change in the detec- tion circuitry (shorter detection code length) to give the same average skip interval. The technique can also be used to generate longer skip intervals using the same LFSR and detection circuitry. Another power reduction technique already mentioned is to redirect the read and write addresses of a memory. Then the data need not be shifted between all latches at each clock cycle, which saves power especially for long shift register lengths. In the description above it has been assumed that the skipped sample is obtained by interpolation. Another alternative is to provide a low perform- ance auxiliary A/D converter that replaces the regular A/D converter during calibration. An important advantage of this embodiment is that the auxiliary A/D converter converts the actual signal, as opposed to calculating an interpolated value from neighboring samples. A few simulation results are included as an indication of possible performance. An auxiliary A/D converter in accordance with the previous paragraph was chosen for this example, using random and equidistant skip intervals respectively. An otherwise ideal 14-bit converter had every k^ sample in a 16384 samples sequence replaced by a 10-b fill sample (from the auxiliary A/D converter) when equidistant skip-and-fill was used. When random intervals were used, the randomization was chosen so that in average every k^ 1 sample was replaced. Figure 15 shows how the spectral performance depends on the (average) interval length k for equidistant and random skip in- tervals. The interval length is swept from 1 to 10.000 samples, where the former extreme is equivalent to a stand-alone 10-b converter. The simulations indicate that randomized spacing allows for a much shorter re- calibration cycle with maintained SFDR than if equidistant calibration cycles are used. Fig. 16 is a flow chart illustrating an exemplary embodiment of the method in accordance with the present invention. Step S I generates a random interval. Step S2 generates a digital sample of the input signal. Step S3 tests whether the generated interval is over. If not, the steps S2 and S3 are repeated. If the interval is over, step S4 initiates a calibration (either a complete cycle or a part thereof) and fills in the missed sample, for example by using an auxiliary A/D converter. Thereafter step S I is repeated to generate a new random interval. From the description above it is appreciated that an advantage of the present invention is that it allows for a more dense spacing of calibration (skip) cycles, which leads to a shorter re-calibration cycle. This, in turn, allows for better tracking of fast-changing operating conditions. The invention represents a generic method, applicable to background calibration of most known wideband A/D converter architectures, and therefore covers a large number of applications, not only those related to digital radio systems. The present invention is not limited to a particular calibration scheme. Instead, by using the present invention it becomes possible to improve the overall system performance while using one of a wide range of novel and existing background calibration schemes. The present invention is not limited to the "auxiliary-ADC" approach used for illustration of the benefits of the invention. It is equally applicable to interpolation-type skip-and-fill background calibration, and in fact any background calibration that occasionally disturbs the data-flow through the main conversion path. The LFSR-based embodiment of the present invention is particularly hardware- and power-efficient, since the timing is defined by directly observing internal states of the LFSR, rather than having an LFSR generating random target vales for the up/down counter. Also, the amount of hardware required for a given sequence length increase very slowly (logarithmically) with the length of the pseudo-random sequence. This is particularly interesting if the logic circuits are to be integrated on-chip, using an analog-oriented manufacturing technology. In such a technology digital circuits usually take more chip area and power than when implemented in a true digital manufacturing process. The invention is applicable to A/D converters used in wideband digital radio systems, such as WCDMA, or multi-carrier/ multi- standard systems. It can also lead to significant performance and/ or reliability improvements and cost-reductions in the design of ADSL/ VDSL systems. It will be understood by those skilled in the art that various modifications and changes may be made to the present invention without departure from the scope thereof, which is defined by the appended claims. REFERENCES [1] US Pat. 5.499.027, "Digitally self-calibrating pipeline analog-to-digital converter", Inventors: A. N. Karanicolas, and H.-S. Lee, Assignee: Massachusetts Institute of Technology. [2] U.-K. Moon, and B.-S. Song, "Background Digital Calibration Techniques for Pipelined ADC's", IEEE Trans. Circ. Syst.- II, pp. 102- 109, Vol. 44, No. 2, Feb. 1997, IEEE. [3] S.-U. Kwak, B.-S. Song, and K. Bacrania, "A 15-b, 5-Msample/ s Low- Spurious CMOS ADC", IEEE J. Solid-State Circ, pp. 1866- 1875, Vol. 32, No. 12, Dec. 1997, IEEE. [4] O. E. Erdogan, P. J. Hurst, and S. H. Lewis, "A 12b Digital- Background-Calibrated Algorithmic ADC with -90dB THD", 1999 Intl. Solid-State Circ. Conf , pp. 316-317, Feb. 1999, IEEE. [5] US Pat. No. 5.606.584, R. Beat. [6] US Pat. No. 5.793.318, R. E. Jewett. [7] US Pat. No. 5.786.951, D. R. Welland et al. [8] T. Ritter, "The Efficient Generation of Cryptographic Confusion Sequences", Cryptologia, pp. 81- 139, Vol. 15, No. 2, Apr. 1991. [9] D. W. Clark, and L.-J. Weng, "Maximal and Near-Maximal Shift Register Sequences: Efficient Event Counters and Easy Discrete Loga- rithms", IEEE Trans. Computers, pp. 560-568, Vol. 43, No. 5, May 1994, IEEE.

Claims: CLAIMS 1. A background calibrated A/D converter, including a random time interval generator for increasing the spurious-free dy- namic range of the A/D converter by initiating background calibration at randomly selected time instants. 2. The A/D converter of claim 1 , wherein said random time interval generator includes a pseudo-random word generator for generating pseudo-random time intervals, and a time interval counter for initiating background calibration each time a pseudo-random time interval has elapsed. 3. The A/D converter of claim 1 , wherein said random time interval generator includes a multi-bit word look-up table for generating pseudo-random time intervals, and a time interval counter for initiating background calibration each time a pseudo-random time interval has elapsed. 4. The A/D converter of claim 1 , wherein said random time interval generator includes a 1-bit word look-up table for generating a pseudo-random bit sequence for initiating pseudo-random background calibration. 5. The A/D converter of claim 1 , wherein said random time interval generator includes a linear feedback shift register; and a detection mask for detecting matches between a part of said linear feedback shift register and a predetermined detection code, thereby generating a sample skip signal initiating background calibration each time a match is found. 6. The A/D converter of any of the preceding claims, including means for restricting the minimum allowed time interval between two consecutive background calibrations to a predetermined value. 7. The A/D converter of any of the preceding claims 1-5, including means for dynamically changing the statistical distribution of the time intervals between background calibrations. 8. The A/D converter of claim 7, including means for sensing at least one pa- rameter representing operating conditions and dynamically controlling the average time interval length with said sensed parameter. 9. The A/D converter of any of the preceding claims 1-5, including an auxiliary A/D converter for filling in samples during background calibration. 10. An A/D converter background calibration method, including the step of: increasing the spurious-free dynamic range of an A/D converter by initiating background calibration at randomly selected time instants. 1 1. The method of claim 10, including the step of restricting the minimum allowed time interval between two consecutive background calibrations to a predetermined value. 12. The method of claim 10 or 1 1 , including the step of dynamically changing the statistical distribution of the time intervals between background calibrations. 13. The method of claim 12, including the step of sensing at least one parameter representing operating conditions and dynamically controlling the average time interval length with said sensed parameter.

Inventors: HELLBERG RICHARD, JONSSON BENGT ERIK, HELLBERG, RICHARD, JONSSON, BENGT, ERIK
Applicants: ERICSSON TELEFON AB L M, TELEFONAKTIEBOLAGET LM ERICSSON
Application year: 2001
Main classification: H03M1
IPC codes: H03M1