FAST SWITCHING INPUT BUFFER

Abstract: An input buffer circuit (300) for a semiconductor device that includes a PMOS transistor (306), an NMOS transistor (308), and a pull-up circuit (314). The pull-up circuit (314) applies a voltage to the bulk region of the PMOS transistor (306) causing a positive body effect which causes the absolute value of the voltage threshold of the PMOS transistor (306) to temporally lower when the input buffer (300) switches. This causes the input buffer (300) to switch faster than conventional input buffers. The input buffer (300) is an inverter, NOR, NAND, or other input buffer.

Description: FAST SWITCHING INPUT BUFFER TECHNICAL FIELD The present invention relates generally to a CMOS input buffer for semiconductor devices. BACKGROUND ART Complementary metal oxide semiconductor (CMOS) input buffer have been used for many years for semiconductor devices. An important characteristic of input buffers is the switching time, that is the time required to transition from a high state to a low state or vice versa. Figure 1 illustrates an example of a conventional CMOS inverter input buffer 100 for semiconductor devices. The CMOS inverter input buffer 100 includes a P-channel MOSFET transistor 106, also called a PMOS transistor, and an N-channel MOSFET transistor 108, also called an NMOS transistor in a complementary configuration. The gates of the PMOS and NMOS transistors 106, 108 are connected with the input node 102, also called the input terminal. Because both gates are connected with the input node 102, the input signal is also called the gate voltage, Vg. The output signal is transmitted from the output node 110, also called the output terminal. The output node 110 is connected with the drains of the PMOS and the NMOS transistors 106, 108. When a low signal, substantially zero volts, is applied to the input node 102, the PMOS transistor 106 is turned on and the NMOS transistor 108 is turned off, driving the output node 110 high. When a high signal, substantially the supply voltage, is applied to the input terminal 102, the PMOS 106 transistor is turned off and the NMOS transistor 108 is turned on driving the output node low. Since one of the PMOS and NMOS transistors is in the off state, little if any DC current is consumed. Figure 2 illustrates an example of a conventional CMOS NOR input buffer 200. The CMOS NOR input buffer 200 includes first and second PMOS transistors 210, 212, and first and second NMOS transistors 214, 216. The gates of the second PMOS transistor 212 and the first NMOS transistor 214 are connected with the input node 202. The output signal is transmitted from the output node 210 connected with the drains of the second PMOS transistor 212 and the first and second NMOS transistors 214, 216. The control signal "power down" is received at the control node 218. The control node 218 is connected with the gates of the first PMOS transistor 210 and the second NMOS transistors 216. DISCLOSURE OF INVENTION An input buffer circuit for a semiconductor device that includes a PMOS transistor, an NMOS transistor, and a pull-up circuit. The pull-up circuit applies a voltage to the bulk region of the PMOS transistor causing a positive body effect that temporally lowers the absolute value of the voltage threshold of the PMOS transistor when the input buffer switches. This causes the input buffer to switch faster than convention input buffers. The input buffer is an inverter, NOR, NAND, or other input buffer. BRIEF DESCRIPTION OF DRAWINGS The present invention is described with reference to the accompanying figures. In the figures, like reference numbers indicate identical or functionally similar elements. Additionally, the left-most digit(s) of a reference number identifies the figure in which the reference number first appears. Figure 1 is an illustration of a conventional CMOS inverter input buffer; Figure 2 is an illustration of a conventional CMOS NOR input buffer; Figure 3 is an illustration of an embodiment of the present invention relating to a CMOS inverter input buffer; Figure 4 is an illustration of an embodiment of the present invention relating to a CMOS NOR input buffer; and Figure 5 is an illustration of a cross-sectional view of a PMOS transistor embodying elements of the present invention. MODE(S) FOR CARRYING OUT THE INVENTION An input device for semiconductor devices, such as memory devices like SRAM and DRAM, provides fast switching between high and low output states. The input device operates at low supply voltages with low current leakage. The present invention temporarily lowers the absolute value of the threshold voltage to reduce the switching time without creating substantial current leakage. An input buffer monitors an input node for a signal and switches an output node based on the input node. While the input buffer and the circuits beyond the output node operate between a supply voltage, Vcc, and ground, the signals received at the input may be in a narrower range, for example Vih and Vil. Vih represents a "High" signal and Vil represent a "Low" signal. As a result of line capacitance and other factors, Vil is often higher than ground and Vih is often lower then the supply voltage. The PMOS transistors tend to switch at even slower rates when operated at low supply voltage. Low supply voltages are supply voltages below 3.3 volts, such as 1.8 volts or 1.6 volts. In many applications it is desirable to have switches operate as quickly as possible. A principle of CMOS design is that PMOS transistors are "weaker" than NMOS transistors. This is due to the mobility factor. Because the absolute value of the threshold voltage, |Vt|, of the PMOS transistor is often very high relative to the threshold voltage of the NMOS transistor, the switching time of the input buffer from "High" to "Low" is generally faster than the switching time from "Low" to "High". The threshold voltage is used to determine if the signal on an input line is high or low. If the absolute value of the threshold voltage of a PMOS transistor is lowered in an attempt to reduce the switching speed, the current leakage in the PMOS transistor will increase, which is undesirable. The present invention temporarily lowers the absolute value of the threshold voltage to reduce the switching time without creating substantial current leakage and is illustrated in Figures 3-5. Figure 3 illustrates an example of a CMOS inverter input buffer 300 with fast switching and low current leakage. The CMOS inverter input buffer 300 includes a PMOS transistor 306, an NMOS transistor 308 in a complementary configuration, a pull-up device 314, and an optional capacitor 312. The gates of the PMOS and NMOS transistors 306, 308 are connected with the input node 302. The output signal is transmitted from the output node 310, which is connected with the drains of the PMOS and the NMOS transistors 306, 308. A pull-up device 314, for example a resistor, is connected with the supply voltage and the bulk of the PMOS transistor 306. The resistance of the pull-up device 314 depends on the characteristics of the input buffer 300 and in particular it depends on the characteristics of the PMOS transistor 306. For example, the resistance value can be 1 KOhm to 3000 KOhms. Other pull-up devices 314 can be used as long as they provide voltage to the bulk region of the PMOS transistor, for example a RL circuit, a diode, or other device. The pull-up device 314 acts as a charging mechanism for supplying a voltage to a bulk of the PMOS transistor 306. An optional capacitor 312 is connected with the gate and the bulk of the PMOS transistor. The capacitor 312 adds gate capacitance to the input buffer 300 when the PMOS and NMOS transistors 306, 308 do not provide sufficient input capacitance to increase the buffer's switching time. When the input signal goes low, that is Vil is received at the input node 302, the gate capacitance momentarily pulls the bulk region of the PMOS transistor 306 low. This makes the absolute value of the threshold voltage, |Vt|, decreases. Thus, the PMOS transistor 306 becomes "stronger" and the current moves thru the P-channel faster. The pull-up device 314 charges the bulk region of the PMOS transistor 306 back toward the supply voltage after the output switches high. Optionally, the PMOS transistor 306 and the pull-up device 314 are connected with different supply voltages. Figure 4 illustrates an example of a CMOS NOR input buffer 400 with fast switching and low leakage current. The CMOS NOR input buffer 400 includes first and second PMOS transistors 410, 412, first and second NMOS transistors 414, 416, first and second pull-up devices 406, 408, and an optional capacitor 422. The gates of the second PMOS transistor 412 and the first NMOS transistor 414 are connected with the input node 402. The output signal is transmitted from the output node 420, which is connected with the drain of the second PMOS transistor 412 and the drains of the first and second NMOS transistors 414, 416. The sources of the first and second NMOS transistors 414, 416 are connected with ground. The source of the second PMOS transistor 412 is connected with the drain of the first PMOS transistor 410. The source of the first PMOS transistor 410 is connected with the supply voltage 404. The control signal, labeled "power down", is received at the control node 418. The control signal is connected with the gates of the first PMOS transistor 410 and the second NMOS transistor 416. The control node 418 and the input node 402 are the inputs to the NOR circuit and the output node is the output of the NOR circuit. A first pull-up device 406 is connected with the supply voltage and the bulk of the first PMOS transistor 410. The second pull-up device 408, also called a pull-up circuit, is connected with the supply voltage 404 and the bulk of the second PMOS transistor 412. The resistance of the pull-up devices 406, 408 depend on the characteristics of the input buffer 400 and depend in particular on the characteristics of the PMOS transistor they are connected with. For example, the resistance of the pull-up devices 406, 408 can be 1 KOhms to 3000 KOhms. Other values are also acceptable depending on the characteristics of the input buffer 400. The pull-up devices 406, 408 can include other circuits as long as the circuits provides voltage to the bulk region of the PMOS transistors 410, 412, for example a RL circuit, a RLC circuit, a diode circuit, or other device. The pull-up devices 406, 408 in this embodiment act as a charging means for supplying a voltage to a bulk of the PMOS transistors 410, 412. In another embodiment, only one of the two pull-up devices 406, 408 is used. An optional capacitor 422 can be added to increase the gate capacitance. The optional capacitor 422 is connected with the gate and the bulk of the second PMOS transistor 412. Optionally, the first PMOS transistor 410 and the pull-up devices 406, 408 are each connected with different supply voltages. Traditional supply voltages are 5.0 volts and 3.3 volts. The present invention is preferably used with low power input buffers. Low power input buffers have supply voltages of 3.3 volts or less. For example the supply voltage can be approximately 2.0 volts to 1.0 volts. The present invention could also be used with other supply voltage ranges. Figure 5 is a cross-sectional view of a PMOS transistor 500 embodying elements of the present invention. The PMOS transistor 500 includes an N-type substrate region 526, a dielectric region 524, two P- type regions 518, 522, and a P-channel region 520, also called an N-well region. The PMOS transistor's 500 external interfaces include a source 512, a gate 514, a drain 516, and a bulk 528. The PMOS transistor 500 has a pull-up device 506 connecting the bulk 528 with the supply voltage at the source node 504. An optional capacitor 508 connects the bulk 528 with the gate 514. The gate 514 is connected with a gate node 502 that receives the gate signal. The drain 516 is connected with the drain node 510 that transmits the output from the PMOS transistor 500. When ground, substantially zero volts, is applied to the gate node 502, no P-channel 520 is created and the drain 516 supplies minimal current. When a negative voltage is applied to the gate node 502, electrons are repelled from the surface and creates a P-channel 520, that is a conductive region and provides a positive current from the source 512 to the drain 516.. The body effect phenomenon in an NMOS transistor occurs when the potential difference between the back-gate voltage, Vb, and the source potential, Vs, called Vbs, is negatively changed by the voltage of an input signal and increases the absolute value of the threshold voltage of the NMOS transistor. For a PMOS transistor, the potential difference Vbs is positively changed to increase the absolute value of the threshold voltage. When this phenomenon occurs in the NMOS transistor, the gate to source voltage, Vgs, decreases, the driving ability of the NMOS transistor decreases, and the signal transfer resistance increases. This is known as a "negative" body effect. The present invention uses a complementary phenomena called a "positive" body effect to temporarily lowers the absolute value of the voltage threshold of a PMOS transistor. The input buffers 300 (Figure 3), 400 (Figure 4) described above have a high DC threshold voltage that results in a lower leakage voltage. Additionally, the input buffers 300, 400 have low AC threshold voltages that provide faster switching and lower leakage voltage. It is estimated that such an input buffer could switch from high to low in about 50% to 60% of the time of a conventional low voltage input buffer. The input buffer 500 can be used with a variety of devices including semiconductor memory for use in a computer, cellular telephone flash memory, logic circuits, and other circuits. In a preferred embodiment, the input buffer 500 is used with low power semiconductor memory. When an input line transitions from high to'low, from logic 1 to logic 0, the gate capacitance is pulled down momentarily. This causes the absolute value of the threshold voltage to decrease. Current then travels thru the P-channel faster. This results in the output voltage, Vo, switching from low to high faster. The voltage at the bulk layer, Vbulk, is charged back to full supply voltage through the pull-up device 506 after the output node 510 has switched to high. Optionally, a capacitor 508 is added to increase the gate to bulk capacitance. The following equation describes the effect on the absolute value of the threshold voltage: |V t | = V t 0 + δ * [sqrt(2Φp + Vbs) - sqrt(2Φ F )] Eqn. 1 Where: |Vt| is the absolute value of the threshold voltage of the PMOS transistor. Vrø is the threshold voltage when Vbs = 0- δ is the substrate's bias effect constant. This constant is a function of the fabrication process and can ' vary between devices. Φp is the bulk potential. The bulk potential is a function of the fabrication process and can vary between devices. Vbs i s e voltage difference between the bulk and the source. In order to temporarily lower the absolute value of the threshold voltage, |Vt| when the gate voltage goes from high to low, |Vbs| is lowered and, that is the bulk voltage, Vb, is raise toward the source voltage, V s , which means that the bulk to source voltage, Vbs, i negative. When the gate voltage switches to low, the bulk voltage is coupled to the gate voltage and is brought lower than the supply voltage. This temporarily lowers the absolute value of the threshold voltage, |Vt|, of the PMOS transistor causing the output voltage, V ou t, to switch faster. The RC circuit, for example 506 and 508 (Figure 5), preferably is scaled to avoid a latch-up condition •when the bulk voltage is less than the source voltage. While Figures 3 to 5 illustrate an inverter and an NOR input buffer, the present invention can be implemented with other input buffer used for semiconductor devices, such as memory devices. For example, the present invention can be used with an NAND input buffer. While preferred embodiments have been shown and described, it will be understood that they are not intended to limit the disclosure, but rather it is intended to cover all modifications and alternative methods and apparatuses falling within the spirit and scope of the invention as defined in the appended claims or their equivalents.

Claims: WHAT IS CLAIMED IS: 1. An input buffer circuit (300) for a semiconductor device, comprising: (a) an input node (302); (b) an output node (310); (c) a PMOS transistor (306) with source, gate, drain, and bulk nodes, the source node of the PMOS transistor (306) being connected with a first supply voltage (304); (d) an NMOS transistor (308) with source, gate, and drain nodes, the source node being connected with ground; wherein the gate nodes of the PMOS and NMOS transistors (306, 308) being connected with the input node (302) and the drain nodes of the PMOS and NMOS transistors (306, 308) being connected with the output node (310); and (e) a pull-up circuit (314) connected with the bulk node of the PMOS transistor (306) and a second supply voltage. 2. The input buffer circuit (300) as recited in claim 1, wherein the input buffer circuit (300) comprises a low power input buffer circuit. 3. The input buffer circuit (300) as recited in claim 1, wherein the first (304) and second supply voltages provide substantially the same voltage. 4. The input buffer circuit (300) as recited in claim 1, wherein the first supply voltage (304) is less than or equal to 1.9 volts. 5. The input buffer circuit (300) as recited in claim 1, wherein the pull-up circuit (314) comprises a resistor. 6. The input buffer circuit (300) as recited in claim 1 , further comprising a capacitor circuit (312) connected with the source and bulk nodes of the PMOS transistor (306). 7. The input buffer circuit (300) as recited in claim 1, wherein the pull-up circuit (314) reduces a threshold voltage of the PMOS transistor (306) and reduces a switching time of the input buffer circuit (300). 8. The input buffer circuit (300) as recited in claim 1, wherein the input buffer circuit (300) comprises a CMOS inverter circuit. 9. An input buffer circuit (400) comprising ari input node (402), an output node (420), a select node (418), first and second PMOS transistors (410, 412) each with source, gate, drain, and bulk nodes wherein the source node of the second PMOS transistor (412) is connected with a first supply voltage (404), first and second NMOS transistors (414, 416) each with source, gate, and drain nodes wherein the source nodes of the first and second NMOS transistors (414, 416) are connected with ground, the drain nodes of the first and second NMOS transistors (414, 416) are connected with the output node (420), the first NMOS transistor's (414) gate node is connected with the input node (402), and the second NMOS transistor's (416) gate node is connected with the select node (418) and wherein the first PMOS transistor's (410) drain node is connected with the output node (420), the first PMOS transistor's (410)gate node is connected with the input node (402), and the second PMOS transistor's (412) gate node is connected with the select node (418); characterized in that a first pull-up circuit (406) is connected with the bulk node of the first PMOS transistor (410) and a second supply voltage and a second pull-up circuit (408) is connected with the bulk node of the second PMOS transistor (412) and a third supply voltage. 10. A memory device, comprising: (a) a CMOS input buffer (300) comprising at least one NMOS transistor (308), at least one PMOS transistor (306) connected with a NMOS transistor (308), and a pull-up circuit (314) connecting a bulk node of a PMOS transistor (306) to a supply voltage (304); and (b) an array of memory connected with the CMOS input buffer (300).

Inventors: CLEVELAND LEE, NGUYEN KENDRA, CLEVELAND, LEE, NGUYEN, KENDRA
Applicants: ADVANCED MICRO DEVICES INC, ADVANCED MICRO DEVICES, INC.
Application year: 2001
Main classification: H03K19
IPC codes: H03K19