SWITCHED CAPACITOR PIPELINE AD-CONVERTER

Abstract: A switched capacitor pipeline AD-converter whose cells comprise means for multiplying the analog input signal by a factor 2. The multiplying means comprise first and second capacitors wich are each loaded by the input signal. For generating the cell output signal the voltages of the capacitors are added without substantial charge transfer between the capacitors.

Description: Switched capacitor pipeline AD-converter The present invention relates to a switched capacitor pipeline AD-converter with a cascade of cells, each of said cells comprising: comparison means to compare a received analog signal with at least one predetermined comparison level and to output one or more digital bits representing the result of the comparison, multiplication and shift-means to multiply the analog signal with a factor 2 and to shift the analog input signal with a shift level which depends on the result of the comparison and means to output the multiplied and shifted analog signal for application to the next cell in the cascade of cells, the multiplication- and shift-means comprising first and second capacitors which are both switched to receive the analog signal during an input mode. AD-conversion plays an important role in present day electronics. Because digital signal processing is easier to design and better to reproduce than analog signal processing, it is the trend to place more of the signal processing into the digital domain. This requires AD-converters with higher conversion rates and higher resolution in combination with, preferably, low power consumption and which can be implemented in low cost standard CMOS technology. It appears that pipeline AD-convertors are good candidates to fulfill these requirements. The cells of the above described prior art pipeline AD-convertor may be realized with one comparison level halfway the maximum range of the analog input signal. The comparison then determines whether the signal level is in the upper half or in the lower half of its range. If the signal is in the upper half, the comparator generates a "one"-bit and the signal is shifted downwardly by one half of the maximum range. On the other hand, if the signal is in the lower half of its range, a "zero"-bit is generated and the signal remains unshifted. Subsequently the signal is multiplied by a factor 2 for application to the next cell. The bits, generated by the cascade of cells, together constitute a digital word, the most significant bit of which is generated by the first cell and the least significant bit by the last cell. This digital word constitutes the digital representation of the analog input signal. However, in this way, a high resolution AD-converter cannot be achieved because the accuracy of the comparison-level of the first cell should be higher then the accuracy represented by the least significant bit generated by the last cell of the cascade. With other words: when a 10-bit word has to be generated, the accuracy of the comparison of the first cell should be better than 1/1024. To avoid this inconvenience, each cell of the pipeline AD-converter may have two comparator levels e.g. at 3/8 and 5/8 of the maximum signal level. Each of the two comparators generates a bit which is "zero" when the analog signal is below the comparison level and which is "one" when the analog signal is above the comparison level. The bits derived from the lower-level comparators of the cells together constitute a digital word and the bits from the higher-level comparators of the cells together constitute another digital word. When the two words are completed, they are added together to make the digital word that constitutes the end-result of the AD-converter. In this case, when the input signal level is close to the mid-level of the range and consequently falls in the mid-range between 3/8 and 5/8 of the maximum level, the decision as to the value of the most significant bit is delayed. Only when the results of the following cells is available and the two digital words are added, the value of the most significant bit is finally determined. The same holds for the determination of the other bits. The effect of this measure is that the value of the comparator levels is much less critical then in the case of a converter with only one comparator level. On the other hand, in each pipeline cell the analogue signal has to be multiplied by a factor 2 to provide the input signal for the next pipeline cell and this factor has to be very accurate in case a high resolution AD-converter is required. In prior art switched capacitor pipeline AD-converters this factor is strongly dependent on the value of the capacitors in the multiplication- and shift-means. It is the primary object of the present invention to substantially improve the accuracy of the multiplication factor and therefore the switched capacitor pipeline AD-converter of the present invention is characterized in that the first and second capacitors are, during an output mode, switched to preserve their respective charges and to add their voltages for generating the analog signal for the next cell. In most prior art circuits the first and second capacitors are, during the output mode, both connected to the inverting input terminal of an operational amplifier, i.e. one is connected between the inverting input and the output of the operational amplifier and the other between the inverting input and a reference potential. The multiplication by the factor 2 is then obtained in that during the output mode the electric charge from the second capacitor is transferred to the first capacitor where it is added to the original charge of this first capacitor. In this way the multiplication by the factor 2 is obtained if the two capacitors are exactly equal. However, in standard CMOS technology it is difficult to make the two capacitors sufficiently equal to each other. The essentiality of the invention is that the charge, which is loaded into the capacitors during the input mode, is kept in their respective capacitor during the output mode and that the multiplication by 2 is obtained by adding the voltages of the two capacitors. This implies that the capacitors may have different values without affecting the multiplication factor. The parasitic capacitances, especially those at the input of the amplifier, cause unequal first and second capacitors to have still some influence on the value of the multiplication factor, but this influence is far lower than in the prior art case where the charge of one capacitor is transferred to the other capacitor to realize the factor 2 multiplication. Other advantages of the AD-converter of the present invention are: Usually the required shift level is added to one of the first and second switched capacitors. The measure of the invention has the result that also the shift level is much less dependent from the value of these capacitors. - Any charge transfer implies energy dissipation which is higher the higher the operating frequency is. By avoiding the transfer of charge during the output mode the required power is substantially reduced. Any charge transfer needs time. By avoiding the charge transfer during the output mode the AD-converter operates faster, so that higher operating frequencies are possible. The multiplication without substantial charge transfer between the two capacitors can be obtained by connecting the capacitors in series during the output mode. However, the parasitic capacitances then still take some of the charge from the capacitors, so that the desired multiplication factor of 2 cannot be reached. A simple and reliable arrangement to overcome this drawback is obtained when, according to a further aspect of the invention, during the output mode the first capacitor is switched between an output and an inverting input of a differential amplifier and the second capacitor is switched between a non-inverting input of the differential amplifier and a reference voltage. With this arrangement it is achieved that the detrimental effect of the parasitic capacitance at one input terminal of the differential amplifier is counteracted by the parasitic capacitance at the other input terminal of the differential amplifier. A preferred pipeline AD-converter in accordance with the invention is further characterized in that during the input mode the first capacitor of the multiplication- and shift- means receives one of the partial signals of a differential input signal and the second capacitor of the multiplication- and shift-means receives the other of the partial signals. With a differential input signal the parasitic capacitances at the inputs of the differential amplifier are usually more equal to each other, so that an improved counteraction of their detrimental effects is obtained. Another advantage is that the shift level need to be available during the output mode, so that the comparison of the input signal with the predetermined comparison level(s) can be achieved during the input mode. When a pipeline cell has a differential signal input, such cell should also have a differential output in order to be able to be connected to the next cell with differential input. However, it is not possible to use a symmetrical arrangement with one single differential amplifier with two fed back differential outputs, because both input terminals of the amplifier are already used for the generation of one single ended output signal. Therefore, the pipeline AD-converter of the present invention may be further characterized in that a differential output is obtained by two identical multiplication- and shift-means which receive the differential input signal in counter-phase and which additionally receive a shift level which is switched in counter-phase. In order to increase the speed and consequently to increase the sample rate and/or the resolution of the AD-converter, the switched capacitor pipeline AD-converter according to the invention may still further be characterized in that the multiplication and switch means comprise two equally circuited sets of switched capacitors, one of said sets of switched capacitors having in- and output-terminals which are interconnected with the corresponding in- and output- terminals of the other of said sets of switched capacitors and in that said sets are switched so that one set operates in the input mode when the other operates in the output mode and vice versa. The invention will be further explained with reference to the attached figures. Herein shows: Figure 1 a schematic diagram of one cell of a pipeline AD-converter, Figure 2 a schematic diagram of a prior art multiplication- and shift-unit for use in a pipeline AD-converter, Figure 3 and 4 schematic diagrams of multiplication- and shift-units for use in a pipeline AD-converter according to the invention, Figure 5 a schematic diagram of one cell of a pipeline AD-converter according to the invention and Figure 6 a schematic diagram of a modified multiplication- and shift-unit for use in the AD-converter-cell of figure 5. In figure 1 a cell S of a pipeline AD-converter comprises an input terminal I to which an analog input signal N is applied which is generated by the previous cell of the converter. The signal N is applied to two comparators Pi and P 2 . The comparator Pi compares the signal N with a comparison level which is e.g. 3/8 of the maximum range of the signal (3/8 N m ). Similarly, the comparator P 2 compares the signal N with a comparison level which is e.g. 5/8 of this maximum range (5/8 V m ). The comparator Pi generates a bit d which is "zero" when N < 3/8 V m and which is "one" when N > 3/8 N m ; equally the comparator P 2 generates a bit e which is "zero" when N < 5/8 V m and which is "one" when N > 5/8 V m . The signal N is also applied to a multiplication- and shift-unit M. This unit delivers the analog output signal N 0 of the cell S which serves as input signal for the next cell in the cascade. The d- and e-bits additionally control a logic unit L which in turn controls the shift operation of the multiplication- and shift-unit M. The overall result is as follows: When the level of the input signal V is below 3/8 N m , the bits d and e are both "zero" and the signal N is amplified with the factor 2 in the unit M. No shift of the signal takes place. When the level of the input signal V is between 3/8 V m and 5/8 V m , the bit d is "one" and the bit e is "zero". The signal V is amplified with the factor 2 and the amplified signal is shifted downwardly by one half of the maximum range V m . When the level of the input signal V is above 5/8 N m , the bits d and e are both "one". The signal N is again amplified with the factor 2 and the amplified signal is shifted downwardly by the full value of the maximum range N m . The same procedure is carried out in the other cells of the cascade, in each next cell one clock period later than in its predecessor. The bits d of all cells are collected and delayed in register means (not shown). The bit d of a particular cell in the cascade is delayed one clock period more than the bit d of the next cell in the cascade, so that all the bits d of one sample are simultaneously available to constitute one digital word. The same holds for the bits e, so that finally one digital word comprising all the bits d and one digital word comprising all the bits e are simultaneously present. The two digital words are then added to constitute the output of the AD-converter. Figure 2 shows an example of a prior art implementation of the multiplication- and shift-unit in the arrangement of figure 1. The unit comprises first and second capacitors Ci and C 2 respectively and an operational amplifier A. Two bipolar switches S a and S b , and a unipolar switch S c are switched synchronously between an input mode and an output mode; in figure 2 they are drawn in the position which they have during the input mode. A tripolar switch S is controlled by the logic L (of figure 1) for delivering the required shift level N s , either 0 or l /N m or N m as is already explained with reference to figure 1. In this figure 2, for easy understanding, the switches S a , Sb and S c are shown as bipolar or tripolar switches, however in practical implementations the bipolar switch S a is preferably formed by two unipolar switches and the tripolar switch S d and the bipolar switch S b by four unipolar switches. Switch S a connects one terminal of the capacitor Ci to the input signal N during the input mode and to the output of the amplifier A during the output mode. Switch Sb connects one terminal of capacitor C 2 to the input signal N during the input mode and to the switch S d during the output mode. The other terminals of capacitors Ci and C are both connected to the inverting input (-) of the operational amplifier. The switch S c connects during the input mode the output of the operational amplifier to its inverting input. The non- inverting input (+) of this amplifier is connected to ground. In operation, during the input mode, the operational amplifier is fed back through the closed switch S c , so that the inverting input (-) assumes substantially the same potential (ground) as the non inverting input (+). Moreover, through the switches S a and Sb, both capacitors Ci and C 2 are loaded with the input signal V. During the output mode the logic L brings the switch S in the position to deliver the required shift level V s and the position of each of the switches S a to S c is changed, so that the capacitor d is now connected between the output and the inverting input of the operational amplifier and the capacitor C 2 is connected between the shift level V s and the inverting input of the operational amplifier. This implies that a current flows from the output of the operational amplifier, through capacitor C\ and through capacitor C 2 to the N s source. This current flow results in a charge transfer between the two capacitors so that the voltage of the inverting input of the operational amplifier equals the voltage (ground) of the non-inverting input. When the capacitances of these capacitors are equal (= C), the charge transfer ΔQ = (V - N S ).C and the output voltage of the operational amplifier N 0 = 2.N - N s , so that both the required amplification by the factor 2 and the required voltage shift is realized. However, when the capacitors Ci and C 2 are unequal the charge transfer ΔQ = (V - N S ).C 2 and the output signal N 0 = V.(l+C 2 /Cι) - Both the amplification factor and the voltage shift are incorrect and dependent on the values of the capacitors. It may be noticed that, in practice, the arrangement of figure 2 may be extended for differential signals when the operational amplifier has a differential output and the rest of the circuit is mirrored, whereby the (+) input terminal of the amplifier serves as the inverting input for the differential counterpart of the signal N 0 . The multiplication- and shift-unit of figure 3 reduces the dependency of the multiplication factor from the capacitors Ci and C 2 .. In this figure corresponding elements with those of figure 2 have been given the same references. A switch Si connects one terminal of the capacitor to the input signal N during the input mode and to the output of the amplifier A during the output mode. A switch S 2 connects the other terminal of the * capacitor to a reference potential (which is supposed to be zero in the calculation below) during the input mode and to the inverting input (-) of the amplifier A during the output mode. A switch S 3 connects one terminal of the capacitor C 2 to the input signal N during the input mode and to the non inverting input (+) of the amplifier A during the output mode. And a switch S 4 connects the other terminal of the capacitor C 2 to said reference potential during the input mode and to the shift level V s during the output mode. Now, during the input mode, capacitor Ci is, again, loaded with the input signal V and capacitor C is loaded with the input signal V minus the shift level V s ; therefore the voltage across C 2 is V - N s . During the output mode, the capacitor C 2 is connected between the non-inverting input of the operational amplifier A and ground, so that the voltage of said non-inverting input is N - V s . Furthermore, the operational amplifier is fed back through capacitor whereby the inverting input (-) adopts the potential N - V s of the non-inverting input (+) and the output voltage N 0 of the operational amplifier is the voltage V of capacitor Ci higher than the voltage N - N s of the inverting input (-). Therefore, the output of the operational amplifier is N 0 = 2.N - V s . This result is irrespective of the capacitance values of d and C 2 , because there is no current flowing through these capacitors during the output mode and consequently there is no charge transfer between the two capacitors during this mode. It may be observed that the voltages, mentioned above, are with reference to "ground" i.e. to the zero-potential of the shift-level N s . In practice this ground potential will usually lay above the negative supply voltage of the circuit. Practical arrangements in standard CMOS-technology may have a "ground"-potential of 0,7 Nolt above the negative supply potential and N m = 1,4 Nolt, so that the signal N may vary from 0,7 to 2,1 Nolt above the negative supply potential. The same holds for the arrangements of the other figures. Theoretically it is also possible to avoid charge transfer between the two capacitors by simply connecting the two capacitors in series during the output mode. This is depicted in figure 4. The capacitors Ci and C 2 are loaded during the input mode by V and V- Ns respectively and during the output mode they are connected in series thereby providing the output signal 2.N-N S . The operational amplifier A is connected as impedance transformer in the output lead, in order to prevent large output current from flowing through the two capacitors. However, when the unavoidable parasitic capacitances are taken into account, it may be seen that, during the output mode, the parasitic capacitance of the interconnection between the capacitors Ci and C 2 with respect to ground and the parasitic capacitance of the interconnection between the capacitor Ci and the non-inverting amplifier input (+) with respect to ground give an attenuation of the output voltage, so that the required amplification factor 2 cannot be obtained. In the arrangement of figure 3 the parasitic capacitance of the non inverting input (+) of the amplifier towards ground gives an attenuation, but the parasitic capacitance of the inverting input (-) with respect to ground gives an amplification. And these two may, in the ideal case, balance out so that the optimum multiplication factor of 2 may be obtained. A serious drawback of the embodiment of figure 3, however, is that the shift level Ns has to be available already during the input mode. Therefore, before the input mode in which the capacitors Ci and C 2 are loaded, an extra mode has to be introduced in which the comparators Pi and P 2 are active. Of course, such extra mode reduces the sampling rate of the AD-converter. Another drawback of the embodiment of figure 3 is that the parasitic capacitance at the interconnection between the capacitor C 2 and the switch S 3 gives an attenuation of the shift level N s at the non inverting input (+) of the amplifier A. These drawbacks may be overcome in the embodiment of figure 5, which shows a pipeline cell with a differential signal input. The embodiment comprises two multiplication- and shift units M and M' respectively, in which corresponding elements with those of the previous figures again have the same reference numerals. The arrangement receives a differential analog input signal consisting of two partial signals N and N m - N. The signal N varies between 0 and N m and the signal N m - N consequently varies in counter-phase between N m and 0. Most essential of this arrangement is that, during the input mode, one of the partial signals (N m - N in unit M) is loaded into the capacitor Ci and the other of the partial signals (N in unit M) is loaded into capacitor C . During the output mode, the switches Si and S 2 connect the capacitor Ci between the inverting input and the output of the operational amplifier A and the switches S 3 and S 4 connect the capacitor C 2 between the shift level N s and the non inverting input of the operational amplifier A of the unit M. Therefore, during the output mode, the non inverting input (+) of the operational amplifier receives the voltage N s - N; the fed-back operational amplifier causes its inverting input (-) to adopt the same voltage N s - N and this voltage plus the voltage N m - N of capacitor constitutes the output voltage N 0 = N s - N + N m - V = N s + V m - 2N of the unit M. Correspondingly in unit M\ the signal N is loaded during the input mode into capacitor Ci and the signal N m - N is loaded during this mode into capacitor C 2 . During the output mode the switches Si and S 2 again connect the capacitor Ci between the inverting input (-) and the output of the amplifier A of this unit M' and the switches S 3 and S 4 connect the capacitor C 2 between, in this case, the shift level N s ' and the non inverting input (+) of the operational amplifier. Therefore, during the output mode, the non inverting input of the amplifier A receives the voltage N s ' minus the voltage V m - N i.e. Ns' - Nm + V. The fed back amplifier causes its inverting input to adopt the same voltage N s ' - V m + V and this voltage plus the voltage N of capacitor Ci constitute the output N 0 ' = N s ' - V m +2.N of the unit M'. It may be noted that, while the shift level N s for the unit M is derived by switch S5, the shift level N s ' for the unit M' is derived by a switch S5' which switches inversely to the switch S5, so that the sum of the two switch levels N s + N s ' = Nm- It can further be seen, that the two output Voltages N 0 and N 0 ' vary in counter-phase between 0 and N m and that their sum N 0 + N 0 ' is also equal to N m : (N s + V m -2.V) + (V g ' - V m + 2.V) = V s + V s ' = V m . Therefore the output signals V 0 and V 0 ' are suitable to be applied to a next pipeline cell which is identical in architecture to the cell depicted in figure 5. The embodiment of figure 5 shows the two comparators Pi and P and the logic unit L which controls the two switches S 5 and S 5 1 . The comparator Pi, like the corresponding comparator of figure 1, compares the analog input signal V with the comparator level of 3/8.V m . The comparator P 2 compares the signal V m - V with the level of 3/8N m , which is identical to comparing the voltage V with the level of 5/8N m of figure 1. In each of the multiplication- and shift-units in the above figures the capacitors (Ci, C 2) ) and their switches ( Si, S 2 , S 3 , S ) may conveniently be doubled with the corresponding input and output terminals interconnected, but with the switches Si to S 4 operating in counter-phase so that one of the sets of capacitors operates in the input mode while the other operates in the output mode and vice versa. This is depicted for the unit M in figure 6 with the capacitors Ci' and C 2 ' and the switches Si' to S 4 ' . In this way the speed of the AD-converter is doubled. Moreover it is avoided that the output voltages of the amplifiers become temporarily undefined. The arrangement of figure 5 may be modified in that the switches S 2 and S 4 are deleted, the capacitor Ci is continuously connected to the inverting input (-) of the amplifier A and this connection is switched during the input mode to the output of the amplifier (as in the prior art arrangement of figure 2) and that the capacitor C 2 is continuously connected to the non inverting input (+) of the amplifier and this connection is switched during the input mode to a reference voltage of e.g. l N m . In this modification the amplifier A for one partial output signal (V 0 or V 0 ') during the input- and the output mode, so that the speed-doubling, as explained above with reference to figure 6, is not possible in this arrangement. It has to be remarked, that the switching from input mode to output mode and vice versa should preferably not be done by all switches simultaneously. In order to avoid inappropriate connections, the switches which connect the input terminals of the operational amplifier (e.g. in figure 5 the switches S2 and S4) should open before the other switches. The subsequent closing of the switches is less critical and may be done simultaneously. It is further remarked that the amplifier A in the arrangement according to the invention is preferably an operational transconductance amplifier (OTA) which transfers the voltage between the two input terminals into an output current

Claims: CLAIMS: 1. A switched capacitor pipeline AD-converter with a cascade of cells, each of said cells comprising: comparison means (Pi, P 2 ) to compare a received analog signal (V) with at least one predetermined comparison level and to output one or more digital bits representing the result of the comparison, multiplication and shift-means (M) to multiply the analog signal with a factor 2 and to shift the analog input signal with a shift level (V s ) which depends on the result of the comparison and means to output the multiplied and shifted analog signal (N 0 ) for application to the next cell in the cascade of cells, the multiplication- and shift-means (M) comprising first (Ci) and second (C ) capacitors which are both switched to receive the analog signal during an input mode, characterized in that the first (Ci) and second (C 2 ) capacitors are, during an output mode, switched to preserve their respective charges and to add their voltages for generating the analog signal (N 0 ) for the next cell. 2. A switched capacitor pipeline AD-converter as claimed in claim 1, characterized in that during the output mode the first capacitor (C is switched between an output and an inverting input of an operational amplifier (A) and that the second capacitor (C 2 ) is switched between a non-inverting input of the operational amplifier and a reference voltage. 3. A switched capacitor pipeline AD-converter as claimed in claim 2 wherein each of the cells receive a differential input signal consisting of two partial signals (V, V m - V), characterized in that during the input mode the first capacitor (Ci) of the multiplication- and shift-means (M) receives one of the partial signals of the differential input signal and the second capacitor (C 2 ) of the multiplication- and shift-means receives the other of the partial signals. 4. A switched capacitor pipeline AD-converter as claimed in claim 3 characterized by two identical multiplication- and shift-means (M, M') which receive the differential input signal (V/V m -V, V m -V/V) in counter-phase and which additionally receive a shift level (N s , N s ') which is switched in counter-phase. 5. A switched capacitor pipeline AD-converter as claimed in any of the preceding claims, characterized in that the multiplication and switch means comprise two equally circuited sets of switched capacitors, one of said sets (Ci, C 2 , Si, S , S 3 , S ) of switched capacitors having in- and output-terminals which are interconnected with the corresponding in- and output- terminals of the other of said sets (Ci', C 2 ', Si', S 2 ', S 3 ', S ') of switched capacitors and in that said sets are switched so that one set operates in the input mode when the other operates in the output mode and vice versa.

Inventors: BOUDEWIJNS ARNOLDUS J J, BOUDEWIJNS, ARNOLDUS, J., J.
Applicants: BOUDEWIJNS ARNOLDUS J J, KONINKL PHILIPS ELECTRONICS NV, BOUDEWIJNS, ARNOLDUS, J., J., KONINKLIJKE PHILIPS ELECTRONICS N.V.
Application year: 2001
Main classification: H03M1
IPC codes: H03M1