DIGITAL FILTER WITH STATE STORAGE

Abstract: A system for digital filtering includes a set of logic gates, a state storage, and a multiplexer. The state storage includes two or more storage banks and may also include combinatorial logic and/or at least one lookup table. In one application, a filtering operation according to a finite-impulse-response filter coefficient vector is performed without runtime multiplications. Applications to symmetric and antisymmetric filter coefficient vectors are described, as well as applications to filter coefficient vectors of arbitrary odd or even length.

Description: DIGITAL FILTER WITH STATE STORAGE BACKGROUND Field of the Invention [0001] This invention relates to digital signal processing. Background Information [0002] Digital signal processing techniques may be used to process signals at baseband, intermediate, and radio frequencies. In addition to their use in new applications, such techniques are also replacing analog processing techniques in existing applications such as signal filtering. The numerous advantages that a digital filter may possess over an analog counterpart include a lack of impedance matching problems, guaranteed stability and/or phase linearity, freedom from a change in response due to aging, and programmability and ease of alteration. [0003] Digital filters are implemented primarily as linear constant coefficient filters. Such filters may be broadly divided into two classes: infinite-impulse- response (IIR) filters and finite-impulse-response (FIR) filters. By incorporating feedback, IIR filters require fewer taps to achieve the same performance. Such filters cause less delay and can be implemented with less hardware than FIR filters with similar characteristics. However, IIR filters are harder to design than FIR filters, generally have nonlinear phase characteristics, and may have stability problems as well. [0004] In contrast to IIR filters, FIR filters are guaranteed to produce a bounded output in response to a bounded input. Moreover, if the coefficients of a FIR filter are symmetric (or antisymmetric), then the filter will have a linear phase response. One basic FIR filter system is illustrated in FIGURE 1. Shift register 20 receives an input signal (e.g. a series of digital values) and outputs an N-element input vector S10 to filter 40. In this example, a new input value is shifted into register 20 upon a predetermined transition of a clock signal from clock 30. Filter 40 contains a filter coefficient vector of length N, N multipliers, and an N-input adder. For each instance of input vector S10 (expressed as a series of values x 0 , xi, x 2 , ..., X N ), filter 40 outputs a value y according to the expression JV-l [0005] y = ∑ χ n K n=0 [0006] Further information on the theory and design of digital filters may be found in such documents as Electronic Filter Design Handbook, 2 nd ed., by A. B. Williams and F. J. Taylor, McGraw-Hill, New York, 1988; Digital Filtering: an introduction, E. P. Cunningham, Houghton Mifflin, Boston, 1992; and section XVI of The Circuits and Filters Handbook, ed. by W.-K. Chen, CRC Press, Boca Raton, FL, 1995. [0007] Lookup tables (LUTs) are used in various computing contexts to hold decision information that cannot easily be expressed mathematically. Two examples of information that may be stored in a LUT are (1) the mapping of IP addresses to aliases or to physical network locations, and (2) colormaps. Lookup tables have also been used in waveform generation applications to hold values that are frequently used but may be cumbersome to calculate, such as a mapping from a time index (x) into a trigonometric value (such as sin x or cos x). [0008] A digital filter as shown in FIGURE 1 is a calculation-intensive circuit. Because the set of possible input values to a digital filter is finite, the response of such a filter is completely deterministic and may be specified before runtime. However, it has not generally been feasible to use LUTs in digital filtering applications. In order to directly represent every possible output of an N-tap FIR filter which receives an input data stream M bits wide, a lookup table of size 2 M xN would be required. For an 8-bit-wide input and a relatively short 16-tap filter, such a table would have to contain 2 128 (or on the order of 10 38 ) symbol storage spaces. [0009] If the input data stream for the filter is only 1 bit wide (i.e. binary- valued), then the size of the lookup table reduces to 2 N symbol storage spaces. Even in this case, however, the size of the filter is severely limited by the resulting storage requirements: for example, a 16-tap filter would require 2 16 symbol storage spaces (i.e. one megabit of storage area for every bit of the width of the output symbols). Where the performance of a longer filter is required or the application imposes severe circuit area and/or power constraints (e.g. as in a portable device for wireless communications), FIR implementation using lookup tables may not be feasible. SUMMARY [00010] A system for digital filtering according to one embodiment of the invention includes a digital filter that has a set of logic gates, a state storage, and a multiplexer. The set of logic gates is configured and arranged to receive an input vector and a phase count signal. The phase count signal may count at a rate that is a multiple of the rate of a clock associated with the input vector. The set of logic gates is configured and arranged to produce a state select vector based on at least a portion of the phase count signal and at least a portion of the input vector. For example, the set of logic gates may map the input vector to the state select vector according to a sequence select signal based on at least a portion of the phase count signal. [00011] The state storage has two or more storage banks, each configured and arranged to receive the state select vector and to produce a state signal indicated by that vector. For example, the state storage (or each of the storage banks) may include one or more lookup tables having values based on components of a finite-impulse- response filter coefficient vector (such as a symmetric or antisymmetric filter coefficient vector). The state storage may also include combinatorial logic configured and arranged to produce a signal (such as a zero select signal) based on at least part of the state select vector. [00012] The multiplexer is configured and arranged to receive the two or more state signals and to pass a selected state signal corresponding to a bank select signal. The bank select signal is based on the phase count signal and may also be based on at least a part of the input vector. [00013] The digital filter may also include an inverter configured and arranged to produce an output signal based on the selected state signal and an invert signal. The invert signal is based on at least part of the input vector and may also be based on the phase count signal. Additionally, components of at least a portion of the state select vector may be based on the invert signal. [00014] Such a system may include a shift register configured and arranged to produce the input vector and a phase counter configured and arranged to produce the phase count signal. The system may also include additional digital filters, with one or more adders configured and arranged to produce a sum based on the selected state signals. [00015] A method of digital filtering according to an embodiment of the invention includes receiving an input vector and a phase count signal and mapping the input vector to a state select vector according to the phase count signal. The method also includes inputting the state select vector to a state storage that includes two or more storage banks. From each of the storage banks, a state signal corresponding to the state select vector is received, and one from among the state signals is selected according to a bank select signal. As noted above, the bank select signal is based on the phase count signal and may also be based on at least a part of the input vector. [00016] Additional embodiments of the invention and applications thereof are described and/or illustrated herein. For example, a system or method according to an embodiment of the invention may be applied to filter a binary data stream according to the 48-tap FIR filter shown in TABLE 1. BRIEF DESCRIPTION OF THE DRAWINGS [00017] FIGURE 1 is a block diagram of a basic FIR filter system. [00018] FIGURE 2 shows an example of a data path for a pulse-shaping filter system. [00019] FIGURES 3 A, 3B, and 3C illustrate signals α, x, y of FIGURE 2, respectively. [00020] FIGURE 4 shows a phase decomposition of a FIR filter. [00021] FIGURE 4B shows a retrieval of two values from a reduced storage for each filter output value. [00022] FIGURES 5A, 5B, and 5C illustrate an approach to reducing storage according to an embodiment of the invention. [00023] FIGURE 6A shows a block diagram of a digital filter 100 according to an embodiment of the invention. [00024] FIGURE 6B shows a block diagram of a system for digital filtering according to an embodiment of the invention. [00025] FIGURE 7 shows a block diagram of an exemplary implementation of set of logic gates 110. [00026] FIGURE 8 shows a block diagram of an exemplary implementation 112 of set of logic gates 110. [00027] FIGURE 9A shows a phase decomposition of a type 2 FIR filter. [00028] FIGURE 9B illustrates a reduction of the decomposition of FIGURE 9 A. [00029] FIGURE 10 shows a block diagram of an implementation 104 of a filter 100 according to an embodiment of the invention. [00030] FIGURE 11 A shows a block diagram of an implementation 114-1 of set of logic gates 110. [00031] FIGURE 1 IB shows a block diagram of an implementation 124cl of storage bank 124c. [00032] FIGURE 12 shows a block diagram of multiplexer 134. [00033] FIGURE 13 A shows a phase decomposition of a type 2 FIR filter. [00034] FIGURE 13B illustrates a reduction of the decomposition of FIGURE 13 A. [00035] FIGURE 14 shows a block diagram of an implementation 114-2 of set of logic gates 110. [00036] FIGURE 15 shows a block diagram of an implementation 124c2 of storage bank 124c. [00037] FIGURE 16 A shows a phase decomposition of a type 2 FIR filter. [00038] FIGURE 16B illustrates a reduction of the decomposition of FIGURE 16 A. [00039] FIGURE 17 shows a block diagram of an implementation 116-1 of set of logic gates 110. [00040] FIGURE 18 shows a block diagram of an implementation 116-2 of set of logic gates 110. [00041] FIGURE 19A shows a phase decomposition of a type 1 FIR filter. [00042] FIGURE 19B illustrates a reduction of the decomposition of FIGURE 19 A. [00043] FIGURE 20 shows a block diagram of an implementation 118 of set of logic gates 110. [00044] FIGURE 21 shows a block diagram of an implementation 200 of a digital filter according to another embodiment of the invention. [00045] FIGURE 22 shows a block diagram of an exemplary implementation of set of logic gates 210. [00046] FIGURE 23 shows a block diagram of an exemplary implementation 212 of set of logic gates 210. [00047] FIGURE 24 shows a block diagram of one binary-input implementation 202 of a filter 200. [00048] FIGURE 25 shows a block diagram of one implementation 204 of a filter 200. [00049] FIGURE 26 shows a block diagram of a set of logic gates 214. [00050] FIGURE 27 shows an exemplary implementation of multiplexer 234. [00051] FIGURE 28 shows a block diagram of a filter 250 according to an embodiment of the invention. [00052] FIGURE 29A shows a phase decomposition of a 24-tap FIR filter. [00053] FIGURE 29B shows a reduction of the decomposition of FIGURE 29A. [00054] FIGURE 30A shows a division of the reduction of FIGURE 29B. [00055] FIGURE 30A shows another division of the reduction of FIGURE 29B. [00056] FIGURE 31 A shows a phase decomposition of a 48-tap FIR filter. [00057] FIGURE 3 IB shows a division of the decomposition of FIGURE 29 A. [00058] FIGURE 32 shows a block diagram of an implementation 260 of filter 250. DETAILED DESCRIPTION [00059] Digital filters are frequently used to modify the frequency characteristics of an input signal. One such application is to control the bandwidth of a baseband signal before transmission (e.g. over a radio-frequency (RF) channel). FIGURE 2 shows one example of a data path for a pulse-shaping filter system that includes a zero-padding operation 10 and a FIR filter 45. FIGURES 3 A, B, and C provide illustrations of signals a = |K , 0 , a x , a 2 , 3 , K ], x- , and y , respectively. [00060] In this non-limiting example, input signal a is binary-valued (±1), while output signal y is more than one bit wide. Zero-padding operation 10 produces upsampled signal x- = |K , 0 ,0,0, a λ ,0,0, a 2 ,0,0, α 3 ,0,0, K ] by inserting (L - 1) zero samples for each sample of signal a (in this example, upsampling factor L = 3, and the zero samples are inserted after each data value). Filter 45 filters signal x- to produce pulse-shaped signal y . Coefficients for one particular example of a pulse- shaping filter are shown in TABLE 1 below; this 48-tap symmetric filter is specified in Table 6.1.3.1.10-1 of TIA/EIA Interim Standard IS-95-A (May 1995, Telecommunications Industry Association, Arlington, NA) for a binary data stream upsampled by L = 4. TABLE 1. [00061] In an application where the Ν-element filter coefficient vector is specified for a zero-padded input stream, the number of nonzero terms that contribute to each output value is limited by N/L rather than N (where L is the upsampling factor and N is the length of the filter coefficient vector). Expressions for each of the L output values y; that are produced for one instance of input vector [a 0 , ai, a , a 3 ] follow, each expression including N/L possibly nonzero terms (in this non-limiting example, L = 4 andN = 16): y 0 = a 0 h 0 + aihk + a 2 h 8 + a 3 hι 2 ; (1) yi = ao i + aιh 5 + a 2 h 9 + a 3 hι 3 ; (2) y 2 = a 0 h 2 + aιh 6 + a 2 hι 0 + a 3 hι 4 ; (3) y 3 = a 0 h 3 + aιh 7 + a 2 hι i + a 3 hι 5 . (4) These expressions are illustrated in FIGURE 4A, which demonstrates that the operations of such a filter may be modeled as separate applications of the input vector to L nonoverlapping cosets (or phases) of the filter coefficients. [00062] The zero-padding and filtering operations shown in FIGURE 2 may also be combined into a single filtering operation. In one possible implementation of these principles, the values of the N terms of expressions (l)-(4) are precalculated and stored for each possible input vector. These values are then retrieved at runtime (according to the phase number and the particular instance of the input vector) as output values of the filter. In such case, the total number of states to be stored may be reduced from P N (2 N for binary input) to L __ P N L (L _ 2 N/L for binary input), where P is the number of possible states for each component of the input vector, and the filter is clocked at a rate at least L times greater than the clock associated with the input vector (e.g. clock 30 in FIGURE 1). In the example of FIGURE 4A, the total number of states to be stored may be reduced from 2 16 to 2 6 for binary input (with the filter output values being arbitrarily wide). [00063] In a case where the filter coefficient vector is symmetric (hj = h (N -i-i)), the maximum required storage capacity may be reduced further (i.e. by a factor of 2). FIGURE 4B illustrates how two values may be retrieved from the reduced storage at runtime (e.g. in successive filter clock periods), each according to the phase number and a respective half of the input vector. These two values are then added together to produce a filter output value. In this case, the filter is clocked at a rate at least 2L times greater than the clock associated with the input vector. Additionally, the two retrieved values to be added may be many bits wide, and an adder having considerable complexity (and possibly a considerable delay) may be required to perform the summing operation. [00064] FIGURES 5A, 5B, and 5C illustrate an alternative approach to reducing the required storage capacity in a case where the filter coefficient vector is symmetric. FIGURE 5 A shows how the symmetry of the coefficients can be exploited to allow the entire input vector to be applied as an index to the reduced storage for each phase. In FIGURE 5B, the L phases are reduced to L/2 banks indexed by a sequence vector having two states. In the first state, the input vector is mapped to the sequence {a 0 , a 3 , ai, a 2 }. In the second state, the input vector is mapped to the sequence {a 3 , a 0 , a 2 , a \ ). FIGURE 5C demonstrates how each desired filter output may be retrieved in a single indexing operation according to a bank select signal and a mapping of the input vector to a selected sequence. [00065] FIGURE 6A shows a block diagram of a digital filter 100 according to an embodiment of the invention. A set of logic gates 110 receives the input vector S10 and a phase count signal S20. In an exemplary implementation, phase count signal S20 is clocked at a rate L times that of the clock associated with input vector S10, such that phase count signal S20 counts from 0 to (L - 1) for each instance of the input vector. Based on at least a portion of phase count signal S20, set 110 selects a sequence and maps the input vector to a state select vector S30 according to the selected sequence. Set 110 also produces a bank select signal S40 based on phase count signal S20 (or a portion thereof). [00066] State storage 120 includes two or more storage banks 120i, each receiving state select vector S30. Each storage bank 120i may include combinatorial logic and/or a lookup table having stored values. In some implementations, two or more of storage banks 120i may include different portions of a single lookup table. [00067] Each storage bank 120i outputs a state signal S60i. Multiplexer 130 receives the state signals S60i and passes one among them as selected state signal S50 according to bank select signal S40. [00068] In one binary-input implementation of the example illustrated in FIGURE 5C, state storage 120 has two storage banks 120a (bank 0) and 120b (bank 1). In this implementation, bank 0 stores the sixteen values represented by the expression (± h 0 ± h 3 ± l ± h 7 ), while bank 1 stores the sixteen values represented by the expression (± hι ± h 2 ± h 5 ± h 6 ). [00069] FIGURE 6B shows a block diagram of a system for digital filtering according to an embodiment of the invention. Shift register 20 receives an input signal S5 and a clock signal from clock 30 and produces an N/L-component input vector S10. Filter 100 receives input vector S10 and phase select signal S20 (from phase counter 300) and produces selected state signal S50. As noted above, filter 100 produces L output values for each instance of input vector S10. [00070] FIGURE 7 shows a block diagram of an exemplary implementation of set of logic gates 110 for a type 2 FIR filter (i.e. having a symmetric filter coefficient vector of even length). In this implementation, multiplexer pairs M10 and M20 map input vector S10 to state select signal S30, switching between the two sequences according to sequence select signal S50 (here, the high bit of phase count signal S20) and inverter 110. XOR gate X40 receives phase count signal S20 and produces bank select signal S40, which controls multiplexer 130 to select between the state signals S60 produced by storage banks 120a, 120b (banks 0, 1) of state storage 120 as discussed above. [00071] FIGURE 8 shows a block diagram of an exemplary implementation 112 of set of logic gates 110 for a type 4 FIR filter (i.e. having an antisymmetric filter coefficient vector of even length). In this implementation, inverters 120 and 130 invert the components in the latter half of input vector S10 (here, a 2 and a 3 ). [00072] A filter according to an embodiment of the invention as shown in FIGURE 6 is not limited to implementations in which input vector S10 has binary- valued components. For example, implementations of sets of logic gates 110 and 112 as shown in FIGURES 7 and 8 may also be used in applications where components of input vector S10 have more than one bit. In such cases, multiplexer pairs M10, M20 may be configured to select between multi-bit input values (in response to a binary control signal), and inverters 120, 130 may be configured to invert multi-bit data values. [00073] Sets 110 (and 112) as shown in FIGURES 7 and 8 may be used in implementing filter coefficient vectors of arbitrary even length N by adding additional multiplexer pairs (and one or more corresponding inverters) as appropriate. As noted above, such filters may be decomposed into (and state storage 120 may be implemented to include) L/2 banks. [00074] FIGURE 9A illustrates an example of a phase decomposition of a Type 2 FIR filter in which L is odd and N/L is even (here, L = 5, N = 10, and N/L = 2). As shown in FIGURE 9B, such a case (having L phases) may be condensed to ceil(L/2) banks (ceil(x) denoting the smallest integer not less than x), where the highest numbered bank has only one sequence (sequence number X indicating 'don't care'). [00075] FIGURE 10 shows a block diagram of an implementation 104 of a filter 100 according to an embodiment of the invention for a case where L is odd and N/L is even (e.g. as shown in FIGURE 9B). In this implementation, state storage 120 include ceil(L/2) banks, each receiving state select vector S34, and multiplexer 134 selects from among the ceil(L/2) state signals S60i according to bank select signal S44. [00076] FIGURE 11 A shows a block diagram of an implementation 114-1 of set of logic gates 110 suitable for the particular case illustrated in FIGURE 9B. In this implementation, XOR gate X60 receives the two high bits of phase count signal S24 (which counts from 0 to (L-l) = 4) and produces sequence select signal S54, and the two low bits of phase count signal S24 serve as bank select signal S44. [00077] As noted in FIGURE 9B, the sequence in which a 0 and a] are mapped to state select signal S34 is irrelevant to bank 2, as both input values correspond to the same filter coefficient value. Another consequence of this correspondence is that if the value of a 0 is the inverse of the value of a\, the filter output is zero. In fact, by including logic to produce zero and inverted values at runtime, bank 2 may be implemented in this case with only one stored value. [00078] FIGURE 1 IB shows a block diagram of an implementation 124cl of storage bank 124c for the binary input case. XOR gate X70 receives state select vector S34. Nia zero select signal S70-1, XOR gate S70 causes multiplexer M40 to output a zero value if the two components of state select vector differ. Value storage 210-1 stores only one value, which is received by XOR gate X80. If invert signal S80-1 (either component of state select vector S34) is high, the stored value is inverted. XOR gate X80 may be implemented to receive one multi-bit value (the stored value) and one binary value (invert signal S80-1). Depending upon the mapping between input and output values in the particular implementation, invert signal S80-1 may be inverted before being inputted to XOR gate X80. [00079] FIGURE 12 shows a block diagram of multiplexer 134 suitable for use in the implementation 104 of filter 100 shown in FIGURE 10. Multiplexer 134a selects between the state signals S64 of bank 0 and bank 2 according to the high bit of bank select signal S44, and multiplexer 134b selects between the state signal S64 of bank 1 and the output of multiplexer 134a according to the low bit of bank select signal S44. [00080] FIGURE 13 A illustrates another example of a phase decomposition of a Type 2 FIR filter in which L is odd and Ν/L is even (here, L = 5, Ν = 20, and Ν/L = 4). FIGURE 13B shows how the L phases may be condensed to ceil(L/2) banks. [00081] FIGURE 14 shows a block diagram of an implementation 114-2 of set of logic gates 110 suitable for the case illustrated in FIGURE 13B. Multiplexer pairs M10 and M20 map input vector S14 to state select vector S34 according to sequence select signal S54 and its inverse. Set 114-2 may be used in implementing filter coefficient vectors of arbitrary even length Ν by adding additional multiplexer pairs (and one or more corresponding inverters) as appropriate. [00082] FIGURE 15 shows a block diagram of an implementation 124c2 of storage bank 124c suitable for the case illustrated in FIGURE 13B. In this case, value storage 210-2 stores only four values. Nia a collection of logic gates (XOR gates XI 10, X120, X130; AND gates A10, A20, A30; OR gate O10; and inverter 140) and multiplexer M50, state select vector S34 is processed to select the appropriate value from value storage 210-2 and to produce zero select signal S70-2 and invert signal S80-2. Other collections of logic gates may be used, and Boolean expression minimization techniques (such as Karnaugh maps) may be used to produce such other collections and/or to extend implementation 124c2 to state select vectors having more components while minimizing the size of value storage 210. As with XOR gate X80 described above, XOR gate X90 may be implemented to receive one multi-bit value (the selected stored value) and one binary value (invert signal S80-2). [00083] As discussed with reference to FIGURE 8, sets of logic gates 114-1 and 114-2 may be extended to apply to the antisymmetric case by inverting the components in the latter half of input vector S10. [00084] FIGURE 16A illustrates an example of a phase decomposition of a type 2 FIR filter in which L is even and N/L is odd (here, L = 4, N = 20, and N/L = 5). FIGURE 16B shows how the L phases may be condensed to L/2 banks. [00085] FIGURE 17 shows a block diagram of an implementation 116-1 of set of logic gates 110 suitable for the case illustrated in FIGURE 16B. As the middle component of input vector SI 6 (here, a 2 ) shares filter coefficients with no other component, this value may pass through to the same component of state select vector S36 for all sequences. [00086] FIGURE 18 shows a block diagram of an implementation 116-2 of set of logic gates 110 suitable for a case as illustrated in FIGURE 16B in which the filter coefficient is antisymmetric. Multiplexer M70 selects between the middle component of input vector SI 6 and its inverse (as produced by inverter 150) according to sequence select signal S50. In applications where components of input vector S16 have more than one bit, multiplexer M70 may be configured to select between multi- bit input values (in response to a binary control signal), and inverter 150 may be configured to invert a multi-bit data value. [00087] Sets of logic gates 116-1 and 116-2 may be used in implementing filter coefficient vectors of arbitrary even length N by adding additional multiplexer pairs (and one or more corresponding inverters) as appropriate. As noted above, such filters may be decomposed into (and state storage may be implemented to include) ceil(L/2) banks. [00088] FIGURE 19A illustrates an example of a phase decomposition of a type 1 FIR filter (i.e. having a symmetric filter coefficient of odd length). In such case, both L and N/L are odd (here, L = 5, N = 15, and N/L = 3). FIGURE 19B shows how the L phases may be condensed to ceil(L/2) banks. [00089] FIGURE 20 shows a block diagram of an implementation 118 of set of logic gates 110 suitable for a case as illustrated in FIGURE 19B. Implementation 118 may be applied to cases of an antisymmetric filter coefficient vector (type 3) and/or components of input vector SI 8 having more than one bit by extension as described herein. Additionally, set of logic gates 118 may be used in implementing filter coefficient vectors of arbitrary odd length N by adding additional multiplexer pairs (and one or more corresponding inverters) as appropriate. [00090] FIGURES 1 IB and 15 above demonstrate how the number of stored values in a storage bank may be reduced by applying an invert signal decoded from the input vector. This principle of exploiting symmetry among the set of output states may also applied more generally to reduce the size of the state storage by a factor of 2. FIGURE 21 shows a block diagram of an implementation 200 of a digital filter according to another embodiment of the invention. In this implementation, set of logic gates 210 produces an invert signal S52, and an inverter (here, XOR gate X50) produces an output signal S70 based on selected state signal S50 (selected from outputs of state storage 220) and invert signal S52. [00091] FIGURE 22 shows a block diagram of an exemplary implementation of set of logic gates 210 to a type 2 FIR filter bank decomposition as shown in FIGURE 5C. In this implementation, the output of a multiplexer of one of the multiplexer pairs M10, M20 serves as invert signal S50. XOR gates XI 0, X20, and X30 receive invert signal S50 and the signals from the other multiplexers and produce the components of state select vector S230. As state storage 220 is only half as large as state storage 120, state select vector S230 is one bit narrower than state select vector S30 as shown in FIGURE 7. [00092] In a case where components of input vector S 10 have more than one bit, one bit of the output of a multiplexer of one of the multiplexer pairs M10, M20 serves as invert signal S50. In such case, the other bits of the output of that multiplexer are inputted to an XOR gate that receives invert signal S50. Like XOR gates XI 0, X20, and X30 described above, this XOR gate also produces components of state select vector S230. [00093] FIGURE 23 shows a block diagram of an exemplary implementation 212 of set of logic gates 210 for a type 4 FIR filter. In this implementation, XOR gate X50 receives sequence select signal S50 and one bit of the output of a multiplexer of one of the multiplexer pairs M10, M20 and produces invert signal S52. [00094] Implementations of filter 200 and set of logic gates 210 may be extended to cases of filter coefficient vectors of arbitrary length, and/or to various odd/even relationships of L and N/L, as described above with respect to implementations of filter 100 and set of logic gates 110. [00095] FIGURE 24 shows a block diagram of one binary-input implementation 202 of a filter 200 that is suitable for application to the example illustrated in FIGURE 5C. In this implementation, state storage 222 has two storage banks 222a (bank 0) and 222b (bank 1), with bank 0 storing the eight values represented by the expression (h 0 ± h 3 ± ± h 7 ) and bank 1 storing the eight values represented by the expression (hi ± h 2 ± h 5 ± h 6 ). [00096] In some applications, it may be desirable to divide one or more of the storage banks into subbanks. For example, it may be desired to modify a state storage 222 as described above by dividing each bank into two subbanks, each subbank receiving the state select vector and producing a state signal. FIGURE 25 shows a block diagram of one such implementation 204 in which subbanks 224a0 and 224al each store the four values represented by the expression (s 0 + si ± s 2 ± s 3 ) [(ho + h 3 ± lu ± h ) and (hi + h ± h 5 ± h 6 ), respectively], while subbanks 224b0 and 224b 1 each store the four values represented by the expression (s 0 - si ± s 2 ± s ) [(ho - h 3 ± φ ± h ) and (hi - h 2 ± h 5 ± h 6 ), respectively]. [00097] FIGURE 26 shows a block diagram of a set of logic gates 214 suitable for use in filter 204. Although the total number of stored states in state storage 224 is the same as the total number of stored states in state storage 222, the number of banks receiving the state select vector and producing a state signal is greater in filter 204 (here, by a factor of two). Consequently, multiplexer 134 selects from among a greater number of inputs. At the same time, the number of states stored in each bank 224 is less (here, also by a factor of two) such that state select vector S234 may be more narrow than state select vector S230. [00098] In this particular example, set 214 is derived from set 210 by moving one of the state select vector components (here, the component corresponding to state s 0 in set 210) to bank select signal S44. In other applications, a different number of banks may be implemented, with a corresponding exchange of components between the state select vector and the bank select signal. FIGURE 27 shows a block diagram of an exemplary implementation of multiplexer 234. [00099] FIGURE 28 shows a block diagram of a filter 250 according to an embodiment of the invention. In this embodiment, input vector S10 is split into two separate input vectors SlOa and SI 0b, each being inputted to a filter 100 (constructed e.g. as shown in FIGURE 6A). The output signals S70 produced by filters 100 are added by adder 400 to obtain filter output signal S80. In one implementation, filters 200a,b receive the same phase count signal; in another implementation, filters 200a,b receive the same sequence select and bank select signals (generated e.g. as described herein). [000100] FIGURE 29A shows a phase decomposition of a 24-tap FIR filter (here, L = 4), and FIGURE 29B shows a reduction of this symmetric (or anti-symmetric) filter into ceil(L/2) banks. Assuming a binary input, the total number of stored states in an application of filter 200 to this example may reach (L _ 2 (N L ~1 ) or 128. [000101] FIGURE 30A shows a division of the reduction of FIGURE 29B into two sections. In an exemplary application of filter 250 to this filter coefficient vector, input vector SlOa includes the components of the first section (h 0 -h 3 ) and input vector SI 0b includes the components of the second section Qu-hn). The total number of stored states in each filter lOOi may reach L times 2 to the power (length of input vector SlOi minus 1). Assuming a binary input in this example, this limit may be calculated as (4 _ 2 2"1 ) or 8 for filter 200a, plus (4 _ 2 4-1 ) or 32 for filter 200b, for a total of 40. [000102] An even further reduction in the total number of stored states may be achieved by using the three-part division shown in FIGURE 30B. In this example, filter 250 is implemented with three filters 100, each receiving a four-component input vector SlOi, and a three-input adder to receive the three output signals S70 and to produce the filter output signal S80. In this example, the total number of stored states may reach only 24 (or 3 _ 8). [000103] In another example, FIGURE 31 A shows a phase decomposition of a 48- tap four-times-oversampled symmetric FIR filter as shown in TABLE 1. Each of the four phase expressions may then be divided into three four-term blocks as shown in FIGURE 3 IB, each block having 16 possible values (for binary input) and serving as an input vector to one of the filters in a three-filter implementation as described above. [000104] Note that the particular grouping of input values shown in FIGURE 3 IB is only one of many possible groupings. For example, FIGURE 31C shows another such grouping, which differs from that of FIGURE 3 IB in the placement of coefficients h 4 -h 7 and h 8 -hπ. A particular grouping may also be chosen on the basis of the magnitude of the corresponding filter coefficients, such that blocks having filter coefficients of low magnitude may be formed for processing using a more narrow logical bus width, storage area, etc. than blocks having filter coefficients of higher magnitude. [000105] In a further example, the stored state values may be normalized. In one implementation, a normalization of the filter coefficient vector is calculated according to a factor determined by dividing the maximum possible output value of the filter (e.g. as determined by the unnormalized filter coefficient vector) by the maximum value that may be represented in the number of bits provided for the filter output. In an exemplary application, normalization is used to support an integer implementation of a filter coefficient vector having floating-point components. [000106] FIGURE 32 shows a block diagram of an implementation 260 of filter 250 as applied to the 48-tap filter of TABLE 1 divided as shown in FIGURE 3 IB. In this example, output signals S70a, S70b, and S70c are eight, nine, and eleven bits wide, respectively, and the outputs of adders 402a and 402b are nine and eleven bits wide, respectively. Filters 200a and 200b are configured to output signed integer values in offset two's complement representation, while filter 200c and adder 402b are configured to output signed integer values in two's complement representation. This particular configuration eliminates the need for an additional adder to process the carry bits from the three filters. [000107] Depending on the numeric representation or representations used in a particular application, it may be desirable to perform additional logic operations when an invert signal is invoked in an implementation as shown, for example, in FIGURE 21. For example, negation of a value encoded in two's complement representation includes both complementation and addition of one. One approach in such case is to include a two-input adder having one input tied to zero, receiving as the other input output signal S70, and having invert signal S50 as the carry-in signal. [000108] FIGURE 32 demonstrates how inversion may be handled without additional logic. Numbers encoded in offset two's complement representation differ from numbers encoded in two's complement representation by including a bias of 0.5. For example, the numbers 00101 and 11010 in offset two's complement representation signify the decimal values 5.5 and -5.5, respectively. One feature of offset two's complement representation is that complementing such a number is equivalent to negating it. As each of the two values inputted to adder 402a has a bias of 0.5, the carry_in input to this adder is set to one, and the adder outputs a value in two's complement representation. [000109] Adder 402b receives two inputs in two's complement representation. As negation of a value encoded in two's complement representation includes both complementation and addition of one, invert signal S50 is inputted to the carry_in input of adder 402b to provide the value of one in case of negation. [000110] The foregoing presentation of the described embodiments is provided to enable any person skilled in the art to make or use the present invention. Various modifications to these embodiments are possible, and the generic principles presented herein may be applied to other embodiments as well. For example, the invention may be implemented in part or in whole as a hard-wired circuit, as a circuit configuration fabricated into an application-specific integrated circuit, or as a firmware program loaded into non- volatile storage or a software program loaded from or into a data storage medium as machine-readable code, such code being instructions executable by an array of logic elements such as a microprocessor or other digital signal processing unit. [000111] In other implementations of filters as described herein, the actual number of stored states may be lower than the limits indicated above. For example, if it is known that certain forms of the input vector will not be encountered in a particular application, states corresponding to those forms need not be stored. [000112] Reduction of the number of stored states by producing and applying an invert signal is described herein. A similar reduction may be performed with respect to other linear relations that may exist among the possible filter states. For example, states in a first portion of the set of possible filter states may be expressible as a multiple of corresponding states in a second portion of the set of possible filter states. In such case, it may be more efficient in a particular application to store only the second portion of states and to derive states of the first portion as needed at runtime. [000113] A filter according to an embodiment of the invention may also be used in conjunction with a circuit configuration as described in copending United States Provisional Patent Application No. 60/245,232, entitled "CIRCUIT FOR DIGITAL DATA TRANSMISSION," attorney docket no. 010086P, filed on November 3, 2000. Thus, the present invention is not intended to be limited to the embodiments shown above but rather is to be accorded the widest scope consistent with the principles and novel features disclosed in any fashion herein. We claim:

Claims: CLAIMS 1. A system for digital filtering, said system including a digital filter comprising: a set of logic gates, said set being configured and arranged to receive an input vector and a phase count signal and to produce a state select vector based on at least a portion of the phase count signal and at least a portion of the input vector; a state storage including a plurality of storage banks, each storage bank configured and arranged to receive the state select vector and to produce a state signal indicated by the state select vector; and a multiplexer configured and arranged to receive the plurality of state signals and a bank select signal based on at least a portion of the phase count signal and to pass a selected state signal, said selected state signal corresponding to the bank select signal. 2. The system for digital filtering according to claim 1, wherein the state storage includes at least one lookup table. 3. The system for digital filtering according to claim 2, wherein the at least one lookup table has values based on components of a finite-impulse-response filter coefficient vector. 4. The system for digital filtering according to claim 3, wherein the at least one lookup table has values based on components of a symmetric filter coefficient vector. 5. The system for digital filtering according to claim 3, wherein the at least one lookup table has values based on components of an antisymmetric filter coefficient vector. 6. The system for digital filtering according to claim 1, wherein the state storage includes combinatorial logic configured and arranged to produce a zero select signal based on at least a portion of the state select vector. 7. The system for digital filtering according to claim 1, wherein each among the plurality of storage banks includes at least one lookup table having values based on components of a finite-impulse-response filter coefficient vector. 8. The system for digital filtering according to claim 1, wherein the set of logic gates is configured and arranged to map the input vector to the state select vector according to a sequence select signal based on at least a portion of the phase count signal. 9. The system for digital filtering according to claim 1, wherein the bank select signal is based on at least a portion of the input vector. 10. The system for digital filtering according to claim 1, said filter further comprising an inverter configured and arranged to receive the selected state signal and an invert signal and to produce an output signal, wherein the invert signal is based on at least a portion of the input vector. 11. The system for digital filtering according to claim 10, wherein the invert signal is based on the phase count signal. 12. The system for digital filtering according to claim 10, wherein the components of at least a portion of the state select vector are based on the invert signal. 13. The system for digital filtering according to claim 1, said system further including a shift register configured and arranged to receive an input signal according to a clock signal and to produce the input vector. 14. The system for digital filtering according to claim 13, said system further including a phase counter configured and arranged to produce the phase count signal, wherein a counting rate of the phase count signal is a multiple of the rate of the clock signal. 15. The system for digital filtering according to claim 1, said system further including a second filter configured and arranged to receive a second input vector and to produce a signal based on a second selected state signal, and an adder configured and arranged to add a signal based on the selected state signal and the signal based on a second selected state signal. 16. The system for digital filtering according to claim 15, wherein said system is configured and arranged to receive values of an input signal over time, and wherein the components of the input vector correspond to values of the input signal received over a first time period, and wherein the components of the second input vector correspond to values of the input signal received over a second time period different than the first time period. 17. A system for digital filtering, said system including: a shift register configured and arranged to receive the input signal and to produce a plurality of input vectors; a plurality of digital filters configured and arranged to receive a phase count signal, each digital filter comprising: a set of logic gates, said set being configured and arranged to receive a corresponding input vector and the phase count signal and to produce a state select vector based on at least a portion of the phase count signal and at least a portion of the input vector, a state storage including a plurality of storage banks, each storage bank configured and arranged to receive the state select vector and to produce a state signal indicated by the state select vector, and a multiplexer configured and arranged to receive the plurality of state signals and a bank select signal based on at least a portion of the phase count signal and to pass a selected state signal, said selected state signal corresponding to the bank select signal; and at least one adder configured and arranged to produce a sum based on the plurality of selected state signals, wherein the components of each of the plurality of input vectors correspond to values of the input signal received over a corresponding time period, each input vector corresponding to a different time period. 18. The system for digital filtering according to claim 17, wherein the state storage of at least one of the digital filters includes at least one lookup table. 19. The system for digital filtering according to claim 18, wherein the at least one lookup table has values based on components of a fmite-impulse-response filter coefficient vector. 20. The system for digital filtering according to claim 17, wherein the set of logic gates of at least one digital filter is configured and arranged to map the corresponding input vector to the corresponding state select vector according to a sequence select signal based on at least a portion of the phase count signal. 21. The system for digital filtering according to claim 17, wherein the bank select signal of at least one digital filter is based on at least a portion of the corresponding input vector. 22. The system for digital filtering according to claim 17, wherein at least one of the digital filters further comprises an inverter configured and arranged to receive the corresponding selected state signal and an invert signal and to produce an output signal, wherein the invert signal is based on at least a portion of the corresponding input vector. 23. The system for digital filtering according to claim 22, wherein the invert signal is based on the phase count signal. 24. The system for digital filtering according to claim 22, wherein the components of at least a portion of the corresponding state select vector are based on the invert signal. 25. A method of digital filtering, said method comprising: receiving an input vector and a phase count signal; mapping the input vector to a state select vector according to at least a portion of the phase count signal; inputting the state select vector to a state storage, said state storage comprising a plurality of storage banks; receiving a state signal corresponding to the state select vector from each of the plurality of storage banks; and selecting a state signal from among the plurality of state signals according to a bank select signal. 26. The method of digital filtering according to claim 25, wherein the state storage has a plurality of stored values, and wherein each of at least a subset of the state signals is based on a corresponding one of the stored values. 27. The method of digital filtering according to claim 26, wherein the stored values are based on components of a finite-impulse-response filter coefficient vector. 28. The method of digital filtering according to claim 26, wherein the stored values are normalized with respect to a predetermined maximum filter output value. 29. The method of digital filtering according to claim 25, wherein the bank select signal is based on at least a portion of the input vector.

Inventors: BUTLER BRIAN K, JOHN DEEPU, MOHSENI JAFAR M, ZHANG HAITAO, BUTLER, BRIAN, K., JOHN, DEEPU, MOHSENI, JAFAR, M., ZHANG, HAITAO
Applicants: QUALCOMM INC, QUALCOMM INCORPORATED
Application year: 2001
Main classification: H03H
IPC codes: G06F17, H03H17, H04L25