TRANSFORM ENGINE FOR DISCRETE MULTI-TONE TRANSCEIVERS

Abstract: A transmitter (110) includes an encoder (130), a sequence generator (140), a transform engine (190), and a buffer (150). The encoder (130) is adapted to generate a complex-valued symbol sequence. The sequence generator (140) receives the complex-valued symbol sequence and generates a real-valued symbol sequence based thereon. The transform engine (190) transforms the real-valued symbol sequence to a time domain sample sequence and can be implemented as an hartley transform. The buffer (150) is adapted to store the time domain sample sequence. The receiver (120) shares the same transform engine (190) for the reverse operation.

Description: TRANSFORM ENGINE FOR DISCRETE MULTI TONE TRANSCEIVERS TECHNICAL FIELD This invention relates generally to the field of telecommunications, and, more particularly, to a reduced complexity fast transform engine useful in broadband data applications, such as discrete multi-tone technologies BACKGROUND ART In communications systems, particularly telephony, it is common practice to transmit signals between a subscriber station and a central switching office via a two-wire, bi-directional communication channel The Plain Old Telephone System (POTS), designed pπmaπh for voice communication, provides an inadequate data transmission rate for many modern applications To meet the demand for high-speed communications, designers have sought innovative and cost-effective solutions that take advantage of the existing network infrastructure Several technological advancements have been proposed in the telecommunications industry that make use of the existing network of telephone wires One of these technologies is the xDSL technology DSL technology uses the existing network of telephone lines for broadband communications An ordinary twisted pair equipped with DSL interfaces can transmit videos, television, and high-speed data DSL systems use digital signal processing (DSP) to increase throughput and signal quality through common copper telephone wire Certain DSL systems provide a downstream data transfer rate from the DSL Point-of-Presence (POP) to the subscriber location at speeds of about 1 5 Megabits per second (MBPS) up to 8 MBPS The transfer rate of 1.5 MBPS, for instance, is fifty times faster than a conventional 28 8 kilobits per second (KBPS) transfer rate One popular version of the DSL technology is the Asymmetrical Digital Subscriber Line (ADSL) technology The ADSL standard is described in ANSI Tl 413 Issue 2, entitled, "Interface Between Networks and Customer Installation - Asymmetric Digital Subscriber Line (ADSL) Metallic Interface," hereinafter referred to as the ADSL standard The increased processing loads associated with the advanced communications algorithms necessary to support such high bandwidth connections make hardw are selection difficult One such area in which it is difficult to meet the processing demands lies in the area of transforms necessary to change between the time and frequency domains in the transmitter and receiver For example, the ADSL standard calls for a discrete multi-tone (DMT) modulation/demodulation scheme implemented using discrete Fourier transform (DFT) and inverse discrete Fourier transform (IDFT) pairs in the transceiver unit Typically, these transforms are implemented using well- known fast Fourier transform (FFT)Λnverse fast Fourier transform (IFFT) pairs The computational loads encountered in the transceiver are sufficiently great such that the use of even the most powerful general purpose processors is precluded Accordingly, special purpose application specific integrated circuits (ASICs) have been developed Such ASICs, such as an Am79C 135 offered by Advanced Micro Devices, Inc , use an FFT algorithm optimized for real-valued data in the receiver (RX) section and an IFFT algorithm optimized for complex-valued data in the transmitter section This division attempts to achieve the maximum computational efficiency by allowing the most efficient individual FFT and IFFT algorithms to be used This increase in computational efficiency comes at the cost of compactness, as two separate Fourier transform blocks must be implemented in silicon Since these two blocks are among the most complex blocks in the DMT ASIC, they represent major components to the overall cost of the device One technique for addressing the increased silicon area necessary to support separate FFT and IFFT algorithms involves the use of a single transform engine adapted to operate on complex-valued data Such an implementation saves silicon area at the expense of computational efficiency, as the cycles used to process the complex components of the real-valued data in the RX path are wasted The present invention is directed to overcoming, or at least reducing the effects of, one or more of the problems set forth above DISCLOSURE OF INVENTION One aspect of the present invention is seen in a transmitter including an encoder, a sequence generator, a transform engine, and a buffer The encoder is adapted to generate a complex-valued symbol sequence The sequence generator is adapted to receive the complex-valued symbol sequence and generate a real-valued symbol sequence based thereon The transform engine is adapted to transform the real-valued symbol sequence to generate a time domain sample sequence The buffer is adapted to store the time domain sample sequence Another aspect of the present invention is seen in a method for communicating data The method includes receiving a complex-valued transmit symbol sequence A real-valued transmit symbol sequence is generated based on the complex-valued transmit symbol sequence A time domain transmit sample sequence is generated based on the complex-valued transmit symbol sequence using a transform engine The time domain transmit sample sequence is stored for transmission on a communications channel BRIEF DESCRIPTION OF THE DRAWINGS The invention may be understood by reference to the following description taken in conjunction with the accompanying drawings, in which like reference numerals identify like elements, and in which Figure 1 is a simplified block diagram of an illustrative communications system in accordance with the present invention, and Figure 2 is a simplified block diagram of a portion of a transceiver in one of the modems of Figure 1 While the invention is susceptible to various modifications and alternative forms, specific embodiments thereof have been shown by way of example in the drawings and are herein described in detail It should be understood, however, that the description herein of specific embodiments is not intended to limit the invention to the particular forms disclosed, but on the contrary, the intention is to cover all modifications, equivalents, and alternatives falling within the spirit and scope of the invention as defined by the appended claims MODE(S) FOR CARRYING OUT THE INVENTION Illustrative embodiments of the invention are described below In the interest of clarity, not all features of an actual implementation are described in this specification It will of course be appreciated that in the development of any such actual embodiment, numerous implementation-specific decisions must be made to achieve the developers' specific goals, such as compliance with system-related and business-related constraints, which will vary from one implementation to another Moreover, it will be appreciated that such a development effort might be complex and time-consuming, but would nevertheless be a routine undertaking for those of ordinary skill in the art having the benefit of this disclosure Referring to Figure 1, a block diagram of a communications system 10 is provided The communications system 10 includes a first modem 15 coupled to a second modem 20 through a connection 25 In the illustrated embodiment, the first modem 15 is located at a customer premise 30, and the second modem 20 is part of a central office 35 The connection 25 is an ordinary twisted pair connection, as is common in present-day telephone networks However, other connection types (e g , wireless, cellular, etc ) are contemplated, depending on the specific implementation Also, it is contemplated that the second modem 20 may not be part of the central office 35, but rather the second modem 20 may be installed in a second customer premise (not shown) For purposes of illustration, the modems 15, 20 are described as they might be implemented under the ADSL protocol (ANSI Tl 413) It is contemplated that the techniques described herein may be applied to other communication protocols, depending on the specific implementation The functions described herein may also be implemented in other communications devices other than modems Turning now to Figure 2, a simplified block diagram of a transceiver 100 used in one of the modems 15, 20 of Figure 1 is provided For clarity and ease of illustration not all features of the transceiver 100 are shown The transceiver includes a transmitter functional block 1 10 and a receiver functional block 120 Onlv those elements useful to an understanding of the transform functions of the transceiver 100 are described Generally, frequency domain data representing downstream data being sent by the modem 15, 20 is transformed into time domain data for transmission over the communication channel 25 Likewise, time domain data representing upstream data received by the modem 15, 20 over the communication channel 25 is transformed into frequency domain data and processed The transmitter functional block 1 10 includes an encoder 130, a transmit sequence generator 140. and a transmit sample buffer 150 The receiver functional block 120 includes a receive sample buffer 160 a receive sequence generator 170, and a decoder 180 A transform engine 190 is shared by both the transmitter functional block 110 and the receiver functional block 120 The outputs from the transform engine 190 are generated based on the inputs from the transmit sequence generator 140, and are stored in the transmit sample buffer 150 for subsequent digital to analog (D/A) conversion and transmission on the connection 25 The samples stored in the receive sample buffer 160, generated by an analog to digital (A/D) conversion of the signal receive over the connection 25 are passed to the transform engine 190 and then to the receive sequence generator 170 The output of the receive sequence generator 170 is passed to the decoder 180 for further processing The specific operations of the encoder 130 and the decoder 180 are not described in greater detail herein to avoid unnecessarily obscuring the present invention These functions are well known to those of ordinary skill in the art, and are independent of the particular method used to transform the transmit and receive data In the illustrated embodiment, the transform engine 190 implements a Hartley transform governed by the following equations H(k) = fκJ ~λ Υ j h n)cas( ) , and ( 1) M=0 N h(n) = H ( k )cas ( ) , where (2) k = 0 N ,2πnk ^ L2τιnk. ,2πnk. cas(——) = cos(— — ) + sm(— — ) (3) N N N The Hartley transform is its own inverse, thus allowing it to be shared by the transmitter functional block 110 and the receiver functional block 120 The Hartley transform is as computationally efficient as standard Fast Fourier Transform (FFT) and Inverse Fast Fourier Transform (IFFT) algorithms, but operates only on real-valued data Thus, in the transmitter functional block 110, the transmit sequence generator 140 converts complex-valued QAM symbols generated by the encoder 130 to produce a single real-valued sequence to be fed to the transform engine 190. Similarly, the receive sequence generator 170 in the receiver functional block 120 generates quadrature amplitude modulation (QAM) symbols (i.e., FFT output) based on the output of the transform engine 190 for the data received. The conversions performed by the transmit and receive sequence generators 140, 170 involve only additions and subtractions, making them computationally efficient (i.e., no divisions or multiplications are required). The output of the encoder 130 that is provided to the transmit sequence generator 140 in the transceiver 100 is a set of complex valued frequency domain points representing QAM symbols defined by the equation: The transmit sequence generator 140 operates in accordance with the following equation: # «[ » ]= te,M-αM). (5 where Q r [n] represents the real component of the value provided by the encoder 130 and Q,[ri\ represents the imaginary component of the value. Thus, the output of the transmit sequence generator 140, H, x [n] is a real- valued sequence that is subsequently fed to the transform engine 190. The output of the transform engine 190 for this sequence, T[«] is transferred to the transmit sample buffer 150 and ultimately communicated over the connection 25. The input to the decoder 180 in the DMT transceiver 100 is a set of complex valued frequency domain points representing QAM symbols defined by the equation: QΛk] = (Qr[k]-JQ,[ki- (6) These values define the data stream that the decoder 180 analyzes (i.e., performs frequency equalizing and slicing functions) on which to base its decisions. The sequence is generally the FFT of the time domain sequence, R[n] stored in the receive sample buffer 160. The transform engine 190 generates the FFT of the time domain sequence, /„[«]. The receive sequence generator 170 receives this transform and converts the sequence to the DFT sequence of R[n] in accordance with the following equations: where N is the length of the transform. The Vi- multipliers on equations 7 and 8 are integrated into the frequency equalizer functions of the decoder 180, thus maintaining the computational efficiency of the receive sequence generator 170 in employing only additions and subtractions. The construct of the transceiver 100 described above provides several advantages. Some of these advantages include providing a simple transform engine common to both the transmitter and receiver functional blocks 1 10, 120. This consolidation reduces the silicon area required to implement this portion of the transceiver 100 by about 30%, a significant savings. The silicon structures used to implement the Hartley transform are physically similar to those of the traditional FFT. Additionally, the cycle performance of the demodulation function performed in the receiver functional block 120 is up to 40% faster than a complex-valued FFT engine of the same length in the general case where Hermitian symmetry is not present. This enhanced cycle performance results in a significant power consumption savings in the receiver functional block 120. Although the invention has been described as it may be implemented to perform the modulation and demodulation functions of the transceiver 100. the transform engine 190 and accompanying sequence generators 140, 170 have broader application. For example, due to the efficiency and simplicity at which the transform engine 190 computes both complex and real valued FFT and IFFT transforms, it may also be used to perform other functions in the transceiver 190, such as convolutional filtering and correlation. Broadly stated, the transform engine 190 may be adapted to increase the efficiency of any complex-valued transform process. The particular embodiments disclosed above are illustrative only, as the invention may be modified and practiced in different but equivalent manners apparent to those skilled in the art having the benefit of the teachings herein. Furthermore, no limitations are intended to the details of construction or design herein shown, other than as described in the claims below. It is therefore evident that the particular embodiments disclosed above may be altered or modified and all such variations are considered within the scope and spirit of the invention. Accordingly, the protection sought herein is as set forth in the claims below.

Claims: CLAIMS 1. A transmitter (1 10), comprising: an encoder (130) adapted to generate a complex- valued symbol sequence; a sequence generator (140) adapted to receive the complex-valued symbol sequence and generate a real- valued symbol sequence based thereon; and a transform engine (190) adapted to transform the real-valued symbol sequence to generate a time domain sample sequence; and a buffer (150) adapted to store the time domain sample sequence. 2. A transceiver (100), comprising: a shared transform engine (190); a transmitter functional block (1 10), including: a transmit sequence generator (140) adapted to receive a complex-valued transmit symbol sequence and generate a real-valued transmit symbol sequence based thereon, the shared transform engine (190) being adapted to receive the real-valued transmit symbol sequence and generate a time domain transmit sample sequence based thereon; and a transmit buffer (150) adapted to store the time domain transmit sample sequence; and a receiver functional block (120), including: a receive buffer (160) adapted to store a time domain receive sample sequence, the shared transform engine (190) being adapted to receive the time domain receive sample sequence and generate a real-valued frequency domain receive symbol sequence; and a receive sequence generator (170) adapted to receive the real-valued frequency domain receive symbol sequence and generate a complex-valued receive symbol sequence based thereon. 3. The transceiver (100) of claim 2, wherein the shared transform engine (190) is adapted to perform a Hartley transform. 4. The transceiver (100) of claim 2, wherein each of the complex-valued transmit symbol includes a real component and an imaginary component, and the transmit sequence generator (140) is adapted to subtract the imaginary component from the real component to generate the real-valued transmit symbol. 5. A method for communicating data, comprising: receiving a complex-valued transmit symbol sequence; generating a real-valued transmit symbol sequence based on the complex-valued transmit symbol sequence; generating a time domain transmit sample sequence based on the complex-valued transmit symbol sequence using a transform engine; and storing the time domain transmit sample sequence for transmission on a communications channel. 6 The method of claim 5, wherein generating the time domain transmit sample sequence based on the complex-valued transmit symbol sequence using a transform engine comprises generating the time domain transmit sample sequence using a transform engine adapted to perform a Hartley transform 7 The method of claim 5, wherein each of the complex-valued transmit symbols includes a real component and an imaginary component, and generating the real-valued transmit symbol sequence includes subtracting the imaginary component from the real component to generate the real-valued transmit symbol 8 The method of claim 5, further comprising receiving a time domain receive sample sequence, generating a real-valued frequency domain receive symbol sequence using the transform engine and generating a complex-valued receive symbol sequence based on the real-valued frequency domain receive symbol sequence 9 The method of claim 8, wherein generating the real-valued frequency domain receive svmbol sequence comprises generating the real-valued frequency domain receive symbol sequence using a transform engine adapted to perform a Hartley transform

Inventors: CANELONES ORLANDO J, CANELONES, ORLANDO, J.
Applicants: LEGERITY INC, LEGERITY, INC.
Application year: 2000
Main classification: G06F17
IPC codes: H04L27