COMPLEX FILTERING/AGC RADIO RECEIVER ARCHITECTURE FOR LOW-IF OR ZERO-IF

Abstract: A low power IF strip architecture suitable for Zero-IF (ZIF) or low-IF (LIF) radio receivers for filtering and amplifying a received signal. The apparatus includes a plurality of sequentially connected complex filter/amplifier stages. Each stage includes a complex filter having one or more poles and an automatic gain controlled amplifier (AGC). Each AGC may be feedback or feedforward with fixed minimum and maximum gains. Each stage further includes a control circuit that produces a gain control signal for controlling the amplifier gain within the fixed minimum and maximum gains as a function of a projected amplitude level. The received signal passes through multiple stages of filtering and controlled amplification to attenuate the interfering signal and amplify the desired signal. This is done at a restricted level in each stage such that the circuits in the stages operate at efficient power saving levels. The individual gain control signals from each stage are summed in a received signal strength indicator to provide the overall gain of the apparatus. The overall gain when taken with the amplitude of the apparatus output signal determines the original strength of the desired received signal.

Description: Complex Filtering/AGC Radio Receiver Architecture for Low-IF or Zero-IF Field of the Invention The invention relates generally to circuitry for filtering and amplifying signals, and more particularly to a complex Filtering/ Automatic Gain Control architecture for zero-IF or low-IF radio receivers. Background of the Invention Present day RF radio receivers must be capable of detecting and demodulating RF signals in which the desired information signal is often much weaker than existing interfering signal. Recently, receivers which directly convert the RF signal to a much lower frequency have been developed. The RF signal is down-converted to a zero-IF or low-IF intermediate frequency where analog and/or digital signal processing is more efficient. Present day radio receivers typically employ real filters to filter out interfering signals, and amplifiers to increase the level of the desired signal. If real filters are used in a LIF path they have the disadvantage of not differentiating between negative frequencies and positive frequencies, hence a high performance image reject mixer is typically used to separate the positive/negative frequencies. In addition, where the frequency of the interfering signal is close to the frequency of the desired signal in a LIF architecture, a substantial number of filter poles are required to filter out the interfering signals and the overall amplifier circuit is such that considerable power is required to amplify the desired signal to an appropriate level for demodulation. In addition, DC offsets caused by both circuit imperfections and characteristics inherent in certain forms of modulation must be removed since they can be several orders of magnitude larger than the desired signal and can degrade the performance of the final demodulator circuit. Therefore, there is a need for a simpler architecture for enhancing the gain performance and removing DC offsets while minimizing power consumption. Summary of the Invention The invention is directed to apparatus for filtering and amplifying a received signal. The apparatus includes a plurality of complex filter/amplifier stages connected in sequence. Each of the stages has a complex filter for attenuating an interfering portion of the received signal relative to the desired portion, a controlled amplifier which has set minimum gain K min and maximum gain K max for amplifying the received signal, where K min may be negative, and a control circuit. The control circuit controls the amplifier gain K where K min ≤ K ≤ K^ such that the controlled amplifier seeks to generate an output signal having a projected amplitude level. The present invention is particularly advantageous in that the apparatus is capable of providing an overall output signal at a predetermined amplitude level within a restricted dynamic range from input signals having a wide variety of signal strengths and at the same time permits for the use of low power consuming subsequent circuits. This is achieved in apparatus that itself draws very low power. The apparatus operates effectively on received signals in the IF band that are low-IF or zero-IF In accordance with another aspect of this invention, the received signal is made up of complex in-phase I and quadrature phase Q signals. The complex filter may be multipolar or may be one or more single pole complex filters connected in series. The controlled amplifier has a first variable gain amplifier for amplifying the in-phase I signal and a second variable gain amplifier for amplifying the quadrature phase Q signal. The control circuit generates a gain control signal which is a function of the outputs or the inputs of the amplifiers as well as a function of a projected amplitude level. In accordance with a further aspect of this invention, the control circuit may include a first and a second rectifier for receiving the inputs of the first and second variable amplifiers respectively or the outputs of the first and second variable amplifiers respectively to provide first and second rectified signals. The rectified signals are added in a summing circuit and fed to an error amplifier where the summed signal is compared to a projected amplitude level signal for producing the gain control signal used to control the gain of the amplifiers. With regard to another aspect of this invention, the apparatus may further include a received signal strength indicator which has a gain summation circuit for receiving the gain control signal from each of the complex filter/amplifier stages to compute the overall gain of the apparatus and a detector to detect the amplitude of the apparatus overall output signal for determining the strength of a desired signal received by the apparatus. Other aspects and advantages of the invention, as well as the structure and operation of various embodiments of the invention, will become apparent to those ordinarily skilled in the art upon review of the following description of the invention in conjunction with the accompanying drawings. Brief Description of the Drawings The invention will be described with reference to the accompanying drawings, wherein: Figure 1 schematically illustrates the invention; Figure 2 illustrates an embodiment of the present invention; Figure 3 illustrates a complex single pole filter which may be used with the present invention; Figure 4a illustrates a quadrature feedback AGC circuit in accordance with the present invention having DC feedback compensation; Figure 4b illustrates a quadrature feedback AGC circuit in accordance with the present invention having DC feedforward compensation; Figure 5a illustrates a quadrature feedforward AGC circuit in accordance with the present invention having DC feedback compensation; Figure 5b illustrates a quadrature feedforward AGC circuit in accordance with the present invention having DC feedforward compensation; and Figure 6 illustrates a control circuit for the AGC's in accordance with the present invention. Detailed Description of the Invention Though the present invention is described in conjunction with figure 1 within the environment of an RF radio receiver, it may also be used in other applications where circuitry that has very low power consumption levels is required. An RF radio receiver 10 includes, at its front end, an RF IF down converter 11 for converting the input RF signal to low-IF (LIF) or zero-IF (ZIF) in-phase I; and quadrature Q, signals. The RF radio receiver further includes a digital demodulator 12 at its back end for digitizing the amplified in-phase I 0 and quadrature Q 0 signals and demodulating the digitized signals to provide at its output the data from the input RF signal. In most circumstances, the quadrature Ij and Qj signals cannot be applied directly to the digital demodulator 12. The desired signal, whether it is too small or too great for the demodulator 12 is embedded in an interfering signal. The desired signal is usually very small relative to the interfering signal, the interfering signal being as high as 60 db greater than the desired signal. In order to be able to detect and demodulate the desired signal portion of the input signal, the amplitude of the desired signal must be made greater than the interfering signal, and the amplitude of the desired signal must also be at a level that can be efficiently digitized and demodulated, this is carried out by passing the input signals through bandpass filters and amplifiers. Figure 1 schematically illustrates a novel cascaded structure 13, in accordance with the present invention, for filtering and amplifying the in-phase Ij and quadrature Qj input signals to produce in-phase I 0 and quadrature Q 0 output signals having which can be efficiently digitized and demodulated. In order to be able to use an efficient analog to digital converter (ADC), it is advantageous that the overall in-phase I 0 and quadrature Q 0 output signals be produced at a predetermined level H within a restricted dynamic range whether the desired portion of the input signal is initially far below or even above the predetermined level H. The more restricted the dynamic range, the smaller the number of bits required in an ADC to digitize the signal, this reduces the power requirements for the ADC. The cascaded structure 13 includes a series of complex filter/amplifier stages 14,, 14 2 , 14 n which each in turn independently filter and amplify the complex signal until the desired portion of the complex signal achieves a predetermined amplitude level H that falls within the desired restricted dynamic range and is relatively greater than the interfering signal. Though the stages 14,, 14 2 , 14 π are described in terms of a filter/amplifier sequence of components, it is understood that the sequence of components could equally be amplifier/filter in all embodiments of the present invention. The filter in each stage 14,, 14 2 , 14 n may be a single or multiple pole filter and the amplifiers in stages 14 , , 14 2 , 14 n are amplitude gain controlled amplifiers which each exhibit an individual gain range having a minimum gain which may be positive or negative and a maximum positive gain. The attenuation of the interfering signal by the filters relative to the desired signal may be distributed equally or unequally over the stages 14,, 14 2 , 14 π and the gain range for each stage 14 , , 14 2 , 14„ may also differ from stage to stage. In addition, AGC settings 15,, 15 2 , 15 n are applied to the amplifiers in stages 14,, 14 2 , 14 n respectively to control the gain of each amplifier such that the amplitude of the signal at the output of each respective amplifier will tend towards a projected signal level as fixed by the respective AGC setting 15,, 15 2 , 15„. It may occur that one or more amplifiers are driven to operate at its minimum or maximum gain without achieving the projected output signal level called for by AGC setting 15„ 15 2 , 15 π at the particular amplifier in that stage. In operation, the complex filter/amplifier stages 14,, 14 2 , 14 n act independently of one another and the stages act sequentially on the . input signal so as to produce a desired output signal having a predetermined signal level H falling within the restricted dynamic range required at the output. The signal level H is achieved in the last stage 14 π by controlling the amplifier within the stage 14 n by the AGC setting 15 n . The AGC setting 15,, 15 2 , 15 n are preset at specific levels and represent the projected amplitude level desired at the output of the respective amplifiers. AGC setting 15,, 15 2 , 15 n are used to control the gain of the respective amplifiers within their respective gain ranges. The number of stages 14,, 14 2 , 14 n in the cascaded structure 13 and the maximum of the gain range for each amplifier is preset in order to obtain the total gain required over the entire cascaded structure 13 to accommodate the variety of desired input signals levels with which the receiver is expected to function properly. The gain ranges or the gain range maximums may be substantially the same, however this will not usually be the case. Each amplifier gain range is preferably selected such that the amplifiers will operate efficiently minimizing power consumption. Initially, at the input to the RF radio receiver, the desired input signal is relatively much smaller than the interfering signals. Each stage 14,, 14 2 , 14 n attenuates the interference signals using a complex filter having one or more poles. The signal is then amplified by an AGC which amplifies both the desired signal as well as the interfering signal. As the signal passes through subsequent stages, the desired signal becomes larger relative to the interfering signal since both are amplified but only the interfering signal is attenuated by the filter. Thus, in the last stages, the desired signal becomes the dominant signal since the interfering signal is being attenuated to towards zero. As an example, a five stage filter/amplifier structure 13 may have gain ranges for the five stages 14„ 14 2 , 14 5 , of +5 to -5, +5 to -5, +20 to -5, +20 to -5, and +15 to -5 respectively in order to accommodate the range of signals that it is to detect. In one scenario, it might be found that a five stage structure 13 is required to detect a desired signal that is 50 db below the level H required for it to be digitized and also about 40 db below the interfering signal. In such a case, the AGC setting 15,, 15 2 will place a gain demand on the first two stages that are very low, say in the order of 2 and 6 db since the interfering signal is high, such that the filters attenuate the interfering signals significantly while the signals are not being amplified significantly by the amplifiers in these early stages. At the third stage, with desired signal and the interfering signal being relatively equal, the AGC setting 15 3 may be set at a level which demands a gain of the amplifier greater than its gain range maximum of 20 db. Thus at this stage the amplifier signal gain will be its maximum while its output is lower than that requested. The fourth stage may again have a high AGC setting 15 4 , which may demand a gain in the order of 14 db which would be below its maximum of 20 db. Going into the final stage, the AGC setting 15 5 will be set to achieve the desired amplifier output level H. Since the overall gain of the desired signal is the sum of the individual gains, it would be 42 db to this point, and the gain demand on the last amplifier will be 8 db which is below its maximum of 15 db. In a second scenario taken at the other extreme of possible input signals for the same five stage structure 13, the desired input signal may already be greater than level H required for it to be digitized say for instance about 6db, and at the same time somewhat smaller than the interfering signal. In such a case, the AGC settings 15,, 15 2 will demand large negative gains of the amplifiers in the first two stages 14,, 14 2 , to get the signal level down. However since the amplifiers have a lower limit of -5db for instance, both the desired signal and the interfering signals will be attenuated by the amplifiers to that limit while the interfering signals will also be attenuated by the filters. It will now be found that the desired signal is below the required output level H by about 4db. In the third to fifth stages 14 3 , 14 4 and 14 5 , the gain demanded by the AGC settings 15 3 , 15 4 , andl5 5 will be small since the desired signal is only 4 db below the required output level. One embodiment of the complex filtering/AGC IF architecture in accordance with the present invention is illustrated in figure 2 as part of an RF radio receiver 20. The front end of the receiver 20 includes a quadrature down converter 21 having a pair of mixers 22 and 23 to which the input RF is applied. A synthetic local oscillator 24 with the phase splitter 25 provides second input signals that are at a predetermined frequency, but 90°out of phase, to the mixers 22 and 23 in order to generate quadrature I and Q signals at a low or zero intermediated frequency (LIF or ZIF). The complex filter/amplifier apparatus 26 comprises a plurality of filter/amplifier stages 27,, 27 2 , 27 n connected in series such that the output of one stage is the input for the next stage. Each stage 27,, 27 2 , 27 n includes a complex filter 28,, 28 2 , 28 π which may have one or more poles as well as an automatic gain controlled amplifier (AGC) 29„ 29 2 , 29 n . The AGC's 29„ 29 2 , 29 π are each fed a level control voltage termed the AGC settings 30,, 30 2 , 30 n . Though each stage 27,, 27 2 , 27 n is shown to include a complex filter 28„ 28 2 , 28 n followed by an AGC 29„ 29 2 , 29 n , the order of these components may be reversed in each stage 27,, 27 2 , 27 n . The output of the last stage 27 n is fed through two analog to digital converters (ADC) 33, 34 and a quadrature detector 39 or digital demodulator which provides the data from the original input data signal. In addition, a signal representing the actual gains 31,, 31 2 , 31 n of each AGC 29,, 29 2 , 29 n is directed to a received signal strength indicator (RSSI) 32 in order to determine the actual input data signal strength. The input data signal strength is estimated by the RSSI 32 from the sum of the actual gains 31„ 31 2 , 31 n which provides the overall gain of the complex filter/amplifier apparatus 26 and the measured signal level H at the output of stage 27 n . When the gains 31 ,, 31 2 , 3 l n of the AGC's 29,, 29 2 , 29 n are controlled to provide an output signal from stage 27 n that has a relatively constant signal level H regardless of the desired signal level at the input of stage 27,, then the signal level H is known to be relatively constant and need not be measured to determine the input data signal strength. The received signal strength indicator 32 output is normally used to trigger the processing of a received signal by the radio receiver. However, its other applications could include notifying the base station that its signal requires boosting for the proper operation of the radio system. An embodiment of a complex filter 28,, 28 2 , 28 n is illustrated in figure 3. The complex filter 35 includes a channel 36 T for the in-phase input I and a channel 36 Q for the quadrature phase input Q. Included in channels 36, and 36 Q are adders 37 r and 37 Q and integrators 38, and 38 Q respectively. In addition to the in-phase signal I and quadrature signal Q being applied to the adders 36, and 36 Q respectively, a feedback with coefficient α which may be any real number is applied to each adder 36, and 36 Q respectively. As well, a feedback with negative coefficient β is applied from the output of integrator 38 Q to adder 36, while a feedback with positive coefficient β is applied from the output of integrator 38, to adder 36 Q . Coefficient β may also be any real number. The selection of α, β and ω 0 will determine the bandwidth and centre frequency of the filter 35. Also, depending on the values of α, β and ω 0 the positive and negative frequencies will experience different attenuations which is desired for an LIF device. Complex filters are particularly advantageous since α, β and ω 0 may be varied to vary the centre frequency of the filter while the width of the bandpass about the varied centre frequency can remain the same without changing the number of poles in the filter. As a result, a programmable IF receiver can be designed to switch between IF frequencies. For a ZIF device, coefficient β goes to 0 as the frequency goes to zero and the cross-coupled coefficients β thus have no effect. In complex filters, the number of poles required to attenuate a signal at a frequency of x Hz away from the centre frequency is independent of the centre frequency while in real filters, the number of poles required to attenuate a signal at a frequency of x Hz away from the centre frequency is dependent on the centre frequency and will always be greater then that required using complex filters except in the case where the centre frequency is zero in which case it is a real filter. Multipolar complex filters having two or more poles may comprise two or more filters of the type described with reference to figure 3 connected in series. Embodiments of the AGC's 29„ 29 2 , 29 π are illustrated in figures 4a, 4b, 5a and 5b. Fast quadrature feedback AGC circuits using differential signalling will be described with reference to figures 4a and 4b and fast quadrature feedforward AGC circuits using differential signalling will be described with reference to figure 5a and 5b. The feedback AGC 40 illustrated in figure 4a comprises a pair of channels 41 , and 41 Q for the in-phase signal I and the quadrature signal Q respectively. Adders 42, and 42 Q and variable gain amplifiers 43, and 43 Q are connected in series in channels 41, and 41 Q respectively. The in-phase signal I is applied to one input of the adder 42,, while the quadrature phase signal Q is applied to one input of adder 42 Q . The gain of VGA's 43, and 43 Q is controlled by a control circuit 44 which has inputs connected to the outputs of VGA's 43, and 43 Q to detect the amplitude level of these signals and which has a further input connected to a level setting signal 45 to determine the projected signal levels at the output of the VGA's 43, and 43 Q . The control circuit 44 output is connected to the VGA's 43, and 43 Q to control their gains as a function of the difference between the actual and the projected output amplitude levels. The gain may be positive or negative depending on whether the actual signal level is lower or higher respectively than the projected signal level. In addition, the amplifier gain variability is limited to a narrow range which may prevent the signal from being amplified to the projected signal level, but also prevents distortion in low power consumption amplifiers. VGA's 43, and 43 Q may be linearly or digitally programmable. Digitally programmable VGA's generally consume less power and are therefore preferred. The feedforward AGC 50 illustrated in figure 5a comprises a pair of channels 51, and 51 Q for the in-phase signal I and the quadrature signal Q respectively. Adders 52, and 52 Q and variable gain amplifiers 53, and 53 Q are connected in series in channels 51, and 51 Q respectively. The in-phase signal I is applied to one input of the adder 52,, while the quadrature phase signal Q is applied to one input of adder 52 Q . The gain of VGA's 53, and 53 Q is controlled by a control circuit 54 which has inputs connected to outputs of adders 52, and 52 Q to detect the amplitude level of the input signals to VGA's 53, and 53 Q and which has a further input connected to a level setting signal 55 to determine the projected signal level at the output of the VGA's 53, and 53 Q . The control circuit 54 output is connected to the VGA's 53, and 53 Q to control their gains as a function of the difference between the actual input and the projected output amplitude levels. The gain may be positive or negative depending on whether the actual signal level is lower or higher respectively than the projected signal level. In addition, the amplifier gain variability is limited to a narrow range which may prevent the signal from being amplified to the projected signal level, but also prevents distortion in low power consumption amplifiers. Once again, VGA's 53, and 53 Q may be linearly or digitally programmable. Digitally programmable VGA's generally consume less power and are therefore preferred. In addition, CD compensation circuits may be added to the VGA's in order to remove the dc offset. This may done either by using a feedback circuit as illustrated in figures 4a and5a or by using a feedforward circuit as illustrated in figures 4b and 5b. The feedback DC compensation circuits 46, and 46 Q in figure 4a detect the dc output of VGA's 43, and 43 Q and feed back a negative voltage to adders 42, and 42 Q in order to remove the dc offset on the input signal before the controller 44 estimates the input signal ac levels. The DC compensation circuits 56, and 56 Q in figure 5a detect the dc output of VGA's 53, and 53 Q and feed back a negative voltage to adders 52, and 52 Q in order to remove the dc offset on the input signal before the controller 54 estimates the input signal ac levels. Using the above feedforward control circuit 54, the inclusion of DC feedback will not make the AGC circuit unstable since the dc gain will always be less than unity. The feedforward DC compensation circuits 47, and 47 Q in figure 4b detect the dc output of VGA's 43, and 43 Q and feed forward a negative voltage to adders 48, and 48 Q in order to remove the dc offset on the output signal before it goes to the next stage in the cascaded structure. Similarly, the feedforward DC compensation circuits 57, and 57 Q in figure 5b detect the dc output of VGA's 53, and 53 Q and feeds forward a negative voltage to adders 58 ! and 58 Q in order to remove the dc offset on the output signal before it goes to the next stage in the cascaded structure. In most circumstances, DC compensation circuits 46, - 46 Q , 56, - 56 Q , 47, - 47 Q and 57, and 57 Q are not required since the filters 28,, 28 2 , 28 π will filter out the dc. In particular, complex filters will attenuate all signals whether unwanted ac or dc. However, since the dc offsets may differ in the I and Q signals, performance may be improved by removing the respective dc offsets by DC compensation circuits. In this manner, the dc offsets will not be amplified limiting the range of the VGA's for the wanted signals. In addition, DC compensation is particularly important for ZIF since the filters do not attenuate the dc offsets. An embodiment of a control circuit 60 which may be used as the control circuit 44, 54 in the embodiments in figures 4a, 4b, 5a, and 5b, is illustrated in figure 6. The control circuit 60 in any filtering/AGC stage detects the magnitude of the ac portion of the amplifier input I and Q signals and sets the required gain for that stage. It is important to accurately detect the magnitude of the ac signal and to quickly make the estimate of the magnitude. In this particular embodiment, the in-phase signal I in channel 61, and the quadrature signal Q in channel 61 Q are fed to two full wave rectifiers 62, and 62 Q respectively providing output signals a and b. Signals a and b are added together in an adder 63 to provide an output c having four amplitude peaks per cycle. This rectifying and summing process provides a greater signal amplitude and a faster peak rise time than would be provided by half wave rectifiers. Since many integrated circuits use differential signalling where the amplifiers are differential amplifiers, it is common to have available in these circuits the in-phase I signal and the quadrature signal Q phase together with the in-phase I signal and the quadrature phase Q signal. Half -wave rectifying each of the four signals above and summing them would provide the same result as full wave rectifying the I and Q signals. The signal c is then fed to an integrator 64 which smooths the peaks and holds the summed signal c basically acting as a low pass filter to provide the signal d. Signal d is applied to an error amplifier 65 where it is compared to an AGC projected level signal e to provide the required gain estimate output K which is proportional to the difference between e and d, when e is greater than d. When d is greater than e, then K is negative. In addition, the error amplifier 65 will provide an output signal K which is limited to the predetermined gain range between K max and K min of the AGC in the particular stage that it is operating. Thus K min ≤ K < K max where K min may be negative. Referring to figure 2, the specific signal K in each particular stage 27„ 27 2 , 27 n is used to the control the I and Q VGA's in that particular stage as well as to provide the gain signals 31 ,, 31 2 , 31 n to the RSSI 32. If the VGA's are linearly controlled and analog in nature, then the error amplifier 65 may be constructed using an analog circuit such as an op-amp whereby both the inputs and outputs are analog. However, if the VGA's are digitally controlled, then the error amplifier 65 may be constructed using digital logic, with inputs and outputs being digital in nature. The overall advantage of the present invention is that it provides a stable filtering/amplifier structure which minimizes power consumption. Since it is capable of providing desired output signals having an amplitude level within a restricted dynamic range, further power savings may be achieved in the analog to digital converters and demodulators that follow. While the invention has been described according to what is presently considered to be the most practical and preferred embodiments, it must be understood that the invention is not limited to the disclosed embodiments. Those ordinarily skilled in the art will understand that various modifications and equivalent structures and functions may be made without departing from the spirit and scope of the invention as defined in the claims. Therefore, the invention as defined in the claims must be accorded the broadest possible interpretation so as to encompass all such modifications and equivalent structures and functions.

Claims: What is claimed is: 1. Apparatus for filtering and amplifying a received signal comprising: a plurality of sequentially connected complex filter/amplifier stages, each stage having: - complex filter means for attenuating an interfering portion relative to a desired portion of the received signal; - controlled amplifier means having set minimum gain K miπ and maximum gain K max for amplifying the received signal; and - control means for controlling the amplifier gain K where K min < K ≤ K,,^ such that the controlled amplifier seeks to generate an output signal having a projected amplitude level. 2. Apparatus as claimed in claim 1 wherein the received signal is in the IF band. 3. Apparatus as claimed in claim 2 wherein the received signal is at a low intermediate frequency (LIF). 4. Apparatus as claimed in claim 2 wherein the received signal is at a substantially zero intermediate frequency (ZIF). 5. Apparatus as claimed in claim 1 wherein the complex bandpass filter means filters the received signal and the amplifier means is connected to the filter means to amplify the filtered received signal. 6. Apparatus as claimed in claim 1 wherein the received signal comprises complex in-phase I and quadrature phase Q signals. 7. Apparatus as claimed in claim 6 wherein each of the complex filter means includes up to two poles. 8. Apparatus as claimed in claim 6 wherein the complex filter means comprises one or more single pole complex filters connected in series. 9. Apparatus as claimed in claim 6 wherein the controlled amplifier means comprises: a first variable gain amplifier for amplifying the in-phase I signal; and - a second variable gain amplifier for amplifying the quadrature phase Q signal, wherein the control means generates a gain control signal for controlling the gain of the first and second amplifiers. 10. Apparatus as claimed in claim 9 wherein the control means determines the control signal as a function of the I and Q inputs to the amplifiers. 11. Apparatus as claimed in claim 9 wherein the control means determines the control signal as a function of the I and Q outputs of the amplifiers. 12. Apparatus as claimed in claim 9 wherein the control means determines the control signal as a function of the projected amplitude level. 13. Apparatus as claimed in claim 9 wherein the control means comprises: - a first rectifier for receiving the output of the first variable amplifier to provide a first rectified signal; - a second rectifier for receiving the output of the second variable amplifier to provide a second rectified signal; - summing means for adding the first and the second rectified signals; and - error amplifier means having a first input coupled to the summing means and a second input coupled to a projected amplitude level signal for producing the gain control signal. 14. Apparatus as claimed in claim 13 wherein the first and second rectifiers are full wave rectifiers. 15. Apparatus as claimed in claim 9 wherein the control means comprises: - a first rectifier for receiving the input of the first variable amplifier to provide a first rectified signal; - a second rectifier for receiving the input of the second variable amplifier to provide a second rectified signal; summing means to add the first and the second rectified signals; and - error amplifier means having a first input coupled to the summing means and a second input coupled to a projected amplitude level signal for producing the gain control signal. 16. Apparatus as claimed in claim 15 wherein the first and second rectifiers are full wave rectifiers. 17. Apparatus as claimed in claim 9 further comprising: received signal strength indicator having: - gain summation means for receiving the gain control signal from each of the complex filter/amplifier stages for computing the overall gain of the apparatus; - means for detecting the amplitude of the apparatus output signal; and - means coupled to the gain summation means and the detector means for indicating the strength of a desired signal received by the apparatus. 18. Apparatus as claimed in claim 1 wherein each complex filter/amplifier stage further includes a dc compensation circuit for attenuating the dc offset of the received signal. 19. Apparatus as claimed in claim 18 wherein the dc compensation circuit is a feedback circuit. 20. Apparatus as claimed in claim 18 wherein the dc compensation circuit is a feedforward circuit. 21. Apparatus as claimed in claim 1 wherein K min is negative.

Inventors: BALTEANU FLORINEL, BIRKETT NEIL A, CHERRY JAMES A, SNELGROVE MARTIN, BALTEANU, FLORINEL, BIRKETT, NEIL, A., CHERRY, JAMES, A., SNELGROVE, MARTIN
Applicants: PHILSAR SEMICONDUCTOR INC, PHILSAR SEMICONDUCTOR INC.
Application year: 2000
Main classification: H04B1
IPC codes: H03G3, H04B1