CIRCUIT ARRANGEMENT PROVIDING IMPEDANCE TRANSLATION FILTERING

Abstract: A circuit arrangement for providing impedance translation filtering comprises a first path and a second path. In a base band variant the first path is a feed forward path which comprises first and second series connected transconductance gain stages (10, 12), and the second path is a feedback path which comprises third and fourth transconductance gain stages (18, 20), each having an inverting output. An output of the first gain stage is coupled to an input of the fourth gain stage. In operation, the impedance (zin) presented at an input of the circuit arrangement is determined by the impedance (z2) presented at its output. In a frequency shifting variant the first and fourth gain stages are replaced by transconductance mixers. The circuit arrangement can be applied to high frequency stages (i.f. or r.f.) of receivers and transmitters.

Description: DESCRIPTION CIRCUIT ARRANGEMENT PROVIDING IMPEDANCE TRANSLATION FILTERING Technical Field The present invention relates to a circuit arrangement providing impedance translation filtering. An application of the present invention is effecting high frequency (i.f. or r.f.) filtering in receivers and transmitters. Background Art Impedance control circuits are known, for example from UK Patent Specification 2,100,949A, for use in subscriber line interface circuits in telephone systems. The cited specification discloses an idealised transmission system having first and second circuits along which signals pass. A current controlled feedback loop in the first circuit is used to control the impedance of that circuit by a single element so that the circuit with feedback initiates an idealised circuit having an impedance representing the first circuit. Thus the current - controlled feedback loop sets the impedance of the circuit. This cited specification does not disclose using impedance translation for effecting high frequency filtering. Disclosure of Invention According to a first aspect of the present invention there is provided a circuit arrangement comprising a first path including a first frequency translation stage, a second path including a second frequency translation stage, an input to the first path being connected to an output of the second path, an output of the first path being connected to an input of the second path, and means for connecting a source of local oscillator signals to the first and second frequency translation stages, wherein the frequency of an input signal is translated by the local oscillator signals to a lower frequency and wherein the impedance as viewed from a higher frequency end of the circuit arrangement is determined by the impedance presented at a lower frequency end of the circuit arrangement. According to a second aspect of the present invention there is provided a circuit arrangement comprising a first path and a second path, the first path comprising first and second series connected transconductance gain stages, the second path comprising third and fourth transconductance gain stages, each having an inverting output, an input of the third gain stage being coupled to an output of the second gain stage, the output of the fourth gain stage being coupled to an input of the first gain stage, and an output of the first gain stage being coupled to an input of the fourth gain stage, whereby an impedance presented at an output of the second gain stage determines the input impedance presented at the input of the first gain stage. According to a third aspect of the present invention there is provided a quadrature receiver comprising input means for connection to a signal source, input signal dividing means coupled to the input means, the dividing means having first and second outputs, first and second circuit arrangements coupled to the first and second outputs, respectively, the first circuit arrangement comprising a first path and a second path, the first path comprising a first transconductance mixer having an output and a first gain stage coupled to the output of the first mixer, and the second path comprising a second transconductance gain stage having an inverting output and second transconductance mixer coupled to the output of the second gain stage, the second mixer having an inverting output coupled to an input of the first mixer, an output of the first gain stage being coupled to an input of the second gain stage, the output of the second mixer being coupled to an input of the first mixer, and the output of the first mixer being coupled to an input of the second mixer, and the second circuit arrangement comprising a first path and a second path, the first path comprising a third transconductance mixer having an output and a third gain stage coupled to the output of the third mixer, the second path comprising a fourth transconductance gain stage having an inverting output and a fourth transconductance mixer coupled to the output of the fourth gain stage, the fourth mixer having an inverting output coupled to an input of the third mixer, an output of the third gain stage being coupled to an input of the fourth gain stage, the output of the fourth mixer being coupled to an input of the third mixer, and the output of the third mixer being coupled to an input of the fourth mixer, and a local oscillator signal source having first and second quadrature related outputs, the first output being coupled to the first and second mixers and the second output being coupled to the third and fourth mixers. According to a fourth aspect of the present invention there is provided a transmitter comprising first and second means for connection to respective first and second signal sources, first and second circuit arrangements coupled to the respective means for connection to the first and second signal sources, the first circuit arrangement comprising a first path and a second path, the first path comprising a first transconductance gain stage having an inverting output and a first transconductance mixer coupled to the output of the first gain stage, the first mixer having an inverting output, the second path comprising a second transconductance mixer having an output and a second gain stage coupled to the output of the second mixer, the output of the second mixer being coupled to an input of the first mixer, an output of the second gain stage being coupled to an input of the first gain stage, the output of the first mixer being coupled to an input of the second mixer and to a signal combining means, and the second circuit arrangement comprising a first path and a second path, the first path comprising a third transconductance gain stage having an inverting output and a third transconductance mixer coupled to the output of the third gain stage, the third mixer having an inverting output, the second path comprising a fourth transconductance mixer having an output and fourth transconductance gain stage coupled to the output of the fourth mixer, the output of the fourth mixer being coupled to an input of the third mixer, an output of the fourth gain stage being coupled to an input of the third gain stage, and the output of the third mixer being coupled to an input of the fourth mixer and to the signal combining means. Combining the ability to be able to use the impedance presented at the output of a circuit arrangement to determine its input impedance with pairs of quadrature mixers performing down- and up-mixing allows a well controlled impedance variation at base band to also produce an impedance variation and thereby a filtering effect at high (i.f. or r.f.) frequencies. The effective r.f. filtering may then be used with advantage in transceiver architectures, for example to avoid external, off-chip components, or to relax performance requirements. Brief Description of Drawings The present invention will now be described, by way of example, with reference to the accompanying drawings, wherein Figure 1 is a block schematic diagram of a baseband model of the circuit arrangement in accordance with the present invention, Figure 2 is a block schematic diagram of an ideal baseband quadrature model of the circuit arrangement made in accordance with the present invention, Figure 3 is a block schematic diagram of a quadrature frequency - shifting model, Figure 4 is a version of Figure 3 showing impedance translation, Figure 5 is a block schematic diagram of a quadrature receiver, Figure 6 is a block schematic diagram of a quadrature transmitter, and Figure 7 is a block schematic of a reciprocal impedance translation stage. In the drawings the same reference numerals have been used to indicate corresponding features. Modes for Carrying Out the Invention Referring to Figure 1 , the basic circuit block is shown within the broken lines and comprises a first, feed forward path comprising first and second series connected transconductance amplifiers 10, 12 having gains of G? and G 2 , respectively. A second, feedback path is connected between the output 14 of the basic circuit block and the input 16 to the basic circuit block. The second path comprises a third and fourth series connected transconductance amplifiers 18, 20 having negative gains G 2 . G 1 and inverting outputs. The output of the first amplifier 10 and the input of the fourth amplifier 20 are interconnected by a conductive link 21. The first to fourth amplifiers 10, 12, 18 and 20 may be differential amplifiers and the inverted outputs of the third and fourth amplifiers 18, 20 may be obtained by swapping over their outputs. The input impedance to the second amplifier 12 is represented by a resistor z ? but is more likely to be implemented as an RC filter. The impedance value of z* is preferably high. The transconductance amplifiers give an output current proportional to the input voltage. As will be demonstrated by the following mathematical analysis, the impedance z s seen at the input 16 of the circuit arrangement is determined by the impedance z 2 presented at the output 14 of the circuit block. For convenience of reference, a source voltage V s is shown connected by the input impedance z s to an input 16. A voltage V 0 at the input of the amplifier 10 is amplified and represented by a current l 0 ' on its output. A voltage \ ι at the input of the amplifier 12 is amplified and represented by a current / 2 ". A current / 2 flows into the impedance z 2 and produces a voltage V 2 . The voltage V 2 on the input of the amplifier 18 is transcond ucted to a current / 2 \ Lastly a voltage Vi on the input of the amplifier 20 is transcond ucted to a current /o". Starting with the conditions at the centre V = (I Q + I 2 )z (1) Now and I 2 = G 2 V 2 so I Q + I 2 = G X V Q - G 2 V 2 giving This gives the output current as: h = G 2 V λ Substituting (2) for \/ \ gives: I 2 = (G l G 2 V 0 + G 2 G 2 V 2 )z ] (3) and the current drawn at the input as: Substituting (2) for V- \ gives: These two equations define the currents at output and input as a function of the voltages at the output and input. Now the current at the output is determined by the load impedance present V 2 = 7 2 z 2 (5) so using this relationship then gives for the output current from eqn. (3) gives and for the input current from eqn. (4) I 0 = -GJGJ Q Z, - G I 2 Z Z 2 using (6) then Given the load impedance, this then has defined the currents flowing in the output and input circuits. The minus sign in expression (7) is explained by the definitions of the current flow, and the expectation that G is negative. Having derived the current at the input the input impedance, z m presented by the block can be calculated, which is simply 2ιn = lj2 = G 2 G 2 z z 2 - X (8) IQ G X G X Z X To see how the circuit behaves when the feedback loop gain is high, if | G 2 G 2 'zrZ 2 | .» 7 then G 2 G z z G \ G \ Z \ . _. G 2 G 1 , z ιn -z? (9) GχG\ The important property of the circuitry block is thus demonstrated, that the impedance at the input is related to (and usually proportional to) the impedance present at its output. In the meantime however, to complete the description, the signal voltage at the output is simply obtained by the output current flowing in the load impedance Eqn. (6) in Eqn. (5) The expression makes sense, as it is the forward gain multiplied by the closed loop response (1 - loop gain) "1 for the feedback loop formed by the output and internal circuit. The loop formed around the input circuit naturally does not have an influence, for a given voltage input V 0 . Again, to see how the circuit behaves when the feedback loop gain is high, if | -G 'z/-z..? | .» 1 then the voltage gain (10) simplifies to - G. V n (11) Intuitively this is the forward gain followed by the feedback G ∑ 'z, with the internal impedance zi dropping out of the expression, and the minus signal explainable by G 2 ' being negative. The current gain, the ratio of the currents flowing in the output and the input is also of interest Eqns. (6) and (7) => IQ which is as it should be, since the voltage V ? is common input to both transconductor amplifiers 12, 20, so the ratio of the currents is that of the gains. The minus sign reflects the fact that the currents are defined in Figure 1 flowing in opposite directions, so G is negative. The result is also consistent with the impedance relationship (9) and the voltage scaling between input and output (11). Now the application of the circuit block together with source circuit, with the voltage source V s and source impedance z s will be examined. The voltage at the input of the block is then determined by the voltage dropped due to the current flow in the source impedance: V 0 = V, (13) substituting in the current flow result (7) we have This makes sense as there are two, nested feedback loops, the first one with loop gain GιGι'zιZ s having its loop gain modified by the second loop with Further rearrangement of (14) then gives the more manageable expression It is important to note the basic effect, that the voltage developed at the input to the circuit block is being determined, as a result of the feedback, by the impedance z 2 presented at its output. This means that if a filter which presents a frequency - dependent input impedance is present at the output, then its effect will also be felt at the input of the circuit block. If there is strong feedback, | G 2 G 2 'z ? z 2 | -» 7 then Note again that the internal impedance Zi has dropped out of the expression; it determines the internal impedance level and the feedback loop gains, only indirectly influence the transfer function between input and output. If | GιGι'z s | --» | G 2 G 2 'z 2 \ as will be the case for example if z 2 is small, for an out-of-band signal, then O2< J 2 Z 2 V Q « V S (17) G \ G \ z s so that if Gi, Gϊ, G 2 , G 2 ', z s are substantially independent of frequency, then V 0 ∞ z 2 - V s (18) and the signal level at the input of the block is simply proportional to the load impedance at the baseband output of the block, z 2 . Turning now to the signal level at the output, combining equations (10) and (14) gives So the forward gain voltage gain of each stage, being the transconductance multiplied by the load impedances, is modified by the feedback loop gains. If there is strong feedback, | G 1 Gι 'zιZ2 | -» / or \ G2G2'zιZ2 \ .» 1 then V, -v. G x G z x z 2 O2 G 2 Z 1 Z 2 + G \ G \ z \ z s -v. G X G : (20) G j G,z- + G 2 G 2 z 2 which is consistent with the impedance scaling result, as can be seen by reformulating as G2G2 S ' ' G 2 z s + G 2 G^ z G.G and then using (9) to re-express in terms of the input impedance z m presented by the block, giving V * -V. (21) G z s + z ιn This is a satisfying result; a potential divider is being formed by z m and z s , with the voltage then being amplified to the output with gain -Gι/G 2 ' as per equation (11). Remember that G 2 ' is negative. If as can be the case for an out-of-band signal the impedance then (20) can be further simplified to -V. (22) and if Gi, G , G 2 , G 2 , z s are all independent of frequency then V 2 oc z 2 -V s The signs all appear to be correct if as expected the signs of Gi' and G ' are negative. This also ensures stability of the feedback loops, 1 X - β where β should be negative. The performance can be improved by making l 0 ' = 12' more closely, that is by increasing z 1 directly or indirectly via buffering circuitry between the current summing junction and the drive to the transconductor amplifiers. Referring to Figure 2 which shows an ideal quadrature model. Comparing Figures 1 and 2 it is evident that the in-phase I and quadrature phase Q circuits are of identical layout with the exceptions that the reference numbers of the transconductance amplifiers has "I" and "Q" added and the subscripts "i" and "q" have been used in the referencing of the various voltages and currents. In the interests of brevity a detailed description will not be given of Figure 2 as the description of the respective I and Q circuits has been amply covered with reference to Figure 1. Figure 3 is a variant of Figure 2 in which the transconductance amplifiers 101, 201, 10Q and 20Q have been replaced by transconductance mixers 22I, 24I, 22Q and 24Q, respectively. The mixers 22I and 22Q have double the gain of the mixers 241 and 24Q. Also the mixers 241 and 24Q have inverting outputs. A signal source 26 is coupled by way of a signal splitter 28 to the inputs 161 and 16Q of the respective circuit blocks. Quadrature related local oscillator signals are supplied to the mixers 22I, 24I and 22Q, 24Q, respectively. In order to explain the operation of Figure 3 in general terms it will be assumed for simplicity that the gains paths are identical and that there is a perfect 90° phase shift between them. There is a frequency down conversion in the mixer 221 or 22Q and a frequency up conversion in the mixer 241 or 24Q. Accordingly it is necessary to consider the effects of both frequency translations in the following mathematical analysis. In the case of frequency translation down by (-f osc ): Input voltage to mixer 221, V Q = a 0 sm{2πft - 0 ) (23) 7 0j = ^{sin(2π{f - f osc )t - φ 0 )+ n{2π{f + f osc )t - φ Q )} The double frequency term is removed by filtering, leaving and similarly 2G x a 0 7 n = {cos(2π{f-f osc )t-φ 0 )-c s{2π(f + f osc )t-φ 0 )} which with the double frequency removed gives 4 = G \ a o cos{2π{f - f osc )t- o) (25) that is for each I and Q path a gain of G ? and a frequency translation down by (-f osc ) In the case of frequency translation up by (+f osc ): Input voltage to mixer 241, Input voltage to mixer 24Q, V, = a COS(2Λ-(/ - f osc )t- ι) (27) then 7 0 "= V i G c s{2πf osc t)+ V Xq G x s {2πf osc t) so by standard trigonometry MISSING AT THE TIME OF PUBLICATION MISSING AT THE TIME OF PUBLICATION MISSING AT THE TIME OF PUBLICATION The above approximate expression for the amplitude a 2 can meaningfully be further rearranged to give a gain of The gain between r.f. input and baseband output is then the ratio of the gains acting on the internal common point, G 1 /G 2 , modified by the impedance across which the signal is developed, the baseband load impedance, z∑ft s - fosc), fed by the r.f. source impedance scaled by the gain ratios and translated to be effective at the baseband output, For the sake of completeness, Figure 4 shows an impedance translation representation of Figure 3. The references z rf and z bb respectively mean the radio frequency impedance and the base band impedance. The remainder of the references have the same meaning as used in Figure 3. Figure 5 illustrates a radio receiver which is based on the frequency shifting model shown in Figures 3 and 4. The signal source in the case of the receiver is an antenna 30 which is coupled to the signal splitter 28. However the signal source could be an i.f. signal derived from the output of a r.f. front end. The outputs from the respective I and Q circuit blocks are applied to low pass filters 32, 34 which select the wanted products from the frequency translation. A local oscillator 36 is shown connected to a phase shifter 38 which quadrature related local oscillator signals cos(ω osc t) and sin(ω osc t) to the mixers 221, 241 and 22Q, 24Q, respectively. The frequency translation and filtering by the circuit blocks has already been described above and in the interests of brevity will not be repeated again. Figure 6 illustrates a transmitter which is based on the frequency shifting model shown in Figures 3 and 4. In operation, quadrature related modulating signals Vj, V q represented by the signal sources 40, 42 are applied to the circuit blocks I and Q by way of low pass filters 32, 34. The signals are frequency up-converted in the mixers 241, 24Q and supplied to a signal combiner 44, which is a reciprocal of a signal splitter, the output of which is coupled to the antenna 30. The signals from the mixers 241, 24Q are frequency down converted in the mixers 221, 22Q, respectively. The oscillator 36 and the phase splitter 38 provide the oscillator signals for up and down conversion, as appropriate. The mathematical analysis provided above for the frequency shifting model is valid for the transmitter. Figure 7 is a simplification of the impedance translation arrangement shown in Figure 4. The simplification comprises omitting the transconductance amplifiers 121, 12Q, 181, 18Q, the conductive links 21 and the impedances z-i. In this simplified arrangement the impedance seen looking into one side of the circuit block is (proportional to) the reciprocal of the impedance z 2 present at the output of the other side. In a practical application of the circuit block the impedance z 2 presents a high impedance for out-of-band baseband signals. When the impedance is reciprocally translated to r.f., the impedance looking into the circuit block is then low for such signals, reducing their amplitude thereby facilitating the filtering of these signals. In the present specification and claims the word "a" or "an" preceding an element does not exclude the presence of a plurality of such elements. Further, the word "comprising" does not exclude the presence of other elements or steps than those listed. From reading the present disclosure, other modifications will be apparent to persons skilled in the art. Such modifications may involve other features which are already known in the design, manufacture and use of transmitters and receivers and components therefor and which may be used instead of or in addition to features already described herein. Industrial Applicability High frequency filters for transmitters and receivers.

Claims: CLAIMS 1. A circuit arrangement comprising a first path including a first frequency translation stage, a second path including a second frequency translation stage, an input to the first path being connected to an output of the second path, an output of the first path being connected to an input of the second path, and means for connecting a source of local oscillator signals to the first and second frequency translation stages, wherein the frequency of an input signal is translated by the local oscillator signals to a lower frequency and wherein the impedance as viewed from a higher frequency end of the circuit arrangement is determined by the impedance presented at a lower frequency end of the circuit arrangement. 2. A circuit arrangement as claimed in claim 1 , characterised in that the determined impedance relationship is a reciprocal one. 3. A circuit arrangement comprising a first path and a second path, the first path comprising first and second series connected transconductance gain stages, the second path comprising third and fourth transconductance gain stages, each having an inverting output, an input of the third gain stage being coupled to an output of the second gain stage, the output of the fourth gain stage being coupled to an input of the first gain stage, and an output of the first gain stage being coupled to an input of the fourth gain stage, whereby an impedance presented at an output of the second gain stage determines the input impedance presented at the input of the first gain stage. 4. A circuit arrangement as claimed in claim 3, characterised in that an impedance device is coupled to an input of the second gain stage. 5. A circuit arrangement as claimed in claim 3 or 4, characterised in that the third and fourth gain stages have negative gains. 6. A circuit arrangement as claimed in claim 3, characterised in that the first gain stage comprises a first transconductance mixer and the fourth gain stage comprises a second transconductance mixer having an inverting output, and in that a source of local oscillator signals is coupled inputs of the first and second mixers. 7. A quadrature receiver comprising input means for connection to a signal source, input signal dividing means coupled to the input means, the dividing means having first and second outputs, first and second circuit arrangements coupled to the first and second outputs, respectively, the first circuit arrangement comprising a first path and a second path, the first path comprising a first transconductance mixer having an output and a first gain stage coupled to the output of the first mixer, and the second path comprising a second transconductance gain stage having an inverting output and a second transconductance mixer coupled to the output of the second gain stage, the second mixer having an inverting output coupled to an input of the first mixer, an output of the first gain stage being coupled to an input of the second gain stage, the output of the second mixer being coupled to an input of the first mixer, and the output of the first mixer being coupled to an input of the second mixer, and the second circuit arrangement comprising a first path and a second path, the first path comprising a third transconductance mixer having an output and a third gain stage coupled to the output of the third mixer, the second path comprising a fourth transconductance gain stage having an inverting output and a fourth transconductance mixer coupled to the output of the fourth gain stage, the fourth mixer having an inverting output coupled to an input of the third mixer, an output of the third gain stage being coupled to an input of the fourth gain stage, the output of the fourth mixer being coupled to an input of the third mixer, and the output of the third mixer being coupled to an input of the fourth mixer, and a local oscillator signal source having first and second quadrature related outputs, the first output being coupled to the first and second mixers and the second output being coupled to the third and fourth mixers. 8. A receiver as claimed in claim 7, characterised in that a first impedance device is coupled to an input of the first gain stage and in that a second impedance device is coupled to the input of the third gain stage. 9. A transmitter comprising first and second means for connection to respective first and second signal sources, first and second circuit arrangements coupled to the respective means for connection to the first and second signal sources, the first circuit arrangement comprising a first path and a second path, the first path comprising a first transconductance gain stage having an inverting output and a first transconductance mixer coupled to the output of the first gain stage, the first mixer having an inverting output, the second path comprising a second transconductance mixer having an output and a second gain stage coupled to the output of the second mixer, the output of the second mixer being coupled to an input of the first mixer, an output of the second gain stage being coupled to an input of the first gain stage, the output of the first mixer being coupled to an input of the second mixer and to a signal combining means, and the second circuit arrangement comprising a first path and a second path, the first path comprising a third transconductance gain stage having an inverting output and a third transconductance mixer coupled to the output of the third gain stage, the third mixer having an inverting output, the second path comprising a fourth transconductance mixer having an output and fourth transconductance gain stage coupled to the output of the fourth mixer, the output of the fourth mixer being coupled to an input of the third mixer, an output of the fourth gain stage being coupled to an input of the third gain stage, and the output of the third mixer being coupled to an input of the fourth mixer and to the signal combining means. 10. An integrated circuit comprising the circuit arrangement as claimed in any one of Claims 1 to 6.

Inventors: MARSHALL CHRISTOPHER B, MINNIS BRIAN J, MARSHALL, CHRISTOPHER, B., MINNIS, BRIAN, J.
Applicants: KONINKL PHILIPS ELECTRONICS NV, KONINKLIJKE PHILIPS ELECTRONICS N.V.
Application year: 2000
Main classification: H03D7
IPC codes: H03D7, H03H11, H04B1