RADIO FM RECEIVER

Abstract: A radio FM receiver is provided with a voltage-controlled oscillator which can be connected via a frequency 2-divider to a quadrature combination circuit for transforming down the frequencies of received radio signals and for supplying quadrature output signals. The receiver is further provided with detection and sound reproduction means connected to this combination circuit. A frequency 3-divider is also present, by means of which the oscillator can be connected to the combination circuit, as well as switching means for connecting the mixer element to the oscillator either through the 2-divider or through the 3-divider.

Description: Radio FM receiver The invention relates to a radio FM receiver provided with a voltage- controlled oscillator which can be connected via a frequency 2-divider to a quadrature combination circuit for transforming down the frequency of received radio signals and for supplying quadrature output signals, as well as with detection and sound reproduction means connected to said combination circuit. A synthesizer is used in electronically tuned radios for tuning a voltage- controlled oscillator (VCO) to a desired reception channel. In practice, the VCO signal is directly supplied to a buffer and subsequently to a combination circuit. In a receiver architecture with integrated means for the suppression of image frequencies, however, the VCO is often tuned to a frequency higher than the frequency necessary for tuning to the desired channel. In such a situation, the oscillator is followed by a frequency divider, in particular a frequency 2-divider, for serving a quadrature combination circuit which renders possible a suppression of image frequencies. The output signals thereof may then be supplied to two buffers and subsequently on a quadrature basis to combination circuits connected thereto and operating at the same frequency. Such a radio FM receiver is known, for example, from US-A-5,761,615. A car radio IC with the type designation TEA 6840 was developed in recent years. An object in the further development of this IC is to enhance its functions by providing a possibility of replacing blocks or adding functions in a manner such that it has a minimum influence on the basic construction of the IC. The reception of the so-called Japanese band is one of the respects in which the TEA 6840 IC, which is attuned to the European/American band, is in need of improvement. A change in the tuning part is required for enhancing its functions. As was noted above, such a change must not result in a change in the basic construction of the IC; the tuning range of the VCO frequency must remain unchanged. The desired reception channels in the FM mode usual in Europe and America lie between 87.3 MHz and 108.3 MHz. In Japan, however, the desired reception channels lie between 76 MHz and 90 MHz. Table I below lists the frequency bands of the reception channels, the oscillator frequency ranges, the combination frequency, the obtained center frequency, and the tuning voltage range of the oscillator for the situation in Europe/America (EU/US), a situation in Japan with the use of a 2-divider (2-JP), and the traditional situation in Japan (1-JP). Table I The frequency 2-divider supplies a signal with a combination frequency feu in a range from 98 MHz to 119 MHz in the case of an oscillator frequency f V co lying in the range of 196 MHz to 238 MHz. The center frequency obtained in the mixer element during tuning for the European/American band then lies at 10.7 MHz. The tuning voltage for the oscillator may vary from approximately 2 to 5.5 V in that case. For the Japanese band (from 76 to 90 MHz; see 2-JP in Table I), the same frequency 2-divider could be used for obtaining the center frequency of 10.7 MHz with an oscillator frequency in the range from 173.4 to 201.4 MHz. The tuning voltage for the oscillator may then vary from approximately 1 to 2.5 V. This situation is undesirable, however, on account of tuning problems which occur in practice. In the situations mentioned above, the frequency to which the unit is tuned lies below the combination frequency. In the traditional situation in Japan (1-JP in Table I), however, the combination frequency lies below the frequency to which the unit is tuned. Image frequency suppression problems then arise in the manufacture of a universal receiver which is suitable both for the European/ American band and for the Japanese band. It is accordingly an object of the invention to provide a radio FM receiver which is suitable for radio reception in Europe and America as well as in Japan and in which the above problems are avoided. According to the invention, the radio FM receiver as described in the opening paragraph is for this purpose characterized in that in addition a frequency 3-divider is present by which the oscillator can be connected to the combination circuit, as well as switching means for connecting the mixer element to the oscillator either by the 2-divider or by the 3- divider. Given an oscillator frequency fvco lying, for example, in the range from 196 MHz to 238 MHz, the 2-divider will supply a signal with a combination frequency feu in the range from 98 MHz to 119 MHz, and the 3-divider will supply a signal with a combination frequency fjp in the range from 65.3 MHz to 79.3 MHz. The center frequency obtained in the mixer element during tuning will then lie at 10.7 MHz both for the European/ American band and for the Japanese band. The measures according to the invention render it possible to avoid the problems arising from the difference in frequency bands for Europe/ America and Japan and the accompanying image frequency suppression problems, as well as the differences in VCO tuning voltages; see Table II Table II If a frequency 2-divider only is used, i.e. if the European/ American and Japanese frequency bands need not be combined, the quadrature signals may easily be obtained with a duty cycle of 50% through switching on the flanks of the VCO signal. A frequency 3-divider with a duty cycle of 50%, however, cannot be obtained in this manner. If the flanks of one of the quadrature signals coincide with the flanks of the VCO signal, the flanks of the other quadrature signal will coincide with the center of a pulse in the VCO signal; the latter quadrature signal cannot be obtained then through switching on the flanks of the VCO signal. It is obviously also possible to generate the second quadrature signal in that the first one is subjected to a phase shift of 90°. This, however, will lead to errors of the order of ± 3° for the frequency band under discussion here, which is unacceptably high. To solve this problem, the radio FM receiver is in addition characterized in that the frequency 3-divider is provided with a divider circuit which supplies n cyclical output signals V n (t) for every three VCO signal cycles, for which it is true that V n (t) = V ! (t-(n-l)Δt) with n = 1, ..., 6, and Δt = the duration of half a VCO cycle, and is provided with two summation networks in each of which the cyclical output signals are combined with predetermined weighting factors designed for obtaining a quadrature component, whereupon the combination signal thus obtained is conducted through a low-pass filter. A frequency 3-divider which is highly accurate in generating quadrature signals becomes possible in this manner, which implies that it also makes sense to include it together with a 2-divider in the radio FM receiver so as to make the latter suitable for reception both in the European/ American band and in the Japanese band. In a preferred embodiment, the weighting factors for obtaining a first quadrature component have a mutual ratio of (-2, +2, +4, +2, -2, -4), and those for obtaining the other quadrature component a mutual ratio of (-3, -3, 0, +3, +3, 0). Cyclical interchange is to be included therein. The invention relates not only to a radio FM receiver, but also to a frequency divider which can be used in a radio FM receiver as claimed in any one of the preceding claims. According to the invention, said frequency divider is provided with a divider circuit which supplies n cyclical output signals V n (t) for every l/2n oscillator signal cycles, for which it is true that V„(t) = V](t-(n-l)Δt), with n being an integer number and Δt the duration of half an oscillator cycle, and is provided with at least one summation network in which the cyclical output signals are combined with predetermined weighting factors, whereupon the combination signal thus obtained is conducted through a low-pass filter. A comparatively simple 3-divider for use in a radio FM receiver as described above is obtained for n = 6 and with two summation networks. Alternative values of n are also possible, n may be equal to 4 in the case of a 2-divider. It is also possible to form signals with a certain frequency from any number of oscillator cycles through adaptation of the weighting factors; a direct relation between the number of oscillator cycles and the frequencies to be formed is not necessary in that case. The invention will now be explained in more detail with reference to the accompanying drawing, in which: Fig. 1 is a block diagram of a radio FM receiver according to the invention; Fig. 2 shows a frequency 3-divider according to the invention which is used in the radio FM receiver of Fig. 1 ; Figs. 3A, 3B, 3C, and 3D are a number of diagrams with reference to which the operation of the 3-divider of Fig. 2 will be explained; Fig. 4 shows a more detailed embodiment of the divider circuit and the two summation networks in the frequency 3-divider; Fig. 5 shows a number of diagrams serving to elucidate the operation of the embodiment shown in Fig. 4; Fig. 6 shows a more detailed second embodiment of the divider circuit and the two summation networks in the frequency 3-divider; and Fig. 7 shows a more detailed embodiment of a complete frequency 3-divider. The radio FM receiver shown as a block diagram in Fig. 1 comprises an antenna 1, a radio frequency receiver part 2, and a combination circuit 3 built up from two mixer units 4 and 5 for obtaining center frequency quadrature signals I and Q, as well as detection and sound reproduction means 6 connected to the combination circuit 3. A voltage- controlled oscillator (VCO) 7 is present whose oscillator control range is such that a division by two of this frequency will cover the control range for the combination frequency for the reception of radio signals over the reception channels usual in Europe and America, whereas a division by three of this frequency will cover the control range for the combination frequency for the reception of radio signals through the channels usual in Japan. As was noted above, an oscillator frequency fvco lying, for example, in the range from 196 MHz to 238 MHz will cause the 2-divider to supply a signal with a combination frequency feu in the range from 98 MHz to 119 MHz, and the 3-divider to supply a signal with a combination frequency fjp in the range from 65.3 MHz to 79.3 MHz. The center frequency obtained in the mixer units during tuning will then lie at 10.7 MHz both for the European/ American band (98-119 MHz) and for the Japanese band (65.3-79.3 MHz). A 2-divider 8 and a 3-divider 9 are connected to the VCO 7 for a division of the frequency by two and by three, respectively. Either the output signals of the 2-divider 8 or the output signals of the 3-divider 9 are supplied to the mixer units 4 and 5, i.e. via switching means 10. The center frequency quadrature signals I and Q obtained after combination in the mixer units 4 and 5 are subsequently supplied to the detection and sound reproduction means 6. The latter unit also comprises control means for controlling the VCO and the switching means 10. Various known types of 2-dividers with a duty cycle of 50% may be used as the 2-divider 8 connected to the VCO. An accurate 3-divider with a duty cycle of 50, however, was not known until now. An embodiment of such a 3-divider is shown in the block diagram of Fig. 2. The 3-divider shown in Fig. 2 comprises a divider circuit 11 which provides n cyclical output signals V n (t) for every three VCO signal cycles, for which it is true in this embodiment that V n (t) = Vj(t-(n-l)Δt) with n = 1, ..., 6, and Δt is the duration of half a VCO cycle, and comprises two summation networks 12 and 13 in each of which the cyclical output signals are combined with predetermined weighting factors designed for obtaining a quadrature component, whereupon the combination signal thus obtained is conducted through a respective low-pass filter 14, 15. The VCO signal is shown in Fig. 3A. The signals V n (t) derived therefrom are depicted in Fig. 3B. Multiplication of these signals V n (t) by respective weighting factors -2, +2, +4, +2, -2, -4 in the summation network 12 and subsequent addition yields a signal as shown in Fig. 3C, which signal results in a signal sin(l/3.ωt) after filtering in the low-pass filter 14. Multiplication of the signals V n (t) by respective weighting factors -3, -3, 0, +3, +3, 0 in the summation network 13 and subsequent addition leads to a signal as shown in Fig. 3D, which signal results in a signal cos(l/3.ωt) after filtering in the low-pass filter 15. The signals obtained have a frequency which is 1/3 of the frequency of the VCO, but they have a phase difference of 90°; the quadrature signals I and Q can be obtained in the mixer units 4 and 5 by means of these signals. A more detailed embodiment of the divider circuit and the two summation networks is shown in Fig. 4. This circuit is built up from a resistance network, switching transistors Ql, Q2, ..., Q6, which are brought into the conductive state consecutively during half a VCO cycle, and two control transistors Qcll and Qcl2 which are triggered by the VCO signal with a phase difference of 180°. The voltages across the collector resistances Rcl, Rc2, ..., Rc6 are referenced V_cl, V_c2, ..., V_c6. Assuming that Ql and Qcll pass current, V_cl will be highest, whereas V_c2, ..., V_c6 will have stepwise decreasing and increasing values as indicated in Fig. 5. The tap voltage values V_T4 and V_T5 will make the bases of Ql and Q2 "high", while the other tap voltage values will keep the bases of the other transistors Q3-Q6 "low". Q2 and Qcl2 will then also pass current in the next half VCO cycle. Now V_c2 will be highest, and V_c3, ..., V_c6, V_cl will decrease and increase stepwise as indicated in Fig. 5. The tap voltage values V_T5 and V_T6 will make the bases of Q2 and Q3 "high", so that Q3 and Qcl 1 will be able to pass current in the next half VCO cycle. A cyclical voltage gradient is thus obtained for V_cl, ..., V_c6. The resistance network realizes a weighting and a summation at the same time. In other words, the divider circuit 11 and the two summation networks 12 and 13 have been integrated. The two quadrature signals can be derived from the collector and tap voltages. Thus, for example, the one quadrature signal may be derived from the voltage difference between the collectors of Q4 and Q5, and the other quadrature signal from the difference between the tap voltages V_T4 and V_T3. Fig. 6 shows an improved embodiment in which the bases of the switching transistors are controlled from an emitter follower. Problems caused by a base current of the conducting switching transistor which is not equal to zero are avoided thereby. In addition, the collector voltage of the switching transistor may be raised without the risk of the transistor entering the saturated state. Furthermore, the one quadrature signal is derived from the voltage difference between the collectors of Q3 and Q6 here, while the other quadrature signal is derived from the difference between the tap voltages V_T5 and V_T2. More symmetrical quadrature voltages are obtained thereby. Fig. 7 is a more detailed diagram of an embodiment of a complete 3-divider. This circuit represents the circuit shown in Fig. 6 augmented with two separate current summation networks including weighting factors, formed by the transistor circuits QCla,b QC2,a,b, ..., QC6a,b, and low-pass filters connected thereto and formed by the resistors RcosA, RcosB, RsinA, and RsinB, and the parasitic capacitances of the transistors in the individual summation networks. The one filtered quadrature signal obtained with the weighting factors -2, +2, +4, +2, -2, -4 is derived from the voltage difference between the points A and B, the voltage at point A being built up by the currents through Q2, Q3, and Q4, and the voltage at point B being built up by the currents through Ql, Q5, and Q6. The other filtered quadrature signal is derived from the voltage difference between the points C and D, the voltage at point C being built up by the currents through Ql and Q2, and the voltage at point D being built up by the currents through Q4 and Q5. In the latter case, weighting by a factor 0 is realized in that the currents through Q3 and Q6 are not included in determining the voltages at points C and D. In this manner, accordingly, the output signals of the 3-divider are derived from the voltage difference between the points where the collector currents with positive weighting factors were added together and the points where the collector currents with negative weighting factors were added together.

Claims: CLAIMS: 1. A radio FM receiver provided with a voltage-controlled oscillator which can be connected via a frequency 2-divider to a quadrature combination circuit for transforming down the frequency of received radio signals and for supplying quadrature output signals, as well as with detection and sound reproduction means connected to said combination circuit, characterized in that in addition a frequency 3-divider is present by which the oscillator can be connected to the combination circuit, as well as switching means for connecting the mixer element to the oscillator either by the 2-divider or by the 3-divider. 2. A radio FM receiver as claimed in claim 1 , characterized in that the frequency 3-divider is provided with a divider circuit which supplies n cyclical output signals V n (t) for every three VCO signal cycles, for which it is true that V n (t) = Vj . (t-(n-l)Δt) with n = 1, ..., 6, and Δt = the duration of half a VCO cycle, and is provided with two summation networks in each of which the cyclical output signals are combined with predetermined weighting factors designed for obtaining a quadrature component, whereupon the combination signal thus obtained is conducted through a low-pass filter. 3. A radio FM receiver as claimed in claim 2, characterized in that the weighting factors for obtaining a first quadrature component have a mutual ratio of (-2, +2, +4, +2, -2, - 4), and those for obtaining the other quadrature component have a mutual ratio of (-3, -3, 0, +3, +3, 0). 4. A radio FM receiver as claimed in claim 2 or 3, characterized in that the divider circuit, the summation networks, and possibly the low-pass filters together form an integrated unit. 5. A radio FM receiver as claimed in claim 2, 3, or 4, characterized in that the frequency 3-divider is provided with two control transistors triggered by the VCO signal, each transistor being capable of controlling three switching transistors, and with a resistance network which comprises the collector resistances of the switching transistors, by means of 1Q which resistance network a current will flow through one of the switching transistors with its accompanying collector resistance in every half VCO cycle, during which stepwise decreasing and increasing currents flow through the other collector resistances, and in each subsequent half VCO cycle a next switching transistor passes current each time in a cyclical succession. 6. A radio FM receiver as claimed in claim 5, characterized in that the output signals of the 3-divider are derived from the voltage difference between the points where the collector currents with positive weighting factors were added together and the points where the collectors current with negative weighting factors were added together. 7. A frequency divider suitable for use in a radio FM receiver as claimed in any one of the preceding claims, characterized in that said frequency divider is provided with a divider circuit which supplies n cyclical output signals V n (t) for every l/2n oscillator signal cycles, for which it is true that V n (t) = Vi(t-(n-l)Δt), with n being an integer number and Δt the duration of half an oscillator cycle, and is provided with at least one summation network in which the cyclical output signals are combined with predetermined weighting factors, whereupon the combination signal thus obtained is conducted through a low-pass filter.

Inventors: KASPERKOVITZ WOLFDIETRICH G, KASPERKOVITZ, WOLFDIETRICH, G.
Applicants: KONINKL PHILIPS ELECTRONICS NV, KONINKLIJKE PHILIPS ELECTRONICS N.V.
Application year: 2000
Main classification: H03D3
IPC codes: H03D3, H03D7, H03K21, H04B1