Encoding of data for transmission over differential lines

Abstract: In order to transmit more than one bit per symbol over a differential transmission line, the data are encoding in the direction of current flow, the magnitude of the current flow, and the balance of currents on the differential line.

Description: BACKGROUND OF THE INVENTION 1. FIELD OF THE INVENTION: The present invention relates to a signal transfer method for transferring multi-bit signals over a transfer path which is allocated to one bit. 2. DESCRIPTION OF THE RELATED ART: Conventionally, two signal lines are employed for transferring signals having values of "0" or "1". At the transmission end of the transfer path, voltages which are selected in accordance with a particular value of a signal for transmission are applied to the two respective signal lines. At the receiving end of the transfer path, the difference between the voltage which is applied to one of the signal lines and the voltage which is applied to the other signal line is detected. For example, if the detected difference is larger than a predetermined voltage value, the received signal may be determined as having the value "1", and if the detected difference is smaller than the predetermined voltage value, the received signal may be determined as having the value "0". Such a pair of signal lines is usually referred to differential signal lines. As a method for transferring a signal which may take one of three or more values (hereinafter such a signal will be referred to as a "multi-value" signal) over such a pair of differential signal lines, a method is known in which the range between a voltage corresponding to the "0" value and a voltage corresponding to the "1" value is divided into a plurality of regions, for example. According to this method, any values other than "0" or "1" can be assigned to the respective divided regions. However, the aforementioned conventional method for transferring multi-value signals, which involves dividing a range between a voltage corresponding to the "0" value and the voltage corresponding to the "1" value into plurality of regions, can only provide a small margin for the determination of signal values at the receiving end. This increases the likelihood of misdetecting signal values at the receiving end. Reference may be made to DE-A-38 09 300 relative to which the present invention is characterized, and to US-A-5 436 887. The object of DE-A-38 09 300 is to develop a known transmission device, in which only a direct current signal as remote-control signal and audio-frequency signals are transmitted via a two-wire line, in such a manner that a plurality of direct current signals can be transmitted. This object is achieved in that a first direct current signal having a first polarity, a second direct current signal having reverse polarity, and a third direct current signal as well as further direct current signals having various currents are transmitted from one telecommunication device to another telecommunication device. US-A-5 436 887 provides a digital full-duplex line driver which allows digital information to be transmitted across a single bus simultaneously in both directions. This is accomplished by using both the voltage level on the bus and the current flowing through either a driver on one side of the bus or through the bus itself to decode the required information. SUMMARY OF THE INVENTION The present invention is defined in the claims. Accordingly, the preferred embodiment of the invention uses a technique for transferring a multi-bit signal over a single signal transfer path, including: respectively assigning a plurality of parameters for a plurality of bits so that a value representing "0" or a value representing "1" is set to each of the plurality of parameters in accordance with a value of a corresponding one of the plurality of bits; outputting an electric signal to the transfer path, the electric signal expressing a combination of the plurality of parameters having the values assigned thereto; receiving the electric signal from the transfer path and extracting the plurality of parameters from the electric signal; and detecting the respective values of the plurality of parameters. The plurality of parameters include a first parameter indicating a direction of an electric current flowing through the transfer path; a second parameter indicating an amount of electric current flowing through the transfer path; and a third parameter indicating a balance between an amount of electric current flowing out to the transfer path and an amount of electric current flowing in from the transfer path. In another embodiment of the invention, the transfer path is a pair of differential signal lines. According to the present invention, an electric signal which express a combination of a plurality of parameters, each parameter having a value representing "0" or "1", is output to a transfer path, and the electrical signal is received from the transfer path. The plurality of parameters are extracted from the received electric signal so that the values of the respective parameters can be detected. Thus, at the transmission end, a multi-bit signal is encoded into an electric signal that can be transferred over a transfer path which is allocated to one bit. At the receiving end, the electric signal which has been received via the transfer path is decoded into a multi-bit signal. As a result, it is possible to transfer a signal having multiple values over a transfer path which is allocated to one bit. Thus, the invention described herein makes possible the advantage of providing a signal transfer method for transferring multi-value signals over a transfer path which is allocated to one bit without increasing the likelihood of misdetecting signal values at the receiving end. This and other advantages of the present invention will become apparent to those skilled in the art upon reading and understanding the following detailed description with reference to the accompanying figures. BRIEF DESCRIPTION OF THE DRAWINGS Figure 1 is a schematic block diagram illustrating the structure of a signal transfer system 1 for implementing the signal transfer method according to the present invention. Figure 2 is a more detailed block diagram illustrating the structure of the signal transfer system 1 . Figures 3A and 3B are circuit diagrams illustrating an example structure of a current direction switching circuit 132 according to the present invention. Figures 4A and 4B are circuit diagrams illustrating an example structure of a common current compensation circuit 252 according to the present invention. DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, the present invention will be described by way of examples, with reference to the accompanying figures. Figure 1 is a schematic block diagram illustrating the structure of a signal transfer system 1 for implementing the signal transfer method according to the present invention. The signal transfer system 1 includes a transmitter 10 , a receiver 20 , and a transfer path 30 which connects the transmitter 10 to the receiver 20 . The transfer path 30 is allocated to one bit. In the example shown in Figure 1 , the transfer path 30 is illustrated as including signal lines 30a and 30b . The signal lines 30a and 30b may also be referred to as "differential signal lines". The transmitter 10 receives a 3-bit signal (A 1 , A 2 , A 3 ). The 3-bit signal (A 1 , A 2 , A 3 ) can express eight (= 2 ×2×2) different values. The transmitter 10 includes an encoder section 10a for encoding the 3-bit signal (A 1 , A 2 , A 3 ) into an electric signal that can be transferred over the transfer path 30 , which is allocated to one bit. The bits A 1 , A 2 , A 3 are respectively assigned to parameters pertaining to different electrical characteristics. For example, the bit A 1 may be assigned to a parameter P 1 which represents the direction of an electric current flowing through the transfer path 30 (hereinafter simply referred to as a "current direction"); the bit A 2 may be assigned to a parameter P 2 which represents the amount of electric current flowing out to the transfer path 30 (hereinafter simply referred to as a "current amount"); and the bit A 3 may be assigned to a parameter P 3 which represents the balance between the amount of electric current flowing out to the transfer path 30 and the amount of electric current flowing in from the transfer path 30 (hereinafter simply referred to as a "current balance"). Each of the parameters P 1 , P 2 , P 3 takes a value representing "0" or "1". The relationship between the values of the parameter P 1 and the current direction may be defined as shown in Table 1 below: In other words, when a current flows in the transfer path 30 in the clockwise direction (i.e., in the order of the signal line 30a → the decoder section 20a → the signal line 30b ), the parameter P 1 takes the "0" value. When a current flows in the transfer path 30 in the counterclockwise direction (i.e., in the order of the signal line 30b → the decoder section 20a → the signal line 30a), the parameter P 1 takes the "1" value. The relationship between the values of the parameter P 2 and the current amount may be defined as shown in Table 2 below: value of parameter P 2 current amount "0" small (e.g., 5 mA) "1" large (e.g., 5.25 mA) In other words, when the amount of current which flows out to the transfer path 30 is relatively small (e.g., 5 mA), the parameter P 2 takes the "0" value. When the amount of current which flows out to the transfer path 30 is relatively large (e.g., 5.25 mA), the parameter P 2 takes the "1" value. The relationship between the values of the parameter P 3 and the current balance may be defined as shown in Table 3 below: value of parameter P 3 current balance "0" amount of current flowing out = amount of current flowing in "1" amount of current flowing out ≠ amount of current flowing in In other words, when the amount of current flowing out to the transfer path 30 is equal to the amount of current flowing in from the transfer path 30 , the parameter P 3 takes the "0" value. When the amount of current flowing out to the transfer path 30 is not equal to the amount of current flowing in from the transfer path 30 , the parameter P 3 takes the "1" value. The encoder section 10a sets the values of the parameter P 1 to P 3 in accordance with the values of the bits A 1 , A 2 , A 3 , and outputs an electric signal which expresses a combination of the parameters P 1 , P 2 , P 3 to the transfer path 30 . For example, if (A 1 , A 2 , A 3 ) = (0, 1, 1), the encoder section 10a sets the values of parameters P 1 , P 2 , and P 3 such that (P 1 , P 2 , P 3 ) = (0, 1, 1), and outputs an electric signal which expresses this combination of parameters P 1 , P 2 , P 3 to the transfer path 30 . In this case, the electric signal which is output to the transfer path 30 is an electric signal which flows in the clockwise current direction (P 1 = "0"), and which has a large current amount (P 2 = "1"), such that the amount of current flowing out to the transfer path 30 is not equal to the amount of current flowing in from the transfer path 30 (P 3 = "1"). Thus, the encoder section 10a encodes the 3-bit signal (A 1 , A 2 , A 3 ) into an electric signal that can be transferred over the transfer path 30 , which is allocated to one bit. The resultant electric signal is output to the transfer path 30 . The receiver 20 includes a decoder section 20a for receiving the electric signal from the transfer path 30 and decoding the electric signal into a 3-bit signal (B 1 , B 2 , B 3 ). Such decoding is achieved by extracting the parameters P 1 , P 2 , and P 3 from the electric signal and detecting the respective values of the parameters P 1 , P 2 , and P 3 . Figure 2 is a more detailed block diagram illustrating the structure of the signal transfer system 1 . In the transmitter 10 , the encoder section 10a includes a converter circuit 10b for converting the 3-bit signal (A 1 , A 2 , A 3 ) into a set of control signals (S 1 , S 2 , S 3 ), and an electric signal output circuit 10c for generating an electric signal in accordance with the set of control signals (S 1 , S 2 , S 3 ,) and outputting the generated electric signal to the transfer path 30 . The electric signal output circuit 10c includes a constant current source 112 (+5 mA) and a constant current source 114 (+0.25 mA). One end of the constant current source 112 is coupled to a source potential, and the other end of the constant current source 112 is coupled to the signal line 130a . One end of the constant current source 114 is coupled to the source potential, and the other end of the constant current source 114 is coupled to the signal line 130a via a switch 116 . The signal line 130a is coupled to a current direction switching circuit 132 . The source potential may be about 3.0 V, for example. The switch 116 is turned on and off in accordance with the control signal S 1 , which is output from the converter circuit 10b . If the control signal S 1 has the "1" value, the switch 116 is turned on. If the control signal S 1 has the "0" value, the switch 116 is turned off. The electric signal output circuit 10c further includes a constant current source 122 (-5 mA) and a constant current source 124 (-0.25 mA). One end of the constant current source 122 is coupled to a ground potential, and the other end of the constant current source 122 is coupled to the signal line 130b . One end of the constant current source 124 is coupled to the ground potential, and the other end of the constant current source 124 is coupled to the signal line 130b via a switch 126 . The signal line 130b is coupled to the current direction switching circuit 132 . The ground potential may be about 0 V, for example. The switch 126 is turned on and off in accordance with the control signal S 2 , which is output from the converter circuit 10b . If the control signal S 2 has the "1" value, the switch 126 is turned on. If the control signal S 2 has the "0" value, the switch 126 is turned off. The current direction switching circuit 132 in the electric signal output circuit 10c switches the direction of the current which flows through the transfer path 30 (i.e., the signal lines 30a and 30b ) in accordance with the control signal S 3 which is output from the converter circuit 10b . When the signal S 3 takes the "0" value, the current direction switching circuit 132 electrically couples the signal line 130a to the signal line 30a , and couples the signal line 130b to the signal line 30b . As a result, the current which flows out from the constant current sources 112 and 114 flows in the clockwise direction (i.e., in the order of the signal line 130a → the signal line 30a → the receiver 20 → the signal line 30b → the signal line 130b ). When the signal S 3 takes the "1" value, the current direction switching circuit 132 electrically couples the signal line 130a to the signal line 30b , and couples the signal line 130b to the signal line 30a . As a result, the current which flows out from the constant current sources 112 and 114 flow in the counterclockwise direction (i.e., in the order of the signal line 130a → the signal line 30b → the receiver 20 → the signal line 30a → the signal line 130b ). Table 4 illustrates the logical operations performed by the converter circuit 10b . A 1 A 2 A 3 S 1 S 2 S 3 0 0 0 0 0 0 0 0 1 0 1 0 0 1 0 1 1 0 0 1 1 1 0 0 1 0 0 0 0 1 1 0 1 0 1 1 1 1 0 1 1 1 1 1 1 1 0 1 The logical operations illustrated in Table 4 can be realized based on the logical formulae shown in eq. 1. The converter circuit 10b can be implemented by any logic circuit which satisfies the logical formula expressed by eq. 1: S 1 = A 2 S 2 = A 3 (if A 2 = "0") = /A 3 (if A 2 = "1") S 3 = A 1 In eq. 1, /A 3 means a logical NOT of A 3 . Arrow A r shown in Figure 2 shows the flow of an electric signal which results from encoding the 3-bit signal (A 1 , A 2 , A 3 ) = (0, 1, 1). According to Table 4, the 3-bit signal (A 1 , A 2 , A 3 ) = (0, 1, 1) is converted into a set of control signals (S 1 , S 2 , S 3 )=(1,0, 0) by the converter circuit 10b . As a result, the control signal S 1 turns on the switch 116 , and the control signal S 2 turns off the switch 126 . The control signal S 3 controls the current direction switching circuit 132 so that an electric current will flow through the transfer path 30 in the clockwise direction. As a result, the current from the constant current sources 112 and 114 (+5.25 mA) flows through the signal line 30a from the transmitter 10 to the receiver 20 . Moreover, a current (-5 mA) flows through the signal line 30b from the receiver 20 to the transmitter 10 , so as to be drawn into the constant current source 122 . The difference (+0.25 mA) between the current flowing through the signal line 30a (+5.25 mA) and the current flowing through the signal line 30b (-5 mA) is compensated for by a common current compensation circuit 252 in the receiver 20 . Thus, by encoding the 3-bit signal (A 1 , A 2 , A 3 ) = (0, 1, 1) in the above-described manner, an electric signal is output to the transfer path 30 which flows therethrough in the clockwise current direction (P 1 = "0"), and which has a large current amount (5.25 mA) flowing out thereto (P 2 = "1"), such that the amount of current (5.25 mA) flowing out to the transfer path 30 is not equal to the amount of current (5 mA) flowing in from the transfer path 30 (P 3 = "1"). This electric signal is an electric signal which expresses a combination of parameters such that (P 1 , P 2 , P 3 ) = (0, 1, 1). Figures 3A and 3B are circuit diagrams illustrating an example structure of the current direction switching circuit 132 . The current direction switching circuit 132 includes transistors 132a to 132d . In Figure 3A , arrows A r1 and A r2 show the current path in the case where the control signal S 3 takes the "0" value. When the control signal S 3 takes the "0" value, the transistors 132a and 132d are turned on. As a result, the signal lines 130a and 30a are electrically interconnected, and the signal lines 130b and 30b are electrically interconnected. In Figure 3B , arrows A r3 and A r4 show the current path in the case where the control signal S 3 takes the "1" value. When the control signal S 3 takes the "1" value, the transistors 132b and 132c are turned on. As a result, the signal lines 130a and 30b are electrically interconnected, and the signal lines 130b and 30a are electrically interconnected. With reference to Figure 2 , the decoding section 20a in the receiver 20 includes an electric signal input circuit 20c for receiving an electric signal from the transfer path 30 and generating output voltages V c1 to V c5 in accordance with the received electric signal, and a converter circuit 20b for converting the set of output voltages (V c1 , V c2 , V c3 , V c4 , V c5 ) into a 3-bit signal (B 1 , B 2 , B 3 ). The electric signal input circuit 20c includes a constant current source 212 (+5.125 mA), a constant current source 214 (-5.125 mA), comparators 222, 224, 226, 228, and 230, resistors 242, 244, 246, and 248 , as well as a common current compensation circuit 252 . One end of the constant current source 212 is coupled to a source potential, and the other end of the constant current source 212 is coupled to the common current compensation circuit 252 via the resistor 246 . One end of the constant current source 214 is coupled to a ground potential, and the other end of the constant current source 214 is coupled to the common current compensation circuit 252 via the resistor 248 . The source potential may be about 3.0 V, for example. The ground potential may be about 0 V, for example. One end of the resistor 242 is coupled to the signal line 30a , and the other end of the resistor 242 is coupled to the resistor 244 and the common current compensation circuit 252 . One end of the resistor 244 is coupled to the signal line 30b , and the other end of the resistor 244 is coupled to the resistor 242 and the common current compensation circuit 252 . The resistors 242 and 244 may each have a resistance of about 50Ω, for example. Each of the comparators 222, 224, 226, 228, and 230 has a + input terminal and a - input terminal. If the voltage which is input at the + input terminal is lower than the voltage input at the - input terminal, each comparator outputs a signal representing the "0" value. If the voltage which is input at the + input terminal is higher than the voltage input at the - input terminal, each comparator outputs a signal representing the "1" value. The comparator 230 is used for detecting the value of the parameter P 1 (current direction). The comparator 230 outputs the output voltage V c5 . The comparators 222 and 224 are used for detecting the value of the parameter P 2 (current amount) and the parameter P 3 (current balance) in the case where an electric current is flowing through the transfer path 30 in the clockwise direction. The comparator 222 outputs the output voltage V c1 , and the comparator 224 outputs the output voltage V c2 . The comparators 226 and 228 are used for detecting the value of the parameter P 2 (current amount) and the parameter P 3 (current balance) in the case where an electric current is flowing through the transfer path 30 in the counterclockwise direction. The comparator 226 outputs the output voltage V c3 , and the comparator 228 outputs the output voltage V c4 . The common current compensation circuit 252 compensates for the difference between the current flowing through the signal line 30a and the current flowing through the signal line 30b . For example, in the case where an electric current of +5.25 mA is flowing through the signal line 30a from the transmitter 10 to the receiver 20 and an electric current of -5 mA is flowing through the signal line 30b from the receiver 20 to the transmitter 10 , an electric current of +0.25 mA is drawn into the common current compensation circuit 252 . For another example, in the case where an electric current of +5 mA is flowing through the signal line 30a from the transmitter 10 to the receiver 20 and an electric current of -5.25 mA is flowing through the signal line 30b from the receiver 20 to the transmitter 10 , an electric current of -0.25 mA is discharged from the common current compensation circuit 252 . Figures 4A and 4B are circuit diagrams illustrating an example structure of the common current compensation circuit 252 . Figure 4A illustrates an electric current of +0.25 mA being drawn into the common current compensation circuit 252 . Figure 4B illustrates an electric current of -0.25 mA being discharged from the common current compensation circuit 252 . Table 5 illustrates the logical operations performed by the converter circuit 20b. V c1 V c2 V c3 V c4 V c5 B 1 B 2 B 3 0 0 - - 0 0 0 0 0 1 - - 0 0 0 1 1 1 - - 0 0 1 0 1 0 - - 0 0 1 1 - - 0 0 1 1 0 0 - - 0 1 1 1 0 1 - - 1 1 1 1 1 0 - - 1 0 1 1 1 1 The logical operations illustrated in Table 5 can be realized based on the logical formulae shown in eq. 2. The converter circuit 20b can be implemented by any logic circuit which satisfies the logical formula expressed by eq. 2: B 1 = V c5 B 2 = V c1 (if V c5 = "0") = V c3 (if V c5 = "1") B 3 = V c2 (if V c5 = "0" and if V c1 = "0") = /V c2 (if V c5 = "0" and if V c1 = "1") = V c4 (if V c5 = "1" and if V c3 = "0") = /V c4 (if V c5 = "1" and if V c3 = "1") In eq. 2, /V c2 means a logical NOT of V c2 , and /V c4 means a logical NOT of V c4 . Thus, the decoder section 20a receives an electric signal from the transfer path 30 and decodes the received electric signal to generate a 3-bit signal (B 1 , B 2 , B 3 ). For example, an electric signal expressing a combination of parameters (P 1 , P 2 , P 3 ) = (0, 1, 1) is decoded into a 3-bit signal (B 1 , B 2 , B 3 ) = (0, 1, 1). The 3-bit signal (B 1 , B 2 , B 3 ) is identical with the 3-bit signal (A 1 , A 2 , A 3 ). Thus, a 3-bit signal can be successfully transferred from the transmitter 10 to the receiver 20 via the transfer path 30 , which is allocated to one bit. Although a transfer of a 3-bit signal is illustrated in the above example, the present invention is not limited to such embodiments. An N-bit signal can be transferred by transferring an electric signal which expresses a combination of N parameters via a transfer path which is allocated to one bit, where N is an integer equal to or greater than 2. Any configuration of the transfer path 30 can be selected so long as the transfer path 30 is allocated to one bit. For example, the transfer path 30 may be composed of one signal line. In the above example, the parameter P 2 is illustrated as indicating the amount of current which flows out to the transfer path 30 . Alternatively, the parameter P 2 may indicate the amount of current which flows in from the transfer path 30 . According to the present invention, an electric signal which express a combination of a plurality of parameters, each parameter having a value representing "0" or "1", is output to a transfer path, from which the electrical signal is received. The plurality of parameters are extracted from the received electric signal so that the values of the respective parameters are detected. As a result, it is possible to transfer a multi-bit signal over a transfer path which is allocated to one bit. Various other modifications will be apparent to and can be readily made by those skilled in the art without departing from the scope of this invention.

Claims: A signal transfer method for transferring a multi-bit signal including first, second and third logical bits (A1, A2, A3) over a transfer path 30, comprising the steps of: encoding said multi-bit signal by assigning the logical value of said first, second and third bits to a respective first, second and third parameter (P1, P2, P3) of an electric signal on the transfer path (30), the parameters being electric characteristics of the electric signal; outputting the electric signal to the transfer path (30), the electric signal having said first, second and third parameters expressing said first, second and third bits in combination; receiving the electric signal from the transfer path; and detecting each of the parameters to decode the first, second and third bits from the electric signal; wherein the first parameter (P1) indicates the direction of an electric current flowing out to the transfer path; the second parameter (P2) indicates the amount of electric current flowing out to the transfer path; characterised in that : the third parameter (P3) indicates whether the amount of an electric current flowing out to the transfer path is equal or not to the amount of an electric current flowing in from the transfer path. A signal transfer method according to claim 1, wherein the transfer path (30) is a pair of differential signal lines (30a, 30b). A signal transfer system for transferring a multi-bit signal including first, second and third logical bits (A1, A2, A3) over a transfer path, comprising: means (10) for encoding said multi-bit signal by assigning the logical value of said first, second and third bits to a respective first, second and third parameter (P1, P2, P3) of an electric signal on the transfer path, the parameters being electric characteristics of the electric signal; means (10) for outputting the electric signal to the transfer path, the electric signal having said first, second and third parameters expressing said first, second and third bits in combination; means (20) for receiving the electric signal from the transfer path; and means (20) for detecting each of the parameters to decode the first, second and third bits from the electric signal; wherein: the first parameter (P1) indicates the direction of an electric current flowing out to the transfer path; the second parameter (P2) indicates the amount of electric current flowing out to the transfer path; characterised in that : the third parameter (P3) indicates whether the amount of an electric current flowing out to the transfer path is equal or not to the amount of an electric current flowing in from the transfer path. Use of first, second and third electric characteristics (P1, P2, P3) of a transfer signal in a transfer path (30) to carry information representing first, second and third bits (A1, A2, A3) of a multi-bit signal respectively, wherein: the first electric characteristic (P1) is the direction of an electric current flowing out to the transfer path; the second electric characteristic (P2) is an amount of electric current flowing out to transfer path; characterised in that : the third electric characteristic (P3) is whether the amount of an electric current flowing out to the transfer path is equal or not to the amount of an electrical current flowing in from the transfer path.

Inventors: YAMAUCHI HIROYUKI, YAMAUCHI, HIROYUKI
Applicants: MATSUSHITA ELECTRIC IND CO LTD, MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.
Application year: 2000
Main classification: H04L25
IPC codes: H04L25, H04L5