COMMUNICATION SYSTEM EMPLOYING A NETWORK OF POWER MANAGED TRANSCEIVERS THAT CAN GENERATE A CLOCKING SIGNAL OR ENABLE DATA BYPASS OF A DIGITAL SYSTEM ASSOCIATED WITH EACH TRANSCEIVER

Abstract: A communication system is provided for interconnecting a network of digital systems. The communication system includes a communication line and a transceiver placed between the communication line and each digital system. The transceiver includes a receiver which can be selectively powered down whenever activity within the communication line ceases. The external conductors extending from each transceiver integrated circuit to an associated digital system are minimal, and the status of a clock/status signal conductor will indicate if the digital system is in a low power state (no clocking signal) or whether the digital system will be in a normal or protected clocking state. When a communication system is initially started, activity within the communication line will not lock the recovery circuits of the transceiver and, therefore, the transceiver will forward the received signal back out the transceiver without causing that signal to enter the associated digital system. In this manner, the latching/delay circuitry of the digital system is bypassed and the initial activity within the communication line can be sent quickly through all nodes of the communication system for rapid start-up procedures.

Description: TITLE: COMMUNICATION SYSTEM EMPLOYING A NETWORK OF POWER MANAGED TRANSCEIVERS THAT CAN GENERATE A CLOCKING SIGNAL OR ENABLE DATA BYPASS OF A DIGITAL SYSTEM ASSOCIATED WITH EACH TRANSCEIVER BACKGROUND OF THE INVENTION 1 Field of the Invention This invention relates to a communication system compπsmg a network of interconnected transceivers and associated digital systems and, more particularly, to mechanisms for selectively clocking the digital systems, bypassing data from bemg routed through the digital systems, or for reducmg power consumption within transceivers and digital systems dependmg on whether data is received by the transceiver, and/or whether the transceivers are locked m sync with the data 2 Description of the Related Art Communication systems are generally well-known as containing at least two nodes interconnected by a communication lme. Each node may mclude both a transmitter and a receiver, generally referred to as a "transceiver". The transceiver provides an interface between signals sent over the communication line and a digital system which operates upon that signal in the digital domain. A set of nodes interconnected by a commumcation lme can be referred to as a communication network A transmitter within one node can transmit a signal to one or more receivers m various nodes across the network In high speed applications, the signal transmitted across the network can contain instructions and/or data, which conceivably could be audio data, video data, or both, and therefore the network may be considered a multi-media network. The transfer rate of multi-media signals is generally quite high and therefore requires a relatively high speed commumcation lme, a suitable lme bemg an optical fiber, for example If an optical fiber is used, then an interface which converts light energy to an electrical signal recognized by each transceiver is needed That interface is generally a photosensor at the receive end of the commumcation lme, or a light emitting diode at the transmit end The interface is therefore an optical interface and therefore the transceiver can be considered a fiber optic transceiver It is believed that most conventional fiber optic transceivers generally encompass elements which perform light/voltage conversion and nothmg else. The system associated with each transceiver may employ both an analog and a digital section which perform manipulation of the received signal, processes that signal, and thereafter presents a transmitted signal compatible with signals forwarded across the optical fiber. Accordmgly, a conventional, optical multi-media network typically employs a rather simplistic fiber optic transceiver, and a digital processmg system, at each node of the network The digital system may be called upon not only to process the signal preferably m real-time, but also to process those signals synchronously Therefore, conventional digital systems not only require a receiver with accurate amplification and data detection, but further utilize a phase-locked loop ("PLL") useful m recovering a clocking signal from the received data. If the amplifiers and data detecting circuits at the receive end, drivers at the transmit end, and the PLL clock recovery circuits impute noise to, or receive noise from, the digital core of the digital processor, then data detection, clock recovery, data transrmttal, and generalized data processmg may be adversely affected. It would be desirable to rnimmize the cross talk between the digital processmg core and the incoming data detection, clock recovery, and outgomg data driving circuits. Digital signal transitions, and/or latching circuits operating on those transitions, can oftentimes mduce significant amounts of noise upon the power and ground conductors extending across the digital system to provide power and ground to the more sensitive clock and data recovery circuits, as well as the data transmit driver In addition to minimizing noise susceptibility of the sensing circuits, it would also be of benefit to provide power management to at least a portion of those circuits. In this manner, a low-power application can be realized as a sigmficant improvement to conventional multi-media commumcation networks. Coupled with noise isolation and power management, the sensing portion of each node should also be made immediately responsive to the data signal forwarded from the network master In this fashion, the slave nodes can recover a clockmg signal m parallel and concurrent with each other so that the clocking signal is available as soon as possible to the corresponding digital systems. SUMMARY OF THE INVENTION The problems outlined above are m large part solved by an unproved multi-media commumcation system. The commumcation system mcludes a set of nodes, wherem each node mvolves a transceiver interface and a digital system. The transceiver is coupled between the commumcation lme and a corresponding digital system, and is used to modify the transmission format and/or protocol mto a sequence of bits recognized by one or more digital systems within corresponding nodes. The transceiver is purposely placed on one or more monolithic substrates separate from a substrate bearing a digital system. The sensitive sensing and driving circuits, as well as the clock recovery PLL, may be embodied upon the transceiver separate from the corresponding digital system, and the noise mduced by that system. The present transceiver mcludes both a receiver and a transmitter The receiver senses data transmitted across the commumcation lme and performs conditioning and amplification to that signal before transferring it to the digital system for processmg. Additionally, the receiver may mclude a PLL which recovers a clock from the received signal, and uses the recovered clockmg signal to synchronize operations within the corresponding digital system. Of benefit, the number of conductors which link the transceiver and corresponding digital system is minimized as, for example, a data output conductor, a clockmg/status signal output conductor, power, and ground. The power and ground conductors may be used to apply a common VDD and VSS supplies between the transceiver and corresponding digital system. It is noted, however, if a common power and ground supply is not needed, then only two conductors need be employed between the receiver of the transceiver and the respective digital system. The sensing circuitry within the receiver generally operates at speeds matching the incoming data. For example, if the data rate of the incoming signal, and therefore the operating speed of the sensing circuitry, is several Mbits second, or more preferably 50 Mbaud or greater, then the power consumed by the sensmg circuitry can be rather substantial. Instead of maintaining power to the sensmg circuitry duπng times when a signal is not present on the commumcation lme, the receiver utilizes an activity detector which de-couples power to the sensmg circuit in times when data is not present on the receiver receive port. In this manner, the present transceiver maintains power to power consumptive devices only when an mput signal is present upon the receive port. Duπng all other times, the power consumptive amplifiers, comparators, and clock recovery circuits (i.e., PLL) are powered down. Thus, a multi-media network employmg the present transceivers can advantageously be placed in a low power environment, or an environment m which power is drawn from a portable power supply, such as a battery. For example, the multi-media network can be used m an automotive application, where audio, video, or generalized traffic information, are bemg sent between digital processors arranged throughout the automobile. Such processors mclude, for example, speech encoders/decoders, video/audio processors, video momtors, audio amplifiers (and associated speakers), sensors, calculators, computers, and FM/AM tuners, all of which can be placed on-board existing automobiles to enhance both usability and performance of the automobile. In an automotive environment, it is desirable that the commumcation lme be fiber optic, and the light-transrmssive data be isolated from each transceiver by photosensors and LEDs. Optical fibers can accommodate the relatively high baud rates of the multi-media network, but also can reliably send those rates to nodes distally located from one another at vaπous locations about the automobile. A transceiver which is isolated on or more chips separate from the noisy digital systems, and which contains receive-sensing circuitry and clock recovery mechanisms is henceforth referred to as a "smart" transceiver. The smart transceiver contains active and passive components which can, m addition to its sensmg, dπvmg, and clock recovery functions, also selectively powers certam components only when mcommg data is present on the receive port. The smart transceiver therefore has power management capability and, furthermore, can selectively bypass the digital system connected to the transceiver. The digital system is bypassed at times when the mput signal is present upon the receive port, yet clock recovery (i.e., PLL "locked" status) has not yet occurred. The bypass feature occurs whenever, for example, mput data m the form of optical energy is received upon the receive port of the transceiver, yet time has not sufficiently elapsed to allow the PLL to lock its voltage-controlled oscillator ("VCO") output to the mcommg data stream transitions. In a network environment, the network is arranged having a plurality of nodes typically configured m a ring. The first node slave within the ring will then initially receive an mcommg signal from a master. Rather than waiting for that node's transceiver PLL to lock upon the mcommg data stream frequency and phase, the first node receiver simply forwards the unlocked data stream signal from the receiver output to its transmitter mput, whereupon the first node transmitter output will then be immediately dispatched to the next node within the network. That node will perform the same bypass operation, thereby allowing all nodes within the network to receive somewhat m parallel the mcommg optical signal. This affords the PLL m each node to lock upon the mcommg hght stream at approximately the same time, thereby achievmg relatively concurrent lockmg among all clock recovery PLLs within each network node. Thereafter, once valid data is sent across the network, any node within that network will be able to immediately recognize and process the valid data smce each and every node will have a pre-existing, recovered clockmg signal. According to one embodiment, a commumcation system is present. The commumcation system mcludes a plurality of digital systems interconnected by respective transceivers to a commumcation lme. At least one of the transceivers compπses a receiver adapted to enter a relatively high power consumptive state from a relatively low power consumptive state duπng times when a signal is present within the commumcation lme. When the signal is absent, the receiver transitions from the high power consumptive state to the low power consumptive state. The receiver mcludes a PLL and mcommg data sensmg circuits. The PLL produces a clockmg signal and forwards the clockmg signal to a respective digital system when the PLL is locked m sync with transitions of the mcommg signal. When the mcommg signal is present yet the PLL is not yet locked in sync with that signal, the PLL will produce a clockmg signal at a reduced clockmg frequency to protect against overdπvmg the digital system connected to receive that clockmg signal. Therefore, at times m which the PLL is in an unlocked state, it can be assured that the digital system will not be dπven at a rate which exceeds the maximum frequency at which it can operate. Accordmg to another embodiment, the digital system can mclude a lock detector which bypasses forwarding the mcommg signal sent to the receiver, through the receiver, and to the digital system. Instead, the lock detector will forward the mcommg signal directly to a transmitter whenever the PLL is not locked m sync with that mcommg signal. Accordmg to yet another embodiment, a receiver is provided havmg a receive port and an activity detector coupled to the receive port. The activity detector produces an activity signal duπng times when an mput signal is forwarded to the receive port. A power supply generator is coupled to the activity detector which then produces a power supply output upon receipt of the activity signal. Coupled to the power supply generator and the receive port is a receiver that compπses receive/sensing circuitry, and preferably a PLL. The PLL produces a clockmg signal from the mput signal duπng times when the power supply output is produced. The activity detector mcludes, for example, a comparator and a timei, both of which work m conjunction to produce the activity signal if a magnitude of the mput signal upon the receive port exceeds a reference voltage for a defined amount of time. A lock detector can be attributed to (i.e., embodied upon ) the digital system or, alternatively, attributed to the transceiver. In the latter instance, the lock detector is output from the transceiver and forwarded to a multiplexer coupled to select the mput signal for transmission to a transmitter m lieu of an output from the digital system if the detector yields an unlock value. Accordmg to yet a further embodiment, a method is provided for regulating power consumption within, and clockmg signal output from, a transceiver While maintaining power needed to detect if and when an mput signal is forwarded to the transceiver, power is de-asserted to sensmg and calibration circuitry of the receiver which receives the mput signal, as well as de-asserting power to a PLL within the receiver whenever an mput signal is absent from a receive port of the receiver. A clockmg signal can be produced from the PLL by asserting power to the PLL only when the mput signal is present. It is understood that the PLL is preferably a part of the receiver; however, the PLL can be part of the digital system and the receiver merely generates a status signal to the power supply generator dependmg of whether the PLL is to receive power. The state of the status signal is thereby dependent on whether activity is detected m the network via the mput signal. BRIEF DESCRIPTION OF THE DRAWINGS Other objects and advantages of the invention will become apparent upon reading the folio wing detailed descπption and upon reference to the accompanying drawings m which: Fig. 1 is a block diagram of a commumcation system, wherem at least one node of the commumcation system mcludes a digital system and a transceiver placed withm a module compπsmg one or more monolithic substrates arranged separate from the digital system; Fig. 2 is a block diagram of a receiver and transmitter, accordmg to one embodiment, of the transceiver shown m Fig. 1; Fig. 3 is a timing diagram of a clock/status output signal dependent upon an mput signal forwarded to the receiver and whether or not the PLL withm the receiver is locked m sync with the mput signal; Fig. 4 is a block diagram of a lock detector coupled to receive data from the receiver and to determine whether if data is to be forwarded to the digital system, or if the data is to bypass the digital system and pass directly to a receiver withm another node of the commumcation system to achieve rapid, parallel lockmg among all networked transceivers which receive an initial sequence of data signal transitions; and Fig. 5 is a block diagram of a lock detector, accordmg to an alternative embodiment. While the invention is susceptible to vaπous modifications and alternative forms, specific embodiments thereof are shown by way of example m the drawings and will herem be descπbed m detail. It should be understood, however, that the drawings and detailed descπption thereto are not mtended to limit the invention to the particular form disclosed, but on the contrary, the intention is to cover all modifications, equivalents and alternatives falling withm the sprπt and scope of the present invention as defined by the appended claims. DETAELED DESCRIPTION OF PREFERRED EMBODIMENTS Turning to the drawings, Fig. 1 illustrates a commumcation system 10 havmg a set of nodes 12 mterconnected withm a network. Each node 12 is mterconnected by a communication lme 14 to form a πng Signals forwarded across the commumcation lme 14 are preferably synchronized to form a synchronized πng topology network of mterconnected nodes. Thus, all nodes are operably synchronized to a tuning reference withm a network master. A suitable commumcation lme compπses an optical fiber. Each node 12 operates as either a master or a slave mterconnected as commumcation system 10. One node of the commumcation system is designed as a master which mitiates the commumcation system 10, and provides a timing reference for the network. The master may also contain a register that is wπtten to by software associated with that master. The software sets the register so that the node attributed to that register is designated as a master separate from other registers of other nodes designated as slaves. Withm each node 12 is a smart transceiver which, if the commumcation lme 14 is an optical fiber, that transceiver is deemed a fiber optic transceiver or "FOT", shown as reference numeral 18. Transceiver 18 provides an interface between the commumcation signal withm commumcation lme 14 and corresponding digital system 20. Transceiver 18 is a smart transceiver and thereby mcludes a receiver for sensmg a signal provided to a receiver port, recovering a clock signal from that mcommg signal, and further mcludes a transmitter for dπvmg an output upon a transmit port. The receive and transmit ports for each transceiver are labeled as "RCV" and "XMT". Digital system 20 mvolves any system which operates pπmaπly m the digital realm to perform relatively rapid manipulation and/or processmg of digital signals forwarded thereto. The manipulations or processmg functions can occur withm one or more integrated circuits, and those circuits are separate from a monolithic substrate upon which at least a portion of transceiver 18 is embodied. Of benefit is a minimal number of conductors which extend externally between a transceiver and coπespondrng digital system withm each node In this fashion, relatively few additional pm connectors need be introduced. Commumcation system 10 can find applications m any environment m which generalized data, instructions, and/or data (i.e., video, voice (audio)), can be transferred between nodes or distπbuted among nodes. One exemplary application mvolves a low power application where transceivers are partially powered down duπng times when a signal is not present at the receive port of the transceiver. A suitable low power application would aπse m an automotive setting, where signals are not present when the automobile is turned off and, therefore, the commumcation network 10 enters a low power or "sleep" state. Fig 2 illustrates a transceiver 18 interposed between a commumcation lme mterface 24 and an associated digital system, accordmg to one embodiment. Interface 24 is dependent on the medium through which the communication signal is sent. Accordmg to one example, the commumcation lme is an optical fiber and therefore mterface 24 is used to convert modulated light mto an mput voltage V m . The receive port is that which receives V m from the commumcation lme, and the transmit port is that which transmits V ouτ from the transmitter. Similar to mterface 24, the transmitter portion of transceiver 18 also mcludes an mterface 26 which converts V ouτ to the proper format for transmission across the commumcation lme. In the example shown, mterface 24 compπses a photosensor and mterface 26 compπses a pm diode, or LED. Further shown is transmitter 18 compπsmg both a receiver 28 and a transmitter 30. Receiver 28 mcludes a low noise transrmpedence amplifier 32, which has a bandwidth and an open loop gam high enough to handle, e.g , a 50 Mbaud data rate. Amplifier 32 is mtended to force the external pm diode 24 to a fixed reverse bias voltage. Amplifier 32 thereby has a wide dynamic range to accommodate the range of currents bemg received. Coupled to the output of amplifier 32 is a high-speed comparator 34 Comparator 34 takes the amplified signal and compares it with hysteresis against a pie-determined tnp-point. The tnp-point is set by a reference voltage ' V RE¥2 - Although not necessary nor required, a pulse-width distortion correction cahbration circuit 36 can be used to take the output from comparator 34 and correct the πsmg or falling edges of the received signal. It is mtended that circuit 36 provide approximately 50% duty cycle to compensate for inaccuracies m the pm diode and LED turn-on and turn-off times. As merely an example, circuit 36 may mclude an even number of inverters connected m seπes. The second inverter withm the seπes can be powered from a differential output of a transconductance amplifier, wherem one mput of that amplifier is connected to a voltage divider, and the other mput is coupled from the output of the seπes-connected inverters. Accordmg to one embodiment, PLL 38 is embodied on the same integrated circuit as the receiver circuits, such as amplifier 32, comparator 34, and calibration circuit 36. Furthermore, the receiver circuits can be embodied on the same, or a dissimilar, monolithic substrate as the digital system. Still further, the receiver circuits can be formed withm a module that is the same as or different from a module which houses the transmitter. PLL 38 takes the data output from circuit 36 and generates a low jitter clock output which can be used to sample the data output from circuit 36. PLL 38 can mclude a phase-frequency detector, low-pass filter, voltage-controlled oscillator, and an output of the voltage-controlled oscillator is fed back to the phase- frequency detector, accordmg to well-known design. The output of the voltage-controlled oscillator is a clockmg signal which may or may not be active, or can be clocked m a protected mode, dependmg on the status of activity withm the commumcation system. Initially, the receiver circuitry (i.e., amplifier 32, comparator 34 and calibration cicuit 36), as well as the PLL is m a low power mode, and the output clockmg signal is maintained m a steady state low value smce there is no activity m the network (i.e., smce an mput signal is not present on the receive port). Once activity m the network is detected, PLL 38 enters normal operation. However, PLL 38 requires a certam amount of time to elapse before it will enter a locked state. When the PLL is unlocked and its frequency is outside, for example, a 5% range of the lockmg frequency, the clock signal output frequency is divided by four. Once the PLL frequency is close to the lockmg frequency, the clock signal output returns to a normal clockmg signal frequency and the lock/unlock conductor bears a valid lock signal mdicated by that conductor yielding a relatively high voltage value. Preferably, the lock signal does not go high until after three valid frames have been detected by PLL 38. Once activity in the network ceases (i.e., the mput signal upon the receive port terminates), the lock signal will go low and the clockmg signal output will also go low. Details regarding the PLL clock status output and lock/unlock output are further descπbed m Fig. 3. Namely, if no light is present (no activity is present) withm the commumcation system, then the PLL outputs will yield an unlock signal and no transitory clockmg values. However, when hght is present and the PLL has yet to lock, the clockmg signal output will be a factor of M (where M may be equal to four) less than the normal clockmg output. Once the PLL is locked and light is still present, then the clockmg signal output will increase to its appropπate frequency which, accordmg to one embodiment, is proportional to the data rate of V m Attributed to receiver 28 is a power supply, or simply a switch to a power supply, shown as reference numeral 40 Power supply 40 responds to a network activity detector 42. It is to be noted that power supply 40 mcludes a generator that produces a selectable power supply output. The output can be current and/or voltage, wherem the current is selectibly supplied to the vaπous receiver components ("receive circuitry"), and voltage may be used to ensure there are no floating nodes or high current paths duπng times when activity is not detected. Detector 42 may mclude a comparator 44 and a timer 46. Comparator 44 is coupled to sense a very small current bemg generated by a pm diode or photosensor, wherem m both instances the pm diode or photosensor compπse mterface 24. Once activity is detected, a low-power oscillator may be used to power up and momtor the output of the comparator. If the output of the comparator still mdicates activity at the pm diode, full power is resumed. In the case of a glitch at the pm diode, comparator 44 will indicate no activity after the oscillator is timed out. Then, the oscillator will power down to save power and the receiver 28 will enter a low power mode. Detector 42 thereby requires a reference voltage V REP , against which the mput voltage V JN will be compared and, if V m exceeds then activity is detected, and timer 46 ensures that the activity must be maintained for a certam timeframe, e.g., 1.0 millisecond., before an activity signal will be present at the timer output The activity signal is fed to power supply 40 to mdicate that power must be applied to items 32, 34, 36, and 38. If the activity signal is not present, then those items remain m their power down state and receiver 28 is said to be in a low power mode. Accordmgly, m the low power mode only detector 42 is powered. The activity signal is also used to enable the data output from circuit 36 and the clockmg signal output from PLL 38. Logic 50 can be used to serve that purpose. Only if activity is detected will the received data be forwarded to the digital system and the high or low speed clockmg signal be sent to the digital system via the clock/status pm. If PLL 38 is unlocked, then the unlocked signal will select output from the divide-by-M output 52. Otherwise, a locked PLL will select the higher speed clockmg output. A multiplexer 54 may serve to perform that select function. Receiver 28 is shown to have four conductors forwarded to the digital system. If the digital system maintains its own ground and power supply, then only two conductors need be presented. The received data (DATA RCV) is processed by the digital system synchronously with transitions of a clockmg signal withm the clock/status conductor Once processmg is complete, then data is returned from the digital system as transmit data (DATA XMT) However, if the digital system is to be bypassed based on the status of the lock/unlock signal, then the received data will be transmitted from the receiver directly back to transmitter 30 as data RCV. In either instance, a dπver 58 is used to present the bypassed received data, or processed transmit data, back upon the commumcation lme. Dπver 58 mcludes, for example, a buffer and/or amplifier necessary to account for voltage and timing differences between the commumcation lme and the digital system. Figs. 4 and 5 illustrate two possible ways m which data can bypass the digital system, or digital signal processor 20. As shown m Fig. 4, a lock detector 60 may be placed withm the digital system to receive data from the transceiver. Accordmg to one embodiment, detector 60 mcludes a decoder 62 and a counter 64. Decoder 62 continuously decodes the data received signal and indicates the occurrence of a pattern that matches a predefined set of valid preambles. Thus, decoder 62 may be designed to decode a specific sequence of binary bits. The sequence being sought is preferably contained withm a set of preambles of the data stream. The preamble contains a coding which is set upon transmission. If codmg changes due to, for example, noise withm the transmission channel or corruption as a result of connector misalignment or detachment, then the binary sequence will change. Decoder 62 is designed to decode a specific set of bits withm the preambles. If that set does not occur for a set peπod of time, possibly indicated by a certam count withm counter 64, then the lock/unlock signal output from counter 64 will mdicate an unlock condition. Counter 64 is a modulo N counter where N clock cycles is the time between preambles. If a valid preamble is detected after N clock cycles, decoder 62 indicates one valid preamble has been detected. Otherwise, it mdicates than an invalid preamble has been detected. A preamble decoded after fewer than N clock cycles will reset the counter 64 to re-synchromze it agam. When, for example, three valid preambles have been detected correctly, lock is declared. A multiplexer 66 receives the lock unlock signal at a select mput of the multiplexer to choose between whether the DSP output (i.e., data XMT) will be forwarded to the transceiver or whether the data at the output of the receiver (i.e., data RCV) will be sent. Fig. 5 recognizes that an unlock condition is commensurate with a frequency vaπation of the mput signal caused by noise or corruption as read by the photodetector. That amount of noise or corruption and associated vaπation m the frequency can be recognized by a frequency detector 70. More importantly, frequency detector 70 can be positioned merely to read changes m frequency of the clock/status signal. If the frequency is steady state indicating no hght is received, or if the frequency is rather low and therefore outside the detected range, then it is noted that the PLL is either not powered or unlocked. However, if the frequency falls withm a pre-defined range, then detector 70 will produce a lock signal forwarded to multiplexer 72. Multiplexer 72 will then perform the same function as multiplexer 66, shown m Fig 4. It is important to note that Figs. 4 and 5 illustrate only two of possibly many alternate ways to mdicate bypass of data if the activity withm the network is unstable. This may come m the form of the PLL 38 (Fig. 2) bemg unlocked, or an improper bmary code bemg sent with the data. In either instance, a resulting unlock signal will allow received data withm one node to be sent to a subsequent node, and so forth, to all nodes withm the commumcation system, thereby beneficially providing a signal to which each transceiver PLL can eventually lock upon rather quickly, and m parallel with one another. In this fashion, each transceiver will be more quickly prepared to forward a normal clockmg signal to its associated digital system for rapid processmg of that received data. It would be appreciated by those skilled m the art havmg the benefit of this disclosure, that this invention is believed to be capable of applications mvolvmg commumcation of signals across a network of mterconnected digital systems, regardless of whether the network is employed withm an automobile or a commumcation system employs an optical fiber. Vaπous modifications and changes may be made to each and every component of the commumcation system or transceiver, all of which would be obvious to a person skilled m the art after havmg the benefit of reviewing this disclosure. It is mtended that the following claims be interpreted to embrace all such modifications and changes and, accordingly, the specification and drawings are to be regarded m an illustrative rather than a restπctive sense.

Claims: WHAT IS CLAIMED IS: 1. A commumcation system, compπsmg a plurality of digital systems mterconnected by respective transceivers to a commumcation lme, wherem at least one of the transceivers compπses a receiver adapted to enter a relatively high power consumptive state from a relatively low power consumptive state duπng times when a signal is present withm the commumcation lme, and wherem said receiver is further adapted to enter said relatively low power consumptive state from the relatively high power consumptive state duπng times when the signal is absent from the communication lme. 2 The commumcation system as recited m claim 1, wherem said commumcation lme compπses an optical fiber. 3 The communication system as recited m claim 2, wherem the receiver compπses a photodetector arranged m proximity to the optical fiber. 4 The communication system as recited m claim 1, wherem said digital system compπses a digital signal processor 5. The communication system as recited in claim 1, wherem said receiver enters said relatively high power consumptive state when the signal is forwarded to the receiver via the commumcation lme. 6. The communication system as recited m claim 1, wherem the receiver compπses a phase-locked loop (PLL) which produces a clockmg signal and forwards the clockmg signal to a respective digital system when the PLL is locked m sync with transitions of the signal. 7 The communication system as recited m claim 1 , wherem the receiver compπses a phase-locked loop (PLL) which produces a clockmg signal at a reduced clockmg frequency and forwards the clockmg signal to a respective digital system when the PLL is not locked m sync with transitions of the signal. 8. The communication system as recited m claim 7, further compπsmg a lock detector which bypasses forwarding the signal to the digital system, and forwards the signal directly to a transmitter of the transceiver, when the PLL is not locked m sync with transitions of the signal. 9. The commumcation system as recited m claim 8, wherem the lock detector is embodied withm the digital system. 10. The communication system as recited m claim 1, wherem at least a portion of each of the transceivers is embodied upon a smgle monolithic substrate dissimilar from the digital systems. 11 The commumcation system as recited m claim 1, wherem a connection between one of the plurality of digital systems and a respective transceiver consists of a power supply conductor, a ground conductor, a clockmg signal conductor, a receive data conductor and a transmit data conductor. 12. The commumcation system as recited m claim 1, wherem a connection between one of the plurality of digital systems and a respective transceiver compπses a clock/status conductor adapted to transmit a signal indicative of the presence or absence of the signal withm the commumcation lme. 13. The commumcation system as recited m claim 1, wherem a connection between one of the plurality of digital systems and a respective transceiver compπses a clock/status conductor adapted to transmit a signal indicative of the frequency at which the signal transitions withm the commumcation lme. 14 The commumcation system as recited m claim 1 , wherem the plurality of digital system are mterconnected m a πng topology. 15. An apparatus, compπsmg : a receive port; receive circuitry coupled to the receive port; an activity detector coupled to the receive port for producmg an activity signal duπng times when an mput signal is forwarded to the receive port; and a power supply generator coupled to the activity detector for producmg a power supply output to the receive circuitry duπng times when the activity detector is producmg the activity signal. 16. The apparatus as recited m claim 15, wherem the receive circuitry compπses a sensmg circuit for sensmg the mput signal. 17. The apparatus as recited m claim 15, further compπsmg a phase-locked loop (PLL) coupled to the power supply generator for producmg a clockmg signal from the mput signal duπng times when the power supply output is produced. 18. The apparatus as recited m claim 15, wherem the activity detector compπses: a comparator havmg a parr of comparator inputs and a comparator output, wherem one of the parr of comparator inputs is coupled to the receive port and another of the pair of comparator inputs is coupled to a first reference voltage; and a timer coupled to the comparator output for producmg the activity signal if a magnitude of the mput signal upon the receive port exceeds the first reference voltage for a defined amount of time. 19. The apparatus as recited m claim 15, wherem the PLL is adapted to produce a lock signal whenever the clockmg signal is synchronized with transitions of the mput signal. 20. The apparatus as recited m claim 15, wherem the PLL is adapted to produce an unlock signal whenever the clock signal is not synchronized with transitions of the mput signal, and wherem the unlock signal is forwarded to a multiplexer coupled to select the mput signal for transmission to a transmitter m heu of an output from a digital system. 21. The apparatus as recited m claim 15, further compπsmg a lock detector coupled to receive the mput signal and produce an unlock signal if the mput signal compπses at least two successive sets of erroneous bmary code or if the mput signal compπses a sequence of bmary bits dissimilar from a pre-defined sequence of bmary bits. 22. The apparatus as recited m claim 15, further compπsmg a lock detector coupled to receive the mput signal and produce an unlock signal if the mput signal transition frequency is outside a pre-defined range. 23. An apparatus, compπsmg: a receiver havmg an output port; a phase-locked loop coupled to receive data presented to the output port; a transmitter havmg an mput port; and a digital system coupled between the receiver and transmitter, wherem the digital system mcludes a lock detector that is operably configured to forward the receive data directly to the transmitter mput port thereby bypassing the digital system duπng times when the phase-locked loop is not locked m sync with the receive data. 24. The apparatus as recited m claim 23, wherem the receiver and transmitter are embodied upon a monolithic substrate separate from the digital system. 25. The apparatus as recited m claim 23, wherem the PLL is embodied upon a monolithic substrate shared by either the receiver or the transmitter. 26. The apparatus as recited m claim 23, wherem the receiver and digital system are connected by no more than four conductors. 27. The apparatus as recited m claim 26, wherem one of said four conductors is adapted to receive a clock/status signal that indicates whether an mput signal is detected by the receiver and/or whether the PLL is locked m sync with the mput signal. 28. The apparatus as recited m claim 23, wherem the receiver and ttansmitter are mterconnected withm a module containing no more than five conductors extending to and coupled with the digital system. 29. The apparatus as recited m claim 28, wherem one of said five conductors is adapted to receive a clock/status signal that mdicates whether an mput signal is detected by the receiver and/or whether the PLL is locked m sync with the mput signal. 30 A method for regulating power consumption withm, and clockmg signal output from, a ttansceiver, compπsmg: while maintaining power needed to detect an mput signal forwarded to the transceiver, deasserting power to a portion of the transceiver and a phase-locked loop (PLL) withm the ttansceiver whenever an mput signal is absent; and producmg a clockmg signal from the PLL by asserting power to the PLL of the transceiver whenever the mput signal is present. 31. The method as recited m claim 30, further compπsmg transmitting the mput signal from a receiver of the ttansceiver directly to a transmitter of the transceiver whenever the clockmg signal is produced yet the PLL output is not synchronized with the mput signal.

Inventors: KNAPP DAVID J, KNAPP, DAVID, J.
Applicants: OASIS DESIGN INC, OASIS DESIGN, INC.
Application year: 2000
Main classification: H04B1
IPC codes: H04B1, H04B10, H04L7, H04L12