Data processing apparatus and integrated circuit

Abstract: With a view to preventing illicit access and reverse engineering, processing apparatus comprises an internal circuit (100) including a CPU (101), internal devices (102 to 105) and a bus line (110) connecting the CPU (101) to the internal devices (102 to 105) and extending externally, and an external circuit (200) including external devices (201 to 203 and 211 to 212) provided externally of an externally extending portion (110a) of the bus line (110). The internal circuit (100) includes a ciphering section (120) provided at an entrance to an external side and ciphering addresses and data on the bus line (110) by ciphering patterns according to a plurality of regions divided from an address space allotted to the entire external devices.

Description: The present invention relates to a processing apparatus comprising an internal circuit having a CPU and internal devices, and an external circuit including external devices provided externally of the internal circuit, and to an integrated circuit incorporating such processing apparatus. With the recent development of LSI, a CPU executing programs, a memory storing the programs executed by the CPU and various other devices have been able to be integrated on one chip, which contributes greatly to making an apparatus small in size, achieving cost reduction and the like. To manufacture such LSI, it suffices to mount a memory storing programs on a LSI chip if a system executes the same programs irrespectively of users and does not need to change programs after completion. However, if it is necessary to execute different programs according to users or to change a program while the program is in use, it is desirable to constitute LSI so that an external memory can be further provided externally of the LSI having the above constitution and to store programs which may be possibly changed while in use or programs which differ according to users in the external memory. Meanwhile, in case of a system capable of adding such an external memory externally of the LSI, however, there is a probability that the content of the external memory is illicitly rewritten or the external memory is replaced by a memory storing an illicit program and having the same specification as that of the external memory, with the result that important programs or data stored in the internal memory are illicitly accessed and the contents of the programs or data are illicitly interpreted. The following is one example of this case. Recently, IC cards and magnetic cards each having a cash value or a point value corresponding to a cash as data is spreading increasingly. Following this, it is of urgent necessity to ensure data security so as to prevent the fabrication or falsification of cards. To this end, methods of preventing the reverse engineering of an apparatus were attempted in the past. Despite these attempts, it is the present situation that illicit ROMs and the like are created and apparatuses are incessantly abused against developers' will. Accordingly, it is desirable to provide a processing apparatus and an integrated circuit intended to prevent illicit access and reverse engineering. In this regard, EP-A-0720098 and US-A-5081675 disclose a processing apparatus comprising: an internal circuit including a CPU executing programs, at least one internal device having a predetermined function and bus line means connecting said CPU to said internal device, extending externally and transferring an address and data; and an external circuit provided externally of an externally extending portion of said bus line means and including at least one external device having a predetermined function, wherein said internal circuit includes a ciphering section interposed at an entrance to an external side and ciphering the address and the data on the bus line means by ciphering patterns according to a plurality of regions divided from an address space allotted to the entirety of said at least one external device. US-A-5515540 and EP-A-1093056 are also of relevance to the problems addressed by the present invention. According to a first aspect of the present invention there is provided a processing apparatus comprising: an internal circuit including a CPU executing programs, at least one internal device having a predetermined function and bus line means connecting said CPU to said internal device, extending externally and transferring an address and data; and an external circuit provided externally of an externally extending portion of said bus line means and including at least one external device having a predetermined function, wherein said internal circuit includes a ciphering section interposed at an entrance to an external side and ciphering the address and the data on the bus line means by ciphering patterns according to a plurality of regions divided from an address space allotted to the entirety of said at least one external device; characterised in that said ciphering section outputs a dummy address and dummy data to the externally extending portion of said bus line means at timing at which said external circuit is not accessed. Since the ciphering section outputs a dummy address and dummy data to the externally extending portion of the bus line at timing at which the external circuit is not accessed, illicit interpretation is made more difficult. Here, the ciphering patterns adopted by the ciphering section include one ciphering pattern in which neither the address nor data is ciphered. As stated above, by dividing the address space into a plurality of areas and ciphering the address and the data by the patterns which differ according to the divided areas, it is made difficult to interpret ciphers. In the first processing apparatus embodying the present invention stated above, it is preferable that the external circuit includes a plurality of external devices; and the ciphering section performs ciphering using ciphering patterns according to the plurality of external devices, respectively. By doing so, it is possible to perform ciphering according to the property of the external device as follows. If a flash ROM is provided as one of the external devices, for example, both the address and the data are ciphered for the flash ROM. As for a RAM, as one of the external devices, which can read continuous addresses at high speed, only the data is ciphered or the addresses are ciphered but the lower bit side of the addresses continuously read are not ciphered. If an I/O device is provided as one of the external devices, neither the address nor data is ciphered. Furthermore, in the processing apparatus embodying the present invention stated above, it is preferable that the CPU is supplied with a clock and executes the programs synchronously with the supplied clock, and the ciphering section is supplied with a clock and performs ciphering synchronously with the supplied clock; and a clock supply section for supplying a clock at a higher speed than a speed of the clock supplied to the CPU, to the ciphering section. This makes complicated ciphering possible. Moreover, in the processing apparatus embodying the present invention, it is preferable that the processing apparatus comprises ciphering pattern determination means for recognizing a constitution of the external circuit and determining a ciphering pattern of the ciphering section according to the constitution of the external circuit. By providing this ciphering pattern determination means, it becomes unnecessary to carry out operations such as the operator's determination of ciphering patterns according to different constitutions of the external circuit. Further, in the processing apparatus embodying the present invention stated above, it is preferable that the ciphering section ciphers the address and the data on the bus line by ciphering patterns according to the plurality of regions divided from the address space allotted to the entirety of the no less than one external device and according to application programs executed by the CPU. This makes ciphering patterns more complicated and illicit interpretation more difficult. Furthermore, in the processing apparatus embodying the present invention stated above, it is preferable that a deciphering section connected to the externally extending portion of the bus line, and returning the ciphered address and the data on the bus line to an address and data which are not ciphered. If debugging is to be performed without providing this deciphering section, the debugging becomes extremely difficult since the address and data are ciphered. Considering this, this deciphering section is provided, thereby making it possible to easily carry out debugging at the time of developing the processing apparatus. This deciphering section becomes unnecessary after the completion of debugging. Therefore, it is preferable that the deciphering section is detached from the processing apparatus, fixed to a disabled state or destroyed. Additionally, in the processing apparatus embodying the present invention stated above, it is preferable that the processing apparatus comprises ciphering pattern change means for changing a ciphering pattern whenever a predetermined initialization operation is carried out for one of the plurality of regions divided from the address space allotted to the entirety of the at least one external device. By resetting the ciphering pattern in a predetermined initialization operation, e.g., when the processing apparatus is powered on or reset and the like, illicit interpretation is made more difficult and security thereby enhances. Also, in the processing apparatus embodying the present invention stated above, it is preferable that the ciphering section adopts a ciphering pattern in which ciphered data is changed according to the address, for one of the plurality of regions divided from the address space allotted to the entirety of the at least one external device, to thereby cipher the data. By adopting the function of addresses as a ciphering function to cipher the data, complicated ciphering is made possible, illicit interpretation is made more difficult and data security thereby enhances. According to a second aspect of the present invention, there is provided an integrated circuit including a processing apparatus in accordance with the first aspect of the present invention. An integrated circuit embodying the present invention has the above constitution and exhibits the same function and advantage as those of the processing apparatus embodying the present invention. In addition, the integrated circuit makes it difficult to interpret the circuit arrangement and the like. In this respect, too, the integrated circuit contributes to enhancing security. Reference will now be made, by way of example, to the accompanying drawings, in which: Fig. 1 is a block diagram of the first embodiment of a processing apparatus according to the present invention; Fig. 2 shows a memory map of the processing apparatus shown in Fig. 1; and Fig. 3 is a flow chart of an initialization program executed when the processing apparatus shown in Fig. 1 is powered on. The embodiments of the present invention will be described hereinafter. Fig. 1 is a block diagram showing an embodiment of a processing apparatus according to the present invention. A processing apparatus 1 shown in Fig. 1 consists of a internal circuit 100 mounted inside of an LSI 10, an external circuit 200 provided externally of the LSI 10 and the others including oscillators 301 and 302 and the like. This LSI 10 corresponds to one embodiment of an integrated circuit of the present invention. The internal circuit 100 provided within the LSI 10 has a central processing unit (CPU) 101 as well as an internal memory 102, a ciphering information register 103, an address decoder 104 and a peripheral circuit 105 which are internal devices according to the present invention. The CPU 101 and the various internal devices are mutually connected through a bus line 110. This bus line consists of an address bus 111 and a data bus 112 and extends externally of the LSI 10. Various external devices are connected to a portion 110a of the bus line 110 which extends externally. The external devices will be described later. The internal circuit 100 constituted within the LSI 10 is provided with a ciphering section 120 interposed at an entrance to an external side. This ciphering section 120 consists of a ciphering circuit 121, a bus interface 122 and a random number generation circuit 123. A clock signal from the oscillator 301 is inputted into the CPU 101. The CPU 101 executes various programs synchronously with the clock signal received from the oscillator 301. A clock signal from another oscillator 302 which generates a clock signal higher in repetition frequency than the clock signal inputted into the CPU 101, is inputted into the ciphering circuit 121. The ciphering circuit 121 conducts a ciphering processing synchronously with the clock signal with a high repetition frequency from the oscillator 302. The detail of the ciphering processing will be described later. The above two oscillators 301 and 302 generate clock signals synchronous with each other. Therefore, the oscillators 301 and 302 may generate clock signals by dividing a high-speed clock obtained by a common oscillation source. Further, a plurality of external devices, i.e., in case of Fig. 1, a liquid crystal display (LCD) 201, a keyboard (KB) 202, a read-only memory (ROM) 203, a flash ROM 211 and a random-access memory (RAM) 212, are connected to the externally extending portion 110a of the bus line 110. In Fig. 1, a device 213 , such as another LSI , which is the same in constitution as the LSI 10 shown in Fig. 1 and which has the same ciphering mechanism as that of the internal circuit 100, and a deciphering circuit 214 for debugging programs operated by the CPU 101 are also connected to the externally extending portion 110a. The device 213 and the deciphering circuit 214 are shown in Fig. 1 for description purposes. The device 213 is connected to the LSI 10 if cipher communication is established between the LSI 10 and the device 213 having a similar constitution to that of the LSI 10. The deciphering circuit 214 is connected for program debugging and detached after the completion of debugging. The LCD 201 and the KB 202 as well as, in case of the embodiment shown in Fig. 1. the ROM 203 belong to external devices which cipher neither addresses nor data. The flash ROM 211 and the RAM, by contrast, belong to external devices which cipher and access addresses or data. Here, the flash ROM 211 ciphers only data and the RAM ciphers both addresses and data. Further, the device 213 ciphers both addresses and data and establishes cipher communication with the LSI 10. When connected to the LSI 10, the deciphering circuit 214 belongs to the devices which cipher neither addresses nor data in this embodiment. Here, the bus line 110 is divided into a portion connected to the CPU 101 (the address and data of which portion are denoted by A1 and D1. respectively), a portion put between the ciphering circuit 121 and the bus interface 122 (the address and data of which portion are denoted by A2 and D2, respectively) and the externally extending portion 110a of the LSI 10 (the address and data of which portion are denoted by A3 and D3, respectively). Fig. 2 shows the memory map of the processing apparatus shown in Fig. 1. A plurality of application programs are stored in the flash ROM which is one of the external devices. OS programs are stored in the internal memory which is one of the internal devices. Also, apparatus constitution information on this processing apparatus, e.g., types of external devices connected and memory capacities are recorded on the ROM which is one of the external devices. Fig. 3 is a flow chart of an initialization program executed when the processing apparatus shown in Fig. 1 is powered on. This initialization program is stored in the internal memory 102 as one of the OS programs and executed by the CPU 101 when power is turned on. According to the initialization program shown in Fig. 3, first, the apparatus constitution information stored in the ROM 203 which is one of the external devices is read (in a step al), a memory map as shown in Fig. 2 is created based on the information and a ciphering pattern is determined for each area of the memory map (in a step a2). It is noted that ciphering patterns include a pattern in which neither addresses nor data are ciphered. In this initialization program, various other initialization processings follow (in a step a3). Description will be continued, with reference back to Fig. 1. The CPU 101 reads and writes information using the address A1 and the data D1. The external devices are accessed using the address A3 and the data D3 irrespectively of whether it is necessary to cipher the devices or not (or it is prohibit the devices from being ciphered). The CPU 101 writes area information on areas to be ciphered (ciphered areas) and a ciphering pattern for each ciphered area on the memory map shown in Fig. 2, in a ciphering information register 103. The address decoder 104 inputs the address A1 and receives the area information indicating to-be-ciphered areas from the ciphering information register 103. Then, the address decoder 104 outputs chip select signals CS0 to CS6 to an access target device and outputs a ciphering control signal Crp, indicating which device is an access target and whether or not it is necessary to conduct ciphering, to the ciphering circuit 121. The ciphering circuit 121 receives the ciphering control signal Crp from the address decoder, conducts ciphering according to the ciphered areas when it is necessary to cipher the address A1 and data D1 based on the ciphering pattern information recorded on the ciphering pattern information register 103, and outputs the address A2 and data D2. The address A2 and data D2 are outputted externally of the LSI 10 as address A3 and data D3 by way of the bus interface 123. An external bus access signal indicating whether an external device is to be accessed is transmitted from the CPU 101 to the bus interface 122. The bus interface 122 outputs the address A2 and data D2 outputted externally from the ciphering circuit 121 as the external address A3 and data D3 when access to the external device is requested, generates a dummy address and dummy data based on the random number from the random number generation circuit 123 and outputs the dummy address and dummy data as the external address A3 and data D3 when access to the external device is not requested. This makes illicit interpretation more difficult. The conversion of addresses and data from internally to externally has been described. As for the data D3 read from the external flash memory 211, RAM 212, ROM 203 and the like is fetched into the internal side as the data D2. If the data is ciphered data, the ciphering circuit 121 deciphers the ciphered data and transmits the data to the CPU 101 and the like as data D1 which is not ciphered. In this embodiment, as the ciphering pattern, a ciphering pattern in which neither addresses nor data are ciphered is adopted. In addition, the following ciphering patterns are adopted: (1) Type 1 A3 = A1 XOR p1 D3 = D1 XOR p1 (2) Type 2 A3 = A1 D3 = A1 + D1 + p1 (3) Type 3 The higher level and lower level of the data as a result of the operation of type 2 are replaced. In above types, reference p1 denotes an appropriate constant obtained by, for example, random numbers; A XOR B signifies performing an exclusive OR operation for bits corresponding to A and B, and A + B signifies an addition operation if A and B are assumed as numeric values. As already described above with reference to Fig. 3, in the initialization operation when power is turned on, the CPU 101 reads the apparatus constitution information stored in the ROM 203 which is one of the external devices, creates a memory map as shown in Fig. 2 and determines a ciphering pattern for each ciphered area. The flash ROM 211 adopts the ciphering pattern of, for example, (2) above in which the address is not ciphered and only the data is ciphered, and the RAM 212 adopts the ciphering pattern of, for example, (1) above in which both the address and the data are ciphered. The RAM 212 adopts the ciphering pattern of type 1 in (1) above. Therefore, if it is assumed that p1 = 0 x 5555 (0 x means that following '5555' is a hexadecimal), both the address and the data become completely different values from the original address and data as A3 (0 x 5455) = A1 (0 x 0100) XOR p1 (0 x 5555) D3 (0 x 5476) = D1 (0 x 0123) XOR p1 (0 x 5555). Further, the flash ROM 211 adopts the ciphering pattern of type 2 in (2) above. Therefore, if it is assumed that p1 = 0×5555, the address has no change and the data becomes a completely different value from the original data as follows: A3 (0 x 0100) = A1 (0 x 0100) D3 (0 x 5778) = A1 (0 x 0100) + D1 (0 x 0123) + p1 (0 x 5555). Here, in ciphering the data, the data is a function of the address A1. Due to this, even if the data is the same, i.e., D1, the ciphered data D3 differs from the original data according to the address A1, thereby further making illicit interpretation difficult and further enhancing security. It is noted that the above description is a calculative example of a ciphering pattern. If an address is to be ciphered, a ciphering algorithm is taken into consideration so that a ciphered address does not overspread the address area of the ciphering target device and does not move to the address area of a device other than the ciphering target device. In addition, even with the same RAM 212, it is possible to change ciphering patterns for accessing the RAM 212 according to application programs executed by the CPU 101. By not only selecting a ciphering pattern according to a memory area (a to-be-accessed external device) but also changing ciphering patterns according to application programs even in the same memory area (same external device), the address and data outputted to the externally extending portion 110a of the bus line 110 are ciphered in a more complicated manner, thereby making illicit interpretation further difficult and further enhancing security. Here, if it is assumed that the CPU 101 and the ciphering circuit 121 operate at the same clocks, the ciphering circuit 121 cannot perform a complex ciphering operation. For example, if the CPU 101 accesses an external device at one-clock intervals, the ciphering circuit 121 is required to complete its ciphering processing within one clock. In case of the type 3 ciphering processing in (3) above, for example, it requires one-clock time to perform the type 2 ciphering in (2) and it further requires one-clock time to exchange the higher level and lower level bits. Namely, it requires a total of two-clock time and it is necessary for the ciphering circuit 121 to complete the ciphering processing within one clock, then the ciphering pattern type 3 in (3) cannot be adopted. In case of the embodiment shown in Fig. 1, the oscillator 302 which generates a higher-speed clock than that of the oscillator 301 which supplies a clock to the CPU 101, is provided and the ciphering circuit 121 operates synchronously with the higher-speed clock supplied from the oscillator 302. Thus, for example, the ciphering pattern of type 3 in (3) above or a more complicated ciphering pattern which requires a plurality of clocks can be adopted. For example, if a clock with 10 MH z is supplied to the CPU 101 and a clock with 100 MH z is supplied to the ciphering circuit 121, the ciphering circuit can perform a ciphering processing using 10 clocks. Moreover, the internal circuit 100 of the processing apparatus shown in Fig. 1 is incorporated into the LSI 10 and address and data ciphered through the ciphering circuit 121 and the bus interface 122 are outputted from the LSI 10. With the address and data as they are, it is quite difficult for the CPU 101 to execute program debugging when developing a product employing this LSI 10. In view of this, a deciphering circuit 214 is connected to the processing circuit shown in Fig. 1. Before debugging, information on a ciphering pattern and a ciphered area having the same content as that written into the ciphered information register 103 from the CPU 101 are written into this deciphering circuit 214. In the following debugging, the deciphering circuit 214 deciphers the ciphered address and data outputted to the externally extending portion 110a of the bus line 110 based on the information on the ciphering pattern and the ciphered area written in advance, and deciphers the address to an address and data which are not ciphered. By doing so, it is possible to monitor the address and data deciphered by the deciphering circuit 214 by using, for example, a measuring instrument and to easily debug programs executed by the CPU 101. If this deciphering circuit 214 is left undetached, the significance of ciphering the address and data with a view to making illicit interpretation difficult is lost. For that reason, the deciphering circuit 214 is constituted as a device different from the processing apparatus and detached therefrom after the completion of debugging. Alternatively, the deciphering circuit 214 may remain attached thereto to be completely disabled. Further, as shown in Fig. 1, the device 213 having the same ciphering mechanism as that of the LSI 10 is connected. If a plurality of LSIs 10 are combined as shown in Fig. 1, it is possible to establish cipher communication among the LSIs on the substrate. In the above-stated embodiment, the circuit incorporated into one LSI is referred to as an internal circuit and a group of devices provided externally of the LSI is referred to as an external circuit. The internal circuit is not necessarily mounted on one LSI. It is also possible, for example, that if a circuit is dispersed and mounted on a plurality of LSIs and the plurality of LSIs are packaged in one integrated circuit package or integrally molded, then the entire circuit dispersed and mounted on these plural LSIs may be referred to as an internal circuit.

Claims: A processing apparatus comprising: an internal circuit (100) including a CPU (101) executing programs, at least one internal device (102-105) having a predetermined function and bus line means (110, 111, 112) connecting said CPU (101) to said internal device (102-105), extending externally and transferring an address and data; and an external circuit (200) provided externally of an externally extending portion (110a) of said bus line means (110, 111, 112) and including at least one external device(301,302) having a predetermined function, wherein said internal circuit (100) includes a ciphering section (120) interposed at an entrance to an external side and ciphering the address and the data on the bus line means (110, 111, 112) by ciphering patterns according to a plurality of regions divided from an address space allotted to the entirety of said at least one external device (200); characterised in that said ciphering section (120) outputs a dummy address and dummy data to the externally extending portion (110a) of said bus line means (110, 111, 112) at timing at which said external circuit (200) is not accessed. A processing apparatus according to claim 1, wherein the ciphering patterns adopted by said ciphering section include one ciphering pattern in which neither the address nor data is ciphered. A processing apparatus according to claim 1, wherein said external circuit (200) includes a plurality of external devices (201, 202, 203, 211, 212); and said ciphering section (120) performs ciphering using ciphering patterns according to said plurality of external devices (201, 202, 203, 211, 212), respectively. A processing apparatus according to claim 1, wherein said CPU (101) is supplied with a clock and executes the programs synchronously with the supplied clock, and said ciphering section (120) is supplied with a clock and performs ciphering synchronously with the supplied clock; and further comprising a clock supply section (302) for supplying a clock at a higher speed than a speed of the clock supplied to said CPU (101), to said ciphering section. A processing apparatus according to claim 1, comprising: ciphering pattern determination means for recognizing a constitution of said external circuit and determining a ciphering pattern of said ciphering section according to the constitution of said external circuit. A processing apparatus according to claim 1, wherein said ciphering section ciphers the address and the data on said bus line means by ciphering patterns according to the plurality of regions divided from the address space allotted to the entirety of said no less than one external device and according to application programs executed by said CPU. A processing apparatus according to claim 1, comprising: a deciphering section connected to the externally extending portion of said bus line means, and returning the ciphered address and the data on the bus line means to an address and data which are not ciphered. A processing apparatus according to claim 1, comprising: ciphering pattern change means for changing a ciphering pattern whenever a predetermined initialisation operation is carried out for one of the plurality of regions divided from the address space allotted to the entirety of said at least one external device. A processing apparatus according to claim 1, wherein said ciphering section adopts a ciphering pattern in which ciphered data is changed according to the address, for one of the plurality of regions divided from the address space allotted to the entirety of said at least one external device, to thereby cipher the data. An integrated circuit including a processing apparatus as claimed in any preceding claim.

Inventors: HASHIMOTO SHIGERU, KAWASAKI YUSUKE, SAKURAI HIROSHI, YAMAMOTO KOKEN, HASHIMOTO, SHIGERU, KAWASAKI, YUSUKE, SAKURAI, HIROSHI, YAMAMOTO, KOKEN, Hashimoto, Shigeru, c/o Fujitsu Limited, Kawasaki, Yusuke, Fujitsu Limited, Sakurai, Hiroshi, c/o Fujitsu Limited, Yamamoto, Koken, c/o Fujitsu Limited
Applicants: FUJITSU LTD, FUJITSU LIMITED
Application year: 2000
Main classification: G06F12
IPC codes: G06F21, G06F12, G06F13