FAST MULTITHREADING FOR CLOSELY COUPLED MULTIPROCESSORS

Abstract: A processor architecture containing multiple closely coupled processors in a form of symmetric multiprocessing system is provide. The special coupling mechanism allows it to speculatively execute multiple threads in parallel very efficiently. Generally, the operating system is responsible for scheduling various threads of execution among the available processors in a multiprocessor system. One problem with parallel multithreading is that the overhead involved in scheduling the threads for execution by the operating system is such that shorter segments of code cannot efficiently take advantage of parallel multithreading. Consequently, potential performance gains from parallel multithreading are not attainable. Additional circuitry is included in a form of symmetrical multiprocessing system which enables the scheduling and speculative execution of multiple threads on multiple processors without the involvement and inherent overhead of the operating system. Advantageously, parallel multithreaded execution is more efficient and performance may be improved.

Description: TITLE: FAST MULTITHREADING FOR CLOSELY COUPLED MULTIPROCESSORS BACKGROUND OF THE INVENTION 1 Technical Field This invention is related to the field of microprocessors and, more particularly, to multithreading m multiprocessors 2 Background Art Computer systems employing multiple processing units hold a promise of economically accommodating performance capabilities that surpass those of current single-processor based systems Within a multiprocessing environment, rather than concentrating all the processing for an application in a smgle processor, tasks are divided into groups or "threads" that can be handled by separate processors The overall processing load is thereby distributed among several processors, and the distributed tasks may be executed simultaneously in parallel The operatmg system software divides various portions of the program code into the separately executable threads, and typically assigns a priority level to each thread Superscalar microprocessors achieve high performance by executing multiple instructions per clock cycle and by choosing the shortest possible clock cycle consistent with the design As used herein, the term "clock cycle" refers to an interval of time accorded to various stages of an instruction processmg pipeline within the microprocessor Storage devices (e g registers and arrays) capture their values according to the clock cycle For example, a storage device may capture a value accordmg to a πsmg or falling edge of a clock signal definmg the clock cycle The storage device then stores the value until the subsequent rising or falling edge of the clock signal, respectively The term "instruction processmg pipeline" is used herein to refer to the logic circuits employed to process instructions in a pipelined fashion Although the pipeline may be divided into any number of stages at which portions of instruction processing are performed, instruction processing generally compπses fetching the instruction, decoding the instruction, executmg the instruction, and storing the execution results in the destination identified by the instruction An important feature of microprocessors is the degree to which they can take advantage of parallelism Parallelism is the execution of instructions in parallel, rather than serially Superscalar processors are able to identify and utilize fine gramed instruction level parallelism by executmg certain instructions in parallel However, this type of parallelism is limited by data dependencies between instructions Further, as mentioned above, computer systems which contain more than one processor may improve performance by dividing the workload presented by the computer processes By identifying higher levels of parallelism, multi-processor computer systems may execute larger segments of code, or threads, m parallel on separate processors Because microprocessors and operatmg systems cannot identify these segments of code which are amenable to parallel multithreaded execution, they are identified by the application code itself Generally, the operatmg system is responsible for schedulmg the various threads of execution among the available processors in a multi-processor system One problem with parallel multithreading is that the overhead involved m schedulmg the threads for execution by the operating system is such that shorter segments of code cannot efficiently take advantage of parallel multithreadmg Consequently, potential performance gams from parallel multithreadmg are not attamable DISCLOSURE OF INVENTION The problems outlmed above are m large part solved by a microprocessor and method as descπbed herein Additional circuitry is mcluded in a form of symmetrical multiprocessing system which enables the schedulmg and speculative execution of multiple threads on multiple processors without the mvolvement and inherent overhead of the operatmg system Advantageously, parallel multithreaded execution is more efficient and performance is unproved Broadly speakmg, a multiprocessor computer is contemplated comprising a plurality of processors, wherem said processors include a register file, a reorder buffer and circuitry to support speculative multithreaded execution In addition, the multiprocessor computer includes one or more reorder buffer tag translation buffers and a thread control device The thread control device is configured to store and transmit instructions between the processors The thread control device and instructions support parallel speculative multithreaded execution In addition, a method is contemplated which comprises performing thread setup for execution of a second thread on a second processor, wherem the setup compπses a first processor conveymg setup instructions to a second processor, where the setup instructions are speculatively executed on the second processor A startup mstruction is conveyed from the first processor to the second processor which begms speculative execution of the second thread on the second processor The second processor beg s speculative execution of the second thread in parallel with the execution of a thread on the first processor, m response to receivmg the startup mstruction Execution of the second thread is terminated, m response to retiring a termination instruction m the second processor Finally, the results of the execution of the second thread are conveyed to the first processor, m response to the second processor receivmg a retrieve result mstruction, where the retrieve result mstruction is speculatively executed by the second processor BRIEF DESCRIPTION OF DRAWINGS Other objects and advantages of the invention will become apparent upon readmg the following detailed description and upon reference to the accompanying drawings in which Fig 1 is a block diagram of one embodiment of a microprocessor Fig 2 is a block diagram of one embodiment of a multiprocessor computer Fig 3A is a diagram showing two microprocessors and a thread control device Fig 3B is a flowchart illustrating thread setup, execution and completion Fig 4 is a diagram showing two microprocessors and a thread control device Fig 5 is a chart showing two threads of instructions and the use of a Sync mstruction Fig 6 shows a synchronous implementation of synchronization logic Fig 7 shows an asynchronous implementation of synchronization logic Fig 8 shows an instruction sequence representing an asynchronous implementation of synchronization logic Fig 9 shows one embodiment of an lnterprocessor communication unit and a thread control device Fig 10 is a block diagram of one embodiment of a computer system including the multiprocessor computer shown in figure 2 While the invention is susceptible to various modifications and alternative forms, specific embodiments thereof are shown by way of example m the drawings and will herem be descπbed in detail It should be understood, however, that the drawings and detailed description thereto are not intended to limit the mvention to the particular form disclosed, but on the contrary, the intention is to cover all modifications, equivalents and alternatives falling within the spirit and scope of the present mvention as defined by the appended claims MODE(S) FOR CARRYING OUT THE INVENTION Processor Overview Turning now to Fig 1, a block diagram of one embodiment of a processor 10 is shown Other embodiments are possible and contemplated As shown m Fig 1, processor 10 mcludes a prefetch/predecode unit 12, a branch prediction unit 14, an mstruction cache 16, an mstruction alignment unit 18, a plurality of decode units 20A-20C, a plurality of reservation stations 22A-22C, a plurality of functional units 24A-24C, a load/store unit 26, a data cache 28, a register file 30, a reorder buffer 32, an MROM unit 34, an mterprocessor communication unit 300, and a bus mterface unit 37 Elements referred to herem with a particular reference number followed by a letter will be collectively referred to by the reference number alone For example, decode units 20A-20C will be collectively referred to as decode units 20 Prefetch/predecode unit 12 is coupled to receive instructions from bus mterface unit 37, and is further coupled to instruction cache 16 and branch prediction unit 14 Similarly, branch prediction unit 14 is coupled to instruction cache 16 Still further, branch prediction unit 14 is coupled to decode units 20 and functional units 24 Instruction cache 16 is further coupled to MROM unit 34 and mstruction alignment unit 18 Instruction alignment unit 18 is m turn coupled to decode units 20 Each decode unit 20A-20C is coupled to load/store unit 26 and to respective reservation stations 22A-22C Reservation stations 22A-22C are further coupled to respective functional units 24A-24C Additionally, decode units 20 and reservation stations 22 are coupled to register file 30 and reorder buffer 32 Functional units 24 are coupled to load/store unit 26, register file 30, and reorder buffer 32 as well Data cache 28 is coupled to load/store unit 26 and to bus mterface unit 37 Bus interface unit 37 is further coupled to an L2 interface to an L2 cache and a bus lnterprocessor communication unit 300 is coupled to reorder buffer 32 and result bus 38 Finally, MROM unit 34 is coupled to decode units 20 Instruction cache 16 is a high speed cache memory provided to store instructions Instructions are fetched from mstruction cache 16 and dispatched to decode umts 20 In one embodiment, mstruction cache 16 is configured to store up to 64 kilobytes of instructions m a 2 way set associative structure havmg 64 byte lmes (a byte compnses 8 binary bits) Alternatively, any other desired configuration and size may be employed For example, it is noted that instruction cache 16 may be implemented as a fully associative, set associative, or direct mapped configuration Instructions are stored into mstruction cache 16 by prefetch predecode unit 12 Instructions may be prefetched prior to the request thereof from instruction cache 16 m accordance with a prefetch scheme A vaπety of prefetch schemes may be employed by prefetch predecode unit 12 As prefetch/predecode unit 12 transfers instructions to mstruction cache 16, prefetch/predecode unit 12 generates three predecode bits for each byte of the instructions, a start bit, an end bit, and a functional bit. The predecode bits form tags indicative of the boundaπes of each mstruction The predecode tags may also convey additional information such as whether a given mstruction can be decoded directly by decode units 20 or whether the mstruction is executed by mvokmg a microcode procedure controlled by MROM unit 34, as will be described m greater detail below Still further, prefetch/predecode unit 12 may be configured to detect branch instructions and to store branch prediction information corresponding to the branch instructions into branch prediction unit 14 Other embodiments may employ any suitable predecode scheme. One encodmg of the predecode tags for an embodiment of processor 10 employing a vaπable byte length instruction set will next be descπbed. A vaπable byte length mstruction set is an mstruction set m which different instructions may occupy diffeπng numbers of bytes. An exemplary variable byte length mstruction set employed by one embodiment of processor 10 is the x86 mstruction set. In the exemplary encodmg, if a given byte is the first byte of an instruction, the start bit for that byte is set. If the byte is the last byte of an instruction, the end bit for that byte is set. Instructions which may be directly decoded by decode units 20 are referred to as "fast path" instructions The remaining x86 instructions are refeπed to as MROM instructions, accordmg to one embodiment. For fast path instructions, the functional bit is set for each prefix byte mcluded in the mstruction, and cleared for other bytes. Alternatively, for MROM instructions, the functional bit is cleared for each prefix byte and set for other bytes. The type of mstruction may be determmed by examining the functional bit corresponding to the end byte. If that functional bit is clear, the mstruction is a fast path mstruction Conversely, if that functional bit is set, the instruction is an MROM instruction The opcode of an mstruction may thereby be located within an mstruction which may be directly decoded by decode units 20 as the byte associated with the first clear functional bit m the mstruction. For example, a fast path mstruction mcludmg two prefix bytes, a Mod R/M byte, and an immediate byte would have start, end, and functional bits as follows' Start bits 10000 Functional bits 1 1000 MROM instructions are instructions which are determmed to be too complex for decode by decode units 20. MROM instructions are executed by mvokmg MROM unit 34 More specifically, when an MROM mstruction is encountered, MROM unit 34 parses and issues the instruction mto a subset of defined fast path instructions to effectuate the desired operation. MROM unit 34 dispatches the subset of fast path instructions to decode units 20 Processor 10 employs branch prediction in order to speculatively fetch instructions subsequent to conditional branch instructions Branch prediction unit 14 is included to perform branch prediction operations In one embodiment, branch prediction unit 14 employs a branch target buffer which caches up to two branch target addresses and corresponding taken/not taken predictions per 16 byte portion of a cache lme m mstruction cache 16. The branch target buffer may, for example, comprise 2048 entries or any other suitable number of entries Prefetch/predecode unit 12 determines initial branch targets when a particular line is predecoded Subsequent updates to the branch targets corresponding to a cache lme may occur due to the execution of instructions within the cache lme Instruction cache 16 provides an indication of the mstruction address being fetched, so that branch prediction unit 14 may determine which branch target addresses to select for forming a branch prediction Decode units 20 and functional units 24 provide update information to branch prediction umt 14 Decode units 20 detect branch instructions which were not predicted by branch prediction unit 14 Functional units 24 execute the branch instructions and determine if the predicted branch direction is incorrect The branch direction may be "taken", m which subsequent instructions are fetched from the target address of the branch instruction Conversely, the branch direction may be "not taken", m which subsequent instructions are fetched from memory locations consecutive to the branch mstruction When a mispredicted branch mstruction is detected, instructions subsequent to the mispredicted branch are discarded from the vaπous units of processor 10 In an alternative configuration, branch prediction unit 14 may be coupled to reorder buffer 32 instead of decode units 20 and functional units 24, and may receive branch misprediction information from reorder buffer 32. A vanety of suitable branch prediction algoπthms may be employed by branch prediction unit 14 Instructions fetched from instruction cache 16 are conveyed to instruction alignment unit 18 As instructions are fetched from mstruction cache 16, the coπesponding predecode data is scanned to provide information to mstruction alignment unit 18 (and to MROM unit 34) regarding the instructions bemg fetched Instruction alignment unit 18 utilizes the scanning data to align an mstruction to each of decode units 20 In one embodiment, mstruction alignment unit 18 aligns instructions from three sets of eight mstruction bytes to decode units 20 Decode unit 20A receives an mstruction which is pπor to instructions concurrently received by decode units 20B and 20C (m program order) Similarly, decode unit 20B receives an mstruction which is pπor to the mstruction concurrently received by decode unit 20C in program order Decode units 20 are configured to decode instructions received from mstruction alignment unit 18 Register operand information is detected and routed to register file 30 and reorder buffer 32 Additionally, if the instructions require one or more memory operations to be performed, decode units 20 dispatch the memory operations to load/store unit 26 Each instruction is decoded into a set of control values for functional units 24, and these control values are dispatched to reservation stations 22 along with operand address information and displacement or immediate data which may be included with the instruction In one particular embodiment, each mstruction is decoded into up to two operations which may be separately executed by functional units 24A-24C Processor 10 supports out of order execution, and thus employs reorder buffer 32 to keep track of the origmal program sequence for register read and wπte operations, to implement register renammg, to allow for speculative instruction execution and branch misprediction recovery, and to facilitate precise exceptions A temporary storage location withm reorder buffer 32 is reserved upon decode of an instruction that mvolves the update of a register to thereby store speculative register states If a branch prediction is mcoπect, the results of speculatively-executed instructions along the mispredicted path can be invalidated in the buffer before they are written to register file 30 Similarly, if a particular instruction causes an exception, instructions subsequent to the particular instruction may be discarded In this manner, exceptions are "precise" (I e instructions subsequent to the particular mstruction causing the exception are not completed pnor to the exception) It is noted that a particular mstruction is speculatively executed if it is executed pπor to instructions which precede the particular instruction in program order Preceding instructions may be a branch instruction or an exception-causing instruction, in which case the speculative results may be discarded by reorder buffer 32 The mstruction control values and immediate or displacement data provided at the outputs of decode units 20 are routed directly to respective reservation stations 22 In one embodiment, each reservation station 22 is capable of holdmg mstruction information (1 e , instruction control values as well as operand values, operand tags and/or immediate data) for up to five pending instructions awaitmg issue to the coπesponding functional unit It is noted that for the embodiment of Fig 1, each reservation station 22 is associated with a dedicated functional unit 24 Accordmgly, three dedicated "issue positions" are formed by reservation stations 22 and functional units 24 In other words, issue position 0 is formed by reservation station 22A and functional unit 24A Instructions aligned and dispatched to reservation station 22A are executed by functional unit 24A Similarly, issue position 1 is formed by reservation station 22B and functional unit 24B, and issue position 2 is formed by reservation station 22C and functional unit 24C Upon decode of a particular mstruction, if a required operand is a register location, register address information is routed to reorder buffer 32 and register file 30 simultaneously In one embodiment, reorder buffer 32 mcludes a future file which receives operand requests from decode units as well Those of skill m the art will appreciate that the x86 register file mcludes eight 32 bit real registers (l e , typically refeπed to as EAX, EBX, ECX, EDX, EBP, ESI, EDI and ESP) In embodiments of processor 10 which employ the x86 processor architecture, register file 30 comprises storage locations for each of the 32 bit real registers Additional storage locations may be included withm register file 30 for use by MROM umt 34 Reorder buffer 32 contams temporary storage locations for results which change the contents of these registers to thereby allow out of order execution A temporary storage location of reorder buffer 32 is reserved for each mstruction which, upon decode, is determmed to modify the contents of one of the real registers Therefore, at various pomts durmg execution of a particular program, reorder buffer 32 may have one or more locations which contam the speculatively executed contents of a given register If following decode of a given instruction it is determmed that reorder buffer 32 has a previous location or locations assigned to a register used as an operand m the given instruction, the reorder buffer 32 forwards to the coπesponding reservation station either 1) the value in the most recently assigned location, or 2) a tag for the most recently assigned location if the value has not yet been produced by the functional unit that will eventually execute the previous mstruction If reorder buffer 32 has a location reserved for a given register, the operand value (or reorder buffer tag) is provided from reorder buffer 32 rather than from register file 30 If there is no location reserved for a required register in reorder buffer 32, the value is taken directly from register file 30 If the operand coπesponds to a memory location, the operand value is provided to the reservation station through load/store unit 26 In one particular embodiment, reorder buffer 32 is configured to store and manipulate concurrently decoded instructions as a unit This configuration will be refeπed to herein as "line-oπented" By manipulating several instructions together, the hardware employed within reorder buffer 32 may be simplified For example, a lme-oπented reorder buffer included in the present embodiment allocates storage sufficient for instruction information pertaining to three instructions (one from each decode unit 20) whenever one or more instructions are issued by decode units 20 By contrast, a vaπable amount of storage is allocated m conventional reorder buffers, dependent upon the number of instructions actually dispatched A comparatively larger number of logic gates may be required to allocate the variable amount of storage When each of the concuπently decoded instructions has executed, the instruction results are stored mto register file 30 simultaneously The storage is then free for allocation to another set of concuπently decoded mstructions Additionally, the amount of control logic circuitry employed per mstruction is reduced because the control logic is amortized over several concuπently decoded mstructions A reorder buffer tag identifying a particular mstruction may be divided mto two fields a lme tag and an offset tag The lme tag identifies the set of concurrently decoded mstructions mcludmg the particular instruction, and the offset tag identifies which mstruction withm the set coπesponds to the particular mstruction It is noted that stormg mstruction results mto register file 30 and freeing the coπesponding storage is refeπed to as "retiring" the mstructions It is further noted that any reorder buffer configuration may be employed m vaπous embodiments of processor 10, mcludmg usmg a future file to store the speculative state of register file 30 As noted earlier, reservation stations 22 store mstructions until the mstructions are executed by the coπesponding functional unit 24 An mstruction is selected for execution if (l) the operands of the mstruction have been provided, and (n) the operands have not yet been provided for mstructions which are withm the same reservation station 22A-22C and which are pπor to the mstruction m program order It is noted that when an instruction is executed by one of the functional units 24, the result of that instruction is passed directly to any reservation stations 22 that are waitmg for that result at the same time the result is passed to update reorder buffer 32 (this technique is commonly refeπed to as "result forwarding") An mstruction may be selected for execution and passed to a functional umt 24A-24C during the clock cycle that the associated result is forwarded Reservation stations 22 route the forwarded result to the functional unit 24 in this case In embodiments m which mstructions may be decoded mto multiple operations to be executed by functional units 24, the operations may be scheduled separately from each other In one embodiment, each of the functional units 24 is configured to perform mteger aπthmetic operations of addition and subtraction, as well as shifts, rotates, logical operations, and branch operations The operations are performed m response to the control values decoded for a particular mstruction by decode units 20 It is noted that a floating point unit (not shown) may also be employed to accommodate floating pomt operations The floating point unit may be operated as a coprocessor, receivmg mstructions from MROM unit 34 or reorder buffer 32 and subsequently communicating with reorder buffer 32 to complete the instructions Additionally, functional units 24 may be configured to perform address generation for load and store memory operations performed by load/store unit 26 In one particular embodiment, each functional unit 24 may compπse an address generation unit for generating addresses and an execute unit for performing the remammg functions The two units may operate mdependently upon different instructions or operations during a clock cycle Each of the functional units 24 also provides information regardmg the execution of conditional branch mstructions to the branch prediction unit 14 If a branch prediction was mcoπect, branch prediction unit 14 flushes mstructions subsequent to the mispredicted branch that have entered the mstruction processing pipeline, and causes fetch of the required mstructions from mstruction cache 16 or mam memory It is noted that m such situations, results of mstructions in the oπgmal program sequence which occur after the mispredicted branch mstruction are discarded, including those which were speculatively executed and temporarily stored m load/store umt 26 and reorder buffer 32 It is further noted that branch execution results may be provided by functional units 24 to reorder buffer 32, which may indicate branch mispredictions to functional units 24 Results produced by functional units 24 are sent to reorder buffer 32 if a register value is being updated, and to load/store unit 26 if the contents of a memory location are changed If the result is to be stored m a register, reorder buffer 32 stores the result m the location reserved for the value of the register when the instruction was decoded A plurality of result buses 38 are included for forwarding of results from functional units 24 and load/store unit 26 Result buses 38 convey the result generated, as well as the reorder buffer tag identifying the instruction being executed Load/store unit 26 provides an interface between functional units 24 and data cache 28 In one embodiment, load/store unit 26 is configured with a first load/store buffer having storage locations for data and address information for pending loads or stores which have not accessed data cache 28 and a second load/store buffer havmg storage locations for data and address mformation for loads and stores which have access data cache 28 For example, the first buffer may compπse 12 locations and the second buffer may compπse 32 locations Decode units 20 arbitrate for access to the load/store unit 26 When the first buffer is full, a decode unit must wait until load/store unit 26 has room for the pendmg load or store request mformation Load/store umt 26 also performs dependency checking for load memory operations agamst pendmg store memory operations to ensure that data coherency is mamtamed A memory operation is a transfer of data between processor 10 and the mam memory subsystem Memory operations may be the result of an instruction which utilizes an operand stored m memory, or may be the result of a load/store instruction which causes the data transfer but no other operation Additionally, load/store unit 26 may include a special register storage for special registers such as the segment registers and other registers related to the address translation mechanism defined by the x86 processor architecture Data cache 28 is a high speed cache memory provided to temporarily store data bemg transfeπed between load/store unit 26 and the mam memory subsystem In one embodiment, data cache 28 has a capacity of stormg up to 64 kilobytes of data m an two way set associative structure It is understood that data cache 28 may be implemented m a vanety of specific memory configurations, mcludmg a set associative configuration, a fully associative configuration, a direct-mapped configuration, and any suitable size of any other configuration lnterprocessor communication unit 300 provides an interface for communicating with another processor in a multithreaded multiprocessor configuration In one embodiment, mterprocessor communication unit 300 may include a reservation station for temporarily stormg mstructions to be executed In addition, in one embodiment, mterprocessor communication unit 300 interfaces to a thread control device which facilitates multithread related communications between processors In one particular embodiment of processor 10 employmg the x86 processor architecture, instruction cache 16 and data cache 28 are linearly addressed and physically tagged The lmear address is formed from the offset specified by the instruction and the base address specified by the segment portion of the x86 address translation mechanism Lmear addresses may optionally be translated to physical addresses for accessmg a mam memory The linear to physical translation is specified by the pagmg portion of the x86 address translation mechanism The physical address is compared to the physical tags to determine a hit/miss status Bus mterface unit 37 is configured to communicate between processor 10 and other components m a computer system via a bus For example, the bus may be compatible with the EV-6 bus developed by Digital Equipment Corporation Alternatively, any suitable interconnect structure may be used mcludmg packet-based, unidirectional or bi-directional links, etc An optional L2 cache mterface may be employed as well for interfacmg to a level two cache Symmetπc Multiprocessmg Fig. 2 is a block diagram of one embodiment of a multiprocessor computer 100 mcludmg a plurality of processmg units 12A-12B, a thread control device 300, a bus bπdge 30 and a memory 20. Each processing unit 12A-12B mcludes a processmg core 14A-14B, an LI cache memory 16A-16B, and a bus mterface 18A-18B, respectively The processmg units 12A-12B are coupled to a mam memory 20 via a system bus 22. The multiprocessor computer 100 of fig. 2 is symmetπcal m the sense that all processmg units 12A-12B share the same memory space (i.e , mam memory 20) and access the memory space usmg the same address mappmg The multiprocessmg system 100 is further symmetπcal m the sense that all processmg units 12A-12B share equal access to the same I/O subsystem. In general, a smgle copy of the operatmg system software as well as a smgle copy of each user application file is stored withm mam memory 20. Each processmg unit 12A-12B executes from these smgle copies of the operatmg system and user application files. Although processing cores 14A-14B may be executmg code simultaneously, it is noted that only one of the processmg units 12A-12B may assume mastership of the system bus 22 at a given time Thus, a bus arbitration mechanism, bus bπdge 30, is provided to arbitrate concuπent bus requests of two or more processmg units and to grant mastership to one of the processmg units based on a predetermined arbitration algoπthm. A vanety of bus arbitration techniques are well-known. The high speed cache memory 16A-16B of each processing unit 12A-12B, respectively, stores data most recently accessed by the respective processmg unit along with address tags that mdicate the mam memory address to which the associated data coπesponds. Smce programs tend to execute the same sections of code and access the same data structures repeatedly, many of the locations accessed will already be stored m the cache if the cache is sufficiently large. The cache mechanisms provide two significant benefits First, because the caches are implemented with high-speed memory and can be accessed without bus arbitration and buffer delays, an access to a location stored m a respective cache is much faster than a mam memory access. Second, because an access to a location stored m the respective cache does not require access to the system bus, the bus utilization of each processor is greatly reduced. The system bus is therefore available to service other requested transactions. Typically, the higher the "hit rate", the better the overall system performance The hit rate is the percentage of accesses by a particular processing core that are to locations already stored in the cache Well designed systems with moderately large caches can achieve hit rates of over ninety percent. An important consideration with respect to multiprocessmg systems that employ cache memories is data coherency Smce multiple copies of the data (and instructions) stored by main memory 20 may concuπently reside in one or more of the cache memories 16A-16B, a specialized mechanism must be employed to maintain the integrity of data m the event that one of the memory subsystems is updated (I e., written with new data). For example, consider a situation wherem a particular section of data is updated withm cache memory 16A by processing core 14A but is not updated within the coπespondmg section of mam memory 20. If processmg core 14B subsequently accesses the same section of code, there must be some reliable mechanism to track which section is up-to-date and which section is no longer valid to ensure that processing core 14B accesses the proper data A vanety of techniques have therefore been developed with the goal of efficiently mamtammg cache coherency, mcludmg those based on so-called wπte-through and wnte-back techniques Various cache coherency techniques are descπbed withm a host of publications of the known prior art, and are not discussed further herem General Operation Figs 3A and 3B illustrate the general operation of multithreaded multiprocessmg In fig 3A, interconnection between two processors 12A-12B and a thread control device 300 is shown Fig 3B is a flowchart illustrating the general operation of the multiprocessor computer shown in fig 3A Each processor 12A-12B mcludes a processmg core 14A-14B, an LI cache 16A-16B, and an mterprocessor communication unit (heremafter ICU) 320A-320B Also shown is thread control device 300 which mcludes first-in- first-out (hereinafter FIFO) buffers 310A-310B, and synchronization logic 314 The ICUs 320 of each processor 12 are coupled to thread control device 300 which facilitates communication between processors 12A and 12B In general, one processor 12A serves as master and the other processor 12B serves as slave The master processor 12A runs all smgle threaded code, sets up and starts thread execution on the slave processor 12B and consolidates execution results followmg thread execution In general, processmg core 14A executes smgle threaded code (block 330) until a multithread setup mstruction is encountered When processmg core 12A encounters a multithread setup mstruction (block 332), processing core 12A conveys thread setup mstructions to ICU 320A which conveys them to FIFO 1 310A ICU 320B retrieves mstructions from FIFO 1 310A and transfers them to processmg core 14B Subsequently, master processor 12A conveys a thread 2 startup mstruction (block 334) to ICU 320A which places the instruction mto FIFO 1 310A ICU 320B retneves the thread startup mstruction from FIFO 1 310A and transfers it to processmg core 14B Processmg core 14B then begms fetchmg and executmg the thread 2 code (block 338) Upon execution and retirement of a JOIN instruction (blocks 340 and 342) by both processors 12, slave processor 12B terminates execution of thread 2 and single threaded execution resumes with master processor 12A Master processor 12A may then convey another instruction to processor 12B which causes slave processor 12B to convey thread 2 execution results to master processor 12A via FIFO 310B Master processor 12A may then consolidate execution results from the separate threads (block 344) and continue normal execution (block 346) To summarize, master processor 12 A sets up a second thread for execution on slave processor 12B Both the master 12A and slave 12B processors execute threads in parallel Master processor 12A then obtams the second thread execution results from the slave processor Detailed Descπption of Operation Fig 4 shows one embodiment of a multithreaded multiprocessor Included in Fig 4 are portions of processors 12A and 12B, thread control device 300, and bus 22 Processors 12 mclude an ICU 320, register file 30, reorder buffer 32, system bus 38 and bus mterface unit 37 In addition, ICU 320 includes a reservation station 402 and a reorder buffer tag translation buffer (heremafter RTB) 400 Thread control device 300 mcludes two FIFOs 310 and synchronization logic 314 ICUs 320 are coupled to reorder buffer 32 and system bus 38 Register file 30 and bus interface unit 37 are coupled to bus 22 Bus mterface unit 37 is also coupled to bus 22 Thread control device 300 is coupled to ICU 320 In one embodiment of the multithreaded multiprocessor shown m Fig. 4, the five followmg mstructions are used for the control of threads: Wr2Proc, RdFrProc, Fork, Jom, Sync. Table 1 below gives a bnef descπption of the purpose of each instruction. Table 1 - Thread Control Instructions Bπefly, master processor 12A sets up a second thread for execution by conveymg Wr2Proc mstructions to slave processor 12B. Wr2Proc mstructions move data from the register file of the master processor to the slave processor To start execution of the second thread, the Fork instruction is used When the master processor 12A conveys a Fork mstruction to slave processor 12B, slave processor 12B places the Fork mstruction in its reorder buffer 32B and begms fetchmg the mstructions for the second thread from the thread address conveyed with the Fork mstruction. Execution of the second thread terminates upon execution of a Jom mstruction. The ability to speculatively execute thread mstructions is important as is discussed below. Support for speculative execution is discussed next, followed by a more detailed discussion of the overall mechanism of thread setup and execution. Support for Speculative Thread Execution State of the art superscalar processors have large mstruction windows. Consequently, to wait for a Fork instruction to retire before thread startup may result m significant delays To allow optimal thread startup, the mechanism should allow for speculative startup of threads This allows the second thread to startup and execute m the slave processor long before the Fork mstruction retires m the master processor. Advantageously, performance of the multithreaded multiprocessor is improved To support speculative thread execution, a reorder buffer tag translation buffer (RTB) 400 is mcluded m each processor 12 which maps the location of an instruction in one processor reorder buffer to the location of the same mstruction m another processor reorder buffer. In one embodiment, the RTB 400 has the same number of entires as the reorder buffer 32. The RTB is addressed with the reorder buffer 32 tag of a first processor and the addressed entry of the RTB 400 contams the coπespondmg reorder buffer tag 32 of the second processor. To enable speculative startup and execution of threads, the Wr2Proc and Fork mstructions are processed speculatively. When Wr2Proc and Fork are dispatched to the master processor ICU 320A, they are also sent to the slave processor 12B via FIFO 1 310A. Two possibilities may exist when the Wr2Proc mstruction is dispatched to the master ICU 320A- data is available or data is not available. If data is available, the mstruction, reorder buffer 32A tag of the mstruction, and an "add mstruction" are sent to the slave processor. The mstruction and data are inserted mto the reorder buffer 32B of the slave processor and the entry is marked as havmg valid data. In addition, the RTB 400B of the slave is updated to mdicate the coπespondence between the reorder buffer 32A entry and the reorder buffer 32B entry If data is not available upon dispatch to the master processor ICU 320A, the mstructions remam in the ICU reservation station 402A of the master processor ICU 320A until data is available. However, the mstruction is still sent to the slave processor 12B. The mstructions are inserted mto the reorder buffer 32B of the slave processor, the entries m the slave processor reorder buffer 32B are marked as not havmg valid data, and the RTB 400B is updated as descπbed above Instructions m slave processor reorder buffer 32B that are marked as not havmg valid data may not execute until data is available When data becomes available for an mstruction waiting m the reservation station 402 A of the master processor 12 A, the instruction is removed from the reservation station 402 A of the master processor 12A and issues to ICU 320A When the ICU 320A receives the mstruction, the data and the reorder buffer 32A tag of the master processor, along with a "data update" command are sent to the slave processor 12B. The slave processor 12B translates the reorder buffer 32A tag usmg the RTB 400B to identify the tag of the mstruction m the slave processor 12B reorder buffer 32B. The coπespondmg reorder buffer 32B tag is then used to insert the data mto the coπect reorder buffer 32B entry. The instruction in the slave processor reorder buffer 32B is now marked as having valid data and dependent instructions m slave processor 12B may issue Thread Setup and Thread Startup To setup a second thread for execution on another processor, master processor 12A conveys speculative Wr2Proc instructions to slave processor 12B via FIFO 1 310A In addition to the Wr2Proc instruction, master processor 12A conveys the reorder buffer 32A tag of the mstruction to slave processor 12B. The mstructions are placed mto the reorder buffer 32B of the slave processor If the data for the Wr2Proc mstruction is available, it is placed in reorder buffer 32B as well. Otherwise, the reorder buffer 32B entry is marked as not havmg valid data In parallel, the RTB 400B of the slave processor is updated by placing the tag of the slave processor reorder buffer 32B m the location indexed by the tag of the master processor reorder buffer 32A. If the reorder buffer 32B of the slave processor 12B is full, no instructions will be received from the master processor 12A When space is available in slave processor reorder buffer 12B, master processor 12A receives an mdication and pendmg mstructions may be sent After setup of the second thread is complete, the Fork instruction is used to start execution of the second thread When a Fork instruction is encountered by the master processor, it is sent to the slave processor 12B via thread control device 300 as described above If the slave processor 12B is already running a thread, the Fork instruction is ignored An mdication is made by the slave processor 12B as to the success of the Fork operation Such an mdication may be made by vaπous means, such as setting an ordinary processor flag which may be checked by the master processor 12A Other embodiments may use other means to ensure an attempt to start a second thread is not made while another thread is already is running, eliminating the need for setting and checkmg of flags If the slave processor 12B is not already running a thread, the Fork mstruction is placed m reorder buffer 32B and the slave processor begms fetchmg mstructions for the second thread The newly fetched thread instructions are placed m reorder buffer 32B behmd the Fork mstruction and are dispatched to the processor functional units for execution Those instructions which have no outstandmg dependencies on the Wr2Proc mstructions may issue Advantageously, many nondependent instructions may issue in the slave processor 12B before the Fork mstruction has retired m the master processor 12A The mechanism of executing the thread mstructions after the Fork mstruction m the slave processor 12B is identical to a regular superscalar processor Branch Misprediction and Coπection When a branch misprediction is detected m the master processor 12A, all entnes in the reorder buffer 32A followmg the branch are invalidated If Wr2Proc or Fork mstructions were mispredicted, these need to be invalidated in the slave processor 12B as well When master processor 12A invalidates entnes in reorder buffer 32A followmg a mispredicted branch, it detects the first Wr2Proc or Fork mstruction followmg the mispredicted branch and sends the reorder buffer 32 A tag of that mstruction along with an invalidation request to the ICU 320A This tag and request are then conveyed to the slave processor 12B where the master processor reorder buffer 32A tag is translated by the RTB 400B to obtam the reorder buffer 32B tag of the slave processor 12B The resultmg reorder buffer 32B tag is then used to invalidate that entry and all followmg entnes m the reorder buffer 32B If a Fork mstruction is encountered dunng invalidation of mstructions m reorder buffer 32B, speculative execution m slave processor 12B stops Ending Second Thread Execution and Retirement The end of the second thread executmg on the slave processor 12B is indicated by a Jom mstruction A Join mstruction is also used in the thread running on the master processor 12A When both the master and slave processors 12 have retired the Jom mstruction, the slave processor 12B stops executmg and execution contmues only in the master processor 12A When a slave processor 12B retires a Jom mstruction, it signals this retirement to the master processor 12A and its reorder buffer 32B is cleared The slave processor 12B then stops execution and waits for the next Fork mstruction When the master processor 12A has received an indication that the slave processor 12B has retired the Join instruction, the master processor 12A marks its Jom mstruction as completed and ready to retire Once both processors 12 have retired the Join instruction, the master processor 12A may access the register file 30B of the slave processor 12B to obtain the execution results of the second thread Access to the slave register file 30B is obtained by use of the RdFrProc instruction The RdFrProc mstruction is dispatched by the master processor 12A to the ICU 320A where it waits in the reservation station 402A until it is at the front and then it is issued The RdFrProc command is then sent to the slave processor 12B Execution of the RdFrProc command m the slave processor 12B reads the contents of the specified register and conveys the results back to the master processor 12A via FIFO 2 310B. The RdFrProc command in the master processor, which is still m the execute phase, retrieves the result and places it on the result bus 38A Normal instruction execution then continues The RdFrProc mstruction may issue before the Join instruction retires, but may not retire until after the Jom instruction retires Because synchronization is not performed prior to a RdFrProc mstruction, a Join instruction must precede that mstruction m both the master and slave threads If a mispredicted branch occurs and RdFrProc instructions are mispredicted, the instruction may still receive the data but the result is discarded by the master processor reorder buffer 32A Advantageously, the above mechanism enables speculative execution of the RdFrProc instruction. Retiring Wr2Proc and Fork Instructions When a Wr2Proc or Fork mstruction retires in the master processor reorder buffer 32A, the reorder buffer 32A tag is sent to the slave processor where it is translated by RTB 400B to the reorder buffer 32B tag of the slave processor. Those mstructions which have retired m the master processor 12A may then be retired from the slave processor 12B as well The retirement of Wr2Proc and Fork instructions may be handled in a vanety of ways One method mvolves a retirement command and the second mvolves a Fork commit command In order to implement branch misprediction recovery as descπbed above, the Wr2Proc and Fork command cannot retire in the slave processor reorder buffer 32B until they have retired m the master processor reorder buffer 32A Consequently, reorder buffer 32A must notify reorder buffer 32B when such a retirement occurs. One way of makmg this notification is to send a retire command along with the reorder buffer 32 A tag to the slave processor 12B whenever a Wr2Proc or Fork mstruction retires m the master reorder buffer 32A The master reorder buffer 32A tag is then translated by RTB 400B m the slave processor 12B to obtain the slave reorder buffer 32B tag The resultmg slave reorder buffer 32B tag is then used to retire the coπespondmg instruction While this method creates additional retirement traffic to slave reorder buffer 32B, the operation of this method is advantageously transparent to software, unlike the followmg method A second method of handling the retirement of Wr2Proc and Fork mstructions involves the use of a Fork commit command. When a Fork instruction is retired in the master reorder buffer 32A, the reorder buffer 32A indicates to the ICU 320A that a Fork mstruction has been retired along with the coπespondmg reorder buffer 32A tag The ICU 320A then sends a Fork commit command and the reorder buffer 32A tag to the slave processor 12B. The reorder buffer 32 A tag is then translated by RTB 400B to obtam the coπesponding reorder buffer 32B tag. The resultmg reorder buffer 32B tag is then used to mark the coπespondmg entry as completed and ready to retire. Also, all previous Wr2Proc mstructions m slave reorder buffer 32B are marked completed and can now retire When usmg this second method, there is a special case to consider If for some reason Wr2Proc instructions are not followed by a Fork instruction, they may not be marked as complete and may remain in the reorder buffer 32B. Subsequent thread setups by the master processor 12A may write more Wr2Proc instructions With each setup, less space is available in the slave reorder buffer 32B This process may contmue and ultimately result m an overflow of the slave reorder buffer 32B To avoid this condition, the software is required to keep track of the available size of the slave reorder buffer 32B. Even though this second method may produce less traffic than the first method descnbed above, requrπng the software to contmuously track the available space m the slave reorder buffer 32B is undesirable. Consequently, the first method described above which utilizes a retirement command and is transparent to software is prefeπed. In one embodiment, the ICU 320 may accept multiple instructions per cycle. Reservation station 402 may accommodate multiple mstructions, with the position of the mstructions within reservation station 402 mdicatmg the order in which they are to be sent to the other processor. In addition, multiple instructions may be conveyed at once to the other processor. Overall, it must be ensured that the mstructions are inserted in-order in the reorder buffer 32B of the other processor. Synchronization of Threads Synchronization usmg Sync Instruction There are times dunng execution of parallel threads when it may be desirable to get the threads mto a determmable state. For example, if data must be exchanged between threads there needs to be a mechanism for synchronizing the execution of the threads. To enable synchronization, in one embodiment a Sync mstruction and synchronization logic may be used. The synchronization mechanism used depends on the characteπstics of the system. If all processors m the system have the same latencies and phases, then a highly synchronous implementation may be used. Otherwise a more flexible implementation may be used. In either case, the mechanism is transparent to the software. The same synchronization code may be used for either implementation. Fig. 5 illustrates how a Sync mstruction may be used to synchronize threads. Fig. 5 mcludes two columns, each representing a thread of mstructions. The first column represents a thread of code running on a master processor and the second column represents a thread of code running on a slave processor. Each column m Fig. 5 is divided into rows with each cell representmg a single mstruction. Instruction 500 represents a label which may serve as a branch entry pomt from elsewhere m the code. The operation of the threads is as follows Thread 1 code executes in parallel with thread 2 code. Thread 1 executes until it reaches the first Sync 502 instruction. Thread 2 code executes the mov instruction 510 which moves the Handle data to regl. Thread 2 then contmues execution to Sync instruction 512 When both threads have reached the first Sync mstruction, 502 and 512 respectively, the Sync mstructions may be retired. When both Sync instructions have exited the synchronization point (retired) execution contmues. Thread 1 executes instruction 504 which reads the data from regl of processor 2 mto regO of its register file. Both threads reach a second synchronization pomt at Sync instructions 506 and 514 When Sync mstructions 506 and 514 are both ready to retire, both are retired and execution continues. Thread 1 then executes a compare mstruction 507 and if they are not identical, the jump mstruction 508 causes execution to continue with mstruction 500 Otherwise, execution of thread 1 contmues wifh other code. As the above example shows, a Sync mstruction may not be retired until all processors are ready to retire their coπespondmg Sync mstructions. This requires that each processor indicate when it is ready to retire a Sync instruction and each processor must know when all other processors have reached the synchronization pomt. Fig. 6 shows a block diagram of a synchronous mechanism to implement the synchronization logic. Shown are synchronization logic 314, SSO signals 600, and SSI signal 602. SSO signals 600 are output from CPUs 1-x and mput to synchronization logic 314. Synchronization logic 314 outputs signal SSI 602. In the synchronous implementation shown in Fig. 6, each processor is connected to synchronization logic 314 with 2 signals: a Sync State Out (SSO) signal 600 and a Sync Signal In (SSI) 602. Each processor outputs an SSO signal 600 to mdicate the state of the Sync mstructions to the synchronization logic 314. In addition, each processor receives SSI signal 602 as input to detect the status of the Sync instructions m other processors. In one embodiment, the state of the SSO signal 600 is descnbed by the followmg table Table 2 Sync mstructions are handled specially by the reorder buffers. In the synchronous implementation, if a Sync mstruction is next to retire, then the SSO signal 600 of that processor is set to state 1 to mdicate to all other processors that it has entered the synchronization pomt. When all SSO signals 600 mput to synchronization logic 314 are set to state 1, synchronization logic 314 sets the SSI signal 602 to state 1. Only when the SSI signal 602 mput to a processor is set to state 1 may that processor retire its Sync mstruction. In this manner, all processors retire their Sync instructions at the same time. When a processor retires a Sync mstruction, its SSO signal 600 is set to state 0 on the following clock cycle to mdicate it has exited the synchronization pomt. The second clock cycle followmg retirement, the SSO signal 600 may be set to state 1 again if a Sync mstruction is ready to retire. In the synchronous implementation, synchronization logic 314 may consist of an AND gate, with all SSO signals 600 as inputs and the SSI signal 602 as output. The synchronous implementation provides the fastest synchronization mechanism. However, it can only be used if the processors operate m a cycle by cycle synchronous manner If synchronous operation between the processors is not guaranteed, an asynchronous implementation of synchronization logic 314 may be used. Fig. 7 is a block diagram illustrating an asynchronous implementation Fig. 7 shows synchronization logic 314, SSO signals 700 input to synchronization logic 314, and SSI signal 702 output from synchronization logic 314. In the asynchronous implementation, each processor includes a two bit SSO signal 700 to indicate the state of its Sync instruction. As m the synchronous implementation, synchronization logic 314 outputs an SSI signal 702 to each processor In one embodiment, the state of the SSO signal 700 may be descπbed by the followmg table. Table 3 As in the synchronous implementation, Sync mstructions are handled specially by the reorder buffers 32 In the asynchronous implementation, if a Sync mstruction is next to retire, then the SSO signal of that processor is set to state 1 to mdicate to the other processors that it is ready to retire its Sync mstruction. When all SSO signals 700 mput to synchronization logic 314 are set to state 1, synchronization logic 314 sets the SSI signal 702 to state 1 Only when the SSI signal 702 mput to a processor is set to state 1 may that processor retire its Sync mstruction. In this manner, all processors retire their Sync mstructions at the same tune. When a Sync mstruction is retired, the SSO signal 700 of that processor is set to state 2 to mdicate to the other processors that it is exiting the synchronization pomt. When a processor has exited the synchronization point and set its SSO signal 700 to state 2, it waits until all other processors have exited the synchronization pomt as well. When all processors have set their SSO signals 700 to state 2, SSI signal 702 is set to state 0. All processors may then detect that SSI signal 702 is set to state 0 and contmue execution. After SSI signal 702 has returned to state 0, a processor may then mdicate another Sync mstruction is ready to retire by setting its SSI signal 700 to state 1. The asynchronous implementation of the synchronization logic 314 may be central logic or may be included as part of one of the processors. The synchronization logic 314 implements a small state machme which may work as illustrated by fig. 8. Fig. 8 represents a continuous loop wherem the state of FSMState is continuously checked FSMState represents the state of the Sync signals SSO in the processors Initially, synchronization logic 314 may be in state WAIT ALL S1. While in state WAIT_ALL_S1, signal SSI is set to state 0 If all SSO signals are m state SI, indicating all processors are ready to retire a Sync mstruction, then the next state for FSMState is ALL S1. Otherwise, the next state for FSMState remams WAIT_ALL_S1 Once all SSO signals are in state SI, FSMState transitions to state ALL_S1 and subsequently to state WAIT_ALL_S2. In state WAIT_ALL_S2, the signal SSI is set to state 1 which allows each processor to retire its Sync mstruction. While m state WAIT_ALL_S2, synchronization logic waits for all SSO signals to enter state 2. Once all processors have exited the synchronization pomt, as mdicated by setting their SSO signals to state 2, FSMState transitions to state ALL_S2 and subsequently to state WAIT_ALL_S1 where it sets signal SSI to state 0 This implementation allows the synchronization of processors even if they do not work in lock step While this implementation is more flexible, it has a longer latency than the synchronous implementation descπbed above Synchronization usmg Scratchpad Another way of exchanging data while multiple processors are processmg different threads is to use a scratchpad register space. Fig. 9 shows a block diagram of an ICU 920A and TCD 900 using scratchpad registers 902 for synchronization. In addition to scratchpad registers 902, additional scratchpad instructions (hereafter SCINS) are added which access the scratchpad registers To implement the scratchpad mechanism, scratchpad logic 902 has been added to the TCD. Shown in fig 9 are ICU 902A and TCD 900. ICU 902A mcludes SCINS Read reservation station 930A, SCINS Wnte reservation station 932A, and FIFO reservation station 402A TCD 900 includes FIFOs 310, synchronization logic 314, and scratchpad registers 902. ICU 902A is coupled to TCD 900 The SCINS are locked read-modify-wπte (hereafter R odW) instructions to a scratchpad register location These instructions enable the modification of shared data during parallel thread execution The scratchpad register may be locked on an address by address basis The SCINS are handled by a special functional unit which may be separate from, or included in, ICU 920. The SCINS functional unit mcludes separate reservation stations, 930 and 932, for read and write accesses. All mstructions are issued m order from the scratchpad reservation stations. Any instruction which modifies a scratchpad location with a RmodW operation is a locked mstruction. SCINS are decoded mto multiple operations. At least a locked Read, ALU operation, and a locked Wπte are generated. The mechanism works as follows: 1 A locked RmodW SCINS is decoded. From this decoded instruction, a locked Read and locked Wπte are dispatched to the SCINS functional unit. 2 The locked Read is inserted mto Locked Read reservation station 930A. The locked Write is inserted mto Locked Write reservation station 932A. 3. When all previous reads m Read reservation station 930A have been completed, the locked Read is issued from Read reservation station 930A. Because all RmodW instructions are issued in order, the coπespondmg Wπte mstruction is now also at the front of the Wπte reservation station 932A. 4 The Read now accesses scratchpad register 902. If it is locked, the Read waits until it is unlocked. Then it locks the scratchpad register 902 location, completes its operation and conveys the result to the result bus. However, the Read mstruction is not yet removed from reservation station 930A. 5. All mstructions dependent on the Read may now issue. Once the locked Wπte in Wπte reservation station 932A receives its mput operand it is ready to issue. However, the Write does not issue until the Wπte is next to retire m the reorder buffer 32. This is required, because only non speculative wπtes are allowed. 6. When the Write is next to retire m the reorder buffer 32, the Write is issued from reservation station 932A and wπtes to scratchpad register 902. This wnte updates the data and unlocks the location The SCINS Read and Write mstructions are now removed from reservation stations 930 and 932, respectively. In 6 above, the Read is removed from reservation station 930 if the associated Wπte retires. The Read must remam m the reservation station 930 m order to properly handle branch misprediction. In the case of a mispredicted branch, the mechanism operates as follows- 1 When a mispredicted branch is detected, the entnes following the mispredicted branch m reorder buffer 32 are nullified. 2. Dunng nullification, a SCINS locked mstruction may be detected. This causes reorder buffer 32 to send the reorder buffer tags for the nullified SCINS to the SCINS functional unit together with an invalidate command. If multiple SCINS mstructions are detected, then only the tags of the first instruction after the branch are required. 3 The SCINS functional unit uses the conveyed reorder buffer tag to invalidate all mstructions in reservation stations 930 and 932 beginning with and following the received reorder buffer tag. 4 If the nullification of instructions m Read reservation station 930A hits a Read at the front of the reservation station 930 A which has already been issued, the logic uses the address of the Read mstruction to unlock that location m the scratchpad register 902 The mechanism described above allows a speculatively locked scratchpad location 902 to be unlocked Advantageously, the above mechanism allows the speculative execution of locked reads While the above discussion uses separate Read and Write reservation stations, other implementations may be used and are contemplated However, it must be possible to unlock a location if a locked Read was mispredicted without executmg the mispredicted locked Wπte Computer System Turning now to Fig 10, a block diagram of one embodiment of a computer system 1800 mcludmg multiprocessor computer 100 coupled to a variety of system components through a bus bπdge 1802 is shown Other embodiments are possible and contemplated In the depicted system, a mam memory 1804 is coupled to bus bπdge 1802 through a memory bus 1806, and a graphics controller 1808 is coupled to bus bπdge 1802 through an AGP bus 1810 Finally, a plurality of PCI devices 1812A-1812B are coupled to bus bndge 1802 through a PCI bus 1814 A secondary bus bndge 1816 may further be provided to accommodate an electπcal mterface to one or more EISA or ISA devices 1818 through an EISA/ISA bus 1820 Multiprocessor computer 100 is coupled to bus bridge 1802 through a CPU bus 1824 and to an optional L2 cache 1828 Bus bπdge 1802 provides an interface between multiprocessor computer 100, mam memory 1804, graphics controller 1808, and devices attached to PCI bus 1814 When an operation is received from one of the devices connected to bus bndge 1802, bus bπdge 1802 identifies the target of the operation (e g a particular device or, m the case of PCI bus 1814, that the target is on PCI bus 1814) Bus bndge 1802 routes the operation to the targeted device Bus bndge 1802 generally translates an operation from the protocol used by the source device or bus to the protocol used by the target device or bus In addition to providmg an mterface to an ISA/EISA bus for PCI bus 1814, secondary bus bndge 1816 may further incorporate additional functionality, as desired An input/output controller (not shown), either external from or mtegrated with secondary bus bπdge 1816, may also be included withm computer system 1800 to provide operational support for a keyboard and mouse 1822 and for vaπous serial and parallel ports, as desired An external cache unit (not shown) may further be coupled to CPU bus 1824 between multiprocessor computer 100 and bus bπdge 1802 m other embodiments Alternatively, the external cache may be coupled to bus bridge 1802 and cache control logic for the external cache may be mtegrated mto bus bπdge 1802 L2 cache 1828 is further shown m a backside configuration to processor 10 It is noted that L2 cache 1828 may be separate from multiprocessor computer 100, mtegrated mto a cartndge (e g slot 1 or slot A) with multiprocessor computer 100, or even mtegrated onto a semiconductor substrate with multiprocessor computer 100 Mam memory 1804 is a memory in which application programs are stored and from which multiprocessor computer 100 primarily executes A suitable mam memory 1804 compnses DRAM (Dynamic Random Access Memory) For example, a plurality of banks of SDRAM (Synchronous DRAM) or Rambus DRAM (RDRAM) may be suitable PCI devices 1812A-1812B are illustrative of a vanety of peripheral devices such as, for example, network mterface cards, video accelerators, audio cards, hard or floppy disk drives or dπve controllers, SCSI (Small Computer Systems Interface) adapters and telephony cards Similarly, ISA device 1818 is illustrative of vaπous types of peripheral devices, such as a modem, a sound card, and a variety of data acquisition cards such as GPIB or field bus mterface cards. Graphics controller 1808 is provided to control the rendermg of text and images on a display 1826. Graphics controller 1808 may embody a typical graphics accelerator generally known in the art to render three- dimensional data structures which can be effectively shifted mto and from mam memory 1804. Graphics controller 1808 may therefore be a master of AGP bus 1810 m that it can request and receive access to a target mterface withm bus bndge 1802 to thereby obtam access to mam memory 1804. A dedicated graphics bus accommodates rapid retrieval of data from mam memory 1804 For certain operations, graphics controller 1808 may fuπher be configured to generate PCI protocol transactions on AGP bus 1810 The AGP interface of bus bπdge 1802 may thus mclude functionality to support both AGP protocol transactions as well as PCI protocol target and initiator transactions. Display 1826 is any electronic display upon which an image or text can be presented. A suitable display 1826 mcludes a cathode ray tube ("CRT"), a liquid crystal display ("LCD"), etc. It is noted that, while the AGP, PCI, and ISA or EISA buses have been used as examples m the above descπption, any bus architectures may be substituted as desired It is further noted that computer system 1800 may be a multiprocessmg computer system mcludmg additional multiprocessor computers (e.g multiprocessor computer 10a shown as an optional component of computer system 1800). Multiprocessor computer 10a may be similar to multiprocessor computer 10. More particularly, multiprocessor computer 10a may be an identical copy of multiprocessor computer 10. Multiprocessor computer 10a may be connected to bus bndge 1802 via an independent bus (as shown m Fig. 5) or may share CPU bus 1824 with processor 10. Furthermore, processor 10a may be coupled to an optional L2 cache 1828a similar to L2 cache 1828. It is noted that the present discussion may refer to the assertion of vaπous signals As used herem, a signal is "asserted" if it conveys a value indicative of a particular condition Conversely, a signal is "deasserted" if it conveys a value indicative of a lack of a particular condition A signal may be defined to be asserted when it conveys a logical zero value or, conversely, when it conveys a logical one value Additionally, various values have been descπbed as being discarded m the above discussion A value may be discarded m a number of manners, but generally mvolves modifymg the value such that it is ignored by logic circuitry which receives the value For example, if the value compnses a bit, the logic state of the value may be inverted to discard the value If the value is an n-bit value, one of the n-bit encodings may indicate that the value is invalid Setting the value to the invalid encodmg causes the value to be discarded Additionally, an n-bit value may mclude a valid bit indicative, when set, that the n-bit value is valid. Resetting the valid bit may compπse discardmg the value. Other methods of discardmg a value may be used as well. Numerous vanations and modifications will become apparent to those skilled m the art once the above disclosure is fully appreciated. It is intended that the following claims be interpreted to embrace all such vanations and modifications. INDUSTRIAL APPLICABILITY This invention is applicable to multi-processing computer systems.

Claims: WHAT IS CLAIMED IS: 1. A multiprocessor computer compπsmg. a plurality of processors, wherem said processors mclude a register file, a reorder buffer and circuitry to support speculative multithreaded execution; and a reorder buffer tag translation buffer; and a thread control device, wherein said thread control device is configured to store and transmit mstructions between said processors, wherem said mstructions support the speculative execution of threads on said processors, wherem said threads may be executed m parallel. 2. The multiprocessor computer of claim 1, wherem said circuitry is configured to support synchronization of said execution of said threads. 3 The multiprocessor computer recited in claim 1, wherem said translation buffer compnses a storage buffer, wherem said storage buffer maps an entry in a reorder buffer of a first processor to an entry m a reorder buffer of a second processor. 4. The multiprocessor recited m claim 1, wherem said thread control device is configured to synchronize execution of said threads on said processors. 5. The multiprocessor computer recited in claim 1, wherem a first processor of said plurality of processors is a master, wherem said master executes all smgle threaded code on said multiprocessor computer. 6 The multiprocessor computer of claim 5, further compnsmg a plurality of multithread mstructions, wherem said master conveys data from a register file of said master to a second processor, m response to a first instruction of said plurality of multithread mstructions; and said second processor conveys data from a register file of said second processor to said master, m response to a second mstruction of said plurality of multithread mstructions; and said second processor begms execution of a thread of mstructions, m response to a third instruction of said plurality of multithread instructions; and said second processor ends execution of said thread of mstructions, m response to a fourth mstruction of said plurality of multithread mstructions; and said master and said second processor synchronize thread execution, in response to a fifth mstruction of said plurality of multithread mstructions. The multiprocessor computer of claim 6, wherein said first mstruction, said second instruction and said third mstruction are speculatively executed in said second processor 8 A method compnsmg. performmg thread setup for execution of said thread on a second processor, wherem said setup compnses a first processor conveymg setup mstructions to said second processor, wherem said setup mstructions are speculatively executed on said second processor; and conveymg a startup mstruction from said first processor to said second processor, wherem said startup mstruction is speculatively executed on said second processor; and executing said thread on said second processor, m response to receiving said startup mstruction, wherem said thread is speculatively executed, wherem said thread is executed m parallel with the execution of a thread on said first processor; and terminating said execution of said thread on said second processor, wherem said termination compnses retiring a first termination mstruction m said second processor; and conveymg results of said execution of said thread on said second processor to said first processor, m response to said second processor receivmg a retπeve result mstruction, wherem said retneve result mstruction is speculatively executed by said second processor. 9. The method recited in claim 8, further compnsmg: storing a reorder buffer tag of a reorder buffer m said first processor in said first FIFO, wherein said reorder buffer tag coπesponds to a location in said reorder buffer m said first processor containing said mstruction; and updating a reorder buffer tag translation buffer, wherem said update compnses storing m a location m said buffer a reorder buffer tag of said reorder buffer of said second processor, wherem said reorder buffer tag of said reorder buffer of said second processor coπesponds to a location of said mstruction m said reorder buffer of said second processor, wherein said location m said buffer is selected by said reorder buffer tag of said reorder buffer of said first processor. 10 The method recited in claim 8, further compnsmg synchronizmg said execution of said thread on said first processor with said execution of said thread on said second processor.

Inventors: CHRISTIE DAVID S, KRANICH UWE, CHRISTIE, DAVID, S., KRANICH, UWE
Applicants: ADVANCED MICRO DEVICES INC, ADVANCED MICRO DEVICES, INC.
Application year: 2000
Main classification: G06F9
IPC codes: G06F9, G06F15