CIRCUIT FOR REDUCTION AND OPTIMIZATION OF WRITE-TO-READ SETTLING TIMES IN MAGNETIC MEDIUM STORAGE DEVICES

Abstract: A preamplifier integrated circuit for a magnetic storage device includes a filter (155) in a forward signal path which has a low corner frequency (LCF) which varies in a time dependent manner related to the duration of a write-to-read disturbance induced by a transition from a write mode to a read mode. Favorably, the filter (155) in the forward signal path is formed by a unity gain differential emitter-follower in the forward path and a low pass filter (LPF) in a feedback path around the differential emitter-follower, the pole of the LPF being moved to achieve the movement of the LCF in the forward path. In the steady-state read mode, the filter arrangement also significant reduces DC offset in the read channel. A capacitance in the LPF is variable or made up of several switchable capacitors. The values of the capacitance may be programmed through a serial interface.

Description: Circuit for reduction and optimization of wπte-to-read settling times m magnetic medium storage devices The invention relates generally to devices which read information from a magnetic medium. More particularly, the invention concerns a control circuit to optimize wπte-to-read settling times of such a device. Magnetic recording devices are used to wπte information to a magnetic medium either in analog or digital form. The magnetic medium is typically a tape, such as used m the well known compact cassette or known high density drives for computers which are used for backup purposes. Another common form is a disc, such as a floppy disc or a hard disc for stoπng programs and data in a computer. The read channel for a magnetic recording device includes a sensor m the form of a magneto-resistive head in close proximity with the magnetic medium. When the magnetic mateπal is moved relative to the sensor, a flux is induced in the sensor in dependence of the local oπentation of the magnetic mateπal, thereby generating an information signal which can be amplified and then decoded. When information is wπtten in digital form, such as for computer data storage or digital recording of music, a current is generated by a wπte channel and passed through a thin film head m one direction to wπte a binary "0" and in the opposite direction to wπte a "1". When the medium is read by the sensor, or read head, the portions recorded with a binary "0" will induce a current in the head in the one direction and portions recorded with a binary " 1 " will induce a current in the opposite direction, which is then decoded by a bit detector Hard disk dπves typically include multiple magnetic discs, or platters, each side of which are used for reading and wπting information. The read heads and wπte heads are mounted on arms positioned at each side of the disk, and in modern systems, servo patterns are embedded in radial patterns on the disk. Reading and wntmg are interchanged in conformance with the servo patterns. Wπte-to-read settling time is an important specification because it impacts directly with dπve capacity Wπte-to-read settling time is defined to be the time required for the read channel to settle and be able to read the next servo field after the wπte channel has stopped wπting. The gap on the magnetic disk between the end of the wπte sector and the start of the servo field is wasted area and hence should be minimized. The disturbance to the read channel during wπte-to-read transition comes mainly from three sources. The first source is a flexible cable which is conventionally used to electrically couple the integrated circuit which embodies the read and wπte channel circuitry to the wπte heads and read sensors This cable has multiple conductors in close proximity, which is a source of interference. The circuitry for the write channel and the read channel are typically embodied on a single integrated circuit, referred to in the art as a "preamplifier IC". The preamplifier IC will have several read and wπte channels, grouped in read/wπte pairs for each read/wπte head combination in the device. The close physical proximity of the read channel circuitry and the wπte channel circuitry on the integrated circuit is a source of undesired capacitive coupling between the wπte and read channels. A third source of interference is from the connection pins, bond wires and bond pads on the integrated circuit, which may also be a source of unwanted coupling. The disturbances from each of these sources needs to be suppressed from propagating to the output of the read channel, so as to avoid eπors in decoding the information read from the disc. On the other hand, excess suppression will also interfere with the proper reading of actual data. The exact duration and nature of wπte-to-read disturbances is somewhat unpredictable. It depends on the assembly of the heads, sensors and flexible cable, as well as other sources as descπbed above, and hence vanes between models of hard disk dπves assembled by a manufacturer of such devices. When designing a preamplifier IC, the designer must model the interference sources, based on design data provided by the disk dπve manufacturer as well as past expeπence (if any) with other models of that manufacturer, to design a suitable filter for interference suppression for the read channel After fabricating the preamplifier IC. the IC is tested in the intended hard disk of the manufacturer If there is too little suppression or too much suppression, unacceptable read errors will occur and the designer will have to re-design the filters in the IC, necessitating changes to the mask set for the IC as well as re-fabncation of the preamplifier IC with the revised filters. Such an iterative process undesirably lengthens the design cycle, increasing costs for both the IC manufacturer and the manufacturer of the hard disk dπve or other magnetic storage device Even after arπving at a suitable design for the preamplifier IC. the hard disk dπve manufacturer still faces problems with chip-to-chip vaπations in the pre-amplifier ICs, as well as dπve-to-dnve vanations in the assembly of the read sensors, wπte heads, flex cables and their interconnection with the preamplifier IC While all elements may be "within spec", the combination of several elements near their outer tolerance limits will often yield a hard disk dπve with a read enor rate outside of acceptable limits. In the present state of the art, suitable tools are not available to the IC manufacturer to avoid the above-mentioned iterations in the design cycle nor for the dπve manufacturer to easily fix read eπor problems aπsing from normal chip-to-chip vaπations and vaπations m the head/sensor/cable interconnect. Accordingly, there is a need for a device which enables reduction of wπte-to- read settling time. There is also a need for a way to allow users to program the duration and intensity of wπte-to-read conection so that it can be optimized easily without the need to reiterate the design cycle. Generally speaking, according to one aspect of the invention, a magnetic information storage apparatus includes a wπte channel for wntmg information to a magnetic medium and a read channel for reading information from the magnetic medium. The read channel includes a sensor which generates an information signal in response to information stored on the magnetic medium. A signal path is coupled to the sensor and amplifies the information to provide an amplified information signal When transitiomng from a wπte mode in which the wπte channel is active to a read mode m which the read channel is active, the transition induces a wπte-to-read disturbance in the read channel. The signal path includes a filter having a zero which vanes over frequency in a time-dependent manner related to the amplitude of the wnte-to-read disturbance. By varying the low corner frequency "LCF")of the filter in a time-dependent manner, the attenuation of the filter can be set to generally match the amplitude of any wnte- to-read disturbances. Generally, this permits high filtenng when the amplitude of the disturbance is expected to be high and low filtenng when the amplitude of the disturbance is expected to be low By not over filtenng or under filtenng, as is typically the case with pnor art systems having a fixed attenuation filter at the front end of the read channel, reduced read eπor rates and reduced transition times are possible relative to the known systems According to a second aspect of the invention, the forward signal path includes at least one gain stage, called filtenng gam stage, the time-dependent filter in the forward signal path being provided by a feedback path having a low pass filter with a pole which vanes in a time-dependent manner and which couples the output of the filtenng gam stage to its input. Varying the pole of the low pass filter in the feedback path vanes the zero in the forward path, and consequently the low corner frequency of the read channel. Favorably, the filtenng gam stage is an emitter-follower, which has the benefit of wide bandwidth, unity ga . and common use m pre-amphfier IC's as a buffer stage. The first two benefits simplify the feedback system by imposing few design constraints, while the latter benefit means the feedback system can be placed anywhere m the read channel such a buffer already exists. According to a third aspect of the invention, the disturbance m the signal path caused by the wnte-to-read transition was found to have a relatively high initial peak amplitude followed by a long tail of decaying amplitude. To effectively filter this type of disturbance, the zero in the forward path is set to vary from a first relatively high frequency to a second relatively low frequency by varying the pole of the low pass filter from a third, relatively high frequency to a fourth relatively low frequency According to a fourth aspect of the invention, the low pass filter includes a vaπable capacitance, the vanation of the capacitance moving the pole of the low pass filter. Favorably, the vanable capacitance includes a plurality of switched capacitors. An equalization circuit is provided to equalize the voltage on each contact node of the capacitors to avoid transients when the capacitors are switched into the circuit According to a fifth aspect of the invention, the apparatus includes a programmable controller programmable by a user, such as a hard disk dnve manufacturer, via an interface (such as a senal interface) to control the time-dependent characteπstics of the user interface. In a sixth aspect of the invention, the forward signal path of the read channel includes a plurality of gam stages. The location of the time-dependent zero is in the "back end" of the signal path. i.e. closer to the output of the signal path than the first gain stage. This helps in reducing DC offset of the read channel. Offset is the difference between the differential DC component at the output and the differential DC component at the input, and is caused by mismatches in components, amplifier differential mismatches, and parasitic resistances in winng Another aspect of the invention concerns a preamplifier integrated circuit which includes a read channel with one or more of the above mentioned features Yet another aspect of the invention is a method for filtenng recurnng transient disturbances in a signal path, the disturbances having an initiation point and decay. The method including filtenng the signal with a filter having controllable attenuation and recunently (1) at the initiation point of the transient disturbance, setting the attenuation of the filter at a first level to substantially filter the disturbance, and (π) reducing the attenuation of the filter in a time dependent manner related to the decay of the disturbance from a first level to a second, lower level. According to another aspect of this method, the disturbance is tnggered by an event in a device, said method further compnsing sensing the event to set the filter at the first attenuation level. In another aspect of the invention, the attenuation level is changed from the first level to the second, lower level by moving a zero in the signal path from a first frequency to a second lower frequency These and other object, features and advantages of the invention will become apparent with reference to the following detailed descπption and the drawings. Figure 1 is a diagram of a magnetic recording apparatus and preamplifier IC according to the invention; Figure 2A is a graph illustrating a transient disturbance aπsing at the front end of a read channel as a result of a transition from a wnte-to-read state of the apparatus of Figure 1 ; Figure 2B is a graph of the gain of a filter having a time-dependent frequency charactenstic; Figure 3 A is a simplified block diagram of a preamplifier integrated circuit according to the invention with a filter as in Fig. 2B in the forward signal path; Figure 3B is a simplified block diagram of a preamplifier integrated circuit m which the filter in the forward is embodied by a low pass filter in a feedback path having a time-dependent low corner frequency. Figure 4A is a circuit diagram showing exemplary circuits for the gain stages 115 and 120 of Figure 3B; Figure 4B is a circuit diagram showing exemplary circuits for the LPF 135 and differential Gm f 140 stages of Fig. 3B; Figure 5 is circuit diagram of an exemplary circuit 170 for generating the control voltages for the LPF 135; Figure 6 is a graph illustrating the time-dependent qualities of the control signals for the LPF 135; Figure 7 is a circuit diagram illustrating a second embodiment to provide a vaπable capacitance with low switching transients of the LPF 135: Figure 8 is a block diagram of a read channel of a magnetic recording/reproducing apparatus having a senal interface for programming wnte-to-read control circuitry; Figure 9 illustrates the different amplitude, width and slope of pulses controlling the feedback transconductor of the first stage by different settings of IbpA, IbpW and W2PJNTDEL1 of the register 205; Figure 10 illustrates the effect of the first stage FBA on a wnte-to-read disturbance; Figure 11 shows the frequency response of the read channel with the feedback loop of LPF 135 and Gm stage 140, illustrating the shifting of the LCF from a high frequency to filter switching disturbances to a lower frequency for the settled read mode: and Fig. 12 is a graph illustrating the significant reduction of wπte-to-read settling time with the preamplifier IC according to the invention. I. REDUCING WRITE-TO-READ SETTLING TIME BY USING TIME-DEPENDENT FILTER Figure 1 illustrates a block diagram of one type of magnetic storage device 10 according to the invention, in this case a hard disk dπve for mass storage of data. The device 10 includes a plurality of magnetic disks (of which only two (1A, IB) are shown for purposes of claπty). and a plurality of pairs of wπte heads 2A1, 2A2; 2B1, 2B2 and read sensors 3A1, 3A2; 3B1. 3B2 mounted on respective servo controlled arms 4 which position the heads and sensors radially relative to coπesponding sides of the spinning disks 1 The servo control of the arms and of the speed of the spinning disks is well known in the art and not pertinent to the present invention, but will be understood to include various servo motors, sensors and control circuits therefor. A preamplifier IC 5 includes a plurality of wnte channels 6A1, 6A2; 6B1, 6B2 and a plurality of read channels 7A1, 7A2; 7B1. 7B2. each wπte channel dnving a respective wπte head to wnte information to a respective side of a disk 1A, IB and each read channel dnvmg a read sensor to read information from a respective side of a disk 1A, IB. These wπte and read channels, grouped conventionally in a pair wise configuration, form a part-per-head (or head interface) portion 5A of the preamplifier IC. The IC 5 is coupled to the read sensors and wnte heads via a flexible cable interconnect 8, which electrically connects the wπte heads and read sensors to the read and wπte channels through connection pins/bumps 9 of the preamplifier IC 5 The IC 5 further includes a back-end read portion 5C and a front-end wnte portion 5B The front-end read portions contain a first gain stage for each read sensor, while the back-end read stage contains a plurality of gain stages and control circuitry common to all of the front-end read channels and is selectively coupled to a front-end read channel 7A1, 7A2, 7B1. 7B2 depending on which read sensor is selected to read information from a disk 1A, IB The preamplifier IC 5 in a hard disk dnve is coupled to a further IC 11 which, for reading information, includes at least an equalizer and a bit detector As previously mentioned, when the disk dπve apparatus transitions from wnting information to a disk to reading information from a disk, this wnte-to-read transition induces spunous disturbances into the read channels due to the interconnect 8, the connections pms and bond wires 9, and the close physical proximity of read and wπte channel front-end circuitry on the IC 5 Figure 2A is a graph which illustrates a voltage waveform of a typical disturbance caused by a wπte-to-read transition At time "I", the wπte- to-read transition occurs and the disturbance rapidly peaks to a peak P duπng time penod A The disturbance rapidly decays through zero volts at time B, to a negative peak ("-P") at a time C Over a penod of time (e g penods C-F n), on the order of micro-seconds, the disturbance has a long tail and decays from the negative peak towards zero volts The waveform of Fig 2A is for illustration purposes only, and each combination of read sensor, wπte head, flexible interconnect and preamplifier IC will generate a proportionally different waveform However, the present inventors have found that the waveforms for wπte-to-read disturbances in a high speed hard disk dπve typically have a high initial peak, a negative peak and decay over time (e g penods A-F, n) with a long tail, and are measurable and charactenzable through component testing Figure 3 A is a block diagram of a read channel 100 according to the invention having a plurality of gam stages, for example 3-5 stages, to amplify the signal from a read sensor 3 so that it can be decoded by a decoding circuit withm the read/wπte channel IC An MR read sensor 3 is coupled to an output buffer 130 via a plurality of gain stages 1 10, 1 15, 120 and 125 (Gmi, Gm n , Gm n+ ι, Gm π+2 ) in the forward signal path 160 of the read channel 100 Together, the gam stages 1 10, 115, 120 and 125 provide an amplified information signal via output buffer 130 to an equalizer 145 and a bit detector 150, which together form part of a decoder circuit, and which converts the analog information signal into a tram of successive digital bits The train of successive digital bits is then decoded according to an algoπthm depending on how the information was encoded when wntten to the magnetic medium In order to suppress transients introduced at the front-end of the read channel (i.e. stage 1 10) so that they do not reach the output of buffer 130. a filter 155 having a time- dependent gain characteπstic is introduced in the forward signal path 60 of read channel 100. Figure 2B illustrates the function of the filter 155. At an initial time penod A in Fig. 2 A corresponding to the peak period of the wπte-to-read transition, the filter has a relatively high LCFΛ, (low gain) exemplified by the line "A". With increasing time, the LCF of the filter 155 is decreased in a fashion generally conesponding to the decay charactenstic of the wπte-to- read disturbance, as illustrated by the time-wise shift (nght-to-left in Fig. 2B) of the LCF of filter 155. Thus, at a time C in which the amplitude (frequency) of the disturbance is generally expected to be less than at a time A as illustrated in Figure 2A, the time-dependent filter will have a coπespondingly increased gain (reduced attenuation) at a given frequency At a time "n" when the amplitude (frequency) of the disturbance is minimal, the filter 155 will have an LCF (LCF n ) and a gain "n" selected to not adversely effect the proper reading of data from the magnetic medium by the read sensor. The time starting with time "n" and thereafter is considered the "settled" state of the read channel when in the READ mode. The number of steps m the gain of the filter is for illustration purposes only, and may vary according to the needs of the application. The gam stage 110 is in the front-end portion of IC 5, and one such gain stage 110 is present for each read channel. The gam stages 115, 120, 125, filter 155 and output buffer 130 are in the back-end circuitry of IC 5 and are common to all of the read channels. The equalizer 145 and bit detector 150 are conventionally on a separate IC 11 Favorably, the zero is introduced in the "back-end" circuits of the read channel to more effectively reduce offsets. By "back-end" circuits is meant the gain stages closer to the buffer 130 than the initial gain stage 110. By placing the zero close to the output, there are no or only few subsequent stages to introduce offset, and conversely the zero reduces the offset of all the pπor circuitry. In Fig. 3 A, the filter is shown connected to output buffer 130. As used herein, a "pole" is defined as the value of the complex vanable s= j T = j2πf for which the transfer function A(s)= (infinity). A "zero" is defined as the value of s, where A(s)= 0. Alternatively, as the context requires, the pole or zero is also refened to in terms of the frequency at which the transfer function is infinity or zero, respectively. In a favorable embodiment (Fig. 3B), the filter 155 in the forward path is embodied by a low pass filter ("LPF") 135 in a feedback path 165 around a unity gain stage 120 m the forward path, the unity gam stage being implemented as an emitter- follower The LPF 135 has a single (dominant) pole which can be vaned from a fairly high frequency FI to a lower frequency F2. This circuit, when in closed loop configuration, introduces a zero in the forward path. The location of this zero is vaπed from a high frequency F A to a low frequency F n as a result of varying the frequency of the pole in the feedback path from a high frequency FI to the lower frequency F2. Varying the location of the pole of LPF 155 vanes the LCF of the zero created thereby in the forward path 160, in the manner illustrated in Fig. 2B. Explained in a different way, as shown in Fig. 2A. wπte-to-read transients are at a lower frequency than the signal frequency being read. In a time domain, the first peak portion (from point I to B) is at a frequency higher than the tail portion starting from point B to point n. This information about the nature of wπte-to-read disturbance frequencies is used to vary the LCF of the signal path in the present invention. For the time penod during the peak portion, the LCF should be higher than the frequency of pulse 1-P-B. After point B, to suppress the tail portion, the LCF can be smaller. After a READ signal is switched ON to activate the read channel 100, for an initial small duration of time (of the order of 100ns) when the transients from the read front- end are very large (e.g. time penod A in Fig. 2A), the effective zero in the forward path is kept at a high frequency F A This filters away most of the wπte-to-read disturbances from reaching the output buffer 130, since the high frequency F A is higher than the frequencies of the wπte-to read disturbances, so maximum attenuation of the initial peal P (Fig. 2A) is achieved. After the initial duration A, the effective LCF in the forward path is moved through lower frequencies F B , F , F D generally corresponding to the times B. C, D m Fig. 2A Ultimately, the LCF reaches frequency F n , where it is kept while the read channel is in the READ mode. This transition from F A through F n coπects the long tail of the wπte-to-read disturbance. Thus, the LCF of the effective filter 155 in the forward path is moved in such a manner that the there is maximum attenuation when the magnitude and frequency of the disturbance is high and lower attenuation when the amplitude and frequency of the disturbance is low. The end point of the LCF is such that it doesn't interfere with normal reading of data; i.e. the frequency of the LCF is much lower than the data frequency This will also simultaneously greatly reduce the offset of the entire read channel. Since the gain of stage 120 is unity, the reduction in offset is roughly proportional to the inverse of the gain of the feedback path 165. More precisely, the transfer function is equal to (Aι 0 /(1 + (Ai2o)(Ai 65 )), where Ano is the gain of stage 120 (unity) and Ai65 is the combined gain of the LPF 135 and of the Gm stage 140. In the present embodiment, the combined gain of stages 135 and 140 is about 20 at LCF n , so the offset is reduced by a factor of21 The output of the LPF 135 is a voltage signal. A differentiator Gm r feedback stage 140 is included in the feedback path 165 to convert the voltage output of LPF 135 to a cunent for feeding back to the forward path at the output of the prior gain stage (in this case stage 115). Here, the feedback loop 165 is shown around the gain stage 120 instead of around the last gam stage 125 Figure 4a shows a circuit diagram of the gain stage 115 and the unity gain stage 120. which operates between an upper voltage supply rail VP and a lower voltage supply rail VN The gam stage 115 includes cascode transistors Tel, Tc2 coupled between load resistors RL1, RL2 and transconductance transistors Tin, Tip, respectively The gain of this stage is equal to the ratio Rll/Rel (R11=R12. Rel=Re2). The output signal currents from the Gm stage 140 are fed back to below the cascode transistors Tel, Tc2 so that the Gm stage 140 does not capacitively load the forward path signal path. Since stage 115 is a transconductance stage (without considenng load resistors R11/R12), the input signal voltage Vip, Vin from the pπor gain stage(s), applied at the bases of the transistors Tin, Tip are converted to currents lgp, ign by these devices. The currents Gpcp, Gpcn from the Gm stage 140 are subtracted therefrom, and applied across the load resistors RL1, RL2 to provide signal voltages gop, gon for the stage 120 Circuit branch 120a of stage 120 includes a first bipolar transistor T2n and a current source 13 biasing the emitter of the transistor T2n. and a circuit branch 120b with a current source 14 biasing the emitter of a second bipolar transistor T2n. The differential voltages gop and gon are applied to the bases of the transistors T2p, T2n. The outputs are differential voltages folp, foln which are fed to the LPF 135, as well as to the next gain stage 125 Since the stage 120 is an emitter-follower and functions as a unity gam buffer, the differential output voltages are approximately of the same magnitude as the differential input voltages for this stage. Figure 4b shows the circuit diagram for the time vaπant LPF 135 and the gm stage 140 The LPF (also refened to as an integrator) includes a number of MOS switches and capacitors to vary the location of the pole of the LPF 135 The inputs to the LPF are voltage signals foln. folp, which are the differential outputs from the stage (Gm n +ι) 120 The signals foln, folp are coupled to the bases of bipolar transistors T3p, T3n. The emitter of each of the transistors T3p, T3n is coupled to a current source 15 via respective resistors R6. R7, the output of cunent source 15 being coupled to a lower voltage suppler rail VN The collector of the transistor T3n is coupled via line LI to the output of a cunent source 16 which is coupled in parallel with a load resistance R4 Similarly, the collector of the transistor T3p is coupled via line L2 to a cunent source 17, also in parallel with a small load resistance R5. The purpose of the cunent sources 16, 17 is to effectively choose the operating point of nodes Ipfh, Ipφ (otherwise it would be (I5/2*RL). Coupled between the lines LI and L2 are a plurality of capacitors CO, Cl, C2, C3. and Cn with capacitor CO being fixed and the remaining capacitances being controllable. The capacitors Cl, C2, C3, and Cn are coupled, respectively, to the lines LI and L2 via MOS devices MIA, M1B; M2A, M2B: M3A. M3B and MnA, MnB The gates of the devices MIA, M IB receive a control voltage VI, the gates of the devices M2A, M2B receive a control voltage V2, the gates of the devices M3A. M3B receive a control voltage V3, and, likewise, the gates of the devices MnA, MnB receive a control voltage Vn. The control voltages are provided to selectively couple the capacitors Cl - Cn between lines LI and L2 to vary the location of the pole of LPF 135. The outputs of the LPF 135 are differential voltages Lpfn, Lpφ. These differential outputs are provided to a further emitter- follower buffer stage including current sources 18, 19 which bias respective bipolar transistors T4p, T4n. The differential outputs of this stage are signal voltages Lpfbn, Lpfbp The feedback gm stage 140 includes a first branch 140a, and a second branch 140b The first branch 140a includes a bipolar transistor T5p having a collector, a base coupled to receive the first differential input voltage Ipfbn, and an emitter biased by a current source 110 Similarly, the second branch includes bipolar transistor T5n having a collector, a base coupled to receive the differential input voltage lpfbp and an emitter biased by the current source 110. The emitters of the transistors T5p, T5n are coupled to the cunent source 110 via respective resistors R15, R16. Additionally, a cunent sources II 1 and a cunent source 112 are coupled, respectively, in the branches 140a, 140b between upper supply rail VP and the collectors of the transistor T2n, T2p The outputs of the gm stage 140 are the cunents Gpcp and Gpcn provided at outputs 43, 44, which are coupled to the pπor amplifier stage 115 (Gm n ) in the forward signal path (as shown in Fig. 4A). The cunent source 110 provide a bias cunent to the emitters of the transistors T5n, T5p Being a transconductance stage, the transistors T5n, T5p convert the differential small signal voltage Lpfbn, Lpfbp. into cunents Gfcp, Gfcn which are proportional to the signal voltages Lpfbn, Lpfbp The cunent sources 11 1, 112 replace the current drawn by the collectors of the transistors T5n. T5p so that the DC cunent at the outputs Gfcp, Gfcn is substantially zero, and therefor does not load and effect the operation of the pnor gam stage 1 15 Ideally, cunents II 1=112= (110/2) so that during operation of the read channel no DC cunent flows through the load resistor RL of the forward signal path. The MOS switches in LPF 135 have to be switched very slowly, in order to minimize transients. Fig. 5 shows one possible implementation of a circuit 170 which generates the control voltages VCl-VCn to dnve the gate of the MOS switches m LPF 135. to achieve the time-dependent movement of the pole of the LPF 135 from the initial relatively high frequency FI to the lower frequency F2. In this example, an R-C ladder structure is used to generate the control voltages in response to a READ control signal received at the input RdDEL. The outputs of the circuit 170 are the control voltages VC1, VC2, VC3 and VCn which control the MOS switches of the vanable capacitor circuit of LPF The READ control signal received at input RdDEl dπves the gates of a PMOS switch T672 and an NMOS switch T673, which together define a switchable cunent path 679 between supply rails VP. VN through a resistor R651. The current path 679 is coupled to dπve the gates of a second pair of PMOS, NMOS transistors T674, T675 via resistor R652. The capacitor C660 and the resistor R651, and the capacitor C662 and the resistor 652 define a first RC time constant. The transistors T674, T675 have main current paths which define a second switchable cunent path 680 between rails VP, VN through serially coupled resistors R653, R654 The cunent path 680 is coupled to dnve the gates of a third pair of PMOS, NMOS transistors T676. T677 which together similarly define a third switchable cunent path 681 through a resistor R655. The transistor T678 is coupled around the resistor R653. When a control signal VC2DEL is applied to the gate of the transistor T678 to render it non- conductive, a second RC time constant is defined by the combination of the two resistors R653. R654 and the two capacitors C664, C665. When a control signal VC2DEL is supplied to render the transistor T678 conductive, the resistor R653 is shunted and a fourth time constant is defined by the combination of the resistor R654 and the two capacitors C663, C664 which is shorter than the third time constant. The third and fourth time constants define the time penod between when the switches T674, T675 rum on and when the switches T676, T677 turn on The combination of a fifth time constant defined by the RC pair of a resistor R655 and a capacitor C666 and of a sixth time constant defined by the RC pair of a resistor R656 and a capacitor C668 controls the time penod between the turning on of the switches T676, T677 and the generation of the control voltage VC3. Subsequent time constants which define the time lapse between the generation of the control signal VC4 and VC3. and between VCn and VC4 are defined by the further RC pairs R657. C669; R658, C670; and R659, C671 The circuit 170 operates as follows. As illustrated m Fig. 6, when the input RdDEL transitions from a logic low to a logic high (conesponding to a wnte-to-read transition), the switch T672 turns off and the switch T673 begins to turn on when RdDel reaches the threshold voltage of switch T673, about 0.7 V This couples the lower supply rail VN to generate the control signal VC2 controlled by the RC time constant of the resistors R651, R652 and capacitors C660 and C662. The signal VC1, as shown m Fig. 6 is initially high, due to the previous state of the signal RdDel being logic low As this signal VC decreases, the NMOS switch T675 turns off and the PMOS switch T674 turns on. This couples the gates of the further switches T676, T677 to the supply rail VP, which turns on the switch T677 and turns off the switch T676. When switch T677 turns on. the outputs VC2, VC3 through VCn are coupled to the rail VN, generating the control voltages VC2, VC3, VCn at these outputs with time delays based on the intervening time constants between the respective delay and the switch T677. The switch T678 serves as an adjustment switch to optionally change the time constants between the control signals VC1 and VC2, by switching creating a shunt around the resistor R653 with the control signal VC2del. The control input signals INTPULSE, Rddel, and Rddel2 and control voltages VC1 to VC4 generated by circuit 170 and dnving the MOS switches m LPF 35 would typically appear as shown in Fig. 6. The slow switching signals for the MOS switches of the vaπable capacitor of Fig 4B can be generated in several other ways, which could be easily implemented by those of ordinary skill in the art in view of the example of Fig. 5 and the waveforms of Fig. 6. Figure 7 is an alternative embodiment of the vanable capacitance circuit within LPF 135. A key requirement of a preamplifier circuit with respect to entenng the steady read mode is the absence of DC transients above 20 mV. In other words, the steady read mode is defined as beginning upon the last occunence of a differential DC transient above this level. Accordingly, it is important that the switching of the capacitors in the LPF not induce differential DC transients. The present inventors recognized that this could occur if the voltage on each node of a capacitor C2 - Cn in LPF 135 were different when that capacitor was switched into the circuit, as different voltages would cause the capacitor to discharge, rapidly creating transient cunents. Additionally, it is important that pnor to the initiation of the read mode the capacitances are not reflected to the nodes Lpfn, Lpφ, so that the pole of filter 135 starts at a high frequency pnor to the capacitors Cl-Cn being switched into the circuit. Figure 7 shows capacitors CO - Cn and PMOS switches MIA - Min, M1B- Mln conesponding to Fig. 4B. Additionally, Fig 7 shows circuitry which equalizes the voltage on the nodes on either side of the capacitors Cl- Cn pnor to the capacitor being switched into the circuit. A transistor T81A is coupled m the branch L3 and has its emitter coupled to the collector of a diode connected transistor T82A. The base of the transistor T81A is coupled to branch LI, and is at the same potential as node Lpfn. Thus, the base of the transistor T82A is one diode drop below node Lpfn. Transistor T83A has its base coupled to the base of the transistor T82A and its emitter coupled to the rail VP via a cunent source 113. The node LpfmA. between the cunent source 113 and the emitter of the transistor T83A is one diode drop above the base of transistor T82A, so is at the same voltage as node Lpfn. The difference in base-emitter voltages due to different cunents and mismatches in transistors is accounted for by appropnate dimensioning of the transistors T82A. T83A to achieve voltage equivalence between nodes Lpfn and LpfmA. The transistors T81B, T82B, T83B are coupled in a conesponding manner to the circuit branches L2, L4, L6. so that the node LpfmB is at the same potential as node Lpφ m branch L2. The control gate of PMOS equalization transistors MIC, MID are coupled to the input RdDel and the control gate of PMOS transistors MIA, M1B are coupled to receive control voltage VC1 of Figure 5. Similarly, the gates of PMOS equalization transistors M2C.M2D; M3C; M3D and MnC. MnD are coupled to receive the signal Rddel2 and the gates of the PMOS transistors M2A.M2B; M3A. M3B and MnA.MnB receive the control voltages VC2, VC3. VCn. With reference to Fig. 6. the signal VC1 is initially high and the signals RdDel and Rddel2 are initially low. Thus, the equalization switches MlC-MnC and MlD-MnD are initially conductive and couple each of the capacitors Cl - Cn to the nodes LPFmA, Lpfmb Both nodes are coupled to the same DC potential thereby. Furthermore, because the nodes LpfmA, LpfmB are coupled to the nodes Lpfn, Lpφ through two emitter followers (formed by the transistors T81A, T82A; T82A, T82B) the capacitance of devices Cl - Cms reduced by a factor of $ 2 and are substantially not reflected to the nodes Lpfn, Lpφ, so that the cut-off frequency of filter 135 is pπmaπly determined by the capacitance of device CO When Rddel goes high, switches MIC and MID turn off, as signal VC1 goes low and switches MIA, M1B turn on to bπng capacitor Cl into circuit. When signal VC1 turns switch MIA, M1B on. both sides of the capacitor Cl will have been at the same potential, so DC switching transients are minimized. Note that devices C2-Cn are still decoupled from the filter m the AC sense by equalization switches M2C-MnC: M2D. Mnd and their conesponding emitter- followers so that their capacitance does not influence the relatively high pole determined by capacitance Cl . Signal Rddel2 then goes logic high, turning equalization switches M2C - MnC off. and signals VC2 - VCn then go logic low is succession to further reduce the pole frequency of LPF 135 Switches MlC-MnC and MlD-MnD introduce gate-source and gate-drain capacitances into the LPF 135. and thus may introduce their own current transients upon switching. To counteract this problem, a number of compensating PMOS transistors (M2An- MnAa; MlCn-MnCn; M2Bn-MnBn; MlDn-MnDn) are provided corresponding to respective ones of the PMOS switches M2A-MnA; MlC-MnC; M2B-MnB; MlD-MnD. The compensating PMOS transistors have their drains coupled to their sources, effectively doubling their capacitive effect and allowing these compensating devices to be substantially reduced in size. Since the source and drams are connected to each other, these PMOS devices do not function as switches, but as capacitors. The compensating PMOS devices are provided with a charging signal at their gates, at the same time their respective equalizing PMOS switches are dnven, which charging signal is selected to induce a charge therein of the opposite sense as the charge induced in the respective equalization switch when it is switched. In this manner, the charging signals can be selected to reduce transient cunents based on the actual transients induced in the IC by the equalization switches, whereas a fixed compensating capacitor could not. Thus, the compensating CMOS devices minimize transients and ensure that the equalization circuitry doesn't degrade its own performance with respect to reducing the settling time of wπte-to-read disturbances. The MOSFET switches T85. T86 receive signal INTON which controls whether the LPF 135 is on or off The switch T4 receives a control signal iNTGALN, and switches the resistor R2 into and out of circuit with the resistor Rl The resistors Rl, R2 determine the DC gain of LPF 135 and signal INTGAIN is used to switch the LPF 135 between a high and a low gam mode. This provides a different gain control mechanism than the vanable capacitance circuitry, which vanes the pole of the LPF II) OPTIMIZATION OF WRITE-TO-READ SETTLING TIME THROUGH A SERIAL INTERFACE REGISTER. It is favorable if the programmabi ty of wnte-to-read settling time in the read channels is programmable. This will enable a user of the preamplifier IC to program the suppression charactenstics in each preamplifier IC to fine tune vaπations in wπte-to-read disturbances in each hard disk dnve, thereby optimizing performance. In one embodiment, programmability is achieved through a senal interface connection with the preamplifier IC. Registers in the senal interface are designated to turn the "knobs" of vanous control elements m the read channel which control wnte-to-read suppression Figure 8 is a block diagram of one embodiment illustrating the programming of a preamplifier IC through a user interface. Elements conesponding to those in previous Figures bear the same reference numbers. In this embodiment, the read channel includes two programmable control elements which control the wnte-to-read suppression The first control element is in the first gain stage 110 coupled to a read sensor 3 The second control element is a "back-end" control circuit W2RINT 180 conesponding to the LPF 135 and Gm stage 140 in combination with the control circuit 170 of Fig. 5. Both of these control elements are controlled by the contents of a senal interface register 205 of a senal interface 200. This senal interface register is an eight bit register stonng the following vanables (in the order of most-significant-bit (MSB) to least-significant-bit (LSB)): BCPW, IBFALL. IBPA, IBPW, W2RTNTDEL2, W2RTNTDEL1, W2RINTG and W2RTNTON. As shown here, the first gain stage 110 has cross coupled capacitors Cl 15, Cl 16 and a feedback amplifier ("FBA") 1 lOe between the differential ouφuts 110c, 1 lOd and the cross-coupled capacitors This first gain stage 110 with cross-coupled capacitors is known, for example, from U.S. Patent 5.559,646 (Voorman et al), incorporated herein by reference This gain stage 1 10 also includes a conventional common mode control circuit which controls the common mode DC voltage. Varying the gain of the feedback amplifier 1 lOe controls the low corner frequency, in other words a zero, of the first stage 110. The feedback amplifier 1 lOe is a transconductance (Gm)stage whose gam is controlled by a biasing cunent lb supplied to it from a digital-to-analog converter ("DAC") 112. The cunent lb is controlled by a control pulse IBPULSE supplied to DAC 112 by a pulse generation circuit 210. It is noted that it is known in the art to vary the cunent lb to change the corner frequency of the first stage between two frequencies and to control the timing of the switchover with a controlled pulse signal. These function are present in Philips Semiconductors' TDA 5360 preamp circuit However, the changeover is controlled internally, and no programmability through a user interface is available. The wπte-to-read circuit senses the onset of the wπte-to-read transition ("WRT") moment, which is graphically illustrated in chart 9A of Fig. 9 (The wπte-to-read transition is known from a control signal in the magnetic storage apparatus which controls when the apparatus switches from the wnte mode to the read mode). The control pulse IBPULSE, illustrated in chart 9B, is supplied by the pulse generation circuit 210. Three of the eight register bits control this bias cunent. The register bit IBPW is used to control the pulse width "PW". (Chart 9B) The pulse width determines the duration of wnte-to-read suppression of the feedback amplifier 1 lOe The register bit IBPA controls the amplitude "PA" of the control pulse, which determines the amplitude of the bias cunent lb, which in rum controls the location of the LCF of the gain stage 1 10 dunng wπte-to-read transition. The register bit IBFALL controls the fall time "FT" (slope) of the pulse IBPULSE to ensure a smooth transition so as not create an extra disturbance in the read channel. Depending on the register setting of IBPW, it generates a pulse width PW approximately 150ns to 300ns long. The register bit BCPW controls the common mode control circuit within stage 110 to further reduce DC transients at the wnte-to-read transition. Under normal operation, the maximum low corner frequency (LCF) of the first stage 1 10 is programmed to be 2MHz to 5MHz. The LCF of the preamplifier IC is determined by the gam of the feedback transconductor m the first stage. Dunng a wπte-to- read transition, the LCF is shifted to a higher frequency to filter out the wπte-to-read transient. Depending on the register setting of IB PA, this higher frequency of the LCF of the first stage 110 can be 6MHz to 10MHz. After the wπte-to-read transient dies away, the LCF is shifted back to its lower programmed value so it will not adversely affect reading of the data signal. The back-end control circuit 180 is controlled by the register bits W2RTNTDEL1, W2RTNTON, W2RING, and W2RTNTDEL2. Pulse generation circuit 210 generates a second pulse TNTPULSE (Chart 9C) which is fed to W2RINT 180. Register bit W2RTNTDEL1 controls the duration that the LCF of circuit 180 is at the first, relatively high frequency. Register bit W2RTNTDEL1 directly controls the delay time of INTPULSE (from the READ signal to reachiong the logic threshold on INTPULSE. INTPULSE is input to control circuit 170 (Fig 5) and therefore controls the delay between the wπte-to-read transition and the activation of switches TT672, T673. Register bit W2RLNTON turns circuit 180 on and off, via the switches T85, T86 (Fig. 7) Register-bit W2RLNTG controls the gain of the LPF 135, via switch T4 Register bit W2RTNTDEL2 is provided to the input VC2Del, and thus controls the duration of change of the LCF from the first, relatively high frequency to the second, relatively low frequency. By way of example, the first relatively high frequency may be 15MHz, the second lower frequency may be 150 KHz. Thus, to suppress wnte-to-read transients, the LCF is initially at 15MHZ to suppress the high initial peak illustrated in Fig 2A. The LCF is moved to 150 Khz gradually to suppress the long tail without over filtenng, and is then maintained at 150 KHz. This very low LCF is to ensure that the existence of the feedback circuit 180 does not have a significant impact on the overall frequency response of the read channel Fig. 10 is a graph which illustrates the effect of the first stage 110 m reducing the wnte-to-read transition. Line "A" is an unconected wnte-to-read disturbance Line "B" is the wπte-to-read disturbance with only the FBA 1 lOe activated to reduce the disturbance Line "C" shows the additional reduction provided by a boost in the gain of the common mode control circuit within stage 110 to reduce DC transients at this first stage. Figure 11 illustrates the frequency response of the entire read channel 100 with the feedback integrator (stages 135. 140) in different gain modes. Line HG represents the high gam mode of the feedback integrator, which would occur if the W2RLNTG bit is set to high. The LCF of the system. LCF HG , m the high gain mode is dominated by the feedback integrator and is at a high frequency to filter the peak portion of the wπte-to-read disturbance. Line LG represents the integrator in a lower gain mode, when the W2RJNTG bit is set to logic high. Line R represents the steady state of the read path frequency response dunng the read mode. Line O is the frequency response of the read channel when the feedback integrator is turned off. As is quite evident, dunng the normal read mode, the integrator has little effect on the frequency response of the read channel. This is because the zero introduced by the W2RLNT 180 when the read channel is nominally operating is sufficiently lower than (approx 10 times lower freq.) than the zero of the first stage 1 10 of the preamplifier that the zero (i.e. the low corner frequency) of the overall read channel is not affected by the zero in the W2RTNT 180. However, as demonstrated earlier, the integrator nonetheless significantly reduces the offset of the preamplifier IC Figure 12 illustrates an actual wnte-to-read disturbance after filtenng with a preamplifier IC having both of the first and second control elements. The wnte-to-read transition is at momet "I" in the Fig The disturbance has a high initial peak "P", of a negative peak "-P", and a tail. As mentioned previously, the beginning of the settled read mode is defined as beginning at the last occunence where the disturbance has a magnitude of 20 mV In Fig. 12, this occurs at a time of 124 Ns, at point "C" In circuits without the filtenng elements of the present invention, settling time was typically on the order of 4 to 10 microseconds. Thus, the present invention provides an improvement in settling time averaging on the order of a factor of 50 With this "wnte-to-read" register, disk dnve manufacturers can optimize the wnte-to-read performance easily by programming through the senal register This also shortens the design cycle because different parameters can be tested without the need of changing the design of the read channel The process or technology by which the of the invention is made is not important and any of the standard bipolar, CMOS or BiCMOS processes can be used Although prefened embodiments of the present invention have been shown and descnbed. it will be appreciated by those skilled in the art that changes may be made in these embodiments without departing from the pπnciples and spint of the invention, the scope of which is defined in the claims The many features and advantages of the invention are apparent from the detailed specification and it is intended by the appended claims to cover all such features and advantages which fall within the true spint and scope of the invention Since numerous modifications and changes will readily occur to those skilled in the art, it is not desired to limit the invention to the exact construction and operation illustrated and descπbed, and accordingly all suitable modifications and equivalents may be resorted to, falling within the scope of the invention

Claims: CLAIMS 1 A magnetic information storage apparatus, compnsing a wnte channel for wπting information to a magnetic medium; and a read channel for reading information from the magnetic medium, said read channel including • a sensor for generating an information signal in response to information stored on the magnetic medium. • an output and • a signal path coupled between the sensor and the ouφut intended to amplify the information signal and to provide the amplified information signal to the ouφut, • the signal path including a filter having a zero which vanes in a time-dependent manner related to a time duration of a wnte-to-read disturbance generated m the read channel by a transition from a wnte mode in which the wnte channel is active to a read mode in which the read channel is active 2 An apparatus according to claim 1 , wherein said signal path includes a forward signal path including a filtenng gam stage having an input and an ouφut, and a feedback signal path coupling said output to said input of the filtenng gain stage, said feedback signal path including a low pass filter having a pole which vanes in a time dependent manner, thereby generating said time dependent zero in said forward path 3 An apparatus according to claim 2, wherein said low pass filter includes a vanable capacitance, the vanation of the capacitance moving the pole of the low pass filter 4 An apparatus according to claim 3, further compnsing a serial interface which allows user input of parameters to program the value of said capacitance 5 An apparatus according to claim 2, wherein said signal path includes a first gain stage coupled to said sensor, an ouφut buffer, and a plurality of ga stages cascaded between said first stage and said output buffer, said filtenng gain stage being compnsed by one of said plurality of gain stages 6 An integrated circuit compnsing a signal path including • a forward signal path with at least one gain stage having a stage input and a stage ouφut, and • a feedback path compnsing a low pass filter coupled between said stage input and said stage ouφut, said low pass filter having a pole which vanes with time, thus varying the location of a zero in the forward signal path 7 An integrated circuit for use in a magnetic storage device having a magnetic medium, a wnte head intended to wnte information to the magnetic medium and a read sensor intended to read information from the magnetic medium and to generate an information signal, said integrated circuit compnsing a signal path intended to receive and amplify the information signal, the signal path including a filter with a zero which vanes from a first frequency to a second, lower frequency in a time-dependent manner 8 An integrated circuit according to claim 7, wherein said signal path includes a forward signal path including at least one gain stage having an input and an ouφut, and a feedback signal path coupling said ouφut to said input of said at least one gam stage, said feedback signal path including (I) a low pass filter having a pole which vanes m a time dependent manner from a third frequency to a fourth lower frequency, thereby generating said time dependent zero in said forward path 9 An integrated circuit according to claim 8, wherein said low pass filter includes a vaπable capacitance, the vanation of the capacitance moving the pole of the low pass filter 10 A method of filtenng recurnng transient disturbances in a signal in a signal path, the disturbances having a magnitude with an initial peak and a tail in which the magnitude decays from the peak, said method compnsing • filtenng the signal with a low pass filter in a feedback path coupled to the signal path, the low pass filter having a controllable corner frequency and • recurrently (1) at the initiation point of the transient disturbance, setting the corner frequency of the low pass filter at a first frequency to substantially filter the peak of the disturbance, and (π) reducing the attenuation of the filter m a time dependent manner related to the decay of the disturbance from the first frequency to a second, lower frequency 1 1 An integrated circuit, compnsing • a signal path transmitting a signal subject to recurnng transient disturbances, the disturbances having a recurnng initiation point, and a substantially consistent peak and decay charactenstic, • filtenng means for filtenng the recurrent transient disturbances, said filtenng means compnsing a low pass filter in a feedback path coupled to said signal path, said low pass filter having a controllable corner frequency and • control means coupled to said filter means for recunently varying the corner frequency of said low pass filter to provide relatively high filtenng when the disturbance has a high magnitude and relatively low filtenng when the disturbance has a low magnitude 12 An integrated circuit according to claim 9, wherein said variable capacitance includes a plurality of capacitances, a plurality of switches selectively coupling said capacitances in circuit m said low pass filter, and an equalization circuit which equalizes the voltage across a capacitor pnor to being switchably coupled m circuit 13 An integrated circuit according to claim 12, wherein said equalization circuit includes a plurality of equalization switches coupled to said capacitances, and a plurality of compensation devices coupled to said capacitances and controlled to induce a transient cunent in an opposite sense to a transient cunent induced by the conesponding equalization switch, thereby minimizing switching transients of the vanable capacitance

Inventors: ALLOUCHE DAVID, BHANDARI SANJAY M, ALLOUCHE, DAVID, BHANDARI, SANJAY, M.
Applicants: KONINKL PHILIPS ELECTRONICS NV, KONINKLIJKE PHILIPS ELECTRONICS N.V.
Application year: 2000
Main classification: G11B5
IPC codes: G11B5, G11B20, H03F3, H03H11