MECHANISM FOR REORDERING TRANSACTIONS IN COMPUTER SYSTEMS WITH SNOOP-BASED CACHE CONSISTENCY PROTOCOLS

Abstract: An apparatus and method for expediting the processing of requests in a multiprocessor shared memory system. In a multiprocessor shared memory system, requests can be processed in any order provided two rules are followed. First, no request that grants access rights to a processor can be processed before an older request that revokes access rights from the processor. Second, all requests that reference the same cache line are processed in the order in which they arrive. In this manner, requests can be processed out-of-order to allow cache-to-cache transfers to be accelerated. In particular, foreign requests that require a processor to provide data can be processed by that processor before older local requests that are awaiting data. In addition, newer local requests can be processed before older local requests. As a result, the apparatus and method described herein may advantageously increase performance in multiprocessor shared memory systems by reducing latencies associated with a cache consistency protocol.

Description: TITLE: MECHANISM FOR REORDERING TRANSACTIONS IN COMPUTER SYSTEMS WITH SNOOP-BASED CACHE CONSISTENCY PROTOCOLS BACKGROUND OF THE INVENTION 1. Field of the Invention This invention relates generally to the field of computer systems and. more particularly, to accelerating cache-to-cache transfers m computer systems with multiple processors 2. Description of the Related Art Data processing systems often include multiple processors that share a common system memory. As used herein, the term processor can be used to refer to an active device that uses a system memory Processors can include microprocessors, input-output bridges, graphics devices, peripheral devices, or other devices that read oi write to a system memory. Processors in data processing systems often include a cache to improve performance Caches in a multiple processor system can include cache tags for each cache line. The cache tags can specily the access rights and ownership responsibilities for a corresponding processoi. Caches in a multiprocessor shaied memory system need to be maintained in a consistent and coherent manner. A set of cache protocol rules can be employed to ensure that data stored m a system memory appears the same to all processors despite being stored m various caches. One approach to cache consistency is the use of a standard snooping protocol. In a standard snooping protocol, each processor bioadcasts all of its requests for cache lines to all of the other processors on an address bus. Each processor, in turn, "snoops" the lequests fiom othei processors and responds, as needed, by updating its cache tags and/or conveying the data coπesponding to the cache line to the other processoi . In a standard snooping piotocol, lequests arrive at all piocessois in the same order, and each piocessor processes the requests in the oider that they aπ ive. A processor can be said to "piocess " a request when the request affects the internal state of the processor. In a standai snooping piotocol, requests include local lequests and foreign lequests. Local requests include lequests generated by the piocessor itself while foreign requests include lequests from other processoi s. Requests can also be referred to as address packets since requests typically specify a cache line by its address Address packets can also be refeπed to as address bioadcasts The terms request, addiess packet, and address broadcast will be used interchangeably heiem. The requirement that requests be processed in the order in which they arrive can be considered a performance drawback of a standaid snooping piotocol. In particular, this requirement can delay the tiansfei of data from one cache to another cache. The requirement can also delay the processing of data received by a processor if the data corresponds to a local request and it arrives before data that correspond to an earlier local request. In processing a local request, a piocessor waits for the data corresponding to the local request to arrive before piocessing other requests. Potentially, multiple processors can be waiting for a single processoi to recen e its data This situation can create an undesirable latency in the system If a processor is allowed to process othei requests pπoi to the data corresponding to a local request arriving, however, starvation can result if a subsequent request revokes the processor's access rights to the cache line of the local request before the processor receives the data A system for reducing the latency of a standard cache consistency protocol is needed without introducing starvation problems into the system SUMMARY The problems outlined above are in large part solved by the use the apparatus and method described herein Generally speaking, an apparatus and method for expediting the processing of requests in a multiprocessor shared memory system is provided In a multiprocessor shared memory system, requests can be processed in any order provided two rules are followed First, no request that grants access rights to a processor can be processed before an older request that revokes access rights from the processor Second, all requests that reference the same cache line are processed m the order in which they arrive In this manner, requests can be processed out-of-order to allow cache-to-cache transfers to be accelerated In particular, foreign requests that require a processor to provide data can be processed by that processor before older local requests that are awaiting data In addition, newer local requests can be processed before older local requests As a result, the apparatus and method described herein may advantageously increase performance in multiprocessor shared memory systems by reducing latencies associated with a cache consistency protocol In one embodiment, a processor can include a fust queue and a second queue to implement the abov e rules The first and second queue can be operated in a first-in-first-out (FIFO) mannei The processor can store address packets that grant access rights to the processor in the first queue The piocessor can also sloie in the fust queue address packets that reference the same cache line as an address packet in the first queue The processor can store all other address packets in the second queue Address packets that require data can remain at the head of a queue until the data arrives The processor can be configured to piocess addiess packets trom the head of eithei queue in any ordei In this manner, foreign packets that require data can be handled before older local packets that are awaiting data BRIEF DESCRIPTION OF THE DRAWINGS Othei ob]ects and advantages of the inv ention will become apparent upon reading the following detailed description and upon reference to the accompanvmg drawings in which Fig 1 is a block diagram illustrating one embodiment of a computer system Fig 2 is a block diagram illustrating one embodiment of a computer system Fig 3 is a block diagram illustrating one embodiment of a computer system Fig 4 is a block diagram illustrating one embodiment of an apparatus configuied to process address packets in a computer system Fig 5 is a chart depicting a method for handling addiess packets Fig 6 is a chait depicting a method for determining if an address packet can be processed Fig 7 is a block diagram illustrating one embodiment of a shared memorv computer system with multiple nodes While the invention is susceptible to \ aπous modifications and alternative forms, specific embodiments thereof are shown by way of example m the draw mgs and will herein be described in detail It should be understood, howev er, that the drawings and detailed description thereto are not intended to limit the invention to the particular form disclosed, but on the contrary, the intention is to cover all modifications, equivalents, and alternatives falling within the spirit and scope of the present invention as defined by the appended claims DETAILED DESCRIPTION OF AN EMBODIMENT Turning now to Fig 1 , a block diagram illustrating one embodiment of a computer system is shown Other embodiments are possible and contemplated In Fig 1, system memory 100, processor A 110a, piocessor B 110b, processor C 110c, cache A 120a, cache B 120b, cache C 120c. address bus 130, data bus 140a, data bus 140b, data bus 140c, and data bus switch 150 are depicted System memory 100 is coupled to address bus 130 and data bus switch 150 Processor A is coupled to address bus 130, data bus 140a and cache A 120a Processor B is coupled to address bus 130. data bus 140b, and cache B 120b Processor C is coupled to address bus 130, data bus 140c, and cache C 120c In Fig 1 , processoi A 110a, processor B 110b, and processor C 1 10c can be configured to access system memory 100 and store data retrieved from system memory 100 m cache A 120a. cache B 120b, and cache C 120c, respectively As noted above, the term processor can be used to reler to an active device that uses a system memory Processors can include microprocessors, input-output bridges, graphics devices, peπpheial devices oi other devices that lead or write to a system memoiy Although Fig 1 illustrates processoi A 1 10a, piocessoi B 110b, and processor C 110c, other processors can be added to the system and can be coupled to address bus 130 and data bus switch 150 in other manners In the discussion of Fig 1 , Fig 2. and Fig 3, piocessoi A 110a, processor B 1 10b, and processor C 110c can be referred individually as a "processor' or collectively the "processors' Similarly, cache A 120a, cache B 120b, and cache C 120c can be referred individually as a 'cache oi collectively the 'caches' In one embodiment configured to employ a snoop-based cache consistency protocol, a processor can be configured to convey a request for data on address bus 130 As noted abov e a request can also be lefened to as an address packet or an addiess bioadcast Each piocessoi can be configured to receive the requests of all of the othei processors In the embodiment of Fig 1. address bus 130 can be said to comprise a bioadcast network such that each request conveyed on addiess bus 130 can be received bv each piocessoi and system memoiy 100 A processor and system memory 100 can be configured to respond to a request based on a cache piotocol employed by the system A piocessor may respond a lequest by altering its access rights and/or prov iding the data accoidmg to the cache protocol If the cache piotocol does not require a processoi to piov ide data in lesponse to a lequest, system memory 100 may be configured to piovide the data In Fig 1 the processors and system memoiy 100 can be configured to piovide the data by conveying it to data bus switch 150 Data bus sw itch 150, in response to receiving data from a processor or system memory, can be configured to route the data to the appropriate piocessoi or system memory 100 In the embodiment of Fig 1 , data bus switch 150 and data buses 140a, 140b, and 140c can be said to comprise a point-to-point switched netwoik In the embodiment of Fig 1 , requests can be configuied to identify data to be obtained by using the address of the data in system memoiy 100 In response to leceiving data, a piocessor can be configuied to store the data in its cache In one embodiment, data can be stored in a location in a cache according to its address Caches can be configured to map data from an addiess into a particulai cache line As a result, the cache of each processoi can be configured to map data to the same location in then respectiv e caches Thus, a request for data fiom a processor can also be said to be a request for a cache line and a processor can respond to a request according to the cache line m its cache that corresponds to the address of the request It can be noted that cache lines can be configured as any suitable size of memory In one embodiment, the caches m Fig 1 include cache tags for each cache line The cache tags can be configured to indicate a processor's access right to the cache line The access rights can be defined according to a cache protocol A cache protocol can define what access rights a processor has to a cache line and whether the processor is to provide the cache line in response to a request In one embodiment, access rights can include a shared state, an exclusive state, and an invalid state Generally speaking, a processor can be said to have access rights to a cache line if its rights are m the shared or exclusive state If a processor's access right is m the exclusiv e state, no other processor can read or write to the cache line If a processor's access right is in the shared state, another processor may also have shared access such that it can read the cache line If a processor's access right to a cache line is in the mv alid state, it will need to gam an access right to the cache line before reading or writing the cache line In one particular embodiment, a MOSI cache protocol can be employed In a MOSI cache protocol, a processor's access right to a cache line can be either modified, owned, shared, or invalid In the modified state, a processor can read and write a cache line and can provide the data of the cache line in response to a request from another processor In the o ned state, a processor can read a cache line but cannot write to it The processor can also provide the data of the cache line m response to a request from another processor m the owned state In the shared state, a piocessor can read a cache line but cannot write to it and does not provide the cache line in response to a request from another processor In the invalid state, a processoi cannot read from or write to a cache line and must convey a lequest to gam access If no processor has a cache line in an owned or modified state, system memory 100 can prov ide the cache line in response to a request Other embodiments can be configured to implement other cache protocols As noted abo e, a standard snooping protocol generally lequires processoi s to piocess requests in the order they aie receiv ed A processor can be said to process' a request when the request affects the internal state of the processor In the protocol employed by the system in Fig 1. however, requests can be processed in any oidei provided the follow mg two rules are obeyed First, no iequest that grants access rights to a piocessor can be processed by that piocessor before an older request that revokes access rights from the processor Second, all requests that reference the same cache line are processed by a piocessoi in the order in which they aπive at the processor In the abo\ e rules, the granting and revocation of access rights can be viewed from the processor that processes a request Certain lequests, foi example may grant access rights to one processor while le okmg rights from another The rules, however, are defined in terms of the effect of a request within the processor that processes the lequest It can be noted that the t o rules can be applied to any cache protocol For purposes of illustration however, the rules vv ill be described with respect to the MOSI cache protocol As noted above, a processor can receive and process local and foreign requests In the MOSI protocol, access rights can be granted or revoked based on the current state of the access rights of a cache line and the type of request In particular, a local request for shared access to a cache line whose current state is invalid constitutes a grant of access rights A local request for exclusive access to a cache line whose current state is invalid, shared, or owned also constitutes a grant of access rights A foreign request for shared access to a cache line whose current state is modified constitutes a revocation of access rights A foreign request for exclusive access to a cache line whose current state is modified, shared, or owned also constitutes a revocation of access rights It can be noted that some requests aie neither grants nor revocations Such requests include a foreign request for shared access to a cache line whose current state is shared, owned, or invalid Other requests can be both a grant and a revocation A local ReadStream packet, for example, can request a read-once copy of a cache line that is invalid In this manner, a local ReadStream packet can grant an access right to read the cache line and can subsequently revoke that access right once the cache is read Requests that neither grant nor revoke access rights and requests that both grant and revoke access rights can be handled in manner consistent with the above rules The use of the above rules can allow requests to be processed in an out-of-order manner and may provide performance advantages over other systems For example, in the above rules, a request that revokes access rights can be processed prior to an older requests as long as the request does not reference the same cache line as the oldei request Similarly, a request that grants access rights can be processed prior to an older request that also grants access rights as long as the request does not reference the same cache line as any of the older requests One particular advantage of the use of the roles over other systems involves cache to cache transfers In the case wheie a processor has modified or owned access rights to a cache line, the processor can provide data corresponding to that cache line to satisfy a foreign request for shared or exclusive access If the processor has a local request that was received prior to the foreign request, it may not have to wait for the data that would satisfy the local request to arrive before sending the data corresponding to the foreign request In other words, the processor could send the data to satisfy the foreign request prior to receiving the data to satisfy the oldei local request It can be noted, with respect to the abov e rules, that the local request would grant access rights to the processor and the foreign request would i evoke access rights from the processor Thus, cache to cache tiansfeis can be expedited when a processor conveys data from its cache to another processoi 's cache prior to completing an older lequest In this manner, the use of the rules can be said to accelerate cache to cache transfeis of data Anothei advantage of the use of the abov e rules concerns the leordeπng of local requests Undei the roles a processor can piocess a local request that grants access rights to the processor pnor to an oldei local request that also grants access rights to the piocessoi as long as the requests reference different cache lines Thus, if the data foi one local request arrives prior to the data for an older local request the processoi can process the newer lequest prior to processing the older request In this manner, local requests can be processed in an expedited manner and may provide performance advantages ov er other systems The two examples just discussed are intended to highlight performance advantages of the use of the abo e rules in a multiprocessoi shared memory system Other performance advantages are possible and contemplated Turning now to Fig 2, a block diagram illustrating one embodiment of a computer system is shown Other embodiments are possible and contemplated In Fig 2, system memoiy 100, processoi A 1 10a, processoi B 110b, processor C 1 10c, cache A 120a. cache B 120b. cache C 120c, address bus 130, and data bus 200 aie depicted System memory 100 is coupled to address bus 130 and data bus 200 Processor A is coupled to address bus 130, data bus 200, and cache A 120a Processor B is coupled to address bus 130, data bus 200, and cache B 120b Processor C is coupled to address bus 130 data bus 200, and cache C 120c In Fig 2, processor A 110a, processor B 110b, and processor C 110c can be configured to access system memory 100 and store data retrieved from system memory 100 in cache A 120a, cache B 120b, and cache C 120c, respectively Although Fig 2 illustrates processor A 110a, processor B 110b, and processor C 110c, other processors can be added to the system and can be coupled to address bus 130 and data bus 200 in other manners The embodiment of Fig 2 can be configured to employ the cache protocol rules as discussed above in Fig 1 In Fig 2, the processors and system memory 100 can be configured to provide data by conveying it on data bus 200 Data bus 200 can be said to comprise a broadcast network Turning now to Fig 3, a block diagram illustrating one embodiment of a computer system is shown Other embodiments are possible and contemplated In Fig 3, system memory 100, processor A 110a, processor B 110b, processor C 110c, cache A 120a, cache B 120b, cache C 120c, and address/data bus 300 are depicted System memory 100 is coupled to address/data bus 300 Processor A is coupled to address/data bus 300 and cache A 120a Processor B is coupled to address/data bus 300 and cache B 120b Processor C is coupled to address/data bus 300 and cache C 120c In Fig 3, processoi A 110a, processor B 110b, and processor C 1 10c can be configured to access system memory 100 and store data retrieved from system memory 100 in cache A 120a cache B 120b, and cache C 120c respectively Although Fig 3 illustrates processor A 1 10a, processor B 110b and processoi C 110c, othei processors can be added to the system and can be coupled to address/data bus 300 in other manners The embodiment of Fig 3 can be configured to employ the cache protocol rules as discussed above m Fig 1 In Fig 3, the processors and system memory 100 can be configured to pro ide data by conveying it on address/data bus 300 Address/data bus 300 can be said to comprise a shared broadcast network as it can be configured to transmit both requests, l e address packets and data Turning now to Fig 4, a block diagram illustrating one embodiment of an apparatus configured to piocess address packets m a computer system is shown Other embodiments are possible and contemplated In Fig 4 queue 410, queue 420 control circuit 430, processing circuit 440, and cache tags 450 aie depicted Control circuit 430 is coupled to queue 410 queue 420 and cache tags 450 Processing circuit 440 is coupled to queue 410 and queue 420 Fig 4 illustrates one embodiment of an apparatus in a processor configured to use the cache piotocol rules discussed abov e in Fig 1 In Fig 4, address packets, I e requests, can be received by control circuit 430 Control circuit 430 can be configured to determine whether the address packets grant or revoke access rights to the processor Control cncuit 430 can also be configured to determine whether an address packet references the same cache line as an oldei address packet in the processor Control circuit 430 can then be configured to store an address packet in queue 410 or queue 420 The address packet can be popped from either queue 410 or 420 and processed by processing circuit 440 consistent with the protocol rules described above In one embodiment control circuit 430 can be configured to leceive an address packet and determine whether that packet grants access rights to the processor Control circuit 430 can be configured to receive the current access rights of the processor from cache tags 450 In one embodiment cache tags 450 can be provided from a cache such as one of the caches shown in Fig 1 , Fig 2 oi Fig 3 In other embodiments, cache tags 450 can be located withm a processor Control circuit 430 can be configured to compare the current access rights received from cache tags 450 with the type of request embodied in the address packet to determine whether the address packet grants an access right to the processor It can be noted that address packets that both grant and revoke access rights, e g a local ReadStream packet, include a grant Thus, control circuit 430 can be configured to determine that a ReadStream address packet grants access rights to the processor If control circuit 430 determines that an address packet grants access rights to a processor, control circuit can be configured to convey the address packet to queue 420 Queue 420 can be configured to store the address packet Control circuit 430 can also be configured to determine whether an address packet references the same cache line as an address packet stored m queue 420 Control circuit 430 can be configured to compare the cache line referenced by an address packet with the cache lines referenced by address packets m queue 420 If control circuit 430 determines that an address packet references the same cache line as an address packet stored in queue 420, control circuit 430 can be configured to convey the address packet to queue 420 and queue 420 can be configured to store the address packet If control circuit 430 determines that an address packet does not grant access rights to the piocessor and the address packet does not reference the same cache line as an address packet stored in queue 420, control circuit 430 can be configured to conv ey the address packet to queue 410 and queue 410 can be configured to store the address packet It can be noted that address packets that do not grant access rights to the processor can either revoke access rights or neither grant nor revoke access rights Processing circuit 440 can be configured to receive address packets from queue 410 and 420 In one embodiment, queue 410 and queue 420 are strictly first-in-first-out (FIFO) queues In this embodiment, processing circuit 440 can be configured to receive and process the address packet from the head of queue 410 and queue 420 As can be seen, processing circuit 440 can receive addiess packets from the head of queue 410 and queue 420 in an order consistent with the protocol rules described in Fig 1 In one embodiment, processing cncuit 440 can be configured to attempt to receiv e an address packet from the head of queue 410 befoie attempting to receive an address packet from the head of queue 420 If queue 410 is empty or processing cncuit 440 determines that the address packet at the head of queue 420 is older than the address packet at the head of queue 410 then processing circuit 440 can be configured to receive the address packet at the head of queue 420 In other embodiments processing circuit 440 can be configured to deteimme v hethei to leceiv e an addiess packet from queue 410 oi queue 420 in other avs consistent with the piotocol roles As described queue 420 includes those addiess packets that grant access rights and those address packets that reference a same cache line as an earlier addiess packet are stored in queue 420 Queue 410 includes those address packets that do not grant access tights and that do not reference a same cache line as an earlier address packet are stored in queue 420 Since queue 410 and queue 420 are FIFO queues in this embodiment, an addiess packet that does not grant access rights but reference a same cache line as an earhei address packet m queue 420 will be processed subsequent to the earlier address packet Thus, addiess packets can be popped and processed from the head of queue 410 and queue 420 consistent w ith the protocol rules In paiticular, the address packets in queue 410 can be processed prior to older address packets m queue 420 without violating the protocol rules In this manner, many foreign requests that require data from the processoi can be processed before older local requests that are awaiting data since the foreign requests w ill be stoied in queue 410 and the oldei local requests will be stored in queue 420 Consequently, the embodiment illustrated in Fig 4 may advantageously accelerate cache to cache transfers as described abov e in Fig 1 In an alternative embodiment, queue 420 may not correspond to a FIFO queue In this embodiment, address packets from queue 420 can be processed m any order as long as they are not processed before an earlier address packet in queue 410 and as long as they are not processed prior to an earlier address packet in either queue 410 or queue 420 that references the same cache line In this embodiment, processing circuit 440 can be configured to enforce these conditions As a result, processing circuit 440 can be configured to process an address packet from queue 420 prior to processing an older address packet from queue 420 In this manner, local requests that receive data can be processed before older local requests that are awaiting data This embodiment may also advantageously accelerate cache to cache transfers as described above Turning now to Fig. 5, a chart depicting a method for handling address packets is shown Variations on the method are possible and contemplated The method includes receiving an address packet in a processor as indicated by block 500. In block 502, a determination can be made as to whether the address packet grants access rights to the processor If the address packet grants access rights to the processor, the address packet can be stored in a first queue as indicated by block 506 If the address packet does not grant access rights to the processor, a determination can be made as to whether the address packet references a same cache line as an address packet m the first queue as indicated by block 504 If the address packet references a same cache line as an address packet in the first queue, the address packet can be stored m the first queue as indicated by block 506 If the address packet docs not reference the same cache line as an address packet in the first queue, the address packet can be stored in a second queue as indicated by block 508 Turning now to Fig 6, a chart depicting a method for determining if an address packet can be processed is shown Variations on the method are possible and contemplated The method includes receiving an addiess packet in a processor as indicated by block 600 In block 602, a determination can be made as to whether the address packet grants access rights to the processor If the address packet grants access rights to the piocessor, a determination can be made as to whether an older address packet revokes an access light from the processor as indicated m block 604 The chart remains at block 604 until no older address packets remain that revoke an access right from the processoi as indicated If no older addiess packet revokes an access right from the piocessoi , a determination can be made as to whether an older address packet refeiences a same cache line as the addiess packet as indicated by block 606 The chart remains at block 606 until no older address packets remain that reference a same cache line as the addiess packet If no older address packets remain that leference a same cache line as the address packet, the addiess packet can be processed as indicated by block 610 If the address packet does not grant access rights to the piocessor, a determination can be made as to whether an older address packet refeiences a same cache line as the address packet as indicated by block 608 The chart remains at block 608 until no older addiess packets remain that reference a same cache line as the address packet If no older address packets remain that reference a same cache line as the addiess packet, the address packet can be processed as indicated by block 610 Fig 6 illustrates a method of processing address packets consistent ith the protocol rules described in Fig 1 Consequently, the method may be used to accelerate cache to cache transfers and expedite out-of-oidei processing of address packets in a multiprocessor shared memory computer system Turning now to Fig 7. a block diagram illustrating one embodiment of a shared memory computer system with multiple nodes is shown Other embodiments are possible and contemplated Fig 7 depicts memoiy 702a, memory 702b, memory 702c, scalable shared memory (SSM) 700a, SSM 700b, SSM 700c, processor Al 710a, cache Al 720a, processor A2 710b, cache A2 720b, processor Bl 730a, cache Bl 740a, processor B2 730b, cache B2 740b, processor Cl 750a, cache Cl 760a, processor C2 750b, and cache C2 760b SSM 700a, SSM 700b, and SSM 700c are coupled to address bus 708 and data bus 706 Processor Al 710a and processor A2 710b are coupled to SSM 700a and memory 702a via address bus 718 and data bus 716 Processor Bl 730a and processor B2 730b are coupled to SSM 700 and memory 702b via address bus 738 and data bus 736 Processor Cl 750a and processor C2 750b are coupled to SSM 700c and memory 702c via address bus 758 and data bus 756 The various caches are coupled to the various processors as indicated in Fig 7 In Fig 7, memory 702a, processor Al 710a, cache Al 720a, processor A2 710b, cache A2 720b, and SSM 700a can be referred to as comprising node A Memory 702b, processor Bl 730a, cache Bl 740a, processor B2 730b, cache B2 740b, and SSM 700b can be referred to as comprising node B Memory 702c, processor Cl 750a, cache Cl 760a, processor C2 750b, cache C2 760b, and SSM 700c can be referred to as comprising node C Fig 7 lllusnates a multmode shared memory computer system As shown, Fig 7 includes node A, node B, and node C which each comprise multiple processors Other embodiments can include other nodes with any number of processors In addition, one or more nodes can be configured to include a point-to-point switch netwoik or a shared broadcast network instead of the broadcast network address buses and data buses shown In the embodiment of Fig 7, the processors can be configured to employ the cache protocol rules as discussed above in Fig 1 As a result, requests can be processed in any order in the processoi s of Fig 7 consistent with the protocol rules In Fig 7, the SSM s can be configured to leceiv e requests from the processors m then respective nodes An SSM can be configured to convey requests to other SSM's to fulfill requests from processoi s m its own node that cannot be satisfied by the other processors or memory in that node An SSM can also be configured to conv ev requests to the processors and memory m its node m order to return data corresponding to a request from another SSM In this manner, the advantages outlined above in Fig 1 may be achieved both m the individual nodes and in the system as a whole Although the embodiments above have been described in considerable detail other versions aie possible Numerous v ariations and modifications ill become apparent to those skilled in the art once the abov e disclosuie is fully appreciated It is intended that the following claims be interpreted to embrace all such variations and modifications

Claims: WE CLAIM: 1. An apparatus comprising: a system memory coupled to an address bus and a data bus; a first processor coupled to said address bus and said data bus; a first cache coupled to said first processor; a second processor coupled to said address bus and said data bus; a second cache coupled to said second processor; wherein said first processor is configured to convey a first address packet on said address bus, wherein said second processor is configured to receive said first address packet, wherein said second processor is configured to receive a second address packet prior to receiving said first address packet, and wherein said second processor is configured to process said first address packet pπoi to said second address packet in response to said first address packet referencing a different cache line from said second address packet and in response to said second address packet not being configured to cause a first access right to be revoked from said second processor 2 The apparatus of claim 1, wherein said data bus comprises a point-to-point switched network 3 The apparatus of claim 1 , wherein said second processor is configured to process said first address packet prior to said second address packet in response to said first address packet referencing said different cache line, m response to said second address packet being configured to cause a second access right to be granted to said second processor, and in response to said first address packet being configured to cause a third access right to be granted to said processor. 4. The apparatus of claim 1, wherein said second processor is configured to convey data on said data bus in response to processing said first address packet 5. The apparatus of claim 1 , wherein said second processor is configured to process said first address packet subsequent to said second address packet in response to said first address packet leferencmg a same cache line as said second address packet 6. The apparatus of claim 1, wherein said first processor and said second processor are configured to employ a MOSI cache-consistency protocol 7. The apparatus of claim 1, wherein said second address packet is generated by said second processor. 8. A processor comprising: a first queue; a second queue; and a control circuit coupled to said first queue and said second queue; wherein said control circuit is configured to receive a first address packet, wherein said control circuit is configured to store said first address packet in said first queue in response to said first address packet being configured to cause an access right to be granted to said processor, wherein said control circuit is configured to store said first address packet in said first queue in response to said first address packet referencing a same cache line as a second address packet stored in said first queue, wherein said control circuit is configured to store said first address packet in said second queue in response to said first address packet not being configured to cause said access right to be granted to said processor and in response to said first address packet not referencing said same cache line as said second address packet. 9. The processor of claim 8, further comprising: a processing circuit coupled to said first queue and said second queue, wherein said processing circuit is configured to process said first address packet prior to processing said second address packet in response to said first address packet being stored in said second queue. 10. The processor of claim 9, wherein said processing circuit is configured to process said first address packet prior to processing said second address packet in response to said first address packet being stored in said first queue and in response to said first address packet not referencing said same cache line as said second address packet. 1 1. The processor of claim 9, wherein said second queue includes a third address packet that, wherein said processing circuit is configured to process said first address packet prior to processing said third address packet in response to said first address packet being stored in said second queue and in response to said first address packet not referencing said same cache line as said third address packet. 12 The processor of claim 11, wherein said processing circuit is configured to process said third address packet prior to processing said first address packet m response to said first address packet being stored in said first queue 13 The processor of claim 9, wherein said processor is configured to convey data to another processor in response to said first address packet 14 A method comprising receiving a first address packet in a processor, receiving a second address packet in a processor prior to said receiving said first address packet, determining whether said second address packet is configured to cause a first access right to be revoked from said processor, determining whether said first address packet references a same cache line as said second address packet, and processing said first address packet prior to said second address packet in response to said second address packet not being configured to cause said first access right to be revoked from said processor and in response to said first address packet not referencing said same cache line as said second address packet 15 The method of claim 14, further comprising processing said first address packet prior to said second address packet in response to said first address packet being configured to cause a second access right to be granted to said processor, in response to said first address packet not leferencmg said same cache line as said second address packet, and in response to said second address packet being configured to cause a third access right to be granted to said piocessoi 16 The method of claim 15, fuither comprising processing said first address packet subsequent to said second address packet m response to said first addiess packet referencing said same cache line as said second address packet The method of claim 14, further comprising conveying data from said processor in response to processing said first address packet The method of claim 14, further comprising storing said first address packet in a first queue in response to said first address packet being configured to cause a second access right to be granted to said processor, storing said first address packet in said first queue m response to said first address packet referencing said same cache line as said second address packet, and storing said first address packet in a second queue m response to said first address packet not being configured to cause said second access right to be granted to said processor and in response to said first address packet not referencing said same cache line as said second address packet A computer system comprising a fust processor, a fust cache coupled to said first processor, a second processor, a second cache coupled to said second piocessor wherein said first processor is configured to leceive a local request wherein said first processor is configured to receiv e a foreign request from said second processor subsequent to receiving said local lequest, and wheiein said first piocessoi is configured to convey data corresponding to said foreign request prior to leceiv mg data corresponding to said local request A computer system comprising a first piocessor a fust cache coupled to said first processor a second piocessor, a second cache coupled to said second processor, wherein said first processor is configured to receive a first local request prior to receiving a second local request, and wherein said first processor is configured to process said second local request prior to processing said first local request in response to receiving data corresponding to said second local request

Inventors: CYPHER ROBERT, HETHERINGTON RICKY C, KUTTANNA BELLIAPPA, CYPHER, ROBERT, HETHERINGTON, RICKY, C., KUTTANNA, BELLIAPPA
Applicants: SUN MICROSYSTEMS INC, SUN MICROSYSTEMS, INC.
Application year: 2000
Main classification: G06F12
IPC codes: G06F12, G06F15