INTERPOLATOR HAVING DUAL TRANSISTOR RANKS AND RATIOMETRIC CONTROL

Abstract: An interpolator utilizes two ranks of transistors to generate a plurality of interpolator currents within the confines of a low power supply voltage. The first rank of transistors are underdriven, thereby generating a plurality of partially switched currents having shallow Gaussian-shaped functions. The partially switched currents are then spatially amplified by the second rank of transistors to reduce the overlap of the currents from adjacent transistors. The first rank of transistors are driven ratiometrically by the difference of two control currents, thereby eliminating errors caused by inaccurate resistors and current sources. A biasing op-amp senses the interpolator currents and servos the first rank of transistors, thereby regulating the interpolator currents to a value determined by a reference voltage which is temperature compensated. Thus, the biasing op-amp automatically compensates for temperature variations and manufacturing uncertainties in devices throughout the entire interpolator. A current generator utilizes a current mirror scheme and current replication techniques to cancel transistor alpha effects, thereby generating precise ratiometric drive currents from a low power supply voltage.

Description: INTERPOLATOR HAVING DUAL TRANSISTOR RANKS AND RATIOMETRIC CONTROL BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates generally to interpolators, and more particularly, to interpolators having two ranks of transistors and ratiometric control. 2. Description of the Related Art A variable gain amplifier using a continuously interpolated attenuator includes an attenuator network, a series of transconductance (gm) stages, an interpolator, a main amplifier, and associated support circuitry. The attenuator receives an input signal and generates a series of progressively attenuated signals at a series of tap points. Each gm stage is coupled to one of the tap points to receive one of the attenuated signals. The outputs from the gm stages are connected together and taken to the main amplifier so that the overall output signal is the sum of the output signals from all of the gm stages. The interpolator steers a bias current to the gm stages in response to a control signal such that, when the highest gain is selected, the gm stage closest to the input end of the attenuator is active, and the remaining gm stages are effectively off. As the gain is reduced, the interpolator steers the bias current to gm stages further away from the input end of the attenuator, thereby selecting gm stages that receive progressively attenuated versions of the input signal. Some examples of interpolators used in variable gain amplifiers having continuously interpolated attenuators are disclosed in U.S. Patent Nos. 5,684,431 and 5,077,541, both having a common inventor with the present application. Another example of an interpolator is disclosed in U.S. Patent No. 5,432,478 also having a common inventor with the present application. These patents are incorporated herein by reference. SUMMARY In one aspect of the present invention, two ranks of transistors are utilized to generate interpolator currents. An input signal is applied to the first rank of transistors which generate a set of partially switched currents which greatly overlap the currents generated by adjacent transistors. The second rank of transistors spatially amplifies the partially switched currents, thereby reducing the overlap of the currents from adjacent transistors. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a schematic diagram of a first embodiment of an interpolator constructed in accordance with the present invention. FIG. 2 is a graph showing the partially switched currents generated by an exemplary 10-transistor rank of partially switched transistors in accordance with the present invention. FIG. 3 is a graph showing final interpolator output currents corresponding to the partially switched currents shown in FIG. 2 and generated by a second rank of 10 transistors in accordance with the present invention. FIG. 4 is a schematic diagram showing more details of an embodiment of a partially switched interpolator layer constructed in accordance with the present invention. FIG. 5 is a simplified schematic diagram of a practical embodiment of an interpolator constructed in accordance with the present invention. FIG. 6 is a simplified schematic diagram of an embodiment of precision ratiometric cuπent generator constructed in accordance with the present invention. FIG. 7 is a schematic diagram showing more details of the circuit of FIG. 6 and illustrating a technique for generating a reference current in accordance with the present invention. FIG. 8 is a schematic diagram of an embodiment of a change-over switch for use with an interpolator and set-point interface in accordance with the present invention. FIG. 9 is a schematic diagram of an embodiment of a change-over switch in accordance with the present invention. FIG. 10 is a schematic diagram of an embodiment of an interpolator layer in accordance with the present invention adapted for use with the change-over switch circuit of FIG. 9. DETAILED DESCRIPTION The present invention provides several techniques for improving the operation of an interpolator. A first aspect of the present invention is the use of two ranks of transistors to generate the interpolator currents. The voltages applied to the first rank of transistors are of a small amplitude, and therefore, this section generates a set of currents which are partially switched. That is, they have shallow Gaussian-shaped functions which greatly overlap the currents generated by adjacent transistors. The partially switched currents are subsequently "spatially amplified" by the second rank of transistors. This process reduces the overlap of the currents from adjacent transistors. An advantage of using two ranks of transistors is that allows the use of a low power supply voltage for all sections of the complete interpolator. Another key aspect of the present invention is the use of two control currents to drive the first rank of transistors ratiometrically. This improves the accuracy of the interpolator because the position of the centroid of the interpolator currents is determined only by the ratio of these two currents and is independent of the specific "scaling" (which may have errors caused by inaccurate resistors and current sources) in the first interpolator layer. A further aspect of the present invention is the use of a biasing servo-loop to define the value of the final interpolator output currents. An error amplifier senses the total interpolator cirrrents and biases the first rank of transistors, thereby regulating the interpolator currents to a precise value determined by a reference voltage. The reference voltage is typically made proportional to absolute temperature (PTAT) to stabilize the gm of the cells driven by the interpolator currents. The biasing servo-loop automatically compensates for temperature variations and manufacturing uncertainties in devices throughout the entire interpolator. For example, the biasing op-amp can compensate for low beta in current mirror transistors that might be coupled between the first and second ranks of transistors. Yet another aspect of the present invention is a precision current generator which utilizes a high-accuracy cuπent minor scheme and current replication techniques to cancel transistor alpha and early voltage effects, thereby generating precise ratiometric drive currents from a low power supply voltage. FIG. 1 is a schematic diagram of a first embodiment of an interpolator constructed in accordance with the present invention. The interpolator shown in FIG. 1 includes a first layer having a first rank of n transistors QPS1, QPS2, . . . QPSn, and a second layer having a second rank of n transistors Ql, Q2, . . . Qn. The first layer includes a plurality (n-1) of base resistors R B connected between the bases of adjacent transistors, a plurality (n-2) of current sources connected to the bases of the first rank of transistors for providing currents I B thereto, and a current source Ij-i connected to emitter node El at which the emitters of the first rank of transistors are commonly connected. The invention can be implemented with different numbers (n) of transistors with different device polarities, and using CMOS rather than bipolar devices, as discussed below. The first rank of transistors QPS1, QPS2, . . . QPSn, generate a plurality of currents Ipsi, Ips2 > • • • Ipsn, respectively, in response to a control voltage V AB applied differentially across terminals A and B. As this control voltage is swept from one end of its range to the other, the transistors in the first rank are partially switched on and then off in sequence starting at one end of the interpolator such that the current I EI is steered to different transistors in sequence. There is some overlap between adjacent transistors, and therefore, the current I E I is divided between the cuπents Ipsi, Ips2, ■ • • Ipsn in varying amounts. This produces what can be described as a "centroid" that moves back and forth along the attenuator as the control voltage is varied up and down. That is, maximum conduction of I E I is moved from left to right, with a linear relationship to the voltage V AB - In prior art interpolators, I B R B was moderately large, and the switching if I EI into the n transistors was fairly complete. This requires a rather large peak swing in the voltage V A B, which cannot be accommodated within the constraints of a 2.7 volt supply voltage. In the circuit of FIG. 1, however, rather than driving the first layer with enough voltage to fully switch the first rank of transistors on and off, the first rank of transistors are underdriven, thereby generating currents I PS1 , Ips 2 , • ■ • Ipsn which are even more partially switched. That is, the Gaussian-shaped function of each of the currents Ipsi, Ips2, • • • Ipsn (as a function of the control voltage) are very shallow and broad as compared to an interpolator in which the transistors are more fully switched. Thus, the first layer is referred to as a partially switched interpolator layer. By underdriving the first rank of transistors, the total drive voltage required to move the centroid from one end of the interpolator to the other can be reduced. For example, whereas about 5 volts would typically be required to fully switch an eight-stage interpolator from one end to the other, a 12 stage interpolator can be partially switched according to the present invention with a total control voltage swing of only about 1.5 volts. However, if the partially switched currents Ipsi, Ips2, ■ • • Ipsn were used to drive the gm stages of a variable gain amplifier using a continuously inteφolated attenuator, there would be no clear selection of one gm stage over another because the current pulses in the partially switched currents overlap too much. Therefore, a second layer is included to "spatially amplify" the partially switched currents. The second layer includes a plurality of resistors R E connected between the collectors of the first rank of transistors and a power supply common terminal GND to first convert the partially switched currents to voltages. The base of each of the second rank of transistors Ql, Q2, . . . Qn is connected to a corresponding one of the collectors of the first rank of transistors. The emitters of the second rank of transistors are connected together at emitter node E2 which receives a current I E2 from a second cuπent source connected thereto. The final interpolator output currents I \ , I 2 , . . . I n are generated at the collectors of Ql, Q2, ... Qn, respectively. The transconductance of the second rank of transistors operating on the voltage across the load resistors R LE causes a spatial amplification that reduces the current overlap between adjacent transistors. That is, the shapes of the interpolator currents Ii, I 2 , . . . I n are elongated and narrowed as compared to the partially switched currents I PSI , Ips 2 , • • • Ipsn, taking on a narrower Gaussian form. This spatial amplification can be better understood with reference to FIG. 2, which shows the partially switched currents Ipsi, Ips2, • • ■ Ipsn for a 10-stage rank of partially switched transistors, and FIG. 3, which shows the corresponding interpolator currents I \ , I , . . . I n . The currents shown in FIGS. 2 and 3 are shown as function of a voltage set-point signal V SET which is related to the control voltage between terminals A and B as described below. As is apparent from FIGS. 2 and 3, a two-layer interpolator in accordance with the present invention generates inteφolator currents having the required Gaussian shape and optimal overlap, but does so within the confines of a low power supply voltage. FIG. 4 is a schematic diagram showing details of an embodiment of a partially switched inteφolator layer constructed in accordance with the present invention now having a ratiometric response. The circuit of FIG. 4 is implemented with a first rank of NPN transistors QPS1, QPS2, . . . QPSn having their emitters connected together at emitter node El for receiving the current I EI • A plurality of n current sources are implemented as PNP transistors QCS1, QCS2, . . . QCSn, each having its emitter connected to a positive power supply Vpos through a resistor R E , and its collector connected to the base of one of the transistors in the first rank. The bases of the current source transistors QCS1, QCS2, . . . QCSn are connected together and to the emitter of a PNP transistor Q55. The collector of Q55 is grounded, and its base is connected to the emitter node El . An important feature of the circuit of FIG. 4 is that the input terminals A and B of the first rank of transistors are driven ratiometrically by currents (l+X)Iχ and (l-X)Iχ, where X is a dimensionless modulation factor that varies between +1 and -1, and Iχ is a fixed current. In the absence of a ratiometric drive, the product of the base resistances Rβ and the currents Iβ determine the scaling sensitivity of the system to the voltage V AB - Therefore, the accuracy depends on the absolute value of both R B and Iβ. However, by using a current mode ratiometric technique, the system responds such that the centroid of the inteφolator currents is determined only by the dimensionless factor X defining the complementary currents, and not by the absolute values of Is, R B or even Iχ. The absolute scaling can then be introduced in a cuπent generator that generates the currents (l+X)Iχ and (l-X)Iχ as described below. In operation, the currents I E ι, (l+X)Iχ, and (l-X)Iχ pull the voltage at node El downward, causing transistor Q55 to drive the current source transistors QCS1, QCS2, . . QCSn into conduction until the currents (1+X)I X and (l-X)Iχ are completely absorbed by the n current source transistors. Since (l+X)Iχ + (l-X)Iχ is simply 2Iχ, the currents I B each settle to a value of 2Iχ/n. When the modulation factor X=0, and for the illustrative case where n is an odd number, the base of the transistor in the center of the first rank is at a higher voltage than all the remaining transistors, and therefore, the highest cuπent flows through the center transistor. Thus, the centroid of action is located at the center of the inteφolator, with smaller cuπents flowing in adjacent transistors. The value of R B determines how strong the partial switching process is. As R B increases, the more strongly the center transistor selects I E I over the other transistors. However, R B does not affect the position of the centroid. (If n is even, the bases of the two center transistors are at the same voltage, and the effective centroid is located between the two central transistors when X=0.) At one extreme, when X=l, a current equal to 2Iχ flows entirely from terminal A, the base of QPSn is at the highest potential, and more of I EI flows through QPSn than any of the other transistors in the first rank, thereby moving the centroid all the way to the right-hand end of the inteφolator. Again, the location of the centroid does not depend on the value of I B , R B , or Iχ, only on the value of the modulation factor X. Likewise, when X=l, the centroid moves to the left-hand end of the network. The position of the centroid is a linear function of the modulation factor X. FIG. 5 is a simplified schematic diagram of a practical embodiment of an inteφolator constructed in accordance with the present invention. The circuit of FIG. 5 is adapted for fabrication using a process that provides high quality NPN transistors, but lesser quality PNP transistors. Therefore, both the first and second ranks of transistors are fabricated with NPN transistors and are coupled together through PNP cuπent minors of relatively poor accuracy. The circuit of FIG. 5 includes a first layer which is in most respects the same as that shown in FIG. 4, but emitter node El, rather than being connected to a current source I EI , is connected to the output terminal of a biasing amplifier 12 to receive a drive signal DRV that sets the cuπent through node El as described below. The circuit of FIG. 5 also includes a second layer much like that shown in FIG. 1, but emitter node E2 is connected to GND through a resistor R EE - Resistors R LE are connected to a node 14 which is connected to GND through a resistor Rl and diode Dl . The partially switched cuπents I PS ι, Ips 2 , • ■ • Ipsn are coupled to the bases of the second rank of transistors through cuπents minors formed by transistor pairs QA1/QB1, QA2/QB2, . . . QAn/QBn. An emitter follower transistor can optionally be connected in series between each of the cunent minors and the base of the conesponding transistor in the second rank to prevent the shape of the inteφolator cunents from depending on the betas of the NPN transistors in the second rank. The noninverting input terminal of biasing op-amp 12, which is principally a transconductance amplifier, is connected to node E2 to sense the cunent I E2 which is the sum of the final inteφolator cunents l \ , I 2 , . . . I n . The inverting input terminal of amplifier 12 receives a reference voltage V PTT - This voltage is usually PTAT and determines the transconductance of the gm cells used in the inteφolating amplifier section. Amplifier 12 drives the emitter node El of the first layer, so as to regulate the value of the cuπent I E2 to a precise value V PT T/R EE - Thus, a well-defined value is established for the inteφolator currents regardless of device tolerances. Another advantage of using a biasing servo scheme as shown in FIG. 5 is that it automatically compensates for the finite beta in the PNP cunent minor transistors. If the ratiometric drive cuπents (l+X)Iχ and (l-X)Iχ are stable over temperature, the strength of the partial switching action of the first layer will change over temperature. If the inteφolator of FIG. 5 is to be used to drive the gm stages of a variable gain amplifier using a continuously inteφolated attenuator, the reference voltage V PTT can be adjusted to compensate for two additional effects in the gm stages. First, a conection can be added to V PTT to compensated for the ohmic resistances of the differential transistors in the gm stages. This can be accomplished by generating V P T with a reference cell that includes transistors that have the same ohmic resistance imperfections as those used in the gm stages. Second, V PT τ can be conected to compensate for the finite beta of the second rank of transistors, and also for the alpha between the emitter nodes and collectors of the differential transistors in the gm stages. FIG. 6 is a schematic diagram of a first embodiment of a precision cunent generator for generating the ratiometric cunents (l+X)Iχ and (l-X)Iχ in accordance with the present invention. The circuit of FIG. 6 includes a transistor Q10 which has its emitter connected to GND through a resistor RIO. An op-amp 15 receives the set-point signal V SET at its noninverting input. The inverting input of op-amp 15 is connected to the emitter of Q10, and its output is connected to the base of Q10 so that the voltage input at V SET is replicated across RIO, thereby generating a conesponding cunent in the emitter of Q10. This cunent is then reduced by the alpha of Q10 and becomes the first output cunent (l+X)Iχ at the collector of Q10. A transistor Ql 1 and resistor Rl 1 are connected in parallel with Q10 and RIO to replicate the first output cunent. This replication cunent from the collector of Ql 1 is summed with a reference cunent I REF generated by cunent source 22. The collector of Ql 1 is also connected to the input terminal of a high gain cuπent minor 16. The second output cunent (l-X)Iχ is output from the cunent minor. When the input V SET is zero, Q10 and Ql 1 are off, and all of I REF is provided as the output cunent to terminal IOP through the cunent minor. As V SET increases, the cunent through Q10 also increases and is provided to the first output terminal IOP, while the cunent through Ql 1 diverts an increasing amount of I REF from the cunent minor, thereby reducing the second output cunent to IOP. Because the outputs are ratiometric, the alpha of Q10 is inconsequential as long as it is replicated in the opposite leg through Ql 1, which has the same alpha. However, the cunent minor 16 must have a very high gain (i.e., must be beta-immune) to avoid introducing an additional enor into the second output cunent. The reference cuπent I REF should also be coπected for the alpha of Ql 1. Thus, the circuit shown in FIG. 6 provides an accurate pair of ratiometric cunents, and it requires less power supply voltage than a fully differential structure would require. FIG. 7 is a schematic diagram showing a more detailed embodiment of the circuit of FIG. 6 and illustrating a technique for generating the reference cunent I REF in accordance with the present invention. The cunent minor 16 is implemented with transistors Q15, Q16 and Q17. The reference cunent I REF is generated by a cunent minor which includes transistors Q12 and Q13, and degeneration resistors R12 and R13. A pre-bias cunent source is connected to the bases of Q12 and Q13 to provide I PB which is most of the base cunent required by Q12 and Q13. The remaining base cunent is provided by an op-amp 18 which has its inputs connected to the collectors of Q12 and Ql 3 so as to cancel the effects of the input cuπents to the op-amp. Thus, the cunents through Q12 and Q13 are precisely balanced. A reference cunent, which is input to the cunent minor formed by Q12 and Q13, is provided by a transistor Q14 which has its emitter connected to GND through R14. Resistor R14 has the same resistance as RIO and Rl 1. The base of transistor Q14 is driven by another op-amp 20 which receives a reference voltage V REF at its noninverting input and has its inverting input connected to the emitter of Q14. Thus, the voltage across R14 is forced to equal V EF , which introduces the scaling for the cunent generator, and consequently, for the inteφolator as described above. The alpha of Q14 replicates that of Q10 and Ql 1, so I REF is automatically conected for the alpha of Ql 1. In some applications, it is very useful to be able to switch the direction in which the output cunents (l+X)Iχ and (l-X)Iχ change in response to changes in V SET - This can be accomplished by using a change-over switch between the inteφolator and the setpoint interface. An aπangement for implementing a change-over switch is shown in FIG. 8 in which an inteφolator 24 and setpoint interface 26 are shown in simplified form. The changeover switch includes a layer of NPN transistors QA through QD which are driven by a switching control voltage Vsw such that the output cunents (l+X)Iχ and (l-X)Iχ are steered to IOP and ION of the inteφolator, respectively, when the outer transistors QA and QD are on. When the inner transistors QB and QC are on, the output cunents are steered to ION and IOP of the inteφolator, respectively. Switching of these cunents is essentially complete when Vsw is sufficiently large (>180mV). The aπangement of transistors QA-QD shown in FIG. 8 is a well-known way of switching the direction of two cunents, but it suffers from at least two major problems. First, the layer of transistors take up an excessive amount of power supply voltage. Second, the alpha of the transistors QA-QD reduce the accuracy of the circuit by as much as a few percent. A better technique for switching the direction of the cunents from the setpoint interface is illustrated in FIG. 9 which is a schematic diagram of an embodiment of a circuit in accordance with the present invention for switching the direction of the output cunents from a setpoint interface. The circuit of FIG. 9 includes a layer of PNP transistors QE, QF, QG, and QH. The emitters of QE and QG are connected to IOP of the inteφolator 24, while the emitters of QF and QH are connected to ION of the inteφolator. The collectors of QE and QF are connected to IOP of the setpoint interface 26, while the collectors of QG and QH are connected to ION of the setpoint interface. The circuit of FIG. 9 also includes four cunent sources 28, 30, 32, and 34, each of which is connected to a conesponding one of the bases of QE-QH to provide a base drive cunent I E , I F , I G , and I H that can be turned on or off. The output cunents from the setpoint interface are steered by turning on either I E and I H or I F and I G depending on the desired direction of cuπent flow. By turning I E and IH on and I F and I G off, the cunent from the terminals IOP and ION of the set-point interface is steered to the terminals IOP and ION, respectively, of the inteφolator. Likewise, by turning I F and I G on and I E and I H off, the cunent from the terminals IOP and ION of the set-point interface is steered to the terminals ION and IOP, respectively, of the inteφolator. The cuπent sources are designed so that the cunents I E , I F , I G , and I H cause their respective transistors to heavily saturate when turned on, thus, they take up very little of the power supply voltage. A further advantage is that there is no longer any alpha loss because the cunent flowing through the collector of each transistor flows through its emitter. When the cunent steering transistors QE-QH are implemented as silicon-on-insulator (SOI) devices, enors caused by the additional cuπents to the substrate when the devices saturate are eliminated. A further refinement in accordance with the present invention is illustrated in FIG. 10 which is a schematic diagram of another embodiment of a partially switched inteφolator layer constructed in accordance with the present invention. If the change-over switch circuit of FIG. 9 were used directly with the inteφolator layer of FIG. 4, the base cuπents I E , I F , I G , and I H would introduce an eπor into the ratiometric cunents (l+X)Iχ and (l-X)Iχ. The circuit of FIG. 10 is similar to that of FIG. 4 except that the outer resistors R E are now replaced by resistors having a resistance of R E /2, and the outer cunent source transistors QCS1 and QCSn have emitter areas "2e" which are twice as large as those of the other cunent source transistors which have emitter areas "e". In the circuit of FIG. 4, each resistor RE canies a cunent equal to I REF /Π. Therefore, if the cunents I E , IF, IG, and I H in FIG. 9 are made equal to I REF ΔI+2, the outer cunent source transistors in the circuit of FIG. 10 can absorb the base cunents through QE-QH of FIG. 9 without affecting the operation of the rank of partially switched transistors QPSl-QPSn in FIG. 10. In a prefened embodiment, the cunent sources 28-34 in FIG. 9 and 22 in FIG. 6 are connected to a common reference circuit so that the cunents I E , I F , I G , and I H have similar characteristics to I REF - Although the embodiments described herein are implemented with bipolar junction transistors (BJT), other devices can be used. The term transistor, as used herein, refers to any device having a control input for controlling the flow of cunent. Therefore, the term "base" refers to the base of a BJT as well as the gate of a field-effect transistor (FET). Other teπτιs specific to BJT transistors are also understood to refer to the conesponding elements of other types of control devices, e.g., a common emitter node refers to a common source node, a collector conesponds to a drain, etc. Having described and illustrated the principles of the invention in a prefened embodiment thereof, it should be apparent that the invention can be modified in anangement and detail without departing from such principles. I claim all modifications and variations coming within the spirit and scope of the following claims.

Claims: CLAIMS 1. An inteφolator comprising: a first rank of transistors for generating a plurality of partially switched cunents responsive to a control signal; and a second rank of transistors coupled to the first rank of transistors for spatially amplifying the partially switched cunents, thereby generating a plurality of inteφolator cunents. 2. An inteφolator according to claim 1 further including a cunent generator coupled to the first rank of transistors for generating the control signal as a ratiometric signal. 3. An inteφolator according to claim 1 further including a series of cunent minors coupled between the first and second ranks of transistors. 4. An inteφolator according to claim 1 further including an amplifier circuit coupled to the first and second ranks of transistors to drive the first rank of transistors, thereby regulating the inteφolator cunents. 5. An inteφolator according to claim 4 wherein the amplifier circuit is adapted to compensate the inteφolator cunents for temperature variations. 6. An inteφolator according to claim 4 wherein the amplifier circuit is adapted to compensate the inteφolator cunents for the ohmic resistances of a plurality of gm stages which can be coupled to receive the inteφolator cunents. 7. An inteφolator according to claim 4 wherein the amplifier circuit is adapted to compensate the inteφolator cuπents for the gain of the second rank of transistors. 8. An inteφolator according to claim 1 wherein the first rank of transistors is part of a first inteφolator layer; the emitters of the first rank of transistors are coupled together at a first emitter node; and the first inteφolator layer further includes: a plurality of base resistors, wherein the bases of adjacent transistors in the first rank are coupled together through one of the base resistors, and a plurality of variable cunent sources, each cunent source coupled to the base of a conesponding transistor in the first rank. 9. An inteφolator according to claim 8 further including a cunent source coupled to the first emitter node. 10. An inteφolator according to claim 9 wherein: the plurality of variable cunent sources includes a plurality of cunent source transistors having their bases coupled together; and the first inteφolator layer further includes a base drive transistor coupled between the bases of the cunent source transistors and the first emitter node to control the plurality of cuπent source transistors responsive to a drive signal received at the first emitter node. 11. An inteφolator according to claim 1 wherein: the second rank of transistors is part of a second inteφolator layer; the emitters of the second rank of transistors are coupled together at a second emitter node; and the base of each transistor in the second rank is coupled to the collector of a conesponding transistor in the first rank to receive a conesponding one of the partially switched cunents. 12. An inteφolator according to claim 11 further including a plurality of cunent minors, wherein the base of each transistor in the second rank is coupled to the collector of a conesponding transistor in the first rank through one of the cunent minors. 13. An inteφolator according to claim 11 further including a plurality of emitter follower transistors, wherein the base of each transistor in the second rank is coupled to the collector of a conesponding transistor in the first rank through one of the emitter follower transistors. 14. An inteφolator according to claim 11 wherein the second inteφolator layer further includes a plurality of resistors, each resistors coupled between the base of one of the transistors in the second rank and the second emitter node. 15. An inteφolator according to claim 11 further including a cunent source coupled to the second emitter node. 16. An inteφolator according to claim 8 wherein: the second rank of transistors is part of a second inteφolator layer; the emitters of the second rank of transistors are coupled together at a second emitter node; the base of each transistor in the second rank is coupled to the collector of a conesponding transistor in the first rank to receive a conesponding one of the partially switched cunents; and the inteφolator further includes an amplifier having a first input terminal coupled to the second rank of transistors to sense the inteφolator cunents, and an output terminal coupled to the first inteφolator layer for controlling the partially switched cunents responsive to the inteφolator cunents, thereby regulating the inteφolator cunents. 17. An inteφolator according to claim 16 wherein the amplifier includes a second input terminal coupled to receive a reference voltage that is proportional to absolute temperature. 18. An inteφolator according to claim 17 wherein the reference voltage is conected so as to compensate for the ohmic resistances of a plurality of gm stages which can be coupled to receive the inteφolator cunents. 19. An inteφolator according to claim 17 wherein the reference voltage is conected so as to compensate for the gain of the second rank of transistors. 20. An inteφolator according to claim 17 wherein the output terminal of the amplifier is coupled to the first emitter node. 21. A method of generating a plurality of inteφolator cunents comprising: generating a plurality of partially switched cunents responsive to a control signal; and spatially amplifying the partially switched cunents, thereby generating the inteφolator cunents. _5 22. A method according to claim 21 further including generating the control signal as a ratiometric signal. 23. A method according to claim 21 further including: 0 sensing the inteφolator cunents; and controlling the partially switched cunents responsive to the inteφolator cuπents, thereby regulating the inteφolator cunents. 24. A method according to claim 23 further including compensating the 5 inteφolator cunents for temperature variations. 25. A method according to claim 23 further including compensating the inteφolator cunents for the ohmic resistances of a plurality of gm stages which receive the inteφolator cunents. 26. A method of operating a first inteφolator layer including: a first rank of transistors having their emitters coupled together at a first emitter node; a plurality of base resistors, wherein the bases of adjacent transistors in the first rank are coupled together through one of the base resistors; and a plurality of cunent sources, each cunent source coupled to the base of a conesponding transistor in the first rank; the method comprising: underdriving the first inteφolator layer, thereby generating a plurality of partially switched cunents; and spatially amplifying the partially switched cunents, thereby generating a plurality of inteφolator cunents. 27. A method according to claim 26 wherein spatially amplifying the partially switched cunents includes coupling a second inteφolator layer to the first inteφolator layer. 28. An inteφolator comprising: means for generating a plurality of inteφolation cunents responsive to a control signal; and means for spatially amplifying the inteφolator cunents. 29. An inteφolator according to claim 28 further including means for generating the control signal as a ratiometric signal. 30. An inteφolator according to claim 28 further including means for regulating the inteφolator cunents. 31. A ratiometric cunent generator comprising: a first transistor for generating a first output cuπent responsive to an input signal; a second transistor coupled in parallel with the first transistor to generate a replication cunent responsive to the input signal; an cunent source coupled to the second transistor to provide a reference cuπent thereto; and a cunent minor coupled to the second transistor for generating a second output cunent responsive to the replication cunent. 32. A cunent generator according to claim 31 further including an op-amp coupled to the first transistor to drive the first transistor responsive to the input signal. 33. A cunent generator according to claim 31 wherein the first and second transistors have substantially identical alphas. 34. A cunent generator according to claim 31 wherein the cunent source includes: a second cunent minor having an output terminal coupled to the second transistor; and a third transistor coupled to an input terminal of the second cunent minor for generating the reference cunent responsive to a reference signal. 35. A cunent generator according to claim 34 wherein the second cunent minor further includes an operational amplifier having a first input terminal coupled to the output terminal of the second cunent minor, a second input terminal coupled to the input terminal of the second cunent minor; and an output terminal coupled to drive the cunent minor so as to match the cuπents from the input and output terminals of the second cunent minor. 36. A cunent generator according to claim 31 wherein: the first transistor has an emitter coupled to a first power supply terminal through a first resistor, a base coupled to receive the input signal, and a collector for providing the first output cunent; and the second transistor has an emitter coupled to the first power supply terminal through a second resistor, a base coupled to the base of the first transistor, and a collector for providing the replication cunent. 37. A cunent generator according to claim 36 wherein the cunent source includes: a third transistor having a base, an emitter coupled to a second power supply terminal, and a collector coupled to the collector of the second transistor; a fourth transistor having a base coupled to the base of the third transistor, an emitter coupled to the second power supply terminal, and a collector coupled to receive a reference cunent. 38. A cuπent generator according to claim 37 wherein the cunent source further includes an op-amp having a first input terminal coupled to the collector of the third transistor, a second input terminal coupled to the collector of the fourth transistor, and an output terminal coupled to the bases of the third and fourth transistors. 39. A cunent generator according to claim 38 wherein the cunent source further includes a second cunent source coupled to the bases of the third and fourth transistors to provide a pre-bias cunent thereto. 40. A cunent generator according to claim 38 wherein the cunent source further includes a fifth transistor having a collector coupled to the collector of the fourth transistor to provide the reference cunent thereto, wherein the alpha of the fifth transistor matches the alpha of the second transistor. 41. A cunent generator according to claim 40 wherein the fifth transistor has a base coupled to receive a reference signal for setting the value of the reference cuπent. 42. A method for generating a first output cunent and a second output cunent, wherein the first and second output cunents vary ratiometrically in response to an input signal, the method comprising: generating the first output cunent responsive to the input signal; replicating the first output cunent, thereby generating a replication cunent; generating a reference cunent; and summing the replication cunent with the reference cunent, thereby generating the second output cuπent. 43. A method according to claim 42 further including coupling the second output cunent through a cunent minor. 44. A method according to claim 42 wherein: generating the first output cunent includes driving a first transistor with the input signal; and replicating the first output cunent includes replicating the alpha of the first transistor in the replication cuπent. 45. A method according to claim 44 wherein generating the reference cunent includes replicating the alpha of the first transistor in the reference cunent. 46. A method according to claim 42 wherein generating the reference cunent includes generating the reference cunent responsive to a reference signal, thereby setting the scaling of the first and second output cunents.

Inventors: GILBERT BARRIE, GILBERT, BARRIE
Applicants: ANALOG DEVICES INC, ANALOG DEVICES, INC.
Application year: 2000
Main classification: H03G
IPC codes: H03G1, H03H11