FSK demodulation

Abstract: In a method for demodulating an analog FSK signal (FSKin), a current sample (Id(k);Id i ) of the downconverted and digital inphase component is multiplied with a previous sample (Qd(k-1);Qd i-1 ) of the downconverted an digital orthogonal phase component. The product thereof is subtracted from the product obtained by multiplying a current sample of said orthogonal phase component (Qd(k); Qd i ) with a previous sample (Id(k-1); Id i-1 ) of said inphase component. Said current and said previous samples of said inphase and said orthogonal phase components are spaced apart by the digital baseband signal period. In a variant method said current sample and said previous sample of said inphase and orthogonal phase component are spaced apart by an integer fraction (n) of said digital baseband signal period,whereby the steps of said method are repeated, thereby further adding consecutive values of the result R i ). A demodulator for performing this method and a receiver including such a demodulator are described as well.

Description: The present invention relates to a method for demodulation of FSK signals and a demodulator for performing such a method, as are respectively described in the non-characterizing portion of claim 1 and claim 7. Such a method and device are already known in the art, e.g. from " US patent 6038268 ". Therein, a direct conversion FSK signal radio receiver is shown whereby, after having deduced from the received signal, the separated two-axis components, processing is done on these components. This operation thereby consists of a differentiation and a multiplication with the other, non-differentiated component, the results of both multiplications then being subtracted such as to obtain the demodulated signal. A drawback of this method is however its sensitivity to noise. Indeed, by operating on the instantaneous value of the incoming signal, and its deduced components, the demodulation method is perturbated by all noise present in the baseband signals. As a consequence the instantaneous frequency represented by the two noisy baseband signals differs strongly from the one represented by the noise-free signals. An FSK receiver related to the present invention is known from US 4647864. The present invention, however, differs by using a fixed oversampling rate together with integration over a symbol period. The receiver uses an oversampling rate which is initially high, but which is gradually decreased. The present invention maintains some of the advantages of this receiver, but has the advantage of simplicity. Another related receiver is known from US 4612509. The present invention, however, differs by using digital processing, oversampling and integration over a symbol period. This had the advantages of linearity and noise immunity. According to the invention, this object is achieved due to the fact that said method includes the steps as described in the characterising portion of claim 1 and that said device is further adapted as is described in the characterising portion of claim 6. In this way, noise immunity is obtained in two ways : firstly the signal is digitized, allowing for more accurate processing on the digital signal, and secondly the mathematical operation is performed at samples which are spaced apart in the time by the symbol transmission period, instead of by an infinitesimally small distance, as in the prior art. Thereby all noise present at frequencies higher than the symbol transmission speed is averaged out. Non-linearities, are thereby alleviated, while still suppressing the noise. The latter is realised by the summation, which as a matter of fact, corresponds to an integration filter function. This will be clearly shown in the describing portion of this document. Offset present in the demodulated symbols is thereby detected and eliminated. By further tuning the local oscillator frequency with the thus obtained offset value, as is mentioned in claims 6 and 13, the offset removal is thereby further improved. The above and other objects and features of the invention will become more apparent and the invention itself will be best understood by referring to the following description of an embodiment taken in conjunction with the accompanying drawings wherein: Fig. 1 represent a block scheme of a first embodiment of a demodulator according to the invention FIG. 2 represents a block scheme of an FSK receiver including another embodiment of a demodulator according to the present invention, Fig. 3a represents the principal mathematical operation of the demodulator device of Fig. 1, Fig. 3b represents the principal mathematical operation of the demodulator of Fig. 2, and Fig. 4 represents a detailed view on the offset correction device OCD included in the receiver of Fig. 2. The present invention is directed to a method for demodulation in an FSK (Frequency Shift Keying) signal radio receiver. Referring to Fig. 2, there is shown a block diagram of the main part of an FSK receiver FSKR, according to one embodiment of this invention. This FSK receiver includes an input terminal INR, which is adapted to receive an FSK signal from an antenna of the receiver. This high-frequency FSK signal, for instance having a frequency of 2.4 GHz, as for Bluetooth applications, is conducted to the input terminal IN of the demodulator DM of the receiver FSKR. This demodulator includes an analog downconversion device ADD which is adapted to perform a first downconversion step on the incoming signal to a lower frequency. In the embodiment depicted in Fig. 2, this represents an intermediate frequency, but in another embodiment, for instance the one shown in Fig. 1, this may as well consist of a downconversion to an analog baseband signal. In Fig. 1, the analog downconversion device is denoted ADD' . This method of full analog downconversion was also described in the already mentioned prior art document. The first downconversion can also be done to a non-zero intermediate frequency, resulting in a receiver embodiment as depicted in Fig. 2. For Bluetooth applications for example, an intermediate frequency of 1 MHz or higher is chosen. In any case, the analog downconversion devices ADD and ADD' are further adapted to deliver two orthogonal analog components of this lower frequency analog signal. These two analog components are respectively denoted Qlf and Ilf in Fig. 2 and Qlf' and IIf' in Fig. 1. These serve as input signals to a digitisation device. The digitisation device DD of Fig. 2 is adapted to perform an analog/digital conversion on these input signals, such as to obtain two respective components of a digital lower frequency signal Qlfd and llfd. In the embodiment depicted in Fig. 2, these two digital components are further digitally downconverted within a digital downconversion device DCC. This is performed by mixing them digitally with the two orthogonal components I LO and Q LO , generated by a numerically controlled oscillator, denoted LO. For Bluetooth applications, the frequency of this local oscillator is thus 1 MHz. Following equations apply, as can be deduced from Fig. 2 : I d = I LO . Ilfd + Q LO . Qlfd = cos (ω LO . Δt) . cos (ω LF . Δt) + sin (ω LO . Δt) . sin (ω LF . Δt) = cos ((ω LO - ω LF ) . Δt) = cos (ω m . Δt) Q d = I LO . Qlfd - Q LO . Ilfd = cos (ω LO .Δt) . sin (ω LF . Δt) - sin (ω LO . Δt) . cos (ω LF . Δt) = sin ((ω LO - ω LF ) . Δt) = sin (ω m . Δt) which, according to the principles of FSK modulation, corresponds to the two othogonal components of the sampled analog baseband signal . In the alternative embodiment of Fig. 1, where Qlf and Ilf were already the components of the analog baseband signal, the digitisation device DD' of Fig. 1 then merely includes the two A/D converters for obtaining the orthogonal components of the digital baseband signal Qd and Id. The thus obtained digital signals are denoted Qd and Id. Qd(k) and Id(k) thereby respectively represent the k-th sample of these components. The digitisation device DD' therefore includes, apart from the two A/D converters, two memory registers M1 and M2, which are adapted to store previous values of the respective signal components. At a certain moment k, four signals are thus delivered by DD' : the k-the sample of Qd and Id, as well as the (k-1)-th sample of these signals. These four samples are provided at the baseband symbol period rate at the four respective output terminals of DD', which are denoted DD1'to DD4'. In a next part of the demodulator DM', the actual symbol recovery takes place based on these four components. This part is denoted P' and includes, two digital multipliers, denoted MP1' and MP2', and a subtraction device denoted SUB. The following mathematical operation is thereby performed R(k)= Qd(k).Id(k-1) - Id(k).Qd(k-1) This expression is mathematically depicted in Fig. 3a. Therein Vk and Vk-1 respectively denote the k-th and the (k-1)-th FSK baseband vector. Following the general principles of FSK modulation, the two Cartesian components respectively correspond to I(k)=Acos(ω m .k.Δt) and Q(k)=Asin(ω m .k.Δt) for the k-th sample of this baseband vector. If we denote ϕk=ω m .k.Δt and ϕk-1=ω m .(k-1).Δt, then the aforementioned equation can as well be described as R(k) =A sin(ϕ k ).A cos(ϕ k-1 ) - A sin (ϕ k-1 ) . A cos(ϕ k ) =A 2 (sin (ϕ k ).cos(ϕ k-1 ) - cos(ϕ k ).sin(ϕ k-1 ) =A 2 sin (ϕ k -ϕ k-1 ) =A 2 sin (α) whereby this angle α is proportional to the frequency ω m by the equation α = ω m . Δt, Δt being the difference in time between sample k and sample k-1. For sufficiently small angles, sin(α) approximates α, and the result R(k) is thus proportional to the modulation frequency ω m , which contains the symbol information. For a binary FSK signal a "1" is for instance transmitted by setting ω m >0, and a "0" implies ω m <0, or vice versa. The demodulator DM', which thus must determine the value of ω m in order to recover the transmitted bit sequence from the received signal, is able to do this from the value of R(k) by means of a logic device (not shown in Fig. 1) which is coupled between the processor means P' and the output terminal OUT'. For binary FSK, a result R(k) larger than zero thus means α positive ω m , and thus a binary "1" is detected. A result R(k) smaller than zero means a negative ω m , and thus α binary "0" is detected. For digital data with a bitrate 1/Tb, Tb being the period between two successive bits, the most straightforward way is thus to take the aforementioned operation of the current vector and the one Tb seconds earlier, whereby Δt=Tb. This gives the biggest angle, and thus the biggest signal. This is more robust to the presence of noise on the received signal, compared with the aforementioned prior art solution which acts on instanteneous values of the signal, and whereby Δt is thus infinitesimally small. For binary FSK, where only the sign of the sinus is important, this is a sufficient solution. It is however to be remarked that for other FSK schemes, such as 4-FSK , it is not only the sign of the angle α which is important, but also its value. If the period Tb is too large, the non-linearity introduced by approximating α by its sine value, can therefore be intolerable. In that case , in order to linearize the relationship between the result R(k), and ω m , one can oversample the I and Q signals. Generally this occurs in the A/D converters which thus oversample the incoming Qlf and Ilf signal. The embodiment used for performing this variant method, as well as the signals used, is depicted in Fig. 2. For n being this oversampling factor, meaning that per period Tb, n samples are taken, an additional shift register and summation operation is performed, respectively by SR and SUM. Following successive samples can then be taken : R 1 ,..., R 1-n , whereby, compared to the embodiment of Fig. 1, R(k) of Fig. 1 corresponds to the n-th sample Ri of Fig. 2, and whereby R(k-1) of Fig. 1 corresponds to the first sample R 1-n of Fig. 2. These samples are then summed within SUM, as to again obtain a more linearized version of the vector product since the angles α i are much smaller than the total angle, and since in this case, the sinus much better approximates the angle itself. Indeed, referring to figure 3b, where the principles of this variant method are explained, following results R 1 to R n are obtained : R 1 = Q 1 .I 0 -Q 0 .I 1 = A 2 sin (α 1 ) R 2 = Q 2 .I 1 -Q 1 .I 2 = A 2 sin (α 2 ) .... R n = Q n .I n-1 -Q n-1 .I n = A 2 sin (α n ) R(k) = Σ R i = Σ (A 2 sin (α 1 )) ≈ A 2 . α k Which thus represents a better approximation of the to be recovered symbol, since the individual angles α i are smaller resulting in a better sine approximation. It is to be remarked that, because of the oversampling at the A/D converter, the shift register received a continuous stream of results R i of the oversampled signal, and that the summation device generates a stream of data, denoted S i , of which only at certain instances, separated from each other by the symbol period, a relevant sample corresponds to the correct demodulated symbol. To solve this problem, a sampling operation performed by and triggered by a clock recovery device CRD is to be included within the demodulator. This clock recovery device is adapted to generate, based on the oversampled data stream generated by SUM, a clock for clocking the sampling operation. The latter, also performed by CRD, will result in only sampling these sums which correspond to the correct symbol, and to provide them to the output terminal OUT of the demodulator device . The resulting data stream is denoted V k , and thus includes a stream of demodulated samples at the symbol period, which are directly proportional to the symbol values α k . In the first variant of the method, the resulting samples R(k) approximate the samples V k of the second variant of the method. For this first variant, it is also mandatory to have clock recovery devices such that the data are sampled at the right moment, for instance in the A/D convertor. In this case the A/D convertor thus also has to include a clock recovery unit. In order not to overload the drawing, this is not shown in Fig. 1. Since embodiments of clock recovery units and clock recovery devices as described above in this document, are well known to a person skilled in the art, these will not be further discussed in this document since they do not represent an essential part of this invention. The FSK receiver device FSKR of Fig. 2 further includes an offset detection and correction device, denoted OCD, which is adapted to determine from the demodulated symbol stream V k , an offset error, denoted Δf k , and to correct the symbol stream such as to obtain a corrected output symbol stream, denoted S k , for provision to the output terminal OUTR of the FSK receiver device OUTR. A more detailed scheme of one embodiment of the offset detection and correction device is shown in Fig. 4. The principle of this offset detection consists of tracking the minimum and the maximum of the input signal, i.e. the incoming symbol stream V k . The offset of this symbol stream is thus denoted Δf k , and is calculated as the average between the latest value of the tracked maximum, denoted as Vmaxnew, and the latest value of the tracked minimum, denoted Vminnew. Compared to the methods where merely the average of a series of values of the data stream is used for calculating the offset, this method has the advantage that it is also applicable for data streams where the number of "1" values is different from the number of "0" values, such as is the case for Bluetooth applications. Moreover, this method is also faster than the aforementioned methods. The values of the current minimum and the current maximum, which are respectively denoted as Vmin and Vmax, are thereby continuously updated, based on the incoming data. This takes place in two comparators, COMP1 and COMP2, which respectively compare the current value of the maximum, respectively the current value of the minimum, with the incoming data. Upon detecting that V k >Vmax, COMP1 will generate a control signal to a first update device UPD1, which will accordingly update Vmax with this V k value. If V k <= Vmax, Vmaxnew will remain the old Vmax. In case of a new value, this will replace the old value within the memory . The same operation takes place for Vmin : the incoming data Vk is compared with the actual value Vmin, and, in case Vk is lower than Vmin, the latter is updated within UPD2. The latest values of both Vmax and Vmin, i.e. Vmaxnew and Vminnew are used for calculating the offset value Δf k , which consists of their average value. This calculation takes place within CALC. The offset is subsequently subtracted within a subtraction device SUB from the incoming data or symbol stream. A corrected symbol stream, denoted S k is thereby obtained for provision to a first output terminal OUT1 of OCD. The offset value Δf k is as well delivered by the calculating device CALC, to a second output terminal OUT2 of OCD. This second output terminal OUT2 is coupled to a control input terminal INF of the digital downconversion device DDC of the demodulator DM, as can be observed from Fig. 2. The digital downconversion device DDC, will use the value of the offset Δf k for directly correcting the value of the downconversion carrier frequency of the local oscillator LO. In other embodiments of the demodulator, such as the one shown in Fig. 1, the frequency offset value can be fed back to the analog downconversion device ADD, where it will also be used for tuning the value of the local oscillator. In the embodiment of the offset detection and correction device OCD depicted in Fig. 4, four more variables are further used for refining the above described method of offset detection. Two of these variable, denoted τ 1H and τ 1T are respectively stored within UPD1, whereas two others, τ 2H and τ 2T , are stored in UPD2. These variables are used in a variant of the method of offset detection which is especially useful in the presence of noisy signals, where for instance a short disturbance might cause Vmax to increase too much beyond the normal limits of the signal. Therefore the update devices are equipped with a track- and hold function on Vmax and Vmin; which are each characterised by the aforementioned two time constancts. Following equations apply : If Vk > Vmax, then Vmaxnew=Vmax + τ 1T . (Vk-Vmax) Else Vmaxnew=Vmax + τ 1H .(Vk-Vmax) Similarly If Vk < Vmin, then Vminnew=Vmin + τ 2T . (Vk-Vmin) Else Vminnew=Vmin + τ 2H . (Vk-Vmin) By using these expressions, the tracking operation of Vmax and Vmin will be more tolerant to noise. The values of the tracking parameters τ 1T and τ 2T are usually stored within the update devices, may be user programmable, and must be chosen as a compromise between the tracking speed and the expected noise magnitude. The value of the hold parameters τ 2T and τ 2H must be chosen as a function of the largest number of consecutive "1" or "0" values that is expected. Remark that other implementations are possible for realising the described method for offset detection and correction. It is further important to notice that also in the receiver of Fig. 2, the presence of a logic device for relating the demodulated signal value with the originally transmitted baseband symbol or bits, is mandatory. Such a device is to be coupled between OCD and the output terminal OUT. In order not to overload the drawing, this device is not shown in Fig. 2. While the principles of the invention have been described above in connection with specific apparatus, it is to be clearly understood that this description is made only by way of example and not as a limitation on the scope of the invention, as defined in the appended claims.

Claims: A method for demodulating an analog FSK signal (FSKin), said method including a step of downconverting said analog FSK signal (FSKin) into a lower frequency analogue signal (IIf',QIf';IIf,QIf), said downconverting step being followed by a digitisation step on said lower frequency analogue signal such as to obtain an in-phase component (Id) and an orthogonal phase component (Qd) of a digital baseband signal, and a step of multiplying a current sample (Id(k);Idi) of said inphase component with a previous sample (Qd(k-1);Qdi-1) of said orthogonal phase component and subtracting the product thereof from the product obtained by multiplying a current sample of said orthogonal phase component (Qd(k); Qdi) with a previous sample (Id(k-1); Idi-1) of said inphase component, thereby obtaining a result (R(k); Ri) which is proportional to a digital symbol of transmitted data, characterised in that said current sample (Idi) and said previous sample (Idi-1) of said inphase component are spaced apart by a period which can be multiplied by an integer, n, greater than 1 to equal a period of the transmitted data, said current sample (Qdi) and said previous sample (Qdi-1) of said orthogonal phase component are spaced apart by said period which can be multiplied by the integer, n, to equal a period of the transmitted data, whereby the steps of said method are repeated, thereby obtaining n consecutive values of said result (Ri), and whereby said n consecutive values of said result (Ri) are subsequently added, such as to obtain subsequent sums (Si). Method according to claim 1 characterised in that : a data stream, at the rate of said transmitted data multiplied by said integer, and consisting of said subsequent sums (Si), is sampled at said transmitted data rate such as to obtain a stream of demodulated symbols (Vk) Method according to claim 2 characterised in that : an offset value (Δ fk) of said demodulated symbols (Vk) is determined, by tracking the minimum and maximum values of said stream of said demodulated symbols (Vk), after which step said offset value (Δ fk) is subtracted from said demodulated symbols for thereby obtaining corrected symbols (Sk). Method according to any preceding claim characterised in that : said digitisation step consists of an analogue digital conversion followed by a digital downconversion such as to obtain said inphase component (Id) and said orthogonal phase component (Qd). Method according to claim 3 or claim 4 when depending on claim 3, characterised in that : said offset value (Δ fk) is used during said digital downconversion step by controlling the value of a numerical controlled oscillator to compensate carrier frequency offset. A demodulator (DM'; DM) for demodulating an analog FSK signal (FSKin), said demodulator (DM'; DM) including an input terminal (IN'; IN) for receiving said analogue FSK signal (FSKin) and an output terminal (OUT'; OUT) for providing a stream of demodulated symbols (R(k); Vk), an analogue downconversion device (ADD'; ADD) coupled to said input terminal (IN';IN) and adapted to derive from said analog FSK signal a lower frequency analogue signal (IIf',QIf';IIf,QIf) said demodulator (DM';DM) further including a digitisation device (DD';DD) adapted to derive from said lower frequency analogue signal (IIf',QIf' ;IIf,QIf) successive samples of an in-phase component and an orthogonal phase component and to deliver, a current sample (Id(k);Idi) and a previous sample (Id(k-1); Idi-1) of said in-phase component and a current sample (Qd(k);Qdi) and a previous sample (Qd(k-1); Qdi-1) of said orthogonal component to respective output terminals of said digitisation device (DD';DD), processor means (P';P), adapted to calculate a first product of said previous sample (Id(k-1); Idi-1) of said in-phase component with said current sample (Qd(k);Qdi) of said orthogonal phase component, to calculate a second product of said previous sample (Qd(k-1); Qdi-1) of said orthogonal phase component with said current sample (Id(k);Idi) of said in-phase component, to calculate the difference between said first product and said second product and to deliver the result (R(k) ;Ri) of said subtraction to an output terminal of said processor means which is coupled to said output terminal (OUT';OUT) of said demodulator (DM';DM), characterised in that : said digitisation device (DD) is further adapted to deliver said current sample (Idi) and said previous sample (Idi-1) of said inphase component , and said current sample (Qdi) and said previous sample (Qdi-1) of said orthogonal phase component, at an integer multiple of the rate of transmitted data, and in that said demodulator (DM) further includes a shift register (SR) adapted to store successive values (Ri-n,...,Ri) of said result and to deliver said successive values to a summation device (SUM) of said demodulator (DM), said summation device (SUM) being adapted to add n of said successive values of said result, and to provide said sum (Si) to an output terminal of said summation device which is coupled to said output terminal (OUT) of said demodulator device (DM). A demodulator (DM) according to claim 6 characterised in that : said demodulator (DM) further includes a clock recovery device (CRD) which is adapted to sample, at the rate of said transmitted data, samples from the data stream consisting of successive values of said sum (Si), and to deliver said samples to said output terminal (OUT) of said demodulator (DM) as a stream of symbols (Vk). An FSK receiver (FSKR) including a receiver input terminal (INR) for receiving an analog FSK signal (FSKin) a receiver output terminal (OUTR) a demodulator (DM';DM) having an input terminal (IN';IN) coupled to said input terminal (INR) of said FSK receiver, said demodulator (DM';DM) being adapted to derive from an analogue FSK signal (FSKin), a stream of demodulated baseband symbols (R(k);Vk) for provision to an output terminal (OUT';OUT) of said demodulator (DM';DM) which is coupled to said receiver output terminal (OUTR) characterised in that : said demodulator device (DM';DM) is further adapted in accordance to claim 6 or 7. An FSK receiver (FSKR) according to claim 8 characterised in that : said FSK receiver (FSKR) further includes an offset correction device (OCD) coupled between said output terminal (OUT';OUT) of said demodulator device (DM';DM) and said receiver output terminal (OUTR), said offset correction device being adapted to determine an offset (Δ fk) of said demodulated baseband symbols (R(k); Vk), by tracking the minimum and maximum value of said stream of demodulated symbols, and to subtract said offset (Δ fk) from said demodulated symbols (R(k) ;Vk) for thereby obtaining corrected digital symbols (Sk) for provision to an output terminal (OUT1) of said offset correction device (OCD) which is coupled to said output terminal (OUTR) of said FSK receiver. An FSK receiver (FSKR) according to claim 8 or 9 characterised in that : said analogue downconversion device (ADD) is adapted to deliver a pair of orthogonal components (IIf,QIf) of said lower frequency analog signal said digitisation device (DD) includes a pair of analogue digital converters , each of which is adapted to receive a respective one of said pair of lower frequency analog signals (Qlf,llf), and to respectively convert it to a digital lower frequency signal (QIfd,IIfd), for delivery to a digital downconversion device (DDC) included in said digitisation device, which is adapted to derive from said pair of digital lower frequency signals (QIfd,IIfd) and from a local oscillator frequency signal (QLO,ILO) provided by a numerically controlled oscillator (LO), said successive samples of said inphase (Idi) and said orthogonal phase (Qdi)component, said digitisation device (DD) further includes memory means (M1,M2), adapted to temporarily store said successive samples of said orthogonal phase (Qdi), resp. said inphase (Idi) component, for providing previous samples of said orthogonal (Qdi-1), resp. said inphase (Idi-1) component. An FSK receiver according to claim 9 or 10 when depending on claim 9, characterised in that : said offset correction device (OCD) includes a second output terminal (OUT2) coupled to a control input terminal (INF) of said digital downconversion device (DDC), said offset correction device (OCD) is further adapted to deliver the value of said offset (Δ fk) to said second output terminal (OUT2), said numerically controlled oscillator (LO) of said digital downconversion device (DDC) being further adapted to tune the frequency of the output reference signal of said numerically controlled oscillator (LO).

Inventors: CRANINCKX JAN FRANS LUCIEN, OP T EYNDE FRANK NICO LIEVEN, CRANINCKX, JAN FRANS LUCIEN, OP'T EYNDE, FRANK NICO LIEVEN
Applicants: ST MICROELECTRONICS NV, STMICROELECTRONICS N.V.
Application year: 2000
Main classification: H04L27
IPC codes: H04L25, H04L27