SPURIOUS FREQUENCIES ATTENUATION FOR A DC REFERENCE VOLTAGE

Abstract: In a television apparatus that includes a television signal decoding integrated circuit (IC) that performs combing, PIP, OSD, chroma and luminance decoding, digitizing, and other functions, particularly on analog signals, an automatic gain control (AGC) circuit is coupled to the television signal decoding IC at its luminance DC restoration pinout. The AGC circuit provides an improved NTSC signal picture by filtering out unwanted noise and oscillations.

Description: SPURIOUS FREQUENCIES ATTENUATION FOR A DC REFERENCE VOLTAGE This application claims the benefit of U.S. Provisional Patent Application Serial No. 60/144,426 filed on July 1 6, 1 999. Field of the Invention The present invention relates to decoders in televisions for decoding received analog audio and video signals or transmissions and, more particularly, to an automatic gain control circuit for a decoder in a television for decoding received analog audio and video signals or transmissions. Background of the Invention Televisions and other similar devices must now be able to receive, decode, and process analog and digital audio and video signals or transmissions. Because of the complexity of modern televisions caused by digital television signals and related processing, and analog television signal processing, many of the capabilities and functions thereof are performed by specialized digital integrated circuits (ICs). Advantageously, it is also preferable to manipulate/process the television signal in the digital domain regardless of whether the original received television signal is analog or digital. Of the various types of ICs used in televisions, decoders and digitizers aid in the processing of the digital and analog television signals. One type of IC that is used in televisions for processing analog television signals is a video decoder. After processing of the analog television signal the video decoder IC generally digitizes the component signals for further processing. However, during processing of the analog signal, it is necessary to provide luminance signal DC restoration. As an example, the H P81 1 7 Video Decoder, from Intersil Corporation, is one type of video decoder that accepts incoming analog NTSC or PAL television signals, processes the analog television signal, digitizes the signals, and then processes/manipulates the digital signals. The HMP 81 1 7 is particularly designed to decode baseband composite or S-video NTSC and PAL signals. Other functions are also supported. In the HMP81 1 7 video decoder, analog signal processing includes the restoration of a luminance signal (luminance signal restoration). Luminance signal restoration is a necessary step of television signal processing. In the HMP81 1 7, a luminance control terminal or pin (LCAP) is furnished to provide a voltage to offset the sync tip of the luminance circuitry to a lower reference of an internal A/D converter. It is recommended by the manufacturer of the HMP81 1 7 to couple a single storage capacitor of a given value to the LCAP pin. Such is typical of video decoders for analog signals. It has been determined, however, that a single storage capacitor for the luminance circuitry does not provide a quality picture when the incoming, original television signal is analog. This is due to noise and oscillations that appear in the luminance decoding because of the analog signal. Summary of the Invention The present invention comprises an automatic gain control network or circuit for luminance signal restoration in an analog television signal video decoder. The video decoder is preferably an integrated circuit (IC) that receives the analog video television signal or transmission. In one form, the present invention comprises a television apparatus that includes processing circuitry adapted to receive an analog television signal, a video decoder coupled to the processing circuitry and adapted to process the analog television signal, the video decoder adapted to provide luminance signal restoration and configured with a luminance voltage offset reference terminal adapted to aid in the luminance signal restoration, and an automatic gain control network coupled to the luminance voltage offset terminal. In another form, the present invention comprises an automatic gain control network for luminance restoration circuitry in a television apparatus, wherein the television is adapted to receive analog television signals, and includes processing circuitry and a video decoder for the analog television signals, the video decoder having a luminance restoration terminal in communication with the luminance restoration circuitry. The automatic gain control network for the luminance restoration circuitry includes, a first circuit branch, a second circuit branch, and a third circuit branch. The first, second, and third branches being situated in parallel. In still another form, the present invention comprises an automatic gain control network for a television apparatus, wherein the television apparatus is adapted to receive analog television signals, has a signal decoding integrated circuit, with the signal decoding integrated circuit having luminance signal restoration capabilities and a luminance voltage offset terminal. The automatic gain control network includes a first circuit branch configured to attenuate a first frequency, a second circuit branch configured to attenuate a second frequency, and a third circuit branch configured to attenuate a third frequency. Brief Description of the Drawings Reference to the following description of the present invention should be taken in conjunction with the accompanying drawings, wherein: Fig. 1 is a block diagram of an exemplary system in which the present invention is utilized; Fig. 2 is a diagram of an exemplary television apparatus circuit as used in the system of Fig. 1 incorporating the principles of the present invention; and Fig. 3 is a diagram of an exemplary automatic gain control circuit as used in the television apparatus circuit of Fig. 2. Corresponding reference characters indicate corresponding parts throughout the several views. Detailed Description of the Invention With reference to Fig. 1 , there is shown a block diagram of a system, generally designated 1 0, which may utilize the present invention. It should be initially appreciated that the system 10 depicted in Fig. 1 is only exemplary and/or representational of the many systems that may utilize the principles of the present invention. The system 1 0 includes a television apparatus that may or may not include a monitor or other similar display device (collectively "television apparatus") generally designated 1 2. The television apparatus 1 2 is adapted through appropriate circuitry, software, and/or other components to decode and process digitally modulated analog audio and video television signals or transmissions ("digital television signals") from a Direct Broadcast Satellite (DBS) system 1 8 as received via a link or line 20. Such signals may be digitally modulated using the QPSK (Quadrature Phase Shift Keying) format. The television apparatus 1 2 is also adapted through appropriate circuitry, software, and/or other components to decode and process digital television signals from terrestrial Digital Television (DTV) antenna 1 4 as received via a link or line 1 6, such as ATSC DTV. Such signals may be digitally modulated using VSB (Vestigal SideBand). The television apparatus 1 2 is also adapted through appropriate circuitry, software, and/or other components, to process analog audio and video television signals ("analog television signals") from a terrestrial analog antenna 22 as received via a link or line 24, as well as analog television signals from a CATV system 26 via a link or line 28. Such processing typically includes digitizing the video and/or audio signals through appropriate circuitry, software, and/or other components. Digital television signals from the CATV system 26 are also decoded and processed as indicated above. It should be appreciated that the television apparatus 1 2 is adapted to receive and process analog and/or digital television signals from sources other than that shown. As an example of the above, the television apparatus 1 2 may be a model DTC 1 00, from Thomson Consumer Electronics, Inc. of Indianapolis, Indiana. In any form, the television apparatus 1 2 typically includes appropriate circuitry, software, and other components to support/provide a display, an integral control system, a user-interface and on-screen display (OSD) functionality. It should be appreciated that the television apparatus 1 2 may take other forms and have additional capabilities and/or functionality other than those shown and/or discussed through appropriate circuitry, software, and/or other components. Referring to Fig. 2, there is shown a block diagram of at least some of the various components of the DTC 100 television apparatus 1 2. The DTC 1 00 television apparatus 1 2 is adapted through appropriate circuitry, software, and/or other components, to receive and process digital television signals and analog television signals. The various blocks and interconnections depicted in Fig. 2 are exemplary of a television capable utilizing analog and digital television signals. Thus, variations in the interconnections and components may vary. The television apparatus 1 2 includes a DSS tuner/IF converter 30 that is adapted to receive a digital television signal (audio, video, and VBI/other) via line 20, allows tuning to the various channels of the digital television signal, converts the digital television signal into an Intermediate Frequency (IF), and sends the IF digital television signal (here shown as QPSK modulated) to a DSS link 32. The DSS link 32 demodulates the IF digital television signal and forwards the resulting digital television signal to a link multiplexer (MUX) 34. The link MUX 34 selectively sends the digital television signal to an ARM transport 36. The ARM transport 36 extracts a digital audio signal that is sent to an MPEG/AC-3 audio decoder 38. The audio decoder 38 decodes the digital audio signal, and sends the decoded digital audio signal to a digital to analog (D/A) converter 44. The D/A converter 44 sends the resulting analog audio signal to an audio processor 46 which send the process analog audio signal to audio amps 48 that are connected to audio speakers. The ARM transport 36 also extracts a digital video signal that is sent to the decoder 50. The decoder 50 provides necessary MPEG circuitry and/or software to decode the digital video signal. The decoded digital video signal is sent to a digital to analog (D/A) converter and filter 52 to provide an analog television signal for further processing before being forwarded to the display. The television apparatus 1 2 also includes a High Definition (HD)/NTSC tuner/IF converter and splitter 40 that receives an HD digital television signal (audio, video, and VBI/other) from the terrestrial digital antenna 1 4 via line 1 6, allows tuning to the various channels of the HD digital television signal, converts the HD digital television signal into an Intermediate Frequency (IF), and sends the HD IF digital television signal (here shown as VSB modulated) to an HDTV link 42. The HDTV link 42 demodulates the HD IF digital television signal and forwards the resulting digital signal to a link multiplexer (MUX) 34. The link MUX 34 selectively sends the digital signal to an ARM transport 36. The ARM transport 36 extracts a digital audio signal that is sent to an MPEG/AC-3 audio decoder 38. The audio decoder 38 decodes the digital audio signal, and sends the decoded digital audio signal to a digital to analog (D/A) converter 44. The D/A converter 44 sends the resulting analog audio signal to an audio processor 46 which send the process analog audio signal to audio amps 48 that are connected to audio speakers. The ARM transport 36 also extracts a digital video signal that is sent to the decoder 50. The decoder 50 provides necessary MPEG circuitry and/or software to decode the digital video signal. The decoded digital video signal is sent to a digital to analog (D/A) converter and filter 52 to provide an analog television signal for further processing before being forwarded to the display. The High Definition (HD)/NTSC tuner/IF converter and splitter 40 also receives digital television signals from the digital cable source 26 via line 28 and processes them in the same manner as for the terrestrial digital television signals. Additionally, the High Definition (HD)/NTSC tuner/IF converter and splitter 40 provides PIP (Picture-ln-Picture) capabilities. The High Definition (HD)/NTSC tuner/IF converter and splitter 40 also receives analog (NTSC) television signals from the terrestrial analog antenna 22 via line 24 and from the analog cable source 26 via line 28. The analog television signal is tuned by the tuner to a channel of the television signal and provides an IF analog television signal to an NTSC video switcher 56. The NTSC video switcher 56 provides the analog television signal to an initial comb filter/PIP and Chroma decoder 58 after which the analog television signal is sent to an NTSC YUV A/D converter 66 before being sent to the decoder 50. The television signal decoding integrated circuit (IC) or chip 50 performs combing, picture-in-picture (PIP), chroma decoding and digitizing, MPEG video decoding, NTSC and PAL video upconversion, OSD, and other functions. Such a decoding IC may be an HMP81 1 7 Video Decoder from Intersil Corporation of Palm Bay, Florida (formally Harris Semiconductor of Harris Corporation of Melbourne Florida), the Harris Semiconductor Data Sheet of January 1 999, File Number 4643, of which is specifically incorporated herein by reference. With additional reference to Fig. 3, the decoding IC 50 is shown in a simplified block form. The decoding IC 50 also performs luminance signal DC restoration for the incoming analog television signal. In particular, the data sheet for the decoding IC 50 indicates that a storage capacitor should be attached to the LCAP (Luminance CAPacitor) pin 76 for providing luminance signal DC restoration. The value of the capacitor is stated to be 0.1 μF, and should be connected between the LCAP pin 76 and an AGND (Analog GrouND) pin (not shown). In accordance with the principles of the present invention, instead of the single storage capacitor being connected to the LCAP pin 76 as suggested by the manufacturer, an automatic gain control (AGC) network or circuit 60 is connected to the LCAP pin 76 and ground. The LCAP voltage offsets a sync tip to the lower reference of an A/D converter (not shown) of the decoder 50. The AGC network 60 improves the quality of the resulting picture of the television apparatus 1 2 over a single storage capacitor by filtering out unwanted noise and oscillations. The AGC network 60 is a branched, parallel network having a node 62 and a common ground 64. A first leg or branch 70, situated between the node 62 and the ground 64, includes a capacitor C1 for filtering out first frequencies of noise and/or oscillations. The capacitor C1 may have a value of 820pF. A second leg or branch 80, situated between the node 62 and the ground 64 and parallel to the first leg 70, includes a resistor R1 in series with a capacitor C2. The second leg 70 filters out second frequencies of noise and/or oscillations. The resistor R1 may have a value of 750Ω, while the capacitor C2 may have a value of 6.8μF. The AGC 60 includes a third leg or branch 90 situated between the node 62 and the ground 64 and parallel to the first and second legs 70 and 80. The third leg 90 filters out third frequencies of noise and/or oscillations, and may have a value of 0.27μF. It should be appreciated that capacitor and resistor values may deviate from those stated above, depending on the desired filtering characteristics of the AGC network 60. As well, networks other than the branched network 60 shown in Fig. 3 may be used. While this invention has been described as having a preferred design and/or configuration, the present invention can be further modified within the spirit and scope of this disclosure. This application is therefore intended to cover any variations, uses, or adaptations of the invention using its general principles. Further, this application is intended to cover such departures from the present disclosure as come within known or customary practice in the art to which this invention pertains and which fall within the limits of the appended claims.

Claims: CLAIMS WHAT IS CLAIMED IS: 1 . A television apparatus comprising: processing circuitry adapted to receive an analog television signal; a video decoder coupled to the processing circuitry and adapted to process the analog television signal, the video decoder adapted to provide luminance signal restoration and configured with a luminance voltage offset reference terminal adapted to aid in the luminance signal restoration; and an automatic gain control network coupled to the luminance voltage offset terminal. 2. The television apparatus of claim 1 , wherein the automatic gain control network comprises a first, second, and third branch, parallel circuit. 3. The television apparatus of claim 2, wherein the first branch includes a first capacitor coupled between an analog ground and the luminance voltage offset terminal, the second branch includes a first resistor coupled in series in with a second capacitor, the first resistor and second capacitor coupled between the analog ground and the luminance voltage offset terminal, and the third branch includes a third capacitor coupled between the analog ground and the luminance voltage offset terminal. 4. The television apparatus of claim 3, wherein the first capacitor has a value of approximately 820 pF, the second capacitor has a value of approximately 6.8 μF, the third capacitor has a value of approximately 0.27 μF, and the first resistor has a value of approximately 720Ω. 5. The television apparatus of claim 3, wherein the first resistor of the second branch is coupled to the luminance voltage offset terminal, and the second capacitor is coupled to the analog ground. 6. The television apparatus of claim 3, wherein values for each component of the first, second, and third branches are selected to filter a particular frequency. 7. In a television apparatus adapted to receive analog television signals, and having processing circuitry and a video decoder for the analog television signals, the video decoder having a luminance restoration terminal in communication with luminance restoration circuitry, an automatic gain control network for the luminance restoration circuitry comprising: a first circuit branch; a second circuit branch; a third circuit branch; and wherein said first, second, and third branches are in parallel. 8. The automatic gain control network of claim 7, wherein said first circuit branch includes a first capacitor, said second circuit branch includes a first resistor in series with a second capacitor, and said third circuit branch includes a third capacitor. 9. The automatic gain control network of claim 8, wherein said first capacitor is coupled between the luminance restoration terminal and an analog ground, said first resistor is coupled between the luminance restoration terminal and said second capacitor which is coupled between said first resistor and the analog ground, and said third capacitor is coupled between the luminance restoration terminal and the analog ground. 1 0. The automatic gain control network of claim 9, wherein said first capacitor has a value of approximately 820 pF, said second capacitor has a value of approximately 6.8 μF, said third capacitor has a value of approximately 0.27 μF, and said first resistor has a value of approximately 720Ω. 1 1 . The automatic gain control network of claim 9, wherein values for each component of said first, second, and third branches are selected to filter a particular frequency. 1 2. In a television apparatus adapted to receive analog television signals, the television apparatus having a signal decoding integrated circuit, the signal decoding integrated circuit having luminance signal restoration capabilities and a luminance voltage offset terminal, an automatic gain control network comprising: a first circuit branch configured to attenuate a first frequency; a second circuit branch configured to attenuate a second frequency; and a third circuit branch configured to attenuate a third frequency. 1 3. The automatic gain control network of claim 1 2, wherein said first, second, and third circuit branches are in parallel. 1 4. The automatic gain control network of claim 1 3, wherein said first circuit branch includes a first capacitor, said second circuit branch includes a first resistor in series with a second capacitor, and said third circuit branch includes a third capacitor. 1 5. The automatic gain control network of claim 14, wherein said first capacitor is coupled between the luminance voltage offset terminal and an analog ground, said first resistor is coupled between the luminance voltage offset terminal and said second capacitor which is coupled between said first resistor and the analog ground, and said third capacitor is coupled between the luminance voltage offset terminal and the analog ground. 1 6. The automatic gain control network of claim 1 5, wherein said first capacitor has a value of approximately 820 pF, said second capacitor has a value of approximately 6.8 μF, said third capacitor has a value of approximately 0.27 μF, and said first resistor has a value of approximately 720Ω.

Inventors: COLMAN GERALD ADOLPH, WATTS RODERICK ANDRE, COLMAN, GERALD, ADOLPH, WATTS, RODERICK, ANDRE
Applicants: COLMAN GERALD ADOLPH, THOMSON LICENSING SA, WATTS RODERICK ANDRE, COLMAN, GERALD, ADOLPH, THOMSON LICENSING S.A., WATTS, RODERICK, ANDRE
Application year: 2000
Main classification: H04N5
IPC codes: H03H7, H04N5