INTERLEAVER AND METHOD FOR INTERLEAVING AN INPUT DATA BIT SEQUENCE USING A CODED STORING OF SYMBOL AND ADDITIONAL INFORMATION

Abstract: The invention relates to a method for storing code symbols and additional control information in a processing means of an encoder of a communication system. In particular, the invention relates to the storing of code symbols together with additional control information in an interleaving memory (IM) of an interleaver. According to the invention, a combining means (COM) combines respective data bits (I, Q) forming a respective code symbol with their associated control bits into a control information/code symbol data word of a predetermined number (K) of bits. A control information/code symbol encoding means (CI/CS-ENC) encodes the control information/code symbol data words into encoded data words of a smaller number of bits. This data word with a smaller number of bits is then stored at a particular memory location in the interleaving memory (IM).

Description: INTERLEAVER AND METHOD FOR INTERLEAVING AN INPUT DATA BIT SEQUENCE USING A CODED STORING OF SYMBOL AND ADDITIONAL INFORMATION FIELD OF THE INVENTION The invention relates to an interleaver for interleaving input data bit sequences of data bits of code symbols each consisting of a number of data bits together with additional information, in particular control information, consisting of a number of control bits which indicate control functions for each code symbol. The invention also relates to a method for interleaving such a data bit sequence. Furthermore, the invention relates to a transmitter where code symbols are processed together with control information. Thus, generally the invention relates to the processing of data symbols together with additional control information. Whilst the storage of the data information together with the control information is comparatively simple when only one user channel is considered, storage problems in the transmitter become quite severe when a great plurality of user channels (providing data information in terms of bits) are to be combined with control information and are to be stored before transmission. BACKGROUND OF THE INVENTION The fact, that data information must be combined with control information before transmission is a common aspect relating generally to telecommunication systems. In particular, this problem becomes severe, when a great plurality of user channels needs to be processed as it is the case in a CDMA system. A base transceiver station BTS of a CDMA system, to which the invention is applicable, is generally shown in Fig. 1. Briefly summarized, the block diagram in Fig. 1 shows a base transceiver station BTS of a CDMA-system comprising a baseband transmitter TX, a baseband receiver RX and a HF section. In the transmitter TX, user data, for example in the form of ATM packets, is input into a channel encoder unit ENC via an ATM switch and a corresponding interface ATM IFX/IFC. The coded (and also interleaved) data is then modulated and spreaded by a baseband transmitter unit BBTX . The modulated data is then filtered and converted to an analog signal m the unit TRX-DIG, upconverted to the desired carrier frequency m the unit TRX-RF, amplified by a power amplifier unit MCPA and finally transmitted to an antenna ANT via a duplex filter. In the receiving part of the HF section, two antennas (diversity reception) are commonly used in each sector to receive the signal which is then amplified in the unit LNA, downconverted in the unit TRX-RF, A/D converted and filtered in the unit TRX-DIG. Then the data is demodulated by a RAKE receiver/despreader in the receiver unit BBRX while random access channels (branched off by an intermediate filter unit BBIF) are detected and demodulated m the un t BBRA . The user data US are then decoded m the decoder unit DEC and transmitted to the ATM switch via a:. ATM interface ATM IFX/IFC. In the CDMA base transceiver station BTS a bit-interleaving and de-interleaving is respectively performed m the encoder ENC m the baseband transmitter TX and the decoder DEC in the baseband receiver RX . Fig. 2 shows a functional overview of the encoder ENC, where a plurality cf data of individual user channels US1, US2 , US3 are input as sequential packets including respective data bit sequences at (_ into the ATM interface field programmable gate array FPGA ATM- IN. UDOΓ. channel coding m the FPGA CCOD-TCH interleaving is performed m the FPGA INTER-MOD at ®. That is, m Fig. 2 a number N UΞα. of user channels (e.g. up to 300 different channels) input user data US at © while control information CI for controlling the transmission of said data bit sequences is input at the digital signal processor DSP © or generally by the FPGA INTER-MOD ®. The data bits plus their associated control information are interleaved and time-aligned m the FPGA modulator FPGA INTERMOD ® using a memory arrangement of 3 RAMs shown at © and the interface FPGA RAM-IF1. The interleaved and time-aligned data is then transmitted to the baseband transmitter unit BBTX via the FPGA BBTX-OUT ©. Tnus, m addition to channel encoding and interleaving the encoder ENC m Fig. 2 combines data symbols from the user channels US1, US2 , US3... and control information CI , whereafter the combined information is provided to the baseband transmitter unit BBTX. Data bits are provided m the form of code symbols representing one element of an alphabet of a digital modulation scheme such as QPSK or 16QAM. Tne control information associated with every code symool is used to control other processing parts within tne baseoand transmitter un t BBTX. In general tne BBTX unit spreads each code symbol to the common chip rate and performs a multiplication with the CDMA code and a weighting with a specific transmission power. Furtnermore, m such a transmitter, the data information cf tne user channel may oe transmitted m individual frames . Wnen several user channels are present, as is the case normally for example m a mobile radio communication system, then several user cnannels each provide digital data information which is to be inserted into the specific frames on the radio link between tne transmitter of tne case stations and tne mobile stations. Each data frame may comprise data packets of several user channels which may arrive sequentially. Each packet is separately encoded and interleaved, before code symbols are formed and provided m parallel for all user channels to the CDMA modulator m the unit BBTX. The parallel processing towards tne CDMA modulator is necessary because of the CDMA technique where all channels are added up prior to transmission. Each packet thus contains a data bit sequence of a predetermined number of data bits (e.g. M-,_ bits) belonging to one user channel . The individual code symbols formed from the input data bit sequence m each packet may consist of e.g. N = 2 data bits representing the 4 possible states of a QPSK modulation (i.e. an I bit and a Q bit) and the control information CI may consist of e.g. L = 4 control bits indicating specific control functions with respect to the corresponding code symbols. As described above, m Fig. 2 a plurality of data of individual user channels US1, US2 , US3 , ... are input as sequential packets comprising respective data bit sequences at ©. An interleaving is tnen performed in the FPGA INTER-MOD © and the memory arrangement ®. In addition, control information CI is input to tne DSP ©. Alternatively, the DSP © or even the FPGA © tnemselves may generate the control information CI . The control information is combined with the data bits, interleaved and time-aligned also m tne FPGA © together witn the memory arrangement of tne 3 RAMs snown at © Tne data bits m form of code symbols (representing one state of a digital modulation scneme) togetner with the associated control information is tner transmitted to the oaseband transmitter un t BBTX via tne FPGA BBTX-OUT © . Although Figs. 1, 2 show a special structure of a CDMA transmitter, generally, a digital transmitter using a frame-wise processing of data packets can be summarized as shown in Fig. 3. That is, a data source DS , provides digital data US in form of packets to a channel encoder CC . The channel encoder CC may be a convolutional encoder, however, also other codes may be used, e.g. block codes, turbo codes, etc.. If the coder is a convolutional encoder it makes use of a specific rate and constraint length as predefined by the encoder polynomial. For example, the channel encoder ENC in Figs. 1, 2 uses a convolutional coder with a rate r = 1/2 and a constraint length c = 9. The channel encoded digital data output by the channel encoder CC are again data packets comprising a data bit sequence BS containing M-j_ data bits . From the individual data bits of the data bit sequence code symbols each consisting cf a number N of data bits are formed depending on the used digital modulation scheme. A write/read means W/R contains a selection means SM for extracting or selecting from the input data b t sequence BS data bits, which respectively belong to each other for forming such code symbols. In a combining means COM the code symbols are combined with their corresponding control information CI (see for example Fig. 4) . Then, the control information and the code symbols are provided as data bit sequence to an mterieaver comprising an interleaving memory IM fcr performing the interleaving. Interleaving is an essential processing step in a mobile communication system tc compensate errors introduced by flat fading more easily. The write/read means W/R comprises a write means WM which writes the code symbols combined with the control information into the memory locations of the interleaving memory and a read means RM which reads out the stored information according to the interleaving scheme. The interleaved digital data sequence BS ' consisting of a specific number of code symbols M-,_/N is output to the digital modulator MOD m the baseband transmitter unit BBTX which performs a modulation of the interleaved code symbols. For example, if the modulator uses a QPSK modulation, the bits are provided to the modulator as code symbols containing two bits, namely an I -bit and a Q-bit . The CDMA transmitter TX shown m Fig. 1 uses a QPSK modulation m the modulator BBTX. However, other digital modulation scnemes can be used that require the provision of code symbols consisting of a different number of data bits. For example, a 16QAM method requires code symbols of four bits each and a 4QAM method requires code symbols of two bits each. As is also seen m Fig. 3, the control information is read out together with the code symbols by the read means RM from the interleaving memory IM and is provided for example to the modulator MOD. For example, the control bits of the control information may indicate a frame start FS , a time-slot start SS, a marker MA and/or a power bit PW for the respective code symbol. In particular, the power bit PW is an important control information used by the modulator MOD. Although Fig. 3 shows tne provision of the control information to the modulator MOD only, this information can of course also oe used m other units of the transmitter. As descrioed witn respect to Fig. 3, tne encoder ENC of the baseband transmitter TX comprises the channel coder CC, the combining means COM and a processing means formed by the interleaving memory IM and tne write/ read means W/R. However, having combined the control information and the code symbols m the combining means COM, a processing means may also take different forms depending on the specific processing desired in the transmitter for a specific modulation technique. However, conventionally the control information, i.e., the control bits, and the code symbols are processed separately in the processing means . The invention should not be limited to the specific CDMA system or the transmitter shown in Figs. 1, 2, 3, but any other processing scheme is applicable to the invention, as long as there is a need for processing the control information and code symbols, respectively data bits together. Storage problem of the control information and code symbols In the course of the processing of the code symbols and the control bits in the processing means, there will always be the necessity to perform at least an intermediate storage of the information in a memory of the processing means, e.g. due to an interleaving process . Such a storage requirement may or example be satisfied by the interleaving memory IM. Whilst the problem of how to store the data information together with the control information before transmission is thus a general proble that already occurs when considering only one user channel, of course, the problem becomes extremely severe when processing a great plurality of user channels (e.g. up tc 30C ' as m Figs. 1, 2, 3. The amount of data to be processed within each time interval of a frame (e.g. T = 10 ms ,) gets very large. Therefore, the processing time and/or the memory requirements to perform channel encoding, bit -interleaving and time-alignment are very demanding. Fig. 4 shows the conventional storage of data bits together wit control bits in a memory, e.g. m the RAM memory shown m Fig. 2 or in the interleaving memory IM m Fig. 3. Such a combined storage is achieved by the conventional combining means COM as is shown m Fig. 3. The data bits and the associated control bits are listed m the rows, where each row is identified by an address. If data of a great plurality of user channels must be stored, preferably code symbols are formed before storing data to the RAM and the control bits are combined with such code symbols. This is possible as long as the control information is related to the code symbols finally transmitted over the air interface. Therefore, a set of two data bits m one row represents one code symool of the data bit sequence wnich is tc £>e transmitted. As is shown m the example m Fig. 4, each data symbol (comprising two data bits) is used together with four control bits containing the control information and, if the memory positions only have a predetermined width of 4 bits, the complete information of 6 bits cannot be stored tnerem and thus the control information and tne data symbols have to be storeα m different memory locations (or different memories) . In addition, if tne data symools and a great variety of control information of many user channels has to be stored, a large memory, i.e., a large address space and many bits per address are necessary. Since it may oe desired to store data symbols together with tne control information for as many user cnanneis as possible to Keep RAM sizes and numoer of RAMs small, tne memory should oe configured sucn that as many memory positions as possible are available. For example, a 64Kbit memory can be configured so as to nave an adαress space of 16 kbit with a 4 bit width, while tne same memory only has an address space of aoout 8 kbit witn a bit widtn of c. Tnus , if data symbols of a specific length are to be stored together with a great variety of control information, obviously a large memory or more memories must be used or only a small number of user channels can be processed m a memory of a predetermined size. Fig. 5 shows how conventionally each bit U Q , d_ ... of a code symbol etc. is stored at a separate memory location IMQO/ I M oi of an interleaving memory IM (or generally m a memory of a processing means) . Already the separate storing of each individual bit of the data symbol thus requires a large memory. However, of course the situation becomes more severe, if also tne control bits need to be stored m the interleaving memory togetner with tne data bits. Furthermore, tne large memory naturally increases the read/write access time to this memory as will be explained below. Moreover, if the control information (bits) belong to respective code symbols to be transmitted and each input data bit is stored separately, then the control information would have to be stored N-times (e.g. N=2 for QPSK) Typical interleaving of an input data bit sequence BS comprising M αata bits dø , d- ± . .. d j ^-i is shown m Fig 5. Fig. 5 shows an interleaving matrix IM (i.e. m an interleaving memory) wnicn is written row by row and read column by column for performing tne interleaving of the data bits. Assuming that the input data bit sequence BS consists of M data bits and eacn bit is stored ir its own memory location, then tne interleaving matrix IM must have at least M memory locations IM Q Q, etc. m an mterleaver memory IM. Tne numoer of columns ^j and the nu oer of rows Kp depends m fact on tne interleaving depth wnicn is nere expressed as tne number of columns before tne writing of data bits ηumps to tne next rov.. Tne interleaving depth is always predetermined m an mterleaver and if the mterleaver depth is 1 , tnen the storage of M data bits requires rows . Conventionally, as is shown m Fig. 5, each data bit d 1 of the input data bit sequence BS is stored at one memory location IM nw nr defined by the respective row and column addresses n^=0, 1, 2...Nrø-1 and nr = 0 , ..., NR-1. AS explained above, the interleaving process itself consists of a write and read process to and from the interleaving matrix m Fig. 5. Each of the processes (writing or reading) for all channels must be accomplisned within a frame period when processing is performed a frame-wise manner, out both processes have to be fast enough to oe able to nandle the great number of data packets of all users m the system within one frame period, even if tne number of user channels US is very large. For example, Fig. 5, all data bits of one packet are written row by row starting m row 0 and all output bits are read column by column starting m column 0. Assuming the dimension of the bit - interleaving matrices to be M=Np* ^ (number of rows* numoer of columns) tne interleaving matrices must be filled completely rjy the αata n t sequences contained one frame the predetermined time period of one frame. Afterwards the proceαure is repeated tne next frame starting at rows 0 again. Tnerefore, m the afore-mentioned time interval of 10ms eacπ matrix has to oe accessed (written or read) NR*N W times. Ana as pacKets arrive sequentially this writing or reading is also αone sequentially . In the conventional metnod during reading, the read means RM outputs tne data bits as coαe symbols as required by the digital modulation method to tne modulator MOD. For example, the read means RM may combine the nits dø and α N after two read cycles by accessing the respective two separate memory locations thereof and then provide the bits as code symbol to the modulator MOD. It will be appreciated that a considerable amount of time is used to read and write the data if the number of user channels is large since all interleaver matrices are accessed sequentially. The time for accessing the matrices as well as the storage requirements for storing the matrices can therefore be very large when a great plurality of user channels is used or when the input data packets comprise a large number M of data bits. If, e.g., each data packet has M bits and U packets arrive in one frame, the total number of bits is either U*M bits (when υ each packet has the same length) or U bits (when the packets H = l have different lengths) for u=l...U. Whilst Fig. 5 for illustration purposes only shows the storage of the data bits d, of course the situation becomes more severe concerning the storage requirements, if the input data bit sequence containing M data bits is extended to also comprise a plurality of contrcl bits for each data bit respectively code symbol as shown in Fig . 4. SUMMARY OF THE INVENTION As explained above, generally and in particular for a CDMA- systerπ, each code symbol to be transmitted is stored together with its associated control information. If the control information is quite large for each code symbol, then the width of a memory location may be insufficient (when a predetermined address space is needed) , since each set of control bits must be stored together with its associated data bits (i.e. in form of code symbols, 1 . In case that there is a great plurality of control bits the memory may not provide a sufficient number of bits per address such that additional read/write accesses must be performed which additionally increases the access time and the memory requirements. In other words, if the width of the memory locations would be sufficient then the RAM may not have enough address space, i.e. not a sufficient number of addressable memory locations, to handle all the data of all user channels . Therefore, the object of the invention is to provide an mterleaver, a transmitter, and a method which allow the storage and transmission of code symbols of a great plurality of user channels together with its respective control information with high processing speed and without needing a large memory m the processing section. SOLUTION OF THE OBJECT This object is solved by an mterleaver according to claim 1 for interleaving input data bit sequences of M data bits comprising code symbols each consisting of a number N of data bits and control information consisting of a numoer L of control bits indicating specific states for each code symbol comprising combining means for combining the respective N data of eacn code symbol with the associated L control bits into a control information/code symbol data word of L+N bits; control information/code symbol encoding means for encoding said L+N bit control information/code sympol data words into data words of F bits, where K<L+N, according to a predetermined encoding scneme; and an interleaving memory for storing said encoded data words at memory locations tnereof . The object is also solved by a transmitter according to claim 11 for transmitting a data bit sequence of M data bits comprising code symbols each consisting of a number N of data bits together with control information consisting of a number L of control bits indicating specific states for each code symbol; comprising combining means for combining the respective N data bits of each code symbol with the associated L control bits into a control information/code symbol data word of L+N bits; control information/code symbol encoding means for encoding said L+N control information/code symbol data words into data words of K bits, where K<L+N, according to a predetermined encoding scheme; processing means for processing said code symbols of said encoded data words m accordance with their control information. Furthermore, tne object is solved by a method according to clairr 13 for interleaving input data bit sequences of M data bits comprising code symbols each consisting of a number N of data bits together with control information consisting of a number L of control bits indicating specific states for each code symbol; comprising the following steps: combining the respective N data bits of each code symbol with the associated L control bits into a control information/code symbol data word of L+N bits; encoding said L+N b t control information/code symbol data worαs into data worαs of K bits, wnere K<L+N, according to a predetermined encoding scneme; and storing said encoded data words at memory locations of a memory. This object is also solved by a method according to claim 18 for transmitting a data bit sequence of M data bits comprising coαe symbols eacn consisting of a number N of data bits togetner wit: control information consisting of a numPer L of control Pits indicating specific states for eacn code symool ; comprising tne following steps : comoming tne respective N data bits of each code symbol with the associated L control bits into a control information/code symbol data word of L+N bits; encoding said L-i-N control information/ code symocl data words into data worαs of Y bits, where K<L+N, according to a predetermined encoding scheme; processing said code symbols of said encoded data words m accordance with their control information; and transmitting said processed code symbols. The invention m particular provides the major advantage, that the width of each memory location m a given storage means can be held small . According to a first aspect of the invention, a combining means is used for combining the data bits of each code symbol with the associated control bits into a control information/code symbol data wore. A control information/ coαe symbol encoding means encodes tms data word into a data word of less bits according to a predetermined encoding scneme . Tms encoded data word is then stored at memory locations of the memory used m the processing section. Tήerefore, instead of using more RAMs with bigger data width and less addressable memory space, the data symbols and the control information according to the invention will pe encoded while using the available bit width. That is, by contrast to just storing control bits (e.g. four bits) togetner witn one αata symbol .e.g two bits of one symbol) one adαressaole memory location, tne invention is based on the comoinmg (encoding; of the data Pits together with the control bits ana the specific combinations (encoding! indicate a specific control function dedicated to the respective code symbol Tnus , a smaller bit widtn per memory location of the RAM can pe used leading to relaxeα memory requirements m the transmitter Having co omed tne data Pits and tne control bits and navmg encoded tne combination into a data word of a smaller numPer of bits, a memory having a smaller numPer of bits per memory location can pe useα. Tms means tnat , using a memory of predetermined size, less bits have to provided per memory location and thus a larger address space is obtained. According to a second aspect of the invention, the data word resulting from the encoding of the data bits combined with the control bits is stored at one single memory location in the memory. Thus, each memory location comprises an encoded entity that indicates the code symbol as well as the control information as one word. Thus, it is prevented that more than one memory location has to be used for one symbol . Advantageous embodiments of the invention Applying the encoding principle according to the invention to an mterleaver or the processing means of the encoder (or more generally the transmitter) , a preferred interleaver according to the invention comprises the combining means and the encoding means when writing to memory locations of the interleaving memory, whilst a decoding means is provided for decoding the respective data words when read out by a read means from the interleaving memory. Advantageously, the separated code symbols and control cits can be provided to a modulator, which performs specific processing on the respective code symbols dependent on the control bits, e.g. a specific power setting for individual code symbols. Hereinafter, the invention will be explained with reference to its embodiments as shown in the drawings and more specifically explained in the following description. Further advantageous embodiments, objects and improvements of the invention may be taken from the dependent claims . BRIEF DESCRIPTION OF THE DRAWINGS In the drawings : Fig. 1 shows a principle overview of a CDMA base transceiver station BTS, to which the invention can be applied; Fig. 2 shows an overview of the encoder block ENC shown m Fig. 1; Fig. 3 shows a principle block diagram of a digital transmitter according to the prior art, showing as summary diagram an interleaving memory IM arranged between a channel coder CC and a digital modulator MOD; Fig. 4 shows the storing of data bits and control bits m a memory according to the prior art; Fig. 5 shows the storing of code symbols m an interleaving matrix according to the prior art ; Fig. 6 shows an emoodiment of an mterleaver, encoder and transmitter according to the invention, specifically comprising an encoding means CI/CS ENC and a decoding means CI/CS DEC according to the invention; Fig. 7 shows the inventive encoding of data bits & control bits and tne associated control function m a memory according to tne invention; Fig. 8 shows a specific example for the combination of control bits FS, SS, MA, PW together with data bits Q, I when encoding the data m the encoding means CI/CS- ENC; Fig. 9 shows a similar coding table as m Fig. 8, showing m particular the decoding function of the decoding means CI/CS -DEC at the output of the interleaving memory IM shown Fig . 6 ; Fig. 10 shows the storage of the data an interleaving matrix, wherein the stored data words are a result of the encoding of the respective code symbols (N data bits) and control bits; Fig. 11a shows entries m the interleaving memory IM, wherein each entry indicates the data bit position of the respective data bits forming a code symbol selected from the input data bit sequence (the control bits are not shown m Fig. 11a) for the case of N=2 and N^=4 ; Fig. lib shows the entries of an interleaving matrix for N=4 and ^=4 similar as m Fig. 11a; Fig. lie shows the entries of the interleaving matrix for N=2 and an odd Nw=7; Fig. 12 shows an embodiment of the read/write means W/R for selecting the code symbols from the input data bit sequence ; Fig. 13a shows an embodiment of the shift register SHR shown in Fig. 12 including two register banks bO , bl for the case of N=2 and even N^. also showing an embodiment of the selection means as a switch means SW1 , SW2 ; Fig. 13b shows an embodiment of the shift register SHR shown m Fig. 12 including two register banks bO , bl for the case of N=2 and an odd w (here ; and Fig. 14 shows a flow- chart of an embodiment of the interleaving method of the invention using the register banks as shown in Fig. 13a. In the drawings, the same or similar reference numerals denote the same or similar parts or steps everywhere. Hereinafter, first the combining and encoding principle of the invention will be explained with reference to Fig. 6. It should, however, be understood that the invention is neither restricted to a CDMA system shown in Figs. 1, 2 nor is the invention limited to the case of a particular digital modulation scheme such as QPSK, 16QAM, etc. In principle, the invention is neither restricted to a frame- wise provision of the input data bit sequences, nor do the individual successive frames have to have the same length, since an interleaving can be carried out according to any length of the input data bit sequence. Also the interleaving depth need not necessarily be an even number. PRINCIPLE OF THE INVENTION Fig. 6 shows an encoder ENC similar to the configuration Fig. 3. Generally, the encoder for transmitting a data bit sequence BS of M data bits for each user channel consisting of code symbols of a number N of data bits together with control information CI of a number L of control bits indicating control functions for each code symbol according to the invention comprises a combining means COM, a control information/code symbol encoding means CI/CS -ENC and a processing means for processing the code symbols with their control information combined in an encoded data word. The encoder ENC may further comprise a encoder CC . The processing means can be formed by an interleaving memory IM, a write/read means W/R, and the control information/control symbol CI/CS decoder DEC. A transmitter TX including such an encoder comprises the combining means COM, the encoder CI/CS-ENC and the processing means for processing the output of the control information/code symbol encoding means CI/CS-ENC as well as the modulator BBTX as explained with reference to Fig. 1. It should be understood that a principle of the invention lies in the combining means COM and the encoder CI/CS-ENC with respect to the processing of the control bits and data bits, whilst the specific interleaving memory IM as well as the decoder CI/CS-DEC is a preferred embodiment of the processing means relating to the specific processing including an interleaving and a decoding as is shown in Fig. 6. As shown m Fig. 6, a selection means SM of a write/read means W/R selects code symbols from the input data bit sequence BS which consists of M data bits. A preferred embodiment cf how the selection can be done will be described below. A v/rite means WM writes the data words formed by the encoding means CI/CS ENC into the interleaving memory IM and a read means RM reads the data words from the interleaving memory IM. The code symbols each consisting of a number N of data bits are input to the combining means COM together with control information CI , i.e. the control bits for the respective code symbols. As described above, such control bits may indicate a frame start FS , a time slot start SS, a marker MA or a power bit PW for the code symbol (also combinations of these control bits are possible) . The control information CI is generally input and determined by a central processing unit of the transceiver station. However, it is desirable to transmit such control information CI together with the code symbols (as shown Fig. 4 and Fig. 7) . The combining means COM combines the respective N data bits of each code symbol with the associated L control bits into a control information/code symbol data word of L+N bits. As is seen m Fig. 7, the combination of data bits and control bits specify a particular function to be executed. The idea is that the control bits and the data bits are not processed separately from each other, but m a combined way, i.e. encoded to a specific data word indicating a specific function. Thus, in the encoded data word more information can be stored, whilst nonetheless the width of the memory does not have to be expanded . Fig. 7 shows each row a respective data word cf L+N bits formed by the combining means. After this combining procedure, a control information/code symbol encoding means CI/CS-ENC encodes the L+N bit control information/code symbol data words into a data word of K bits, where K < L + N, according to a predetermined encoding scheme. As already indicated m Fig. 7 (and further illustrated with more detail Fig. 8), the encoding to reduce the number of bits is only possible, if the total number of possible cases for the L+N bits is equal or less than 2^- a z a widtn O; F the available data width. Tnat is, combining the control bits and data bits into one data word and realizing that not all combinations of the L+N bits are possible allows to encode the data word into a data word with a smaller number of nits (or some cases can be treated equally) . If this combining means COM and the control information/code symbol encoding means CI/CS-ENC is used for providing data words as inputs to an interleaving memory IM, the interleaving memory IM stores the encoded data words at specific memory locations thereof as will be described with more detail below. A decoding means CI/CS-DEC preferably decodes the read out data words again into the code symbols and the control bits according to an inverse of the predetermined encoding scheme. Preferably, the modulator MOD then uses the decoded control bits for performing specific processing of the read out and decoded code symbols . As will be also explained below, a preferred embodiment of an interleaver using the means COM, CI/CS-ENC, the interleaving memory IM and the means CI/CS-DEC stores at each memory location of the interleaving memory IM one data word respectively consisting of the encoded combination of a code symbol and its associated control bits. A preferred embodiment of the transmitter also comprises a convolutional encoder into which a data bit sequence is input and which outputs data bit sets each including a predetermined number 1/r of bits resulting from a convolutional encoding of a respective data bit using a predetermined coding rate, e.g. r=l/2, in a convolutional encoder CC preceding said interleaving memory IM. With the provision of data bits in parallel by the convolutional encoder C , the selection process for selecting code symbols from the input data bit sequence BS can be accelerated, as will be seen with more detail in Fig. 13a. Fig. 8 shows an example similar to Fig. 7 how the combining and encoding cf the code symbols and the control bits FS , SS, MA, PW is performed. In Fig. 8 N=2 data bits (i.e. two data bits I, C for a QPSK modulation) together with L=4 control bits are combined into one data word consisting of K=4 bits. As is seen in Fig. 8, by the encoding of the bit row FS , SS, MA, PW (control bits) and I, Q (code symbol) more complex information for the functional behaviour of one code symbol can be compressed to less bits. Obviously, if the control bits FS , SS, MA, PW are stored without an encoding then 64 (2 6 =2 N+L ) different possibilities can be indicated. These 64 possibilities can of course not be maintained in the case of performing the encoding. That is, a reduction to 4 bits is only possible with the encoding, if some of the 64 combinations are actually not used or are redundant. However, if it has been realized that some of the combinations are not necessary, then, due to the encoding, in total only 4 bits are sufficient . This is only the case if from the 64 possible combinations of control bits and code symbols some cases do not occur at all or if two or more cases can be combined to one case (see "X" don't care i Fig. 8) . Thus, the number of bits K is e.g. determined by lld(2N+L _ N U )] if Nu denotes the number of combinations which are not used or are redundant . The column "encoded data value (in hexadecimal notation)" denotes the encoded data word resulting from the encoding of the 6 bits formed by the 2 code symbol and the 4 control bits. As is seen, even though each combination of I , Q has associated combinations of control signals (see e.g. the row for the encoded data words 4, 5, 6, 7, where both SS and PW are "1"; , the 16 different control functions for the individual code symbols can be encoded (as expressed with the hexadecimal notation) to only four bit (16 data words) . Despite only using 4 bit the encoded data word, there are still functions defined where Q, I can be arbitrary and still a specific control function is associated with it (see e.g. the hexadecimal values C, D, E and F) . Thus, these bits denoted with "X" are irrelevant for the formation of the data word. However, as it is seen from Fig. 8, there is no necessity to use all combinations of the 6 data control bits, since in fact the combination of the data bits and the control bits can be encoded into an encoded data word of a smaller number of bits, here K=4 for covering the max. 16 possibilities. The reduction of 6 bit to 4 bit reduces the memory space requirements (and possibly also the memory access time) as already explained above. A preferred storage of the encoded data word is such that the complete encoded data word of K bits is stored a one memory location, since each memory location in the interleaving memory IM (or in fact in any memory in a processing means of an encoder or transmitter) has a predetermined width that allows to store more than one bit. This will be further highlighted with reference to Figs. 10, 11 and 12. Any configuration of a transmitter and encoder using a processing means for processing code symbols together with control bits may benefit from the encoding as is shown in Fig. 8. Therefore, the invention is not restricted specifically to the usage and the storage requirements with respect to an interleaving, although the interleaver is a preferred embodiment of the invention. With respect to the preferred terleaver, Fig. 9 shows the function of the decoding means CI/CS-DEC provided at the output of the interleaving memory IM. That is, reading out an encoded data value 0, 1, 2, 3 ... A ... F (hex notation) from the interleaving memory IM by the read means RM a decoding can be performed to extract the data bits I, Q, as well as the control bits FS , SS, MA, P . Thus, the control information, which was originally sent as configuration data from a base station control means to the combining means COM, is now obtained again and can for example be preferably used by the modulator MOD. As shown m Fig. 9, the combinations of "X" for I , Q m Fig. 8 have been decoded or set with the data bits "0" during the decoding of the encoded words C, D, E and with the data bit "1" during the decoding of the encoded word F. However, since their specific data bit has no meaning before the encoding, they can be set to an arbitrary value. Thus, the combining means, the encoder and the decoder cooperate such that during the processing, i.e. during the interleaving, a smaller number of bits are stored m a memory of tne processing means, for example m the interleaving memory IM, sucn that the memory requirements can be reduced. Since a smaller number of bits need to be processed and transmitted this can potentially also reduce access and processing times m other units of the system. Fig. 10, Fig. 11 and Fig. 12 show specific embodiments of an terleaver using such an encoding and decoding of data words as snown Fig. 8, Fig. 9 m comomation with Fig 7. Special storage of the code symbols/control bits As explained above, due to tne data encoding m Fig. 8, a data word is formed wnich nas a smaller number K of bits m comparison with tne complete number NTL of bits available witnout tne encoding. Again one possiPility would pe to also store tne encoded data word witn its bits at separate memor locations in tne interleaving memory IM as explained apove for tne prior art m Fig. 5, or witn tne full bit widtn at one address . According to a preferred embodiment of the terleaver according to the invention, a special storage of the encoded data words is performed as generally shown m Fig. 10. In principle, each encoded data word is stored at one memory location. That is, whilst Fig. 5 shows the "bit-wise" storage of the data bits the terleaver matrix, Fig. 10 shows the usage of the IL matrix with encoded data words formed by the encoding of the data bits &_ control bits . Before coming to a more detailed discussion of Fig. 10, one important aspect regarding the interleaving matrices should be noted. This aspect also relates to the interleaving matrix in Fig. 5. That is, as explained above, each pacKet contains a "data bit sequence" consisting of K λ bits. Each "data bit sequence" fills one interleaving matrix. Tnerefore, each interleaving memory typically comprises several (a plurality of ) interleaving matrices. That is, each interleaving matrix separately interleaves the data bits belonging to one packet. Fig. 10 snows the mterleaver matrix having a number of locations IM , I Q I, ■ ■ • for storing tne encoded data words. As snown m Fig. 10, each location stores, an encoded data word ( V bits) resulting from an encoding of a data word consisting cf a respective code symbol comprising a predetermined number N of data bits selected from the input data bit sequence BS plus its associated control bits (L bits) . Whilst Fig. 10 shows an example N=2, i.e. each code symbol consists e.g. of two pits I and Q for a QPSK modulation representation, tne principle snown m Fig. 10 is generally applicable to any integer value of ϊ ~ . According to the invention, an intrinsic property cf performing the interleaving m a interleaving memory is that each memory location can not only store one single individual bit, but a plurality of K bits for example K= , K=5, K=16 or even K=32 bit for eacn memory location. Assuming that the encoded data word stored in each memory location consists of K bits, then the size of the interleaving matrix can be reduced to N^*NR/K memory locations, whilst the interleaving matrix can still store the M data bits of the input data bit sequence together with the control bits for each code symbol . N w denotes the number of columns corresponding to the interleaving depth and thus for storing M data bits as encoded data words (K bits) resulting from an encoding of a respective code symbol (N bits selected from, the M data bits) plus its control bits (L bits) using a predetermined interleaving depth, the interleaving matrix only comprises N R /K rows. Since in Fig. 10 the numbering m the column and row direction starts at 0, the highest column address is N^-l and the highest row address is NR/K-1. Thus, selecting from the input data bit sequence of M bits respectively a number of N data bits as one code symbol, combining these N code symbol data bits with the L control bits in the means COM, encoding the N+L bits as an encoded data word of K bits and storing the encoded data word in one memory location, the access time and the needed memory space for the interleaving matrix IM in the interleaving memory can be reduced . Of course, assuming that the same data bits as in Fig. 5 will again form the code symbol (e.g. for N=2 the combination of dø , d N ) data bits of the data word before they are coded together with the control bits it is assumed that during the writing process in the row direction the respective data bits of the input data bit sequence are already present as the required set of data bits forming the corresponding code symbols. This selection of the appropriate data bits (for forming the code symbols cf the respective data words) from the input data bit sequence by the selection means SM will be explained below with reference to Fig. 11a, lib, lie. Since the CDMA base transceiver station BTS schematically illustrated in Fig. 1, Fig. 2 uses a QPSK modulation (i.e. N=2) the storage of all bits of an encoded data word resulting from an encoding of a code symbol (N bits) and its control bits (L bits) at one memory location as shown in Fig. 10 can advantageously be applied to this transmitter. That is, the user data (data bits and control bits) is not stored bit-wise but data-word-wise (I and Q data bits together with the control bits encoded as a data word having K bits) in the interleaving matrix, since the modulator MOD requests the provision of code symbols consisting cf two bits I and Q and their associated control bits. Thus, the symbols dø & • • • '< ..-! & d2N . ,-i are selected for the data word to be encoded with its control bits and to be stored in the first row 0 in the interleaving matrix. Assuming an encoding to K bits it automatically follows that the number of rows required is only N /K whilst the number of columns remains N^ (i.e. the interleaving depth is the same as m Fig. 5) . Storing the symbols as indicated m Fig. 10 decreases at least the read time from the interleaving matrix. That is, for the read process the matrix only has to be accessed ^*NR/K times now. In the write process, bits will be written to the matrix alsc only ^* R /K times. However, this presupposes that the code symbols, e.g. dø , d are already available as a data bit pair selected from the input data bit sequence by the select means before they are combined with the corresponding control bits to the respective data word which is then encoded to K bits before storage as an encoded data word of K bits in one memory location in the matrix. Since the data arrives serially from the convolutional encoder, the select means SM is provided to select the appropriate bits from the serially arriving input data bit sequence. According to one embodiment of the invention shown in Fig. 12, 13, this can advantageously be carried out by using a plurality of registers as explained below. However, before coming to a specific discussion of the embodiment of the selection, combining, encoding and storage process with respect to the code symbols representing the QPSK modulation (N=2), Fig. 11 is used to generally describe which data bits need to be selected for each code symbol (depending on an arbitrarily selected interleaving depth N^ and code symbol length N) , i.e. selected for the combination with the corresponding control bits as the respective data word to be encoded before storage in the memory. The illustration in Fig. 11a, lib, lie respectively only show the data bits of the code symbol of the respective data word before combining and encoding them together with the control bits. Hereinafter, the selection process for the appropriate data bits forming one code symbol is described, however, it should be understood that the code symbols are of course first combined and encoded together with the control bits before they are written to the respective memory location as an encoded data word of K bits (K<N+L) . As was explained above, generally a read/write means (see W/R in Fig . 6 or Fig. 12) is provided for writing an encoded version of the data bits (code symbols) together with the control bits intc the memory locations such that each memory location stores the encoded data word consisting of K bits resulting from the encoding cf a data word consisting of a number N of selected data bits forming one code symbol together with the control bits and for reading out said encoded data words as K bits again from said memory locations and decoding them again into a data word consisting of the code symbol data bits (N bits) and the control bits (L bits) to provide the interleaved output data bit sequence of the stored code symbols and the control bits to the modulator MOD. Interleaving is achieved by different address generation for write and read process. Essentially, the modulation scheme determines how many data bits and which data bits need to be combined from the input data bit sequence. For explaining the selection of data bits from the input data bit sequence BS by the select means SM the following assumptions are made. The bit positions m the input data bit sequence are numbered m=0 , 1 , 2... M-l , i.e. the first arriving data bit has the index m=C . The interleaving depth (i.e. the number of columns) is Ntø and tne first column index is denoted n^=0. Likewise, tne number of rows necessary m order to store the M data bits is NR/K (K being the total number of bits after encoding the selected data bits together with their control bits) and the first row index is denoted n^=0 (see Fig. 11) . N denotes the number of data bits per code symbol and n=l denotes the first data bit, n=2 denotes the second data bιt...n=N denotes the N-th bit of the code symool . Fig. 11a shows the example for N=2 (i.e. QPSK modulation; and Fig. lib shows the example for N=4 (i.e. 16QAM) Tne numoers m the matrices Fig. 11a, lib denote tne bit position m of tne input data bit sequence having M data bits . Whilst Fig 11 shows for illustration purposes the bit positions m of the respective data bits forming the respective code symbols, tne additional control bits, which are stored together with the code symools are not illustrated, since tney do not undergo tne selection process oy the select means SM, but are only appended to tne respective code symbol the combining means COM. The combination of selected data bits and the appended control bits is then encoded into tne encoded data word . In Fig. 11a an equation is stated that indicates the bit position m of the data bits that need to be combined for each code symbol and memory position. That is, the bit position m in the input data bit sequence is expressed as: m=n w + (n-1) *N w +n R *N w *N (1) That is, each code symbol is formed by N respective data bits respectively selected from the m-th positions (as indicated with the above equation) of the input data bit sequence, where n=l,2...N denotes the n-th data bit of the code symbol, Q , 1...Ntø- 1 denotes the column address cf the memory location of the code symbol and np=0,l... (NR/K-1) denotes the row address of the memory location of the respective data word comprising the encoded combination of the code symbol together with the control bits . This is illustrated with an example in Fig. 11a (see the framed code symbols) . For example, if the memory location IM Q Ø of the location n^=0, n^=0 in the top left corner is to be specified, then N w and N is entered in the above equation (1) and m(n=l)=0 and m(n=2)=4 indicate that the 1-st and the 5-th bit of the input data bit sequence is selected to form the code symbol IMøo= ø,d (or _j , dø , depending on the location of the most significant bit) . The code symbol IMτ_τ_=d9 , 0^3 is formed by the 10-th and the 14-th bit of the input data bit sequence. This is carried out for all two-bit code symbols in Fig. 11a. Likewise, in Fig. lib four data bits form one code symbol whilst still the above equation (1) can be used fcr determining the bit positions to be written to the respective memory location. The above equation (1) also holds generally for an arbitrary interleaving depth N^ in the column direction. Thus, effectively the same code symbols as would be supplied by an IL line in Fig. 5 are also supplied by an IL line in Fig. 10 using the general expression in equation (1) , but the memory locations now each store a data word resulting from an encoding of the respective code symbol with its control information which are - after reading out and decoding - to be provided to the modulator MOD. This generally reduces the access time and the memory requirements . The selection cf the data bits according to the above given equation (1) is general and independent of the special combination of N^j, N and M and K. However, the main advantage is that the input data bit sequence having a length of M=Nw*N R bits can be written and read from the interleaving memory as data word resulting from an encoding respective code symbols together with their control bits) in only N W *N R /K write/read cycles. As explained above, a method cf the invention for interleaving an input data bit sequence of M data bits using an interleaving memory having a number of memory locations for storing the M data bits comprises a simultaneous selection of a predetermined number N of data bits from the input data bit sequence to form a respective code symbol (as illustrated with the above equation (1) and with reference to Fig. 11) and the combination cf the code symbols with the control bits and the encoding of the combination into an encoded data word of smaller length (i.e. number cf bits) . As can be seen from the above description, the interleaving scheme is also independent of the convolutional encoder, however, the input data bit sequence BS of M data bits can preferably consist of data bit sets each including a predetermined number l/r of bits resulting from a convolutional encoding of a respective data bit using a predetermined coding rate, e.g. r=l/2, a convolutional encoder CC shown m Fig. 6. However, the only information needed by the write/read means W/R is how long the input data bit sequence is (e.g. M) before a combining with the control bits, an encoding and a writing of the interleaving matrix should be performed. Whether or not the actual data bits of the bit sequence relate to encoded or uncoded bits is of no relevance for the interleaving process itself, but the case of convolutionally encoded bits, these bits can arrive parallely and thus the writing time, more specifically a preload time, can be reduced during the selection process as explained below with further details. FIRST EMBODIMENT OF THE WRITE/READ MEANS Fig. 12 shows an embodiment of the write/read means W/R used for selecting the data bits from the input bit sequence BS before they are combined, encoded and written as encoded data words to the interleaving matrix m the row direction and for reading out the encoded data words sequentially m the column direction to provide interleaved encoded data words which are tnen decoded into the data bits and the control bits to be provided to a modulation unit MOD generally shown Fig. 6. As shown m Fig. 12, the write/read means W/R comprises a shift register means SHR, a select means SM, a write means WM , a read means RD, a preload means PLD and a shift means SHFT . User data, i.e. the input data Pit sequence BS , is input to tne snift register means SHR. It should be noted that tne emoodiment using a shift register means SHR and a select/write means SM/WM is only one emoodiment of the invention in order to select the data bits from the input data bit sequence BS which are supposed to form a respective code symbol to be combined with the control bits in the combining means COM. Other embodiments are also possible, as long as the selection of the appropriate data bits for the formation of the respective code sy bols is guaranteed. Independent of the number N of data bits forming the code symbol and independent of the interleaving depth ^ one possibility of the selection of the data bits is of course to use a single shift register of length M, whereafter the select/write means SM/WM will run through the complete data bit sequence of M bits and will perform the respective selection of the data bits. However, this may not be a very feasible solution, since the number of data bits M per bit sequence may be very large. However, for the sequential formation of the code symbols it is not necessary to have available the complete data bit sequence of M bits in a shift register, but it is only necessary to have available in a shift register respectively at each clock timing the two (or N) bits that will form the respective code symbols. As is seen in Fig. lia, lib and as is also indicated with the above equation (1) , it is sufficient to have available simultaneously in a shift register means SHR the respective data bits of bit positions m (n=l) , m (n=2) ... ir. (n=N) which respectively form a code symbol. Therefore, the length of the shift register in the shift register means SHR only need to be N*N W or it is possible to provide N registers each having a length cf ^ . Stepping through the memory locations by changing the row index (the writing of code symbols is performed in the row direction) , of course a shift means SHFT is necessary in order to sequentially shift the registers m order to have available in the shift register the data bits to be stored (encoded with the control bits) as encoded data words in tne new memory location, whilst during the shifting of the shift register already new bits can be read in from the input data bit sequence . As will be explained below, with a more concrete example for N=2 in Fig. 13a, Fig. 14, it is possible to always read data bits from a first register at particular register positions and then switch to the reading from another register in the next step, wherein the next step here means that the next memory location in the row direction is written with an encoded data word resulting from the encoding of the selected data bits (code symbol) together with their control bits. If for example the even index input bits of the input data bit sequence are stored in a first register and the odd index bits are stored in a second register, then a code symbol reading can be carried out alternately between the first and second register if N w is an even number. Namely, as is seen in Fig. 11a, lib, independent of the selected number N, a present code symbol, e.g. d , d 4 , dg , is always formed of bits at even bit positions whereas the code symbol for the next (row-wise) memory location is formed by 0^,05,03, i.e. bits at odd bit positions before they are combined with their respective control bits. Therefore, in Fig. 11a two bits are respectively read alternately from the first and second register. It is interesting to note that this alternate reading from the registers is independent of N, however, it is not independent of . As is shown m Fig. lie, for N^,j=7, i.e. for an odd N w , each code symbol of the respective data word is formed by a combination cf a data bit at an even position and a data bit at an odd position (e.g. d , 0 7 or 0^5,022' • This is also generally true for any N, as is indicated with the dashed line in Fig. lie. However, the above-mentioned equation (1) generally also holds for this case, since it indicates the exact bit positions to be read from the input data bit sequence. Also in the above case for an odd N^, i.e. an odd interleaving depth, only one register of length N*N^ or N registers of length N^j will be sufficient, only that now bits will have to be read from specific bit positions from several registers simultaneously. As will be appreciated from Fig. 11a, lib, as long as w is an even number, the odd bits can always be read for each code symbol independent of N from one register and the even bits from the other register. In Fig. lie, for the general case of N^T being odd, it is possible to derive relationships as to which bit positions should be alternately read from all the shift registers for each N. SECOND EMBODIMENT (N=2 AND R=l/2) Hereinafter, with reference to Fig. 13a, Fig. 14 an embodiment is described for forming code symbols consisting of two data bits, i.e. N=2 for an arbitrary (even) N . It should be noted that this embodiment advantageously uses parallely output data bits from a convolutional encoder operating with a coding rate of r=l/2, however, it is also possible that the data bits arrive serially, which case different timing relationships must be considered. However, the embodiment with several shift registers as shown Fig. 13a and described hereinafter is not restricted to a combination with a particular convolutional encoder of r=l/2, since the number of (parallely; output data bits from the convolutional encoder is not directly linked to the number of data bits forming one code symbol. That is, the channel encoder performs a special channel encoding outputting a predetermined number cf bits, whilst the modulation scheme (QPSK, 16QAM etc.) the modulator determines how many data bits form one code symbol . As is seen Fig. 13a, the embodiment of the shift register means SHR comprises two shift register banks bø , b each consisting of a first register børø, b ] _rø and a second shift register børη , bir . The length of each shift register corresponds to the interleaving depth ^ . The switch means SW1 , SW2 output the data bits to be stored at the respective memory location m the interleaving matrix IM (together with the respective control bits as an encoded data word) whicn is addressed by the write means WM . That is, the shift registers are located before combining means and the bit interleaving matrix IM (e.g. a RAM) used for interleaving. As is seen m the section "after preload" (the preloading will be described with more detail below) the first register of the first bank bør stores Nw data bits of even bit positions m the input data bit sequence. Similarly, the first register of the second bank b ] _r stores data bits from the odd bit positions of tne input data bit sequence, respectively indicated witn d , θ2 , ■ • • , d_2N w -2 anc ^ ^1 ' ( ^3,--- ' < ^2N--l ιn Fig 13a As stated above, various possibilities can be used m order to nave the odd and even bits present m tne first and second respective register. In a preferred embodiment, it is easy to clock m the respective odd and even data bits into tne two registers, if the convolutional encoder outputs two bits parallely for a r=l/2 encoding. Such bits tnen arrive on tne two data lines coming from tne convolutional encoder as is scnematically snown m Fig 13a (data 0, data 1) . Tne provision of the registers (having length N- Λ τ and having bit positions numoered 0, I... , N w pegmnmg with tne least significant bit position 0 at the far right) will allow to form the code symbols to be combined and encoded with the control bits for all memory locations of one row, as may be taken from Fig. 11a. As can be seen from the "write step 1", each code symbol m Fig. 13a (for even ^ consists alternately of two data bits selected from two specific bit positions m one respective register. In Fig. 13b (for odd ^) each code symbol consists of two data bits selected for two respective bit positions m two separate registers as explained below m more detail . That is, the select means SM respectively reads the least significant bit dø at the least significant bit position 0 at the far right end m Fig. 13a (which was tne first bit loaded during the preload phase) and the bit d at the bit position N w /2 (if the bit positions are numbered from 0 to N^-l as described above) which are output as code symbol and which are then combined and encoded together with the respective control bits and written to memory location IMØ Q . For the example m Fig. 11a, this would be the code symbol (0,4) . Tnen, tne switch means SV.l , SW2 switches tc tne first register of tne second register Dank b ] _ , rg containing the bits of tne ode bit positions. Thus, the code symbol d^ . d^ i is read from the least significant bit position 0 at the far right end m the register and the bit position N w /2 the shift register bη_rø . For tne example Fig. 11a, this would be tne coαe symbol (1,5) . As is also indicated m "write step 1", after each reading tne shift means SHFT shifts the register which was read m tne last write cycle. That is, when a bit pair is read from the first register of the second ban.:, the first register of the first bank is shifted one bit. Tnus , tne first register of tne first bank is prepared to allow the reading out of the next code symbol for the next memory position from the same bit positions as before. Simultaneously, as is indicated in the "write step 1" the data bits of the next 2 ^j bit positions are read into the second registers of the first and second bank, where again the second register of the first bank stores the even bits and the second register of the second bank stores the odd bits. That is, while one register m a bank is loaded with bits, two bits of the other one are read out to the interleaving matrix IM. The two registers of each bank change their function alternately after N w clock periods. It is seen from Fig. 10, that the writing of one memory location m the matrix requires the provision of pairs of data bits, e.g. dø , d N which are then combined with the control bits and encoded. Actually stored at the memory location are then the bits of the encoded data word. The provision of four registers as m Fig. 13a enables a pre-stormg of the bits as well as a grouping of bits and selecting of bits pair-wise, whilst still only N^ clock periods are necessary for forming the respective pairs of one row. Thus, the write time becomes the same as the read time since every period (N w cycles) 2*N^ bits can be stored to the interleaving matrix . As is shown m Fig. 13a an additional "preload" time is needed by a preload means PLD for loading the shift registers SHR for the first time. As will be appreciated, since one row (e.g. row 0) Fig. 10 has to store a total cf 2Nrø bits, the shift register SHR has to have a length cf 2* ^ if data arrives from the convolutional encoder m a serial form. Due to the fact that the data arrives serially at the mterleaver ® Fig. 2, i.e. serially at the shift register SHR m Fig. 12, 2N^ clock periods are needed addition to tne write accesses principle. However, m a convolutional encoder of rate, e.g. r=l/2 two bits dø , d_ are generated m a parallel form and the two bits could arrive at the same time. If the bits thus arrive m parallel, a reduction of the preload time needed by the preload means PLD for loading the shift registers rø with the odd and even bits can be achieved, when the two registers with length N^ j are loaded during the "preload" time of now only N w clock periods. Tnerefore, the combination of a convolutional encoder of r=l/2 with code symbols of N=2 is a very advantageous embodiment. Tnen the clocking m of data bits m pairs of two can be performed at the same clock rate as tne reading out of the respective two bits from the respective shift registers. That is, during tne clocking m of 2N^ bits, exactly 2N^ bits for code symbols of memory locations m one row are read out from the respective other registers and are then combined with the control information bits. Therefore, whilst m general the idea of the invention is directed to the symbol-wise combination of two bits together with tne control Pits and to tne encoding of the data word formed therefrom ana tne storing of bits of tne encodea data word m one location of the interleaving matrix, it is particularly advantageous if tne QPSK modulation method togetner with a convolutional encoder of rate 1/2 and two parallel snift register banKs is used. However, as explained aoove , tne invention can also pe generally applied with a single register of iengtn 2*N^_ only tnaf here tne "preload time" is twice as long. THIRD EMBODIMENT (INTERLEAVING METHOD FOR N=2 , EVEN N w ) Whilst the specific usage of the register banks is shown generally in Fig. 13a, where data bits from a convolutional encoder with r=l/2 are stored in four registers and where the data selection is done parallely, Fig. 14 shows a flow chart of the operation for the interleaving method of N=2 in Fig. 13a. In step S2 , the so-called "preload phase", in total 2N W bits are stored in registers 0 of bank 0 and bank 1. As is seen in Fig. 13a, the even bits d , d2-.. ^f w _2, < j . • • Q2N---2 are stored in børø (bank 0, register 0) and the odd bits ά 1 , d3... d^ j 1 , d Nw+1 ... 2N w -i are stored in b]_rø (bank 1, register 0) . Thus, a length of N^ for each register is completely sufficient. After completing step S2 , in total the bits dø to d2N w -i are stored in registers . In step S3 the bits stored in the two registers in step S2 must be combined to be written with the control bits encoded together to a first memory location 0 in the interleaving matrix. Therefore, in step S3 one symbol is read from those registers. Essentially, in Fig. 13a the gray-shaded rows in the "preload phase" correspond to the symbols stored in row 0 in Fig. 10 if the switches SWl, SW2 respectively select odd and even bits from the respective register. Simultaneously with the reading of bits from bank 0, register 0 and bank 1, register 0, the registers 1 of banks 0 and bank 1 are filled with a number of 2N bits intended for the next row 1 in the matrix in Fig. 1C . The next 2N W data bits are denoted 02^... to d4^___ 1 . The operation of the switch means SWl, SW2 is such that the correct pairs of bits are selected. While reading the registers a symbol is therefore built by taking two bits of one register. For the first symbol, the bits dø and d of register 0 m bank 0 are taken. Whilst m the position of the switches SWl, SW2 m Fig. 13a the data d , d have been read out from two particular bit positions of register 0 m bank 0, the switches are then set to read one symbol, i.e. 2 bits dη , d^ w+ ι from the register 0 of bank 1 at exactly the same bit positions m write step 2. Whenever a pair of bits has been read from a register, the contents of the register is shifted one bit to the right (as can be seen from the blank bit position m register 0, bank 0 m "write step 1" Fig. 13a) . If step S3/S4 tne switches SWl, SW2 have respectively oeen switched to read a pair from bank 0/1 the corresponding register is shifted one bit to the right. As is indicated with the square boxes at the arrows denoted data l, data q, m Fig. 13a these square boxes always indicate the last read pair of bits (one symbol) from the respective register. The alternate reading (and shifting! of a pair of bits respectively from Dank 0, register 0 and bank 1, register 0 m the write step 1 and tne write step 2 is performed total exactly N^ j times for setting one row of data symbols until the process cnanges to the alternate reading (again N w -tιmes) from bank 0, register 1 and bank 1, register 1 into which the next data bits nave been written during the alternate reading process from bank 0, register 0 and Dank 1, register 0. Tnuε , wnile reading tne register a symbol is ouilt by taking twc bits of one single register. For tne first symbol, tne bits dø and d^ j of register 0 m bank 0 are taken. Tne position for reaα out is kept, but m the second reading the register 0 of bank 1 is used and data bits di , ^ w _τ_ are read. Tnen the register contents is shifted to tne right. Therefore, once the preload step S2 is finished, the registers are shifted every second clock period (during the whole read period) while the output lines for the I and Q bits switch from one to the other bank with every clock period. Thus, the outgoing I bit and the Q bit will be stored as symbol together to the same memory address of the terleaver matrix IM. As is indicated m step S5 , obviously, after having read 2 ^j data bits, having combined them with the control bits, encoded same into an encoded data word and stored these as encoded data words in the matrix IM, the function of the registers 0, 1 of each bank is reversed. Namely, as explained above, after ^ j clock periods the complete data necessary for selecting symbols in the next row need to be read from the register 1, whilst the next data for the row 3 will again be stored m the register 0 of each bank. Essentially, table 1 shows the sequential reading of code symbols from the registers: Tabl e 1 Tne process described m Fig. 13a, 14 allows to fill the interleaving matrix exactly m N^*N R /K access steps, namely n exactly the same time that is necessary for reading out the interleaving matrix, wherein additional N^ cycles are needed for preloading the shift registers. Thus, the complete interleaving and forming of code symbols can be done m less time with less memory requirements. FOURTH EMBODIMENT (INTERLEAVING METHOD FOR N=2 , ODD N w ) As explained above, even when N^ is an odd number, the aoove described method can be applied. But then, step S5, tne positions for reading I and Q bits have to be changed after N^- clock periods. Tms is explained with reference to Fig 13b below . Fig. 13b shows step © the situation m the "after preload" as m Fig. 13a for the case of N=2 and an odd ^=7. 14 (=2N W ) bits are stored the registers b rø and b ] _rø and two bits 14, 15 will be written into the registers b r ] _ and b ] _rη , respectively, when bits 0, 7 are read out the first reading out process of "write step 1". In tne first N^ (N^=7) steps ©-G, code symbols are reaα out alternately either from the least significant bit position LSB (at tne far right end position 0) of the register børø and fro the central position (N^-l)/2 (if the bit positions are nurnoerec from 0 to N^-l as αescπoed aoove ι of the register b_rø or fror the central position of the register Pøi'ø and the least significant bit position LSB (at tne far right end) of tne register b_r whilst the respective even and odd bits are successively read into the registers which are fully filled after step G For the next cycle of steps beginning with step ©, the alternate reading starts again, now reading alternately the least significant position LSB in the register b r ] _ and the central position in register b ] _r ] _ and vice versa. Thus, the procedure for odd Nw is essentially the same as the one for even Nw, only that in the "write step 1" in Fig. 14, the reading is performed from two different banks bOrO <__ blrO and "m the write step 2" in Fig. 9 the reading is also performed from two different banks bOrO & blrO . In total, step S3 and step S4 together are carried out N w (=7) times, before the registers are switched in step S5. Essentially, table 2 shows the sequential reading of code symbols from the registers for odd Nw which is essentially the same as the one for even N^, only that two different registers are used for reading each code symbol pair: Tabl e 2 The result of a reading and writing process for Nw=7 is shown in Fig. lie. INDUSTRIAL APPLICABILITY As explained above, a first aspect of the invention resides m the combination of the control bits and the data bits of a respective code symbol and m the encoding of this combination into a new data word. Such a comDination and encoding process can be used at any stage m a processing means of a transmitter or an encoder. If the combining and encoding process is specifically used m an mterleaver, then the encoded data word is stored with all bits at one individual memory location m the interleaving memory IM, whilst after reading out the data words from the interleaving memory IM a decoding process again obtains the original code symbols and their associated control information (control bits) due to an inverse of the encoding scheme used during the encoding process. The control bits can then for example be provided to a modulator to perform specific processing for each code symbol . Furthermore, according to the invention the encoded data word formed by an encoding of a combination of the data bits together with the control bits is stored at one memory location of the interleaving memory , (or in general m a memory of a processing means of tne transmitter or encoder . Here, tne fact is used that each memory location can store more than one bit and thus the read/write time necessary for reading/writing to/from the memory can De reduced and a smaller size memory can be used. After reading out tne data bits of tne stored encoded data word this data word is decoded using an inverse of the encoding scheme used and tne code symbol data Dits and the respective control bits are provided to the modulator. Although the invention has oeen αescπbed specifically for a CDMA communication system, where a plurality of user channel provide a data information m packets, it snould be noted that the invention can be applied to any communication system, transmitter and receiver where code symbols need to be processed together with control information. Therefore, the invention is not specifically limited to the CDMA base transceiver station as described above . Furthermore, the invention is not restricted to any embodiment or example described herein and the above described embodiments are presently perceived as the best mode of the invention. Therefore, a skilled person can perform various modifications and variations withm the scope of protection on the basis of the above teachings. Furthermore, the invention can comprise separate features disclosed m the specification and described the claims even when not specifically mentioned m the description. Therefore, the scope of the invention is not limited to the specific embodiments described herein and comprises all features and combinations as defined by the scope of the appended claims. Furthermore, reference numerals m the claims only serve illustration purposes and do not limit tne scope of protection.

Claims: Claims An interleaver (IL) for interleaving input data bit sequences (BS) of M data bits comprising code symbols each consisting of a number N of data bits (e.g. I, Q for N=2) and control information (CI) consisting of a number L of control bits (e.g. FS , SS, MA, PW for L=4) indicating specific states for each code symbol; comprising: a) combining means (COM) for combining the respective N data bits (I, Q) of each code symbol with the associated L control bits (FS, SS, MA, PW) into a control information/code symbol data word of L+N bits; b) control information/code symbol encoding means (CI/CS- ENC) for encoding said L+N bit control information/code symbol data words into data words of K bits, where K<L+N, according to a predetermined encoding scheme; and c) an interleaving memory (IM) for storing said encoded data words at memory locations (IM00, IM01...) thereof . An interleaver (IL) according to claim 1, characterized by a write/read means (W/R) for writing said encoded data words to an interleaving matrix within said interleaving memory at specific memory locations (IMOC, IM01...) a row direction and for reading out said encoded data words from said interleaving matrix in the column direction and a control information/code symbol decoding means (CI/CS-DEC) for decoding said K bit data words read out from said interleaving matrix in said interleaving memory (IM) into said N bit code symbols and said L bit control bits (e.g. FS, SS, MA, PW) according to an inverse of said predetermined coding scheme . 3. An interleaver (IL) according to claim 1, characterized in that L=4 and N=2 , wherein said control bits (FS, SS, MA, PW) indicate a frame start (FS) , a time slot start (SS) , a marker (MA) , a power bit (PW) for the code symbol consisting of said 2 data bits. 4. An mterleaver (IL) according to claim 1, characterized in that one control bit (PW) indicates a transmission power ON/OFF control (PW) of said code symbols. 5. An interleaver (IL) according to claim 2, characterized in that each memory location (IM00, IM01...) stores one data word respectively consisting of said encoded combination of a predetermined number N of data bits selected from said input data bit sequence by a selection means (SM) of said write/read means (W/R) and said control bits. 6. An interleaver (IL) according to claim 1, characterized in that said input data bit sequence (BS) of M data bits consists of data bit sets each including a predetermined number (1/r) of bits resulting from a convolutional encoding (CC; of a respective data bit using a predetermined coding rate (e.g. r=l/2) in a convolutional encoder (CC) preceding said interleaving memory (IM) . J . An mterleaver (IL) according to claim 1, characterized in that said interleaving memory (IM) has N w x N R /K memory locations (IM00, IM01) for storing said the K data bits of the encoded data words, wherein w denotes the number of columns corresponding to the interleaving depth, K denotes the predetermined number of data bits forming one said data word and N R /K denotes the number of rows m said interleaving memory. 3. An mterleaver (IL) according to claim 2 and 7, characterized in that said write/read means (W/R) comprises a selection means (SM) for building code symbols by selecting N respective data bits from the [n + (n-l)N + n R N -N]-th positions of the input data bit sequence, where n = 1, 2...N denotes the n-th data bit of the code symbol, n = 0 , 1, ...N -1 denotes the column address m the interleaving matrix and n R = 0, 1, ... (N R /K) -1 denotes the row address m the interleaving matrix of the data word resulting from a combining encoding of tne code sympol and the additional control bits. 3. An mterleaver (IL) according to claim 8, characterized in that said selection means (SM) selects data bits for said code symbols from said input data bit sequence (BS) and provides said selected code symbol data bits to said combining means (COM/ and comprises for N=2 data bits per code symbol and even N : two shift register banks (bO, bl) each consisting of a first and a second shift register (rO, rl) of length Nw, wnerem the even and odd numoered data bits of said input data bit sequence are respectively stored in said first registers (rO) of said first and second shift register bank; select/write means (SWl, SW2 ) for selecting at each write cycle 2 data bits of the least significant bit position and the N /2 position from the first registers (rO) alternately from the first and second register bank and for providing said 2 selected bits as one code symbol to said combining means (COM) to be combined with said respective control bits; shift means (SHFT) for shifting the register (rO, rl) which was read at the last write cycle and the second registers of the register banks (bO, bl) while reading m the next odd and even bits of a next input data bit sequence to the respective second register (rl)of each register bank; and wherein after Nw alternate data bit selecting and shifting cycles the function of the registers is reversed . 10. An mterleaver (IL) according to claim 8, characterized in that said selection means (SM) selects data bits for said code symbols from said input data bit sequence (BS) and proviαes said selected code symbol data bits to said combining means (COM) and comprises for N=2 data bits per code symbol and two shift register banks (bO, bl) each consisting of a first and a second shift register (rO, rl) of length K , wnerem the even and odd numoered data bits of said input data bit sequence are respectively stored m said first registers (rO) of said first and second shift register bank; select/write means (SM/RW) for selecting at each write cycle 2 data bits alternately either from the least significant bit position (LSB) of the first register of the first bank (børø) and from the central position ((Nw-l)/2) of the first register of the second bank b ] _rø or from the central position of the first register of the first bank børø and the least significant bit position (LSB) of the first register of the second bank (b rø) , and for writing said 2 selected bits as one code symbol to a respective memory position m said interleaving memory; shift means (SHFT) for shifting the two registers (rO, rO) which were read at the last write cycle and the registers of the register banks (bO, bl) which were not read, while reading m the next odd and even bits of a next input data bit sequence to the respective second register (rl) cf each register bank; and wherein after Nw alternate data bit selecting and shifting cycles the function of the registers within each bank is reversed. 11. A transmitter for transmitting a data bit sequence (BS) of M data bits comprising code symools each consisting of a number N of data bits (e.g. I, Q) together with control information (CI) consisting of a number L of control bits (e.g. FS, SS, MA, PW) indicating specific states for each code symbol; comprising: a) combining means (COM) for combining the respective N data bits (I, Q) of each code symbol with the associated L control bits (FS, SS, MA, PW) into a control information/code symbol data word of L+N bits; b) control information/code symbol encoding means (CI/CS- ENC) for encoding said L+N control mformation/code symbol data words into data words of K bits, where K<L+N, according to a predetermined encoding scheme ; c) processing means (IL, MOD) for processing said code symbols of said encoded data words m accordance with their control information. 12. A transmitter (IL) according to claim 11, characterized by said processing means (IL, MOD) comprising a modulation means (MOD) for modulating said decoded code symbols m accordance to the specific state of the code symbol as indicated by the respective control bits. 13. A metnod for interleaving input data bit sequences (BS) of M data bits comprising cooe symbols each consisting of a number N of data bits (I, Q) together with control information (CI) consisting of a number L of control bits (FS, SS, MA, PW) indicating specific states for each code syrαool ; comprising the following steps: a) coπiDining tne respective N data bits (e.g. I, Q for N=2) of each code symbol with the associated L control bits (e.g. FS, SS, MA, PW for L=4) into a control information/code symbol data word of L+N bits; b) encoding said L+N bit control information/code symbol data words into data words of K bits, where K < L+N, according to a predetermined encoding scheme; and c) storing said encoded data words at memory locations (IM00, IM01...) of a memory. 14. A method according to claim 13, characterized by the following steps : writing said encoded data words to an interleaving matrix withm said interleaving memory at specific memory locations (IM00, IM01 ...) m a row direction and reading out said encoded data words from said interleaving matrix (IM) in the column direction and decoding said K bit data words read out from said interleaving matrix m said interleaving memory (IM) into said N bit code symbols and said L bit control bits (e.g. FS , SS, MA, PW) according to an inverse of said predetermined coding scheme. 15. A method according to claim 13, characterized by the following steps : processing decoded code symbols m accordance to the specific states of the code symool as indicated by the respective control bits. 16. A method according to claim 13 characterized in that L=4 and N=2 , wnerem said control bits (FS, SS, MA, PW) indicate a frame start (FS) , a time slot start (SS) , a marker (MA) , a power bit (PW) for the code symbol consisting of said 2 data Pits. 17. A method according to claim 13, characterized in that one control bit (PW) indicates a transmission power ON/OFF control (PW) of said code symbols. 18. A method for transmitting a data bit sequence (BS) of M data bits comprising code symbols each consisting of a number N of data bits (e.g. I, Q for N=2) together with control information (CI) consisting of a number L of control bits (e.g. FS , SS, MA, PW for L=4 ) indicating specific states for each code symbol; comprising the following steps: a) combining the respective N data bits (e.g. I, Q for N=2) of each code symbol with the associated L control bits (e.g. FS , SS, MA, PW for L=4) into a control information/code symbol data word of L+N bits; b) encoding said L+N control information/code symbol data words into data words of K bits, where K<L+N, according to a predetermined encoding scheme; c) processing said code symbols of said encoded data words m accordance witn tneir control information, and d) transmitting said processed code symbols. 19. An encoder (ENC) of a transmitter for transmitting a data bit sequence (BS) of M data bits comprising code symbols eacn consisting of a number N of data bits (e.g. I, Q for N=2) together with control information (CI) consisting of a number L cf control bits (e.g. FS , SS, MA, PW for L=4) indicating specific states for each code symbol; comprising : a) combining means (COM) for combining the respective N data bits (I, Q) of each code symbol with the associated L control bits (FS, SS, MA, PW) into a control information/code symbol data word of L+N bits; b) control information/code symbol encoding means (CI/CS- ENC) for encoding said L+N bit control information/code symbol data words into data words of K bits, where K<L+N, according to a predetermined encoding scheme; c) processing means (IL, MOD) for processing said code symbols of said encoded data words m accordance with their control information.

Inventors: HUAMAN-BOLLO GIAN, SOENNING RAIMUND, HUAMAN-BOLLO, GIAN, SOENNING, RAIMUND
Applicants: ERICSSON TELEFON AB L M, TELEFONAKTIEBOLAGET LM ERICSSON (PUBL)
Application year: 2000
Main classification: H03M13
IPC codes: H03M13