SILICON STRAIN GAGE HAVING A THIN LAYER OF HIGHLY CONDUCTIVE SILICON

Abstract: A semiconductor strain gage (10) having an electrically resistive substrate layer (12) and a layer of electrically conductive silicon (14) supported by the substrate layer. The silicon layer can be an epitaxial silicon layer grown on a surface of the substrate layer (12) or a diffused or ion-implanted layer formed on the surface of the substrate layer. Also, a force measuring and detecting device including a force responsive member and the above-described semiconductor strain gage (10) attached to the force responsive member, the strain gage measuring forces applied to the force responsive member.

Description: SILICON STRAIN GAGE HAVING A THIN LAYER OF HIGHLY CONDUCTIVE SILICON FIELD OF INVENTION This invention relates to a silicon semiconductor strain gage and in particular, to a silicon semiconductor strain gage compπsing a thin layer of highly conductive silicon on a semi-insulating host substrate layer. BACKGROUND OF THE INVENTION Silicon is commonly used as a semiconductor sensor matenal because it exhibits many large physical effects to vaπous applied sensitivities or signals and permits cost-efficient batch fabπcation of sensors. One very useful effect that silicon exhibits is piezoresistance. This effect is exhibited by silicon m response to an applied a mechanical strain. This effect is considerable in silicon because the average mobility of electrons and holes therein is largely affected by strain. Numerous strain gages based on silicon semiconductor mateπals have been designed and are presently available. Many of these strain gages are fabπcated from bulk single crystal silicon usmg conventional photolithography and etching techniques. A major disadvantage of such semiconductor strain gages is that their strain gage resistance depends directly on their thickness. When manufactured in bulk, the strain gage resistance from gage to gage can vary by a factor of 3 or more because current etching processes are incapable of maintaining thickness uniformity, on the order of 0.0005 inches or 12 microns. This mainly due to the pre-etching thickness of the gages which is typically about 0.006 inches and requires over 90% of the silicon to be removed. Overshooting the gage thickness by a mere 0.00 1 inch results in a 20% change in the gage's strain gage resistance. Accordingly, a need exists for a silicon strain gage with improved uniformity of strain gage resistance. SUMMARY OF THE INVENTION In accordance with the invention, a semiconductor strain gage compπsing an electπcally resistive substrate layer and a layer of electπcally conductive silicon supported by the substrate layer. The silicon layer can be an epitaxial silicon layer grown on a surface of the substrate layer or a diffused or ion-implanted layer formed m the surface of the substrate layer. In further accordance with the invention, a force measuπng and detecting device compπsing a force responsive member and the above-descπbed semiconductor strain gage attached to the force responsive member, the strain gage measuπng forces applied to the force responsive member. BRIEF DESCRIPTION OF THE DRAWINGS The advantages, nature and vaπous additional features of the invention will appear more fully upon consideration of the illustrative embodiments now to be descnbed in detail in connection 15 with accompanying drawings wherein: FIG. 1 is a perspective view of a silicon semiconductor strain gage according to an embodiment of the present invention; FIG. 2 is an elevational view of a force measunng and detecting device which employs the strain gage of the invention; and FIG. 3 is a perspective view of a silicon semiconductor strain gage according to a second embodiment of the invention. It should be understood that these drawings are for purposes of illustrating the concepts of the invention and are not to scale. DETAILED DESCRIPTION OF THE INVENTION FIG. 1 shows a perspective view of a silicon semiconductor strain gage 10 according to the present invention. The strain gage 10 of the invention is a piezoresistive device that utilizes a force to cause a resistance change due to mechanical strain. The strain gage 10 compπses a thin layer 14 of highly electrical-conductive (highly conductive) silicon of a desired conductivity type supported by a relatively highly electrical-resistive (highly resistive) host substrate layer 12. The host substrate layer 12 is typically composed of crystalline or polycrystalhne semi-insulating matenal, such as lntπnsic silicon or lightly doped (p or n type) silicon. The strain gage 10 of the invention is especially useful for measunng forces applied to metallic force responsive members of vanous configurations, such as beams, diaphragms, plates, rods and the like. Such force responsive members are commonly used in pressure measuπng applications as strain gage pressure transducers, in weight measuπng applications as strain gage load 15 cells and strain gage transducers, and in other measuring and like applications which use force responsive members. FIG. 2 shows a typical force measuπng and detecting device 20 that employs strain gages 10 of the invention. Such a device is descnbed in co-pendmg U.S. Patent application no. assigned to Measurement Specialties, Inc., the assignee herein. This Patent application is incorporated herein by reference to show an exemplary force measunng and detecting device which can utilize the strain gage device of the invention. The device includes a metal force responsive member 22 with strain gages 10 according to the invention attached thereto using conventional glass bonding or other suitable attaching techniques. The strain gages are attached to the force responsive member in a Wheatstone bπdge circuit. Although this device includes a force responsive member with four strain gages, one of ordinary skill m the art will recognize that force responsive members of other devices can employ as few as a single strain gage. As can be seen by refemng again to FIG. 1 , the strain gage of the invention can be conventionally configured in an M or sepertine shape. However, many other available configurations have been previously descnbed that are adapted for the direction and sense of the stresses or strains produced m a corresponding force responsive member m response to a force and/or are adapted for resistance changes produced by such stresses m crystalline silicon for a given conductivity type, crystal oπentation and direction of current flow. It is contemplated that the strain gage of the invention can be fabricated in virtually any of such strain gage configurations if desired. In a typical embodiment of the strain gage of the invention (FIG. 1), the highly conductive silicon layer comprises a 2-4 micron (0 00008-0 00017 inches) thick, 0 025-0 060 ohm-cm epitaxial silicon layer (epi-sihcon layer), and the host substrate layer comprises an 8-10 micron (0.00033- 0.00042 inches) thick, 10 ohm-cm or greater single crystal silicon layer This strain gage embodiment can be made in bulk by growing an epi-sihcon layer on an appropπately polished and cleaned surface of a single crystal silicon wafer using any conventional epitaxial deposition technique. Epitaxial deposition generally utilizes vapor-phase deposition in an epitaxial reactor. In a typical process, the polished and cleaned surface of the wafer is heated and the epi-sihcon layer is deposited thereon by reacting hydrogen with a silicon compound such as silicon tetrachlodde in a earner gas. The thickness and the conductivity of the epi-layer of silicon can be controlled by regulating the deposition rates and introducing controlled amounts of suitable dopants into the carπer- gas stream. After epitaxial deposition, the epi-layer side of the wafer is patterned into individual strain gages using conventional photolithographic and etching techniques The patterning typically extends about 12-14 microns into the wafer from the epi-layer side thereof. The substrate layer sideof the, wafer is then lapped from a starting thickness of about 0.015 inches to a thickness of about 100 microns. After lapping, the epi-layer side of the wafer is coated with resist matenal and the wafer is chemically back-etched using conventional techniques until the pattern of the gages are visible to provide an overall gage thickness (including the epi-sihcon layer) of 10 to 14 microns The resist matenal is then conventionally removed and metallized electncal contacts are formed on the epi- silicon layer portion of the gages. FIG. 3 shows a strain gage 30 according to a second embodiment of the invention. In this embodiment, a thin, highly conductive layer 36 is formed in a surface 34 of a silicon-based host substrate layer 32. This highly conductive layer can be formed by diffusion or ion-implantation. Although not shown, other embodiments of the strain gage can also compπse a highly conductive epitaxial silicon layer grown on an insulating host substrate layer made from single crystal alumina or any other highly resistive matenal that permits epitaxial growth of silicon. The strain gage of the invention advantageously provides a strain gage resistance which is generally independent of the overall thickness of the gage. A strain gage of the invention made from an 0.025 ohm-cm, 6 micron (0 00025 inches) thick epi-sihcon layer grown on a host host substrate of 25 ohm-cm silicon has the following resistance as a function of overall gage thickness: Overall gage Thickness Resistance 16.8 microns (0.0007 inches) 2994 ohms 14.4 microns (0.0006 inches) 2995 ohms 12.0 microns (0.0005 inches) 2997 ohms 9.6 microns (0.0004 inches) 2998 ohms 7.2 microns (0.0003 inches) 2999 ohms Another benefit of the strain gage of the invention is that it can be manufactured in large numbers with higher resistance values that are more uniform from gage to gage than conventional strain gages as demonstrated in Tables 1 and 2 below In particular. Table 1 shows the resistance values of strain gages selected from 5 different wafers of strain gages of the invention and Table 2 shows the resistance values of strain gages selected from 5 different wafers of conventional strain gages. All the strain gages were of the same dimensions. The resistance measurements were obtained by glass bonding each selected strain gage to a 0.072 thick beam-like force responsive member and applying the same force to each member. Table 1 Table 2 Using data from Table 1 , the strain gages of the invention boasted a mean resistance of about 4070 ohms, a maximum resistance of about 4460 ohms and a minimum resistance of about 3780 ohms. The standard and average standard deviations for these strain gages were 168.2 ohms and 97.1 ohms respectively and the percent average standard deviation was 2.39. In contrast, the conventional strain gages of Table 2 demonstrated a mean resistance of only about 1399.8 ohms, a maximum resistance measuπng about 1660 ohms and minimum resistance measuπng about 1190 ohms. The standard deviation for these strain gages was 111.754 ohms and the standard deviation was 7.984. While the foregoing invention has been descnbed with reference to the above embodiments, vaπous modifications and changes can be made without departing from the spint of the invention. Accordingly, all such modifications and changes are considered to be within the scope of the appended claims.

Claims: CLAIMS What is claimed is- 1. A semiconductor strain gage compπsmg: an electncally resistive substrate layer; and a layer of electπcally conductive silicon supported by the substrate layer. 2. The gage according to claim 1, wherein the substrate layer is composed of semi-insulating matenal. 3. The gage according to claim 2, wherein the semi-insulating matenal is silicon. 4. The gage according to claim 2, wherein the semi-insulating matenal has a resistivity of greater than 10 ohm-cm. 5. The gage according to claim 1, wherein the substrate layer has a thickness of about 8-10 microns. 6. The gage according to claim 1 , wherein the silicon layer is composed of epitaxial silicon. 7 The gage according to claim 6, wherein the epitaxial silicon has a thickness of about 2- microns. 8. The gage according to claim 1 , wherein the silicon layer has a resistivity of about 0.025- 0.060 ohm-cm. 9. The gage according to claim 1 , wherein the gage is useful for measunng forces applied to a force responsive member, the substrate layer permitting the gage to be attached to the force responsive member. 10. The gage according to claim 1, wherein the substrate layer is composed of insulating matenal. 1 1. The gage according to claim 10, wherein the insulating matenal is alumina. 12. The gage according to claim 1 , wherein the silicon layer is a diffused layer. 13. The gage according to claim 1 , wherein the silicon layer is an ion-implanted layer. 14. A force measuπng and detecting device compπsing: a force responsive member; and a semiconductor strain gage attached to the force responsive member, the strain gage measuπng forces applied to the force responsive member, the strain gage including an electπcally resistive substrate layer and a layer of electπcally conductive silicon disposed on the substrate layer. 15. The device according to claim 14, wherein the force responsive member is metallic. 16. The device according to claim 14, wherein the substrate layer is composed of one of a semi- lnsulatmg matenal and an insulating matenal. 17. The device according to claim 16, wherein the semi-insulating matenal is silicon and the insulating matenal is alumina. 18. The device according to claim 14, wherein the substrate layer has a resistivity of greater than 10 ohm-cm and a thickness of about 8-10 microns. 19. The device according to claim 14, wherein the silicon layer is composed of epitaxial silicon. 20. The device according to claim 19, wherein the epitaxial silicon has a thickness of about 2- microns. 21. The device according to claim 14. wherein the silicon layer havmg a resistivity of about 0.025-0.060 ohm-cm. 22. The device according to claim 15, wherein the substrate layer is glass bonded to the force responsive member. 23. The device according to claim 14, wherein the substrate layer is glass bonded to the force responsive member. 24. The device according to claim 14, wherein the silicon layer is a diffused layer. 25. The device according to claim 14, wherein the silicon layer is an ion-implanted layer.

Inventors: GROSS CHRIS, GROSS, CHRIS
Applicants: GROSS CHRIS, MEASUREMENT SPEC INC, GROSS, CHRIS, MEASUREMENT SPECIALTIES, INC.
Application year: 2000
Main classification: H01L29
IPC codes: G01L1