LINEAR FLASH MEMORY COMPATIBLE WITH COMPACTFLASH3 MECHANICAL INTERFACE

Abstract: A linear flash memory (110) with a linearly addressable memory space of up to 64 MB is implemented within the CompactFlash3 50-signal physical specification. This is achieved by sacrificing certain signals lines associated with the CompactFlash3 specification and mapping otherwise unavailable address lines to the unused signal lines to allow the host computer to address the linear memory through those additional address lines. The technology is particularly suited to embedded systems that require compact packaging such as provided by the CompactFlash DOLLAR (m)3 specification.

Description: LINEAR FLASH MEMORY COMPATIBLE WITH COMPACTFLASH® MECHANICAL INTERFACE S P E C I F I C A T I O N Field of the Invention The present invention relates to data storage devices for use in embedded and other applications and more particularly to linear flash memory devices that are partly compatible with the CompactFlash® specification. Background of the Invention In the early 90's, rapid growth of portable computers and embedded systems drove the development of smaller, lighter, and more portable systems. One of the developments that helped spur this trend is PC Card technology. The power and versatility of PC Cards quickly made them standard equipment in portable computers. Fast development and near-universal adoption of PC Card technology is due largely to the standards efforts of the Personal Computer Memory Card International Association (PCMCIA). One of the most popular applications of PCMCIA or PC-card technology as it has lately come to be called, are flash memories. Flash memories provide a fast portable mass storage device to replace the hard disks associated with notebooks and desktop computers. Another standard, CompactFlash®, provides an even smaller form factor than the PCMCIA standard and is well suited to embedded systems. Although the CompactFlash® specification provides a smaller form factor, the number of signal lines is substantially smaller than that of the PCMCIA specification. To address large memories, therefore, conforming memory devices are required to be addressed via a page mode process in which blocks of data are read from the memory and the particular data required retrieved from the blocks after they are read into the working memory of a host computer. CompactFlash® memory cards are used in many embedded system applications because of their small size. In many embedded system applications, data retrieved by the embedded system may routinely be downloaded from, or uploaded to, the mass storage of the embedded system device. A convenient way to expedite this process is to employ removable mass storage devices or media. This permits the mass storage devices to be collected from the embedded system users and read (or written to) by a single support computer. For example, measured data can be stored on the removable media used by distributed embedded systems (i.e., data loggers). This is a common situation. In many embedded system applications, data retrieved by the embedded system is routinely downloaded from, or uploaded to, the mass storage of the embedded system device. If the mass storage is provided by a detachable device, they can be collected from the embedded systems and consecutively read (or written to) by the support computer. For example, data downloaded could be data collected via the host data terminal (i.e., data logger). In some embedded systems, it is desirable to address a small detachable memory linearly. On a PC card, taking advantage of the 68 pin physical configuration of the PC card format, flash memories are built with a 26 bit address space of linearly addressable memory. Such linear flash memories generally map comfortably into the 68 pin PCMCIA standard interface. The CompactFlash® standard interface provides only 50 pins, and so flash memories built for this interface are generally addressed via the page mode system that does not permit particular addresses to be addressed individually and directly. (I.e., the memory is "random access memory" or "RAM.") Referring to Table 1, the pin assignments used to implement linear flash memories in a PCMCIA compatible format are shown. As can be seen, all of the signals of the linear flash device map comfortably into the PCMCIA format. There are 26 address signal lines in the linear flash memory. Table 1 - Signal Mapping for PCMCIA Card Referring to Table 2, the pin assignments used to implement CompactFlash® in a 50 pin standard CFA interface are shown. As can be seen, the CompactFlash® memory, with only eleven address lines, has a much smaller linearly addressable space than the linear flash and relies on a page addressing scheme to address a large address space. This is a severe limitation on devices that might seek to take advantage of a larger address space in the CFA specification's compact physical format. Table 2 - Signal Mapping for CompactFlash® Card Summary of the Invention The address space of CFA standard memories is only eleven bits wide. The requirement is, to address linear memory is 2 n =Mbit of non-volatile RAM, n discrete address lines are required. The address space of linear flash memory is much higher, but requires a large physical connection, at least in terms of the number of signal lines. There are many devices that can use the smaller physical size of the CFA form factor to advantage whilst also taking advantage of the larger number of address signals of the linear memories. The invention permits a linear memory device to be mapped into the physical format of the CFA interface. To accomplish the mapping of the linear flash memory with its larger number of address signals into the 50-pin physical configuration of the CFA interface, the data and address lines of the CompactFlash® format are followed up to the last of the CompactFlash® address lines, namely address line number 10. Beyond address line 10, address lines 11-23 are mapped variously to the signals that are dropped from the PCMCIA implementation of the linear flash memory. The following signals are not used in the Compact Linear Flash® physical configuration in comparison to the CFA® standard: #IORD, #IOWR, WP, R/B, RESET, #REG, #WAIT, #VS1, #VS2, #BVD1, #BVD2, #CSEL, and #INPACK. The "recovered" pins are mapped to address lines spanning 11-23. This provides a 24 bit linearly addressable space. According to an embodiment, the invention provides a memory card with a memory. The memory has N address lines and is packaged according to a standard that provides only N-M address lines. The standard provides P terminals to connect with a host computer. These P terminals are used to provide signals other than the address line signals. M of the P terminals are connected to M of the N address lines so that the linearly addressable memory conforms to the package standard while providing N address lines. Optionally, the memory may include a linear flash memory. Also, the package standard may include the CompactFlash® specification. Also, at least one of the P terminals is used, according to the standard, to provide a signal indicating a voltage requirement. According to another embodiment, the invention provides a computer with a linear flash memory packaged in a CompactFlash® housing. The CompactFlash ® housing provides a plurality of signal lines conforming to the CompactFlash® specification. A linear flash memory is wired to the plurality of signal lines such that the linear flash memory is linearly addressable. Preferably, the plurality of signal lines are address lines and the address lines are more than a number of address lines provided in the CompactFlash® specification. According to still another embodiment, the invention provides a memory device, with an electrical signal terminal conforming to a physical portion of a standard specification for computer peripheral devices. The device has a linear memory. The standard specification provides for page-mode addressing using a certain number of lines associated with the terminal, but the address lines actually used is greater than the number of lines provided by the specification, which contemplates page mode addressing. Thus, the actual number of address lines connected between the terminal and the linear memory permits a linear addressing of a larger space than would be possible if the number of address lines were limited to those provided for page mode addressing. Optionally, the standard specification is the CompactFlash® specification. The standard specification may be other than the CompactFlash® specification and still provide for a data bandwidth signal line that indicates a bandwidth of data transmission through the data signal lines. In this standard specification, at least one of the data bandwidth signal lines is usurped for use as an address line of the linear memory. The standard specification may provide for a write protection signal line and the write protection signal line may be usurped to serve as an address line of the linear memory. The non CompactFlash® standard specification may provide for a busy signal, which indicates that a host computer must wait for a process to be completed before attempting to read or write data to/from a device. This busy signal line may usurped and mapped to an address line of the linear memory. The non CompacfFlash®-standard specification may provide for reset signal line to reset the device that submits to the standard and this reset signal line usurped and mapped to an address line of the linear memory. The non CompactFlash® standard specification may provide for an attribute memory enabling signal line. This attribute memory enabling signal line may be mapped to an address line of the linear memory. The standard specification may provide for a voltage signal line that indicates a voltage to be applied to a device. This voltage signal line may be mapped to an address line of the linear memory. According to still another embodiment, the invention is a memory card, having a memory having N address lines. It is packaged in conformance with a standard providing N-M address lines and P terminals for connecting signal lines other than the address lines. M of the P terminals are connected to M of the N address lines so that the linearly addressable memory conforms to the package standard while providing N address lines. Note that the memory includes a linear flash memory. According to still another embodiment, the invention is a memory card, having a memory having N address lines. It is packaged in conformance with a standard providing N-M address lines and P terminals for connecting signal lines other than the address lines. M of the P terminals are connected to M of the N address lines so that the linearly addressable memory conforms to the package standard while providing N address lines, the memory including a linear flash memory. The package standard includes the CompactFlash® specification. According to still another embodiment, the invention is a memory card, having a memory having N address lines. It is packaged in conformance with a standard providing N-M address lines and P terminals for connecting signal lines other than the address lines. M of the P terminals are connected to M of the N address lines so that the linearly addressable memory conforms to the package standard while providing N address lines. At least one of the P terminals is used, according to the standard, to provide a signal indicating a voltage requirement. The invention will be described in connection with certain preferred embodiments, with reference to the following illustrative figures so that it may be more fully understood. With reference to the figures, it is stressed that the particulars shown are by way of example and for purposes of illustrative discussion of the preferred embodiments of the present invention only, and are presented in the cause of providing what is believed to be the most useful and readily understood description of the principles and conceptual aspects of the invention. In this regard, no attempt is made to show structural details of the invention in more detail than is necessary for a fundamental understanding of the invention, the description taken with the drawings making apparent to those skilled in the art how the several forms of the invention may be embodied in practice. Detailed Description of the Illustrated Embodiments Referring to Table 3, a linear flash memory is incorporated in a CompactFlash® mechanical package providing addressing for 32 and 48 MB of memory without the page addressing mode restriction otherwise imposed by the small number of address lines of the CompactFlash® standard. This is accomplished by sacrificing certain signals and mapping the unused lines so that they carry the additional address signals necessary to address up to 32 or up to 64 MB of memory directly. Table 3 - Signal Mapping for Compact Linear Flash Device The PCMCIA signals that are sacrificed to fit the linear flash memory into the CompactFlash® form factor are: • #CE2 - Card Enable 2. The choice was made to dedicate the Compact Linear Flash memory to use all 16 data lines. Since #CE1 and #CE2 are used to enable the upper and lower data bytes respectively, and since the CLF cards of 32 MB capacity and higher always use 16 data lines, the #CE2 signal could be sacrificed for these cards. The cards of less than 32MB capacity still use #CE2 signal to enable the upper data byte. • #IORD - Input Output Read - This signal is used for I/O devices and is not necessary for memory cards so it could be sacrificed with no loss of functionality. • #IOWR - Input Output Write - This signal is also used for I/O devices and is not necessary for memory cards so it could be sacrificed with no loss of functionality. • WP - Write Protection - By dropping the option of having write protection, and requiring that the card always be available for writing data, this signal could be sacrificed. • R/B - Ready Busy signal. This is another output from the external device. This signal indicates to the host that the device is active and that the host must wait to do another operation. This signal could be sacrificed because the same information can be achieved by reading the content of internal registers of each memory component of the card. Note that the same role as the R/B signal can be played by internal registers of memory card, which hold information about the memory device. • RESET - This signal is used to reset the card. It is optional because all external devices have some simple circuitry to reset the card to power-up condition. During certain conditions, the card is held in reset state. The device resets itself upon power-on condition. • #REG - This signal enables attribute memory. This option was sacrificed to recover this signal line because attribute memory is not required in a linear flash memory device. • #WAIT - An output that tells the host that extended time is needed to complete a task. For a memory device, this line is rarely used. Therefore, this signal was mapped into another address line. • #VS1, #VS2 - Output from device indicates the voltage that should be applied. This feature is sacrificed on the Compact Linear Flash device. In one application to which the Compact Linear Flash is envisioned to be particularly beneficial, the Compact Linear Flash devices are used in embedded systems, which are intermittently connected to a support computer to download data. In connecting to the support computer, the Compact Linear Flash device is connected through an adapter (or "shuttle"), which provides this signal. This signal helps to insure that the computer does not provide the wrong voltage to the device. • #BVD1, #BVD2 - indicates to the host the status of the battery. In a flash memory device, this feature serves no function since such memory devices require no battery. • #CSEL - This signal is Cable Select which is used for ATA/IDE drives. The device of the invention is linear so it does not use this signal. • #INPACK - This signal is Input Port Acknowledge, which is used for I/O cards and not memory cards so this signal can be sacrificed. Referring to Fig. 1, a host computer 100 provides an interface 120 with the signal lines shown in Table 3. A Compact Linear Flash device 110 contains a flash memory (not shown) of up to 32 or up to 64 MB of storage space depending on whether signal A24 is implemented. The Compact Linear Flash device 110 has a physical housing and pin layout conforming to the CompactFlash® specification. Thus, the Compact Linear Flash device fits into standard slots configurations for CompactFlash® devices. The host computer can be programmed to permit it to interface with devices with the signal attributes of the Compact Linear Flash device or devices conforming to the CompactFlash® specification. By sacrificing the above signals and retaining the remaining signals (which can be seen in any of the tables), a total 25 signal lines for addressing can be obtained, which is sufficient to address a 64MB space directly. In an alternative design, the #CE2 signal is retained to permit data to be exchanged as 8 bit or 16 bit words under the control of the host computer. In other words, the #CE2 signal is not sacrificed to make another address line available, thereby reducing the linearly addressable space to 32 MB, but preserving the #CE2 signal. Referring to Figs. 2A and 2B, one way that the Compact Linear Flash device 110 can be used is in the context of multiple embedded system computers 180 such as optical scanners, autonomous cash register terminals, customer information terminals, data loggers, or other embedded system applications. In this context, where multiple embedded systems are employed by an entity, data may be gathered or downloaded from the embedded system computers 180 as shown in Fig. 2A. The Compact Linear Flash device 110 can be intermittently removed from the embedded system computer 180 and connected to the support computer 200 for down uploading of data. To connect the Compact Linear Flash device 110 to the support computer 200, the support computer 200 is provided with a PCMCIA standard interface and a PCMCIA-CLF® adapter interface 150 that maps the signal lines from the Compact Linear Flash device 110 specification to the PCMCIA specification. Also, the PCMCIA- CLF® adapter interface 150 may provide some signals that the Compact Linear Flash device 110 specification does not provide. For example, the PCMCIA-CLF® adapter interface 150 may provide #VS1 and #VS2 to indicate the voltage to be supplied or any of the other signal lines of the PCMCIA standard interface that are not supplied by the Compact Linear Flash device 110 specification. Once the Compact Linear Flash device 110 is connected to the PCMCIA-CLF® adapter interface 150, the latter is connected to the support computer 200 and support computer 200 can access the linear flash memory inside the Compact Linear Flash device 110. Of course the up/down-loading of data to/from the support computer could be accomplished by means of a Modified interface 120 on the support computer. The above is merely a convenient alternative. Also note that although all of the features of the invention are discussed in the context of the CompactFlash® mechanical specification, it is clear that many features of the invention can be implemented according to other specifications. Thus, is will be evident to those skilled in the art that the invention is not limited to the details of the foregoing illustrative embodiments, and that the present invention may be embodied in other specific forms without departing from the spirit or essential attributes thereof. The present embodiments are therefore to be considered in all respects as illustrative and not restrictive, the scope of the invention being indicated by the appended claims rather than by the foregoing description, and all changes which come within the meaning and range of equivalency of the claims are therefore intended to be embraced therein.

Claims: We claim: 1. A memory card, comprising: a memory having N address lines; a package conforming to a standard providing, according to said standard, N-M address lines; said package standard providing P terminals, according to said standard, for connecting signal lines other than said address lines; M of said P terminals being connected to M of said N address lines, whereby said linearly addressable memory conforms to said package standard while providing N address lines; said standard having at least one terminal used for a signal to indicate upper and lower data bytes and said M terminals includes said at least one terminal. 2. A device as in claim 1, wherein said memory includes a linear flash memory devices. 3. A device as in claim 1, wherein said package standard includes the CompactFlash® specification. 4. A device as in claim 1 , wherein at least one of said P terminals is used, according to said standard, to provide a signal indicating a voltage requirement. 5. A computer, comprising: a linear flash memory packaged in a CompactFlash® housing; said CompactFlash ® housing providing a plurality of signal lines conforming to the CompactFlash® physical specification; a linear flash memory wired to said plurality of signal lines such that said linear flash memory is linearly addressable. 6. A computer as in claim 5, wherein said plurality of signal lines is 50 in number. 7. A computer as in claim 5, wherein certain of said plurality of signal lines are address lines and said address lines are more than a number of address lines provided in the CompactFlash® specification. 8. A memory card, comprising: an electrical signal terminal conforming to a physical portion of a standard specification for data storage devices; a linear memory; said standard specification providing for page-mode addressing; a number of address lines connected between said terminal and linear memory being greater than a number specified by said specification; said number of address lines being connected to permit a linear addressing of said linear memory. 9. A card as in claim 8, wherein said standard specification is the CompactFlash® specification. 10. A card as in claim 8, wherein said standard specification provides for a data bandwidth signal line that indicates a bandwidth of data transmission through data signal lines, and at least one of said data bandwidth signal lines is mapped to an address line of said linear memory. 11. A card as in claim 8, wherein said standard specification provides for a write protection signal line and said write protection signal line is remapped as an address line of said linear memory. 12. A card as in claim 8, wherein said standard specification provides for a busy signal, which indicates that a host computer must wait for a process to be completed before attempting to read or write data to/from a device, and said busy signal line is remapped as an address line of said linear memory. 13. A card as in claim 8, wherein said standard specification provides for a reset signal line to reset a device and said reset signal line is remapped as an address line of said linear memory. 14. A card as in claim 8, wherein said standard specification provides for attribute memory enabling signal line and said attribute memory enabling signal line is mapped to an address line of said linear memory. 15. A card as in claim 8, wherein said standard specification provides for a voltage signal line that indicates a voltage to be applied to a device and said voltage signal line is mapped to an address line of said linear memory. 16. A memory card, comprising: a memory having N address lines; a package conforming to a standard providing, according to said standard, N-M address lines; said package standard providing P terminals, according to said standard, for connecting signal lines other than said address lines; M of said P terminals being connected to M of said N address lines, whereby said linearly addressable memory conforms to said package standard while providing N address lines; said memory including a linear flash memory. 17. A memory card, comprising: a memory having N address lines; a package conforming to a standard providing, according to said standard, N-M address lines; said package standard providing P terminals, according to said standard, for connecting signal lines other than said address lines; M of said P terminals being connected to M of said N address lines, whereby said linearly addressable memory conforms to said package standard while providing N address lines; said memory including a linear flash memory; said package standard including the CompactFlash® specification. 18. A memory card, comprising: a memory having N address lines; a package conforming to a standard providing, according to said standard, N-M address lines; said package standard providing P terminals, according to said standard, for connecting signal lines other than said address lines; M of said P terminals being connected to M of said N address lines, whereby said linearly addressable memory conforms to said package standard while providing N address lines; said memory including a linear flash memory; at least one of said P terminals being used, according to said standard, to provide a signal indicating a voltage requirement.

Inventors: BRONSHTEYN SIMON, COLLINS LARRY, MERRY DAVID, BRONSHTEYN, SIMON, COLLINS, LARRY, MERRY, DAVID
Applicants: BRONSHTEYN SIMON, CENTENNIAL TECHNOLOGIES INC, COLLINS LARRY, MERRY DAVID, BRONSHTEYN, SIMON, CENTENNIAL TECHNOLOGIES, INC., COLLINS, LARRY, MERRY, DAVID
Application year: 2000
Main classification: G06F12
IPC codes: G11C8