SENSOR

Abstract: A system for acquiring environmental information measurements. The 5 system (100) utilizes a sensor, (205) a front-end circuit, (310) a loop filter (315), a switch controller (206), and a reduced-order loop control circuit to provide reliable data measurements while providing robust system behavior. The system further includes a sensor simulator (330) for simulating the operation of the sensor (205) and testing the operation of the front-end circuit (310) and the loop filter (315).

Description: SENSOR Background of the Invention This invention relates generally to data measurement and, more specifically, to a control system for data measurement. Sensor equipment is used in a variety of applications to acquire environmental data measurements. The existing technology for acquiring data measurements suffers from a number of limitations. For example, the existing technology may suffer from a degradation of system performance as a result of system startup, system overloading, or stray capacitance within the system. Furthermore, testing the output of a sensor controller in the existing technology is time-consuming and expensive. The present invention is directed to overcoming one or more of the limitations of the existing technology for acquiring environmental data measurements. Summary According to one embodiment of the present invention, a sensor system for recording environmental data measurements is provided that includes a sensor for detecting environmental data, a controller for controlling the operation of the sensor, including a front-end circuit coupled to the sensor, a loop filter coupled to the front-end circuit, a multiphase clock generator coupled to the front-end circuit and the loop filter, and a startup sequencer coupled to the loop filter, and a communication interface for coupling the sensor and the controller. According to another embodiment of the present invention, a controller for controlling the operation of a sensor is provided that includes a front-end circuit coupled to the sensor, a loop filter coupled to the front-end circuit, a multiphase clock generator coupled to the front-end circuit and the loop filter, a startup sequencer coupled to the loop filter and the multiphase clock generator, a sensor simulator for simulating the performance of the sensor coupled to the startup sequencer, the multiphase clock generator, and the front-end circuit, and an overload detection device coupled to the loop filter and the startup sequencer. According to another embodiment of the present invention, a controller for controlling the operation of a sensor is provided that includes a front-end circuit coupled to the sensor, a loop filter coupled to the front-end circuit, a multiphase clock generator coupled to the front-end circuit and the loop filter, a startup sequencer coupled to the loop filter and the multiphase clock generator, and an overload detection device coupled to the loop filter and the startup sequencer. According to another embodiment of the present invention, a front-end circuit for providing electrostatic forces and position sensing for a measurement mass in a sensor is provided that includes a plurality of switches for controlling the operation of the sensor and a sense amplifier for sensing the position of the measurement mass within the sensor. According to another embodiment of the present invention, a loop filter for providing control to a sensor system is provided that includes one or more integrators for providing a signal for controlling the sensor system, one or more derivative controllers for providing a signal for controlling the sensor system, one or more proportional controllers for providing a signal for controlling the sensor system, and a summer for combining the signals from the integrators, the derivative controllers, and the proportional controllers. According to another embodiment of the present invention, a method of operating a loop filter within a sensor system is provided that includes sending a signal to the loop filter indicating an operating mode of the sensor system, operating the loop filter in a reduced-order mode while the sensor system is operating in a start-up mode, operating the loop filter in the reduced-order mode for a predetermined period of time after the sensor system transitions from the start-up operating mode to a sigma-delta operating mode, and operating the loop filter in a normal mode during the sigma-delta operating mode after the predetermined period of time during which the loop filter operates in reduced- order mode. According to another embodiment of the present invention, a method of operating a loop filter within a sensor system is provided that includes sending a signal to the loop filter indicating an operating mode of the sensor system, operating the loop filter in a reduced-order mode while the sensor system is operating in a start-up mode, operating the loop filter in the reduced-order mode for a predetermined period of time after the sensor system switches from the start-up operating mode to a sigma-delta operating mode, operating the loop filter in the reduced-order mode while the sensor system is operating in the sigma-delta operating mode, and operating the loop filter in a normal mode while the sensor system operates in the sigma-delta operating mode after the predetermined period of time during which the loop filter operates in reduced- order mode. According to another embodiment of the present invention, a method of controlling the operation within a sensor system of a loop filter including one or more integrators, a proportional controller, and a derivative controller is provided that includes sending a signal to the loop filter indicating the operating mode of the sensor system, holding the integrators in a reset mode to place the loop filter in a reduced-order operating mode when the sensor system is operating in a start-up mode, and taking the integrators out of the reset mode to place the loop filter in a normal operating mode when the sensor system is operating in a sigma-delta operating mode. According to another embodiment of the present invention, a method of placing a loop filter including one or more integrators, a proportional controller, and a derivative controller in a reduced-order operating mode is provided that includes sending a signal to the loop filter to control the operating mode of the loop filter, holding the integrators within the loop filter in a reset mode to place the loop filter in the reduced-order operating mode. According to another embodiment of the present invention, a method of providing control to a sensor assembly is provided that includes determining an operating mode of the sensor assembly, adjusting a mode of operation of a loop filter in the sensor assembly, providing feedback loop compensation to the sensor assembly during a start-up mode of operation for the sensor assembly, and providing noise shaping to the sensor assembly during a sigma-delta mode of operation for the sensor assembly. According to another embodiment of the present invention, a multiphase clock generator for providing clock signals for controlling the operation of a sensor system is provided that includes a digital signal generator and a data- independent clock resynchronization circuit coupled to the digital signal generator. According to another embodiment of the present invention, a sensor simulator for simulating the operation of a sensor is provided that includes a filter adapted to receive one or more input signals and generate an output signal representative of the operating state of the sensor and an input signal selector operably coupled to the filter adapted to controllably select the input signals as a function of the simulated operating state of the sensor. According to another embodiment of the present invention, a system for testing the operation of a controller in a sensor system is provided that includes a sensor simulator for simulating the operation of a sensor and a controller coupled to the simulator. According to another embodiment of the present invention, a method of controlling the operation of a sensor system is provided that includes using a controller to apply electrostatic forces to a sensor to create one or more sensor operating states and sequentially arranging the operating states into which the sensor is placed to create one or more operating modes for the sensor system. According to another embodiment of the present invention, a feedback control system for providing control to a sensor system is provided that includes a startup sequencer for selecting the mode of operation of the feedback control system and a loop filter coupled to the startup sequencer. According to another embodiment of the present invention, a multiphase clock generator for generating clock signals for use within a sensor system is provided that includes a digital signal generator for generating a first clock signal and a clock resynchronization circuit coupled to the digital signal generator for receiving the first clock signal from the digital signal generator and resampling the first clock signal to generate a second clock signal. According to another embodiment of the present invention, a clock resynchronization circuit for resampling clock signals is provided that includes a plurality of inverters, a plurality of NOR gates coupled to the inverters, a plurality of NAND gates coupled to the inverters, a plurality of XNOR gates coupled to the NAND gates and the inverters, a plurality of asynchronous set double-edge flip-flops coupled to the NOR gates, and a plurality of asynchronous reset double-edge flip-flops coupled to the NOR gates. According to another embodiment of the present invention, a device for resampling an input signal on a rising edge and a falling edge of a clock signal is provided that includes a plurality of transmission gates, one or more NOR gates coupled to the transmission gates, and a plurality of inverters coupled to the NOR gates and the transmission gates. According to another embodiment of the present invention, a device for resampling an input signal on a rising edge and a falling edge of a clock signal is provided that includes a plurality of transmission gates, one or more NAND gates coupled to the transmission gates, and a plurality of inverters coupled to the NAND gates and the transmission gates. According to another embodiment of the present invention, a method of generating a clock signal for a sensor assembly is provided that includes generating a first clock signal and resampling the first clock signal to generate a second clock signal to restore signal integrity and provide a timing relationship. According to another embodiment of the present invention, a method of resampling an input signal is provided that includes resampling the input signal in a first level-sensitive latch, including one or more transmission gates, one or more NOR gates, and one or more inverters, on one edge of a clock input signal, and resampling the input signal in a second level-sensitive latch, including one or more transmission gates, one or more NOR gates, and one or more inverters, acting in parallel with the first level-sensitive latch, on another edge of the clock input signal. According to another embodiment of the present invention, a method of resampling an input signal is provided that includes resampling the input signal in a first level-sensitive latch, including one or more transmission gates, one or more NAND gates, and one or more inverters, on one edge of a clock input signal, and resampling the input signal in a second level-sensitive latch, including one or more transmission gates, one or more NAND gates, and one or more inverters, acting in parallel with the first level-sensitive latch, on another edge of the clock input signal. According to another embodiment of the present invention, a method of operating an analog control circuit is provided that includes generating a first clock signal, resampling the first clock signal to generate a second clock signal to restore signal integrity and provide a proper timing relationship, and driving the analog control circuit using the second clock signal. According to another embodiment of the present invention, a controller assembly is provided that includes a sensor, a sensor simulator for simulating the operation of the sensor, a controller for controlling the sensor and the sensor simulator, and a switch for coupling the controller to the sensor or the sensor simulator. According to another embodiment of the present invention, a method of testing a controller in a controller assembly is provided that includes connecting a sensor simulator to the controller, supplying an input signal of a known value to the sensor simulator, converting the input data to the sensor simulator into an output stream from the sensor simulator, sending the output stream from the sensor simulator to the controller, processing the output stream from the sensor simulator within the controller to create an output stream from the controller, and analyzing the output from the controller to determine the accuracy of the controller. According to another embodiment of the present invention, a method of fabricating a controller assembly for a sensor is provided that includes providing a substrate, fabricating one or more controllers on the substrate, fabricating one or more sensor simulators on the substrate, and coupling the controller and the sensor simulator. According to another embodiment of the present invention, a method of offsetting the effects of external acceleration forces on a sensor is provided that includes applying electrostatic forces to the sensor to offset the effects of the acceleration force. The present embodiments of the invention provide a system for acquiring environmental information measurements, utilizing a sensor, a front-end circuit, a loop filter, a switch controller, and a reduced-order loop control circuit to provide reliable data measurements while providing robust system behavior. The system further includes a sensor simulator for simulating the operation of the sensor and testing the operation of the front-end circuit and the loop filter. Brief Description of the Drawings FIG. 1 illustrates an embodiment of a system for acquiring environmental data measurements. FIG. 2 illustrates an embodiment of a sensor and controller for use in the system of FIG. 1. FIG. 3 illustrates an embodiment of the sensor and the controller of FIG. 2. FIG. 4 illustrates an embodiment of the front-end circuit used in the controller of FIG. 3. FIG. 5 illustrates an embodiment of the loop filter used in the controller of FIG. 3. FIG. 6 illustrates an embodiment of the multiphase clock generator used in the controller of FIG. 3. FIG. 7 illustrates an embodiment of the startup sequencer included within the controller of FIG. 3. FIG. 8 illustrates an embodiment of the overload detection device used in the controller of FIG. 3. FIG. 9 illustrates an embodiment of the sensor used in the system of FIG. 1. FIG. 10 illustrates an embodiment of the sensor of FIG. 9 operating in a DUMMY FORCE DOWN STATE. FIG. 11 illustrates an embodiment of the sensor of FIG. 9 operating in a DUMMY FORCE UP STATE. FIG. 12a illustrates an embodiment of the sensor of FIG. 9 operating in a FIRST MODULATOR FORCE UP STATE. FIG. 12b illustrates an alternative embodiment of the sensor of FIG. 9 operating in a SECOND MODULATOR FORCE UP STATE. FIG. 12c illustrates an embodiment of the sensor of FIG. 9 operating in a FIRST MODULATOR FORCE DOWN STATE. FIG. 12d illustrates an alternative embodiment of the sensor of FIG. 9 operating in a SECOND MODULATOR FORCE DOWN STATE. FIG. 13 illustrates an embodiment of the sensor of FIG. 9 operating in a RETURN-TO-ZERO STATE. FIG. 14 illustrates an embodiment of the sensor of FIG. 9 operating in a GRAVITY CANCELLATION STATE. FIG. 15 illustrates an embodiment of the sensor of FIG. 9 operating in a VOLTAGE EQUALIZATION STATE. FIG. 16a illustrates an embodiment of the sensor of FIG. 9 operating in a SENSING (CHARGE SUMMATION) STATE 1. FIG. 16b illustrates an alternative embodiment of the sensor of FIG. 9 operating in a SENSING (CHARGE SUMMATION) STATE 2. FIG. 17 is a chart indicating the position of switches within the front-end circuit of FIG. 4 during the various exemplary operating states of the sensor. FIG. 18 is an embodiment of a clocking diagram of the sensor of FIG. 9 in OPERATING MODE 1. FIG. 19a illustrates an embodiment of the sensor of FIG. 9 operating in the SECOND MODULATOR FORCE UP STATE or the SECOND MODULATOR FORCE DOWN STATE during OPERATING MODE 1. FIG. 19b illustrates an embodiment of the sensor of FIG. 9 operating in the VOLTAGE EQUALIZATION STATE during OPERATING MODE 1. FIG. 19c illustrates an embodiment of the sensor of FIG. 9 operating in the SENSING STATE 2 during OPERATING MODE 1. FIG. 20 is an embodiment of a clock diagram of the sensor of FIG. 9 in OPERATING MODE 2. FIG. 21a illustrates an embodiment of the sensor of FIG. 9 operating in the RETURN-TO-ZERO STATE during OPERATING MODE 2. FIG. 21b illustrates an embodiment of the sensor of FIG. 9 operating in the GRAVITY CANCELLATION STATE during OPERATING MODE 2. FIG. 21c illustrates an embodiment of the sensor of FIG. 9 operating in the VOLTAGE EQUALIZATION STATE during OPERATING MODE 2. FIG. 2 Id illustrates an embodiment of the sensor of FIG. 9 operating in the SENSING STATE 1 during OPERATING MODE 2. FIG. 22 illustrates an embodiment of the sensor of FIG. 9 including stray capacitances. FIG. 23a illustrates an embodiment of the positioning of a measurement mass within the sensor of FIG. 9. FIG. 23b illustrates an embodiment of the positioning of the measurement mass of FIG. 23a within the sensor of FIG. 9 containing stray capacitances. FIG. 24 is an embodiment of a clock diagram of the sensor of FIG. 9 in OPERATING MODE 3. FIG. 25a illustrates an embodiment of the sensor of FIG. 9 operating in the DUMMY FORCE DOWN STATE during OPERATING MODE 3. FIG. 25b illustrates an embodiment of the sensor of FIG. 9 operating in the DUMMY FORCE UP STATE during OPERATING MODE 3. FIG. 25c illustrates an embodiment of the sensor of FIG. 9 operating in the GRAVITY CANCELLATION STATE during OPERATING MODE 3. FIG. 25d illustrates an embodiment of the sensor of FIG. 9 operating in the VOLTAGE EQUALIZATION STATE during OPERATING MODE 3. FIG. 25e illustrates an embodiment of the sensor of FIG. 9 operating in the SENSING STATE 1 during OPERATING MODE 3. FIG. 26 illustrates an embodiment of a clocking diagram of the sensor of FIG. 9 during OPERATING MODE 4.1. FIG. 27 illustrates an embodiment of a clocking diagram of the sensor of FIG. 9 during OPERATING MODE 4.2. FIG. 28 illustrates an embodiment of a clocking diagram of the sensor of FIG. 9 during OPERATING MODE 4.3. FIG. 29 illustrates an embodiment of a clocking diagram of the sensor of FIG. 9 during OPERATING MODE 4.4. FIG. 30 illustrates an embodiment of a clocking diagram of the sensor of FIG. 9 during OPERATING MODE 4.5. FIG. 31 illustrates an embodiment of a clocking diagram of the sensor of FIG. 9 during OPERATING MODE 4.6. FIG. 32 illustrates an embodiment of a clocking diagram of the sensor of FIG. 9 during OPERATING MODE 4.7. FIG. 33 illustrates an embodiment of a clocking diagram of the sensor of FIG. 9 during OPERATING MODE 4.8. FIG. 34 illustrates an embodiment of a startup sequence for the sensor and controller of FIG. 2 without a stray capacitance calibration step. FIG. 35 illustrates an embodiment of a startup sequence for the sensor and controller of FIG. 2 including a stray capacitance calibration step. FIG. 36 illustrates an embodiment of a startup sequence for the sensor and controller of FIG. 2 without a stray capacitance step in which the controller remains in analog output mode. FIG. 37 illustrates an embodiment of a startup sequence for the sensor and controller of FIG. 2 including a stray capacitance step in which the controller remains in analog output mode. FIG. 38 illustrates an embodiment of the sensor and controller of FIG. 2 positioned in an upright manner and experiencing a downward acceleration force. FIG. 39 illustrates a downward electrostatic force applied to the upright sensor of FIG. 38 by the controller to offset the effects of the downward acceleration force. FIG. 40 illustrates an embodiment of the sensor and controller of FIG. 2 positioned in an upside-down manner and experiencing a downward acceleration force. FIG. 41 illustrates a downward electrostatic force applied to the upside- down sensor of FIG. 38 by the controller to offset the effects of the downward acceleration force. FIG. 42 illustrates an embodiment of the loop filter of FIG. 5 operating in a reduced-order mode. FIG. 43 is an embodiment of a method of providing control to the sensor system of FIG. 1. FIG. 44 illustrates a preferred embodiment of the multiphase clock generator of FIG. 6. FIG. 45a illustrates a portion of an embodiment of a clock resynchronization circuit used in the multiphase clock generator of FIG. 44. FIG. 45b illustrates another portion of the clock resynchronization circuit of FIG. 45a. FIG. 45c illustrates another portion of the clock resynchronization circuit of FIG. 45a. FIG. 45d illustrates another portion of the clock resynchronization circuit of FIG. 45a. FIG. 45e illustrates another portion of the clock resynchronization circuit of FIG. 45a. FIG. 46 illustrates an embodiment of a set dual edge flip-flop used in the multiphase clock generator of FIG. 44. FIG. 47 illustrates an embodiment of a reset dual edge flip-flop used in the multiphase clock generator of FIG. 44. FIG. 48 is an embodiment of a timing diagram for the clock resynchronization circuit of FIG. 45a. FIG. 49 is an embodiment of another timing diagram for the clock resynchronization circuit of FIG. 45a. FIG. 50 is an embodiment of a method of controlling the operation of the front-end circuit of FIG. 4. FIG. 51 illustrates an embodiment of a system for testing the operation of the controller of FIG. 2. FIG. 52 illustrates an embodiment of a sensor simulator used in the system of FIG. 51. FIG. 53 is an embodiment of a method of testing the output of the controller of FIG. 2. FIG. 54a illustrates an embodiment of the system of FIG. 51 when the system is operating in a normal operating mode. FIG. 54b illustrates an embodiment of the system of FIG. 51 when the system is operating in a testing mode. FIG. 55 is an embodiment of a method of creating a controller assembly. FIG. 56 is an embodiment of a controller assembly for use in the method of FIG. 55. FIG. 57 is an embodiment of a method of creating a sensor assembly. Detailed Description of the Illustrative Embodiments Referring to FIGS. 1, 2, 3, 4, 5, 6, 7 and 8, a system for acquiring environmental data measurements will now be described. Referring initially to FIG. 1, a preferred embodiment of a sensor system 100 for acquiring environmental data measurements is illustrated. The system 100 preferably includes a measurement device 105 for detecting environmental data measurements, a controller 110 for controlling the measurement device 105, and a communication interface 115 for couphng the measurement device 105 and the controller 110. The measurement device 105 is preferably adapted to detect environmental data measurements. In a preferred embodiment, the measurement device 105 is coupled to the controller 110 by the commimication interface 115. The measurement device 105 may include any number of conventional commercially available measurement devices suitable for acquiring environmental data measurements. As illustrated in FIG. 2, in a preferred embodiment, the measurement device 105 includes a sensor 205, a controller 206, and an interface 207 for coupling the sensor 205 and the controller 206. The sensor 205 may include any number of sensors suitable for detecting and recording environmental data measurements such as, for example, a geophone, a hydrophone, a pressure sensor, a temperature sensor, or an accelerometer. In a preferred embodiment, the sensor 205 is an accelerometer. The accelerometer 205 may be micromachined from wafers made from any number of conventional commercially available materials suitable for creating a sensor, such as, for example, silicon, polysilicon, germanium, quartz, pyrex, gallium arsenide, gallium phosphate, or plated metals. In a preferred embodiment, the accelerometer 205 is micromachined from silicon. The design of the sensor 205 is preferably provided substantially as described in United States patent apphcation serial number , attorney docket number 14737.737, filed on , and as described in United States patent number 5,852,242, the disclosures of which are incorporated herein by reference. In a preferred embodiment, as illustrated in FIGS. 3 and 4, the sensor 205 includes conductive plates 305, 306, 307, and 308, a measurement mass 309, and springs 301 for supporting the measurement mass 309 within the sensor 205. In a preferred embodiment, the conductive plates 305, 306, 307, and 308 are substantially identical. The plates 305, 306, 307, and 308 may be formed from any number of conventional commercially available materials suitable for forming conductive plates. In a preferred embodiment, the plates 305, 306, 307, and 308 are provided substantially as described in one or more of the following: United States Patent number 5,852,242, United States Patent number 5,652,384, United States Patent number 5,777,226, and United States patent application serial number , attorney docket number 14737.737, filed on , the disclosures of which are incorporated herein by reference. The plates 305, 306, 307, and 308 may be arranged within the sensor 205 in any manner suitable for initiating the interaction between the plates 305, 306, 307, and 308 necessary to create a sensor. In a preferred embodiment, the plate 305 is positioned substantially opposite the plate 306 and the plate 307 is positioned substantially opposite the plate 308. The measurement mass 309 may be formed from any number of conventional commercially available materials, such as, for example, silicon, polysilicon, germanium, quartz, pyrex, gallium arsenide, gallium phosphate, or plated metals. In a preferred embodiment, the measurement mass 309 is micromachined from silicon. The springs 301 are preferably adapted to couple the measurement mass 309 to the sensor 205 and to support the measurement mass 309 within the sensor 205. The springs 301 preferably further provide electrical connections between the measurement mass 309 and the sensor 205. The design of the springs 301 is preferably provided substantially as described in one or more of the following: United States Patent number 5,652,384 and United States Patent number 5,777,226, the disclosures of which are incorporated herein by reference. The controller 206 may include any number of controllers suitable for controlling the operation of the sensor 205, such as, for example, a frequency/amplitude modulation controller or an application specific integrated circuit (ASIC). In a preferred embodiment, the controller 206 is an ASIC. In a preferred embodiment, the controller 206 is a sigma-delta ASIC controller. In a preferred embodiment, as illustrated in FIG. 3, the controller 206 includes a front-end circuit 310, a loop filter circuit 315, a multiphase clock generator 320, a startup sequencer 325, a sensor simulator 330, and an overload detection device 335. In a preferred embodiment, the front-end circuit 310 interfaces to the sensor 205 and is adapted to provide electrostatic forcing and position sensing for the measurement mass 309 within the sensor 205. In a preferred embodiment, the front-end circuit 310 is operably coupled to the sensor 205 by the interface 207. The front-end circuit 310 is also preferably operably coupled to the loop filter 315, the multiphase clock generator 320, and the sensor simulator 330. The front-end circuit 310 may include any number of circuits suitable for providing electrostatic forcing and position sensing for the sensor 205. In a preferred embodiment, the front-end circuit 310 is an analog circuit. As illustrated in FIG. 4, the front-end circuit 310 preferably includes switches phsul, phsu2, phul, phu2, phdl, phd2, phgl, phtc, phbc, phg2, phsg, phs, phf, phloop, phsim, phxbuf, phz, and pha for connecting the sensor 205 to a variety of voltage sources, and a sense amplifier 405 for sensing the position of the measurement mass 309 within the sensor 205. The switches phsul, phsu2, phul, phu2, phdl, phd2, phgl, phtc, phbc, phg2, phsg, phs, phf, phloop, phsim, phxbuf, phz, and pha may be any number of conventional commercially available switches suitable for connecting the sensor 205 to a variety of voltage sources. The sense amplifier 405 may be any number of sense amplifiers suitable for sensing the position of the measurement mass 309 in the sensor 205. In a preferred embodiment, the sense amplifier 405 is a switched-capacitor circuit. In a preferred embodiment, the output Vx of the sense amplifier 405 in the front- end circuit 310 is a voltage representing the position of the measurement mass 309 within the sensor 205. The position of the measurement mass 309 within the sensor 205 may be representative of the amount of an acceleration force experienced by the measurement mass 309. The loop filter 315 is preferably adapted to receive the output Vx from the sense amplifier 405 and create output streams for providing feedback loop compensation and noise shaping for the sensor 205. In a preferred embodiment, the loop filter 315 is operably coupled to the front-end circuit 310, the multiphase clock generator 320, the startup sequencer 325, and the overload detection device 335. In a preferred embodiment, as illustrated in FIG. 5, the loop filter 315 includes one or more integrators 505, a derivative controller 510, a proportional controller 515, summers 520 and 525, a comparator 530, a buffer 535, and scaling devices 507. In a preferred embodiment, the loop filter 315 is an analog circuit. In a preferred embodiment, the integrators 505 are used to provide control to the sensor 205. The integrators 505 preferably generate third, fourth, and fifth integral terms for fifth-order noise shaping of 1-bit quantization noise. The integrators 505 may include any number of conventional commercially available integrators suitable for providing integral control to sensor 205. In a preferred embodiment, the integrators 505 are switched-capacitor circuits. The scaling devices 507 preferably scale the output streams from the integrators 505. The scaling devices 507 may be any number of devices suitable for scaling the output streams from the integrators 505. In a preferred embodiment, the scaling devices 507 are switched-capacitor circuits. The derivative controller 510 preferably provides derivative control to the sensor 205. In a preferred embodiment, the derivative controller 510 provides derivative control to the sensor 205 by generating a velocity term as the first integral of acceleration by using a derivative of the x-position of the measurement mass 309 within the sensor 205. The derivative controller 510 may be any number of conventional commercially available controllers suitable for providing derivative control to the sensor 205. In a preferred embodiment, the derivative controller 510 is a switched-capacitor circuit. The proportional controller 515 preferably provides additional control to the sensor 205. In a preferred embodiment, the proportional controller 515 provides proportional control to the sensor 205 by generating a displacement term as a second integral of the acceleration force experienced by the sensor 205. The proportional controller 515 may be any number of conventional commercially available controllers suitable for providing proportional control to the sensor 205. In a preferred embodiment, the proportional controller 515 is a switched-capacitor circuit. The summers 520 preferably receive the output streams from the integrators 505 and combine the streams into a single output data stream. In a preferred embodiment, the summers 520 receive the scaled output streams from the scaling devices 507 and combine them into a single output data stream. In a preferred embodiment, the output data streams from the summers 520 are sent to the next integrator 505. The summers 520 may be any number of conventional commercially available devices suitable for combining data streams from the integrators 505 into a single output data stream. In a preferred embodiment, the summers 520 are switched-capacitor circuits. The summer 525 preferably receives the output streams from the scaling devices 507, the derivative controller 510, and the proportional controller 515 and combines the streams into a single output data stream. In a preferred embodiment, the output data stream from the summer 525 drives the comparator 530. In another preferred embodiment, the output from the summer 525 drives the buffer 535. The summer 525 may be any number of conventional commercially available devices suitable for combining data streams from the scaling devices 507, the derivative controller 510, and the proportional controller 515 into a single output data stream. In a preferred embodiment, the summer 525 is a switched-capacitor circuit. The comparator 530 preferably provides a feedback signal to the front-end circuit 310 when the system 100 is operating in a normal sigma-delta operating mode. In a preferred embodiment, the output stream IMOD from the comparator 530 is a digital 1-bit representation of the output of the loop filter 315. In a preferred embodiment, the input into the loop filter 315 is the output Vx of the front-end circuit 310, which is representative of the position of the measurement mass 309 within the sensor 205. The position of the measurement mass 309 preferably varies as acceleration forces are applied to the sensor 205. The comparator 530 may be any number of conventional commercially available comparators. In a preferred embodiment, the comparator 530 is an analog circuit. The buffer 535 preferably provides a feedback signal to the front-end circuit 310 during the start-up of the system 100. In a preferred embodiment, the output stream Vsum of the buffer 535 is a voltage representation of the acceleration experienced by the sensor 205. In a preferred embodiment, the input into the loop filter 315 is the output Vx of the front-end circuit 310, which is representative of the position of the measurement mass 309 within the sensor 205. The buffer 535 may include any number of conventional commercially available buffers. In a preferred embodiment, the buffer 535 is an analog circuit. In a preferred embodiment, as illustrated in FIG. 6, the multiphase clock generator 320 is adapted to receive input data streams and convert the input streams to output clock signals used to control the switches in the front-end circuit 310 and the loop filter 315. The input streams received by the multiphase clock generator 320 may include, for example, the output stream IMOD from the loop filter 315, an external test signal XTST, a test stream TEST designed to combine with the output stream IMOD from the loop filter 315 if the value of the external test signal XTST is high, a master clock signal CLK, and a control signal CTRL for indicating the operating mode of the sensor 205. In a preferred embodiment, as illustrated in FIG. 3, the multiphase clock generator 320 is operably coupled to the front-end circuit 310, the loop filter 315, the startup sequencer 325, and the sensor simulator 330. The multiphase clock generator 320 may be any number of conventional commercially available clock generators suitable for controlling switches in the front-end circuit 310 and the loop filter 315. In a preferred embodiment, the multiphase clock generator 320 is a digital circuit. The startup sequencer 325 is preferably adapted to provide stability to the sensor 205 during the start-up of the system 100. The startup sequencer 325 is also preferably used to help the sensor 205 handle high-level inputs and recover from unexpected overloads. In a preferred embodiment, the startup sequencer 325 controls the different modes of operation used by the controller 206 for startup and calibration of the sensor 205. In a preferred embodiment, as illustrated in FIG. 3, the startup sequencer 325 is operably coupled to the loop filter 315, the multiphase clock generator 320, the sensor simulator 330, and the overload detection device 335. In a preferred embodiment, as illustrated in FIG. 7, the input streams into the startup sequencer 325 are the master clock signal CLK and an overload detection signal OVL. The output streams from the startup sequencer 325 are preferably the control signal CTRL for indicating the operating mode of the sensor 205, the digital signal XTST for indicating that the controller 206 should use an external test bitstream, and a reset signal RST for resetting the integrators 505 in the loop filter 315, the sense amplifier 405 in the front-end circuit 310, and the multiphase clock generator 320. The startup sequencer 325 may be any number of conventional commercially available circuits suitable for helping the sensor 205 handle high-level inputs and recover from unexpected overloads. In a preferred embodiment, the startup sequencer 325 is a digital circuit. The sensor simulator 330 is preferably used to substantially duplicate the performance characteristics of the sensor 205 in order to test the operation of the controller 206. In a preferred embodiment, the sensor simulator 330 is operably coupled to the front-end circuit 310, the multiphase clock generator 320, and the startup sequencer 325. The sensor simulator 330 may be any number of devices suitable for duplicating the performance characteristics of the sensor 205 such as, for example, operational amplifiers, capacitors, switches, resistors, or transistors. The overload detection device 335 preferably provides detection of high level inputs and system 100 overloads. In a preferred embodiment, as illustrated in FIG. 3, the overload detection device 335 is operably coupled to the loop filter 315 and the startup sequencer 325. As illustrated in FIG. 8, the input streams into the overload detection device 335 may include, for example, the output stream IMOD from the loop filter 315, the external test stream XTST, and a test overload signal TESTOVL. The output stream OVL from the overload detection device is preferably sent to the startup sequencer 325 when an overload in the system 100 has been detected. The overload detection device 335 may be any number of conventional commercially available devices suitable for providing overload detection for the controller 206. In a preferred embodiment, the overload detection device 335 is a digital counter circuit. In a preferred embodiment, as illustrated in FIG. 2, the interface 207 couples the sensor 205 to the controller 206. The interface 207 may be any number of conventional commercially available interfaces suitable for coupling the sensor 205 and the controller 206 such as, for example, fiber optics or wireless telemetry. In a preferred embodiment, as illustrated in FIG. 4, the interface 207 includes electrical cables extending from the conductive plates 305, 306, 307, and 308 positioned within the sensor 205. In a preferred embodiment, as illustrated in FIG. 9, the conductive plate 306 is positioned within the sensor 205 on a top surface of the measurement mass 309, substantially opposite the conductive plate 305. The conductive plates 305 and 306 preferably interact to form a variable capacitor Cl within the sensor 205. In a preferred embodiment, conductive plate 307 is positioned within the sensor 205 on a bottom surface of the measurement mass 309, substantially opposite the conductive plate 308. The conductive plates 307 and 308 preferably interact to form a variable capacitor C2 within the sensor 205. Referring to FIGS. 4, 10, 11, 12, 13, 14, 15, 16, and 17, the operation of the measurement device 105 will now be described. In a preferred embodiment, the front-end circuit 310 interacts with the sensor 205 to place the sensor 205 in a variety of operating states. The different operating states into which the sensor 205 is placed preferably include (1) a DUMMY FORCE DOWN STATE, (2) a DUMMY FORCE UP STATE, (3) a FIRST MODULATOR FORCE UP STATE, (4) a SECOND MODULATOR FORCE UP STATE, (5) a FIRST MODULATOR FORCE DOWN STATE, (6) a SECOND MODULATOR FORCE DOWN STATE, (7) a RETURN-TO-ZERO STATE, (8) a GRAVITY CANCELLATION STATE, (9) a VOLTAGE EQUALIZATION STATE, (10) a SENSING (CHARGE SUMMATION) STATE 1, and (11) a SENSING STATE 2. In a preferred embodiment, as illustrated in FIGS. 4, 10 and 17, the controller 206 places the sensor 205 in the DUMMY FORCE DOWN STATE by applying a negative reference voltage -V ref to conductive plates 305, 306 and 307 and a positive reference voltage +V ref to conductive plate 308. The negative reference voltage -V ref is preferably applied to the conductive plates 305, 306, and 307 by turning on switches phdl and phtc to connect the plates 305, 306, and 307 to the negative reference voltage -V ref source. The positive reference voltage + V ref is preferably applied to conductive plate 308 by turning on switch phd2 to connect plate 308 to the positive reference voltage + V ref source. The positive reference voltage + V ref on conductive plate 308 combined with the negative reference voltage -V ref on plate 307 on the measurement mass 309 preferably results in an electrostatic attraction between the measurement mass 309 and the conductive plate 308. The net effect of the attractive forces created within the sensor 205 is to apply an electrostatic force on the measurement mass 309. In a preferred embodiment, the electrostatic force applies a downward force to the measurement mass 309 during the DUMMY FORCE DOWN STATE. In a preferred embodiment, as illustrated in FIGS. 4, 11 and 17, the controller 206 places the sensor 205 in the DUMMY FORCE UP STATE by applying a positive reference voltage + V ref to conductive plate 305 and a negative reference voltage -V ref to conductive plates 306, 307, and 308. The positive reference voltage + V ref is preferably applied to the conductive plate 305 by turning on switch phul to connect the plate 305 to the positive reference voltage -l-V ref source. The negative reference voltage -V ref is preferably applied to conductive plates 306, 307, and 308 by turning on switches phu2 and phbc to connect plates 306, 307, and 308 to the negative reference voltage -V ref source. The positive reference voltage + V ref on conductive plate 305 combined with the negative reference voltage -V ref on plate 306 on the measurement mass 309 preferably results in an electrostatic attraction between the measurement mass 309 and the conductive plate 305. The net effect of the attractive forces created within the sensor 205 is to apply an electrostatic force on the measurement mass 309. In a preferred embodiment, the electrostatic force applies an upward force to the measurement mass 309 during the DUMMY FORCE UP STATE. In a preferred embodiment, as illustrated in FIGS. 4, 12a, and 17, the controller 206 places the sensor 205 in the FIRST MODULATOR FORCE UP STATE during the normal sigma-delta operating mode by applying a positive reference voltage + V ref to conductive plate 305 and a negative reference voltage - V ref to conductive plates 306, 307, and 308. In a preferred embodiment, the controller 206 places the sensor 205 in the FIRST MODULATOR FORCE UP STATE when the output stream IMOD from the loop filter 315 has a negative value. The positive reference voltage + V ref is preferably applied to the conductive plate 305 by turning on switch phul to connect the plate 305 to the positive reference voltage + V ref source. The negative reference voltage -V ref is preferably applied to conductive plates 306, 307, and 308 by turning on switches phu2 and phbc to connect plates 306, 307, and 308 to the negative reference voltage -V ref source. The positive reference voltage +V ref on conductive plate 305 combined with the negative reference voltage -V ref on plate 306 on the measurement mass 309 preferably results in an electrostatic attraction between the measurement mass 309 and the conductive plate 305. The net effect of the attractive forces created within the sensor 205 is to apply an electrostatic force on the measurement mass 309. In a preferred embodiment, the electrostatic force applies an upward force to the measurement mass 309 during the FIRST MODULATOR FORCE UP STATE. In another preferred embodiment, as illustrated in FIGS. 4, 12b, and 17, the controller 206 places the sensor 205 in the SECOND MODULATOR FORCE UP STATE during system 100 start-up by applying a voltage V DDA to conductive plate 305, applying a voltage Vgs A to conductive plate 308, and applying the output Vsum from the reduced-order loop filter 315 to plates 306 and 307 on the measurement mass 309. In a preferred embodiment, the controller 206 places the sensor 205 in the SECOND MODULATOR FORCE UP STATE when the output stream Vsum from the reduced-order loop filter 315 has a value of less than zero volts. The voltage V DDA is preferably applied to the conductive plate 305 by turning on switch phsul to connect the plate 305 to the voltage V DDA source. The voltage V SSA is preferably applied to conductive plate 308 by turning on switch phsu2 to connect plate 308 to the voltage V SSA source. The voltage Vsum is preferably applied to plates 306 and 307 by turning on switch phloop to connect plates 306 and 307 to the output Vsum from the reduced-order loop filter 315. The voltage V DDA on conductive plate 305 combined with the voltage Vsum on the plate 306 on the measurement mass 309 preferably results in an electrostatic attraction between the measurement mass 309 and the conductive plate 305. The voltage Vgg A on conductive plate 308 combined with the voltage Vsum on the plate 307 on the measurement mass 309 preferably results in an electrostatic attraction between the measurement mass 309 and the conductive plate 308. The net attractive forces may, for example, move the measurement mass 309 upwards or downwards. In a preferred embodiment, the net effect of the attractive forces created within the sensor 205 is to apply a net force upward on the measurement mass 309 during the SECOND MODULATOR FORCE UP STATE. The amount of upward force applied to the measurement mass 309 preferably depends on the level of the voltage Vsum (<0 V). In a preferred embodiment, as illustrated in FIGS. 4, 12c and 17, the controller 206 places the sensor 205 in the FIRST MODULATOR FORCE DOWN STATE during normal sigma-delta operating mode by applying a negative reference voltage -V ref to conductive plate 305, 306 and 307 and a positive reference voltage +V ref to conductive plate 308. In a preferred embodiment, the controller 206 places the sensor 205 in the FIRST MODULATOR FORCE DOWN STATE when the output stream IMOD from the loop filter 315 has a positive value. The negative reference voltage -V ref is preferably applied to the conductive plates 305, 306, and 307 by turning on switches phdl and phtc to connect the plates 305, 306, and 307 to the negative reference voltage -V ref source. The positive reference voltage + V ref is preferably applied to conductive plate 308 by turning on switch phd2 to connect plate 308 to the positive reference voltage + V ref source. The positive reference voltage +V ref on conductive plate 308 combined with the negative reference voltage -V ref on plate 307 on the measurement mass 309 preferably results in an electrostatic attraction between the measurement mass 309 and the conductive plate 308. The net effect of the attractive forces created within the sensor 205 is to apply an electrostatic force on the measurement mass 309. In a preferred embodiment, the electrostatic force applies a downward force to the measurement mass 309 during the FIRST MODULATOR FORCE DOWN STATE. In another preferred embodiment, as illustrated in FIGS. 4, 12d, and 17, the controller 206 places the sensor 205 in the SECOND MODULATOR FORCE DOWN STATE during system 100 start-up by applying a voltage V DDA to conductive plate 305, applying a voltage V SSA to conductive plate 308, and applying the output Vsum from the loop filter 315 to plates 306 and 307 on the measurement mass 309. In a preferred embodiment, the controller 206 places the sensor 205 in the SECOND MODULATOR FORCE DOWN STATE when the output stream Vsum from the reduced-order loop filter 315 has a value of greater than zero volts. The voltage V DDA is preferably applied to the conductive plate 305 by turning on switch phsul to connect the plate 305 to the voltage V DDA source. The voltage Vgs A is preferably applied to conductive plate 308 by turning on switch phsu2 to connect plate 308 to the voltage V SSA source. The voltage Vsum is preferably applied to plates 306 and 307 by turning on switch phloop to connect plates 306 and 307 to the output Vsum of the reduced-order loop filter 315. The voltage V DDA on conductive plate 305 combined with the voltage V SUM on plate 306 on the measurement mass 309 preferably results in an electrostatic attraction between the measurement mass 309 and the conductive plate 305. The voltage V SSA on conductive plate 308 combined with the voltage V SUM on plate 307 on the measurement mass 309 preferably results in an electrostatic attraction between the measurement mass 309 and the conductive plate 308. The net attractive forces may, for example, move the measurement mass 309 upwards or downwards. In a preferred embodiment, the net effect of the attractive forces created within the sensor 205 is to apply a net force downward on the measurement mass 309 during the SECOND MODULATOR FORCE DOWN STATE. The amount of downward force applied to the measurement mass 309 preferably depends on the level of the voltage Vsum (>0 V). In a preferred embodiment, as illustrated in FIGS. 4, 13, and 17, the controller 206 places the sensor 205 in a RETURN-TO-ZERO STATE by grounding the conductive plates 305, 306, 307, and 308 to reduce signal dependent current draw from reference sources. In a preferred embodiment, the conductive plate 305 is grounded by turning on switch phgl to connect the conductive plate 305 to a grounding source. In a preferred embodiment, conductive plates 306 and 307 are grounded by turning on switch phsg to connect the conductive plates 306 and 307 to a grounding source. In a preferred embodiment, the conductive plate 308 is grounded by turning on switch phg2 to connect the conductive plate 308 to a grounding source. In this configuration, the charges across capacitors Cl and C2 are preferably equal to zero. In a preferred embodiment, no net electrostatic force is applied to the measurement mass 309 in the RETURN-TO-ZERO STATE. In a preferred embodiment, as illustrated in FIGS. 4, 14, and 17, the controller 206 places the sensor 205 in the GRAVITY CANCELLATION STATE by applying a positive reference voltage + V ref to plate 305, applying a negative reference voltage -V ref to plate 308, and applying a voltage V dac or V sum on plates 306 and 307. The positive reference voltage + V ref is preferably applied to plate 305 by turning on switch phul to connect the conductive plate 305 to the positive reference voltage + V ref source. The negative reference voltage -V ref is preferably applied to the conductive plate 308 by turning on switch phu2 to connect the conductive plate 308 to the negative reference voltage -V ref source. The voltage V dac is preferably applied to the conductive plates 306 and 307 by turning on switch phf to connect the conductive plates 306 and 307 to a voltage V dao source. The voltage V 8Um is preferably applied to the conductive plates 306 and 307 by turning on switch phloop to connect the conductive plates 306 and 307 to a voltage V sum source. The positive reference voltage + V ref on conductive plate 305 combined with the voltage V dac or V sum on the conductive plates 306 and 307 preferably results in an electrostatic attraction between the measurement mass 309 and the conductive plate 305. The negative reference voltage -V ref on the conductive plate 308 combined with the voltage V dao or V sum on the conductive plates 306 and 307 preferably results in an electrostatic attraction between the measurement mass 309 and the conductive plate 308. The net effect of the attractive forces created within the sensor 205 is to apply an electrostatic force on the measurement mass 309. The electrostatic force created by the attractive forces may, for example, move the measurement mass 309 upwards or downwards. In a preferred embodiment, the electrostatic force on the measurement mass 309 during the GRAVITY CANCELLATION STATE substantially cancels a 1-g static field experienced by the sensor 205. In a preferred embodiment, as illustrated in FIGS. 4, 15, and 17, the controller 206 places the sensor 205 in the VOLTAGE EQUALIZATION STATE by applying a positive reference voltage + V ref to the plate 305, applying a negative reference voltage -V ref to the plate 308, and by sequentially grounding the plates 306 and 307 to dissipate charges on the plates 306 and 307 and then connecting the plates 306 and 307 to the sense amplifier 405. The sense amplifier 405 input offset voltage is preferably stored for subsequent cancellation. The positive reference voltage + V ref is preferably applied to the plate 305 by turning on switch phul to connect the conductive plate 305 to the positive reference voltage + V ^f source. The negative reference voltage -V ref is preferably applied to the conductive plate 308 by turning on switch phu2 to connect the conductive plate 308 to the negative reference voltage -V ref source. In a preferred embodiment, the conductive plates 306 and 307 are grounded by turning on switch phsg to connect the conductive plates 306 and 307 to a grounding source. In a preferred embodiment, the voltage equal to the offset of the sense amplifier is applied to the plates 306 and 307 by turning on switch phs to connect the conductive plates 306 and 307 to the sense amplifier 405. In a preferred embodiment, the conductive plates 306 and 307 are initially grounded while the positive reference voltage + V ref is applied to plate 305 and the negative reference voltage -V ref is applied to the conductive plate 308. In a preferred embodiment, no electrostatic forces are applied to the sensor 205 and the charges across capacitors Cl and C2 are preferably substantially equal. Next, the voltage equal to the offset of the sense amplifier 405 is applied to the plates 306 and 307 while the positive reference voltage +V ref is applied to plate 305 and the negative reference voltage -V ref is applied to the conductive plate 308. In this configuration, electrostatic forces are preferably applied to the sensor 205. The electrostatic forces alter the charges across capacitors Cl and C2. The magnitude of the variation in charges across capacitors Cl and C2 depends on the magnitude of the offset voltage of the sense amplifier 405. In a preferred embodiment, as illustrated in FIGS. 4, 16a, and 17, the controller 206 places the sensor 205 in the SENSING STATE 1 (CHARGE SUMMATION STATE) by applying the negative reference voltage -V ref to the conductive plate 305, applying the positive reference voltage + V ref to the conductive plate 308, and connecting the sense amplifier 405 to the conductive plates 306 and 307. In a preferred embodiment, the controller 206 places the sensor 205 in the SENSING STATE 1 following the VOLTAGE EQUALIZATION STATE. During the SENSING STATE 1, the charge differential on capacitors Cl and C2 is measured to determine the position of the measurement mass 309 within the sensor 205. In a preferred embodiment, the negative reference voltage -V ref is applied to plate 305, the positive reference voltage + V ref is applied to plate 308, and the plates 306 and 307 are connected to the sense amplifier 405. The negative reference voltage -V ref is preferably applied to the plate 305 by turning on switch phdl to connect the plate 305 to the negative reference voltage -V ref source. The positive reference voltage + V ref is preferably applied to the plate 308 by turning on switch phd2 to connect the plate 308 to the positive reference voltage +V ref source. The plates 306 and 307 are preferably connected to the sense amplifier by turning on switch phs to connect the plates 306 and 307 to the inverting terminal of the sense amplifier 405. In a preferred embodiment, as illustrated in FIGS. 4, 16b, and 17, the controller 206 places the sensor 205 in the SENSING STATE 2 by grounding plates 305 and 308 while connecting plates 306 and 307 to inverting terminal of the sense amplifier 405. The controller 206 preferably grounds plate 305 by turning on switch phgl to connect the plate 305 to the grounding source. The controller 206 preferably grounds plate 308 by turning on switch phg2 to connect the plate 308 to the grounding source. The controller 206 preferably connects plates 306 and 307 to the sense amplifier 405 by turning on switch phs. The DUMMY FORCE DOWN STATE, the DUMMY FORCE UP STATE, the FIRST MODULATOR FORCE UP STATE, the SECOND MODULATOR FORCE UP STATE, the FIRST MODULATOR FORCE DOWN STATE, the SECOND MODULATOR FORCE DOWN STATE, the RETURN-TO-ZERO STATE, the GRAVITY CANCELLATION STATE, the VOLTAGE EQUALIZATION STATE, the SENSING STATE 1 and the SENSING STATE 2 may be used in any combination to create any number of operating modes for the sensor 205. Each operating mode is preferably implemented by setting up a forcing pattern during sixteen clock periods of a 2 MHZ clock. In a preferred embodiment, the sixteen clock periods of the 2 MHZ clock are broken down into thirty-two half-periods. In a preferred embodiment, the forcing pattern is repeated periodically at 128 kHz. In a preferred embodiment, the sensor 205 experiences four types of operating modes under the control of the controller 206: a measurement mass 309 setup operating mode (OPERATING MODE 1), a gravity cancellation operating mode (OPERATING MODE 2), a stray capacitance calibration operating mode (OPERATING MODE 3), and a sigma-delta operating mode (OPERATING MODE 4). The gravity cancellation mode (OPERATING MODE 2) and the stray capacitance calibration mode (OPERATING MODE 3) preferably work together to cancel the effects of gravity and stray capacitances on the sensor 205. Referring to FIGS. 18, 19a, 19b, and 19c, the OPERATING MODE 1 will now be described. During the OPERATING MODE 1, the controller 206 preferably pulls the measurement mass 309 off stops within the sensor 205 and positions the measurement mass 309 so that capacitors Cl and C2 are substantially equal. The controller 206 may utilize any of the eleven generic operating states described above, and variations thereof, to create the OPERATING MODE 1. In a preferred embodiment, as illustrated in FIGS. 18, 19a, 19b, and 19c, the controller 206 places the sensor 205 in the MODULATOR FORCING STATE, the VOLTAGE EQUALIZATION STATE, and the SENSING STATE during the OPERATING MODE 1. In a preferred embodiment, as illustrated in FIG. 19a, the controller 206 initially interacts with the sensor 205 to place the sensor 205 in one of the modulator forcing states. In this configuration, the system 100 is preferably operating in start-up mode, and the loop filter 315 is operating in reduced-order mode. Therefore, the controller 206 preferably places the sensor 205 in either the SECOND MODULATOR FORCE UP STATE or the SECOND MODULATOR FORCE DOWN STATE, depending on the value of the output Vsum of the reduced-order loop filter 315. The controller 206 may place the sensor 205 in the SECOND MODULATOR FORCE UP STATE or the SECOND MODULATOR FORCE DOWN STATE for any number of the sixteen clock periods within the operating cycle. In a preferred embodiment, the controller 206 places the sensor 205 in the SECOND MODULATOR FORCE UP STATE or the SECOND MODULATOR FORCE DOWN STATE for clock periods 1 through 14 of the OPERATING MODE 1. Next, as illustrated in FIG. 19b, the controller 206 preferably places the sensor 205 in the VOLTAGE EQUALIZATION STATE. The controller 206 may place the sensor 205 in the VOLTAGE EQUALIZATION STATE for any number of the sixteen clock periods within the operating cycle. In a preferred embodiment, the controller 206 places the sensor 205 in the voltage equalization state during clock period 15 of the OPERATING MODE 1. Finally, as illustrated in FIG. 19c, the controller 206 preferably completes the OPERATING MODE 1 by placing the sensor 205 in the SENSING STATE 2. The controller 206 may place the sensor 205 in the SENSING STATE 2 for any number of the sixteen clock periods within the operating cycle. In a preferred embodiment, the controller 206 places the sensor 205 in the SENSING STATE 2 during clock period 16 of the OPERATING MODE 1. Referring to FIGS. 20, 21a, 21b, 21c, and 21d, the OPERATING MODE 2 will now be described. During the OPERATING MODE 2, the controller 206 preferably cancels the effects of gravitational forces on the sensor 205 and calibrates the voltage V DAG applied to plates 306 and 307 during normal sigma- delta mode so that the operating range of the sensor 205 is approximately +/- O.lg. Also, during the OPERATING MODE 2, the voltage Vsum is digitized for use during the stray capacitance calibration of the OPERATING MODE 3. The controller 206 may utilize any of the eleven generic operating states, or variations thereof, to create the OPERATING MODE 2. In a preferred embodiment, as illustrated in FIGS. 20, 21a, 21b, 21c, and 21d, the controller 206 places the sensor 205 in the RETURN-TO-ZERO STATE, the GRAVITY CANCELLATION STATE, the VOLTAGE EQUALIZATION STATE, and the SENSING STATE 1 during the OPERATING MODE 2. In a preferred embodiment, as illustrated in FIGS 20 and 21a, the controller 206 begins the OPERATING MODE 2 by placing the sensor 205 in the RETURN-TO-ZERO STATE to remove any charges from the conductive plates 305, 306, 307, and 308. The controller 206 may place the sensor 205 in the RETURN-TO-ZERO STATE for any number of the sixteen clock periods within the OPERATING MODE 2. In a preferred embodiment, the controller 206 places the sensor 205 in the RETURN-TO-ZERO STATE for clock periods 1 through 4 of the OPERATING MODE 2. Next, as illustrated in FIGS. 20 and 21b, the controller 206 preferably places the sensor 205 in the GRAVITY CANCELLATION STATE to cancel the effects of the 1-g static field from within the sensor 205. The controller 206 may place the sensor 205 in the GRAVITY CANCELLATION STATE for any number of the sixteen clock periods within the OPERATING MODE 2. In a preferred embodiment, the controller 206 places the sensor 205 in the GRAVITY CANCELLATION STATE for the clock periods 5 through 12 of the OPERATING MODE 2. Next, as illustrated in FIGS. 20 and 21c, the controller 206 preferably places the sensor 205 in the VOLTAGE EQUALIZATION STATE to equalize the voltage across capacitors Cl and C2 within the sensor 205. The controller 206 may place the sensor 205 in the VOLTAGE EQUALIZATION STATE for any number of the sixteen clock periods within the OPERATING MODE 2. In a preferred embodiment, the controller 206 places the sensor 205 in the VOLTAGE EQUALIZATION STATE for clock periods 13 and 14 of the OPERATING MODE 2. Finally, as illustrated in FIGS. 20 and 21d, the controller 206 preferably places the sensor 205 in the SENSING STATE 1. The controller 206 may place the sensor 205 in the SENSING STATE 1 for any number of the sixteen clock periods within the OPERATING MODE 2. In a preferred embodiment, the controller 206 places the sensor 205 in the SENSING STATE 1 for clock periods 15 and 16 of the OPERATING MODE 2. Referring to FIGS. 22, 23a, 23b, 24, 25a, 25b, 25c, 25d, and 25e, the OPERATING MODE 3 will now be described. In a preferred embodiment, the controller 206 cancels the effects of stray capacitances within the sensor 205 during the OPERATING MODE 3. In a preferred embodiment, the controller 206 utilizes the digitized voltage Vsum from the OPERATING MODE 2 during the stray capacitance calibration of the OPERATING MODE 3. In a preferred embodiment, the stray capacitance calibration is performed substantially as described in United States patent apphcation serial number 09/268,072, attorney docket number 456020.12-IOS12, filed on 3/12/1999, the disclosure of which is incorporated herein by reference. During the course of operation of the sensor 205, the performance of the sensor 205 may be affected, for example, by external factors known as stray capacitances. Stray capacitances may be caused by any number of sources, but two mechanisms typically responsible for the stray capacitances are process variations within or internal to the sensor 205 and the sensor 205 package, and external effects related to socketing PC board layout. As illustrated in FIG. 22, the external stray capacitances are lumped together and denoted as Clse and C2se, and the internal stray capacitances are lumped together and denoted as Clsi and C2si. In a preferred embodiment, as illustrated in FIG. 23a, the measurement mass 309 is centered approximately at the mechanical center x=0 of the sensor 205 under normal operating conditions. Normal operating conditions occur when stray capacitances Clsi, Clse, C2si, C2se are not present within the sensor 205, or when the stray capacitances Clsi and C2se are approximately equally matched with stray capacitances C2si and C2se, canceling each other out. However, as illustrated in FIG 23b, a mismatch in the stray capacitances Clsi, Clse across plate 305 and the stray capacitances C2sl, C2se across plate 308 may result in an offset in the position x of the measurement mass 309 away from the mechanical center x=0 of the sensor 205. An offset of the measurement mass 309 away from the mechanical center x=0 of the sensor 205 results in a degradation of sensor 205 performance. During the OPERATING MODE 3, the controller 206 preferably utilizes the effects of the OPERATING MODE 2 to calibrate the voltage Vdac for 1-g cancellation and to cancel the effects of stray capacitances within the sensor 205. The controller 206 may utilize any of the eleven generic operating states described above, or variations thereof, to create the OPERATING MODE 3. In a preferred embodiment, the controller 206 places the sensor 205 in the DUMMY FORCE DOWN STATE, the DUMMY FORCE UP STATE, the GRAVITY CANCELLATION STATE, the VOLTAGE EQUALIZATION STATE, and the SENSING STATE 1 during the OPERATING MODE 3. In a preferred embodiment, as illustrated in FIGS 24 and 25a, the controller 206 begins the OPERATING MODE 3 by placing the sensor 205 in the DUMMY FORCE DOWN STATE to force the measurement mass 309 down away from plate 305 towards plate 308. The controller 206 may place the sensor 205 in the DUMMY FORCE DOWN STATE for any number of the sixteen clock periods within the OPERATING MODE 3. In a preferred embodiment, the controUer 206 places the sensor 205 in the DUMMY FORCE DOWN STATE for clock periods 1 and 2 of the OPERATING MODE 3. Next, as illustrated in FIGS. 24 and 25b, the controller 206 preferably places the sensor 205 in the DUMMY FORCE UP STATE to force the measurement mass 309 up away from plate 308 and towards plate 305. The controller 206 may place the sensor 205 in the DUMMY FORCE UP STATE for any number of the sixteen clock periods within the OPERATING MODE 3. In a preferred embodiment, the controller 206 places the sensor 205 in the DUMMY FORCE UP STATE for clock periods 3 and 4 of the OPERATING MODE 3. Next, as illustrated in FIGS. 24 and 25c, the controller 206 preferably places the sensor 205 in the GRAVITY CANCELLATION STATE. The controller 206 may place the sensor 205 in the GRAVITY CANCELLATION STATE for any number of the sixteen clock periods within the OPERATING MODE 3. In a preferred embodiment, the controller 206 places the sensor 205 in the GRAVITY CANCELLATION STATE for clock periods 5 through 12 of the OPERATING MODE 3. Next, as illustrated in FIGS. 24 and 25d, the controller 206 preferably places the sensor 205 in the VOLTAGE EQUALIZATION STATE. The controller 206 may place the sensor 205 in the VOLTAGE EQUALIZATION STATE for any number of the sixteen clock periods within the OPERATING MODE 3. In a preferred embodiment, the controller 206 places the sensor 205 in the VOLTAGE EQUALIZATION STATE for clock periods 13 and 14 of the OPERATING MODE 3. Finally, as illustrated in FIGS. 24 and 25e, the controller 206 preferably completes the OPERATING MODE 3 by placing the sensor 205 in the SENSING STATE 1 to measure the differential charge on capacitors Cl and C2. During the SENSING STATE 1, the controller 206 preferably analyzes the differential charges to determine the position of the measurement mass 309 within the sensor 205. The differential charges across capacitors Cl and C2 may, for example, be equal or unequal. The controller 206 may place the sensor 205 in the SENSING STATE 1 for any number of the sixteen clock periods within the OPERATING MODE 3. In a preferred embodiment, the controller 206 places the sensor 205 in the SENSING STATE 1 for clock periods 15 and 16 of the OPERATING MODE 3. Referring to FIGS. 26, 27, 28, 29, 30, 31, 32, and 33, the OPERATING MODE 4 will now be described. During the OPERATING MODE 4, the sensor 205 preferably operates in a sigma-delta operating mode. The controller 206 may alter the arrangement of the eleven generic operating states described above, or variations thereof, to create any number of different sigma-delta operating modes. In a preferred embodiment, the controller 206 utilizes eight different configurations to create sub-modes of the OPERATING MODE 4, including: (1) a long forcing mode with dummy forces in OPERATING MODE 4.1, (2) a long forcing mode with dummy forces and test bit interleaving in OPERATING MODE 4.2, (3) a short forcing mode with dummy forces in OPERATING MODE 4.3, (4) a long forcing mode with return-to-zero forces in OPERATING MODE 4.4, (5) a long forcing mode with return-to-zero forces and test bit interleaving in OPERATING MODE 4.5, (6) a short forcing mode with return-to-zero forces in OPERATING MODE 4.6, (7) a short forcing mode with return-to-zero forces and test bit interleaving in OPERATING MODE 4.7, and (8) a very long forcing mode with return-to-zero forces in OPERATING MODE 4.8. In a preferred embodiment, as illustrated in FIG. 26, the controller 206 utilizes a long forcing mode with dummy forces during the OPERATING MODE 4.1. The controller 206 may utihze any number of the eleven generic operating states described above, or variations thereof, to create the OPERATING MODE 4.1. In a preferred embodiment, the controller 206 utilizes the DUMMY FORCE DOWN STATE, the FIRST MODULATOR FORCE UP STATE or the FIRST MODULATOR FORCE DOWN STATE, the DUMMY FORCE UP STATE, the GRAVITY CANCELLATION STATE, the VOLTAGE EQUALIZATION STATE, and the SENSING STATE 1 to create the OPERATING MODE 4.1. In a preferred embodiment, the controller 206 begins the OPERATING MODE 4.1 by placing the sensor 205 in the DUMMY FORCE DOWN STATE to force the measurement mass 309 down away from plate 305 towards plate 308. The controller 206 may place the sensor 205 in the DUMMY FORCE DOWN STATE for any number of the sixteen clock periods within the OPERATING MODE 4.1. In a preferred embodiment, in the OPERATING MODE 4.1, the controller 206 places the sensor 205 in the DUMMY FORCE DOWN STATE for clock period 1 of the OPERATING MODE 4.1. Next, the controller 206 preferably places the sensor 205 in the FIRST MODULATOR FORCE UP STATE or the FIRST MODULATOR FORCE DOWN STATE to force the measurement mass 309 as a function of the position of the measurement mass 309 within the sensor 205. The controller 206 may place the sensor 205 in the FIRST MODULATOR FORCE UP STATE or the FIRST MODULATOR FORCE DOWN STATE for any number of the sixteen clock periods within the OPERATING MODE 4.1. In a preferred embodiment, in the OPERATING MODE 4.1, the controller 206 places the sensor 205 in the FIRST MODULATOR FORCE UP STATE or the FIRST MODULATOR FORCE DOWN STATE for clock periods 2 and 3 of the OPERATING MODE 4.1. Next, the controller 206 preferably places the sensor 205 in the DUMMY FORCE UP STATE to force the measurement mass 309 up away from plate 308 towards plate 305. The controller 206 may place the sensor 205 in the DUMMY FORCE UP STATE for any number of the sixteen clock periods within the OPERATING MODE 4.1. In a preferred embodiment, the controller 206 places the sensor 205 in the DUMMY FORCE UP STATE for clock period 4 of the OPERATING MODE 4.1. Next, the controller 206 preferably places the sensor 205 in the GRAVITY CANCELLATION STATE. The controller 206 may place the sensor 205 in the GRAVITY CANCELLATION STATE for any number of the sixteen clock periods within the OPERATING MODE 4.1. In a preferred embodiment, the controller 206 places the sensor 205 in the GRAVITY CANCELLATION STATE for clock periods 5 through 12 of the OPERATING MODE 4.1. Next, the controller 206 preferably places the sensor 205 in the VOLTAGE EQUALIZATION STATE. The controller 206 may place the sensor 205 in the VOLTAGE EQUALIZATION STATE for any number of the sixteen clock periods within the OPERATING MODE 4.1. In a preferred embodiment, the controller 206 places the sensor 205 in the VOLTAGE EQUALIZATION STATE for clock periods 13 and 14 of the OPERATING MODE 4.1. Finally, the controller 206 preferably places the sensor 205 in the SENSING STATE 1. The controller 206 may place the sensor 205 in the SENSING STATE 1 for any number of the sixteen clock periods within the OPERATING MODE 4.1. In a preferred embodiment, the controller 206 places the sensor 205 in the SENSING STATE 1 for clock periods 15 and 16 of the OPERATING MODE 4.1. In another preferred embodiment, as illustrated in FIG. 27, the controller 206 utilizes a long forcing mode with dummy forces and test interleaving during the OPERATING MODE 4.2. The controller 206 may utihze any number of the eleven generic operating states described above, or variations thereof, to create the OPERATING MODE 4.2. In a preferred embodiment, the controller 206 utilizes the DUMMY FORCE DOWN STATE, the FIRST MODULATOR FORCE UP STATE or the FIRST MODULATOR FORCE DOWN STATE, a test force state, the DUMMY FORCE UP STATE, the GRAVITY CANCELLATION STATE, the VOLTAGE EQUALIZATION STATE, and the SENSING STATE 1 to create the OPERATING MODE 4.2. In a preferred embodiment, the controller 206 begins the OPERATING MODE 4.2 by placing the sensor 205 in the DUMMY FORCE DOWN STATE to force the measurement mass 309 down away from plate 305 towards plate 308. The controller 206 may place the sensor 205 in the DUMMY FORCE DOWN STATE for any number of the sixteen clock periods within the OPERATING MODE 4.2. In a preferred embodiment, the controller 206 places the sensor 205 in the DUMMY FORCE DOWN STATE for clock period 1 of the OPERATING MODE 4.2. Next, the controller 206 preferably places the sensor 205 in the FIRST MODULATOR FORCE UP STATE or the FIRST MODULATOR FORCE DOWN STATE to force the measurement mass 309 as a function of the position of the measurement mass 309 within the sensor 205. The controller 206 may place the sensor 205 in the FIRST MODULATOR FORCE UP STATE or the FIRST MODULATOR FORCE DOWN STATE for any number of the sixteen clock periods within the OPERATING MODE 4.2. In a preferred embodiment, the controller 206 places the sensor 205 in the FIRST MODULATOR FORCE UP STATE or the FIRST MODULATOR FORCE DOWN STATE for clock period 2 of the OPERATING MODE 4.2. Next, the controller 206 preferably places the sensor 205 in a test forcing state. The controller 206 preferably creates the test state by interleaving a test bit input into the data stream in place of the FIRST MODULATOR FORCE UP STATE or the FIRST MODULATOR FORCE DOWN STATE, depending on the value of the output stream IMOD from the loop filter 315. In a preferred embodiment, the controller 206 interleaves the test bit stream substantially as described in United States Patent No. 6,023,960, the disclosure of which is incorporated herein by reference. The controller 206 may place the sensor 205 in the test forcing state for any number of the sixteen clock periods within the OPERATING MODE 4.2. In a preferred embodiment, the controller 206 places the sensor 205 in the test forcing state for clock period 3 of the OPERATING MODE 4.2. Next, the controller 206 preferably places the sensor 205 in the DUMMY FORCE UP STATE to force the measurement mass 309 up away from plate 308 towards plate 305. The controller 206 may place the sensor 205 in the DUMMY FORCE UP STATE for any number of the sixteen clock periods within the OPERATING MODE 4.2. In a preferred embodiment, the controller 206 places the sensor 205 in the DUMMY FORCE UP STATE for clock period 4 of the OPERATING MODE 4.2. Next, the controller 206 preferably places the sensor 205 in the GRAVITY CANCELLATION STATE. The controller 206 may place the sensor 205 in the GRAVITY CANCELLATION STATE for any number of the sixteen clock periods within the OPERATING MODE 4.2. In a preferred embodiment, the controller 206 places the sensor 205 in the GRAVITY CANCELLATION STATE for clock periods 5 through 12 of the OPERATING MODE 4.2. Next, the controller preferably places the sensor 205 in the VOLTAGE EQUALIZATION STATE. The controller 206 may place the sensor 205 in the VOLTAGE EQUALIZATION STATE for any number of the sixteen clock periods within the OPERATING MODE 4.2. In a preferred embodiment, the controller 206 places the sensor 205 in the VOLTAGE EQUALIZATION STATE for clock periods 13 and 14 of the OPERATING MODE 4.2. Finally, the controller 206 preferably places the sensor 205 in the SENSING STATE 1. The controller 206 may place the sensor 205 in the SENSING STATE 1 for any number of the sixteen clock periods within the OPERATING MODE 4.2. In a preferred embodiment, the controller 206 places the sensor 205 in the SENSING STATE 1 for clock periods 15 and 16 of the OPERATING MODE 4.2. In another preferred embodiment, as illustrated in FIG. 28, the controller 206 utihzes a short forcing mode with dummy forces during the OPERATING MODE 4.3. The controller 206 may utihze any number of the eleven generic operating states described above, or variations thereof, to create the OPERATING MODE 4.3. In a preferred embodiment, the controller 206 utihzes the DUMMY FORCE DOWN STATE, the FIRST MODULATOR FORCE UP STATE or the FIRST MODULATOR FORCE DOWN STATE, the DUMMY FORCE UP STATE, the GRAVITY CANCELLATION STATE, the VOLTAGE EQUALIZATION STATE, and the SENSING STATE 1 to create the OPERATING MODE 4.3. In a preferred embodiment, the controller 206 begins the OPERATING MODE 4.3 by placing the sensor 205 in the DUMMY FORCE DOWN STATE to force the measurement mass 309 down away from plate 305 towards plate 308. The controller 206 may place the sensor 205 in the DUMMY FORCE DOWN STATE for any number of the sixteen clock periods within the OPERATING MODE 4.3. In a preferred embodiment, the controller 206 places the sensor 205 in the DUMMY FORCE DOWN STATE for clock period 1 and the first half of clock period 2 of the OPERATING MODE 4.3. Next, the controller 206 preferably places the sensor 205 in the FIRST MODULATOR FORCE UP STATE or the FIRST MODULATOR FORCE DOWN STATE to force the measurement mass 309 as a function of the position of the measurement mass 309 within the sensor 205. The controller 206 may place the sensor 205 in the FIRST MODULATOR FORCE UP STATE or the FIRST MODULATOR FORCE DOWN STATE for any number of the sixteen clock periods within the OPERATING MODE 4.3. In a preferred embodiment, the controller 206 places the sensor 205 in the FIRST MODULATOR FORCE UP STATE or the FIRST MODULATOR FORCE DOWN STATE for the second half of clock period 2 and the first half of clock period 3 within the OPERATING MODE 4.3. Next, the controller 206 preferably places the sensor 205 in the DUMMY FORCE UP STATE to force the measurement mass 309 up away from plate 308 towards plate 305. The controller 206 may place the sensor 205 in the DUMMY FORCE UP STATE for any number of the sixteen clock periods within the OPERATING MODE 4.3. In a preferred embodiment, the controller 206 places the sensor 205 in the DUMMY FORCE UP STATE for the second half of clock period 3 and clock period 4 of the OPERATING MODE 4.3. Next, the controller 206 preferably places the sensor 205 in the GRAVITY CANCELLATION STATE. The controUer 206 may place the sensor 205 in the GRAVITY CANCELLATION STATE for any number of the sixteen clock periods within the OPERATING MODE 4.3. In a preferred embodiment, the controUer 206 places the sensor 205 in the GRAVITY CANCELLATION STATE for clock periods 5 through 12 of the OPERATING MODE 4.3. Next, the controUer 206 preferably places the sensor 205 in the VOLTAGE EQUALIZATION STATE. The controUer 206 may place the sensor 205 in the VOLTAGE EQUALIZATION STATE for any number of the sixteen clock periods within the OPERATING MODE 4.3. In a preferred embodiment, the controUer 206 places the sensor 205 in the VOLTAGE EQUALIZATION STATE for clock periods 13 and 14 of the OPERATING MODE 4.3. FinaUy, the controUer 206 preferably places the sensor 205 in the SENSING STATE 1. The controUer 206 may place the sensor 205 in the SENSING STATE 1 for any number of the sixteen clock periods within the OPERATING MODE 4.3. In a preferred embodiment, the controUer 206 places the sensor 205 in the SENSING STATE 1 for clock periods 15 and 16 of the OPERATING MODE 4.3. In another preferred embodiment, as iUustrated in FIG. 29, the controUer 206 ut izes a long forcing mode with return-to-zero forces during the OPERATING MODE 4.4. The controUer 206 may utilize any number of the eleven generic operating states described above, or variations thereof, to create the OPERATING MODE 4.4. In a preferred embodiment, the controller 206 utihzes the RETURN-TO-ZERO STATE, the FIRST MODULATOR FORCE UP STATE or the FIRST MODULATOR FORCE DOWN STATE, the GRAVITY CANCELLATION STATE, the VOLTAGE EQUALIZATION STATE, and the SENSING STATE 1 to create the OPERATING MODE 4.4. In a preferred embodiment, the controUer 206 begins the OPERATING MODE 4.4 by placing the sensor 205 in the RETURN-TO-ZERO STATE to remove charges from the conductive plates 305, 306, 307, and 308. The controUer 206 may place the sensor 205 in the RETURN-TO-ZERO STATE for any number of the sixteen clock periods within the OPERATING MODE 4.4. In a preferred embodiment, the controller 206 places the sensor 205 in the RETURN-TO-ZERO STATE for clock periods 1 and 4 of the OPERATING MODE 4.4. Next, the controller 206 preferably places the sensor 205 in the FIRST MODULATOR FORCE UP STATE or the FIRST MODULATOR FORCE DOWN STATE to force the measurement mass 309 as a function of the position of the measurement mass 309 within the sensor 205. The controUer 206 may place the sensor 205 in the FIRST MODULATOR FORCE UP STATE or the FIRST MODULATOR FORCE DOWN STATE for any number of the sixteen clock periods within the OPERATING MODE 4.4. In a preferred embodiment, the controller 206 places the sensor 205 in the FIRST MODULATOR FORCE UP STATE or the FIRST MODULATOR FORCE DOWN STATE for clock periods 2 and 3 of the OPERATING MODE 4.4. Next, the controUer 206 preferably places the sensor 205 in the GRAVITY CANCELLATION STATE. The controUer 206 may place the sensor 205 in the GRAVITY CANCELLATION STATE for any number of the sixteen clock periods within the OPERATING MODE 4.4. In a preferred embodiment, the controUer 206 places the sensor 205 in the GRAVITY CANCELLATION STATE for clock periods 5 through 12 of the OPERATING MODE 4.4. Next, the controUer 206 preferably places the sensor 205 in the VOLTAGE EQUALIZATION STATE. The controller 206 may place the sensor 205 in the VOLTAGE EQUALIZATION STATE for any number of the sixteen clock periods within the OPERATING MODE 4.4. In a preferred embodiment, the controUer 206 places the sensor 205 in the VOLTAGE EQUALIZATION STATE for clock periods 13 and 14 of the OPERATING MODE 4.4. Finally, the controller 206 preferably places the sensor 205 in the SENSING STATE 1. The controller 206 may place the sensor 205 in the SENSING STATE 1 for any number of the sixteen clock periods within the OPERATING MODE 4.4. In a preferred embodiment, the controller 206 places the sensor 205 in the SENSING STATE 1 for clock periods 15 and 16 of the OPERATING MODE 4.4. In a preferred embodiment, as Ulustrated in FIG. 30, the controller 206 utilizes a long forcing mode with return-to-zero forces and test bit interleaving during the OPERATING MODE 4.5. The controller 206 may utUize any number of the eleven generic operating states described above, or variations thereof, to create the OPERATING MODE 4.5. In a preferred embodiment, the controUer 206 utilizes the RETURN-TO-ZERO STATE, the FIRST MODULATOR FORCE UP STATE or the FIRST MODULATOR FORCE DOWN STATE, the test forcing state, the GRAVITY CANCELLATION STATE, the VOLTAGE EQUALIZATION STATE, and the SENSING STATE 1 to create the OPERATING MODE 4.5. In a preferred embodiment, the controller 206 begins the OPERATING MODE 4.5 by placing the sensor 205 in the RETURN-TO-ZERO STATE to remove charges from the conductive plates 305, 306, 307, and 308. The controUer 206 may place the sensor 205 in the RETURN-TO-ZERO STATE for any number of the sixteen clock periods within the OPERATING MODE 4.5. In a preferred embodiment, the controller 206 places the sensor 205 in the RETURN-TO-ZERO STATE for clock period 1, the first half of clock period 3, and the second half of clock period 4 of the OPERATING MODE 4.5. Next, the controUer 206 preferably places the sensor 205 in the FIRST MODULATOR FORCE UP STATE or the FIRST MODULATOR FORCE DOWN STATE to force the measurement mass 309 as a function of the position of the measurement mass 309 within the sensor 205. The controUer 206 may place the sensor 205 in the FIRST MODULATOR FORCE UP STATE or the FIRST MODULATOR FORCE DOWN STATE for any number of the sixteen clock periods within the OPERATING MODE 4.5. In a preferred embodiment, the controller 206 places the sensor 205 in the FIRST MODULATOR FORCE UP STATE or the FIRST MODULATOR FORCE DOWN STATE for clock period 2 of the OPERATING MODE 4.5. Next, the controUer 206 preferably places the sensor 205 in the test forcing state. The controller 206 preferably creates the test state by interleaving a test bit input into the data stream in place of the FIRST MODULATOR FORCE UP STATE or the FIRST MODULATOR FORCE DOWN STATE, depending on the value of the output stream IMOD from the loop filter 315. In a preferred embodiment, the controUer 206 interleaves the test bit stream substantiaUy as described in United States Patent No. 6,023,960, the disclosure of which is incorporated herein by reference. The controUer 206 may place the sensor 205 in the test forcing state for any number of the sixteen clock periods within the OPERATING MODE 4.5. In a preferred embodiment, the controller 206 places the sensor 205 in the test forcing state for the second half of clock period 3 and the first half of clock period 4 of the OPERATING MODE 4.5. Next, the controUer 206 preferably places the sensor 205 in the GRAVITY CANCELLATION STATE. The controUer 206 may place the sensor 205 in the GRAVITY CANCELLATION STATE for any number of the sixteen clock periods within the OPERATING MODE 4.5. In a preferred embodiment, the controUer 206 places the sensor 205 in the GRAVITY CANCELLATION STATE for clock periods 5 through 12 of the OPERATING MODE 4.5. Next, the controUer 206 preferably places the sensor 205 in the VOLTAGE EQUALIZATION STATE. The controUer 206 may place the sensor 205 in the VOLTAGE EQUALIZATION STATE for any number of the sixteen clock periods within the OPERATING MODE 4.5. In a preferred embodiment, the controller 206 places the sensor 205 in the VOLTAGE EQUALIZATION STATE for clock periods 13 and 14 of the OPERATING MODE 4.5. Finally, the controller 206 preferably places the sensor 205 in the SENSING STATE 1. The controUer 206 may place the sensor 205 in the SENSING STATE 1 for any number of the sixteen clock periods within the OPERATING MODE 4.5. In a preferred embodiment, the controUer 206 places the sensor 205 in the SENSING STATE 1 for clock periods 15 and 16 of the OPERATING MODE 4.5. In another preferred embodiment, as Ulustrated in FIG. 31, the controUer 206 utihzes a short forcing mode with return-to-zero forces during the OPERATING MODE 4.6. The controUer 206 may utihze any number of the eleven generic operating states described above, or variations thereof, to create the OPERATING MODE 4.6. In a preferred embodiment, the controUer 206 utUizes the RETURN-TO-ZERO STATE, the FIRST MODULATOR FORCE UP STATE or the FIRST MODULATOR FORCE DOWN STATE, the GRAVITY CANCELLATION STATE, the VOLTAGE EQUALIZATION STATE, and the SENSING STATE 1 to create the OPERATING MODE 4.6. In a preferred embodiment, the controUer 206 begins the OPERATING MODE 4.6 by placing the sensor 205 in the RETURN-TO-ZERO STATE to remove charges from the conductive plates 305, 306, 307, and 308. The controUer 206 may place the sensor 205 in the RETURN-TO-ZERO STATE for any number of the sixteen clock periods within the OPERATING MODE 4.6. In a preferred embodiment, the controUer 206 places the sensor 205 in the RETURN-TO-ZERO STATE for clock periods 1, 3 and 4 of the OPERATING MODE 4.6. Next, the controller 206 preferably places the sensor 205 in the FIRST MODULATOR FORCE UP STATE or the FIRST MODULATOR FORCE DOWN STATE to force the measurement mass 309 as a function of the position of the measurement mass 309 within the sensor 205. The controller 206 may place the sensor 205 in the FIRST MODULATOR FORCE UP STATE or the FIRST MODULATOR FORCE DOWN STATE for any number of the sixteen clock periods within the OPERATING MODE 4.6. In a preferred embodiment, the controUer 206 places the sensor 205 in the FIRST MODULATOR FORCE UP STATE or the FIRST MODULATOR FORCE DOWN STATE for clock period 2 of the OPERATING MODE 4.6. Next, the controller 206 preferably places the sensor 205 in the GRAVITY CANCELLATION STATE. The controUer 206 may place the sensor 205 in the GRAVITY CANCELLATION STATE for any number of the sixteen clock periods within the OPERATING MODE 4.6. In a preferred embodiment, the controUer 206 places the sensor 205 in the GRAVITY CANCELLATION STATE for clock periods 5 through 12 of the OPERATING MODE 4.6. Next, the controller 206 preferably places the sensor 205 in the VOLTAGE EQUALIZATION STATE. The controller 206 may place the sensor 205 in the VOLTAGE EQUALIZATION STATE for any number of the sixteen clock periods within the OPERATING MODE 4.6. In a preferred embodiment, the controUer 206 places the sensor 205 in the VOLTAGE EQUALIZATION STATE for clock periods 13 and 14 of the OPERATING MODE 4.6. Finally, the controller 206 preferably places the sensor 205 in the SENSING STATE 1. The controUer 206 may place the sensor 205 in the SENSING STATE 1 for any number of the sixteen clock periods within the OPERATING MODE 4.6. In a preferred embodiment, the controUer 206 places the sensor 205 in the SENSING STATE 1 for clock periods 15 and 16 of the OPERATING MODE 4.6. In another preferred embodiment, as Ulustrated in FIG. 32, the controller 206 utihzes a short forcing mode with return-to-zero forces and test bit interleaving during the OPERATING MODE 4.7. The controUer 206 may utUize any number of the eleven generic operating states described above, or variations thereof, to create the OPERATING MODE 4.7. In a preferred embodiment, the controller 206 utilizes the RETURN-TO-ZERO STATE, the FIRST MODULATOR FORCE UP STATE or the FIRST MODULATOR FORCE DOWN STATE, the test forcing state, the GRAVITY CANCELLATION STATE, the VOLTAGE EQUALIZATION STATE, and the SENSING STATE 1 to create the OPERATING MODE 4.7. In a preferred embodiment, the controUer 206 begins the OPERATING MODE 4.7 by placing the sensor 205 in the RETURN-TO-ZERO STATE to remove charges from the conductive plates 305, 306, 307, and 308. The controUer 206 may place the sensor 205 in the RETURN-TO-ZERO STATE for any number of the sixteen clock periods within the OPERATING MODE 4.7. In a preferred embodiment, the controUer 206 places the sensor 205 in the RETURN-TO-ZERO STATE for clock period 1, the first half of clock period 3, and the second half of clock period 4 of the OPERATING MODE 4.7. Next, the controUer 206 preferably places the sensor 205 in the FIRST MODULATOR FORCE UP STATE or the FIRST MODULATOR FORCE DOWN STATE to force the measurement mass 309 as a function of the position of the measurement mass 309 within the sensor 205. The controUer 206 may place the sensor 205 in the FIRST MODULATOR FORCE UP STATE or the FIRST MODULATOR FORCE DOWN STATE for any number of the sixteen clock periods within the OPERATING MODE 4.7. In a preferred embodiment, the controUer 206 places the sensor 205 in the FIRST MODULATOR FORCE UP STATE or the FIRST MODULATOR FORCE DOWN STATE for clock period 2 of the OPERATING MODE 4.7. Next, the controUer 206 preferably places the sensor 205 in the test forcing state. The controUer 206 preferably creates the test state by interleaving a test bit input into the data stream in place of the FIRST MODULATOR FORCE UP STATE or the FIRST MODULATOR FORCE DOWN STATE, depending on the value of the output stream IMOD. In a preferred embodiment, the controUer 206 interleaves the test bit stream substantiaUy as described in United States Patent No. 6,023,960, the disclosure of which is incorporated herein by reference. The controUer 206 may place the sensor 205 in the test forcing state for any number of the sixteen clock periods within the OPERATING MODE 4.7. In a preferred embodiment, the controller 206 places the sensor 205 in the test forcing state for the second half of clock period 3 and the first half of clock period 4 of the OPERATING MODE 4.7. Next, the controUer 206 preferably places the sensor 205 in the GRAVITY CANCELLATION STATE. The controUer 206 may place the sensor 205 in the GRAVITY CANCELLATION STATE for any number of the sixteen clock periods within the OPERATING MODE 4.7. In a preferred embodiment, the controUer 206 places the sensor 205 in the GRAVITY CANCELLATION STATE for clock periods 5 through 12 of the OPERATING MODE 4.7. Next, the controUer 206 preferably places the sensor 205 in the VOLTAGE EQUALIZATION STATE. The controUer 206 may place the sensor 205 in the VOLTAGE EQUALIZATION STATE for any number of the sixteen clock periods within the OPERATING MODE 4.7. In a preferred embodiment, the controller 206 places the sensor 205 in the VOLTAGE EQUALIZATION STATE for clock periods 13 and 14 of the OPERATING MODE 4.7. FinaUy, the controUer 206 preferably places the sensor 205 in the SENSING STATE 1. The controUer 206 may place the sensor 205 in the SENSING STATE 1 for any number of the sixteen clock periods within the OPERATING MODE 4.7. In a preferred embodiment, the controller 206 places the sensor 205 in the SENSING STATE 1 for clock periods 15 and 16 of the OPERATING MODE 4.7. In another preferred embodiment, as Ulustrated in FIG. 33, the controUer 206 utihzes a very long forcing mode with return-to-zero forces during the OPERATING MODE 4.8. The controUer 206 may utUize any number of the eleven generic operating states described above, or variations thereof, to create the OPERATING MODE 4.8. In a preferred embodiment, the controller 206 utihzes the RETURN-TO-ZERO STATE, the FIRST MODULATOR FORCE UP STATE or the FIRST MODULATOR FORCE DOWN STATE, the VOLTAGE EQUALIZATION STATE, and the SENSING STATE 1 to create the OPERATING MODE 4.8. In a preferred embodiment, the controUer 206 begins the OPERATING MODE 4.8 by placing the sensor 205 in the RETURN-TO-ZERO STATE to remove charges from the conductive plates 305, 306, 307, and 308. The controUer 206 may place the sensor 205 in the RETURN-TO-ZERO STATE for any number of the sixteen clock periods within the OPERATING MODE 4.8. In a preferred embodiment, the controUer 206 places the sensor 205 in the RETURN-TO-ZERO STATE for clock periods 1, 10, 11, and 12 of the OPERATING MODE 4.8. Next, the controUer 206 preferably places the sensor 205 in the FIRST MODULATOR FORCE UP STATE or the FIRST MODULATOR FORCE DOWN STATE to force the measurement mass 309 as a function of the position of the measurement mass 309 within the sensor 205. The controUer 206 may place the sensor 205 in the FIRST MODULATOR FORCE UP STATE or the FIRST MODULATOR FORCE DOWN STATE for any number of the sixteen clock periods within the OPERATING MODE 4.8. In a preferred embodiment, the controller 206 places the sensor 205 in the FIRST MODULATOR FORCE UP STATE or the FIRST MODULATOR FORCE DOWN STATE for clock periods 2 through 9 of the OPERATING MODE 4.8. Next, the controUer 206 preferably places the sensor 205 in the VOLTAGE EQUALIZATION STATE. The controller 206 may place the sensor 205 in the VOLTAGE EQUALIZATION STATE for any number of the sixteen clock periods within the OPERATING MODE 4.8. In a preferred embodiment, the controUer 206 places the sensor 205 in the VOLTAGE EQUALIZATION STATE for clock periods 13 and 14 of the OPERATING MODE 4.8. FinaUy, the controUer 206 preferably places the sensor 205 in the SENSING STATE 1. The controUer 206 may place the sensor 205 in the SENSING STATE 1 for any number of the sixteen clock periods within the OPERATING MODE 4.8. In a preferred embodiment, the controUer 206 places the sensor 205 in the SENSING STATE 1 for clock periods 15 and 16 of the OPERATING MODE 4.8. The controller 206 preferably uses the OPERATING MODE 1, the OPERATING MODE 2, the OPERATING MODE 3, and the OPERATING MODE 4 to create a startup sequence for the system 100. The controller 206 may arrange the OPERATING MODE 1, the OPERATING MODE 2, the OPERATING MODE 3, and the OPERATING MODE 4 in any number of combinations suitable for creating a start-up sequence for the sensor system 100. The controUer 206 preferably applies the OPERATING MODE 1, the OPERATING MODE 2, the OPERATING MODE 3, and the OPERATING MODE 4 in four arrangements to create four different startup sequences, including (1) a startup sequence 3400 without stray capacitance calibration, (2) a startup sequence 3500 with stray capacitance calibration, (3) a startup sequence 3600 without stray capacitance calibration where the controller 206 remains in an analog output mode, and (4) a startup sequence 3700 with stray capacitance calibration where the controUer 206 remains in an analog output mode. Referring to FIG. 34, a startup sequence 3400 without stray capacitance calibration will be described. In a preferred embodiment, the startup sequence 3400 includes: using the OPERATING MODE 1 to set up the measurement mass 309 within the sensor 205 in step 3405, using the OPERATING MODE 3 to calibrate the sensor 205 in step 3410, and using the OPERATING MODE 4 to run the controUer 206 with the sensor 205 inside a delta-sigma modulator loop in step 3415. In a preferred embodiment, in step 3405 the controller 206 begins the startup sequence 3400 by utihzing the OPERATING MODE 1. The controUer 206 preferably uses the OPERATING MODE 1 to pull the measurement mass 309 from a resting position within the sensor 205 and to position the measurement mass 309 within the sensor 205 so that the charges across capacitor Cl and capacitor C2 are substantially equal in magnitude. Next, in step 3410, the controUer 206 preferably utihzes the OPERATING MODE 3 to cancel the effects of gravitational forces on the sensor 205 and to calibrate the sensor 205. In a preferred embodiment, the controUer 206 calibrates the sensor 205 so that the operating range of the sensor 205 is approximately +/- O.lg. Finally, in step 3415 the controUer 206 preferably concludes the startup sequence 3400 by operating the sensor system 100 in the OPERATING MODE 4. In a preferred embodiment, the controller 206 operates the sensor system 100 in a sigma-delta operating mode during the OPERATING MODE 4. The controUer 206 may utUize any of the eight sub-modes of the OPERATING MODE 4 described above, such as, for example, the OPERATING MODE 4.1, the OPERATING MODE 4.2, the OPERATING MODE 4.3, the OPERATING MODE 4.4, the OPERATING MODE 4.5, the OPERATING MODE 4.6, the OPERATING MODE 4.7, or the OPERATING MODE 4.8. In a preferred embodiment, during the OPERATING MODE 4, the controUer 206 applies electrostatic forces to the sensor 205 designed to offset the effects of external acceleration forces experienced by the sensor 205. Referring to FIG. 35, a startup sequence 3500 with stray capacitance calibration wUl now be described. In a preferred embodiment, the startup sequence 3500 includes: using the OPERATING MODE 1 to set up the measurement mass 309 within the sensor 205 in step 3505, using the OPERATING MODE 2 to cahbrate the sensor 205 in step 3510, applying the OPERATING MODE 3 to cancel the effects of stray capacitance within the sensor 205 in step 3515, and using the OPERATING MODE 4 to run the controUer 206 with the sensor 205 inside a delta-sigma modulator loop in step 3520. In a preferred embodiment, in step 3505 the controUer 206 begins the startup sequence 3500 by utihzing the OPERATING MODE 1. The controller 206 preferably uses the OPERATING MODE 1 to puU the measurement mass 309 from a resting position within the sensor 205 and to position the measurement mass 309 within the sensor 205 so that the capacitor Cl and capacitor C2 are substantiaUy equal in magnitude. Next, in step 3510 the controUer 206 preferably utUizes the OPERATING MODE 2 to cancel the effects of gravitational forces on the sensor 205 and to cahbrate the sensor 205. In a preferred embodiment, the controller 206 calibrates the sensor 205 so that the operating range of the sensor 205 is approximately +/- O.lg. Next, in step 3515 the controUer 206 preferably utihzes the OPERATING MODE 3 to optimize the performance of the sensor 205 by canceling the effects of stray capacitances within the sensor 205. The controUer 206 preferably utihzes the OPERATING MODE 2 and the OPERATING MODE 3 together to cahbrate the sensor 205 and cancel the effects of gravity and stray capacitances on the sensor 205. FinaUy, in step 3520 the controUer 206 preferably concludes the startup sequence 3500 by operating the sensor system 100 in the OPERATING MODE 4. In a preferred embodiment, the controUer 206 operates the sensor system 100 in a sigma-delta operating mode during the OPERATING MODE 4. The controUer 206 may utUize any of the eight sub-modes of the OPERATING MODE 4 described above, such as, for example, the OPERATING MODE 4.1, the OPERATING MODE 4.2, the OPERATING MODE 4.3, the OPERATING MODE 4.4, the OPERATING MODE 4.5, the OPERATING MODE 4.6, the OPERATING MODE 4.7, or the OPERATING MODE 4.8. In a preferred embodiment, during the OPERATING MODE 4, the controUer 206 apphes electrostatic forces to the sensor 205 designed to offset the effects of external acceleration forces experienced by the sensor 205. Referring to FIG. 36, a startup sequence 3600 without stray capacitance cahbration where the controUer 206 remains in an analog output mode wUl now be described. In a preferred embodiment, the startup sequence 3600 includes: using the OPERATING MODE 1 to set up the measurement mass 309 within the sensor 205 in step 3605, and applying an OPERATING MODE 2 Extended to continuously servo the measurement mass 309 to the center position between plates 305 and 308 in response to external accelerations in step 3610. The startup sequence 3600 is preferably used when the sensor 205 is to operate as an approximately +/- 2g analog output accelerometer. In a preferred embodiment, in step 3605 the controUer 206 begins the startup sequence 3600 by utihzing the OPERATING MODE 1. The controUer 206 preferably uses the OPERATING MODE 1 to pull the measurement mass 309 from a resting position within the sensor 205 and to position the measurement mass 309 within the sensor 205 so that the capacitor Cl and the capacitor C2 are substantially equal in magnitude. In step 3610, the controUer 206 preferably concludes the startup sequence 3600 by utihzing an extended version of the OPERATING MODE 2. In a preferred embodiment, the extended version of the OPERATING MODE 2 cancels the effects of external acceleration forces on the sensor 205 within a range of approximately +/- 2g. Referring to FIG. 37, a startup sequence 3700 with stray capacitance cahbration where the controUer 206 remains in an analog output mode wiU now be described. In a preferred embodiment, the startup sequence 3700 includes: using the OPERATING MODE 1 to set up the measurement mass 309 within the sensor 205 in step 3705, using the OPERATING MODE 2 to cahbrate the sensor 205 in step 3710, applying the OPERATING MODE 3 to cancel the effects of stray capacitance within the sensor 205 in step 3715, and using the OPERATING MODE 2 Extended to continuously servo the measurement mass 309 to the center position between plates 305 and 308 in response to external accelerations in step 3720. In a preferred embodiment, in step 3705 the controller 206 begins the startup sequence 3700 by utihzing the OPERATING MODE 1. The controUer 206 preferably uses the OPERATING MODE 1 to pull the measurement mass 309 from a resting position within the sensor 205 and to position the measurement mass 309 within the sensor 205 so that the capacitor Cl and the capacitor C2 are substantiaUy equal in magnitude. Next, in step 3710 the controUer 206 preferably utUizes the OPERATING MODE 2 to cancel the effects of gravitational forces on the sensor 205 and to cahbrate the sensor 205. In a preferred embodiment, the controUer 206 calibrates the sensor 205 so that the operating range of the sensor 205 is approximately +/- O.lg. Next, in step 3715 the controller 206 preferably utUizes the OPERATING MODE 3 to optimize the performance of the sensor 205 by canceling the effects of stray capacitances within the sensor 205. The controUer 206 preferably utUizes the OPERATING MODE 2 and the OPERATING MODE 3 together to cahbrate the sensor 205 and cancel the effects of gravity and stray capacitances on the sensor 205. Finally, in step 3720 the controller 206 preferably concludes the startup sequence 3700 by utihzing an extended version of the OPERATING MODE 2. In a preferred embodiment, the extended version of the OPERATING MODE 2 cancels the effects of external acceleration forces on the sensor 205 within a range of approximately +/- 2g. During normal operation of the sensor system 100, the sensor 205 preferably experiences external acceleration forces that cause the measurement mass 309 to move around within the sensor 205. In a preferred embodiment, the controUer 206 cancels the effects of acceleration forces experienced by the sensor 205 by utihzing the OPERATING MODE 4 during normal sigma-delta operation. The controUer 206 may cancel the effects of the acceleration forces on the sensor 205 during the OPERATING MODE 4 using any number of methods suitable for canceling the acceleration forces, such as, for example, pulse width modulation or multi-bit sigma-delta modulation. In a preferred embodiment, the controUer 206 uses a 1-bit sigma-delta modulated dynamic acceleration canceling force to cancel the effects of acceleration on the sensor 205. Referring to FIGS. 38, 39, 40, and 41, the dynamic acceleration canceling force wUl now be described. In a preferred embodiment, the dynamic acceleration canceling forcing uses orientation-independent electrostatic forcing to offset the effects of acceleration forces on the sensor 205. In a preferred embodiment, as Ulustrated in FIG. 38, the sensor 205 is positioned in an upright manner and a downward acceleration force is apphed to the sensor 205. The position of the conductive plates 305, 306, 307, and 308 within the sensor 205 preferably creates the variable capacitors Cl and C2 within the sensor 205. In a preferred embodiment, the conductive plates 305 and 306 interact to create the capacitor Cl. In a preferred embodiment, the conductive plates 307 and 308 interact to form the capacitor C2. In a preferred embodiment, the downward acceleration force apphed to the upright sensor 205 causes the measurement mass 309 to move upward. The upward movement of the measurement mass 309 causes the conductive plate 306 to move towards the conductive plate 305, and the conductive plate 307 to move away from the conductive plate 308. As a result, when the upright sensor 205 experiences a downward acceleration force, the capacitance across the capacitor Cl becomes greater than the capacitance across the capacitor C2. The sense amplifier 405 preferably senses the capacitances across the capacitors Cl and C2 when the controller 206 operates in a sensing mode. When the capacitor Cl is greater than the capacitor C2, the output V x from the sense amplifier 405 in the front-end circuit 310 is preferably positive. In a preferred embodiment, during sigma-delta operation, the positive output V x from the sense amplifier 405 in the front-end circuit 310 is sent to the loop filter 315. The loop filter 315 preferably receives the positive output Vx from the sense amplifier 405 and converts it into an output signal IMOD. The output signal IMOD from the loop filter 315 is preferably supphed by the comparator 530. When the output Vx from the sense amplifier 405 is positive, the output signal IMOD from the loop filter 315 preferably equals, on the average, zero. In a preferred embodiment, when the output signal IMOD equals zero, the controUer 206 switches from the sensing mode to a forcing mode and apphes the FIRST MODULATOR FORCE DOWN STATE to the sensor 205. In a preferred embodiment, as Ulustrated in FIG. 39, the FIRST MODULATOR FORCE DOWN STATE is created by applying the positive reference voltage + V ref to the conductive plate 305, the positive reference voltage + V ref to the conductive plates 306 and 307 on the measurement mass 309, and the negative reference voltage -V ref to the conductive plate 308. The electrostatic force resulting from the voltages + V ref and -V ref preferably moves the measurement mass 309 downward away from the conductive plate 305 and towards the conductive plate 308, canceling the upward movement of the measurement mass 309 caused by the downward acceleration force on the sensor 205. The magnitude of the electrostatic force, FI, used to cancel the effects of the downward acceleration on the upright sensor 205 is preferably given by: where: ε = the dielectric constant of the gaps between the plates 305, 306, 307, and 308, A = area of the plates 305, 306, 307, and 308, V p = magnitude of the positive reference voltage apphed to conductive plates 305, 306, and 307, V n = magnitude of the negative reference voltage apphed to conductive plate 308, and D = distance between the center of the measurement mass 309 and the conductive plate 308, as Ulustrated in FIG. 39. In another preferred embodiment, as Ulustrated in FIGS. 40 and 41, the sensor 205 is positioned in an upside down manner and a downward acceleration force is apphed to the sensor 205. The position of the conductive plates 305, 306, 307, and 308 within the sensor 205 preferably creates variable capacitors Cl and C2 within the sensor 205. In a preferred embodiment, the conductive plates 305 and 306 interact to create the capacitor Cl. In a preferred embodiment, the conductive plates 307 and 308 interact to form the capacitor C2. In a preferred embodiment, the downward acceleration force applied to the upside down sensor 205 causes the measurement mass 309 to move upward, which corresponds to a downward movement of the measurement mass 309 in an upright sensor 205. The upward movement of the measurement mass 309 causes the conductive plate 307 to move towards the conductive plate 308, and the conductive plate 306 to move away from the conductive plate 305. Therefore, when the upside down sensor 205 experiences a downward acceleration force, the capacitance across the capacitor C2 becomes greater than the capacitance across the capacitor Cl. The sense amplifier 405 preferably senses the capacitances across the capacitors Cl and C2 when the controUer 206 operates in the sensing mode. When the capacitor C2 is greater than the capacitor Cl, the output V x from the sense amplifier 405 is preferably negative. In a preferred embodiment, during sigma-delta operation, the negative output V x from the sense amplifier 405 in the front-end circuit 310 is sent to the loop filter 315. The loop filter 315 preferably receives the negative output Vx from the sense amplifier 405 and converts it into an output signal IMOD. The output signal IMOD from the loop filter 315 is preferably supphed by the comparator 530. When the output Vx from the sense amplifier 405 is negative, the output signal IMOD from the loop filter 315 preferably equals, on the average, one. In a preferred embodiment, when the output signal IMOD from the loop filter 315 equals one, the controUer 206 switches from the sensing mode to the forcing mode and apphes the FIRST MODULATOR FORCE UP STATE to the sensor 205. In a preferred embodiment, as illustrated in FIG. 41, the FIRST MODULATOR FORCE UP STATE is created by applying the positive reference voltage +V ref to plate 305, the negative reference voltage -V ref to plates 306 and 307 on the measurement mass 309, and the negative reference voltage -V ref to plate 308. The electrostatic force resulting from the application of the voltages + V^ and -V ref preferably moves the measurement mass 309 down away from plate 308 and towards plate 305, canceling the upward movement of the measurement mass 309 caused by the acceleration force on the sensor 205. The magnitude of the electrostatic force, F2, used to cancel the effects of the downward acceleration apphed to the upside-down sensor 205 is preferably given by: where: ε = dielectric constant of the gaps between the plates 305, 306, 307, and 308, A = area of the plates 305, 306, 307, and 308, V p = magnitude of the positive reference voltage apphed to conductive plate 305, V n = magnitude of the negative reference voltage applied to conductive plates 306, 307, and 308, and D = distance between the center of the measurement mass 309 and the conductive plate 308, as Ulustrated in FIG. 41. In a preferred embodiment, the magnitude of the electrostatic force F2 applied to cancel the effects of the downward acceleration force on the upside down sensor 205 is substantiaUy the same as the electrostatic force FI apphed to cancel the effects of an upward acceleration force of the same magnitude on the upright sensor 205. Likewise, the electrostatic force apphed to cancel the effects of the upward acceleration force on the upside down sensor 205 is preferably substantiaUy identical to the force apphed to cancel the effects of an downward acceleration force of the same magnitude on the upright sensor 205. Therefore, in a preferred embodiment, the electrostatic forces required to offset the effects of acceleration forces on the sensor 205 are dependent on the directional movement of the measurement mass 309 with respect to the conductive plates 305, 306, 307, and 308 and are independent of the orientation of the sensor 205. Referring to FIGS. 5, 42, and 43, the operation of the loop filter 315 in the controUer 206 wUl now be described. The operation of the loop filter 315 may, for example, vary as a function of the operating mode of the sensor 205. The loop filter 315 may, for example, operate in a normal operating mode or in a reduced- order mode. In a preferred embodiment, the loop filter 315 operates in the reduced-order mode during the OPERATING MODE 1, the OPERATING MODE 2, the OPERATING MODE 3, and parts of the OPERATING MODE 4. In a preferred embodiment, the loop filter 315 operates in the normal operating mode during parts of the OPERATING MODE 4. In a preferred embodiment, the loop filter 315 preferably operates in normal operating mode and provides noise shaping for the sensor 205 during sigma-delta operation (OPERATING MODE 4). The loop filter 315 may provide noise shaping to the sensor 205 using any number of methods suitable for providing noise shaping to a measurement device, such as, for example, n th order 1-bit sigma-delta modulation or n th order multi-bit sigma-delta modulation. In a preferred embodiment, as Ulustrated in FIG. 5, the loop filter 315 provides noise shaping to the sensor 205 by utihzing the output streams supphed by the integrators 505, the derivative controUer 510, and the proportional controUer 515. In a preferred embodiment, the loop filter 315 receives the output Vx of the sense amplifier 405 in the front-end circuit 310 as the input into the loop filter 315. The derivative controller 510 preferably generates a velocity term as the first derivative of the x position of the measurement mass 309 as determined by the output Vx of the sense amplifier 405. The proportional controUer 515 preferably generates a displacement term by applying a proportional constant to the output Vx of the sense amplifier 405. The integrators 505 preferably use the output Vx of the sense amplifier 405 to generate a third, fourth, and fifth integral term for fifth-order noise shaping of the 1-bit quantization noise. The output streams from the integrators 505, the derivative controUer 510, and the proportional controUer 515 are preferably scaled as needed and received by the summer 525. The summer 525 preferably combines the output streams from the integrators 505, the derivative controUer 510, and the proportional controller 515 into a single output stream. During the normal sigma-delta operating mode (OPERATING MODE 4), the output stream from the summer 525 is preferably sent to the comparator 530. The comparator 530 preferably converts the output stream from the summer 525 into an output stream IMOD from the loop filter 315. In a preferred embodiment, the output IMOD from the loop filter 315 is a sigma-delta modulated 1-bit signal representing the external acceleration forces on the sensor 205, excluding the approximately 1-g static field. In a preferred embodiment, the output IMOD from the loop filter 315 equals, on the average, either zero or one. In another preferred embodiment, the loop filter 315 preferably operates in reduced-order mode and provides feedback loop compensation for the sensor 205 during the OPERATING MODE 1, the OPERATING MODE 2, and the OPERATING MODE 3, and noise shaping during parts of the OPERATING MODE 4. The loop filter 315 may provide feedback loop control or noise shaping to the sensor 205 using any number of methods of providing feedback loop control or noise shaping to a sensor. The loop filter 315 preferably provides feedback loop control to the sensor 205 by operating in the reduced-order mode. In a preferred embodiment, as Ulustrated in FIG. 42, the loop filter 315 operates in reduced-order mode by holding the integrators 505 in reset and utihzing the output streams supphed by the derivative controUer 510 and the proportional controUer 515. In a preferred embodiment, the loop filter 315 receives the output Vx of the sense amplifier 405 in the front-end circuit 310 as the input into the loop filter 315. The derivative controUer 510 preferably generates a velocity term as the first derivative of the x position of the measurement mass 309 as determined by the output Vx of the sense amplifier 405. The proportional controller 515 preferably generates a displacement term by applying a proportional constant to the output Vx of the sense amphfier 405. The output streams from the derivative controller 510 and the proportional controller 515 are preferably scaled as needed and received by the summer 525. The summer 525 preferably combines the output streams from the derivative controller 510 and the proportional controller 515 into a single output stream. During the OPERATING MODE 1, the OPERATING MODE 2, and the OPERATING MODE 3, the output stream from the summer 525 is preferably sent to the buffer 535. The buffer 535 preferably converts the output stream from the summer 525 into an output stream Vsum from the buffer 535. In a preferred embodiment, the output Vsum from the buffer 535 is apphed to the plated 306 and 307 during the GRAVITY CANCELLATION STATE. In a preferred embodiment, the loop filter 315 operates in the reduced- order mode whUe the system 100 switches from a system 100 start-up operating mode to the system 100 sigma-delta operating mode. In a preferred embodiment, the loop filter 315 further operates in the reduced-order mode for a predetermined amount of time after the system 100 switches into sigma-delta operating mode. The reduced-order loop filter 315 may, for example, reduce spurious instabilities that occur during the transition of the system 100 from the start-up operating mode to the sigma-delta operating mode. Referring to FIG. 43, a method 4300 of providing control to the sensor system 100 wUl now be described. In a preferred embodiment, as Ulustrated in FIG. 43, the method 4300 of providing control to the sensor system 100 includes: determining the mode of operation of the sensor system 100 in step 4305, adjusting the mode of operation of the loop filter 315 in step 4310, providing feedback loop compensation to the sensor system 100 during the OPERATING MODE 1, the OPERATING MODE 2, the OPERATING MODE 3, and parts of the OPERATING MODE 4 in step 4315, and providing noise shaping to the sensor system 100 during parts of the OPERATING MODE 4 in step 4320. In a preferred embodiment, in step 4305 the mode of operation of the sensor system 100 is determined. The system 100 may, for example, operate in a start-up mode (the OPERATING MODE 1, the OPERATING MODE 2, and the OPERATING MODE 3) or in a normal sigma-delta mode (the OPERATING MODE 4). In a preferred embodiment, the startup sequencer 325 is used to determine the operating mode of the sensor system 100. The startup sequencer 325 may determine the operating state of the system 100 using any number of methods suitable for determining the operating mode of the system 100. In a preferred embodiment, the startup sequencer 325 determines the operating state of the system 100 by using a state machine implemented in digital logic. In a preferred embodiment, in step 4310 the startup sequencer 325 adjusts the mode of operation of the loop filter 315. The startup sequencer 325 may, for example, place the loop filter 315 in a reduced-order mode or allow the loop filter 315 to operate in normal operating mode. When the start-up sequencer 325 detects that the system 100 is in the OPERATING MODE 1, the OPERATING MODE 2, or the OPERATING MODE 3, the start-up sequencer 325 preferably sends a signal to the loop filter 315 that holds the integrators 505 within the loop filter 315 in reset and places the loop filter 315 in reduced-order mode. The startup sequencer 325 may, for example, also signal the loop filter 315 to operate in the reduced-order mode when the system 100 is in normal sigma- delta mode during the OPERATING MODE 4. The loop filter 315 preferably holds the integrators 505 in reset when the loop filter 315 operates in the reduced-order mode. The integrators 505 are typicaUy a source of instability within the system 100 because the integrators 505 tend to overload when the input into the system 100 exceeds a system 100 limit. By holding the integrators 505 in reset, the loop filter 315 preferably provides additional stability to the system 100 by eliminating a potential source of instability. Therefore, the loop filter 315 preferably operates in reduced-order mode whUe the system 100 operates in sigma-delta mode during the OPERATING MODE 4 to help the system 100 recover from an unexpected system 100 overload. In another preferred embodiment, the loop filter 315 operates in reduced-order mode whUe the system 100 is operating in sigma-delta mode during OPERATING MODE 4 to prevent instability within the system 100 when high input levels into the system 100 are expected. The start-up sequencer 325 aUows the loop filter 315 to operate in the normal operating mode when the start-up sequencer 325 detects that the system 100 is operating in normal sigma-delta mode during the OPERATING MODE 4 without high input levels or system 100 overloading. When the start-up sequencer 325 stops sending the signal to the loop filter 315, the loop filter 315 preferably takes the integrators 505 out of reset and operates in the normal operating mode. In a preferred embodiment, in step 4315 feedback loop compensation is provided to the system 100. The feedback loop compensation may be provided using any number of methods suitable for supplying feedback loop compensation to the system 100. In a preferred embodiment, the feedback loop compensation is provided by the loop filter 315 when the loop filter 315 operates in the reduced- order mode. In a preferred embodiment, the startup sequencer 325 holds the integrators 505 in reset during the reduced-order operating mode, and the loop filter 315 provides feedback loop compensation to the system 100. In a preferred embodiment, in step 4320 noise shaping is provided to the system 100. The noise shaping is preferably provided when the system 100 is operating in normal sigma-delta mode. The noise shaping may be provided using any number of methods of providing noise shaping to the system 100. In a preferred embodiment, the noise shaping is provided by the loop filter 315, which operates in normal operating mode when the system 100 operates in normal sigma-delta mode during the OPERATING MODE 4. In another preferred embodiment, the noise shaping is provided by the loop filter 315, which operates in reduced-order mode when the system 100 operates in normal sigma-delta mode during the OPERATING MODE 4. In a preferred embodiment, the loop filter 315 utUizes the integrators 505, the derivative controUer 510, and the proportional controUer 515 to supply noise shaping to the system 100. Referring to FIGS. 44, 45a, 45b, 45c, 45d, 45e, 46, 47, 48, 49, and 50, a preferred embodiment of the operation of the multiphase clock generator 320 in the controller 206 wUl now be described. The multiphase clock generator 320 preferably provides clock signals that are used to control the switches phsul, phsu2, phul, phu2, phdl, phd2, phgl, phtc, phbc, phg2, phsg, phs, phf, phloop, phsim, phxbuf, phz, and pha in the front-end circuit 310. In a preferred embodiment, as Ulustrated in FIG. 44, the multiphase clock generator 320 includes a digital signal generator 4403, a clock resynchronization circuit 4405, a communication interface 4410, and a substrate 4415. The digital signal generator 4403 preferably generates original clock signals. In a preferred embodiment, the digital signal generator 4403 is positioned on the substrate 4415. The digital signal generator 4403 is preferably operably coupled to the clock resynchronization circuit 4405 by the communication interface 4410. The digital signal generator 4403 may include any number of conventional commercially avaUable signal generators suitable for generating clock signals for the sensor system 100 such as, for example, a state machine, a mux decoder, or a digital decoder. In a preferred embodiment, the digital signal generator 4403 is a state machine. In a preferred embodiment, the clock resynchronization circuit 4405 resamples the clock signals generated by the digital signal generator 4403 using a delayed clock reference for the front-end circuit 310. The clock resynchronization circuit 4405 is preferably positioned on the substrate 4415. In a preferred embodiment, the clock resynchronization circuit 4405 is operably coupled to the digital signal generator 4403 by the communication interface 4410. The clock resynchronization circuit 4405 may include any number of circuits suitable for resampling the clock signals used to control the switches phsul, phsu2, phul, phu2, phdl, phd2, phgl, phtc, phbc, phg2, phsg, phs, phf, phloop, phsim, phxbuf, phz, and pha in the front-end circuit 310. In a preferred embodiment, as Ulustrated in FIGS. 45a, 45b, 45c, 45d, and 45e, the clock resynchronization circuit 4405 includes a signal generator 4520, inverters 4510a, 4510b, 4510c, 4510d, 4510e, 4510f, 4510g, 4510h, 4510i, 4510j, 4510k, 45101, 4510m, 4510n, 4510o, 4510p, 4510q, 4510r, 4510s, 4510t, 4510u, 4510v, 4510w, 4510x, 4510y, 4510z, 4510aa, 4510bb, 4510cc, 4510dd, 4510ee, 4510ff, 4510gg, 4510hh, 4510U, 4510jj, 4510kk, 4510U, 4510mm, 4510nn, 4510oo, 4510pp, 4510qq, and 4510rr, NAND Gates 4515a, 4515b, 4515c, 4515d, 4515e, 4515f, 4515g, and 4515h, NOR Gates 4525a, 4525c, 4525d, 4525e, 4525f, 4525g, 4525h, 4525i, 4525j, 4525k, 45251, 4525m, 4525n, 4525o, 4525p, 4525q, 4525r, 4525s, 4525t, 4525u, 4525v, 4525x, 4525y, 4525z, 4525aa, 4525bb, 4525cc, 4525dd, and 4525ee, XNOR gates 4525b and 4525w, asynchronous reset double edge flip-flops 4530a, 4530b, 4530c, 4530d, 4530e, 4530f, 4530g, and 4530h, and asynchronous set double edge flip-flops 4535a, 4535b, 4535c, 4535d, 4535e, 4535f, 4535g, 4535h, and 4535i. The signal generator 4520 preferably receives one or more input signals and generates an output signal signal_out for use in the clock resynchronization circuit 4405. The signal generator 4520 may include any number of signal generators suitable for use in the clock resynchronization circuit 4405. In a preferred embodiment, the signal generator 4520 is a comphmentary metal oxide semiconductor (CMOS). The inverters 4510a, 4510b, 4510c, 4510d, 4510e, 4510f, 4510g, 4510h, 4510i, 4510j, 4510k, 45101, 4510m, 4510n, 4510o, 4510p, 4510q, 4510r, 4510s, 4510t, 4510u, 4510v, 4510w, 4510x, 4510y, 4510z, 4510aa, 4510bb, 4510cc, 4510dd, 4510ee, 4510ff, 4510gg, 4510hh, 4510ii, 4510jj, 4510kk, 451011, 4510mm, 4510nn, 4510oo, 4510pp, 4510qq, and 4510rr are preferably used to achieve an appropriate drive strength for different switch loads and metal trace loads on the substrate 4415. The inverters 4510a, 4510b, 4510c, 4510d, 4510e, 4510f, 4510g, 4510h, 4510i, 4510j, 4510k, 45101, 4510m, 4510n, 4510o, 4510p, 4510q, 4510r, 4510s, 4510t, 4510u, 4510v, 4510w, 4510x, 4510y, 4510z, 4510aa, 4510bb, 4510cc, 4510dd, 4510ee, 4510ff, 4510gg, 4510hh, 4510ii, 4510jj, 4510kk, 4510U, 4510mm, 4510nn, 4510oo, 4510pp, 4510qq, and 4510rr may be any number of conventional commercially avaUable inverters suitable for use in the clock resynchronization circuit 4405. In a preferred embodiment, the inverters 4510a, 4510b, 4510c, 4510d, 4510e, 4510f, 4510g, 4510h, 4510i, 4510j, 4510k, 45101, 4510m, 4510n, 4510o, 4510p, 4510q, 4510r, 4510s, 4510t, 4510u, 4510v, 4510w, 4510x, 4510y, 4510z, 4510aa, 4510bb, 4510cc, 4510dd, 4510ee, 4510ff, 4510gg, 4510hh, 4510U, 4510jj, 4510kk, 4510U, 4510mm, 4510nn, 4510oo, 4510pp, 4510qq, and 4510rr are CMOS. The NAND Gates 4515a, 4515b, 4515c, 4515d, 4515e, 4515f, 4515g, and 4515h are preferably used to perform a required digital functionahty within the clock resynchronization circuit 4405. The NAND Gates 4515a, 4515b, 4515c, 4515d, 4515e, 4515f, 4515g, and 4515h may be any number of conventional commercially avaUable NAND gates suitable for use in the clock resynchronization circuit 4405. In a preferred embodiment, the NAND Gates 4515a, 4515b, 4515c, 4515d, 4515e, 4515f, 4515g, and 4515h are CMOS. The NOR Gates 4525a, 4525c, 4525d, 4525e, 4525f, 4525g, 4525h, 4525i, 4525j, 4525k, 45251, 4525m, 4525n, 4525o, 4525p, 4525q, 4525r, 4525s, 4525t, 4525u, 4525v, 4525x, 4525y, 4525z, 4525aa, 4525bb, 4525cc, 4525dd, and 4525ee are preferably used to perform a required digital functionahty within the clock resynchronization circuit 4405. The NOR Gates 4525a, 4525c, 4525d, 4525e, 4525f, 4525g, 4525h, 4525i, 4525j, 4525k, 45251, 4525m, 4525n, 4525o, 4525p, 4525q, 4525r, 4525s, 4525t, 4525u, 4525v, 4525x, 4525y, 4525z, 4525aa, 4525bb, 4525cc, 4525dd, and 4525ee may be any number of conventional commerciaUy avaUable NOR gates suitable for use in the clock resynchronization circuit 4405. In a preferred embodiment, the NOR Gates 4525a, 4525c, 4525d, 4525e, 4525f, 4525g, 4525h, 4525i, 4525j, 4525k, 45251, 4525m, 4525n, 4525o, 4525p, 4525q, 4525r, 4525s, 4525t, 4525u, 4525v, 4525x, 4525y, 4525z, 4525aa, 4525bb, 4525cc, 4525dd, and 4525ee are CMOS. The XNOR Gates 4525b and 4525w are preferably used to perform a required digital functionahty within the clock resynchronization circuit 4405. The XNOR Gates 4525b and 4525w may be any number of conventional commerciaUy avaUable XNOR gates suitable for use in the clock resynchronization circuit 4405. In a preferred embodiment, the XNOR Gates 4525b and 4525w are CMOS. The asynchronous set double edge flip-flops 4535a, 4535b, 4535c, 4535d, 4535e, 4535f, 4535g, 4535h, and 4535i are preferably D flip-flops that pass data on both clock edges with asynchronous set inputs. In a preferred embodiment, the asynchronous set double edge flip-flops 4535a, 4535b, 4535c, 4535d, 4535e, 4535f, 4535g, 4535h, and 4535i are used to resample clock signals. The asynchronous set double edge flip-flops 4535a, 4535b, 4535c, 4535d, 4535e, 4535f, 4535g, 4535h, and 4535i preferably allow the clock resynchronization circuit 4405 to clock data through the circuit 4405 at approximately twice the speed of a conventional single-edge flip-flop. In a preferred embodiment, as Ulustrated in FIG. 46, the asynchronous set double edge flip-flops 4535a, 4535b, 4535c, 4535d, 4535e, 4535f, 4535g, 4535h, and 4535i include inverters 4610a, 4610b, 4610c, 4610d, and 4610e, NOR Gates 4615a and 4615b, and transmission gates 4620a, 4620b, 4620c, 4620d, 4620e, and 4620f. The inverters 4610a, 4610b, 4610c, 4610d, and 4610e may be any number of inverters suitable for use in the asynchronous set double edge flip-flops 4535a, 4535b, 4535c, 4535d, 4535e, 4535f, 4535g, 4535h, and 4535L In a preferred embodiment, the inverters 4610a, 4610b, 4610c, 4610d, and 4610e are CMOS. The NOR gates 4615a and 4615b may be any number of NOR gates suitable for use in the asynchronous set double edge flip-flops 4535a, 4535b, 4535c, 4535d, 4535e, 4535f, 4535g, 4535h, and 4535i. In a preferred embodiment, the NOR gates 4615a and 4615b are CMOS. The transmission gates 4620a, 4620b, 4620c, 4620d, 4620e, and 4620f may be any number of transmission gates suitable for use in the asynchronous set double edge flip-flops 4535a, 4535b, 4535c, 4535d, 4535e, 4535f, 4535g, 4535h, and 4535L In a preferred embodiment, the transmission gates 4620a, 4620b, 4620c, 4620d, 4620e, and 4620f are CMOS. The asynchronous reset double edge flip-flops 4530a, 4530b, 4530c, 4530d, 4530e, 4530f, 4530g, and 4530h are preferably D flip-flops that pass data on both clock edges with asynchronous reset inputs. In a preferred embodiment, the asynchronous reset double edge flip-flops 4530a, 4530b, 4530c, 4530d, 4530e, 4530f, 4530g, and 4530h are used to resample clock signals. The asynchronous reset double edge flip-flops 4530a, 4530b, 4530c, 4530d, 4530e, 4530f, 4530g, and 4530h preferably aUow the clock resynchronization circuit 4405 to clock data through the circuit at approximately twice the speed of a normal single-edge flip- flop. In a preferred embodiment, as Ulustrated in FIG. 47, the asynchronous reset double edge flip-flops 4530a, 4530b, 4530c, 4530d, 4530e, 4530f, 4530g, and 4530h include inverters 4710a, 4710b, 4710c, 4710d, 4710e, and 4710f, NAND Gates 4715a and 4715b, and transmission gates 4720a, 4720b, 4720c, 4720d, 4720e, and 4720f. The inverters 4710a, 4710b, 4710c, 4710d, 4710e, and 4710f may be any number of inverters suitable for use in the asynchronous reset double edge flip- flops 4530a, 4530b, 4530c, 4530d, 4530e, 4530f, 4530g, and 4530h. In a preferred embodiment, the inverters 4710a, 4710b, 4710c, 4710d, 4710e, and 4710f are CMOS. The NAND Gates 4715a and 4715b may be any number of NAND gates suitable for use in the asynchronous reset double edge flip-flops 4530a, 4530b, 4530c, 4530d, 4530e, 4530f, 4530g, and 4530h. In a preferred embodiment the NAND Gates 4715a and 4715b are CMOS. The transmission gates 4720a, 4720b, 4720c, 4720d, 4720e, and 4720f may be any number of transmission gates suitable for use in the asynchronous reset double edge flip-flops 4530a, 4530b, 4530c, 4530d, 4530e, 4530f, 4530g, and 4530h. In a preferred embodiment, the transmission gates 4720a, 4720b, 4720c, 4720d, 4720e, and 4720f are CMOS. The various components within the clock resynchronization circuit 4405 may interact to perform any number of functions. In a preferred embodiment, the signal generator 4520 receives one or more input signals and generates an output signal signal out for use in the clock resynchronization circuit 4405. The signal generator 4520 may receive any number of input signals. In a preferred embodiment, the input signals into the signal generator 4520 include an input reset signal POR from a power-on reset circuit, an input reset signal reset from a state sequencer, and an input clock signal xclk_fe_rst. The output signal signal_out from the signal generator 4520 is preferably sent to the NOR gate 4525a along with a signal rst rncgb. The signal rst rncgb is preferably a reset signal generated by the multiphase clock generator 320. The NOR gate 4525a preferably processes the input signals signal_out and rst_mcgb to create an output signal resetb advanced. In a preferred embodiment, the output signal resetb advanced is sent to the NAND gates 4515d and 4515h. In another preferred embodiment, the output signal resetb advanced is sent to the inverters 4510o, 4510k, 45101, 4510m, and 4510n. The inverters 4510o, 4510k, 45101, 4510m, and 4510n preferably strengthen the drive capabihty of the output signal resetb_advanced to create an input signal synch_reset for the asynchronous set double edge flip-flops 4535a, 4535b, 4535c, 4535d, 4535e, 4535f, 4535g, 4535h, and 4535i and the asynchronous reset double edge flip-flops 4530a, 4530b, 4530c, 4530d, 4530e, 4530f, 4530g, and 4530h. The input signal synch reset preferably resets the asynchronous reset double edge flip-flops 4530a, 4530b, 4530c, 4530d, 4530e, 4530f, 4530g, and 4530h and sets the asynchronous set double edge flip-flops 4535a, 4535b, 4535c, 4535d, 4535e, 4535f, 4535g, 4535h, and 4535i on a rising edge of the input clock signal xclk fejrst. The input signal synch_reset preferably releases the asynchronous reset double edge flip-flops 4530a, 4530b, 4530c, 4530d, 4530e, 4530f, 4530g, and 4530h and the asynchronous set double edge flip-flops 4535a, 4535b, 4535c, 4535d, 4535e, 4535f, 4535g, 4535h, and 4535i on a falling edge of the input clock signal xclk fe rst. In a preferred embodiment, the NAND gates 4515g and 4515h, the inverters 4510dd, 4510ee, and 4510ff, the asynchronous reset double edge flip- flop 4530g, and the XNOR gate 4525w within the clock resynchronization circuit 4405 interact to generate constant width pulses rise delay and rise delayb. The constant width pulses rise delay and rise_delayb are preferably generated using a clock signal XCLK. The clock signal XCLK may be any number of clock signals suitable for use in the clock resynchronization circuit 4405. In a preferred embodiment, the clock signal XCLK is 2 MHZ clock signal with a 50% duty cycle. The constant width pulses rise_delay and rise_delayb may be any number of constant width pulses suitable for use in the clock resynchronization circuit 4405. The width of the constant width pulses rise delay and rise delayb may be determined by any number of factors that influence the width of constant width pulses. In a preferred embodiment, the widths of the constant width pulses rise delay and rise_delayb are determined by a propagation delay through the asynchronous reset double edge flip-flop 4530g and the NAND gate 4515h. The propagation delay may be increased as needed to increase the width of the constant width pulses rise delay and rise_delayb. In a preferred embodiment, the propagation delay is increased by adding additional delay buffers at an input A of the NAND gate 4515h. The XNOR gate 4525w preferably ensures that the constant width pulse rise delay returns to the previous level after the completion of the propagation delay. During the generation of the constant width pulses rise_delay and rise delayb, a feedback wire rise delay latched is preferably sent back from the NAND gate 4515h to an input B into the NAND gate 4515g and the inverter 4510dd. The feedback wire rise delay latched is preferably used to prepare an input D into the asynchronous reset double edge flip-flop 4530g to receive the next clock edge. The next clock edge may include any number of clock edges suitable for use in the clock resynchronization circuit 4405. In a preferred embodiment, the next clock edge is configured in the opposite direction of the previous clock edge received by the asynchronous reset double edge flip-flop 4530g. In a preferred embodiment, the NAND gates 4515c and 4515d, the inverters 4510p, 4510q, and 4510r, the asynchronous reset double edge flip-flop 4530a, and the XNOR gate 4525b interact to generate constant width delay pulses rise_delay_plus and rise_delayb_plus. The constant width delay pulses rise_delay_plus and rise_delayb_plus are preferably generated using a clock XCLK delayed. The clock XCLK delayed may be any number of clocks suitable for use in the clock resynchronization circuit 4405. In a preferred embodiment, as Ulustrated in FIGS. 48 and 49, the clock XCLK delayed is further delayed from the clock reference XCLK. The extra clock delay may be generated using any method for creating an extra clock delay. In a preferred embodiment, the extra clock delay is generated by feeding the clock signal XCLK through the NAND gates 4515a and 4515b and the inverters 4510a, 4510b, 4510c, 4510d, 4510e, 4510f, 4510g, 4510h, 4510i, and 4510j. The extra clock delay preferably aUows the two sets of constant delayed non-overlapping clocks XCLK and XCLK_delayed to be generated on each clock edge of an input clock. The two sets of constant delayed clocks XCLK and XCLK delayed are preferably used to achieve the clocking scheme utilized in the front-end circuit 310. The constant width pulses rise delay and rise delayb and the constant width delay pulses rise_delay_plus and rise_delayb plus may be utilized for any suitable purpose within the clock resynchronization circuit 4405. In a preferred embodiment, the constant width pulses rise_delay and rise_delayb and the constant width delay pulses rise_delay_plus and rise_delayb_plus are preferably utilized to ensure that the switches within the front-end circuit 310 have adequate time to turn off before additional switches within the front-end circuit 310 are turned on. In a preferred embodiment, the clock resynchronization circuit 4405 further receives input clock signals phadb_in, phsb_in, phsib in, and phzb_in from the multiphase clock generator 4403. The input clock signals phadb in, phsb in, phsib in, and phzb in may be used for any suitable purpose within the clock resynchronization circuit 4405. In a preferred embodiment, the input clock signals phadb in, phsb_in, phsib in, and phzb_in are latched in the double edge flip-flops 4535g, 4535h, 4535i, and 4530h, respectively, on every rising edge and falling edge of the input clock signal XCLK to create latched clock signals phadb latched, phsb latched, phsib_latched, and phzb latched. In a preferred embodiment, the input clock signals phadb_in, phsb in, phsib_in, and phzb in are latched in the double edge flip-flops 4535g, 4535h, 4535i, and 4530h to remove ghtches from the input clock signals phadb in, phsb_in, phsib in, and phzb in. The latched clock signals phadb latched, phsb latched, phsib latched, and phzb latched may be used for any suitable purpose within the clock resynchronization circuit 4405. In a preferred embodiment, the latched clock signals phadb_latched, phsb latched, phsib_latched, and phzb latched provide stable signals for the clock resynchronization circuit 4405. In a preferred embodiment, the latched clock signals phadb_latched, phsb latched, phsib latched, and phzb latched are sent to NOR gate feedback pairs 4525x and 4525y, 4525z and 4525aa, 4525bb and 4525cc, and 4525dd and 4525ee, respectively, along with the constant width pulse rise delayb. The NOR gate feedback pairs 4525x and 4525y, 4525z and 4525aa, 4525bb and 4525cc, and 4525dd and 4525ee, preferably convert the latched input signals phadb_latched, phsb latched, phsib_latched, and phzb latched into signals phad_delayed, phs delayed, phsi delayed, and phz delayed. The signals phad_delayed, phs_delayed, phsi_delayed, and phz delayed are preferably processed within the clock resynchronization circuit 4405 to create the output signals phadb delayed, phsb delayed, phsib_delayed, and phzb delayed. The output signals phadb delayed, phsib delayed, and phzb delayed are preferably used by the clock resynchronization circuit 4405 to control the switches pha, phs, and phz, respectively, in the front-end circuit 310. The NOR gate feedback pairs 4525x and 4525y, 4525z and 4525aa, 4525bb and 4525cc, and 4525dd and 4525ee preferably utihze the constant width pulse rise_delayb to ensure that the output signals phadb delayed, phsib delayed, and phzb_delayed turn off the switches pha, phs, and phz in the front-end circuit 310, if required, before the clock resynchronization circuit 4405 sends one or more signals to turn on switches within the front-end circuit 310. In a preferred embodiment, the latched clock signals phadb_latched, phsb_latched, phsib_latched, and phzb_latched are sent to an input A into the NOR gates 4525y, 4525aa, 4525cc, and 4525ee within the NOR gate feedback pairs 4525x and 4525y, 4525z and 4525aa, 4525bb and 4525cc, and 4525dd and 4525ee, respectively. Additionally, signals inter_nodel2, inter_nodel3, inter_nodel4, and inter nodelδ are preferably sent from an output Y of the NOR gates 4525x, 4525z, 4525bb, and 4525dd to an input B into the NOR gates 4525y, 4525aa, 4525cc, and 4525ee, respectively. The signals inter_nodel2, inter_nodel3, inter_nodel4, and inter nodelδ may be any number of signals suitable for use in the clock resynchronization circuit 4405. The NOR gates 4525y, 4525aa, 4525cc, and 4525ee preferably process the latched clock signals phadb_latched, phsb_latched, phsib latched, and phzb latched along with the signals inter_nodel2, inter_nodel3, inter_nodel4, and inter nodelδ to create the signals phad delayed, phs delayed, phsi delayed, and phz delayed. During the processing of the latched input signals phadb latched, phsb_latched, phsibjatched, and phzb latched, feedback signals 4540a, 4δ40b, 4δ40c, and 4δ40d are preferably sent from the NOR gates 4δ2δy, 4δ2δaa, 4δ2δcc, and 4δ2δee to the NOR gates 4δ2δx, 4δ2δz, 4δ2δbb, and 4δ2δdd, respectively. The feedback signals 4δ40a, 4δ40b, 4540c, and 4540d preferably correspond to the signals phad delayed, phs delayed, phsi_delayed, and phz_delayed. The feedback signals 4δ40a, 4δ40b, 4δ40c, and 4δ40d from the NOR gates 4δ2δy, 4δ2δaa, 4525cc, 4δ2δee to the NOR gates 4δ2δx, 4525z, 452δbb, and 4δ2δdd may be utilized for any suitable purpose within the clock resynchronization circuit 440δ. In a preferred embodiment, the feedback signals 4δ40a, 4δ40b, 4δ40c, and 4δ40d are provided to ensure that switches within the front-end circuit 310 remain unchanged when the current latched input signals phadb_latched, phsb latched, phsib_latched, and phzb_latched to the NOR gates 4δ2δy, 4525aa, 4525cc, and 4δ2δee are the same as the previous latched input signals phadb latched, phsb latched, phsib latched, and phzb latched to the NOR gates 4δ2δy, 4δ2δaa, 4525cc, and 4δ2δee. In a preferred embodiment, the clock resynchronization circuit 440δ further receives input clock signals phdb_in, phub in, ph tcb in, phjbcb in, phgb in, phsub in, phsimin, phxbufb in, phloopb in, phfb in, and phsgb in from the digital signal generator 4403. The input clock signals phdb in, phub in, ph_tcb_in, phbcb in, phgb_in, phsub_in, phsimin, phxbufb_in, phloopb in, phfb_in, and phsgb in may be used for any suitable purpose within the clock resynchronization circuit 440δ. In a preferred embodiment, the input clock signals phdb_in, phub in, ph tcb in, ph_bcb_in, phgb_in, phsub in, phsimin, phxbufb in, phloop in, phfb in, and phsgb in are latched in the double edge flip- flops 4δ3δa, 4δ3δb, 4530b, 4530c, 4δ30d, 4δ3δc, 4δ30e, 4δ3δd, 4δ3δe, 4δ3δf, and 4δ30f, respectively, on every rising edge and falling edge of the clock signal XCLK_delayed to create latched clock signals phdb latched, phub latched, ph tcb latched, phbcb latched, phgb_latched, phsub latched, phsimlatched, phxbufb latched, phloopb latched, phfb_latched, and phsgb latched. The latched clock signals phdb latched, phub latched, ph tcb latched, phbcb latched, phgb_latched, phsub latched, phsimlatched, phxbufb latched, phloopb_latched, phfb latched, and phsgb latched may be used for any suitable purpose within the clock resynchronization circuit 440δ. In a preferred embodiment, the latched signals phdb_latched, phub_latched, ph_tcb_latched, phbcb latched, phgb latched, phsub_latched, phxbufb latched, phloopb_latched, phfb latched, and phsgb_latched are sent to NOR gate feedback pairs 4δ2δc and 4δ2δd, 4δ2δe and 4δ2δf, 4δ2δg and 4δ2δh, 4δ2δi and 4δ2δj, 4δ2δk and 4δ2δl, 4δ2δm and 4525n, 452δo and 4525p, 4δ25q and 4525r, 4δ2δs and 4δ2δt, and 4δ2δu and 4δ2δv, respectively, along with the constant width pulse rise_delayb_plus. The NOR gate feedback pairs 4δ2δc and 4δ2δd, 4δ2δe and 4δ2δf, 4δ2δg and 4δ2δh, 4δ2δi and 4δ2δj, 4δ2δk and 4δ251, 452δm and 4δ25n, 452δo and 4δ2δp, 4δ2δq and 4δ2δr, 4δ2δs and 4δ2δt, and 4δ2δu and 4δ2δv preferably convert the latched input signals phdb_latched, phub latched, ph_tcb_latched, phbcb latched, phgb latched, phsub latched, phxbufb latched, phloopbjatched, phfb latched, and phsgb latched into signals phd delayed, phu delayed, ph tc delayed, ph_bc_delayed, phg delayed, phsu delayed, phxbuf delayed, phloop delayed, phf delayed, and phsg delayed. The signals phd delayed, phu delayed, ph tc delayed, ph bc delayed, phg delayed, phsu delayed, phxbuf delayed, phloop delayed, phf delayed, and phsg_delayed are then preferably processed within the clock resynchronization circuit 440δ to create the output signals phdb delayed, phub delayed, ph tcb delayed, ph bcb delayed, phgb delayed, phsub_delayed, phxbufb delayed, phloopb_delayed, phfb_delayed, and phsgb delayed. The clock resynchronization circuit 440δ preferably uses the output signals phdb delayed, phub delayed, ph tcb delayed, ph bcb delayed, phgb delayed, phsub_delayed, phxbufb_delayed, phloopb_delayed, phfb_delayed, and phsgb_delayed to control the switches phdl and phd2, phul and phu2, phtc, phbc, phgl and phg2, phsul and phsu2, phxbuf, phloop, phf, and phsg, respectively, in the front-end circuit 310. In a preferred embodiment, the latched clock signal phsim latched is sent to a NAND gate feedback pair 4δlδe and 4δlδf along with the constant width delay pulse rise_delay_plus. The NAND gate feedback pair 4δlδe and 4δl5f preferably converts the latched signal phsim latched into the output signal phsim delayed. The output signal phsim_delayed is preferably used by the clock resynchronization circuit 4405 to control the switch phsim in the front-end circuit 310. The NOR gate feedback pairs 452δc and 4δ2δd, 4δ2δe and 4δ2δf, 4δ2δg and 4δ2δh, 4δ25i and 452δj, 4δ2δk and 4δ2δl, 4δ2δm and 4δ2δn, 4δ2δo and 4δ2δp, 4δ2δq and 4δ2δr, 4δ2δs and 4525t, and 4δ25u and 4525v, preferably utUize the constant width pulse rise_delayb_plus to ensure that the output signals phdb_delayed, phub_delayed, ph_tcb_delayed, ph_bcb_delayed, phgb delayed, phsub delayed, phxbufb_delayed, phloopb delayed, phfb delayed, and phsgb delayed turn off the relevant switches in the front-end circuit 310 before the clock resynchronization circuit 4405 sends a signal to turn on relevant switches within the front-end circuit 310. The NAND gate feedback pair 4δlδe and 4δlδf preferably utUizes the constant width delay pulse rise_delay_plus to ensure that the output signal phsim_delayed turns off the relevant switch in the front-end circuit 310 before the clock resynchronization circuit 440δ sends a signal to turn on other relevant switches within the front-end circuit 310. In a preferred embodiment, the latched clock signals phdb latched, phub_latched, ph tcbjatched, phjbcb latched, phgb latched, phsub latched, phxbufb_latched, phloopb_latched, phfb latched, and phsgbjatched are sent to an input A into the NOR gates 4δ2δd, 4δ2δf, 4δ2δh, 4δ2δj, 4δ2δl, 4δ2δn, 4δ2δp, 4δ2δr, 4δ2δt, and 4δ2δv within the NOR gate feedback pairs 4δ2δc and 4δ2δd, 4δ2δe and 4δ2δf, 4δ2δg and 4δ2δh, 4δ2δi and 4δ2δj, 4δ2δk and 46251, 452δm and 4δ2δn, 4δ2δo and 4δ2δp, 4δ2δq and 4δ2δr, 4δ2δs and 4δ2δt, and 4δ2δu and 4δ2δv, respectively. AdditionaUy, signals inter nodel, inter_node2, inter_node3, inter_node4, inter nodeδ, inter_node6, inter nodeδ, inter_node9, inter nodelO, and inter nodell are preferably sent from an output Y of the NOR gates 4δ2δc, 4δ2δe, 4δ2δg, 4δ2δi, 4δ25k, 452δm, 4δ2δo, 4δ2δq, 4δ2δs, and 4δ2δu to an input B into the NOR gates 4δ2δd, 4525f, 4δ2δh, 4δ2δj, 45251, 452δn, 4δ2δp, 4δ2δr, 4δ2δt, and 4δ2δv, respectively. The signals inter_nodel, inter_node2, inter_node3, inter_node4, inter nodeδ, inter_node6, inter nodeδ, inter nodeθ, inter nodelO, and inter_nodell may be any number of signals suitable for use in the clock resynchronization circuit 440δ. The NOR gates 4δ2δd, 4δ2δf, 4δ2δh, 4δ2δj, 4δ2δl, 4δ2δn, 4δ2δp, 4δ25r, 452δt, and 4δ2δv preferably process the latched clock signals phdb_latched, phub_latched, ph tcbjatched, ph_bcb_latched, phgb_latched, phsub latched, phxbufb latched, phloopb_latched, phfb_latched, and phsgb latched along with the signals inter_nodel, inter_node2, inter_node3, inter_node4, inter_nodeδ, inter nodeθ, inter_node8, inter_node9, inter nodelO, and inter_nodell, respectively, to create the signals phd_delayed, phu_delayed, ph tc delayed, phj c delayed, phg delayed, phsu_delayed, phxbuf delayed, phloop delayed, phf_delayed, and phsg delayed. During the processing of the latched input signals phdbj-atched, phub latched, ph_tcb_latched, phjbcb latched, phgb latched, phsub latched, phsim_latched, phxbufb_latched, phloopb latched, phfb latched, and phsgbjatched, feedback signals 4δ40e, 4δ40f, 4540g, 4540h, 4δ40i, 4540j, 4540k, 4δ401, 4540m, and 4540n are preferably sent from the NOR gates 4525d, 4δ2δf, 4δ2δh, 4δ2δj, 4δ2δl, 4δ25n, 452δp, 4δ2δr, 4δ2δt, and 4525v, to the NOR gates 4δ25c, 452δe, 4δ2δg, 4δ2δi, 4δ2δk, 4δ25m, 452δo, 4δ2δq, 4δ2δs, and 4δ25u, respectively. The feedback signals 4540e, 4δ40f, 4δ40g, 4δ40h, 4δ40i, 4δ40j, 4δ40k, 4δ401, 4δ40m, and 4540n preferably correspond to the signals phd delayed, phu delayed, ph tc delayed, phjbc delayed, phg delayed, phsu delayed, phxbuf delayed, phloop_delayed, phf delayed, and phsg delayed, respectively. The feedback signals 4540e, 4δ40f, 4δ40g, 4δ40h, 4δ40i, 4δ40j, 4δ40k, 45401, 4540m, and 4δ40n from the NOR gates 4δ2δd, 4δ2δf, 4δ2δh, 4δ2δj, 4δ251, 452δn, 4δ2δp, 4δ2δr, 4δ2δt, and 4δ2δv, to the NOR gates 4δ2δc, 4δ25e, 4525g, 4525i, 4δ2δk, 4δ2δm, 4δ2δo, 4δ2δq, 4δ2δs, and 4δ2δu may be utilized for any suitable purpose within the clock resynchronization circuit 440δ. In a preferred embodiment, the feedback signals 4δ40e, 4δ40f, 4δ40g, 4δ40h, 4δ40i, 4δ40j, 4δ40k, 4δ401, 4δ40m, and 4δ40n are provided to ensure that switches within the front-end circuit 310 remain unchanged when the current latched input signals phdb latched, phub latched, ph tcb latched, ph icb Jatched, phgb latched, phsub_latched, phxbufb latched, phloopb latched, phfb latched, and phsgbjatched to the NOR gates 4δ2δd, 4δ2δf, 4δ2δh, 4δ2δj, 4δ2δl, 4δ2δn, 4δ25p, 452δr, 4525t, and 4δ2δv are the same as the previous latched input signals phdbjatched, phub latched, ph tcb latched, ph bcbjatched, phgb latched, phsub latched, phxbufbjatched, phloopb latched, phfb latched, and phsgbjatched to the NOR gates 4δ2δd, 4δ2δf, 4δ2δh, 4δ2δj, 4δ2δl, 4δ2δn, 4δ2δp, 4δ2δr, 4δ2δt, and 4δ2δv. In a preferred embodiment, the latched clock signal phsim Jatched is sent to an input A into the NAND gate 4δlδf within the NAND gate feedback pair 4515e and 4δlδf. Additionally, a signal inter_node7 is preferably sent from an output Y of the NAND gate 4δlδe to an input B into the NAND gate 4515f. The signal inter_node7 may be any number of signals suitable for use in the clock resynchronization circuit 4405. The NAND gate 45 lδf preferably processes the latched clock signal phsim latched along with the signal inter_node7 to create the output signal phsim_delayed. During the processing of the latched input signal phsim Jatched, a feedback signal 4δ40o is preferably sent from the NAND gate 4δlδf to the NAND gate 4δlδe. The feedback signal 4δ40o preferably corresponds to the signal phsim delayed. The feedback signal 4δ40o from the NAND gate 4δlδf to the NAND gate 4515e may be utilized for any suitable purpose within the clock resynchronization circuit 440δ. In a preferred embodiment, the feedback signal 4δ40o is provided to ensure that the switch phsim within the front-end circuit 310 remains unchanged when the current latched input signal phsim latched to the NAND gate 4δl5f is the same as the previous latched input signal phsim Jatched to the NAND gate 451δf. The asynchronous set double edge flip-flops 4δ3δa, 4δ3δb, 4δ3δc, 4δ3δd, 4δ3δe, 4δ3δf, 4δ3δg, 4δ3δh, and 4δ3δi may process input signals using any method suitable for processing input signals. In a preferred embodiment, the operation of the asynchronous set double edge flip-flops 4δ3δa, 4δ3δb, 4δ3δc, 4δ35d, 453δe, 4δ3δf, 4δ3δg, 4δ3δh, and 4δ3δi is dependent on the level of the input clock signal CLK. When the input clock CLK is set high, the transmission gates 4620a, 4620e, and 4620f are preferably turned off whUe the transmission gates 4620b, 4620c, and 4620d are preferably turned on. The inverter 4610a and the transmission gate 4620b preferably provide local feedback for the NOR gate 461δa. When a set input S and the input clock signal CLK into the asynchronous set double edge flip-flops 453δa, 4δ3δb, 4δ3δc, 4535d, 453δe, 4δ3δf, 4δ3δg, 4δ3δh, and 4δ3δi are set high, the feedback from the transmission gate 4620b to the NOR gate 461δa preferably provides an input B into the NOR gate 461δa. The set input S may be any number of inputs suitable for use in the asynchronous set double edge flip-flops 4δ3δa, 4δ3δb, 4δ3δc, 4δ3δd, 4δ3δe, 4δ3δf, 4δ3δg, 4δ3δh, and 4δ3δi. In a preferred embodiment, the set input S is the input signal synch_reset. In a preferred embodiment, the set input S provides the input B to match an input A into the NOR gate 461δa. When the set input S is low and the input clock signal CLK is low, the feedback from the transmission gate 4620b preferably reinforces an input D into the NOR gate 461δa after the rising edge of the clock input CLK. The inputs D into the asynchronous set double edge flip-flops 4δ3δa, 4δ3δb, 4δ3δc, 4δ3δd, 4δ3δe, 4δ3δf, 4δ3δg, 4δ3δh, and 4δ3δi preferably correspond to the input signals phdbjn, phub in, phsub in, phxbufb in, phloopbjn, phfb_in, phadb in, phsb in, and phsib in, respectively. On the rising edge of the clock input CLK, the transmission gates 4620a, 4620f, and 4620e preferably turn off at substantially the same time that transmission gates 4620b, 4620c, and 4620d turn on. As a result, the input D into the asynchronous set double edge flip-flops 4δ3δa, 4δ3δb, 4δ3δc, 4δ3δd, 4δ3δe, 4δ3δf, 4δ35g, 453δh, and 4δ3δi is preferably disconnected from the NOR gate 461δa input B at substantiaUy the same time that the inverter 4610a output Y is connected to the input B. In this embodiment, the NOR gate 461δa, the inverter 4610a, and the transmission gates 4620a and 4620b preferably form a level-sensitive latch J. The input B into the NOR gate 461δa within the level- sensitive latch J is preferably provided as a feedback stream from the inverter 4610a and the transmission gate 4620b when the input clock signal CLK is high. The output Y from the inverter 4610a may be used for any suitable purpose within the asynchronous set double edge flip-flops 4535a, 453δb, 4δ3δc, 4535d, 4δ3δe, 4δ3δf, 4δ3δg, 4δ3δh, and 4δ3δi. In a preferred embodiment, the output Y from the inverter 4610a reinforces the set input S into the double edge flip-flop 4δ3δa when the input S is high. In another preferred embodiment, the output Y from the inverter 4610a reinforces the input D into the double edge flip-flop 4δ3δa when the set input S is low. The output from the level-sensitive latch J is preferably passed through the transmission gate 4620c when the input clock signal CLK is high, and is provided to the input A to the inverter 4610b. The inverter 4610b preferably converts the output from the level-sensitive latch J into the output Q. The output Q is preferably held substantiaUy constant until the next clock edge of the clock input CLK. On the falling edge of the clock signal CLK, the transmission gate 4620d preferably turns off, disconnecting the input D into the asynchronous set double edge flip-flops 4δ3δa, 4535b, 453δc, 4δ3δd, 4δ3δe, 4δ35f, 453δg, 4δ3δh, and 4δ3δi from the input B into the NOR gate 461δb. The transmission gate 4620c preferably turns off, disconnecting the NOR gate 461δa in the level-sensitive latch J from driving the output Q. The transmission gates 4620e and 4620f preferably turn on. In a preferred embodiment, the NOR gate 461δb, the inverter 4610c, and the transmission gates 4620d and 4620e work together to act as a second level-sensitive latch K in parallel with the level-sensitive latch J. The latch K preferably works on an inverted version of the clock signal CLK on which latch J works. The output from the level-sensitive latch K is preferably passed through the transmission gate 4620f when the input clock signal CLK is low, and is provided to the input A to the inverter 4610b. The inverter 4610b preferably converts the output from the level-sensitive latch K into the output Q. The output Q is preferably held substantially constant until the next clock edge of the clock input CLK. The input D into the asynchronous set double edge flip-flops 4δ3δa, 4δ3δb, 4δ3δc, 4δ3δd, 4δ35e, 453δf, 4δ3δg, 4δ3δh, and 4δ3δi preferably translates to the output Q on every edge of the clock input CLK when the set input S is low. The outputs Q from the asynchronous set double edge flip-flops 4δ3δa, 4δ3δb, 4535c, 453δd, 4δ3δe, 4δ3δf, 4δ35g, 4535h, and 453δi preferably correspond to the latched signals phdb Jatched, phub latched, phsub Jatched, phxbufb latched, phloopb latched, phfb latched, phadb latched, phsb latched, and phsib Jatched, respectively. The asynchronous reset double edge flip-flops 4δ30a, 4535b, 4530c, 4δ30d, 4530e, 4530f, 4δ30g, and 4δ30h preferably receive reset inputs R and digital data inputs D, and provide digital data outputs Q. The reset inputs R may be any number of inputs suitable for use in the asynchronous reset double edge fhp-flops 4δ30a, 4δ30b, 4δ30c, 4δ30d, 4δ30e, 4δ30f, 4δ30g, and 4δ30h. In a preferred embodiment, the reset input R is the input signal synch reset. The digital data inputs D may be any number of inputs suitable for use in the asynchronous reset double edge flip-flops 4δ30b, 4δ30c, 4δ30d, 4δ30e, 4δ30f, and 4δ30h. In a preferred embodiment, the digital data inputs D into the asynchronous reset double edge flip-flops 4δ30b, 4δ30c, 4δ30d, 4δ30e, 4δ30f, and 4δ30h correspond to the input signals ph tcb in, ph bcb in, phgb in, phsim in, phsgb_in, and phzb in, respectively. The asynchronous reset double edge flip-flops 4δ30a, 4δ30b, 4δ30c, 4δ30d, 4δ30e, 4δ30f, 4530g, and 4530h may process the input signals D and R using any method suitable for processing input signals in a double-edge flip-flop. In a preferred embodiment, the operation of the asynchronous reset double edge flip-flops 4δ30a, 4δ30b, 4δ30c, 4δ30d, 4δ30e, 4δ30f, 4δ30g, and 4δ30h is dependent on the level of the input clock signal CLK. The inverter 4710a and the transmission gate 4720b preferably provide local feedback for the NAND gate 471δa. When the reset input R and the input clock signal CLK are high, the feedback from the transmission gate 4720b to the NAND gate 471δa preferably provides an input B into the NAND gate 471δa. In a preferred embodiment, the reset input R provides the input B to match an input A into the NAND gate 471δa. When the reset input R is low and the input clock signal CLK is low, the feedback from the transmission gate 4720b preferably reinforces the input D into the NAND gate 4715a after the rising edge of the clock input CLK. On the rising edge of the clock input CLK, the transmission gates 4720a, 4720f, and 4720e preferably turn off at substantially the same time that transmission gates 4720b, 4720c, and 4720d turn on. As a result, the input D into the asynchronous reset double edge flip-flop 4530a is preferably disconnected from the NAND gate 471δa input B at substantially the same time that the inverter 4710a output Y is connected to the input B. In this embodiment, the NAND gate 471δa, the inverter 4710a, and the transmission gates 4720a and 4720b preferably form a level-sensitive latch L. The input B into the NAND gate 471δa within the level-sensitive latch L is preferably provided as a feedback stream from the inverter 4710a and the transmission gate 4720b when the input clock signal CLK is high. The output Y from the inverter 4710a may be used for any suitable purpose within the asynchronous reset double edge flip-flops 4530a, 4530b, 4530c, 4530d, 4δ30e, 4δ30f, 4δ30g, and 4δ30h. In a preferred embodiment, the output Y from the inverter 4710a reinforces the reset input R into the asynchronous reset double edge flip-flop 4δ3δa when the input R is high. In another preferred embodiment, the output Y from the inverter 4710a reinforces the input D into the asynchronous reset double edge flip-flop 4δ30a when the reset input R is low. The output from the level-sensitive latch L is preferably passed through the transmission gate 4720c when the input clock signal CLK is high, and is provided to the input A to the inverter 4710b. The inverter 4710b preferably converts the output from the level-sensitive latch L into the output Q. The output Q is preferably held substantiaUy constant until the next clock edge of the clock input CLK. On the falling edge of the clock signal CLK, the transmission gate 4720d preferably turns off, disconnecting the input D into the asynchronous reset double-edge flip-flop 4δ30a from the input B into the NAND gate 471δb. The transmission gate 4720c preferably turns off, disconnecting the NAND gate 471δa in the level-sensitive latch L from driving the output Q. The transmission gates 4720e and 4720f preferably turn on. In a preferred embodiment, the NAND gate 471δb, the inverter 4710c, and the transmission gates 4720d and 4720e work together to act as a second level-sensitive latch M in parallel with the level-sensitive latch L. The latch M preferably works on an inverted version of the clock signal CLK on which latch L works. The output from the level- sensitive latch M is preferably passed through the transmission gate 4720f when the input clock signal CLK is low, and is provided to the input A to the inverter 4710b. The inverter 4710b preferably converts the output from the level- sensitive latch M into the output Q. The output Q is preferably held substantially constant until the next clock edge of the clock input CLK. The input D into the asynchronous reset double edge flip-flops 4δ30a, 4δ30b, 4δ30c, 4530d, 4530e, 4δ30f, 4δ30g, and 4δ30h preferably translates to the output Q on every edge of the clock input CLK when the reset input R is low. In a preferred embodiment, the outputs Q from the asynchronous reset double edge flip-flops 4δ30b, 4δ30c, 4δ30d, 4δ30e, 4δ30f, and 4δ30h correspond to the latched signals ph tcb Jatched, ph bcb latched, phgb latched, phsim latched, phsgbjatched, and phzb latched, respectively. The communication interface 4410 preferably operably couples the clock resynchronization circuit 440δ and the digital signal generator 4403. The communication interface 4410 may include any number of conventional commercially available communication interfaces suitable for transmitting the clock signals from the digital signal generator 4403 to the clock resynchronization circuit 4406. In a preferred embodiment, the communication interface includes a plurahty of metal traces running across the substrate 4416. The substrate 4415 may include any number of conventional commerciaUy avaUable materials suitable for forming a substrate from which the clock resynchronization circuit 4405 and the digital signal generator 4403 may be fabricated. In a preferred embodiment, the substrate 441δ is a silicon p-type substrate. For circuits with time-division multiplexing of analog signals, the duty cycle of each signal preferably must be fixed whUe stiU providing the non-overlap of signal sources. The conventional manner of providing non-overlapping clock signals is through the use of cross-coupled gates. For clocking signals that include data, using cross-coupled gates typicaUy causes the non-overlapping signals to have a data dependent duty cycle. A data dependent duty cycle is typically not critical for most switched-capacitor circuits as long as a satisfactory settling time is provided for the circuit. However, for circuits that create a signal strength or reaction that is relative to the amount of time the analog switch is enabled, a data dependent duty cycle typicaUy can create distortion in the signal or reaction. Minor changes in duty cycle of the clock signals driving switches on a circuit with an analog front-end (AFE), such as, for example, the front-end circuit 310, can typicaUy cause signal distortion. The non-overlapping clocks typicaUy must be fixed with respect to a high precision/low jitter clock edge so that the duty cycle of the time-division multiplexed clock signals are not data dependent. The clock signals driving the analog switches such as, for example, the switches phsul, phsu2, phul, phu2, phdl, phd2, phgl, phtc, phbc, phg2, phsg, phs, phf, phloop, phsim, phxbuf, phz, and pha in the front-end circuit 310 typically must be low noise signals having both a fixed duty cycle and sharp edges. The original signals may be generated in a digital area, such as, for example, the digital signal generator 4403, where substrate noise is typically less critical. The clock resynchronization circuit 440δ may, for example, be used to resample the clock signals generated in the digital signal generator 4403, create the fixed duty cycle non-overlap, and drive the switches phsul, phsu2, phul, phu2, phdl, phd2, phgl, phtc, phbc, phg2, phsg, phs, phf, phloop, phsim, phxbuf, phz, and pha with the sharp edged signals. By resynchronizing the signals in the clock resynchronization circuit 440δ using different supplies, the DC on values of the clock signals are preferably less likely to have digital noise from either the supply or the substrate 4415. The digital signal generator 4403 preferably uses cross-coupled gates to generate the non-overlapping clock signals. The clock signals may, for example, change on either a rising or falling edge of the clock, which typically makes them susceptible to ghtches in the clock generation when the clock signals are generated using level-sensitive latches. The clock signals from the digital signal generator 4403 are preferably routed across the substrate 4415 to the clock resynchronization circuit 4405. The routing of the clock signals across the substrate 441δ typicaUy introduces glitches or noise into the clock signals. To help aUeviate the problem of ghtches and noise in the clock signals, the clock resynchronization circuit 440δ preferably uses the asynchronous reset double edge flip-flops 4530a, 4530b, 4δ30c, 4530d, 4δ30e, 4δ30f, 4δ30g, 4530h and the asynchronous set double edge flip-flops 4δ3δa, 4δ3δb, 4δ3δc, 4δ3δd, 4δ3δe, 4535f, 4535g, 453δh, 4535i to restore signal integrity. The asynchronous reset double edge flip-flops 4δ30a, 4δ30b, 4δ30c, 4δ30d, 4530e, 4530f, 4δ30g, 4δ30h and the asynchronous set double edge flip-flops 4535a, 453δb, 4δ35c, 453δd, 4δ3δe, 4δ3δf, 4δ3δg, 4δ3δh, 4δ3δi preferably sample the signals on both the rising edge and the faUing edge of a delayed clock to provide signal alignment and reduce signal glitches causing signal integrity problems. In a preferred embodiment, a clock edge is used to turn off the switches phsul, phsu2, phul, phu2, phdl, phd2, phgl, phtc, phbc, phg2, phsg, phs, phf, phloop, phsim, phxbuf, phz, and/or pha in the front-end circuit 315. In a preferred embodiment, a fixed delay from the clock edge is used to turn on the switches phsul, phsu2, phul, phu2, phdl, phd2, phgl, phtc, phbc, phg2, phsg, phs, phf, phloop, phsim, phxbuf, phz, and/or pha in the front-end circuit 315. The use of the clock edge and the fixed delay preferably ensures a non-overlap and a fixed duty cycle for each clock signal. Similarly, for signals requiring a cascading effect of non-overlap, the delay clock preferably incorporates a larger local delay and drives the same type of non-overlapping sampling circuit. In a preferred embodiment, the asynchronous reset double edge flip-flops 4530a, 4530b, 4δ30c, 4δ30d, 4δ30e, 4530f, 4530g, and 4δ30h and the asynchronous set double edge flip-flops 4δ3δa, 4δ3δb, 4δ3δc, 4δ3δd, 4δ3δe, 4535f, 4δ3δg, 4δ3δh, and 4δ3δi resynchronize input signals to create fixed-delay, non-overlapping signals. The fixed delay is preferably generated by creating the constant width pulses rise delay and rise_delay_plus. The constant width pulses rise delay and rise_delay_plus are preferably used to determine how large the fixed non-overlap delay should be with respect to the incoming clock edge. The sampled signals used to turn off the switches phsul, phsu2, phul, phu2, phdl, phd2, phgl, phtc, phbc, phg2, phsg, phs, phf, phloop, phsim, phxbuf, phz, and/or pha are preferably driven to the off position on the rising edges of the constant width pluses rise_delay and rise_delay_plus. The sampled signals used to turn on the switches phsul, phsu2, phul, phu2, phdl, phd2, phgl, phtc, phbc, phg2, phsg, phs, phf, phloop, phsim, phxbuf, phz, and pha are preferably driven to the on position on the falling edges of the constant width pulses rise delay and rise_delay_plus. Referring to FIGS. 4δa, 4δb, 4δc, 4δd, 4δe, and 48, an exemplary embodiment of the creation and use of a fixed-delay, non-overlapping signal wiU now be described. In a preferred embodiment, the input signal ph Jcb_in is received by the asynchronous reset double edge flip-flop 4δ30b within the clock resynchronization circuit 4405 on an edge of the clock signal XCLK delayed. The input signal ph tcb_in is preferably processed within the clock resynchronization circuit 4405 along with the constant width delay pulse rise_delay_plus to create the output signal ph tcb delayed. In a preferred embodiment, the output signal ph tcb delayed is used to control the switch phtc in the front-end circuit 310 by driving the switch phtc to an on or off position. The output signal ph cb delayed, when necessary, preferably drives the switch phtc in the front-end circuit 310 to the off position on the rising edge of the constant width delay pulse rise_delay_plus. The output signal ph tcb delayed, when necessary, preferably drives the switch phtc in the front-end circuit 310 to the on position on the falling edge of the constant width delay pulse rise_delay_plus. A substantiaUy identical process is used to process the input signals phdb in, phub in, phjbcb n, phgb in, phsub in, phsim in, phxbufb in, phloopb Jn, phfb in, and phsgb in to create the output signals phdb delayed, phub_delayed, ph_bcb_delayed, phgb delayed, phsub_delayed, phsim_delayed, phxbufb delayed, phloopb delayed, phfb delayed, and phsgb delayed, respectively. The output signals phdb_delayed, phub delayed, ph bcb delayed, phgb delayed, phsub delayed, phsim delayed, phxbufb delayed, phloopb delayed, phfb delayed, and phsgb delayed are preferably used to control the switches phdl and phd2, phul and phu2, phbc, phgl and phg2, phsul and phsu2, phsim, phxbuf, phloop, phf, and phsg in the front-end circuit 310. The time lapse between the rising and falling edges of the constant width delay pulse rise_delay_plus preferably creates a delay in the transmission of the output signals phdb delayed, phub_delayed, ph tcb_delayed, phjbcb delayed, phgb delayed, phsub delayed, phsim_delayed, phxbufb_delayed, phloopb_delayed, phfb_delayed, and phsgb delayed from the clock resynchronization circuit 4405 to the front-end circuit 310. The delay preferably ensures that the signals used to turn on the relevant switches in the front-end circuit 310 are non-overlapping with respect to the signals used to turn off the relevant switches in the front-end circuit 310. The degree of non-overlap between the signals used to turn on the relevant switches in the front-end circuit 310 and to turn off the relevant switches in the front-end circuit 310 is preferably determined by the width of the constant width delay pulse rise_delay_plus. In a preferred embodiment, the width of the constant width delay pulse rise_delay_plus is adjusted using extra gates in the feedback comparison path. Referring to FIGS. 45a, 45b, 45c, 45d, 45e, and 49, another exemplary embodiment of the creation of a fixed-delay, non-overlapping signal wUl now be described. In a preferred embodiment, the input signal phsib in is received by the asynchronous set double edge flip-flop 4δ3δi within the clock resynchronization circuit 440δ on an edge of the clock signal XCLK. The input signal phsibjn is preferably processed within the clock resynchronization circuit 440δ along with the constant width delay pulse rise ielay to create the output signal phsib_delayed. In a preferred embodiment, the output signal phsib delayed is used to control the switch phs in the front-end circuit 310. The output signal phsib delayed, when necessary, preferably drives the switch phs in the front-end circuit 310 to an off position on the rising edge of the constant width pulse rise delay. The output signal phsib delayed, when necessary, preferably drives the switch phs in the front-end circuit 310 to an on position on the falling edge of the constant width pulse rise_delay. A substantiaUy identical process is used to process the input signals phab in, phsb Jn, and phzb in in the clock resynchronization circuit 440δ to create the output signals phab delayed, phsb delayed, and phzb_delayed, respectively. The output signals phab_delayed and phzb delayed preferably control the switches pha and phz, respectively, in the front-end circuit 310. The time lapse between the rising and falling edges of the constant width pulse rise_delay preferably creates a delay in the transmission of the output signals phsb delayed, phab delayed, phsib_delayed, and phzb delayed from the clock resynchronization circuit 440δ to the front-end circuit 310. The delay preferably ensures that the signals used to turn off the relevant switches in the front-end circuit 310 are non-overlapping with respect to the signals used to turn on the relevant switches in the front-end circuit 310. The degree of non-overlap between the signals used to turn off the relevant switches in the front-end circuit 310 and to turn on the relevant switches in the front-end circuit 310 is preferably determined by the width of the constant width pulse rise delay. In a preferred embodiment, the width of the constant width pulse rise_delay is adjusted using extra gates in the feedback comparison path. Referring to FIG. δO, a method δOOO of controlling the operation of front- end circuit 310 wiU now be described. In a preferred embodiment, time-division multiplexing is used to control the front-end circuit 310. In a preferred embodiment, the method δOOO includes: generating a first clock signal in step δOOδ, resampling the first clock signal to generate a second clock signal in step δOlO, and driving the front-end circuit 310 using the second clock signal in step δOlδ. In a preferred embodiment, in step 5005 a first clock signal is generated. The first clock signal may be generated using any number of conventional commercially avaUable methods of generating a first clock signal such as, for example, using a state machine or a decoder. In a preferred embodiment, the first clock signals are generated in the digital signal generator 4403 within the multiphase clock generator 320. In a preferred embodiment, in step 5010 the first clock signal generated by the digital signal generator 4403 is resampled by the clock resynchronization circuit 4405 to generate a second clock signal. In a preferred embodiment, the first clock signal is transmitted from the digital signal generator 4403 to an analog signal generator, which resamples the first clock signal. The analog signal generator may include any number of conventional commercially avaUable signal generators suitable for generating the second clock signal. In a preferred embodiment, the analog signal generator is the clock resynchronization circuit 4405. The clock resynchronization circuit 440δ preferably incorporates edge sensitive double-edge fhp-flops that sample the signal on both the rising edge and falling edge of a delayed clock to reduce the likelihood of signal glitches causing signal integrity problems. In a preferred embodiment, the double edge flip-flops include the asynchronous reset double edge flip-flops 4δ30a, 4δ30b, 4δ30c, 4δ30d, 4δ30e, 4δ30f, 4δ30g, and 4δ30h and the asynchronous set double edge flip-flops 4δ3δa, 4δ3δb, 4δ3δc, 4δ3δd, 4δ3δe, 4δ3δf, 4δ3δg, 4δ3δh, and 4δ3δi. In a preferred embodiment, in step δOlδ the second clock signal is used to drive the front-end circuit 310. In a preferred embodiment, the clock resynchronization circuit 440δ sends the sampled signal to the front-end circuit 310 as the second clock signal. In a preferred embodiment, a clock edge is used to turn off switches within the front-end circuit 310, and a fixed delay from the clock edge is used to turn on switches within the front-end circuit 310. In a preferred embodiment, the signals are non-overlapping signals with a fixed duty cycle. Referring to FIGS, δl and δ2, a system δlOO for simulating the output of the sensor 20δ wUl now be described. In a preferred embodiment, the system δlOO includes the sensor 20δ, the controUer 206, the sensor simulator 330, and a switch δlOδ for controllably connecting the sensor 20δ to the controUer 206 or the sensor simulator 330. The sensor 20δ preferably converts a physical quantity of interest into an electrical quantity. The physical quantity of interest may include any physical quantity such as, for example, acceleration, pressure, or temperature. In a preferred embodiment, the physical quantity of interest is acceleration. The electrical quantity into which the physical quantity of interest is converted may be any electrical quantity such as, for example, resistance, capacitance, charge, voltage, or current. In a preferred embodiment, the electrical quantity is capacitance. In a preferred embodiment, the sensor 20δ is coupled to the controller 206 during normal operation. The sensor 20δ may include any combination of nonelectrical devices, integrated circuit and discrete circuit components. The sensor 20δ may include any number of conventional commercially avaUable transducers suitable for converting physical data into an electrical quantity such as, for example, integrated pressure sensors or integrated temperature sensors. In a preferred embodiment, the sensor 20δ is a micromachined accelerometer with capacitive position sensing and electrostatic feedback forcing, the design of which is provided substantially as described in one or more of the following: United States Patent number δ,8δ2,242, and in United States patent application serial number , attorney docket number 14737.737, filed on , the disclosures of which are incorporated herein by reference. The controUer 206 is preferably coupled to the sensor 20δ and controls the sensor 20δ during normal operation. The controUer 206 is preferably coupled to the sensor simulator 330 and controls the sensor simulator 330 during a test mode of operation. The controUer 206 may include any combination of integrated circuit and discrete circuit components. The controUer 206 may include any number of conventional commercially available controllers suitable for converting electrical input into a more convenient output data form such as, for example, an amplitude/frequency modulation, a PID controUer, or a sigma- delta controUer. In a preferred embodiment, the controller 206 is provided substantially as described above with reference to FIGS. 1-50. In a preferred embodiment, during normal operation, the controller 206 determines the position of the measurement mass 309 within the sensor 205 by applying voltages and electrostatic forces to the sensor 205 and measuring the effects of the voltages and the electrostatic forces on the variable capacitors Cl and C2 within the sensor 205. In a preferred embodiment, the position of the measurement mass 309 within the sensor 205 is substantiaUy indicative of the acceleration forces experienced by the sensor 205. The position of the measurement mass 309 within the sensor 205 is preferably conveyed to the controller 206 in the form of an electrical quantity. In a preferred embodiment, the controUer 206 converts the electrical quantity indicative of the position of the measurement mass 309 within the sensor 205 into an output signal of convenient magnitude, phase, and form such as, for example, voltage, current, or digital data. In a preferred embodiment, the controUer 206 converts the electrical quantity indicative of the position of the measurement mass 309 within the sensor 205 into the voltage IMOD. The sensor simulator 330 preferably simulates the input-output relations of the sensor 20δ. In a preferred embodiment, the sensor simulator 330 is coupled to the controller 206 during the test mode of operation. The sensor simulator 330 may include any combination of integrated circuit and discrete circuit components. In a preferred embodiment, as iUustrated in FIG. δ2, the sensor simulator 330 includes a filter δ20δ and an input signal selector δ210. The filter 520δ preferably receives one or more input signals and generates an output signal Vsim that is representative of the operating mode of the sensor 205. The filter 5206 may include any number of conventional commercially avaUable filters such as, for example, a continuous-time analog filter, a switched-capacitor filter, or a digital filter. In a preferred embodiment, the filter 5205 is a second order low-pass filter, implemented as a discrete-time switched-capacitor filter. The input signal selector 5210 preferably selects the input signal as a function of the operating mode simulated by the filter 5205. In a preferred embodiment, the output of the input signal selector 5210 is dependent on the operating mode specified by the filter 520δ. In a preferred embodiment, the input signal selector 5210 is an electrical switch. Referring to FIGS. 53, 54a, and 54b, a method 6300 of testing the output of the controUer 206 wiU now be described. In a preferred embodiment, as Ulustrated in FIG. 53, the method 5300 of testing the output of the controUer 206 includes: connecting the sensor simulator 330 to the controUer 206 in step 530δ, supplying electrical input to the sensor simulator 330 in step 5310, converting the input into the sensor simulator 330 to electrical output in step 5315, sending the output from the sensor simulator 330 to the controller 206 in step 5320, obtaining the output IMOD from the controller 206 in step 5325, and comparing the output IMOD from the controUer 206 with the anticipated output in step 5330. In a preferred embodiment, in step 6305 the sensor simulator 330 is connected to the controUer 206. The sensor simulator 330 may be connected to the controller 206 using any number of methods suitable for connecting the sensor simulator 330 and the controUer 206. In a preferred embodiment, as iUustrated in FIG. 54a and 54b, the sensor simulator 330 is electrically connected to the controller 206 by the electrical switch 5105. In a preferred embodiment, as iUustrated in FIG. 54a, the switch 5105 connects the sensor 205 to the controUer 206 during normal operation of the sensor 205. In another preferred embodiment, as iUustrated in FIG. 54b, the switch 5105 connects the sensor simulator 330 to the controller 206 during the test mode of operation. The switch 5105 may be any number of conventional commercially avaUable switches suitable for connecting the sensor 205 or the sensor simulator 330 to the controUer 206 such as, for example, a DG613 analog switch or a SST211 MOSFET. In a preferred embodiment, in step 5310 input is supplied to the sensor simulator 330. The input may be supphed by any number of sources suitable for supplying input data to the sensor simulator 330 such as, for example, an analog oscillator, an external test source, or a digital signal in memory. In a preferred embodiment, the sensor simulator 330 receives input data from an external test source and receives feedback information from the controller 206. In a preferred embodiment, the filter 5205 preferably receives one or more input data signals and uses the signals to determine the operating state of the sensor 205. The filter 520δ then preferably generates a new signal indicative of the operating state of the sensor 205 and transmits the information to the controller 206. The input signal selector 5210 preferably controllably selects input signals as a function of the operating mode indicated by the startup sequencer 325. In a preferred embodiment, in step 6315 the sensor simulator 330 converts the input received in step 5310 into an electrical output Vsim. In a preferred embodiment, the output Vsim of the sensor simulator 330 depends on the operating state indicated by the filter 5205. The output Vsim of the sensor simulator 330 may be in any form of electrical quantity such as, for example, resistance, capacitance, charge, voltage, or current. In a preferred embodiment, the output Vsim of the sensor simulator 330 is in the form of a voltage. In a preferred embodiment, the electrical input and transfer function of the sensor simulator 330 are approximately mathematically equivalent to the input and transfer function of a typical sensor. Therefore, the behavior of the sensor simulator 330 preferably approximately mimics the behavior of the sensor 205. The output Vsim from the sensor simulator 330 varies depending on the operating mode of the sensor 205. The operating modes of the sensor 205 include the measurement mass 309 setup mode (OPERATING MODE 1), the gravity cancellation mode (OPERATING MODE 2), the stray capacitance cahbration mode (OPERATING MODE 3), and the sigma-delta operating mode (OPERATING MODE 4). In a preferred embodiment, the z-transform Vc(z) of the simulator 330 output voltage Vsim during the four operational modes OPERATING MODE 1, OPERATING MODE 2, OPERATING MODE 3, and OPERATING MODE 4 is given by: during the OPERATING MODE 1, during the OPERATING MODE 2 and the OPERATING MODE 3, and V c (z) = H(z) during the OPERATING MODE 4, where, V c (z) = z-transform of the simulator output voltage Vsim, H(z) = z-transform of the discrete-time sensor model, m = proof mass of the sensor 205, d = gap distance between the capacitor plates of Cl and C2, V R = reference voltage supphed by the front-end circuit 310, V DD = power supply voltage supphed by system power input, C 0 = nominal plate capacitance of Cl and C2 in FIG. 9, D GS1 = duty factor of 1-g canceUation force in OPERATING MODE 1, D GS23 = duty factor of 1-g cancellation force in OPERATING MODE 2 and OPERATING MODE 3, D G4 = duty factor of 1-g canceUation force in OPERATING MODE 4, D F4 = duty factor of modulator feedback forcing in OPERATING MODE 4, V AC (z) = z-transform of a voltage-equivalent input acceleration test signal supplied by an external signal input, V SUM (z) = z-transform of feedback voltage in OPERATING MODES 1, 2 and 3, and D 0 (z) = z-transform of a feedback bitstream. For a sensor transfer function H(s) given by: where B is a damping coefficient and K is an effective spring constant, the "step- invariant" z-transform of H(s) is preferably given by: (A - B + ϊ)z- l + (C- A)z --2 H{z) = K 0 (7) \- Bz- χ + Cz '2 where: m A= e "a secφcos(ωT-φ), B=2e aT cosωT, C=e 2aT , ' - ( fi φ=tan _1 ω J B a= , and 2m B ω= 2 J In a preferred embodiment, the values of the variables associated with Equation (7) are given by: T= sample interval, m=proof mass of the sensor 205, K= spring constant, Q= quality factor, and B= = damping factor. The variables are preferably plugged into Equations (3), (4), or (5) along with other variables and constants to obtain the value of the output Vsim from the sensor simulator 330. In a preferred embodiment, in step 5320 the output Vsim from the sensor simulator 330 is transmitted to the controUer 206. The output Vsim may be sent from the simiύator 330 to the controUer 206 using any number of conventional commercially avaUable methods of sending the output Vsim from the simulator 330 to the controUer 206. In a preferred embodiment, the output Vsim from the simulator 330 is sent to the controUer 206 by an electrical switch. In a preferred embodiment, the output Vsim from the simulator 330 is in the form of a voltage. In a preferred embodiment, in step 5325 the controller 206 receives the input from the sensor simulator 330 and converts it into an output signal of convenient magnitude, phase, and form such as, for example, voltage, current, or digital data. In a preferred embodiment, the output IMOD of the controUer 206 is in the form of voltage. The output Vsim from the sensor simulator 330 may be processed by the controUer 206 using any number of processes suitable for converting the output data Vsim from the sensor simulator 330 into a more convenient form such as, for example, analog filtering or amplitude modulation. In a preferred embodiment, the processing in the controller 206 occurs by switched-capacitor filtering and sigma-delta modulation. In a preferred embodiment, in step δ330 the output IMOD from the controUer 206 is analyzed to determine if the controller 206 is operating properly. The output IMOD from the controUer 206 may be analyzed using any number of methods suitable for determining the accuracy of the controUer 206 output IMOD. In a preferred embodiment, the controUer 206 output IMOD is analyzed to check the stability of the closed-loop system by spectrum analyzing the bitstream outputs from the controUer 206 and comparing the bitstream outputs IMOD from the controller 206 with known frequency response characteristics of working sigma-delta modulators. If the output IMOD from the controUer 206 is inconsistent with the expected output, the controller 206 is identified as a possible source of error within the system 100. Referring to FIGS, δδ and δ6, a method δδOO of creating a controller assembly δ600 wUl now be described. In a preferred embodiment, as iUustrated in FIG. δδ, the method δδOO of creating the controller assembly δ600 includes: providing a substrate δ60δ for the controUer assembly δ600 in step δδOδ, fabricating the controller 206 on the substrate δ60δ in step δδlO, fabricating the sensor simulator 330 on the substrate δ60δ in step δδlδ, and coupling the controUer 206 and the sensor simulator 330 in step δδ20. In a preferred embodiment, in step δδOδ the substrate δ60δ is provided onto which the controUer assembly δ600 is implemented. The substrate δ60δ may include any number of conventional commercially available materials suitable for acting as a substrate for the controUer assembly 5600. In a preferred embodiment, the substrate 560δ is silicon. In a preferred embodiment, in step δδlO the controller 206 is fabricated onto the substrate δ60δ. The controller 206 may be fabricated onto the substrate δ60δ using any number of methods suitable for fabricating a controller onto a substrate. In a preferred embodiment, the controller 206 is fabricated onto the substrate δ60δ by using a 1.5 micron double poly, double metal CMOS process with weak bipolars. In a preferred embodiment, in step δδlδ the sensor simulator 330 is fabricated onto the substrate δ60δ. The sensor simulator 330 may be fabricated onto the substrate δ60δ using any number of methods for fabricating a simulator onto a substrate. In a preferred embodiment, the sensor simulator 330 is fabricated onto the substrate δ60δ by using a 1.5 micron double poly, double metal CMOS process with weak bipolars. In a preferred embodiment, in step 5δ20 the controller 206 is coupled to the sensor simulator 330. The controUer 206 and the sensor simulator 330 may be coupled using any number of methods suitable for coupling electronic components. In a preferred embodiment, the electrical switch δlOδ is used to couple the controUer 206 and the simulator 330. In another preferred embodiment, the switch δlOδ is turned off to disconnect the controUer 206 and the sensor simulator 330 and is turned on to connect the controUer 206 and the sensor 20δ. In this manner, for example, the operation of the controller 206 may be tested without assembling the entire sensor system 100. In another preferred embodiment, in step δδlO a plurahty of controllers 206 are fabricated onto the substrate δ60δ, and in step δδlδ a plurahty of sensor simulators 330 are fabricated onto the substrate δ605. In step 5δ20, the plurahty of controUers 206 and the plurality of sensor simulators 330 are preferably coupled, creating a plurahty of controller assemblies 5600 on a single substrate 560δ. In this configuration, for example, the operation of a plurality of controUers 206 may be tested by using a single substrate δ60δ, eliminating the need to use a plurahty of substrates δ60δ. Referring to FIG. δ7, a method δ700 of creating the sensor system 100 will now be described. In a preferred embodiment, the method δ700 of creating the sensor system 100 includes: creating a controller assembly in step δ70δ, testing the controUer assembly in step δ710, and couphng the controUer assembly to a sensor 20δ in step δ71δ. In a preferred embodiment, in step δ705 the controller assembly is created. The controUer assembly preferably includes the sensor simulator 330, the controUer 206, and the substrate 560δ. The controUer assembly may be created using any method suitable for creating a controller assembly. In a preferred embodiment, the controller assembly is created by fabricating the sensor simulator 330 and the controUer 206 on the substrate 560δ, substantiaUy as described in the method δδOO of creating the controller assembly δ600. In a preferred embodiment, the controUer assembly δ600 includes the controUer 206 and the sensor simulator 330 implemented as an apphcation specific integrated circuit (ASIC). In a preferred embodiment, in step 5710 the operation of the controUer assembly 5600 is tested. The operation of the controUer assembly 5600 may be tested using any number of methods suitable for testing a controUer. In a preferred embodiment, the operation of the controller assembly 5600 is tested by checking the stabUity of a closed-loop system by spectrum analyzing the bitstream outputs IMOD from the controUer 206 and comparing them with known frequency response characteristics of working sigma-delta modulators. The controUer 206 preferably processes the output Vsim of the sensor simulator 330 and produces the controUer 206 output IMOD. The output IMOD of the controller 206 is preferably compared with the expected output associated with the known output Vsim from the sensor simulator 330. If the actual output IMOD of the controller 206 and the expected output of the controller 206 are equal, the controUer assembly 5600 is operating properly. In a preferred embodiment, in step δ71δ the controUer assembly δ600 is coupled to the sensor 20δ. In a preferred embodiment, the controller assembly 6600 is coupled to the sensor 20δ after the controUer assembly 5600 is found to be operating properly in step 5710. The sensor 205 and the controller assembly 5600 may be coupled using any number of methods suitable for coupling a sensor to a controller. In a preferred embodiment, the sensor 205 and the controUer assembly δ600 are coupled using the electrical switch δlOδ. Although Ulustrative embodiments of the invention have been shown and described, a wide range of modification, changes and substitution is contemplated in the foregoing disclosure. In some instances, some features of the present invention may be employed without a corresponding use of the other -9δ- features. Accordingly, it is appropriate that the appended claims be construed broadly and in a manner consistent with the scope of the invention.

Claims: Claims 1. A sensor system for recording environmental data measurements, comprising: a sensor for detecting environmental data; a controller for controUing the operation of the sensor, including: a front-end circuit coupled to the sensor; a loop filter coupled to the front-end circuit; a multiphase clock generator coupled to the front-end circuit and the loop filter; and a startup sequencer coupled to the loop filter; and a communication interface for coupling the sensor and the controUer. 2. A controUer for controlling the operation of a sensor, comprising: a front-end circuit coupled to the sensor; a loop filter coupled to the front-end circuit; a multiphase clock generator coupled to the front-end circuit and the loop filter; a startup sequencer coupled to the loop filter and the multiphase clock generator; a sensor simulator for simulating the performance of the sensor coupled to the startup sequencer, the multiphase clock generator, and the front-end circuit; and an overload detection device coupled to the loop filter and the startup sequencer. 3. A controUer for controUing the operation of a sensor, comprising: a front-end circuit coupled to the sensor; a loop filter coupled to the front-end circuit; a multiphase clock generator coupled to the front-end circuit and the loop filter; a startup sequencer coupled to the loop filter and the multiphase clock generator; and an overload detection device coupled to the loop filter and the startup sequencer. 4. A front-end circuit for providing electrostatic forces and position sensing for a measurement mass in a sensor, comprising: a plurahty of switches for controlling the operation of the sensor; and a sense amplifier for sensing the position of the measurement mass within the sensor. 5. A loop filter for providing control to a sensor system, comprising: one or more integrators for providing a signal for controlling the sensor system; one or more derivative controUers for providing a signal for controUing the sensor system; one or more proportional controUers for providing a signal for controlling the sensor system; and a summer for combining the signals from the integrators, the derivative controUers, and the proportional controllers. 6. A method of operating a loop filter within a sensor system, comprising: sending a signal to the loop filter indicating an operating mode of the sensor system; operating the loop filter in a reduced-order mode while the sensor system is operating in a start-up mode; operating the loop filter in the reduced-order mode for a predetermined period of time after the sensor system transitions from the start- up operating mode to a sigma-delta operating mode; and operating the loop filter in a normal mode during the sigma-delta operating mode after the predetermined period of time during which the loop filter operates in reduced-order mode. 7. A method of operating a loop filter within a sensor system, comprising: sending a signal to the loop filter indicating an operating mode of the sensor system; operating the loop filter in a reduced-order mode while the sensor system is operating in a start-up mode; operating the loop filter in the reduced-order mode for a predetermined period of time after the sensor system switches from the start-up operating mode to a sigma-delta operating mode; operating the loop filter in the reduced-order mode whUe the sensor system is operating in the sigma-delta operating mode; and operating the loop filter in a normal mode whUe the sensor system operates in the sigma-delta operating mode after the predetermined period of time during which the loop filter operates in reduced-order mode. 8. A method of controUing the operation within a sensor system of a loop filter including one or more integrators, a proportional controUer, and a derivative controUer, comprising: sending a signal to the loop filter indicating the operating mode of the sensor system; holding the integrators in a reset mode to place the loop filter in a reduced-order operating mode when the sensor system is operating in a start-up mode; and taking the integrators out of the reset mode to place the loop filter in a normal operating mode when the sensor system is operating in a sigma-delta operating mode. 9. A method of placing a loop filter including one or more integrators, a proportional controUer, and a derivative controller in a reduced-order operating mode, comprising: sending a signal to the loop filter to control the operating mode of the loop filter; holding the integrators within the loop filter in a reset mode to place the loop filter in the reduced-order operating mode. 10. A method of providing control to a sensor assembly, comprising: determining an operating mode of the sensor assembly; adjusting a mode of operation of a loop filter in the sensor assembly; providing feedback loop compensation to the sensor assembly during a start-up mode of operation for the sensor assembly; and providing noise shaping to the sensor assembly during a sigma-delta mode of operation for the sensor assembly. 11. A multiphase clock generator for providing clock signals for controUing the operation of a sensor system, comprising: a digital signal generator; and a data-independent clock resynchronization circuit coupled to the digital signal generator. 12. A sensor simulator for simulating the operation of a sensor, comprising: a filter adapted to receive one or more input signals and generate an output signal representative of the operating state of the sensor; and an input signal selector operably coupled to the filter adapted to controUably select the input signals as a function of the simulated operating state of the sensor. 13. A system for testing the operation of a controUer in a sensor system, comprising: a sensor simulator for simulating the operation of a sensor; and a controUer coupled to the simulator. 14. A method of controUing the operation of a sensor system, comprising: using a controUer to apply electrostatic forces to a sensor to create one or more sensor operating states; and sequentially arranging the operating states into which the sensor is placed to create one or more operating modes for the sensor system. 15. A feedback control system for providing control to a sensor system, comprising: a startup sequencer for selecting the mode of operation of the feedback control system; and a loop filter coupled to the startup sequencer. 16. A multiphase clock generator for generating clock signals for use within a sensor system, comprising: a digital signal generator for generating a first clock signal; and a clock resynchronization circuit coupled to the digital signal generator for receiving the first clock signal from the digital signal generator and resampling the first clock signal to generate a second clock signal. 17. A clock resynchronization circuit for resampling clock signals, comprising: a plurahty of inverters; a plurality of NOR gates coupled to the inverters; a plurahty of NAND gates coupled to the inverters; a plurahty of XNOR gates coupled to the NAND gates and the inverters; a plurahty of asynchronous set double-edge fhp-flops coupled to the NOR gates; and a plurahty of asynchronous reset double-edge fhp-flops coupled to the NOR gates. 18. A device for resamphng an input signal on a rising edge and a falling edge of a clock signal, comprising: a plurahty of transmission gates; one or more NOR gates coupled to the transmission gates; and a plurahty of inverters coupled to the NOR gates and the transmission gates. 19. A device for resampling an input signal on a rising edge and a faUing edge of a clock signal, comprising: a plurality of transmission gates; one or more NAND gates coupled to the transmission gates; and a plurahty of inverters coupled to the NAND gates and the transmission gates. 20. A method of generating a clock signal for a sensor assembly, comprising: generating a first clock signal; and resampling the first clock signal to generate a second clock signal to restore signal integrity and provide a timing relationship. 21. A method of resampling an input signal, comprising: resampling the input signal in a first level-sensitive latch, including one or more transmission gates, one or more NOR gates, and one or more inverters, on one edge of a clock input signal; and resampling the input signal in a second level-sensitive latch, including one or more transmission gates, one or more NOR gates, and one or more inverters, acting in parallel with the first level-sensitive latch, on another edge of the clock input signal. 22. A method of resampling an input signal, comprising: resampling the input signal in a first level-sensitive latch, including one or more transmission gates, one or more NAND gates, and one or more inverters, on one edge of a clock input signal; and resampling the input signal in a second level-sensitive latch, including one or more transmission gates, one or more NAND gates, and one or more inverters, acting in parallel with the first level- sensitive latch, on another edge of the clock input signal. 23. A method of operating an analog control circuit, comprising: generating a first clock signal; resampling the first clock signal to generate a second clock signal to restore signal integrity and provide a proper timing relationship; and driving the analog control circuit using the second clock signal. 24. A controUer assembly, comprising: a sensor; a sensor simulator for simulating the operation of the sensor; a controller for controlling the sensor and the sensor simulator; and a switch for coupling the controller to the sensor or the sensor simulator. 25. A method of testing a controUer in a controller assembly, comprising: connecting a sensor simulator to the controller; supplying an input signal of a known value to the sensor simulator; converting the input data to the sensor simulator into an output stream from the sensor simulator; sending the output stream from the sensor simulator to the controUer; processing the output stream from the sensor simulator within the controUer to create an output stream from the controUer; and analyzing the output from the controller to determine the accuracy of the controUer. 26. A method of fabricating a controUer assembly for a sensor, comprising: providing a substrate; fabricating one or more controUers on the substrate; fabricating one or more sensor simulators on the substrate; and coupling the controller and the sensor simulator. 27. A method of offsetting the effects of external acceleration forces on a sensor, independent of an orientation of the sensor, comprising: applying electrostatic forces to the sensor to offset the effects of the acceleration force.

Inventors: ABRAMS MICHAEL L, BLACKBURN JEFF, BROSEGHINI JAMES, BURCHFIELD MARK E, DEVOLK BURTON A, DUPIE SCOTT T, JOHNSON RICHARD A, JONES BEN, MAHER ROGER, MAYO FRANK, ZAVALETA MAURICIO A, ABRAMS, MICHAEL, L., BLACKBURN, JEFF, BROSEGHINI, JAMES, BURCHFIELD, MARK, E., DEVOLK, BURTON, A., DUPIE, SCOTT, T., JOHNSON, RICHARD, A., JONES, BEN, MAHER, ROGER, MAYO, FRANK, ZAVALETA, MAURICIO, A.
Applicants: ABRAMS MICHAEL L, BLACKBURN JEFF, BROSEGHINI JAMES, BURCHFIELD MARK E, DEVOLK BURTON A, DUPIE SCOTT T, INPUT OUTPUT INC, JOHNSON RICHARD A, JONES BEN, MAHER ROGER, MAYO FRANK, ZAVALETA MAURICIO A, ABRAMS, MICHAEL, L., BLACKBURN, JEFF, BROSEGHINI, JAMES, BURCHFIELD, MARK, E., DEVOLK, BURTON, A., DUPIE, SCOTT, T., INPUT/OUTPUT, INC., JOHNSON, RICHARD, A., JONES, BEN, MAHER, ROGER, MAYO, FRANK, ZAVALETA, MAURICIO, A.
Application year: 2000
Main classification: G01N
IPC codes: G01D11, G01D18, G01H1, G01L27, G01N1, G01P1, G01P15, G01P21, G01V1, H01L21, H01L29, H05K5