An output buffer with constant switching current

Abstract: The buffer has an output stage (10) formed by two complementary MOS transistors (MPOUT, MNOUT) connected so as to operate in phase opposition between the supply terminals (VDD, earth) and two driver stages (14 and 15) having the input (IN) in common. Each driver stage (14, 15) has a first branch comprising a current-generator (MN4, MP4) connected between the gate electrode of the transistor to be driven (MPOUT, MNOUT) and a supply terminal (earth, VDD) and an electronic switch (MP1, MN1) controlled by the input (IN) and connected between the same gate electrode and the other supply terminal (VDD, earth), and a second branch which comprises, connected in series, a transistor connected as a diode (MP3, MN3) and an electronic switch (MP2, MN2) controlled by the output (OUT), and is arranged between the gate electrode of the transistor to be driven (MPOUT, MNOUT) and a respective supply terminal (VDD, earth). The buffer can control a load (13) with a constant switching current, is simple in structure, and occupies a small area.

Description: The present invention relates to integrated circuits and, more particularly, to an output buffer for digital signals as defined in the preamble of Claim 1. Document US-A-5 367 210 and EP-A-0 331 341 disclose an output buffer as defined in the preamble of claim 1. As is known, in an integrated circuit, an output buffer for digital signals is an interface circuit which serves for driving a load which, in most cases, is outside the integrated circuit. Normally, the circuit is dimensioned on the basis of direct-current operating specifications, that is, on the basis of the maximum value of the supply voltage and on the maximum value of the current to be supplied to a predetermined resistive load. As a result of this dimensioning, the switching speed is often much greater than required and this may give rise to serious disadvantages. In particular, as the number of functions which can be integrated in a single chip of semiconductor material increases, the number of outputs of the integrated device increases. The outputs are often grouped in "buses" and have to be switched simultaneously by the respective output buffers. In these cases, very high pulsed currents pass through the impedances and the parasitic resistances associated with the electrical connections between the integrated circuit and the external terminals during switching. These current transients require the external supply to deliver, for very short periods, currents much greater than those required on average for the operation of the device, and therefore necessitate the use of over-dimensioned supply means. This problem is experienced in particular when the integrated device forms part of portable apparatus, that is, of apparatus having limited electrical energy resources. Moreover, the current transients may give rise to spurious internal switching, and hence to losses or alterations of the data associated with the digital signal. In mixed integrated circuits, that is, those containing both digital portions and analog portions, the current transients may prejudice the performance of the analog circuits. To prevent or at least attenuate the problems explained above, devices must be designed with supply-connection tracks of sufficiently large cross-section. A solution cf this type is completely unsatisfactory since it leads to a great wastage of area and does not solve the problem of excessive demands on the supply. A known output buffer designed to address the problems explained above is shown in Figure 1. In this example, the buffer is constituted by four pairs of complementary MOS transistors connected so as to operate in phase opposition, in pairs (M1n-M4n; M1p-M4p), but it could be constituted by a much larger number of such pairs. The pairs of transistors are connected between two supply terminals, indicated by the earth symbol and +VDD, and have, as a common terminal, the drain electrodes of the transistors which are connected to an output terminal OUT. The gate electrodes of the first pair M1p, M1n are connected together to the input terminal IN of the buffer and the gate electrodes of the subsequent pairs are connected together to the gate electrodes of the respective preceding pairs by means of delay circuits which, in this example, have equal delay times Δt. The transistors are of a size such that each pair can supply one quarter of the output current to the load, not shown. As a result of the delays, a transition in the level of a signal applied to the input IN gives rise to a much slower transition in the output signal than in the input signal, reducing any current peaks. However, this circuit operates satisfactorily only if it is constituted by a large number of pairs of transistors. This involves the wastage of a large area of the integrated circuit so that this solution is not in practice very much favoured by designers. Another known buffer is shown schematically in Figure 2. It is formed by a single pair of complementary MOS transistors Mp and Mn controlled by respective driver stages DRp and DRn. The stages DRp and DRn operate in a manner such as to switch the respective transistors off rapidly and to switch them on slowly by the generation of a constant-current front long enough to cause the output OUT to switch gradually. However, this known buffer is rather complex and, in the same manner as the other known buffer described briefly above, supplies a current which varies in dependence on the load. An object of the present invention is to propose an output buffer for digital signals in which the switching current, that is, the current delivered or absorbed during the transitions of the digital signal, is independent of the load. Another object is to propose an output buffer for digital signals which is simple and reliable and occupies a small area. These objects are achieved by the provision of the buffer defined and characterized in general in Claim 1. The invention will be understood further from the following detailed description of two embodiments thereof, given by way of non-limiting example, with reference to the appended drawings, in which: figures 1 and 2 show the circuits of two known buffers, figure 3 shows the circuit cf a buffer according to a first embodiment of the invention, figure 4 shows some wave-forms which illustrate the operation of the circuit of Figure 3, figure 5 shows a second embodiment of the invention, and figure 6 shows the circuit of a possible practical implementation of the embodiment of Figure 5. The circuit shown in Figure 3 comprises an output stage 10 with complementary MOSFET transistors, more precisely, a p-channel transistor MPOUT and an n-channel transistor MNOUT, connected so as to operate in phase opposition between a first supply terminal +VDD and a second supply terminal, indicated by the earth symbol. The node common to the two transistors, that is, the connection node between their two drain electrodes, is the output terminal OUT of the buffer and is connected, by means of a respective pin of the integrated circuit, to an external load 13, typically a substantially capacitive load. The circuit comprises two stages 14 and 15 for driving the transistors of the output stage 10. The driver stage 14 is constituted by two circuit branches: a first circuit branch comprises an n-channel MOS transistor MN4 and a p-channel MOS transistor MP1. The transistor MN4 which, as will be explained below, has the function of generating current, has its source electrode connected to earth, its drain electrode connected to the gate electrode of the output transistor MPOUT, and its gate electrode connected to the input terminal IN of the buffer. The transistor MP1, which has the function of a controlled electronic switch, has its gate electrode connected to the input terminal IN of the buffer. The second circuit branch of the driver stage 14 comprises a p-channel MOS transistor MP3 connected in the so-called diode arrangement, that is, with its gate and drain connected to one another, in series with a p-channel MOS transistor MP2 having the function of a controlled electronic switch. The common electrodes of the transistor MP3 are connected to the gate electrode of the output transistor MPOUT and the gate electrode of the transistor MP2 is connected to the output terminal OUT of the buffer. The driver stage 15, as can be seen from Figure 3, is constituted by a third branch (MP4, MN1) and by a fourth branch (MN3, MN2) having structures duplicating those of the first and second branches of the driver stage 14. Before the operation of the buffer of Figure 3 is 'examined, it is appropriate to make some remarks relating to the nature and the dimensions of the transistors which form parts thereof. The dimensions of the output transistors MPOUT and MNOUT are determined by the same criteria as are used for the buffer of the prior art, that is, on the basis of the maximum value of the supply voltage and on the maximum value of the current to be supplied to a resistive load during direct-current operation. The transistor MP2 must operate substantially is a switch and must therefore have as low as possible an impedance when it is made conductive. The transistor MP3 must conduct a current which is a predetermined fraction of the current of the output transistor MPOUT and will therefore have dimensions correspondingly correlated with those of the transistor MPOUT (typically, it will have the same channel length and a width which is a fraction of the width of MPOUT). The transistor MN4 is intended to operate in saturation conditions, that is, with a large impedance, and must be able to supply the necessary current to MP3. The transistor MP1 is intended to operate as a switch for rapidly interrupting conduction of the output transistor MPOUT when required and is therefore dimensioned accordingly. Wholly similar remarks may be made with regard to the dimensions of the transistors of the driver stage 15 of the output transistor MNOUT. The operation of the buffer during a switch from 0 to 1 of a digital signal applied to the input terminal IN will now be considered with reference to Figure 4. It can easily be seen that, in the absence of a signal, with the input IN at level 0, that is, at the earth potential, the output OUT is also at 0, that is, MNOUT is conductive (on) and MPOUT is non-conductive (off). When the signal is applied to the input IN, immediately after the leading edge from 0 to 1, MP4 becomes non-conductive (off) and MN1 becomes conductive (ON). The output transistor MNOUT switches off because its gate electrode DN goes to 0. At the same time, in the driver stage 14, MP1 switches off and MN4 switches on. Since the output OUT is at 0, MP2 is on so that a current flows through MP2, MP3 and MN4, connected in series. At the gate electrode DP of the output transistor MPOUT, there will be a voltage VDD-VDS(MP2)-VTH(MP3)-VOD(MP3), that is, the supply voltage VDD, minus the voltage drop in MP2 in saturation conditions, minus the threshold voltage of MP3, minus the voltage beyond the threshold (overdrive) due to the current imposed by MN4 in MP3. By way of indication, the voltage at the node DP will be below the supply voltage VDD by a value of between 0.7 and 1.5V, according to the relative dimensions of the various transistors. In these conditions, the output transistor MPOUT, which was initially off, starts to conduct a current substantially proportional to that which passes through the transistor MP3 and to charge the capacitance of the load 13. The coefficient of proportionality is determined by the scale factor, that is, by the dimensional ratio between MPOUT and MP3. This situation is maintained throughout the time for which MP2 remains on. When the voltage at the output terminal OUT reaches a value equal to VDD minus the threshold of MP2, minus the overdrive of MP2 (very small if MP2 is of a suitable size), MP2 switches off, interrupting the flow of current through MP3 and MN4. Since MN4 is still on because the input IN is at high level (VDD), the node DP goes to 0, MPOUT is switched on and the output OUT goes to VDD. The rise in the voltage at the output OUT to VDD takes place with a constant rate of change (slew rate) for the greater portion of its swing, that is, the portion determined substantially solely by the current reflected by MP3 on MPOUT. The small residual swing is controlled by the zeroing rate of the node DP, that is, by the capacitance associated therewith (substantially the gate capacitance of MPOUT) and does not lead to a substantial increase in the current of the output transistor MPOUT which operates in the linear zone in these conditions. When the input IN goes from 1 to 0, the output OUT switches from 1 to 0 in a manner precisely mirroring that described above. As is clear from the foregoing, in the buffer according to the invention, the current delivered to the load 13 or absorbed thereby during the transitions of the signal is substantially independent of the load and is determined basically by the dimensions of the components of the driver stages. It should also be noted that, in contrast with the known buffer shown in Figure 2, in which the slow voltage variation front at each of the gate electrodes of the output transistors is inactive until the threshold of the respective output transistor is exceeded, with a consequent delay of the output signal, the response of the buffer according to the invention is very rapid since the charging of the gate capacitances of the output transistors takes place by means of the series connection of a transistor connected as a diode (MP3 or MN3) and of a transistor with the function of a switch (MP2 or MN2), both of which have low resistance. Finally, the area required to produce the buffer according to the invention is very small, by virtue of the low number of components. According to the embodiment shown in Figure 5, the transistors MN4 and MP4 of Figure 3, which have the function of current generators, are replaced by constant-current generators IGEN1 and IGEN2 in series with respective transistors MN5 and MP5 having the function of switches controlled by the input signal. The constant-current generators IGEN1 and IGEN2 may be formed with the use of n-channel and p-channel transistors, respectively, connected as current mirrors to a biasing circuit. A biasing circuit may be provided in the integrated circuit for other purposes so that, in this case, further comoonents are not necessary to complete the buffer, or the biasing circuit may be formed appropriately. Figure 6 shows a possible embodiment of the biasing circuit. The transistors MIGEN1 and MIGEN2 which perform the functions of the generators IGEN1 and IGEN2 of Figure 5 are connected as current mirrors to two transistors, MN6 and MP6, respectively, which are connected as diodes in series with a resistor R, between the supply terminals VDD and earth. The current reflected is determined substantially solely by the supply voltage and by the resistance R and, to a large extent, is insensitive to variations of the process parameters and of the operating temperature of the circuit. It should also be noted that the transistors MIGEN1 and MIGEN2 are conductive only during the transitions in the level of the input signal, by virtue of the action of the series transistors MN4 and MP5, respectively, so that their contribution to the consumption of electrical energy is very limited. The buffer may also be used to control an internal load of the integrated circuit which contains the buffer, rather than for controlling an external load as in the embodiments described.

Claims: An output buffer for digital signals having an output stage comprising a first output MOS transistor of a first type (P) and a second MOS transistor of a second type (N) with respective source electrodes connected to a first supply terminal (VDD) and to a second supply terminal (earth), respectively, drain electrodes connected together to an output terminal (OUT) of the buffer, and gate electrodes connected to an input terminal (IN) of the buffer by means of a first driver stage (14) and a second driver stage (15), respectively, characterized in that : the first driver stage (14) comprises: a first circuit branch comprising first current-generator means (MN4) connected between the gate electrode (DP) of the first output transistor (MPOUT) and the second supply terminal (earth) and a first controlled electronic switch (MP1) connected between the gate electrode (DP) of the first output transistor (MPOUT) and the first supply terminal (VDD) and having a control electrode connected to the input terminal (IN) of the buffer, and a second circuit branch comprising a first MOS transistor of the first type (P) connected as a diode (MP3) in series with a second controlled electronic switch (MP2) between the gate electrode (DP) of the first output transistor (MPOUT) and the first supply terminal (VDD), the second electronic switch (MP2) having a control terminal connected to the output terminal (OUT) of the buffer, and the second driver stage (15) comprises: a third circuit branch comprising second current-generator means (MP4) connected between the gate electrode (DN) of the second output transistor (MNOUT) and the first supply terminal (VDD) and a third controlled electronic switch (MN1) connected between the gate electrode (DN) of the second output transistor (MNOUT) and the second supply terminal (earth) and having a control electrode connected to the input terminal (IN) of the buffer, and a fourth circuit branch comprising a second MOS transistor of the second type (N) connected as a diode (MN3) in series with a fourth controlled electronic switch (MN2) between the gate electrode (DN) of the second output transistor (MNOUT) and the second supply terminal (earth), the fourth electronic switch (MN2) having a control terminal connected to the output terminal (OUT) of the buffer. An output buffer according to Claim 1 in which the first current-generator means comprises a third MOS transistor (MN4) of the second type (N) having its gate terminal connected to the input terminal (IN) of the buffer and the second current-generator means comprises a fourth MOS transistor (MP4) of the first type (P) having its gate terminal connected to the input terminal (IN) of the buffer. An output buffer according to Claim 1 in which the first current-generator means comprises a first current generator (IGEN1) in series with a fifth controlled electronic switch (MN5) having a control terminal connected to the input terminal (IN) of the buffer and the second current-generator means comprises a second current generator (IGEN2) in series with a sixth controlled electronic switch (MP5) having a control terminal connected to the input terminal (IN) of the buffer.

Inventors: CONFALONIERI PIERANGELO, NAGARI ANGELO, NICOLLINI GERMANO, CONFALONIERI, PIERANGELO, NAGARI, ANGELO, NICOLLINI, GERMANO
Applicants: ST MICROELECTRONICS SRL, STMICROELECTRONICS S.R.L.
Application year: 2000
Main classification: H03K19
IPC codes: H03K19, G11C7