IMAGE SENSOR'S UNIT CELL WITH INDIVIDUALLY CONTROLLABLE ELECTRONIC SHUTTER CIRCUIT

Abstract: A method of individually controlling exposure of a pixel during a given time period. The method includes establishing an integration interval (T) representing the given time period, and establishing in the integration interval (T) a plurality N of program sub-periods. Each program sub-period is followed by an associated integration sub-period (T'0, T'1, T'2), wherein the integration sub-periods (T'0, T'1, T'2) are of various periods of time.

Description: IMAGE SENSOR'S UNIT CELL WITH INDIVIDUALLY CONTROLLABLE ELECTRONIC SHUTTER CIRCUIT FIELD OF THE INVENTION The invention disclosed herein relates generally to a CMOS image sensor unit cell, and more particularly, to a charge integration control circuit which provides individual exposure control of each such unit cell. BACKGROUND OF THE INVENTION Image sensors generally comprise a number of sensing unit cells arranged in a focal plane array (FPA). Each unit cell is a picture element (a pixel) which is exposed to light, and produces an electrical response representative thereof. The electrical response is then collected by the image sensor and converted into a video signal. Existing image sensors fall far behind the capabilities of the human eye in their ability to capture wide dynamic range scenes. The following approaches have been taken to improve their performance. Orly Yadid-Pecht and Eric R. Fossum in their article " Wide Intrascene Dynamic Range CMOS APS Using Dual Sampling" describe a multiple exposure method which consists of combining several images at different charge- integration periods. Typically, the images are of the. same scene and are captured in a single snap. These images are readout from the FPA, and then combined into a single wide dynamic range image. The multiple exposure approach, however, has a number of disadvantages. One such is the requirement for further processing in order to combine several images, which limits the ability of true-motion video. Typically, image combination is complex and results in artifacts of different kinds in the displayed image may be introduced into scenes. Such efforts may create imaging limitations. Delbruck T. and C. Mead in their article "Photo-transconduction by Continuous Time, Adaptive Logarithmic Photo-receptor Circuits" describe a unit cell which responds logarithmically to photocurrent. Via their described method, a wide photocurrent range value proportional to light intensity can be compressed into the signal dynamic range of a relatively limited dynamic range unit cell. However, the logarithmic approach also has drawbacks. A mismatch between circuit components in cells results in a wide spread in the response of the cells, even for adjacent pixels. This in-turn translates into fixed pattern noise (FPN). Furthermore, the implementation of such a cell can be of high complexity, and results in lower sensitivity since a substantial area is occupied by the active circuit, which leaves decreased area for the photoreceptor. The percentage of the area occupied by the photoreceptor of the entire pixel area is defined as the fill factor. The smaller the area occupied by the photoreceptor, the lower the sensitivity of the pixel to light. For a given pixel pitch (which defines the image sensor's resolution) a smaller fill factor means lower image sensor sensitivity, or alternatively, a non-reduced sensitivity but a lower resolution. Currently, the ultimate manner to imitate the performance of the human's eye is via autonomous per-pixel exposure. Examples of approaches for such are described by Orly Yadid-Pecht in her article "CMOS Active Pixel Sensor Star Tracker with Regional Control circuit", and by Christopher Clark et al in their article "Application of APS Arrays to Star and Feature Tracking Systems". The autonomous per-pixel exposure method facilitates an independent exposure time for each pixel in the image sensor. Proper setting of an exposure time for each pixel allows direct compression of a signal's dynamic range in the focal plane array, without any artifacts. This method is suitable for most demanding wide dynamic range applications, such as, tracking stars and galaxies which emit light with broadly varying light intensities. One approach, as outlined by Chen S. and Ginosar R. in "Adaptive Sensitivity CCD image sensor", is limited due to the complexity of the unit cell involved. The described unit cell effectively reduces the image sensor's resolution and sensitivity, and makes its use impractical in large arrays. Another approach, as described by Orly Yadid-Pecht in her article "Wide Dynamic Range APS Star Tracker", is known as the independent pixel reset (IPR), and requires an independent reset of charge in every unit cell. This approach provides each unit cell with its individual independent reset, however, the architecture inherently limits the dynamic range of the exposure time. In one particular application described in Yadid-Pecht's article, the exposure time is programmable in four steps, ranging from 1 , Vi, , 1 / 8 , and 1 /i 6 of the maximum integration time. Although this exposure time range may be sufficient for a star tracker application, it is limiting from other viewpoints. First, the variation in integration time range is limited to 16:1 , which may not be sufficient since this limits the range of exposure times, and therefore, also limits the dynamic range. Additionally, the suggested four integration time steps are too rough to perform high-quality focal plane image dynamic range compression. A preferably method would provide at a minimum 16 integration time steps, each step equal to 1/16 step, instead of 4 greatly spaced steps. Existing implementations of individually-set pixel charge-integration times have inherent limitations that limit their application to real-time/high-resolution video. The inherent limitations are size, complexity and low dynamic range, poor resolution and sensitivity. Furthermore, the IPR approach consumes too much time to facilitate video rate operation, and limits the image sensor's minimum integration time. As noted in " Wide Dynamic Range APS Star Tracker", for every sixteenth of an integration period, the minimum integration time is in the order of one second, as compared to less than 20 msec for one entire full integration period. For these reasons, the IPR approach is not suitable for continuous-tone/real-time motion video. SUMMARY OF THE INVENTION The multi-integration sub-period method and charge integration control circuit disclosed herein are conceptually different from the prior art approaches, and eliminate the drawbacks of those approaches. The invention is a new simple cell structure that supports high resolution, high sensitivity and wide dynamic range of exposure times, making it applicable to ultra high dynamic range scenes in real time video. The invention disclosed herein relates generally to an individually controllable electronic shutter circuit, each such circuit dedicated to an associated image sensing unit cell. More particularly, the invention describes a charge-integration time electronic shutter circuit for use in an image sensor, where a single dedicated individually controlled shutter circuit is provided for each individual pixel to control the collection or storage of image information therefrom. The inventive control circuit may be implemented in Complementary MOS (CMOS) technology as part of a CMOS Focal Plane Array (FPA) Active Pixel Sensor (APS) unit cell which utilizes active transistors in the unit cell. The invention facilitates construction of a superior class of CMOS image sensors in which each pixel charge-integration time, or "exposure time" can be individually and autonomously controlled during each integration interval. Furthermore, this can be done at video speed and in a variation range which dramatically boosts the image sensor's dynamic range. One of the ways that the described invention is technically different from the other methods is that the present invention discloses segmenting the integration interval into a set of discrete, isolated in time, varying duration integration sub-periods. The effective, total charge integration interval is the sum of the integration sub-period segments which were programmed to be exposed. This technical advancement is brought about by the innovative combination of an analog memory and a programmable control circuit. The present invention additionally discloses utilizing an integration capacitor as an analog memory element, not only during the readout phase, however, as in other sensors, but also during integration of sub-period segments within the integration interval. Prior art utilizes the integration capacitor as an analog memory device for retaining collected charge after the integration interval, only, with a charge readout taking place after the completion the entire integration. The present innovative method uses the charge retention capabilities of the integration capacitor to continuously receive and store the charge during the discrete, different time-length integration sub-periods. Hence, during suspension of charge integration, the capacitor retains the prior accumulated charge, and upon resumption of integration, resumes collection of charge. Readout of the charge is performed only after all the integration sub-periods are completed. The present invention thus enables multiple integration sub-periods during each integration interval. Employing a unit cell which incorporates such a charge-integration-time control circuit, along with integration access methods as described in provisional application 60/145,950, CMOS Image Sensor with Autonomous/Per-Pixel Charge Integration Control, and included herein by reference, enable implementation of a CMOS image sensors arrays with autonomous/per-pixel controlled charge integration time. The innovative charge-integration time control circuit disclosed herein utilizes a dynamically storing latch as a memory cell, and a simple transfer transistor for integration control. Therefore, the present invention requires an addition of only two transistors and a capacitor. The simplicity of the present invention does not create a major overhead on the overall unit cell complexity. The present invention also provides an alternative control circuit which includes a single pass transistor and is implementable with CMOS technology. The control circuit facilitates a wide dynamic range of integration time values. As an example, for motion video, simultaneous pixel integration time dynamic range of 10-bit (2 10 ) can be easily accomplished, and for still-video, 20-bit is feasible. This can facilitate much higher intra-scene dynamic range. The control circuit additionally enables control of the integration time in fine steps of minimal time period. For instance, if the integration time dynamic range is 2 10 (10 bits), the integration time can be controlled in 1/1024 steps from 1/1024 to (2 10 -1). Consequently, wide dynamic range scenes can be compressed with high fidelity and displayed. The charge integration circuit, which resides in each unit cell, is simple, and therefore does not consume large percentage of the pixels size. The image sensor can be effectively controlled and results in flexible and scene-adaptable dynamic range compression. It is an object of the invention herein to provide a control circuit for an image sensor that has a wide dynamic range. There is therefore provided, in accordance with a preferred embodiment of the present invention, a method of individually controlling exposure of a pixel during a given time period. The method includes establishing an integration interval representing the given time period, and establishing in the integration interval a plurality N of program sub-periods. Each program sub-period is followed by an associated integration sub-period, wherein the integration sub-periods are of various periods of time. Charge is transferred between the photosensor and a charge storage device during the integration sub-periods, only. The capacitor charge is read out and consequently discharged after N program/integration sub-periods are over. The step of establishing the plurality of the program sub-periods includes preconditioning each of the pixels to an integrate or not integrate state. The step of enabling includes transferring charge when in the integrate states, and not transferring charge when in the non-integrate states. The method further includes accumulating charge in the charge storage device when the charge is transferred and retaining a charge level on the charge storage device when the charge is not transferred. The charge level on the charge storage device is related to the cumulative transfer of charge during the integrate states. There is therefore additionally provided in accordance with a preferred embodiment of the present invention, an imaging system including an array of pixels and a programmable memory for each of the pixels. The pixels include at least one photosensor and an associated storage device per photosensor. The combination of the storage device plus the programmable memory allows for a plurality of integration sub-periods of within frame. Furthermore, each of the storage devices stores a charge indicative of a plurality of integration sub-periods. The storage device is preferably a capacitor. The programmable memory has a pass transistor, a capacitor connected to the pass transistor, and a transfer transistor connected to the capacitor. The programmable memory selectively enables the transfer transistor to transfer or not transfer an integrate signal. The programmable memory is either a dynamic storage latch or a static latch. Additionally, the programmable memory circuit includes means for functioning in an array, and when functioning in an array, receives programming data signals and programming control signals. There is therefore additionally provided in accordance with a preferred embodiment of the present invention, an imaging system including a unit cell and a storage device. The unit cell senses light during one or more integration sub-periods and outputs an electrical charge relatively indicative of the sensed light. The storage device receives and accumulates the charge for the one or more integration sub-periods. Preferably the one or more integration sub-periods are intermingled with one or more non-integration sub-periods. Furthermore, preferably the storage device is a capacitor, and/or acts as an analog memory element. Hence the storage device accumulates charge during the one or more integration sub-periods, and retains the accumulated charge during the one or more non-integration sub-periods. Preferably, the storage device discharges the accumulated charge after a plurality of the integration sub-periods and non-integration sub-periods. In one of the preferred embodiments, the one or more integration and non-integration sub-periods are of varying time periods. The unit cell preferably includes a photosensor; and an exposure control and readout device connected between the photosensor and the storage device. The control circuit selectively couples and decouples the photosensor with the storage device. Alternatively, the unit cell includes a preamplifier connected to the photosensor. There is therefore additionally provided in accordance with a preferred embodiment of the present invention, a method for sensing an image. The method includes sensing light during one or more integration sub-periods, and not sensing light during one or more non-integration sub-periods, wherein said integration and non-integration sub-periods are preconditioned. Charge is accumulated after each step of sensing and retained during each the step of not sensing. Preferably, each step of sensing and/or not sensing is preceded by an associated step of programming, which defines occurrence of the integration sub-periods and the non-integration sub-periods, respectively. The method further includes repeating the step of accumulating and retaining a plurality of times and discharging the accumulated charge following the repeated steps of accumulating and retaining. BRIEF DESCRIPTION OF THE DRAWINGS The invention is illustrated in the figures of the accompanying drawings which are meant to be exemplary and not limiting. Like or associated references in the different figures refer to like or corresponding parts. In the accompanying drawings: Figs. 1A to 1 D are block diagrams of a CMOS unit cell according to preferred embodiments of the present invention; Fig. 2 is a schematic circuit diagram of an embodiment of a charge integration control circuit, according to a preferred embodiment of the present invention; Figs. 3A to 3H are timing diagrams of various signals in the charge integration control circuit of Fig. 2; and Fig. 4 is a schematic circuit diagram of an alternative charge integration control circuit, according to an alternative preferred embodiments of the present invention. DESCRIPTION OF THE PREFERRED EMBODIMENTS Reference is now made in parallel to Figs. 1A - 1 D, which illustrate unit cells 10A - 10D, respectively. Except for the differences to be described in detail hereinbelow, unit cells 10A - 10D function similarly, and descriptions herein referring to unit cell 10A are also addressed to unit cells 10B - 10D. Similar elements are similarly referenced and will not be explained in further detail. Fig. 1A illustrates a preferred embodiment of an image sensor unit cell 10A. Each unit cell 10A comprises a novel charge integration control circuit 12, a photosensor 14, a preamplifier 16, a capacitor Cι and a readout circuit 18. In a preferred embodiment of the present invention, novel control circuit 12 works in tandem with capacitor Q, thereby providing image sensor unit 10A with the capability to accumulate multiple separate discrete time-integrated charges during one integration interval. For purposes of clarity herein, an integration interval is defined as the time period spanning from a readout of the charge collected in unit cell 10A, to the subsequent readout of the same unit cell 10A. This integration interval is equivalent to the time period from capacitor reset to capacitor reset. In a preferred embodiment, one integration interval comprises a multiplicity of duration variant integration sub-periods, wherein during each integration sub-period a discrete charge is collected. Photosensor 14 is typically either a photo-diode, or a phototransistor, and functions as a photocurrent source, providing a current l ph proportional to the light photon flux impinging on the photosensor. Preamplifier 16 amplifies the signal transferred by photosensor 14, and is an optional element. Preamplifier 16 serves as a low-input-/high-output impedance amplifier which decouples photosensor 14 from the rest of the elements comprised within unit cell 10A to maintain constant photocurrent for a constant light intensity. Thus, preamplifier 16 enables the bias of photosensor 14 to be independent of the bias on capacitor C|. Furthermore, preamplifier 16 maintains current l pn to be integrated-charge invariant . Control circuit 12, upon receipt of the appropriate signal, selectively couples or decouples preamplifier 16 with capacitor C|, thereby selectively enabling or disabling a current lc from being to capacitor C|. Preferably, current lc is equal to current l pn , e.g. when enabled, l c = l h , and when disabled, lc = 0 Capacitor Cι receives and integrates the current lc passed by the control circuit 12, and accumulates the integrated charge until readout circuit 18 is activated. Readout circuit 18 selectively couples the capacitor Cι to a sense line ColSense. In a preferred embodiment of unit cell 10A, control circuit 12 is connected to a set of associated inputs lines, a reset (Rst) , an integrate (Int) line, a line program (LnPrg) and a column program (ColPrg) input lines.. It is noted that one of the essential elements of the present invention, the Int signal, commences and terminates the sub-periods, e.g., when the Int signal goes high, the integration sub-period commences, and when the Int signal goes low, the integration sub-period terminates. Integration occurs only when the Int is high. The Rst signal discharges capacitor Cι before the integration interval. The LnPrg signal enables control circuit 12 to be programmed, and the ColPrg signal preconditions the control circuit for integration/non-integration during the subsequent Int signal sub-period. . For purposes of clarity herein, the various digital signals are referred to as having a state that is either high or low. Furthermore, the single unit cell 10A depicted in Fig. 1A constitutes a picture element in a focal plane array and the use of the terms line program (LnPrg) and column program (ColPrg) refers to the lines and columns, respectively, of the array. It is noted that each unit cell 10A is uniquely connected to a pair of row and column signals. The following is an example of one preferred process for operation of unit cell 10A. All the unit cells 10A are subjected to a Rst signal which discharges the capacitors . Alternatively, if during the previous readout cycle readout circuit 18 drained capacitor Cι, then capacitor Cι may initially be in the zero charge state. Therefore, commencing the process with Rst signal is optional and dependent upon the operation of readout circuit 18. The LnPrg signal is set high, or active, and received by control circuit 12. This drives the control circuit 12 to be programmed by the ColPrg signal carried on the ColPrg line. Control circuit 12 is then programmed to either a "0" or "1" level, as determined by the ColPrg signal. In a preferred embodiment, programming control circuit 12 with a "0" enables charge integration to be accumulated in capacitor Cι when the Int signal is high (active). Conversely, programming control circuit 12 with a "1" disables accumulation of charge integration to capacitor C|. For example, when the Int signal is high and the control circuit 12 is programmed with a "0", control circuit 12 enables current l ph to pass from the preamplifier 16 to capacitor Cι,. Thus l c = l Ph and charge is accumulated in capacitor C|. In contrast, , if control circuit 12 is programmed with a "1", current flow from the input to the output is disabled, even if the Int signal is high. Thus lc = 0, and no charge is accumulated and no charge is accumulated during this integration sub-period. It is noted that preferably control circuit 12 is programmed with a series of states "1 " and "0", such that depending on the programmed state, control circuit 12 either enables or disables current flow to capacitor C|. Hence, capacitor Cι alternately accumulates additional charge, and alternately maintains in its present state without accumulating more charge. Furthermore, it is additionally noted that although capacitor is not continuously charged, once it has accumulated charge, it retains the accumulated charge until readout. In a preferred embodiment of the present invention, charge integration capacitor Cι performs a novel function in unit cell 10A. During the charge retention period, when the Int, Rst, and LnRd signals are inactive, there is no current flow in to or out of the capacitor C|, and the capacitor Cι retains the accumulated charge. The capacitor Cι thus functions as an analog memory element that "memorizes" the accumulated integrated charge. During the charge integration sub-period, when Int is active and the control circuit 12 is programmed to enable charge integration (l c = l Ph ,), capacitor Cι again accumulates charge, adding further charge to the already accumulated charge. Thus the capacitor Cι acts as charge-summing element. In a preferred embodiment of the present invention, each unit cell 10A receives a unique combination of "0's" and "1 's" from its associated LnPrg line and ColPrg line, and hence, each unit cell 10A has a unique integration charge accumulation sequence. Thus, during the duration of the integration sub-period (when Int is "High" or active), each unit cell 10A enables or disables charge integration as per its individual programming sequence. Therefore, when the Int signal is active, the unit cell 10A either passes the lp h current from the preamplifier 16 to the capacitor Cι (l c = l P h), or not (l c = 0). As noted above, this depends on the preconditioned programming value of the control circuit 12. Conversely, when the Int signal is "0", the current path between the preamplifier 16 and the capacitor Cι is disconnected, and the integration capacitor Cι retains the charge so far accumulated. When the control circuit 12 is enabled again, charge integration continues and capacitor Cι accumulates further charge. This continues until completion of the integration interval . The readout circuit 18 transfers the charge stored in the capacitor Cι via the ColSense line to the image sensor's sense amplifier (not shown). The readout method itself may vary depending on the type of readout circuit. Readout circuit 18 may be a source follower, a direct charge readout circuit, or any other type of compatible readout circuit. One implementation of readout circuit 1 8 is described in "CMOS Image Sensor: Electronic Camera-On-A-Chip", by Eric R. Fossum, , IEE Transactions on Electron Devices, Vol. 44, No. 10 October . Therefore, as described hereinabove, in a preferred embodiment of the present invention, the charge integration interval is composed of several programming cycles, each followed by a discrete charge integration sub-period. Thus, the integration interval comprises multiple integration sub periods, and the charge integration time is an accumulation of all the integration sub-periods which occur during that integration interval. In a preferred embodiment of the present invention, it is noted that the charge integration time may not equal the integration interval time. The charge integration time is a composite of the integration sub-periods wherein capacitor Cι accumulated charge, while the integration interval is a composite of all the integration sub-periods, whether capacitor Cι was allowed to accumulate charge or not. Or in other words, the charge integration time is an accumulation of the sub-periods when both control circuit 12 and Int signal are active, while the integration interval is the period when the Int signal is active, regardless of the state of the control circuit 12. The operation of capacitor d will now be explained. Capacitor Cι accumulates and sums charge during the sub-periods, such that, if: Q a ,-ι is the accumulated charge at the beginning of integration interval i; T, is the time length of the current integration interval; p, is the value programmed into control circuit 12 by latching the value of the ColPrg signal (p, = "1 " when LnPrg = "0", and p, = "0" when LnPrg = "1"); then: (1) Q a , = Q a ,ι + p, ■ l ph • T, where Q a , is the accumulated charge at the end of current integration interval. Provided that the capacitor Cι is linear, if V c ,.-] is the voltage on the capacitor Cι, at the beginning of the integration interval, and V c , is the voltage on the capacitor Cι, at the end of the integration interval, then (2) V c , = Q a , / Cι , and (3) \ , = V 1 -, ., + p, ■ l ph • T, / C Formulas (1), (2) and (3) are valid and contingent upon the above noted assumptions of retention, accumulation, and charge linearity. In alternative embodiments, capacitance non-linearity vs. current or voltage can be compensated for by various mathematically solutions, such as by mapping linearity vs. voltage and current. Additionally, charge leakage from capacitor Ci, can be determined and compensated for, however, such compensation complicates implementation of the invention. Fig. 1 B illustrates unit cell 10B, an alternative preferred embodiment of the present invention. In this embodiment the ColPrg signal is applied only during the integration interval, while the ColSense is used only during the readout period (when LnRd is active). Therefore, the two signals are mutually exclusive and a single line may be used to perform both the column programming and the column sensing function. Hence, unit cell 10B has a single ColPrg/ColSense line, which replaces the separate ColPrg and ColSense lines of unit cell 10A. The control circuit 12 may also operate in reverse polarity, as depicted in unit cell 10C. Unit cell 10C is similar to the unit cell 10A, however, the polarity of the photosensor 14 is reversed, and the l ph current flows in the opposite direction. In this reverse current polarity embodiment, rather than resetting the capacitor Cι, it is preset (precharged), to an initial value by a PRst signal. The precharged capacitor Cι is discharged in a controlled manner by control circuit 12. Because the initial capacitor precharge value is fixed, the charge/current/voltage value readout from unit cell 10C provides the same information in relationship to the pixel's photo current as does unit cell 10A. Unit cell 10D is an alternative preferred embodiment of unit cell 10C. Similar to unit cell 10B, a single ColPrg/ColSense line replaces the two ColPrg and ColSense lines. Unit cells 10A - D, when operated with the novel charge integration control circuit 12, enable a digitally controlled integration time. This is accomplished by dividing the integration interval into several integration sub-periods, and summing the sub-period integration charges. The calculations for the total integration charge and the voltage accumulated at the end of an integration interval are calculated as follows: let there be k integration sub-periods following the Rst signal; assuming that the photosensor's current l pn is constant through the entire integration interval, therefore, if; p, is the programming value in the i-th integration sub period, for p, = 1 ; then l ph is the charging current through the capacitor Cι, otherwise the charging current is zero; Tι is the width of the Int pulse, Q a is the total integration charge, and V c is the voltage on capacitor C| at the end of the integration interval, then: and, T / k-\ (5) yc = 7 ' c ' ∑ ι=0 P> T > k-X where ∑p,T l represents the total charge integration time, and, (7) Q a = lph T Therefore, assuming that the values of Tj are predetermined (fixed) for all possible integration intervals, since the capacitor Cι retains (memorizes) the recently accumulated charge, the total integration time is simply dependant upon the set of values {p k -ι, Pk-2, -- , Pι,Po}- Thus, the entire integration interval can be determined by selecting a unique combination of p, programmable coefficients. The principles of the invention encompass any combination of Int signal widths, and any sequence of p, coefficients. For alternative embodiments where T 0 is the basic time unit, (9) T i = 2 i - To, i = 0,1 , ... , k-2, k-1 , then, k-1 (10) T = T 0 -Σpr 2 1 , or i = 0 (11) T = T 0 • (Pk-i Pk-2 ■■•• P2 P1 Po)2 Therefore, the integration interval is programmable through the binary number (pk-1 p k -2 -- P2 Pi P0.2 • When (pk-i Pk-2 • ■ • P2 Pi Po is (0 0 ... 0 1) 2 , Tj (min) = To, which is the shortest possible integration sub-period. When (p k -ι Pk-2 ■■ ■ P2 Pi P 0. 2 is (1 1 ... 1 1) 2 , Tj (max) = To * (2 k - 1 ), which is the longest possible integration sub-period. (Pk-1 Pk-2 ... P2 Pi Po)2 can be any integer number between the minimum and the maximum values. Therefore, the integration time can be any value starting with To in steps of T 0 , up to T 0 * (2 k - 1). The ratio between the longest and the shortest integration time, known as integration time dynamic range (DRT) is an important parameter which controls the range of charge integration. The DR T is defined as, (12) DRτ = 20 - log 1 o ( T ma χ / T mi n ) Therefore since T max = (2 k - 1) and T min = 1 , (13) DR T = 20 log 10 (2 k -1) Usually, k >> 1 , therefore, (14) DR T = 6.02 k , where k is the number of bits (or integration sub periods) in the integration programming word. Reference is now made to Fig. 2, which illustrates an implementation of the control circuit 12. Elements similar to Figs. 1A - D are similarly referenced, and will not be described further. Reference is also made to Figs. 3A-3H which show the timing of control signals, the current l c , and the voltage V c at the output of the control circuit 12. As depicted in Fig. 2, control circuit 12 includes a single pass transistor T1 (NMOS), a transistor T2 (PMOS), a data latch or memory device L1 , and a reset transistor T3 (NMOS). Transistors T1 , T2 and T3 have gates G1 , G2 and G3, respectively. Transistor T2, together with the Int line, controls the state of transistor T1. Memory L1 comprises incoming nodes Ld and D, output nodes Q and ϋ and is programmable to enable or disable integration prior to the Int signal becoming active. The input of the pass transistor T1 is connected to the preamplifier 16 and receives current l P . Integration capacitor is connected to the output of the pass transistor T1 , and charged by current l c . Pass transistor T1 controls the current flow between the input (connected to preamplifier 16) and the output (connected to capacitor Cι) of circuit 12. When the voltage at gate G1 is zero or below, T1 is cut-off and there is no current flow to output line. Memory L1 is coupled to the ColPg and LnPrg lines at nodes D and Ld, respectively; G1 is coupled to noted Q; transistor T2 is coupled to the Int line; and, reset transistor T3 is coupled to the Rst line. In a preferred embodiment, reset transistor T3 discharges the capacitor Cι when Rst is "high". This usually happens prior to the start of the charge integration. It is noted that although not shown, in a preferred embodiment, a circuit is needed in the bias circuit of photosensor 14 to drain the input current l ph . There is preferably an alternative path for the current l ph , since if l ph is not completely drained, photosensor 14 may become forward biased and highly capacitive, which attributes to a slow switching response. Typically, this requirement is implemented by a transistor which forms a path through the photosensor to ground. In the instance of a photodiode, the logical location for this circuit is at the photodiode's anode (preamplifier input). When the voltage at the gate G1 is "High", transistor T1 conducts, and the charging current lc equals the input current l pn . The state of the gate G1 node is controlled by transistor T2, which in turn is controlled by the state of the gate G2 and the state of the Int signal. The ColPrg signal is normally at the Vdd voltage level. When the LnPrg signal transitions from "Low" to "High", the ColPrg signal is at "High". Therefore, node Q goes to zero feeding into gate G2, causing the transistor T2 to conduct. With transistor T2 on, gate G1 discharges to zero (or stays at zero if it was at zero beforehand), since the Int signal is also at "Low", and the pass transistor T1 does not conduct. A "High" LnPrg signal latches a new state into the memory L1. The ColPrg signal is "High" when the LnPrg signal transitions from "Low" to "High" , thus causing the discharge of node G1 from any residual charge. Hence, the programming cycle typically starts with G2 being at zero, thus causing the transistor T2 to conduct. If the control circuit 12 has to conduct current through T1 during the next time Int signal is "High", the ColPrg signal remains "High" for the entire latch period Otherwise, the ColPrg signal transitions to "Low" before the LnPrg transitions to "Low", resulting in T2 being cut off Then, the ColPrg signal returns to "High" after the LnPrg signal returns to "Low" It is noted that the cycle is repeated when Rst signal goes high again and ^ the transistor T3 discharges the charge accumulated in capacitor Cι Figs 3A - 3H show the timing for the circuit depicted in Fig 2 and demonstrates charge integration The Rst signal (Fig 3A) starts the cycle and causes the capacitor to discharge As a result, the accumulated voltage V c (Fig 3H) is reset to zero volts While the ColPrg signal (Fig 3B) is "High", the 0 LnPrg signal (Fig 3C) transitions to "High" causing the gate G2 (Fig 3D) to go "Low" Thus, transistor T2 is caused to conduct When the Int signal (Fig 3E) transitions to "High" for a T 0 integration sub period, gate G1 (Fig 3F) goes "High" for the same time period Consequently, the pass transistor T1 conducts, providing a conduction path from the input line ( preamplifier 16) to the output s line (capacitor Cι) Thus, the current l ph at the input line equals the current l c (Fig 3G) at the output line (lc = l Ph ), and the current lc charges the capacitor Cι, resulting in an accumulated voltage Vc (Fig 3H) When the first Int pulse, or sub-period (Fig 3E) is terminated, the voltage Vc (Fig 3H) reaches the l pn • T 0 / C| voltage level After the Int pulse terminates, 0 the pass transistor T1 is cutoff, and the capacitor Cι retains its charge and maintains the l ph • T 0 / Cι voltage level During the next LnPrg programming pulse (Fig 3C) the ColPrg signal (Fig 3B) transitions from "High" to "Low", causing the gate G2 (Fig 3D) to go "High" and transistor T2 to cutoff Since the gate G1 was set to zero before -Ϊ latching the G2 gate node to "High", the pass transistor T1 remains in cutoff when next (second) Int pulse (Fig 3E) appears for a Ti period Therefore no charge integration will occur during this second Int pulse During the third LnPrg pulse, the ColPrg line (Fig 3B) is "High" (as during the first LnPrg), and the pass transistor T1 conducts for the duration of the third Int pulse for a T time period Therefore, charge integration by C| takes place (Fig 3H), and the voltage over the capacitor will reach the l ph * (T 0 + T 2 )/ Cι voltage level Thus, the capacitor Cι sums up the charge of those Int periods, during which transistor T2 is programmed to conduct. Fig. 4 illustrates a preferred embodiment of memory L1. Memory L1 comprises a transistor T4 (NMOS) and a capacitor C p , which holds the gate G2 voltage when transistor T4 is cutoff (and the latch function is performed). Preferably, the threshold voltage V T N of transistor T4 is smaller than the absolute value of the threshold voltage V T p of transistor T2. Typically, the greater the difference between V TN and |VT P |, and the greater the value of C P , the better the voltage retention at gate G2. Therefore, preferably a DRAM CMOS process is utilized for the implementation memory L1 , rather than a SRAM CMOS process. However, it might be demonstrated that during the overwhelming part of the integration interval, the ColPrg line is "High". During this period the sub-threshold channel conduction, if it occurs at all, will be into the gate G2. This helps to retain gate G2 at "High". Since retention of the "High" state is usually the limiting factor in the performance of the value retention function of a dynamic latch, the requirement for a large C P capacitor is reduced. Hence, alternately, a static RAM CMOS process is usable. The value retention function can be further helped if the LnPrg signal varies in a greater swing than from zero to Vdd (the main supply voltage value). If for instance the LnPrg signal "Low" value is - 0.5 volts rather than zero, the leakage of the transistor T4 channel is reduced substantially by orders of magnitude. This is equivalent to having an orders of magnitude larger capacitor Cp. If the LnPrg signal "High" value is (Vdd + 1) v, then the gate G2 can reach Vdd, rather than Vdd - VT N - This provides better discharge margins at gate G2. As such, for this embodiment, use of a CMOS DRAM process is eliminatable. While the invention has been described and illustrated in connection with preferred embodiments, many variations and modifications, as will be apparent to those of skill in the art, may be made without departing from the spirit and scope of the invention. For example, circuit implementation of a charge integration control circuit and a latch have been disclosed demonstrating the principles of the invention using a certain set of NMOS, and PMOS transistors, and control signals. Other variations of transistor types, and appropriate signal polarities, which are obvious variants of the described circuits can be used. Such variations are encompassed within the principles described herein, and should not be viewed as outside the scope of the invention. It is additionally noted that the herein mentioned invention can be implemented with either positive or negative polarity, and the relevant depletion/ enhancement p-channel transistor. Accordingly, the invention as set forth in the appended claims is thus not limited to the precise details of construction set forth above as such variations and modifications are intended to be included within the spirit and scope of the invention as set forth in the claims.

Claims: CLAIMS 1. A method of individually controlling exposure of a pixel during a given time period, the method comprising the steps of: establishing a per pixel integration interval representing said given time period; establishing in said integration interval a plurality N of program sub-periods each followed by an associated integration sub-period, wherein said associated integration sub-periods are of various periods of time; enabling a transfer of charge between said photosensor and a charge storage device only during said integration sub-periods; reading-out said charge stored in said charge storage device; and discharging the charge storage device after N times is over. 2. A method according to claim 1 wherein said step of establishing said plurality of program sub-periods comprises the step of preconditioning each said pixel to an integrate or non-integrate state. 3. A method according to claim 2, wherein said step of enabling comprises the steps of: transferring charge when in said integrate states, and not transferring charge when in said non-integrate states. 4. A method of according to claim 3, further comprising the steps of: accumulating charge in said charge storage device when said pixel is in said integrate state, and such that said charge is transferred; and retaining a charge level on said charge storage device when said pixel is in said non-integrate state, and such that said charge is not transferred, whereby said charge level on said charge storage device is related to said cumulative transfer of charge during said integrate states. 5. An imaging system, comprising: an array of pixels; and a programmable memory for each said pixel, wherein said pixel includes at least one photosensor and an associated storage device per said photosensor, and wherein a combination of each said storage device plus said programmable memory allows for a plurality of within frame exposures. 6. An imaging system, comprising: an array of pixel; and a programmable memory for each said pixel, wherein said pixel includes at least one photosensor and an associated storage device per photosensor, wherein each said storage device storing a charge indicative of a plurality of integration sub-periods. 7. An imaging system according to claim 6, wherein said storage device is a capacitor. 8. An imaging system according to claim 6, wherein each said programmable memory includes: a first pass transistor a capacitor connected to said first pass transistor; and a transfer transistor connected to said capacitor, wherein, said programmable memory selectively allows transfer or not transfer of an integration signal by said transfer transistor. 9. An imaging system according to claim 8, wherein said programmable memory is one of the following types: a dynamic storage latch, and a static storage latch. 10. An imaging system according to claim 6, wherein said programmable memory includes means for functioning in an array, and which receives programming data signal and programming control signals. 11. An imaging system comprising: a unit cell, which senses light during one or more integration sub-periods and outputs an electrical charge relatively indicative of said sensed light; and a storage device in communication with one or more said unit cells, which receives said charge, and accumulates said charge for said one or more integration sub-periods, whereby said one or more integration sub-periods are intermingled with one or more non-integration sub-periods. 12. An imaging system according to claim 1 1 , wherein said storage device is a capacitor. 13. An imaging system according to claim 1 1 , wherein said storage device acts as an analog memory element which accumulates said charge during said one or more integration sub-periods and retains said accumulated charge during said one or more non-integration sub-periods. 14. An imaging system according to claim 11 , wherein one or more integration sub-periods are of various time periods. 15. An imaging system according to claim 11 , wherein one or more non-integration sub-periods are of various time periods. 16. An imaging system according to claim 11 , wherein said unit cell comprises: a photosensor; and an exposure control and readout device connected between said photosensor and said storage device, which selectively couples and decouples said photosensor with said storage device. 17. An imaging system according to claim 16, wherein said unit cell comprises a preamplifier connected to said photosensor. 18. An imaging system according to claim 11 , wherein said storage device discharges said accumulated charge after a plurality of said integration sub-periods and non-integration sub-periods. 19. A method for sensing an image, comprising the steps of: sensing light during one or more integration sub-periods and not sensing light during one or more non-integration sub-periods, wherein said integration and non-integration periods are preconditioned; and accumulating said charge after each step of sensing and retaining during each said step of not sensing. 20. A method according to claim 19, wherein each step of sensing and not sensing is preceded by an associated step of programming which defines occurrence of said integration sub-periods and said non-integration sub-periods. 21. A method according to claim 19, further comprising the steps of: repeating said step of accumulating and retaining a plurality of times; and discharging said accumulated charge following said repeated steps of accumulating and retaining.

Inventors: STARK MOSHE, STARK, MOSHE
Applicants: STARK MOSHE, VISION SCIENCES LTD, STARK, MOSHE, VISION-SCIENCES LTD.
Application year: 2000
Main classification: H04N5
IPC codes: H01L27, H04N3, H04N5