ANALOGUE FRONT END WITH MULTILEVEL SIGMA-DELTA MODULATOR FOR ADSL

Abstract: The present invention, generally speaking, achieves a highly efficient line driver for high crest-factor signals such as DMT/ADSL signals. In an exemplary embodiment, a digital signal produced by a digital signal processor or the like is processed by a sigma-delta modulator to produce one or more binary signal pairs. The signals of a signal pair are low-pass filtered, if necessary, and applied across the winding of a transformer. The transformer has a single secondary winding connected to the line and may have as many primary windings as the number of signal pairs. The transformer may have a unity turns ratio or may have a turns ratio for accomplishing voltage step-up. For one signal pair, the number of possible resulting signals levels on the secondary side is three, for two signal pairs five, etc. Using more than two signal levels, it becomes possible to recreate from the digital signals the corresponding analog waveform with the required accuracy. The circuit requires only a single supply voltage, is inherently balanced and provides high-voltage DC isolation.

Description: Analogue front end with multi l evel sigma-del ta modulator for ads The present invention relates to line drivers for high-speed digital communications. Broadband communications solutions, such as ADSL (Asynchronous Digital Subscriber Line) are increasingly in demand. The ability to achieve high data rates (e.g., 1Mbps and above) between customer premises and the telephone system central office over existing (unconditioned) telephone lines poses a considerable technical challenge. ADSL is simply one example of a class of communications techniques generally known as Discrete Multitone (DMT). In DMT, a broad band of spectrum is divided into potentially a large number of sub-bands having a particular center frequency (tone). Conceptually, a digital communications signal is sent within each sub-band, all of the sub-band signals being added together to form a single complex signal. Referring to Figure 1, in the specific case of ADSL, about 250 discrete tones are placed within a band from about 0.1 to 1.2MHz (above the voice band, or POTS region), with information being modulated on each tone. Using such an arrangement, a combined bandwidth of up to 8Mbps can be achieved. An ADSL signal presents special problems for circuit designers because of its large "crest factor," defined as the ratio of the peak signal voltage to the average signal voltage. For ADSL, the crest factor is typically about 5.6. This high crest factor is accounted for by noting that, whereas the discrete multitone signals comprising an ADSL signal usually sum together to a relatively low average value, occasionally, the signals align in such as way as to sum together to a relatively high peak value. A typical ADSL signal might appear as shown in Figure 2, for example, characterized by a high peak value, Vpk, and a low average value, Vave. The signal is produced by a digital signal processor (DSP) in the form of a digital signal having a sample rate in the range of about 3 to 5MHz. (Also identified in Figure 2 are voltage levels Vs j and Vs 2 , referenced in the description that follows.) Figure 3 shows a first example of a prior-art ADSL line driver circuit. An 8Mbps information stream is input to a DSP, which produces a complex modulated signal in the form of samples (e.g., 12 bit) at the aforementioned sample rate. The samples are converted to analog and the resulting signal low-pass filtered to produce a transmission signal. The transmission signal is applied to a linear (e.g., Class A) radio amplifier. Typically, the amplifier operates from + 15V power supplies and receives about 10W of power. About 9.9W of power are dissipated within the amplifier, while about 0.1W of power is output through an isolation transformer to the phone line. Because of the power consumption and heat dissipation of the circuit of Figure 3 , only a few hundred such line drivers can be accommodated within a typical central office of the telephone system. That is, only a very small percentage of the subscriber's serviced by the central office can be provided with broadband service without rebuilding or reconfiguring the central office, which besides being very expensive is often not feasible. Figure 4 shows an improved prior-art ADSL line driver circuit. This circuit differs from that of Figure 3 in that a "Class G" amplifier is used, comprising the usual Class A amplifier in combination with a switchable power supply. During normal operation, a supply voltage select circuit is set to apply a lower supply voltage Vs 2 , say +5V, to the amplifier. When greater signal range is required, the DSP produces a control signal PK that sets the supply voltage select circuit is set to apply a higher supply voltage Vsl (e.g., +5V) to the amplifier. The Class G amplifier dissipates about 3W, as compared to almost 10W in the original approach. While the circuit of Figure 4 provides a substantial improvement over the circuit of Figure 3, the underlying problems of excessive power consumption, excessive heat dissipation, and low efficiency remain to a large degree. Because of the linearity requirements of DMT/ ADSL signals, circuits used heretofore for DMT/ ADSL line drivers have been linear circuits. Other existing non-linear, switch-mode circuits have generally not been considered for this purpose. One such circuit is the sigma-delta modulator. Sigma-delta modulators are widely used for data conversion. A sigma-delta converter modulates a varying-amplitude analog input signal into a simple digital code at a frequency much higher than the Nyquist rate. Another non-linear prior-art circuit is the Class D amplifier, most commonly used for audio applications. In a Class D amplifier, an input signal (typically an audio signal) is transformed into an output signal capable of being reproduced into the original signal on an external load, usually a speaker. In the basic operation of a Class D amplifier, an incoming signal is converted by a pulse- width modulator into a high-frequency rectangular wave, the average value of which tracks the original signal. The rectangular wave is fed into an output stage which provides level shifting and splits the signal into a driving signal high/low driving signals. The driving signals are filtered to remove switching noise, providing an averaged output to drive a load such as a speaker. Within the output stage, however, the high/low signals result in significant distortion due to imperfectly matched components. More particularly, pulses produced by pull-up and pull-down transistors, respectively, exhibit substantially different shapes. Such distortion is unacceptable in applications such as ADSL. There remains a need for a line driver circuit for high crest-factor signals such as DMT/ADSL signals that consumes less power, dissipates less heat and is more efficient. The present invention, generally speaking, achieves a highly efficient line driver for high crest-factor signals such as DMT/ADSL signals. In an exemplary embodiment, a digital signal produced by a digital signal processor or the like is processed by a sigma-delta modulator to produce one or more binary signal pairs. The signals of a signal pair are low-pass filtered, if necessary, and applied across the winding of a transformer. The transformer has a single secondary winding connected to the line and may has as many primary windings as the number of signal pairs. The transformer may have a unity turns ratio or may have a turns ratio for accomplishing voltage step-up. For one signal pair, the number of possible resulting signals levels on the secondary side is three, for two signal pairs five, etc. Using more than two signal levels, it becomes possible to recreate from the digital signals the corresponding analog waveform with the required accuracy. The circuit requires only a single supply voltage, is inherently balanced and provides high-voltage DC isolation. Figure 1 is a diagram showing the spectrum occupied by an ADSL signal; Figure 2 is an exemplary waveform diagram of an ADSL signal; Figure 3 is a circuit diagram of a prior art ADSL driver; Figure 4 is a circuit diagram of an improved prior art ADSL driver; Figure 5 is circuit diagram of one embodiment of an ADSL driver in accordance with present invention; Figure 6 is a circuit diagram of another embodiment of an ADSL driver in accordance with the present invention; Figure 7 is a diagram illustrating multiple signal levels produced in response to different logical combinations of signals of a binary signal pair; Figure 8 is a block diagram of one embodiment of a sigma-delta modulator that can be used with the present invention; and Figure 9 is a block diagram of another embodiment of a sigma-delta modulator that can be used with the present invention. Referring now to Figure 5, a block diagram is shown of a line driver circuit in accordance with an exemplary embodiment of the present invention. A digital signal processor or the like produces a signal composed of digital samples of a high crest-factor, e.g., DMT/ ADSL, communications signal. The communications signal is input to a sigma-delta modulator. Preferably, the sigma-delta modulator is second order or higher. The sigma-delta modulator produces one or more pairs of digital output signals. In the example of Figure 5, the sigma-delta modulator produces a single pair of digital output signals, signals A and B. Two signals yield four possible logic combinations. One of these combinations, however, is redundant. That is, the effect of a 11 logic combination is the same as the effect of a 00 logic combination. The circuit of Figure 5 is therefore described as a three-level ADSL driver, with the logic combinations corresponding to the different levels as shown. The digital output signals are buffered in respective logic buffers and filtered, if necessary, using respective low-pass filters to remove switching noise caused by the sigma-delta modulator. The pair of digital output signals is then applied across a primary winding of a transformer. In an exemplary embodiment, the transformer is a 1:2 transformer having a primary winding of some number of turns and a secondary winding having twice the number of turns. In general, the turns ratio is set so as to achieve a desired output level on the communications line, having a standard 120 ohm impedance, for example. Figure 6 shows a five level ADSL driver in which the sigma delta modulator produces two pairs of signals, AB and CD. Although circuits having a still greater number of levels are readily achievable, five levels has been found to be sufficient for purposes of the present ADSL standard. After buffering and filtering, each pair of digital output signals is then applied across a primary winding of a transformer. In an exemplary embodiment, the transformer is a 1:1:2 transformer having a first primary winding of some number of turns, a second primary winding of the same number of turns, and a secondary winding having twice the number of turns. The output signal induced in the secondary winding is the result of superposition of the signals in the first and second primary windings. That is, the first and second pairs of signals are summed in the transformer. Referring to Figure 7, the effect of applying to a primary winding a pair of digital output signals consisting of offset positive-going pulses is shown. During a first interval, the positive-going pulse at terminal 701 of the primary produces a positive-going pulse at terminal 705 of the secondary. During a second intervening time interval between the two pulses, the terminals 701 and 703 of the primary are at the same voltage level with the result that no current flows through the primary and no voltage is produced in the secondary. During a third time interval, the positive-going pulse at terminal 703 of the primary produces a negative-going pulse at terminal 705 of the secondary. The three resulting voltage levels produced at terminal 705 of the secondary are voltages corresponding to weights of + 1 , 0 and -1, respectively. When multiple primary windings are coupled to a single secondary winding, a signal summation occurs. A plus 1 and a plus 1 sum to a plus 2. Likewise, a minus 1 and a minus 1 sum to a minus 2. Possible outputs on the secondary side therefore include -2, -1, 0, + 1 and +2. The task of the sigma delta modulator is to apply a sequence of these possible outputs to be applied to the secondary in such a way as to reproduce the digital input signal. An example of a sigma delta modulator for performing the foregoing function is shown in Figure 8 for the three-level case. The sigma delta modulator is second order, although higher orders can be used. Within the feedforward path, there are a first summer, a first accumulator Rl (e.g. , 15-bit), a divide-by-two block, a second summer, a second accumulator R2 (e.g., 14-bit), and quantizing logic. The quantizing logic divides the contents of the accumulator R2 by 1024. The result may range from -1 to 3. If the result is greater than two, then the quantizing logic outputs the value 2. If the result is negative, then the quantizing logic outputs a zero value. Otherwise, the quantizing logic outputs the contents of the accumulator R2. The resulting output signal T of the quantizing logic is a three level output signal having the possible levels 0, 1 and 2. In the feedback path, the signal T is multiplied by 1024 and the result applied to the negative input of the first and second summers. The signal T is applied to a logic transform block. The logic transform block is responsive to the three-level signal to produce a corresponding signal pair AB to be applied to the transformer primary. Figure 9 shows the corresponding circuit for the five-level case. In the five-level case, the quantizing logic produces an output signal T having five possible levels, 0, 1, 2, 3, and 4. In particular, the quantizing logic divides the contents of the accumulator R2 by 1024. The result may range from -1 to 6. If the result is greater than four, then the quantizing logic outputs the value 2. If the result is negative, then the quantizing logic outputs a zero value. Otherwise, the quantizing logic outputs the contents of the accumulator R2. The resulting output signal T of the quantizing logic is a five-level output signal having the possible levels 0, 1, 2, 3 and 4. The signal T is applied to a logic transform block. The logic transform block is responsive to the five-level signal to produce two corresponding signal pairs AB and CD to be applied to respective transformer primary windings. The circuits of Figure 5 and Figure 6, or circuits of the type shown in Figure 5 and Figure 6, have several desirable properties. Unlike prior art circuits, circuits of this type require only a single power supply. A supply voltage in the range of 5-10V is sufficient, especially given the availability of voltage step-up through the transformer. The transformer provides high- voltage DC isolation, a requirement in any case. Whereas prior-art circuits use a transformer expressly for that purpose, in the circuits of Figure 5 and Figure 6, the transformer is needed for the summation function but additionally provides the needed isolation. Another important advantage of the circuits of Figure 5 and Figure 6 is that the circuit is inherently balanced. That is, a -1 is produced by a positive-going pulse just as is a + 1. The switches used to produce the respective pulses may therefore be very closely matched. This inherent balance avoids the asymmetry problem experienced in Class D amplifier circuits, for example. Most notably, since the sigma-delta modulator uses low-loss switches, it dissipates approximately a factor of six less power than the prior art circuit of Figure 4, 0.5W as compared to 3W. As a result, a central office can be expected to accomodate six times as many line drivers, enabling demand to be more readily satisfied.

Claims: What is claimed is: 1. A line driver circuit having a digital input signal and an analog output signal coupled to a communications line, comprising: a sigma-delta modulator responsive to the digital input signal for producing at least one pair of digital signals; and a transformer having at least one primary winding and a secondary winding, the pair of digital signals being applied to the primary winding, the secondary winding being coupled to the communications line. 2. The apparatus of Claim 1, wherein the sigma-delta modulator produces multiple pairs of digital signals, the transformer comprising multiple primary windings, each pair of digital signals being applied to a respective primary winding. 3. The apparatus of Claim 2, wherein the sigma-delta modulator produces a multi-level signal having at least three levels. 4. The apparatus of Claim 5, further comprising logic responsive to the multi-level signal for producing the multiple pairs of digital signals. 5. The apparatus of Claim 1 , wherein the sigma-delta modulator produces a multi-level signal having at least three levels. 6. The apparatus of Claim 5, further comprising logic responsive to the multi-level signal for producing the pair of digital signals. 7. A method of driving a complex analog signal on a subscriber line, comprising: receiving a digitized signal representing the complex analog signal; performing sigma delta modulation of the digitized signal to produce a multi-level signal having at least three levels; and coupling the multi-level signal to the subscriber line through a transformer. 8. The method of Claim 7, wherein the sigma-delta modulator produces multiple pairs of digital signals, the transformer comprising multiple primary windings, each pair of digital signals being applied to a respective primary winding. 9. The apparatus of Claim 8, wherein the sigma-delta modulator produces a multi-level signal having at least three levels. 10. The apparatus of Claim 9, further comprising using logic to transform the multi-level signal, producing the multiple pairs of digital signals. 11. The apparatus of Claim 7, wherein the sigma-delta modulator produces a multi-level signal having at least three levels. 12. The apparatus of Claim 11, further comprising using logic to transform the multi-level signal, producing the pair of digital signals. 13. Apparatus comprising: a digital signal representing an analog waveform; and means responsive to the digital signal for producing at least one pair of signals representing the analog waveform. 14. The apparatus of Claim 13, wherein said means produces multiple pairs of signals representing the analog waveform. -ills. The apparatus of Claim 14, further comprising a transformer having a secondary winding and multiple primary windings, each primary winding being coupled to one of the multiple pairs of signals. 16. The apparatus of Claim 15, wherein the secondary winding drives a subscriber line. 17. Method comprising: receiving a digital signal representing an analog waveform; and responsive to the digital signal, producing at least one pair of signals representing the analog waveform. 18. The method of Claim 17, further comprising producing multiple pairs of signals representing the analog waveform. 19. The method of Claim 18, further comprising coupling one of the multiple pairs of signals to respective primary windings of a transformer having a secondary winding and multiple primary windings. 20. The method of Claim 19, further comprising driving a subscriber line using the secondary winding.

Inventors: MCCUNE EARL W, SANDER WENDELL, MCCUNE, EARL, W., SANDER, WENDELL
Applicants: MCCUNE EARL W, SANDER WENDELL, TROPIAN INC, MCCUNE, EARL, W., SANDER, WENDELL, TROPIAN, INC.
Application year: 2000
Main classification: H04L27
IPC codes: H04L27