HIGH DENSITY SUBSTRATE AND METHODS FOR MANUFACTURING SAME

Abstract: This invention concerns ultra-thin metal layer containing substrates useful for manufacturing high density circuits as well as novel methods for using the substrates to manufacture laminates, circuits, interposers, and other electronic laminates.

Description: SPECIFICATION (Case No. 30-4805) TITLE: High Density Substrate and Methods For Manufacturing Same BACKGROUND OF THE INVENTION This application is a continuation-in-part of co-pending U.S. Patent Application Serial No. 09/075,736, filed on May 1 1. 1998, which claims priority to U.S. Provisional Patent Application Serial No. 60/047,019, filed on May 13, 1997. This application hereby incorporates the entire specification of prior copending U.S. Patent Application Serial No. 09/075,732 herein by reference. (1) Field of the Invention This invention concerns substrates useful for manufacturing high density circuits as well as novel methods for using the substrates to manufacture laminates, circuits, interposers, and other electronic laminates using fewer steps in comparison to standard panel plating and pattern plating techniques. (2) Description of the Art The electronics industry continues to seek enhanced product performance in order to meet consumer demand for higher functionality, lower cost computers and electronics equipment. Among the means the electronic industry can use to increase system performance, is by the design of circuit boards that have smaller, finer circuit lines and spaces. Increasing line density leads to fewer circuit layers resulting in smaller electronic devices. Finer features are required on printed wiring board substrates as well as in interposer applications within chip packaging. As the electronic industry migrates towards small surface mount packaging with area array interconnect technology, routing I/O signals within a motherboard become very challenging due to the package fine pitch solder ball connections. As solder ball pitch decreases, escape circuits routed between ball pads must narrow to maintain electrical isolation. Not meeting such requirements requires circuit designed to use blind vias and added circuit layers thereby incurring higher costs. Likewise, the surface mount chip packaging interposers themselves have significant challenges. Producing substrates capable to route wire bond or flip chip connections in excess of 1000 inputs and outputs will lead to increased escape routing constraints. Without finer line capability, added circuit layers and added cost w ill have to be incurred to route from the die to the package solder balls Traditionally substrates used in pπnted wiπng board manufacturing and in creating chip packaging interposers, consist of glass reinforced resin composite laminates capped w ith copper foil sheeting Laminates are manufactured by pressing copper foil sheets to a glass cloth reinforced resin The copper foil serves as a seed layer for forming circuits on the laminate surface Foils typically used ithin high density circuit formation are electroplated films formed w ith a rough surface to embed "teeth" into the laminate enhancing the electroplated foil adhesion Ho er. this rough surface has a disadvantage, the foil roughness and embedded copper impose difficulties in etching circuits Etching copper bet een fine circuit traces is difficult because the roughness approaches the dimensions of the circuit In addition, to completely remov e the teeth, longer and more severe etch conditions are required, impacting line quality Clearlv alternativ e substrate technologies are required to meet the ever increasing demand in finer circuit features. SUMMARY OF THE INVENTION This invention includes efficient methods for manufacturing electronic substrates using thin metal clad laminates. This invention also includes electronic substrates manufactured from thin metal clad laminates. In addition, this invention includes methods for manufacturing electronic substrates with fine conductors. In one embodiment, this invention includes electrical substrates prepared from a metal clad laminate. The substrates comprise a carrier film, a release agent layer covering the surface of the carrier film, wherein the release agent layer comprises an aqueous soluble polymer and is capable of being mechanically peeled from the carrier layer; and a conductive metal layer having a thickness no greater than 10,000 Angstroms. In another embodiment, this invention includes A method for forming at least one circuit trace on an electrical substrate using a metal-clad laminate. The method comprises the steps of adhering a metal clad laminate comprising a carrier film, a release agent layer covering the surface of the carrier film, wherein the release agent layer comprises an aqueous soluble polymer and is capable of being mechanically peeled from the carrier layer, and a conductive metal layer having a thickness no greater than 10,000 Angstroms to a reinforced resin layer to form an electrical substrate. The carrier film is removed from the clad substrate. At least one via is introduced into the clad substrate and a photoresist layer is applied to a surface of the clad substrate. The photoresist layer is exposed and developed to expose a first portion of the conductive metal layer and to cover a second poπion of the conductive metal layer. The exposed first portion of the conductive metal layer and at least one via is electroplated with a conductive material. The remaining resist layer is removed from the metal clad laminate to expose the second portion of the conductive metal layer, and the metal clad laminate is flash etched to remove the exposed second poπion of the conductive metal layer from the laminate. In still another embodiment, this invention includes a method for forming at least one circuit trace on an electrical substrate using a metal-clad laminate. The method comprises the steps of adhering a metal clad laminate comprising a carrier film, a release agent layer covering the surface of the carrier film, wherein the release agent layer comprises an aqueous soluble polymer and is capable of being mechanically peeled from the carrier layer, and a conductive metal layer having a thickness no greater than 10,000 Angstroms to a reinforced resin layer to form an electrical substrate. At least one via is introduced into the clad substrate. The carrier film is removed from the clad substrate and photoresist layer is applied to a surface of the clad substrate. The photoresist layer is exposed and developed to expose a first portion of the conductive metal layer and to cover a second portion of the conductive metal layer. The exposed first poπion of the conductive metal layer and at least one via is electroplated with a conductive metal. Then the remaining resist layer is removed from the metal clad laminate to expose the second poπion of the conductive metal layer. Finally, the Clad laminate is flash etched tn remove the expn r l ςpr.nnd pnrrinn nf trie-- -u3dii ti £-mpfal- layer from the laminate. DESCRIPTION OF THE FIGURES Figure 1 is a cross-sectional illustration of a metal-clad laminate intermediate constructed in accordance with the present invention; Figure 2 is a cross-sectional illustration of an alternative metal-clad laminate constructed in accordance with the present invention; Figures 3-6 illustrate cross-sectional views of alternative embodiments of the invention; Figures 7A-7K illustrate an embodiment of a pattern plating process including prior art steps that are superfluous as a result of using the metal clad laminates of this invention in the process; Figures 8A-8K illustrate an embodiment of a simplified pattern plating process including prior an steps that are superfluous as a result of using metal clad laminates of this invention in the process; and Figures 9A-9K illustrate an embodiment of a pattern plating process including the prior art steps that are superfluous as a result of using metal clad laminates of this invention in the process. Figure 10 is a circuit cross-section using 5 μm foil as prepared in Example 11. 5 Figure 1 1 is a circuit cross-section using 0.6 μm cladding as prepared in Example 1 1. DESCRIPTION OF THE CURRENT EMBODIMENT The present invention is directed toward very ultra thin metal conductive layers which are formed by vapor deposition or sputtering of the conductive metal on a polymeric or metal carrier 10 film which has been coated with an organic polymeric release agent. The metal conductive layer can then be bonded to a printed wiring board substrate, such as an epoxy based laminate. Then the carrier film can be separated from the polymeric release agent, leaving the metal conductive layer bonded to the substrate. Using this approach, conductive metal layers in the range of 0.005 μm to 1.0 μm (50 to 10,000 Angstroms) become practical. -4-5- — In-ae€θfdancc with the present invention, a metal-clad laiiiinate piυducl fυi use in the manufacture of printed circuit boards can be made including a polymer or metal foil carrier layer, a polymeric paπing layer formed on the carrier film, a very ultra thin metal layer formed on the release agent layer. Shown in Figure 1 is a metal-clad intermediate 10 made in accordance with the present invention. The intermediate 10 is made up of a carrier film 1 1 to which is applied a 20 polymeric release agent layer 12, onto which is applied a very ultra thin conductive metal layer 13. Shown in Figure 2 is an alternative embodiment of such a metal clad laminate product here designated 20. In the embodiment of Fig. 2, a carrier film 21 has applied to it a polymeric release agent layer or parting layer, 22. Onto the release agent layer 22 is deposited a primary 25 very ultra thin conductive metal layer 23. On top of the primary metal layer 23 is a secondary metal layer 24, also preferably formed by sputtering or vapor deposition. Shown in Fig. 3 is an alternative embodiment metal clad intermediate 30 is illustrated which includes a carrier film 31 , a release agent or paπing layer 32, and a primary very ultra thin conductive metal layer 33. Also deposited on the metal layer 33 is an adhesion layer 35. Shown in Fig. 4 is another embodiment which includes in a metal clad intermediate 40, a earner film 41, a release agent layer 42, a very ultra thin primary metal layer 43, a secondary metal layer 44 and an adhesive layer 45. Shown in Fig. 5 an alternative metal clad intermediate 50 is shown which includes a carrier film 51 , a release agent layer 52, a very ultra thin primary metal layer 53, and an adhesion layer 54. This embodiment also includes two layers of circuit board resin laminate material, or pre-preg, designated here 56 and 57. Shown in Fig. 6 is another alternative metal clad intermediate 60 including a carrier film 61 , a release agent layer 62, a primary metal layer 63, a secondary metal layer 64, an adhesion layer 65, and two layers of resin laminate materials 66 and 67. These alternative embodiments are illustrated and discussed to exemplify the wide van ation in selection and number of layers that can be used to assemble such lntermedia es. Preferably, the carrier film comprises a flexible, dimensionally stable material with good tear and chemical resistances. The carrier film should be able to tolerate above-ambient temperatures. Preferably, the carrier film is made of a material having low absorbed moisture and residual solvent, because water and solvents can interfere with the metallization step. Suitable materials include polymeric film or metal foils. A metal foil is preferred because metal foils tend to have high tensile strength at elevated temperatures, low absorbed moisture, and low residual solvent. The carrier film employed in the examples below was an electroplated copper foil, a polyimide film, or a polyester film. Other metal foils that would make suitable carrier films include rolled or electrodeposited metal and metal alloys including steel, aluminum (Alcoa, AllFoils), and copper (Gould Inc., Oak Mitsui 30 Inc.). It is expected that certain polymeric films would be suitable for the practice of the present invention. Examples of suitable polymeric films include polyesters such as polyethylene terephthalate, poly-butylene terephthalate and polyethylene naphthalate (Kaladex® ICI America), poly-propylene, ιnyl fluoride (Tedlarg DuPont), polyimide (Kaptong, DuPont, Upilex UBES Industπes), and nylon (Capran'S, Al edSignal) The release agent layer ( 1 1 in Fig 1 , 21 in Fig 2, 31 in Fig 3, etc ) is used to facilitate remov al of the earner film from the very ultra thin metal layer In order to avoid the problem of picking, which results in incomplete transfer of the very ultra thin metal foil to the substrate under lamination, the release agent layer is designed to peel at the interface between the parting layer and film earner The partmg layer is subsequently removed with the aid of a plasma, an oxidating environment, intense light, or an appropπate solvent Preferably, the layer is removed by washing with a solvent, most preferably an aqueous solution In methods that lack a release agent layer, and methods that employ a release agent layer that peels at the interface between the parting layer and the very ultra thin metal layer, incomplete transfer of the metal of the very ultra thin metal foil to the substrate commonly occurs The parting layer (12 m Fig 1 , 22 in Fig 2, etc ) is made of a polymenc matenal Preferably, the parting layer is an aqueous-soluble mateπal to facilitate its convemence removal from the very ultra thin metal layer Because photo resists are developed in an alkaline environment, it would be most preferable to use a parting layer that is soluble in an alkaline aqueous solution A useful polymer is one that is of a good film-forming matenal. The polymer can be coated from water with the aid of a volatile base such as ammonium hydroxide to aid solubility Optionally, the partmg layer compπses a water-soluble surfactant to improve solution wetting properties, and to control drying defects As detailed in the examples below, one useful release agent, or partmg layer, is applied as a formulation compπsmg a polyvmylpyrro done (PVP) polymer, a surfactant, and water. The wet weight composition of the partmg layer formulation descπbed in the examples is 10% PVP and 0 5% surfactant It is expected that formulations contaimng PVP in the range of from about 1% PVP to about 50% PVP, and surfactant tn the range of from about 0% surfactant to about 5% surfactant would also be suitable for the practice of the present in ention Preferred PVPs for use m the present invention have a molecular weight in the range of about 10,000 to about 5,000,000. It is reasonable to expect that a release agent layer comprising a polymer such as acid modified acrylic polymers, acrylic copolymers, urethanes. and polyesters, carboxylic acid functional styrene acrylic resins (S.C. Johnson Wax, JoncrylS), polyvinyl alcohols (Air Products & Chemicals, Airvoi ), and cellulose based polymers could be successfully employed in the practice of the present invention. Other suitable water soluble surfactants that could be used to in the parting layer of the present invention include alkylarylpolye-her alcohols (Rohm & Haas, Triton® XI 00), glycerin, ethoxylated castor oil (CasChem Inc., Surfactols® 365), and fluoroaliphatic polymeric esters (3M Corporation, Fluorad∑ 430). The release agent layer formulation is applied in an amount sufficient to achieve a dry weight of from about 10 mg/ft 2 to about 1000 mg/f 2 , about 0.1 μm to 10 μm in thickness. Preferably, the release agent layer formulation is applied in an amount sufficient to achieve a dry weight of from about 100 mg/ft 2 to about 400 mg'ft", about 1 μm to 4 μm in thickness. As described in detail in the examples, a thin primary conductive metal layer (13 in Fig. 1, 23 in Fig. 2, etc.) can be deposited onto the parting layer by sputtering using a Desk HI (Denton Vacuum), or a 903 M (MRC) sputtering unit. It is expected that any sputtering or vapor deposition method known in the art may be successfully used in this invention. The primary metal layer is used as a plating seed layer for subsequent circuit formation. In the examples below, the metal layer was made from gold, chrome, or copper. Other suitable metals include, but are not limited to, tin, nickel, aluminum, titanium, zinc, chromiurrj-zinc alloy, brass, bronze, and alloys of the same. The metal layer may be made from a mixture of suitable metals. The primary layer is from about 0.005 mμ (50 .Angstroms) to about 1.0 μm (10,000 Angstroms) in thickness. Most preferably the primary layer has thickness of from about 0.1 μm to about 0.3 μm (1000 to about 3000 Angstroms). Optionally, a secondary metal layer (such as layer 24 in Fig. 2, 44 in Fig. 4 or 64 in Fig. 6) may be employed to protect the primary layer from oxidation, to increase adhesion during lamination, or to act as a barrier to metal migration. The secondary layer may be from about 0.001 μm (10 Angstroms) to about 0.1 gm (1000 Angstroms) in thickness. Most preferably the secondary layer has thickness of from about 0 01 μ ( 100 Angstroms) to about 0 03 μm (300 Angstroms) To form the secondary metal layer, a layer of zinc, indium, tin, cobalt, aluminum, chrome, nickel, nickel-chrome, brass, or bronze is deposited on the first metal layer Other suitable metals include magnesium, titanium, manganese, bismuth, molybdenum, silver, gold, tungsten, zirconium, antimony, and chromium-zinc alloys. The secondary metal layer prev ents the metal in the first metal layer from oxidizing after removal from the metallizing chamber, and increases adhesion to thermosetting resin systems Optionally, an adhesion layer (e.g. 35 in Fig. 3, 45 in Fig. 4. etc.) can be applied to the metal layer. The adhesion layer may be employed m order to increase the bond between the metal layers and the substrate layers following lamination. The adhesion layer may be organic, organometallic, or inorganic compounds, and applied to a thickness of 0.0005 μm (5 Angstroms) to 10 μm (100,000 Angstroms). Multiple layers may be used such as an organometallic layer followed by an organic layer. Typically when an organometallic layer is used such as a silane, the coating will be from 0.0005 μm (5 Angstroms to 0.005 j im (^00 Angstroms) in thickness. When using organic adhesion layers, such as thermoplastics, thermoseπing polymers, or mixtures, the coating would be 0 1 μm ( 1000 Angstroms) to 10 μm (100,000 Angstroms) in thickness. Useful organometallic compounds include materials based on zirconium, titanium, and silicon. Silicon based organometallics, known as silanes or coupling agents, are widely used and available. The coupling agent may be applied neat or applied after dissolving it in an appropriate solvent Suitable coupling agents typically have a sύane-hydrolyzable end group with alkoxy, acyloxy, or amine functionality, and an organofunctional end gτoup. The hydrolyzable end group reacts with the metal surface while the organofunctional group bonds to the substrate layer to which the metal is laminated. Coupling agents can be subjected to a hydrolysis reaction prior to coating if dissolved in an acidic medium. Useful coupling agents include compounds such as N-(2-am oeώyl)-3aminopropyltrimethoxy silane (Dow Corning, Huls America Inc.) and 3-Glycidoxypropyltrimethoxy silane (Dow Corning, Huls America Inc.). Organic adhesion layers consisting of thermoplastics, thermosetting polymers, or mixtures are appropriate adhesion layers. These adhesives can be based on polyimide resins, epoxy resins, polyester resins, acrylic resins, butadiene rubbers, and the like. One useful adhesive consisting of a polyester epoxy system is available (Cortaulds, Z-Flex™). Resin layers can be applied to the metal layer or to the adhesive layer (if present) in uses where a controlled dielectric thickness is required. Such uses include built up technologies. Typically the resins are thermosetting systems that are coated from an appropriate solvent. After drying, the resins can be cured to a semi-cured state if additional cure is required before lamination to a circuit board. A single semicured resin layer can be used. Preferably, two resin layers are used where the first resin layer down (primary layer) is cured to a greater extent than the second resin layer. The first resin layer serves as a controlled dielectric spacing layer and has a thickness of from about 5 to about 500 μms, preferably from about 20 to about 50 μms. Appropriate resin systems include (but are not limited to): epoxy resins cured by phenolic or iicyandiamide hardeners, cyanate esters, bismaleimides. and polyimide systems. The second layer can have a different composition than the primary layer; however, to attain good interlayer adhesion, it is preferable that the composition of the second layer is similar to that of the first resin layer. The second resin layer serves as an adhesion layer and as a void filling layer during lamination and has a thickness between 5 and 500 μm, preferably between 20 and 50 μm. By "laminating under suitable lamination conditions" it is meant laminating under appropriate conditions of temperature and pressure for a suitable period of time to adhere the layers together for practical use in making a circuit board laminate. The metal clad laminates of this invention are useful in the manufacture of various types of electronic substrates. The laminates are also useful for manufacturing single sided rigid substrates, double sided layer pairs useful as chip packaging interposers, and use with built-up technologies. For example, one or more of the laminates may be incorporated into a multilayer printed wiring board. The laminates of this invention are typically incorporated into technical components by various plating process including the panel plating and pattern plating processes with or without the introduction of vias into the substrate under manufacture. In fact, the laminates are preferably used in panel and pattern plating process to produce multilayer electrical substrates. The use of laminates of this invention in pattern plating process allows the number of steps in the prior processes to be reduced. Therefore, an aspect of this invention are novel panel plating and pattern plating process using laminates of this invention. Figures 7-9 simplify novel panel and pattern plating processes that use the laminates of this invention. Each processes begin with a clad substrate 100. Clad substrate 100 consists of a sandwich including opposing carrier film layers 101 , release agent layers 102, both within a conductive metal layers 103, optional secondary metal layer 104, and optional adhesion layer 105. The layers are each associated with a resin reinforced core layer 107 wherein two resin reinforced layers are adhered to one another to form core 107. -Ue ^ZB, the carrier film 101 is removed from dad-sub tr te---nd^e-r-e4ease-ag-ea ay^r- 102 is removed as described above to expose ultra thin conductive metal layers 103 in step 7C. A via 110 is drilled or lased into clad substrate 100. In a departure from the prior an process, a photo resist 111 is applied to ultra thin conductive metal layers 103 and to cover via 110. In step 7F, the photo resist is exposed and developed to produce an exposed first poπion of this ultra thin conductive metal layer 103 corresponding to a circuit pattern 112 and a covered second poπion 1 15 of ultra thin conductive metal layer 103. In step 7G, the via 110 is electroplated along with the exposed circuit traces to give an electroplated layer 114. Figure 7H depicts a step in the prior an wherein an etch resist would typically be applied to the desired circuit traces. However, because the ultra thin conductive metal layer 103 is so thin, the remaining resist layer may be removed in step 7i to expose second portion 115 of ultra thin metal layer 103 and the clad substrate is flash etched in step 7J to remove any exposed non-built-up second portions 115 of ultra thin conductive metal layer 103. The flash etching is achieved by spraying, dipping, coating commercially available etchants such as persulfates or ferrous chlorides. Flash etching step 7J also eliminates the prior an step shown in Figure 7K which consists of removing the etch resist that normally would have been applied to the circuit trace in prior an step 7H. The flash etching product shown in Figure 7j is a layer pair including a first circuit 1 16 and a second circuit 116'. Figure 8 shows an alternative pattern plating method that uses the advantages of the laminates of this invention to reduce the number of steps necessary to produce a laminate including one or more circuit traces. The process of Figure 8 is identical to the process of Figure 7 except that release agent layer 103 is not removed in step 8C as it is in step 7C. Instead, a via 110 is drilled in the clad substrate and step 7D, the photo resist is applied in step 7E and exposed in step 7F. The exposure and developing of the photo resist is also removes the paπing layer portion corresponding to the removed photo resist poπion thereby exposing a first poπion 1 12 of ultra thin conductive metal layer 103 that corresponds to a circuit trace. Vias 110 and the circuit traces are electroplated in step 8G. The step of applying an etch resistant in step 8H is omitted and the remaining paπing layer is removed in step 8i to expose the covered second poπion 1 15 of ultra-thin metal layer 103. Finally, the exposed second poπion 115 of ultra thin conductive metal layer 103 is flash etched from the substrate including the desirable circuit traces. Figure 9 depicts a pattern plating-drill enhancing process of this invention using the metal clad substrates of this invention. An important aspect of the process is step 9b in which a via 110 is drilled or lased into clad substrate 100 without removing carrier film layers 101 or release agent layer 102. Once via 1 10 is located in clad substrate 100, carrier film layer 101 and the release agent layer 102 may be removed as in steps 9C and 9D. Next a photo resist is applied to the ultra thin conductive metal layer, and exposed and developed to form circuit traces in steps 9E and 9F. The circuit traces and via 110 are electroplated with a conductive metal in step 9G. At this point, no etch resistant needs to be added would be the case with prior an methods. Instead, the resist is stripped and the substrate is flash etched to remove ultra thin conductive metal layer 103 and any optional secondary metal layer 104 and the adhesion layer 105. The following nonlimiting examples are intended to be purely illustrative. Example 1 Upilex® 50 um polyimide film was obtained from the Ube Industries for use as the carrier film. 0.15 μm ( 1500 Angstroms) of copper was sputtered coated, followed by 0.01 μm ( 100 Angstroms) of a nickel-chrome alloy. The sample was pressed to make a circuit board laminate. Four layers of an FR-4 pre-preg known as FR406(AlliedSignal) was placed on a glass reinforced Teflon® sheet. Under the sheet was a stainless steel press plate. The above construction was placed metal side down on the FR4O6 pre-preg. A second layer of glass reinforced Teflon® sheet was placed on the top and covered with a second stainless steel press plate. The stack was placed in a pre-heated press at 350°F and pressed for 1.2 hours at 50psi. Attempts were made to peel the film, but peeling was difficult. Peel strength was measured at an ang le of 180° and found to vary between 1 -5 lbs./in. Sections of the metal coating approximately 100 μm in size did not transfer and were left on the film. The above was performed a second time, and it was determined that the metal coating would not peel from the film carrier. Metal adhesion to the film was high enough to cause the film to tear during a peel attempt. Example 2 A sample of 1 oz. electroplated copper foil was obtained from Gould Inc. for use as a carrier film. A release agent layer was formed by coating parting layer formulation PI (Table 1) onto the copper carrier layer using a No. 18 wire-wound rod. Following application to the carrier film, the release agent layer was dried at 160°C for about 2 minutes. The coating was clear. A gold metal conductive layer was sputtered onto the clear parting layer using a Desk HJ sputtering unit with air as the processing gas. Gold was deposited for 3 minutes. Examination an edge of the gold coating by microscopy revealed that a gold layer of approximately 0.3 μm (3000 Angstroms) in thickness was deposited. The sample was pressed to make a circuit board laminate. Four layers of an FR-4 epoxy based pre-preg known as FR406 (AlliedSignal) was placed on a glass reinforced Teflon®) sheet. Under the sheet was a stainless steel press plate. The above construction was placed metal side down on the FR406 pre-preg A second laver of glass reinforced Teflon® sheet was placed on the top and cov ered with a second stainless steel press plate. The stack was placed in a preheated press at about 350°F and pressed for about 1.2 hours at 50psι After cooling to room temperature, the copper earner film peeled easily revealing the parting layer transferred completely with the metal coating Washing the surface in warm water removed the release agent layer and revealed a shiny metal surface Table 1. Composition of parting layer formulation PI I Component | Source Amount Polyvinvlpyrrolidone, PVP-K90 ISP Technologies 5 00B Surfactol 365 I CasChem 0 025g Water | 44.975s Example 3 A sample of 1 oz. electroplated copper foil was obtained from Gould Inc for use as the carrier film. A release agent layer was formed by coating formulation PI (Table 1) onto the copper earner film using a No 18 wire-wound rod. Following application to the earner film, the parting layer was dried at 160°C for about 2 minutes. The coating was clear. A gold release agent layer was dried at 160°C for about 2 minutes. The coating was clear. A gold metal conductive layer was sputtered onto the clear partmg layer using a Desk ITI sputtering unit with air as the processing gas. Gold was deposited for 3 minutes Examination an edge of the gold coating by microscopy revealed that a gold layer of approximately 0.3 μm (3000 Angstroms) in thickness was deposited. The sample was pressed to make a circuit board laminate. Four layers of ar, FR-4 epoxy based pre-preg known as FR406 (AlliedSignal) was placed on a glass reinforced Teflon® sheet. Under the sheet was a stainless steel press plate. The above construction was placed metal side down on the FR406 pre-preg. A second layer of glass reinforced Teflon® sheet was placed on the top and covered with a second stainless steel press plate. The stack was placed in a pre-heated press at about 350°F and pressed for about 1.2 hours at 50psi. After cooling to room temperature, the copper carrier film peeled easily revealing the parting layer transferred completely with the metal coating and resin layers. Washing the surface in warm water removed the parting layer and revealed a shiny metal surface. Table 2. Composition of resin formulation Rl. Table 3. Composition of parting layer formulation P2. i Component j Source Amount ! Polyvinylpyπ-olione, PVP-K120 ISP Technologies 5.00B TSurfacloi its CasLhem 0.25g i Water 1 44.975g This formulation, P2, differs from PI in the choice of PVP K120, which has a weight average molecular weight of 2,900,000. The PVP used in the Formulation PI was PVP K90, which has a weight average molecular weight of 1,270,000. Higher molecular weight is desirable for coating and film formation while lower molecular weight is desirable for increased layer solubility. Examples 4-7 A sample of 1/2 oz. electroplated high temperature elongation copper foil was obtained from Oak-Mitsui for use as a carrier film. Release agent formulation P2 was coated on the carrier film using a No. 18 wire-wound rod and dried at 160°C for 2 minutes. The coating was clear and measured to be 250mg/fr. Different metal layer combinations are sputter deposited onto the P2 coating using argon as the processing gas: The constructions are of the form illustrated in Fig. 1. An adhesion layer consisting of a silane was coated on the metal layer in example 6 and 7. A solution of Gamma-glycidoxypropyl trimethoxy silane was made to 0.5% in a mixture of methanol and water, where the methanol was 90% and the water was 10%. The solution was coated on the metal surface and dried at 90°C for 1 minute. Each sample was pressed to make a circuit board laminate. Four layers of an FR-4 pre-preg known as FR406 (AlliedSignal) was placed on a glass reinforced Teflon® sheet. Under the sheet was a stainless steel press plate. The above construction was placed metal side down on the FR406 pre-preg. A second layer of glass reinforced Teflon® sheet was placed on the top and covered with a second stainless steel press plate. The stack was placed in a pre-heated press at 350°F and pressed for 1.2 hours at 50psi. After cooling to room temperature, the copper carrier film peeled easily revealing the parting layer transfeπed completely with the metal coating. Washing the surface in warm water removed the parting layer and revealed the shiny metal surface of the conductive layer. The peel force required to remove the carrier layer was measured at an angle of 180° in Example 6 and Example 7. The peel force was determined to be very low and was highly repeatable. Example 6 was measured at 0.025 lbs./in. while Example 7 was measured at 0.015 lbs./in. Example 8 Upilex® 50 μm polyimide film was obtained from the Ube Industries. Release formulation P2 was coated on the carrier film using a No. 18 wire-wound rod and dried at 160°C for 2 minutes. The coating was clear and measured to be 250 mg ft". A gold metal layer was sputtered on the clear coating using a Desk III sputtering unit with air as the processing gas. Gold was deposited for 3 minutes. Examining an edge of the gold coating using a visible microscope revealed 0.3 μm (3000 Angstroms) of gold was deposited. The sample was pressed to make a circuit board laminate. Four layers of an FR-4 pre- preg known as FR406 (AlliedSignal) was placed on a glass reinforced Teflon® sheet. Under the sheet was a stainless steel press plate. The above construction was placed metal side down on the FR406 pre-preg. A second layer of glass reinforced Teflon® was placed on the top and covered with a second stainless steel press plate. The stack was placed in a pre-heated press at 350°F and pressed for 1.2 hours at 50psi. .After cooling to room temperature, the polyimide film peeled easily revealing the parting layer transferred completely with the metal r.nating. waςhipg the surface in warm water removed the parting layer and revealed a shiny metal surface. Example 9 Upilex® 50 μm polyimide film was obtained from the Ube Industries for use as the carrier film. Release formulation P2 is coated on the carrier film using a No. 18 wire-wound rod and dried at 160°C for 2 minutes. The coating was clear and measured to be 250 mg/fr\ A copper metal layer was vapor deposited on the clear coating using a CVΕ vacuum Chamber manufactured by CVC Products, Inc. Copper was deposited for approximately 4 minutes. An adhesion layer consisting of a silane was coated on the metal layer. A solution of Gamma- glycidoxypropyl rrimethoxy silane was made to 0.5% in a mixture of methanol and water, where the methanol was 90% and the water was 10%. The solution was coated on the metal surface and dried at 90°C for 1 minute. The sample was pressed to make a circuit board laminate. Six layers of an FR-4 pre-preg known as FR408 (AlliedSignal) was placed on a glass reinforced Teflon® sheet. Under the sheet as a stainless steel press plate. The above construction was placed metal side down on the FR408 pre-preg. A second layer of glass reinforced Teflon® sheet was placed on the top and covered with a second stainless steel press plate. The stack was placed in a pre-heated press at 350 e F and pressed for 1.2 hours at 50psi. After cooling to room temperature the polyimide film peeled easily revealing the parting layer transferred completely with the metal coating. Washing the surface in warm water removed the parting layer and revealed a shiny metal surface. The peel force required to remove the carrier layer as measured at an angle of 180° and found to be very low at 0.010 lbs./in. and to be highly repeatable. Example 10 A sample of the 1/2 oz. electroplated high temperature elongation copper foil was obtained from Oak-Mitsui for use as a carrier film. Release formulation P2 was coated using a No. 18 wire-wound rod and dried at 160°C for 2 minutes. The coating was clear and measured to be 250 mg/ft 2 . A copper metal layer was vapor deposited on the clear coating using a CVE vacuum chamber manufactured by CVC Products, Inc. Copper was deposited for approximately 4 minutes. The sample was pressed to make a circuit board laminate. Four layers of an FR-4 pre- preg known as FR406 (AlliedSignal) was placed on a glass reinforced Teflon® sheet was placed on the top and covered with a second stainless steel press plate. The stack was placed in a preheated press at 350°F and pressed for 1.2 hours at 50psi. After cooling to room temperature, the copper carrier film peeled easily revealing the parting layer transferred completely with the metal coating. Washing the surface in warm water removed the parting layer and revealed a shiny metal surface. Example 11 Polyester film 2 mil. in thickness was obtained from DuPont for use as a carrier film. A release parting layer formulation shown in Table 4 was prepared and coated on the film using conventional coating technology. After drying at 100°C for approximately 2 minutes the coating was clear. Afterwards the coated film was metalized in a continuous film sputtering system depositing 6000 Angstroms of copper, followed by 100 Angstroms of chrome passivation. The metalized very ultra thin construction was sheeted and prepared for lamination. Table 4. Composition of Parting Layer Component j Source I Amount Polyvinylpyrrolidone, PVP- 120 j ISP Technologies i 500.0 g Surfactol 365 CasChem 2.5g Water 4497.5g The metallized construction was compared against a 5 μm electroplated copper foil supplied on a 72 μm thick copper foil carrier available from Circuit Foils. The 5 μm foil, -being— a--r-^leetropl-rted^oH H-^d--a-rou^h--sur-faee- vith ^ceώ^o— eι.-bedHrto— HaminateT Laminates were prepared with each cladding using Ultrastable™ pre-preg obtained from AlliedSignal Laminate Systems. The foils were laminated to the pre-preg under heat and pressure forming double sided clad substrates with an overall thickness of 200μm (8 mils). A circuit with design rules of 2 mil lines, 2mil spaces, 6 mil drilled holes in 14 mil pads was attempted on each cladding using the pattern plating technique. The very ultra thin clad laminate was prepared by removing the polyester cover sheet and washing the paπing layer in warm water revealing a clean copper surface. The 5 μm clad substrate was prepared by removing its copper foil cover sheet. Each substrate was drilled with conventional technology known in the art forming 6 mil holes. Afterwards, each substrate was passed through conventional desmear and electroless chemistries to clean and seed the hole walls for electroplating. A negative acting dry film photo resist was laminated to each substrate, exposed through a negative, and developed revealing a negative of the circuit. Each substrate was electroplated forming the circuit traces and pads. The resist was stripped and the cladding layers flashed etched forming the isolated traces and pads. The sub micron cladding and the 5 μm electroplated copper foil processed well through plating and resist strip. However, differences became apparent when monitoring the etch process. The panels were passed through the etchant, periodically removed, and studied with optical microscopy. Etching was continued until no foot was apparent at the circuit base and the background between lines was metal free. Panels using the 5 μm copper foil required a 607c increase in etch time compared to the sub-micron technology Etch factors are frequently monitored within the printed wiring board industry to judge circuit quality. Etch factors are determined by taking a circuit cross section and measuring the height and width of a trace. From these measurements, etch factors are calculated as the circuit height divided by the trace width at the base compared to the circuit face. An etch factor is determined using the formula: It Etch Factor = B-T wherein T is the width of a circuit trace at is top; B is the width of the circuit trace base, and t is the circuit trace height. Most circuit patterning processes produce circuits with etch factors from 2.5 to 3.5. Higher quality circuits with straight circuit walls give higher etch factors. The quality of circuit traces using the 5 micron foil were compared to the sub-micron technology. After etching, circuits were cross-sectioned. Optical microscopy was used to examine the circuits, and etch factors were determined. Figure 10 and Figure 11 show typical circuits from the 5 micron foil and the sub-micron cladding. From these images, the high quality of the sub-micron material was apparent. The traces made with the sub-micron copper had vertical line walls with very little slope. The 5 micron sample, however, had comparatively shorter line heights and sloping line side walls. It is believed that this difference results because, with the 5 micron copper, longer etch times are needed to etch through the thicker seed layer and remove embedded teeth. Etch factors were determined for each cladding and are shown in Table 5. The higher quality of the sub-micron samples can be seen from its in a very impressive etch factor of 8.0 in this Example. Table 5. Circuit Line ualit

Claims: What we claim is: 1. An electrical substrate prepared from a metal clad laminate comprising: a carrier film; a release agent layer covering the surface of the carrier film, the release agent layer comprising an aqueous soluble polymer, the release agent layer being capable of being mechanically peeled from the carrier layer; and a conductive metal layer having a thickness no greater than 10,000 Angstroms. 2. The electrical substrate of claim 1 wherein the substrate is selected from the group consisting of a printed wiring board, a laminate including at least one circuit trace, and a laminate including at least one conductive via. 3. The electrical substrate of claim 1 further comprises an adhesive layer on the conductive metal layer on its side opposite from the release agent layer. 4. The electrical substrate of claim 1 further comprising at least one semi-cured res in Ja inateJayer adhered to i c condnr.tivp metal aye. — 5. A method for forming at least one circuit trace on an electrical substrate using a metal-clad laminate comprising the steps of; (a) adhering a metal clad laminate comprising a carrier film, a release agent layer covering the surface of the carrier film, wherein the release agent layer comprises an aqueous soluble polymer capable of being mechanically peeled from the carrier layer, and a conductive metal layer having a thickness no greater than 10,000 Angstroms to a reinforced resin layer to form an electrical substrate; (b) removing the carrier film from the clad substrate; (c) introducing at least one via into the clad substrate; (d) applying a photoresist layer to the surface of the clad substrate; (e) exposing and developing the photoresist layer to expose a first poπion of the conductive metal layer and to cover a second poπion of the conductive metal layer; (f) electroplating the exposed first poπion of the conductive metal layer and at least one via with a conductive metal; (g) removing the resist layer from the metal clad laminate to expose the second poπion of the conductive metal layer; and (h) flash etching the clad laminate to remove the exposed second poπion of the conductive metal layer from the laminate. 6. The method of claim 5 wherein the release layer is removed after the carrier film is removed in step (b) and before the via is introduced into the substrate in step (c). 7. The method of claim 5 wherein the metal clad laminate includes a secondary metal layer located between the conductive metal layer and the reinforced resin layer. 8. The method of claim 7 wherein the secondary metal layer associated with the exposed second poπion of the conductive metal layer is removed from the electrical substrate during flash etching step (h). 9. The method of claim 7 wherein the metal clad laminate includes an adhesion layer-lcκ^t£d--t£t ee-- he^econdary-^ 10. The method of claim 9 wherein the adhesion layer is removed from the electrical substrate during flash etching step (h). 11. The method of claim 9 wherein the adhesion layer is removed from the electrical substrate following flash etching step (h). 12. A method for forming at least one circuit trace on an electrical substrate using a metal -clad laminate comprising the steps of; (a) adhering a metal clad laminate comprising a carrier film, a release agent layer covering the surface of the carrier film, wherein the release agent layer comprises an aqueous soluble polymer that is capable of being mechanically peeled from the carrier layer, and a conductive metal layer having a thickness no greater than 10,000 Angstroms to a reinforced resin layer to form an electrical substrate; (b) introducing at least one via into the clad substrate; (c) removing the carrier film from the clad substrate; (d) applying a photoresist layer to the surface of the clad substrate; (e) exposing and developing the photoresist layer to expose a first poπion of the conductive metal layer and to cover a second ponion of the conductive metal layer; (f) electroplating the exposed first poπion of the conductive metal layer and at least one via with a conductive metal; (g) removing the resist layer from the metal clad laminate to expose the second poπion of the conductive metal layer; and (h) flash etching the clad laminate to remove the exposed second poπion of the conductive metal layer from the laminate. 13. The method of claim 12 wherein the release layer is removed after the carrier film :s removed in step (c) and before the via is introduced into the substrate in step (d). 14. The method of claim 12 wherein the metal clad laminate includes a secondary meta! layer located between the conductive metal layer and the reinforced resin layer. 15. The method of claim 1 whprpin thf .>rnr-Ha._y-__m-> d---la -^^ -the- exposed second poπion of the conductive metal layer is removed from the electrical substrate during flash etching step (h). 16. The method of claim 14 wherein the metal clad laminate includes an adhesion layer located between the secondary metal layer and the reinforced resin layer. 17. The method of claim 16 wherein the adhesion layer is removed from the electrical substrate during flash etching step (h). 18. The method of claim 16 wherein the adhesion layer is removed from the electrical substrate following flash etching step (h). 19. The method of claim 12 wherein the via is introduced into the electrical substrate with a drill or with a laser.

Inventors: ANDROFF NANCY M W, GOTRO JEFFREY T, HEIN MARC, SMITH GORDON, ANDROFF, NANCY, M., W., GOTRO, JEFFREY, T., HEIN, MARC, SMITH, GORDON
Applicants: ALLIED SIGNAL INC, ALLIEDSIGNAL INC.
Application year: 2000
Main classification: H05K3
IPC codes: B32B15, H05K1, H05K3