Rail to rail rectifying integrator

Abstract: A rectifying integrator of an input signal (VIN) with full output dynamic, relative to a voltage reference (VREF) intermediate in respect to the dynamic of the input signal (VIN), the line of integration of which is composed of an integrator of that portion of the input signal that exceeds the voltage reference (VREF) and of a hold capacitor (C 3a ) coupled in cascade to the integrator, includes a second line of integration, identical to the first line of integration, that integrates that portion of the input signal (VIN) that remains below the voltage reference (VREF), and an adder output stage that generates an output signal (VOUT) equal to the difference between the voltages existing on the hold capacitors (C 3a , C 3b ) of the lines of integration first and second.

Description: The present invention relates in general to a circuit for rectifying and integrating a signal relative to an intermediate reference voltage, outputting a rail-to-rail signal. BACKGROUND OF THE INVENTION The document DE 3114770 A 1 discloses a peak-to-peak detector wherein the positive peak and the negative peak are fed to the inputs of an operational amplifier that sums the relative voltage information to produce an output signal. The document US Patent No. 5,614,851 discloses a peak-to-peak CMOS voltage detector having a low power consumption. US Patent No. 4,554,508 describes a carrier detector circuit including a rectification stage, an integrator, a comparator and a digital counter for establishing long time constance without requiring external components. US Patent No. 5,281,860 discloses a method and apparatus for improved multiple channel sensor interface circuits, including a plurality of input integrator circuits, coupled in parallel, a switched capacitor multiplexer coupled to the input integrator circuits and an output integrator stage coupled to the switched capacitor multiplexer. Japanese abstract of application No. 57161948 describes an A/D converter with polarity switching circuit, sample and old circuit and rectifying switched capacitor system. Japanese abstract application No. 60231234 discloses a rectifying and smoothing circuit wherein the full-wave rectified voltage is smoothed and amplified by an arithmetic and a logic amplifier 5 and a switched capacitor. Japanese abstract application No. 60194773 describes a rectifying circuit in which the input signal voltage is sampled and the negative samples inverted to avoid diode dissipation. US Patent 4,109,308 discloses an AC to DC converter which includes two resetable integrators each for sampling an alternate half-wave of the AC voltage to be converted. Rectifying and integrating circuits of an alternating input voltage in respect to a reference voltage are used in many applications and are included in many commercially available devices. A rectifying integrator circuit may be realized, as depicted in the basic scheme of Figure 1, by a rectifier having in cascade thereto an integrator stage and a Sample&Hold stage. However, by using these three blocks alone it is possible to obtain an output voltage that varies between the voltage reference (VREF) and the maximum (or the minimum) input voltage, that is with a reduced dynamic, rather than between the minimum and the maximum input voltage, as it would be preferred. In particular, if the voltage reference corresponds to the intermediate value between the maximum and minimum input voltage V IN , the dynamic of the output voltage is practically halved if compared to the maximum input dynamic. This drawback may be averted by placing in cascade to the three above mentioned blocks, an output stage having a gain value equal to two and which also functions as a level shifter, thus obtaining an output voltage Vout with a full dynamic. The disadvantage of this solution is the fact that a gain stage placed at the end of the cascade sensibly lowers the signal/noise ratio. This problem may be overcome by the use of a switched-capacitor integrator as shown in Figure 2, which also function as a rectifier and level shifter. The input voltage VIN is sampled on the capacitor C1 in respect to the voltage reference VREF. The switches driven by the driving phases Φ 2a and Φ 2b of Figure 2 connect the node of the capacitor C1 at the lowest potential to the inverting node of the operational amplifier, while the other node of the capacitor is connected to a common ground node VGND. Hence, the integration and rectification of the input voltage are carried out simultaneously because the integrating capacitor C2 is always charged with voltages of the same sign, regardless of whether VIN is higher or lower than VREF. The circuit of Figure 2 provides for an output voltage with full dynamic, however it has two drawbacks: the operational amplifier of the integrator functions with an input connected to ground VGND, that is at the lowest voltage, thus originating imprecisions in presence of relatively small input signals; the switches exhibit parasite capacitances which, when discharged, produce currents in opposition to the integrating current, which brings to a below ground potential the inverting input of the operational at the start of each half-period of integration. There exists a need for a rectifying integrator able to produce a full dynamic output voltage free of the above noted drawbacks. OBJECT AND SUMMARY OF THE INVENTION The above noted drawbacks are eliminated by the full output voltage dynamic rectifying integrator of this invention. Substantially, the circuit of the invention consists of a pair of integrators, both referred to an intermediate voltage reference within the dynamic voltage range of the input signal and coupled to a pair of respective hold capacitors, which integrate the part of the input signal that either exceeds the voltage reference or remains below the voltage reference, respectively. The voltages on the respective hold capacitors are eventually combined to produce the desired output voltage. Preferably, the two integrators are combined in a unique integrating stage that is realized according to an offset recovery switched-capacitance technique, using two integrating capacitors coupled to respective hold capacitors at the output to a single amplifier, that are alternatively connected to the integration feedback line of the amplifier depending on whether the input voltage exceeds or remains below the voltage reference. The voltages on the hold capacitors, respectively higher or lower than the voltage reference, are input to a voltage adder which produces an output voltage VOUT corresponding to the difference between the voltages present on the two hold capacitors. The invention is defined in the annexed claims BRIEF DESCRIPTION OF THE DRAWINGS The various aspects and advantages of the invention will be even clearer upon describing in detail few embodiments of the invention and by referring to the attached drawings, wherein: Figure 1 is the functional diagram of a rectifying integrator and of representative signals; Figure 2 illustrates the diagrams of a known switched-capacitor rectifier and integrator and of representative signals; Figure 3a is a basic functional diagram of the circuit of the invention; Figure 3b shows an embodiment of the circuit of the invention Figure 4 illustrates the main signals of the circuit ofFigure 3b; Figure 5 is another embodiment of the circuit of the invention; Figure 6 illustrates the main signals of the circuit of Figure 5. DESCRIPTION OF EMBODIMENTS OF THE INVENTION The basic functional scheme of the circuit of the invention is shown in Figure 3a. The two half-wave rectifiers feed two functionally distinct integrators, both referred to the voltage reference VREF intermediate respect to the voltage range of variation of the input signal Vin, with the portions of the input signal that exceed or are lower than VREF, respectively. Therefore, each integrator is input with a signal that is always of the same order of magnitude of VREF, so that the hold capacitors SAMPLE&HOLD will be charged with voltages of opposite sign and having a dynamic swing that is substantially halved if compared to the dynamic of the input signal. By subtracting the voltages present on the two hold capacitors by an adder we obtain an output voltage VOUT with a maximum dynamic. Preferably, the circuit of the invention is realized using a unique integrator, according to a common switched-capacitance technique in order to eliminate offset effects. Two integrating capacitors are alternatively switched to the line of integration depending on whether the voltage VIN exceeds or is lower than the voltage VREF, causing each capacitor to be always charged at voltages of the same sign. On the output node of the integrator amplifier there will be alternatively two voltages both of a relatively reduced dynamic, one increasing and the other decreasing, which will be stored in the respective hold capacitors. Finally, an adder combines such voltages generating an output voltage of full dynamic. A first practical embodiment of the circuit of the invention is shown in Figure 3b. The switched input capacitor C 1 is alternately connected to the input voltage and to the voltage reference, by driving in phase opposition of two switches, by the two driving phases signals Φ1 e Φ2 A CONTROL_LOGIC circuit generates sub-phases Φ 2a and Φ 2b , of the primary driving phase Φ 2 , in function of the two primary driving phases Φ 1 e Φ 2 and in function of the ratio VIN/VREF. Two integrating capacitors C2a e C2b are alternatively connected to the line of integration of the operational amplifier, by the complementary switching of respective switches driven by the sub-phases Φ2a e Φ2b, as illustrated in the temporal diagrams of Figure 4. Each integrating capacitor is coupled to a respective hold capacitor C3a and C3b connected to the output of the amplifier by way of a switch that is switched after a certain delay from the sub-phase that drives the respective capacitor of integration. In the example of Figure 4, when the input voltage exceeds the reference voltage, the capacitor C2a is charged to an increasing voltage VC3a, while the capacitor C2b is charged to a decreasing voltage VC3b. Two buffers, coupled to respective hold capacitors, feed the voltage supplies to a voltage adder, that generates an output voltage having full dynamic and corresponding to the difference between the two voltages VC3a e VC3b. Alternatively, the circuit of the invention may include a comparator of the voltages VIN and VREF, producing a signal SIGN_VIN that is fed to the control logic as an indication of the current ratio between the input voltage and the voltage reference. If the continuous component of the input voltage is equal to the voltage reference, as shown in the example, the voltages on the two hold capacitances will reach their respective maximum values during consecutive half-periods of integration. However, if the continuous component of VIN does not coincide with VREF, one of the two voltages VC3a or VC3b will reach its respective maximum value before the other, and therefore VOUT will not have the maximum dynamic. The preferred embodiment of the invention, shown in Figure 5, may be used to prevent this problem. This circuit differs from the one of Fig. 3b in that the switched input capacitor is linked to the input line through switches driven by three sub-phases Φ3, Φ4 e Φ5 of the primary driving phase Φ2. In addition, two comparators compare the voltages of the respective hold capacitors with the limit voltages VCC-ΔV e VGND+ΔV, and the produced signals: sat_up e sat_down, signal to the Control_Logic the reaching of the maximum voltage (saturation) on any of the two hold capacitors. As it may be observed in the signal diagrams of Figure 6, the sub-phases Φ3 e Φ4 are complementary and the sub-phase Φ5 is in phase opposition to Φ4. As long as none of the hold capacitors saturates, the sub-phase Φ3 coincides with Φ2 and the circuit of Figure 5 functions exactly as the one of in Figure 3b. When any one of the two hold capacitors saturates, in the example of Figure 6 C3a is the first to saturate, the sub-phases Φ4 e Φ5 are modulated such that the capacitor that has not yet reached the respective maximum voltage continues to be charged, whereas the saturated capacitor (C3a) is disconnected (phase Φ2a disabled). In practice, when the voltage of one of the two hold capacitors reaches saturation level, the connections of the circuit are modified such that the other hold capacitor is charged with a voltage of the same sign, regardless of the ratio between V IN and V REF . When also the voltage on the other hold capacitor reaches the saturation level, the output voltage reaches its maximum value. Similarly, if the capacitor C 3b is the first to reach saturation, it will be disconnected (Φ 2b disabled). The above described circuital solution permits to combine in a unique circuital block the rectifying, the integrating and the level shifting functions, thus eliminating the problems of the known circuits. In particular, the fact of combining in a unique block the above noted functions, permits to eliminate the need to use an amplifier with a gain equal to 2 connected in cascade, which according to certain prior art circuits is required to attain a full output dynamic and to enhance signal/noise ratio. Finally, the operational amplifier of the integrator functions in respect to the voltage reference in such a way as to ensure that the discharge of the parasite capacitances of the switches, due to their intrinsically small value, will never bring the amplifier of the integrator to function below ground voltage VGND.

Claims: A rectifying integrator of an input signal (VIN) with full output dynamic, relative to a voltage reference (VREF) intermediate in respect to the dynamic of the input signal (VIN), the line of integration of which is composed of an integrator of that portion of the input signal that exceeds the voltage reference (VREF) and of a hold capacitor (C 3a ) coupled in cascade to the integrator, including a second line of integration identical to said first line of integration integrates that portion of the input signal (VIN) that remains below said voltage reference (VREF), and an adder output stage generates an output signal (VOUT) equal to the difference between the voltages existing on the hold capacitors (C 3a , C 3b ) of said lines of integration first and second, said identical lines of integration share a generator of primary control phases, first ( 1 ) and second ( 2 ) in phase opposition to each other, for offset compensation and integration, and each includes at least an output buffer (B1, B2), said rectifying integrator comprising an integrating stage having two identical capacitors (C 2a , C 2b ) connected into a feedback path of the integrating stage and two identical hold capacitors (C 3a , C 3b ) alternately connected to the output of said integrating stage, said distinct output buffers (B1, B2) being coupled to said two hold capacitors (C 3a , C 3b ), respectively, characterized in that said integrating stage comprises also an operational amplifier (OP-AMP I) said that said identical lines of integration share a common offset free switched-capacitor integrator referred to said intermediate voltage reference (VREF); said identical capacitors (C 2a , C 2b ), being alternately connected into the feedback path of the operational amplifier by switches driven by a pair of complementary sub-phases ( 2a ,  2b ) of said second primary control phase ( 2 ), and said hold capacitors (C 3a , C 3b ) being alternately connected to the output of said operational amplifier (OP-AMP-I) by switches controlled by said sub-phases ( 2a ,  2b ) delayed by a certain time interval by a delay circuit (DELAY). The rectifying integrator of claim 1, characterized in that it includes two comparators coupled to said hold capacitors (C 3a , C 3b ), respectively, each generating a saturation signal (SAT_UP, SAT_DOWN) if the voltage on the respective hold capacitor reaches the respective saturation level (V CC -ΔV, V GND +ΔV); said generator generates control sub-phases, third (3) and fourth (4) of said second primary phase (2), and fifth (5) of said first primary phase (1), in function of said saturation signals (SAT_UP, SAT_DOWN), said third sub-phase (3) being complementary to said fourth sub-phase (4) and in phase opposition to said fifth sub-phase (5). The circuit according to claim 2, in which said generator switches: said sub-phases, fourth ( 4 ) and fifth ( 5 ), only when any one of said saturation signals (SAT_UP, SAT_DOWN) is active; and the first of said pair of complementary sub-phases ( 2a ,  2b ) only if the hold capacitor driven by it is not saturated while the other hold capacitor is saturated, or else if the input signal (VIN) exceeds the voltage reference (VREF) while both the hold capacitors (C 3a , C 3b ) are not saturated.

Inventors: PERNIGOTTI ELENA, POMA ALBERTO, PROTTI CARLO, PERNIGOTTI, ELENA, POMA, ALBERTO, PROTTI, CARLO
Applicants: ST MICROELECTRONICS SRL, STMICROELECTRONICS S.R.L.
Application year: 2000
Main classification: H03K5
IPC codes: G01R19