MICROCONTROLLER HAVING WRITE ENABLE BIT

Abstract: A microcontroller having a memory programmable in user mode. The microcontroller contains circuitry for detecting whether a programming level voltage has been activated. Also included is a Longwrite enable register containing an enable bit for enabling/disabling programming of the memory. When the register contains the bit indicating programming as enabled, and the programming level voltage is detected, the microcontroller allows the program memory to be programmed. The programming can take place in user mode. The programming level voltage signal is also used to detect whether to enter into a test mode. Programming of the program memory is also possible in the test mode. The invention is also directed to a method for operating a microcontroller for controlling programming of the program memory. The microcontroller according to the invention allows increased functionality by detecting whether to enter the test mode without the requirement of a test mode select input signal.

Description: MICROCONTROLLER HAVING WRITE ENABLE BIT BACKGROUND OF THE INVENTION Field of the Invention: The present invention relates to microcontrollers, and in particular to microcontrollers having internal memory allowing programming of the memory in user mode using a write enable bit. Description of the Background Microcontrollers have been designed having on-chip non- volatile memory, typically in electrically erasable programmable read only memory form (EEPROM and EPROM). The EEPROM allows the microcontroller to be programmed according to the requirements of an application. The EEPROM also allows revision or complete erasure of the programming. It is important to protect the non-volatile memory in a microcontroller from being accidentally or intentionally programmed or reprogrammed. There have been many approaches in addressing this problem. One approach is described in U.S. 5,808,544. The EEPROM in this microcontroller is programmable only when the central processing unit (CPU) is executing instructions within the internal read only memory (ROM). A microcontroller 100 includes security logic 116 outputting a ROM control signal on the conductor 118 coupled to ROM 110 and an EEPROM control signal on conductor 120 coupled to EEPROM 109. Security logic 116 disables access to EEPROM 109 when the CPU is attempting to program EEPROM 109 while executing code external to the internal ROM 110. Access to the ROM is disabled whenever code is being executed outside of ROM 110. Also, ROM security logic is included in security logic 116 and contains a current address comparator 202 which compares the current address in the program counter 204 to the first and second addresses in a secured address range register. If the program counter address is greater than the first address and less than the second address, the current address is determined to be in the secured address range. The current address comparator outputs a high level logic signal if the current address is in the secured address range and otherwise outputs a low logic level. Other approaches focus on avoiding reprogramming due to undesired drops in the power supply voltage. One such approach is described in U.S. 5,349,669. Here, the circuit monitors when a main power supply voltage is switched to a backup power supply voltage. When the switching occurs, a data protection set released discriminating circuit detects this break in the power supply and enables a data protection control signal to protect the data. Another example is described in U.S. 5,199,032. This microcontroller includes a low voltage program inhibit (LVPI) circuit which monitors the supply voltage. If the supply voltage falls below a predetermined voltage level, the LNPl circuit inhibits the use of the EEPROM programming register, preventing programming or erasing of the EEPROM. Another system, such as the PIC17C42 manufactured by the assignee of this application contains a separate pin, TEST, for test mode selection control. Another pin, MCLR/V pp acts as the master clear reset input and also accepts the programming voltage during programming mode. In this device programming of the memory occurs during a special mode and is not possible during a normal user mode, and a separate pin is allocated for the test mode selection signal. SUMMARY OF THE INVENTION It is an object of the present invention to provide a microcontroller programmable in user mode. It is another object of the present invention to increase functionality in the microcontroller by multiplexing input pins allowing internal detection of mode selection, and eliminating the need to allocate a separate pin for mode selection control. It is a further object of the present invention to increase functionality in a pin- compatible family of devices such as microcontrollers. These and other objects are achieved by a circuit using a microcontroller with a program memory having a program memory write enable register, a voltage detector circuit and a decoder circuit connected to the register and the detector circuit. A reset circuit may also be connected to the register and the detector circuit. The reset circuit may output a signal resetting the register. The reset circuit may also comprise a means for resetting a register only when resetting the microcontroller. The microcontroller may also have an input pin connected to the reset circuit and to the detector circuit. The decoder circuit may also comprise a first input connected to receive an output of the detector circuit and a second input connected to receive an output of the register. The decoder circuit may also include means for outputting a test mode enable signal and a program memory enable signal based upon the outputs of the detector circuit and register. In one embodiment, the microcontroller may include a data memory and the register may comprise a memory location in the data memory. The register may also be implemented as a separate register or as a fuse. The above objects may also be achieved by a method of programming a memory in a microcontroller including the steps of detecting a programming level voltage, determining whether programming of the memory is enabled, and programming the memory after detecting the voltage and determining that the memory has been enabled for programming. The method may also include a step of entering a test mode when a voltage is detected and the memory is not enabled for programming. The invention may further include entering the test mode, enabling the memory for programming and programming the memory while in the test mode. The determining of whether to enter the test mode could be done internally by the microcontroller. Internally determining whether to enter the test mode may be accomplished using the programming level voltage. The microcontroller can be operated in a normal user mode and the memory may be programmed during the normal user mode. The method may also include detecting a program level voltage on an input pin of the microcontroller and multiplexing at least one other signal on the pin, such as a reset signal. The above objects may also be achieved by a method for increasing functionality in a microcontroller including the steps of identifying first and second input signals required to carry out respective first and second predetermined functions. The first signal is used to carry out the first function and is internally used to determine whether to carry out the second function. The second input signal is eliminated as an input to the microcontroller. This method may also include the step of identifying the first signal as a programming level voltage for programming a memory in the microcontroller, identifying the second signal as a test mode signal and determining whether to enter the test mode using the program level voltage. The test mode select signal may be eliminated as an input signal. Internally using the first signal may include detecting the programming level voltage, determining whether to enable programming of the program memory in the microcontroller, and entering a programming mode when detecting the programming level voltage and determining if programming of the memory is enabled. The program mode may be entered during a normal user mode of the microcontroller, and after entering the test mode. BRIEF DESCRIPTION OF THE DRAWINGS A more complete appreciation of the invention and many of the attendant advantages thereof will be readily obtained as the same becomes better understood by reference to the following detailed description when considered in connection with the accompanying drawings, wherein: FIG. I is a pin diagram of a microcontroller according to the invention; FIG. 2 is a schematic block diagram of the microcontroller according to the invention; FIG. 3 is a diagram of circuitry in the microcontroller according to the invention; FIG. 4 is a diagram of data memory in the microcontroller according to the invention; and FIG. 5 is a timing diagram illustrating operation of the microcontroller according to the invention. DESCRIPTION OF THE PREFERRED EMBODIMENTS Referring now to the drawings, and in particular to FIG. 1, the microcontroller according to the invention is illustrated. FIG. I shows a pin diagram of the present invention applied to a microcontroller. This microcontroller is used as an example of a device to which the invention can be applied, and is not to be construed as limiting the invention. In FIG. 1 reference numeral 10 designates the pin diagram of the microcontroller packaged in a DIP. The microcontroller could also be packaged in other configurations such as a plastic leaded chip carrier or a plastic surface mount package. The pin designations RA0-RA5 correspond to a bidirectional I/O port A. Similar designations are indicated for the bidirectional I/O ports B, C, D and E. Information is transferred to and outputted from the pins of the bidirectional I/O ports. The package 10 also includes pins for the power supply (V DD and V ss ), oscillator input and output (OSC1 and OSC2) and a master clear/programming voltage input pin MCLR/ypp. Also shown in FIG. 1 is a voltage switch 11 through which either a 5V or 12V power supply is fed to the MCLR/ PP pin. Voltage switch 11 can be implemented with well known circuitry. Switch control line 12 controls switching between the 5V and 12V power sources, and is shown connected to pin RA4 of I/O port A. It is also possible to use another appropriate pin for switching control. The voltage switching is performed under the control of the CPU. The 5V power supply is also fed to the V DD pins and ground is applied to the V ss pins. An oscillator 13 is connected between the OSCI and OSC2 pins to provide the clock input. Oscillator 13 can be a crystal resonator. A more detailed block diagram of some of the pertinent elements of the microcontroller 10 is shown in FIG. 2. Elements have been omitted from this drawing only for brevity. A CPU 45, shown by the dashed lines, contains elements 33-36 and 38-43 described in more detail below, controls the operation of the microcontroller. FIG. 2 also includes PORTA 20, PORTB 21, PORTC 23, PORTD 23 and PORTE 24 each connected to data bus 25. PORTA 20 in this example is a 6-bit wide data port and may be multiplexed with peripheral features of the microcontroller. PORTB 21 and PORTC 22 are 8-bit wide bidirectional ports and may also be multiplexed with peripheral features of the microcontroller. PORTD 23 is also an 8-bit bidirectional port and may also be used as a system bus address/data port. PORTE 24 is a 3 -bit bidirectional port and its pins may be used for such functions as address latch enable, output enable or write. The circuit of FIG. 2 also includes arithmetic logic unit 26 and peripheral devices in block 27. Block 28 includes a number of circuit elements such as the power- up timer, oscillator start-up timer, power-on reset, watch dog timer, brown-out reset and test mode select. MCLR, V DD and V ss pins are connected to block 28. The function of these elements is believed to be well understood and their description are omitted here. The OSC1 and OSC2 pins are input through a buffer 32 to timing generation circuit 31, which is also connected to block 28. Timing generation circuit 31 is also connected to a 4XPLL circuit 30, with circuit 30 being connected to block 28. Precision bandgap reference 29 is connected to block 28. Instructions are decoded using instruction decode and control circuit 33. The memory of the microcontroller consists of two components. The first is program memory 37 which may contain approximately 2M bytes and address and data latches. The program memory may be implemented as either a ROM or EEPROM and holds the software programs executed by the microcontroller. Addresses are input to memory 37 from program counter 40 and table pointer 39 through multiplexer 38. N- level stack 41 is connected to program counter 40. The microcontroller also includes data RAM 44 for storing data used by the microcontroller. Addresses are fed to the data RAM via address multiplexer 43. Selection of the addresses is carried out by register select logic 42. FIG. 2 also shows other latches and registers used in the system such as table latch 36, ROM latch 35 and IR register 34. A more detailed view of the circuitry in circuit 28 connected to the MCLR pin is shown in FIG. 3. In FIG. 3 the MCLR signal and the programming voltage levels are applied through pin 50. Arrow 51 indicates the connection of the program voltage to the appropriate circuitry for programming information into the program memory. A high voltage detection circuit 52 connected to pin 50 detects the programming voltage level. This can be performed any number of ways. For example, the detect circuit 52 can look for an absolute voltage level (i.e, greater than, for example, 12 volts) or cart look at a voltage difference between two voltages. In this case the voltage could be compared to the supply voltage and if the difference is greater than a certain amount, the input voltage can be detected as the programming voltage. This circuitry is typically comprised of a mix of analog and digital components such as simple comparators and voltage references and consisting of transistor threshold and/or resistor dividers. Also connected to pin 50 is reset logic 53. Reset logic carries out resetting of the microcontroller when an appropriate signal is applied to pin 50. For example, during normal operation the power supply voltage could be applied to pin 50. If the voltage on pin 50 is dropped to the ground level, the reset logic could detect this as the appropriate reset signal and carry out resetting. Connected to the output of high voltage detect circuit 52 is decode logic 54. Decode logic may be implemented with basic digital circuitry. This circuit generates two outputs: Test_Enable and Longwrite_Enable. These signals are generated based upon the inputs from high voltage detect circuit 52 and longwrite enable register 55. Activating the Test_Enable signal places the microcontroller in the test mode while activating the Longwrite_Enable signal allows programming of the program memory 37. When the high voltage level is detected by circuit 52 and the long write enable register has not been activated, decode logic 54 activates the Test Enable signal. Once the test mode is enabled, if the Longwrite bit (LWRT) is activated, decode circuit 54 will maintain the test enable signal active and the Longwrite enable signal will also become active. The device allows programming of program memory 37 in test mode. In the case where the LWRT bit is activated prior to presenting the high voltage on the pin 50, the Longwrite_Enable signal becomes active but the test enable does not activate. Programming of memory 37 can thus take place while the microcontroller is in normal user mode, i.e., when executing instructions in the program memory. In both cases, the Longwrite_Enable will not be active if either the LWRT bit or the high voltage is not present. The normal user mode is where code execution is strictly based upon instructions fetched from the user's program memory (in this example memory 37). In the case of a microcontroller with only internal memory, this mode would be limited to memory 37. When the microcontroller has external code execution capability, an external memory bus may also be present. It is also possible to construct decode logic 54 where if the test mode is already initiated, activating the LWRT bit does not allow programming in test mode. The programming mode is entered by first activating the LWRT bit and subsequently detecting the high voltage using circuit 52. Longwrite enable register 55 contains the LWRT bit which is set by the user code in the microcontroller to indicate the user desires to program the nonvolatile memory in the program memory. Once the LWRT bit is set, raising the voltage on pin 50 will cause the microcontroller to enter a mode allowing the user to program the program memory while the microcontroller is operating in a normal execution mode. The register which contains the LWRT bit may be implemented in several ways. A separate register may be included in the microcontroller and controlled by the user code executed by the CPU. The existing code of the microcontroller is used to direct information into or read information out of longwrite register 55. The register could also be part of the user data memory, in this case art SRAM cell, where the user can freely read and write the cell. The register could further be implemented as a fuse. The case where The LWRT register is implemented in data RAM 44 is shown in FIG. 4. Data RAM 44 contains a data latch 46, an address latch 48, and data area 49. A section 47 of data area 49 is designated for special function registers (SFRs). The LWRT register resides as part of the user's data RAM area 49 in SFR space 47. The SFRs are used to perform specific functions, such as controlling I/O ports, and any peripherals which are part of the microcontroller. The configuration of the watchdog timer, brown-out reset, etc. can also be controller by the SFRs. Writing to the LWRT bit will now be described. Program memory 37 contains a series of instructions specific to the microcontroller's instruction set. These instructions are fetched by the CPU 45 from program memory 37 and are decoded/interpreted by instruction register 34 and instruction decode 33. The specific sequence of instructions will contain directives to present the correct values onto data bus 25 while enabling the LWRT register, indicated as 56 in FIG. 3. In the case where the LWRT register resides in memory 44, register select logic 42 enables the LWRT register in the SFR space 47 and, based upon register select logic 42, an address is presented to memory 44 enabling the SFR which contains the LWRT register. Once the LWRT register is enabled for writing, the value from data bus 25 is transferred into the register. Reset logic 53 is connected to Longwrite enable register 55, Once the LWRT bit is set, it can only be cleared by a physical chip reset. This guards the user from accidentally clearing the bit while the programming voltage levels are present on pin 50, which may cause an undesired change in the execution mode. A timing diagram illustrating the operation of the device is illustrated in FIG. 5. After powering on the chip, the MCLR signal is raised from OV to the power supply voltage (in this case 5V), allowing the microcontroller to enter the normal execution mode. Initially, when the MCLR signal is at OV, the microcontroller is reset by reset logic 53, as described above. At some point during operation the Longwrite enable register is activated. This is indicated by raising the LWRT signal to a high logic level. This signal also represents the case where this value is written into the register or the data memory and is recognized as enabling programming of the program memory 37. At this point the Longwrite enable register 55 indicates to decode logic 54 that the LWRT bit has been activated. At a later point in the execution of the program in the microcontroller, the switch line is activated to apply the program level voltage to the MCLR pin 50. As, discussed above, activating the switch line could occur before the LWRT bit is set, or during test mode. As shown in FIG. 5, the MCLR signal is then raised to 12V. This causes high voltage detect circuit 52 to indicate to decode logic 52 the presence of the programming level voltage. The Longwrite_Enable signal is thus activated, in this case being set to a high level. Programming of the program memory 37 is now possible. While not shown in FIG. 5, following the activating of the Longwrite_Enable signal, the MCLR signal is returned to OV to reset the LWRT bit. Both the LWRT and the Longwrite Enable voltages will then return to OV. In the present invention a signal, the programming voltage, is required for carrying out a predetermined function, in this case programming the program memory. This signal may also be used to instruct the microcontroller to enter either the test enable mode. Such instruction in the past has been carried with a separate test mode select signal. The Longwrite enable mode is detected by circuitry attached to the pin to which the signal is applied indicate to the chip to enter a particular mode, or carry out separate functions. The present invention thus allows a reduction in the number of pins necessary in order to allow the microprocessor to carry out all intended functions. The reduction of pin count is especially advantageous in the case where one is developing a family of pin-compatible devices. Once a user has designed a footprint for a microcontroller, freeing up additional pins to allow additional functionality offers the ability to supply more powerful microcontrollers having greater functionality while adhering to the constraints imposed by the user of maintaining pin footprint compatibility. Having upward compatibility is a significant advantage since a user does not have to undertake costly and time-consuming redesign activities when incorporating the newest version of a family of chips, or when he wants or needs the extra functionality. Further, feature upgrades which can be used by modifying the software/firmware rather than hardware are usually preferred. The present invention allows a user to modify the software/firmware in user mode without having to stop normal mode and enter a separate programming mode. Both the functionality of a microcontroller is improved or increased by freeing up a pin and the ability to upgrade or modify the software is improved and made more flexible. Obviously, numerous modifications and variations of the present invention are possible in light of the above teachings. For example, while the present invention has been explained using the example of a master clear/programming voltage input pin, it is not so limited. The present invention can be applied to the case where signals applied to a microcontroller, or other device, may be multiplexed to a pin and detected using internal circuitry to allow the appropriate modes/functionality to be carried out, while eliminating the need to allocate a separate pin. The invention is also not limited to any type or particular microcontroller, but is especially advantageous for pin-compatible families of devices. It is therefore to be understood that within the scope of the appended claims, the invention may be practiced otherwise than as specifically described herein.

Claims: CLAIMS 1. A circuit used in a microcontroller having a program memory, comprising: a program memory write enable register; a voltage detector circuit; and a decoder circuit connected to said register and said detector circuit. 2. A circuit as recited in claim 1, comprising: a reset circuit connected to said register and said detector circuit. 3. A circuit as recited in claim 2, wherein: said reset circuit outputs a signal resetting said register. 4. A circuit as recited in claim 3, wherein: said reset circuit comprises means for resetting said register only when resetting said microcontroller. 5. A circuit as recited in claim 2, comprising: an input pin of said microcontroller connected to said reset circuit and said detector circuit. 6. A circuit as recited in claim 1, wherein said decoder circuit comprises: a first input connected to receive an output of said detector circuit; a second input connected to receive an output of said register; means for outputting a test mode enable signal and a program memory enable signal based upon said outputs of said detector circuit and said register. 7. A circuit as recited in claim 1, wherein: said microcontroller comprises a data memory; and said register comprises a memory location in said data memory. 8. A method of programming a memory in a microcontroller, comprising: detecting a programming level voltage; determining whether programming of said memory is enabled; and programming said memory after detecting said voltage and determining said memory to be enabled for programming. 9. A method as recited in claim 8, comprising: entering a test mode when said voltage is detected and said memory is not enabled for programming. 10. A method as recited in Claim 9, comprising: entering said test mode; enabling said memory for programming; and programming said memory while in said test mode. 11. A method as recited in claim 8, comprising: internally determining whether to enter a test mode. 12. A method as recited in claim 11 , comprising: internally determining whether to enter said test mode using said programming level voltage. 13. A method as recited in claim 8, comprising: operating said microcontroller in a normal user mode; and programming said memory during said normal user mode. 14. A method as recited in claim 8, comprising: detecting a program level voltage signal on an input pin of said microcontroller; and multiplexing at least one other signal on said pin. 15. A method as recited in claim 14, comprising: multiplexing a reset signal on said pin. 16. A method for increasing functionality in a microcontroller, comprising: identifying first and second input signals required to carry out respective first and second predetermined functions; using said first signal to carry out said first function; internally using first signal to detect whether to carry out said second function; and eliminating said second input signal as an input to said microcontroller. 17. A method as recited in claim 16, comprising: identifying said first signal as a programming level voltage for programming a memory in said microcontroller; identifying said second signal as a test mode select signal; detecting whether to enter said test mode using said programming level voltage; and eliminating as an input said test mode select signal. 18. A method as recited in claim 16, wherein internally using said first signal comprises: detecting said programming level voltage; determining whether to enable programming of a program memory in said microcontroller; entering said test mode when detecting said programming level voltage and determining programming of said memory to be not enabled; and entering a programming mode when detecting said programming level voltage and determining programming of said memory to be enabled. 19. A method as recited in claim 18, comprising: entering said programming mode while operating said microcontroller in a normal user mode. 20. A method as recited in claim 18, comprising: entering said programming mode after entering said test mode.

Inventors: TRIECE JOSEPH W, WOJEWODA IGOR, TRIECE, JOSEPH, W., WOJEWODA, IGOR
Applicants: MICROCHIP TECH INC, MICROCHIP TECHNOLOGY INCORPORATED
Application year: 2000
Main classification: G11C16
IPC codes: G06F9, G06F15, G11C16