Non-integer order dynamic systems

Abstract: A circuit implementing a non-integer order dynamic system includes a neural network (1 to 5) adapted to receive at least one input signal (IS) and to generate therefrom at least one output signal (OS). The input and output signals (IS, OS) are related to each by a non-integer order integro-differential relationship through the coefficients of the neural network (1 to 5). A plurality (I, II) of such circuits, implementing respective non-integer order (PI λ D µ ) controllers can be interconnected in an arrangement wherein any of the integral (200) or differential (202) blocks included in one of those circuits generates a signal which is fed to any of the integral (200) or differential (204) blocks of another circuit in the system.

Description: Field of the invention The present invention relates to dynamic systems and was developed by paying specific attention to the possibility of implementing non-integer order dynamic systems such as, for example, PID (Proportional, Integral, Derivative) controllers. Description of the prior art The idea of fractional integro-differential operators (i.e. derivatives and integrals) seems to be a somehow strange topic, very hard to explain, due to the fact that, unlike commonly used differential operators, it is not related to some direct geometrical meaning, such as the trend of functions or their convexity. A number N of first order differential equations usually model complex dynamics. In system theory, we call N the degree of the system. Moreover, the theory of Laplace transforms in the case of linear systems provides the possibility of analysing the input-output relationship of a system via the ratio of its Laplace transform, which is called the "Transfer Function" of the system and whose denominator is a polynomial of degree N. For that reason, such a mathematical tool could be judged "far from reality". But many physical phenomena have "intrinsic" fractional order description and so fractional order calculus is necessary in order to explain them. In fact some physical phenomena exist whose analysis/involves transfer functions of degree m, m being a non integer number. Transmission lines, various kinds of electrical noises, dielectric polarization and heat transfer phenomena are some of the fields involving "non integer order" physical laws. Evidence of this is provided e.g. by: J.C. Wang, "Realization of generalized Warburg impedance with RC ladder and transmission lines", J. Electrochem. Soc., vol. 134, N° 8, pp.1915-1940, 1987; M. S. Keshner, "1/f Noise", Proceedings of the IEEE, vol. 70, N° 3, pp. 212-218, March 1982; B. Mandelbrot, "Some noises with 1/f spectrum, a bridge between direct current and white noise", IEEE Trans. Inform. Theory, vol. IT-13, N° 2, pp. 289-298, 1967; P. Arena, R. Caponetto, L. Fortuna and D. Porto, "Nonlinear Norder Circuits and Systems: An Introduction", Nonlinear Science, Series A, Vol. 38. World Scientific; A. Le Mehaute', "Fractal Geometries", CRC Press Inc. Boca Raton - Ann Arbor - London, 1991; B. Onaral, H. P. Schwan, "Linear and non linear properties of platinum electrode polarization, Part I, Frequency dependence at very low frequencies" Met. Bio. Eng. Comput., vol. 20, pp. 299-306, 1982. Following, for instance, K. B. Oldham, J. Spanier, "Fractional Calculus", Academic Press, N.Y., 1974 or B. Ross, Editor, "Fractional Calculus and its Applications", Berlin: Springer Verlag, 1975, the most common definition of a non integer order integral is the following: The lower limit is chosen to be zero (it could be any real number) because in the following, time series with t>0 will be considered. In the above definition, Γ(q) is the factorial function, defined for a positive real value q, by the following expression: for which, when q is an integer, it holds that: Γ ( q + 1) = q ! The definition of fractional derivative easily derives from (1) by taking an n order derivative ( n being a suitable integer) of an m order integral ( m suitable non integer) to obtain an n-m = q -order one: Object and summary of the invention Specifically, the present invention aims at providing a circuit arrangement adapted to implement non-integer order dynamic systems, such as e.g. non -integer order PID controllers. According to the present invention, that object is achieved by means of a system having the features set forth in the annexed claims. Brief description of the drawings The invention will now be described, purely by way of example, with reference to the annexed drawings, wherein: Figure 1 shows some examples of magnitude Bode plots of fractional systems, Figure 2 shows some examples of corresponding phase diagrams, Figure 3 shows the impulse response of a fractional system, Figure 4 shows the step response of a fractional system, Figure 5 shows a finite element of a non inductive transmission line, Figure 6 shows the circuit usually indicated as Chua's circuit, Figures 7 and 8 show respective plots of a chaotic variable in Chua's circuit, Figure 9 shows a multi-layer perceptron adapted for simulating an m-order integrator, Figure 10 shows a switch configuration for a non-integer order derivative, Figure 11 shows a respective signal for the learning phase, Figure 12, comprised of four sections designated a) to d), respectively, shows various output signals used in the training of various neural networks implementing a non-integer order integro-differentiator, Figure 13 shows the results of order 0.3 integration of a square wave, Figures 14 and 15 show, by way of comparison, the representation of a classical integrator and the block scheme of a non-integer order integrator, Figure 16 shows one possible implementation of the blocks shown in Figure 15, Figure 17 shows a block scheme of a PID controller, Figures 18 and 19 show the possible implementation of a non-integer order PI λ D µ controller, Figure 20 shows the connection scheme of two non-integer order PI λ D µ controllers, and Figures 21 and 22 show two possible implementations of some of the blocks shown in the previous figures. Theoretical principles of the invention By way of introduction to the description of a preferred embodiment of the invention, the basic underlying theoretical principles of the invention will be briefly discussed. It is now useful to introduce the most important features of fractional systems. They will be discussed using the same tools usually adopted for integer order systems which allow an easy comparison among the two different behaviors. For example, let us focus on Bode diagrams, that is one of the basic tools in system and control theory. By considering the following equation: F ( s ) = k s p + 1 m and assuming s = j ω, we obtain: and, therefore the magnitude expressed in decibels is It must be noted that, if ω→∞, (7) becomes -20 m log 10 (ω/ p ) resulting, in a semi-logarithmic plane, in a line having slope -20m dB/dec (instead of 20 dB/dec for first order systems). This fact is useful to plot an asymptotic diagram whose maximum error e max can be found close to the pole ω=- p . This error can be calculated as follows: while for first order systems this value is 3 dB. Examples of magnitude Bode diagrams are reported in Fig. 1, which shows magnitude Bode plot of fractional system F(s) =1/ (s + 1) m for m =1 (solid), m =0.5 (dashed), m =1.5 (dotted). It is quite evident that the fractional order m modulates the slope of the magnitude diagram, providing a parameter useful e.g. for the open loop synthesis of a controller. Regarding the phase displacement, it must be noted that, considering the exponent of expression (6), it holds that: Expression (9) shows that m modulates the scale of the phase law. In fact, it can be easily seen that for ω→∞ the phase angle approaches -mp /2 instead of -p /2 typical of first order systems. Examples of phase diagrams are depicted in Fig. 2, which shows the phase Bode plot of fractional system F(s) = 1/ (s+1) m for m =1 (solid) , m =0.5 (dashed), m =1.5 (dotted). Let us now consider the impulse canonical responses. Taking into account the Laplace transformation, the following relations hold: where n is an integer such that n -1 <q<n . The above expression becomes very simple if all the derivatives are zero: Expression (11) is very useful in order to calculate the inverse Laplace transform of elementary transfer functions, such as non integer order integrators (1/s q ). In fact, replacing q with -q and considering f(t) = s(t), the Dirac impulse, by means of the definition (1), it holds that: that is the impulse response of a non integer order integrator. Another important result can be derived by the well known frequency translation formula L -1 {F(s + a)} = e -at L -1 {F(s)} applied to (12) From (13) the following expression for impulse response can be written: The most relevant consideration regarding (14) is that, if m <1, for t → 0 f(t) is infinite, as demonstrated by Fig. 3, which shows the impulse response of a fractional system for different values of m (dashed m=0.5, solid m=1, dotted=1.5). However it can be shown that, for any positive m , f(t) satisfies the hypothesis of Cauchy's theorem on the existence of the integral, and therefore the step response can be calculated. If we introduce the following definition of Incomplete Gamma Function the step response of the fractional system in question can be expressed by the simple formula: In Fig. 4 the step response is shown of a fractional system for different values of m (dashed m=0.5, solid m=1, dotted=1.5). By looking at Fig. 4, a faster response of the system having m<1 can be observed. This fact, due to the infinite value of the derivative for t =0, may be successfully exploited for all those applications in which a high speed is required. This may be the case of e.g. applications in the areas of fast control schemes (see A. Outstaluop "Systèmes asservis lineaires d'ordre fractionnaire", Masson, Paris, 1983) or image processing (see e.g. P. Arena, L. Bertucco, L. Fortuna, G. Nunnari, D. Porto "CNN with Non-Integer Order Cells", 5 th IEEE International Workshop on Cellular Neural Networks (CNNA '98), London, Great Britain, April 1998, pp. 372-378. During the nineteenth and twentieth centuries, the use of traditional differential calculus became the fundamental tool for describing any physical phenomena we can find in nature. Complex dynamics are usually modeled by a number N of first order differential equations. However many complex physical phenomena exist whose analysis can be successfully performed via transfer functions of degree m , m being a non integer number. As shown in several of the works cited in the introductory portion of this description, transmission lines, electrical noises, dielectric polarization and heat transfer phenomena are some of the fields involving "non integer order" physical laws. In the time domain, these phenomena have been modeled using differential equations of infinite order, which are not so easy to handle. In the following, some examples of non-integer order systems and relative transfer functions, which may be found when studying this kind of physical phenomena, are reported. In all of them the role of non-integer order integration is quite evident. Transmission lines Transmission lines are currently widely used in the fields of communications and power transmission. Because of their length, Kirchhoff laws cannot be adopted when studying them. In fact, it is well known that they are a particular case of Maxwell equations only if circuit dimensions are very small with respect to the minimum wavelength of the voltages (currents) flowing through them. However, if a transmission line is subdivided into a large number of elementary circuits of lengths dz, each of them can be considered a concentrated circuit as shown in Fig. 5. There, a finite element of length dz in a non inductive transmission line is shown. From Kirchhoff laws and for dz → 0, the following partial differential equations can be derived: These equations are easily solvable by using Laplace transform, which reduces the problem to an ordinary differential equation. In fact, it can be demonstrated that the solutions, in the s -domain, are the following: The positive exponential (reflection wave term) disappears in both solutions if and only if the input impedance of the line is the following: V ( s ,0) I ( s ,0) = r g + sc This result, which holds even for all z (characteristic impedance of a non inductive transmission line), shows a voltage-current relation expressed by a fractional order transfer function with one pole belonging to the generic kind F ( s ) = k s p + 1 m where k = ( r / g ) 0.5 , m= 0.5, p=g / c. Polarization phenomena Since dielectric mediums can be modeled as distributed parameter systems, their behavior can be analysed in a way similar to what has been done for transmission lines. But for metal electrodes, it can be shown that for certain kinds of noble materials (e.g. gold, silver, and platinum), the frequency polarization impedance response follows a more complex fractional order law. Expression (20) is not adapted to describe this phenomenon and for that reason it has to be replaced by its more general form: where n is the number of poles of the multiple-pole transfer function. Experimental results seem to suggest a small value for n , which leads to a more comfortable approximation if we use a frequency domain method. As an example, a platinum electrode, when the sinusoidal input amplitude is 65 mV, is described by the following three-pole transfer function: H ( s ) = 1 (1 + 10000 s ) 0.11 (1+210 s ) 0.36 (1+0.124 s ) 0.35 Obviously, (22) can be considered as a cascade of three single poles fractional order systems and each of them may be studied separately in frequency domain. Numerical differintegration As explained previously, the integral of definition (1) reproduced in the foregoing is not always solvable in a closed form. For this reason, a numerical approximation is needed, in order to allow an automatic evaluation of it. Obviously, the first step starts from (1), which is here rewritten: Let us divide the interval [0, t ] into k subintervals, k +1 being the number of samples of f ( t ) which are indicated for simplicity, in the following way: The integral extended to the whole interval [0, t ] may be decomposed into the sum of k integrals: Assuming f to be constant inside each subinterval (for example, equal to the mean value of the two extreme samples), its value can be extracted from the integral Finally, the following formula is obtained (see also the work by Oldham and Spanier already cited in the foregoing): where T is the sample time t / k , whose choice becomes relevant if q >1. It must be noted that the calculation of every value requires the availability of all the preceding samples (i.e. a theoretically infinite memory). This fact may lead to a long computation time when a lot of steps are necessary. Non integer order PI λ D µ controller v. the classical PID controller The control of dynamic chaos has been obtained in a number of vastly different physical systems including electronic circuits lasers, physiological heartbeats and chemical systems. The elimination of unstable behavior in such system is generally advantageous, as the system under study is transformed from a state of unpredictability into one of the absolute regularity. In Fig. 6, the so-called Chua circuit is shown, providing for the presence of a chaotic variable V R and a differentiating circuit. The feedback signal, which is proportional to the time derivative of V R , continuously modulates the negative resistance value of the Chua diode R N . In order to control the Chua circuit, a continuous feedback, proportional to the derivative of the chaotic signal, can be used. Using first order derivative, the plot of chaotic variable V R of the Chua circuit is as shown in Fig. 7, where trend of the variable V R in the Chua circuit with PD controller is shown. Conversely, in Fig. 8 the plot of chaotic variable V R is depicted when a derivative of order 0.7 is used. From the comparison of the two pictures, it is possible to observe that when the non integer order PD controller has been used, there is a faster response and smaller oscillation with respect to the classical PD controller. More specifically, the present invention relates to a non-integer PID controller having the features set forth in the preamble of Claim 1. Such a controller is known, per se , from I. Podlubry: "Fractional order systems and PID-controllers" IEEE Transactions on Automatic Control, vol. 44, no. 1, January 1999. The invention is characterised by the further features set forth in Claim 1. Also the article by P. Arena et al.; "CNN with Non-Integer Order Cells" already mentioned in the foregoing and US-A-5 625 552 are of some interest for the the invention. Detailed embodiment of the invention As outlined previously prior art solutions for non integer order circuit realization are not always very exact, due to frequency limitations and approximations error. In particular analog design implies the realization of a time varying capacitors usually difficult to modulate according to desired trend (see e.g. the work edited by B. Ross already cited in the foregoing) and digital circuitry needs a large memory area to store function samples. Conversely a neural network modeling may guarantee, at the same time, a good degree of approximation and the possibility, by keeping a fixed structure, of changing the integration order by well-defined configuration of weights. Also an hardware realization of the obtained networks can be easily designed. As explained e.g. in the work by Keshner referred to in the foregoing, the more integer order poles are used for obtaining the desired approximation, the more accurate the approximation results. For that reason a multi-layer perceptron is chosen with a sufficiently large number of inputs in order to simulate a high order system. The integrator according to formula (1) is adapted to be modeled by the following NARMAX equation: y ( k ) = F [ y ( k -1),...., y ( k -19), u ( k -1),...., u ( k -19)] This equation can be implemented by means of a neural network and, as predicted in the theory of black box identification, the network in question must have 38 inputs and 1 output. The number of neurons in the hidden layer can be set initially to 20 and then moved to 25 so the total number of weights is 950. An example of structure for the network is reported in Fig. 9, which shows the multi-layer perceptron adopted for the simulation of the m-order integrator (38-25-1). The type of integrator be to realized is now to be considered. Due to expected applications in the field of control, we focus our attention on orders 0.3, 0.4, 0.5, 0.7. Furthermore it must be noted that, with a suitable combination of them, it is possible to obtain a universal integro-differentiator whose order can be changed in the range of [-1,1] by means of steps of 0.1. This is shown in Fig. 10 with specific reference to a switch configuration for a derivative of order 0.7. To this aim, four different neural networks are trained with a chirp signal containing frequencies from 1 to 100 Hz (see Fig. 11) and with their m-order integrals (see Fig. 12, where the output signals used in the training of the four networks are shown in the sections designated a) to b), respectively. Nineteen samples are fed back at each step). The number of learning patterns used for the training phase has been fixed to 10,000. The neural networks thus obtained are then tested with a square wave signal at the frequency of 10 Hz. This choice has been made since a square wave is a signal with a good number of harmonics. It can be represented by the following equation: The frequencies contained in the signal are the odd ones (10, 30, 50, 70 Hz) and have appreciable amplitude until 190 Hz. The assumption that the networks have been trained with a signal having 100 Hz, as the maximum frequency does not affect the final results. In fact, every network seems to fit quite well the expected results and therefore it can be concluded that they perform exactly the desired integration. Specifically, Fig. 13 shows the results of order 0.3 integration of a square wave. The output of the network (dashed) is very close to the real one (solid). Turning now specifically to the hardware realization of a non integer order integrator, a representation of a classical integrator block is given in Fig. 14, while the proposed block scheme of the non integer controller integrator is given in Fig. 15. There, references 1 and 2 designate input and output sections of a neural network adapted to receive OSan input signal IS and to deliver an output signal OS, respectively. Reference 3 designates the core of the network, while references 4 and 5 designate input/output and memory blocks, respectively. Arrows 1-3, 2-1, 3-1, 3-2, 3-4 and 3-5 show flow of data between the various blocks considered in the foregoing. One possible implementation of the blocks reported in Fig. 15 is given in Fig. 16. The weights w j and the bias values b i (i.e. the coefficients) of the neural network, previously determined by using the back propagation algorithm, are acquired through an I/O port 4 and then stored into the memory block 5. The input signal IS (X) is acquired and loaded into a shift register (S 1 ), controlled by the core 3. The core 3 control unit manages also the shift register S 2 , utilized for the feedback of the output. For each input stored in the shift registers S 1 and S 2 , the core, reads the appropriate weights, moves it in blocks Σ(·) i (designated 20) that calculate the input for the each neuron, according to the formula: ∑(w j x i )+b i . Using a multiplexer 21, it is possible to calculate the output for every neuron using only one sigmoidal function F(u) (block 22) . Another Σ(·) block (designated 23) realizes the output layer that received the input from the previous layer and the weights and bias from the core; it calculates the neural network output OS. An interesting application of a non integer order integrator is a non-integer order PI λ D µ controller. A PID (Proportional, Integral, Differential) controller consists (as shown in Fig. 17) of three main blocks: an integrator 100 plus an (integral) gain 101, a derivator 102 with a corresponding (derivative) gain 103 and one proportional block 104. By properly setting the respective gains these blocks act on the input signal providing the output control variable which is obtained by means of an adder 105 summing the results of integration, differentiation and proportional gain. The proposed block scheme of the neural non integer order PID is given in Fig. 18 while one possible implementation of the blocks reported in Fig. 18, is given in Fig. 19. In those figures the same references already used in figures 15 and 16 were used to designate parts or elements identical or equivalent to those already described. Also, references 200, 202, 204 and 205 designate blocks which applying to the signals fed thereto respective integral (200), derivative (202) and proportional (204) processing. An adder generating the main output signal OS is designated 205. Transfer of data takes place along lines designated, as in the foregoing, by the references of the respective interconnected blocks separated by a hyphen. In particular the derivative block 202 is obtained from the integrator one 200. In fact, the not integer order derivative is the integer order derivative of an opportune not integer order integral (see equation (4)). In this way, it is possible to realize a device that can compute both the integral and derivative, while also providing intermediate (optional) inputs/outputs as shown by D-EXT, I-EXT, OUT-D or OUT-I. The possible relevance of such intermediate inputs/outputs will be better appreciated in the following in respect of the possible connection of several PI λ D µ controllers. The weights and the bias of the neural network, previously determined by using the back propagation algorithm are acquired through the I/O port 40 and then stored into the memory block 5. As in the foregoing, the input signal IS (X) is acquired and loaded into a shift register S 1 , controlled by the core. The core control unit manages also the shift registers S 2 and S 3 , utilized for the feedback of the integrator and derivative outputs. For each input stored in the shift register S 1 -S 3 , the core 3, reads the appropriate weights and moves it in the blocks Σ(·) i 20 that calculate the input for the each neuron, according to the formula: ∑(w j x i )+b i . Using multiplexer 21, it is possible to calculate the output for every neuron using single Sigmoidal Function F(u) (block 22). The Σ(·) block 23 (SUM out ) realizes the output layer that received the input from the previous layer and the weights and bias from the core; it calculates the neural network output. The output of the block 23 is sent alternatively to the S2 shift register or to the derivative block 204. The core 3 manages this switching. Due to the fact that only one block is used to perform both the non-integer order derivative and the non-integer order integral, the core unit 3 has to load from the memory block once the data to compute the former and once the data for the latter, processing always the same input. The sum of input, its derivative and its integral, multiplied respectively by the gains K p , K d and K i (implemented by respective multiplexers designated 104, 103 and 101 for consistency with Fig. 17), gives the system output. Two multiplexers are additionally provided, which are designated MUX1 and MUX2. By using MUX1, managed via the core, it is possible to receive, and then manage, a derivative term D-EXT computed outside: for example a simple derivative term computed by an analogous device. In the same way by using MUX2 it is possible to manage an external integrative term I-EXT. So by using MUX1 and MUX2 signal it is possible to manage a modular architecture based on the proposed PI λ D µ system. The connection scheme of two non-integer PI λ D µ controllers I and II is given in Fig. 20, where the same reference numerals are reproduced which were already used in Fig. 18. Finally, an example of implementation of the neuron blocks contained in a non integer order PI λ D µ controller will be given. Let us consider, any of the blocks Σ(·) i and Σ(·) designated 20 and 22 in Fig. 19. They implement the following relationship: A possible way of implementing the captioned sum (in fact a linear combination ) is described by the block schemes of figures 21 and 22. Specifically, the implementation of Fig. 21 provides for the presence of a product block 50 followed by a recursive adder block 51. The advantage of this implementation is the small area requirement. In fact in this case it is necessary only one sum block and one multiplier. The disadvantage is due to the large number of iteration and therefore to the large number of clock cycles. Another possible implementation is the one shown in Fig. 22 providing for the presence of a plurality of multiplier blocks 50l, ..., 50N whose outputs are fed to a single non-recursive adder block 51. The output sum value of adder 51 is controlled by a bias line 52. Advantages and the disadvantages of this structure are dual with respect to the previous one. In fact, the sum is performed within few clock cycles because the operations are executed in parallel. However this fact implies a larger area occupation. Of course, the basic principles of the invention remaining the same, the details of implementation and the embodiments may vary, without thereby departing from the scope of the invention as defined in the annexed claims.

Claims: A non-integer order PID controller adapted to receive at least one input signal (IS) and to generate therefrom at least one output signal (OS), said input and output signals (IS, OS) being related to each other by a non-integer order integro-differential relationship characterised in that said controller includes a neural network circuit (1 to 5) and the coefficients (w j , b i ) of said neural network (1 to 5) implement said integro-differential relationship, wherein said neural network includes at least one input layer register (S 1 ) to receive said input signal (IS) and at least one adder block (20) to calculate the input of a respective neuron of the neural network based on said input signal (IS) and a respective set of coefficients (w j ; b i ), as well as at least one weighing function block (22) to compute the output of at least one neuron in said neural network on the basis of a respective weighing function, and wherein said circuit includes at least one of: a proportional block (204) adapted to add (105) to said output signal (OS) an input signal component subject to a proportional weighing coefficient (K p ), an integral block (200) adapted to add (105) to said output signal (OS) a non-integer integral signal component subject to an integral weighing coefficient (K i ), said integral block having associated therewith a respective input register (S 2 ) for feeding the output of said integral block (200) back to the input of said neural network, and a derivative block (202) adapted to add (105) to said output signal (OS) a non-integer derivative signal component subject to a derivative weighing coefficient (K d ), said derivative block (204) having associated therewith a respective input register (S 3 ) for feeding the output of said derivative block (202) back to the input of said neural network. The circuit of claim 1, characterised in that said neural network (1 to 5) includes a memory (4) for storing said coefficients as determined by a back propagation algorithm through said neural network. The circuit of claim 1 or claim 2, characterised in that said neural network includes an input port (40) for receiving said coefficients. The circuit of claim 1, characterised in that set neural network includes a plurality of neurons as well as a single multiplexer circuit (22) to apply respective weighing functions to a plurality of said neurons. The circuit of any of claims 1 or 4 characterised in that it includes at least one output layer adder circuit (23) to calculate the output of said neural network (OS) from the outputs of said at least one neuron. The device of any of claims 1, 4 or 5 characterised in that it includes at least one additional first layer shift register (S 2 ) for feeding the output (OS) of the neural network back to the input thereof. The circuit of any of claims 1, 4, 5, or 6 characterised in that the neural network (1 to 5) includes at least one neuron block to realize a linear combination of a respective input signal (x i ) with a set of weights (w i ) and bias values (b j ), wherein said at least one neuron block includes a single product block (50) as well as a single adder block (51) implementing said linear combination recursively over a plurality of clock cycles. The circuit of any of claims 1, 4, 5, 6 or 7 characterised in that the neural network (1 to 5) includes at least one neuron block to realize a linear combination of a respective input signal (x i ) with a set of weights (w i ) and bias values (b j ), wherein said at least one neuron block includes a plurality (501, 502, ..., 50n) of product blocks implementing respective products of said input signal (x i ) with given weights (w 1 , w 2 , ..., w n ) plus a single adder block (51) simultaneously adding the results of said products and said bias values (52). The circuit of claim 1, characterised in that it includes both said integral block (200) and said derivative block (202) wherein said non-integer derivative signal component is obtained as an integer order derivative of a non-integer integral signal component generated by said integral block (200). The circuit of claim 1 or claim 9, characterised in that said integral block (200) has associated an integral input port (MUX2) to manage an external integral term. The circuit of any claims 1, 9, or 10 characterised in that said derivative block (200) has associated therewith derivative input port (MUX1) to manage an external derivative term. A dynamic system including a plurality (I,II) of circuits according to any of claims 10 or 11, whereby any of said integral (200) or derivative (202) blocks included in one of said plurality of circuits generates at least one respective output signal which is fed to any of said integral (200) or derivative (202) blocks included in another of said plurality of circuits in the dynamic system.

Inventors: ABBISSO SALVATORE, CAPONETTO RICCARDO, DI COLA EUSEBIO, DIAMANTE OLGA, FORTUNA LUIGI, PORTO DOMENICO, ABBISSO, SALVATORE, CAPONETTO, RICCARDO, DI COLA, EUSEBIO, DIAMANTE, OLGA, FORTUNA, LUIGI, PORTO, DOMENICO
Applicants: ST MICROELECTRONICS SRL, STMICROELECTRONICS S.R.L.
Application year: 2000
Main classification: G05B13
IPC codes: G05B11, G06N3, G05B13