Device and process for timing reconstruction of a constant frequency data channel transported on a packet network

Abstract: A memory (2) for data accumulation includes an input (3) on which such data are entered as a stream of input data (Pin) under the control of an input timing signal (X IN ), and an output (4) starting from which the data entered in the memory (2) are read as a stream of output data (Pout) under the control of a reconstructed timing signal (X OUT ). A phase-locked loop (7) uses this input timing signal (X IN ) as an input signal to generate a corresponding phase-locked output signal (X OUT ). The reconstructed timing signal is obtained starting from the output signal of such phase-locked loop output (7). Means (8) are provided to measure residual phase wander and act (23, 9, 10) on the transfer function band of the phase of phase-locked loop output (7), which is preferable without ring filters.

Description: This invention addresses the issue of reconstructing the timing of a constant frequency digital data channel downstream of its transport on a packet transmission network. The networks using packet transport divide numerical information to be transported into separate transmission sequences (packets) that other information fields are added to and enable the execution of several functions such as packet routing for instance. The packets containing data on different users are multiplexed with time-sharing techniques to transit on high capacity transmission channels. Transit through switching nodes introduces delays that are typically variable from packet to packet. Packet delay is therefore generally variable according to the specific technique taken into consideration. These different functional features require mechanisms capable of absorbing the discontinuity of incoming signals to reconstruct their original timing in the network terminal node to be provided. A solution to this problem (used as a preamble to claims 1 and 17) is that data incoming discontinuously from packets received are entered in a First-In-First-Out (FIFO) buffer memory. The memory is read at regular time intervals corresponding to the known fixed frequency of original timing ensuring that the memory is prevented from being too full or too empty. This invention has the objective of achieving a mechanism based on this basic principle that is capable of operating effectively and securely on a very ample frequency bandwidth without imposing any synchronization constraint on the data channel transported. According to this invention, this objective is achieved by means of a device having the features specifically mentioned in the claims that follow. The invention also appertains to the related process. A device according to the preamble of claim 1 is known from prior art document FR-A-2 755 552 (TELEDIFFUSION FSE). The contents of document EP-A-0915587 (CIT ALCATEL) relate to changing the bandwidth of a filtering device by changing the time constants of amplifiers. The invention will now be described as a non-limiting example with reference to the enclosed drawings, where: figure 1 illustrates the block diagram of the general structure of a device according to he invention, and figure 2 illustrates the block diagram of the structure of some of the parts of the device illustrated in figure 1. Reference 1 of figure 1 illustrates a device that can be used to reconstruct the timing of a data channel transported on a packet network. The need to achieve such timing reconstruction generally occurs in the terminal end of a packet network where the sequence of data transmitted must be reconstructed together with original timing after such timing has been disturbed by packet creation and transit through the network. The sequence of input data is illustrated schematically in the upper left part of figure 1 as Pin. The corresponding data stream with reconstructed timing is shown schematically in the upper right part as Pout. For illustration of the invention, both input stream Pin and output stream Pout can be seen as a sequence of individual bits irregularly spaced in time in input stream Pin and regularly in output stream Pout due to the effect of the action of device 1. Experts will appreciate that this representation includes the use condition in which irregular input data spacing occurs between subsequent data packets (such as between octets or bytes, or multi-byte words for instance) regardless of whether reception is serial or parallel. In the former case, serial reception anyhow originates a stream of individual bits that are spaced regularly inside their respective groups (bytes, words and the like) but irregularly timed between subsequent groups due to altered timing consequent on transmission on the network. In the latter case, the train of individual bits indicated with Pin in figure 1 can be seen as the sequence of bits each representing the instant of arrival of the respective packet in the sequence of subsequent packets. The above also applies for a memory 2 organized in a First-In-First-Out (FIFO) scheme receiving the Pin stream on an input 3 and returning the Pout stream on an output 4 with regularly reconstructed timing. Number references 5 and 6 illustrate two other inputs of memory 2 respectively acting as a writing command input (WR) and as a reading command input (RD). A phase X IN signal (hereinafter also simply referred to as signal X IN ) derived from input stream Pin is brought to input 5 as a writing command signal. It can for instance be a synchronization signal obtained from the rising edges of individual bits included in stream Pin or simply by the Pin signal itself. A reading command corresponding to reconstructed timing is applied to input 6. This phase X OUT signal (also hereinafter referred to as signal X OUT for brevity) can simply consist of a signal with frequency directly corresponding to the average of signal X IN (minus the effects of network disturbance which can essentially be seen as a very extensive amplitude and frequency phase disturbance) or of a signal tied to a signal representing the frequency of an octect or word f B equivalent to N times the frequency of a bit f b (obviously with N = 8 in the case of octect frequency). Signal X OUT (hereinafter reference will primarily be made to this signal for simpler illustration) is generated by a complex of parts indicated with 7 allocated to essentially perform the function of a Digital Phase Locked Loop DPLL. The further group of parts indicated with 8 co-operates with lock loop 7 with the main purpose of measuring the level of wander with respect to optimum timing reconstruction conditions to implement automatic lock loop 7 adjustment. Passing on to review the various lock loop 7 parts in detail, reference numbers 9 and 10 indicate two divisors (with M IN and M OUT division ratio hereinafter postulated as being identical and equivalent to M) whose function is to confer greater operational flexibility to the device. This occurs, as will be explained better later on, due to the effect of adjustment of M in the respective division factors actuated on their respective adjustment inputs 9a and 10a. This division factor M can of course be equivalent to the unit. Divisor 9 receives signal X IN as an input and divisor 10 receives signal X OUT as an input. Their respective outputs are sent to a counter 11 and more specifically to increase counter 11a and decrease counter 11b inputs of the counter itself. Output from counter 11 indicated with k is supplied to a Digital Controlled Oscillator DCO 12 preferably implemented according to the scheme described in "Digital Phase-Locked Loop with Jitter Bounded" by Steven M. Walters and Terry Troudet, IEEE Transactions on Circuits and Systems, Volume 36, Number 7, July 1989, pages 980 - 987. Oscillator 12 essentially consists of an adder 13 and an accumulator register 14 acting at operating frequency f s generated by a local oscillator 15. The value accumulated in register 14 is fed back through a line 16 to the input of adder 13 that adds the value accumulated in the register and received through line 16 to the value k from counter 11 for loading into register 14. In other words, accumulator register 14 stores at operating frequency f s a numerical value given by the sum of its present value with number k. The summation is executed on module 2 n where n is the register and adder size in bits. Oscillator 12 output on line 17 thus consists of the most significant bit of accumulator register 14. This output signal divided if so required by factor N of a further divisor 18 identifies the X OUT signal used as the timing reconstruction signal to pilot synchronized data reading starting from memory 2 through input 6. According to the actuation form preferred now and illustrated here, lock loop 7 uses two-directional counter 11 as a phase detector and provides connection to counter 11 output (value k) directly at digital oscillator 12 input and thus preferably with no intermediate filter. Counter 11 value k increases on the rising edges of the signal from divisor 9 and decreases on the rising edges from divisor 10. The instantaneous signal k values received in this fashion are accumulated in oscillator 12 register. Lock loop phase transfer function is of the first degree in complex variable s: x OUT (s) x IN (s) = f s 2 n MN s+ f s 2 n MN where M and N represent the division factors applied in divisors 9 and 10 (M) and in divisor 18 (N) and f s is the frequency of oscillator 15. Phase transfer function band B is expressed by: B = 1 2π · f x 2 n MN Jitter j due to quantification of phase is: j = f B f s Frequency quantification jitter is: j = Mf s 2 n f B If j max is maximum jitter expressed in percent admitted on output f B , the two previous expressions determine lock interval in frequency, given by: f s M j Max 2 n < f B < j MAX f s which indicates the advantage of a high value for f s with respect to f B (such as f s ≥ 10 f B for instance). Maximum lock time T a postulating initial k equivalent to 0 is: T a = 1 2πB The solution described enables obtaining a one-pole phase transfer function without stability problems and featuring a wide frequency lock interval. In this connection, experts will appreciate that the terms Phase Lock and Phase-Locked Loop are used in this description and in the enclosed claims with reference to their current meaning in the field and therefore include in the lock action also the frequency lock normally executed by these devices. The amplitude and frequency of deviations normally defined as jitter and wander according to their respective frequency contents present in phase X IN of memory 2 write signal which loop 7 is to lock to depend on the frequency of the data signal transported, on packet size and construction frequency and on network transport modality. Loop 7 essentially behaves as a phase filter and its output presents residual wander proportional to its band B. Lock time T a is inversely proportional to this same parameter and its value thus becomes especially important. The possibility therefore exists to opt for a compromise by assigning B a fixed value, which is equivalent to setting a value for product MN once and for all. It however appears advantageous to opt for an alternative solution directed at dynamically reducing the value of band B during locking to reduce both lock time and residual output wander. The rated value of B should not anyhow be lower than necessary in order to optimize lock time. This is why the device according to the invention preferably contains the complex of parts indicated with 8, the function of which is to achieve a dynamic lock function with adaptive B variation, by: identifying the moment at which lock is achieved; assessing residual output wander; increasing the value of M to reduce band B without causing discontinuity in lock-loop 7 operation, in case of excess wander. The first of these functions is executed by the module or block 19 whose function is essentially to generate a lock signal on a line 20. In practice, block 19 compares the subsequent values of k received at counter 11 output on a line 21 and identifies the lock condition when a certain number (such as L for instance) of consecutive values of k are equivalent, limited to the N k most significant bits of k. These consecutive values are identified with a frequency preferably corresponding to frequency f s generated by oscillator 15. Block 19 essentially includes two registers, a comparator and a counter. When block 19 indicates achievement of lock conditions, residual output wander is measured through the block indicated with 22, whose structure is illustrated in greater detail at figure 2. Operation of block 22 is based on the fact that, with the period of residual wander in lock conditions being identified with T w , there are shorter duration time intervals (such as T M = T w /10 for instance) during which phase X OUT increases monotonously with respect to the phase of a constant frequency signal, other time intervals during which it decreases (monotonously) and others during which passage between the two previous conditions occurs. Wander amplitude can thus be estimated starting from simple signal period measurements. Module 22 input stage therefore consists of a counter 220 receiving as an input frequency f s and phase signal X OUT to continuously execute measurement of the period corresponding to loop 7 output frequency f B . All this is achieved by once again using the fact that f s is selected preferably much greater than f B . Subsequent measurements by counter 220 are stored in two registers 221 and 222 mounted in cascade. The result of comparison between two subsequent measurements executed in a comparator 223 identifies a differential value of the first order used to pilot a counter 224. This is initialized at time intervals equivalent to T M depending on a synchronization signal generated by an oscillator 225 (it may in practice be the same oscillator 15 whose output signal is de-multiplexed) and which is increased whenever the content of register 221 is greater than the content of register 222, that is to say at decrease of phase X OUT with respect to the phase of a constant frequency signal. At the end of each measurement interval T M , the value of counter 224 coincides with the total number of times that it occurred. The values obtained this way are higher than those obtained when the same phase X OUT is inverting its trend, when the phase X OUT increases or decreases monotonously due to the wander effect. A functional control block 226 can thus assess wander starting from the variations to counts by counter 224 (which make up a second order differential value) and send a corresponding piloting signal to a block 23 enabled to operate by the signal from block 19 through line 20. From the mathematic standpoint, the function completed in block 22 is equivalent to calculating the second derivative of phase X OUT. In fact: x OUT = 2 π f B t + A W sin (2 f W t) x' OUT = 2 π f B + A W cos (2Π f W t) x'' OUT = - A w sin (2 f W t) In essence, block 23 is a threshold comparator capable of comparing residual wander amplitude (in practice A w ) with a given threshold level. When this value is found to be too high (A w over the threshold), block 23 acts on divisors 9 and 10 by increasing the values of their respective division factors. At the same time the value N k that regulates block 19 operation is increased to enable block 19 to identify the lock condition characterized by more stable values of k. The process is repeated until residual wander is lower than a preset amplitude and band limit. Block 24 is a numerical filter that receives value k on line 21 to calculate its average value (typically on a time interval equivalent to T w ). This average value is compared with the current value of k (received on line 21) in another comparator 25. This latter comparator is allocated to send an enabling signal to block 23 so that block 23 acts to modify the division factor of divisors 9 and 10 at the instant at which k is equivalent to its average value. This enables limiting output signal phase discontinuity at the moment of modification. The solution according to the invention thus enables executing reconstruction of a constant rate data channel transported on a packet system using a system capable of completely digital implementation with all the related advantages over the use of analogic loops (such as greater reliability and immunity from disturbances, and no need for calibration, for instance). This result is achieved in the absence of synchronization constraints on the data channel and the network transporting it and with the further possibility of operating within a wide lock interval, thus without the need for prior knowledge of the value of the frequency to be regenerated. Stable operation is also ensured independently of the characteristics of memory 2 write signal phase and the further capability of limiting residual wander by automatically changing the operating band and optimizing lock times.

Claims: A device for reconstructing the timing of a stream of constant frequency data transported on a packet network, comprising a memory (2) for accumulation of the data of such stream, such memory featuring: an input (3) whose data are entered as a stream of input data (Pin) under control of an input timing signal (X IN ), and an output (4) starting from which such data are read as a stream of output data (Pout) under control of a reconstructed timing signal (X OUT ), a phase-lock loop (7) having a phase transfer function with a band (B) and that uses such input timing signal (X IN ) as an input signal to be locked to generate a corresponding output signal in lock conditions (X OUT ), said phase-lock loop (7) having: a digital controlled oscillator (12), and a counter (11) for controlling the digital controlled oscillator (12), characterized in that said counter (11) is associated to two divisors (9, 10) respectively using said input timing signal (X IN ) and said output signal (X OUT ) and being adapted to vary their respective division factors (M) in order to adaptively change the band (B) of said phase-lock loop (7). A device according to claim 1, characterized by the fact that such phase-lock loop (7) is a digital type lock loop. A device according to any of the claims from 1 to 2, characterized in that said counter (11) comprises two count inputs, an increasing one (11a) and a decreasing one (11b), supplied respectively by such phase-lock loop (7) input timing signal (X IN ) and output timing signal (X OUT ) through said two divisors (9, 10). A device according to any of the previous claims, characterized by the fact that such phase-lock loop (7) includes a phase comparator (11) acting on such input timing signal (X IN ) and its corresponding output timing signal (X OUT ) to generate a phase deviation signal (k), and an oscillator loop (12) supplied with such phase deviation signal (k); such oscillator loop (12) being a digital oscillator including an accumulator register (14) capable of storing a numerical value given by the sum of its present value and the value of such phase deviation signal (k), the output signal (X OUT ) of such phase-lock loop (7) having been identified starting from the most significant bit of such accumulator register (14). A device according to claim 4, characterized by the fact that it also includes another divisor (18) generating the output signal (X OUT ) of such phase-lock loop (7) by division of such oscillator (12). A process for reconstructing the timing of a stream of input data (Pin) transported on a packet network by the accumulation of the data of such stream inclusive of the operations of: storing data as a stream of input data (Pin) under control of an input timing signal (X IN ), reading such stored data as a stream of output data (X OUT ) under control of a reconstructed timing signal (X OUT ), executing a phase lock (7) using such input timing signal (X IN ) as an input signal to lock with a phase transfer function having a band (B); and characterized in generating a corresponding output signal in lock conditions (X OUT ), such reconstructed timing signal having been obtained by adaptively changing the band (B) of said phase transfer function of said phase-lock loop (7) through a counter (11) and two divisors (9,10) respectively using said input timing signal (X IN ) and said output signal (X OUT ), the band of said phase transfer function of said phase-lock loop being changed by varying the division factors (M) of said two divisors. A process according to claim 6, characterized by the fact that such loop lock is achieved with a digital type phase-lock loop (7). A process according to any of the claims 6 and 7, characterized by the fact that such loop lock includes a phase comparison step implemented by means of increasing (11a) and of decreasing (11b) counts (11) piloted by the input timing signal (X IN ) and by the output signal on lock conditions (X OUT ), respectively. A process according to any of the claims 6 to 8, characterized by the fact that such phase lock (7) includes operations of implementing a phase comparison (11) between such input timing signal (X IN ) and its corresponding output signal (X OUT ), generating a respective phase deviation signal (k), supplying such phase deviation signal (k) to a digital oscillator (12) inclusive of an accumulator register (14) capable of storing a numerical value given by the sum of its present value with such phase deviation signal (k), and identifying such output signal in locked conditions (X OUT ) starting from the most significant bit of such accumulator register (14). A process according to claim 9, characterized by the fact that it also includes the operation of generating such output signal (X OUT ) by division of such oscillator (12) output.

Inventors: BONELLO ROBERTO, DA DALT NICOLA, MOSCA PAOLO, NERVO GIACOLINO, QUASSO ROBERTO, BONELLO, ROBERTO, DA DALT, NICOLA, MOSCA, PAOLO, NERVO, GIACOLINO, QUASSO, ROBERTO
Applicants: TELECOM ITALIA SPA, TELECOM ITALIA S.P.A.
Application year: 2000
Main classification: H04J3
IPC codes: H03L7, H04L7, H04J3, H04L12