Analog/digital PWM control circuit of a winding

Abstract: A feedback control circuit of the current in a load constituted by a winding in series to a current sensing resistor, coupled to a full-bridge output stage, an amplifier (SENSE_AMPL) coupled to the terminals of the sensing resistor, a controller fed with the output of the amplifier and with a voltage reference (V IN ) and producing a correction signal, has a PWM converter for generating a pair of control signals (I N +, I N -) that comprises an up/down counter producing a count value and a logic circuitry that produces the complement to two of the correction signal. A pair of registers first (D_I N +) and second (D_I N -) are coupled to the outputs of the controller and of the logic circuitry. A first comparator (COMP_1) coupled to the outputs of the counter and of the first register (D_I N +) produces the first control signal (I N +) if the count signal exceeds the value stored in the first register (D_I N +) and a second comparator (COMP_2) coupled to the counter and to the second register (D_I N -), produces the second control signal (I N -) if the count signal overcomes the value stored in the second register (D_I N -).

Description: FIELD OF THE INVENTION The present invention relates to a circuit for controlling the current flowing in a winding driven in pulse width modulation (PWM) mode through a full-bridge stage. BACKGROUND OF THE INVENTION In a PWM switching regulator, a square wave drives the control terminal of a switch of a full-bridge stage determining its ON or OFF state. Alternating conduction states to nonconduction states, the load driven by the full-bridge stage will be either crossed by a current or not whose mean value during a turn-on and a turn-off phase can be controlled by varying the duty cycle of the driving square wave. A particularly effective method of controlling a full-bridge is the one disclosed in the European patent application EP-A-0 760 552 in the name of the same applicant. A block diagram of a circuit implementing the method, including by a control loop of the PWM driver at a constant frequency, is depicted in Fig. 1. The peculiarity of this method is that the current flowing in the load is controlled by varying the respective duty cycle of the two outputs OUT+ and OUT- of the power stage POWER_AMPL. By increasing the duty cycle of the output OUT+ and by decreasing the duty cycle of the output OUT- or viceversa, a current having direction and intensity that depend on the difference between the duty cycles of the outputs is forced in the load. The current is controlled by detecting the voltage drop on a current sensing resistance connected in series to the winding to be controlled, amplifying this voltage drop with an operational amplifier SENSE_AMPL that produces a feedback voltage, and closing the feedback loop with the amplifier ERROR_AMPL, that compares the feedback voltage with a reference value representing the desired current value. The output ERR_OUT of the amplifier ERROR_AMPL is compared with two reference triangular wave signals TRIA1 and TRIA2 of opposite phases thus generating the two driving signals IN+ and IN- of the power stage. A critical aspect of such a system is that the two signals TRIA1 and TRIA2 of opposite phase must be precisely generated with the same amplitude and with a mean value equal to the reference voltage VREF to which the SENSE_AMPL and the ERROR_AMPL are referred. This is not easy to achieve because of the offset of the operational amplifiers that make the generation of the two triangular wave oscillating signals critical and very often the two signals are not perfectly symmetrical and do not have the same mean value VREF. This results in a degradation of the performance of the current control when operating at low currents and particularly when controlling at null current. In fact in that situation, by setting the input voltage VCTL equal to the reference voltage VREF, the output ERR_OUT of the ERROR_AMPL tends to equal VREF. However, because of asymmetries and unbalances of the two triangular wave references, the two driving signals of the power stage IN+ and IN- do not result perfectly in phase and do not have the same duty cycle and so the differential voltage applied to the load is not null but assumes a value proportional to the difference between the two triangular wave voltage references. It is evident that then is a need for a PWM current control circuit that prevents such a degradation of the control at a relatively low level of current in the load. OBJECT AND SUMMARY OF THE INVENTION It has been found and is the object of the present invention a partly analog and partly digital circuit controlling through a feedback loop the current flowing in a winding of an induction machine, such as a DC motor or a Voice Coil Motor that overcomes the drawback of known circuits. The current flowing in the load is delivered by a full-bridge stage driven by a PWM digital converter. More precisely, the object of the invention includes a feedback control circuit of the current flowing in a load constituted by a winding in series to a current sensing resistor, comprising an output full-bridge stage, driven by a pair of first and second control signals, an amplifier having a noninverting and an inverting input respectively coupled to the terminals of the current sensing resistor, producing an amplified replica of the voltage drop on the sensing resistor, a controller coupled to the output of said amplifier and to a reference voltage representing a desired value of the current in the load, producing a correction signal, a PWM converter coupled to the output of the controller and to a clock signal for generating said pair of control signals. The peculiarity of the control circuit of the invention consists in the structure of the PWM converter that comprises an up/down counter fed with said clock signal, producing a certain count, combinatory logic circuitry coupled to the output of the controller producing a signal that is the complement to two of the correction signal, a pair of first and second registers coupled to the outputs of the controller and of the combinatory logic circuitry, respectively, a first comparator coupled to the outputs of the counter and of the first register producing the first control signal if the count exceeds the value stored in the first register, and a second comparator coupled to the counter and to the second register, producing the second control signal if the count overcomes the value stored in the second register. According to a preferred embodiment of the invention the controller can be realized by an adder coupled to the reference voltage and to the output of the amplifier producing an error signal, and a correction filter coupled to the output of the adder, producing said correction signal. BRIEF DESCRIPTION OF THE DRAWINGS The different aspects and advantages of the invention will become clearer through the following detailed description and by referring to the attached drawings wherein: Figure 1 is a block diagram of the current control loop described in the European patent application EP-A-0760552 in the name of the same applicant; Figure 2 is a block diagram of the current control loop of the invention; Figure 3 is a block diagram of the PWM_CONVERTER of Fig. 2; Figure 4 shows the waveforms of operation of the PWM_CONVERTER; Figure 5 shows the waveforms of operation of the PWM_CONVERTER; Figure 6 is a block diagram of an alternative embodiment of the invention. DESCRIPTION OF SEVERAL EMBODIMENTS OF THE INVENTION The present invention consists in a PWM current control circuit that overcomes the mentioned problem of lack of precision when controlling driving at minimum or null value the current flowing in the load caused by asymmetry an unbalances between the two triangular wave references. A block diagram of a possible embodiment of the mixed analog/digital circuit of the invention is depicted in Fig. 2. The use of analog circuits together with digital circuits reveals itself very convenient because it makes possible the realization of a system that is perfectly compatible with the systems used at present wherein the driving voltage interface is an analog circuit, and to obtain an improved precision and ruggedness in generating the driving signals for the power stage. In fact the generation of these signals is done by a digital circuit, that is practically exempt from the above mentioned asymmetry and unbalance problems. The purely analog part of the circuit is constituted by the sensing amplifier SENSE_AMPL and by the error amplifier ERROR_AMPL. The SENSE_AMPL detects the current flowing in the load and the sensing resistor R S producing an amplified voltage that is fedback and compared with the input voltage VIN, representing the desired value of the current to be forced in the winding. The error signal resulting from the comparison is amplified by the ERROR_AMPL that also guarantees stability and a reduction of the high frequency components by means of the compensation network R C and C C . In this way a quality detection of the current in the load and an outstanding precision in controlling the current is obtained while using the same analog interface with the driving voltage VIN as in known circuits. The analog to digital converter A/D, which in Fig. 2 is depicted as a N bits converter, couples the analog part with the digital part of the current control loop. In the example considered, N is equal to 8 and so the output of the A/D converter is an integer number comprised between 0 and 255. Of course, N may also be different from 8. The input dynamic of the A/D converter is established by the two references maximum VXX+ and minimum VXX- and is centered on the value of VREF. In this way, if the output of the ERROR_AMPL is equal to VREF, the output of the A/D converter is equal to 128, if the output of the ERROR_AMPL is equal to or lower than VXX-, the output of the A/D converter is equal to 0, while if the output of the ERROR_AMPL is equal to or greater than VXX + , the output of the A/D converter is equal to 255. The digital conversion of the output voltage of the ERROR_AMPL is carried out in a synchronous manner in respect to the switching of the output stage and is commanded by the enable signal ADSTART produced by the PWM_CONVERTER. A block diagram of the PWM_CONVERTER of the circuit of the invention is depicted in Fig. 3. It comprises two registers D_IN+ and D_IN-, whereby the value ADOUT produced by the A/D converter is written in the first register and the complement to two of the bit-string representing the value is written in the second register, an up/down counter UP/DN_COUNTER and two digital comparators COMP1 and COMP2. The counter and the comparators are of 8 bits according to the example considered. The counter UP/DN_COUNTER is increased and/or decreased at the rate of a system clock signal SYSCLK, determining with a complete up and down count cycle the switching frequency of the current in the load. The datum ADOUT is complemented to two by producing a complement signal which, summed to ADOUT, provides a value equal to the number of states of the counter. In such a way, the digital comparators COMP1 and COMP2 will produce two signals having complementary duty cycles, i.e. duty cycles whose sum is equal to 1. It is important that such a condition be verified in order to make the difference between the duty cycles of IN+ and IN-, that determines the intensity of the current forced in the load, vary in the broadest possible range, i.e. between -1 and+1. The contents of the two registers D_IN+ and D_IN- are compared with the output of the UP/DN_COUNTER by the digital comparator COMP1 and by the digital comparator COMP2, respectively. The control signals IN+ and IN- of the comparators are respectively active when the value stored in D_IN+ or in D_IN- are equal to or greater than the output of the counter. The enabling signal of the analog/digital conversion is generated by the PWM_CONVERTER, for example, each time the UP/DN_COUNTER attains the values 0 and 255, or when it assumes the value of 128 or even in both cases. Such a choice depends on the desired sampling frequency and on the conversion speed of the A/D that is used. The case in which the enable signal ADSTART is generated when the output of the UP/DN_COUNTER is equal to 0 or 255, will be considered by way of example. If the ERROR_AMPL produces a voltage ERR_OUT whose value is converted in the digital number ADOUT=128, then the PWM_CONVERTER generates two signals IN+ and IN- having the same phase and duty cycle equal to 50%, because the registers D_IN+ and D_IN- will contain the same value. In fact if ADOUT=128, the two registers D_IN+ and D_IN- will contain the same value so that the comparators COMF1 and COMP2 generate the same result IN+ and IN- identical having the same phase and duty cycle equal to 50%. It is clear that in such a condition the current in the load is null because the two branches of the full-bridge output stage are driven by two signals with the same phase and the same duty cycle, so even if the current terminal OUT+ and OUT- of the load are continuously switched from GND to the supply voltage VP, across the load the potential difference is null. Should a current be forced in the load, from OUT + to OUT-, the input datum VIN must be greater than VREF and as a consequence, when the control loop reaches a stable condition, the output of the ERROR_AMPL assumes a value greater than VREF. The digital conversion of the output of the ERROR_AMPL produces a number comprised between 128 and 255, for example 150. The PWM_CONVERTER stores this datum in the register D_IN+, while the value 106 (i.e. the complement to two of the 8 bits string representing the number 150) is stored in the register D_IN-. The comparators COMP1 and COMP2 compare the content of the registers D_IN+ and D_IN- with the output of the counter UP/DN_COUNTER generating a signal IN+ with duty cycle greater than 50% and a signal IN- with duty cycle lower than 50% respectively, as depicted in Fig. 4. On the contrary, should a current be forced in the load, from OUT- to OUT + ,, the input datum VIN must be lower than VREF and as a consequence, when the control loop reaches a stable condition, the output of the ERROR_AMPL assumes a value lower than VREF. The digital conversion of the output of the ERROR_AMPL produces a number comprised between 0 or 128, for example 30. The PWM_CONVERTER stores this datum in the register D_IN+, while the value 226 (i.e. the complement to two of the 8 bits string representing the number 30) is stored in the register D_IN-. The comparators COMP1 and COMP2 compare the content of the registers D_IN+ and D_IN- with the output of the UP/DN COUNTER generating a signal IN+ with duty cycle lower than 50% and a signal IN- with duty cycle greater than 50%, respectively, as depicted in Fig. 5. In both cases it is possible to note that the enable signal of the A/D converter is synchronous with the peaks of the triangular wave produced by the UP/DN_COUNTER, therefore the digital conversion of the output of the ERROR_AMPL is carried out in the middle of the free-wheeling phase of the current in the load, when both the outputs OUT + and OUT- are coupled to GND or to VP. The block diagram of another embodiment of the PWM current control circuit of the invention, is different from the one of Fig. 2 because almost completely digital. According to this alternative embodiment, the analog/digital conversion is carried out at the output of the SENSE_AMPL, producing a feedback signal of the control loop in digital form that allows a digital embodiment of the controller. The input datum DIGITAL_VIN, representing the value of the desired current in the load, is in digital form and is fed together with the feedback signal to the controller (CONTROLLER). The controller may be realized by hard wired logic and provides for summation amplification and filtering of the error signal ERR with a certain transfer function F(z) satisfying the bandwidth constraint and ensuring stability to the current control loop. At each sampling of the voltage produced by the SENSE_AMPL, determined by the signal ADSTART, the controller calculates the error signal ERR as the difference between the input datum DIGITAL_VIN indicating the current to be forced in the load and the feedback datum ADOUT, producing by the filter F(z) the desired correction signal. A generic digital filter F(z) can be described by the following polynomial: y n = a 0 x n + a 1 x n -1 + ... + b 1 y n -1 + b 2 y n -2 + ... wherein x i is the i-th input, y i is the i-th output and the dots indicate that there are other terms depending on the order of the filter. The calculation of a filter generally needs M+N+1 products, where M is the order of the numerator and N the order of the denominator of the transfer function, and M+N sums. This must be considered when designing the filter because, when the adder has produced the error value ERR, the filter F(z) must be able to complete its computations before the next ADSTART signal. Once the coefficients a n , b n and the signals x i and y i have been quantized, the filter is calculated with an infinite precision, therefore in designing the filter it is necessary to avoid internal saturations and thus destine a sufficiently great number o bits for each internal signal. In particular it is more convenient to assign to the coefficients a n , b n of the filter a sufficiently great number of bits in order to prevent that the calculation of the filter may introduce an excessive too high quantization noise. According to a preferred embodiment of the invention, the filter F(z) is an IIR filter of the first order, whose transfer function is: H(z) = a 0 z + a 1 b 0 z + b 1 Depending on the desired performances in terms of bandwidth and phase margin of the current control loop, the order of the filter can be changed.

Claims: A feedback control circuit for current flowing in a load comprising a winding in series with a current sensing resistor, the feedback control circuit comprising a full-bridge stage, coupled to the load and for being driven by first (IN+) and second (IN-) control signals, an amplifier (SENSE_AMPL) having a noninverting input and an inverting input respectively coupled to the terminals of said sensing resistor, producing an amplified replica voltage (VSENSE) of the voltage drop on said sensing resistor, a controller (CONTROLLER) receiving an output of said amplifier and a voltage reference from outside (VIN) representing a desired value of the current in the load, producing a correction signal, a PWM converter receiving the correction signal from said controller and a clock signal (SYS_CLK),and generating said first and second control signals (IN + , IN-), characterized in that said PWM converter comprises an up/down counter receiving said clock signal (SYS_CLK), and producing a count value; a logic circuitry receiving the correction signal from said controller, and producing a two's-complement signal of the correction signal; first and second registers (D_IN+, D_IN-) respectively receiving the correction signal and the two's-complement signal; a first comparator (COMP_1) coupled to the outputs of said counter and of said first register (D_IN + ), producing said first control signal (IN + ) when the count value exceeds the value stored in the first register (D_IN + ); and a second comparator (COMP_2) coupled to the outputs of said counter and of said second register (D_IN-), producing said second control signal (IN-) when the count value exceeds the value stored in the second register (D_IN-). The circuit of claim 1 wherein said controller comprises an adder receiving said voltage reference (VIN) and the output of said amplifier (SENSE_AMPL), producing an error signal (ERR); and a correction filter receiving the error signal from said adder, producing said correction signal. The circuit of claim 2, wherein said counter produces an enable flag (ADSTART) each time it attains one of a top count value and a bottom count value, wherein said controller includes an integrator coupled to the output of said adder producing an intermediate signal (ERR_OUT), and an analog/digital converter enabled by said enable flag (ADSTART) and coupled to an output of said integrator, producing said correction signal. The circuit according to claim 2, wherein said counter produces an enable flag (ADSTART) each time it attains one of a top count value and a bottom count value; said controller comprises an analog/digital converter enabled by said enable flag (ADSTART), coupled to the output of said amplifier (SENSE_AMPL) and providing to said adder a datum (A/DOUT) representing said amplified replica voltage (VSENSE); and said correction filter is an infinite impulse response digital filter (IIR).

Inventors: GALBIATI EZIO, NESSI MAURIZIO, PALESTRA MARCO, GALBIATI, EZIO, NESSI, MAURIZIO, PALESTRA, MARCO
Applicants: ST MICROELECTRONICS SRL, STMICROELECTRONICS S.R.L.
Application year: 2000
Main classification: H02M7
IPC codes: H02M7