METHOD AND DEVICE FOR CONSERVING POWER IN A CDMA MOBILE TELEPHONE

Abstract: Disclosed is a method and a system for conserving power. The method and system maintains continuous CDMA system time using a 32 kHz clock source. Specifically, one embodiment of the present invention includes a method for conserving power during a low power mode of a communication device while dynamically maintaining a Code Division Multiple Access (CDMA) system time. The method includes the step of causing a mobile station to enter a low power mode and utilizing a low power consuming inaccurate clock source (e.g., 32 kHz) to dynamically maintain a CDMA system time while limiting power input to a high power consuming accurate clock source, e.g., a Voltage Control Temperature Control Crystal Oscillator (VCTCXO). Furthermore, the method includes the step of utilizing an adjustment function to update a polynomial function (e.g., long PN) at a fixed increment which is part of the CDMA system time in order to minimize pilot signal acquisition time when the mobile station wakes up from the low power mode.

Description: METHOD AND DEVICE FOR CONSERVING POWER IN A CDMA MOBILE TELEPHONE TECHNICAL FIELD The present invention relates to the field of wireless telecommunications. More particularly, the present invention relates to the field of Code Division Multiple Access (CDMA) system time. In one embodiment discussed in this text there is described a method and a system of maintaining continuous CDMA system time using a 32 kHz clock source. BACKGROUND ART Cellular telephony has become a widely available mode of communication in modern society. Within the field of wireless telecommunications systems there exists a system referred to as a Code Division Multiple Access system, otherwise known as CDMA. It is appreciated that the Code Division Multiple Access system is among the most commonly deployed cellular technology. Within the Code Division Multiple Access system, a user of a mobile station (e.g. handset) is able to communicate with a user of another telecommunication device by way of a base station. A mobile station and a base station of the Code Division Multiple Access system communicate by way of a wireless digital radio interface. Along with providing its users wireless voice communication, the CDMA system also provides facsimile (fax) and multimedia communication capabilities. The CDMA system has the ability to operate both indoors and outdoors, which offers greater communication opportunities. For instance, the indoor operations include using it within homes, office spaces, shopping malls, hotels, and airports. Furthermore, the outdoor operations of the CDMA system include using it within suburban and city areas. It should be appreciated that there are disadvantages associated with mobile or portable stations. Specifically, one of the disadvantages is that a mobile or portable station typically operates under the limited power of an internal battery source. As such, in order to extend the life of the internal battery source, it is important to optimize the power consumption within the mobile station during various modes of operation (e.g., sleep mode). Accordingly, a need exists for a method and system for optimizing power consumption during sleep mode within a mobile station of the CDMA system. - - DISCLOSURE OF THE INVENTION The present invention provides a method and system for optimizing power consumption during sleep mode within a mobile station of the Code Division Multiple Access (CDMA) system. Furthermore, the present invention provides the above accomplishment while maintaining the CDMA system time during sleep mode. Specifically, one embodiment of the present invention includes a method for conserving power during a low power mode of a communication device while dynamically maintaining a Code Division Multiple Access (CDMA) system time. The method includes the step of causing a mobile station to enter a low power mode and utilizing a low power consuming inaccurate clock source (e.g., 32 kHz) to dynamically maintain a CDMA system time while limiting power input to a high power consuming accurate clock source, e.g., a Voltage Control Temperature Control Crystal Oscillator (VCTCXO). Furthermore, the method includes the step of utilizing an adjustment function to update a polynomial function (e.g., long PN) at a fixed increment which is part of the CDMA system time in order to minimize pilot signal acquisition time when the mobile station wakes up from the low power mode. Another embodiment of the present invention also includes a circuit for conserving power during a low power mode of a communication device while dynamically maintaining a CDMA system time. The circuit includes a low power consuming clock source. Additionally, the circuit includes a timing circuit coupled to the low power consuming clock source in order to dynamically maintain a CDMA system time during a low power mode of a communication device. It should be appreciated that the timing circuit utilizes an adjustment function to update a polynomial function at a fixed increment which is part of the CDMA system time in order to minimize pilot signal acquisition time when the communication device wakes up from the low power mode. These and other advantages of the present invention will no doubt become obvious to those of ordinary skill in the art after having read the following detailed description of the preferred embodiments which are illustrated in the drawing figures. BRIEF DESCRIPTION OF THE DRAWINGS The accompanying drawings, which are incorporated in and form a part of this specification, illustrate embodiments of the invention and, together with the description, serve to explain the principles of the invention: FIGURE 1 illustrates a general overview of a Code Division Multiple Access (CDMA) system in accordance with one embodiment of the present invention. FIGURE 2 is a block diagram of slotted paging mode circuitry used in accordance with one embodiment of the present invention. FIGURE 3 is a block diagram of master timer circuit of Figure 2 in accordance with one embodiment of the present invention. FIGURE 4 is a block diagram of the clock generator circuit of Figure 2 in accordance with one embodiment of the present invention. FIGURE 5 shows how the polynomial of the long PN state circuit of Figure 3 is defined in accordance with one embodiment of the present invention. FIGURE 6 is a flowchart of a method in accordance with one embodiment of the present invention. The drawings referred to in this description should be understood as not being drawn to scale except if specifically noted. BEST MODE FOR CARRYING OUT THE INVENTION Reference will now be made in detail to the preferred embodiments of the invention, examples of which are illustrated in the accompanying drawings. While the invention will be described in conjunction with the preferred embodiments, it will be understood that they are not intended to limit the invention to these embodiments. On the contrary, the invention is intended to cover alternatives, modifications and equivalents, which may be included within the spirit and scope of the invention as defined by the appended claims. Furthermore, in the following detailed description of the present invention, numerous specific details are set forth in order to provide a thorough understanding of the present invention. However, it will be obvious to one of ordinary skill in the art that the present invention may be practiced without these specific details. In other instances, well known methods, procedures, components, and circuits have not been described in detail as not to unnecessarily obscure aspects of the present invention. Some portions of the detailed descriptions which follow are presented in terms of procedures, logic blocks, processing, and other symbolic representations of operations on data bits within a computer memory. These descriptions and representations are the means used by those skilled in the data processing arts to most effectively convey the substance of their work to others skilled in the art. In the present application, a procedure, logic block, process, etc., is conceived to be a self- consistent sequence of steps or instructions leading to a desired result. The steps are those requiring physical manipulations of physical quantities. Usually, though not necessarily, these quantities take the form of electrical or magnetic signals capable of being stored, transferred, combined, compared, and otherwise manipulated in electronic circuitry and/or electronic computing device. It has proved convenient at times, principally for reasons of common usage, to refer to these signals as bits, values, elements, symbols, characters, terms, numbers, or the like. It should be borne in mind, however, that all of these and similar terms are to be associated with the appropriate physical quantities and are merely convenient labels applied to these quantities. Unless specifically stated otherwise as apparent from the following discussions, it is appreciated that throughout the present invention, discussions utilizing terms such as "utilizing", "causing", "updating", "determining", "receiving", "initializing", "using", "transmitting" or the like, refer to the actions and processes of electronic circuitry, or electronic computing device. The electronic circuitry or electronic computing device manipulates and transforms data represented as physical (electronic) quantities within registers, memories, and other electronic circuitry into other data similarly represented as physical quantities within the memories or registers or other such information storage, or transmission. The present invention operates within a communication system known as the Code Division Multiple Access (CDMA) system which provides its users wireless voice communication. Along with providing its users wireless voice communication, the CDMA system also provides facsimile (fax) and multimedia communication capabilities. The CDMA system has the ability to operate both indoors and outdoors, which offers greater communication opportunities. For instance, the indoor operations include using it within office spaces, homes, hotels, shopping malls and airports. Furthermore, the outdoor operations of the CDMA system include using it within _ _ suburban and city areas. The CDMA system is well known by those of ordinary skill in the art. Figure 1 illustrates a general overview of a Code Division Multiple Access (CDMA) system 100 in which the present invention operates. The two main components which comprise the CDMA system 100 are a base station device 102 and a mobile station device (e.g., 104). When an embodiment in accordance with the present invention is implemented within the CDMA system 100, it typically resides within a mobile station 104 and/or a base station 102. Since optimizing power consumption within a mobile station 104 is very critical, the following detailed discussion about the present invention focuses on its implementation within mobile station 104. However, it is understood that the present invention operates equally well within base station 102 of the CDMA system 100. Referring still to Figure 1 , mobile stations 104-108 are similar in function to cordless telephone handsets and have the ability to transmit and receive voice information along with other types of data. Base station 102 is a transmitter and receiver base station which can be implemented by coupling it into an existing network 114, such as a public telephone network. Implemented in this way, base station 102 enables the users of mobile stations 104-108 to communicate with each other and with the users of telephones 110 and 1 12, which are coupled by wire to the existing network 114. The information that is communicated between base station 102 and mobile stations 104-108 is the same type of information (e.g., voice/data etc.) that can normally be transferred and received over a public telephone wire network system. Instead of communicating over a wire network, the CDMA system uses a wireless digital radio interface to communicate information between base station 102 and mobile stations 104-108. One embodiment in accordance with the present invention is used during a sleep mode of a mobile station (e.g., 104) in order to maintain continuous CDMA system time while using a 32 kHz clock source. Material which is related to the present invention is described in co-pending US patent application serial number 09/322,240 which was filed on May 28, 1999, entitled "Device and Method for Maintaining Time Synchronous with a Network Master Time," by McDonough et al., attorney docket number DOT1180 and is herein incorporated by reference as background material. Referring now to Figure 2, which is a slotted paging mode circuit 200 used in accordance with one embodiment of the present invention. .It should be appreciated that in order to extend the standby time of a mobile station (e.g., 104), it is important to have very low power consumption during sleep mode and also shorten the slotted paging time. In order to maintain very low power consumption during sleep mode, a 32 kHz clock source is used within one embodiment in accordance with the present invention to maintain keypad and CDMA system time operations. It should be appreciated that accurately maintained CDMA system time in slotted mode is important in order to shorten slotted paging time. Within the present embodiment, preparing for slotted paging mode is described in four separate processes: calibration, entering sleep mode, sleep mode, and exiting sleep mode. Calibration Within the present embodiment, after the Sync Channel is acquired (which is well known by those of ordinary skill in the art), software initiates a calibration process. Within the present embodiment, a 32.768 kHz crystal is used as a low power consuming clock source 202. As such, a minimum of 500 millisecond (ms) calibration is usually done by the present embodiment. It should be appreciated that within the present embodiment, any length of time can be used during the calibration process. Furthermore, many different low power consuming clock sources with varying frequencies can be used for the low power consuming clock source 202 of the present embodiment. Additionally, the calibration process of the present embodiment can take place at many different times. For example, the present invention is also well suited to embodiments in which the calibration process occurs other than after the Sync Channel is acquired. The calibration process of the present embodiment is described in more detail below with reference to Figure 4. Entering Sleep Mode With reference still to Figure 2, once the calibration process has been completed and circumstances cause mobile station 104 to enter sleep mode, a processor 216 commands a clock generator circuit 206 to go to sleep. There are several handshake steps which are used by the present embodiment in order to cause mobile station 104 to enter sleep mode. During the first step, processor 216 programs the total sleep time into a counter of sleep timer circuit 214. During the next step, clock generator circuit 206 sends a sleep signal 220 to master timer circuit 208 on a rising edge of a low power consuming clock signal 234 (e.g., 16.384 kHz). Next, master timer circuit 208 updates the last short pseudonoise (PN) and long PN at chip rate (e.g., 1 .2288 MHz) and sends back a sleep request signal 222 to clock generator circuit 206. During the next step of entering sleep mode, clock generator circuit 206 holds clock signal 226 to a low and sends a sleep grant signal 224 to master timer circuit 208. Additionally, clock generator circuit 206 switches clock signal 226 from a 16 times chip rate (e.g., 19.6608 MHz) to a low power consuming clock rate (e.g., 16.384 kHz). At the same time, clock generator circuit 206 enables sleep timer circuit 214. During the next step, master timer circuit 208 switches to sleep mode and sets the short PN, long PN, and frame index to be updated at 75 chips or PNs every clock cycle. It should be appreciated that the short PN, long PN, and frame index can be updated at any number of chips or PNs within the present embodiment. Furthermore, processor 216 turns off a high power consuming clock source 204, e.g., Voltage Control Temperature Control Crystal Oscillator (VCTCXO). In this manner, mobile station 104 enters sleep mode. Sleep Mode With reference to Figure 2, it is appreciated that during sleep mode, most of the hardware blocks of slotted paging mode circuit 200 are inactive. For purposes of the present application, the term sleep mode will be synonymous with low power mode. During sleep mode, some hardware blocks continue to operate. That is, within the present embodiment sleep timer circuit 214, a keypad circuit 218, a portion of master timer circuit 208, and a portion of clock generator circuit 206 continue to operate during the sleep mode of mobile station 104. Specifically, master timer circuit 208 continues to update the short PN, long PN, and frame index at 75 chips every low power consuming clock rate of clock signal 226. Furthermore, clock generator circuit 206 continues to send clock signal 226, which has a frequency of the low power consuming clock rate, to master timer circuit 208. Sleep timer circuit 214 of the present embodiment keeps track of the total sleep time using a counter. Additionally, keypad circuit 218 continues to monitor keypad activities of mobile station 104 during sleep mode. Exiting Sleep Mode Any interrupt generated by keypad circuit 218 or sleep timer circuit 214 automatically enables high power consuming clock source 204 and wakes up the processor 216. Within the present embodiment, several steps are utilized in order to cause mobile station 104 to exit sleep mode. Specifically, when an interrupt occurs from keypad circuit 218 or sleep timer circuit 214, processor 216 waits for stabilization of high power consuming clock source 204. During this step, processor 216 continues to operate at the low power consuming clock rate. Next, processor 216 removes the sleep command. As such, clock generator circuit 206 waits until a rising edge of the low power consuming clock signal and switches the demodulator clock node to 16 times chip rate. At the same time, clock generator circuit 206 disables the sleep grant signal 224 and operates processor 216 at the high power consuming clock rate. During the next step, sleep timer circuit 214 is disabled at the same time the sleep grant signal 224 is disabled. Next, processor 216 reads the counter of sleep timer circuit 214 in order to figure out the total amount of sleep time. Once read, processor 216 calculates an estimated frequency error and adjusts for the frequency error by advancing/retarding master timer circuit 208. Next, a searcher process is initiated in order to locate the pilot signal transmitted by base station 102. During the next step, a finger is assigned to receive the paging message. In this fashion, mobile station 104 exits sleep mode. Referring to Figure 2, it is important to note that portions of the present method and system are comprised of computer-readable and computer-executable instructions which reside, for example, in computer-usable media of a mobile station or base station. Figure 2 illustrates an exemplary slotted paging mode circuit 200 used during implementation of one embodiment in accordance with the present invention. It is appreciated that slotted paging mode circuit 200 of Figure 2 is exemplary only and that the present invention can operate within a number of different circuits. Specifically, within the present embodiment sleep mode timer (SMT) 214 operates in sleep mode, e.g., when sleep grant signal 224 from clock generator circuit 206 is high. It should be appreciated that sleep mode timer 214 of the present embodiment is a low power timer circuit. It should be appreciated that within the present embodiment, the low power consuming clock source 202 is an inaccurate clock source compared to the high power consuming clock source 204. It should be further appreciated that the high power consuming clock source 204 is a very accurate clock source compared to the low power consuming clock source 202. Referring now to Figure 3, which is a block diagram of master timer circuit 208 in accordance with one embodiment of the present invention. During normal operation (e.g., non-sleep mode), a short pseudonoise (PN) index counter 306 and a long PN state 308 operate at a chip rate frequency. It is appreciated that the chip rate frequency can be many different values in accordance with the present embodiment. During sleep mode, the present embodiment is implemented using 16.384 kHz (75 chips) in order to update CDMA system time. In other words, every 16.384 kHz clock period, the short PN, the long PN, symbol and frame index shall advance 75 chips. It should be appreciated that the CDMA system time can be updated using many different frequencies in accordance with the present embodiment. Within the present embodiment, when entering sleep mode there is a switch from the high power consuming clock source 204 to the low power consuming clock source 202. During this clock switching, the first rising edge of the low power consuming clock signal (e.g., 16.384 kHz) shall occur approximately 75 chips after the last high power consuming clock update. When existing sleep mode a switch takes place from the low power consuming clock source 202 to the high power consuming clock source 204. During this clock switching, the last rising edge of low power consuming clock shall update 75 chips at the end of sleep mode. To minimize switch time PN error, a state machine to control the interface between chip rate and the low power consuming clock source 202 is accomplished by monitoring the location of the signal of the high power consuming clock source 204. Before switching to the low power consuming clock source 202, master timer circuit 208 shall signal to clock generator circuit 206 that it is ready to go to sleep. The switching time shall be within 1 chip time. Sleep controller circuit 302 interfaces with clock generator circuit 206. When sleep command 220 is received from clock generator circuit 206, sleep controller circuit 302 shall monitor the last chip enable and immediately send a sleep request signal 222 to clock generator circuit 206. As soon as sleep grant signal 224 is granted from clock generator circuit 206, both a short PN index counter 306 and a long PN state 308 shall always be enabled. Also, the logic to control 75 chips loading shall be active. With reference still to Figure 3, long PN states 308 is implemented within the present embodiment using a Linear Feedback Shift Register (LFSR) method. The polynomial for this long PN state can be defined by the IS-95 specification as shown in Figure 5, which is well known by those of ordinary skill in the art. The states of the 42 registers at time n, written in vector form S(n), can be expressed as: s n (n + 1 ) £"•1 1 0 .. 0 0 .*« ( «) 5 4l (// + 1 ) g t 0 1 0 0 s (rι) S(n + 1 ) = = G - S(n) Λ >(/1 + 1 ) S i 0 0 .. 0 1 s : (n) Λ ,(/J + I ) So 0 0 .. 0 0 s t (n) where g(k) is defined as follows: 42 p(x) = ∑ g k • x k = x" 2 + x 35 + x 33 + x 31 + x 27 + x 26 + x 25 + x 22 + x 21 + x 19 + k=0 X 18 + x 17 + x 16 + x 10 + x 7 + X 6 + X 5 + X 3 + X 2 + X 1 + 1 In other words, since transfer matrix G is solely determined by the fixed polynomial p(x) and is always full-rank, we can compute S(n - m) or S(n + m) directly from S(n) for any positive integer m by using the following relations: S(n - m) = G ~m • S(n) S(n + m) = G m • S(n) From the above information, advancing the LFSR of long PN state 308 75 chips is achieved within the present embodiment by a G 75 block 316 which is looped back to load in the LFSR every 16.384 kHz cycle. Therefore, during sleep mode, the present embodiment is able to update the long PN at 75 chips by using adjustment function G 75 . Still referring to Figure 3, sleep controller circuit 302 is coupled to receive sleep signal 220 and sleep grant signal 224 from clock generator circuit 206 (Figure 2). Furthermore, sleep controller circuit 302 is coupled to output sleep request signal 222 to clock generator circuit 206. Additionally, sleep controller circuit 302 is coupled to enable both short PN index counter circuit 306 and long PN state circuit 308. Moreover, sleep controller circuit 302 is coupled to receive a chip rate signal 324 from a decimator circuit 312. It should be appreciated that a frame indicator circuit 304 is coupled to also receive chip rate signal 324 from decimator circuit 312. Furthermore, decimator circuit 312 is coupled to receive Advance/Retard signals 320 from processor 318. It should be further appreciated that decimator circuit 312, frame indicator circuit 304, short PN index counter circuit 306, and long PN state circuit 308 are each coupled to receive clock signal 226 from clock generator circuit 206. The processor 318 is coupled to send signals to a master correct value circuit 314. Additionally, processor 318 is coupled to receive a long PN symbol signal 322 from a long PN mask 310. Long PN state circuit 308 is coupled to output signals to G 75 block 316 and long PN mask 310. G 75 block 316 is coupled to output signals to feed back into long PN state circuit 308. Moreover, master correct value circuit 314 is coupled to output signals to short PN index counter circuit 306 and frame indicator circuit 304. Short PN index counter circuit 306 is coupled to output signal to a searcher, finger front ends (FFEs) and a modulator (all not shown). Referring to Figure 4, it should be appreciated that the low power consuming clock source 202 is not as accurate as the high power consuming clock source 204. In order to keep track of low power consuming clock source 202 frequency error for CDMA system time correction upon exiting sleep mode, calibration from time to time is implemented by the present embodiment. Before starting a calibration process of the present embodiment, processor 216 specifies the calibration duration in terms of the number of low power consuming clock cycles (e.g., 16.384 kHz) by loading NSLOW register (not shown). After being activated, calibration unit 406 starts to count the number of high power consuming clock source signal 232 periods on the first edge of the signal of the low power consuming clock source 202. By the end of calibration, the number of counted high power consuming clock periods is stored within NFAST register, which is read by processor 216. The processor 216 then passes this information to DEMOD master timer circuit 208 for CDMA system time correction upon wake-up. With reference to Figure 6, a flowchart 600 of steps performed in accordance with one embodiment of the present invention for conserving power during a low power sleep mode of a communication device (e.g., mobile station 104) while maintaining a CDMA system time. Flowchart 600 includes processes of the present invention which, in one embodiment, are carried out by electrical components under the control of computer readable and computer executable instructions. Although specific steps are disclosed in flowchart 600 of Figure 6, such steps are exemplary. That is, the present invention is well suited to performing various other steps or variations of the steps recited in Figure 6. In step 602, in one embodiment of the present invention, a calibration process is performed in order to determine a frequency error between a first clock source (e.g., high power consuming clock source 204) and a second clock source (e.g., low power consuming clock source 202) of a communication device. It should be appreciated that the first clock source of the present embodiment can be implemented as an accurate clock having high power consumption. Furthermore, the second clock source of the present embodiment can be implemented as an inaccurate clock source having low power consumption. Additionally, the communication device of the present embodiment can be a mobile station within a CDMA system. Moreover, the communication device of the present embodiment can also be a base station within the CDMA system. At step 604, the present embodiment causes the communication device to enter a low power sleep mode. In step 606, the present embodiment limits the power input to the first clock source (e.g., high power consuming clock source 204). At step 608, the present embodiment utilizes a signal (e.g., 16 kHz) from the second clock source to dynamically maintain CDMA system time. As part of dynamically maintaining CDMA system, the present embodiment performs steps 610-614 simultaneously. Specifically, in step 610, the present embodiment utilizes an adjustment function to update at a fixed increment a long PN (a polynomial function) which is part of the CDMA system time in order to minimize pilot signal acquisition time when the communication device wakes up from the low power sleep mode. It should be appreciated that the fixed - - increment of the present embodiment can be preselected in order to facilitate efficient computation. Furthermore, the fixed increment can be measured by a certain number of chips (e.g., 37.5, 75, 1 12.5, etc.) or PNs. Moreover, the fixed increment can be measured by an integer amount of chips (e.g., 75, 150, etc.) or PNs. At step 612 of Figure 6, the present embodiment updates at the fixed increment a short PN (a polynomial function) which is also part of the CDMA system time in order to minimize pilot signal acquisition time when the communication device wakes up from the low power sleep mode. As previously mentioned above, the fixed increment of the present embodiment can be preselected in order to facilitate efficient computation. Additionally, the fixed increment can be measured by a certain number of chips (e.g., 37.5, 75, 112.5, etc.) or PNs. Furthermore, the fixed increment can be measured by an integer amount of chips (e.g., 75, 150, etc.) or PNs. In step 614, the present embodiment updates at the fixed increment a frame index which is also part of the CDMA system time in order to minimize pilot signal acquisition time when the communication device wakes up from the low power sleep mode. At step 616, the present embodiment determines whether the communication device is waking up from the low power sleep mode. If present embodiment determines that the communication device is not waking up from the sleep mode, the present embodiment proceeds to the beginning of step 608. If the present embodiment determines that the communication device is waking up from the sleep mode, the present embodiment proceeds to step 618. In step 618, the present embodiment increases the supply of power to the first clock source (e.g., high power consuming clock source 204) and subsequently switches from using the second clock source to using the first clock source. At step 620, the present embodiment corrects for any frequency error by performing an Advance/Retard function to the CDMA system time of the communication device. In step 622, the present embodiment performs a search in order to acquire a pilot signal transmitted by a base station of the CDMA system. After completing step 622, the present embodiment of flowchart 600 is exited. Accordingly, the present invention provides a method and system for optimizing power consumption during sleep mode within a mobile station of a Code Division Multiple Access (CDMA) system., Furthermore, the present invention provides the above accomplishment while maintaining a CDMA system time during the sleep mode. Moreover, the present embodiment provides the above accomplishments while utilizing, for example, a 32 kHz clock source during sleep mode. There are several advantages associated with utilizing the 32 kHz clock source during sleep mode. One of the advantages is that it consumes very little power compared to a VCTCXO clock source. Another advantage is that the 32 kHz clock source is widely available, thereby causing them to be inexpensive. Still another advantage is that the 32 kHz clock source is small in size enabling a size reduction of mobile stations. The foregoing descriptions of specific embodiments of the present invention have been presented for purposes of illustration and description. They are not intended to be exhaustive or to limit the invention to the precise forms disclosed, and obviously many modifications and variations are possible in light of the above teaching. The embodiments were chosen and described in order to best explain the principles of the invention and its practical application, to thereby enable others skilled in the art to best utilize the invention and various embodiments with various modifications as are suited to the particular use contemplated. It is intended that the scope of the invention be defined by the Claims appended hereto and their equivalents.

Claims: CLAIMS What is claimed is: 1. A method for conserving power during a low power mode of a communication device while dynamically maintaining a Code Division Multiple Access (CDMA) system time, said method comprising the steps of: (a) causing a communication device to enter a low power mode and utilizing a second clock source to dynamically maintain a Code Division Multiple Access (CDMA) system time while limiting power input to a first clock source; and (b) utilizing an adjustment function to update a polynomial function at a fixed increment which is part of said CDMA system time in order to minimize pilot signal acquisition time when said communication device wake up from said low power mode. 2. The method as described in Claim 1 wherein said step (a) comprises: causing said communication device to enter said low power mode and utilizing said second clock source to dynamically maintain said Code Division Multiple Access (CDMA) system time while limiting power input to said first clock source, wherein said first clock source is a high power consuming clock source and said second clock source is a low power consuming clock source. 3. The method as described in Claim 1 wherein said step (a) comprises: causing said communication device to enter said low power mode and utilizing said second clock source to dynamically maintain said Code Division Multiple Access (CDMA) system time while limiting power input to said first clock source, wherein said first clock source is an accurate and high power consuming clock source and said second clock source is an inaccurate and low power consuming clock source. 4. The method as described in Claim 1 wherein said step (a) comprises: causing said communication device to enter said low power mode, wherein said communication device comprises a mobile station. 5. The method of Claim 1 wherein the communication device is a mobile station, said first clock source is a high power consuming clock source, said second clock source is a low power consuming clock source. 6. The method of Claim 1 or 5 further comprising the step of: (c) calibrating said second clock source using said first clock source to determine a frequency error. 7. The method as described in Claim 1 or 5 further comprising the step of: (c) determining a total time said device is in said low power mode utilizing said second clock source. 8. The method as described in Claim 1 or 5 further comprising the steps of: (c) calibrating said second clock source using said first clock source to determine a frequency error; and (d) determining a total time said device is in said low power mode utilizing said second clock source. 9. The method as described in Claim 8 wherein said step (a) comprises: causing said communication device to enter said low power mode and -24- utilizing said second clock source to dynamically maintain said Code Division Multiple Access (CDMA) system time while limiting power input to said first clock source, wherein said first clock source is a high power consuming clock source and said second clock source is a low power consuming clock source. 10. The method as described in Claim 8 wherein said step (a) comprises: causing said mobile station to enter said low power mode and utilizing said power consuming clock source to dynamically maintain said Code Division Multiple Access (CDMA) system time while limiting power input to said high power consuming clock source, wherein said high power consuming clock source is an accurate clock source and said low power consuming clock source is an inaccurate clock source. 11. The method as described in Claim 1 or 5 wherein said step (b) comprises: utilizing an adjustment function to update a polynomial function at a fixed increment which is part of said CDMA system time, wherein said polynomial function comprises a long pseudonoise (PN) 12. The method as described in Claim 1 or 5 wherein said step (b) comprises: utilizing an adjustment function to update a polynomial function at a fixed increment which is part of said CDMA system time, wherein said polynomial function comprises a short pseudonoise (PN). 13. The method as described in Claim 1 or 5 further comprising the step of: (c) updating at said fixed increment a frame index which is part of said CDMA system time. 14. The method as described in Claim 1 or 5 wherein said step (b) comprises: utilizing an adjustment function to update a polynomial function at a fixed increment which is part of said CDMA system time, wherein said fixed increment is preselected such that it facilitates efficient computation. 15. The method as described in Claim 1 or 5 wherein said step (b) comprises: utilizing an adjustment function to update a polynomial function at a fixed increment which is part of said CDMA system time, wherein said fixed increment is measured as a certain number of chips. 16. The method as described in Claim 1 or 5 wherein said step (b) comprises: utilizing an adjustment function to update a polynomial function at a fixed increment which is part of said CDMA system time, wherein said fixed increment is measured as an integer number of chips. 17. The method as described in Claim 1 or 5 wherein said step (b) comprises: utilizing an adjustment function to update a polynomial function at a fixed increment which is part of said CDMA system time, where said fixed increment comprises 75 chips. 18. The method as described in Claim 5 wherein said step (a) comprises: causing said mobile station to enter said low power mode and utilizing said low power consuming clock source to dynamically maintain said Code Division Multiple Access (CDMA) system time while limiting power input to said high power consuming clock source, wherein said high power consuming clock source is an accurate clock source and said low power consuming clock source is an inaccurate clock source. 19. The method as described in Claim 1 or 5 wherein said step (a) comprises: causing said device to enter said low power mode and utilizing said second clock source to dynamically maintain said Code Division Multiple Access (CDMA) system time while limiting power input to said first clock source, wherein said second clock source has a frequency of substantially 32 kilohertz (kHz). 20. A circuit for conserving power during a low power mode of a communication device while dynamically maintaining a Code Division Multiple Access (CDMA) system time, said circuit comprising: a low power consuming clock source; and a time circuit coupled to said low power consuming clock source in order to dynamically maintain a Code Division Multiple Access (CDMA) system time during a low power mode of a communication device, wherein said timing circuit utilizes an adjustment function to update a polynomial function at a fixed increment which is part of said CDMA system time in order to minimize pilot signal acquisition time when said communication device wakes up from said low power mode. 21. The circuit as described in Claim 20 further comprising: a high power consuming clock source; and a calibrating circuit coupled to said low power consuming clock source and said high power consuming clock source, wherein said calibration circuit determines a frequency error between said low power consuming clock source and said high power consuming clock source. 22. The circuit as described in Claim 20 further comprising: a low power mode timer circuit coupled to said low power consuming clock source, wherein said low power mode timer circuit determines a total time said communication device is in said low power mode. 23. The circuit as described in Claim 20 further comprising: a high power consuming clock source; a calibration circuit coupled to said low power consuming clock source and said high power consuming clock source, wherein said calibration circuit determines a frequency error between said low power consuming clock source and said high power consuming clock source; and a low power mode timer circuit coupled to said low power consuming clock source, wherein said low power mode timer circuit determines a total time said communication device is in said low power mode. 24. The circuit as described in Claim 23 wherein: said high power consuming clock source is an accurate clock source; and said low power consuming clock source is an inaccurate clock source. 25. The circuit as described in Claim 20 wherein said polynomial function comprises a long pseudonoise (PN). 26. The circuit as described in Claim 20 wherein said polynomial function comprises a short pseudonoise (PN). 27. The circuit as described in Claim 20 wherein said timing circuit updates at said fixed increment a frame index which is part of said CDMA system time. 28. The circuit as described in Claim 20 wherein said fixed increment is preselected such that it facilitates efficient computation. 29. The circuit as described in Claim 20 wherein said fixed increment is measured as a certain number of chips 30. The circuit as described in Claim 20 wherein said fixed increment is measured as an integer number of chips. 31. The circuit as described in Claim 20 wherein said fixed increment comprises 75 chips. 32. The circuit as described in Claim 20 wherein said low power consuming clock source has a frequency of substantially 32 kilohertz (kHz). 33. The circuit as described in Claim 20 wherein said low power consuming clock source is an inaccurate clock source. 34. The circuit as described in Claim 20 wherein said communication device comprises a mobile station.

Inventors: CHEN DAVID, NGUYEN TIEN Q, CHEN, DAVID, NGUYEN, TIEN, Q.
Applicants: PHILIPS SEMICONDUCTORS INC, PHILIPS SEMICONDUCTORS, INC.
Application year: 2000
Main classification: H04B1
IPC codes: H04B1, H04B7, H04J13, H04M1