ATM ADAPTATION LAYER TYPE 1 INTEGRATED CIRCUIT BETWEEN PCM AND ATM

Abstract: This invention is an integrated circuit to be used between Pulse Code Modulation (PCM) bus (2, 2') and Asynchronous Transmission Mode (ATM) bus (4, 4'), which feature is, that implements the voice and data transmission in various X.30/V.110 formats and various bit rates between the end users on the PCM bus who are connected to a telecommunication network, as ATM Adaptation Layer Type:1 (AAL1) (3, 6), while implementing that, it uses the Convergence Sublayer (CS) (A, C) which has full parametric algorithms when mapping voice and data information into ATM cells.

Description: ATM ADAPTATION LAYER TYPE: 1 INTEGRATED CIRCUIT BETWEEN PCM AND ATM Technical Field The present invention involves an integrated circuit used between Pulse Code Modulation (PCM) bus and Asynchronous Transmission Mode (ATM) bus in telecommunication systems. In a more clear expression, the present invention involves an Asynchronous Transmission Mode Adaptation Layer Type: 1 (AAL1) integrated circuit which bridges between PCM bus which carries voice and data information in X.307V.110 format and transparent information up to 64 kbps, and ATM bus, which carries packets called ATM cells. The present invention especially involves the Convergence Sublayer in the AAL1 integrated circuit and the new methods implemented therein. Bacground of the Invention Today most of the telecommunication systems are using a protocol called Asynchronous Transmission Mode (ATM). In this technology, information is transmitted in 53 byte packets called ATM cells while users who are connected to the telecommunication system network send information to one another. One byte consists of 8 bits; one bit can be either 0 (zero) or 1 (one), in this way values that are carried in the bits and in the bytes can be mapped to an information and with this presentation, information can be transferred from one end user to another end user in a telecommunication system. The advantage of the ATM technology is, that it uses better algorithms than the other telecommunication protocols do, in order to avoid congestion for the voice and data traffic in the multi-user telecommunication systems. In the technology called ATM, the end user on the Transmitter Side, shown in Figure 1 , can send information to the place where the information will be converted into a structure that is appropriate to be carried on ATM bus by using a bus called Pulse Code Modulation (PCM) before having sent the information it will send to the Receiver Side to the telecommunication system, or, the end user on the Receiver Side, shown in Figure 1 , can receive the information it will receive from the Transmitter Side via PCM bus from the place where the information will be converted from the structure which is appropriate to be carried on ATM bus into the structure which is appropriate to be carried on PCM bus. In each PCM bus, the information of the 32 end users are carried in consecutive time slots, each time slot consists of 8 consecutive bits whici ι carry the information of an end user, and each PCM bus consists of two buses which are the Transmitter bus and the Receiver bus. The information of the end users are carried with PCM buses to the node where those will be transferred to the ATM bus, and those will be transported with the ATM network to the node where it will be read through PCM buses by the other peer end user. It is required to have systems called ATM Adaptation Layer (AAL) for information interchange between the end user and the ATM in the telecommunication system. Up to now, 5 different types of AAL1 have been defined by the international standard institutes. Among those, AAL1 is used for constant bit rate (real time) information transfer. Voice transmission is an example for this type of information interchange. Phone call is an application of voice transmission and jt requires systems running in real time. Today in the market such AAL1 integrated circuits exist that support up to 16 PCM buses. All of those support 64 kbps connections (kilobits per second, number of 1000 bits per second) which is the maximum capacity of the information transfer that is defined for an end user on a PCM bus. But none of those support bit rates lower than 64 kbps and X.30/V.110 format. It is necessary to convert information of the end user on the Transmitter Side who will be connected to ISDN (Integrated Services Digital Network) and who has lower bir rate capacity than the rate capacity ISDN supports to an end user, into a structure called X.30Λ/.110 in order to be carried on ISDN appropriately, and to extract the information of the end user the Receiver Side who will be connected to ISDN from a structure called X.30/V.110 in order to receive its information from ISDN, correctly. Current AAL1 products in the market do not support an end user who runs lower rate than ISDN offers to an end user, on the other side who wants to be connected to ISDN. Therefore those do not support X.30/V.110 format. Summary of the Invention The present invention has been developed to overcome the restrictions covered above. According to the standards, AAL1 consists of CS (Convergence Sublayer) and SAR (Segmentation and Reassembly sublayer). The said CS quantizes information coming from the end user on the Transmitter Side into packets and passes to packet to the end users on the Receiver Side. The said SAR attaches etiquette to each packet sends on the Transmitter Side and analyzes etiquette of packets and sends CS on the Receiver Side. The CS part of the AAL1 integrated circuits in the market support the end users of 64 kbps rate only. Therefore the end users who will be have the benefit of this type of AAL1 must run in this bit rate. The integrated circuit described throughout this document has been designed in order that both the end user of the old systems and the end users on the new systems can be connected to the ATM network which supports ISDN services. According to that, the CS part of the AAL1 integrated circuit that has been designed supports more end user variety than the other products do in the market. Thanks to this new CS, connections of all types of transparent format up to 64 kbps and all types of X.30/V.110 formats, totally up to 128 end users are supported at the same time. Other advantages of the current invention are, that thanks to the parametric algorithms embedded in the CS of the integrated circuit, the information of the end user on the Transmitter Side, which comes on its own PCM channel, can be written in any place of the ATM cell payload; the information of the end user on the Transmitter Side, which comes on its own PCM channel, can be mapped into other sizes than the ATM cells have; the information of the end user on the Receiver Side, which will be sent on its own PCM channel, can be read from any place of the ATM cell payload; and the information of the end user on the Receiver Side, which will be sent on its own PCM channel, can be read from the packets of other sizes than the ATM cells have. The packet size can be from 1 byte up to 4096 bytes. The Transmit Parametric Algorithm operates with the control information called parameter, which programs itself according to the requests of the end users on the Transmitter Side, who are connected to the AAL1 , and to the request of the microprocessor which controls the AAL1. Typical features of the Transmit Parametric Algorithm of the present invention are following: 1. This system which can handle 128 channels on the Transmitter Side loads the control infromation of the current state during the turn of the corresponding channel, writes back the information of the next state by generating the pointer which points to the location for the bit that comes from the PCM bus for the corresponding channel. This feature defines the Parametric Finite State Machine (PFSM). 2. Because every entry in the Transmit Pointer Table tells to place the bit on the PCM bus to desired location, it can place the corresponding bit into any place of the ATM cell and this defines the size of the packet. 3. The Transmit Parametric Algorithm is capable of processing PCM information of any kind of X.30/V.1 10 format and any bit rate up to 64 kbps on the Transmitter Side. The Receive Parametric Algorithm operates with the control information called parameter, which programs itself according to the requests of the end users on the Receiver Side, who are connected to the AAL1 , and to the request of the microprocessor which controls the AAL1. Typical features of the Receive Parametric Algorithm of the present invention are following: 1. This system which can handle 128 channels on the Receiver Side loads the control information of the current state during the turn of the corresponding channel, writes back the information of the next state by generating the pointer which points to the location for the bit that will go to the PCM bus for the corresponding channel. This feature defines the Parametric Finite State Machine (PFSM). 2. Because every entry in the Receive Pointer Table tells to place the bit on the PCM bus from desired location, it can read the corresponding bit from any place of the ATM cell and this defines the size of the packet. 3. The Receive Parametric Algorithm is capable of processing PCM information of any kind of X.30/V.1 10 format and any bit rate up to 64 kbps on the Receiver Side. Another advantage of the invention is that the size of the packet, combination of information placement to packet and combination of the information read from packets are completely left to the microprocessor and thus it provides flexibility to the user who controls the system. Brief Explanation of the Figures Figure 1 is a view of the transformation of the information transferred between the end users according to the present invention, Figure 2 is a view of the structure of the Convergence Sublayer (CS) on the Transmitter Side according to the present invention, Figure 3 is a view of the information transformation in the CS on the Transmitter Side, Figure 4 is a view of the usage of the Pointer Table on the Transmitter Side, Figure 5 is a view of how the X.30/V.110 format is sent from a channel on PCM bus is acquired, Figure 6 is a view of the Segmentation and Reassembly sublayer (SAR) on the Transmitter Side of the AAL1 integrated circuit, Figure 7 is a view of the Receiver Side of the AAL1 integrated circuit, Figure 8 is a view of the information transformation in the CS on the Receiver Side, and, Figure 9 is a view of the usage of the Pointer Table on the Receiver Side. Reference Numerals (A) AAL1 Integrated Circuit Transmitter CS (B) AAL1 Integrated Circuit Transmitter SAR (C) AAL1 Integrated Circuit Receiver CS (D) AAL1 Integrated Circuit Receiver SAR 1. End user (Transmitter Side) 1'. End user (Receiver Side) 2. PCM buses (Transmitter Side) 2'. PCM buses (Receiver Side) 3. AAL1 on the Transmitter Node 4. ATM bus (Transmitter Side) 4'. ATM bus (Receiver Side) 5 ATM network 6. AAL1 on the Receiver Node 7. PCM frame 8. PCM channel 9. ATM header 10. AAL1 header 11 ATM cell payload (voice or data information) 12 4 x PCM buses (Transmitter Side) 12 4 x PCM buses (Receiver Side) 13 Microprocessor (Transmitter Side) 13 Microprocessor (Receiver Side) 14 Transmit Static Parameter Table 14 Receive Static Parameter Table 15 Transmit Parametric Algorithm 15 Receive Parametric Algorithm 16 Transmit Dynamic Parameter Table 16' Receive Dynamic Parameter Table 17 Transmit Memory Interface 17' Receive Memory Interface 18 Transmit Pointer Table 18 Receive Pointer Table 19 Transmit Payload RAM 19' Receive Payload RAM 20 Control information that selects the Transmit Pointer Table of the channel 20 Control information that selects the Receive Pointer Table of the channel 21. Sequence information from the Transmit Dynamic Parameter Table 21'. Sequence information from the Receive Dynamic Parameter Table 22. Bit position (Transmitter Side) 22'. Bit position (Receiver Side) 23. Byte position (Transmitter Side) 23'. Byte position (Receiver Side) 24. Pointer (Transmitter Side) 24'. Pointer (Receiver Side) 25. X.30/V.110 frame 26. Header Calculator 27. Channel Scheduler 28. ATM Bus Interface (Transmitter Side) 28'. ATM Bus Interface (Receiver Side) 29. Receive Look Up Table 30. Comparator 31. Transmit Payload Flag RAM 31'. Receive Payload Flag RAM 32. Transmit Pointer Flag 32'. Receive Pointer Flag Detailed Description of the Invention The integrated circuit described here is used as shown in Figure 1. The AAL1 on the Transmitter Node (3) receives the information coming from the PCM bus (2) of the end user (1) and drops it to the ATM network (4, 5). The AAL1 on the Receiver Node (6) passes th? information coming from ATM network (4') to the PCM bus (2') of the end user (1'). The ATM buses (4, 4') and the ATM network (5) carry information between the Transmitter and the Receiver. On the Transmitter Side, the information of the end user (1) enter the Transmitter CS at the AAL1 on the Transmitter Node (3) through the PCM bus (2). As shown in Figure 1 , a PCM frame (7) contains 32 PCM channels (8), which are named Ch.O, Ch.1 , .... Ch.31. A PCM channel (8) consists of 8 bits, which are named Bit 0, Bit 1 , ..., Bit 7, and comes in 3.9 us intervals. On the Transmitter Side, an end user (1) has been defined for each channel. As it can been in the figure, the information of the end user on the Transmitter Side come to the node at every 125 us. As it can be seen in Figure 2, the AAL1 on the Transmitter Node (3) has 4 x PCM buses (12), i.e. 4 pieces of PCM bus inputs. In this way, on the Transmitter Side, (4 x 32) 128 end users (1 ) can send their information to the peer through the ATM network (4). The information of the end users (1) send to PCM buses (2) on the Transmitter Side can be any transparent format of bit rate up to 64 kbps and any X.30/V.110 format. Information coming from the PCM bus (2) of the end user (1) on the Transmitter Side is transformed into 47 byte packets named ATM cell payload (11), via the algorithms inside the Transmitter CS (A) of the AAL1 on the Transmitter Node (3). 47 byte packets are named the ATM cell payload (11 ). Each packet which has the turn is attached an etiquette (1 byte AAL1 header (10), and 5 byte ATM header (9), respectively) and is sent to the Transmit ATM Bus (4). 53 byte packets sent to the ATM bus (4) are called ATM cells. ATM cells which arrive at the Receiver Side are analyzed if those belong to the end user defined at that time. If those do, ATM cells are transferred to the PCM buses (2'). In order that the AAL1 on the Transmitter Node (3) can process the information coming from the end user (1) on the PCM bus (2) in a correct way, special parameters dedicated to each of the end user (1) which is active on the Transmitter Side must be written by the microprocessor (13) into an internal memory called the Transmit Static Parameter Table (14) of the AAL1 on the Transmitter Node (3), as shown in Figure 3. The Transmit Static Parameter Table (14), is a memory where the control information is stored which do never change as long as an end user (1) is active. That the end user is active on the Transmitter Side, means, that the end user sends the information to its peer, i.e. the Receiver Side, using the ATM bus (4) through the ATM network (5). On of the static parameters is a bit which tells if the corresponding end user (1) on the Transmitter Side is active or not. If this bit is active, the AAL1 on the Transmitter Node (3) processes the information coming from the PCM bus (2) of the end user (1 ) on the Transmitter Side. Whenever the end user on the Transmitter Side is active or inactive, the microprocessor (13) must inform the integrated circuit, i.e. it must update the corresponding region of the Transmit Static Parameter Table (14). The Transmit CS (A) can be seen in Figure 2, which connects the end users (1) on the Transmitter Side and the Transmit AAL1 (3) integrated circuit on the Transmitter Side. The information coming from the PCM bus (2) of the end user (1) on the Transmitter Side in the Transmit AAL1 are traced by the a block named the Transmit Parametric Algorithm (15), if it is informed by the microprocessor (13) by writing the Transmit Static Parameter Table (14), that the end user is active. The Transmit Parametric Algorithm (15) performs an individual execution for each bit coming from the PCM bus (2) of the end user (1) on the Transmitter Side. Firstly ft reads the state information of the channel that the bit belongs to, from a state memory named the Transmit Dynamic Parameter Table (16). The dynamic parameters. are state information that change during the time while the end user (1) is active and tell which bit is being processed at that time. The Transmit Parametric Algorithm (15) generates the pointer (24) address of the current bit from this state information. This address is the address of a memory named the Transmit Pointer Table (18). The information in this address tells into which position in the ATM cell payload (11) the current bit on the PCM bus (2) will be written. This address information is connected to the address input of the Transmit Payload RAM (19). The Transmit Payload RAM (19) is a memory in which the ATM cell payload (11), which is obtained from the information coming from the PCM bus (1) of the end user (1), will be kept temporarily, until it is read by the Transmit SAR (B) system of the AAL1 integrated circuit. Firstly, the byte, where the current t ' . coming from the PCM bus (2) of the end user (1) will be placed, are read by the RAM Interface (17), the bit is placed into the corresponding position of the byte and then is written back into the Transmit Payload RAM (19). After the executions for the current bit have been finished, the Transmit Parametric Algorithm (15) calculates the new state information of the corresponding channel and writes it back into the Transmit Dynamic Parameter Table (16). In this way, every bit coming from the PCM bus (2) of the corresponding end user (1) on the Transmitter Side is sequentially placed into the Transmit Payload RAM (19), to form a 47 byte packet finally, as shown in Figure 3. The information taken from the address of the Transmit Pointer Table (18) which is generated by the Transmit Parametric Algorithm (15) can point any place of an ATM cell payload (11), as shown in Figure 4. For example, as soon as the channel has been opened, the first coming bit can be placed into any bit position of the last byte, and the last coming bit can be placed into any bit position of the first byte. In order that the pointer can point 47 bytes of the ATM cell payload (11 ), the least significant 9 bits of every pointer that is defined as 16 bits in the Transmit Pointer Table (18) contains position information. The most significant 6 bits of the 9 bits contain information which points to which byte position (23) of the ATM cell payload (1 1) the bit coming from the PCM bus (2) of the end user and that the pointer (24) corresponds to, is written. The least significant 3 bits of the 9 bits contain information which points to which bit position (22) of the byte of the ATM cell payload (11) the bit coming from the PCM bus (2) of the end user and that the pointer (24) corresponds to, is written. The most significant bit (31 ) of the pointer (24) contains information that show if the bit coming from the PCM bus (2) of the end user (1) and that the pointer (24) corresponds to, shall be written into the ATM cell payload (11). If the value of this bit is a "0", the bit coming from the PCM bus (2) of the end user (1 ) is not written into th? ATM cell payload (11), otherwise, if the value of this bit is a "1", the bit coming from the PCM bus (2) of the end user (1) is written into the ATM cell payload (11). In case the unused bits of the pointer (24), i.e. 14th, 13th, 12th, 11th, 10th and 9th bits, which are not used by the AAL1 , are used, theoretically packets of size up to 4096 bytes can be formed in the Transmit Payload RAM (19). After the Transmit CS (A) has acquired the information of the ATM cell payload (11) quantity from the information coming from the PCM bus (2) of the end user (1 ) on the Transmitter Side and has written into the Transmit Payload RAM (19), it sets the bit, that the ATM cell payload corresponds to, in the Transmit Payload Flag RAM (30), in order that the SAR (B) on the Transmitter Side can the ATM cell. In case the Transmit SAR (B) reads the bit in the Transmit Payload Flag RAM (30) defined for the payload in turn, as "1", the ATM cell is created by the Transmit SAR (B) and it will be sent into the ATM bus (4). In case the information of the end user are sent in X.30/V.110 format to the Transmitter Side of the AAL1 , it is shown in Figure 5 how the X.30/V.110 frame (25), that comes from the PCM channel (2) of the end user (1), can be acquired. The Transmit Parametric Algorithm (15) builds a parametric counter circuit (27) together with the Transmit Dynamic Parameter Table (16) it uses for its own execution. With this feature, there is only one counter (27) in hardware, on the other hand, virtually, the number of the counters can be defined thanks to the Transmit Dynamic Parameter Table (16), which can be as much as the number of the PCM channels (8). This avoids area and resource consumption in terms of hardware. The CS (A) defined by AAL1 (3) standards gains a quite flexible structure in terms of system design, according to the unii-> described above. A block diagram is described that show the Segmentation and Reassembly sublayer (SAR) (B) of the Transmitter Side of the AAL1 in Figure 6. After the information which is the amount of the ATM cell payload (11) has been acquired, the Transmit SAR (B) is responsible for preparing and sending the ATM cell. A counter (27) in the Transmit SAR (B) looks at the bits in the Payload Flag RAM (31) of every PCM channel (8) in a round-robin fashion. If it is recognized that an ATM cell payload (11) is ready by looking at the bit of the end user (1) on the PCM channel (8), which is in the Transmit Payload Flag RAM (31), the 5 byte ATM header (9) and the 1 byte AAL1 header (10) is attached in front of the ATM cell payload (11). The generated ATM cell is sent to the ATM bus (4). The Receiver Side of the AAL1 integrated circuit, which consists of the Receive CS (C) and the Receive SAR (D), is shown in Figure 7. The ATM cells coming into the Receiver Side of th.; AAL1 (6) integrated circuit, enter the Receiver SAR (D). Whether an ATM cell belongs to one of the active end user (1) connected to the Receiver AAL1 (6), can be found, by using the Receive Look Up Table (RX LUT) (29) made up of the ATM headers (9') of the active end user (1 ') channels informed by the microprocessor (13'). The information in the ATM header (9') of an ATM cell that arrives at the Receiver is compared with each element in the Receive Look Up Table (29). If the information in the header matches one of the entries in the table, it is called "the ATM cell belongs to AAL1 (6)" and the AAL1 (6) performs executions for the corresponding ATM cell. These executions are well defined in the AAL1 (6) standards. If it is recognized that the ATM cell does not belong to the AAL1 (6), it is discarded. The ATM cell payload (11 ') which contains the information of the end user (1') in the ATM cells that recognized to belong to the AAL1 (6) will be placed into the Receive Payload RAM (19'). After the SAR In the Receiver Side (D) has written the ATM cell payload (11 '), that belongs to an active end user (1') defined in the AAL1 and that comes from the ATM bus (4'), into the Receive Payload RAM (19'), it sets the bit in the Receive Payload Flag RAM (31'), that belongs to the corresponding payload, to "1", in order to send the ATM cell payload to the PCM channel (8) of the end user (1 ') of the Receive CS (C) in a later stage. When the bit in the Receive Payload Flag RAM (19') which is defined for the current payload, is read "1" by the Receive CS (C), the ATM cell payload (1 1') is sent to the PCM channel (8) of the end user (1') on the Receiver Side in the Receiver CS (C), and Receiver CS (C) writes a "0" to the bit in the Receive Payload Flag RAM (31 ') which belongs to the current payload. As shown in Figure 7, in order that the information that will be sent to the PCM bus (2') of the end user (1') on the Receiver Side of the AAL1 (6) can be processed correctly, special control information of each active end user must be written by the microprocessor (13') into the memory called the Receive Static Parameter Table (14') of the Receive CS (C) and the ATM cell header (9') of each active end user on the ATM bus (4') into the Receive Look Up Table (29) of the Receiver SAR (D). That an end user is active, means, that the information of the corresponding end user (1') is coming from the ATM bus (4') and this information will be sent into the PCM bus (2') of the corresponding end user (1 1 ) on the Receiver Side appropriately. One of the static parameters is a bit that shows if the corresponding end user (1') is active or not. If this bit is active, the AAL1 (6) on the Receiver Side puts the contents of the ATM cells (11') of the active end users into the PCM bus (2'). Whenever the end user on the Receiver Side is active or inactive, the microprocessor (13') must inform this condition to the AAL1 (6), i.e. it must update the Receive Static Parameter Table (14') and the Receive Look Up Table (29). The end users (1 ') on the Receiver Side, as shown in Figure 8, receive information that belong to themselves, from the PCM channel (8) that belong to themselves. The PCM buses (2') which are made up of these PCM channels (8) are connected to the Receiver CS (C) of the AAL1. The end users (1') can receive their information from the AAL1 (6) only if they are active. Whether an end user is active or not, is dependent upon the control information in the Receive Static Parametric Table (14') that belong to that end user (1') are active or not. If an end user (1') is active, the Receive Parametric Algorithm (15') in the Receiver CS (C) places the information of end user (1 ') into its PCM channel (8) on the Receiver Side. The information to be placed into the PCM channel (8) is an ATM cell payload (11') of the corresponding end user (1'), which the Receiver SAR (D) has written into the Receive Payload RAM (19') and is kept temporarily un*i' the Receiver CS (C) reads. For each of the active end user (1') there is state information in the Receive Dynamic Parameter Table (16'). These contain information which position in the time domain the information to be placed into the PCM bus (2') of the end user (1 '). Dynamic parameters are state information that change during the time while the end user on the Receiver Side is active, and tells which bit in the ATM cell payload (11') is the bit to be placed in that time to the PCM bus (2'). According to this information, the Receive Parametric Algorithm (15') generates the address of the pointer (24') for the corresponding bit. This address is the address of a memory named the Receive Pointer Table (18'). The information in this address tells that the bit to be placed into the PCM bus (2') of the end user (1') on the Receiver Side must be read from which position in the ATM cell payload (11') written into the Receive Payload RAM (19') by the Receiver SAR (D) before. This information is connected to the address input of the Receive Payload RAM (19'). The Receive Payload RAM (19') is a memory where the ATM cell payload (11') is kept temporarily until it is sent to the end users (1'). The bit that will be sent to the end users is read here and will be placed into the PCM bus (2'). After having finished the executions of the corresponding bit, the Receive Parametric Algorithm (15') calculates the new state state information and writes it back into the Receive Dynamic Parameter Table (16'). In this way the bit of each channel is placed into the PCM channel (8) of the end user (1') on the Receiver Side by reading from 47 byte ATM cell payload (1 1 ') sequentially, bit by bit. . The information acquired from the address of the Receiver Pointer Table (18') that is generated by the Receive Parametric Algorithm (15') can show any place of the ATM cell payload (11), as shown in Figure 9. For example, as soon as the channel is open, the first bit which will be placed into the PCM bus (2') can be read from any bit of the last byte, the last bit which will be placed into the PCM bus (2') can be read from any bit of first byte of the ATM cell payload (11'>. In order that the pointer can point any bit in one byte ans 47 bytes of the ATM cell payload (11'), the least significant 9 bits of each pointer (24') defined as 16 bits in the Receive Pointer Table (18') contains position information. The most significant 6 bits of these 9 bits contain information from which byte position (23') in the ATM cell payload the bit that will be sent to the PCM channel (8) of the end user (1') on the Receiver Side and that belongs to the corresponding pointer (24'), will be read, whereas the least significant 3 bits of these 9 bits contain information from which bit position (22') of the byte to be read in the ATM cell payload the bit that will be sent to the PCM channel (9) of the end user (1') on the Receiver Side and that belongs to the corresponding pointer (24'), will be read. The most significant bit (31') of the pointer (24') contains information whether the bit, that will be sent to the PCM channel (8) of the end user (1') and that belongs to the pointer (24'), will be read from the ATM cell payload (11') or not. If th? value of this bit is a "0", the bit that will be sent to the PCM channel (8) of the end user (1') is not read from the ATM cell payload (11'), otherwise it is read. In case the unused bits of the pointer (24'), 14th, 13th, 12th, 11th, 10th and 9th bits, that are normally not used by the -AAL1 (6), are used, theoretically packets of size up to 4096 bytes can be defined in the Receive Payload RAM (19'). The block diagrams shown in figures and described above do not play a role that restricts the ,AAL1 integrated circuit (3, 6) which is the present invention subject, instead, the description covered here contains structure of the circuit and explanatory quality to understand the idea better.

Claims: CLAIMS 1. This invention is related to an ATM Adaptation Layer Type:1 Integrated Circuit which bridges between PCM bus (2, 2') where end users (1 , 1 ') perform information transfer and ATM bus (4, 4') which enable information transfer on a network, characterized by: comprising flexible Convergence Sublayer (A, C) and Segmentation and Reassembly sublayer (B, D), programmable by a microprocessor as requested; supporting PCM connections (2, 2') i any transparent bit rate from 1 bps up to 64 kbps and/or the PCM connections (2, 2') of any X.30/V.110 format in both Transmitter and Receiver; being capable of writing and reading information coming from an end user (1 , 1 ') and to the end user (1 , 1 ') from any place and to any place; can map packets of any size from 1 byte up to 4096 bytes thanks to parametric algorithms (15, 15') and through that, thanks to Pointer Tables (18, 18'); using parametric finite state machines (15, 15') for these; possibility to define many virtual counters (27) through state memories, although there is only one hardware counter (27) while using each finite state machine. 2. An AAL1 (3, 6) integrated circuit according to claim 1 , characterized by the parametric algorithms (15, 15') both on the Transmitter Side and on the Receiver Side which support the PCM connections (2, 2') of any type of X.30/V.110 format, stated in the standards, and/or any transparent format of bit rate from 1 bps up to 64 kbps. 3. A circuit according to anyone of the proceeding claims wherein, at said CS (A), the Parametric Algorithm (15) on the Transmitter Side, or, the Transmit Parametric Algorithm (15), which operates with the control information that programs itself through the requests of the microprocessor, which controls the AAL1 (3) and through the requests of the end users who are connected to the AAL1 (3), where the information coming from the PCM channel (8) of the end user on the Transmitter Side can be written into any desired place of the ATM cell payload (11) and the information can be mapped into other sizes of packets than the ATM cells have, from 1 byte up to 4096 bytes. 4. A circuit according to anyone of the proceeding claims wherein, at said CS (C), the Parametric Algorithm (15') on the Receiver Side, or, the Receive Parametric Algorithm (15'), which operates with the control information that programs itself through the requests of the microprocessor, which controls the AAL1 (6) and through the requests of the end users who are connected to the AAL1 (6), where the information going to the PCM bus (2') of the end user on the Receiver Side can be read from any desired place of the ATM cell payload (11 ') and the information can be mapped from other sizes of packets than the ATM cells have, from 1 byte up to 4096 bytes. 5. Parametric Algorithm (15, 15') according to claims 3 and 4 characterised by the features that: the said system that can process 128 channels can read the state information of the corresponding channel during the turn of the corresponding channel; it can write back the next state information of the channel, after having generated the address of the pointer (24) which shows the location where the bit that is currently coming from the PCM bus (2) of the corresponding channel; since every entry of the Pointer Table (18) tells where to place the bit on the PCM bus (2), it can put the corresponding bit into any desired place of the ATM cell, thus it can define the size of the packet and it is capable of processing the PCM information in both the X.30/V.110 format and 64 kbps format. 6. Parametric Algorithm (15') according to claims 3 to 5 characterised by the features that: th said system that can process 128 channels can read the state information of the corresponding channel during the turn of the corresponding channel; it can write back the next state information of the channel, after having generated the address of the pointer (24') which shows the location where the bit that is currently going to the PCM bus (2') of the corresponding channel; since every entry of the Pointer Table (18') tells from where to read bit on the PCM bus (2'), it can read the corresponding bit from any desired place of the ATM cell, thus it can define the size of the packet and it is capable of processing the PCM information in both the X.30/V.110 format and 64 kbps format. 7. A circuit according to anyone of the proceeding claims, charaterized by defining the information of a definite PCM user (2, 2') on the PCM bus in the locations of the ATM cells in any manner, through the parametric algorithms (15, 15') and Pointer Tables (18, 18') embedded inside. 8. A circuit according to anyone of the proceeding claims wherein the Convergence Sublayer (A, C) can be programmed by the microprocessor (13, 13') in any manner, in order to improve the support that is avaible to the user and the user variety. 9. A circuit according to anyone of the proceeding claims characterized by letting the microprocessor to set the size of the packet on the Transmitter and Receiver Sides, placing of information into packets and reading of information from the packets, in the Convergence Sublayer (A, C) inside. 10. A circuit according to anyone of the proceeding claims wherein an AAL1 integrated circuit (B) can map the information of the end users (1) into the packets of size from 1 byte till 4096 bytes, through said Transmit Parametric Algorithm (15) and said Transmit Pointer Table (18). 11. A circuit according to anyone of the proceeding claims wherein an AAL1 integrated circuit (C) can read the information of the end users (1 ') from the packets of size from 1 byte till 4096 bytes, through said Receive Parametric Algorithm (15') and said Receive Pointer Table (18'). 12. A circuit according to anyone of the proceeding claims wherein each of the said parametric algorithms (15, 15') is made up of one counter (27) in reality, on the other side when using them together with state memories, virtually, the number of counters as much as the number of PCM channels (8), which are supported, can be defined. 13. A circuit according to anyone of the proceeding claims wherein Convergence Sublayer (CS) (A, C) includes the Transmit Parametric Algorithm (15) and the Receive Parametric Algorithm, (15'). 14. The present invention is an information transfer system which includes an ATM Adaptation Layer Type:1 integrated circuit that bridges between the PCM bus (2, 2'), where the end users (1 , 1 ') perform information transfer, and the ATM bus (4, 4'), which enable information transfer on a network; where the said integrated circuit contains a flexible Convergence Sublayer (CS) (A, C) and Segmentation and Reassembly sublayer (SAR) (B, D); the said sublayers operating both as a transmitter and as a receiver, the said CS and SAR can be programmed by the microprocessor in any manner, PCM connections of any kind of X.30/V.1 10 frame and/or any transparent format of bit rate frm 1 bps up to 64 kbps, as defined in the corresponding standards; where the information coming from the end users (1) and going to the end user (1 ') can be written in any desired place of the ATM cells and can be read from any desired place of the ATM cells, thanks to the embedded parametric algorithms; where the information of the end user can be defined in the packets of size from 1 byte till 4096 bytes in the Payload RAMs (19, 19'), thanks to the parametric algorithms and the Pointer Tables (18, 18') that those use when executing that, Finite State Machines (15, 15') are used; where the said Parametric Finite State Machines (15, 15') are actually one counter (27) each, on the other side virtually up to desired number of counter can be defined through the state memories named Dynamic Parameter Tables (16, 16').

Inventors: AYDIN OMER, OZCAN UTKU, TOPCU ISMAIL HAKKI, AYDIN, OMER, OZCAN, UTKU, TOPCU, ISMAIL, HAKKI
Applicants: AYDIN OMER, NETAS NORTHERN ELECTRIC TELECO, OZCAN UTKU, TOPCU ISMAIL HAKKI, AYDIN, OMER, NETAS NORTHERN ELECTRIC TELECOMMUNICATION A.S., OZCAN, UTKU, TOPCU, ISMAIL, HAKKI
Application year: 2000
Main classification: H04Q11
IPC codes: H04L12, H04Q11