A STACKED VCO RESONATOR

Abstract: An integrated VCO (10), preferably in a radio ASIC (110), with a resonator comprising an M-M capacitor (80) and a varicap (90), wherein the M-M capacitor (80) is connected to and stacked on top of the varicap (90). Typically, the stacking of the M-M capacitor on top of the varicap is not possible in an ASIC-process due to parasitic capacitance (120, 130). However, since the M-M capacitor (80) already is connected (100) to the varicap (90), the parasitic capacitance (130) is short-circuited. Thus, the stacking of the M-M capacitor on top of the varicap implies reduced resonator dimension saving valuable ASIC area (110) while improving performance.

Description: APPLICANT: TELEFONAKTIEBOLAGET LM ERICSSON TITLE OF INVENTION: A STACKED VCO RESONATOR Field of invention The present invention relates to an integrated VCO, preferably in a radio ASIC, with a resonator comprising capacitors and varicaps. Background of the invention In a radio ASIC there is a need for a stable frequency to move information up and down in frequency. This stable frequency is normally generated by locking an unstable VCO (Voltage Controlled Oscillator) to a very stable reference fre- quency, e.g. 13MHz, using a PLL (Phase Locked Loop)-circuit. In figure 1 a PLL- circuit is disclosed containing a phase detector 150, a filter&amplifier 160, a VCO and a divider with e.g. a dividing factor of 72. The PLL strives for maintaining the same signal frequencies at the inputs I, II of the phase detector. If for example the signal at input I of the phase detector has a reference frequency of 13 MHz (13MHz-clock in the telephone) the other input II of the phase detector 150 strives for having the same frequency. This means that the VCO must run at a frequency of 72 multiplied by 13MHZ equals 936MHz, since the divider divides the signal from the VCO by a factor 72. Thus, the output signal III of the VCO is a very stable 936 MHz-signal, which could be used for the GSM-band. As mobile terminals constantly decrease in size, more and more components have to be integrated on the same ASIC (Application Specific Integrated Circuit). The integration of the VCO on the ASIC will cover a major part of the ASIC area, and since the area cost is the main part of the total ASIC cost it is important to minimise it. The parts of the VCO that consume most area are the inductors, the coupling capacitors and the varicaps. Since the area of the VCO is large, the parasitic capacitance down to the silicon substrate is large. The parasitic capacitance acts to decrease the VCO frequency, which reduces the tuning range. Since the Q-value of the parasitic capacitance is rather poor, the parasitic capacitance will reduce the Q-value of the complete resonator. If the Q-value is reduced, the noise performance of the VCO will be degraded, and to compensate for this degradation the power consumption of the VCO has to be increased. Thus, the main object of the present invention is to reduce the area of an on-chip VCO. Summary of the invention The above object is achieved by means of an integrated VCO, preferably in a radio ASIC, with a resonator comprising capacitors and varicaps, wherein the capacitors are connected to and stacked on the varicaps. Thanks to this stacking arrangement, the dimension of the resonator in the VCO is reduced saving a lot of valuable ASIC-area. Since the capacitors are connected to the varicaps, the parasitic capacitance is short-circuited implying an increased tuning range, improved noise performance and power consumption. An advantageous way of implementing the above varicap is to use a collector-base junction in a bipolar process or a MOS-structure, which is claimed in claim 3 and 4, respectively. 5 In a preferred embodiment of claim 6, the capacitor is a Metal-Metal capacitor. Other characteristics of the invention are set out in the other dependent claims. l o Brief description of the drawings The present invention will now be described in more detail with reference to preferred embodiments of the present invention, given only by way of examples, and illustrated in the accompanying drawings in which: Fig. 1 illustrates the VCO-function in a PLL; 15 Fig. 2 discloses a schematic view of the parasitic capacitance between a capacitor and a varicap in an integrated VCO; Fig. 3 illustrates a schematic view of the stacking principle of the capacitor and the varicap according to the present invention; Fig. 4 is an implementation of an integrated VCO; and 0 Fig. 5 is a schematic view of on-chip capacitors and varicaps according to prior art. Detailed description of embodiments of the invention It should be emphasised that this invention is related to pending applica- 25 tions titled "A Dual Band VCO" and "A VCO Switch, applicant: Telefonaktiebo- laget LM Ericsson, inventors: Magnus Nilsson (A Dual Band VCO), Magnus Nilsson, Thomas Mattsson (A VCO Switch). These applications, "A Dual band VCO" and "A VCO Switch", respectively are herewith to be incorporated in this application by reference. The embodiments that will now be discussed reduce the area of an on-chip VCO, while improving the performance of the VCO. Figure 2 discloses a Metal-Metal capacitor 80 used as a coupling capacitor in the resonator of the VCO. This Metal-Metal capacitor will now be referred to as an M-M capacitor. The M-M capacitor 80 contains two metal plates 20, 40 and an insulating layer 30 between the same plates. Figure 2 also discloses a varicap 90 comprising an n-electrode 70 and a p-electrode 50 and a pn-junction 60 between the same electrodes 50, 70. It should be emphasised that varicap in this application is defined as a voltage controlled capacitance. The idea of the invention is to use the M-M capacitor and stack it on top of the varicap as can be seen in figures 2 and 3, respectively. In this way the capacitor 80 is put on top of the varicap 90 which means that resonator of the VCO will take up less space on the chip 110 (substrate). In prior art the M-M capacitor 80 has always been positioned beside the varicap 90 on the chip 110 as can be seen in figure 5. The reason for position the capacitor 80 and the varicap 90 beside each other on the chip 110 (see figure 5) is that it is normally not allowed in an ASIC-process to put the M-M capacitor on top of the varicap due to the increased parasitic capacitance 120 that will occur between the M-M capacitor 80 and the underlying varicap 90 (see figure 2). Due to this parasitic capacitance 120 an unwanted voltage will lie over the parasitic capacitance 120, and an unwanted current (RF-signal) will float between the M-M capacitor 80 and the varicap 90. The parasitic capacitance in figure 5 will affect the Q-value of the resonator in a detrimental way. However, the present invention according to figure 3 is related to the integration of a VCO and a resonator on a radio ASIC. In the resonator, the coupling capacitor 80, i.e. the M-M capacitor, is always connected 100 to the varicap 90, which implies that the parasitic capacitance 130 is short-circuited. This means that there are no problems anymore to stack the M-M capacitor on top of the varicap as can be seen in figure 3, since the parasitic capacitance 130 does not affect the resonator i.e. no current will float through the parasitic capacitance. By stacking the coupling capacitor 80 on the varicap 90 as is shown in figure 3, the area consumption of the VCO can be reduced by a factor 2 if using external inductors. If the inductors are integrated on the chip, the area consumption of the VCO will be reduced by 25 percent. Since the parasitic capacitance 130 of the coupling capacitor 80 is removed, the tuning range can be increased, and the noise performance and the power consumption will be improved. It should be realised that instead of a pn-junction, any means with capaci- tive properties could be used, i.e. a MOS-structure etc. The varicap could for ex- ample be a collector-base junction in a bipolar process. The embodiments described above relate only to one capacitor stacked on one varicap. It should of course be realised that several or all capacitors 80 in the VCO 10 normally are stacked on top of the varicaps 90. Figure 4 discloses an implementation of a VCO in a radio ASIC. The lower part is the active part of the VCO consuming only a small part of the ASIC silicon area. The upper part is the resonator containing inductors 120, coupling capacitors 80 and varicaps 90 consuming a major part of the ASIC silicon area. The inductors 120 normally consume the same area as the coupling capacitors 80 and the varicaps 90 together. A way to improve the Q-value of the VCO is to put the inductors 120 outside the ASIC-circuit. When implementing the VCO 10 according to figure 4 on the chip 1 10, the coupling capacitors 80 in figure 4 are stacked on the varicaps 90. The stacking principle described above has been successfully tested in a laboratory environment. It should be realised that the VCO 10 could be implemented in an arbitrary electronic circuit. However, in the preferred embodiment, the VCO is to be inte- grated in a radio ASIC in a mobile terminal, i.e. a mobile telephone or a mobile computer. It would be appreciated by those of ordinary skill in the art that the present invention could be embodied in other specific forms without departing from the spirit or essential character thereof. The presently disclosed embodiments are therefore considered in all respects to be illustrative and not restrictive. The scope of the invention is indicated by the appended claims rather than the foregoing description, and all changes which come within the meaning and range of equivalence thereof are intended to be embraced therein.

Claims: Claims 1. An integrated VCO (10), preferably in a radio ASIC, with a resonator comprising a capacitor (80) and a varicap (90), characterised in that said capacitor (80) is connected to and stacked on said varicap (90). 2. An integrated VCO as claimed in claim 1, characterised in that said varicap is a diode (90). 3. An integrated VCO as claimed in claim 2, characterised in that said diode is a collector-base-junction in a bipolar process. 4. An integrated VCO as claimed in claim 1, characterised in that said varicap is a MOS-structure. 5. An integrated VCO as claimed in any of the preceding claims, characterised in that said capacitor is a coupling capacitor (80). 6. An integrated VCO as claimed in any of the preceding claims, characterised in that said capacitor (80) is a Metal-Metal capacitor. 7. An integrated VCO as claimed in any of the preceding claims, charac- terised in that said capacitor (80) and said varicap (90) of said resonator are integrated on the substrate (110) of an integrated circuit. 8. An integrated VCO as claimed in any of the preceding claims, characterised in that it contains several capacitors (80) with their associated varicaps (90), wherein said capacitors are connected and stacked on top of said varicaps. 9. An integrated VCO as claimed in any of the preceding claims, characterised in that it is integrated on a radio ASIC (110). 10. A radio ASIC, characterised in that it comprises an integrated VCO according to any of claims 1 to 9. 11. A mobile terminal, characterised in that it comprises an integrated VCO and/or a radio ASIC according to any of claims 1 to 10. 12. An electronic device, preferably a computer, characterised in that it comprises an integrated VCO and/or a radio ASIC according to any of claims 1 to 10.

Inventors: NILSSON MAGNUS, NILSSON, MAGNUS
Applicants: ERICSSON TELEFON AB L M, TELEFONAKTIEBOLAGET LM ERICSSON (PUBL)
Application year: 2000
Main classification: H03B5
IPC codes: H01L27, H03B5, H03B7, H03L7