Cavity resonator for reducing phase noise of voltage controlled oscillator and method for fabricating the same

Abstract: A cavity resonator for reducing the phase noise of microwaves or millimetre waves output from a monolithic microwave integrated circuit (MMIC) voltage controlled oscillator (VCO) by using silicon (Si) or a compound semiconductor and a micro electro mechanical system (MEMS), and a method for fabricating the cavity resonator are provided. In the cavity resonator, instead of an existing metal cavity, a cavity which is obtained by finely processing silicon or a compound semiconductor is coupled to a microstrip line (30) to allow the cavity resonator to be adopted in a reflection type voltage controlled oscillator. A pole (40) is provided to connect the edge of the microstrip line (30) to a predetermined location of a cavity lower thin film (10). A coupling slot (50) is formed by removing a predetermined width of a cavity upper thin film (20) adjacent to the pole (40) which comes in contact with the cavity upper thin film (20). A resistive thin film (60) for impedance matching is formed around the cavity lower thin film (10) which comes in contact with the pole (40). Consequently, the cavity resonator reduces the phase noise of microwaves or millimetre waves which are output from a voltage controlled oscillator.

Description: The present invention relates to a cavity resonator for reducing the phase noise of microwaves or millimetre waves output from a monolithic microwave integrated circuit (MMIC) voltage controlled oscillator (VCO) by using silicon (Si) or a compound semiconductor and a micro electro mechanical system (MEMS), and a method for fabricating the cavity resonator. Conventional MMICs or hybrid VCOs frequently use dielectric disks or transmission lines as resonators. However, dielectric resonators for micro/millimetre waves are very expensive and are difficult to mass produce because the frequency at which resonance occurs depends on the locations of dielectric resonators, and thus it is difficult to determine the locations of dielectric resonators in an MMIC substrate or hybrid VCO substrate. Moreover, the Q-factor of transmission line resonators are too small to reduce phase noise. US-A-5821836 discloses a miniature silicon micromachined resonance chamber, fed with a microstrip line and a slot in the ground layer. According to the invention, there is provided a cavity resonator for reducing the phase noise of a voltage controlled oscillator. The cavity resonator includes a cavity formed by shaping a semiconductor into a rectangular parallelepiped and plating the surfaces of the rectangular parallelepiped with a conductive thin film. A microstrip line serves as a waveguide at a predetermined distance from the upper thin film of the cavity. A pole couples the end of the microstrip line to a predetermined location of the lower thin film of the cavity. A coupling slot is formed by removing a section having a predetermined width of part of the upper thin film of the cavity. The part of the upper thin film comes in contact with the pole. A resistive thin film is formed around the part of the lower thin film which comes in contact with the pole, for impedance matching. The cavity resonator of the invention reduces the phase noise of a voltage controlled oscillator. Instead of a conventional metal cavity, a cavity which is obtained by finely processing silicon or a compound semiconductor is combined with a microstrip line to allow the cavity resonator to be used in a reflection type voltage controlled oscillator. Preferably, the conductive thin film, the microstrip line and the metal pole, are formed of gold (Au). There is also provided a method for fabricating a cavity resonator for reducing the phase noise of a voltage controlled oscillator, wherein first, second and third wafers are made and a metal cavity is coupled to a microstrip line via a conductor pole. The method includes the step of forming a microstrip line pattern by depositing chromium (Cr) on one surface of the first wafer and patterning the chromium, and forming the microstrip line by plating the microstrip line pattern with gold. An upper metal pole and a cavity upper thin film are formed on a via-hole and the other surface of the first wafer, respectively, by plating the other surface of the first wafer with gold after forming the via-hole on the other surface of the first wafer. A cavity lower thin film is formed by depositing gold plate and a resistive thin film on the surface of the third wafer, after forming a pattern on one surface of the third wafer by depositing chromium (Cr) on the surface of the third wafer, and removing the chromium from a part of the third wafer which will come in contact with the conductor pole and from a part which will be a matching resistor in the third wafer. The second wafer is bonded to the third wafer. A cavity is formed by etching the second wafer bonded to the third wafer until the cavity lower thin film formed on the third wafer is exposed, while allowing the part of the second wafer which will be the lower part of the conductor pole to remain. The metal cavity and a lower metal pole are formed by plating the cavity and the part which will be the lower part of the conductor pole with chromium (Cr) and gold (Au). The first wafer is bonded to the exposed surface of the second wafer, which is bonded to the third wafer, such that the metal pole formed in the via-hole of the first wafer is coupled to the lower metal pole formed on the second wafer. An example of the invention will now be described in detail with reference to the accompanying drawings, in which: FIG. 1A shows the shape of a cavity which is adopted in a cavity resonator according to the present invention; FIGS. 1B and 1C are a plan view and a sectional view, respectively, for showing the schematic structure of a cavity resonator according to the present invention; FIGS. 2A through 2G are sectional views for showing the steps of a method for fabricating a cavity resonator according to the present invention; and FIG. 3 is a simulated S-parameter of the cavity resonator depicted in FIGS. 1B and 1C. The same reference numerals or characters in different drawings represent the same element, and thus their description will not be repeated. The phase noise of oscillators is one of the most important factors influencing the performance of transmitting and receiving systems. The resonance frequency of a rectangular parallelepiped metal cavity, as shown in FIG. 1A, is expressed as the following formula. Reference characters a, b and c indicate the width, depth and length, respectively, of the rectangular parallelepiped metal cavity. f 0 = V ph 2 l a + m b + n c Here, V ph is a phase velocity inside the cavity and l, m and n are integers indicating resonance modes. There are three kinds of Q factors used for measuring the performance of a cavity. The three Q factors are defined as follows: unloaded Q (Q U ): Q U = f 0 /Δf = (2πf 0 )W/P loss loaded Q (Q L ): unloaded Q considering the input and output load external Q (Q E ): 1/Q E = 1/Q L -1/Q U . Here, f 0 is a resonance frequency, W is stored energy, and P loss is lost energy. Phase noise is inversely proportional to the square of the Q value of a resonator so that a resonator having a large Q value must be used to reduce phase noise. To excite the resonator, electromagnetic wave energy is coupled to the cavity of the resonator using a coaxial cable, a waveguide or a microstrip line ,or through an aperture. As shown in FIGS. 1B and 1C, a cavity resonator of the present invention is fabricated using a fine semiconductor processing technology in such a manner that electromagnetic wave energy is coupled to an electric or a magnetic field within a resonator via a microstrip line. In other words, a cavity resonator of the present invention is fabricated using a micro electro mechanical system (MEMS), such that electromagnetic waves of a resonance frequency are totally reflected, and electromagnetic waves of the other frequencies are attenuated by a matching resistor in the cavity resonator. FIG. 1B is a plan view for showing the schematic structure of the cavity resonator according to the present invention. FIG. 1C is a sectional view taken along the line A-A' of FIG. 1B. In the cavity resonator according to the present invention, instead of a conventional metal cavity, a cavity, which is obtained by finely processing silicon or a compound semiconductor, is combined with a microstrip line to allow the cavity resonator to be adopted in a reflection type voltage controlled oscillator. Specifically, the cavity resonator for reducing the phase noise of a voltage controlled oscillator according to the present invention, includes a rectangular parallelepiped cavity defined by thin gold (Au) films, and a microstrip line 30 which is formed of a thin gold film to serve as a waveguide at a predetermined distance from a cavity upper thin film 20. The cavity resonator also includes a pole 40 for connecting the end of the microstrip line 30 to a predetermined location of a cavity lower thin film 10 of the cavity. A coupling slot 50 is formed by removing a section having a predetermined width of the cavity upper thin film 20 adjacent to the pole 40 which also comes in contact with the cavity upper thin film 20. A resistive thin film 60 is formed around the cavity lower thin film 10 which comes in contact with the pole 40. In the fabrication of the cavity resonator for reducing the phase noise of a voltage controlled oscillator, as shown in FIG. 2A, chromium (Cr) is deposited on the top surface of a first wafer 100 and then patterned to form a microstrip line pattern 30b. The microstrip line pattern 30b is plated with gold 30a, thereby forming the microstrip line 30. Next, as shown in FIG. 2B, a via-hole 100a and a coupling slot 50 are formed on the bottom surface of the first wafer 100. Then, the sidewall of the via-hole 100a is plated with gold, thereby forming an upper metal pole 40' in the via-hole 100a. Then, as shown in FIG. 2C, chromium (Cr) is deposited on the top surface of a third wafer 300 and patterned to form patterns used for forming a part 10, which will come in contact with a conductor pole, and a matching resistor 60. Then, gold plate and a resistive thin film are deposited on a resultant structure. Thereafter, as shown in FIG. 2D, a second wafer 200 is bonded to the third wafer 300. Then, as shown in FIG. 2E, wet or dry etching is performed on the surface of the second wafer 200 until the patterns of the third wafer are exposed, while a part 40a of the second wafer 200, which will be a conductor pole, is left, thereby forming a cavity. Next, as shown in FIG. 2F, the cavity and the pole 40a are plated with chromium (Cr) and gold (Au), thereby forming a metal cavity and a lower metal pole 40". Finally, as shown in FIG. 2G, the first wafer 100 is bonded to the top surface of the second wafer 200, which has been bonded to the third wafer 300, such that the upper metal pole 40', which is formed in the via-hole 100a, comes in contact with the lower metal pole 40". FIG. 3 shows the characteristic of a simulated parameter S11 of the cavity resonator which is fabricated through the above processes. Simulated resonance frequency is 31.4GHz and the simulated parameter S11 is approximately 1 at the simulated resonance frequency. As described above, in a cavity resonator for reducing the phase noise of a voltage controlled oscillator according to the present invention, instead of an existing metal cavity, a cavity, which is obtained by finely processing silicon or a compound semiconductor, is coupled to a microstrip line to allow the cavity resonator to be adopted in a reflection type voltage controlled oscillator. A pole is provided to connect the edge of the microstrip line to a predetermined location of a cavity lower thin film. A coupling slot is formed by removing a predetermined width of a cavity upper thin film adjacent to the pole which comes in contact with the cavity upper thin film. A resistive thin film for impedance matching is formed around the cavity lower thin film which comes in contact with the pole. Consequently, the cavity resonator of the present invention reduces the phase noise of microwaves or millimetre waves which are output from a voltage controlled oscillator.

Claims: A cavity resonator for reducing the phase noise of a voltage controlled oscillator, the cavity resonator comprising: a cavity formed by shaping a semiconductor into a rectangular parallelepiped and plating the surfaces of the rectangular parallelepiped with a conductive thin film; a microstrip line (30) for serving as a waveguide at a predetermined distance from the upper thin film (20) of the cavity; a coupling slot (50) formed by removing a section having a predetermined width of part of the upper thin film (20) of the cavity, characterised by a pole (40) for coupling the end of the microstrip line (30) to a predetermined location of the lower thin film (10) of the cavity; said part of the upper thin film (20) coming in contact with the pole (40); and a resistive thin film (60) formed around the part of the lower thin film (10) which comes in contact with the pole (40), for impedance matching. The cavity resonator of claim 1, wherein the conductive thin film is formed of a conductor selected from the group consisting of gold (Au), silver (Ag) and copper (Cu). The cavity resonator of claim 1 or 2, wherein the microstrip line (30) is formed of a conductor selected from the group consisting of gold (Au), silver (Ag) and copper (Cu). The cavity resonator of claim 1, 2 or 3, wherein the pole (40) is formed of gold (Au) or the surface of the pole is plated with gold (Au). A method for fabricating a cavity resonator for reducing the phase noise of a voltage controlled oscillator, wherein first, second and third wafers are made and a metal cavity is coupled to a microstrip line via a conductor pole, the method comprising the steps of: forming a microstrip line pattern by depositing chromium (Cr) on one surface of the first wafer and patterning the chromium, and forming the microstrip line by plating the microstrip line pattern with gold; forming an upper metal pole and a cavity upper thin film on a via-hole and the other surface of the first wafer, respectively, by plating the other surface of the first wafer with gold after forming the via-hole on the other surface of the first wafer; forming a cavity lower thin film by depositing gold plate and a resistive thin film on the surface of the third wafer, after forming a pattern on one surface of the third wafer by depositing chromium (Cr) on the surface of the third wafer, and removing the chromium from a part of the third wafer which will come in contact with the conductor pole and from a part which will be a matching resistor in the third wafer; bonding the second wafer to the third wafer; forming a cavity by etching the second wafer bonded to the third wafer until the cavity lower thin film formed on the third wafer is exposed, while allowing the part of the second wafer which will be the lower part of the conductor pole to remain; forming the metal cavity and a lower metal pole by plating the cavity and the part which will be the lower part of the conductor pole with chromium (Cr) and gold (Au); and bonding the first wafer to the exposed surface of the second wafer, which is bonded to the third wafer, such that the metal pole formed in the via-hole of the first wafer is coupled to the lower metal pole formed on the second wafer.

Inventors: CHEON CHANGYUL, KANG SEOKJIN, KIM CHUNGWOO, KWON YONGWOO, SONG CIMOO, SONG INSANG, CHEON, CHANGYUL, KANG, SEOKJIN, KIM, CHUNGWOO, KWON,YONGWOO, SONG, CIMOO, SONG, INSANG, Kang, Seokjin, Samsung Advanced Institute of Tec., Kim, Chungwoo, Samsung Advanced Institute of Tec., KWON,YONGWOO 123-902 PARK TOWN SAMIK APT., Song, Cimoo, Samsung Advanced Institute of Tec., Song, Insang, Samsung Advanced Institute of Tec.
Applicants: SAMSUNG ELECTRONICS CO LTD, SAMSUNG ELECTRONICS CO., LTD.
Application year: 2000
Main classification: H01P7
IPC codes: H01P5, H01P7, H01P11