RMS-DC CONVERTER HAVING GAIN STAGES WITH VARIABLE WEIGHTING COEFFICIENTS

Abstract: An RMS-DC converter generates a series of progressively amplified signal pairs which are then multiplied and weighted in such a way as to cancel uncorrelated noise while still providing true square-law response. The converter includes two series of gain stages for generating the amplified signal pairs, and a series of four-quadrant multipliers for multiplying and weighting the amplified signal pairs in response to series of weighting signals. The outputs from the multipliers are summed and averaged, and a final output signal is generated by integrating the difference between the averaged signal and a reference signal. To preserve the square-law response over a wide range of input voltages, the system is servoed by feeding the final output signal back to an interpolator which generates the weighting signals as a series of continuously interpolated, overlapping, Gaussian-shaped current pulses having a centroid that moves along the length of the interpolator as the final output signal varies. An embodiment can also be implemented with a single series of gain stages that generate a series of amplified signals which are squared, weighted, and averaged.

Description: RMS-DC CONVERTER HAVING GAIN STAGES WITH VARIABLE WEIGHTING COEFFICIENTS BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates generally to RMS-DC converters, and more particularly, to RMS-DC converters which utilize gain stages and variable weighting coefficients to provide a very wide measurement range. 2. Description of the Related Art RMS-DC converters are used to convert the RMS (root-mean-square) value of an arbitrary signal into a quasi-DC signal that represents the true power level of the signal. Various techniques have been devised for performing RMS-to-DC conversions at frequencies ranging from DC to several GHz, some of which are disclosed in co-pending U.S. Patent Application Nos. 09/245,051 filed February 4, 1999 and 09/256,640 filed February 24, 1999 which are by the same inventor as the present application, and are incorporated herein by reference. Performing accurate RMS-DC conversions over a wide dynamic range has proven difficult, especially at RF frequencies of several GHz. The need for wide dynamic range true-power measurement at very high frequencies has become more critical because the signals generated by modern communications systems such as those using CDMA have very wide instantaneous bandwidth and complex waveforms, with high crest factors, and because operating f equencies are continuously being pushed higher. Logarithmic amplifiers (log amps) are often used to measure the power of RF signals because they can provide a good indication of power over a very wide bandwidth, but the measurement depends on the waveform of the RF signal. Synchronous log amps are of special interest in this regard because they reduce the noise floor compared to other log amps, and therefore, provide extended dynamic range. A synchronous log amp is disclosed in U.S. Patent No. 5,298,811 which issued to the inventor of the present application and which is incorporated by reference. However, logarithmic amplifiers, including synchronous log amps, do not provide an RMS response. When a signal of substantial amplitude is applied to a log amp, most of the amplifier cells operate in a limiting mode which precludes the attainment of a square-law response in the constituent detector cells, or in the sum of their outputs. SUMMARY In one aspect of the present invention, a series of cascaded gain stages generate a series of progressively amplified signals which are squared and weighted and then summed to provide a true square-law response. In another aspect of the present invention, two parallel series of cascaded gain stages generate a series of progressively amplified signal pairs which are multiplied and weighted and then summed to provide a true square-law response while also canceling uncorrelated noise. In a further aspect of the present invention, two signals are generated by exponential signal generators responsive to an input signal, and combined to provide an output signal which approximates the squared value of the input signal. In another aspect of the present invention, four signals are generated by exponential signal generators responsive to two input signals, and combined to provide an output signal which approximates the multiplication of the input signals. In an additional aspect of the present invention, an exponential signal is generated responsive to an input signal by maintaining a constant current in a first pair of series-connected junctions, thereby generating a first voltage across the first pair of junctions; and driving a second pair of series-connected junctions with a voltage equal to the first voltage minus the voltage of the signal. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a simplified schematic of an embodiment of a backbone of an RMS-DC converter in accordance with the present invention. FIG. 2 is a simplified schematic of an embodiment of an RMS-DC converter in accordance with the present invention which utilizes a backbone similar to that of FIG. 1. FIG. 3 is a schematic diagram of an alternative embodiment of an averaging circuit for the system of FIG. 2 in accordance with the present invention. FIG. 4 is a schematic diagram of a second alternative embodiment of an averaging circuit for the system of FIG. 2 in accordance with the present invention. FIG. 5 is a simplified schematic showing how the system of FIG. 2 can be configured for operation in a measurement mode in accordance with the present invention. FIG. 6 is a simplified schematic showing how the system of FIG. 2 can be configured for operation in a controller mode in accordance with the present invention. FIG. 7 is a simplified schematic showing how the system of FIG. 2 can be configured for operation in a measurement mode for measuring true power in a nonlinear load in accordance with the present invention. FIG. 8 is a schematic diagram of a preferred embodiment of a wideband amplifier cell in accordance with the present invention suitable for use in a practical implementation of the circuit of FIG. 2. FIG. 9 shows the large-signal gain function of the wideband amplifier cell of FIG. 8. FIG. 10 is a schematic diagram of an embodiment of a four-quadrant multiplier in accordance with the present invention for use in a practical implementation of the circuit of FIG. 2. FIG. 11 is a simplified schematic diagram of an embodiment of an averaging circuit in accordance with the present invention for a practical implementation of the circuit of FIG. 2. FIG. 12 is a schematic diagram showing more details of a practical embodiment of the averaging circuit of FIG. 11. FIG. 14 shows a preferred arrangement of differential attenuators and multipliers in accordance with the present invention for a practical implementation of the circuit of FIG. 2. FIG. 14 is a simplified schematic diagram of an embodiment of a current source in accordance with the present invention suitable for use in the averaging circuit of FIGS. 11 and 12. FIG. 15 is a schematic diagram showing more details of a practical embodiment of the current source of FIG. 14 in accordance with the present invention. FIG. 16 is a schematic diagram of a conventional current mirror. FIG. 17 illustrates the output characteristics of the current mirror of FIG. 16. FIG. 18 is a schematic diagram showing a preferred embodiment of an averaging circuit for a practical implementation of an RMS-DC converter in accordance with the present invention. FIG. 19 is a simplified schematic of an embodiment of an RMS-DC converter which utilizes a single series of gain stages in accordance with the present invention. FIG. 20 is a schematic diagram of an embodiment of a squaring cell in accordance with the present invention. FIG. 21 is a schematic diagram of an embodiment of a four-quadrant multiplier in accordance with the present invention. FIGS. 22 and 23 are simulation plots that illustrate the operation of the multiplier of FIG. 21. DETAILED DESCRIPTION FIG. 1 is a simplified schematic of an embodiment of a backbone of an RMS-DC converter 8 in accordance with the present invention. The system of FIG. 1 includes a first chain or series of gain stages 12A, a second series of gain stages 12B, a first series of four quadrant multipliers Ml, M2, . . . MN, and a second series of weighting multipliers Wl, W2, . . . WN which only need to operate in two quadrants. The first series of gain stages are connected in a cascade arrangement and generate a first series of progressively amplified signals Vk A (k = 1 . . . N) in response to the input voltage V - Likewise, the second series of gain stages generate a second series of progressively amplified signals V kB (k = 1 . . . N) in response to Vm. The signals V IA and V are simply the input voltage VΓ N (plus the noise from sources en A and e n e as described below). The first series of multipliers are coupled to the first and second series of gain stages so that each multiplier Mk generates an output signal in response to the conesponding amplified signals V kA and VkB- Noise sources e nA and e„B are not a separate part of the system but are shown connected in series with the inputs of the first and second series of gain stages to represent the total input-referred thermal noise of each amplifier and to aid in explaining the effects of the thermal noise on the operation of the system of FIG. 1 as described below. The outputs from the first series of multipliers are coupled to the second series of multipliers Wl, W2, . . . WN. Each of the second multipliers Wk multiplies the output from the corresponding first multiplier by a corresponding weighting signal cx to generate a weighted output current I k . The value of the weighting signal ok therefore acts as a weighting coefficient for the kth pair of amplified signals V kA and V k B and their product V kA V kB - The series of weighted output currents l \ , I 2 , . . . I N from the multipliers Wk are then summed at a summing node Nl to generate the summed output current I O U T - Each pair of conesponding multipliers Mk and Wk can be viewed as forming a combined multiplier/weighting stage. An advantage of implementing the output signals I k as cunents is that they can be summed by simply combining the cunents at a summing node Nl . However, the present invention is not limited to embodiments in which the signals are realized as specific voltages or cunents. For example, the multiplier/weighting stages could be implemented so that their output signals are in the form of voltages. In this case, the summing circuit could not be a simple summing node, but would need to be a more complicated circuit capable of summing several voltage signals. As another example, the input signal is shown as a voltage V I N, however, implementations in which the input signal is applied as a cunent are possible. For purposes of explanation, the signals V IN , V A and V kB are hereinafter assumed to be voltages, and the weighted output signals I are hereinafter assumed to be cunent-mode signals. The operation of the system of FIG. 1 will now be described by first considering the multipliers Mk and Wk. In the cunent-mode, the output cunent from Wk is the full product ik = akVkAVkB ( E q- !) where o^ is conectly dimensioned. Assuming the input voltage V IN s applied equally to both series of gain stages, and neglecting at this point the thermal noise of the circuit (represented by e nA and e nB ), then V kA = V B = V , and the weighted output of the k-th multiplier is Ik = OkVk 2 (Eq. 2) The total output is thus IOUT = diVi 2 + α 2 V 2 2 + . . + QNV N 2 = ∑α k V, (Eq. 3) k = l Since the amplification between each stage is G, and assuming the amplifiers are fully linear, the total output (again ignoring noise) is simply IOUT = cήVm 2 + Q! 2 (GV IN ) 2 + . . . + (Eq. 4) When the amplifiers are fully linear, VΓ N 2 can be extracted as follows showing that the system exhibits a square-law response to V I N- However, in a practical system, the amplifiers 12A and 12B are not fully linear, but exhibit a limiting function as described below with reference to FIGS. 8 and 9. In a practical amplifier, large inputs will cause later stages in each chain to limit. To preserve the square-law response over a wide range of input voltages, the system is servoed by adjusting the weighting signals ι, Oz, . . . ^ so that most of the weighting signals are essentially zero, thereby disabling most of the multiplier/weighting stages. Those left in operation respond to a linear replica of the inputs. With the maximum input signal, the system servoes by adjusting the weighting signals so that only the first multiplier/weighting stage is enabled. That is, cή adjusts to a suitable full scale value « FS , and α , α 3 , . . . otø are all set to zero, or very nearly zero as described below. This prevents enors due to a loss of the square-law response which would be caused by limiting in the higher-numbered gain stages or multipliers. For smaller input signals, the system servoes by adjusting the weighting signals. Over the full input signal range, progressively higher numbered multiplier/weightmg stages are enabled and then disabled as the signal decreases, until finally, with a very small input signal, the weighting signals are adjusted so that only the last multiplier/weighting stage is enabled, and the remainder are disabled (i.e., α l5 c , . . . ofa-i are all set to zero, and Q!N is set to cψs). In a practical embodiment, the weighting signals are generated by an interpolator such as that described below with reference to FIG. 2 which does not completely turn off the weighting signals that are set to zero. Instead, they are reduced to a finite, but very small value. Also, the weighting signals "closest" to the large- valued signal may be significantly greater than zero. With a small input signal, the combined gain G N_1 of the N-1 amplifiers in each series of gain stages raises the small input signal to one of substantial amplitude G N_1 VI N and provides a usefully strong drive V A and VN B to the last multiplier MN. Since only the last multiplier/weighting stage is enabled in response to a sufficiently small input signal, the summed output cunent for that condition is: I OUT = α F sG 2(N - 1) V IN 2 (Eq. 6) The signals VkB always have the same waveform as the input signal V IN in theory. However, they are also affected in practice by the thermal noise generated internally within UBSnTUlESHEET(RULE26) the system. This noise is represented in FIG. 1 by sources e„ A and β nB which have essentially the same RMS amplitude, but are fully unconelated. This noise affects the waveforms of V A and VkB by vector summation with V I N as follows: V '„kA = G t Λ V I I M N i +e ■ ΗA (Eq. 7) V kB = G k - 1 4 V IN + e nB (Eq. 8) Their cross-product after weighting is thus which can be manipulated as follows: 2(k- L ouτ = α FS G '^ ^fi^ (Eq. 10) I X Then, using the approximation vl + x ∞ 1 +— when x is small I nB x ouτ = a tx, Fs G 2(k_1) V v m : 1 1 + ■ " (Eq. l l) which can be expanded to: where δ is a very small residue which can be ignored. Then, FS G 2(k - 1) [v iN 2 +e n 2 ] (Eq. 13) where enA = e„B -e n , and δ is disregarded. The baseline output in the absence of any applied signal VIN is then ± T ouτ = — aFS Gv_r 2(W) e e n 2 (Eq. 14) SUBSTTU7E SHEET (RULE 26 This always represents a miniscule instantaneous cunent, but with the dual amplifier scheme shown in FIG. 1, the cross-product averages asymptotically to zero over a sufficiently long interval because of the lack of coherence or conelation between the two noise signals e„ A and e n β. Furthermore, even when averaged over a finite, moderate interval, the effective noise bandwidth is that of a low-pass filter (described below) which is used to extract the average from I OU T- This is in very strong contrast to a single amplifier having a squared noise I OUT wherein the net demodulated noise is that of the full-bandwidth signal, thereby imposing significant limitations on the dynamic range. FIG. 2 is a simplified schematic of an embodiment of an RMS-DC converter 10 in accordance with the present invention. The system of FIG. 2 includes a backbone similar to that of FIG. 1, but each multiplier/weighting stage is implemented more efficiently as a single multiplier having a third input for scaling the multiplication in response to the conesponding weighting signal. Thus, the multiplication and weighting functions are combined in a single cell. This cell will typically, though not necessarily, have a transconductance form, producing a cunent output. The outputs of the multipliers may therefore be coupled directly together at summing node Nl to generate the complete output cunent I OUT - Another difference is that the lower numbered "gain" stages are now implemented as attenuators rather than amplifiers. For example, the lowest gain stage includes resistors Rl A, RIB, and R1C. The output signals from the attenuators are still refened to as amplified signals, although they are "amplified" with a gain of less than one. By implementing some of the gain stages as attenuators, the system can accommodate larger input signals. Therefore, the total number of weighting stages can be increased and the dynamic range of the system can be extended even further. It should also be noted that any suitable number of both the attenuator-type gain stages and the amplifier-type gain stages can be used, including zero in either case, depending on the total input signal range required, and the gain or attenuation at each stage may have any suitable value. A typical value may be lOdB. Thus a total often gain and weighting stages provides an overall dynamic range of lOOdB. The system of FIG. 2 also includes an averaging circuit and an interpolator 14. The averaging circuit includes a capacitor C AV E, which is coupled between the summing node Nl and power supply ground GND, a cunent source 16 which provides a reference cunent I REF to the summing node Nl, and an optional unity gain buffer amplifier 18 which buffers the voltage across C AVE to provide the final output voltage VQU T - Referring again to FIG. 2, the interpolator 18 generates the weighting signals 0 , α 2 , . . . « N in response to the control signal VC TRL - hi a prefened embodiment, the weighting signals are a series of continuous, overlapping Gaussian-shaped current pulses having a centroid whose location moves along the length of the interpolator as V CTRL is varied so that most of the weighting signals are nearly zero, but adjacent stages near the centroid are enabled to some extent. Also, the sum of all the weighting coefficients are typically, though not necessarily, a constant value cψs: N ∑« k = « FS (Eq. 15) k=l An interpolator capable of generating Gaussian-shaped current pulses meeting these requirements is disclosed in U.S. Patent No. 5,077,541 by the same inventor as the present application. In a prefened embodiment, the interpolator is of the type described in co- pending U.S. Patent Application Ser. No. 09/466,050, Atty. Docket No. 1482-117, filed December 17, 1999 entitled "interpolator Having Dual Transistor Ranks and Ratiometric Control" by the same inventor as the present application and which is incorporated by reference. The use of Gaussian-shaped weighting signals produces a small sinusoidal ripple in the enor between the actual response of the system and the response of an ideal RMS measurement system. A linear inteφolator such as that disclosed in U.S. Patent No. 5,432,478, also by the same inventor as the present application, could be used, but would result in a larger, quadratic ripple in the output function. In the embodiment of FIG. 2, the gain stages 12A and 12B are implemented as "G/0" cells or "limiting" cells. That is, the incremental gain is G in response to very small signals, but then falls off to zero as the signal increases in magnitude, as shown in FIG. 9. (These G/0 cells are also refened to as "A/0" cells in other patents and the inventor's literature). The gain stages can be implemented as simple bipolar pairs, in which case the large-signal function is a hyperbolic tangent function (tanh), and the incremental gain has a hyperbolic secant-squared (sech ) form. However, it might be useful to provide a more linear gain function, so multi-tanh cells can be used. Examples of multi-tanh cells are described in U.S. Patent Applications Ser. No. 09/212,089 filed December 15, 1998, and Ser. No. 09/015,614 filed January 29, 1998. Alternatively, the small-signal linearity can be improved using emitter degeneration or any other suitable technique. It should also be noted that the gain stages do not need to be specifically of the limiting type in order for the principles of the present invention to be realized, although all practical amplifiers will eventually reach limiting operation. As with the multipliers Mk and Wk in FIG. 1, the multipliers Mk in FIG. 2 are preferably implemented with cunent outputs to facilitate the summation of their weighted output currents I k , which can be performed by a simple wire connection at a summing node rather than requiring a more complicated summing circuit. However, the present invention is not limited to embodiments having cunent outputs. The system of FIG. 2 can be configured for operation in a measurement mode as shown in FIG. 5, in which case the signal to be measured is applied as the input V ΓN , and the final output voltage V OUT is used as a feedback signal by coupling it back to the interpolator as the control signal V CTRL - With this connection, the system automatically servoes by adjusting the weighting signals until the average value of the output current I O U T is equal to the reference cunent I REF - The output voltage V O U T then indicates the logarithm of the RMS value of the input signal, that is, the output is a linear-in-dB measure of the power of the input signal. Alternatively, the system of FIG. 2 can be configured to operate as a controller. For example, it can be used to control the power delivered to an antenna 22 by an RF power amplifier 24 as shown in FIG. 6, in which case the final output voltage V OUT is used to control the gain of the power amplifier, the input voltage V I N is provided by a directional coupler 26 which samples the power from the amplifier, and a set-point signal is applied to the interpolator as the control signal V CTR L- In this configuration, the feedback path is through the power amplifier and directional coupler. The system servoes until the power output from the amplifier conesponds to the value of the set-point signal. Again, the scaling relationship is linear-in-dB. In the embodiments described above, a single input signal V ΓN is applied equally to the first and second series of gain stages at input terminals TJM_A and IN_B. This provides an accurate measure of the true power conesponding to the input signal V IN , provided this voltage is measured across a linear load. However, by applying separate input signals to the first and second series of gain stages as shown in FIG. 7, the system of FIG. 2 can also be configured to measure the true power in a nonlinear load. Referring to FIG. 7, the voltage V L across a load L is divided down by a resistive attenuator R1,R2 and applied as the first input signal IN_A to the first series of gain stages. A cunent shunt RS is connected in series with the load and generates a voltage which is proportional to the cunent I through the load and used as the second input signal JJSMB. In this configuration, the final output voltage V O UT is used as a feedback signal by coupling it back to the interpolator as the control signal V CTRL , to implement the measurement function. If the circuit of FIG. 2 is used for high frequency (RF) applications, the averaging circuit must accommodate two types of averaging: RF ripple filtering of the carrier signal, and long-term averaging of the modulation envelope. The averaged signal must also be compared to a setpoint. In the averaging circuit shown in FIG. 2, the comparison and averaging functions are performed directly at connection of the reference signal I REF and the averaging capacitor C AVE - TO prevent offset enors when used in the configurations shown in FIGS. 5-7, the averaging circuit should also accommodate an integration function to drive the enor signal to zero. In the averaging circuit shown in FIG. 2, this is inherently performed in the averaging capacitor CA VE , which integrates the enor signal I ERR . When the system has servoed to a particular input signal V I N, I O U T = I REF and I ERR = 0, at which point the voltage on the capacitor remains at a stable value. An alternative averaging circuit is shown in FIG. 3 where a resistor R is connected in parallel with the averaging capacitor C AVE - Here, the averaging function is performed by resistor R and capacitor CA VE - The comparison function is performed by the operational amplifier 20 which integrates the enor signal V ERR which is the difference between the voltage V AVE across the capacitor and a reference voltage V REF - Another alternative averaging circuit is shown in FIG. 4. In the circuit of FIG. 4, the capacitor CA VE is connected between the output terminal and noninverting input terminal of the operational amplifier 20. The noninverting input terminal of the op amp is also connected to node Nl and to V REF through a resistor R. The inverting input terminal of the op amp is grounded. For the averaging circuit of FIG. 4 to work properly in an RMS-DC converter for RF applications, the op amp would need to be a very wide band amplifier, otherwise, some RF ripple filtering would need to be performed before the signal is feed to the amplifier. In a practical monolithic realization, the gain stages, multipliers, and summing circuits shown in FIG. 2 would preferably be implemented with fully differential inputs and outputs as described below. FIG. 8 is a schematic diagram of a prefened embodiment of an amplifier cell suitable for use in a practical implementation of the circuit of FIG. 2. The amplifier of FIG. 8 is based on the circuits disclosed in U.S. Patent Application Ser. No. 09/241,359 titled "Logarithmic Amplifier With Self-Compensating Gain For Frequency Range Extension" filed January 29, 1999 by the same inventor as the present application, and which is herein incorporated by reference. The circuit of FIG. 8 is shown configured as one of the "A" series of amplifiers 12A and includes an differential pair of transistors Ql and Q2 which receive the input signal VkAP and V kA M, which is a differential form of one of the signals V k A shown in FIG. 2. If the circuit of FIG. 8 was used for one of the "B" series of amplifiers, the inputs would be V βP and V sM. The operation of a wideband amplifier such as that shown in FIG. 8 is described in detail in the above-referenced application Ser. No. 09/241,359, but will be briefly summarized here for convenience. Transistors Ql and Q2 are biased by a cunent source transistor Q7 in response to a bias voltage Vβ. The outputs from Ql and Q2 drive emitter-follower transistors Q5 and Q6 through transistors Q3 and Q4 which act mainly as cascodes. By cross-connecting the bases of Q3 and Q4 to a fraction of the total output voltage, the fraction determined by the ratios R6/(R3+R6) and (equally) R5/(R4+R5), the effect of parasitic capacitance at the collectors of Q3 and Q4 can be largely eliminated. The differential output signal V^^ A P, V ( H)A M is provided at the emitters of emitter- follower transistors Q5 and Q6 which are biased by cunent source transistors Q8 and Q9 which are also driven by Vβ. By sampling the load cunents using R5 and R6, and also using positive feedback, the effect of the input capacitance of the following stage can be largely eliminated. The circuit of FIG. 8 provides about lOdB of gain and is down -3dB at about 3.1GHz. FIG. 9 shows the gain function of the wideband amplifier cell of FIG. 8. At low signal levels, the gain is linear and has a slope of "G". As the input signal level increases, the amplifier enters a limiting domain of operation at about ±E where the small signal gain approaches zero. FIG. 10 is a schematic diagram of an embodiment of a four-quadrant multiplier Mk for use in a practical implementation of the circuit of FIG. 2. The circuit of FIG. 10 includes a core of four transistors Q1-Q4 having their emitters connected together at a common node N2. A cunent source transistor Q5 sets up the weighting signal ok in the form of a variable bias cunent (or "tail cunent") to transistors Q1-Q4 at node N2 in response to the control signal Vps k which is generated in the inteφolator 18. The collectors of Ql and Q4 are connected together at node N3 which is connected to output terminal 32, and the connectors of Q2 and Q3 are connected together at node N4 which is connected to output terminal 30. The first "A" signal input terminal 34 is connected to the bases of Ql and Q2 through resistors Rl and R3, respectively, while the second "A" input terminal 36 is connected to the bases of Q3 and Q4 through R5 and R7, respectively. Likewise, the first "B" signal input terminal 38 is connected to the bases of Ql and Q3 through R2 and R6, respectively, while the second "B" input terminal 40 is connected to the bases of Q2 and Q4 through R4 and R8, respectively. The first differential input signal V kA P,V kA M, is applied to terminals 34 and 36, respectively, and the second differential input signal V B P, V βM , is applied to terminals 38 and 40, respectively. The differential output signal I k P - I k M, which is generated at terminals 30 and 32 , is the result of the multiplication of the first and second input signals. By varying the weighting cunent ok, which acts as the tail cunent for Q1-Q4, the transconductance of the entire multiplier is modulated so that the weighting signal acts as a third multiplying input that weights the output of the multiplier of FIG. 10 in proportion to the value of c^. The multiplier of FIG. 10 has a linear input range at its "A" and "B" inputs of about ±40mV, beyond which, the behavior starts to enter a limiting domain of operation. A major advantage of the multiplier of FIG. 10 is that both inputs have the same common mode voltage, and also, the DC response is symmetric with respect to both inputs. The use of Q5 as a current source allows scaling of the multiplication operation in response to the weighting signal. More importantly, the AC response is also identical with respect to both. However, any other type of variable cunent source can be used to achieve the third scaling input, or a fixed cunent source can be used if only a two-input multiplier with no scaling is required. As discussed above, the inteφolator 18 is preferably implemented as an inteφolator having dual transistor ranks such as that described in co-pending U.S. Patent Application Ser. No. 09/466,050, Atty. Docket No. 1482-117, filed December 17, 1999 entitled "Inteφolator Having Dual Transistor Ranks and Ratiometric Control" by the same inventor as the present application and which is incoφorated by reference. If such an inteφolator is used, then each transistor in the second rank of transistors in the inteφolator also functions as the cunent source transistor Q5 in one of the multipliers of FIG. 10. The signal Vps k is then a partially switched voltage signal generated by forcing a partially switched cunent Ips k from the first rank of transistors through a resistor connected to the base of Q5. FIG. 11 is a simplified schematic diagram of an embodiment of an averaging circuit in accordance with the present invention for use in a practical realization of the circuit of FIG. 2. The circuit of FIG. 11 generates the final output voltage V OUT in response to the differential input signal I OUT P, I OUT M which is a differential version of the output signal I OU T of FIG. 2 obtained by separately summing the output signals LP and LJV1 from the multipliers of FIG. 9. Referring again to FIG. 11, resistors R3 and R4 provide a load for the cunents I OU TP and I OUT M. The op amp 20 forces Q9 to absorb the difference between I OUT P and I OUT M. The emitter current of Q9, which is a single-ended replica of the differential input cunent, is summed at node N5 with the cunent I R EF from cunent source 16. Capacitor CAV E , which is also connected to node N5, integrates the enor signal which is the difference between I REF and the cunent through Q9. The voltage across CA VE is then the final output voltage V OUT , which is used to control the inteφolator in the measurement mode. FIG. 12 is a schematic diagram showing more details of a practical embodiment of the averaging circuit of FIG. 11. Referring to FIG. 12, resistors R3 and R4 provide a load for the cunents I O U T P and I OUT M, and also provide bias cunent for cascode transistors Q4 and Q5. Cunent source transistor Ql establishes cunents in Q2 and Q3, which in turn, establish an anchor voltage at the bases of Q4 and Q5 through beta compensation resistor R2. The cunents in Q4 and Q5 are thus replicas of the cunents through Q2 and Q3. By scaling the area ratios between Q2, Q3 and Q4, Q5 the cunent through Ql can be used to set the quiescent cunent through Q4 and Q5 in the absence of any differential between the input cunents I OUT P, I OUT M. Any difference between I O U T P and I O U T M appears as a difference between the collector cunents through Q4 and Q5. Therefore, the quiescent cunent must be large enough to accommodate the largest expected difference between I OUT P and I OUT M. Transistors Q6 and Q7 form a cunent minor which is optionally degenerated by resistors R6 and R7. Transistor Q10 provides beta compensation to the cunent minor in a conventional manner. Transistors Q9 and Ql 1 maintain the cunent minor in a balanced state because any difference between the cunents I O U T P and I OUT M causes capacitor Cl to charge or discharge through Q5 or the minor which alters the cunent in Q9 and Ql 1. For the cunent in the minor to remain balanced, Q9 must absorb the difference, and the result is a cunent through Q9 and Ql 1 which is proportional to the difference between I O U T P and I O U T M. The circuit of FIG. 12 converts the differential input cunent, which exists at a voltage level close to the positive power supply rail Vp, to a single ended cunent through Q9 which can swing very close to the ground rail GND. The cunent source 16 should also be able to source the reference cunent I REF at a voltage all the way down near GND. An embodiment of the cunent source 16 is described below with respect to FIGS 14 and 15. This allows the output voltage V O U T to swing close to GND which makes it easy to use V O U T as the feedback voltage VC TRL for driving the inteφolator when the system is configured as a controller. FIG. 18 is a simplified schematic diagram showing a prefened embodiment of an averaging circuit for a practical implementation of the system of FIG. 2. Referring to FIG. 18, the averaging circuit includes load resistors R3 and R4 which convert the cunents I O U T P and I OUT to voltage signals which are input to an op amp 42 having differential cunent outputs connected to a cunent minor 44. The capacitors across R3 and R4 perfonn high frequency ripple filtering. The op amp 42, which can be a simple gm cell, senses the voltage difference between the nodes NIP and N1M. Any imbalance in the voltage between the nodes causes an imbalance in the cunent outputs of the gm cell. Since the cunent minor 44 maintains equal currents in both sides, the differential output cunent from the op amp charges or discharges the filter capacitor C AVE - The output signal V OUT , which is preferably buffered by buffer amplifier 46, is generated across CAV E - The reference cunent I REF is provided by current source 16 which is connected across the nodes NIP and N1M. An advantage of the circuit of FIG. 18 is that it charges and discharges the capacitor C AVE at the same slew rate. This is in contrast to the circuit of FIG. 12 in which the capacitor is charged quickly by Q9, but only discharges at a rate established by the cunent IR EF - FIG. 13 shows a prefened anangement of differential attenuators and multipliers at the low numbered end of a practical embodiment of the backbone of the system of FIG. 2. As is apparent from FIG. 13, the input resistors to the multiplier cells also function as part of the attenuator network. Therefore, the multipliers Ml and M2 shown in FIG. 13 only include the core of four transistors Q 1 -Q4 shown in FIG. 10. In a practical embodiment of the system of FIG. 2, a dynamic range of over lOOdB can be achieved using four pairs of attenuating gains stages and six pairs of amplifying gain stages, each having lOdB of attenuation or gain. The values of the components should be chosen so that when the output cunent I OUT is equal to the reference cunent I REF , the multiplier or multipliers which are enabled by bias cunents from the inteφolator are operating in the accurate portion of their operating range. That is, they have not reached an output limiting range (as occurs in a logarithmic amplifier) but instead are acting essentially as true squaring cells. FIG. 14 is a simplified schematic of a cunent minor suitable for use as the cunent source 16 in FIGS. 11 and 12, and the cunent minor 44 of FIG. 18, and for other applications as well. Referring to FIG. 14, transistors Q12 and Q13 are configured much like in a basic cunent minor. However, rather than connecting the collector of Q12 back to its base, the collectors of Q12 and Q13 are connected to the noninverting and inverting inputs, respectively, of an op amp 28. The output of op amp 28 drives the bases of Q12 and Q13 and forces their collector voltages to track so that Q12 and Q13 both operate at the same collector voltage. Thus, the output cunent I REF into the collector of Q13 precisely replicates the input cunent I I N into the collector of Q12, even when the collector of Q13 swings all the way down to within a few millivolts of ground. The benefits of the circuit of FIG. 14 can be better understood by considering the conventional cunent minor Q18, Q19 shown in FIG. 16, and the output characteristic of transistor Q19 shown in FIG. 17. In the circuit of FIG. 16, the bases of Q18 and Q19 always operate at about a V B E (~800mV) above GND. When the collector of Q19 is greater than a V BE above GND, the cunent through the collector of Q19 tracks the cunent through the collector of Ql 8 reasonably well. However, when the collector voltage of Q19 drops below V CE(S A T) , the base-collector junction of Q19 begins to saturate, thereby causing a very large enor between the collector cunents of Q18 and Q19. Saturation of Q19 also causes base cunent to be diverted from Q18 through the base-collector junction of Q19. The circuit of FIG. 14, however, eliminates this problem by maintaining the collectors of Q12 and Q13 at the same voltage, all the way down to a within few millivolts of GND. Even though Q12 and Q13 are deeply in saturation when their collectors are much lower than V CE ( S A T) , all of the base cunent to Q12 and Q13 is provided by the op amp, so none of the base cunent required by Q12 is lost in the coupling to Q13. A further advantage of the circuit of FIG. 14 is that, because Q12 and Q13 operate at the same collector voltage, the output impedance is infinite. An additional benefit is that the input offset voltage of the op amp 28 can be relatively high because a few millivolts of offset between the collectors of Q12 and Q13 does not have much effect on the operation of the circuit. Therefore, a simple inexpensive op amp can be utilized. FIG. 15 is a schematic diagram showing more details of a practical embodiment of the cunent source of FIG. 14 in accordance with the present invention. In the circuit of FIG. 15, the op amp 28 is realized as a differential pair of PNP transistors Q14 and Q15 which are loaded by a cunent minor formed by NPN transistors Q16 and Q17. Since the collectors of Q12 and Q13 are equal, the base currents in Q14 and Q15 are also equal, so there is no enor due to base cunents. Also, since the collectors of Q12 and Q13 are equal, the input cunent source 30 must have enough compliance to accommodate the expected voltage swing at the output node N5. Many of the advantages of the present invention can still be realized even with a single series of gain stages as shown in FIG. 19. The system of FIG. 19 is in many respects similar to those of FIGS. 1 and 2, but it only utilizes a single series of gain stages to generate a single series of amplified signals which are individually squared and weighted, and then summed to generate an output signal. The squaring and weighting functions could be performed individually using a series of squaring/weighting stages, each having a squaring cell with a fixed scale factor and a multiplier for weighting the output from the squaring cell by multiplying it with a weighting signal. In a prefened embodiment, however, each squaring/weighting stage includes a single squaring cell (SI, S2, . . . SN) that can simultaneously square and weight the signal from the gain stage responsive to a weighting signal as shown in FIG. 19. The summed output signal I 0 uτ from the system of FIG. 19 is averaged and utilized in the same manner as that in FIGS. 1 and 2. As with the systems of FIGS. 1 and 2, the system of FIG. 19 can be implemented with any number of gain stages, and some of the lower numbered gain stages can be attenuators rather than amplifiers. The system of FIG. 19 provides wide dynamic range power measurement at high operating frequencies, albeit without the benefit of unconelated noise cancellation obtained with a dual series of gain stages. FIG. 20 shows an embodiment of a squaring cell in accordance with the present invention suitable for use as one of the squaring cells SI, S2, . . . SN of FIG. 19. The squaring cell of FIG. 20 includes two exponential cunent generators 52 and 54, which generate output cunents lei and Ic 2 that vary exponentially in response to the differential input voltage Vx which is the difference between the separate signals VxP and VxM. The first exponential current generator 52 includes a first emitter follower transistor Ql which receives the signal VxP at its base and has its emitter connected to the emitter of Q2 which is diode-connected. A cunent source 56 is connected to the collector and base of Q2 at node N6. A second emitter follower transistor Q3 receives the signal VxM at its base and has its emitter connected to the emitter of Q4 through an optional resistor Rs. The base of Q4 is connected to the base of Q2, and the collector of Q4 is connected to a summing node N7. The cunent source 56 maintains a constant cunent I 0 through Ql and Q2, thereby establishing a certain voltage across the series-connected base-emitter junctions of Ql and Q2. Assuming Q1-Q4 have equal emitter areas, and neglecting the effect of Rs for now, the cunent through Q3 and Q4 is: The construction and operation of the second exponential cunent generator 54 is similar to that of generator 52, except that the bases of the emitter follower transistors Q5 and Q7 are connected to receive the opposite signals, so the cunent through Q7 and Q8 is: The cunents Ici and Ic 2 are summed at node N7 to produce a final output cunent I SQR which closely approximates the squared value of the input signal Vx. When the input signal Vx is zero, I SQR has a quiescent offset value of 2I 0 . As the input signal increases in either direction, one of the exponential functions dominates, and I SQR increases accordingly in the positive direction. The square law approximation can be better understood by using Taylor series expansions for the exponential functions. First, the final output current I SQR is: (Eq. 18) The expansions for the general exponential functions e x and e "x are: e x = l + x + — + — + (Eq. 19) 2! 3! 4! and 2 3 4 X X : 1 - X + + (Eq. 20) 2! 3! 4! thus e λ + e " 2 X : 2 + X 2 + (Eq. 21) 12 Using the expansion of Eq. 21 with Eq. 18 yields: which shows that the form of the final output cunent I SQR is dominated by the square term. The squaring cell of FIG. 20 can be optimized for a particular application by including the resistors Rs which alter the cunents Ici and Ic 2 so as to soften the shape of the exponential functions, thereby providing a better approximation to a true square law behavior over a certain range of Vx. The inclusion of the resistors Rs diminishes the effect of the higher-order terms in the series expansion of Eq. 22. When Rs>0, the outputs from the exponential current generators are not truly exponential, but instead, are less than that which would be generated by an exact exponential behavior. As used herein, the term exponential cunent generator refers not only to a circuit that generates a true exponential cunent, but also to a circuit that generates a "sub- exponential" function, that is, an output cunent which follows a nonlinear law which may be deliberately "softened", either by choice of transistor types or geometry, or by choice of bias cunents, or by the inclusion of degeneration resistors Rs so as to result in an output that deviates from an ideal exponential function, as for example, for the purpose of more closely approximating an ideal square law when used for a squaring cell, or an ideal multiplicative law when used for a multiplier circuit as described below. Likewise, as used herein the term exponential cunent or signal refers not only to a true exponential cunent or signal, but also to an altered exponential cunent or signal. It should also be understood that the term exponential cunent generator also refers to any exponential function generator (e.g., voltage rather than current) that can generate exponential or sub-exponential functions which can be used to synthesize a squaring cell or multiplier. To compensate for temperature variations, the cunents I 0 should preferably be made proportional to absolute temperature (PTAT), and Vx is preferably ananged to also be PTAT~for example, as the output of a basic BJT gain stage. An advantage of the circuit of FIG. 20 is that it can accommodate larger input voltage swings than other types of squaring circuits while still maintaining adequate square-law behavior. The peak output current I d in the circuit of FIG. 20 is not limited by the value of a bias cunent source as it is in the squaring cell disclosed in U.S. Patent Application No. 09/245,051 filed February 4, 1999. Also, when the input signal and output cunent Ici of the circuit of FIG. 20 become very large, the output cunent I can still behave according to an approximately exponential function, and the sum of two exponentials can provide a better approximation to a square law than the more-nearly linear behavior encountered with large signals in the squaring cell disclosed in U.S. Patent Application No. 09/256,640 filed February 24, 1999. A further advantage of the circuit of FIG. 20 is that it can operate on a power supply voltage of 2 volts minimum for typical silicon transistors. Many variations of the circuit of FIG. 20 are contemplated by the present invention. For example, in FIG. 20, the cunents I d and I_c 2 are taken from the collectors of Q4 and Q8, and the collectors of Q3 and Q7 are shown connected to the power supply rail Vp. Alternatively, the cunents I d and Ic 2 could be taken from the collectors of Q3 and Q7, in which case, the collectors of Q4 and Q8 would be connected to GND. Although transistors Ql, Q3, Q5, and Q7 are shown as NPN devices and Q2, Q4, Q6 and Q8 are shown as PNP devices, other polarities and device types, including CMOS transistors, can be utilized. Also, the squaring cell of FIG. 20 is suitable not only for use as one of the squaring cells SI, S2, . . . SN of FIG. 19, but for other applications as well. Transistors Ql and Q2, along with cunent source 56, in FIG. 20 form what can be refened to as a "constant cunent stack" because cunent source 56 maintains a constant cunent (or a PTAT current as discussed above, or a quasi-constant cunent as discussed below) through Ql and Q2. Transistors Q3 and Q4 (and optionally Rs) form what can be refened to as a variable cunent stack because the cunent I varies in response to Vx. Different numbers of these stacks can be combined in accordance with the present invention to create additional useful circuits such as the four-quadrant multiplier described below with reference to FIG. 21. If the cunents I 0 from sources 56 and 58 in FIG. 20 are maintained at a constant level, the squaring cell will have a fixed scaling factor. However, if the cunents I 0 are made to vary in response to a control signal, such as one of the weighting signals Gk of FIG. 19, then the scale factor of the squaring cell will vary in response to the weighting signal, and the squaring and weighting functions can be performed simultaneously. In this case, the constant cunent I 0 can be refened to as a quasi-constant current, that is, even though the cunent can be varied, the variation is generally independent of the input signal Vx. As used herein, the term constant cunent refers to both a constant cunent and a quasi-constant cunent. FIG. 21 is a schematic diagram of an embodiment of a four-quadrant multiplier in accordance with the present invention. The multiplier of FIG. 21 is suitable for use as one of the multipliers Mk in a practical implementation of the circuit of FIG. 2, as well as for numerous other applications. The multiplier of FIG. 21 includes four exponential cunent generators, each having a constant cunent stack and a variable cunent stack similar to those in the squaring cell described above with reference to FIG. 20. However, the stacks in the multiplier circuit of FIG. 21 are cross-connected so as to generate two output cunents I MI and I M2 , the difference of which represents the four-quadrant multiplication of the input signals Vx and Vy. The first exponential cunent generator generates the cunent I d and includes a constant cunent stack (Ql, Q2, CS1) driven by VxP and a variable current stack (Q3, Q4) driven by VyP. The second exponential cunent generator generates the cunent Ic 2 and includes a constant cunent stack (Q5, Q6, CS2) driven by VxM and a variable cunent stack (Q7, Q8) driven by VyM. The third exponential cunent generator generates the cunent Ic 3 and includes a constant cunent stack (Q9, Q10, CS3) driven by VyM and a variable cunent stack (Ql 1, Q12) driven by VxP. The fourth exponential cunent generator generates the cunent Ic 4 and includes a constant cunent stack (Q13, Q14, CS4) driven by VyP and a variable cunent stack (Q15, Q16) driven by VxM. The cunents I d and Ic 2 are summed at node N9 to generate I MI , while the cunents Ic 3 and Ic 4 are summed at node N10 to generate IM2- The cunents I M ι and I M2 are converted to voltages by resistors Rπ and R L2 to generate the final output voltage V M - As with the squaring cell of FIG. 20, multiplying behavior of the multiplier of FIG. 21 can be better understood by using Taylor series expansions for the exponential functions. Taking the final output signal as a cunent I M , which is the difference between the cunents lui and I M2 , and using x to denote Vx/2Vχ and y to denote Vy/2Vχ, the final output cunent I M is: I M = I 0 [exp(x+y) + exp(-x-y) - exp(x-y) - exp(y-x)] (Eq. 23) I 0 (e x -e- χ )(e y -e- y ) (Eq. 24) Using the expansions for (e x -e "x ) and (e y -e "y ) yields: IM - (Eq. 25) = In 4xy + -(xy 3 +yx 3 )+- (Eq. 26) The cubic terms are unimportant provided x and/or y are less than 1 (which requires Vx and/or Vy to be less than 2Vχ , that is, less than about 52mV at T=27°C), so the final output cunent is dominated by the "xy" term. If the resistors Rs are included, the exponential functions are modified so as to soften the response to large values of Vx and Vy, while not seriously degrading the accuracy for more moderate values. As with the squaring cell of FIG. 20, the curve-shaping resistors Rs in the multiplier of FIG. 21 are optional, and the currents I d through Ic 4 can be obtained from either end of the variable cunent stacks. If no gain scaling is used, I 0 should preferably be made PTAT to compensate for temperature variations. Also, the cunent sources can be designed to vary I 0 in response to a weighting signal Ok so the multiplying and weighting functions can be performed simultaneously when the multiplier of FIG. 21 is used as one of the multipliers Mk in the circuit of FIG. 2. An advantage of the multiplier of FIG. 21 is that it can accommodate input signals up to about ±300mV at T=27°C. FIGS. 22 and 23 are simulation plots that illustrate the operation of the multiplier of FIG. 21 where 10 = lOOμA and the NPN and PNP transistors have 0.8μm by lOμm emitters. FIG. 22 shows the output voltage V M as Vx is varied between -400mV and +400mV for several different values of Vy. As is apparent from FIG. 22, the multiplier maintains reasonably good linearity until the input signal reaches about ±300mV. FIG. 23 shows the incremental gain of the multiplier vs. frequency for Vy = 50mV, lOOmV, 150 mV, and 200mV. The -3dB points for these voltages are at 1.86GHz, 2.21GHz, 2.59GHz, and 2.87GHz, respectively. Having described and illustrated the principles of the invention in prefened embodiments thereof, it should be apparent that the invention can be modified in anangement and detail without departing from such principles. For example, although he principles of the present invention have been illustrated with embodiments implemented with bipolar junction transistors (BJTs), it will be apparent that they can also be realized in different technologies, including CMOS, usually with fairly minor changes to the detailed design. We claim all modifications and variations coming within the spirit and scope of the following claims.

Claims: CLAIMS 1. A method for performing an RMS-DC conversion comprising: generating a first series of amplified signals with a first series of gain stages; generating a second series of amplified signals with a second series of gain stages, wherein each of the second series of amplified signals forms a pair with a conesponding one of the first series of amplified signals; multiplying and weighting each of the pairs of amplified signals, thereby generating a series of weighted output signals; and summing the weighted output signals, thereby generating a summed output signal. 2. A method according to claim 1 wherein multiplying and weighting each of the pairs of amplified signals includes: multiplying each the first series of amplified signals by a conesponding one of the second series of amplified signals, thereby generating a series of output signals; generating a series of weighting signals; and multiplying each of the series of the output signals by a conesponding one of the weighting signals. 3. A method according to claim 1 wherein multiplying and weighting each of the pairs of amplified signals includes: generating a series of weighting signals; and multiplying each the first series of amplified signals by a conesponding one of the second series of amplified'signals and by a conesponding one of the weighting signals. 4. A method according to claim 1 further including averaging the summed output signal. 5. A method according to claim 4 wherein averaging the summed output signal includes: comparing the summed output signal to a reference signal, thereby generating an enor signal; and integrating the enor signal, thereby generating a final output signal. 6. A method according to claim 4 further including: comparing the average of the summed output signal to a reference signal, thereby generating an enor signal; and integrating the enor signal, thereby generating a final output signal. 7. A method according to 1 claim wherein multiplying and weighting each of the pairs of amplified signals includes: generating a series of weighting signals responsive to a control signal; and multiplying and weighting each of the pairs of amplified signals responsive to the weighting signals. 8. A method according to claim 7 wherein the series of weighting signals is a series of continuously inteφolated cunent pulses. 9. A method according to claim 8 wherein the continuously inteφolated cunent pulses are overlapping Gaussian cunent pulses. 10. A method according to claim 7 further including: applying a single input signal to the first and second series of gain stages; and using the final output signal as the control signal. 11. A method according to claim 7 further including: controlling the output of a variable gain device responsive to the final output signal; generating an input signal by sampling the output from the variable gain device; applying the input signal to the first and second series of gain stages; and using a set-point signal as the control signal. 12. A method according to claim 7 further including: applying a first input signal to the first series of gain stages; and applying a second input signal to the second series of gain stages. 13. A method according to claim 12 further including using the final output signal as the control signal. 14. An RMS-DC converter comprising: a first series of gain stages for generating a first series of amplified signals; a second series of gain stages for generating a second series of amplified signals; and a series of multiplier/weighting stages coupled to the first and second series of gain stages for generating a series of weighted output signals responsive to the first and second series of amplified signals and a series of weighting signals. 15. An RMS-DC converter according to claim 14 wherein each multiplier/weighting stage includes: a first multiplier having a first input coupled to receive one of the first series of amplified signals, a second input coupled to receive one of the second series of amplified signals, and an output; and a second multiplier having a first input coupled to the output of the first multiplier, a second input for receiving one of the series of weighting signals, and an output. 16. An RMS-DC converter according to claim 14 wherein each multiplier/weighting stage includes a multiplier having a first input coupled to receive one of the first amplified signals, a second input coupled to receive one of the second amplified signals, and a third input for receiving one of the series of weighting signals, and an output. 17. An RMS-DC converter according to claim 14 further including an inteφolator for generating the series of weighting signals responsive to a control signal, wherein each of the multiplier/weighting stages is coupled to the inteφolator to receive a conesponding one of the weighting signals. 18. An RMS-DC converter according to claim 14 further including a summing circuit coupled to the series of multiplier/weighting stages for summing the weighted output signals from the multiplier/weighting stages, thereby generating a summed output signal. TE SHEET (RULE26 19. An RMS-DC converter according to claim 18 further including an averaging circuit coupled to the summing circuit for generating a final output signal responsive to the summed output signal. 20. An RMS-DC converter according to claim 19 wherein the summing circuit is a summing node. 21. An RMS-DC converter according to claim 20 wherein the averaging circuit includes: a capacitor coupled to the summing node; and a cunent source coupled to the summing node. 22. An RMS-DC converter according to claim 14 wherein each amplified signal is a differential signal and each multiplier/weighting stage includes: a first pair of input terminals; a second pair of input terminals; four transistors, each having a first terminal coupled to a common node and a second terminal coupled to one of two output terminals; a cunent source coupled to the common node to provide a bias cunent to the four transistors; and eight resistors, each coupled between a third terminal of one of the transistors and one of the output terminals such that the four transistors provide a differential output cunent at the two output terminals in response to the four-quadrant multiplication of the input signals received at the first and second pair of input terminals. 23. An RMS-DC converter according to claim 22 wherein the cunent source is a variable cunent source for providing a variable bias cunent to the four transistors as a weighting signal. 24. An RMS-DC converter according to claim 14 wherein the first series of gain stages includes a series of amplifiers coupled in series. 25. An RMS-DC converter according to claim 14 wherein the first series of gain stages includes a series of attenuators coupled in series. 26. An RMS-DC converter comprising: a series of gain stages for generating a series of amplified signals; a series of squaring/weighting stages coupled to the series of gain stages for generating a series of weighted output signals responsive to the series of amplified signals and a series of weighting signals. 27. An RMS-DC converter according to claim 26 wherein each squaring/weighting stage includes a squaring cell having a fixed scale factor, and a multiplier coupled to the squaring for weighting the output from the squaring cell by multiplying it with a weighting signal. 28. An RMS-DC converter according to claim 26 wherein each squaring/weighting stage includes a squaring cell that can simultaneously square and weight a conesponding one of the amplified signals responsive to a weighting signal. 29. An RMS-DC converter according to claim 26 further including an inteφolator coupled to the series of squaring cells for generating the series of weighting signals. 30. A method for performing an RMS-DC conversion comprising: generating a series of amplified signals with a series of gain stages; squaring and weighting each of the amplified signals, thereby generating a series of weighted output signals; and summing the weighted output signals, thereby generating a summed output signal. 31. A method according to claim 30 wherein squaring and weighting each of the amplified signals includes: squaring each the amplified signals, thereby generating a series of output signals; generating a series of weighting signals; and multiplying each of the output signals by a conesponding one of the weighting signals. 32. A method according to claim 30 wherein squaring and weighting each of the amplified signals includes: squaring each of the amplified signals with one of a series of squaring cells, each squaring cell having a scale factor; generating a series of weighting signals; and controlling the scale factor of each squaring cell responsive to a conesponding one of the weighting signals. 33. A method according to claim 32 wherein generating a series of weighting signals includes generating a series of continuously inteφolated signals. 34. A squaring cell comprising: a first exponential cunent generator for generating a first cunent responsive to an input signal; and a second exponential cunent generator for generating a second cunent responsive to the input signal; wherein the first and second exponential cunent generators are coupled together to combine the first and second cunents. 35. A squaring cell according to claim 34 wherein each of the exponential cunent generators includes: first and second junctions coupled in series between a first input terminal and a node; third and fourth junctions coupled in series between a second input terminal and the node; and a cunent source coupled to the node. 36. A squaring cell according to claim 34 wherein each of the exponential cunent generators further includes a resistor coupled between the third and fourth junctions. 37. A squaring cell according to claim 34 wherein each of the exponential cunent generators includes: a first transistor of a first polarity having a base coupled to a first input terminal for receiving a first side of the input signal; a second transistor of a second polarity having an emitter coupled to an emitter of the first transistor, a base coupled to a node, and a collector coupled to the node; a cunent source coupled to the node; a third transistor of the first polarity having a base coupled to a second input terminal for receiving a second side of the input signal; and a fourth transistor of the second polarity having an emitter coupled to an emitter of the third transistor, and a base coupled to the node. 38. A squaring cell according to claim 37 wherein each of the exponential cunent generators further includes a resistor coupled in series with the third and fourth transistors. 39. A squaring cell according to claim 34 wherein each of the exponential cunent generators includes: a constant cunent stack coupled to a first input terminal; and a variable cunent stack coupled to a second input terminal and the constant cunent stack. 40. A squaring cell according to claim 39 wherein: the constant cunent stack includes a first emitter-follower transistor coupled to a first input terminal, a diode-connected transistor coupled to the emitter follower transistor, and a current source coupled to the diode-connected transistor; and the variable current stack includes a second emitter-follower transistor coupled to a second input terminal, and a fourth transistor coupled between the second emitter-follower transistor and the diode-connected transistor. 41. A squaring cell according to claim 40 wherein the variable cunent stack further includes a resistor coupled between the second emitter-follower transistor and the fourth transistor. 42. A squaring cell according to claim 34 wherein: the first exponential cunent generator includes: a first transistor having a base coupled to a first input terminal, a second transistor having an emitter coupled to an emitter of the first transistor, and a base and collector coupled together at a first node, a first cunent source coupled to the first node, a third transistor having a base coupled to a second input terminal, a fourth transistor having an emitter coupled to an emitter of the third transistor, and a base coupled to the first node; and the second exponential cunent generator includes: a fifth transistor having a base coupled to the second input terminal, a sixth transistor having an emitter coupled to an emitter of the fifth transistor, and a base and collector coupled together at a second node; a second cunent source coupled to the second node; a seventh transistor having a base coupled to the first input terminal; and an eighth transistor having an emitter coupled to an emitter of the seventh transistor, and a base coupled to the second node. 43. A squaring cell according to claim 42 wherein: the first exponential cunent generator further includes a first resistor coupled between the third and fourth transistors; and the second exponential cunent generator further includes a second resistor coupled between the seventh and eighth transistors. 44. A squaring cell according to claim 42 wherein a collector of the fourth transistor is coupled to a collector of the eight transistor at an output node for summing the first and second cunents. 45. A squaring cell according to claim 44 wherein: the first, third, fifth, and seventh transistors include collectors coupled to a first power supply terminal; and the first and second cunent sources are coupled to a second power supply terminal. 46. A squaring cell according to claim 42 wherein a collector of the third transistor is coupled to a collector of the seventh transistor at an output node for summing the first and second cunents. 47. A method for squaring a signal comprising: generating a first cunent which varies exponentially responsive to the signal such that the first cunent increases when the signal increases; generating a second cunent which varies exponentially responsive to the signal such that the second cunent decreases when the signal increases; and combining the first and second cunents. 48. A method according to claim 47 wherein the signal is a voltage signal, and generating the first current includes: maintaining a first constant cunent in a first pair of series-connected junctions, thereby generating a first voltage across the first pair of junctions; and driving a second pair of series-connected junctions with a voltage equal to the first voltage minus the voltage of the signal, thereby generating the first cunent in the second pair ofjunctions. 49. A method according to claim 48 wherein generating the second cunent includes: maintaining a second constant cunent in a third pair of series-connected junctions, thereby generating a second voltage across the third pair ofjunctions; and driving a fourth pair of series-connected junctions with a voltage equal to the second voltage plus the voltage of the signal, thereby generating the second cunent in the fourth pair ofjunctions. 50. A method according to claim 49 wherein combining the first and second currents includes summing the first and second cunents. 51. A method according to claim 47 further including scaling the first and second cunents responsive to a control signal. 52. A method according to claim 48 further including varying the first and second constant cunents. 53. A method according to claim 47 further including altering the first and second cunents. 54. A multiplier comprising: a first exponential cunent generator for generating a first cunent responsive to a first input signal and a second input signal; , a second exponential cunent generator for generating a second cunent responsive to a third input signal and a fourth input signal; a third exponential cunent generator for generating a third cunent responsive to the first input signal and the fourth input signal; and a fourth exponential cunent generator for generating a fourth cunent responsive to the third input signal and the second input signal; wherein the first and second exponential cunent generators are coupled together to combine the first and second cunents; and wherein the third and fourth exponential cunent generators are coupled together to combine the third and fourth cunents. 55. A multiplier according to claim 54 wherein each of the exponential cunent generators includes: first and second junctions coupled in series between a first input terminal and a node; third and fourth junctions coupled in series between a second input terminal and the node; and a cunent source coupled to the node. 56. A multiplier according to claim 55 wherein each of the exponential cunent generators further includes a resistor coupled between the third and fourth junctions. 57. A multiplier according to claim 54 wherein each of the exponential cunent generators includes: a first transistor of a first polarity having a base coupled to a first input terminal for receiving a first side of the input signal; a second transistor of a second polarity having an emitter coupled to an emitter of the first transistor, a base coupled to a node, and a collector coupled to the node; a cunent source coupled to the node; a third transistor of the first polarity having a base coupled to a second input terminal for receiving a second side of the input signal; and a fourth transistor of the second polarity having an emitter coupled to an emitter of the third transistor, and a base coupled to the node. 58. A multiplier according to claim 57 wherein each of the exponential cunent generators further includes a resistor coupled in series with the third and fourth transistors. 59. A multiplier according to claim 54 wherein each of the exponential cunent generators includes: a constant cunent stack coupled to a first input terminal; and a variable cunent stack coupled to a second input terminal and the constant cunent stack. 60. A multiplier according to claim 59 wherein: the constant cunent stack includes a first emitter-follower transistor coupled to a first input terminal, a diode-connected transistor coupled to the emitter follower transistor, and a cunent source coupled to the diode-connected transistor; and the variable cunent stack includes a second emitter-follower transistor coupled to a second input terminal, and a fourth transistor coupled between the second emitter-follower transistor and the diode-connected transistor. 61. A multiplier according to claim 60 wherein the variable cunent stack further includes a resistor coupled between the second emitter-follower transistor and the fourth transistor. 62. A multiplier according to claim 54 wherein: the first exponential current generator includes: a first transistor having a base coupled to a first input terminal, a second transistor having an emitter coupled to an emitter of the first transistor, and a base and collector coupled together at a first node, a first cunent source coupled to the first node, a third transistor having a base coupled to a second input terminal, a fourth transistor having an emitter coupled to an emitter of the third transistor, and a base coupled to the first node; the second exponential cunent generator includes: a fifth transistor having a base coupled to a third input tenninal, a sixth transistor having an emitter coupled to an emitter of the fifth transistor, and a base and collector coupled together at a second node; a second cunent source coupled to the second node; a seventh transistor having a base coupled to a fourth input terminal; and an eighth transistor having an emitter coupled to an emitter of the seventh transistor, and a base coupled to the second node; the third exponential cunent generator includes: a ninth transistor having a base coupled to the fourth input terminal, a tenth transistor having an emitter coupled to an emitter of the ninth transistor, and a base and collector coupled together at a third node, a third cunent source coupled to the third node, an eleventh transistor having a base coupled to the first input terminal, a twelfth transistor having an emitter coupled to an emitter of the eleventh transistor, and a base coupled to the third node; and the fourth exponential cunent generator includes: a thirteenth transistor having a base coupled to the second input terminal, a fourteenth transistor having an emitter coupled to an emitter of the thirteenth transistor, and a base and collector coupled together at a fourth node; a fourth cunent source coupled to the fourth node; a fifteenth transistor having a base coupled to the third input terminal; and a sixteenth transistor having an emitter coupled to an emitter of the fifteenth transistor, and a base coupled to the fourth node. 63. A multiplier according to claim 62 wherein: the first exponential cunent generator further includes a first resistor coupled between the third and fourth transistors; and the second exponential cunent generator further includes a second resistor coupled between the seventh and eighth transistors. the third exponential current generator further includes a third resistor coupled between the eleventh and twelfth transistors; and the fourth exponential cunent generator further includes a fourth resistor coupled between the fifteenth and sixteenth transistors. 64. A multiplier according to claim 62 wherein: a collector of the fourth transistor is coupled to a collector of the eight transistor at a first output node for summing the first and second cunents; and a collector of the twelfth transistor is coupled to a collector of the sixteenth transistor at a second output node for summing the first and second cunents. 65. A multiplier according to claim 64 wherein: the first, third, fifth, seventh, ninth, eleventh, thirteenth, and fifteenth transistors include collectors coupled to a first power supply terminal; and the first, second, third, and fourth cunent sources are coupled to a second power supply terminal. 66. A multiplier according to claim 62 wherein: a collector of the third transistor is coupled to a collector of the seventh transistor at a first output node for summing the first and second cunents; and a collector of the eleventh transistor is coupled to a collector of the fifteenth transistor at a second output node for summing the third and fourth currents 67. A method for multiplying a first signal and a second signal, wherein the first input signal is the difference between a first signal and a third signal, and the second input signal is the difference between a second signal and a fourth signal, the method comprising: generating a first cunent which varies exponentially responsive to the first signal and the second signal; generating a second cunent which varies exponentially responsive to the third signal and the fourth signal; generating a third cunent which varies exponentially responsive to the fourth signal and the first signal; generating a fourth cunent which varies exponentially responsive to the second signal and the third signal; combining the first and second cunents; and combining the third and fourth cunents. 68. A method according to claim 67 wherein the first and second signals are voltage signals, and generating the first cunent includes: maintaining a first constant cunent in a first pair of series-connected junctions, thereby generating a first voltage across the first pair ofjunctions; and driving a second pair of series-connected junctions with a voltage equal to the first voltage plus the voltage difference between the first and second signals, thereby generating the first cunent in the second pair ofjunctions. 69. A method according to claim 68 wherein: generating the second cunent includes: maintaining a second constant cunent in a third pair of series-connected junctions, thereby generating a second voltage across the third pair ofjunctions, and driving a fourth pair of series-connected junctions with a voltage equal to the second voltage plus the voltage difference between the third and fourth signals, thereby generating the second cunent in the fourth pair ofjunctions; generating the third current includes: maintaining a third constant cunent in a fifth pair of series-connected junctions, thereby generating a third voltage across the fifth pair ofjunctions, and driving a sixth pair of series-connected junctions with a voltage equal to the third voltage plus the voltage difference between the fourth and first signals, thereby generating the third cunent in the sixth pair ofjunctions; and generating the fourth cunent includes: maintaining a fourth constant cunent in a seventh pair of series-connected junctions, thereby generating a fourth voltage across the seventh pair ofjunctions, and driving an eighth pair of series-connected junctions with a voltage equal to the fourth voltage plus the voltage difference between the second and third signals, thereby generating the fourth cunent in the eighth pair ofjunctions; and 70. A method according to claim 67 wherein: combining the first and second cunents includes summing the first and second cunents; and combining the third and fourth cunents includes summing the third and fourth cunents. 71. A method according to claim 67 further including scaling the first, second, third, and fourth currents responsive to a control signal. 72. A method according to claim 69 further including varying the first, second, third, and fourth constant currents. 73. A method according to claim 69 further including altering the first, second, third, and fourth currents. 74. A method for generating an exponential cunent responsive to an input signal comprising: maintaining a constant cunent in a first pair of series-connected junctions, thereby generating a first voltage across the first pair ofjunctions; and driving a second pair of series-connected junctions with a voltage equal to the first voltage minus the voltage of the signal, thereby generating the exponential cunent in the second pair ofjunctions. 75. A method according to claim 74 further including altering the exponential cunent. 76. An RMS-DC converter according to claim 20 wherein the averaging circuit includes: a capacitor coupled to the summing node; and an operational amplifier having a first input terminal coupled to the summing node and a second input terminal coupled to receive a reference signal.

Inventors: GILBERT BARRIE, GILBERT, BARRIE
Applicants: ANALOG DEVICES INC, ANALOG DEVICES, INC.
Application year: 2000
Main classification: G01R19
IPC codes: G01R19