Frequency modulation using a digital filter for baseband waveshaping

Abstract: A multi-mode loop frequency modulator (10) for modulating a carrier signal according to various modulation pulse shapings and data signals to provide a modulated output signal (VCOout). The multi-mode loop frequency modulator (10) includes a waveform generator (12) and two multiplexers (14,38) to perform various pulse shaping filtering and/or predistortion of the pulse shaping filter impulse response for either a dual port modulation or for a single port modulation. The waveform generator (12) can optionally provide interpolation for input frequency deviation and can optionally provide scaling for various reference frequency clock signals provided by the crystal (30) and the reference divider (28). The low pass filter (22) is used for providing the phase lock loop filtering and also for providing a smoothing filter for the high port DAC (18).

Description: Field of the Invention This invention, as it is defined in the independent claims relates to a frequency modulator, and more particularly, to a frequency modulator using a waveform generator. Background of the Invention Many digital radio communication systems, such as cellular, cordless and data transmission systems, use FSK (Frequency Shift Key), GFSK (Guaussien Frequency Shift Key), or GMSK (Guaussien Mean Shift Key) modulation techniques. These types of modulation techniques are in fact simply frequency modulation (FM) with the radio frequency (RF) signal envelope constant. Since there is no amplitude modulation (AM) involved in these types of modulation, the voltage controlled oscillator (VCO) frequency of the transmitters can be directly modulated by the baseband signal, as is typical in regular analog FM transmitters, such as in analog cellular systems. Significant cost reductions can be obtained by directly modulating the VCO frequency. Such arrangements are particularly desirable in digital applications where low cost is a strategic factor. For example, the overall cost of a digital solution such as DECT (Digital European Cordless Telephone) must be very low to be competitive with well known analog systems such as CT0 (Cordless Telephone ). In order to avoid any inter-symbol interference which can introduce signal distortion and degrade the bit error rate of the transmission in the digital system, the amplitude transfer function and the group delay transfer function on the modulation path has to be kept constant across the entire spectrum of the baseband signal. This requires the transfer function of the phase lock loop (PLL) to be high enough to pass the entire modulation spectrum. Furthermore, in order to meet the applicable radio specifications, the spectral purity of the RF signal source to be transmitted should be maintained as near the carrier signal as possible for phase noise and modulation accuracy, and should be maintained as far from the carrier signal as possible to reduce harmonics, the noise floor, and discrete spurious signals. As a consequence, the transfer function of the PLL must be low enough to filter the noise. A technique called Dual Port modulation is known to provide the capability to generate a low port modulation signal as well as a high port modulation. The low port modulation signal is used to drive a noise shaping circuit that controls the divider of the PLL, while at the same time the high port frequency modulation signal is used as a input to a high port path which utilizes a digital to analog converter (DAC) to directly drive the input voltage of a voltage controlled oscillator (VCO). The effect of the dual port modulation is to provide a low pass transfer function for the generated noise of the reference clock and the noise shaping circuitry, and to provide an all pass function to the input frequency deviation. Existing dual port modulation circuits have several problems. First, directly coupling the DAC output to the VCO input can produce noise at the output of the VCO. Second, a smoothing filter at the DAC output is needed in order to filter the analog output produced by the DAC. And third, several look-up tables are required to store the frequency deviation pulse shaping values for a given frequency modulation. Some frequency modulations require different crystal clocks to drive the PLL, or for a given crystal clock require different reference clocks for the PLL, in order to provide different band ranges (e.g. for private mobile radio systems). If the reference clock has to be modified, the number of look-up tables must be increased for various reference clocks, which then results in an increased system cost. Patent Specification US 5 548 541 describes a data transmission system including a quadrature phase shift key ('QPSK') modulator for predistorting a data signal, combining the pre-distorted data signal with a carrier signal to produce a modulated output signal but does not envisage the use of a dual ports modulation circuit. Summary of the invention The present invention provides a frequency modulator, a transmitter and a transceiver as described in the accompanying claims. Brief Description of the Drawings A frequency modulator in accordance with the present will now be described, by way of example only, with reference to the accompanying drawings in which: FIG. 1 is a block diagram of a multi-mode loop FM modulator 10 in accordance with one embodiment of the present invention; FIG. 2 is a schematic diagram of one embodiment of a resistive attenuator 20 and loop filter 22 of FIG. 1 in accordance with one embodiment of the present invention; FIG. 3 is a schematic diagram of an alternate embodiment of a resistive attenuator 20 and loop filter 22 of FIG. 1 in accordance with one embodiment of the present invention; and FIG. 4 and FIG. 5 together form a block diagram of a portion of waveform generator 12 of FIG. 1 in accordance with one embodiment of the present invention. Detailed Description of Embodiments of the Invention Description of the Drawings FIG. 1 illustrates one embodiment of a multi-mode loop FM modulator 10. In one embodiment of the present invention an FM waveform generator 12 receives an initial frequency deviation 43 which is used to provide an initial frequency deviation value. FM waveform generator 12 also receives input data by way of input data port 40. Select span length 45, oversampling select 42, decimation select 44, and pulse shaping coefficient input 46 are used to provide control and select information to FM waveform generator 12. FM waveform generator 12 is used to generate a high port frequency deviation signal 54 which is provided to a first input of multiplexer 14. A zero frequency input signal is provided as the second input to multiplexer 14. Mode select signal 48 is provided to multiplexer 14 to select which input of multiplexer 14 is provided to programmable delay circuit 16. The mechanism by which programmable delay circuit 16 is programmed may be either software or hardware, or a combination of hardware and software. The output of programmable delay circuit 16 is coupled to an input of digital to analog converter (DAC) 18. In some embodiments of the present invention the gain of DAC 18 may be programmable. In FIG. 1, the output of DAC 18 is provided to resistive attenuator 20. The output of resistive attenuator 20 is provided to loop filter 22. The output of loop filter 22 is provided to voltage controlled oscillator (VCO) 24. The output of VCO 24 is a signal, called VCO output 41, which is the output of multi-mode loop FM modulator 10. The VCO output signal 41 is also provided to an input of divider 32. In one embodiment of the present invention, divider 32 may divide the VCO output signal 41 by a programmable value N. The value of N may be provided in software or hardware to divider 32 (not shown). The output of divider 32 is provided to both noise shaper 34 and phase detector and charge pump circuit 26. Noise shaper 34 uses the output of divider 32 as a clock signal. In one embodiment of the present invention, noise shaper 34 uses the clock to clock one or more accumulators within noise shaper 34. Phase detector and charge pump 26 receives a signal from divider circuit 28. Divider circuit 28 receives a signal from a crystal 30. Phase detector and charge pump circuit 26 also receives a mode select signal 48 which is used to turn the charge pump on and off. The output of phase detector and charge pump circuit 26 is provided to loop filter 22. Still referring to FIG. 1, a second output of FM waveform generator 12 is low port frequency deviation 56. Low port frequency deviation 56 is provided as an input to multiplexer 38. Multiplexer 38 also receives as an input a zero frequency signal. At least one mode select signal 48 is provided to multiplexer 38 as a select signal to select which input is provided as an output by multiplexer 38 to adder 36. Adder 36 also receives a channel input 50 and an automatic frequency correction for crystal input 52. A channel input 50 may be used to change the channel on which VCO output 41 is provided. The automatic frequency correction for crystal input 52 may be an input added to adder 36 to compensate for deviations between the nominal frequency of crystal 30 and the actual frequency of crystal 30. The output of adder 36 is provided to noise shaper circuit 34. Circuit 11 receives the high port frequency deviation signal 54 and the low port frequency deviation signal 56 from waveform generator 12 and provides the VCO output signal 41. FIG. 2 illustrates one embodiment of resistive attenuator 20 and loop filter 22 of FIG. 1. In one embodiment, resistive attenuator 20 includes resistor 62 and resistor 61; and, loop filter 22 includes resistors 64, 66, and 68, as well as capacitors 63, 65, 67, and 69. A first terminal of resistor 61 is coupled to a first terminal of resistor 62 and a first terminal of capacitor 60. A second terminal of resistor 62 is coupled to receive the output from DAC 18. A second terminal of resistor 61 is coupled to a first power supply voltage. In one embodiment of the present invention, this first power supply voltage is approximately ground. A second terminal of capacitor 60 is coupled to a node 70. Node 70 is also coupled to phase detector and charge pump circuit 26, a first terminal of capacitor 63, a first terminal of resistor 64, and a first terminal of resistor 66. A second terminal of resistor 66 is coupled to a first terminal of resistor 68 and a first terminal of capacitor 67. A second terminal of resistor 68 is coupled to a first terminal of capacitor 69 and is also provided to VCO 24 as an input. A second terminal of resistor 64 is coupled to a first terminal of capacitor 65. A second terminal of capacitor 63 a second terminal of capacitor 65, a second terminal of capacitor 67, and a second terminal of capacitor 69, which are all coupled to the first power supply voltage. FIG. 3 illustrates an alternate embodiment of resistor attenuator 20 and loop filter 22 of FIG. 1. In one embodiment, resistor attenuator 20 includes resistor 82; and, loop filter 22 includes resistors 84, 86, and 88, as well as capacitors 83, 85, 87, and 89. A first terminal of resistor 82 is provided from the output of DAC 18. A second terminal of resistor 82 is coupled to a first terminal of capacitor 80, a first terminal of resistor 84, and a second terminal of capacitor 85. A second terminal of resistor 84 is coupled to the first power supply voltage. The first terminal of capacitor 85 is coupled to a first terminal of capacitor 83 and a first terminal of resistor 86. A second terminal of capacitor 83 is coupled to the first power supply voltage. The second terminal of resistor 86 is coupled to node 91. Node 91 is also coupled to a first terminal of capacitor 87 and a first terminal of resistor 88. The second terminal of resistor 88 is coupled to a first terminal of capacitor 89 and is provided to VCO 24. A second terminal of capacitor 87 and a second terminal of capacitor 89 are both coupled to the first power supply voltage. The first terminal of capacitor 83 is coupled to phase detector and charge pump circuit 26. The second terminal of capacitor 80 is coupled to node 91. FIG. 4 and FIG. 5 together illustrate a portion of FM waveform generator 12 of FIG. 1. Although FIGS. 4 and 5 illustrate a fourth order system, alternate embodiments of the present invention may use any order system. In the embodiment illustrates in FIG. 4, the first order derivative is generated by the circuitry 100-109 and 150. Multiplexer 100 is used to determine whether the coefficients are loaded from pulse shaping coefficient input 46 or from the feedback output provided at the output of storage circuit 107. In one embodiment, storage circuits 102-107 are used to store the coefficients of the first order derivative of the impulse response of the pulse-shaping filter. Multiplier 108 multiplies the coefficient value by the input data value provided at the output of storage circuit 147. The output of multiplier 108 is provided to a summation circuit 109. The output of summation circuit 109 is provided to a storage circuit 150. The output of storage circuit 150 is fed back as one of the addition inputs to the summation circuit 109. The output of storage circuit 150 is also provided to storage circuit 167. In one embodiment of the present invention summation circuit 109 and storage circuit 150 are performing an accumulation function. The second order derivative is generated by the circuitry 110-119 and 151. Multiplexer 110 is used to determine whether the coefficients are loaded from pulse shaping coefficient input 46 or from the feedback output provided at the output of storage circuit 117. In one embodiment, storage circuits 112-117 are used to store the coefficients of the second order derivative of the impulse response of the pulse-shaping filter. Multiplier 118 multiplies the coefficient value by the input data value provided at the output of storage circuit 147. The output of multiplier 118 is provided to a summation circuit 119. The output of summation circuit 119 is provided to a storage circuit 151. The output of storage circuit 151 is fed back as one of the addition inputs to the summation circuit 119. In one embodiment of the present invention summation circuit 119 and storage circuit 151 are performing an accumulation function. The third order derivative is generated by the circuitry 120-129 and 152. Multiplexer 120 is used to determine whether the coefficients are loaded from pulse shaping coefficient input 46 or from the feedback output provided at the output of storage circuit 127. In one embodiment, storage circuits 122-127 are used to store the coefficients of the third order derivative of the impulse response of the pulse-shaping filter. Multiplier 128 multiplies the coefficient value by the input data value provided at the output of storage circuit 147. The output of multiplier 128 is provided to a summation circuit 129. The output of summation circuit 129 is provided to a storage circuit 152. The output of storage circuit 152 is fed back as one of the addition inputs to the summation circuit 129. In one embodiment of the present invention summation circuit 129 and storage circuit 152 are performing an accumulation function. The fourth order derivative is generated by the circuitry 130-139 and 153. Multiplexer 130 is used to determine whether the coefficients are loaded from pulse shaping coefficient input 46 or from the feedback output provided at the output of storage circuit 137. In one embodiment, storage circuits 132-137 are used to store the coefficients of the fourth order derivative of the impulse response of the pulse-shaping filter. Multiplier 138 multiplies the coefficient value by the input data value provided at the output of storage circuit 147. The output of multiplier 138 is provided to a summation circuit 139. The output of summation circuit 139 is provided to a storage circuit 153. The output of storage circuit 153 is fed back as one of the addition inputs to the summation circuit 139. In one embodiment of the present invention summation circuit 139 and storage circuit 153 are performing an accumulation function. Lower frequency clock 180 is used to clock the movement of data in and out of storage circuits 150-153. Still referring to FIG. 4, input data 40 is provided as one input to multiplexer 140. A load data select input of the multiplexer 140 selects whether input data 40 is provided at the output of the multiplexer or whether the feedback path from storage circuit 147 is provided at the output of multiplexer 140. The output of multiplexer 140 is coupled to storage circuit 142. The output of storage circuit 142 is coupled to the input of storage circuit 143. The output of storage circuit 143 is couple to a first input of multiplexer 141. A second input of multiplexer 141 is coupled to the output of multiplexer 140. The output of multiplexer 141 is coupled to the input of storage circuit 144. The output of storage circuit 144 is coupled to the input of storage circuit 145. The output of storage circuit 145 is coupled to the input of storage circuit 146. The output of storage circuit 146 is coupled to the input of storage circuit 147. The output of storage circuit 147 is coupled to an input of multiplexer 140, and to multipliers 138, 128, 118 and 108. Note that although the illustrated embodiment in FIG. 4 allows the select span length to be selected as either 4 or 6, alternate embodiments of the present invention may use more or fewer multiplexers to allow the select span length 45 to be varied in any manner (see multiplexers 101, 111, 121, 131, and 141). Waveform generator 12 also includes an integrator 200 as illustrated in FIG. 5. Summation circuit 160 receives inputs from storage circuit 153 and storage circuit 161, and the result is provided to storage circuit 161. Storage circuit 161 is also coupled to receive input from storage circuit 152, is clocked by oversample clock 181, and is coupled to provide information to circuit 162. Circuit 162 performs a shift right function. Summation circuit 163 receives inputs from circuit 162 and storage circuit 164, and the result is provided to storage circuit 164. Storage circuit 164 is also coupled to receive input from storage circuit 151, is clocked by oversample clock 181, and is coupled to provide information to circuit 165. Circuit 165 performs a shift right function. Summation circuit 166 receives inputs from circuit 165 and storage circuit 167, and the result is provided to storage circuit 167. Storage circuit 167 is also coupled to receive input from storage circuit 150, is clocked by oversample clock 181, and is coupled to provide information to circuit 168. Circuit 168 performs a shift right function. Summation circuit 169 receives inputs from circuit 168 and storage circuit 170, and the result is provided to storage circuit 170. Storage circuit 170 is also coupled to receive input from the initial frequency deviation signal 43, is clocked by oversample clock 181, is coupled to provide the high port frequency deviation signals 54, and is coupled to storage circuit 171. Storage circuit 171 is clocked by low port clock 182 and provides the low port frequency deviation signals 56. Description of Operation Referring to FIG. 1, using a waveform generator 12 within an FM modulator 10 allows different and programmable pulse shaping filters to be used for various frequency modulation schemes. For example, waveform generator 12 may be used to predistort the overall dual port transfer function such that the combined predistortion and the dual port transfer function have a reduced ripple in gain and in phase over frequency. Note that FM waveform generator 12 can be used to do just interpolation, or can alternately be used to do filtering as well as interpolation. If waveform generator 12 is used to do just interpolation, then another integrated circuit, such as a digital signal processor (not shown), may be used to do the filtering and may provide input data 40 to waveform generator 12. The prior art methods often used a look-up table to perform interpolation. The use of waveform generator 12 allows a significant amount of flexibility which the prior art look-up table did not allow. Waveform generator 12 can be used to predistort the input signal to both the high port (high port frequency deviation signal 54) and the low port (low port frequency deviation signal 56). The output of waveform generator 12 may be scaled as a function of the reference frequency. This can be used to adjust for the use of crystals of different frequencies or for a change in the value M of divider 28. This scaling is accomplished by selecting different coefficients for waveform generator 12 at the pulse shaping coefficient input 46. Note that the proper selection of the pulse shaping coefficient values at input 46 in conjunction with the proper selecting of the oversampling select value at input 42 can be used by waveform generator 12 to interpolate values between the input data values provided at input 40. The oversampling select input 42 may be used to select how many points are interpolated between each pair of input data values provided at input 40. Another feature of the present invention is that the output of DAC 18 is filtered by loop filter 22. In prior art methods, the output of DAC 18 bypassed loop filter 22 and was provided directly to the input of VCO 24. In one embodiment of the present invention, the output of DAC 18 is provided to loop filter 22 by way of resistive attenuator 20, and thus the output of DAC 18 is now filtered. As a result, loop filter 22 now provides a dual function in that it filters the input signal to VCO 24 as well as filtering the output of DAC 18. In one embodiment of the present invention the high port frequency deviation 54 and the low port frequency deviation 56 are related to each other in that low port frequency deviation 56 is a decimation of the high port frequency deviation 54. The decimation relationship between the high port frequency deviation 54 and the low port frequency deviation 56 may be programmed by way of the decimation select input 44 to waveform generator 12. FIGS. 2 and 3 illustrate alternate ways in which DAC 18 may be coupled to loop filter 22. In addition, the specific circuits of resistive attenuator 20 and loop filter 22 may be implemented in a variety of ways. What is important is that loop filter 22 now provides at least some filtering of the output of DAC 18 If DAC 18 is coupled directly to the input of VCO 24 and by-passes loop filter 22, then more noise is generated at VCO output 41. In one embodiment, the present invention couples the output of DAC 18 to some point within loop filter 22 so that loop filter 22 serves a dual purpose of filtering the output of DAC 18 as well as filtering the signal provided by phase detector and charge pump 26. Alternate embodiments of the present invention may couple DAC 18 to loop filter 22 in a variety of ways. For example, The circuit illustrated in FIG. 3 allows resistor 61 (see FIG. 2) to be removed because resistor 84 within loop filter 22 serves a similar attenuation function. Although FIG. 2 and FIG. 3 have been shown as alternate embodiments for coupling DAC 18 to loop filter 22, there may be a variety of ways in which the coupling can take place. Note that capacitor 60 has been added to the circuit in FIG. 2 in order to couple the resistive attenuator 20 and loop filter 22. In a similar manner capacitor 80 has been added to the circuit in FIG. 3 to couple resistive attenuator 20 to loop filter 22. Again, note that alternate embodiments of the present invention may couple DAC 18 to loop filter 22 in many different ways. By coupling DAC 18 to VCO 24 by way of loop filter 22, the transfer function of FM modulator 10 is no longer constant over frequency. This now presents a problem that can be solved by waveform generator 12. Waveform generator 12 may be programmed by way of pulse shaping coefficients provided at input 46 to predistort the transfer function in such a way that the distortions caused by the direct coupling of DAC 18 and loop filter 22 are significantly reduced. This is another example of the flexibility provided by adding waveform generator 12 to FM modulator 10. Note that the waveform generator 12 can also be used to perform a filtering function in order to reduce the sensitivity of FM modulator 10 to variations in the gain of VCO 24. This filtering performed by waveform generator 12 could be performed by any type of linear phase filter, such as, for example, a Bessel filter. Note that this linear phase filtering is in addition to the predistortion and the pulse shaping filtering which are also performed by waveform generator 12. In one embodiment of the present invention, the linear phase filtering, the predistortion, and the pulse-shaping filtering can all be performed using one filter within wave form generator 12. Alternate embodiments of the present invention may instead implement multiple filters within waveform generator 12. In addition, alternate embodiments of the present invention may perform fewer, more, or different filtering and wave shaping functions within waveform generator 12. The following several paragraphs describe how the linear phase filtering, the predistortion, and the pulse-shaping filtering can all be performed using one filter within wave form generator 12. It is possible to express the VCO output frequency Fout versus the input frequency deviation Fin for the general case of Dual Port as: Gcl,dp(s) = Fout Fin = [Kdacan*Vhpf(s)* Kv] + [(Icp * Zlpf(s) *Kv) / (S*N)] 1+ [(lcp *Zlpf(s) *Kv) / (S * N)] where Kv is the VCO slope expressed as Megahertz/Volts x unit, N is the divider 32 programmed value, Icp is the charge pump 26 current value expressed in milliamperes, Kdacatt is the gain of the DAC 18 and the attenuator 20, Zlpf(s) is the loop filter low port impedance transfer function between the output of the charge pump 26 and the output of the loop filter 22 expressed in Volts/milliampere, Vhpf(s) is the loop filter high port transfer function between the output of the attenuator 20 and the output of the loop filter 22 expressed in Volts/Volts, and s is the Laplace transform variable. In order to have equation 1 be constant over frequency, it is required that Kdacatt*Vhpf(s)*Kv = 1 over the useful signal spectrum (equation 2). Note that the ideal dual port case, where the high port frequency deviation is added directly at the VCO input, and thus Vhpf(s)=1, would require Kdacatt*Kv =1, which does not depend on frequency. Equation 2 cannot be satisfied within the useful signal spectrum when Vhpf(s) is a function of the frequency. A possible solution would be to have a predistortion within the high port path to modify the value of Vhpf(s), however this would require adding another programmable waveform generator to the high port path in addition to the waveform generator already used in the low port path. The present invention allows a single waveform generator to be used to drive both the high port and the low port by implementing the pulse shaping filter transfer function F(s) combined with a predistortion transfer function Hpd(s), that is F(s)*Hpd(s) where Hpd(s) is an approximation of ≅ 1+ [(Icp *Zlpf(s) *Kv / (S* N)] [Kdacan*Vhpf(s)*Kv] + [(Icp * Zlpf(s) * Kv) / (S*N)] In one embodiment, the predistortion transfer function can reduce overall gain ripple and group delay ripple, without totally eliminating these ripples since the predistortion is done on both ports to avoid using two waveform generators. One of the key advantages to using a waveform generator 12 with FM modulator 10 is that waveform generator 12 can be programmed in variety of ways to adjust the behaviour of modulator 10 based on various changes that are made within the circuit of modulator 10. Thus a designer of multi-mode loop FM modulator 10 now has a significant amount of flexibility in adjusting the filtering and interpolation that can be performed within the FM modulator 10. Note that alternate may use both of multiplexers 14 and 38, may use just one of them, or may alternately use neither of them. Also, note that by having a zero input to multiplexer 14 and multiplexer 38, a user of FM modulator 10 can select a system in which VCO 24 is driven by the high port alone, the low port alone, or both the high port and low port together. In an alternate embodiment, DAC 18 may by-pass loop filter 22 and may be coupled to the input of VCO 24 by way of an operational amplifier (not shown). However, one drawback to this approach is that an operational amplifier may add significant cost and noise to FM modulator 10. In addition, the output of DAC 18 is no longer filtered by loop filter 22. FIG. 4 illustrates one embodiment of a portion of waveform generator 12 of FIG. 1. In the embodiment illustrates in FIG. 4, the select span length signal 45 selects whether storage circuits 102 and 103 are bypassed or not. Thus, select span length 45 determines whether the span length is selected to be 4 (using storage circuits 104-107,) or whether the span length is selected to be 6 (using storage circuits 102-107). Alternate embodiments may use more multiplexers (e.g. 100,101), or multiplexers placed in different locations than that illustrates in FIG. 4. For example, an additional multiplexer, similar to multiplexer 101, may be coupled between storage circuit 105 and 106 in order to allow the select span length 45 to be selected to be 2,4, or 6. The span length determines the number of previous data input values that are used by the filter of waveform generator 12 at a given time. Various pre-detemined protocols require different span lengths. Thus, the waveform generator 12 illustrated in FIG. 4 may be used for a variety of these protocols since the span length is programmable. An additional feature of waveform generator 12 is that multipliers 108, 118, 128, and 138 are operating at the input data rate multiplied by the selected span length as selected at input 45. The input data rate is the frequency at which input data is provided at input 40. It was common in the prior art to use a separate multiplier for each of the storage circuits (e.g. 102-107) in the span length. Thus, the present invention allows one multiplier to be used repeatedly at a higher clock frequency, while the prior art required multiple multipliers which operated at a lower clock frequency. The present invention allows the oversampling rate to be programmable by changing the oversampling clock 181 and a shift number input to shifters 162, 165, and 168. Note that integrator circuit 200 performs an integration function where the last stage receives an initial frequency deviation value 43 which allows the FM modulator 10 to be set to a predetermined initial value. Integrator circuit 200 uses the oversample clock 181 to integrate the derivatives of the input data 40. Integrator 200 generates and provides the high port frequency deviation signal 54 and the low port frequency deviation signal 56. The shift by N circuits 162,165 and 168 can be used to adjust for the difference between the oversampling clock and the input data rate. Note that by using a simple shift circuit, the assumption is made that the oversampling clock and the input data clock are related by a power of 2. The amount by which shift circuits 162, 165 and 168 are shifted can be a programmable value N. Note that the low port clock 182 provided at the input to storage circuit 171 can be used to perform the decimation function. Thus in one embodiment, the low port frequency deviation signal is a decimation of the high port frequency deviation signal 54. Alternate embodiments of the present invention may do decimation in an alternate way, or may not use decimation at all. In other words only one out of X of the values of the high port frequency deviation signal 54 are actually provided and passed on through as part of the low port frequency deviation signal 56, where X is a positive integer. Although one embodiment of waveform generator 12 has been illustrated in FIG. 4, there are a wide variety of embodiments of waveform generators that may be used for the present invention. For example, although waveform generator 12 has been illustrated as being implemented primarily in hardware form, it is important to note that alternate embodiments of the present invention may more software and less hardware in implementing waveform generator 12. Note also that the storage circuits used throughout FIGS. 1-5 may be implemented in a variety of ways, including one or more registers.

Claims: A frequency modulator (10) for modulating a carrier signal according to a modulation data signal (40) to provide a modulated output signal (41), the frequency modulator comprising: a waveform generator (12) coupled to receive the modulation data signal for predistorting the modulation data signal in a selected manner to provide at least one predistorted modulation data signal (54, 56); and a circuit (11) coupled to receive the at least one predistorted modulation data signal for generating and providing the modulated output signal at an output characterised in that said at least one predistorted modulation data signal comprises a high port frequency deviation signal and a low port frequency deviation signal, and the decimation ratio between the high port frequency deviation signal (54) and the low port frequency deviation signal (56) is programmable. A frequency modulator according to any preceding claim wherein the waveform generator performs interpolation. A frequency modulator according to any preceding claim wherein the waveform generator performs filtering. A frequency modulator according to any preceding claim wherein the span length (45) of the waveform generator is programmable. A frequency modulator according to any preceding claim wherein the waveform generator comprises at least one shift circuit (162, 165,168) to adjust for a difference between a frequency of the modulation data signal and a frequency of an oversampling clock (181). A frequency modulator according to any preceding claim wherein the waveform generator has an oversampling rate (42) which is programmable. A frequency modulator according to any preceding claim wherein the waveform generator comprises a multiplier circuit (108, 118, 128, 138) operating at the frequency of the modulation data signal. A frequency modulator according to any preceding claim wherein the waveform generator comprises at least one adder circuit (160, 163, 166, 169) operating at the frequency of the oversampling clock. A frequency modulator according to any preceding claim wherein the waveform generator is operable to scale the at least one predistorted modulation data signal as a function of a reference frequency (30). A frequency modulator according to any preceding claim wherein the circuit for generating and providing the modulated output signal comprises: a loop filter (22); and a VCO (24), coupled to receive an input from the loop filter, for generating the modulated output signal at an output of the VCO, wherein the a high port frequency deviation signal is not directly provided to the VCO as an input, but wherein the high port frequency deviation signal affects the VCO by way of the loop filter. A transmitter for a digital radio communication device having a transmit path comprising: a frequency modulator according to claim 10 for modulating a carrier signal according to a modulation data signal to provide a modulated output signal; a power amplifier for amplifying the modulated output signal: and an antenna coupled to the power amplifier. A transceiver for a digital radio communication device having a transmit path and a receive path, the transmit path comprising: a frequency modulator according to claim 10 for modulating a carrier signal according to a modulation data signal to provide a modulated output signal, a power amplifier for amplifying the modulated output signal: and an antenna for coupling to the power amplifier.

Inventors: KHLAT NADIM, KHLAT, NADIM
Applicants: FREESCALE SEMICONDUCTOR INC, FREESCALE SEMICONDUCTOR, INC.
Application year: 2000
Main classification: H03C3
IPC codes: H03L7, H04L27, H03C3