DIELECTRIC FORMATION TO SEAL POROSITY OF ETCHED LOW DIELECTRIC CONSTANT MATERIALS

Abstract: A method is provided, the method including forming a first dielectric layer (130) above a structure layer (110), and forming a first opening (220) in the first dielectric layer (130), the first opening (220) having sidewalls. The method also includes forming a second dielectric layer (430) on the sidewalls of the first opening (220).

Description: DIELECTRIC FORMATION TO SEAL POROSITY OF ETCHED LOW DIELETRIC CONSTANT MATERIALS TECHNICAL FIELD This invention relates generally to semiconductor fabrication technology, and, more particularly, to techniques for filling contact openings and vias with copper and creating copper interconnections and lines. BACKGROUND ART There is a constant drive within the semiconductor industry to increase the operating speed of integrated circuit devices, e.g., microprocessors, memory devices, and the like. This drive is fueled by consumer demands for computers and electronic devices that operate at increasingly greater speeds. This demand for increased speed has resulted in a continual reduction in the size of semiconductor devices, e.g., transistors. That is, many components of a typical field effect transistor (FET), e.g., channel length, junction depths, gate dielectric thickness, and the like, are reduced. For example, all other things being equal, the smaller the channel length of the FET, the faster the transistor will operate. Thus, there is a constant drive to reduce the size, or scale, of the components of a typical transistor to increase the overall speed of the transistor, as well as integrated circuit devices incorporating such transistors. Additionally, reducing the size, or scale, of the components of a typical transistor also increases the density, and number, of the transistors that can be produced on a given amount of wafer real estate, lowering the overall cost per transistor as well as the cost of integrated circuit devices incorporating such transistors. However, reducing the size, or scale, of the components of a typical transistor also requires reducing the size and cross-sectional dimensions of electrical interconnects to contacts to active areas, such as N + (P + ) source/drain regions and a doped-polycrystalline silicon (doped-polysilicon or doped-poly) gate conductor, and the like. As the size and cross-sectional dimensions of electrical interconnects get smaller, resistance increases and electromigration increases. Increased resistance and electromigration are undesirable for a number of reasons. For example, increased resistance may reduce device drive current, and source/drain current through the device, and may also adversely affect the overall speed and operation of the transistor. Additionally, electromigration effects in aluminum (Al) interconnects, where electrical currents actually carry Al atoms along with the current, causing them to electromigrate, may lead to degradation of the Al interconnects, further increased resistance, and even disconnection and/or delamination of the Al interconnects. The ideal interconnect conductor for semiconductor circuitry will be inexpensive, easily patterned, have low resistivity, and high resistance to corrosion, electromigration, and stress migration. Aluminum (Al) is most often used for interconnects in contemporary semiconductor fabrication processes primarily because Al is inexpensive and easier to etch than, for example, copper (Cu). However, because Al has poor electromigration characteristics and high susceptibility to stress migration, it is typical to alloy Al with other metals. As discussed above, as semiconductor device geometries shrink and clock speeds increase, it becomes increasingly desirable to reduce the resistance of the circuit metallization. The one criterion that is most seriously compromised by the use of Al for interconnects is that of conductivity. This is because the three metals with lower resistivities (Al has a resistivity of 2.824xl0 "6 ohms-cm at 20°C), namely, silver (Ag) with a resistivity of 1.59xl0 ~6 ohms-cm (at 20°C), copper (Cu) with a resistivity of 1.73x10 "6 ohms-cm (at 20°C), and gold (Au) with a resistivity of 2.44χl0 "6 ohms-cm (at 20°C), fall short in other significant criteria. Silver, for example, is relatively expensive and corrodes easily, and gold is very costly and difficult to etch. Copper, with a resistivity nearly on par with silver, immunity from electromigration, high ductility (which provides high immunity to mechanical stresses generated by differential expansion rates of dissimilar materials in a semiconductor chip) and high melting point (1083°C. for Cu vs. 660°C. for Al), fills most criteria admirably. However, Cu is difficult to etch in a semiconductor environment. As a result of the difficulty in etching Cu, an alternative approach to forming vias and metal lines must be used. The damascene approach, consisting of etching openings such as trenches in the dielectric for lines and vias and creating in-laid metal patterns, is the leading contender for fabrication of sub-0.25 micron (sub-0.25 μ) design rule Cu-metallized circuits. However, the lower resistance and higher conductivity of the Cu interconnects, coupled with higher device density and, hence, decreased distance between the Cu interconnects, may lead to increased capacitance between the Cu interconnects. Increased capacitance between the Cu interconnects, in turn, results in increased RC time delays and longer transient decay times in the semiconductor device circuitry, causing decreased overall operating speeds of the semiconductor devices. One conventional solution to the problem of increased capacitance between the Cu interconnects is to use "low dielectric constant" or "low K" dielectric materials, where K is less than or equal to about 4, for the interlayer dielectric layers (ILD's) in which the Cu interconnects are formed using the damascene techniques. However, low K dielectric materials are difficult materials to use in conjunction with the damascene techniques. For example, low K dielectric materials are susceptible to being damaged and weakened during the etching and subsequent processing steps used in the damascene techniques. In particular, the sidewalls of openings such as trenches and/or vias formed in low K dielectric materials are especially vulnerable. In addition, low K dielectric materials are porous and are a weak and non-uniform substrate for the deposition of a barrier metal layer. In particular, after etching and ashing (to remove photoresist masks used for patterning), porous low K dielectric materials will have open pores (caused in part by air retained in the porous low K dielectric materials), which are undesirable in a substrate on which a barrier metal layer is to be deposited because of outgassing and surface roughness. The present invention is directed to overcoming, or at least reducing the effects of, one or more of the problems set forth above. DISCLOSURE OF INVENTION In one aspect of the present invention, a method is provided, the method including forming a first dielectric layer above a first structure layer, and forming a first opening in the first dielectric layer, the first opening having sidewalls. The method also includes forming a second dielectric layer on the sidewalls of the first opening. BRIEF DESCRIPTION OF THE DRA INGS The invention may be understood by reference to the following description taken in conjunction with the accompanying drawings, in which the leftmost significant digit(s) in the reference numerals denote(s) the first figure in which the respective reference numerals appear, and in which: Figures 1-8 schematically illustrate a single-damascene copper interconnect process flow according to various embodiments of the present invention; Figure 9 schematically illustrates multiple layers of copper interconnects according to various embodiments of the present invention; Figure 10 schematically illustrates copper interconnects according to various embodiments of the present invention connecting source/drain regions of an MOS transistor; Figures 1 1-18 schematically illustrate a dual-damascene copper interconnect process flow according to various embodiments of the present invention; Figure 19 schematically illustrates multiple layers of copper interconnects according to various embodiments of the present invention; and Figure 20 schematically illustrates copper interconnects according to various embodiments of the present invention connecting source/drain regions of an MOS transistor. While the invention is susceptible to various modifications and alternative forms, specific embodiments thereof have been shown by way of example in the drawings and are herein described in detail. It should be understood, however, that the description herein of specific embodiments is not intended to limit the invention to the particular forms disclosed, but, on the contrary, the intention is to cover all modifications, equivalents, and alternatives falling within the spirit and scope of the invention as defined by the appended claims. MODE(S) FOR CARRYING OUT THE INVENTION Illustrative embodiments of the invention are described below. In the interest of clarity, not all features of an actual implementation are described in this specification. It will of course be appreciated that in the development of any such actual embodiment, numerous implementation-specific decisions must be made to achieve the developers' specific goals, such as compliance with system-related and business-related constraints, which will vary from one implementation to another. Moreover, it will be appreciated that such a development effort might be complex and time-consuming, but would nevertheless be a routine undertaking for those of ordinary skill in the art having the benefit of this disclosure. Illustrative embodiments of a method for semiconductor device fabrication according to the present invention are shown in Figures 1-20. Although the various regions and structures of a semiconductor device are depicted in the drawings as having very precise, shaφ configurations and profiles, those skilled in the art recognize that, in reality, these regions and structures are not as precise as indicated in the drawings. Nevertheless, the attached drawings are included to provide illustrative examples of the present invention. In general, the present invention is directed towards the manufacture of a semiconductor device. As will be readily apparent to those skilled in the art upon a complete reading of the present application, the present method is applicable to a variety of technologies, for example, NMOS, PMOS, CMOS, and the like, and is readily applicable to a variety of devices, including, but not limited to, logic devices, memory devices, and the like. As shown in Figure 1, a first dielectric layer 120 and a first conductive structure 140 (such as a copper intermetal via connection) may be formed above a structure 100 such as a semiconducting substrate. However, the present invention is not limited to the formation of a Cu-based interconnect above the surface of a semiconducting substrate such as a silicon wafer, for example. Rather, as will be apparent to one skilled in the art upon a complete reading of the present disclosure, a Cu-based interconnect formed in accordance with the present invention may be formed above previously formed semiconductor devices and/or process layer, e.g., transistors, or other similar structure. In effect, the present invention may be used to form process layers on top of previously formed process layers. The structure 100 may be an underlayer of semiconducting material, such as a silicon substrate or wafer, or, alternatively, may be an underlayer of semiconductor devices (see Figure 10, for example), such as a layer of metal oxide semiconductor field effect transistors (MOSFETs), and the like, and/or a metal interconnection layer or layers (see Figure 9, for example) and/or an interlayer dielectric (ILD) layer or layers, and the like. In a single-damascene copper process flow, according to various embodiments of the present invention, as shown in Figures 1 -8, the first dielectric layer 120 is formed above the structure 100, adjacent the first conductive structure 140. A second dielectric layer 130 is formed above the first dielectric layer 120 and above the first conductive structure 140. A patterned photomask 150 is formed above the second dielectric layer 130. The first dielectric layer 120 has the first conductive structure 140 disposed therein. The first dielectric layer 120 has an etch stop layer (ESL) 1 10 (typically silicon nitride, Si 3 N 4 , or SiN, for short) formed and patterned thereon, between the first dielectric layer 120 and the second dielectric layer 130 and adjacent the first conductive structure 140. If necessary, the second dielectric layer 130 may have been planarized using chemical-mechanical planarization (CMP). The second dielectric layer 130 has an etch stop layer 160 (typically also SiN) formed and patterned thereon, between the second dielectric layer 130 and the patterned photomask 150. The first and second dielectric layers 120 and 130 may be formed from a variety of "low dielectric constant" or "low K" (K is less than or equal to about 4) dielectric materials. The low K first and second dielectric layers 120 and 130 may be formed by a variety of known techniques for forming such layers, e.g., chemical vapor deposition (CVD), low-pressure CVD (LPCVD), plasma-enhanced CVD (PECVD), sputtering, physical vapor deposition (PVD), spin-on glass, and the like, and each may have a thickness ranging from approximately 3000 A-8000 A, for example. The low K first and second dielectric layers 120 and 130 may be formed from a variety of low K dielectric materials, where K is less than or equal to about 4. Examples include Applied Material's Black Diamond ® , Novellus' Coral ® , Allied Signal's Nanoglass ® , JSR's LKD5104, and the like. In one illustrative embodiment, the low K first and second dielectric layers 120 and 130 are each comprised of Applied Material's Black Diamond ® , each having a thickness of approximately 5000 A, each being formed by being blanket-deposited by an LPCVD process for higher throughput. As shown in Figure 2, a metallization pattern is then formed by using the patterned photomask 150, the etch stop layer's 160 and 1 10 (Figures 1 -2), and photolithography. For example, openings (such as an opening or trench 220 formed above at least a portion of the first conductive structure 140) for conductive metal lines, contact holes, via holes, and the like, are etched into the second dielectric layer 130 (Figure 2). The opening 220 has sidewalls 230. The opening 220 may be formed by using a variety of known anisotropic etching techniques, such as a reactive ion etching (RIE) process using hydrogen bromide (HBr) and argon (Ar) as the etchant gases, for example. Alternatively, an RIE process with CHF 3 and Ar as the etchant gases may be used, for example. Dry etching may also be used in various illustrative embodiments. The etching may stop at the etch stop layer 1 10 and at the first conductive structure 140. As shown in Figure 3, the patterned photomask 150 (Figures 1-2) is stripped off. by ashing, for example. Alternatively, the patterned photomask 150 may be stripped using a 1 : 1 solution of sulfuric acid (H 2 S0 4 ) to hydrogen peroxide (H 2 0 2 ), for example. The etching of the opening 220 and the removal of the patterned photomask 150 (Figures 1-2), by ashing or otherwise, may cause the porous low K dielectric material of the second dielectric layer 130 to have open pores 300 in the sidewalls 230 of the opening 220. The open pores 300 in the sidewalls 230 of the opening 220 may be caused in part by air retained in the porous low K dielectric material of the second dielectric layer 130. The open pores 300 in the sidewalls 230 of the opening 220, if left uncovered, would be an undesirable substrate for the deposition of a barrier metal layer because of outgassing and surface roughness. As shown in Figure 4, the open pores 300 in the sidewalls 230 of the opening 220 may be covered by a dielectric layer 430 adjacent the opening 220. The dielectric layer 430 covers and/or seals the open pores 300 in the sidewalls 230 of the opening 220, producing smoother and more stable surfaces 440 of the dielectric layer 430 adjacent the opening 220. The smoother and more stable surfaces 440 of the dielectric layer 430 adjacent the opening 220 provide better adhesion for one or more subsequently formed barrier metal layers (such as a barrier metal layer 525A, described more fully below with reference to Figure 5) In various illustrative embodiments, the dielectric layer 430 may be formed by a variety of known techniques for forming such a layer, e g , chemical vapor deposition (CVD), low-pressure CVD (LPCVD), plasma-enhanced CVD (PECVD), sputtering, physical vapor deposition (PVD), thermal growing, spin-on glass, and the like The dielectric layer 430 may have a thickness in a range of about 50-500 A In one illustrative embodiment, the dielectric layer 430 is comprised of silicon dioxide (Sι0 2 ) having a thickness of approximately 100 A, formed by being blanket-deposited by an LPCVD process for higher throughput The dielectric layer 430 may be formed from a variety of dielectric materials and may, for example, be an oxide (e g , Ge oxide), an oxynitride (e g , GaP oxynitπde), silicon dioxide (Sι0 2 ), a nitrogen-bearing oxide (e g , nitrogen-bearing Sι0 2 ), a nitrogen-doped oxide (e g , N 2 -ιmplanted Sι0 2 ), silicon oxynitride (Sι x O y N z ), and the like The dielectric layer 430 may also be formed of any suitable "high dielectric constant" or "high K" material, where K is greater than or equal to about 8, such as titanium oxide (Tι x O y , e g , Tι0 2 ), tantalum oxide (Ta x O y , e g , Ta 2 0 5 ), barium strontium titanate (BST, BaTι0 3 /SrTι0 3 ), and the like In various alternative embodiments, the dielectric layer 430 may be formed from a variety of low K dielectric materials, where K is less than or equal to about 4 Examples include Applied Material's Black Diamond ® , Novellus' Coral ® , Allied Signal's Nanoglass ® , JSR's LKD5104, and the like In one illustrative embodiment, the dielectric layer 430 is comprised of Applied Material's Black Diamond ® , having a thickness of approximately 300 A, formed by being blanket-deposited by an LPCVD process for higher throughput Alternatively, after the etching of the opening 220 and the removal of the patterned photomask 150 (Figures 1-2), by ashing or otherwise, the structure 100 may be inserted into a dielectric deposition chamber (not shown) and a low K dielectric material may be blanket-deposited by an LPCVD process and a sotropically etched, forming spacers on the sidewalls 230 of the opening 220, as shown in Figure 4, reducing the roughness of the sidewalls 230 of the opening 220, and improving the step coverage of one or more subsequently formed barrier metal layers (such as the barrier metal layer 525A, described more fully below with reference to Figure 5) In various other alternative embodiments, the dielectric layer 430 may be formed from a variety of low K dielectric materials by being deposit-etch cycled layer by layer for about 20-30 layers using a high-density plasma (HDP) device such as Applied Material's Producer ® device As shown m Figure 5, the etch stop layer 160 is then stripped and the thin barrier metal layer 525 A and a copper seed layer 525B (or a seed layer of another conductive material) are applied to the entire surface using vapor-phase deposition The barrier metal layer 525A and the Cu seed layer 525B blanket-deposit an entire upper surface 530 of the second dielectric layer 130 as well as the smoother and more stable surfaces 440 and a bottom surface 550 of the opening 220, forming a conductive surface 535, as shown in Figure 5 The barrier metal layer 525A may be formed of at least one layer of a barrier metal material, such as tantalum or tantalum nitride, and the like For example, the barrier metal layer 525A may also be formed of titanium nitride, titanium-tungsten, nitπded titanium-tungsten, magnesium, or another suitable barrier material The copper seed layer 525B may be formed on top of the one or more barrier metal layers 525A by physical vapor deposition (PVD) or chemical vapor deposition (CVD), for example The bulk of the copper trench-fill (or trench-fill of another conductive material) is frequently done using an electroplating technique, where the conductive surface 535 is mechanically clamped to an electrode (not shown) to establish an electrical contact, and the structure 100 is then immersed in an electrolyte solution containing Cu ions (or ions of another conductive material) An electrical current is then passed through the wafer-electrolyte system to cause reduction and deposition of Cu (or ions of another conductive material) on the conductive surface 535 In addition, an alternating-current bias of the wafer-electrolyte system has been considered as a method of self-planaπzing the deposited Cu film (or film of another conductive material), similar to the deposit-etch cycling used in high-density plasma (HDP) tetraethyl orthosilicate (TEOS) dielectric depositions As shown in Figure 6, this process typically produces a conformal coating of Cu 640 (or another conductive material) of substantially constant thickness across the entire conductive surface 535 As shown in Figure 7, once a sufficiently thick layer of Cu 640 has been deposited, the layer of Cu 640 is planaπzed using chemical mechanical polishing (CMP) techniques The planaπzation using CMP clears all Cu and barrier metal from the entire upper surface 530 of the second dielectric layer 130, leaving the Cu 640 only in a metal structure such as a Cu-filled trench, forming a Cu-mterconnect 745, adjacent remaining portions 725A and 725B of the one or more barrier metal layers 525A and copper seed layer 525B (Figures 5 and 6), respectively, as shown in Figure 7 As shown in Figure 7, the Cu-interconnect 745 may be formed by annealing the Cu 640, adjacent the remaining portions 725 A and 725B of the one or more barrier metal layers 525 A and copper seed layer 525B (Figures 5 and 6), to the first conductive structure 140 The anneal process may be performed in a traditional tube furnace, at a temperature ranging from approximately 100-500°C, for a time period ranging from approximately 1-180 minutes, in a nitrogen-containing ambient that may include at least one of ammonia (NH 3 ), molecular nitrogen (N 2 ), molecular hydrogen (H 2 ), argon (Ar), and the like Alternatively, the anneal process may be a rapid thermal anneal (RTA) process performed at a temperature ranging from approximately 100-500°C for a time ranging from approximately 10-180 seconds in a nitrogen-containing ambient that may include at least one of molecular nitrogen (N 2 ), molecular hydrogen (H 2 ), argon (Ar), and the like As shown in Figure 8, the low K second dielectric layer 130 may be planaπzed, as needed, using chemical mechanical polishing (CMP) techniques Planaπzation would leave the planaπzed low K second dielectric layer 130 adjacent the Cu-interconnect 745 and above the etch stop layer 110, forming a Cu-interconnect layer 800 The Cu-interconnect layer 800 may include the Cu-mterconnect 745 adjacent the treated regions 430 of the second dielectric layer 130 The Cu-interconnect layer 800 may also include the etch stop layer 1 10 As shown in Figure 8, the Cu-mterconnect layer 800 may also include an etch stop layer 820 (also known as a "hard mask" and typically formed of silicon nitride, Sι 3 N 4 , or SiN, for short) formed and patterned above the second dielectric layer 130 and above at least a portion of the Cu-interconnect 745 As shown in Figure 9, the Cu-interconnect layer 800 may be an underlying structure layer (similar to the structure 100) to a Cu-mterconnect layer 900 The Cu-interconnect layer 900 may include a Cu-filled trench 940 and an mtermetal via connection 910 adjacent treated regions 945 of planaπzed low K dielectric layer 935 The intermetal via connection 910 may be a Cu structure similar to the first Cu structure 140, and the mtermetal via connection 910 may be annealed to the Cu-filled trench 940 in a similar fashion to the anneal described above in relation to the formation of the Cu-interconnect 745 (Figure 7) The Cu-interconnect layer 900 may also include the etch stop layer 820 and/or etch stop layer 915 and/or etch stop layer 920 (also known as "hard masks" and typically formed of silicon nitride, Sι 3 N 4 , or SiN, for short) formed and patterned above the planaπzed low K dielectric layers 925 and/or 935, respectively The etch stop layer 920 may also be formed above at least a portion of the Cu-filled trench 940 As shown in Figure 10, an MOS transistor 1010 may be an underlying structure layer (similar to the structure 100) to a Cu-interconnect layer 1000. The Cu-interconnect layer 1000 may include Cu-filled trenches 1020 and copper intermetal via connections 1030 adjacent treated regions 1050 of a planarized low K dielectric layer 1040. The copper intermetal via connections 1030 may be Cu structures similar to the first Cu structure 140, and the copper intermetal via connections 1030 may be annealed to the second Cu structures 1020 in a similar fashion to the anneal described above in relation to the formation of the Cu-interconnect 745 (Figure 7). As shown in Figure 1 1, a first dielectric layer 1 105 and a first conductive structure 1 125 (such as a copper intermetal via connection) may be formed above a structure 1 100 such as a semiconducting substrate. However, the present invention is not limited to the formation of a Cu-based interconnect above the surface of a semiconducting substrate such as a silicon wafer, for example. Rather, as will be apparent to one skilled in the art upon a complete reading of the present disclosure, a Cu-based interconnect formed in accordance with the present invention may be formed above previously formed semiconductor devices and/or process layer, e.g., transistors, or other similar structure. In effect, the present invention may be used to form process layers on top of previously formed process layers. The structure 1 100 may be an underlayer of semiconducting material, such as a silicon substrate or wafer, or, alternatively, may be an underlayer of semiconductor devices (see Figure 20, for example), such as a layer of metal oxide semiconductor field effect transistors (MOSFETs), and the like, and/or a metal interconnection layer or layers (see Figure 19, for example) and/or an interlayer dielectric (ILD) layer or layers, and the like. In a dual-damascene copper process flow, according to various embodiments of the present invention, as shown in Figures 1 1-18, a second dielectric layer 1 120 is formed above the first dielectric layer 1 105 and above the first conductive structure 1 125. A third dielectric layer 1 130 is formed above the second dielectric layer 1 120. A patterned photomask 1 150 is formed above the third dielectric layer 1 130. The first dielectric layer 1 105 has an etch stop layer (ESL) 1 1 10 (also known as a "hard mask" and typically formed of silicon nitride, Si 3 N 4 , or SiN, for short) formed and patterned thereon, between the first dielectric layer 1105 and the second dielectric layer 1 120. Similarly, the second dielectric layer 1 120 has an etch stop layer 1 1 15 (also typically formed of SiN) formed and patterned thereon, between the second dielectric layer 1 120 and the third dielectric layer 1130. As will be described in more detail below in conjunction with Figure 12, the first etch stop layer 1 1 10 and a second etch stop layer 1 1 15 define a lower (via) portion of the copper interconnect formed in the dual-damascene copper process flow. If necessary, the third dielectric layer 1 130 may be planarized using chemical-mechanical planarization (CMP). The third dielectric layer 1 130 has an etch stop layer 1 160 (typically also SiN) formed and patterned thereon, between the third dielectric layer 1 130 and the patterned photomask 1 150. The first, second and third dielectric layers 1 105, 1 120 and 1 130 may be formed from a variety of "low dielectric constant" or "low K" (K is less than or equal to about 4) dielectric materials. The low K first, second and third dielectric layers 1105, 1120 and 1130 may be formed by a variety of known techniques for forming such layers, e.g., chemical vapor deposition (CVD), low-pressure CVD (LPCVD), plasma-enhanced CVD (PECVD), sputtering, physical vapor deposition (PVD), spin-on glass, and the like, and may each have a thickness ranging from approximately 3000 A-8000 A, for example. The low K first, second and third dielectric layers 1 105, 1 120 and 1 130 may be formed from a variety of low K dielectric materials, where K is less than or equal to about 4. Examples include Applied Material's Black Diamond ® , Novellus' Coral ® , Allied Signal's Nanoglass ® , JSR's LKD5104, and the like. In one illustrative embodiment, the low K first, second and third dielectric layers 1 105, 1 120 and 1 130 are each comprised of Applied Material's Black Diamond ® , each having a thickness of approximately 5000 A each being formed by being blanket-deposited by an LPCVD process for higher throughput As shown m Figure 12, a metallization pattern is then formed by using the patterned photomask 1 150, the etch stop layer's 1160, 11 15 and 1 1 10 (Figures 1 1-12), and photolithography For example, first and second openings, such as via 1220 and trench 1230, for conductive metal lines, contact holes, via holes, and the like, are etched into the second and third dielectric layers 1120 and 1130, respectively (Figure 12) The first and second openings 1220 and 1230 have sidewalls 1225 and 1235, respectively The first and second openings 1220 and 1230 may be formed by using a variety of known amsotropic etching techniques, such as a reactive ion etching (RIE) process using hydrogen bromide (HBr) and argon (Ar) as the etchant gases, for example Alternatively, an RIE process with CHF 3 and Ar as the etchant gases may be used, for example Dry etching may also be used in various illustrative embodiments The etching may stop at the etch stop layer 1 1 10 and at the first conductive structure 1 125 As shown in Figure 13, the patterned photomask 1 150 is stripped off, by ashing, for example Alternatively, the patterned photomask 1 150 may be stripped using a 1 1 solution of sulfuπc acid (H?S0 4 ) to hydrogen peroxide (H 2 0 2 ), for example The etching of the openings 1220 and 1230, and the removal of the patterned photomask 1 150 (Figures 1 1-12) by ashing or otherwise, may cause the porous low K dielectric material of the first and second dielectric layers 1 120 and 1 130 to have open pores 1300 in the respective sidewalls 1225 and 1235 of the openings 1220 and 1230, respectively The open pores 1300 may be caused in part by air retained in the porous low K dielectric material of the first and second dielectric layers 1 120 and 1 130 The open pores 1300, if left uncovered, would be an undesirable substrate for the deposition of a barrier metal layer because of outgassing and surface roughness As shown in Figure 14, the open pores 1300 may be covered by dielectric layers 1420 and 1430 adjacent the openings 1220 and 1230, respectively The dielectric layers 1420 and 1430 cover and/or seal the open pores 1300, producing smoother and more stable respective surfaces 1425 and 1435 of the dielectric layers 1420 and 1430 adjacent the openings 1220 and 1230, respectively The smoother and more stable respective surfaces 1425 and 1435 of the dielectric layers 1420 and 1430 adjacent the openings 1220 and 1230, respectively, provide better adhesion for one or more subsequently formed barrier metal layers (such as a barrier metal layer 1525 A, described more fully below with reference to Figure 15) In various illustrative embodiments, the dielectric layers 1420 and 1430 may be formed by a variety of known techniques for forming such layers, e g , chemical vapor deposition (CVD), low-pressure CVD (LPCVD), plasma-enhanced CVD (PECVD), sputtering, physical vapor deposition (PVD), thermal growing, spin-on glass, and the like The dielectric layers 1420 and 1430 may each have a thickness in a range of about 50-500 A In one illustrative embodiment, the dielectric layers 1420 and 1430 are each comprised of silicon dioxide (Sι0 2 ), each having a thickness of approximately 100 A, formed by being blanket-deposited by an LPCVD process for higher throughput The dielectric layers 1420 and 1430 may be formed from a variety of dielectric materials and may, for example, be an oxide (e g , Ge oxide), an oxynitride (e g , GaP oxynitride), silicon dioxide (Sι0 2 ), a nitrogen-bearing oxide (e g , nitrogen-bearing Sι0 2 ), a nitrogen-doped oxide (e g , Sι0 2 ), silicon oxynitride (Sι x O y N z ), and the like The dielectric layers 1420 and 1430 may also be formed of any suitable "high dielectric constant" or "high K" material, where K is greater than or equal to about 8, such as titanium oxide (Tι x O y , e g , Tι0 2 ), tantalum oxide (Ta x O y , e g , Ta 2 0 5 ), barium strontium titanate (BST, and the like In various alternative embodiments, the dielectric layers 1420 and 1430 may be formed from a variety of low K dielectric materials, where K is less than or equal to about 4 Examples include Applied Material's Black Diamond ® , Novellus' Coral ® , Allied Signal's Nanoglass ® , JSR's LKD5104, and the like In one illustrative embodiment, the dielectric layers 1420 and 1430 are each comprised of Applied Material's Black Diamond ® , each having a thickness of approximately 300 A, each being formed by being blanket-deposited by an LPCVD process for higher throughput For example, after the etching of the openings 1220 and 1230, and the removal of the patterned photomask 1 150 (Figures 1 1-12), by ashing or otherwise, the structure 1 100 may be inserted into a dielectric deposition chamber (not shown) and low K dielectric material may be blanket-deposited by an LPCVD process onto the sidewalls 1225 and 1235 of the openings 1220 and 1230, respectively The low K dielectric material may then be etched anisotropically, using RIE, for example, to form spacer-like dielectric layers 1420 and 1430, as shown in Figure 14, reducing the roughness of the sidewalls 230 of the opening 220, and improving the step coverage of one or more subsequently formed barrier metal layers (such as the barrier metal layer 1525 A, described more fully below with reference to Figure 15) In various other alternative embodiments, the dielectric layers 1420 and 1430 may be formed from a variety of low K dielectric materials by being deposit-etch cycled layer by layer for about 20-30 layers using a high-density plasma (HDP) device such as Applied Material's Producer ® device As shown in Figure 15, the etch stop layer 1 160 is then stripped and the thin barrier metal layer 1525 A and a copper seed layer 1525B (or a seed layer of another conductive material) are applied to the entire surface using vapor-phase deposition The barrier metal layer 1525 A and the Cu seed layer 1525B blanket-deposit the entire upper surface 1530 of the third dielectric layer 1 130 as well as the smoother and more stable respective surfaces 1425 and 1435, and respective bottom areas 1540 and 1550, of the first and second openings 1220 and 1230, respectively, forming a conductive surface 1535, as shown m Figure 15 The barrier metal layer 1525 A may be formed of at least one layer of a barrier metal material, such as tantalum or tantalum nitride, and the like For example, the barrier metal layer 1525 A may also be formed of titanium nitride, titanium-tungsten, nitπded titanium-tungsten, magnesium or another suitable barrier material The copper seed layer 1525B may be formed on top of the one or more barrier metal layers 1525 A by physical vapor deposition (PVD) or chemical vapor deposition (CVD), for example The bulk of the copper trench-fill (or trench-fill of another conductive material) is frequently done using an electroplating technique, where the conductive surface 1535 is mechanically clamped to an electrode (not shown) to establish an electrical contact, and the structure 1 100 is then immersed in an electrolyte solution containing Cu ions (or ions of another conductive material) An electrical current is then passed through the wafer-electrolyte system to cause reduction and deposition of Cu (or ions of another conductive material) on the conductive surface 1535 In addition, an alternating-current bias of the wafer-electrolyte system has been considered as a method of self-planaπzing the deposited Cu film (or film of another conductive material), similar to the deposit-etch cycling used in high-density plasma (HDP) tetraethyl orthosilicate (TEOS) dielectric depositions As shown in Figure 16, this process typically produces a conformal coating of Cu 1640 (or another conductive material) of substantially constant thickness across the entire conductive surface 1535 As shown in Figure 17, once a sufficiently thick layer of Cu 1640 has been deposited, the layer of Cu 1640 is planarized using chemical mechanical polishing (CMP) techniques The planaπzation using CMP clears all Cu and barrier metal from the entire upper surface 1530 of the third dielectric layer 1 130, leaving the Cu 1640 only in a metal structure such as a Cu-filled trench and via, forming a Cu-interconnect 1745, adjacent remaining portions 1725 A and 1725B of the one or more barrier metal layers 1525 A and copper seed layer 1525B (Figures 15 and 16), respectively, as shown in Figure 17 As shown in Figure 17, the Cu-interconnect 1745 may be formed by annealing the Cu 1640, adjacent the remaining portions 1725A and 1725B of the one or more barrier metal layers 1525A and copper seed layer 1525B (Figures 15 and 16), to the first conductive structure 1125 The anneal process may be performed in a traditional tube furnace, at a temperature ranging from approximately 100-500°C, for a time period ranging from approximately 1 -180 minutes, in a nitrogen-containing ambient that may include at least one of ammonia (NH 3 ), molecular nitrogen (N 2 ), molecular hydrogen (H 2 ), argon (Ar), and the like Alternatively, the anneal process may be a rapid thermal anneal (RTA) process performed at a temperature ranging from approximately 100-500°C for a time ranging from approximately 10-180 seconds in a nitrogen-containing ambient that may include at least one of molecular nitrogen (N 2 ), molecular hydrogen (H ), argon (Ar), and the like As shown in Figure 18, the low K third dielectric layer 1130 may be planarized, as needed, using chemical mechanical polishing (CMP) techniques Planaπzation would leave the planarized low K third dielectric layer 1 130 adjacent the Cu-interconnect 1745 and above the etch stop layer 1 1 15, forming a portion of a Cu-interconnect layer 1800 The Cu-mterconnect layer 1800 may include the Cu-interconnect 1745 adjacent the respective treated regions 1420 and 1430 of the second and third dielectric layers 1 120 and 1 130, respectively The Cu-interconnect layer 1800 may also include the first etch stop layer 1 1 10 As shown in Figure 18, the Cu-interconnect layer 1800 may also include an etch stop layer 1820 (also known as a "hard mask" and typically formed of silicon nitride, Sι 3 N 4 , or SiN, for short) formed and patterned above the third dielectric layer 1130 and above at least a portion of the Cu-interconnect 1745 As shown in Figure 19, the Cu-interconnect layer 1800 may be an underlying structure layer (similar to the structure 1 100) to a Cu-interconnect layer 1900 In various illustrative embodiments, the Cu-interconnect layer 1900 may include a Cu-filled trench 1940 adjacent treated regions 1945 of a planarized low K dielectric layer 1935, an intermetal via connection 1910 adjacent a planarized low K dielectric layer 1925. and an etch stop layer 1915 between the low K dielectric layers 1935 and 1925 The intermetal via connection 1910 may be a Cu structure similar to the first Cu structure 1 125, and the intermetal via connection 1910 may be annealed to the Cu-filled trench 1940 in a similar fashion to the anneal described above in relation to the formation of the Cu-interconnect 745 (Figure 7) The Cu-interconnect layer 1900 may also include the etch stop layer 1820 and/or an etch stop layer 1920 formed and patterned above the planarized low K dielectric layer 1935 and above at least a portion of the Cu-filled trench 1940 In various alternative illustrative embodiments, the Cu-mterconnect layer 1900 may be similar to the Cu-interconnect layer 1800, the Cu-interconnect layer 1900 having a Cu-mterconnect disposed therein (not shown) that is similar to the Cu-mterconnect 1745 (Figures 17-18), for example The Cu-interconnect disposed in the Cu-interconnect layer 1900 may be annealed to the Cu-interconnect 1745 disposed in the Cu-mterconnect layer 1800 in a similar fashion to the anneal described above in relation to the formation of the Cu-interconnect 1745 (Figure 17) As shown in Figure 20, an MOS transistor 2010 may be an underlying structure layer (similar to the structure 1 100) to a Cu-interconnect layer 2000 The Cu-interconnect layer 2000 may include Cu-filled trenches and vias 2020 adjacent treated regions 2050 a planarized low K dielectric layer 2040 The Cu-filled trenches and vias 2020 may be annealed to an underlying conductive structure such as source/dra regions 2015 of the MOS transistor 2010 in a similar fashion to the anneal described above in relation to the formation of the Cu-interconnect 1745 (Figure 17) The dual-damascene copper process flow according to various embodiments of the present invention, as shown in Figures 1 1-18, combines the intermetal via connection formation with the Cu trench-fill formation by etching a more complex pattern before the formation of the barrier metal layer and Cu seed layer and before the Cu trench-fill The trench etching continues until the via hole (such as the first opening 1220 in Figure 12) has been etched out The rest of the dual-damascene copper process flow according to various embodiments of the present invention, as shown in Figures 13-18, is essentially identical with the corresponding single-damascene copper process flow according to various embodiments of the present invention, as shown in Figures 3-8 Overall, however, the dual-damascene copper process flow according to various embodiments of the present invention significantly reduces the number of processing steps and is a preferred method of achieving Cu-metalhzation Any of the above-disclosed embodiments of a method of forming a copper interconnect enables a copper interconnect to be formed using conventional damascene techniques in conjunction with covered pore low K dielectric materials that are far more robust than the conventional low K materials typically used in conventional damascene techniques The covered pore low K dielectric materials are far less susceptible to damage during the etching and subsequent processing steps of the conventional damascene techniques than are the conventional low K materials By forming a covered pore low K dielectric layer adjacent the copper interconnect, all of the advantages of using a low K dielectric layer to reduce the capacitance and RC delays between adjacent copper interconnects are retained, without any of the difficulties of forming the copper interconnect using a conventional open pore low K dielectric during the conventional damascene processing The particular embodiments disclosed above are illustrative only, as the invention may be modified and practiced in different but equivalent manners apparent to those skilled in the art having the benefit of the teachings herein Furthermore, no limitations are intended to the details of construction or design herein shown, other than as described in the claims below It is therefore evident that the particular embodiments disclosed above may be altered or modified and all such variations are considered within the scope and spirit of the invention Accordingly, the protection sought herein is as set forth in the claims below

Claims: CLAIMS 1 A method comprising forming a first dielectric layer (130) above a structure layer (100), forming a first opening (220) in the first dielectric layer (130), the first opening (220) having sidewalls (230), and forming a second dielectric layer (430) on the sidewalls (230) of the first opening (220) 2 The method of claim 1 , further comprising planaπzing the first dielectric layer (130), wherein forming the first dielectric layer (130) includes forming the first dielectric layer (130) using a low dielectric constant (low K) dielectric material, having a dielectric constant K of at most about four 3 The method of claim 1, wherein forming the second dielectric layer (430) includes forming the second dielectric layer (430) using a low dielectric constant (low K) dielectric material, having a dielectric constant K of at most about four, and forming the second dielectric layer (430) using one of chemical vapor deposition (CVD), low-pressure CVD (LPCVD), plasma-enhanced CVD (PECVD), sputtering, physical vapor deposition (PVD), and spin-on glass 4 A method comprising forming a first dielectric layer ( 120) above a structure layer ( 100), forming a conductive structure (140) in the first dielectric layer (120), forming a second dielectric layer (130) above the first dielectric layer (120) and above the conductive structure (140), forming an opening (220) in the second dielectric layer (130) above at least a portion of the conductive structure (140), the opening (220) having sidewalls (230), and forming a third dielectric layer (430) on the sidewalls (230) of the opening (220) 5 The method of claim 4, further comprising forming a second conductive layer above the second dielectric layer (130) and in the opening (220), the second conductive layer contacting the at least the portion of the conductive structure (140), forming a conductive interconnect by removing portions of the second conductive layer above the second dielectric layer (130), leaving the conductive interconnect in the opening (220), and annealing the conductive interconnect to the conductive structure (140) 6 The method of claim 5, further comprising planaπzmg the second dielectric layer (130), wherein forming the second dielectric layer (130) includes forming the second dielectric layer ( 130) using a low dielectric constant (low K) dielectric material, having a dielectric constant K of at most about four 7. The method of claim 4, wherein forming the first dielectric layer (120) includes forming the first dielectric layer (120) using a low dielectric constant (low K) dielectric material, having a dielectric constant K of at most about four, and forming the first dielectric layer (120) using one of chemical vapor deposition (CVD), low-pressure CVD (LPCVD), plasma-enhanced CVD (PECVD), sputtering, physical vapor deposition (PVD), and spin-on glass. 8. The method of claim 4, wherein forming the third dielectric layer (430) includes forming the third dielectric layer (430) using a low dielectric constant (low K) dielectric material, having a dielectric constant K of at most about four, and forming the third dielectric layer (430) using one of chemical vapor deposition (CVD), low-pressure CVD (LPCVD), plasma-enhanced CVD (PECVD), sputtering, physical vapor deposition (PVD), and spin-on glass. 9. The method of claim 5, wherein forming the second conductive layer (640) includes forming the second conductive layer (640) using electrochemical deposition of conductive material, forming at least one barrier layer (525A) and a conductive material seed layer (525B) in the second opening (220) before the electrochemical deposition of the conductive material, and removing portions of the second conductive layer (640) includes planarizing the conductive material using chemical mechanical polishing after the electrochemical deposition of the conductive material. 10. A method of forming a copper interconnect ( 1745), the method comprising: forming a first dielectric layer (1 120) above a structure layer (1 100); forming a copper via (1 125) in the first dielectric layer (1120); forming a second dielectric layer (1 130) above the first dielectric layer (1120) and above the copper via (1 125); forming an opening (1230) in the second dielectric layer (1 130) above at least a portion of the copper via (1 125), the opening (1230) having sidewalls (1235) having open pores (1300); and forming a third dielectric layer (1430) on the sidewalls (1235) of the opening (1230) to cover the open pores (1300).

Inventors: APELGREN ERIC M, BESSER PAUL R, MARTIN JEREMY I, SMITH JONATHAN B, SRIKANTEWARA DAKSHINA-MURTHY, APELGREN, ERIC, M., BESSER, PAUL, R., MARTIN, JEREMY, I., SMITH, JONATHAN, B., SRIKANTEWARA, DAKSHINA-MURTHY
Applicants: ADVANCED MICRO DEVICES INC, ADVANCED MICRO DEVICES, INC.
Application year: 2000
Main classification: H01L21
IPC codes: H01L21