METHOD FOR IMPROVING THE RESISTANCE DEGRADATION OF THIN FILM CAPACITORS

Abstract: A method for ion implantation of high dielectric constant materials with dopants to reduce film leakage and improve resistance degradation is disclosed. Particularly, the invention relates to ion implantation of (Ba,Sr)TiO3 (BST) with donor dopants to reduce film leakage and improve resistance degradation of the BST film. The invention also relates to varying the ion implantation angle of the dopant to uniformly dope the high dielectric constant materials when they have been fabricated over a stepped structure. The invention also relates to integrated circuits having a doped thin film high dielectric material used as an insulating layer in a capacitor structure.

Description: METHOD FOR IMPROVING THE RESISTANCE DEGRADATION OF THIN FILM CAPACITORS Field of the Invention The invention relates generally to ion implantation of high dielectric constant materials with dopants to reduce film leakage and improve resistance degradation. Particularly, the invention relates to ion implantation of (Ba,Sr)Ti0 3 (BST) with donor dopants to reduce film leakage and improve resistance degradation of the BST film. The invention also relates to integrated circuits having a doped thin film high dielectric material, used, for example, as an insulating layer in a capacitor. Background of the Invention High dielectric constant (HDC) materials have many microelectronic applications, such as DRAMs, embedded DRAMs, SRAMs, FeRAMS, on-chip capacitors and high frequency capacitors. Typically, these applications employ HDC materials in a capacitive structure, although the present invention may be used to make an HDC thin film with improved properties which is not part of a capacitor. To facilitate construction of larger DRAMs with correspondingly smaller memory cells, capacitor structures and materials which can store the necessary charge in smaller spaces are needed. One of the most promising avenues of research to achieve this goal is the area of HDC materials. HDC materials generally have dielectric constants greater than 50. Examples of particular HDC materials are metal oxide materials such as, lead zirconate titanate (PZT), barium titanate, strontium titanate (SrTi0 3 ), and barium strontium titanate (BST). It is desirable that such a material, if used for DRAMs and other microelectronics applications, be formable over an electrode and underlying structure (without significant harm to either), have low leakage current characteristics and long lifetime, and, for most applications, possess a high dielectric constant. The present invention relates to a method of forming a doped HDC film, specifically a barium and/or strontium titanate dielectric with improved resistance degradation and reduced film leakage. While BST materials have been manufactured in bulk form previously, the physical and electrical properties of the material is not well understood when BST is formed as a thin film (generally less than 5 um) on a semiconducting device. While the dielectric constant of undoped bulk BST is maximized for median grain sizes of between about 0.7 um and about 1.0 um, for smaller grain sizes the dielectric constant fails off rapidly. Thus, BST having extremely small grain size is usually undesirable. Unfortunately, in submicron microcircuits such as DRAM capacitors, particular constraints are placed on BST grain size in the thin film. First, the annealing temperature for BST thin films must generally be kept far below the temperatures commonly used for sintering bulk BST ceramics (generally less than 700 °C. vs. typically greater than 1100 °C. for bulk BST) to avoid damage to the underlying device structure. Thus, the grain nucleation and growth kinetics of the BST crystal lattice is inhibited resulting in smaller grain sizes. Second, the desired film thickness in microelectronic applications may be much less than 5 um (preferably between about 0.05 um and about 0.1 um). It has been found that median grains sizes generally less than half the BST film thickness are required to control dielectric uniformity and avoid shorted capacitors. Thus, a method for producing a HDC material in a thin film structure having good dielectric properties is needed. Generally, the introduction of dopant materials has been shown to affect the dielectric properties of the HDC thin film materials. Doped metal oxide materials, such as BST, in a MOCVD or sol-gel doping process are known to be useful in the manufacture of integrated circuit thin film capacitors having high dielectric constants. See for example, U.S. Pat. No. 5,122,923, herein incorporated by reference. However, while the effects of some dopants is known, dopant chemistry is far from an exact science. It is known to be much harder to accurately control and predict the electrical properties of doped metal oxides as compared with traditional doped materials. Further, the usual methods of making oxides, such as BST, i.e. sputtering and pressing of powders, are inherently difficult to exactly control. In both formation processes, the dopants tend to be more highly concentrated in some parts of the film than in other areas of the film. Prior methods used to dope the (Ba,Sr) Ti0 3 material utilized appropriate precursors of the possible dopants in a metal organic chemical vapor deposition (MOCVD) process. Typical MOCVD deposition of BST utilizes the precursors of Ba(bis(2,2,2,6-tetramethyl-3,5-heptanedionate)) 2 - tetraethylene glycol dimethyl ether; Sr(bis(2,2,2,6-tetramethyl-3,5- heptanedionate)) 2 -tetraethylene glycol dimethyl ether and Ti(bis(isopropoxy)) 2 bis(2,2,2,6-tetramethyl-3,5-heptanedionate) 2 . A liquid delivery system mixed, metered and transported the precursors at room temperature and high pressure to a heated zone, where the precursors were then flash vaporized and mixed with a carrier gas, typically argon, to produce a controlled temperature, low pressure vapor stream. The gas stream was then flowed into a reactor mixing manifold where the gas stream mixed with oxidizer gases. Typically the oxidizer gases were 0 2 δc N 2 0. The mixture of the gas stream and the oxidizer gases then passed through a shower head injector into a deposition chamber. In the MOCVD deposition, both the ratio of the concentrations of the metalorganic compounds in the vaporized liquid and the deposition conditions determine the final film stoichiometry. As can be realized, three component MOCVD process (for BST thin films) is quite complicated. Adding one or more additional components to the process (such as Nb, Ta or Sb dopants) will generate more complexity in the process chemistry. Additionally, developing the precursor chemistry of the multicomponent system to dope BST is also an important requirement. A second prior method for doping BST is using a sol-gel process. Studies on a BST sol-gel process have been undertaken. These studies seem to show that doping of BST or other perovskite titanates via sol-gel process is possible. However, for DRAM technology, sol-gel technology for doping BST films is not a viable deposition process since step coverage with 10 to 1 aspect ratios can not be achieved with the sol-gel processes. Thus, when doping BST in a sol-gel process it is difficult to accurately dope the BST film along the sidewalls of a deep trench capacitor or a tall stud capacitor. Therefore, in the MOCVD and sol-gel processes, doping BST with higher valence cations, such as, for example, Nb, Ta La or Sb, is challenging. Having stable precursors of such elements, adequate incorporation efficiency, uniformity in deposited films and control of stoichiometry in BST with process conditions still need to be explored. The present invention overcomes the difficulties of MOCVD and sol- gel doping of BST thin film dielectrics by using an ion implantation method to dope the BST thin film. Summary of the Invention The present invention overcomes the drawbacks of the conventional methods and provides an ion implanted high dielectric constant material having reduced film leakage and improved resistance degradation. Particularly, the present invention provides a method for ion implantation of BST thin film dielectric material having reduced film leakage and improved resistance degradation. Further, the inventors have observed that stoichiometry of BST formed on the sidewalls of trenches can deviate from the target values. This becomes a serious issue for deep trenches (e.g., 10:1 aspect ratios) since properties such as dielectric constant, leakage, relaxation and resistance degradation will deviate at the sidewalls from other locations on a semiconductor. With the present invention sidewalls can be doped to achieve the desired stoichiometries by using appropriate implant angles. Thus, with appropriate doping levels, side wall stoichiometries can be tailored to achieve desired physical properties. The above and other advantages and features of the invention will be more clearly understood from the following detailed description which is provided in connection with the accompanying drawings. Brief Description of the Drawings FIG. 1 is a schematic view of one embodiment of an apparatus used in the present invention. FIG. 2 is a cross sectional view of a container capacitor formed according to the present invention. FIG. 3 is representative view of an ion implantation of the sidewalls of a semiconductor device having a stud formation. Detailed Description of the Preferred Embodiments The terms wafer or substrate used in the description include any semiconductor-based structure having an exposed silicon surface in which to form the contact electrode structure of this invention. Wafer and substrate are to be understood as including silicon-on insulator (SOI) technology, silicon-on-sapphire (SOS) technology, doped and undoped semiconductors, epitaxial layers of silicon supported by a base semiconductor foundation, and other semiconductor structures. Furthermore, when reference is made to a wafer or substrate in the following description, previous process steps may have been utilized to form regions/junctions in the base semiconductor structure or foundation. It should also be understood that the term wafer or substrate may relate to a base semiconductor structure having undergone processing steps to arrive at a semiconductor platform which may undergo further processing. The term "metal oxide" or "high dielectric constant material (HDC)" used herein means a material of the general form AB0 3 where A and B are cations. The term is intended to include materials were A and B represent multiple elements; for example, it includes materials of the form A , A , l B0 3 , AB , B"0 3 , and A'A"B'B"0 3 , where A 1 , A", B 1 and B" are different metal elements. Preferably, A, A" , A" , are metals selected from the group of metals consisting of Ba, Bi, Sr, Pb, Ca, and La, and B, B', and B" are metals selected from the group consisting of Ti, Zr, Ta, Mo, W, and Nb. Preferably the metal oxide is a perovskite. Many of these metal oxides are ferroelectrics; however the present invention is not so limited. The metal oxides or high dielectric constant materials according to the present invention are doped by ion implantation of dopants into the host lattice of the metal oxide or HDC material. Ion implantation is a well known process for the implantation of dopant elements into a material. The dopants are selected from those known in the art. The dopants should be selected to optimize the desired physical characteristics of the HDC thin film, such as reduced film leakage, improved resistance degradation improved fatigue lifetime, imprint prevention and the like. The dopant also should be selected based on the lattice of the particular HDC material. Preferably the doping materials are those such as niobium, tantalum, antimony at the B-site and lanthanum at the A- site. As will be understood by those skilled in the art, most crystalline materials having an AB0 3 formula are perovskite crystalline compounds. These structures ideally have a unit cell forming a simple cubic structure including A-type cations at the corners of a cube, a B-type cation at the centroid of the cube, and oxygen atoms entered at each facial plane of the cube; however, this idealized structure may vary considerably with temperature. Other forms of perovskite-type compounds can be classified, for example, as orthombic, pseudocubic, pseudotetragonal, rombohedral, and tetragonal. Materials such as barium strontium titanate (BST) exhibit electrical properties that are often very different when measured from bulk ceramics, as compared to the thin film materials (i.e., those less than about ten microns thick) that are used in integrated circuits. Bulk ceramics are typically sintered at temperatures reaching from 1400 °C to 1500 °C, and this high temperature tends to produce a correspondingly high degree of defect-free crystallization. On the other hand, thin films are generally not sintered above about 900 °C to 1100 °C due to the potential for breakdown of integrated circuit wiring, layer interdiffusion, and cracking. Thin films are most often deposited by conventional sputtering techniques, e.g., radio frequency or DC magnetron sputtering. On a microscopic level, these techniques can provide clumped areas of massed materials having nonuniform thicknesses, stratified layers that are improperly mixed to non-homogeneic proportions that are incapable of forming proper average crystals according to the mixture of ingredients. Accordingly, those attempting to replicate bulk ceramic behavior in thin film electronic components have often been unable to duplicate these parameters, even if the electron transfer mechanism remains the same between the two thicknesses of materials. The Ba/Sr ratio of BST should be about 70/30 allowing the material to operate in the paraelectric region for DRAM applications since this will reduce the complexity of understanding the material's response. Therefore, the importance of Ba/Sr ratio in the BST material is controlling the curie temperature (Tc) to be nearly room temperature, thus giving the material the advantage of having a high dielectric constant since the dielectric constant exhibits a peak near Tc while allowing the material to be in the paraelectric region for the operating temperature of the DRAM cell. By maintaining a Ba/Sr ration of about 70/30, the danger of shifting to ferroelectric state by a possible shift in temperature (less than room temperature) is eliminated. This is because the material exhibits a curie -point at room temperature for Ba/Sr: 70/30, but does not go to the ferroelectric phase until temperatures of about 190°K. Capacitor size requirements presently constitute a limiting factor in further reductions of DRAM cell size. A reduction in DRAM cell size is essential to further significant increases in DRAM cell densities for use in an integrated circuit, but this size reduction advantage will require a further reduction in the size of the cell capacitor. Reduction of the capacitor size can be achieved by increasing the dielectric constant of the material used in the dielectric layer of the capacitor, in order to permit the use of a smaller surface area in a capacitor having the desired dielectric properties. Prior methods for increasing the dielectric constant of materials have met with failure because these methods also increased the leakage current and the corresponding conductive current density of the dielectric material at fixed bias voltages. Excessive leakage current or conductive current density renders the material unfit for capacitors in integrated circuits and, in particular, unfit for capacitors in DRAM cells. It remains a problem in the field to increase the dielectric constant of materials, even for high dielectric constant material, such as BST, without significantly increasing the leakage current. The current benchmark for advanced DRAMs is a 10 year lifetime at 85°C and 1.1 V. Under these projected operating conditions, the most important failure mechanism in perovskite titanate thin films is resistance degradation. Resistance degradation is denned as a slow increase of the leakage currents under a constant applied electric field (AC or DC field) after prolonged times. As temperature and applied voltage increase, degradation lifetime decreases. The theories for resistance degradation are based on electromigration of oxygen vacancies under an applied electric field. Oxygen vacancies (Vo- ') are present in significant concentrations in undoped and acceptor- doped alkaline-earth titanates. They are positively charged with respect to host lattice and they can migrate toward the cathode under an electric field. While oxygen vacancies pile-up in front of the cathode and are compensated by the electrons injected from the cathode, a chemical reduction, as exemplified below, can occur at the anode producing additional Vo ": 0 0 x = l/20 2 + Vo- • + 2e- This reaction causes the formation of a p-n junction biased in the forward direction and leads to an increase of leakage currents. In insulating perovskite titanates, it has been observed that acceptors are compensated by oxygen vacancies, while donors are compensated by cation vacancies. It has also been observed that resistance degradation has been stabilized with donor doping. While not wishing to be bound by theory, it is believed that resistance degradation can be improved by reducing oxygen vacancies in the thin film lattice. The resistance degradation mechanism for oxygen vacancy reduction will now be described with reference to a BST type material. It should be understood that similar reaction will take place to reduce oxygen vacancy for similar HDC materials. For BST material: A-site (Ba 2+ , Sr 2+ ) donor dopant: La 3+ B-site (Ti 4+ ) donor dopants: Nb 5+ , Ta 5+ , Sb 5+ These representative dopants for BST material are appropriate by considering their atomic sizes. Having these dopants in the lattice is expected to compensate positively charged oxygen vacancies. Charge equilibrium will be maintained by having these donors in the lattice, as opposed to oxygen vacancy formation. The defect reaction takes place as (e.g., for Nb 5+ doping on B-site): [Nb'] + 2[Vo"] + [h'j => reduction in V ". e.g., for Nb 5+ doped BaTi0 3 : 2BaO + Nb 2 O s — -> 2Nb- χi + 2TΪ Ti + 2Ba Ba + 6O0 + l/20 2 (g) equivalent to: [Nb-] + 2[Vo"] + [h'j or — - >Nb 2 O s + Vo — >2Nb Ti + 50 0 Thus, the addition of the donor dopants to the B-site of the BST host lattice reduces the oxygen vacancies, thereby inhibiting the formation of a p-n junction and reducing the resistance degradation of the film. An exemplary apparatus used in the process for ion implantation according to one embodiment of the present invention is described below. It is to be understood, however, that this apparatus is only one example of many possible different arrangements that may be used to implant dopants according to the invention. The invention is not intended to be limited by the particular apparatus described below. Referring now to FIG. 1, a closed ion implant system 10 for ion implanting semiconductor wafers in accordance with the method of the invention is shown. The ion implant system 10 includes an ion implanter 16. The construction for the ion implanter 16 shown in FIG. 1 is merely illustrative as other types of ion implanter constructions would also be suitable. In the illustrative embodiment, the ion implanter 16 includes a wafer holder 40 for receiving a wafer 18 from the transport channel 26 and for holding the wafer for implantation. The wafer 18 has a high dielectric thin film layer formed thereon as discussed above. The ion implanter 16 includes an ion source 42, an analyzing magnet 44, an acceleration tube 46, a focus 48, and a gate plate 50. The ion implanter 16 is in flow communication with a suitable vacuum source (not shown) such as a turbo molecular pump. This generates a vacuum within the process chamber of the ion implanter 16. With this arrangement an ion implant beam 52 is focused on the high dielectric constant thin film on the surface of the wafer 18 for implanting a desired dopant (such as, for example, niobium, tantalum, antimony or lanthanum) into the crystal lattice structure of the high dielectric constant thin film. After ion implantation the wafer 18 is transferred from the wafer holder 40 to another transport channel 28. At the transport channel 28, the wafer 18 is discharged from the system 10. At this point, the wafer 18 has a conductive layer 60 formed of a suitable conductive material with a doped dielectric film layer 65 formed over the conductive layer 60. A second conductive layer 68 is then formed over doped dielectric film layer 65 to form the container capacitor structure as shown in FIG. 2. The conductive layers 60, 68 may be formed of any conductive material such as metals, i.e., Pt, Ru, Ir, Pd, Au or conductive oxides such as RuOx, IrOx. The doped dielectric film layer 65 is formed by doping a HDC material as described above. Reference is now made to FIG. 3. This figure shows a representative view of a second embodiment of the present invention. Dopant levels of BST formed on the sidewalls 102 of a stud 100 can deviate from the target values. This becomes a serious issue for deep trenches (e.g., 10:1 aspect ratios) or studs as shown in FIG. 3 since properties such as dielectric constant, leakage, relaxation and resistance degradation will deviate at the sidewalls from the values for these properties in the horizontal portions of the device. According to the present invention the BST dielectric layer 105 formed over a conductive layer 120 on the sidewalls 102 can be doped to achieve the desired stoichiometries by appropriate implant angles 110-119 by appropriate movement of wafer holder 40. A second electrode (not shown) may then be formed over BST layer 105 to arrive a capacitor structure. Thus, with appropriate doping levels, the BST layer 105 overlying the conductive layer 120 on sidewalls 102 can be tailored to achieve desired physical properties. The present invention provides a method for ion implantation of high dielectric constant materials with dopants to reduce film leakage and improve resistance degradation. The invention also provides a method for varying the ion implantation angle of the dopant to uniformly dope the high dielectric constant materials when they have been fabricated over a stepped structure. It should again be noted that although the invention has been described with specific reference to DRAM memory circuits and container capacitors, the invention has broader applicability and may be used in any integrated circuit, such as, for example in a capacitor. Similarly, the process described above is but one method of many that could be used. Accordingly, the above description and accompanying drawings are only illustrative of preferred embodiments which can achieve the features and advantages of the present invention. It is not intended that the invention be limited to the embodiments shown and described in detail herein. The invention is only limited by the spirit and scope of the following claims. What is claimed is:

Claims: 1. A method for improving the physical properties of a high dielectric constant thin film material, said method comprising: providing a high dielectric constant thin film material on a substrate; doping said high dielectric thin film material with a dopant by ion implantation. 2. The method according to claim 1, wherein said high dielectric constant thin film material is selected from the group consisting of BST, SBT, SrTiO, and PZT. 3. The method according to claim 2, wherein said high dielectric constant thin film material is BST. 4. The method according to claim 1, wherein said dopants are selected from the group consisting of niobium, lanthanum, antimony and tantalum. 5. The method according to claim 1, wherein said high dielectric constant thin film material is a pervoskite of the formula AB0 3 where A represents metals selected from Ba, Bi, Sr, Pb, Ca, and La, and B represents metals selected from Ti, Zr, Ta, Mo, W, and Nb. 6. The method according to claim 5, wherein said doping step includes doping the A-site of said high dielectric constant thin film material with a lanthanum 3* ion. 7. The method according to claim 5, wherein said doping step includes doping the B-site of said high dielectric constant thin film material with a dopant selected from the group consisting of Nb s+ , Sb 5+ and Ta 5+ . 8. The method according to claim 5, wherein said pervoskite is barium strontium titanite and said doping step includes doping the A-site with a lanthanum 3* ion. 9. The method according to claim 5, wherein said pervoskite is barium strontium titanite and said doping step includes doping the B-site with a dopant selected from the group consisting of Nb 5+ , Sb 5+ and Ta 5+ . 10. A method for reducing the oxygen vacancies of a high dielectric constant thin film material, said method comprising: providing a high dielectric constant thin film material; doping said high dielectric thin film material with a dopant by ion implantation. 11. The method according to claim 10, wherein said high dielectric constant thin film material is selected from the group consisting of BST, SBT, SrTiO, and PZT. 12. The method according to claim 11, wherein said high dielectric constant thin film material is BST. 13. The method according to claim 10, wherein said dopants are selected from the group consisting of niobium, lanthanum, antimony and tantalum. 14. The method according to claim 10, wherein said high dielectric constant thin film material is a pervoskite of the formula AB0 3 where A represents metals selected from Ba, Bi, Sr, Pb, Ca, and La, and B represents metals selected from Ti, Zr, Ta, Mo, W, and Nb. 15. The method according to claim 14, wherein said doping step includes doping the A-site of said high dielectric constant thin film material with a lanthanum 3* ion. 16. The method according to claim 14, wherein said doping step includes doping the B-site of said high dielectric constant thin film material with a dopant selected from the group consisting of Nb 5+ , Sb 5+ and Ta 5+ . 17. The method according to claim 14, wherein said pervoskite is barium strontium titanite and said doping step includes doping the A-site with a lanthanum 3* ion. 18. The method according to claim 14, wherein said pervoskite is barium strontium titanite and said doping step includes doping the B-site with a dopant selected from the group consisting of Nb 5* , Sb 5+ and Ta 5* . 19. A method for improving the resistance degradation of a BST high dielectric constant thin film material, said method comprising: providing a BST high dielectric constant thin film material; doping said BST high dielectric thin film material with a dopant by ion implantation. 20. The method according to claim 19, wherein said dopants are selected from the group consisting of niobium, lanthanum, antimony and tantalum. 21. The method according to claim 19, wherein said doping step includes doping the A-site of said BST high dielectric constant thin film material with a lanthanum 3* ion. 22. The method according to claim 19, wherein said doping step includes doping the B-site of said BST high dielectric constant thin film material with a dopant selected from the group consisting of Nb 5* , Sb 5* and Ta s* . 23. The method according to claim 19, further comprising varying the implant angle of said ion implantation step to evenly dope said BST high dielectric constant film. 24. A BST high dielectric constant thin film material having improved resistance degradation formed by the steps of: providing a BST high dielectric constant thin film material; doping said BST high dielectric thin film material with a dopant by ion implantation. 25. The BST high dielectric constant thin film material according to claim 24, wherein said dopants are selected from the group consisting of niobium, lanthanum, antimony and tantalum. 26. The BST high dielectric constant thin film material according to claim 24, wherein said doping step includes doping the A-site of said BST high dielectric constant thin film material with a lanthanum 3* ion. 27. The BST high dielectric constant thin film material according to claim 24, wherein said doping step includes doping the B-site of said BST high dielectric constant thin film material with a dopant selected from the group consisting of Nb 5* , Sb 5* and Ta 5* . 28. The BST high dielectric constant thin film material according to claim 24, wherein said BST high dielectric constant film material is uniformly doped by varying the implant angle of said ion implantation. 29. The BST high dielectric constant thin film material according to claim 24, wherein said BST high dielectric thin film material is included in a DRAM cell. 30. The BST high dielectric constant thin film material according to claim 24, wherein said BST high dielectric thin film material is formed in a capacitor. 31. A method for fabricating a high capacitance thin film integrated circuit capacitor device, said method comprising: providing a substrate; forming a first electrode on said substrate; forming a high capacitance thin film layer over said first electrode; implanting said high capacitance thin film layer with dopants by ion implantation; and forming a second electrode on said doped high capacitance thin film layer to complete said integrated circuit capacitor. 32. The method according to claim 31, wherein said high capacitance thin film layer is selected from the group consisting of BST, SBT, SrTi0 3 and PZT. 33. The method according to claim 32, wherein said high capacitance thin film layer is BST. 34. The method according to claim 33, wherein the ratio of Ba to Sr is about 70:30. 35. The method according to claim 31, wherein said dopants are selected from the group consisting of niobium, lanthanum, antimony and tantalum. 36. The method according to claim 31, wherein said high dielectric constant thin film material is a pervoskite of the formula AB0 3 where A represents metals selected from Ba, Bi, Sr, Pb, Ca, and La, and B represents metals selected from Ti, Zr, Ta, Mo, W, and Nb. 37. The method according to claim 36, wherein said doping step includes doping the A-site of said high dielectric constant thin film material with a lanthanum 3* ion. 38. The method according to claim 36, wherein said doping step includes doping the B-site of said high dielectric constant thin film material with a dopant selected from the group consisting of Nb 5* , Sb 5* and Ta 5* . 39. The method according to claim 36, wherein said pervoskite is barium strontium titanite and said doping step includes doping the A-site with a lanthanum 3* ion. 40. The method according to claim 36, wherein said pervoskite is barium strontium titanite and said doping step includes doping the B-site with a dopant selected from the group consisting of Nb 5* , Sb 5* and Ta 5* . 41. The method according to claim 31, wherein said first and second electrodes are selected from the group consisting of Pt, Ru, Ir, Pd, Au RuOx, and IrOx. 42. The method according to claim 31, further comprising varying the implant angle of said ion implantation step to evenly dope said high capacitance thin film layer. 43. The method according to claim 33, further comprising varying the implant angle of said ion implantation step to evenly dope said BST high capacitance thin film layer. 44. The method according to claim 31, wherein said integrated circuit capacitor is fabricated in a DRAM cell. 45. A method for fabricating an integrated circuit containing a doped BST layer, said method comprising: providing a substrate; forming a first electrode on said substrate; forming a thin film layer of BST over said first electrode; implanting said thin film BST layer with dopants by ion implantation; and forming a second electrode on said doped thin film BST layer to complete said integrated circuit capacitor. 46. The method according to claim 45, wherein the ratio of Ba to Sr is about 70:30. 47. The method according to claim 45, wherein said dopants are selected from the group consisting of niobium, lanthanum, antimony and tantalum. 48. The method according to claim 45, wherein said doping step includes doping the A-site of said thin film BST layer with a lanthanum 3 * ion. 49. The method according to claim 45, wherein said doping step includes doping the B-site of said thin film BST layer with a dopant selected from the group consisting of Nb 5* , Sb 5* and Ta 5* . 50. The method according to claim 45, wherein said first and second electrodes are selected from the group consisting of Pt, Ru, Ir, Pd, Au RuOx, and IrOx. 51. The method according to claim 45, further comprising varying the implant angle of said ion implantation step to evenly dope said thin film BST layer. 52. The method according to claim 45, wherein said integrated circuit capacitor is used in a DRAM cell. 53. An integrated circuit capacitor device formed by the steps of: providing a substrate; forming a first electrode on said substrate; forming a thin film dielectric layer of a high capacitance material over said first electrode; implanting said thin film layer with dopants by ion implantation; and forming a second electrode on said doped thin film layer to complete said integrated circuit capacitor. 54. The integrated circuit capacitor device according to claim 53, wherein said thin film layer is selected from the group consisting of BST, SBT, SrTiO, and PZT. 55. The integrated circuit capacitor device according to claim 54, wherein said thin film layer is BST. 56. The integrated circuit capacitor device according to claim 55, wherein the ratio of Ba to Sr is about 70:30. 57. The integrated circuit capacitor device according to claim 53, wherein said dopants are selected from the group consisting of niobium, lanthanum, antimony and tantalum. 58. The integrated circuit capacitor device according to claim 53, wherein said thin film layer is a pervoskite of the formula AB0 3 where A represents metals selected from Ba, Bi, Sr, Pb, Ca, and La, and B represents metals selected from Ti, Zr, Ta, Mo, W, and Nb. 59. The integrated circuit capacitor device according to claim 58, wherein said doping step includes doping the A-site of said thin film layer with a lanthanum 3* ion. 60. The method according to claim 5, wherein said doping step includes doping the B-site of said high dielectric constant thin film material with a dopant selected from the group consisting of Nb 5* , Sb 5* and Ta 5* . 61. The integrated circuit capacitor device according to claim 58, wherein said pervoskite is barium strontium titanite and said doping step includes doping the A-site with a lanthanum 3* ion. 62. The integrated circuit capacitor device according to claim 58, wherein said pervoskite is barium strontium titanite and said doping step includes doping the B-site with a dopant selected from the group consisting of Nb 5* , Sb 5* and Ta 5* . 63. The integrated circuit capacitor device according to claim 53, wherein said first and second electrodes are selected from the group consisting of Pt, Ru, Ir, Pd, Au RuOx, and IrOx. 64. The integrated circuit capacitor device according to claim 53, wherein said integrated circuit capacitor is a container capacitor. 65. The integrated circuit capacitor according to claim 53, wherein said integrated circuit capacitor is formed over a stud. 66. The integrated circuit capacitor according to claim 64, further comprising varying the implant angle of said ion implantation step to evenly dope said high capacitance thin film layer. 67. The integrated circuit capacitor according to claim 65, further comprising varying the implant angle of said ion implantation step to evenly dope said high capacitance t-hin film layer. 68. The integrated circuit capacitor device according to claim 54, wherein said integrated circuit capacitor is a container capacitor. 69. The integrated circuit capacitor according to claim 54, wherein said integrated circuit capacitor is formed over a stud. 70. The integrated circuit capacitor according to claim 68, further comprising varying the implant angle of said ion implantation step to evenly dope said high capacitance thin film layer. 71. The integrated circuit capacitor according to claim 69, further comprising varying the implant angle of said ion implantation step to evenly dope said high capacitance thin film layer. 72. The integrated circuit capacitor according to claim 53, wherein said integrated circuit capacitor is fabricated in a DRAM cell.

Inventors: AL-SHAREEF HUSAM N, BASCERI CEM, AL-SHAREEF, HUSAM, N., BASCERI, CEM
Applicants: MICRON TECHNOLOGY INC, MICRON TECHNOLOGY, INC.
Application year: 2000
Main classification: H01L21
IPC codes: H01L21