Interconnection scheme for semiconductor storage device

Abstract: In a semiconductor storage device, a line of lower-side backing wiring is provided on a line of gate wiring via an insulation layer, and a line of upper-side backing wiring is provided further on the top layer thereof via another insulation layer. Contacts between the gate wiring and upper-side backing wiring are distributed and arranged on two or more different lines extending in an orthogonal direction with respect to a direction to which the gate wiring extends, and any contacts adjacent to each other of the contacts are arranged on different lines. The lower-side backing wiring passes through between the adjacent contacts.

Description: The present invention relates to a semiconductor integrated circuit device. More particularly this invention relates to a semiconductor integrated circuit device having a multi-layered wiring structure in which auxiliary signal lines are provided together with signal lines each made with polysilicon or polycide to prevent a delay in signal transmission. EP0817197A discloses a circuit which is designed with a first lower conductor (500) having two ends. One end of the first lower conductor is coupled to a first signal source (386). A first upper conductor (544) has two ends and is spaced apart from the first lower conductor by a distance less than an allowable spacing between adjacent lower conductors. One end of the first upper conductor is coupled to a second signal source (384). A second upper conductor (508) has two ends. One end of the second upper conductor is coupled to another end of the first lower conductor for receiving a signal from the first signal source. A second lower conductor (552) has two ends and is spaced apart from the second upper conductor by a distance less than the allowable spacing between adjacent lower conductors. One end of the second lower conductor is coupled to another end of the first upper conductor for receiving a signal from the second signal source. Since the upper and lower conductors are spaced apart by a distance less than an allowable spacing between adjacent lower conductors, layout area is conserved. Total resistance of conductors connected to each signal source is the same, so signal delay is the same. US5442212 discloses a semiconductor memory device, in which pitch of bit lines is made larger than pitch of word lines, and a storage node contact is positioned in each rectangular area surrounded by the bit lines and the word lines. The distance between centers of adjacent storage node contacts and the distance between centers of a bit line contact and an adjacent storage node contact are both made larger than the pitch of word lines. By this structure, planar area per unit memory cell can be increased, registration margin between the storage node and the storage node contact can be enlarged, short-circuit between the bit line and the storage node contact is prevented, and thus a memory cell structure of high production yield and high reliability can be realized. For example, a DRAM (dynamic random access memory) as one of semiconductor integrated circuit devices is configured to provide a MOS transistor and a capacitor in each of memory cells arranged in a matrix. A word line of the DRAM is formed by gate wiring of the MOS transistor, which is made of a material such as polysilicon or polycide having a comparatively large resistance. Therefore, by providing an auxiliary signal line called a backing wiring along the gate wiring, a signal can be propagated from one end of the word line to the other end thereof without development of long delays in its propagation. Fig. 1 is a layout showing a conventional type of wiring pattern between memory cells of a DRAM having auxiliary signal lines for backing provided along lines of gate wiring. In general, each auxiliary signal line 11 is formed so as to extend along each gate wiring 12, as shown in Fig. 1, in a low-resistive wired layer provided on a layer above the gate wiring 12. The auxiliary signal line 11 is electrically connected to the gate wiring 12 via a contact 14 between a memory cell 13 and another memory cell 13. In this contact 14, a line width of the gate wiring 12 is wider than that of a wiring section other than the contact. A wiring pitch of the auxiliary signal line 11 becomes wider by a widened line width of the gate wiring 12 in the contact 14. The wiring pitch of the auxiliary signal line 11 matches the pitch of the gate wiring 12, namely the pitch of the gate wiring 12 depends on the pitch of the auxiliary signal line 11. Thus, the pitch of the gate wiring 12 may become wider than the minimum pitch of the gate wiring 12 which can originally be produced due to restriction on the process. This causes a higher degree of integration of a DRAM to be prevented. It should be noted that, in Fig. 1, a dotted line within the memory cell 13 represents the fact that the gate wiring 12 and auxiliary signal line 11 are electrically connected to each other inside the memory cell 13. To solve the above problem, there has been proposed a word line backing system that an auxiliary signal line for backing is divided into two different wired layers in upper and lower sides. Each wiring pitch of the upper and lower auxiliary signal lines is made two times wider than the pitch of the gate wiring by alternately arranging the upper and lower auxiliary signal lines for the gate wiring and making the pitch of the gate wiring narrower (e.g., Japanese Patent Laid-Open Publication No. HEI 7-45720). According to this system, there is provided a wiring pattern that contacts, each for electrically connecting the auxiliary signal line provided on the upper side to the gate wiring, are arranged in a line in the vertical direction with respect to the direction to which the gate wiring extends and a lower-side linear auxiliary signal line passes through between the adjacent contacts. Further, there has also been proposed a hierarchical word line system in which, in place of provision of the auxiliary signal line for backing, as shown in Fig. 2, a word line is divided into multiple sections to provide sub-word lines 15, and a sub-low decoder 16 is provided between the memory cells 13. In the word line backing system disclosed in Japanese Patent Laid-Open Publication No. HEI 7-45720, however, the minimum pitch of the gate wiring actually depends on a space between a contact provided between an upper-side auxiliary signal line and gate wiring and a lower-side auxiliary signal line. Therefore, the pitch of the gate wiring can not be made narrow enough to achieve a higher degree of integration. Accordingly, there has been a problem that further higher degree of integration can not be achieved with the same semiconductor chip size or that a chip size can not be reduced with the same degree of integration. Further, the above-described hierarchical word line system has a problem as follows. Because a plurality of sub-low decoders are distributed and arranged, the pitch of the word line can be made narrower. However, increase in the area due to provision of those sub-low decoders is larger than the case where a contact between gate wiring and the above-described auxiliary signal line for backing is provided. Resultantly, a higher degree of integration or reduction of a chip size can not be achieved. Embodiments of the present invention aim to solve the problems described above. Specifically, embodiments of the present invention aim to provide a semiconductor integrated circuit device in which a higher degree of integration or reduction of a chip size can be achieved by providing upper and lower two-layered auxiliary signal lines in a specified wiring pattern. The present invention is defined in the attached independent claims 1 and 7, to which reference should now be made. Further, preferred features may be found in the sub-claims appended thereto. In the present invention, auxiliary signal lines are provided in upper and lower layers on a signal line (gate wiring) via an insulation layer, contacts each between the signal line and the upper-side auxiliary signal line (upper-side backing wiring) are distributed and arranged on two or more different lines extending in a vertical direction with respect to a direction to which the signal line extends, any contacts in a pair adjacent to each other among the contacts between the signal line and the upper-side auxiliary signal line are arranged on different lines, and the lower-side auxiliary signal line (lower-side backing wiring) passes through between the adjacent contacts. With the present invention, the contacts each between the signal line and the upper-side auxiliary signal line are distributed and arranged on two columns, and also adjacent contacts in a pair are arranged on the different columns, and further the lower-side auxiliary signal line passes through between the adjacent contacts so as to weave through from one to the other. Therefore, even when a line width of the signal line is widened in the contact, the pitch of the lower-side auxiliary signal line does not need to be widened. Accordingly, wiring pitch of the upper and lower auxiliary signal lines can be made narrower, which allows a higher degree of integration of a semiconductor integrated circuit device or reduction of a chip size to be achieved. In addition, auxiliary signal lines are provided in upper and lower layers on a signal line via an insulation layer, contacts each between the signal line and the upper-side auxiliary signal line are distributed and arranged on two or more different lines extending in a vertical direction with respect to a direction to which the signal line extends, any adjacent contacts in a pair among the contacts each between the signal line and the upper-side auxiliary signal line may be arranged on the different lines between the lower-side auxiliary signal lines in a pair adjacent to each other. According to one feature of the present invention, contacts each between the signal line and the upper-side auxiliary signal line are distributed and arranged on two columns, and any adjacent contacts in a pair are arranged on the different columns between adjacent lower-side auxiliary signal lines in a pair. Therefore even when a line width of the signal line is widened in the contact, the pitch of the lower-side auxiliary signal line does not need to be widened. Accordingly, wiring pitch of upper and lower auxiliary signal lines can be made narrower, which allows a higher degree of integration of a semiconductor integrated circuit device or reduction of a chip size to be achieved. In addition, the contact consists of a conductive island formed on the same wired layer as that of a lower-side auxiliary signal line, a first auxiliary contact for electrically connecting a signal line to the island, and a second auxiliary contact for electrically connecting the island to an upper-side auxiliary signal line, so that the first auxiliary contact and second auxiliary contact may be arranged on the same line. Further, the contact consists of a conductive island formed on the same wired layer as that of a lower-side auxiliary signal line, a first auxiliary contact for electrically connecting a signal line to the island, and a second auxiliary contact for electrically connecting the island to a second auxiliary signal line, in which the first auxiliary contact and the second auxiliary contact may be displaced from each other and arranged on two different stages, and the signal line and the upper-side auxiliary signal line may also directly and electrically be connected to each other. Furthermore, the first contact and the second contact may be provided alternately for every one unit or every two units for a plurality of signal lines. Embodiments of the present invention will now be described by way of example with reference to the accompanying drawings, in which: Fig. 1 is a layout showing a known type of wiring pattern between memory cells of the DRAM; and Fig. 2 is a layout showing configuration between memory cells of the DRAM based on a known type of hierarchical word line system; Fig. 3 is a layout showing a wiring pattern between memory cells of the DRAM in a first embodiment of the semiconductor integrated circuit device according to the present invention; Fig. 4 is a layout showing a wiring pattern between memory cells of the DRAM in the first embodiment of the semiconductor integrated circuit device according to the present invention; Fig. 5 is a cross-sectional view of the wiring pattern taken along the line A-A in Fig. 3; Fig. 6 is a circuit diagram of the DRAM with the present invention applied therein; Fig. 7 is a layout showing a wiring pattern between memory cells of the DRAM in a second embodiment of the semiconductor integrated circuit device according to the present invention; Fig. 8 is a cross-sectional view of the wiring pattern taken along the line B-B in Fig. 7; Fig. 9 is a layout showing a wiring pattern between memory cells of the DRAM in a third embodiment of the semiconductor integrated circuit device according to the present invention; Fig. 10 is a cross-sectional view of the wiring pattern taken along the line C-C in Fig. 9; Fig. 11 is a layout showing a wiring pattern between memory cells of the DRAM in a fourth embodiment of the semiconductor integrated circuit device according to the present invention; Fig. 12 is a layout showing a wiring pattern between memory cells of the DRAM in a fifth embodiment of the semiconductor integrated circuit device according to the present invention; Fig. 13 is a layout showing a wiring pattern between memory cells of the DRAM in a sixth embodiment of the semiconductor integrated circuit device according to the present invention; Fig. 14 is a layout showing a wiring pattern between memory cells of the DRAM in a seventh embodiment of the semiconductor integrated circuit device according to the present invention; Fig. 15 is a layout showing a wiring pattern between memory cells of the DRAM in the seventh embodiment of the semiconductor integrated circuit device according to the present invention; Fig. 16 is a layout showing a wiring pattern between memory cells of the DRAM in an eighth embodiment of the semiconductor integrated circuit device according to the present invention. In the Embodiments below, a case where the semiconductor integrated circuit device according to the present invention is applied in a DRAM is explained. Fig. 3 and Fig. 4 are layouts showing a wiring pattern between memory cells of the DRAM in a first embodiment. Fig. 5 is a cross-sectional view of the wiring pattern along the line A-A in Fig. 3. Fig. 6 is a circuit diagram of the DRAM with the present invention applied therein. As shown in Fig. 6, the DRAM has a MOS transistor Q for switching and a capacitor C for accumulation of charge in each of memory cells and gate wiring of the transistor Q is a word line W. As shown in Fig. 5, the DRAM in this first embodiment consists of a line of gate wiring 21 as a signal line. Further, there is provided a line of lower-side backing wiring 23 as a first auxiliary signal line formed on a wired layer provided on a layer upper than the gate wiring 21 via a first insulation layer 22, and a line of upper-side backing wiring 25 as a second auxiliary signal line formed on a wired layer provided on a layer upper than the lower-side backing wiring 23 via a second insulation layer 24. The second auxiliary signal line 25 is covered with a protective film or a third insulation layer 26 acting as an inter-layer insulation film between the immediate upper layer. The first through third insulation layers 22, 24, and 26 are not shown in Fig. 3. Further, dotted lines inside a memory cell 20 represent the fact that the gate wiring 21 (211 to 218), the lower-side backing wiring 23, and the upper-side backing wiring 25 (251 to 254) are electrically connected to each other inside the memory cell 20 (the same applies for Fig. 4, Fig. 7, Fig. 9, and Fig. 11 to Fig. 16 explained below). The lines of gate wiring 21 are provided in a staggered arrangement for every one line. Namely, as shown in Fig. 3, for instance, lines of odd-numbered gate wiring 211, 213, 215, and 217 from the top are provided between the memory cell 20 and the adjacent memory cell 20A on the right-hand side, whereas lines of even-numbered gate wiring 212, 214, 216, and 218 are provided between the memory cell 20 and the adjacent memory cell 20B on the left-hand side. The lower-side backing wiring 23 is provided along each of the lines of odd-numbered gate wiring 211, 213, 215, and 217. The upper-side backing wiring 25 is provided along each of the lines of even-numbered gate wiring 212, 214, 216, and 218. The lines of low-side and upper-side backing wiring 23 and 25 are made of, for instance, aluminum or copper. However, there is no particular restriction on the material. Each of the lines of odd-numbered gate wiring 211, 213, 215, and 217 and the corresponding lower-side backing wiring 23 are electrically connected to each other by a first contact 27. This first contact is a conductor penetrating the first insulation layer 22 between the memory cell 20 and the adjacent memory cell 20A. Each of the lines of even-numbered gate wiring 212, 214, 216, and 218 and the corresponding upper-side backing wiring 25 are electrically connected to each other by second contacts 28 (281 to 284) between the memory cell 20 and the adjacent memory cell 20B provided on the opposite side of the memory cell 20A. The second contacts 28 are alternately arranged on two different lines extending in a substantially orthogonal (in the figure vertical) direction with respect to the direction to which the gate wiring 21 extends (lateral direction in the figure). Namely, for example, the second contacts 281 and 283 for the lines of odd-numbered upper-side backing wiring 251 and 253 in Fig. 3 are arranged thereon closer to the memory cell 20B on the left-hand side, whereas the second contacts 282 and 284 for the lines of even-numbered upper-side backing wiring 252 and 254 are arranged thereon closer to the memory cell 20 at the center thereof. As shown in Fig. 4, the second contacts 28 may alternately be arranged for every two units on the two different lines extending in the vertical direction with respect to the direction to which the gate wiring 21 extends (lateral direction in the figure). Namely, of second contacts 28 provided in both sides of the second contact 28, at least only either one of the contacts may be arranged on the different line described above. The lines of lower-side backing wiring 23 are provided by bending so as to weave through between the second contacts 281, 282, 283, and 284 which are alternately arranged as described above. More specifically, the lower-side backing wiring 23 is formed in a substantially Z shape or in a substantially reverse Z shape provided along the second contacts 28 by being apart therefrom as far as possible between the memory cell 20 and the memory cell 20B. In the first embodiment, the second contact 28 consists of a first auxiliary contact 31 made of a conductor penetrating the first insulation layer 22, a conductive island 32 provided on the same wired layer as the lower-side backing wiring 23, and a second auxiliary contact 33 made of a conductor penetrating the second insulation layer 24. The gate wiring 21 and the island 32 are electrically connected to each other by the first auxiliary contact 31, whereas the island 32 and the upper-side backing wiring 25 are electrically connected to each other by the second auxiliary contact 33. In the first embodiment, the second auxiliary contact 33 is provided on the same line as that of the first auxiliary contact 31. A manufacturing process of the DRAM in this first embodiment is explained below. At first, a MOS transistor Q and a capacitor C are formed on a semiconductor substrate to form a line of gate wiring 21 in a desired pattern. In the next step, the top surface thereof is laminated with the first insulation layer 22, and contact holes are made thereon. The contact holes are filled with conductive material such as metal to form the first contact 27 and the first auxiliary contact 31. At the same time the lower-side backing wiring 23 and islands 32 are patterned and formed on the first insulation layer 22. In the next step, the top surface thereof is laminated with the second insulation layer 24, contact holes are made thereon, and the holes are filled with conductive material such as metal to form the second auxiliary contacts 33. The upper-side backing wiring 25 is formed on the second insulation layer 24 and the top surface thereof is covered with a third insulation layer 26. Each of the processes can be executed through the known process. According to the first embodiment, in an area where eight lines of gate wiring 211, 212, 213, 214, 215, 216, 217, and 218 are provided, four lines of upper-side backing wiring 25 are provided, whereas six lines in total of the lower-side backing wiring 23 including the islands 32 are provided, thus the upper-side backing wiring 25 can be provided with a pitch twice wider as compared to the pitch of the gate wiring 21 and the lower-side backing wiring 23 can be provided with a pitch around four by three (4/3) times wider. Therefore, the gate wiring 21 can be provided with a pitch smaller than the wiring pitch of the upper-side backing wiring 25 and lower-side backing wiring 23. In this DRAM, the second contacts 28 are provided in a staggered arrangement so as not to be arranged in a line, and the lower-side backing wiring 23 is provided by bending so as to weave through between the second contacts by being apart therefrom as far as possible. Therefore, even if the line width of the gate wiring 21 is widened in the second contact 28, a pitch of the lower-side backing wiring 23 does not need to be widened and can be left as it is. Therefore, each wiring pitch of the lines of upper and lower side backing wiring 23 and 25 can be made narrower, which allows the gate wiring 21 to be provided with a still smaller pitch, thus a higher degree of integration of a DRAM or reduction of a chip size can be achieved. Fig. 7 is a layout showing a wiring pattern between memory cells of a DRAM in the second embodiment. Fig. 8 is a cross-sectional view of the wiring pattern along the line B-B in Fig. 7. As shown in Fig. 7 and Fig. 8, the second embodiment is realized by directly and electrically connecting the gate wiring 21 to the upper-side backing wiring 25 with the help of second contacts 29 instead of the second contacts 28 in the first embodiment. The other elements of the configuration are the same as those in the first embodiment, therefore the same reference numerals are assigned to the elements corresponding to those in the first embodiment and description thereof is omitted herein. In the second embodiment, after the top surface is laminated with the first insulation layer 22, only contact holes for forming first contacts 27 is made therein. Contact holes for forming the second contacts 29 are made after the top surface of the contact is laminated with the second insulation layer 24. According to the second embodiment, both of the lines of backing wiring 23 and 25 can be provided with a pitch around four by three (4/3) as compared to the pitch of the gate wiring 21, therefore the gate wiring 21 can be provided with a pitch smaller than each wiring pitch of the upper-side backing wiring 25 and lower-side backing wiring 23. Thus, a higher degree of integration in the DRAM or reduction of a chip size can be achieved in the same manner as in the first embodiment. Fig. 9 is a layout showing a wiring pattern between memory cells of a DRAM in a third embodiment. Fig. 10 is a cross-sectional view of the wiring pattern along a line C-C shown in Fig. 9. As shown in Fig. 9 and Fig. 10, the third embodiment is realized by arranging the first auxiliary contacts 31 and the second auxiliary contacts 33 based on displacement thereof from each other on the plane layout in the first embodiment. Locations of the first auxiliary contacts 31 and the second auxiliary contacts 33 on the plane are interchanged between adjacent second contacts 28. Namely, in Fig. 9, a case where the first auxiliary contact 31 is located on the right-hand side from the second auxiliary contact 33 and a case where the first auxiliary contact 31 is located on the left-hand side therefrom repeat alternately. The other elements of the configuration are the same as those in the first embodiment, therefore the same reference numerals are assigned to the elements corresponding to those in the first embodiment and description thereof is omitted herein. According to the third embodiment, in addition to the same effect as that of the first embodiment, as the first auxiliary contacts 31 and the second auxiliary contacts 33 are displaced from each other, a concave section which may be formed on the upper edge of the second auxiliary contacts 33 in formation of the contacts can be made smaller. Therefore, poor contact due to a bigger concave section can be prevented, thus it is possible to obtain such an effect that the second auxiliary contacts 33 and the upper-side backing wiring 25 can electrically be connected to each other more securely. Fig. 11 is a layout showing a wiring pattern between memory cells of a DRAM in a fourth embodiment. As shown in Fig. 11, the fourth embodiment is realized by providing the lines of gate wiring 21 in the first embodiment in a staggered arrangement for every two lines. The lower-side backing wiring 23 is electrically connected to each of lines of first, fourth, fifth, and eighth gate wiring 211, 214, 215, and 218 from the top in Fig. 11 via the first contacts 27. The upper-side backing wiring 25 is electrically connected to each of lines of second, third, sixth, and seventh gate wiring 212, 213, 216, and 217 from the top in Fig. 11 via the second contacts 28. The other elements of the configuration are the same as those in the first embodiment, therefore the same reference numerals are assigned to the elements corresponding to those in the first embodiment and description thereof is omitted herein. According to the fourth embodiment, the upper-side backing wiring 25 can be provided with a pitch twice as wide as compared to the pitch of the gate wiring 21 and the lower-side backing wiring 23 can be provided with a pitch around four by three (4/3) times wider. Therefore, the gate wiring 21 can be provided with a pitch smaller than each wiring pitch of the upper-side backing wiring 25 and lower-side backing wiring 23, thus a higher degree of integration in the DRAM or reduction of a chip size can be achieved in the same manner as in the first embodiment. Fig. 12 is a layout showing a wiring pattern between memory cells of a DRAM in a fifth embodiment. As shown in Fig. 12, the fifth embodiment is realized by distributing second contacts 28, in the first embodiment, on three columns between the memory cell 20 and memory cell 20B and arranging the second contacts on the same column for every two units. The other elements of the configuration are the same as those in the first embodiment, therefore the same reference numerals are assigned to the elements corresponding to those in the first embodiment and description thereof is omitted herein. According to the fifth embodiment, the upper-side backing wiring 25 and the lower-side backing wiring 23 can be provided with a pitch twice as wide and with a pitch around three by two (3/2) times wider as compared to the pitch of the gate wiring 21. Therefore, the gate wiring 21 can be provided with a pitch smaller than each wiring pitch of the upper-side backing wiring 25 and lower-side backing wiring 23, thus a higher degree of integration in the DRAM or reduction of a chip size can be achieved in the same manner as in the first embodiment. Fig. 13 is a layout showing a wiring pattern between memory cells of a DRAM in a sixth embodiment. As shown in Fig. 13, the sixth embodiment is realized by providing the lines of gate wiring 21, in the first embodiment, in a staggered arrangement for every two lines, also distributing second contacts 28 on four columns between the memory cell 20 and memory cell 20B, and arranging the contacts on columns by successively shifting from a column to the next. The other elements of the configuration are the same as those in the first embodiment, therefore the same reference numerals are assigned to the elements corresponding to those in the first embodiment and description thereof is omitted herein. According to the sixth embodiment, the upper-side backing wiring 25 and the lower-side backing wiring 23 can be provided with a pitch around eight by five (8/5) times wider as compared to the pitch of the gate wiring 21. Therefore, the gate wiring 21 can be provided with a pitch smaller than each wiring pitch of the upper-side backing wiring 25 and lower-side backing wiring 23, thus a higher degree of integration in the DRAM or reduction of a chip size can be achieved in the same manner as in the first embodiment. Fig. 14 and Fig. 15 are layouts each showing a wiring pattern between memory cells of a DRAM in a seventh embodiment. As shown in Fig. 14, the seventh embodiment is different from the first embodiment in that a pair of lines of lower-side backing wiring 23 are provided so as to sandwich a pair of second contacts 28 therebetween in place of the lower-side backing wiring 23 passing through between the second contacts 28 which are distributed and arranged on two columns between the memory cell 20 and memory cell 20B. The other elements of the configuration are the same as those in the first embodiment, therefore the same reference numerals are assigned to the elements corresponding to those in the first embodiment and description thereof is omitted herein. Of the second contacts 28 adjacent to each other, second contacts 28 not in a pair may be arranged on two different lines extending in the vertical direction with respect to the direction to which the gate wiring 21 extends (lateral direction in the figure) as shown in Fig. 14, and also may not be arranged on two different lines as shown in Fig. 15. According to the seventh embodiment, the upper-side backing wiring 25 and the lower-side backing wiring 23 can be provided with a pitch around four by three (4/3) times wider as compared to the pitch of the gate wiring 21. Therefore, in addition to such an effect that a higher degree of integration in the DRAM or reduction of a chip size can be achieved like in the first embodiment, there is another effect that the width of the second contacts 28 can be made smaller as compared to that in the first embodiment because the lower-side backing wiring 23 is not provided between the second contacts 28. Fig. 16 is a layout showing a wiring pattern between memory cells of a DRAM in an eighth embodiment. As shown in Fig. 16, the eighth embodiment is different from the first embodiment in that a pair of lines of lower-side backing wiring 23 are provided so as to sandwich a pair of second contacts 28 therebetween like in the seventh embodiment. In addition, the lines of gate wiring 21 are provided in a staggered arrangement for every two lines. The other elements of the configuration are the same as those in the first embodiment, therefore the same reference numerals are assigned to the elements corresponding to those in the first embodiment and description thereof is omitted herein. According to the eighth embodiment, the upper-side backing wiring 25 and the lower-side backing wiring 23 can be provided with a pitch around four by three (4/3) times wider as compared to the pitch of the gate wiring 21. Therefore, in addition to such the effect that a higher degree of integration in the DRAM or reduction of a chip size can be achieved like in the first embodiment, there is another effect that the width of the second contacts 28 can be made smaller as compared to that in the first embodiment because the lower-side backing wiring 23 is not provided between the second contacts 28. The present invention as described above is applicable to backing wiring for a bit line of a DRAM and also applicable to backing wiring for a signal line of any semiconductor integrated circuit device other than the DRAM. In the third to eighth Embodiments, the gate wiring 21 and the upper-side backing wiring 25 may electrically be connected to each other directly by the second contacts 28 in the same manner as in the second embodiment. As described above, with the present invention, even when a line width of a signal line in a contact for electrically connecting a signal line to an upper-side auxiliary wired layer is widened, a pitch of a lower-side auxiliary signal line does not need to be widened. Therefore, each wiring pitch of the upper and lower auxiliary signal lines can be made narrower. This allows a higher degree of integration of a semiconductor integrated circuit device or reduction of a chip size to be achieved.

Claims: A semiconductor integrated circuit device comprising: a signal line (21); a first auxiliary signal line (23) formed on a wired layer provided on a layer upper than said signal line via an insulation layer (22); a second auxiliary signal line (25) formed on a wired layer provided on a layer upper than said first auxiliary signal line via an insulation layer (24); first contacts (27) for electrically connecting said signal line to said first auxiliary signal line; and second contacts (28) for electrically connecting said signal line to said second auxiliary signal line, wherein said second contacts (28) are distributed and arranged on two or more different lines extending in a substantially orthogonal direction with respect to a substantial direction to which the said signal line (21) extends, and a pair of said second contacts (28) adjacent to each other are arranged on different lines, and said first auxiliary signal line (25) is formed into a bent pattern so as to pass through between said pair of second contacts (28) adjacent to each other, characterised in that a first bent pattern of the first auxiliary signal line (25) and a second bent pattern of the first auxiliary signal line (25) which sandwich a second contact (28) are symmetric with respect to a line which includes the second contact (28) and extends to the substantial direction in which said signal line (21) extends. The semiconductor integrated circuit device according to Claim 1; wherein each of said second contacts (28) comprises a conductive island (32) formed on the same wired layer as that of said first auxiliary signal line (23); a first auxiliary contact (31) for electrically connecting said signal line (21) to said island (32); and a second auxiliary contact (33) for electrically connecting said island (32) to said second auxiliary signal line (25), and said first auxiliary contact (31) and said second auxiliary contact (33) are arranged on the same line. The semiconductor integrated circuit device according to Claim 1 or Claim 2; wherein each of said second contacts (28) comprises a conductive island (32) formed on the same wired layer as that of said first auxiliary signal line (23); a first auxiliary contact (31) for electrically connecting said signal line (21) to said island (32); and a second auxiliary contact (33) for electrically connecting said island (32) to said second auxiliary signal line (25), and said first auxiliary contact (31) and said second auxiliary contact (33) are arranged by being displaced from each other on two different stages. The semiconductor integrated circuit device according to any of claims 1 to 3; wherein each of said second contacts (28) directly and electrically connects said signal line (21) to said second auxiliary signal line (25). The semiconductor integrated circuit device according to any of Claims 1 to 4; wherein said first contacts (27) and said second contacts (28) are provided alternately for every one unit or every two units for a plurality of signal lines (21). The semiconductor integrated circuit device according to any of Claims 1 to 5; wherein said signal line (21) is a word line or a bit line of a semiconductor storage device. A semiconductor integrated circuit device comprising: a signal line (21); a first auxiliary signal line (23) formed on a wired layer provided on a layer upper than said signal line via an insulation layer (24); a second auxiliary signal line (25) formed on a wired layer provided on a layer upper than said first auxiliary signal line via an insulation layer (24); first contacts (27) for electrically connecting said signal line to said first auxiliary signal line; and second contacts (28) for electrically connecting said signal line to said second auxiliary signal line; said second contacts (28) are distributed and arranged on two or more different lines extending in a substantially orthogonal direction with respect to a substantial direction to which said signal line (21) extends, pairs of said second contacts (28) adjacent to each other are arranged on different lines 25 between pairs of said first auxiliary signal lines (23) adjacent to each other, characterised in that said first (23) and second auxiliary lines (25) extend in said substantial direction in which said signal line (21) extends. The semiconductor integrated circuit device according to claim 7, wherein the first auxiliary signal line has a small bent pattern in a substantially orthogonal direction with respect to the substantial direction in which the signal line extends. The semiconductor integrated circuit device according to Claim 7 or 8; wherein each of said second contacts (28) comprises a conductive island (32) formed on the same wired layer as that of said first auxiliary signal line (23); a first auxiliary contact (31) for electrically connecting said signal line to said island; and a second auxiliary contact (33) for electrically connecting said island to said second auxiliary signal line, and said first auxiliary contact and said second auxiliary contact are arranged on the same line. The semiconductor integrated circuit device according to Claim 7 or Claim 8; wherein each of said second contacts (28) comprises a conductive island (32) formed on the same wired layer as that of said first auxiliary signal line; a first auxiliary contact for electrically connecting said signal line to said island; and a second auxiliary contact for electrically connecting said island to said second auxiliary signal line, and said first auxiliary contact and said second auxiliary contact are arranged by being displaced from each other on two different stages. The semiconductor integrated circuit device according to any of Claims 7 to 10; wherein each of said second contacts (28) directly and electrically connects said signal line (21) to said second auxiliary signal line (25). The semiconductor integrated circuit device according to any of Claims 7 to 11; wherein said first contacts (27) and said second contacts (28) are provided alternately for every one unit or every two units for a plurality of signal lines. The semiconductor integrated circuit device according to any of Claims 7 to 12; wherein said signal line is a word line or a bit line of a semiconductor storage device.

Inventors: HIGUCHI TSUYOSHI, HIGUCHI, TSUYOSHI, Higuchi, Tsuyoshi, c/o Fujitsu Limited
Applicants: FUJITSU LTD, FUJITSU LIMITED
Application year: 2000
Main classification: H01L27
IPC codes: H01L23, H01L27, H01L21