LOW TURN-ON VOLTAGE InP SCHOTTKY DEVICE AND METHOD FOR MAKING THE SAME

Abstract: A Schottky diode, and a method of making the same, which is fabricated on InP material (1) and employs a Schottky layer (9) including InxAll-xAs with x > 0.6, or else including a chirped graded superlattice in which successive periods of the superlattice contain progressively less GaInAs and progressively more A1InAs, the increase in A1InAs being terminated before the proportion of A1InAs within the last period (adjacent the anode metal) exceeds 80 %. Such fabrication creates an InP-based Schottky diode having a low turn-on voltage which may be predictably set within a range by adjusting the fabrication parameters.

Description: LOW TURN-ON VOLTAGE InP SCHOTTKY DEVICE AND METHOD FOR MAKING THE SAME FIELD OF THE INVENTION The present invention pertains to Schottky diodes, and more particularly to Schottky diodes fabricated using InP semiconductor material. BACKGROUND Schottky diodes are well-known in GaAs and Si technologies. Some Si-based Schottky diodes have fairly low turn-on voltages but suffer from high series resistance and relatively poor frequency response. Si-based Schottky diodes are not easily integrated into InP-based semiconductor fabrication. Low turn-on voltages are often desirable for Schottky diodes, particularly for mixer applications. U.S. Patent No. 5,665,999 issued September 9, 1997 to H. Brugger, teaches that low turn-on voltage Schottky diodes permit a low conversion loss without requiring a high pumping capacity in the local oscillator, and without using a bias voltage which may lead to Townsend current-hum disturbances. A GaAs Schottky device with reduced turn-on voltage is taught as fabricated using a graded In^Ga,,.^ As layer over a GaAs substrate, where the In content, x, increases continuously in the direction of the metal contact. Compatibility with InP is not taught, and the spatially varying lattice mismatch created by this process is thought potentially unreliable with InP technologies. Schottky diodes compatible with InP semiconductor technology are known. For example, U.S. Patent No. 5,652,435, issued July 29, 1997 to E. Martin et al., describes a Schottky diode optical detector wherein the light-sensitive InGaAs layer is cladded front and back with InAlAs current-blocking layers. This device has a relatively high turn-on voltage similar to that of conventional GaAs Schottky diodes. Some investigation into the relationship between Schottky barrier height and the proportion of In in In^A-l^As material on an InP substrate has been undertaken by C.L. Lin, et al. in "Composition dependence of Au/In χ Al ] _ χ As Schottky barrier heights/' Applied Physics Letters 49 (23), 8 December 1986, pp. 1593-1595. Lin performs tests on the noted compound for .45 < x < .55, a range producing relatively high Schottky barriers. InP-compatible Schottky diodes using a graded superlattice Schottky layer are also known. For example, U.S. Patent No. 5,198,682 issued March 30, 1993 to C.-S. Wu et al. describes an infrared photodetector using a superlattice having a graded dopant concentration, thereby developing an internal field which aids in the collection of photoexcited carriers. Lee et al., in Appl. Phys. Lett. Vol. 54, May 1989, pp. 1863-1865, teaches use of a graded superlattice of InGaAs/InAlAs to obtain enhanced Schottky barrier height. U.S. Patent No. 5,572,043, issued November 5, 1996 to Shimizu et al. describes another SL-based Schottky diode, using sublayers of variously lattice-mismatched compounds and alternating compressively and tensilely strained layers to balance the mismatches. Each of these three references describe Schottky diodes having a relatively high turn-on voltage of ~.6V - .7V. InP-compatible Schottky diodes having high turn-on voltages are known. For example, U.S. Patent No. 4,471,367 issued September 11, 1984 to C. Chen et al. discloses a MESFET- gate Schottky structure composed of a thin, heavily doped InGaAs layer overlying a layer of low-doped InGaAs having an increased barrier height. Another example is U.S. Patent No. 4,954,851, issued September 4, 1990 to W. Chan, which describes a Schottky diode with a cadmium-containing layer overlying an InAlAs layer. The Cd-containing layer enhances the barrier height of the diode. Thus, Schottky diodes with reduced turn-on voltages exist but are not known to be compatible with InP-based fabrication techniques. Schottky diodes compatible with InP are known, but all have conventional or high turn-on voltages. Yet, InP-based fabrication technologies are desirable, and low turn-on voltage Schottky diodes are particularly useful in certain applications, such as high-frequency mixers. A need therefore exists for low turn-on voltage Schottky diodes, and a method of making the same, which are compatible with InP fabrication technologies. SUMMARY OF THE INVENTION The present invention addresses the need for low turn-on voltage Schottky diodes compatible with InP-based fabrication by employing an InP lattice-compatible Schottky layer which interfaces with the Schottky metal layer and provides a relatively low Schottky barrier height resulting in a low turn-on voltage. The Schottky metal layer is preferably Ti/Pt/Au. The Schottky layer is preferably grown over a low-doped GalnAs layer, which in turn is preferably grown over a highly doped GalnAs layer. The highly-doped GalnAs layer forms the Schottky cathode contact. The cathode contact is grown over a buffer layer, such as 2500A of AHnAs or 100A of undoped GalnAs, preferably grown directly on the InP substrate. According to the present invention, the Schottky layer is processed to produce a low turn-on voltage. According to a first embodiment of the invention, the Schottky layer includes strained AL j Jii j . As, and for x = 0.70 produces a turn-on voltage of J5V @ 1mA. The corresponding J Al content is lower than that which lattice-matches InP, and accordingly the thickness of the layer is preferably around 100 A to limit effects from the strain. According to second, third and fourth embodiments of the invention, the Schottky layer includes a chirped superlattice composed of a plurality of periods, each period containing sublayers of Ga 47 In 53 As and Al 48 In 52 As, which are lattice-matched to InP. The proportional thickness of the two compounds is varied from period to period to provide a step-wise, or chirped, grade in composition of the superlattice from GalnAs toward AHnAs. The turn-on voltage can be precisely controlled by truncating the grading steps before completing a transition to predominantly AHnAs. Throughout this patent, GalnAs refers to Ga 0 47 In 0 53 As, and AHnAs refers to Al 0 48 In 0 52 As, unless a different composition is specified. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is the layer structure of a diode according to the present invention after a first etch. Fig. 2 shows the structure of the diode after a second etch step. Fig. 3 shows the structure of the diode after a third etch step. Fig. 4 shows the structure of the diode after passivation and etching of the passivation layer. Fig. 5 shows the structure of the completed diode. Fig. 6 depicts a chirped graded superlattice having nine periods. Fig. 7 depicts the Schottky layer structure for the second embodiment of the present invention. Fig. 8 depicts the Schottky layer structure for the third embodiment of the present invention. Fig. 9 depicts the Schottky layer structure for the fourth embodiment of the present invention. Fig. 10 shows I-V curves for three embodiments of the present invention. DESCRIPTION OF THE PREFERRED EMBODIMENTS While discrete Schottky diodes can be made according to the present invention, the present invention is very well suited to integrated fabrication. Such fabrication, as shown in Fig. 1, preferably uses Molecular Beam Epitaxy (MBE) to grow each of the layers on InP substrate 1, though any other compatible process, such as Metal Organic Vapor Phase Epitaxy(MOVPE), may be used. Buffer layer 3 is grown directly on InP substrate 1. Buffer layer 3 is about 2500 A of undoped AHnAs, or may alternatively be about 100 A of undoped GalnAs. Cathode contact layer 5 is grown on the buffer layer, preferably highly doped, preferably with Si, to n = 1 x 10 19 cm -3 . Cathode contact layer 5 is preferably grown to about 3000 A of GalnAs, the thickness helping to reduce bulk resistance of the cathode and also simplifying the later etch step down to cathode contact layer 5 which permits deposition of cathode contact 21 (Fig. 2). Depletion layer 7 is about 1000 A of undoped GalnAs grown atop cathode contact layer, and helps to minimize the diode capacitance by increasing the depletion width of the diode. Schottky layer 9 is grown next. In a first embodiment of the invention the Schottky layer is undoped, strained Al ] χ In χ As, preferably A1 Q 3 In 0 7 As. In this first embodiment, Schottky layer 9 is preferably grown to about 100 A thick to reduce crystal anomalies due to the strain from the lattice mismatch. Schottky layer 9 is described further below in accordance with second, third and fourth alternative embodiments of the invention. After Schottky layer 9, a cap layer of about 50 A of undoped GalnAs (not shown) is grown to protect AllnAs in the Schottky layer from ambient oxygen. Fig. 1 shows the device after the first etch step has removed the cap, and Schottky metal layer 10 has been deposited by any standard technique. Schottky metal layer 10 is preferably about 250 A Ti, 1000 A Pt, and 6000 A Au. An etch step, preferably using Schottky metal 10 as an etch stop, mesa etches Schottky layer 9 and depletion layer 7 to expose cathode contact layer 5 as shown in Fig. 2. Due to the thickness of cathode contact layer 5, a timed wet etch may be used, or any compatible etch process. Next, cathode ohmic contact 21 is deposited on cathode contact layer 5, preferably with 900 A AuGe, 100 A Ni, and 2000 A Au. Fig. 3 shows the result of the next two steps. Cathode contact layer 5 and depletion layer 3 are both mesa-etched using any compatible etch technique, to isolate the diode structure on substrate 1. Thereafter, first level interconnect metal 31 is deposited, using any compatible metal, to provide means for connecting external circuits to the device. Fig. 4 shows the device after the step of adding passivation layer 41 of preferably silicon nitride, and after the subsequent step of etching passivation layer 41 to expose Schottky metal 10 and first layer metallization 31. Fig. 5 shows airbridge 51 placed to connect Schottky anode metal 10 to first layer metallization 31. Airbridge 51 is preferred for high frequency applications, as it reduces diode capacitance. In many applications, the anode may be connected by other well-known metallization techniques. Fig. 6 shows the layer structure of a superlattice composed of nine periods 61-69 which are each compound of first sublayer 60 and second sublayer 70. Such a superlattice may be used to grade a material in a stepwise or "chirped" fashion, from predominantly the material of second sublayer 70 in first period 61, to predominantly the material of first sublayer 60. Between successive periods, the thickness of first sublayer 60 is increased, while the thickness of second sublayer 70 is correspondingly decreased. For convenience, first sublayer 60 is about 10% of the thickness of first period 61 of a nine-period chirped graded superlattice, increasing linearly to 90% of the thickness of ninth period 69; while second sublayer 70 is about 90% of the thickness of first period 61, reducing to about 10% of the thickness of ninth period 69. Fig. 7 shows Schottky layer 9 according to a second embodiment of the present invention. For convenience, periods 71-77 are each about 33 A thick. First sublayers 78 are AllnAs, and second sublayers 79 are GalnAs, both lattice-matched to InP. In first period 71, first sublayer 78 is about 3J A thick; subsequent sublayers 78 increase by about 3J A in each successive period so that in seventh period 77, first sublayer 78 is about 23 J A thick. Second sublayer 79 decreases by about 3.3 A per period from about 29.7 A in first period 71 to about 9.9 A in seventh period 77. Thus, Fig. 7 shows a chirped graded superlattice based on a nine- period grading transition, but truncated at seven periods. A Schottky diode fabricated according to this embodiment results in a room-temperature turn-on voltage of about .37V at 1 mA. I-V curve 700 of Fig. 10 is for this embodiment of the invention. Fig. 8 shows the layer structure of Schottky layer 9 according to a third embodiment of the present invention. This embodiment is also based on a nine-period superlattice grading arrangement, but is truncated at 5 layers instead of at 7. First sublayer 88 of first period 81 is about 3J A of AllnAs, increasing by about 3.3 A in successive periods 82, 83, 84 and 85 so that in fifth period 85 it is about 16.5 A. Second sublayer 89 is GalnAs, and is about 29.7 A in first period 81, decreasing to about 16.5 A in fifth period 85. A Schottky diode fabricated according to this embodiment results in a room-temperature turn-on voltage of about .25 V at 1 mA. I-V curve 800 of Fig. 10 is for this embodiment of the invention. Fig. 9 shows the layer structure of Schottky layer 9 according to a fourth embodiment of the present invention. This embodiment is also based on a nine-period superlattice grading arrangement, but is truncated at 3 layers instead of at 5 or 7. First sublayer 98 of first period 91 is about 3.3 A of AllnAs, increasing by about 3.3 A in successive periods 92 and 93 so that in third period 93 it is about 10 A. Second sublayer 99 is GalnAs, and is about 29.7 A in first period 91, decreasing to about 23 A in third period 93. A Schottky diode fabricated according to this embodiment results in a room-temperature turn-on voltage of about J5V at 1 mA. I-V curve 900 of Fig. 10 is for this embodiment of the invention. Fig. 10 shows an I-V curve for each of three described embodiments. Curve 700 is the I-V curve for the embodiment of Fig. 7, curve 800 for the embodiment of Fig. 8 (below), and curve 900 for the embodiment of Fig. 9 (below). For sufficiently thin periods, the effective bandgap tracks the average composition of the superlattice. Since the superlattice of the second, third and fourth embodiments of the invention is chirped, the Schottky barrier height changes discontinuously from period to period. Small chirped grading steps produce smaller Schottky barrier height discontinuities, and hence are thought to help reduce carrier pile-up which may occur on Schottky barrier height discontinuities. Since such pile-up may reduce speed, smaller grading steps may thus enhance speed. Accordingly, the present invention could be practiced with a superlattice truncated partway through a GalnAs to AllnAs grading arrangement which requires more than nine periods to complete, and correspondingly has smaller steps from period to period. Embodiments of the present invention have been described which truncate a nine-period grading arrangement at three, five and seven periods. Truncating at different numbers of periods permits close control of the turn-on voltage of Schottky diodes fabricated according to the present invention. If truncation is based upon grading arrangements requiring more than nine periods to completion, the on-voltage step size between different truncation points is correspondingly reduced, enhancing the fineness of fabrication control of that parameter. Periods of different, and indeed varying, thickness are within contemplation of the present invention. The composition of sublayers need not change in equal-sized steps between successive periods. Periods may have sublayers of alternative materials, and may have additional materials added. Fabrication details are merely exemplary; the invention is defined by the following claims.

Claims: CLAIMS What is claimed is: 1. A Schottky diode comprising a cathode contact layer and a semiconductor Schottky layer adjacent a Schottky anode metallization, wherein said Schottky layer is a superlattice having a plurality of layer periods from a first layer period nearest the cathode contact layer to a last layer period nearest the anode metallization, each layer period having a thickness and including a first sublayer of GalnAs having a thickness and a second sublayer of AllnAs having a thickness, and each layer period having a proportion of GalnAs to AllnAs; the thickness of the first and second sublayers is varied between adjacent layer periods such that the proportion of GalnAs to AllnAs varies stepwise between adjacent layer periods; and the thickness of AllnAs in said last layer period is less than 80% of the thickness of said last layer period. 2. A Schottky diode according to claim 1 , wherein each layer period is composed of said first and second sublayers, and said first and second sublayers are lattice -matched to InP. 3. A Schottky diode according to either claim 1 or claim 2, wherein the thicknesses of successive first sublayers is varied conversely to thicknesses of successive second sublayers so as to vary the proportions of GalnAs to AllnAs by a similar amount between each successive adjacent layer period from the first layer period to the last layer period. 4. A Schottky diode according to any of the above claims wherein the Schottky anode metallization of the device is connected via an airbridge to metallization interconnected to external circuitry. 5. A Schottky diode according to any of the above claims, wherein within the first layer period the first sublayer thickness is about 10% of the first layer period thickness and the second sublayer thickness is about 90% of the first layer period thickness, and within the last layer period the first sublayer thickness is about 30% of a last layer period thickness and the second sublayer thickness is about 70% of the last layer period thickness. 6. A Schottky diode according to any of claims 1 to 4, wherein within the first layer period the first sublayer thickness is about 10% of a first layer period thickness and the second sublayer thickness is about 90% of the first layer period thickness, and within the last layer period the first sublayer thickness is about 50% of the last layer period thickness. 7. A Schottky diode according to any of claims 1 to 4, wherein within the first layer period the first sublayer thickness is about 10% of the first layer period thickness and the second sublayer thickness is about 90% of the first layer period thickness, and within the last layer period the first sublayer thickness is about 70% of a last layer period thickness and the second sublayer thickness is about 30% of the last layer period thickness. 8. A Schottky diode according to any of the above claims, wherein layer periods are composed of sublayers of GalnAs lattice-matched to InP and AllnAs lattice-matched to InP. 9. A Schottky diode comprising: an InP substrate; a Schottky anode metallization; and a semiconductor Schottky layer adjacent the Schottky anode metallization, wherein said Schottky layer is predominantly In^Al j ^As with x greater than 0.6. 10. A Schottky diode according to claim 9, wherein said Schottky anode metallization device is connected through an airbridge to metallization for interconnection to external circuitry. 11. A Schottky diode according to either claim 9 or claim 10, wherein x is about 0.7. 12. A method of making a Schottky diode comprising steps of: preparing an InP substrate; establishing a doped cathode contact layer of GalnAs above the substrate; establishing a semiconductor Schottky layer above the cathode contact layer, the Schottky layer being either: (a) a truncated chirped superlattice of GalnAs and AlIAs, or (b) predominantly In-Al^As with x greater than 0.6; and depositing a metal anode contact of the Schottky layer. 13. The method of claim 12, wherein the GalnAs and the AllnAs are lattice-matched to InP. 14. The method of either claim 12 or claim 13, wherein the Schottky layer is a truncated chirped superlattice, and the step of growing the Schottky layer includes the steps of: growing a plurality of layer periods including a first layer period nearest the cathode contact layer and a last layer period nearest the metal anode contact, each layer period having a thickness, and each layer period including as constituents a first sublayer of AllnAs having a thickness and a second sublayer of GalnAs having a thickness, the AllnAs in each layer period being a proportion of a total of material composing that layer period; and truncating growth of further layer periods such that a proportion of AllnAs in the last layer period grown does not exceed 80% of the total material of the last layer period; wherein the thicknesses of the first sublayers of each layer period are varied for successive layer periods and the thicknesses of the second sublayers of each layer period are varied for successive layer periods to stepwise change the proportion of AllnAs to the total material of successive layer periods. 15. The method of claim 14, wherein the first sublayer of each layer period is grown with increasing thickness in each successive layer period; and the second sublayer of each layer period is grown with decreasing thickness in each successive layer period; such that the proportion of AllnAs increases stepwise for each successive layer period. 16. The method of claim 15 wherein the stepwise increase in the proportion of AllnAs is approximately uniform for each successive layer period. 17. The method of any of claims 14 to 16, wherein AllnAs does not exceed 60% of total material of the last layer period. 18. The method of any of claims 14 to 17, wherein the number of layer periods is five. 19. The method of any of claims 14 to 18, wherein the superlattice is composed of AllnAs lattice-matched to InP and GalnAs lattice-matched to InP, and the proportion of AllnAs of the last layer period is between 30% and 70% of the total material of the last layer period. 20. The method of any of claims 14 to 19 wherein the proportion of AllnAs in the last layer period is about 50% of the total material of the last layer period.

Inventors: LUI MARK, SCHMITZ ADELE E, WALDEN ROBERT H, YU MARK K, LUI, MARK, SCHMITZ, ADELE, E., WALDEN, ROBERT, H., YU, MARK, K.
Applicants: HRL LAB LLC, LUI MARK, SCHMITZ ADELE E, WALDEN ROBERT H, YU MARK K, HRL LABORATORIES, LLC., LUI, MARK, SCHMITZ, ADELE, E., WALDEN, ROBERT, H., YU, MARK, K.
Application year: 2000
Main classification: H01L29
IPC codes: H01L29