DIGITAL DATA TRANSMISSION VIA MULTI-VALUED LOGIC SIGNALS

Abstract: A digital communication system is presented including at least one transmission line coupled between a first and second communication devices and used to convey binary data from the first communication device to the second communication device. A termination resistor and one end of the transmission line are coupled to an input node of the second communication device. An electrical voltage level existing at the input node of the second communication device may be substantially dependent upon an amount of electrical current flowing through the termination resistor. The termination resistor may have a value substantially equal to a characteristic impedance of the transmission line such that signal reflections and distortion occurring within the transmission line are substantially reduced. Three or more different voltage levels may be present upon the transmission line dependent upon the binary data. The resulting increase in data transmission capability may be used to reduce the total number of transmission lines coupled between the first and second communication devices, or to increase the rate at which the binary data is transmitted from the first communication device to the second communication device. The ternary signals may also be used to encode a clock signal with binary data upon one or more transmission lines such that a separate clock transmission line is not needed, and clock signal reception is ensured even in case of transmission line failure.

Description: TITLE: DIGITAL DATA TRANSMISSION VTA MULTI-VALUED LOGIC SIGNALS BACKGROUND OF THE INVENTION 1 Field of the Invention This invention relates to digital communication systems, and more particularly to unidirectional source- synchronous digital data transmission systems. 2. Description of the Relevant Art Digital electronic devices typically communicate via electrical signals (e.g., voltages and/or currents) driven upon electrical conductors (e.g., metal wires). Operations within a digital electronic device transmitting data (i.e., a "sender") may be performed in response to (i.e., synchronized) by a first clock signal, and operations withm another digital electronic device receiving the data (i.e , a "receiver") may be synchronized by a second clock signal. In order for the receiver to receive the data correctly and efficiently, the first and second clocks may need to be synchronized such data reception by the receiver occurs in unison with data transmission by the sender Fig. 1 is a diagram of a digital communication system 10 employing source-synchronous data transmission. A sender 12 is coupled to a receiver 14 via n data transmission lines 16 and a clock transmission line 18. Sender 12 includes n drivers 20 for driving one end of the n data transmission lines 16 according to binary data signals DATA1 through DATA/t, and a driver 22 for driving one end of clock transmission line 18 according to a binary clock signal CLOCK. Sender 12 drives one of two voltage levels upon each of the n data transmission lmes 16 dependent upon the logic value of the corresponding binary data signal. Similarly, sender 12 drives one of two voltage levels upon clock transmission line 18 dependent upon the logic value of clock signal CLOCK. Further, sender 12 drives data transmission lines 16 in synchronization with clock signal CLOCK (e g., in response to a rising or falling transition or "edge" of CLOCK). Receiver 14 includes n comparators 24 coupled to receive the voltage levels driven upon the n data transmission lines 16 by sender 12, and a comparator 26 coupled to receive the voltage levels driven upon clock transmission line 18 by sender 12 Each of the n comparators 24 and comparator 26 also receive a reference voltage level V ωF , where reference voltage level V REF is selected to be between the two voltage levels. Comparator 26 produces binary clock signal CLOCK at an output terminal. Receiver 14 also includes n flip-flops 28 receiving the outputs of the n comparators 24 at input terminals and clock signal CLOCK signal at control terminals. As a result, the n flip-flops 28 produce corresponding data signals DATA1 through DATAH in response to the CLOCK signal produced by comparator 26 As the operating frequencies (l e., "speeds") of digital electronic devices increase, electrical conductors used to route signals between components (i.e., signal lines) begin to behave like transmission lines. Transmission lines have characteristic impedances If the input impedance of a receiving device connected to a transmission line does not match the characteristic impedance of the transmission line, a portion of an incoming signal is reflected back toward a sending device. Such reflections cause the received signal to be distorted. If the distortion is great enough, the receiving device may erroneously interpret the logical value of the incoming signal. Bmary digital signals typically have a low voltage level associated with a logic low (1 e., a logic "0"), a high voltage level associated with a logic high (i.e., a logic "1"), "rise times" associated with transitions from the low voltage level to the high voltage level, and "fall times" associated with transitions from the high voltage level to the low voltage level. A signal lme behaves like a transmission line when the signal rise time (or signal fall tune) is short with respect to the amount of time required for the signal to travel the length of the signal line (i.e., the propagation delay time of the signal line). As a general rule, a signal line begins to behave like a transmission line when the propagation delay time of the signal line is greater than about one-quarter of the signal rise time (or signal fall time). Resistive "termination" techniques are often applied to transmission lines, and signal lines long enough to behave like transmission lines, in order to reduce reflections and the resultant signal distortion One or more electrically resistive elements (e.g., resistors) may be inserted between a driver and an end of a transmission line in order to cause the effective output impedance of the driver to more closely match the characteristic impedance of the transmission line. Similarly, one or more electrically resistive elements may be coupled to an end of a transmission line at a receiver in order to cause the effective input impedance of the receiver to more closely match the characteristic impedance of the transmission l e. Fig. 2 is a diagram of a representative transmission line 30 coupled between sender 12 and receiver 14, wherein resistive terminations are employed in order to reduce signal reflections and distortion within transmission line 30. Transmission line 30 may be one of the n data transmission lines 16 or clock transmission lme 18. Switchmg circuitry 32 withm a dnver of sender 12 switches a first end of transmission lme 30 between a first power supply voltage level V DD and a second power supply voltage level V ss dependent upon a bmary input signal (i.e., a binary data signal or binary clock signal CLOCK). It is noted that second power supply voltage level V ss may be a reference ground electrical potential, and V DD may be referenced to V ss . A first termination resistor 34, having a value equal to the characteristic impedance Z 0 of transmission line 30, is connected between switchmg circuitry 32 and the first end of transmission line 30 m order to reduce signal reflections and distortion withm transmission line 30. A second end of transmission line 30 is connected a first input terminal of a comparator 36 withm receiver 14. A second termination resistor 38, having a value equal to the characteristic impedance Z 0 of transmission line 30, is connected between the first input terminal of comparator 36 and power supply voltage level V DD in order to reduce signal reflections and distortion within transmission line 30 When first termination resistor 34 and second termination resistor 38 are coupled to opposite ends of transmission line 30 m order to reduce signal reflections and distortion, they form a voltage divider network which restricts the range of voltage levels which may be used to convey binary signals from sender 12 to receiver 14 Fig. 3 is a graph of voltage levels V present within sender 12 and upon transmission 30 of Fig. 2. When switching circuitry 32 connects the first end of transmission lme 30 to V DD through first termmation resistor 34, a voltage level equal to V DD exists at the first end transmission lme 30 When switchmg circuitry 32 connects the first end of transmission line 30 to V ss through first termmation resistor 34, first termmation resistor 34 and second termmation resistor 38 are connected in series between V DD and V ss , and a voltage level equal to (V DD /2) exists at the first end transmission lme 30 (where V DD is referenced to V ss ). As a result, the two voltage levels used to convey binary signals from sender 12 to receiver 14, V DD and (V DD /2), exist only in an upper half of the voltage range between V DD and V ss as shown m Fig. 3. It is noted that a lower half of the voltage range between V DD and V ss is unused due to the use of both first termmation resistor 34 and second termmation resistor 38. Reference voltage level V ω „ connected to a second input terminal of comparator 36 withm receiver 14, is selected between the two voltage levels V DD and (V DD 2) as descπbed above Voltage values between (V DD /2) and received at the first mput terminal of comparator 36 may cause comparator 36 to produce a bmary logic 0 signal at an output terminal, and voltage values between V^ and V DD received at the first mput terminal of comparator 36 may cause comparator 36 to produce a binary logic 1 signal at the output terminal. It would be beneficial to have a data transmission system which employs resistive termmation of at least one transmission lme coupled between a sender and a receiver, and wherem the at least one transmission lme is capable of conveying one of k logic states, where k > 2. Such increased data transmission capability could be used to reduce a total number of transmission lines coupled between the sender and the receiver, or to increase the rate at which binary data is transmitted from the sender to the receiver via the total number of transmission lmes SUMMARY OF THE INVENTION A digital communication system is presented which includes at least one transmission line coupled between a first communication device and a second communication device. The transmission line is used to convey binary data from the first communication device to the second communication device. At least one termmation resistor, coupled to an end of a transmission line at the second communication device m order to reduce signal reflections and distortion, is also used to generate three or more different voltage levels upon the transmission line dependent upon the bmary data. The resultmg increase m data transmission capability may be used to reduce the total number of transmission lines coupled between the first and second communication devices, or to increase the rate at which the binary data is transmitted from the first communication device to the second communication device. In a first embodiment of the digital communication system, the first communication device has an output node coupled to a first end of a transmission line, and the second communication device has an mput node coupled to a second end of the transmission lme. The second communication device includes a termination resistor coupled between the input node and a power supply voltage level (e.g., V DD ). The second communication device may be configured such that an electrical voltage level existing at the input node is substantially dependent upon an amount of electrical current flowing through the termination resistor. The termination resistor may have a value substantially equal to a characteristic impedance of the transmission line such that signal reflections and distortion occurring within the transmission lme are substantially reduced. The first communication device drives the output node m one of/, drive states, where p ≥ 3. Each of the p drive states causes a different amount of electrical current to flow through the termination resistor such that a different electrical voltage level exists at the input node in each of the p drive states The different electrical voltage levels existing at the input node in each of the p drive states may differ by substantially equal amounts, and may be associated with different logic levels. The three or more logic levels represent an mcrease in data transmission capability over the two logic levels used in bmary data transmission. The first communication device may include an output section receivmg bmary data and driving the output node in one of the p drive states dependent upon the bmary data. The output section may also receive a first clock signal, and may drive the output node m response to the first clock signal. The second communication device may mclude an mput section coupled to the mput node and configured to produce the bmary data from the different electrical voltage levels existing at the input node. The mput section may produce the bmary data m response to a second clock signal. The first and second clock signals may be synchronized in one of several possible ways m order to achieve synchronous data transmission For example, the first communication device may provide the first clock signal to the second communication device via a dedicated clock transmission line. Alternately, the second communication device may generate the second clock signal m synchronization with voltage level transitions present upon the transmission line conveymg data. In a second embodiment of the digital communication system, the second communication device may include two termmation resistors: a first termmation resistor coupled between the input node and the first power supply voltage level (e.g., V DD ), and a second termmation resistor coupled between the mput node and a second power supply voltage level (e.g., V ss ). The second communication device may be configured such that an electπcal voltage level existmg at the input node is substantially dependent upon an amount of electrical current flowing through the first termmation resistor. The first and second termmation resistors may have values substantially equal to twice the characteristic impedance of the transmission line such that the transmission lme is terminated in the characteristic impedance of the transmission line, and signal reflections and distortion occurring withm the transmission line are substantially reduced. The first communication device may include drive circuitry withm the output section. The output section may electrically couple the dπve circuitry to the output node in p dπve states, where p ≥2, and dπve the output node m the p dπve states via the drive circuitry. The output section may not drive the output node m an additional "non-dπve" state. In the non-dπve state, the output section may electπcally decouple the dπve circuitry from the output node. In each of the p dπve states and the non-drive state, a different amount of electrical cuπent may flow through the first termination resistor such that a different electπcal voltage level exists at the input node. The different electrical voltage levels existing at the mput node in each of the p drive states and the non-drive state may differ by substantially equal amounts and may be associated with different logic levels. In the second embodiment, the drive circuitry may drive the output node in one of the p dπve states dependent upon the bmary data and m response to the first clock signal. The output section may also electrically decouple the drive circuitry from the output node m the non-drive state dependent upon the binary data and in response to the first clock signal. As described above, the second communication device may include an input section coupled to the input node and configured to produce the binary data from the different electπcal voltage levels existing at the input node The input section may produce the binary data in response to a second clock signal The first and second clock signals may be synchronized as described above m order to achieve synchronous data transmission In a third embodiment of the digital communication system, the first communication device has m data output nodes and a clock output node. The second communication device has m data input nodes corresponding to the m data output nodes, and a clock input node coπesponding to the clock output node. In the third embodiment, the digital communication system mcludes m data transmission lines coupled between the corresponding m data output nodes and m data input nodes, and a clock transmission lme coupled between the clock output and mput nodes The second communication device mcludes an mput section havmg m+\ termination resistors. Each of m of the termination resistors is coupled between a different one of the m data mput nodes and a power supply voltage level (e.g., V DD ), and the remammg termmation resistor is coupled between the clock mput node and the power supply voltage level. The second communication device may be configured such that: (1) an electπcal voltage level existmg at a given data mput node is substantially dependent upon an amount of electπcal current flowmg through the termmation resistor coupled between the given data mput node and the power supply voltage level, and (π) an electrical voltage level existing at the clock mput node is substantially dependent upon an amount of electπcal current flowing through the termmation resistor coupled between the clock input node and the power supply voltage level. Each termination resistor may have a value substantially equal to a characteπstic impedance of a coπespondmg transmission line such that signal reflections and distortion occurπng withm the correspondmg transmission line are substantially reduced. In the third embodiment, the first communication device includes an output section coupled to receive n binary data signals and a binary clock signal. The output section drives each of the m data output nodes in one of p drive states dependent upon the n binary data signals and in response to the bmary clock signal, where n > m and p > 3. Each of the p drive states used to drive a given data output node causes a different amount of electπcal current to flow through the termination resistor coupled to the correspondmg data mput node such that a different electπcal voltage level exists at the corresponding data input node m each of the p dπve states. The different electπcal voltage levels existmg at the corresponding mput node in each of the p dπve states may differ by substantially equal amounts and may be associated with different logic levels. The output section also drives the clock output node in one of q dπve states dependent upon the bmary clock signal, where q ≥ 2. Each of the q dπve states causes a different amount of electπcal current to flow through the termmation resistor coupled to the clock input node such that a different electπcal voltage level exists at the clock input node in each of the q dπve states. The different electrical voltage levels existing at the clock input node in each of the q dπve states may be associated with different logic levels. The input section is configured to: (I) produce the binary clock signal from the electπcal voltage levels existmg at the clock input node, and (n) produce the « binary data signals from the electrical voltage levels existing at the m data input nodes m response to the binary clock signal. The n binary data signals simultaneously convey one of 2 n logical states. The m data transmission lines having one of p voltage levels present thereupon simultaneously convey one of p m logical states. Thus the minimum value of m for simultaneous conveyance of the one of 2" logical states is the smallest integer greater than or equal to logp(2") For example, n and/? may both equal 3. In this case, log 3 (2 3 ) is approximately 1.89, and the minimum value of m for simultaneous conveyance of one of 2 3 (8) logical states is 2, the smallest integer greater than or equal to 1 89 In a fourth embodiment of the digital communication system, the first communication device agam has m data output nodes and a clock output node, and the second communication device has m data input nodes corresponding to the m data output nodes and a clock input node correspondmg to the clock output node. A total of m data transmission lines are coupled between corresponding data mput and output nodes, and a clock transmission lme is coupled between the clock input node and the clock output node. In the fourth embodiment, the second communication device mcludes an mput section havmg; (1) a first m termination resistors each coupled between a different one of the m data mput nodes and a first power supply voltage level (e.g., V DD ), (n) a second m termmation resistors each coupled between a different one of the m data input nodes and a second power supply voltage level (e.g., V ss ), and (in) a termmation resistor coupled between the clock mput node and the first power supply voltage level. The second communication device may be configured such that: (1) an electπcal voltage level existing at a given data mput node is substantially dependent upon an amount of electπcal current flowmg through the termmation resistor coupled between the given data mput node and the first power supply voltage level, and (n) an electπcal voltage level existmg at the clock mput node is substantially dependent upon an amount of electπcal cuπent flowmg through the termmation resistor coupled between the clock input node and the first power supply voltage level. Each of the two termmation resistors coupled to a given data mput node may have a value substantially equal to twice a characteristic impedance of a data transmission line coupled to the input node such that the data transmission lme is terminated m its characteristic impedance. As a result, signal reflections and distortion occurπng within the m data transmission lines are substantially reduced. As in the third embodiment, the first communication device mcludes an output section coupled to receive n binary data signals and a bmary clock signal In the fourth embodiment, the output section may dπve each of the m data output nodes in one of p dπve states, where n > m and p ≥ 2. The first communication device may include dπve circuitry withm the output section connected to each of the m data output nodes in each of the /7 dπve states dependent upon the bmary data and in response to the first clock signal. The output section may not dπve a given data output node m an additional "non-drive" state. In the non-dπve state, the output section may electrically decouple the dπve circuitry from the given data output node dependent upon the binary data and m response to the first clock signal. In each of the p drive states and the non-dπve state, a different amount of electπcal current may flow through the two termmation resistors coupled to the data input node corresponding to a given data output node such that a different electrical voltage level exists at the data mput node. The different electπcal voltage levels existing at the data input node in each of the p drive states and the non-drive state may differ by substantially equal amounts and may be associated with different logic levels The output section also dπves the clock output node in one of q drive states dependent upon the binary clock signal, where q ≥ 1. When q = 1 , an additional termination resistor may be coupled between the clock input node and the second power supply voltage level, and the output section may electrically decouple dπve circuitry from the clock output node in an additional "non-dπve" state as described above. The values of the one or more termination resistors coupled to the clock input node may be selected such that the mput resistance at the clock input node is substantially equal to the characteristic impedance of the clock transmission lme. In this case, signal reflections and distortion occurring withm the clock transmission line are substantially reduced. Each of the q dπve states causes a different amount of electπcal current to flow through the termmation resistor coupled to the clock input node such that a different electπcal voltage level exists at the clock input node m each of the q dπve states. As in the third embodiment, the input section is configured to: (l) produce the bmary clock signal from the electncal voltage levels existmg at the clock input node, and (π) produce the n bmary data signals from the electrical voltage levels existmg at the m data mput nodes m response to the bmary clock signal. The structures of the first and second embodiments descπbed above may be used to implement a data transmission scheme which facilitates the generation of the second clock signal withm the second communication device and the synchronization of the second clock signal to the first clock signal. A ternary data stream mcludmg ternary data is produced upon the transmission line as descnbed above, wherem a voltage level transition occurs withm the ternary data stream every cycle of the first clock signal. The first communication device may generate the ternary data m a manner which guarantees a voltage level transition upon the transmission lme for every cycle of the first clock signal even when the logic levels of the bmary data remam unchanged from one cycle of the first clock signal to the next. The second communication device may reproduce the binary data from the ternary signals of the ternary data stream received via the transmission line. In a method for implementing the above data transmission scheme, control logic withm an output section of the first communication device may encode the binary data to form the ternary data stream The second communication device may receive the ternary data stream and synchronize the second clock signal to the first clock signal usmg the voltage level transitions occurπng withm the ternary data stream. Circuitry within an mput section of the second communication device may be used to decode the ternary data withm the ternary data stream in response to the second clock signal thereby reproducing the binary data from the ternary data signals. It is noted that the data transmission scheme described above eliminates the need for a separate clock transmission line to convey the first clock signal from the first communication device to the second communication device. It is noted that the ternary signals produced usmg the data transmission scheme may be used to encode the first clock signal with binary data upon multiple transmission lines coupled between the first communication device and the second communication device such that reception of the first clock signal by the second communication device is ensured even m case of transmission lme failure. BRIEF DESCRIPTION OF THE DRAWINGS Other objects and advantages of the invention will become apparent upon reading the following detailed description and upon reference to the accompanying drawings in which Fig. 1 is a diagram of a digital communication system employing source-synchronous data transmission, wherein the communication system includes a sender and a receiver coupled to opposite ends of n data transmission lmes, and wherein n binary data signals are conveyed simultaneously from the sender to the receiver via the n data transmission lines, and wherem the receiver produces the n binary data signals m response to a clock signal conveyed from the sender to the receiver via a dedicated clock transmission lme, Fig. 2 is a diagram of a representative one of the transmission lmes of Fig. 1, wherein resistive terminations are employed at both ends of the representative transmission line in order to reduce signal reflections and distortion, Fig. 3 is a graph of voltage levels present withm the sender and upon the representative transmission lme illustrated in Fig 2, Fig 4 is a diagram of one embodiment of a first digital communication system m accordance with the present mvention, wherem the first digital communication system mcludes a first communication device and a second communication device coupled to opposite ends of a transmission lme; Fig. 5 is a graph of voltage levels present within the first communication device and dπven upon the transmission lme of Fig. 4; Fig. 6 is a diagram of an alternate embodiment of the first digital communication system of Fig. 4, Fig. 7 is a graph of voltage levels present within the first communication device and dnven upon the transmission lme of Fig. 6, Fig. 8 is a diagram of one embodiment of a second digital communication system m accordance with the present mvention; Fig. 9 is a state diagram of an exemplary state machme which may be embodied withm control logic of the first communication device of Fig. 4 or Fig. 6 in order to implement a data transmission scheme which uses ternary data signals to produce a voltage level transition every clock cycle in a data stream conveyed from the first communication device to the second communication device; Fig 10 is a state diagram of an exemplary state machine which may be embodied withm decode logic of the second communication device of Fig. 4 or Fig. 6 in order to implement the data transmission scheme descπbed above with regard to Fig. 9, Fig. 11 is a graph of a clock signal CLOCK 1, a binary data signal DATA, and an output voltage at an output node of the first communication device of Fig 4 or Fig 6 versus time illustrating the data transmission scheme described above with regard to Fig. 9; and Fig. 12 is a graph of an input voltage at an mput node of the second communication device versus tune used to illustrate a method for decodmg ternary data encoded withm the output voltage of Fig. 11. While the invention is susceptible to various modifications and alternative forms, specific embodiments thereof are shown by way of example in the drawings and will herem be descnbed in detail. It should be understood, however, that the drawings and detailed description thereto are not mtended to limit the mvention to the particular form disclosed, but on the contrary, the intention is to cover all modifications, equivalents and alternatives falling withm the spirit and scope of the present invention as defined by the appended claims. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Fig. 4 is a diagram of one embodiment of a digital communication system 40 m accordance with the present invention. Digital communication system 40 includes a first communication device 42a and a second communication device 42b coupled to opposite ends of a transmission lme 44. Communication device 42a drives one of three different voltage levels upon a first end of transmission lme 44 dependent upon multiple binary data signals. Communication device 42b is coupled to a second end of transmission lme 44. Communication device 42b receives the voltage levels driven upon transmission line 44 and reproduces the oπgmal multiple bmary data signals from the voltage levels. Transmission line 44 may be a signal line which behaves like a transmission lme due to the fact that transition times (i.e., signal rise or fall times) between voltage levels driven upon transmission line 44 are short with respect to the propagation delay time of the signal lme as described above. For example, transmission line 44 may be a signal line having a propagation delay time greater than about one-quarter of any transition time between voltage levels. Communication device 42a mcludes an output section 46 coupled to an output node 48. Output node 48 is coupled to the first end of transmission line 44. Output section 46 mcludes control logic 50 and a driver circuit 52. Dπver circuit 52 is coupled between control logic 50 and output node 48. Control logic 50 receives bmary data signals DATA and a bmary clock signal CLOCK1, and produces control signals coupled to dπver circuit 52 dependent upon the bmary data signals DATA and in response to the binary clock signal CLOCK1. In the embodiment of Fig 4, driver circuit 52 mcludes three switchmg elements 54a-c. Each switchmg element 54 includes two switch termmals and a control terminal. Each switchmg element 54 receives a different control signal from control logic 50 at the control termmal, and is either in an open state or a closed state dependent upon the received control signal. In the open state, a given switchmg element 54 offers a relatively high electπcal resistance between the switch termmals. In the closed state, the given switching element 54 offers a relatively low electπcal resistance between the switch termmals. Switchmg elements 54a-c may be, for example, metal oxide semiconductor (MOS) transistors One switch termmal of each switchmg element 54 is coupled to output node 48. The second switch termmal of switching element 54a is coupled to one terminal of a resistor 56a. A second termmal of resistor 56a is coupled to a first power supply voltage level V DD . Switching element 54a connects output node 48 to V DD through resistor 56a in response to the control signal received from control logic 50. The second switch termmals of switchmg elements 54b are coupled to one terminal of respective resistors 56b and 56c, and second termmals of resistors 56b and 56c are coupled to a second power supply voltage level V ss Herembelow, second power supply voltage level will be regarded as a reference ground electπcal potential, and first power supply voltage level V DD is referenced to V ss . Switchmg element 54b connects output node 48 to V ss through resistor 56b in response to the control signal received from control logic 50, and switching element 54c connects output node 48 to V ss through resistor 56c in response to the control signal received from control logic 50. Communication device 42b includes an input section 58 coupled to an input node 60. Input node 60 is coupled to the second end of transmission line 44. Input section 58 includes a termmation circuit 62, two comparators 64a-b, and decode logic 66. Termmation circuit 62 mcludes a termmation resistor 68 havmg a value substantially equal to a characteristic impedance Z 0 of transmission line 44 One terminal of termination resistor 68 is coupled to input node 60, and the other termmal of resistor 68 is coupled to V DD . Comparators 64a-b each have two mput terminals and an output terminal. A first input terminal of comparator 64a is coupled to input node 60, and the second input terminal is coupled to a first reference voltage level A first mput terminal of comparator 64b is coupled to input node 60, and the second mput termmal is coupled to a second reference voltage level V REF2 . The output terminals of comparators 64a-b are coupled to decode logic 66. Decode logic 66 also receives a binary clock signal CLOCK2. Decode logic 66 reproduces bmary data signals DATA usmg binary output signals produced by comparators 64a-b and in response to clock signal CLOCK2. Clock signal CLOCK2 may be generated within input section 58 and synchronized to clock signal CLOCK1, or may be a copy of clock signal CLOCK1 provided to input section 58 by communication device 42a. Driver circuit 52 drives output node 48 m one of three dnve states dependent upon data signals DATA. In each dπve state, one of the switchmg elements 54a-c is in the closed state. In a first drive state, switchmg element 54a is in the closed state, and switchmg elements 54b and 54c are in the open state. Output node 48 is coupled to V DD through switchmg element 54a and resistor 56a. Resistor 56a has a value substantially equal to characteπstic impedance Z 0 of transmission lme 44 In the first drive state, no electπcal current flows through termmation resistor 68, and mput node 60 is at a voltage level of V DD In a second drive state, switchmg element 54b is m the closed state, and switchmg elements 54a and 54c are m the open state Output node 48 is coupled to V ss through switching element 54b and resistor 56b Resistor 56b has a value substantially equal to twice the characteristic impedance Z 0 of transmission line 44 Termmation resistor 68 and resistor 56b are connected in seπes between V DD and V ss , forming a voltage divider network In the second drive state, an electπcal current of about (V DD / 3 Z 0 ) flows through termmation resistor 68, and input node 60 is at a voltage level of approximately (2 V DD /3) In the third drive state, switching element 54c is in the closed state, and switchmg elements 54a and 54b are in the open state Output node 48 is coupled to V ss through switching element 54c and resistor 56c Resistor 56c has a value substantially equal to half the characteristic impedance Z 0 of transmission lme 44 Termination resistor 68 and resistor 56c are connected in series between V DD and V ss , forming a voltage divider network In the third drive state, an electπcal current of about (2 V DD / 3 Z 0 ) flows through termination resistor 68, and input node 60 is at a voltage level of (V DD /3) Fig 5 is a graph of voltage levels V present within communication device 42a and dπven upon transmission line 44 of Fig 4 In the first, second, and third dnve states of dπver circuit 52, respective approximate voltage levels of V DD , (2 V DD /3), and (V DD /3) are dnven upon transmission line 44 by driver circuit 52 as descnbed above The three voltage levels associated with the three drive states are used to convey binary data signals DATA from communication device 42a to communication device 42b A lower third of the voltage range below (V DD 3) is unused First reference voltage level is selected between voltage levels V DD and (2 V DD 3) as indicated in Fig 5 Voltage values less than V REFI received at the first input terminal of comparator 64a may cause comparator 64a to produce a binary logic 0 signal at the output terminal, and voltage values greater then received at the first input termmal of comparator 64a may cause comparator 64a to produce a binary logic 1 signal at the output terminal Second voltage level V REF2 is selected between voltage levels V DD /3 and (2 V DD /3), as indicated m Fig 5 Voltage values less than V REF2 received at the first input terminal of comparator 64b may cause comparator 64b to produce a binary logic 0 signal at the output terminal, and voltage values greater then V^,.-. received at the first input termmal of comparator 64b may cause comparator 64b to produce a binary logic 1 signal at the output termmal The two bmary outputs of comparators 64a-b indicate which of the three voltage levels exists upon transmission line 44 For example, when the first voltage level of V DD is present upon transmission line 44, the outputs of comparators 64a-b may both be a binary logic 1 When the second voltage level of (2 V DD 3) is present upon transmission line 44, the output of comparator 64a may be a bmary logic 0, and the output of comparator 64b may be a binary logic 1 When the third voltage level of (V DD /3) is present upon transmission line 44, the outputs of comparators 64a-b may both be a binary logic 0 As descπbed above, decode logic 66 uses the bmary outputs of comparators 64a-b to reproduce binary data signals DATA The values of three binary data signals DATA convey one of 2 3 (8) logical states Two successive voltage levels driven upon transmission lme 44 carry 3 2 or 9 logical states Thus three binary data signals DATA may be conveyed usmg two successive voltage levels driven upon transmission lme 44. This reduction m the number of voltage levels which must be dnven upon transmission lme 44 m order to convey a certain quantity of information may be used to mcrease the rate at which data is transmitted from communication device 42a to communication device 42b, or to reduce a required number of transmission lmes connected between communication device 42a and 42b while maintaining a given data transmission rate. Fig. 6 is a diagram of an alternate embodiment of digital communication system 40 in accordance with the present invention. In the embodiment of Fig. 6, output section 46 of first communication device 42a includes a dπver section 70 coupled between control logic 50 and output node 48, and mput section 58 of second communication device 42b mcludes a termination circuit 72 coupled between mput node 60 and comparators 64a- b Dπver circuit 70 includes two switchmg elements 74a-b. Each switchmg element 74 mcludes two switch terminals and a control termmal Each switching element 74 receives a different control signal from control logic 50 at the control termmal, and is either in an open state or a closed state dependent upon the received control signal In the open state, a given switchmg element 74 offers a relatively high electπcal resistance between the switch termmals. In the closed state, the given switching element 74 offers a relatively low electπcal resistance between the switch terminals. Switching elements 74a-b may be, for example, metal oxide semiconductor (MOS) transistors One switch termmal of each switching element 74 is coupled to output node 48. The second switch termmal of switchmg element 74a is coupled to one terminal of a resistor 76a. A second termmal of resistor 76a is coupled to first power supply voltage level V DD . Switchmg element 74a connects output node 48 to V DD through resistor 76a m response to the control signal received from control logic 50. The second switch termmal of switchmg element 74b is coupled to one termmal of a resistor 76b, and the second terminal of resistor 76b is coupled to second power supply voltage level V ss Switchmg element 74b connects output node 48 to V ss through resistor 76b in response to the control signal received from control logic 50 Termmation circuit 72 includes two termination resistors a first termmation resistor 78a and a second termmation resistor 78b, each having a value substantially equal to twice the characteπstic impedance Z 0 of transmission line 44 One terminal of first and second termination resistors 78a-b are coupled to input node 60 A second terminal of termination resistor 78a is coupled to V DD , and a second termmal of termination resistor 78b is coupled to V ss Driver circuit 70 drives output node 48 in one of two dπve states, and does not drive output node 48 in a third "non-drive" state, dependent upon data signals DATA. In each of the two drive states, one of the switching elements 74a-b is in the closed state. In a first drive state, switchmg element 74a is m the closed state, and switching element 74b is in the open state Output node 48 is coupled to V DD through switchmg element 74a and resistor 76a. Resistor 76a has a value substantially equal to half the charactenstic impedance Z 0 of transmission lme 44. In the first dnve state, an electrical current of about (V DD / 12 Z 0 ) flows through first termmation resistor 78a, an electπcal current of about (5 V DD 12 Z 0 ) flows through second termination resistor 78b, and mput node 60 is at a voltage level of (5 V DD 6) In the second drive state, switching element 74b is m the closed state and switchmg element 74a is m the open state Output node 48 is coupled to V ss through switchmg element 74b and resistor 76b. Resistor 76b has a value substantially equal to half the charactensnc impedance Z 0 of transmission lme 44 In the second dπve state, an electncal current of about (5 V DD 12 Z 0 ) flows through first termmation resistor 78a, an electncal current of about (V DD / 12 Z 0 ) flows through second termmation resistor 78b, and input node 60 is at a voltage level of (V DD / 6) In the third "non-dπve" state, switchmg elements 74a-b are both m the open state, and driver circuit 70 does not drive output node 48 Input node 60 is coupled to V DD through first termmation resistor 78a, and to V ss through second termination resistor 78b First and second termmation resistors 78a-b both have values substantially equal to twice the characteristic impedance Z 0 of transmission lme 44 In the third "non-dnve" state, an electncal current of about (V DD / 4 Z 0 ) flows through first and second termmation resistors 78a-b, and input node 60 is at a voltage level of (V DD / 2) Fig 7 is a graph of voltage levels V present within communication device 42a and present upon transmission line 44 of Fig 6 In the first and second drive states of driver circuit 70, respective approximate voltage levels of (5 V DD /6) and (V DD /6) are dnven upon transmission line 44 by dπver circuit 70 as descπbed above In the third "non-drive" state of dπver circuit 70, first and second termination resistors 78a-b of termmation circuit 72 force a voltage level of (V DD /2) upon transmission lme 44 as descπbed above The three voltage levels associated with the two drive states and the non-drive state are used to convey binary data signals DATA from communication device 42a to communication device 42b Upper and lower one-sixths of the voltage range between V DD and V ss are unused as shown in Fig 7 First reference voltage level provided to the second input termmal of comparator 64a is selected between voltage levels (5 V DD /6) and (V DD 2) as mdicated in Fig 7 Voltage values less than received at the first input terminal of comparator 64a may cause comparator 64a to produce a bmary logic 0 signal at the output terminal, and voltage values greater then V^, received at the first input termmal of comparator 64a may cause comparator 64a to produce a binary logic 1 signal at the output termmal Second voltage level V REF2 provided to the second input termmal of comparator 64b is selected between voltage levels (V DD /2) and (V DD /6) as indicated in Fig 7 Voltage values less than V,^ received at the first input terminal of comparator 64b may cause comparator 64b to produce a binary logic 0 signal at the output termmal, and voltage values greater then V REF2 received at the first input terminal of comparator 64b may cause comparator 64b to produce a binary logic 1 signal at the output termmal As described above, the binary outputs of comparators 64a-b indicate which of the three voltage levels exists upon transmission line 44 For example, when the first voltage level of (5 V DD 16) is present upon transmission lme 44, the outputs of comparators 64a-b may both be a bmary logic 1 When the second voltage level of (V DD /2) is present upon transmission lme 44, the output of comparator 64a may be a bmary logic 0, and the output of comparator 64b may be a binary logic 1 When the third voltage level of (V DD /6) is present upon transmission line 44, the outputs of comparators 64a-b may both be a binary logic 0 Decode logic 66 uses the bmary outputs of comparators 64a-b to reproduce binary data signals DATA as descnbed above Fig 8 is a diagram of one embodiment of a digital communication system 80 in accordance with the present invention Digital communication system 80 includes a first communication device 82a and a second communication device 82b coupled to opposite ends of m data transmission lmes 84 (m ≥ 2) and a clock transmission line 86 Communication device 82a dnves one of three different voltage levels upon first ends of the m data transmission lmes 84 dependent upon the logical values of n bmary data signals DATA1 through DAT AH (n ≥ 2) and m response to a clock signal CLOCK. Communication device 82a also dnves at least one voltage level upon a first end of clock transmission lme 86 in response to clock signal CLOCK. Communication device 82b is coupled to second ends of the m data transmission lmes 84 and clock transmission lme 86. The m data transmission lines 84 and clock transmission lme 86 may be signal lmes which behave like transmission lme due to the fact that signal rise and fall tunes between voltage levels are short with respect to propagation delay tunes of the signal lines as described above. Communication device 82b receives the voltage levels driven upon the m data transmission lmes 84 and clock transmission line 86 Communication device 82b reproduces the original clock signal CLOCK from the at least one voltage level driven upon clock transmission line 86 Communication device 82b reproduces the oπg al n binary data signals DATA1 through DATAw from the voltage levels driven upon the m data transmission lines 84 and in response to clock signal CLOCK. Communication device 82a includes an output section 88 coupled to m data output nodes 90 and a clock output node 92. Each of the m data output nodes 90 is coupled to the first end of a different data transmission line 84, and clock output node 92 is coupled to the first end of clock transmission line 86. Output section 88 mcludes control logic 94, m driver circuits (DC) 96 each coupled to a corresponding one of the m data output nodes 90, and a dnver circuit (DC) 98 coupled to clock output node 92. Each of the m dπver circuits 96 is coupled between control logic 94 and the coπespondmg one of the m data output nodes 90. Control logic 94 receives the n binary data signals DATA1 through DATAn and a bmary clock signal CLOCK. Control logic 94 produces control signals coupled to the m dnver circuits 96. Control logic 94 produces the control signals dependent upon the n binary data signals DATA1 through DATAn and in response to the bmary clock signal CLOCK. Each of the m dπver circuits 96 may be driver circuit 52 or driver circuit 70 descπbed above. Each of the m driver circuits 96 may dπve the coπespondmg one of the m output nodes 90 m one of three dπve states dependent upon the control signals received from control logic 94 (driver circuit 52). Alternately, each of the m dnver circuits may drive the coπesponding one of the m output nodes 90 in one of two dnve states, and may not dnve the coπesponding one of the m output nodes 90 in a third "non-drive" state, dependent upon the control signals received from control logic 94 (driver circuit 70). Communication device 42b includes an mput section 100 coupled to m data input nodes 102 and a clock input node 104. Each of the m data input nodes 102 is coupled to the second end of a corresponding one of the m data transmission lines 84, and clock mput node 104 is coupled to the second end of clock transmission line 86. Input section 100 includes m termination circuits 106 each coupled to a correspondmg one of the m data mput nodes 102, a termination circuit 108 coupled to clock input node 104, m pairs of comparators 110, a comparator 112, and decode logic 114. Each of the m termmation circuits 106 within communication device 82b coπesponds to a different one of the m dπver circuits withm communication device 82a just as termination circuit 108 corresponds to dπver circuit 98. Each of the m termmation circuits 106 and termmation circuit 108 may be termmation circuit 62 or termination circuit 72 dependent upon whether the correspondmg driver circuit is a dπver circuit 52 or dπver circuit 70. A given one of the m termination circuits 106 may be termination circuit 62 when the correspondmg one of the m dnver circuits 96 is dnver circuit 52, and termmation circuit 108 may be termmation circuit 62 when dnver circuit 98 is dπver circuit 52. Similarly, the given one of the m termmation circuits 106 may be termmation circuit 72 when the corresponding one of the m dnver circuits 96 is driver circuit 70, and termmation circuit 108 may be termmation circuit 72 when driver circuit 98 is driver circuit 70 Each comparator of the m pairs of comparators 110 has two mput termmals and an output terminal. A first input termmal of each comparator of the m pairs of comparators 110 is coupled to a corresponding one of the m data input nodes 102 through a coπespondmg one of the m termmation circuits 106. The second mput termmal of a first comparator of each of the m pairs of comparators 110 is coupled to first reference voltage level V MF1 . The second input terminal of a second comparator of each of the m pairs of comparators 110 is coupled to second reference voltage level V RE ^. Each of the m pairs of comparators 110 produce bmary logic signals at the output terminals which indicate which of three voltage levels are present upon the conesponding one of the m data transmission lines 84. Comparator 112 has two mput terminals and an output terminal. A first mput termmal of comparator 112 is coupled to clock input node 104 through termination circuits 108. The second mput termmal of comparator 112 is coupled to a third reference voltage level V REF3 . Third reference voltage level V R ^ is between two voltage levels present upon clock transmission line 86 such that comparator 112 reproduces bmary clock signal CLOCK at the output termmal. Decode logic 114 receives the binary output signals produced by the m pairs of comparators 110 and the bmary clock signal CLOCK reproduced by comparator 112. Decode logic 114 mcludes n flip-flops 116 controlled by clock signal CLOCK. Decode logic 114 uses the binary output signals received from the m pairs of comparators 110 to reproduce the n binary data signals DATA1 through DATAn, and produces the n bmary data signals DATA1 through DAT AH at output terminals of the n flip-flops 116 m response to clock signal CLOCK. The H binary data signals DATA1 through DATAn simultaneously convey one of 2 n logical states. The m data transmission lines 84, each having one of three voltage levels present thereupon, simultaneously convey one of 3 m logical states. Thus the minimum value of m required to simultaneously convey one of 2 n logical states is the smallest integer greater than or equal to log 3 (2") The present invention contemplates a digital communication system with at least one transmission line having one of , voltage levels present thereupon, where p ≥ 3. In general, m data transmission lines having one of p voltage levels present thereupon simultaneously convey one of p m logical states. Thus the minimum value of m required to simultaneously convey one of 2" logical states is the smallest integer greater than or equal to logr>(2 n ). Three binary data signals simultaneously convey one of 2 3 (8) logical states, and two transmission lines having one of three voltage levels present thereupon simultaneously convey one of 3 2 (9) logical states. Thus two transmission lines having one of three voltage levels present thereupon can convey the information of three bmary data signals simultaneously, and can thus replace three binary transmission lines. Table 1 below shows logic levels which may be used to implement an exemplary communication system conveymg three binary data signals over two transmission lines simultaneously, where DATA1, DATA2, and DATA3 are the logical levels of the three binary data signals, and Tl and T2 are the logical levels associated with the voltage levels present upon the two transmission lmes. Table 1. Logic Levels for an Exemplary Communication System. DATA1 DATA2 DATA3 Tl T2 0 0 0 Logic LO (0) Logic LO (0) 0 0 1 Logic LO (0) Logic MID (1) 0 1 0 Logic LO (0) Logic HI (2) 0 1 1 Logic MID (1) Logic LO (0) 1 0 0 Logic MID (1) Logic MID (1) 1 0 1 Logic MID (1) Logic HI (2) 1 1 0 Logic HI (2) Logic LO (0) 1 1 1 Dgic HI (2) Logic MID (l) The logic LO (0), MID (1), and HI (2) levels of the two transmission lines may be associated with the voltage levels mdicated in Figs. 5 and 7 It is noted that one logical state of the two transmission lines, where Tl = logic HI (2) and T2 = logic HI (2), is not used. Using two transmission lmes having one of three voltage levels present thereupon to replace three binary transmission lmes represents a one-third reduction m the number of required signal paths between devices and a one-third savings in associated elements (e.g., signal transmission lmes, device package termmals, dπve circuitry, receive circuitry, etc.) and the amount of physical space occupied by such elements. Alternately, an oπgmal number of signal paths may be retamed, allowmg an mcrease in the rate at which bmary data may be transmitted from one device to another A data transmission scheme which uses ternary data signals to produce a voltage level transition every clock cycle in a data stream conveyed from one communication device to another will now be descnbed Control logic 50 of digital communication system 40 (Figs 4 and 6) may be configured to encode the binary data signals DATA into ternary signals in a manner which guarantees a voltage level transition upon transmission line 44 for every cycle of clock signal CLOCK1 even when the logic levels of the bmary data signals DATA remam unchanged from one cycle of CLOCK1 to the next. Decode logic 66 (Figs. 4 and 6) may be configured to reproduce the binary data signals DATA from the bmary outputs of comparators 64a-b coπesponding to ternary logic levels upon transmission lme 44. The data transmission scheme greatly simplifies the tasks of generatmg clock signal CLOCK2 and synchronizing CLOCK2 to clock signal CLOCK 1 Fig. 9 is a state diagram of an exemplary state machine which may be embodied within control logic 50 in order to implement the data transmission scheme described above The state diagram includes three states: a first state 120, a second state 122, and a third state 124. A different voltage level is present upon transmission line 44 in each of the three states, and while in any one of the three states, a received binary data signal causes a transition to a different state such that a voltage level transition occurs upon transmission lme 44 In state 120, control logic 50 causes the dπver circuit of communication device 42a to produce the ternary logic LO (0) level at output node 48 (See Figs 5 and 7 ) While in state 120, a received bmary logic 0 causes a transition to state 122, and a received bmary logic 1 causes a transition to state 124 In state 122, control logic 50 causes the driver circuit of communication device 42a to produce the ternary logic MID (1) level at output node 48 While in state 122, a received bmary logic 0 causes a transition to state 120, and a received bmary logic 1 causes a transition to state 124. In state 124, control logic 50 causes the dnver circuit of communication device 42a to produce the ternary logic HI (2) level at output node 48 While m state 124, a received binary logic 0 causes a transition to state 120, and a received bmary logic 1 causes a transition to state 122. Fig. 10 is a state diagram of an exemplary state machine which may be embodied withm decode logic 66 in order to implement the data transmission scheme described above. The state diagram includes four states: a first state 126, a second state 128, a third state 130, and a fourth state 132. In state 126, decode logic 66 produces a binary logic 0 data signal DATA While in state 126, received binary outputs of comparators 64a-b coπesponding to a ternary logic MID (1) level upon transmission lme 44 cause a transition to state 128, and received bmary outputs of comparators 64a-b coπesponding to a ternary logic HI (2) level upon transmission lme 44 cause a transition to state 130 In state 128, decode logic 66 produces a bmary logic 0 data signal DATA. While in state 128, received binary outputs of comparators 64a-b coπesponding to a ternary logic LO (0) level upon transmission line 44 cause a transition to state 126, and received binary outputs of comparators 64a-b coπespondmg to a ternary logic HI (2) level upon transmission lme 44 cause a transition to state 130. In state 130, decode logic 66 produces a bmary logic 1 data signal DATA While in state 130, received binary outputs of comparators 64a-b coπesponding to a ternary logic MID (1) level upon transmission line 44 cause a transition to state 132, and received bmary outputs of comparators 64a-b coπespondmg to a ternary logic LO (0) level upon transmission lme 44 cause a transition to state 126. In state 132, decode logic 66 produces a bmary logic 1 data signal DATA. While m state 132, received bmary outputs of comparators 64a-b coπespondmg to a ternary logic HI (2) level upon transmission line 44 cause a transition to state 130, and received binary outputs of comparators 64a-b coπespondmg to a ternary logic LO (0) level upon transmission lme 44 cause a transition to state 126. Fig. 11 is a graph of the clock signal CLOCK1, binary data signal DATA, and the output voltage at output node 48 of communication device 42a versus time illustrating the data transmission scheme descπbed above. In Fig. 11, the HIGH output voltage level at node 48 is associated with the ternary logic HI (2) level, the MEDIUM output voltage level is associated with the ternary logic MID (1) level, and the LOW output voltage level is associated with the ternary logic LO (0) level. (See Figs. 5 and 7.) It is noted that the output voltage at output node 48 changes every cycle of clock signal CLOCK 1 even when the logic levels of the binary data signals DATA remain unchanged from one cycle of CLOCK 1 to the next. In a method for implementing the data transmission scheme, control logic 50 of communication device 42a may encode the bmary data signals DATA to form a ternary data stream mcludmg ternary data signals such that a voltage level transition occurs within the ternary data stream every cycle of clock signal CLOCK 1 as described above and illustrated m Fig. 11. Communication device 42b may receive the ternary data stream (e.g., via transmission line 44) and synchronize clock signal CLOCK2 to clock signal CLOCK1 usmg the voltage level transitions occurring within the ternary data stream Comparators 64a-b and decode logic 66 of communication device 42b may be used to decode the ternary data within the ternary data stream m response to clock signal CLOCK2 thereby reproducmg the binary data signals DATA from the ternary data signals. Fig. 12 is a graph of the mput voltage at mput node 60 of communication device 42b versus time used to illustrate an alternate method for usmg the outputs of comparators 64a-b to decode the ternary data withm the ternary data stream of Fig. 11. Communication device 42b may receive the ternary data stream and produce the lό clock signal CLOCK2 delayed m time with respect to clock signal CLOCK1 (e g., through the use of a delay lock loop or DLL). This would allow decode logic 66 to wait a fraction of a penod of the clock signal CLOCK1 (1 e., a fraction of a bit time) labeled a "wait time" in Fig. 12 following the mput voltage crossmg one reference voltage threshold (i.e., m order to determine if the mput voltage crosses both reference voltage thresholds (i.e., V REP , and V^^) m the same bit time. Referring to Fig. 12, decode logic 66 distinguishes and mput voltage transition from the logic LO (0) level to the logic MID (1) level (i.e., an mput voltage transition from point A to pomt B) from an input voltage transition from the logic LO (0) level to the logic HI (2) level (i.e., an mput voltage transition from point A to pomt E) by waiting the wait time penod after the input voltage crosses the V^ threshold. If the input voltage does not cross the V REF1 threshold during the wait time period, the input voltage transition is from the logic LO (0) level to the logic MID (1) level. On the other hand, if the mput voltage crosses the V^p, threshold duπng the wait time penod, the mput voltage transition is from the logic LO (0) level to the logic HI (2) level. It is noted that the DLL may be used to set the wait window period dependent upon the rate of change of the mput voltage, the V^, and V^^ reference voltage levels, and the bit time. While the invention is susceptible to vaπous modifications and alternative forms, specific embodiments thereof are shown by way of example in the drawings and will herein be descnbed in detail. It should be understood, however, that the drawings and detailed description thereto are not intended to limit the invention to the particular form disclosed, but on the contrary, the intention is to cover all modifications, equivalents and alternatives falling within the spiπt and scope of the present mvention as defined by the appended claims.

Claims: WHAT IS CLAIMED IS: 1 A digital communication system, compπsmg a first communication device having an output node coupled to a first end of a transmission lme and a second communication device having an input node coupled to a second end of the transmission line, wherein the second communication device compπses a termination resistor coupled between the input node and a power supply voltage level, wherein an electncal voltage level existmg at the input node is substantially dependent upon an amount of electrical cuπent flowing through the termination resistor, wherein the first communication device is configured to dπve the output node in one of p drive states, where p ≥ 3, and wherem each of the p drive states causes a different amount of electncal cuπent to flow through the termination resistor such that a different electrical voltage level exists at the input node m each of the p drive states 2 The digital communication system as recited in claim 1 , wherein the different electπcal voltage levels existing at the mput node in each of the p dπve states are associated with different logic levels 3 The digital communication system as recited in claim 1 , wherein the transmission line has a characteπstic impedance, and wherem the termmation resistor has a value substantially equal to the charactenstic impedance of the transmission line 4 The digital communication system as recited in claim 1, wherein the first communication device compπses an output section coupled to receive binary data and configured to drive the output node in one of the p drive states dependent upon the binary data 5 The digital communication system as recited in claim 4, wherem the output section is coupled to receive a clock signal and configured to drive the output node in response to the clock signal 6 The digital communication system as recited in claim 4, wherein the second communication device includes an input section coupled to the input node and configured to produce the bmary data from the different electrical voltage levels existing at the input node 7 The digital communication system as recited in claim 6, wherein the mput section is configured to produce the binary data in response to a clock signal 8 The digital communication system as recited m claim 1 , wherein the electrical voltage levels existmg at the input node m each of the p drive states differ by substantially equal amounts 9 A digital communication system, compπsmg a first communication device having an output node coupled to a first end of a transmission line and a second communication device havmg an mput node coupled to a second end of the transmission lme; wherein the second communication device comprises a first termmation resistor coupled between the mput node and a first power supply voltage level and a second termmation resistor coupled between the input node and a second power supply voltage level, wherein an electrical voltage level existing at the input node is substantially dependent upon an amount of electncal cuπent flowing through the first termmation resistor; wherein the first communication device comprises dπve circuitry, and wherein the first communication device is configured to- (I) electncally couple the drive circuitry to the output node in each of p dnve states, where p >2, and to drive the output node in each of the p dπve states via the dπve circuitry, and (n) electrically decouple the dπve circuitry from the output node in a non-dπve state; wherein a different amount of electrical cuπent flows through the first termination resistor in each of the p dnve states and the non-drive state such that a different electπcal voltage level exists at the input node in each of the p drive states and the non-drive state. 10. The digital communication system as recited in claim 9, wherem the different electncal voltage levels existmg at the input node in each of the p dnve states and the non-dπve state are associated with different logic levels. 11 The digital communication system as recited in claim 9, wherein the transmission lme has a characteπstic impedance, and wherein the first and second termination resistors have values substantially equal to twice the characteristic impedance of the transmission line 12. The digital communication system as recited in claim 9, wherein the first communication device comprises an output section coupled to receive binary data and configured to drive the output node in one of the p dnve states dependent upon the binary data 13 The digital communication system as recited in claim 12, wherem the output section is coupled to receive a clock signal and configured to drive the output node in response to the clock signal 14 The digital communication system as recited in claim 12, wherem the second communication device includes an input section coupled to the input node and configured to produce the bmary data from the different electrical voltage levels existing at the input node. 15 The digital communication system as recited m claim 14, wherem the mput section is configured to produce the binary data m response to a clock signal 16 The digital communication system as recited in claim 10, wherem the electπcal voltage levels existmg at the mput node m each of the p dnve states and the non-drive state differ by substantially equal amounts 17 A digital communication system, compnsing a first communication device having m data output nodes and a clock output node, a second communication device having m data input nodes and a clock mput node, wherein each of the m data mput nodes coπesponds to a different one of the m data output nodes, and wherein the clock mput node corresponds to the clock output node, m data transmission lines coupled between coπespondmg data output and input nodes, and a clock transmission line coupled between the clock output and mput nodes, wherein the second communication device compπses an mput section mcludmg m+\ termination resistors, wherem each of m of the m+\ termmation resistors is coupled between a different one of the m data mput nodes and a power supply voltage level, and wherem one of the m+l termination resistors is coupled between the clock input node and the power supply voltage level, wherem an electncal voltage level existmg at a given data mput node is substantially dependent upon an amount of electrical cuπent flowing through the termination resistor coupled between the given data input node and the power supply voltage level, wherem an electrical voltage level existing at the clock mput node is substantially dependent upon an amount of electπcal cuπent flowing through the termination resistor coupled between the clock mput node and the power supply voltage level, wherein the first communication device compnses an output section coupled to receive n binary data signals and a binary clock signal, and wherein the output section is configured to (I) dπve each of the m data output nodes in one of p dπve states dependent upon the n binary data signals and in response to the binary clock signal, and wherem n > m and p ≥ 3, and wherein each of the p drive states used to drive a given data output node causes a different amount of electrical cuπent to flow through the termmation resistor coupled to the coπesponding data input node such that a different electπcal voltage level exists at the coπesponding data mput node in each of the p drive states, and (π) drive the clock output node in one of q drive states dependent upon the binary clock signal, and wherein q ≥ 2, and wherem each of the q dπve states causes a different amount of electrical cuπent to flow through the termmation resistor coupled to the clock input node such that a different electπcal voltage level exists at the clock mput node in each of the q drive states, and wherein the input section is configured to (l) produce the binary clock signal from the electrical voltage levels existing at the clock input node, and (n) produce the n binary data signals from the electrical voltage levels existing at the m data input nodes in response to the binary clock signal 18 The digital communication system as recited in claim 17, wherein m is the smallest integer greater than or equal to logp(2") 19. The digital communication system as recited m claim 17, wherem each transmission lme is coupled to a different input node and has a charactenstic impedance, and wherem a value of one of the m+l termmation resistor coupled to a given mput node is substantially equal to the characteπstic impedance of the transmission lme coupled to the given mput node. 20. The digital communication system as recited m claim 17, wherem the electπcal voltage levels existmg at a given data input node m each of the p drive states differ by substantially equal amounts. 21. A digital communication system, compπsing- a first communication device havmg m data output nodes and a clock output node, a second communication device having m data input nodes and a clock mput node, wherem each of the m data input nodes coπesponds to a different one of the m data output nodes, and wherein the clock mput node coπesponds to the clock output node; m data transmission lines coupled between coπespondmg data mput and output nodes, and a clock transmission line coupled between the clock input node and the clock output node, wherein the second communication device comprises an input section including 2 +l termmation resistors, wherein each of m of the termmation resistors is coupled between a different one of the m data input nodes and a first power supply voltage level, and wherem each of m of the termmation resistors is coupled between a different one of the m data input nodes and a second power supply voltage level, and wherem one of the 2/n+l termmation resistors is coupled between the clock input node and the first power supply voltage level; wherein an electπcal voltage level existmg at a given data mput node is substantially dependent upon an amount of electrical cuπent flowing through the termination resistor coupled between the given data input node and the first power supply voltage level; wherein an electπcal voltage level existing at the clock input node is substantially dependent upon an amount of electrical cuπent flowing through the termination resistor coupled between the clock input node and the first power supply voltage level, wherein the first communication device comprises an output section coupled to receive n binary data signals and a binary clock signal, and wherein the output section is configured to: (I) dπve each of the m data output nodes in one of/, drive states dependent upon the n binary data signals and in response to the binary clock signal, and wherein n > m and p ≥ 2, and wherein each of the p drive states used to drive a given data output node causes a different amount of electrical cuπent to flow through the termination resistor coupled to the coπespondmg data mput node such that a different electrical voltage level exists at the coπespondmg data mput node in each of the ? dπve states, and (n) drive the clock output node in one of q drive states dependent upon the binary clock signal, and wherein q ≥ 1, and wherem each of the q dπve states causes a different amount of electπcal cuπent to flow through the termination resistor coupled to the clock input node such that a different electrical voltage level exists at the clock mput node in each of the q dnve states, and wherem the mput section is configured to: (1) produce the bmary clock signal from the electncal voltage levels existmg at the clock mput node, and (n) produce the n bmary data signals from the electπcal voltage levels existmg at the m data mput nodes m response to the bmary clock signal. 22. The digital communication system as recited in claim 21, wherem each data transmission lme is coupled to a different data input node and has a characteπstic impedance, and wherein each termmation resistor coupled to a given data input node has a value substantially equal to twice the charactenstic impedance of the data transmission line coupled to the given input node. 23 The digital communication system as recited m claim 21 , wherein the clock transmission line has a charactenstic impedance, and wherem the value of the termination resistor coupled between the clock mput node and the first power supply voltage level is selected such that the input resistance at the clock input node is substantially equal to the characteristic impedance of the clock transmission line. 24 A method for transmitting binary data from a first communication device to a second communication device, compnsing' the first communication device encoding the binary data to form a ternary data stream comprising ternary data such that a voltage level transition occurs withm the ternary data stream every cycle of a first clock signal. 25. The method as recited in claim 24, further comprising: the second communication device receivmg the temary data stream and synchronizing a second clock signal to the first clock signal usmg the voltage level transitions occurπng withm the ternary data stream; and the second communication device decoding the ternary data withm the ternary data stream in response to the second clock signal thereby reproducing the binary data from the ternary data

Inventors: DOBLAR DREW, YUAN LEO, DOBLAR, DREW, YUAN, LEO
Applicants: SUN MICROSYSTEMS INC, SUN MICROSYSTEMS, INC.
Application year: 2000
Main classification: H04L25
IPC codes: H04L25