Redundancy architecture for an interleaved memory

Abstract: A redundancy architecture for a memory wherein the array of memory cells is divided in at least a pair of banks or semiarrays (EVEN_BANK, ODD_BANK) singularly addressable (ADDR_latch_E, ADDR_latch_O), organized in rows and columns; the architecture comprising a certain number of packets each composed of a certain number of redundancy columns of cells (REDUNDANCY), contemplates dividing said number of packets (REDUNDANCY) in two subsets of packets (REDUNDANCY_EVEN, REDUNDANCY_ODD), each one addressable independently from the other by way of respective address circuits and providing redundancy columns of cells exclusively for a respective bank or semiarray (EVEN_BANK, ODD_BANK).

Description: FIELD OF THE PRESENT INVENTION The present invention relates to memory redundancy architectures and in particular to an architecture for burst interleaved memories. BACKGROUND OF THE INVENTION Redundancy is a hardware technique that allows the recovering of possible defects of a memory array in order to increase the effective yield of the fabrication process of the device. In most cases, when speaking of redundancy a "column" redundancy is generally intended, i.e. to the possibility of substituting matrix columns containing one or more defects with (spare) redundant columns. The document US-A-5 999 463 discloses a semiconductor memory device having a reduced number of column redundancy fuse boxes. The device has a plurality of normal column selection line drivers for the banks or semiarrays in which the memory is divided, a plurality of redundant column selection line drivers for the two semiarrays and a column redundancy fuse box connected in common to the redundant column selection line drivers of the two semiarrays. If a defective memory cell exists in both of the two memory blocks or semiarrays or even if a defective memory cells exits in only one of the two semiarrays, it is replaced by a redundant memory cell simultaneously in both semiarrays. The commonly used architecture for managing the addresses of so substituted locations is mainly constituted by banks of non-volatile memory units, briefly called CAM, which can be programmed and erased by the manufacturer during a phase of testing of the devices. These CAM units store information suitable to identify univocally the memory locations to be substituted. Information stored in CAM can be of different kinds: addresses of the location to be repaired, which packet of bit of an addressed word must be replaced, whether or not the bank of CAM is used to store a fail address, etc. The function of a redundancy managing architecture is to verify whether or not the addressed location is comprised among the redunded ones and, in case of positive result, to activate the redundant columns and at the same time to deactivate the decoding of the defective location of the matrix. This must be done for each operation, reading or writing, that implies addressing the defective (fail) location. The number of CAM banks used in a redundancy architecture fixes the maximum number of packets (columns, byte, rows ...) of the whole array of memory cells that can be substituted. In a "traditional" functioning of a so-called standard (asynchronous) memory, there are no particular difficulties in dedicating a redundancy packet to any fail of the memory, nor are there restrictions on activation times of any redundant element. By contrast, in the case of synchronous memories operating with a "burst interleaved" protocol there is the need of properly differentiating the activation instants for contiguous substituted locations during burst read cycles. In fact, in a burst interleaved access mode, two contiguous readings (e.g.: add0→add1) are carried out with a certain time overlap. This means that, while a data is being output, the successive data has been already addressed and is in the process of being read. Therefore, it is clear that redundancy architectures for this kind of interleaved memories, must consider this peculiarity, in order to differentiate correctly, without conflicts, the turn-on instant of the redundancy elements, for example in the hypothesis of addressing two contiguous locations (according to a burst access mode) that are both substituted. Normally the redundancy architecture is similar to the corresponding decoding structure of the memory matrix. Similarly, by referring to the architecture of a typical matrix, the redundancy unit is constituted, as depicted in Fig. 1, by a Main Bit Line (defined in Metal2), starting from which, four Real Bit Line (defined in Metall) that are connected to the drains of the respective redundancy cells, are decoded. To realize a so called "column" redundancy, two alternative approaches are normally followed: redundancy by output (replacement of the single line to which the fail belongs); redundancy by "packets" (fully or partial substitution of the group of BitLines of the word affected by a fail, as addressed during a reading). For example the redundancy architecture may contemplate the repairing of an 8 bit packet (i.e. of the byte high or of the byte low) of an addressed 16 bit word, irrespectively of the fact that the defect be verified on a single bit of one or of the other byte and not on all the 8 bits. According to this second approach, on one hand there is a "waste" of silicon area due to the superfluous number of columns that in the majority of repairs of single bit fail would not be necessary, on the other hand it is required a greatly simplified circuitry for managing the redundancy, thus reducing the silicon area of integration of the managing circuitry. For example there may be four redundancy banks for the whole array, i.e. the possibility of using four column packets for possible replacements. In an interleaved memory, the whole array of cells is split in several parts (typically in two semiarrays EVEN/ODD) that are individually addressable in order to avoid problems in managing two partly time overlapped readings as previously discussed, using a number of sense amplifiers equal to the number of outputs. In a "classical" memory, the selection of the redundant column and the deselection of the column to be substituted is commonly done by acting on the first decoding level while the other decoding levels of the memory matrix remain active. On the contrary, the last decoding level that determines which of the BitLines connected to the MBL itself (Fig. 1) will be the selected one is active for both the memory matrix and the redundancy structure. Normally, the read bus is common to both the memory matrix and the redundancy structure, so when a "repaired" location is addressed, the matrix local decoding is disabled while the redundancy local decoding is activated, thus allowing the connection between the redundant physical column and the sensing circuitry. By implementing a redundancy per byte, only the matrix local decoding of the word to which the packet (byte) to be replaced belongs will be deactivated, while the other eight local decodings will still be selecting a matrix location. It is clear that the redundancy, which is essential to guarantee an acceptable yield of the fabrication process, has a sensible cost in terms of silicon area consumption and therefore it is of great importance optimizing its performances while minimizing the area dedicated to it. OBJECT AND SUMMARY OF THE INVENTION It has been found that great advantages can be attained by subdividing the number of redundancy column packets in subgroups, each one addressable independently from the other subgroups and providing columns of redundancy cells only for a respective bank in which the memory cell array is divided. Each subgroup of packets of redundancy columns has a capacity appropriate to satisfy statistically determined needs of possible bit fail of the single bank to which the subgroup is associated. The redundancy selection circuitry, or the number of banks of CAM, remains unchanged because nothing else is modified. In practice, the total number of packets of redundancy columns is simply split, i.e. subdivided into subgroups. This arrangement proves itself extremely advantageous. It simplifies the managing of the redundancy and determines a saving of silicon area. In particular the approach of the invention does not impose any restriction but the fact that it is no longer possible to substitute two bytes of a same addressed location (word). On the other side, the condition of independence of redundancy for the banks of subdivision of an interleaved memory is fully accomplished allowing, as already discussed in the preamble, the possibility of substituting successive locations that could be read during the same time interval when accessing the memory in burst mode. Another advantage of the subdivision of the redundancy architectures in distinct subgroups consists in the fact that in terms of layout, the width of the read and write buses for a memory organized in 16 bit words can be of 16 bit only along the whole width of the physical memory array, because the buses to which the redundant MBL will possibly be connected, will be local and related to a single bank (in the case of an interleaved memory) and to a single read/write path. For the same design choice of redundancy by bytes, a commonly used technique to save area consists in using separately the four right columns and the four left columns of a packet of eight columns, thus dividing in two portions a full packet of redundancy columns, but this known technique has the following drawbacks: impossibility of substituting two successive locations according to the burst-interleaved reading mode, because it is not possible to activate at the same time 16MBL related to two substituted bytes of the two successive locations (EVEN-ODD) during the same reading cycle; difficulty in "routing" the read/write bus that must have a 32 bit width for the whole width of the array of memory cells, because redundancy of all the banks using the same elements (spare packets of columns) must be ensured. According to another aspect of the invention, a number of banks of nonvolatile registers (CAM) equal to the maximum number of substitutions that must be ensured, defmed during the design of the device, associate to each bank of subdivision of the cells of the whole memory array (typically two semiarrays of an interleaved memory) a number of redundancy packets, equal to a pre-defined number of banks of non-volatile registers (CAM). For each of the two address systems relative to the subdivision banks of the memory array, for example relative to the EVEN semiarray and to the ODD semiarray of an interleaved memory, suitable XOR structures and one or several nonvolatile registers are employed for selecting the semiarray or bank affected by defects and one or several structures of nonvolatile registers thus selecting the portion of an addressed word that must be substituted. This approach allows a reduction (a halving, in the case of a two bank interleaved memory) of the required number of nonvolatile registers with a consequent silicon area saving. Moreover, this architecture for managing the redundancy has great flexibility. In fact, the redundancy resources can be freely assigned to any subdivision bank of the array and in any combination and/or ratio. Essentially, according to the present invention, a double XOR structure for generating the HIT signals and a CAM dedicated to the storage of the most significant column address used as a multiplexing signal of the HIT signals towards the correct portion of the array, for example towards the EVEN bank or towards the ODD bank of a common interleaved memory subdivided in two semiarrays, are employed. The invention is more precisely defined in the attached independent claim 1. BRIEF DESCRIPTION OF THE DRAWINGS Figure 1 shows the constitution of a unity, or a packet of redundancy columns composed of a Main Bit Line (Metal2), or briefly MBL, from which four Real Bit Line (Metal1), that are thus connected to the drain of the respective redundancy memory cells, are decoded. Figure 2 is a functional diagram of the CAM dedicated to the storage of the most significant column address and of the related multiplexing circuitry of the HIT signals towards the correct portion of the memory array. Figure 3 is an embodiment of the invention for a burst interleaved memory, divided in two semiarrays EVEN and ODD. Figure 4 is a diagram of the redundancy process of the invention for the case of a burst interleaved memory. DESCRIPTION OF AN EMBODIMENT OF THE INVENTION The reading (as well as any writing cycle) of a memory location, whether it is a standard asynchronous memory (with random access) or a synchronous memory (with Burst access), always begins with the assignation of an address by the user or by an internal dedicated circuitry. The decoding circuitry decodes the assigned address in order to identify univocally the location of interest and allow either a read or a write operation. If the device has been made redundant during its testing at the end of fabrication, more steps are required to identify the "real physical location" of the memory. As diagrammatically depicted in Fig. 2, the assigned address is XOR combined with the addresses of the substituted locations and, if it corresponds to one of them, a HIT signal is generated that activates the redundancy circuitry substituting the packet of columns containing the fail with the packet of redundant columns: In the case considered of redundance by packets of columns (byte) the generated HIT signal is multiplexed in order to replace the correct packet (byte) of the addressed word. In the considered example, although the reading is carried out by words, the redundancy is activated by substituting packets of eight columns, according to the diagram depicted in Fig. 4. Successively, the effective activation of the redundancy occurs at the decoding level where the signal HIT_lowbyte/HIT_highbyte so generated, activates the YMR redundancy decoding, and disables the column decoding in the main semiarray (YM_lowbyte/YM_highbyte), as schematically depicted in Fig. 3. The read bus, as well as the Program Load, relative to the byte fail, is connected to the redundant columns corresponding to the columns of the semiarray containing a fail. By referring to the diagram of Fig. 3, the use of a double XOR structure to generate the HIT signals and the introduction of a CAM for storing the most significant column address that is used for multiplexing the HIT signals towards the correct semiarray (EVEN or ODD) guarantees an independent redundancy for the two semiarrays EVEN/ODD of the (interleaved) memory, fully satisfying the requirements imposed to the overlap of the readings. In standard memories, the managing of the redundancy consists in comparing all column addresses with the values stored in the CAMs of the redundancy banks. A logic AND of the single bits of the result of such a comparison produces the HIT signal that, depending on the other essential information (High_Byte/Low_Byte) stored in another CAM, activates the redundancy circuitry relative to the byte that need to be substituted. In the case of the considered burst interleaved memory, only n-1 column address, instead of n, stored in the respective CAMs are used to produce the HIT signal by a logic XOR operation. In fact, also the most significant address (A0) is stored in a CAM, but its function is that of multiplexing the produced HIT signal towards the correct semiarray. Practically the n-1 addresses point to two symmetrical locations, one for each semiarray EVEN/ODD, while the n-th address A0 serves for selecting between the two symmetrical locations. Successively the two XOR structures are input with the addresses stored in the CAMs and differ from each other because of the other input that the address bus EVEN or ODD presents to the input structures (address latch). As a consequence, also the redundancy value is kept unchanged for the whole duration of the reading of a semiarray, because the information of the address latches remains unchanged during the entire duration of a reading, independently from the fact that either the EVEN or ODD semiarray be considered, depending on the content of the CAM even_bank/odd_bank that stores the address A0. These considerations are valid for each of the redundancy banks that are present (4). This implies that, even if in different redundancy banks, it is possible to substitute the same location pointed by the n-1 addresses in both semiarrays. Practically it is sufficient to store in the two banks the same n-1 addresses only varying the content of the CAM odd/even_bank corresponding to the most significant address A0.

Claims: A redundancy architecture for a burst interleaved memory wherein the array of memory cells organized in rows and columns is divided in at least a pair of banks or semiarrays (EVEN_BANK, ODD_BANK)each having individually addressable memory locations, the architecture comprising a certain number of packets each composed of a certain number of redundancy columns of cells (REDUNDANCY), characterized in that said number of packets (REDUNDANCY) is divided into two subsets of packets (REDUNDANCY_EVEN, REDUNDANCY_ODD), any packet belonging to one of the two subsets of packets being addressable independently from any packet belonging to the other one of said two subsets of packets and substantially at the same time, in consideration of the time overlap that exists between consecutive readings occurring alternately in one and in the other bank (EVEN_BANK, ODD_BANK) of the burst interleaved memory, by way of respective distinct address circuits (ADDR_latch_E. ADDR_latch_o) of said two subsets; each of the two subsets providing redundancy columns of cells exclusively for a respective bank or semiarray (EVEN_BANK, ODD_BANK) of the burst interleaved memory. A redundancy architecture according to claim 1, wherein said address circuits share non volatile memory units programmable during the testing of the device, containing the addresses (ADDCAM<1,n-1>) pointing to symmetrical locations in said banks or semiarrays where there are damaged memory cells to be substituted in one or another of said banks or semiarrays (EVEN_BANK, ODD_BANK); a nonvolatile memory unit containing the most significant bit of a column address (ADDCAM<0>) pointing to the bank or semiarray to which the fail locations belong; each address circuit further comprising: an XOR logic gate for each subset of redundancy packets associated to a respective bank or semiarray, comparing the read/write address related to one or the other semiarray (ADDR_O<1,n-1>, ADDR_E<1,n-1) with the addresses (ADDCAM<1,n-1>) of said symmetrical locations of substituted cells in one or another of said banks or semiarrays contained in said nonvolatile memory unit; a selection switch (SW_E, SW_O) functionally in cascade to a respective XOR logic gate configured by the content (ADDCAM<0>) of said nonvolatile memory unit containing the most significant bit of said addresses of substituted cells, directing an enable signal (HIT) to the subset of redundancy packets relative to the respective bank or semiarray; means multiplexing the output of each of said two subsets of redundancy packets controlled by the content of said nonvolatile memory unit containing the bit coupling the output of the addressed redundancy packet to the subset of the read bus (YMS_H, YMS_L) relative to the outputs of lines containing failed cells.

Inventors: CAMPANELE FABRIZIO, DE AMBROGGI LUCA GIUSEPPE, KUMAR PROMOD, NICOSIA SALVATORE, TOMAIUOLO FRANCESCO, CAMPANELE, FABRIZIO, DE AMBROGGI, LUCA GIUSEPPE, KUMAR, PROMOD, NICOSIA, SALVATORE, TOMAIUOLO, FRANCESCO
Applicants: ST MICROELECTRONICS SRL, STMICROELECTRONICS S.R.L.
Application year: 2000
Main classification: G06F11
IPC codes: G11C29