POWER CONVERTING CIRCUIT WITH REDUCED HARMONIC CONTENT

Abstract: In a power control circuit comprising power transistors, a capacitor interconnected between the emitter and the collector of the power transistors is provided, so that the fall time after that a transistor is closed is increased and that the generation of harmonics thereby is reduced.

Description: POWER CONVERTING CIRCUIT WITH REDUCED HARMONIC CONTENT Technical field The present invention relates to an arrangement for power control of an electrical load. In particular the invention relates to an arrangement for reducing harmonics content in power control. Background of the invention and prior art In power control of electrical loads harmonics will always be formed. These harmonics are always undesired and one therefore tries to reduce the amount of harmonics. Both in terms of amplitude and frequency. Furthermore, many countries have a legislation which governs the amount of harmonic which maximally is allowed for different applications. The reason for this is that harmonics generated in power control will be transferred to the mains. In the international patent application WO 95/06353, incorporated herein by reference, a circuit for power control is described. The circuit described in WO 95/06353 can be used for controlling a number of different electrical loads, such as electrical motors, light arrangements, such as street lights, etc. If the circuit described in WO 95/06353 is used for power control of resistive, capacitive or inductive loads, the amount of harmonics will for many applications be too large. The conventional method of avoiding harmonics generated in power control from being transferred to the mains is to first rectify the current fed from the mains and then perform power control of the power fed to the load using a circuit comprising very fast transistors having very short rise and fall times. Summary It is an object of the present invention to provide a power control circuit, which generates a significantly less amount of harmonics and which hence is more suited to be used in applications where the electrical power is fed from the mains and which moreover is cheap to manufacture. Yet another object of the present invention is to avoid the use of a rectifying circuit for avoiding that harmonics are fed to the mains. This object and others are obtained by a power control circuit comprising driving stages, which can be connected to e.g. a three phase mains in order to pass voltage from the mains to an electrical load being controlled by a power control signal, in particular a pulse width modulated signal, where each driving stage comprises a power circuit preferably comprising a bridge connection having two parallel or antiparallel connected power transistors, which can be connected in series with a blocking diode each, where a capacitor is interconnected between the emitter and the collector of the power transistors. By means of providing a capacitor in this manner in the power control circuit the fall time after that a transistor is turned off is made longer. This in turn has been shown to lead to that the generation of harmonics is reduced to such an extent that the need of a circuit for avoiding that harmonics are fed to the mains ceases to exist. The power control circuit according to the present invention improves significantly the performance compared to power control circuits according to the prior art, for example the circuit described WO 95/06353. In particular the generation of harmonics is reduced, which is a requirement in many present power networks. The power control circuit according to the present invention provides a solution to the problems which the present legislation poses when implementing power control circuits in existing power networks in a simple and cost effective way. Description of the figures The present invention will now be described in more detail with reference to the accompanying drawings, in which Fig. 1 is an overview of a circuit intended to be used for power control of resistive, capacitive and inductive loads, Fig. 2 shows another modification of a circuit intended to be used for power control of resistive and inductive loads, Fig. 3 shows yet a modification of a circuit intended to be used for power control of resistive and conductive loads, Fig. 4 shows yet a modification of a circuit intended to be used for power control of resistive and inductive loads, Fig. 5a - 5f show circuit arrangements for power transistors with associated wave forms. Description of preferred embodiments In Fig. 1 a circuit for power control of an electrical load is shown. The circuit in accordance with Fig. 1 is designed in accordance with the teachings of the international patent application WO 95/06353. In Figures 2 - 4 modifications of the circuit in Fig. 1, also these in accordance with the international patent application, WO 95/06353 are shown. A problem relating to the power control circuits described in WO 95/06353 is that these generate a relatively large amount of harmonics. It can be shown that by connecting a capacitor interconnected between emitter and collector of the power transistors 70 and 72 connected in anti- parallel, so that the fall time after that the transistor has been closed is increased and that the generation of harmonics thereby is reduced. In Fig. 5a - 5f capacitors 702, 703, and 704 connected to the power transistors 70 and 72, respectively, in order to obtain such a reduction of harmonics and the wave forms obtained in the different circuit arrangements are shown. By means of interconnecting a capacitor 702 between the emitter and the collector of the power transistor 70, 72, as is shown in Fig. 5a, a long fall time after that the transistor is turned off is obtained, which in turn counteracts the generation of harmonics. This is clear from the corresponding wave forms shown in Fig. 5b. By means of connecting a capacitor 704 in series with the power transistor 70, 72, as is shown in Fig. 5c, a lower amplitude in the wave form is obtained. This has in turn shown to provide a significantly reduced variation in the current through the load in relation to an ideal wave form. This is particularly advantageous in great power reduction, where, when the power control is to take place over a large range, the capacitor 704 can be disconnectable or have a capacitance which is variable and which is controlled in response to the desired power reduction. Corresponding wave forms are shown in Fig. 5d. In Fig. 5e the capacitors 702 and 704 are shown connected in an arrangement having two power transistors connected in anti parallel, and where a capacitor 703 also has been connected over the transistor 72. The corresponding wave forms are shown in Fig. 5f. Suitable capacitors to use in these applications are capacitors which withstand high voltages and which further withstand AC voltage. Suitable values can be 1 - 100 microfarad ( μF). By using a capacitor having a capacitance which can be varied, connected over the respective power transistors, the capacitance and hence the rise and fall time, respectively, can be controlled. In a preferred embodiment a variable capacitance is obtained by connecting a number of capacitors in parallel and connecting them to be connected in response to a control signal controlling switching elements which connects, and disconnects, the capacitors connected in parallel. In a similar way the amplitude can be varied by means of providing a capacitor having a variable capacitance in series with the power transistor. The variable capacitance is preferably obtained in the corresponding way as the variable capacitance over the power transistors, i.e. using a number of capacitors connected in parallel and which can be controlled in a corresponding way as these.

Claims: CLAIMS 1. A power control circuit comprising at least one driving stage provided for letting through voltage from the mains to an electrical load being controlled by a power control signal, each driving stage comprising a power circuit having at least one power transistor, characterized by a capacitor interconnected between the emitter and the collector of at least one of the power transistors. 2. A circuit according to claim 1, characterized in that one capacitor is connected in series with at least one of the power transistors. 3. A circuit according to any of claims 1 - 2, characterized in that the circuit is arranged to be connected to a three phase mains network. 4. A circuit according to any of claims 1 - 3, characterized in that the power control signal is a pulse width modulated signal. 5. A circuit according to any of claims 1 - 4, characterized in that the power circuit comprises a bridge circuit having two power transistors connected in parallel or in anti-parallel. 6. A circuit according to claim 5, characterized in that the power transistors connected in parallel or antiparallel are connected in series with a blocking diode each. 7. A circuit according to any of claims 1 - 6, characterized in that said at least one capacitor interconnected between the emitter and the collector is variable. 8. A circuit according to any of claims 2 - 7, characterized in that said at least one capacitor connected in series with a power transistor is variable.

Inventors: OLSSON HANS-AAKE, WIKLUND GUNNAR, OLSSON, HANS-AAKE, WIKLUND, GUNNAR
Applicants: OLSSON HANS AAKE, WIKLUND GUNNAR, WOEEL ELEKTRONIK AB, OLSSON, HANS-AAKE, WIKLUND, GUNNAR
Application year: 2000
Main classification: H02M1
IPC codes: H02M1, H03K17