IC-COMPATIBLE PARYLENE MEMS TECHNOLOGY AND ITS APPLICATION IN INTEGRATED SENSORS

Abstract: A combined IC/Mems process forms the IC parts first, and then forms the MEMS parts (110). One option forms a parylene overlayer, then forms a cavity under the parylene overlayer.

Description: IC-COMPATIBLE PARYLENE MEMS TECHNOLOGY AND ITS APPLICATION IN INTEGRATED SENSORS BACKGROUND Microelectronic, or MEMS, devices often form structures using semiconductor material . Integrated Circuit or ("IC") technologies form electronic structure using that same material. Certain applications make it desirable to integrate MEMS devices with integrated circuit electronics on a single substrate. The prior art has taught making these units in certain ways. A first way processes the IC part first. The MEMS process is then formed onto the semi-finished IC wafer. The MEMS process must have certain compatibilities, in order to avoid attacking the functionality of an electronic circuit. One primary concern is with operating temperature. All post-IC electronic processes typically need to be done below 400°C: the maximum temperature for aluminum in electronic connections. This eliminates many of the common MEMS structural materials, such as LPCVD silicon nitride and polysilicon deposition; both of which have been typically done above 400°C. Therefore, this IC processing system was often used for devices which did not require certain IC dielectrics like polysilicon or metalization layers. Moreover, many IC foundries do not have processes for mechanical material properties. These foundries focus on producing reliable electronic circuits, as compared with structural processes. As such, these microstructures can have residual stresses and stress gradients. Equally problematic is that the characteristics may vary from run to run. MEMS devices can form microstructures with various film thicknesses and high aspect ratios. However, the vertical dimensions of the IC layers are often fixed in advance, in order to optimize the IC design. This in turn can limit MEMS design parameters. For example, in order to make free-standing MEMS structures, vertical stress gradients due to the composite nature of the structures can cause curling out of the plane of the substrate. In a mixed semiconductor/MEMS process, the MEMS processing can be carried out first, or an interweaved process is known in which parts of each are carried out alternately. However, due to the incompatibility of most MEMS materials with the IC processes, this can be difficult . SUMMMARY According to the techniques disclosed herein, more complex, reliable, and economic integrated circuits can be formed by special techniques described herein. BRIEF DESCRIPTION OF THE DRAWINGS These and other aspects will now be discussed with reference to the accompanying drawings, wherein: Figures la-If show a CMOS integrated circuit formation process which adds MEMS structures; Figure 2 shows an array of shear stress sensors; Figure 3 shows a close up of the shear stress sensor; Figures 4A - 4D show details of the formation process ; Figure 5 shows voltage to current transfer curves of the poly elements, before and after their release from the substrate; Figure 6 shows a schematic of the biasing circuit which is used and the Wheatstone bridge in the shear stress sensors. DETAILED DESCRIPTION The present application describes using special MEMS materials along with a semiconductor process. A specific material used is parylene, deposited after formation of the semiconductor structure, also called "post-deposited parylene". The parylene is used as a MEMS structural element. The parylene can be used along with photoresist, sputtered or low temperature- evaporated metals. A sacrificial material, such as amorphous silicon can also be used. In a disclosed mode, gas phase bromine trifluoride is used as a isotropic silicon etchant . The structure is etched in such a way to form a cavity under the parylene layer, and such that the parylene layer forms a structural part. Chemical vapor deposited ("CVD") parylene has a thickness that can range between submicrons, and more than 20 microns. This thickness ratio is desirable to enable formation of high aspect ratio microstructures. The combined post-IC process operates around room temperature and also on wafer scale substrates using standard lithography. Also disclosed herein is an integrated shear stress sensor using a hot wire operating element. The formation process is shown in Figures la-lf. Figure la shows a CMOS wafer that is fabricated by an industrial foundry. This includes a silicon substrate 100, and a dielectric layer 102 which has certain semiconductor structures thereon. These structures may include a conductive line 104 which can be aluminum, and can include one or more polysilicon structures 106. The structures are then patterned and etched in Figure lb. The dielectric passivation layer of the IC wafer is patterned and etched by combining reactive ion dry etching and buffered hydrofluoric wet etching. This forms semiconductor layers 106 which are patterned to include some, but a reduced amount, of dielectric material . A first layer of parylene 110 is deposited as shown in Figure lc . This first layer of parylene has enhanced adhesion. In one disclosed mode, the parylene can be parylene-N also called poly-para-xylylene . This thin film polymer can be conformally deposited at room temperature at a pressure of 0.1 Torr . The parylene forms a good mechanical material for forming the MEMS structures. The MEMS structures can have smaller Young's modulus and intrinsic stress as compared with an LPCVD silicon nitride. The parylene is then further processed to form a cavity. This can be done in one of two different ways. A first processing technique is shown in Figure ID. The structure is patterned using an oxygen plasma, to form etching holes as shown in Figure Id. The etching holes 120 can also be freed from the substrate, to form the gap 122. The etching can use BrF 3 or XeF 2 . The cavity 120 underneath the parylene structure is used in making micro-sized beams, membranes, and diaphragms. Hence, in summary, this first technique etches away part of the silicon substrate 100 below the part having semiconductor structures thereon ("the active part"), leaving an opening beneath the active part. The silicon etching step requires controllable selectivity over the CMOS dielectric layers, aluminum and parylene. It also requires maintaining the integrity of the parylene-substrate interface. The inventors found that BrF 3 and XeF 2 gas phase etching produce certain advantages when doing this. First, since the etching of the silicon is carried out as a dry etching, the micromachining meniscus force is mostly obviated. This is mostly done without plasma, so the possible damage to the electronic circuitry is minimized. It was also found that BrF 3 does less damage to the parylene-substrate interface than do many wet etching agents. A second processing technique to form alternative microstructures is shown in Figures le and If. These difficult-to-form microstructures can be formed by using a sacrificial layer between two structural layers, and then removing the sacrificial layer. The sacrificial layer can include photoresist- sputtered metal, or amorphous silicon. Photoresist is easily applied and etched away using acetone at room temperature. Therefore photoresist forms a sacrificial layer that has certain advantages . Figure le shows photoresist 130 being used as a sacrificial layer. The layer is removed to form cavity 140 shown in Figure If. Additional layers of metal 132, or other materials, can then be added. In addition, as shown by step 145, the composite layer deposition can be repeated to form additional layers. This process produces significantly improved results, as demonstrated by the embodiment - - which shows forming a parylene membrane shear stress sensor on a single substrate. Active control of boundary layer turbulent flows over a large surface often require distributed sensing actuation and control. MEMS devices are often used for this purpose. Wafer scale integration of the MEMS devices with IC electronics can facilitate this operation. The present shear stress device forms using the above-described IC-add-on process using parylene N as the sensor diaphragm material, and using BrF 3 etching as the means to free the diaphragm. Parylene and BrF 3 etching has significant advantages. This forms a hot film shear stress sensor with a small heat loss to the substrate. It also forms a diaphragm cavity structure in the post-IC process. The diaphragm cavity structure is shown in Figures 2 and 3. Figure 2 shows an array of shear stress sensors 200 with an on chip biasing circuit 210 and a number of bridges 220. A close up of the shear stress sensor 200 is shown in Figure 3. This includes a parylene diaphragm 310 with a poly sensor 320 integrated therein. The formation process is shown herein with respect to Figures 4A - 4D. First, in Figure 4a, the electrical structure such as the biasing circuit 210, amplifying circuits, and other circuits are fabricated using a MITEL, 2 micron double-poly double-metal IC process. A gate poly structure of 3225A thick, 20 Ohms/sq, 0/l%°C TCR is also used as the hot wire sensing element, on top of the gate oxide. The aluminum layer also forms an etch stop for the passivation layer opening. A parylene gate 400 is surrounded by insulation 402 and covered by an aluminum wiring layer 404. Figure 4b shows etching away parts of the aluminum and insulator, to leave a partial structure. In Figure 4c, the parylene N is deposited as layer 420. This layer can be deposited at 0.1 Torr . Openings 422 are formed as described above. Finally, as shown in Figure 4d, a cavity 430 is formed, leaving an opening below the semiconductor elements . The voltage to current transfer curves of the poly elements, before and after their release from the substrate, are shown in Figure 5. This clearly shows the heating effects of the freed sensor element due to the successful reduction of the conductive heat loss through the substrate and the diaphragm. Each integrated sensor has elements arranged in a Wheatstone bridge configuration in order to achieve an automatically biased 10% overheat ratio. Figure 6 shows a schematic of the biasing circuit which is used and the Wheatstone bridge. Although only a few embodiments have been disclosed above, other modifications are possible.

Claims: What is claimed is: 1. A method of forming a structure, comprising: obtaining a semiconductor structure with multiple semiconductor layers; forming a structural portion over the semiconductor structures, said structural portion including parylene; and etching an opening which leaves said parylene structure and semiconductor structure intact. 2. The method of claim 1 wherein said etching an opening comprises etching a hole under the structure using bromine trifluoride etching. 3. A method as in claim 1, wherein said etching a hole comprises forming a sacrificial layer, and removing said sacrificial layer. 4. The method of claim 3 , wherein said sacrificial layer includes photoresist. 5. The method of claim 3, wherein said sacrificial layer includes amorphous silicon. 6. The method of claim 1, wherein said parylene is poly-para-xylylene . 7. The method of claim 1, wherein said etching uses a gas phase etchant. 8. A method of forming a structure, comprising: first forming a semiconductor structure of a substrate; after forming said semiconductor structure, forming a parylene structural element, coupled to at least part of said semiconductor structure, and physically supporting said semiconductor structure. 9. The method of claim 8, wherein said semiconductor structure includes a dielectric portion formed of parylene . 10. The method of claim 8, wherein said parylene structural element supports a cavity. 11. The method of claim 8, wherein said parylene is used along with photoresist. 12. The method of claim 8, further comprising etching using a gas phase etchant. 13. The method of claim 12, wherein said gas phase etchant is gas phase bromine trifluoride used as a isotropic silicon etchant, used to form a cavity under the parylene layer. 14. A device, comprising: an electrical structure including a biasing circuit, amplifying circuit, and at least one other circuits formed using an integrated circuit process, on a semiconductor substrate; a parylene gate, associated with said electrical structure; and a parylene structural element, associated with said electrical structure, and covering an opening below the electrical structure. 15. A device as in claim 14, further comprising a heating element, located in said opening.

Inventors: HAN ZHIGANG, JIANG FUKANG, TAI YU-CHONG, WANG XUAN-QI, HAN, ZHIGANG, JIANG, FUKANG, TAI, YU-CHONG, WANG, XUAN-QI
Applicants: CALIFORNIA INST OF TECHN, HAN ZHIGANG, JIANG FUKANG, TAI YU CHONG, WANG XUAN QI, CALIFORNIA INSTITUTE OF TECHNOLOGY, HAN, ZHIGANG, JIANG, FUKANG, TAI, YU-CHONG, WANG, XUAN-QI
Application year: 2000
Main classification: H01L21
IPC codes: B81B3, B81B7, B81C1, H01L21, H01L29