TELECOMMUNICATION NETWORK ELEMENT WITH MEANS FOR SHARING RESOURCES ON A SINGLE DIE

Abstract: The invention relates to a telecommunication network element with means for sharing resources on a single die by a plurality of communication channels (201), these means comprise at least one multiplexing unit (202), and at least one combinational unit (204), and at least one storing unit (205), and at least one control unit (206), which improves the efficiency of the chip design in a telecommunication network element in a way that said multiplexing unit (202), said combinational unit (204), said storing unit (205), and said control unit (206) are logically separated from each other on said die, and that said plurality of communication channels (201) are multiplexed by said multiplexing unit (202) into one multiplexed output signal (203), and that said multiplexed output signal (203) is processed by said combinational unit (204) in time multiplex, where said combinational unit (204) represents one same Boolean equation for each channel separately, and that the result of the combinational unit is stored by said storing unit (205) for each channel individually, and that said control unit (206) controls the interworking between said multiplexing unit (202), said combinational unit (204), and said storing unit (205). Emboliment: mapping of PDH signals into SDH signal.

Description: Telecommunication network element with means for sharing resources on a single die This invention relates to a telecommunication network element with means for sharing resources on a single die by a plurality of communication channels, comprising at least one multiplexing unit, and at least one combinational unit, and at least one storing unit, and at least one control unit. In current telecommunication network elements, the communication channels are processed by a number of low order functions. These functions are realised in functional units in embedded chips on semiconductor dies. For each communication channel, one functional unit is placed on the die. Each functional unit comprises storage units and combinational units. In particular, the storage units can be random access memory (RAM) elements and the combinational units represent Boolean equations. The storage units and the combinational units comprise a huge amount of gates to realise their function. When, for instance mapping a plesiochronous digital hierarchy (PDH) signal with a plurality of 2,048 MHz clock frequency communication channels into a synchronous digital hierarchy (SDH) with 155 MHz clock frequency, as many combinational units as communication channels are being mapped, have to be placed on the die. A problem resulting hereform is, that the design complexity grows with every additional communication channel. As there are storage as well as combinational units in a functional unit, these units are mixed up on the die, and the design gets more and more complicated. Thus the die size can not be used efficiently. Another problem is that the functional unit design can not be reused, because the design for each functional unit changes with every additional communication channel. An additional problem is, that the number of gates used on the die grows at least by the number of gates used for every single functional unit with each additional communication channel. Therefore, it is the object of the present invention to improve the efficiency of the chip design in a telecommunication network element of the kind specified above . The invention solves these problems by providing a telecommunication network element with means such said multiplexing unit, said combinational unit, said storing unit, and said control unit are logically separated from each other on the die, and that the plurality of communication channels are multiplexed by said multiplexing unit into one multiplexed output signal, the multiplexed output signal is processed by said combinational unit in time multiplex, where said combinational unit represents one same Boolean equation for each channel separately, and that said result of the combinational unit is stored by said storing unit for each channel individually, and that said control unit controls the interworking between said parallel to serial converter, said combinational unit, and said storing unit . S uch a telecommunication network element allows an efficient chip design. Only one combinational unit is used by all communication channels in time multiplex. The result of the combinational unit is stored in the storing unit, for each channel individually, for instance as a state vector. By separating the combinational unit from the storing unit, the die size can be used more efficiently. The combinational unit can be reused for different processes, because the functionality is separated from the storing unit. The interworking between the storing unit and the combinational unit has to be monitored and controlled by a control unit. This control unit decides which communication channel will be served by the combinational unit next, which state vector is stored in the storing unit and which state vector is passed to the next combinational unit or to the output of the network element. The number of gates used on the die is increased by the control unit. But the overall number of gates used for realisation of a certain functionality is less than the number of gates used by a conventional solution. This is because the combinational unit can be used by all channels separately. Thus the combinational unit is only realised once. The number of communication channels has no effect on the number of gates used for the combinational unit. Only the RAM size has to be adapted to the number of communication channels, because for each communication channel an address range in the storing unit is reserved. The telecommunication network element can further comprise means for mapping the signals from one communication network to another communication network, where the communication networks have different clock frequencies. Thus it is possible to have a common design for the combinational unit without taking care of the number of communication channel being processed. Only the size of the storing unit has to be adapted to the number of channels. The telecommunication network element can further be implemented in a way that said combinational unit comprises a serial to parallel converter, a mapping buffer write controller, a mapping buffer, a mapping buffer read controller, a phase detector, and a byte multiplexer, and that at least one byte buffer is associated to the serial to parallel converter, and that at least one storage element is associated to the mapping buffer write controller, and that the mapping buffer comprises storage elements for each channel individually, and that at least one storage element is associated to the mapping buffer read controller, and that at least one storage element is associated to the phase detector, and that at least one storage element is associated to one said byte multiplexer. The serial to parallel (S/P) converter fill level, which is the number of bits stored in the at least one byte buffer, depends on the frequency jitter of the first communication network. By using the at least one byte buffer, it is possible to monitor the number of bits currently stored in the S/P converter. The write controller calculates the physical storage address for writing channel data in the mapping buffer by using the associated storage element that stores the address of the previously stored channel. By using the mapping buffer it is possible to compensate a frequency offset between the first and the second communication network. The read controller calculates the physical read address for reading channel data in the mapping buffer by using the associated storage element that stores the address of the previously stored channel and the fill level of said at least one storage element associated to said byte multiplexer. The phase detector calculates the overall buffer fill level. Thus it is possible to justify frequency jitter in a bit resolution. By using the multiplexer, it is possible to multiplex the communication channels of the first communication network into a second communication network with, for example, another bit order or another clock frequency. The write controller of the telecommunication network element can further comprise means for generating a write address for storing data in said mapping buffer. Thus the storage address is calculated in the write controller and the buffer fill level can be monitored in the write controller. By calculating the write address in the write controller, storage conflicts can be avoided. The write controller of the telecommunication network element can further comprise means for initiating a mapping buffer initialisation. Thus the mapping buffer can be initialised for different operation modes and in case of a failure. The write controller of the telecommunication network element can further comprise means for setting an alarm signal. Thus it is possible to set an alarm signal in the output signal. The write controller of the telecommunication network element can further comprise means for setting a buffer overflow or underflow interrupt. Thus it is possible to react to an over- or underflow of the mapping buffer. The write controller of the telecommunication network element can further comprise means for setting status bits in the S/P converter. Thus the write controller can set status bits in the S/P converter. As an example, the S/P converter might comprise a status bit, that tells whether the content of one of the byte buffers has already been written to the mapping buffer or not. This status bit could be set by the write controller. A telecommunication network element for synchronous mapping of a signal that is characterised in that the storage element of the mapping buffer consists of a plurality of bits, where at least one bit is used for a time slot marker and a plurality of bits are used for channel data is a further implementation of the invention . By adding a time slot marker to the data stored in the mapping buffer, it is possible to recognise the beginning of a signal frame. Thus the mapping can be done in a way, that each frame of the first communication network is mapped into a corresponding frame of the second communication network. The phase detector of the telecommunication network element can further comprise means for receiving the fill level of the at least one byte buffer from the S/P converter, means for receiving the write position, and means for receiving the read position, and means for receiving the fill level of said storage element of said byte multiplexer. Because the bit timing information in a resource shared architecture gets lost and only byte timing information is available, it is necessary to recover the bit timing information to enable timing justifications on a per bit basis. By enabling the phase detector to read the fill level of all storage elements, it is possible for the phase detector to calculate the overall fill level of the functional unit. The justification events shall be spread over time regularly. Therefore the phase detector calculates a pseudo average fill level, which means, that the average of the fill level does not react to short time frequency jitters and smoothens the justification and mapping jitter in the second telecommunication network. The write controller of the telecommunication network element can further comprise means for synchronisation between the functional unit and a pointer generator which is associated to a tributary unit. Thus the justification events can be generated by a pointer generator and controlled by the write controller. The read controller of the telecommunication network element can further comprise means for providing a frame alignment signal. By providing a frame alignment signal a pointer generator can be synchronised with the input signal . The multiplexer of the telecommunication network element can further comprise at least one byte buffer, and the phase detector can comprise means for receiving the fill level of the at least one byte buffer from the serial to parallel converter, and means for receiving the write position, and means for receiving the read position, and means for receiving the fill level of the at least one byte buffer from the multiplexer. Thus an asynchronous mapping of communication network signals is possible. The invention can be implemented such that the first communication network is a plesiochronous digital hierarchy (PDH) network and the second network is a synchronous digital hierarchy (SDH) . Thus it is possible to map a plurality of communication channels of a PDH network into a plurality of communication channels of a SDH network. The invention can be implemented such that the the first communication network is a synchronous digital hierarchy (SDH) network and the second network is a plesiochronous digital hierarchy (PDH) . Thus it is possible to map a plurality of communication channels of a SDH network into a plurality of communication channels of a PDH network. A method for sharing resources on a single die in a telecommunication network element by using at least one combinational unit, at least one storing unit, at least one control unit, and at least one multiplexing unit, with said combinational unit, said storing unit, said control unit, and said multiplexing unit are logically separated from each other on said die, and where said plurality of communication channels are processed by said combinational unit in ~ ime multiplex, where said combinational unit represents one same Boolean equation for each channel separately, and where the result of the combinational unit is stored by said storing unit for each channel individually, and where the stored data is multiplexed by said multiplexing unit into one multiplexed output signal, and where said control unit controls the interworking between said multiplexing unit, said combinational unit, and said storing unit, is also disclosed. Such a method makes the design process for telecommunication network elements much easier, because a combinational unit can be reused in other designs when it has been designed once. The invention and the various features thereof may be fully understood from the following description, when read together with the accompanying drawings in which: Fig. 1 is a block diagram showing the prior art approach; Fig. 2 is a block diagram showing the approach according to an embodiment of the invention; Fig. 3 is a more detailed block diagram showing the mapping of communication channels; Fig. 4 is a block diagram showing the sources for fill level averaging; and Fig. 5 is a diagram showing the justification thresholds . The following description in addition with the figures is one possible implementation of the invention and shall not restrict the invention to its content. Fig. 1 shows a telecommunication network element with a plurality of communication channels 101 at its input. Each channel is processed by a combinational unit 102 and the result of the combinational unit is stored in a storing unit 103 . Usually, a communication channel is processed by more than one combinational units, that are placed behind the storing unit of the previous processing step. After being processed by the combinational units , the communication channels are being multiplexed by a multiplexer 104 into one output signal 105. It is obvious, that for each communication channel a processing line consisting of combinational units 102 as well as storing units 103 has to be provided on the same die. Thus the number of gates used for realising such a telecommunication network element grows with every additional communication channel . Fig. 2 shows a telecommunication network element according to the invention. A plurality of communication channels from one telecommunication network 201 is multiplexed by a multiplexing unit 202 into one time division signal 203. The data of the incoming communication channels 201 is bit serial. At first, the bit serial data is converted into byte parallel data in the multiplexing unit 202. After that, the multiplexing unit multiplexes the byte parallel data into one time division signal 203. The combinational unit 204 processes the multiplexed signal 203 in time multiplex. The result of the combinational unit is stored in the storing unit 205 as a state vector for each channel individually. The storing unit and the combinational unit receive a frequency clock signal 208 for synchronisation, respectively. The control unit 206 controls the multiplexing unit 202 by using a control signal 209, the output of the storing unit 205, as well as the storing of state vectors in the storing unit is controlled by a control signal 210 of the control unit 206. The output 207 of such a functional unit is passed to a following functional unit or to the output of the telecommunication network element. It is obvious, that only one combinational unit is used in time multiplex for the plurality of communication channels. The storing unit 205 has to be adapted to the number of communication channels, because each communication channel needs an address range in the storing unit, so that the output of the combinational unit 204 can be stored in the storing unit before it is processed by a next combinational unit, or linked to the output of the telecommunication network element . Fig. 3 shows a telecommunication network element for asynchronous mapping of a plurality of communication channels of a plesiochronous digital hierarchy network into an output signal of a synchronous digital hierarchy network. The serial to parallel (S/P) converter 302 comprises at least one byte buffer as well as a serial to parallel converter logic. It comprises means for receiving a 2M data stream 301, and a reset byte ready signal. The byte buffer fill level and data bits are send to the phase detector 305 and the S/P converter output data stream is send to the mapping buffer 304. The incoming 2M serial data stream is mapped consecutively into a first byte buffer and after the first byte buffer has been filled the data is written into a second byte buffer. After one byte buffer has been filled, the data is written to the output stream as a bit parallel 2M data stream. After the content of the byte buffer has been written to the data stream, this byte buffer can be filled again with new incoming data. After the data is written onto the parallel 2M data stream, a monitoring bit is set. This bit indicates that the data have been written on the data stream, but not yet into the mapping buffer. After the data have been written into the mapping buffer 304, this status bit is reset. The overall fill level of the byte buffers is monitored in the S/P converter and indicated to the phase detector 305. The mapping buffer 304 comprises physical storage elements for storing channel data being received from the S/P converter 302, it also comprises means for receiving a 2M data stream, 2M data frame alignment signals, and write as well as read addresses. The mapping buffer 304 further comprises means for sending a 2M data frame alignment signal and a 2M data stream. The incoming 2M data stream is written into the storage elements according to the write address, which is set by the mapping buffer write controller 303. The output data is written from the storage element, which is set by the mapping buffer read controller 306. The mapping buffer write controller 303 comprises means for receiving a 2M channel valid signal, a 2M channel address signal, a pointer generator synchronisation signal from a tributary unit (not shown) , a 2M data frame alignment signal, a control signal, a reset acknowledge signal, and a buffer under/overflow signal. It also comprises means for sending a load new pointer signal to the tributary unit, a write address signal to the mapping buffer 304, a byte write address signal to the phase detector 305, and a reset byte ready flag signal to the S/P converter 302. The mapping buffer write controller 303 controls the writing of the 2M data stream into the mapping buffer 304 by setting the physical storage element address for each channel individually. The write address is send to the phase detector 305 and after the data is written into the mapping buffer 304, the byte ready flag in the S/P converter 302 is reset. The mapping buffer write controller 303 also serves as a master for initiating a mapping buffer initialisation, and for setting an alarm signal in the output data stream, and for setting a buffer under or overflow interrupt. The phase detector 305 incorporates the following functions : 1. Calculation of the overall buffer fill; 2. Monitoring the mapping buffer for buffer under/overflow; 3. Averaging the overall buffer fill; 4. Generating Justification Control signals by threshold comparisons; 5. Passing control information from write to read side of the mapping buffer. The phase detector 305 comprises means for receiving the byte write address, the S/P fill level and the status of the byte ready flag, the byte read address, a justification buffer fill signal, and a control signal. It also comprises means for sending a buffer under/overflow signal, and a justification request signal . By receiving the byte read address, the byte write address, the S/P fill level, and the justification buffer fill level, the phase detector is able to calculate an overall buffer fill level. With the buffer fill level and the result of the previous fill level calculation, the phase detector 305 is able to calculate an overall buffer fill average. As will be described with Fig. 5, the average is compared to thresholds, and thus the phase detector 305 decides whether justifications have to be taken or not. By comparing the byte read with the byte write address, the phase detector 305 is able to detect a buffer under/overflow and in such a case an interrupt signal is send. The mapping buffer read controller 306 comprises means for receiving a 2M data frame alignment signal, a tributary unit channel valid signal, a tributary unit channel address signal, a control signal, a read address update enable signal, and a reset acknowledge signal. It also comprises means for sending a read address signal, a byte read address signal, and a 2M frame alignment signal. In the mapping buffer read controller 306, the read address is calculated, from which the data is read. This address is also passed to the phase detector 305 for the overall buffer fill calculation. By receiving the tributary unit signals, the mapping buffer read controller 305 is enabled to update the byte read address with every valid tributary unit cycle. The read address will be stored in the associated storing unit, so that it is available for the next read address calculation. The C 12 byte multiplexer 307 comprises means for receiving the 2M data signal, a control signal, a tributary unit channel valid signal as well as a channel address signal, a service channel data signal, a VC-12 marker signal, a justification request signal, and a reset acknowledge signal. It also comprises means for sending a justification buffer fill signal, a read address update enable signal, a C-12 data signal, and a tributary unit C-12 pointer justification request signal. The C-12 byte multiplexer comprises the following functions : 1. C-12 byte multiplexing, building up a C 12 container; 2. Bit-base justification + justification counter; 3. Justification buffer controller; 4. 2M alarm signal insertion; 5. Passing pointer justification request to pointer generator; 6. Adding service channel or μP bytes to the output stream. The received data from the mapping buffer 304 is multiplexed into a C 12 data container. As there are timing differences between the PDH network and the SDH network, justifications have to be performed. During a justification event, bits are stuffed into the output signal, where these bits have no relation to the input signal. By adding the justification bits into the output signal, a mapping jitter occurs in the output signal. To achieve a low mapping jitter, it is necessary to spread the justification events regularly over time. This is possible by using the phase detector, which is able to calculate the overall buffer fill level on a bit basis. Thus it is possible to insert single stuffing bits, by which a low mapping jitter is archived. Fig. 4 shows a phase detector 401, that receives fill level signals from the S/P converter 403, the mapping buffer 402, and the justification buffer 404. The fill level of the mapping buffer 402 can only be measured in byte resolution. To enable the byte multiplexer to perform bit based justifications, the overall buffer fill level calculation in the phase detector 401 has to be performed on a bit basis. Thus the fill level of the S/P converter 403 is measured in bit resolution as well as the fill level of the justification buffer 404. With this information, the phase detector 401 is able to calculate the fill level in bit resolution. To spread the justification events regularly over time, the overall buffer fill level is compared in the phase detector 401 with justification thresholds, as shown in Fig. 5. The buffer centre represents the average buffer fill size. The normal upper and lower thresholds represent the points, were justification events have to be initiated. In case of the upper threshold, a negative justification request is initiated, which results that one payload bit more per VC-12 multiframe must be inserted in asynchronous mapping mode or one byte more per every 4th TU-12 multiframe must be inserted in synchronous mapping mode. In case of the lower threshold, a positive justification request is send. In such a case one payload bit less per VC-12 multiframe must be inserted in asynchronous mode or on byte less per every 4th TU-12 multiframe must be inserted in byte synchronous mode. In case the buffer size reaches the emergency thresholds, justification events are initiated immediately. By comparing the average buffer fill level with the actual buffer fill level, it is possible to detect a drift between these two values. The drift thresholds are used to check that there is now contradirectional drift between these two values.

Claims: Claims 1. Telecommunication network element with means for sharing resources on a single die by a plurality of communication channels (201), these means comprise at least one multiplexing unit (202), and at least one combinational unit (204), and at least one storing unit (205) , and at least one control unit (206) , characterised in that said multiplexing unit (202), said combinational unit (204), said storing unit (205), and said control unit (206) are logically separated from each other on said die, and that said plurality of communication channels (201) are multiplexed by said multiplexing unit (202) into one multiplexed output signal (203), and that said multiplexed output signal (203) is processed by said combinational unit (204) in time multiplex, where said combinational unit (204) represents one same Boolean equation for each channel separately, and that the result of the combinational unit is stored by said storing unit (205) for each channel individually, and that said control unit (206) controls the interworking between said multiplexing unit (202), said combinational unit (204), and said storing unit (205) . 2. Telecommunication network element according to claim 1, characterised in that said network element provides means for mapping of signals from a plurality of communication channels (201) from one first communication network to one second communication network. Telecommunication network element according to claim 1 or 2, characterised in that the combinational unit (204) comprises a serial to parallel converter (302), and a mapping buffer write controller (303) , and a mapping buffer (304), and a mapping buffer read controller (306) , and a phase detector (305) , and a byte multiplexer (307), and that at least one byte buffer is associated to said serial to parallel converter (302), and that at least one storage element is associated to said mapping buffer write controller (306), and that the mapping buffer (304) comprises storage elements for each channel individually, and that at least one storage element is associated to said mapping buffer read controller (306) , and that at least one storage element is associated to said phase detector (305) , and that at least one storage element is associated to said byte multiplexer (307) . Telecommunication network element according to claim 1 or 3, characterised in that the write controller (303) comprises means for generating a write address for storing data in said mapping buffer (304) . 5. Telecommunication network element according to claim 1 or 3, characterised in that the write controller (303) comprises means for initiating a mapping buffer initialisation. 6. Telecommunication network element according to claim 1 or 3, characterised in that the write controller (303) comprises means for setting an alarm signal. 7. Telecommunication network element according to claim 1 or 3, characterised in that the write controller (303) comprises means for setting a buffer overflow or underflow interrupt. 8. Telecommunication network element according to claim 1 or 3, characterised in that the write controller (303) comprises means for setting status bits in said serial to parallel converter . 9. Telecommunication network element according to claim 1 or 3 for synchronous mapping of a signal, characterised in that said storage element of said mapping buffer (304) consists of a plurality of bits, where at least one bit is used for a time slot marker and a plurality of bits are used for channel data. 10. Telecommunication network element according to claim 1 or 3, characterised in that that said phase detector (305) comprises means for receiving the fill level of the at least one byte buffer from said serial to parallel converter (302), and means for receiving the write position of said mapping buffer (304), and means for receiving the read position of said mapping buffer (304), and means for receiving the fill level of said storage element of said byte multiplexer (307) . 11. Telecommunication network element according to claim 1, 3 or 9, characterised in that said write controller (303) comprises means for synchronisation between said functional unit and a pointer generator. 12. Telecommunication network element according to claim 1 or 3, characterised in that said read controller (306) comprises means for providing a frame alignment signal, and means for generating a read address for reading data in said mapping buffer (304) . 13. Telecommunication network element according to claim 1 or 3 for asynchronous mapping of a signal, characterised in that said multiplexer comprises at least one byte buffer, and that said phase detector comprises means for receiving the fill level of said at least one byte buffer from said serial to parallel converter, and means for receiving the write position, and means for receiving the read position, and means for receiving the fill level of said at least one byte buffer from said multiplexer. 14. Telecommunication network element according to claim 1, characterised in that the first communication channel of the plurality of communication channels is a plesiochronous digital hierarchy (PDH) channel and the second channel is a synchronous digital hierarchy (SDH) channel. 15. Telecommunication network element according to claim 1, characterised in that the first communication channel of the plurality of communication channels is a synchronous digital hierarchy (SDH) channel and the second channel is a plesiochronous digital hierarchy (PDH) channel. 16. Method for sharing resources on a single die in a telecommunication network element by using at least one combinational unit, and at least one storing unit, and at least one control unit, and at least one multiplexing unit, characterised in that said combinational unit, said storing unit, said control unit, and said multiplexing unit, are logically separated from each other on said die, and that said plurality of communication channels are processed by said combinational unit in time multiplex, where said combinational unit represents one same Boolean equation for each channel separately, and that the result of the combinational unit is stored by said storing unit for each channel individually, and that the stored data is multiplexed by said multiplexing unit into one multiplexed output signal, and that said control unit controls the interworking between said combinational unit, said storing unit, and said multiplexing unit.

Inventors: KAEUFER UWE, KAEUFER, UWE
Applicants: KAEUFER UWE, NOKIA NETWORKS OY, KAEUFER, UWE
Application year: 2000
Main classification: H04J3
IPC codes: H04J3