VLIW processor and program code compression device and method

Abstract: A VLIW processor includes a plurality of containers (2, 3) holding a plurality of sub-instructions in a VLIW instruction, an exchanging portion (8) exchanging the plurality of sub-instructions held in the plurality of containers (2, 3) and inputting the instructions to the plurality of containers (2, 3), a plurality of decoders (4, 5) decoding the sub-instructions held in the plurality of containers (2, 3), and a plurality of processing units (6, 7) executing the sub-instructions decoded by the plurality of decoders (4, 5). Since the exchanging portion (8) exchanges a plurality of sub-instructions held in the plurality of containers (2, 3) and inputs the instructions to the plurality of containers (2, 3), a compressed code can be executed in such an execution sequence that is taken prior to compression.

Description: BACKGROUND OF THE INVENTION Field of the Invention The present invention relates to VLIW (Very Long Instruction Word) processors and more particularly to a VLIW processor which executes a compressed program code, a code compression device which compresses a program code, a code compression method, and a medium on which a code compression program is recorded. Description of the Background Art There have been increasing demands for improved processor performance in various fields such as multimedia processing and high resolution image processing. However, the current LSI (Large Scale Integration) manufacturing technique has a limit in attaining higher device speed. Therefore, VLIW processors have been drawing attention and actively researched and developed. The VLIW processor which contains a plurality of processing units aims to improve the performance of a program-controlled processor by executing a plurality of instructions in the same cycle and thus increasing parallelism. In the VLIW processor, a processing unit corresponding to an instruction field is predetermined and therefore not all the instruction slots are filled with valid instructions. Thus, a nop (no operation) instruction, as an invalid instruction, is inserted in a code, resulting in the essential problem of low code density. The VLIW processor in which two instructions are simultaneously issued cannot simultaneously execute "load mem (100) → R1" and "add R1, R2 → R3" as shown in code example 1 below. code example 1: code number instruction sequence for left sub-instructions instruction sequence for right sub-instructions 1 store R0 → mem (200) : sub R4, R5 → R6 2 load mem (100) → R1 : nop 3 nop : add R1, R2 → R3 In the following the terms "instruction" and "sub-instruction" will be used to denote the same subject matter, contrary to VLIW (see below). Since one of them is an instruction to load a value to a register R1 and the other is an instruction to refer to the value of the same register R1, the instructions cannot be executed at the same time. In this case, a nop instruction is inserted as shown in code example 1. In the following description, a long instruction formed by combining two instructions is called a VLIW (Very Large Instruction Word) instruction and each instruction included in the VLIW instruction (load, nop and add instructions in code example 1) is called a sub-instruction or instruction. Inventions disclosed in H. Sato, T. Yoshida, M. Matsuo, T. Kengaku and K. Tsuchihashi; "A Dual-Issue RISC Processor for Multimedia Signal Processing," IEICE Trans. Electron., vol. E81-C, No. 9, Sep. 1998 and Japanese Patent Laying-Open No. 9-84004 aim to solve the problem above. According to these inventions, code compression is carried out by separating a VLIW instruction, which includes instructions to be executed originally at the same time, into two sub-instructions and executing the sub-instructions. In other words, "load mem (100) → R1" and "add R1, R2 → R3" are described as one VLIW instruction, and the VLIW instruction is divided into two cycles during execution to separately execute the sub-instructions as shown in code example 2 below. code example 2: code number instruction sequence for left sub-instructions instruction sequence for right sub-instructions 1 store R0 → mem (200) : sub R4, R5 → R6 2 load mem (100) → R1 : add R1, R2 → R3 For this operation, FM (Format-Specifying) bits are assigned to lower order two bits of the 32-bit VLIW instruction, and the instruction is executed by processor in the following manner according to the FM bit pattern. (1) FM=00 : simultaneously execute two sub-instructions (2) FM=01: execute the left sub-instruction and then execute the right sub-instruction (3) FM=10 : execute the right sub-instruction and then execute the left sub-instruction (4) FM=11 : execute two sub-instructions by regarding the two sub-instructions as one long instruction Since the operation mode in the case of FM=11 is irrelevant to the present invention, it will not be described in detail. Fig. 1 schematically shows relations between FM bits and instruction execution. Code example 1 is described as code example 3 below. code number FM instruction sequence for left sub-instructions instruction sequence for right sub-instructions 1 00 store R0 → mem (200) : sub R4, R5 → R6 2 01 load mem (100) → R1 : add R1, R2 → R3 In executing code example 3, a processor executes instructions as shown in execution sequence example 1. step number instruction sequence for left sub-instructions instruction sequence for right sub-instructions 1 store R0 → mem (200) : sub R4, R5 → R6 2 load mem (100) → R1 : 2' : add R1, R2 → R3 In the 2nd cycle, an arithmetic unit corresponding to the add instruction assumes the non-operation state and carries out substantially the same operation as execution of the nop instruction. In the 2'nd cycle, an arithmetic unit corresponding to the load instruction assumes the non operation state and carries out substantially the same operation as execution of the nop instruction. Therefore, execution sequence example 1 is equivalent to execution of code example 1. Since instructions are stored in an instruction memory in the format of code example 3, they are compressed to 2/3 times the capacity compared with code example 1. In the conventional VLIW processor above, the order of describing sub-instructions can be determined more freely and the code density can be improved by adding FM bits to a VLIW instruction. Since the FM bits are assigned to two bits of an instruction field, however, the number of instruction types is limited. Further, instructions need to be mapped prior to instruction decoding, which increases circuit delay. Since the exchanging portion exchanges a plurality of sub-instructions and inputs them to the plurality of containers, a compressed code can be executed in such an execution sequence that is taken prior to compression. From the US-Patent 5 475 824 a VLIW processor according to preamble of claim 1 can be taken. If an operand interference occurs a mov instruction is first issued to a first pipe while a NOP instruction is issued to a second pipe. An add instruction is issued to first pipe in the following cycle. An instruction subsequent to that add instruction is issued to the second pipe. A sequential order of steps is executed. SUMMERY OF THE INVENTION It is an object of the present invention to provide a VLIW processor capable of processing a compressed program in such an execution sequence that is taken prior to compression without assigning a special bits to an instruction field, which preferably corresponds to the VLIW method of at least 3-ways, capable of processing a compressed program in such an execution sequence that is taken prior to compression, and which preferably corresponds to the 2 n-way VLIW method, capable of processing a compressed program in such an execution sequence that is taken prior to compression. Such an object is solved by a VLIW processor according to claim 1. Preferred developments of the invention are given in the dependent claims. The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 schematically shows relations between FM bits used in a conventional VLIW method and instruction execution. Fig. 2 schematically shows a VLIW processor in a first embodiment. Fig. 3 is a block diagram showing a schematic structure of the VLIW processor in the first embodiment. Fig. 4 is a block diagram showing a schematic structure of a VLIW processor in a second embodiment. Fig. 5 is a block diagram showing a schematic structure of a code compression device in a fourth embodiment. Fig. 6 is a flow chart for describing a processing procedure of the code compression device in the fourth embodiment. Fig. 7 shows an example of the external view of the code compression device in the fourth embodiment. Fig. 8 is a schematic structure of computer 41 shown in Fig. 7. Fig. 9 schematically shows a VLIW processor in a sixth embodiment. Fig. 10 schematically shows a VLIW processor in a seventh embodiment. Fig. 11 shows a schematic structure of the VLIW processor in the seventh embodiment. DESCRIPTION OF THE PREFERRED EMBODIMENTS First Embodiment A VLIW processor in a first embodiment of the present invention will be described in the following. Terms used in this embodiment will be described first. A "main cycle" refers to a cycle when an instruction is issued, that is, a cycle in which step numbers are indicated only by numerals in an execution sequence. A "sub cycle" refers to a cycle executed one cycle after the main cycle, that is, a cycle in which step numbers are indicated by numerals with dashes (') in an execution sequence. The sub cycle is not always executed after the main cycle. A "left container" refers to the left one of instruction buffers in which VLIW instructions are placed. A "left instruction decoder" refers to a decoder which decodes an instruction placed in the left container. A "left processing unit" refers to a processing unit which executes the instruction decoded by the left instruction decoder. A "left sub-instruction" (or "left instruction") belongs to an instruction sequence for left sub-instructions (or left instructions), that is, an instruction which is predetermined to be processed in the left processing unit. A "right container" refers to the right one of instruction buffers in which VLIW instructions are placed. A "right instruction decoder" refers to a decoder which decodes an instruction placed in the right container. A "right processing unit" refers to a processing unit which executes the instruction decoded by the right instruction decoder. A "right sub-instruction" (or "right instruction") belongs to an instruction sequence for right sub-instructions (or right instruction), that is, an instruction which is predetermined to be processed in the right processing unit. Fig. 2 schematically shows a VLIW processor in this embodiment. The VLIW processor includes an instruction memory 1, a left container 2, a right container 3, a left instruction decoder 4, a right instruction decoder 5, a left processing unit 6, and a right processing unit 7. As shown in Fig. 2, left and right containers 2 and 3 perform a swapping operation to exchange their sub-instructions. The processing rule of VLIW instructions will be described in the following. (1) When a left sub-instruction 1 is issued to the left container and a right sub-instruction 2 is issued to the right container, these two sub-instructions are simultaneously transferred to corresponding instruction decoders. In the main cycle, the sub-instructions are decoded by the decoders and simultaneously executed by corresponding processing units. In this case, a sub cycle is not caused. (2) When a left sub-instruction 3 is issued to the left container and a left sub-instruction 4 is issued to the right container, these two sub-instructions are simultaneously transferred to corresponding instruction decoders. In the main cycle, left sub-instruction 3 is decoded by the left decoder and executed in the left processing unit. Meanwhile, the right decoder fails to decode left sub-instruction 4 and deals with it as a nop instruction because it is invalid, and left sub-instruction 4 is not processed in the right processing unit. At the same time, existence of the instruction associated with the instruction sequence for left sub-instructions is detected in the right container, and the contents of the left and right containers are exchanged. In the sub cycle, left sub-instruction 4 is decoded by the left decoder and executed in the left processing unit. Meanwhile, the right decoder fails to decode left sub-instruction 3 and deals with it as a nop instruction because it is invalid, and left sub-instruction 3 is not processed in the right processing unit. That is, a VLIW instruction which includes left sub-instruction 3 and a right nop instruction is executed in the main cycle, and a VLIW instruction which includes left sub-instruction 4 and a right nop instruction is executed in the sub cycle. (3) When a right sub-instruction 5 is issued to the left container and a right sub-instruction 6 is issued to the light container, these two sub-instructions are simultaneously transferred to corresponding instruction decoders. In the main cycle, right sub-instruction 6 is decoded by the right decoder and executed in the right processing unit. Meanwhile, the left decoder fails to decode right sub-instruction 5 and deals with it as a nop instruction because it is invalid, and right sub-instruction 5 is not processed in the left processing unit. At the same time, existence of the instruction associated with the instruction sequence for right sub-instructions is detected in the left container, and the contents of the left and right containers are exchanged. In the sub cycle, right sub-instruction 5 is decoded by the right decoder and executed in the right processing unit. Meanwhile, the left decoder fails to decode right sub-instruction 6 and deals with it as a nop instruction because it is invalid, and right sub-instruction 6 is not processed in the left processing unit. That is, a VLIW instruction which includes right sub-instruction 6 and a left nop instruction is executed in the main cycle, and a VLIW instruction which includes right sub-instruction 5 and a left nop instruction is executed in the sub cycle. (4) When a right sub-instruction 7 is issued to the left container arid a left sub-instruction 8 is issued to the right container, these two sub-instructions are simultaneously transferred to corresponding instruction decoders. In the main cycle, the left decoder fails to decode right sub-instruction 7 and deals with it as a nop instruction because it is invalid, and right sub-instruction 7 is not processed in the left processing unit. Meanwhile, the right decoder fails to decode left sub-instruction 8 and deals with it as a nop instruction because it is invalid, and left sub-instruction 8 is not processed in the right processing unit. At the same time, existence of the instruction associated with the instruction sequence for right sub-instructions is detected in the left container, and existence of the instruction associated with the instruction sequence for left sub-instructions is detected in the right container. Thus, the contents of the left and right containers are exchanged. In the sub cycle, right sub-instruction 7 is decoded by the right decoder and executed in the right processing unit. Meanwhile, left sub-instruction 8 is decoded by the left decoder and executed in the left processing unit. That is, a VLIW instruction which includes a right nop instruction and a left nop instruction is executed in the main cycle, and a VLIW instruction which includes right sub-instruction 7 and left sub-instruction 8 is executed in the sub cycle. Fig. 3 is a block diagram showing a schematic structure of the VLIW processor in this embodiment. The VLIW processor includes an instruction memory 1, a left container 2, a right container 3, a left instruction decoder 4, a right instruction decoder 5, a left processing unit 6, a right processing unit 7, an exchanging portion 8 which exchanges the contents of left and right containers 2 and 3, a program counter 9, a branch target register (BTR) 10, selectors 11 and 12, an incrementer 13, and a control system 14 which controls the entire processor. Instruction memory 1 includes a plurality of memory cells 15, and an address decoder 16 which decodes the contents of program counter 9 to select memory cell 15. Exchanging portion 8 includes a register 17 which holds the contents of left container 2, a register 18 which holds the contents of right container 3, and selectors 19 and 20. Left container 2, right container 3, program counter 9 and branch target register 10 hold input signals at a rise of a clock signal not shown. Registers 17 and 18 hold input signals at a fall of the clock signal. When left and right containers 2 and 3 hold sub-instructions from instruction memory 1 in one cycle, therefore, they can exchange and receive the sub instructions in the next cycle. For main cycle processing, control system 14 controls so that selector 11 selects the output of incrementer 13, selector 12 selects the output of selector 11 and selectors 19 and 20 select the outputs of instruction memory 1. For sub cycle processing, control system 14 controls so that selector 11 selects the outputs of program counter 9, selector 12 selects the output of selector 11 and selectors 19 and 20 select the outputs of registers 18 and 17, respectively. In writing operation to program counter 9 shown in Fig. 3, it is controlled so that the output of branch target register 10 is given priority over the output of incrementer 13. This is because programmers coded instructions while a nop instruction is inserted as in code example 1 described in the prior art and therefore if branching is found before the cycle of code number 3, the branch has to be given priority without executing "add R1, R2 → R3" as a sub cycle. It is assumed as an example that a programmer made the program of code example 4 below. code example 4: code number instruction sequence for left sub-instructions instruction sequence for right sub-instructions 1 store R0 → mem (200) : nop 2 load mem (100) → R1 : nop 3 shift R4, R5 → R6 : add R1, R2 → R3 This code example 4 program is converted into code example 5 below by a code compression algorithm described below. code example 5: code number instruction sequence for left sub-instructions instruction sequence for right sub-instructions 1 store R0 → mem (200) : load mem (100) → R1 2 shift R4, R5 → R6 : add R1, R2 → R3 When the VLIW processor in this embodiment executes the code example 5 program, the execution sequence is as follows. execution sequence example 2: step number instruction sequence for left sub-instructions instruction sequence for right sub-instructions 1 store R0 → mem (200) : nop [load mem (100) → R1] 1' load mem (100) → R1 : nop [store R0 → mem (200)] 2 shift R4, R5 → R6 : add R1, R2 → R3 Here, "nop [load mem (100) → R1]" means that when a left sub-instruction "load mem (100) → R1" is issued to the instruction sequence for right sub-instructions, the instruction is processed as a nop instruction. Hereinafter, the description of "nop [ ]" means that when a right sub-instruction is issued to the instruction sequence for left sub-instructions or when a left sub-instruction is issued to the instruction sequence for right sub-instructions, the instruction is processed as a nop instruction. As described above, according to the VLIW processor in this embodiment, when a right sub-instruction is issued to the instruction sequence for left sub-instructions or when a left sub-instruction is issued to the instruction sequence for right sub-instructions, the sub-instructions are exchanged and processed in the sub cycle, and therefore a code-compressed program can be processed in such an execution sequence that is taken prior to compression. Second Embodiment Fig. 4 is a block diagram showing a schematic structure of a VLIW processor in a second embodiment of the present invention. The only difference from the VLIW processor in the first embodiment shown in Fig. 3 is the structure of exchanging portion 8. Therefore, detailed description of overlapped structures and functions will not be repeated. In this embodiment, the reference numeral of the exchanging portion is 8'. Exchanging portion 8' includes selectors 21 and 22. In the main cycle, control system 14 controls to selector 21 to select a sub-instruction, which belongs to the instruction sequence for left sub-instructions, from instruction memory 1, and selector 22 to select a sub-instruction, which belongs to the instruction sequence for right sub-instructions, from instruction memory 1. In the sub cycle, control system 14 controls selector 21 to select a sub-instruction, which belongs to the instruction sequence for right sub-instructions, from instruction memory 1, and selector 22 to select a sub-instruction, which belongs to the instruction sequence for left sub-instructions, from instruction memory 1. The VLIW processor in the first embodiment shown in Fig. 3 detects a transition to the sub cycle at the decode stage, and causes sub-instructions held in left and right containers 2 and 3 to be fed back and swapped. At the decode stage, therefore, the value of program counter 9 has already be incremented and a VLIW instruction read from instruction memory 1 has been updated for the next step instruction. Thus, registers 17 and 18 are necessary to feed back and swap sub-instructions in left and right containers 2 and 3. Since the VLIW processor in this embodiment can control not to increment the value of program counter 9 by detecting a transition to the sub cycle at the instruction fetch stage, there is no need to feed back, eliminating the need for circuits corresponding to registers 17 and 18. In a processor in which an instruction fetch cycle is a critical path, however, the clock rate, that is, processing speed may be lowered. As described above, according to the VLIW processor in this embodiment, a simple circuit structure and cost reduction can be attained compared with the VLIW processor in the first embodiment. Third Embodiment A VLIW processor in a third embodiment of the present invention is the same as the VLIW processor structures in the first and second embodiments. The only difference is that the nop instruction of a left sub-instruction and the nop instruction of a right sub-instruction are supported in this embodiment. Therefore, detailed description of overlapped structures and functions will not be repeated. Here, the nop instruction of a left sub-instruction is an Lnop instruction and the nop instruction of a right sub-instruction is an Rnop instruction. It is assumed as an example that a compressed code as in code example 6 below is described. code example 6: code number instruction sequence for left sub-instructions instruction sequence for right sub-instructions 1 Lnop : Lnop When the VLIW processor in this embodiment executes the program of code example 6, the program is processed as shown in execution sequence example 3 below. execution sequence example 3: step number instruction sequence for left sub-instructions instruction sequence for right sub-instructions 1 Lnop : nop [Lnop] 1' Lnop : nop [Lnop] As described above, according to the VLIW processor in this embodiment, execution corresponding to two cycles of nop instructions can be made possible by one VLIW instruction, and therefore code compression can be performed efficiently. Fourth Embodiment A fourth embodiment of the present invention relates to a code compression device (linker) which performs the above described code compression. Fig. 5 is a block diagram showing a schematic structure of the code compression device. The code compression device includes an uncompressed source code storing portion 31 which stores an uncompressed source code, a code extracting portion 32 which extracts two consecutive rows of VLIW instructions from the source code, a code compressing portion 33 which compresses the code extracted by code extracting portion 32, a code outputting portion 34 which outputs the compressed code, and a compressed source code storing portion 35 which stores the code output from code outputting portion 34. Fig. 6 is a flow chart for describing the processing procedure of code compression. First, code extracting portion 32 reads a source code to be compressed from uncompressed source code storing portion 31 (S1), and "1" is set to a variable i (S2). Then, code extracting portion 32 extracts codes of the ith code and the (i + 1)th rows from the source code (S3). Thereafter, code compressing portion 33 determines if a label has not been added to the code of the (i + 1)th row extracted by code extracting portion 32 and if at least two sub instructions of the codes of the ith and the (i + 1)th rows are nop instructions (S4). If a label has been added to the code of the (i + 1)th row, or if there is less than two sub-instructions, which are nop instructions, of the codes of the ith and the (i + 1)th rows (S4, No), step S11 is entered. If a label has not been added to the code of the (i + 1)th row and at least two sub-instructions of the codes of the ith and the (i + 1)th rows are nop instructions (S4, Yes), code compressing portion 33 determines if the code of the ith row is a combination of a left sub-instruction and a nop instruction and the code of the (i + 1)th row is a combination of a left sub-instruction and a nop instruction (S5). If the ith row is not a combination of a left sub-instruction and a nop instruction, or if the (i + 1)th row is not a combination of a left sub-instruction and a nop instruction (S5, No), step S7 is entered. If the ith row is a combination of a left sub-instruction and a nop instruction and the (i + 1)th row is a combination of a left sub-instruction and a nop instruction (S5, Yes), code compressing portion 33 compresses instructions so that the left sub-instruction of the ith row is input to left container 2 and the left sub-instruction of the (i + 1)th row is input to right container 3 (S6). Then, code outputting portion 34 stores the compressed code into compressed source code storing portion 35. In step S7, code compressing portion 33 determines if the ith row is a combination of a nop instruction and a right sub-instruction and the (i + 1)th row is combination of a nop instruction and a right sub-instruction. If the ith row is not a combination of a nop instruction and a right sub-instruction, or if the (i + 1)th row is not a combination of a nop instruction and a right sub-instruction (S7, No), step S9 is entered. If the ith row is a combination of a nop instruction and a right sub-instruction and the (i + 1)th row is a combination of a nop instruction and a right sub-instruction (S7, Yes), code compressing portion 33 compresses instructions so that the right sub-instruction of the (i + 1)th row is input to left container 2 and the right sub-instruction of the ith row is input to right container 3 (S8). Then, code outputting portion 34 stores the compressed code into compressed source code storing portion 35. In step S9, code compressing portion 33 determines if the ith row is a combination of a nop instruction and a nop instruction and the (i + 1)th row is a combination of a left sub-instruction and a right sub-instruction. If the ith row is not a combination of nop instructions, or if the (i + 1)th row is not a combination of left and right sub-instructions (S9, No), step S11 is entered. If the ith row is a combination of nop instructions and the (i + 1)th row is a combination of left and right sub-instructions (S9, Yes), code compressing portion 33 compresses instructions so that the right sub-instruction of the (i + 1)th row is input to left container 2 and the left sub-instruction of the (i + 1)th row is input to right container 3 (S10). Then, code outputting portion 34 stores the compressed code into compressed source code storing portion 35. In step S11, a determination is made as to if compression processing has been performed for all rows of the source code (S 11). If there is any row which has not been compressed (S11, No), (i + 1) is substituted for variable i and the process returns to step S3. If compression has been performed for all rows (S11, Yes), the compression process is ended. Fig. 7 shows an example of the external view of the code compression device according to the present invention. The code compression device includes a computer 41, a graphic display device 42, a magnetic tape device 43 in which a magnetic tape 44 is inserted, a keyboard 45, a mouse 46, a CD-ROM (Compact Disc-Read Only Memory) device 47 in which a CD-ROM 48 is inserted, and a communication modem 49. A code compression program is supplied by a storage medium such as magnetic tape 44 or CD-ROM 48. The code compression program is executed by computer 41, and an operator compresses source codes by operating keyboard 45 or mouse 46 while referring to graphic display device 42. The code compression program may be supplied to computer 41 from another computer via communication lines and communication modem 49. Fig. 8 is a block diagram showing an example of the structure of the code compression device according to the present invention. Computer 41 shown in Fig. 7 includes a CPU 50, a ROM (Read Only Memory) 51, a RAM (Random Access Memory) 52, and a hard disc 53. CPU 50 carries out processing by transmitting and receiving data to and from magnetic tape device 43, keyboard 45, mouse 46, CD-ROM device 47, communication modem 49, ROM 51, RAM 52, or hard disc 53. A code compression program recorded on magnetic tape 44 or CD-ROM 48 is once stored in hard disc 53 via magnetic tape device 43 or CD-ROM device 47 by CPU 50. CPU 50 compresses a source code by loading the code compression program as necessary in RAM 52 for execution. As described above, according to the code compression device in this embodiment, a source code can be compressed in a format which enables operation of the VLIW processor described in the first embodiment. Thus, capacity of an instruction memory, for example, can be used efficiently. Fifth Embodiment A code compression device in a fifth embodiment of the present invention is similar to the one in the fourth embodiment described with reference to Figs. 5 to 8. Although data dependence is not considered for code compression in the code compression device in the fourth embodiment, data independence is taken into account in the code compression device in this embodiment (in this embodiment, a scheduler function is added to the code compression device in the fourth embodiment). It is assumed as an example that the program of code example 7 below is described. code number instruction sequence for left sub-instructions instruction sequence for right sub-instructions 1 store R0 → mem (200) : sub R4, R5 → R6 2 load mem (100) → R7 : Rnop 3 Lnop : add R1, R2 → R3 Since VLIW instructions shown in code numbers 2 and 3 do not have any data independence, the codes can be changed as in code example 8 below. code number instruction sequence for left sub-instructions instruction sequence for right sub-instructions 1 store R0 → mem (200) : sub R4, R5 → R6 2 Lnop : Rnop 3 load mem (100)→ R7 : add R1, R2 → R3 The program shown in code example 8 can be compressed as in code example 9 below by the code compression device in the fourth embodiment. code example 9: code number instruction sequence for left sub-instructions instruction sequence for right sub-instructions 1 store R0 → mem (200) : sub R4, R5 → R6 2 add R1, R2 → R3 : load mem (100) → R7 When the program shown in code example 9 is executed, it is processed as shown in execution sequence example 4 below. sequence example 4: step number instruction sequence for left sub-instructions instruction sequence for right sub-instructions 1 store R0 → mem (200) : sub R4, R5 → R6 2 nop [add R1, R2 → R3] : nop [load mem (100) → R7] 2' load mem (100) → R7 : add R1, R2 → R3 By thus carrying out scheduling while taking into account data independence, codes can be compressed more efficiently. The following code example 10 is an example of codes which cannot be compressed. code example 10: code number instruction sequence for left sub-instructions instruction sequence for right sub-instructions 1 store R0 → mem (200) : sub R4, R5 → R6 2 load mem (100) → R1 : Rnop 3 Lnop : add R1, R2 → R3 Since the left sub-instruction of code number 2 "load mem (100) → R1" causes data to be loaded in register R1 and the right sub-instruction of code number 3 "add R1, R2 → R3" causes data of register R1 to be referred, compression to the same VLIW instruction cannot be performed. As described above, according to the code compression device in this embodiment, scheduling is carried out while taking into account data independence, codes can be compressed more efficiently compared with the code compression device in the fourth embodiment. Sixth Embodiment Fig. 9 schematically shows a VLIW processor in a sixth embodiment of the present invention. The VLIW processor in this embodiment has the structure formed by connecting a plurality of the VLIW processors in the first embodiment shown in Fig. 2, that is, the VLIW type processor in this embodiment is a 2n-way VLIW processor. Fig. 9 shows a VLIW processor when n = 3. As described above, the VLIW processor in this embodiment can have higher parallelism and processing speed than the VLIW processor in the first embodiment. Seventh Embodiment Fig. 10 schematically shows a VLIW processor in a seventh embodiment of the present invention. The VLIW processors in the first to sixth embodiments are the 2n-way VLIW processors which include two right and left sub-instructions, while the VLIW processor in this embodiment is based on the VLIW method of at least 3-ways which exchanges instructions by shifting them rather than exchanges instructions by swapping them. The VLIW processor in this embodiment includes an instruction memory 61, a first container 62, a second container 63, a third container 64, a fourth container 65, a first instruction decoder 66, a second instruction decoder 67, a third instruction decoder 68, a fourth instruction decoder 69, a first processing unit 70, a second processing unit 71, a third processing unit 72, and a fourth processing 73. For processing, sub-instructions are shifted from first container 62 to fourth container 65, from fourth container 65 to third container 64, from third container 64 to second container 63, and from second container 63 to first container 62. Fig. 11 is a block diagram showing a specific structure of the VLIW processor in this embodiment. The VLIW processor includes an instruction memory 61, a first container 62, a second container 63, a third container 64, a fourth container 65, a first instruction decoder 66, a second instruction decoder 67, a third instruction decoder 68, a fourth instruction decoder 69, a first processing unit 70, a second processing unit 71, a third processing unit 72, a fourth processing unit 73, an exchanging portion 74 which exchanges the contents of first to fourth containers 62 to 65 by sequentially shifting the contents, a program counter 75, a branch target register (BTR) 76, selectors 77 and 78, an incrementer 79, and a control system 80 which control the entire processor. Instruction memory 61 includes a plurality of memory cells 81, and an address decoder 82 which decodes the contents of program counter 75 to select memory cell 81. Exchanging portion 74 includes a register 83 which holds the contents of second container 63, a register 84 which holds the contents of third container 64, a register 85 which holds the contents of fourth container 65, a register 86 which holds the contents of first container 62, and selectors 87 to 90. First to fourth containers 62 to 65, program counter 75 and branch address register 76 hold input signals at a rise of a clock signal not shown. Registers 83 to 86 hold input signals at a fall of the clock signal. When first to fourth containers 62 to 65 hold sub-instructions from instruction memory 1 in one cycle, therefore, they can shift and input the sub-instructions to corresponding containers in the next cycle. For main cycle processing, control system 80 controls so that selector 77 selects the output of incrementer 79, selector 78 selects the output of selector 77, and selectors 87 to 90 select the outputs of instruction memory 1. For sub cycle processing, control system 80 controls so that selector 77 selects the output of program counter 75, selector 78 selects the output of selector 77, and selectors 87 to 90 select the outputs of registers 83 to 86, respectively. It is assumed as an example that a programmer made the program of code example 11 below. code example 11: code number instruction sequence for first sub-instructions instruction sequence for second sub-instructions instruction sequence for third sub-instructions instruction sequence for fourth sub-instructions 1 first sub-instruction 1 : nop : nop : nop 2 first sub-instruction 2 : nop : nop : nop 3 first sub-instruction 3 : nop : nop : nop 4 first sub-instruction 4 : nop : nop : nop 5 first sub-instruction 5 : second sub-instruction 6 : nop : fourth sub-instruction 7 When the program of code example 11 is compressed, it is described as in code example 12 below. code example 12: code number instruction sequence for first sub-instructions instruction sequence for second sub-instructions instruction sequence for third sub-instructions instruction sequence for fourth sub-instructions 1 first sub-instruction 1 : first sub-instruction 2 : first sub-instruction 3 : first sub-instruction 4 2 first sub-instruction 5 : second sub-instruction 6 : nop : fourth sub-instruction 7 When the program shown in code example 12 is executed by the VLIW processor in this embodiment, it is processed as in execution sequence example 5 below. execution sequence example 5: step number instruction sequence for first sub-instructions instruction sequence for second sub-instructions instruction sequence for third sub-instructions instruction sequence for fourth sub-instructions 1 first sub-instruction 1 : nop [first sub-instruction 2] : nop [first sub-instruction 3] : nop [first sub-instruction 4] 1' first sub-instruction 2 : flop [first sub-instruction 3] : nop [first sub-instruction 4] : nop [first sub-instruction 1] 1" first sub-instruction 3 : nop [first sub-instruction 4] : nop [first sub-instruction 1] : nop [first sub-instruction 2] 1"' first sub-instruction 4 : nop [first sub-instruction 1] : nop [first sub-instruction 2] : nop [first sub-instruction 3] 2 first sub-instruction 5 : second sub-instruction 6 : nop : fourth sub-instruction 7 As described above, according to the VLIW processor in this embodiment, the VLIW method of at least 3-ways can be applied, and codes can be compressed more efficiently compared with the 2n-way VLIW processor. Although the present invention has been described and illustrated in detail, it is clearly understood that the same is by way of illustration and example only and is not to be taken by way of limitation, the scope of the present invention being limited only by the terms of the appended claims.

Claims: A VLIW processor, comprising: a plurality of containers (2, 3, 62-65) holding instructions; a plurality of decoders (4, 5, 66-69), one of said decoders being connected to each of said plurality of containers (2, 3, 62-65) and decoding the instructions output from its associated of said plurality of containers (2, 3, 62-65); and a plurality of processing units (6, 7, 70-73), one of said processing units being connected to each of said plurality of decoders (4, 5, 66-69) and executing the instructions decoded by its associated of said plurality of decoders (6, 7, 70-73); characterized by an exchanging unit (8, 8', 74) updating the content held in one of said plurality of containers (2, 3, 62-65) with the content held in another of said plurality of containers (2, 3, 62-65) and updating the content held in another of said plurality of containers (2, 3, 62-65) with the content held in said one of said plurality of containers (2, 3, 62-65). The VLIW processor according to claim 1, wherein said plurality of containers (2, 3, 62-65) include a left container (2) holding a first instruction in a VLIW instruction, and a right container (3) holding a second instruction in said VLIW instruction, said plurality of decoders (4, 5, 66-69) include a left instruction decoder (4) decoding the first instruction held in said left container (2), and a right decoder (5) decoding the second instruction held in said right container (3), said plurality of processing units (6, 7, 70-73) include a left processing unit (6) executing the instruction decoded by said left instruction decoder (4), and a right processing unit (7) executing the instruction decoded by said right instruction decoder (5), said left instruction decoder (4) decodes a left instruction and outputs the instruction to said left processing unit (6) when said first instruction is the left instruction, and outputs a right instruction as a nop instruction when said first instruction is the right instruction, and said right instruction decoder (5) decodes a right instruction and outputs the instruction to said right processing unit (7) when said second instruction is the right instruction, and outputs a left instruction as a nop instruction when said second instruction is the left instruction. The VLIW processor according to claim 2, further comprising: a program counter (9-13) outputting an address to fetch a VLIW instruction, wherein in at least one of the cases when said first instruction is a right instruction and when said second instruction is a left instruction, said left instruction decoder (4) decodes said first instruction and said right instruction decoder (5) decodes said second instruction in a main cycle, in a sub cycle, said left instruction decoder (4) decodes said second instruction exchanged by said exchanging portion (8) and said right instruction decoder (5) decodes said first instruction exchanged by said exchanging portion (8), and said program counter (9-13) increments a program counter value during said main cycle processing, and keeps the program counter value unchanged during said sub cycle processing. The VLIW processor according to claim 3, wherein said program counter (9-13) includes a branch target register (10) holding a branch target address, and said program counter (9-13) preferentially outputs a value of said branch target register (10) if branching is found before said sub cycle. The VLIW processor according to claim 3, wherein said exchanging portion (8) includes a first selector (19) selecting said first instruction in said main cycle and said second instruction in said sub cycle and outputting the instructions to said left container (2), and a second selector (20) selecting said second instruction in said main cycle and said first instruction in said sub cycle and outputting the instructions to said right container (3). The VLIW processor according to claim 2, wherein said exchanging portion (8) includes a first register (17) holding the first instruction held by said left container (2) and outputting the instruction to said right container (3), and a second register (18) holding the second instruction held by said right container (3) and outputting the instruction to said left container (2). The VLIW processor according to claim 1, wherein said exchanging portion (74) sequentially shifts a plurality of instructions held in said plurality of containers (62-65) and input the instructions to said plurality of containers (62-65). The VLIW processor according to claim 1, wherein said plurality of containers (2, 3) include a (2i - 1)th container (2) holding a (2i - 1)th instruction in said VLIW instruction, and a (2i)th container (3) holding a (2i)th instruction in said VLIW instruction, with i being a natural number 1 to n, said plurality of decoders (4, 5) include a (2i - 1)th decoder (4) decoding the (2i - 1)th instruction held in said (2i - 1)th container (2), and a (2i)th decoder (5) decoding the (2i)th instruction held in said (2i)th container (3), said plurality of processing units (6, 7) include a (2i - 1)th processing unit (6) executing the instruction decoded by said (2i - 1)th decoder (4), and - a (2i)th processing unit (7) executing the instruction decoded by said (2i)th decoder (5), and said exchanging portion (8, 8') exchanges the (2i - 1)th instruction held in said (2i - 1)th container (2) and the (2i)th instruction held in said (2i)th container (3). The VLIW processor according to claim 1, comprising: a first selection circuit (19, 21, 87) selecting an instruction output from said memory (1) in a first case, selecting the instruction held in a first container (3, 63) of said plurality of containers (2, 3, 62-65) in a second case, and supplying the selected instruction to a second container (2, 62) of said plurality of containers (2, 3, 62-65), which is different from said first container, as an instruction to be held. The VLIW processor according to claim 9, further comprising a register (18,83) receiving the instruction from said first container, wherein said first selection circuit (19,87) has a first input connected to said memory (1), a second input connected to said second container and an output connected to said first container. The VLIW processor according to claim 9, wherein said first selection circuit (21) has a first input connected to said memory (1) through a first line, a second input connected to said memory (2) through a second line and output connected to said first container, said first and second lines for transferring the instructions to said first and second containers, respectively. The VLIW processor according to one of claim 9 to 11, further comprising a controller (14,80) receiving the instruction from said first container (3,63) and controlling said first selection circuit (19,21,87), wherein said plurality of decoders include first and second decoders (5,4,67,66) connected to said first and second containers, (3,2,63,62) said second decoder dealing with a predetermined kind of instruction as a nop instruction by which the processing unit connected to said first decoder performs no operations, wherein when said first and second containers hold first and second instructions, respectively, and said first instruction is said predetermined kind of instruction, by a control of said controller, said first and second decoders decode the first and second instructions, respectively, in a main cycle, and said second decoder decodes the first instruction in a sub cycle next to said main cycle. The VLIW processor according to claim 9, further comprising a second selection circuit (20,22) selecting an instruction output from said memory (1) in a third case, selecting the instruction held in said second container (2) in a fourth case and supplying the selected instruction to said first container (8) as an instruction to be held. The VLIW processor according to claim 13, further comprising a controller (14) receiving the instructions from said first and second containers (3,2) and controlling said first and second selection circuits (19,20,21,22), wherein said plurality of decoders include first and second decoders (5,4) connected to said first and second containers (3,2), said first decoder (5) dealing with a first kind of instruction as a nop instruction by which the processing unit connected to said first decoder (5) performs no operations, and said second decoder (49 dealing with a second kind of instruction as a nop instruction by which the processing unit connected to said second decoder (4) performs no operation, when said first and second containers hold first and second instructions, respectively, and in at least one of case when said first instruction is said first kind of instruction and when said second instruction is said second kind of instruction, by a control of said controller, said first and second decoders decode the first and second instructions, respectively, in a main cycle, and decode the second and first instructions, respectively, in a sub cycle next to said main cycle. The VLIW processor according to claim 12 or 14, further comprising a program counter (9-13) outputting a program counter value to said memory (1) to fetch a VLIW instruction, said program counter incrementing a program counter value and stopping the incrementation by a control of said controller.

Inventors: SUZUKI HIROAKI, SUZUKI, HIROAKI, Suzuki, Hiroaki, c/o Mitsubishi Denki K. K.
Applicants: MITSUBISHI ELECTRIC CORP, MITSUBISHI DENKI KABUSHIKI KAISHA
Application year: 2000
Main classification: G06F9
IPC codes: G06F9