TWO CLOCK DOMAIN PULSE TO PULSE SYNCHRONIZER

Abstract: A synchronization circuit (P2P) for interfacing a first digital circuit functioning with a first clock (CLK1) and a second digital circuit functioning with a second clock (CLK2) that may be different from the first clock (CLK1) in terms of frequency and/or phase is constituted by a transmitting section functioning with the first clock (CLK1), a receiving section functioning with the second clock (CLK2) and a feedback section functioning with the first clock (CLK1). A bidirectional synchronizer transfers commands with a strobe signal (STR) from a microprocessor interface (MPRI) functioning with the first clock (CLK1) to an application circuit (APL) functioning with the second clock (CLK2) and alarm signals from the application circuit (APL) to the microprocessor interface (MPRI).

Description: TWO CLOCK DOMAIN PULSE TO PULSE SYNCHRONIZER FIELD OF THE INVENTION The present invention relates to microprocessor interface synchronization circuits and in particular to a two-clock domain pulse to pulse synchronizer. The disclosed invention is particularly suited to be applied in the modular design area (macro-cell based designs). BACKGROUND OF THE INVENTION Operations in digital systems can be carried out concurrently or must obey a precedence relationship. If two operations obey a precedence relationship, then the role of synchronization is to ensure that operations are carried out in the correct order. So, in the context of digital systems, synchronization implies a set of techniques used to ensure that operations are performed in the correct order. Before introducing synchronization techniques some definitions taken from literature are given. If two isochronous signals (signals characterized by uniformly time spaced transition opportunities, that is, transition opportunity times occur at a constant frequency) have the same frequency and the instantaneous phase difference between them is null, they are said to be synchronous. Even if only one of the two previous conditions is not satisfied, the two signals are said to be asynchronous. When all signals belonging to a system are synchronous, the system itself is said synchronous. In synchronous systems a synchronization technique named Synchronous Interconnect is used. A common isochronous periodic signal named clock beat the time. More precisely, the positive clock edge beats transition opportunity times for all sequential devices (flip-flops) of the system. All signals are slaved to this clock, that is, their values are considered meaningful only at positive edges of the clock, for this reason all the memory devices used in the system are edge triggered (i.e. edge triggered flip-flops storing incoming signals on the positive clock edge). Supposing that two circuits have to exchange data, the direction of data flow is from the originating circuit or originating element to the receiving circuit or receiving element. The synchronous interconnection technique consists in connecting the signal carrying information, namely data from the originating circuit to the receiving circuit and providing the same clock to the two elements (no other subsidiary signals being required). The fundamental hypothesis is that the two circuits are clocked with the same clock, that is all the signals of the two elements, and thus data, are isochronous. By the reasons explained above the edge triggered sequential device receiving the signal data will correctly sample it. This "straightforward" method of interconnection can only be used in synchronous systems. Connecting edge triggered memory elements belonging to two different asynchronous clock domains (two domains whose clocks are asynchronous) by using the synchronous interconnection technique is not possible. In this case two problems arise: a first problem is related to metastability and a second one is related to the impossibility of determining a correct strobing point for the signal data from the receiving element; this problem is related to the protocol of communication (also named synchronization protocol) between the two elements. The first problem occurs when the variation of signal data fall into the setup/hold windows of the edge triggered memory device located in the receiving element; this, as proved in literature, can cause the memory device to go into a metastable state. In this state outputs of the memory device assume indeterminate values, that is electrical levels not meaningful for digital electronics. As an example, for TTL (Transistor Transistor Logic) the digital value "one" is represented by a value falling into the interval 1.5 ÷ 5 Volts while the digital value "zero" is represented by a value falling into the interval 0 ÷ 0.5 Volts. Any value not belonging to said two intervals is considered indeterminate. A TTL gate, supplied with such a value, will not operate correctly. This example shows how important metastability is. A known method to avoid metastability is the so-called "multiple sampling". Let us consider an originating circuit that must transfer data to a receiving circuit, belonging the two circuits to two different asynchronous clock domains. The theory of metastability states that including a cascade of N flip-flops circuit for sampling the incoming data in the receiving element, the probability that the output of the Nth flip-flop assumes an undefined logic value decreases in an exponential fashion with N. In all cases of practical interest, using a cascade of two flip-flops the probability of having an undefined logic value on the output of the 2nd flip-flop is negligible. It is important to point out that the fact of avoiding metastability does not ensure that the communication between the originating circuit and the receiving circuit is reliable. If for instance the originating circuit transmits 0 followed by 1 and the first flip-flop of the receiving circuit samples this signal while it is switching from 0 to 1 (the variation happens into the setup/hold windows of the flip-flop), it can go into a metastable state. Let us suppose that this first flip-flop really goes into a metastable state. The second flip-flop sampling the output of the first flip-flop do not go into a metastable state, but resolves the undeterminated logic value at its input and switches to 0. This can happen because the theory of metastability ensures that metastability is resolved with a cascade of flip-flops. Such a theory does not ensures that the output of the last flip-flop of the cascade correctly reproduces the input sampled by the first flip-flop. This last question it is about how to ensure a reliable communication between elements in the hypothesis that metastability is resolved with proper techniques. In general, even if metastability did not exist, the synchronous interconnection would not be reliable in case of asynchronous clock domains connected together. This is shown in the following example. Let us suppose that the two clock domains of the originating circuit and of the receiving circuit are asynchronous, and in particular that their periods are different. If for example the period of the clock of the receiving circuit is M times the period of the clock of the originating circuit, the receiving circuit can catch at most one datum out of M. On the contrary, if the period of the clock of the originating circuit is M times the period of the clock of the receiving circuit, the last one catches M times the same datum. From this example it is evident that synchronous communication depends on delays and more precisely on the duration of a valid datum and the time needed from the receiving circuit to catch it. Moreover, the data flow is not only unreliable but also not regulated. As an example, even if the receiving circuit is not ready to receive a datum, the originating circuit continues transmitting data because it has no means to know this. It is clear that, if the two elements are clocked with clocks of different frequencies and the clock of the receiving circuit has a frequency lower than the one of the originating circuit, sooner or later the receiving circuit will be filled of data. To avoid loss of data the transmission should not exceed a certain data rate affordable by the receiving circuit. To grant reliable communication a proper protocol has to be used. The general way of interconnecting two circuits or elements that are asynchronous is the so called "Asynchronous Interconnect" protocol. In this technique both the isochronous assumption and the use of a global clock signal have been abandoned. Interconnections between elements belonging to an asynchronous system are designed to operate in a delay insensitive manner, that is operates reliably regardless of what the delays are. This is accomplished by having each element ofthe system able to generate a completion signal. The completion signal is a sort of locally generated clock, and is used to synchronize different elements. Examples are given in the case of "Synchronous Interconnect" protocol modified by adding two completion signals also named handshake signals. The originating circuit generates a request signal that is a signal indicating to the receiving circuit that data are available. The receiving circuit replies generating an acknowledge signal indicating to the originating circuit that the request signal has been received and the originating circuit is free to proceed with the generation of a new request signal coupled to new data. The correct operation of the Asynchronous Interconnect protocol does not depend on assumptions about delays. This happens because the round-trip feedback ensures that the two operations are synchronized. Summarizing the above, it may be said that synchronization is provided through the following operations: 1. Recovery from metastability. 2. Two phase handshake (other known cases are less general than two phase handshake). Recovery from metastability is well explained in the paper of Debora Grosse, titled "KEEP METASTABILITY FROM KILLING YOUR DIGITAL DESIGN", published by EDN (Electronic Design), June 23, 1994. Point 2 with all the questions risen in the technical background discussed above, has been explained in large measure in the paper of David G. MESSERSCHMIT, "SYNCHRONIZATION IN DIGITAL SYSTEM DESIGN", published on IEEE JOURNAL ON SELECTED AREAS IN COMMUNICATIONS, vol. 8, No. 8, October 1990. The present invention is not particularly concerned with recovery from metastability. Indeed, nowadays the double sampling technique of a signal generated with a certain transmission clock by using an asynchronous reception clock is a consolidated practice. The invention relates specifically to the other aspect of synchronization. In Figure 1 a commonly known two-phase handshake system is shown. The system includes a transmission block TX clocked with a clock Ck T χ and a receiving block RX clocked with a second clock Ck RX , asynchronous to the clock Ckrx. Transmission block TX is connected to the reception block RX by means of a first wire for a signal DATA to be transmitted, a second wire for a request signal REQ, and a third wire for an acknowledge signal ACK. The block TX includes a further block LG-HANχχ representing an interface circuit for signal REQ and the block RX includes a further block LG-HAN RX representing an interface circuit for signal ACK. Both interface circuits are required for handshake management. Transmission block TX is either able to generate by itself the transmission signal DATA or to act on behalf of an external agent. In both cases when the transmission signal DATA is a burst or a stream, the block TX generally includes a transmission buffer like a FIFO (First In First Out) memory for accumulating a certain amount of data. The system of Fig. 1 works properly until the following relation is true: Troughput τx < Troughput χ (1) after which, even if a transmission buffer is used, a data loss will occur. The throughput condition has been written for highlighting that the handshake is not sufficient per se for transferring data successfully. A drawback of the known system of Figure 1 is that it does not promote modularity of the design, because of the presence of the two blocks LG-HAN T χ and LG-HAN RX and the two wires for signals REQ and ACK. For example, modification of the design from a not isochronous interface to an isochronous one is not easy, for the reason that both blocks TX and RX must be redesigned for eliminating the two interface circuits LG-HANτχ e LG-HAN RX . A long time felt need in the field of synchronization of modular designs with two asynchronous clock domains is that of having a module able to perform both recovery from metastability and synchronization in an autonomous way. Such a module could be simply interposed between the two blocks TX and RX of respective different clock domains, and simply removed or disabled when the isochronous option is preferred (the TX clock domain coincident with the RX clock domain), without any change in the interface circuits. The availability of such a self standing module would be a great asset for designing modular systems as the so called macro-cells based designs which are becoming so popular nowadays. A first known attempt in the direction of simplifying the asynchronous protocol consists in embedding a counter in the block TX. Such a block, by counting a certain number of clock periods corresponding to a time interval T samp ij ng in which the transmitting data is held at constant level, permits to the block RX to perform double sampling for recovery from metastability. Although this solution avoids handshake, it does not eliminate completely the circuitry inside the blocks TX and RX. But the major drawback is that, being the time interval T samp ij ng dependent on the ratio between the frequencies of the two clocks, Ck T χ and Ck RX , a change of one of the two asynchronous clocks needs a setting of a new counting window. OBJECT AND SUMMARY OF THE INVENTION It has been found and is the object of the present invention a synchronization circuit allowing the generation of a pulse lasting one period of a clock of an arrival clock domain starting from an incoming pulse, or a step signal, referred to an originating clock that may be different in phase and/or frequency from the arrival clock. The circuit of the invention is free from the drawbacks of the known art when the relation (1) is satisfied, as in the majority of practical cases. The synchronization circuit of the invention can be functionally placed between two asynchronous starting and arrival clock domains without the need of undertaking handshake procedure or other operations requiring an "ad hoc" logic circuit in the blocks at the two ends ofthe connection. The synchronization circuit ofthe invention operating between two different clock domains is insensitive to changes of the frequency ratio between the two different clocks. Yet another objective of the invention is that of providing a bidirectional synchronizer for transferring digital words between two different clock domains, suitable for words like commands (pulses) accompanied by a strobe signal or alarms (steps or pulses). The invention is clearly defined in the attached claims. BRIEF DESCRIPTION OF THE DRAWINGS All advantages of the present invention will become clearer through the detailed description of several embodiments of the invention and by referring to the attached drawings wherein: Figure 1 depicts a handshake system ofthe prior art; Figure 2 shows a synchronization unit ofthe present invention; Figure 3 is a timing representation of important signals of Figure 2; Figure 4 depicts a bidirectional synchronizer including the synchronized command register DIR-SY and the synchronized alarm register INV-SY of the invention; Figure 5 is a detailed description ofthe block DIR-SY of Figure 4; Figure 6 is a detailed description ofthe block INV-SY of Figure 4. DESCRIPTION OF SEVERAL EMBODIMENTS OF THE INVENTION A block P2P, where the acronyms P2P means pulse to pulse, representing a preferred embodiment of a synchronization unit of the invention is depicted in Figure 2. At the right side there are an input pin 1 for an input signal SIN and a clock pin CLKl for a first clock CLKl and at the left side there are an output pin 2 for an output signal SOUT and a clock pin CLK2 for a second clock CLK2 that may be asynchronous in frequency and/or phase in respect to the first clock domain. The circuit is split into two clock domains, namely CLKl domain and CLK2 domain which extend outside the synchronization unit P2P. Within the block P2P, the CLK2 domain includes a cascade of two type-D flip-flop DFF1 and DFF2, and a rising edge detector FR1. The CLKl domain within the P2P block includes a rising edge detector FRO, a set-reset flip-flop SRFF1, a cascade of two type-D flip-flop DFF3 and DFF4, and a rising edge detector FR2. All elements of the CLKl domain are clocked with the rising edge of the clock CLKl, except flip-flop DFF3, which is clocked with the falling edge. All elements of the CLK2 domain are clocked with the rising edge of the clock CLK2, except flip-flop DFF1, which is clocked with the falling edge. Even if other solutions are possible, all the devices that compose the P2P block can be conveniently realized with D-type flip-flops and with logic gates because in this way the entire P2P circuit can be realized with any digital component library available on the market. The arrow direction sketched inside each memory device indicates the sensitivity of the memory device to the rising (up arrow direction) or falling (down arrow direction) clock edge. Even if is possible to use only one active edge of clock, using both clock edges reduces the time taken by the synchronization process. In general, component libraries make available only memory devices sensitive to a clock rising edge, and the simplest way to obtain a memory device sensitive to a clock falling edge is to negate the clock by an inverter and to provide this negated clock to a memory device sensitive to the clock rising edge. The use of an inverter does not introduce skew problems (not even in an ASIC device) provided the number of memory devices to be supplied is relatively low, like in the present case. The fundamental property of the P2P circuit is to transform a pulse or a step signal SIN clocked with the clock CLKl being input on pin 1 into a pulse SOUT clocked with CLK2 output on pin 2. The synchronization circuit of the present invention transforms a pulse or a step signal SlN synchronous with a first clock CLKl into a pulse SOUT synchronous with a second clock CLK2 whatever the phase and frequency relationship between the two clocks is. In order to operate correctly, the synchronization block P2P of the invention only needs the presence of the two clocks and of the incoming signal to be converted. No handshake procedure nor a counter in the transmitting block are requested. The necessary handshake for synchronization, as implied by a communication between two asynchronous clock domains, is resolved internally in the block P2P. The functioning of the synchronization unit of the invention can be explained by referring the waveforms of the signals CLKl, CLK2, SO, SI, S2, S3, S4, S5 and S6 depicted in Fig.3. Time is divided into time frames FI to F32, wherein each time frame represents half period ofthe fastest clock CLKl . Either a pulse (sketched with dotted line) or a step (sketched with continuous line) signal SO, representing an input signal SIN, can be fed to the input ofthe rising edge detector FRO. In both cases the output of the rising edge detector FRO is a pulse SI that is fed to the set input of the flip-flop SRFF1. This pulse is asserted in cycles from FI to F3. Flip-flop SRFF1 samples the asserted pulse signal SI with the rising edge of CLKl at the time frame F2. As a consequence, flip-flop SRFF1 switches and during F3 the signal S2 is asserted. The signal S2 is kept asserted and is not possible for any signal belonging to the clock domain CLKl to negate it. The signal S2 is then transmitted to the second clock CLK2 domain. In the clock domain of CLK2, a first double sampling (with the clock CLK2) is performed to avoid metastability. In particular, a double sampling with opposite clock phases is perforaied to avoid metastability without wasting two clock pulses, but as said before a more traditional solution using two flip-flops triggered by the same edge is also satisfactory. The double sampling practically ensures that at the output of DFF2 the signal S3 does not assume illegal values. The duration of the active phase of the signal S2 is a key-factor to provide for correct communication between the two clock domains. In fact, if the duration of the signal S2 were less than two CLK2 cycles, the generation of the signal S3 from the signal S2 would become unreliable even performing a double sampling. In fact, if the transition zero-to-one of the flip-flop SRFF 1 happened in the setup- hold window of the flip-flop DFF1, the output of this flip-flop could assume an illegal value (a value unrecognized by logic devices) with a non negligible probability. By virtue of the double sampling, the output of the second flip-flop DFF2 assumes a legal logic value (either zero or one) in any case. The theory of metastability does not ensure that the recognized value is the correct one, it only ensures that the recognized value is a legal logic value, such not to cause metastability in logic devices to which is input. By way of an example, the recognized signal S3 could be zero even if signal S2 switched from zero to one. Being the signal S2 a pulse, the information carried by it could be lost. To avoid such a possible loss of information, the signal S2 must be kept stable. Stability allows the flip-flop DFF2 to perform more than one single sampling. In this way the flip-flop DFF2 has the opportunity of sampling a stable signal S2, as provided by the flip-flop SRFF 1. The signal S3, which is a step signal asserted in cycle F10, is input to the front detector FRl that produces a pulse S6, clocked with the clock CLK2 and lasting one clock period. The signal S6 output from the front detector FRl is made available on the pin 2 of P2P unit as output signal SOUT. At the same time, the signal S3 is fed-back to the CLKl domain. The cascade of flip-flops DFF3 and DFF4 is input with the signal S3, for avoiding metastability, and produces a signal S4. The signal S4 is input to the front detector FR2. The front detector FR2 outputs a pulse S5, clocked with the clock CLKl and lasting one CLKl period (that is from F13 to F15). The signal S5, which is coupled to the reset pin of the flip-flop SRFF1, resets it, making the signal S2 assume a logic zero value at the time frame F15, and so do signals S3 and S4 at time frames F22 and F25, respectively. The loop composed of devices SRFF1, DFF1, DFF2, DFF3, DFF4 and FR2 ensures that the signal S2 is negated after its effect has been felt by the device FRl, providing for reliable communication between signals SI and S6. The synchronization circuit of the invention described above can be simply interposed between any two different clock domains without the need of embedding dedicated logic interfaces in the originating block and in the terminating block. The synchronization circuit of the invention can be consequently and advantageously seen as an independent block capable of making the design of asynchronous interfaces highly modular. Being the double sampling with the two opposite edges of the sampling clock the preferred sampling modality for recovery from metastability in the two directions inside the synchronizer P2P, it is necessary to consider the worst case affecting synchronization time T SYNC H R due to the skew of the two clocks and to the various delays that are introduced in the synchronizer P2P. Attention is drawn to the fact that the restriction imposed by the synchronizer circuit of the invention to the interarrival time T INTR between two successive input pulses SlN, determines the maximum time of synchronization. The following relation expresses this restriction: TINTR ≥ TSYNCHR (2) The analysis of the timing waveforms of Figure 3 allows evaluation of the time T SYNCHR for the worst case, so that the relation (2) shall refer to the worst T SYNCHR as the maximum time that is spent for synchronization. This expedient is useful for maintaining a good safeguard in the design. To define the worst T SYNCHR time, the following considerations are made: • the widest phase offset between the signal S2 and the clock CLK2 takes away one period TCLK2 of clock CLK2 at the output of flip-flop DFF1 , a further half period T C 2 is taken by the flip-flop DFF2 for sampling; the sum is 1,5 period T C L 2 for the two flip-flops DFF1 and DFF2; • on account of phase offsets similar to the above mentioned offsets, a further delay of 1 ,5 period T LKI of clock CLKl is introduced by the flip-flops DFF3 and DFF4; • the initial condition that must be restored to make the synchronizer ready to accept a new pulse, is reached when the signal S4 switches low, that is when the chain of events promoted by the signal SI completes the two routes of the loop, starting from and ending to the flip-flop SRFF 1. Therefore, it can be stated that the relation (2) is equivalent to the following expression: TI TR ≥ (TSYNCHR worst) = (3T CL 2 + 4T C LKI) (3) where CLKl is the clock of the starting domain and CLK2 of the arrival domain. Expression (3) is not restrictive in the majority of practical applications, so it can be easily satisfied while achieving the great advantage of modularity. If clock CLK2 is the fastest of the two clocks in Figure 2, a set of waveforms can be obtained by making the same considerations that have been made for the case discussed in relation to Figure 3. In such a case, the new waveforms would have the same phase relationship as the previous ones, nevertheless the inverted speed ratio between the two clocks affects the maximum T SYNCHR time, cause the clock asymmetry of the expression (3). The case presently discussed, namely in which clock CLKl at the homonym pin of the P2P unit is faster than clock CLK2 at the homonym pin, is that with the shorter TSYNCHR time. The synchronization unit P2P of the invention can be used to build a bidirectional synchronizer transferring a command, together with a strobe pulse for write or an alarm information, between two asynchronous clock domains. Using the P2P unit of the invention, it is possible to provide suitable control signals in order to regulate the transfer of Command and Alarm words, avoiding metastability and incorrect logic values. It is useful to remind that one-bit command is associated with a pulse of one clock pulse duration, while one-bit alarm is associated either with a step of indefinite duration or with a pulse of one clock period duration. More one-bit commands in parallel "cluster" a command word and more one-bit alarms in parallel "cluster" an alarm word. A write strobe signal is always coupled to a command word. A basic diagram of the synchronizer of the invention is depicted in Figure 4. The block BID-SY representing a bidirectional synchronizer of the invention is interposed between a block MPRI representing a Microprocessor Interface and a block APL representing an Application Logic circuit driven through the microprocessor interface MPRI. Block BID-SY is constituted by a synchronized command register DIR-SY and a synchronized alarm register INV-SY, that represents additional important aspects of the invention. The block DIR-SY has two inputs SlN and STR and an output SOUT and two clock pins CKIN and CKOUT. Block INV-SY has two inputs SIN and ACK and an output SOUT and two clock pins CKIN and CKOUT. The inputs SlN and STR of DIR-SY are connected to two corresponding inputs Id and 2d of the main block BID-SY. Inputs Id and 2d are connected to a data bus of the microprocessor interface MPRI carrying a signal COMMAND_FROM_MPRI[31 :0](Pfl), and to an output of the microprocessor interface MPRI outputting a write strobe signal SYNC_WR_COMMAND(Pfl), respectively. The output SOUT of the synchronized command register DIR-SY is connected to an output 3d of the block BID-SY; this output is further connected to an input of the application block APL for sending a command COMMAND_TO_APL[31 :0](P£2). To CKIN and CKOUT of the block DIR-SY are applied two respective clock signals CBUS_CLK and APPL_CLK, the first belonging to the clock domain of the microprocessor interface MPRI and the second to the clock domain ofthe block APL. The inputs SlN and ACK of the synchronized alarm register INV-SY are connected to two corresponding inputs li and 2i of the main block BID-SY. The inputs li and 2i are further respectively connected to a data bus ALARM_FROM_APL[31:0](f2) of an application block APL and to a pin of microprocessor interface MPRI outputting an acknowledge signal S YNC_RD_ALARM(Pf 1 ). The output SOUT of the synchronized alarm register INV-SY is connected to the output pin 3i of the block BID-SY. The pin 3i is further connected to corresponding input of the microprocessor interface MPRI for sending an alarm ALARM_TO_MPRI[31 :0](fl). The pins CKIN and CKOUT of the block INV-SY are coupled to two respective clock signals: APPL_CLK and CBUS_CLK, belonging to the respective clock domains of the block APL and of the microprocessor interface MPRI. A detailed description of a preferred embodiment of the synchronized command register DIR-SY of Figure 4 is depicted in Figure 5. Two sub-blocks, separated by a dashed line in the figure, compose the block: the first sub-block is named Command Register while the second sub-block is named Command Synchronizer. The sub-block named Command Register may be embedded even into the microprocessor interface MPRI without changing the working principle of the synchronizer ofthe invention. The synchronized command register DIR-SY includes: two identical blocks ID1 and ID2 producing a pre-established signal, a three-way multiplexer MUX1, a two-way multiplexer MUX2, a clocked set-reset flip-flop SRFF2, a first D-type flip-flop DFF5 and two identical synchronization circuits P2P_1 and P2P_2 of the invention. Optionally a second D-type flip- flop DFF6 sampling the output of the second multiplexer MUX2 can be used. The symbol #32 means that the shadowed blocks MUXl, DFF5, DFF6, and MUX2 have multiplicity/width 32 to operate on a 32 bits signal, alike to the number of bits of the data bus COMMAND_FROM_MPRI[31 :0](Pfl). Symbols in parenthesis attached to the name of signals have the following meaning: The Command Register sub-block has the function of outputting the command word on the base of an input provided by the microprocessor interface MPRI. The Command Synchronizer sub-block has the function of synchronizing to the application clock APPL_CLK the command word provided by the first sub-block, which is synchronous to the clock CBUS_CLK. The blocks IDl and ID2 feed the multiplexers MUXl and MUX2 with two identical fixed 32 bit patterns of logic ones and zeros, named IDLE CODE. This pattern is the hardwired binary translation of a parameter used as initialization value for the Command Register embedded into the Synchronized Command Register DIR-SY. Each bit of the command register represents an independent command. Thus, when the microprocessor interface MPRI wants to write a command to a specific bit N of the Command Register, it writes a bit of opposite value in respect to the bit having the same position in the IDLE CODE hard-wired into blocks IDl and ID2. As an example, if bit N of both blocks IDl and ID2 is 0, than the command expressed by the bit N is active high (the opposite ofthe one hard- wired into bit N of the IDLE CODE). The microprocessor interface MPRI writes 1 to the Nth bit of the Command Register, while the remaining bits are set equal to the same value that is hard- wired into blocks IDl and ID2. The written word is sent from microprocessor interface MPRI on COMMAND_FROM_MPRI[31 :0](Pfl) bus. This word is paired with a relative strobe pulse SYNC_WR_COMMAND(Pfl), which is sent on a separate wire. Both signals COMMAND_FROM_MPRI[31 :0](Pfl) and SYNC_WR_COMMAND(Pfl) are pulse signals associated to clock CBUS_CLK at frequency fl and phase PHI. The pulse SYNC_WR_COMMAND(Pfl) sets the SRFF2 flip-flop, which asserts the STROBE_CMD(fl) signal, and at the same time the pulse causes the multiplexer MUXl to switch from the idle position (selecting the IDLE CODE) to the selection of the input signal COMMAND_FROM_MPRI[31:0](Pfl). As a consequence, the flip-flop DFF5 samples the value sent from the microprocessor interface MPRI and the bit N on CMD[31 :0](f 1 ) bus switches from 0 to 1. When the SRFF2 flip-flop is set the STROBE_CMD(fl) signal switches to the active level. This event is coupled to the outputting of the command CMD[31 :0](fl). The signal SYNC_WR_COMMAND(Pfl) lasts one clock pulse of CBUS_CLK and when it is negated, the signal STROBE_CMD(fl) is asserted and the multiplexer MUXl holds the output of DFF5. More precisely, the multiplexer MUXl holds the output of DFF5 when both SYNC_WR_COMMAND(Pfl) and ACK_CMD(Pfl) are negated and STROBE_CMD(fl) is asserted, selects the IDLE CODE regardless to the values of other selection inputs when ACK_CMD(Pfl) is asserted, selects the input connected to the data bus at the SΓN input when SYNC_WR_COMMAND(Pfl) is asserted and other selection signals are negated. At this point the command on bit N has been provided. This command is synchronous with clock CBUS_CLK with frequency fl and phase PHI . The pulse carried by the STROBE_CMD(f 1 ) signal is sent to the input pin 1 of the P2P_1 unit. This block translates the signal at frequency fl and phase PHI associated to the clock CBUS_CLK into a pulse at frequency £2 and phase PH2 associated to the clock APPL_CLK. This last pulse, renamed MUX_CTRL(Pf2), is output from pin 2 of the P2P_1 unit and drives the selection on multiplexer MUX2. As a consequence the multiplexer MUX2 switches from its idle position selecting the block ID2 to the selection of the input of data pattern CMD[31 :0](fl). The bit N of CMD[31 :0](fl) is provided to the flip-flop DFF6 to be sampled by the clock APPL_CLK (with frequency £2 and phase PH2). This sampling cannot lead the DFF6 flip-flop into a metastable state because within the setup/hold window centred across the rising edge of APPL_CLK, the signals composing CMD[31 :0](fl) are all stable. This happens because, when STROBE_CMD(fl) signal is asserted, all bits of the bus CMD[31 :0](fl) are stable because the output ofthe flip-flop DFF5 is stable as long as ACK CMD(Pfl) signal is negated. The pulse signal MUX_CTRL(Pf2) output by pin 2 of P2P_1 unit is asserted after the assertion of incoming STROBE_CMD(fl) signal inputting P2P_1 unit on pin 1. So when the multiplexer MUX2 driven by MUX_CTRL(Pf2) signal switches its input, the data CMD[31 :0](fl) are stable. The same output pin 2 of P2P_1 unit, driving the MUX_CTRL(Pf2) signal, also drives the input pin 1 of P2P_2 unit, which outputs on pin 2 a pulse signal ACK_CMD(Pfl).. The pulse ACK_CMD(Pfl), which is synchronous to clock CBUS_CLK of frequency fl and phase PHI, causes the multiplexer MUXl to switch to the input connected to the IDLE CODE block IDl, thus so the flip-flop DFF5 samples the hard-wired pattern IDLE CODE and idle condition is restored. This means that bit N switches from 1 to 0, which is the idle value set by the hard-wired pattern IDLE CODE. As stated above, the presence of the flip-flop DFF6 is optional: its presence decouples the Application Logic block APL from the presence of delays due to the propagation delay in the multiplexer MUX2. The use of such a flip-flop DFF6 though preferable is a matter of choices. A representation of waveforms of the signals belonging to the block DIR-SY can be readily inferred from those of Figure 3. In such a bidirectional embodiment, the maximum time spent in synchronization T SYNCHR is about twice the time defined by the relation (3) concerning the single unit P2P of Figure 2, because two identical units, namely P2P_1 and P2P_2, are connected in series for completing a single synchronization transaction. The above clearly indicates that the circuit diagram of Figure 5, in which two P2P units are nested as building blocks, is able to reproduce the same functions of the circuit diagram of a single unit P2P though at a higher level. A detailed diagram of a preferred embodiment of a synchronized alarm register INV-SY of Figure 4 is depicted in Figure 6. Two sub-blocks separated by a dashed line compose the block. The first sub-block is named Alarm Register while the second sub-block is named Alarm Synchronizer. Naturally, the sub-block named Alarm Register may even be embedded into the microprocessor interface MPRI without affecting the working principle of the synchronizer of the invention. The synchronized alarm register of the invention INV-SY includes: one two-way multiplexer MUX3, one hardwired logic one block, one hardwired logic zero block, one D-type flip-flop DFF7 and a synchronization circuit P2P_3 of the invention. The symbol #32 means that the shadowed hardwired zero and one blocks, MUX3, DFF7 and P2P_3 operate on a 32 bits signal, that is with the same number of bits as the bits of the buses ALARM_FROM_APL[31 :0](f2) and ALARM_TO_MPRI[31:0](fl). The Nth bit (with N belonging to the interval 1 to 32) of each block of Figure 6 is connected to a corresponding Nth bit of respective 32 bit wide buses. The only exception to this rule is the S YNC_RD_ALARM(Pf 1 ) signal which is unique for all instance of multiplexer MUX3. The shadowed blocks can also be considered as multiple instances (from 1 to 32) of a component arranged according to the so called "bit slice" technique, where the instance N is charged of manipulating the Nth bit. This vision is particularly suited to understand the working principle and will be used for this purpose. The Alarm Register sub-block has the function of trapping the alarm provided by the application logic APL via the Alarm Synchronizer sub-block. The Alarm Synchronizer sub-block has the function of synchronizing to the clock CBUS_CLK the alarm provided by the application logic APL, which is synchronous to the clock APPL_CLK. Each bit of the signal ALARM_FROM_APL[31 :0](f2) carries an alarm from application logic block APL. In the same way each bit of the signal ALARM_TO_MPRI[31 :0](fl) carries an alarm to the microprocessor interface MPRI. An acknowledge signal SYNC_RD_ALARM(Pfl) is provided to the ACK input pin for indicating that the signal ALARM_TO_MPRI[31 :0](Pfl) has been read by the microprocessor interface MPRI. The operation of the Synchronized Alarm Register is described starting from idle conditions. In idle state the Q output of each slice of DFF7, SYNC_RD_ALARM(Pfl) and MUX_CTRL[31 :0](Pfl) are negated (zero) and each slice ofthe multiplexer MUX3 selects its hardwired zero input. When an alarm bit, let us suppose the Nth bit, reaching the SlN input pin of the Alarm Synchronizer sub-block is asserted, it is translated into a pulse synchronous to the clock CBUS_CLK from the Nth slice P2P_3 block. Assertion of MUX_CTRL[N](Pfl) causes the Nth slice of multiplexer MUX3 to select the hardwired one input, so Nth slice of the flip-flop DFF7 is input with a "one". After sampling, this asserted value is outputted on the Q output ofthe Nth slice of DFF7. The selection logic of the Nth slice of multiplexer MUX3 is designed to select its hardwired logic one until the selection signal output from the Q pin of the Nth slice of flip-flop DFF7 is asserted. In this way the alarm is trapped and is retained regardless to the value ofthe signal ALARM_FROM_APL[N](Pf2). The only way to reset DFF7 is through the assertion of the signal SYNC_RD_ALARM(Pfl) by the microprocessor interface MPRI. In this way a new alarm can be trapped.

Claims: CLAIMS 1. A synchronization circuit (P2P) for interfacing a first digital circuit clocked with a first clock (CLKl) and a second digital circuit clocked with a second clock (CLK2) that may be different from said first clock (CLKl) in terms of frequency and/or phase constituted by a transmitting section clocked with said first clock (CLKl) comprising an input edge detector (FRO) of an input signal (SlN) producing a set pulse signal (SI), a block (SRFF1) coupled to said set pulse signal (SI) producing a first signal (S2) if said set pulse signal (SI) is asserted until a reset pulse signal (S5) is received, a receiving section clocked with said second clock (CLK2) comprising a first metastability recovery block producing a second signal (S3) by sampling said first signal (S2) a first pre-established number of times with said second clock (CLK2), an output edge detector (FRl) of said second signal (S3) producing an output pulse signal (S6), a feedback section clocked with said first clock (CLKl) comprising a second metastability recovery block producing a third signal (S4) by sampling said second signal (S3) a second pre-established number of times with said first clock (CLKl), a feedback edge detector (FR2) of said third signal (S4) producing said reset pulse signal (S5). 2. The synchronization circuit of claim 1 wherein said first metastability recovery block is a cascade of at least a first type D flip-flop clocked on raising clock edges and a second type D flip-flop clocked on falling clock edges. 3. The synchronization circuit according to one of the preceding claims wherein said second metastability recovery block is a cascade of at least a third type D flip-flop clocked on raising clock edges and a fourth type D flip-flop clocked on falling clock edges. 4. The synchronization circuit according to one of the preceding claims wherein said block (SRFF1) is a set-reset flip-flop having said set pulse signal (SI) as set input and said reset pulse signal (S5) as reset input. 5. The synchronization circuit according to one of the preceding claims wherein said first pre-established number is equal to two. 6. The synchronization circuit according to one of the preceding claims wherein said second pre-established number is equal to two. 7. A synchronized alarm register for trapping and transferring an application alarm signal (ALARM_FROM_APL(f2)) from an application circuit (APL) clocked with a third clock (APPL_CLK) to said microprocessor interface (MPRI) clocked with a fourth clock (CBUS_CLK) that may be different in terms of frequency and/or phase from said third clock (APPL_CLK) constituted by an alarm synchronizer comprising at least a synchronization circuit (P2P) according to one of claims from 1 to 6 being input with said application alarm signal (ALARM_FROM_APL(f2)) and said clocks third (APPL_CLK) and fourth (CBUS_CLK) producing an synchronized alarm signal (MUX_CTRL(Pfl)), an alarm register trapping said synchronized alarm signal and providing to said microprocessor interface (MPRI) an output alarm signal (ALARM_TO_MPRI(fl)) until an acknowledgement signal (SYNC_RD_ALARM(Pfl)) provided by said microprocessor interface (MPRI) is received. 8. The synchronized alarm register of claim 7 wherein said alarm register comprises a logic block producing an active logic value (1), a logic block producing a logic zero value (0), a multiplexer (MUX3) coupled with said active logic value (1), said logic zero value (0), said output alarm signal (ALARM_TO_MPRI(fl)), said acknowledgement signal (SYNC_RD_ALARM(Pfl)) and said alarm word (MUX_CTRL(Pfl)), outputting a signal (M3) equal to said logic zero value (0) if said acknowledgement signal (SYNC_RD_ALARM(Pfl)) has an active logical value or if both said output alaπn signal (ALARM_TO_MPRI(fl)) and said synchronized alarm signal (MUX_CTRL(Pfl)) have a logic zero value, or equal to said active logic value (1) if said output alarm signal (ALARM_TO_MPRI(fl)) or said synchronized alarm signal (MUX_CTRL(Pfl)) assumes its active logical value while said acknowledgement signal (SYNC RD ALARM(Pfl)) assumes its logic zero value, a D type flip-flop reading said signal (M3) at clock edges of said fourth clock (CBUS CLK). 9. A synchronized command register forming and transferring a command signal basing on an input data signal (SIN) with a strobe signal (STR) from a microprocessor interface (MPRI) clocked with a fourth clock (CBUS_CLK) to an application circuit (APL) clocked with a third clock (APPL_CLK) that may be different from said fourth clock (CBUS_CLK) in terms of frequency and/or phase constituted by a command register clocked with said fourth clock (CBUS_CLK) comprising a strobe trapping circuit coupled to said strobe signal (STR) outputting a second strobe signal (STROBE_CMD(fl)) if said strobe signal (STR) has been activated until an acknowledge signal (ACK CMD(Pfl)) is received, an input selection and hold circuit coupled with said input data signal (SlN) outputting a second data signal (CMD(fl)) equal to said input data signal (SIN) if said strobe signal (STR) or said second strobe signal (STROBE_CMD(fl)) are activated, or equal to a first idle signal (IDl) if said acknowledge signal (ACK_CMD(Pfl)) is received; a command synchronizer being input said second data signal (CMD(fl)) and said second strobe signal (STROBE CMD(fl)) clocked with said fourth clock (CBUS_CLK) comprising a first synchronization circuit (P2P_1) according to one of claims from 1 to 6 being input with said a second strobe signal (STROBE_CMD(fl)) producing an output strobe signal (MUX_CTRL(Pf2)) clocked with said third clock (APPL_CLK), an output selection and hold circuit providing to said application circuit (APL) a second idle signal (ID2) or said second data signal (CMD(f 1 )) depending on said output strobe signal (MUX_CTRL(Pf2)), a second synchronization circuit (P2P_2) according to one of claims from 1 to 6 being input with said output strobe signal (MUX_CTRL(Pf2)) clocked with said third clock (APPL_CLK), producing said acknowledge signal (ACK_CMD(Pfl)) clocked with said fourth clock (CBUS_CLK). 10. The synchronized command register of claim 9 wherein said strobe trapping circuit comprises a set-reset flip flop whose set input is said strobe signal (STR) and said reset signal is said acknowledge signal (ACK_CMD(Pfl)). 1 1. The synchronized command register according to one of claims from 9 to 10 wherein said input selection and hold circuit comprises a first idle code generator producing said first idle signal (IDl), a multiplexer (MUXl) coupled with said first idle signal (IDl), input data signal (SIN), second data signal (CMD(fl)), strobe signal (STR), acknowledge signal (ACK CMD(Pfl)) and said second strobe signal (STOBE_CMD(fl)) outputting an inteπnediate data signal equal to said input data signal (SlN) if said strobe signal (STR) or said second strobe signal (STOBE CMD(fl)) are activated, or equal to said first idle signal (IDl) if said acknowledge signal (ACK_CMD(Pfl)) is received, a D type flip-flop input with said intermediate signal producing said second data signal (CMD(fl)). 12. The synchronized command register according to one of claims from 9 to 1 1 wherein said output circuit comprises a second idle code generator producing said second idle signal (ID2), a second multiplexer (MUX2) coupled with said second idle signal (ID2), said second data signal (CMD(fl)) and said output strobe signal (MUX_CTRL(Pf2)) providing an output signal to said application circuit (APL). 13. The synchronized command register according to one of claims from 9 to 12 wherein said second multiplexer (MUX2) is coupled to said application circuit (APL) by means of a D type flip-flop clocked with said third clock (APPL_CLK). 14. A bidirectional synchronizer transferring digital words with a strobe signal (STR) from a microprocessor interface (MPRI) functioning with a first clock (CLKl) to an application circuit (APL) functioning with a second clock (CLK2) that may be different from said first clock (CLKl) in terms of frequency and/or phase and alarm signals from said application circuit (APL) to said microprocessor interface (MPRI) comprising a synchronized command register according one of claims from 9 to 13 and a synchronized alarm register according to claims 7 or 8.

Inventors: GEMELLI RICCARDO, PAVESI MARCO, GEMELLI, RICCARDO, PAVESI, MARCO
Applicants: GEMELLI RICCARDO, ITALTEL SPA, PAVESI MARCO, GEMELLI, RICCARDO, ITALTEL S.P.A., PAVESI, MARCO
Application year: 2000
Main classification: G06F5
IPC codes: G06F5, H04L7