SYSTEM AND METHOD FOR HIGH SPEED DATA TRANSMISSION

Abstract: A transmission device and method are capable of high speed transmission over existing telephone lines using acoustic tones. Data can be transmitted over existing telephone lines (20) by converting the data to a pair, triplet or other grouping of acoustic tones and transmitting the composite signal. The data, such as an ASCII character (22), is first converted to an eight bit binary number (24). The binary number is then used to select two tones, a high frequency tone (28) and a low frequency tone (26). These tones (26, 28) are mixed to form the composite signal (30) that is transmitted (32) over the telephone lines (20). The tones (26, 28) may be configured to have differing amplitudes or be separated by chirp tones, and are mixed to form a composite signal that is transmitted over the telephone lines (20). The received composite signal (30) can then be broken down into its constituent tones and decoded to generate the transmitted data (22) at the receiving device.

Description: SYSTEM AND METHOD FOR HIGH SPEED DATA TRANSMISSION FIELD OF THE INVENTION The invention relates to high speed data communication between computers and other media. More particularly, the invention relates to high speed data transfer over existing telephone lines and point-to-point dedicated communication lines using acoustic tones, which in certain embodiments may differ in amplitude, be synchronized with chirp signals, or be configured in other ways. BACKGROUND OF THE INVENTION Existing data transmission devices, including modems, are capable of transmitting and receiving data over conventional twisted pair telephone lines. The data transfer speed of these conventional devices over the telephone lines is, however, limited. This limitation is at least in part the result of the use of quadrature amplitude modulation ("QAM") as an encoding scheme. Traditional modem designs using QAM communicate over telephone lines using phase- locked loop based decoders. The decoders use a series of processing iterations that systematically modify a reference signal to approximate the incoming data signal. When a phase-locked loop detector outputs a zero phase differential, the reference signal is locked onto the incoming data signal. This process is time- consuming and results in a processing delay (or latency) of over 40 milliseconds per character sent. Transmission devices that transmit data over telephone voice channels are limited by phase distortion. In a typical telephone voice channel not all of the frequency components of the input signal will propagate to the receiving end in exactly the same time, resulting in phase distortion. To counter this problem, existing devices typically select a frequency that exhibits minimal phase distortion and use that frequency as a basis for the QAM. This problem can also be countered by improving bandwidth efficiency. Improving the bandwidth efficiency in QAM can be accomplished by employing a higher level of modulation. However, higher levels of modulation require greater signal to noise ratios to maintain an acceptable bit error rate. This means a certain power premium is necessary to maintain an acceptable bit error rate. However, FCC regulations and other factors constrain the amount of the power that can be delivered into telephone lines. Other drawbacks of data transmission devices exists. SUMMARY OF THE INVENTION An object of the invention is to overcome these and other drawbacks of existing data transmission devices and methods. Another object of the invention is to provide a method and device for high speed data transmission. Another object of the invention is to provide a method and device for high speed data transmission over existing telephone lines. Another object of the invention is to provide a method and device for high speed data transmission over ohmic connectors where the binary information transmitted is separate from the continuous transmission transport or carrier wave. Another object of the invention is to provide a method and device for high speed data transmission over ohmic connectors using multi-tone input. Another object of the invention is to provide a method and device for high speed data transmission over existing telephone lines which employ acoustic tone groups, such as pairs, whose individual components may be synchronized using separators, chirp signals, or configured in other ways, such as differing amplitudes The invention in one regard relates to a high speed data transmission device that utilizes a system of remote analog to digital conversion without the usual quadrate amplitude modulation. The device converts binary numbers into acoustic sound frequencies in pairs, triplets or other groupings, and transports data more efficiently than previously existing systems. The invention in one embodiment uses 24 tones, two at a time, to communicate up to 276 ASCII characters. The transmission begins with the receipt of an ASCII character as an input. This character is represented by 8 data bits which are used to generate a low frequency tone and a high frequency tone. These two tones are mixed and transmitted over the telephone or other communication channel in the same manner as the seven DTMF tones conventionally used for dialing a telephone. The process of reception includes receiving the mixed tones from the telephone lines and separating them into the high and low frequency components using analog filters. After filtering, the two tones are passed to a zero crossing chip. The waves typically oscillate near zero and each time a wave crosses zero, the zero crossing chip generates a pulse which is used to recreate the 8-bit ASCII characters. The invention in another regard relates to an embodiment that uses 31 tones, two at a time, to communicate up to 276 ASCII characters. The tone may be configured to have differing amplitudes, be detectable in less than (1/2) of a full wave cycle, be separated by chirp signals, or in other ways. These and other objects and advantages of the invention will be apparent from the detailed description of the preferred embodiments which follows. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 shows a flowchart for transmission of data according to a first embodiment of the invention. Fig. 2 shows a flowchart for reception of transmitted data according to the first embodiment of the invention. Fig. 3 shows a perspective view of a high speed transfer device. Fig. 4 shows a block diagram of a transmitting circuit for a high speed transfer device according to the first embodiment of the invention. Fig. 5 shows a block diagram of a receiving circuit according to the first embodiment of the invention. Fig. 6 shows a graph of a mixed signal having two sinusoidal components according to the first embodiment of the invention. Fig. 7 shows a flowchart for the transmission of data according to a second embodiment of the invention. Fig. 8 shows a schematic of a transmitting circuit according to the second embodiment of the invention. Fig. 9 shows a schematic of a receiving circuit according to the second embodiment of the invention. Fig. 10 shows an allocation table according to the second embodiment of the invention. Fig. 11 shows a bus driver according to the second embodiment of the invention. Figs. 12A-C show a null point intercept graph of two mixed signals according to the second embodiment of the invention. Fig. 13 shows a tone generator and Wein bridge oscillator according to the second embodiment of the invention. Fig. 14 shows a timer according to the second embodiment of the invention. Fig. 15 shows a missing pulse detector according to the second embodiment of the invention. Fig. 16 shows a flowchart for transmission and reception of data according to a third embodiment of the invention. Fig. 17 shows a schematic of a transmitting circuit using two tones of fixed time duration-serial mode with tone separators according to an embodiment of the invention. Fig. 18 shows a schematic of distribution circuit. Fig. 19 shows a schematic of a fast digital decoder and tone evaluator. Fig. 20 shows a schematic of a circuit for determination of an ASCII character.. Fig. 21 shows a schematic of a transmitting circuit using two tones of fixed time duration in serial format without separators. Fig. 22 shows a schematic of a transmitting circuit using two tones mixed in parallel where tone two has a lower amplitude than tone one. Fig. 23 shows a flowchart for the decoding process according to an embodiment of the invention. DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS As illustrated in Fig. 3, a high speed data transmission device 10 according to the invention generally includes a transmitting circuit 12 and a receiving circuit 14. The data transmission device 10 can be used to transmit data over any transmission medium such as twisted pair copper wires, fiber optic cables, coaxial cables, and wireless transmission but is described herein with reference to existing twisted pair copper telephone lines. Data transmission device 10 can be installed at a first location 16 and communicate with another data transmission device 10 installed at a second location 18 connected over conventional twisted pair copper telephone line 20. The data transmission device 10 can be connected to the telephone line 20 using standard telephone line cord typically provided with telephones or modems, connecting at one end to the transmission device 10 with an RJ-1 1 jack and the other end to an existing telephone line outlet. The data transmission device 10 can provide high speed data transfer between like transmission devices 10 over existing telephone lines 20 using a new form of data modulation employed by the invention. This new form of modulation is an optimization between analog and digital waveforms generated by a certain form of pulse analog to digital conversion. The data transmission device 10 according to a first embodiment of the invention converts binary information signals into analog signals for transmission, without the use of D/A converters or the quadrature amplitude modulation typically used by conventional data transmission processors or modems. The data transmission is achieved by converting binary numbers into acoustic frequencies, in pairs or triplets or other combinations of tones, which can be transmitted more efficiently than conventional quadrate amplitude modulation systems. The process is a fully duplex technique where the final conversion of an analog trigger frequency into digital characters occurs at the receiving circuit 14 installed in a recipient computer, printer, or other medium. Data transmission over telephone voice channels is limited by phase distortion in the transmission wave. The shorter the wavelength or higher the frequency, the more severe the phase distortion will be. The invention eliminates such phase difficulties by the simultaneous transmission of two waves of different frequencies. The two waves are combined to form a composite signal with offsetting effects that stabilize an overall group wave velocity. Phase distortion is also known as envelope delay distortion and, in conventional transmission methods, the transmitted bit length is greater than or equal to the envelope delay distortion. By using pulse analog-to-digital conversion, a direct relationship between delay distortion and bit width or bit number is avoided in the practice of the invention. Pulse conversion as used herein refers to using analog trigger pulses to instantaneously generate a bit string of any desired length at an output gate. This conversion is almost noise- free because the duration is deterministic and a filter can be designed to nullify distortion effects. The transmission process operates over existing telephone lines 20, both upstream and downstream. Communication rates of a minimum of 8 megabytes per second can be achieved by the invention, which is not limited in application by distance. The transmission rate is determined by the rate at which a trigger pulse is sent to a hex latch, such as hex latches 96 and 98. Each trigger pulse determines the value of a symbol. As shown in step 42, one embodiment of the invention sends a trigger pulse to a hex latch every 0.875 microseconds. The system rate is calculated by multiplying the number of bits per transmission, illustratively 8 bits, and the pulse rate for each bit, 1,142,857 pulses every second. Fig. 1 shows an example of the steps in a typical transmission by data transmission device 10. The process begins with the sender selecting an ASCII character in step 22. ASCII characters are represented by 8 bit binary numbers. The binary ASCII representation of a character is partitioned into upper and lower 4 bit segments in step 24. The lower 4 bits are used to generate a low frequency tone 25 in step 26. In step 28, the upper 4 bits are used to generate a high frequency tone 29. These two tones represent the selected character and are mixed in step 30. After mixing, the tones are transmitted in step 32 over existing telephone lines 20. Fig. 2 shows an example of a typical reception process for a data transmission device 10. The process starts in step 34 with reception of the encoded tones transmitted in step 32 over an existing telephone line 20. The received tones are separated into their high and low frequency components 25 and 29 by analog filter 76 in step 36. In step 38, the binary count is scaled to represent coordinates in a matrix space encoding the ASCII character set. Priority encoding for noise/error recovery is then used in step 40. Step 42 involves a transmission of a 0.875 microsecond pulse at a hex latch 96 or 98 for each of the 8 bits in the transmitted character. Fig. 4 shows a transmitting circuit 12 according to one embodiment of the invention in more detail. Transmitter circuit 12 includes a binary input divider 44, where the 8 bit binary number corresponding to the selected ASCII character is input to the transfer device 10. The 8 bit binary number of the binary input divider 44 is divided into 2 four-bit binary numbers. One four-bit binary number is sent to a first decoder 46 and the second four-bit binary number is sent to a second decoder 48. Each decoder 46 and 48 accepts as input a four bit binary number which causes one of the 16 output pins of the decoder 46 and 48 to go to a positive voltage. Each decoder 46 and 48 is connected to an OR gate 50, 52, 54 and 56. The output of each of the OR gates 50, 52, 54 and 56 is connected to the open/closed pin of a corresponding switch 58, 60, 62, and 64. The contact arm of each of the first switch 58, second switch 60, third switch 62, and fourth switch 64 is connected to a Wein bridge oscillator circuit 66. The contact pins of the first switch 58, second switch 60, third switch 62, and fourth switch 64 are connected to the base of an output transistor in a transistor array 68. Each decoder 46 and 48 generates a tone by interacting with the Wein bridge oscillator circuit 66 through the OR gates 50, 52, 54 and 56. The two tones 25 and 29 are then mixed in transistor array 68. The mixed tones 25 and 29 are transferred from the transistor array 68 to a telephone connection 70. Telephone connection 70 provides an interface to connect the transfer device 10 to an existing telephone line 20 for transmission of the composite tone. An example of the operation of the transmitting circuit will now be described with reference to the ASCII character code for the character "E". The binary representation of "E" is 01000101 (ASCII coding actually employs the last 7 bits of an 8-bit word, with a leading zero). When the binary number is received, it is divided into the lower four bits and the upper four bits by the binary input divider 44. The upper four bits are transferred from binary input divider 44 to a first decoder 46 and the lower four bits are transferred from binary input divider 44 to a second decoder 48. The first and second decoders 46 and 48 transform the two binary numbers into a positive voltage on each chip's pin position. These pins are connected to the input of the first OR gate 50, second OR gate 52, third OR gate 54 and fourth OR gate 56. Each OR gate is connected to a corresponding switch 58, 60, 62, and 64. If the pin output from either the first decoder 46 or the second decoder 48 for a respective OR gate 50, 52, 54, and 56 is at a positive voltage, the corresponding switch 58, 60, 62 and 64 of the respective OR gate 50, 52, 54. 56 closes. Closing of one of the switches, 58, 60, 62, or 64, transfers the input from the oscillator 66 to the base of the transistor array 68. The input to the transistor array 68 is thus a sinusoidal wave form. The application of this waveform to the transistor array 68 sends a waveform to the telephone line 20 through telephone interface 70. This process is also carried out on the lower four bits whose waveform appears at the array 68 at the same time as the upper four bits. Two signals are thus mixed and transmitted through the telephone line 20, the two signals being separated on the reception side into a low frequency wave 25 and a high frequency wave 29. This separation is performed with analog filter 76, as illustrated in Fig. 5. Once the appropriate high and low pass analog filter 76 passes the two waves 25 and 29, they are input to a zero crossing chip, for example, a commercially available NTE995. When a sinusoidal wave passes through a capacitor, such as in the zero crossing chip, it oscillates near zero, as illustrated in Fig. 6. Each time the wave crosses zero, the chip generates a trigger pulse. The reception process according to one embodiment of the invention will be further discussed with reference to Fig. 5. Fig. 5 shows a receiving circuit 14 for receiving an acoustic wave and transforming that wave into a binary number. The transformation process is initiated by a separation of the composite wave into the low and high frequency components. The composite wave is transmitted over existing telephone line 20 and input to the receiving circuit 14 through the telephone connection 72. The two input waves are transferred to an operational amplifier configuration 74. The operational amplifier configuration 74 includes a capacitor in series with an operational amplifier, thus allowing the configuration to emulate an inductor. By scaling the appropriate values of capacitors and resistors, a bandpass or high frequency filter can be constructed. The composite signal is received at 74 and separated by filter 76. Filter 76 separates the high frequency and the low frequency waves. According to one embodiment, filter 76 includes an internal chip circuit called a charge pump, that includes a capacitor and resistor to differentiate the output of the filter 76. Filter 76 can also include a battery and leakage voltage circuit to reduce the negative spikes of the differentiated wave, particularly when coupled with a reverse bias diode and output transistor acting as an emitter follower. The differentiated high frequency wave is input to a first flip flop 78 while the low frequency wave is input to a second flip flop 80. As the low or high frequency wave crosses zero, an output pulse is generated from the filter and input to the corresponding flip flop 78 or 80. Each flip flop 78, 80 switches from an on off position and vice-versa in response to trigger pulses from the filter 76 as its corresponding wave crosses zero. Flip flop 78 is coupled to a timer 82 through a first switch 84. Flip flop 80 is coupled to the timer 82 through a second switch 86. The output of switch 84 is input to a first counter 88 and the output of switch 86 is input to a second counter 90. Flip flop 80 is also coupled to a first edge detector 92 and flip flop 78 is coupled to a second edge detector 94. Edge detector 92 clears the counter 88 and transfers its count to a first hex latch 96. Similarly, second edge detector 94 clears counter 90 and transfers its count to a second hex latch 98. The binary numbers registered in the first and second hex latches 96 and 98 are transferred to a binary output 100. Binary output 100 combines the two binary inputs to generate a received ASCII character. The generation of a received character involves transferring the binary count of the low and high frequency wave components to an EEROM. The binary representation of each wave, high and low, is transferred to a separate EEROM and then to a separate decoder. Each decoder produces a voltage at a certain location an a grid representing an ASCII character space. The binary representation of the low frequency wave generates a voltage at an x-coordinate while that of the high frequency generates a voltage at a y-coordinate. The location of the x,y coordinate pair determines which character is generated in an ASCII character array. A high speed data transmission device 110 according to a second embodiment of the invention is illustrated in Figs. 7-15. Data transmission device 110 generally includes a transmitting circuit 112 shown in Fig. 8 and a receiving circuit 114 shown in Fig. 9. The device 110 can be used with any transmission medium such as twisted pair copper wires, fiber optic cables, coaxial cables and wireless transmission but is again described with reference to existing twisted pair copper telephone lines. An octal bus buffer 115, shown in Fig. 11, can be used for the pulse conversion in this embodiment of the invention. The bus buffer 115 is configured to link two buses, 117 and 1 19. An enable interface 121 connects to input pins 201 and 219 and controls the operation of buffer 115. A trigger pulse with a defined pulse width is input to enable interface 121 to switch the interface 121 from a high voltage state to a low voltage state and vice versa. When a high voltage is applied to enable interface 121, input pins 203, 205, 207, 209, 212, 214, 216, and 218 of buffer 1 15 are placed in a high impedance state and function to isolate bus 117 from bus 119. Input pins 202, 204, 206, 208, 211, 213, 215, and 217 have a permanent ASCII character bank encoded in them. When the enable interface 121 is brought from a high voltage level to a low voltage level, the ASCII character is transferred from bus 117 to bus 119 within the trigger pulse width. This generates an emission rate of 8 bits per delta T, where T is the pulse width of the trigger pulse. Fig. 8 shows transmitting circuit 112 of data transmission device 110. Eight bit data bytes 1 16 are input to buffer 115 from bus 117. The output of buffer 115 is connected by bus 119 to EEROM's 118 and 120. EEROM's 118 and 120 begin the transformation of each of the succession of data bytes 1 16 into a pair of acoustic tones. EEROM 118 inputs and outputs eight bits to a decoder 122. Likewise, EPROM 120 inputs data byte 1 16 and outputs eight bits to a decoder 124. Decoders 122 and 124 transform the eight bit inputs from EEROM's 118 and 120 into acoustic tones selecting two audio oscillator frequencies based on the inputs. Decoder 122 selects a low frequency and decoder 124 selects a high frequency. Fig. 10 shows one example of a frequency allocation table for ASCII characters. The low frequency tone is transferred into a null point intercept (NPI). An NPI is composed of a low frequency and a high frequency wave and has a time duration that is two wavelengths of the lowest frequency wave. NPI is a unit of transmission and is used in conjunction with a finite frequency extraction filter. To begin the transformation, the low frequency tone is input to a zero crossing chip 124. The low frequency input pulses are shaped into trigger pulses for a J-K flip/flop 128 by a shaping circuit 130. Shaping circuit 130 develops a trigger pulse for J-K flip/flop 128 based on the low frequency tone. The illustrated J-K flip/flop 128 is configured to divide by five. The J-K flip/flop 128 activates a square wave oscillator 132. An example of a square wave oscillator 132 is shown in Fig. 14. The square wave oscillator transmits pulses to a missing pulse detector 134. An example of the missing pulse detector 134 is shown in Fig. 15. Detector 134 resets the counter every fifth pulse such that the output is low and decoders 122 and 124 are reset to zero. This process creates an NPI by permitting the tones generated to be mixed for two cycles of the lower frequency. A tone allocation table for ASCII characters is illustrated in Fig. 10. The tones, high and low, are generated by tone generators 136 and 138. Generator 136 generates a low frequency tone and generator 138 generates a high frequency tone. An example of a tone generator is shown in Fig. 13. The two tone signals are mixed in a mixing circuit 140 to form a composite output signal 142. The composite output signal 142 is transmitted across a telephone interface 70 and is received by a receiving circuit 1 14. An example of a receiving circuit 114 is shown in Fig. 9. The composite signal 142 transmitted through interface 70 across telephone lines 20 is input to receiving circuit 114 through a low pass filter 144 and a high pass filter 146 Fig 12A shows an example of composite signal 142 and Figs 12B and 12C show signal 142 after passing through low pass filter 144 and high pass filter 146, respectively The filtered low frequency signal is sampled and shaped into trigger pulses for J-K flip/flop square wave oscillator 150 which continues to output until a second tπgger pulse turns it off The action of oscillator 150 results m an output pulse that resets the J-K flip/flop 148 and a binary counter clock 152 The binary counter 152 converts the pulses from oscillator 150 into a binary number that is the address of an ASCII character stored m an EPROM 154 A similar process takes place for the filtered high frequency signal as it passes from filter 146 through a J-K flip/flop 156, a square wave oscillator 158, and a binary counter 160 to an EPROM 162 EPROM 162 generates an ASCII character EEROM's 154 and 162 output the ASCII information to respectn e decoders 164 and 166 Decoders 164 and 166 receive and generate the transmitted ASCII characters Decoder 166 also generates a second tπgger pulse that activates an oscillator 168 which traverses a tessellate, or character space arra> The resulting characters generated by the EPROM 154 and decoder 164 and EPROM 162 and decoder 166 are combined m an AND switch 169 that passes the wave from oscillator 168 that is traveling through the tessellate to the designated latch A third pulse is combined with the designated latch of the hard-wired ASCII character, and a proper bit rate is achieved by controlling the pulse width of the third pulse A method for data transmission according to the second embodiment is illustrated m Fig 7 Processing starts with the generation of frequency tones using Wem bπdge oscillators 136 and 138 m step 170 A high frequency signal, step 172, and a low frequency signal, step 174, are generated by the oscillators based on a data input 1 16 After generation, the high and low frequency signals are mixed to form a composite signal 142 in step 176. The composite signal 142 is used to create an NPI, step 178. The NPI is then transmitted over a transmission medium in step 180. The transmitted NPI is received in step 182 and immediately separated in step 184. The NPI is separated into the high frequency signal, step 186, and the low frequency signal, step 188. Both high and low signals are converted into binary number in steps 190 and 192 respectively. The high signal binary number is transformed into a y coordinate in step 194, and the low signal binary number is transformed into an x coordinate. A trigger pulse is also generated by the high signal binary number in step 198. The trigger pulse controls the rate at which each new character is generated or released from the character grid. In step 199, the x and y coordinates of steps 194 and 196 are combined in the AND switch 169 to generate a pulse for a latch on an ASCII-encoded tessellate. The x and y coordinates correspond to a latch on the tessellate and the AND switch 169 passes a pulse to the latch corresponding to the x and y coordinates. Each latch encodes a unique ASCII character. Once a particular latch is isolated by the generated x and y coordinates, a pulse for the AND switch is sent to that latch and the encoded character is generated or released at the time the trigger pulse is received at the latch. The pulse from step 198 is combined with the pulse from step 199 at the designated latch to indicate a transmitted character. The system is reset in step 200 by releasing the latch associated with the indicated character. Thus, a high speed data transmission device 10 according to an embodiment of the invention illustrated in Fig. 3 generally includes a transmitting circuit 12 and a receiving circuit 14. The data transmission device 10 can be used to transmit data over any transmission medium such as twisted pair copper wires, fiber optic cables, coaxial cables, and wireless transmission but is described herein with reference to existing twisted pair copper telephone lines. As illustrated in Fig. 3, data transmission device 10 can be installed at a first location 16 and communicate with another data transmission device 10 installed at a second location 18 connected over conventional twisted pair copper telephone line 20 In an embodiment descnbed herein, data transport may be accomplished through m-band signaling of tone pairs or other groupings, whose component waves may be configured to differ in amplitude or other characteπstics The data transmission device 10 can be connected to the telephone line 20 using standard telephone line cord typically provided with telephones or modems, connecting at one end to the transmission device 10 with an RJ-1 1 jack and the other end to an existing telephone line outlet The data transmission device 10 can provide high speed data transfer between like transmission devices 10 over existing telephone lines 20 using a new form of data representation employed by the mvention The data transmission device 10 accordmg to an embodiment of the invention converts input digital signals into analog signals for transmission, without the use of D/A converters or the quadrature amplitude modulation typically used by conventional data transmission processors or modems The data transmission is achieved by converting binary numbers into acoustic tones of audible frequencies, which can be transmitted more efficiently than conventional quadrate amplitude modulation systems The process is a fulK duplex system where the final conversion of an analog "trigger" wave takes place at the receiving circuit 14 installed m a recipient computer, pπnter, oi other medium Data transmission over telephone voice channels is limited by phase distortion in the transmission wave The shorter the wavelength or higher the frequency, the more severe the phase distortion will be The invention eliminates such phase difficulties by the simultaneous transmission of two oi more waves of different frequencies The waves are combined to form a composite signal with offsetting effects that stabilize an overall group wa\ e velocity The transmission process operates over existing telephone lines 20, both upstream and downstream. The transmission rate is determined by the number of bytes either simultaneously modulated in pairs with the minority amplitude designating the second character. The transmission rate is further affected by the mode of transmission, chirp mode or continuous mode. The chiφ mode separates a continuous stream of characters by partitioning frequencies (tone separators) referred to as chhps. The continuous mode transmits a continuous stream of characters and holds them on the transmission line until processed by a receiver. Fig. 16 shows an example of the steps in a typical transmission by data transmission device 10 in a third embodiment of the invention. The process illustratively begins with the sender selecting an ASCII character in step 2200. ASCII characters are represented by 8 bit binary numbers. Step 2200, two bytes, i.e., 16 bits, designated as bytes 42 and 44 are loaded into an EEPROM as shown in step 2400. The EEPROM is preconfigured to operate according to instructions programmed into the EEPROM. Three preferable modes of wave mixing are a) two tones of fixed time duration is serial configuration without tone separators, b) two tones of fixed time duration in a serial configuration with tone separators, and c) two tones mixed in a parallel manner the duration of which depends on how long it takes to decode them. Of these modes, mode b is the more powerful and will be discussed hereafter. In step 2400, two tones are selected according to the tone selection method programmed into the EEPROM, in general reflecting a matrix representation of ASCII or other data, the axes of the matrix being associated with individual tone components. Illustratively, one tone may be assigned for byte 42 and one tone for byte 44. In step 2600, five operative auxiliary tones may be generated for byte manipulation. The operative auxiliary tones may operate to modify the significance of the information payload when present, such as to adjust: 1) upper case literal or alpha, 2) numeric indicator or numeral, 3) data separator or delineator (chiφ), 4) frequency times ten operator, and 5) frequency divided by two operator. In step 2800, a tone transmission mode is selected. Once the tone transmission mode is selected, the two tones corresponding to bytes 42 and 44 are transmitted along with the tone separators (or chiφs) to the receiver. In step 3000, the transmitted tones received by the receiver for operative decoding. In step 3200, the received tones for bytes 42 and 44 are distributed with one tone to the first byte in and one tone to the second byte in. In step 3400, the distributed tones are sent to a fast digital decoder and then to a phase locked loop. In step 3600, the output tone from the decoder and phase locked loop are sent to a latch. In step 3800, the decoded tone is compared to a reference tone. In step 4000, if the decoded tone does not match the reference tone, a warning may be generated. In step 4200, in the absence of two successful evaluations in step 4000, an error message is generated. Fig. 17 shows one example of a transmitting circuit 1200 using mode (b) noted above, namely two tones of fixed time duration in a serial configuration with tone separators. Two bytes designated as bytes "A" (42) and "B" (44) are loaded into EEPROMs 4600 and 4800. The EEPROMs 4600 and 4800 are programmed to select two tones associated with the input binary numbers. A sequencer 5000, composed of a square wave oscillator 5200 and two "D" flip- flops 5400 and 5600 and NOR gates 5800, 6000, 6200, and 6400, releases a square wave signal to activate a switch 6600. This closes the relay and releases a data tone 6800 through a capacitor 7000 and attenuated by a resistor 7200 to the operational amplifier 7400. After a specified time, a second pulse from 5200 multiplexes and creates a high on NOR gate 6000. This closes 7600 and releases a separator tone through 7800 into amplifier 7400 to the telephone line 20. Again after a specified time, 5200 emits another pulse that makes NOR gate 6200 high which closes 8000 which releases data tone 8200 through capacitor 8400 to amplifier 7400 and releases composite tone output to the telephone line 20. Finally, oscillator 5200 releases a fourth pulse which makes NOR gate 6400 high and closes switch 8600 which transfers separator tone 8800 through capacitor 9000 to amplifier 7400 to the telephone line 20. Step 3000 consists of the manipulation of auxiliary tones. These tones may be adjustments to encoded data to create: 1) upper case literals or alpha, 2) numeric indicator or numeral, 3) data separator or delineator, 4) frequency times ten operator, and 5) frequency divided by two operator, or other modifications. These five auxiliary tones add versatility to the 26 lower case literal or alpha tones representing the 26 letters of the alphabet, or that subset of the ASCII character set by permitting modifications to the fixed character representations. In another embodiment, the reception of two tones close in frequency over a noisy telephone line is performed by dividing one tone frequency by two and then decoding of the tone. Thus, the transmission reliability can be enhanced at the receiver. The distribution process indicated in step 3200 of Fig. 16 according to one embodiment of the invention will be discussed with reference to Fig. 18. Fig. 18 shows a bandpass filter 9200 consisting of operational amplifier ("AMP") 9400, resistors 9600, 9800, 10000, capacitors 10200 and 10400. The distribution process also includes a comparator 10600 including AMP 10800 and AMP 11000. The voltage of the input is divided by upper voltage divider 11200 and lower voltage divider 11400. Voltage divider 11200 includes resistors 11600 and 11800 and sets the upper voltage limit 12000. Voltage divider 11400 includes resistors 12200 and 12400 and sets the lower voltage limit 12600. The input tones are filtered by AMP 9400 and bandpass filter 9200. The filtered frequency is compared by voltage dividers 11200 and 11400 to fix its position according to reference points 12000 and 12600. Any voltage excess above upper voltage limit 12000 is regarded as excessive and activates an error warning. An output from comparator 10600 between limits 12000 and 12600 is designated as a first byte. Anything below lower voltage limit 12600 is regarded as a second byte. The tones, first and second bytes, are further transferred to the evaluation phase, step 3400. The tone evaluation phase of step 3400 according to one embodiment will be discussed with reference to Fig. 19. A digital decoder 12800, shown in Fig. 19, includes three main components. The first section consists of diode 13000, resistors 13200 and 13400, capacitor 13600, and AMP 13800. The first section converts a sinusoidal tone into a series of square wave pulses designated 14000 and 14200. These pulses are in effect used as start and stop pulses for the counting process. The second section consists of J-K flip- flop 14400 and a-stable multi -vibrator constructed by using a timer chip 14600 to supply counting pulses to assist in synchronizing receipt of tone-encoded data. The initial configuration has the "Q" output of flip-flop 14400 in a low state, i.e., zero. When the pulses 14000 clocks flip-flop 14400, the "Q" output goes high, i.e., one, and closes switch 14800. This transfers the pulses generated by the timer 14600 to a binary counter 15000. This accumulates a count until pulse 14200 clicks flip-flop 14400 back to its Q = O state. The count is compared to the expected count through the NOR gate assembly 15200. If the count is equal to the expected count, the proper byte is loaded into the proper character position, and synchronization and data validity may be assumed. Simultaneously, the same tone is sent to a third section or phase locked loop 15400 for evaluation. The output waves are compared to a reference wave 15600. If equal, the digital byte or other encoded data is released to the data bus. The decoding process is a significant facet of the receiver according to the invention, and permits a fast digital decoding process in part because triggering or synchronization is accomplished in less than a full sinusoidal cycle, as illustrated in Fig. 20. One embodiment of digital decoding will be discussed according to that figure. As shown in Fig. 20, bandpass filter 15800 is made up of resistors 16000, 16200, 16400, and AMP 16600 and filters input signal 16800. The signal 16800 is then tuned and amplified by circuit 17000 and passed on to the phase control circuit 17200. The phase control circuit 17200 includes resistors 17400, 17600, 17800, diode 18000, and a silicon-controlled rectifier 18200. Resistor 17800 and diode 18000 determine a voltage point 18400, which is located between 90° and 180° of the input wave 16800. The angle at which the voltage 18400 is located represents the point at which conduction of rectifier 18200 begins and continues until the wave crosses zero. The process of digital decoding relative to this embodiment consists of supplying the start pulses to a high frequency oscillator and then a stop pulse that marks the termination of a process. The pulses generated between the beginning and termination interval are counted by a binary counter. The comparator circuit 18600 includes resistors 18800, 19000, 19200, and 19400, and differential amplifiers 19600 and 19800. The decoding circuit 18600 determines the beginning and termination points relative to the input signal wave 16800, between which digital counting takes place. The counting process is executed by the J-K flip-flop 20000, high frequency oscillator 20200, switch 20400, and binary counter 20600. In its initialized state, the flip-flop 20000 has its "Q" output equal to zero. The signal input wave reaching voltage level 20800 exceeds a reference point 21000 determined by resistors 18800 and 19000 in comparator circuit 18600. This produces an output wave from differential amplifier 19600 and pulse-shaping device 21200 that toggles flip- flop 20000 that activates switch 20400 and begins counting. The input wave 16800 moves to voltage level 18400 and activates differential amplifier 21400 that toggles the flip-flop 20000 back to Q = O state. This terminates counting. The observed count is compared with the expected count 21600. If the count is equal to the expected value, the corresponding ASCII character 21800 is selected. If the expected count is not observed, this activates a decoding process, outlined in Fig. 23. As shown in Fig. 23, a decoding process may begin with the application of an analog bandpass filter in step 30200. In step 30400, the amplitude of received tone signals may be examined on a FIFO basis. In step 30600, a decoding may be performed for instance as illustrated in Fig. 20, in which an individual tone may be isolated by detecting a point A on the leading edge of a predefined tone near peak amplitude, and a point B on the trailing edge which when both present uniquely identifies one of the tone group. In this regard, different components of a tone pair or other groupings may be impressed with different amplitudes according to a generator embodiment shown in Fig. 22, generally similar to other circuitry discussed herein but developing tones of different absolute amplitude. Thus point A may be associated with particular transmitted tone components. Fig. 21, in contrast, illustrates an embodiment of the invention in which two tones may be generated according to a fixed duration of length, but having no embedded separators. Returning to the processing of Fig. 23, in step 30800 a comparison of the (1/4) wave or other fast-trigger decoding is made to an expected result of counts or other criteria. In step 31000, if that result accords with the expected result, in step 33000 an ASCII character is selected, followed by delivery of a corresponding byte of date into an output FIFO buffer in step 33200, delivery to a data output bus in step 33400 for transmission, and an end point in step 33600. Alternatively, in step 31000 if the result of the fast decoding is not the expected value, in step 31200 a decoding process according to full wavelength interval is performed. In step 31400, that result is compared to the expected result of count or other criteria, and if in accord processing proceeds to step 33000 for output. If the result of full-cycle decoding does not match the expected result, in step 31800 a phase locked loop decoding may be performed, and the result compared with the expected result in step 32200. If the result is in accord with the expected result, processing proceeds to step 33000 for output. If the comparison of step 32200 does not match the expected results, in step 32400 the receiver is searched for possible tone pairings that my represent two correct decodings. If such a decoding is found, in step 32600 the receiver is reset, otherwise the receiver issues an error message in step 32800, where processing may likewise end in step 33600. Other embodiments and uses of the invention will be apparent to those skilled in the art from consideration of the specification, which should be considered exemplary only. For instance, while the mvention has been described in terms of the transmission of 8-bit ASCII characters, other data formats such as Unicode and others may be employed. For further instance, while the invention has been described in terms of the transmission of 8-bit ASCII characters, other data formats such as Unicode and others may be employed. The scope of the invention is intended to be limited only by the following claims.

Claims: WHAT IS CLAIMED IS: 1. A method of data communication, comprising the steps of: a) receiving a binary input for transmission; b) generating a first signal and a second signal based on the binary input; c) combining the first signal and the second signal to form a composite signal representing the binary input; and d) transmitting the composite signal. 2. The method of claim 1, wherein the first signal comprises a high frequency signal and the second signal comprises a low frequency signal. 3. The method of claim 2, further comprising the step of (e) splitting the binary input into a first portion and a second portion. 4. The method of claim 3, wherein the first portion corresponds to the high frequency signal and the second portion corresponds to the low frequency signal. 5. The method of claim 4, wherein the binary input comprises an ASCII character code. 6. The method of claim 5, wherein the most significant four bits of the ASCII character code correspond to the high frequency signal, and the least significant four bits of the ASCII character code correspond to the low frequency signal. 7. The method of claim 1, wherein the composite signal comprises audio frequency tones. 8. The method of claim 7, wherein the audio frequency tones are transmitted over telephone lines. 9. The method of claim 1, further comprising the step of (f) receiving the transmitted composite signal. 10. The method of claim 9, further comprising the step of (g) separating the transmitted composite signal into a first received signal and a second received signal. 11. The method of claim 10, further comprising the step of (h) generating a binary output based on the first received signal and the second received signal. 12. The method of claim 11, wherein the step of (h) generating the binary output comprises the step of addressing an ASCII character array using the first received signal and the second received signal. 13. A system for data communication, comprising: an input interface for receiving a binary input for transmission; a generator unit, communicating with the input interface, the generator unit generating a first signal and a second signal based on the binary input; a combining unit, communicating with the generator unit, the combining unit combining the first signal and the second signal to form a composite signal representing the binary input; and an output interface, communicating with the combining unit, the output interface transmitting the composite signal. 14. The system of claim 13, wherein the first signal comprises a high frequency signal and the second signal comprises a low frequency signal. 15. The system of claim 14, further comprising a splitter unit, the splitter unit splitting the binary input into a first portion and a second portion. 16. The system of claim 15, wherein the first portion corresponds to the high frequency signal and the second portion corresponds to the low frequency signal. 17. The method of claim 16, wherein the binary input comprises an ASCII character code. 18. The system of claim 17, wherein the most significant four bits of the ASCII character code correspond to the high frequency signal, and the least significant four bits of the ASCII character code correspond to the low frequency signal. 19. The system of claim 13, wherein the composite signal comprises audio frequency tones. 20. The system of claim 19, wherein the composite signal is transmitted over telephone lines. 21. The system of claim 13, further comprising a receiving unit for receiving the transmitted composite signal. 22. The system of claim 21, further comprising a separating unit for separating the transmitted composite signal into a first received signal and a second received signal. 23. The system of claim 22, further comprising an output generator unit for generating a binary output based on the first received signal and the second received signal. 24. The system of claim 23, wherein the output generator unit generates the binary output by addressing an ASCII character array using the first received signal and the second received signal. 25. A system for data communication, comprising: input interface means for receiving a binary input for transmission; generator means, communicating with the input interface means, the generator means generating a first signal and a second signal based on the binary input; combining means, communicating with the generator means, the combining means combining the first signal and the second signal to form a composite signal representing the binary input; and output interface means, communicating with the combining means, the output interface means transmitting the composite signal. 26. The system of claim 25, wherein the first signal comprises a high frequency signal and the second signal comprises a low frequency signal. 27. The system of claim 26, further comprising splitting means, the splitting means splitting the binary input into a first portion and a second portion. 28. The system of claim 27, wherein the first portion corresponds to the high frequency signal and the second portion corresponds to the low frequency signal. 29. The system of claim 25, wherein the binary input comprises an ASCII character code. 30. The system of claim 29, wherein the most significant four bits of the ASCII character code correspond to the high frequency signal, and the least significant four bits of the ASCII character code correspond to the low frequency signal. 31. The system of claim 25, wherein the composite signal comprises audio frequency tones. 32. The system of claim 31, wherem the audio frequency tones are transmitted over telephone lines. 33. The system of claim 25, further comprising receiving means, the receiving means receiving the transmitted composite signal. 34. The system of claim 33, further comprising separating means, the separating means separating the transmitted composite signal into a first received signal and a second received signal. 35. The system of claim 34, further comprising output generator means, the output generator means generating a binary output based on the first received signal and the second received signal. 36. The system of claim 35, wherein the output generator means generates the binary output by addressing an ASCII character array using the first received signal and the second received signal. 37. A method of data communication, comprising the steps of: a) receiving a binary input for transmission; b) generating a first signal and a second signal based on the binary input, the first signal and the second signal differing in at least one characteristic other than frequency; c) combining the first signal and the second signal to form a composite signal representing the binary input; and d) transmitting the composite signal. 38. The method of claim 37, wherein the first signal comprises a high frequency signal and the second signal comprises a low frequency signal. 39. The method of claim 38, wherein the binary input comprises an ASCII character code. 40. The method of claim 37, wherein the composite signal comprises audio frequency tones. 41. The method of claim 40, wherein the at least one characteristic comprises amplitude. 42. The method of claim 41, further comprising a step of (e) receiving the transmitted composite signal. 43. The method of claim 42, further comprising a step of (f) separating the transmitted composite signal into a first received signal and a second received signal by detecting the at least one characteristic. 44. The method of claim 43, further comprising the step of (f) separating comprises a step of (g) detecting the amplitude in less than (1/2) cycle of the first received signal or the second received signal. 45. The method of claim 44, further comprising a step of (h) generating a binary output by addressing an ASCII character array using the first received signal and the second received signal. 46. A system for data communication, comprising: an input interface for receiving a binary input for transmission; a generator unit, communicating with the input interface, the generator unit generating a first signal and a second signal based on the binary input, the first signal and the second signal different in at least one characteristic other than frequency; a combining unit, communicating with the generator unit, the combining unit combining the first signal and the second signal to form a composite signal representing the binary input; and an output interface, communicating with the combining unit, the output interface transmitting the composite signal. 47. The system of claim 46, wherein the first signal comprises a high frequency signal and the second signal comprises a low frequency signal. 48. The system of claim 47, wherein the binary input comprises an ASCII character code. 49. The system of claim 48, wherein the composite signal comprises audio frequency tones. 50. The system of claim 49, wherein the at least once characteristic comprises amplitude. 51. The system of claim 50, further comprising a receiving unit for receiving the transmitted composite signal. 52. The system of claim 51, further comprising a separating unit for separating the transmitted composite signal into a first received signal and a second received signal by detecting the at least one characteristic. 53. The system of claim 52, further comprising an output generator unit for generating a binary output based on detecting the amplitude in less than (1/2) cycle of the first received signal or the second received signal. 54. The system of claim 53, wherein the output generator unit generates the binary output by addressing an ASCII character array using the first received signal and the second received signal. 55. A system for data communication, comprising: input interface means for receiving a binary input for transmission; generator means, communicating with the input interface means, the generator means generating a first signal and a second signal based on the binary input, the first signal and the second signal differing in at least one characteristic other than frequency; combining means, communicating with the generator means, the combining means combining the first signal and the second signal to form a composite signal representing the binary input; and output interface means, communicating with the combining means, the output interface means transmitting the composite signal. 56. The system of claim 55, wherein the first' signal comprises a high frequency signal and the second signal comprises a low frequency signal. 57. The system of claim 55, wherein the binary input comprises an ASCII character code. 58. The system of claim 57, wherein the composite signal comprises audio frequency tones. 59. The system of claim 58, wherein the at least one characteristic comprises amplitude. 60. The system of claim 59, further comprising receiving means, the receiving means receiving the transmitted composite signal. 61. The system of claim 60, further comprising separating means, the separating means separating the transmitted composite signal into a first received signal and a second received signal by detecting the at least one characteristic. 62. The system of claim 61, further comprising output generator means, the output generator means generating a binary output by detecting the amplitude in less than (1/2) cycle of the first received signal or the second received signal. 63. The system of claim 62, wherein the output generator means generates the binary output by addressing an ASCII character array using the first received signal and the second received signal.

Inventors: CAIRNS JOHN P, CAIRNS, JOHN, P.
Applicants: DATAMEG CORP, DATAMEG CORP.
Application year: 2000
Main classification: H04M11
IPC codes: H04L27