TRANSACTION CLASS

Abstract: A system and method for circuitry design verification testing which provides for maximized code re-use without unnecessary allocation of system resources. A circuit simulation subsystem is interfaced with a test subsystem. The test subsystem employs a system transaction class which collects convenience routines and thereby maximizes code re-use. The system transaction class contains pointers to device transaction classes which correspond to each of the functional models in the simulation subsystem, but does not require instantiation of all of the device transaction classes and associated device objects. One or more configuration transaction classes derived from the system transaction class define transactions between selected ones of the functional models within the simulation subsystem. The configuration transaction classes inherit the convenience routines of the system transaction class, but cause instantiation of the respective functional models only when needed for a transaction.

Description: TITLE: TRANSACTION CLASS BACKGROUND OF THE INVENTION 1 Field of the Invention The present invention relates generally to computer ystems an runt, particularly to methods and apparatus for facilitating the testing and verification of integrated circuit designs usmg simulation tools 2 Description of the Relevant Art Because of the complexity of the circuitry in modern mtegrated circuits (ICs), the design of the circuitry is thoroughly tested before the actual circuit is manufactured The testing is mtended to identify errors m the design of the circuitry so that the errors can be corrected with minimal effort and expense Typically, this testing is accomplished by simulating the functioning of the circuitry on a computer system usmg a hardware descπption language (References herein to "HDL" will indicate a hardware reference language which may be Veπlog or any other hardware descnption language ) The design engmeers use an HDL to generate a detailed functional description of the circuitry including, for example, the input signals to be provided to the circuitry and the output signals which are produced in response thereto The descπption of the circuitry may compπse descriptions of sub-components or "cells" and the interrelationships between these components The resulting model can be used to simulate the behavior of the circuitry The HDL model of the circuitry is implemented in a simulation system to verify the proper functioning of the circuitry The simulation system may compπse any one of a number of such systems, one example bemg the Veπlog system, which is well known to those in the art "Venlog" also refers to a particular HDL The simulation system accepts data which defines the behavior of the circuitry as well as the signals to be input to the circuitry and, m response, generates data corresponding to simulated output signals Traditionally, the entire simulation system, including the functional descπption of the newly designed circuitry, has been wntten in HDL Because HDL is used to form a detailed functional descπption of circuitry such as ASICs (Application-Specific Integrated Circuits), it is by nature a specialized and complex language With the increasing complexity of these circuits, veπfication of functionality at the gate level is often insufficient because of the difficulty of observing the internal state of the circuitry at its I/O interface Further, generatmg a set of tests for this circuitry can be a dauntmg task smce HDL does not have many of the features which are found in higher-level languages and which make it easier for programmers to handle large software projects It is therefore desirable to have an interface mechanism which allows tests wntten in higher-level languages to control a simulation wntten m HDL The need to allow tests to be wntten in high level languages and then interfaced to the HDL resulted in the development of interface systems such as CVI CVI is descnbed m U S Patent No 5,732,247 to Dearth, et al CVI allows tests to be wntten m higher-level languages such as C and C++ and serves as an interface between the HDL simulation system and the higher-level-language test system CVI translates the test statements to simulated bus activity in the simulation system CVI is particularly useful in the development of simulation systems because the venfication engmeers who wnte the test procedures normally are not the same engmeers who wnte the functional descπption of the new circuitry One important aspect of the CVI mechanism is that it allows the design of device objects which present a low-level register interface to the test writer This is useful because it presents the test wnter with a consistent interface style shared by all transactors and provides a consistent documentation format The low-level register interface is also intuitively appealing because the register model mimics modern computer system operation and is well understood by programmers The CVI mechanism introduces a device dπver abstraction which shields users from the low-level details of complex circuitry This level of abstraction agam provides test wnters with a consistent view of many dissimilar devices The device dnvers in the simulation system maintain state information regarding the devices in order to simplify control and schedulmg of the operations of the device SUMMARY OF THE INVENTION The issues surrounding the abstractions outlined above may be solved by vaπous embodiments of the system and method of the present invention One embodiment of the invention compnses a simulation system configured to model a circuit design and a test system configured to operate in cooperation with the simulation system The systems compnse one or more software applications which may be stored on computer-readable media such as magnetic disks or tape, and which may be executed on a suitable computer system In one embodiment, a mechanism is provided to facilitate testmg of circuitry designs m a device simulation environment The mechanism is implemented in a high-level programming language and is used m conjunction with a simulation system, which is wntten in an HDL, and a simulation system interface The mechamsm simplifies test wnting by performing a function similar to that of an operating system device dnver The mechanism provides consistent high-level interfaces to device objects, device object information hidmg, simplification of random environment testmg, effective parallel operation without threading, state driven test wnting style, encapsulation/aggregation of convenience routines, simplification of device object configuration management and storage of parameters for convemence routines m class member vanables One embodiment of the invention compnses a hierarchical set of transaction classes The uppermost class defines a base transaction All transaction classes rnhent from this class Below the base transaction class are a device transaction class and a system transaction class The device transaction class is associated with the device class through an object reference The system transaction class is used to collect convenience routines The system transaction class contams pointers to each of the required device transaction classes The next level m the hierarchy mcludes one or more configuration transaction classes which reference selected device objects This class structure provides a mechamsm through which a test wnter can easily wnte and mamtam program code to test a simulated device The system transaction class provides an infrastructure upon which the test wnter can build the code The system transaction class contams pomters to device transaction objects for all of the devices m the simulated system and aggregates the convemence routines which may be useful in wnting the tests. The system transaction class is not instantiated directly, but is instead used as the basis for the configuration transaction classes Each configuration transaction class represents a selected subset of the devices in the simulated system and is instantiated to test transactions mvolvmg the corresponding devices Because the configuration transaction classes use object references to the device objects, the user is forced to supply the appropπate device objects at the time of instantiation and the compiler is therefore able to perform static type checking The configuration transaction classes thus enable the test wnter to use all of the convenience routines defined m the system transaction class while only instantiating those device objects which are needed for the corresponding configuration At the same time, the test wnter can more easily maintain the test code because all of the convenience routines are wntten only once and collected m the system transaction class. BRIEF DESCRIPTION OF THE DRAWINGS Other objects and advantages of the mvention will become apparent upon readmg the following detailed descnption and upon reference to the accompanying drawings m which: Fig. 1 is a functional diagram of a simple simulation system m one embodiment of the mvention Fig. 2 is a block diagram of a design venfication system m one embodiment of the mvention Fig. 3 is a diagram of a class structure implemented m a test subsystem m one embodiment of the mvention While the mvention is subject to vanous modifications and alternative forms, specific embodiments thereof are shown by way of example m the drawings and will herem be descnbed m detail. It should be understood, however, that the drawmg and detailed descnption thereto are not mtended to limit the mvention to the particular form disclosed, but on the contrary, the intention is to cover all modifications, equivalents and alternatives falling within the spint and scope of the present mvention as defined by the appended claims DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of the mvention is descnbed below In this embodiment, a set of transaction classes is implemented m the test subsystem of a circuit design venficanon system. The test system compnses one or more tests wntten m a high-level language. In this instance, the high-level language is C++ In other embodiments, a different high-level language can be used The test system is used m conjunction with a simulation system which is wntten in a lower-level language such as the Venlog HDL The test system and the simulation system are coupled by an mterface such as CVI In other embodiments, different HDL's and interface systems can be used. The transaction classes provide a mechanism through which a programmer can easily test selected functions m a circuit design The classes form a hierarchy, the top of which is a base transaction class The base transaction class contams several virtual functions which are used to initialize device objects and enable the device objects to handle signals and dnve transacnons during testmg A device transaction class is denved from the base transaction class and is used to provide a level of abstraction between the test wnter and the device objects A system transaction class is denved from the base transaction class and is used to provide an abstracted model of the circuit design under test The system transaction class contams pomters to device transaction classes corresponding to device objects in the design under test. A configuration transaction class is denved from the system transaction class and is used to configure and test selected portions of the circuit design model. Both the device transaction class and the configuration transaction class contain references to device objects and, m fact, the configuration transaction class sets up device transactions for device objects to be used for executing tests. It should be noted that, while the embodiment descnbed here refers to a structure of interrelated classes, the mvention contemplates a structure of interrelated objects as well. As will be appreciated by persons skilled m the art of the mvention, objects are instantiations of classes. The distinction between classes and objects may therefore be viewed as one of code implementation versus memory implementation, or of source code versus executable code. Persons skilled m the art will appreciate these distinctions as well as the fact that the mvention need not be limited to one or the other Accordingly, the references herem to classes are mtended to encompass objects which are instantiated from the classes. Likewise, references to objects are, for the purposes of this descnption, mtended to encompass the classes from which they are instantiated. The design venfication system is designed to be implemented m a general-purpose computer system. The design venfication system compnses a set of software applications which model the functions of a circuit design and perform a senes of tests to verify these functions. It should be noted that, m alternate embodiments, one or more parts of the system can be implemented in hardware designed specifically for that purpose The design venfication system mcludes a test subsystem, a hardware simulation system and an interface subsystem The hardware simulation system is a software application which mcludes functional descnptions of the hardware to be simulated, mcludmg the newly designed circuitry. The hardware simulation system is used to model the operation of the hardware. The simulation system is typically wntten m a computer language specifically designed for that purpose (i.e., an HDL). In this mstance, the simulation system is a wntten m Venlog. The hardware simulation system mcludes a number of functional models representative of portions of the system bemg modeled These functional models will be referred to herem as bus functional models, although it should be noted that the portions of the system bemg modeled may compnse items other than buses. In addition to the bus functional models, the simulation system mcludes a functional model of the newly designed circuitry (1 e. the design under test, or device under test). Referring to Fig. 1, a functional diagram of a simple simulation system 10 is shown The simulation system 10 mcludes a simulation core 18 and a hardware functional model 20 The hardware functional model 20 mcludes a host bus functional model 12 and an I O bus functional model 16 which represent the behavior of the model's interfaces. The functional model of the design under test 14 is inserted mto the system and is operatively coupled to the host and I/O bus functional models 12 and 16, just as the hardware device would be coupled to the hardware buses In operation, the host bus functional model 12 would provide a signal as a stimulus to the design under test 14, which would then respond to this stimulus The stimulus consists of a set of signals which may correspond to a function call or some other command to the design under test The design under test 14 may in turn convey one or more signals to the I/O bus functional model 16 The I/O bus functional model 16 would then convey a responsive signal to the design under test 14, which would subsequently convey a signal to the host bus functional model 12 so that the proper operation of the system could be venfied for the corresponding function A portion of the bus functional models and the design under test are wntten m HDL These functional models interact on a chip I/O level. That is, the models operate on individual bits or signals m the same way the physical devices which they represent operate on individual bits or signals which are mput to the respective devices The models and the corresponding designs can therefore be examined with a very high level of detail This level of detail, however, is very difficult to work with when a programmer is mterested m testmg the high level operations of the devices. For example, if the programmer wants to test a simple function, such as copying a file from one location to another, the number of signals which need to be controlled at the device I/O level may be very high. The programmer therefore needs a mechanism by which he can use a simple command or set of command"- to achieve this mnction mstead of mdividually programmmg each bit signal. In other words, a level of abstraction is necessary to simplify the programmer's task. This level of abstraction is provided by the interface subsystem. The interface subsystem translates test commands m a high-level language (e.g., C or C++) to the appropnate chip I/O level signals m HDL. As a result, the programmer is able to wnte tests m the high-level language. The test system can therefore take advantage of features such as object-oπented programmmg constructs, which are available m the high-level language, but not m the HDL. In one embodiment, CVI (descnbed above) is employed as the interface system As shown m Fig. 2, a block diagram of the design venfication system, test subsystem 32, interface subsystem system 34 and hardware simulation subsystem 36 execute within the environment of operating system 38 The interface subsystem system 34 controls the interaction between the HDL based hardware simulation subsystem 36 and the C++ based test subsystem 32 The interface subsystem allows tests to be wntten usmg an object-onented paradigm and provides the programmer with device objects which translate the tests mto HDL bus signals. Just as the mterface subsystem adds a first level of abstraction between the test wnter and the HDL test environment, the use of object-onented programmmg principles m the test system allows additional levels of abstraction to be obtamed within the test subsystem. For example, system level transactions may be defined to generate activity m several devices m response to a single system level function call Object-onented principles also provide benefits to the programmer such as the ability to re-use code and to hide data from the test subsystem wnter. The test subsystem controls each of the device functional objects m the simulated hardware system in order to venfy the functionality of the design. The test subsystem utilizes device transaction objects to abstract away some of the details of the device operation Configuration transaction objects likewise abstract away some of the details of transactions involving more than one functional device. The configuration transaction objects are denved from a system transaction class m order to group together convenience routines and make them available to the configuration transactions. Convenience routines are functions that simplify the process of managmg test data and control sequences The system transaction class also collects test flow control routines for use m simulation of the configuration transactions Referring to Fig. 3, a diagram of a class structure used in one embodiment of the test system is shown (In Fig. 3, a tnangular shape on the line between the two classes mdicates lnhentance from the higher class ) Object references m the figure are mdicated by an arrow with an accompanying ampersand (&). Pomters are mdicated by an arrow with an accompanymg asteπsk (*) One-to-one relationships between objects and/or classes m the figure are mdicated by an open circle at the head of the corcesponding pomter or object reference arrow. A blackened circle mdicates that there may be one or more pomters or object references The dashed lmes from the configuration transaction classes to the device transaction classes mdicate that the latter are created in the process of instantiating the former Fig 3 shows a hierarchical class structure which has a base transaction class 40 at the top of the class hierarchy Base transaction class 40 is an abstract class which is not directly instantiated Instead, base transaction class 40 serves to provide a set of basic services which are common to all of the transactions The services are provided through methods or functions which are declared m the base transaction class and are inherited by the classes which will be denved therefrom In this embodiment, base transaction class 40 mcludes several virtual functions which are common to all of the transaction classes in the hierarchy The use of a common set of interface function names is necessary to take advantage of polymorphism, which is a useful feature of object-onented programmmg languages Polymorphism allows the programmer to create transaction objects and work with these objects in an abstract way while deferring to run time that task of figunng out which device is actually bemg used Polymorphism provides several other advantages, mcludmg providing consistent high-level interfaces to similar objects, hiding from the programmer object information which he doesn't need to see and simplifying program code by encapsulating object-specific vaπations within the objects themselves In this embodiment, the functions declared by base transaction class 40 include the following ιnιt(), setup_trans(), setup_resp(), and servιce_sιgnal() Inιt() initializes the device associated with the transaction class Setup_trans() enables the associated device to dnve transactions m the simulation Setup_resp() controls how the associated device responds to transactions directed to it Servιce_sιgnal() is called to handle CVI signal messages sent from the HDL to the device A base device class (not shown m the figure) is used m the same manner as the base transaction class One or more sub-classes can be denved from the base device class The sub-classes inhent a common set of methods from the base device class and may define additional methods which are specific to the sub-classes The base device class and its sub-classes enable the instantiation of the device objects which are shown in the figure Through mhentance, the base device class provides a common mterface to all of the bus functional models m the hardware simulation system Device transaction class 44 is denved from base transaction class 40 Device transaction class 44 therefore inhents the four methods listed above from base transaction class 40 In this embodiment, the methods declared m base transaction class 40 are virtual methods That is, they are declared, but the implementation of each of the methods is not defined It is left to the device transaction classes (e g , device transaction class 44) to provide the program code which implements each of the methods Device transaction class 44 becomes associated with a smgle device object 42 through an object reference Device transaction class 44 controls the transactions which device 42 executes Because an object reference must always be satisfied, the use of an object reference to associate device 42 with device transaction class 44 forces the user to supply a device object when the device transaction class is instantiated By forcmg the user to supply the device object at instantiation, the possibility of changing the pomter or usmg a NULL pomter is elimmated and the compiler is allowed to perform static type checkmg These properties make the object reference inherently safer to use than a standard C pomter They add some complexity to the system, however, which will be discussed m more detail below Device transaction class 44 serves to hide the low-level details of the operation of device 42 from the test wnter and thereby simplifies the communications between the test subsystem and the bus functional models of the hardware simulation subsystem Device transaction class 44 also serves to maintain the state of device 42 between invocations of transactions mvolvmg the device The test wnter can set up high-level transaction information such as data, address, size and mode m the transaction class and then call a function such as setup_trans() to translate this information mto individual register operations at the device level Therefore, the test wnter does not need to know which specific register operations are mvolved m performing a particular function call Device transaction class 44 thus acts m a manner similar to that of a device dnver while also enablmg the compiler to perform static type checkmg In addition to enablmg static type checkmg and providmg a level of abstraction between device-level operations and the test wnter, device transaction class 44 allows the test wnter to define convemence methods associated with the device or device transaction The test wnter is free to define these test methods and any necessary instance vanables, both of which may be encapsulated mto the device transaction class Although the use of device classes and device transaction classes may considerably enhance the test wnting environment, there remain some problems associated with multiple-device transactions which are not resolved simply by the use of these classes For example, a test wnter may want to develop convenience routmes for transactions mvolvmg several devices These convenience routines may mampulate data, affect the control flow of the simulation (e g , advance the simulation time) or perform some other function The convenience routines must, of course, be defined so that they have access to the appropnate devices The test wnter might therefore create a system transaction class m which all of these convemence routines are defined This would provide a groupmg of common routines and would therefore potentially achieve the best re-use of program code, but might cause problems m terms of the desired use of object references Because the test wnter wants to have static type checkmg and wants to avoid NULL pomters, as explamed above, the system transaction classes should use object references The use of object references, however, requires that the associated device object be provided when the system transaction class and the object reference are instantiated If the system transaction class contams convenience routines relating to all the devices m the design under test, any test which uses this system transaction class (1 e any of the convemence routines m the class) must instantiate every device referenced m the class (I e all of the devices ) This would limit the performance of the system because tests would automatically reserve devices which would never be used for those tests The unnecessary reservation of devices would also make it very difficult for tests to share device objects Another approach which might be taken by a test wnter would be to define a configuration transaction class for every possible system configuration In other words, a separate configuration transaction class would be wntten for each combination of devices which might be tested Usmg this approach, only those devices which are mvolved m a transaction are instantiated for each test configuration There is no unnecessary reservation of devices which are not used The improved efficiency m the instantiation of device objects, however, is obtamed at the expense of the efficient re-use of program code Many of the configurations defined by the test wnter would probably need very similar [access and] convemence routines, but these routines could not be collected m a smgle transaction class Instead, the test wnter would have to reproduce the code for particular routines m each of the transaction classes which uses the respective routines Any code sharing could only be achieved by physically copymg the routines from one transaction class to another This would create more work for the test wnter and would result m a program which is very difficult to maintain because each of the copies of a routine must be mdividually updated. In one embodiment, the problems of the two approaches descnbed above are overcome by usmg a combination of the different approaches. As descnbed m the first approach, a system transaction class 46 is created as a subclass of base transaction class 40 System transaction class 46 is a collector of all the convemence routines which may be needed by the test wnter. Because system transaction class 46 uses pomters to device objects mstead of object references, it is not necessary to instantiate each device m the system for every test. The instantiation of device objects is left to the configuration transaction classes. As shown m Fig. 3, the system transaction class 46 is sub-classed to create one or more configuration transaction classes 47, 48. The configuration transaction classes contam object references to each of the device objects which are mvolved m a transaction of the respective configuration. The configuration transaction class is used to create all of the required device transaction classes. The device object reference of the system transaction class is used to set the device transaction class pomters inhented from the system transaction class, so the system transaction class' use of pomters is acceptable from a type checkmg perspective. Further, the configuration transaction class inhents all of the convenience routines from the system transaction class, so the programmer does not have to rewrite or copy the routines mto each of the configuration transaction classes. This reduces the workload of the programmer and greatly mcreases the maintainability of the program code. One embodiment of the mvention uses CVI as the interface subsystem. CVI uses an mterrupt dnven model for the test environment. An mterrupt dnven model allows the test to retam very tight control over execution m the simulation subsystem. The use of an mterrupt dπven model may, however, create difficulties for a test wnter because he or she must be prepared to receive any type of mterrupt at any pomt m the simulation — the test subsystem cannot only handle those types of interrupts which are of mterest to the test wnter. The use of the class hierarchy shown in Fig. 3 simplifies the program code required to implement an mterrupt dnven model and reduces the burden on the test wnter by enablmg a state dnven style of test wnting In a state dnven style of test wnting, the control flow of the tests are tied to a state sequencer (i.e., finite state machme, or FSM) m a manner resemblmg a hardware design style The state sequencer may be defined m the base transaction class or m the system transaction class. The purpose of the state sequencer is to handle signals directed to the device based on the current state of the sequencer This generally improves the readability of threads in the test subsystem because state information which is usually embedded m the program code is removed. This state information is moved mto the device transaction class and stored m a format suitable for the state sequencer The program code of the test subsystem can therefore be wntten as a simple stimulus generator. This greatly reduces the complexity of the code. The state dnven style of test wnting may also simplify the wnting of convemence routines Usmg other styles of test wnting, it may be necessary to include code m convemence methods which returns control to the simulation subsystem. In a state dnven style, routines can return control to the simulation subsystem at a high level, allowing parallel operation without the need for multi-threading. This is a great benefit m a random testing environment. In a system m which there is only one pendmg transaction and m which the transaction mvolves only two bus functional models there will be no random interaction of signals within the system. Thus, when a system is tested with only one transaction at a time, the testing cannot account for such random interactions and the possible effects of these interactions. Using a state driven style of testing, several transactions can be pending at once, allowing the random interaction of the transactions in much the same way as they would occur in the actual operation of the device under test. Because the test transactions are written as objects in a state driven test program, they may easily be performed in parallel to obtain the random interaction which cannot be obtained by the individual transactions. While the present invention has been described with reference to particular embodiments, it will be understood that the embodiments are illustrative and that the invention scope is not limited to these embodiments. Many variations, modifications, additions and improvements to the embodiments described are possible. These variations, modifications, additions and improvements may fall within the scope of the invention as detailed within the following claims.

Claims: WHAT IS CLAIMED IS: 1. A framework for a test subsystem of a circuit design venfication system, the cncuit design venfication system mcludmg a cncuit simulation system which models a plurality of functional umts m the circuit design, wherein the framework compnses- a device class, one or more device transaction classes, each of which contams a reference to a conespondmg device instantiated from said device class; a system transaction class which contams one or more device transaction pomters; and one or more configuration transaction classes which are denved from said system transaction class and rnhent one or more methods from said system transaction class, each of said configuration transaction classes contammg one or more object references to corresponding ones of said devices; wherem said test subsystem is configured to operate on said devices through said device transaction pomters 2. The framework of claim 1 further compnsmg a base transaction class from which said device transaction class and said system transaction class are denved. 3. The framework of claim 2 wherem said base transaction class defines one or more methods for initializing objects instantiated from said configuration transaction classes 4. The framework of claim 1 wherem said system transaction class contams a device transaction class pomter for each device m system. 5 The framework of claim 4 wherem said test system is wntten m a high-level language 6. The framework of claim 5 wherem said high-level language is selected from the group consisting of C and C++ 7 The framework of claim 1 wherem said system transaction class contams one or more convenience routines. 8. The framework of claim 1 wherem said system transaction class contams a finite state machine 9. The framework of claim 1 wherem said configuration transaction classes create ones of said device transaction classes corresponding to said referenced devices 10. A circuit design venfication system configured to venfy the operation of a design under test, the circuit design venfication system compnsing. a simulation subsystem, wherem said simulation subsystem mcludes one or more functional models, each of said functional models configured to simulate operation of a corresponding device within said design under test; and a test subsystem, wherem said test subsystem mcludes a system transaction class containing one or more convemence routines and one or more device transaction pomters, a configuration transaction class denved from said system transaction class and containing one or more object references, one or more device objects corresponding to said one or more object references, and one or more device transaction classes, each of said device transaction classes corresponding to one of said one or more device objects and contammg an object reference to said one of said one or more device objects 11 The circuit design venfication system of claim 10 further compπsmg a base transaction class from which said system transaction class and said device transaction classes are denved. 12. The circuit design venfication system of claim 10 further compnsmg an mterface subsystem. 13. The circuit design venfication system of claim 12 wherem said simulation subsystem is wntten m HDL 14 The circuit design venfication system of claim 13 wherem said test subsystem is wntten in a high-level language 15. The circuit design venfication system of claim 14 wherem said high-level language is selected from the group consisting of C and C++ 16. The circuit design venfication system of claim 14 wherem said mterface subsystem compnses CVI 17. A method for testing a circuit design m a venfication system, the venfication system havmg a test system, a simulation system and an mterface system which couples the test and simulation systems, wherem the method compnses: defining a system transaction which contams one or more device transaction pomters and contams one or more convemence routines, wherem said system transaction conesponds to a set of potential simulation system transactions, instantiating said one or more devices, defining one or more configuration transactions, wherem each of said configuration transactions is denved from said system transaction and contams references to one or more of said devices; creating one or more device transactions corresponding to said one or more devices, each of said device transactions havmg a reference to a corresponding one of said one or more devices; and executing a test which performs one or more of said configuration transactions 18. The method of claim 17 wherem said configuration transactions create said one or more device transactions corresponding to said one or more devices. 19. The method of claim 18 further compnsmg constructing one or more device classes. 20. The method of claim 19 further compnsmg constructing one or more device transaction classes, each of which contams a reference to a corresponding device. 21. The method of claim 17 wherem executing said test compnses performing a plurality of said configuration transactions and wherem said test is configured to cause mteraction of said configuration transactions. 22. A computer-readable medium contammg a test subsystem of a circuit design venfication system, wherem the circuit design venfication system mcludes a simulation subsystem for modelmg the operation of a test circuit and an mterface subsystem for translating test signals from the test subsystem mto sunulation signals for the simulation subsystem, wherem the test subsystem on the computer-readable medium compnses: a device class, one or more device transaction classes, each of which contams a reference to a corresponding device instantiated from said device class; a system transaction class which contams one or more device transaction pomters; and one or more configuration transaction classes which are denved from said system transaction class and lnhent one or more methods from said system transaction class, each of said configuration transaction classes contammg one or more object references to corresponding ones of said devices; wherem said test subsystem is configured to operate on said devices through said device transaction pomters

Inventors: DEARTH GLENN A, MEETH SCOTT R, PABISZ JOHN P, PARIKH TUSHAR A, PLOUFFE GEORGE R JR, WHITTEMORE PAUL M, DEARTH, GLENN, A., MEETH, SCOTT, R., PABISZ, JOHN, P., PARIKH, TUSHAR, A., PLOUFFE, GEORGE, R., JR., WHITTEMORE, PAUL, M.
Applicants: SUN MICROSYSTEMS INC, SUN MICROSYSTEMS, INC.
Application year: 2000
Main classification: G06F17
IPC codes: G06F11, G06F17