VOLTAGE REGULATOR PROVIDED WITH A CURRENT LIMITER

Abstract: A voltage regulator for converting an input voltage (1Vi) into an output voltage (2V0). The input voltage may be burdened with a ripple. The output voltage (2VO) supplied by the voltage regulator is virtually free from ripple. The voltage regulator comprises an input terminal (1Vi) for receiving the input voltage (1Vi), an output terminal for supplying the output voltage (2V0) in response to the input voltage (1Vi), and current limiting means for limiting the maximum absolute value of an output current (3IO taken from the output terminal (2). The current limiting means comprise a field effect transistor (4TCL). The voltage regulator further comprises a first current mirror (5CM1) comprising transistors (6T11, T12), a second current mirror (7CM2) comprising transistors (8T13, T14), and a third current mirror comprising transistors (9T15, T16). In a typical operation, the field effect transistor (4TCL) is in the linear region and thus behaves like a resistance. With an increasing output current (3IO), the current through the field effect transistor (4TCL) also increases, and the voltage between the drain and the source of the field effect transistor (4TCL) increases. When the voltage between the drain and the source of the field effect transistor (4TCL) has exceeded a certain level, the field effect transistor (4TCL) enters its saturation region and accordingly behaves like a constant-current source. As a consequence the output current (3IO) can no longer rise.

Description: Voltage regulator provided with a current limiter The invention relates to a voltage regulator for converting an input voltage, which may be affected by a ripple, into an output voltage which is substantially not affected by a ripple, comprising an input terminal for receiving the input voltage, an output terminal for supplying the output voltage in response to the input voltage, and current limiting means for limiting the maximum absolute value of an output current supplied from the output terminal. Such a voltage regulator is known from Japanese patent abstract JP 2-136029 A. The known voltage regulator comprises a current mirror with an input and an output and, a bipolar transistor whose base is connected to the current mirror and whose emitter forms the output terminal of the voltage regulator. The known voltage regulator further comprises a voltage divider which consists of two resistors connected in series. The voltage divider is connected between the emitter of the bipolar transistor and a supply voltage terminal. The known voltage regulator further comprises a comparator, a first current source which supplies a comparatively small current, and a second current source which supplies a comparatively large current. A switch is connected in series with the second current source. The comparator is connected by a first input to the common junction point of the two resistors connected in series, and is connected by a second input to a reference voltage source, and is connected by an output to a control electrode of the switch. In a normal operational state of the voltage regulator, the switch is in the conducting state. The current supplied to the input of the current mirror in that case is determined by the sum of the currents supplied by the first and the second current source. This current is delivered from the output of the current mirror to the base of the bipolar transistor. The bipolar transistor amplifies this current and delivers the amplified current to the voltage divider. As the current through the voltage divider rises, the voltage at the first input of the comparator will become greater than the voltage at the second input of the comparator at a given moment. As a result of this, the voltage at the output of the comparator changes, such that the switch switches from the conducting state to a nonconducting state. In this state, the current supplied to the input of the current mirror is dependent on the first current source only. As a result, the current supplied from the output of the current mirror is reduced, so that the current supplied from the emitter of the bipolar transistor to the voltage divider is limited. A disadvantage of the known voltage regulator is that the current limitation is achieved in a comparatively complicated manner. It is an object of the invention to provide a voltage regulator which reduces the above mentioned disadvantage. According to the invention, the voltage regulator mentioned in the opening paragraph is for this purpose characterized in that the current limiting means comprise a current limiting transistor with a main current path, and in that the current limiting means are designed such that, if the voltage across the main current path is higher than a given threshold voltage of the current limiting transistor, at which the current limiting transistor acts as a current source, the maximum absolute value of the output current is limited. The invention is based on the recognition that the transistor is in its linear operational range as long as a voltage across the main current path of a transistor lies below a certain limit, so that the transistor behaves as a resistor, and on the recognition that, as the voltage across the main current path rises, there comes a moment when the voltage across the main current path exceeds said limit, so that the transistor starts behaving as a current source. The transistor thus acts as a current limiting transistor. The current limiting transistor may be constructed, for example, with a field effect transistor. When the drain-source voltage of the field effect transistor is smaller than the difference between the gate-source voltage and the so-called threshold voltage V t , the field effect transistor is in its linear operational range. When the drain-source voltage of the field effect transistor is higher than the difference between the gate-source voltage and the so-called threshold voltage V t , the field effect transistor is in its saturation range, wherein the field effect transistor acts as a constant- current source. The current limiting transistor may alternatively be constructed with a bipolar transistor. When the collector-emitter voltage of the bipolar transistor is below the so-called saturation voltage, the transistor is in saturation and behaves more or less as a resistor. When the collector-emitter voltage of the bipolar transistor is greater than the so-called saturation voltage, the bipolar transistor is not in the saturated state. The bipolar transistor then acts as a constant-current source. Further advantageous embodiments of the invention are defined in claims 2 and 3. The invention will be explained in more detail with reference to the attached drawing, in which: Fig. 1 is a circuit diagram of a first embodiment of a voltage regulator according to the invention; and Fig. 2 is a circuit diagram of a second embodiment of a voltage regulator according to the invention. Corresponding components or elements have been given the same reference symbols in these Figures. Fig. 1 shows a circuit diagram of a first embodiment of a voltage regulator according to the invention. The voltage regulator is supplied from a supply voltage source S V which is connected between a supply voltage terminal Vss and a further supply voltage terminal V DD - The voltage regulator has an input terminal 1 for receiving an input voltage V; and an output terminal 2 for supplying an output voltage Vo in response to the input voltage Vj. A load Z L is connected between the output terminal 2 and the supply voltage terminal Vss- An output current Io supplied from the output terminal 2 flows through the load Z L . The voltage regulator further comprises a first current mirror CM] with field effect transistors T π and T 12 , a second current mirror CM 2 with field effect transistors T 13 and T 1 , field effect transistors Tγ to T 8 , current limiting field effect transistor T CL , tail resistor R TL , and a voltage divider which is implemented with a series arrangement of a resistor Ri and a resistor R 2 , which series arrangement is connected between the output terminal 2 and the supply voltage terminal Vss- The gates of transistors Tπ and T 1 and the drain of transistor Tπ are interconnected and form the input of the first current mirror CMt. The drain of transistor T 12 forms the output of the first current mirror CM] and is connected to the output terminal 2. The sources of transistors Tπ and T 12 are interconnected and form a reference connection point of the first current mirror CMi and are connected to the input terminal 1. The gates of transistors T 13 and Tj and the drain of transistor Tι 3 are interconnected and form the input of the second current mirror CM . The drain of transistor T 14 forms the output of the second current mirror CM 2 and is connected to the input of the first current mirror CMi. The sources of transistors Tj 3 and T 14 are interconnected and form a reference connection point of the second current mirror CM 2 . The sources of transistors T , T 7 , T 8 and of current limiting transistor T C are connected to the supply voltage terminal Vss- The drain of transistor T 6 and the gates of transistors T 6 , T 7 , T 8 and of the current limiting transistor T C are connected to a current reference terminal I B - The drain of current limiting transistor T CL is connected to the reference connection point of the second current mirror CM 2 . The sources of transistors T 3 , T 4 , and T 5 are connected to the further supply voltage terminal V DD - The drain of transistor T 3 and the gates of transistors T 3 and T 4 are connected to the drain of transistor Ti. The gate of transistor Ti is connected to a voltage reference terminal V RF . The source of transistor Ti is connected to the drain of transistor T 7 . The drain of transistor T 4 and the gate of transistor T 5 are connected to the drain of transistor T 2 . The source of transistor T 2 is connected to the drain of transistor T 8 . The tail resistor R TL is connected between the source of transistor T] and the source of transistor T 2 . The gate of transistor T 2 is connected to the common junction point of the resistors R] and R 2 . The circuit operates as follows. The voltage across the resistor R 2 is controlled so as to be equal to the reference voltage which is offered between the voltage reference terminal V RF and the supply voltage terminal Vss- As a result of this, the output voltage V 0 between the output terminal 2 and the supply voltage terminal Vss is equal to said reference voltage multiplied by the sum of the values of the resistors R] and R 2 and divided by the value of resistor R 2 . Since the reference voltage is free from ripple, the output voltage Vo is also free from ripple. The ripple which may be present on the input voltage Vi accordingly does not extend itself to the output voltage V 0 - For an optimum operation, however, the input voltage Vi should always be greater than the output voltage Vo- As long as the voltage regulator is in a normal operating condition, i.e. no current limitation takes place, the output current Io will rise as the impedance of the load Z L decreases. In this normal operating condition, the current limiting transistor T CL is in its linear operating range. The current limiting transistor T CL thus acts as a resistor. As the output current Io rises, there will come a moment when the voltage U between the drain and the source of the current limiting transistor T CL becomes so great that the current limiting transistor T CL changes from its linear operating range to its so-called saturation region. The current limiting transistor T CL acts as a constant current source as a result of this. The current which is supplied by transistor T 5 cannot be controlled upwards any further because in that case the potential at the drain of transistor T 5 will rise quickly, which will render the source-drain voltage of transistor T 5 so low that the transistor T 5 changes from the saturation region to the linear operating region. Since the current to the input of the second current mirror CM 2 is limited thereby, the output current Io is also limited via the second current mirror CM 2 and via the first current mirror CMi. The tail resistor R TL serves to improve the stability of the voltage regulator, so that there is no risk of undesirable oscillations occurring. Fig. 2 shows a circuit diagram of a second embodiment of a voltage regulator according to the invention. An advantage of this second embodiment over the first embodiment of Fig. 1 is that the reference voltage between the voltage reference terminal V RF and the supply voltage terminal Vss may be chosen to be lower. For this purpose, all transistors having a p-conductivity type are replaced by transistors having an n-conductivity type, except for transistors Tπ and T 12 , and all transistors having an n-conductivity type are replaced by transistors having a p-conductivity type. A third current mirror CM 3 is added, composed with field effect transistors T 15 and T 16 . The drain of transistor T 15 and the gates of transistors T 15 and T 16 are interconnected and form the input of the third current mirror CM 3) which is connected to the output of the second current mirror CM 2 . The drain of transistor T 16 forms the output of the third current mirror CM 3 and is connected to the input of the first current mirror CM]. The sources of transistors T 15 and T 16 are interconnected and form a reference connection terminal of the third current mirror CM 3 , which is connected to the supply voltage terminal Vss of the voltage regulator. The operation of the circuit of Fig. 2 is equivalent to the operation of the circuit of Fig. 1. A further advantage of a voltage regulator according to the invention is that the output voltage Vo can be substantially equal to the input voltage V,. The differential pair Υ \ , T 2 may be replaced by some other type of differential stage, for example a cascoded differential stage. The voltage regulator may either be constructed from discrete components or be implemented in an integrated circuit. The voltage regulator may be constructed with field effect transistors as well as with bipolar transistors. A combination of field effect transistors and bipolar transistors may also be used. It is also possible to replace all p-type transistors with n-type transistors, provided all n-type transistors are replaced with p-type transistors at the same time.

Claims: CLAIMS 1. A voltage regulator for converting an input voltage (Vj), which may be affected by a ripple, into an output voltage (Vo) which is substantially not affected by a ripple, comprising an input terminal (1) for receiving the input voltage(Vj), an output terminal (2) for supplying the output voltage (Vo) in response to the input voltage (Vj), and current limiting means for limiting the maximum absolute value of an output current (Io) supplied from the output terminal (2), characterized in that the current limiting means comprise a current limiting transistor (T CL ) with a main current path, and in that the current limiting means are designed such that, if the voltage (U) across the main current path is higher than a given threshold voltage of the current limiting transistor(Tc L ), at which the current limiting transistor (T CL ) acts as a current source, the maximum absolute value of the output current (Io) is limited. 2. A voltage regulator as claimed in claim 1, characterized in that the current limiting means further comprise a first current mirror (CMO with an input, an output coupled to the output terminal (2) and a reference connection point which is coupled to the input terminal (1); and a second current mirror (CM 2 ) with an input, an output coupled to the input of the first current mirror (CMO, and a reference connection point, and in that the main current path of the current limiting transistor (T CL ) is connected in series with the reference connection point of the second current mirror (CM 2 ) and a supply voltage terminal (Vss) of the voltage regulator. 3. A voltage regulator as claimed in claim 1, characterized in that the current limiting means further comprise a first current mirror (CMO with an input, an output coupled to the output terminal (2) and a reference connection point which is coupled to the input terminal (1); a second current mirror (CM ) with an input, an output, and a reference connection point; and a third current mirror (CM 3 ) with an input coupled to the output of the second current mirror (CM 2 ), an output coupled to the input of the first current mirror (CMO, and a reference connection point which is coupled to the supply voltage terminal (Vss) of the voltage regulator; and in that the current limiting transistor (T CL ) is connected in series with the reference connection point of the second current mirror (CM 2 ) and a further supply voltage terminal (V DD ) of the voltage regulator.

Inventors: ANTHEUNIS ROLAND A B, ANTHEUNIS, ROLAND, A., B.
Applicants: KONINKL PHILIPS ELECTRONICS NV, KONINKLIJKE PHILIPS ELECTRONICS N.V.
Application year: 2000
Main classification: G05F3
IPC codes: G05F3, H02H9