Demodulating receiver with simple structure

Abstract: A receiver includes inversely spreading circuit (12), a RAKE synthesizing circuit (13), a noise measuring circuit (15), a weighting circuit (16) and a decoder (14). The inversely spreading circuit inversely spreads a reception signal for every path using a spreading code to produce path data signals for paths. The RAKE synthesizing circuit synthesizes the path data signals to output a RAKE synthesis signal while carrying out a weighting operation for every path such that the RAKE synthesis signal has a maximum S/N ratio. The noise measuring circuit measures a noise level of each of the path data signals, and calculates a total noise amount for the paths from the measured noise levels. The weighting circuit carries out a weighting operation of the RAKE synthesis signal based on the total noise amount to produce a weighted signal such that a time change of distortion in the RAKE synthesis signal is cancelled. The decoder decodes the weighted signal to produce an information sequence.

Description: Background of the Invention 1. Field of the Invention The present invention relates to a demodulating method and a demodulating circuit in a radio receiver according to the preamble of claims 1 and 10. More particularly, the present invention relates to a method and a circuit for demodulating a reception signal in which selective fading occurs on a transmission path. 2. Description of the Related art In code division multiple access (CDMA) systems, information bit sequences are subjected to primary modulation on a transmitting side and then are multiplied by different spreading codes for respective channels to be modulated and transmitted using an identical frequency band. In a demodulating circuit on the receiving side, a reception signal is multiplied by a spreading code identical with the spreading code used for a desired one of the plurality of channels on the transmitting side. Thus, the information bit sequence for the desired channel is taken out and is demodulated. Asthe transmission frequency band of the CDMA system is wide, the CDMA system is strong in the selective fading on multi-path, so that information for a lot of channels can be transmitted in the identical frequency band. Also, there is secrecy that it is not possible to demodulate the information if the same spreading code as on the transmitting side is not used. Therefore, the CDMA system is suitable for a multiple access system for a mobile communication system. Fig. 1 is a block diagram of an example of a conventional demodulating circuit of a receiver in the above-mentioned CDMA system. In Fig. 1, a reception signal as a digital signal with a predetermined frame format is inputted to a path searching circuit 11 and an inversely spreading circuit 12. For example, when the CDMA system is applied to a mobile communication system, this inputted reception signal is the signal having been radio-transmitted from the mobile terminal and having been received by a base station. The reception signal is a modulated wave obtained by carrying out phase shift keying (PSK) modulation to a carrier. Moreover, the reception signal is a signal in which one symbol is spread over a plurality of chips with the spreading code. Each of the slots of this reception signal is a unique word composed of real part (I signal) of data and an imaginary part (Q signal) of a fixed pattern, as shown in Figs. 2A and 2B. Each of the symbols of the I signal and the Q signal is spread over the plurality of chips with the spreading code. The format shown in Figs. 2A and 2B is defined in 3GPP (3rd Generation Partnership Project). Supposing that the inversely spreading circuit 12 of Fig. 1 has M (M is an integer equal to or more than 2) correlating units, the path searching circuit 11 of Fig. 1 produces a delay profile from the above-mentioned inputted reception signal, and allocates M paths of the detected and separated paths to the inversely spreading circuits 12. The inversely spreading circuit 12 inversely spreads the reception signal for each path using a delay quantity obtained from the delay profile calculated by the path searching circuit 11. Through the inverse spreading, the data in each path is changed from the chip unit base to the symbol unit base. The data outputted from the inversely spreading circuit 12 is supplied to the RAKE synthesizing circuit 13. The estimation of the channel and phase compensation are carried out here for every data in each path. After that, a weighting operation is carried out for a maximum S/N (signal-to-noise) ratio in the RAKE synthesizing circuit and then data for the respective paths are summed. The signal taken out from the RAKE synthesizing circuit 13 is supplied to a decoder 14 and is decoded through metric calculation. By the way, when the above-mentioned CDMA system is applied to the mobile communication system, an error correcting code which has a high coding gain is introduced. In this case, it is known that the coding gain is maximum in the decoder of the demodulating circuit, when the distortion of the reception signal cancels a time change or fluctuation (for example, "Digital Communication Receivers", (pp. 690 - 697) by H. Meyr). However, in the conventional demodulating circuit shown in Fig. 1, the weighting operation is carried out in the RAKE synthesizing circuit 13 such that an S/N (signal-to-noise) ratio after synthesis is maximized. In this case, because no weighting operation to a synthetic output signal is carried out, the S/N ratio of the input signal of the decoder 14 is not large enough. Therefore, the value of the metric calculation has sometimes received a time fluctuation at the time of the metric calculation by the decoder 14. Therefore, conventionally, a demodulating circuit is proposed in Japanese Laid Open Patent Application (JP-A-Heisei 10-173629), in which the path timing which should be synthesized is stably extracted, a RAKE synthesis is reliably realized and demodulation with a low error rate can be carried out, when RAKE synthesis is carried out. In the conventional demodulating circuit, an autocorrelation value of the spreading code is calculated. Numerical values obtained by synthesizing a calculation result and a measured reception quality measurement result from the RAKE synthesis signal are set as upper and lower thresholds for an error range of the autocorrelation value. Also, the cross-correlation value of the spreading code and the reception signal allocated for a mobile station itself is calculated. The cross-correlation value and the above-mentioned upper and lower thresholds are compared by the comparing means. If the cross-correlation value is between the upper and lower thresholds, the cross-correlation value is regarded as an invalid correlation value and a corresponding weighting coefficient of a weighting section is set to "0". The weighting section weights the signal obtained by inversely spreading the reception signal using the spreading code. If the cross-correlation value is out of the range between the upper and lower thresholds, the cross-correlation value is regarded as an effective correlation value and the above-mentioned weighting coefficient is set to a predetermined value. After that, the output signals of the weighting section are added, synthesized and outputted to the decoder as the RAKE synthesis signal. In the conventional demodulating circuit, a wrong timing is never extracted based on the autocorrelation of the spreading code. When the effective reception signal exists in the place of the wrong timing extracted based on the autocorrelation, a threshold is set based on the autocorrelation value, because the cross-correlation value of the reception signal is different from the autocorrelation value of the spreading code. As a result, influence of the autocorrelation value is excluded, and the RAKE synthesis can be carried out, the error rate of the decoder can be suppressed low. However, the above-mentioned conventional demodulating circuit is complex in the circuit structure, because various circuits are necessary such as a section for calculating the autocorrelation value of the spreading code, a section for calculating the quality (SIR) of the reception signal from the signal obtained through RAKE synthesis, and a comparing section for comparing the cross-correlation value and the autocorrelation value of the reception signal. In conjunction with the above description, a spectrum spreading communication receiver is disclosed in Japanese Laid Open Patent Application (JP-A-Heisei 8-237171). In this reference, a plurality of sets of antenna, correlator and Rake synthesizing circuit are provided. The levels of the output signals of the RAKE synthesizing circuits are compared so as to select one of the output signals having the highest level and the selected output signal is outputted to a demodulating circuit. Also, a CDMA demodulating circuit is disclosed in Japanese Laid Open Patent Application (JP-A-Heisei 8-335899). In this reference, the output of a phase error compensating section (107) is carried out in a pilot symbol period. It is held for a few symbol periods by a timing adjust function section (110). By using the held phase compensation value, an error generating circuit (109) generates an error vector for every information symbol from signal vectors before and after identification determination. The error vector is sequentially supplied to a tap coefficient control section (111) in the symbol period. The tap coefficient control section (111) updates the tap coefficients of an orthogonal filter in the symbol period. Thus, the tap coefficients are converged in a short time. EP 0 893 888 A discloses a receiver according to the preamble of claim 1. US 5 809 020; D.L.Noneaker in Proceedings of the Military Communications Conference 1998 (Milcom 98) in Boston, MA, U.S.A. from 18-21 Oct. 1998, New York, NY, U.S.A., p. 842-846; and EP 0 749 215 A disclose other related receivers. Summary of the Invention Therefore, the object of the present invention is to provide a receiver for a demodulating method and circuit, in which the decode gain is maximized and a RAKE synthesis signal can be demodulated while the error rate is suppressed to low. Another object of the present invention is to provide a receiver for a demodulating method and circuit, in which it is possible to improve the performance of a receiver which receives a reception signal of the CDMA system with a simple structure. The invention achieves these objects with the features of claims 1 and 10. Brief Description of the Drawings Fig. 1 is a block diagram showing the structure of an example of a conventional receiver; Fig. 2A and 2B are diagrams showing the format of data and a unique word; Fig. 3 is a block diagram showing the structure of a receiver according to an embodiment of the present invention; Fig. 4 is a block diagram showing the structure of an inversely spreading circuit in the receiver shown in Fig. 3; Fig. 5 is a block diagram showing the structure of a RAKE synthesizing circuit in the receiver shown in Fig. 3; Fig. 6 is a block diagram showing the structure of a channel estimator in the receiver shown in Fig. 5; Fig. 7 is a block diagram showing the structure of a noise measuring circuit in the receiver shown in Fig. 3; Fig. 8 is a block diagram showing the structure of a noise measuring unit in the receiver shown in Fig.3 ; and Fig. 9 is a block diagram showing the structure of a weighting circuit in the receiver shown in Fig. 3. Description of the Preferred Embodiments Hereinafter, a receiver of the present invention will be described with reference to the attached drawings. Fig. 3 is a block diagram showing the structure of a demodulating circuit of the receiver according to an embodiment of the present invention. Referring to Fig. 3, the same components as those in Fig. 1 are allocated with the same reference numerals, respectively. The embodiment shows a demodulating circuit of a base station, for example. The demodulating circuit communicates with mobile terminals in a mobile communication system in which the mobile terminal communicates with a counter terminal through the base station and a network. Referring to Fig. 3, a reception signal is supplied to a path searching circuit 11 and an inversely spreading circuit 12. The reception signal includes a unique word composed of a real part (I signal) of data and an imaginary part (Q signal) of a known fixed pattern, as shown in Figs. 2A and 2B. Each of symbols of the I signal and the Q signal is spread over a plurality of chips with a spreading code. That is, the reception signal is a PSK modulation wave in which a frequency spectrum is spread with the spreading code. The path searching circuit 11 is a circuit for the synchnization establishment. As the path searching circuit, there is conventionally known a circuit using a sliding correlating unit and a circuit using a matched filter. In this example, either of them is usable. For example, in the circuit using the sliding correlating unit, a spreading code (a PN series) with a suitable phase and a reception signal are multiplied on a chip unit basis. The multiplication result is integrated over one period of the spreading code. If the integration value is equal to or larger than a predetermined threshold, the point is selected as a synchronization point. If the integration value is lower than the threshold, the phase of the spreading code is shifted a little bit and the phase-shifted spreading code is multiplied by the reception signal again. The multiplication result is integrated. When the multiplication with the reception signal and the integration are carried out for one period of the spreading code in this way, a peak of the correlation can be detected somewhere when the transmission signal has been spread with the same spreading code as that on the receiving side and then has been received by the receiving side. Then, the phase of a spreading code outputted from a spreading code generator is adjusted to the position of the peak. In the circuit using the matched filter, a reception signal is supplied to a shift register. A signal is outputted from a bit output terminal of the shift register corresponding to a positive value of the spreading code and is added by an first adder. A signal is outputted from the bit output terminal corresponding to a negative value of the spreading code and then is added by the second adder. In the circuit, those addition outputs are synthesized and the peak determination of the correlation value is carried out. A transmission signal is reflected by a building and so on or is subjected to diffraction and scattering. Then, the transmission signal is received by a receiver via some routes (paths). Therefore, the above-mentioned reception signal is a signal in which signals with different delay times are superimposed. Therefore, the path searching circuit 11 carries out the above-mentioned correlation peak determination to each of M (M is an integer equal to or larger than 2) paths with different delay times. In this way, the path searching circuit 11 carries out a correlation value peak determination to each of the M paths and supplies a signal indicative of the detected timings to the inversely spreading circuit 12. Fig. 4 shows a block diagram of an example of the inversely spreading circuit 12. The inversely spreading circuit 12 shown in Fig. 3 is composed of M correlating units/circuits 181 to 18M. The correlation between a spreading code pn common to them and the reception signal is calculated at the timing of each path from the path searching circuit 11. The calculation of the correlation is called inverse spreading. The signals from of the M correlating units 181 to 18M are outputted as data in the respective M paths. The data on the respective paths are converted from the data of the chip unit basis into the data of the symbol unit basis through the inverse spreading. It should be noted that each of the M correlating units 181 to 18M has a correlator for the I signal of the reception_signal and a correlator for the Q signal. A first spreading code is supplied in common to the M correlators for the I signal. A second spreading code is supplied in common to the M correlators for the Q signal. Also, the M correlating units 181 to 18M as M sets of two correlators are provided for the number of users receiving service from the base station. However, as shown in Fig. 4, the I signal and the Q signal will be collectively described for simple description, unless being especially noted in this specification. The data signals outputted from the inversely spreading circuit 12 are supplied to the RAKE synthesizing circuit 13 with the structure shown in Fig. 5 and the noise measuring circuit 15 with the structure shown in Fig. 7, respectively. In this embodiment, the noise measuring circuit 15 is provided and the weighting circuit 16 is provided between the RAKE synthesizing circuit 13 and the decoder 14. Fig. 5 shows a block diagram of an example of the RAKE synthesizing circuit 13. In Fig. 5, the data signals for the paths outputted from the M correlating units 181 to 18M of the inversely spreading circuit 12 are supplied to channel estimators 211 to 21M provided for the respective paths. The channel estimators 211 to 21M detect distortion components of the respective paths. The channel estimators 211 to 21M have the same structure. For example, as shown in the block diagram of Fig. 6, the channel estimator is composed of an inversely modulating unit 211 and a phase estimator 212. The inversely modulating unit 211 multiplies an input signal by the unique word to carry out inverse modulation and supplies an inverse modulation resultant signal to the phase estimator 212. The phase estimator 212 estimates the phase of each symbol of inverse modulation signal and outputs as a distortion component. Returning to Fig. 5 again, the above-mentioned distortion component is multiplied by the data signal outputted from a corresponding one of the correlating units 181 to 18M. The data signal is delayed by a corresponding one of delay circuits 201 to 20M obtaininga delay time for the processing time of a corresponding one of the channel estimators 211 to 21M. The delay circuits 201 to 20M are used to adjust timings of multiplication in the multipliers 221 to 22M for the phase compensation. The respective output signals of the multipliers 221 to 22M are separately supplied to multipliers 231 to 23M. Also, weighting coefficients W1 to WM are supplied to the multipliers 231 to 23M. The multipliers 231 to 23M multiplies the output signals from the multipliers 221 to 22M by the weighting coefficients W1 to WM, respectively, such that a S/N ratio after synthesis is maximized. The output data of the respective paths outputted from the multipliers 231 to 23M are supplied to an adder 24 and added or synthesized there, and the addition result is outputted as a RAKE synthesis signal RSS. The structure of the RAKE synthesizing circuit 13 itself of Fig. 5 is conventionally known. Fig. 7 is a block diagram showing an example of the noise measuring circuit 15. In Fig. 7, the data signals of the respective paths outputted from the M correlating units 181 to 18M of the inversely spreading circuit 12 are supplied to the noise measuring units 311 to 31M which are provided for the respective paths. Noise is measured and detected here for every path, and each measurement result is supplied to the adder 32 and an addition or synthesization is carried out there. The addition result is supplied to the weighting circuit 16 of Fig. 3 as a noise measurement signal Fig. 8 shows a block system of an example of the optional one in the noise measuring units 311 to 31M. As shown in Fig. 8, the noise measuring unit 31k in the k-th finger or path is supplied with the output signal from the inversely spreading circuit 12. The noise measuring unit is composed of a channel estimator 34, a dividing unit 35, square circuits 36 and 38, a subtracting unit 37, a multiplier 39 and a an averaging circuit 40. _The channel estimator 34 carries out estimation of a channel and outputs a distortion component for fading. The dividing unit 35 divides the output signal from the inversely spreading circuit 12 by the output signal from the channel estimator 34. The square circuit 36 calculates the square of an absolute value of the value of the output signal from dividing unit 35. The square circuit 38 calculates the square of the absolute value of the value of the output signal from channel estimator 34. The subtracting unit 37 subtracts "1" from the output signal of the square circuit 36. The multiplier 39 multiplies the output from the subtracting unit 37 by the output from the square circuit 38. The averaging circuit 40 calculates an average of the signal taken out from the multiplier 39. The signal outputted from the averaging circuit 40 is supplied to the adder 32 of Fig. 7 and is synthesized there. The weighting circuit 16 of Fig. 3 comprises a multiplier 45 as shown in Fig. 9. The weighting circuit 16 multiplies the RAKE synthesis signal from the RAKE synthesizing circuit 13 by the noise measurement signal from the noise measuring circuit 15 as the weighting coefficient. The weighting circuit 16 outputs the signal of the multiplication result to the decoder 14. The RAKE synthesis signal weighted by the weighting circuit 16 is a demodulation signal in which noise is removed or reduced, as described later. The decoder 14 carries out the decoding operation to the demodulation signal outputted from the weighting circuit 16 and outputs an information signal which is subjected to error correction. For example, the decoder 14 may be a known Viterbi decoder. The decoder 14 calculates a branch metric from the input signal, and sums the branch metric for every clock to calculate a path metric. The decoder 14 selects the data sequence having the highest reliability from a path memory such that the path metric is the smallest. The path memory stores a plurality of candidate sequences and outputs as the decode data the candidate sequence selected in accordance with the path metric value. Next, the operation of the main section of this embodiment will be further described detail. The RAKE synthesizing circuit 13 is associated with the M paths as shown in Fig. 5. It is supposed that the input signal to the RAKE synthesizing circuit 13 in the k-th finger (path) of the M paths is: c k · a(t) + n k where a(t) is a transmission signal, ck is fading, n k is noise and each variable is a complex number. The output signal of the channel estimator 21k of the k-th finger is expressed as 1/c k when the estimation is ideally carried out. Therefore, in an ideal case, the multiplier 22k of the k-th finger is shown as: {c k · a(t) + n k }/c k The output signal of the multiplier 22k is subjected the phase compensation. Next, the output signal of the multiplier 22k is supplied to the multiplier 23k and multiplied by the weighting coefficient Wk which maximizes the S/N ratio after synthesis. Therefore, the output signal of the multiplier 22k is shown as: (c k · a(t) + n k ) · W k /c k where the above-mentioned weighting coefficient W k is |c k | 2 . Supposing that the fading is a complex value of c k and a complex conjugate is c k *, c k · c k * = ck 2 Therefore, it is possible to show the output signal of the multiplier 23k after weighting operation as the following equation. (c k · a(t) + n k ) · W k /c k = (c k · a(t) + n k ) · c k * = c k 2 a(t) + n k · c k * Since the adder 24 adds or synthesizes the respective output signals of the multipliers 231 to 23M for the M paths, the RAKE synthesis signal outputted from the adder 24 can be expressed by the following equation (6). As the RAKE synthesis signal is inputted to the decoder 14, it is supposed that the input signal of the decoder 14 is expressed by the following equation (7) by transforming equation (6). In this case, the branch metric in the decoder 14 is shown by the following equation (8) using equation (6). It should be noted that b(t) in the (8) equation is a branch value in the decoder 14. Also, equation (8) is an equation when b(t) = a(t), i.e., a right path selection is carried out. When noise components have no correlation with each other, equation (8) can be rewritten into the following equation (9). Therefore, it is sufficient that the branch metric is a constant value with no relation to t in order to cancel the time fluctuation by the branch metric for the optimization of the decoding gain. Therefore, the following equation (10) should be satisfied. In the equation (10), â ( t ) - b ( t ) 2 = â ( t ) 2 - 2 · â ( t ) · b ( t ) + b ( t ) 2 Since the value of this equation (11) is summation of errors, it is desirable that the value is minimum. Therefore, in order to make the left side of equation (11) minimum, it is necessary to render the following term in the right side of equation (11) a maximum. â ( t ) × b ( t ) For this purpose, it is necessary to multiply the input signal to the decoder 14 by the following coefficient on the right side of the branch metric of equation (10) The input signal to the decoder 14 which is obtained by multiplying the input RAKE synthesis signal to the decoder 14 shown by equation (3) by the weighting coefficient is obtained as the following equation (14) from equation (6). When the right side of the above-mentioned equation (14) and the RAKE synthesis signal of equation (5) are compared, it is necessary to multiply the RAKE synthesis signal by as the weighting coefficient. Next, the generation of the weighting coeffcient will be described. The noise measuring unit 31k shown in the Fig. 7 of the k-th finger of the noise measuring circuit 15 is supplied with the following signal from the correlating unit 18k of the inversely spreading circuit 12, as the input signal of the RAKE synthesizing circuit 13 of the k-th finger c k · a(t) + n k The channel estimator 34 takes out a fading component c k and supplies it to the dividing unit 35. The dividing operation of the above-mentioned input signal and the fading component c k is carried out so as to obtain a signal expressed as follows. a(t) + (n k /c k ) Also, the fading component c k is supplied to the square circuit 38 and is used to calculate the square value of the absolute value. The output signal of the dividing unit 35 is supplied to the square circuit 36 and used to calculate the square value of the absolute value as follows. a(t) + (n k /c k ) 2 After calculation of the square value, the calculation result is supplied to the subtracting unit 37 and the following calculation is carried out there. The output signal of the subtracting unit 37 shown by the above-mentioned equation (19) is supplied to the multiplier 39 together with the signal outputted from the square circuit 38. The output signal from the subtracting unit 37 and the signal from the square circuit 38 are multiplied there to produce a multiplication signal shown as |c k | 2 . Then, the multiplication signal is supplied to the adder 32 of Fig. 7 through the averaging circuit 40. The adder 32 adds and synthesizes the reciprocal value of the output signals |c k | 2 from the noise measuring circuit for the M paths, and generates the noise measurement signal shown by equation (15). The weighting circuit 16 (the multiplier 45 of Fig. 9) of Fig. 3 adds and synthesizes the square values of the noise components for the above-mentioned respective paths from the noise measuring circuit 15 to the RAKE synthesis signal of equation (5) from the RAKE synthesizing circuit 13 and multiplies the addition result by the noise measurement signal shown by equation (15) as the weighting coefficient. Thus, the multiplication result shown by equation (13) is produced and supplied to the decoder 14. By this, the decoding gain can be made a maximum in the decoder 14 without influence of the time fluctuation to the distortion of the input signal at the metric calculation, and thus as known from the above-mentioned literature. Also, it is possible to keep a bit error rate (BER) low after error correction. Also, because the means for calculation of the spreading code autocorrelation, comparing means, reception level measuring means are unnecessary, the circuit structure can be simplified. It should be noted that the present invention is not limited to the above-mentioned embodiment. For example, the signal format may be another format in which data and the unique word are multiplexed in time, other than the format of Figs. 2A and 2B. Also, the weighting coefficient calculating method can be applied to the system using a maximum ratio RAKE synthesis in addition to CDMA. Also, in the above embodiments, the weighting coefficient which is expressed by equation (15) is generated by the adder 32 of the noise measuring circuit 15. However, the structure may be employed in which the adder 32 calculates a value of the denominator of equation (15) and the RAKE synthesis signal is divided by the noise measurement signal in the weighting circuit 16. As described above, according to the present invention, the noise of the inversely spread signal is measured for every path. The noise measurement results are added and synthesized to generate a noise measurement signal. The weighting coefficient is calculated based on the noise measurement signal to cancel the time fluctuation of the distortion of the input signal at the metric calculation in the decoder. The weighting coefficient is multiplied by the RAKE synthesis signal. Therefore, the gain of the decoder can be made maximum. Also, the demodulation can be carried out, while the bit error rate (BER) can be suppressed low, compared with the conventional example. Thus, the receiver performance can be improved. Also, according to the present invention, the noise of the inversely spread signal is measured for every path, and a weighting coefficient is calculated from the measurement results. Therefore, means of calculating the autocorrelation value of the spread code, means for calculating the quality (SIR) of the reception signal from the signal that RAKE synthesis, and comparing means for comparing the cross-correlation value and the autocorrelation value of the reception signal can be made unnecessary, and the circuit structure can be simplified compared with the conventional, one.

Claims: Receiver comprising: an inversely spreading circuit (12) which inversely spreads a reception signal for every path using a spreading code to produce path data signals for paths; a RAKE synthesizing circuit (13) which synthesizes the path data signals to output a RAKE synthesis signal while carrying out a weighting operation for every path such that the RAKE synthesis signal has a maximum S/N ratio; a weighting circuit (16) which carries out a weighting operation; a decoder (14) which decodes the weighted signal to produce an information sequence; characterized in that the receiver further comprises a noise measuring circuit (15) which measures a noise level of each of the path data signals, and calculates a total noise amount for the paths from the measured noise levels; and that the weighting circuit (16) carries out a weighting operation of the RAKE synthesis signal based on the total noise amount to produce a weighted signal such that the time fluctuation of the distortion in the RAKE synthesis signal is cancelled. Receiver according to claim 1, characterized in that the noise measuring circuit calculates a reciprocal of a summation of the measured noise levels, and the weighting circuit multiplies the RAKE synthesis signal by the reciprocal of the summation of the measure noise levels. Receiver according to claim 1, characterized in that the noise measuring circuit calculates the summation of the measured noise levels, and the weighting circuit divides the RAKE synthesis signal with a reciprocal of the summation of the measured noise levels. Receiver according to any of claims 1 to 3, characterized in that the noise measuring circuit includes: a plurality of noise measuring devices (31), each of which is provided for a corresponding path and measures the noise level of one of the data path signals for the corresponding path; and a summing circuit (32) summing the measured noise levels to output the total noise amount. Receiver according to claim 4, characterized in that each of the plurality of noise measuring devices includes: a channel estimator (34) estimating the distortion of a corresponding one of the data path signals; a divider (35) dividing the corresponding data path signal by the estimated distortion to produce a divided signal; a first square circuit (36) calculating a first square of the divided signal; a second square circuit (38) calculating a second square of the estimated distortion; a subtracter (37) subtracting one from the first square to produce a subtracted signal; a multiplier (39) multiplying the subtracted signal by the second square; and an averaging circuit (40) averaging the multiplying results by the multiplier. Receiver according to any of claims 1 to 5. characterized in that the receiver is adapted to be used in a base station. Receiver according to claim 6, characterized in that the reception signal is a signal from a mobile terminal of a CDMA system. Receiver according to any of claims 1 to 6, characterized in that the receiver uses a maximum ratio RAKE synthesis. Base station containing a receiver according to one of claims 1 to 8. Method of demodulating a reception radio signal, comprising: inversely spreading the radio signal for every path using a spreading code to produce path data 5 signals for paths; carrying out a RAKE synthesis of path data signals to generate a RAKE synthesis signal; carrying out a weighting operation for every path such that the RAKE synthesis signal has a maximum S/N ratio; and decoding the weighted signal to produce an information sequence; characterized in that the method further comprises: measuring a noise level of each of the path data signals, and calculating a total noise amount for the paths from the measured noise levels; and weighting the RAKE synthesis signal based on the total noise amount to produce a weighted signal. The method according to claim 10, characterized in that the weighting includes: cancelling the time fluctuation of the distortion in the RAKE synthesis signal. The method according to claim 10 or 11, characterized in that the RAKE synthesis and the weighting operation are carried out simultaneously. The method according to any of claims 10 to 12, characterized in that the measuring includes: calculating a reciprocal of a summation of the measured noise levels, and the weighting includes: multiplying the RAKE synthesis signal with the reciprocal of the summation of the measured noise levels. Method according to any of claims 10 to 12, characterized in that the measuring includes: calculating a summation of the measured noise levels, and the weighting includes: dividing the RAKE synthesis signal with a reciprocal of the summation of the measured noise levels. Method according to any of claims 10 to 14, characterized in that the measuring includes: measuring the noise level of each of the data path signals; and summing the measured noise levels over the paths to output the total noise amount. Method according to claim 15, characterized in that measuring the noise level includes: estimating the distortion of a corresponding one of the data path signals; dividing the corresponding data path signal by the estimated distortion to produce a divided signal; calculating a first square of the divided signal; calculating a second square of the estimated distortion; subtracting one from the first square to produce a subtracted signal; multiplying the subtracted signal by the second square; and averaging the multiplying results by the multiplier. The method according to any of claims 10-16, characterized in that the reception signal is a signal from a mobile terminal of a CDMA system.

Inventors: SUGITA NAOHIKO, SUGITA, NAOHIKO
Applicants: NIPPON ELECTRIC CO, NEC CORPORATION
Application year: 2000
Main classification: H04B1
IPC codes: H04B1, H04B7