RF/MICROWAVE TUNABLE DELAY LINE

Abstract: A tunable delay line includes an input (36), an output (38), a first conductor (18) electrically coupled to the input (36) and the output (38), a ground conductor (16) and a voltage tunable dielectric layer (12) positioned between the first conductor (18) and the ground conductor (16). DC blocks (32, 34) and impedance matching sections (24, 26) are connected between the first conductor and the input (36) and output (38). Additional layers of tunable dielectric material and additional conductors can be positioned in parallel with the voltage tunable layer.

Description: RF/MICROWAVE TUNABLE DELAY LINE CROSS REFERENCE TO RELATED APPLICATION This application claims the benefit of the filing date of United States Provisional Application No. 60/166,267, filed November 18, 1999. FIELD OF INVENTION The present invention relates to electronic delay lines, and more particularly to such delay lines that can be controlled to provide a controllable delay. BACKGROUND OF INVENTION Electronic delay lines are used in many devices to delay the transmission of an electric signal. To achieve changes in the delay, some delay lines add or subtract delay elements to achieve different delay times, or adjust the corresponding delay elements in a delay line chain to obtain the desired delay time. The element tolerances need to be calibrated, and the choice is limited. One needs prior knowledge of the system to choose the elements necessary for proper delay time. Some programmable delay lines use analog- to-digital and digital-to-analog converter circuits to digitally control the delay time. The structure is rather complicated. In addition, the speed for digital conversion is slow. Also most importantly, such digital circuits typically cannot operate at microwave frequencies. There are many applications for tunable delay lines. An example, of an application for such tunable delay lines is the feed-forward amplifier. Because of their superior linearity, feed-forward amplifiers are widely used in telecommunications. The theory for achieving such linearity is described as follows. A two-tone signal is fed into a power splitter. One output path from the power splitter is connected to an amplifier and the other output path is connected to a delay line. The output of the amplifier will have a certain delay time, signal gain, intermodulation products, and a 180-degree phase shift. The output of the delay line is still a linear signal without phase shift or intermodulation products. By setting the same delay time for both paths, and using a hybrid coupler to couple the output of the amplifier to the output of the delay line with the same amplitude, the two-tone signal will be cancelled by the phase difference but the intermodulation products will not be cancelled. The intermodulation products will then be amplified by a second amplifier to obtain a 180 degree phase sift. Meanwhile, part of the output from the first amplifier is fed to a coupler that connects to a second delay line. The delay time of the second delay line is made equal to the delay time of the second amplifier. Finally, the output of the second amplifier is coupled to the output of the second delay line with the same amplitude of the intermodulation products. The result is that the intermodulation products are cancelled but not the two-tone signal. Therefore, a linear signal is obtained. In this type of application, the delay time needs to be accurate, reliable, and easily controlled. Previous patents relating to tunable/adjustable delay lines include United States Patents No 4,701,714; 4,766,559; and 5,631,593. Programmable delay lines are shown in United States Patents No. 5,933,039; 5,923,197; 5,641,954; 5,900,762; 5,465,076; 5,355,038; 5,144,173; 5,140,688; 5,013,944; and 4,197,506. Tunable ferroelectric materials are materials whose permittivity (more commonly called dielectric constant) can be varied by varying the strength of an electric field to which the materials are subjected. Even though these materials work in their paraelectric phase above the Curie temperature, they are conveniently called "ferroelectric" because they exhibit spontaneous polarization at temperatures below the Curie temperature. Tunable ferroelectric materials including barium-strontium titanate (BST) or BST composites have been the subject of several patents. Dielectric materials including barium strontium titanate are disclosed in U.S. Patent No. 5,312,790 to Sengupta, et al. entitled "Ceramic Ferroelectric Material"; U.S. Patent No. 5,427,988 to Sengupta, et al. entitled "Ceramic Ferroelectric Composite Material-BSTO-MgO"; U.S. Patent No. 5,486,491 to Sengupta, et al. entitled "Ceramic Ferroelectric Composite Material - BSTO-ZrO 2 "; U.S. Patent No. 5,635,434 to Sengupta, et al. entitled "Ceramic Ferroelectric Composite Material -BSTO-Magnesium Based Compound"; U.S. Patent No. 5,830,591 to Sengupta, et al. entitled "Multilayered Ferroelectric Composite Waveguides"; U.S. Patent No. 5,846,893 to Sengupta, et al. entitled "Thin Film Ferroelectric Composites and Method of Making"; U.S. Patent No. 5,766,697 to Sengupta, et al. entitled "Method of Making Thin Film Composites"; U.S. Patent No. 5,693,429 to Sengupta, et al. entitled "Electronically Graded Multilayer Ferroelectric Composites"; and U.S. Patent No. 5,635,433 to Sengupta, entitled "Ceramic Ferroelectric Composite Material-BSTO-ZnO". These patents are hereby incorporated by reference. A copending, commonly assigned United States patent application titled "Electronically Tunable Ceramic Materials Including Tunable Dielectric And Metal Silicate Phases", by Sengupta, filed June 15, 2000, discloses additional tunable dielectric materials and is also incorporated by reference. The materials shown in these patents, especially BSTO-MgO composites, show low dielectric loss and high tunability. Tunability is defined as the fractional change in the dielectric constant with applied voltage. Many prior art tunable delay lines have complicated tuning structures or too many tuning elements, and the tolerance of each delay element may affect repeatability and stability. There is a need for tunable delay lines that are relatively simple in structure and can be rapidly controlled over a broad frequency range of operation. SUMMARY OF THE INVENTION Tunable delay lines constructed in accordance with this invention include an input, an output, a first conductor electrically coupled to the input and the output, a ground conductor, and a voltage tunable dielectric layer positioned between the first conductor and the ground conductor. DC blocks and impedance matching sections are connected between the first conductor and the input and output. Additional layers of tunable dielectric material and additional conductors can be positioned in parallel with the voltage tunable layer. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is an isometric view of a tunable dielectric delay line constructed in accordance with a first embodiment of the invention; FIG. 2 is a top plan view of another embodiment of the invention; FIG. 3 is a side elevation view of the delay line of FIG. 2; FIG. 4 is an isometric view of a stack of layers of tunable dielectric materials such as can be included in the waveguide tunable delay line of FIGs. 2 and 3; and FIG. 5 is an isometric view of a tunable dielectric delay line constructed in accordance with another embodiment of the invention. DETAILED DESCRIPTION OF THE INVENTION This invention provides electronic delay lines that operate at room temperature and include voltage tunable materials. The tunable delay lines can be constructed using microstrip, coplanar or waveguide structures. When a DC tuning voltage is applied to the tunable material, the dielectric constant of the material changes, which causes a change in the group velocity and therefore produces a controllable delay time in the delay line. Referring to the drawings, FIG. 1 is an isometric view of a tunable microstrip delay line 10 constructed in accordance with a first embodiment of the invention. The delay line includes a layer of tunable high dielectric constant material 12 on a top planar surface 14 of a metal carrier 16. For the purposes of this description, a high dielectric constant is a dielectric constant in the range of 50 to 1000, and typically around 100 to 300. A conductor in the form of a microstrip 18 is positioned on a surface of the tunable high dielectric constant material 12, opposite the planar surface of the metal carrier. Layers of low dielectric constant material 20 and 22 are positioned on the surface of the carrier at opposite ends of the tunable layer of high dielectric constant material 12. Impedance matching lines 24 and 26 are positioned on surfaces 28 and 30 of the layers 20 and 22 of low dielectric constant material, respectively. For the purposes of this description, a low dielectric constant is a dielectric constant less than 30, typically in the range of 2 to 10. The impedance matching lines are coupled to the ends of tunable delay line section 18 by DC block capacitors 32 and 34. Connectors 36 and 38 serve as an input and an output, and are provided at the ends of lines 24 and 26 for connection to an external circuit. The metal carrier serves as a ground conductor and is connected to a controllable voltage source 40 by conductor 42. Conductor 44 connects the tunable section to the voltage source. By controlling the voltage applied to the microstrip line 18, the dielectric constant of the tunable layer 12 can be controlled. By controlling the dielectric constant, the delay of a signal passing through the delay line can be controlled. The DC blocks can be any of a microstrip chip capacitor, a coupled microstrip line, or a microstrip filter. In the preferred embodiment the tunable dielectric layer is preferably comprised of Barium-Strontium Titanate, Ba x Srι -x TiO 3 (BSTO), where x can range from zero to one, or BSTO-composite ceramics. Examples of such BSTO composites include, but are not limited to: BSTO-MgO, BSTO-MgAl 2 O 4 , BSTO-CaTiO 3 , BSTO-MgTiO 3 , BSTO-MgSrZrTiO 6 , and combinations thereof. Other tunable dielectric materials may be used partially or entirely in place of barium strontium titanate. An example is Ba x Caι_ χTiO 3 , where x ranges from 0.2 to 0.8, and preferably from 0.4 to 0.6. Additional alternative tunable ferroelectrics include Pb x Zr ]-x TiO 3 (PZT) where x ranges from 0.05 to 0.4, lead lanthanum zirconium titanate (PLZT), lead titanate (PbTiO 3 ), barium calcium zirconium titanate (BaCaZrTiO 3 ), sodium nitrate (NaNO 3 ), KNbO 3 , LiNbO 3 , LiTaO 3 , PbNb 2 O 6 , PbTa 2 O 6 , KSr(NbO 3 ), and NaBa 2 (NbO 3 ) 5 and KH 2 PO 4 . In addition, the present invention can include electronically tunable materials having at least one metal silicate phase. The metal silicates may include metals from Group 2 A of the Periodic Table, i.e., Be, Mg, Ca, Sr, Ba and Ra, preferably Mg, Ca, Sr and Ba. Preferred metal silicates include Mg 2 SiO 4 , CaSiO 3 , BaSiO 3 and SrSiO 3 . In addition to Group 2A metals, the present metal silicates may include metals from Group 1A, i.e., Li, Na, K, Rb, Cs and Fr, preferably Li, Na and K. For example, such metal silicates may include sodium silicates such as Na 2 SiO 3 and NaSiO 3 -5H 2 O, and lithium-containing silicates such as LiAlSiO 4 , Li 2 SiO 3 and Li 4 SiO 4 . Metals from Groups 3A, 4A and some transition metals of the Periodic Table may also be suitable constituents of the metal silicate phase. Additional metal silicates may include Al 2 Si 2 O 7 , ZrSiO 4 , KAlSi 3 O g , NaAlSi 3 O g , CaAl 2 Si 2 O g , CaMgSi 2 O 6 , BaTiSi 3 O 9 and Zn 2 SiO 4 . The above tunable materials can be tuned at room temperature by controlling an electric field that is applied across the materials. In an example embodiment of the invention, the tunable section of the delay line includes a low impedance microstrip line of about 3 to 10 ohms, which is on a tunable high dielectric constant substrate layer with thickness of around 0.25 mm. The material choice in this example is BSTO-MgO. The dielectric constant of the tunable material is chosen to be about 800, so that the tunable length of a 10 nsec delay line is about 10 cm long. If the straight delay line is changed to an S shaped line then the length of the device can be further reduced. The length of the tunable delay line is calculated as: L = C - ( The tuning range of the delay line is defined as: Here, t is the delay time of the tunable delay line and c is the speed of light. ε rl and ε _ 2 are the zero biased, and fully biased dielectric constants respectively. The width of the microstrip line conductor 18 in the tunable delay line affects the impedance. When a high dielectric constant material is used, a thin microstrip line can be only a fraction of an ohm or a few ohms. For easier impedance matching, one should choose the thinner line to get higher impedance. However, the effective tunability is proportional to W/H, where W is the width of the tunable delay line, and H is the thickness of the tunable material. Because of the fringing effect of the delay line, the material biased underneath a thin microstrip line cannot be tuned effectively. Therefore, the choice between impedance and tunability is a trade off. Two sections of quarter-wave length lines 24 and 26 at the input and output provide matched impedance to the center tunable delay line 18. The circuit is matched to 50 ohms at the input and the output with about 30% bandwidth. The dielectric material 20 and 22 in the matching sections is not tunable. In the illustrated embodiment, these materials are low dielectric constant substrates such as Duroid or another type of material. In one embodiment, the matching section materials 20 and 22 have a dielectric constant of about 10 with the same thickness as the center tunable line layer 12. The total circuit delay time for this example is about 10 nsec with ± 0.3 nsec tuning. The tunable delay line is symmetrical with respect to the center of the assembly. The two matching section conductors 24 and 26 connect the input port (or the output port) to the center microstrip line 18. Both matching sections are a quarter wavelength long and have different impedances. The matching sections contribute about 0.5 nsec of fixed delay time. Therefore, the tunable section should contribute a delay of 9.5 nsec. The tuning voltage required is about 100 to 500 volts, which is based on 40% tuning, and the tuning voltage is proportional to its thickness of the tunable layer. The electric field applied to the tunable layer can range from about 2 volts per μm to 8 volts per μm. The tuning voltage is connected to the center line by a coax cable 44. Two DC blocks 32 and 34 are used to couple the microstrip line to the input and the output. Alternatively, at higher frequencies, filters or couplers may be used to act as DC blocks. FIGs. 2 and 3 are top plan and elevation views of another embodiment of the invention. These figures illustrate a waveguide tunable delay line 50 with the same delay time and using the same materials as described with respect to the delay line of FIG. 1. The waveguide tunable delay line 50 includes a plurality of layers 52, 54, 56 of tunable dielectric material positioned to extend in an axial direction within a waveguide 58 housing. The waveguide housing includes an upper half 60 and a lower half 62. Adapters 64 and 66 extend from opposite ends of the waveguide and support connectors 68 and 70 respectively. A plurality of ceramic matching sections 72, 74 and 76 are positioned at each end of the layers of tunable dielectric material. FIG. 4 is an isometric view of a stack 78 of layers of tunable dielectric materials such as can be included in the waveguide tunable delay line of FIGs. 2 and 3. The stack 78 includes eight layers of tunable dielectric material, several of which are numbered as items 52, 54 and 56. Typically the layers would be the same material. However, special applications might exist such that mixing different materials could compensate for some performance parameters. Electrodes are provided on each side of the stack and between the layers so that the DC control voltage can be applied to the layers to control their dielectric constants. In this embodiment, electrode 80 on the top surface of the stack is a plated layer of gold with thickness of 3 μm that covers the top surface of layer 52 except for a portion of the surface near the edges thereof, referred to as a margin 82. The margin is included to avoid voltage breakdown at the edges of the stack. A copper shim 84 is used to couple the control voltage to the plated electrode. Similar plated electrodes and shims are positioned on the bottom surface of the stack and between the layers. A control voltage feed assembly 86 is used to connect the positive control voltage to the top and bottom electrodes and to electrodes between alternate layers. A ground connection assembly 88 is used to connect to similar electrodes between alternate layers. The electrodes serve as ground conductors. In one embodiment of the invention, the layer thickness is about 1 mm and 10 layers are used in the stack. The delay line input and output matches a WR430 waveguide, which then matches to the waveguide and to the coaxial adapter. The total insertion loss including adapters is approximately 2 to 3 dB. The center tunable line can be 100 mm to 300 mm long based on the delay time required, and in turn the material chosen. Each layer's top and bottom are metalized for introducing tuning voltage. Usually, one side of the layer onto which positive voltage is applied, will have a margin at each edge in order to avoid high voltage breakdown. The impedance matching sections 72, 74 and 76 are non-tunable ceramic materials that can have different dielectric constants and may be different thickness. These sections connect to the stack of tunable dielectric layers in the center tunable section to the input and the output. Depending on bandwidth, loss and VSWR requirements, the matching can include from 2 to 5 sections. The waveguide should make a tight fit for the ceramic materials. However, indium foil can be used to fill up all air gaps. The indium foil acts as an extension of the waveguide walls to squeeze out air between the ceramic and the waveguide walls. The tuning voltage is introduced through a thin coax cable structure from one side of the waveguide. A low pass filter 90 may be added to the control voltage circuit to block signal leakage, particularly at higher frequencies. This invention includes, tunable/adjustable delay lines that are fabricated using a voltage tunable dielectric material. When the tuning voltage is applied to an electrode positioned adjacent to the tunable material, the dielectric constant of the material is decreased. The rate of change is approximately linear. The tunability is defined as: tunability = (ε r ι - ε r2 )/ε rl. Here, ε rl is the material dielectric constant before applying the tuning voltage and ε r2 is the dielectric constant after tuning. By choosing the proper dielectric constant, tuning range and loss tangent, the delay lines can be constructed that operate in a frequency range from 800 MHz to 40 GHz. The delay lines of this invention can be electronically tuned to reach the accuracy of a fraction of a nanosecond, which is repeatable and stable. Since the tunable material is a good insulator, the DC power consumption of the tuning voltage supply is very low, with a current far less than a milliampere. The voltage tuned delay lines have the advantage of fast tuning, good tunability, small size, simple control circuits, low power consumption, and low cost. In addition, the delay lines show good linear behavior and can be radiation hardened. In order to satisfy the need for adjustable delay time, such as for example in the feed-forward amplifier, the present invention uses a voltage tunable material to make tunable delay lines. The invention can take the form of a microstrip delay line or a multilayer of tunable material filled waveguide delay line. For tuning the delay line, a biasing DC voltage is applied across the tunable material and the voltage is adjusted until the desired time delay is obtained. Tuning and settling time are in the nano-second range. The tuning structure is simple and reliable. The delay lines of this invention can also be constructed in a coplanar format. FIG. 5 is an isometric view of a coplanar tunable dielectric delay line 92 constructed in accordance with the invention. In Figure 5, the metallized microstrip center line is connected to the tuning voltage as in FIG. 1. Ground plane electrodes 94 and 96 are mounted on the surface of the tunable dielectric material and are positioned to form two parallel gaps between the microstrip and the ground plane electrodes. The ground plane electrodes are connected to the ground through conductor 96. A voltage applied between the center microstrip conductor and the ground plane electrodes is used to control the dielectric constant of the tunable material in the vicinity of the gaps, and to thereby control the delay time of a signal passing through the center line. In this embodiment, the tunable ceramic is a thick film that has been screen printed on a substrate base before the metallization. The base material can be a non-tunable low loss ceramic. The frequency of the delay lines depends upon the material, and can range from 800 MHz to 40 GHz. The present invention takes advantage of low loss voltage tunable materials to build tunable delay lines that vary the dielectric constant by a change of voltage across the material. The waveguide delay line is made of multiple layers of tunable material. The dielectric constant can be selected form a range of 30 to 1000. For the low frequency and small size requirement, one can choose a higher dielectric constant material because the signal wavelength is such a material will be much shorter. For the high frequency, the wavelength in the high dielectric constant material is too small. Therefore, one should choose low dielectric constant material. The choice of thickness for the dielectric material is a tradeoff among loss, mechanical strength, and tuning voltage. Thinner material requires less tuning voltage, but thinner material has increased losses and lower mechanical strength. A design tradeoff between size, tunability and the loss requirement is therefore exercised. When multi-layer structures are used, the tuning voltage range will be considered only for the single layer. This structure allows one to use thicker material by layering without increasing the control voltage. In the design process, the increase of thickness can also provide an increase of characteristic impedance to provide better impedance matching. The same tunable dielectric constant material can be used for the microstrip delay line. For the same delay time, the microstrip delay line will be lossier. However, it will be smaller in overall width and height. Other methods can be used to implement the tunable delay line. Such as a delay line fabricated on a tunable, thick or thin film that is deposited on the surface of a low loss non-tunable ceramic. The present invention provides a DC voltage linearly tunable delay line, which can be rapidly controlled by a computer program. The delay lines can operate over a broad frequency range. As examples, three delay lines have been described. The first embodiment is a microstrip line structure. The second embodiment is a waveguide filled with bulk tunable ceramic material. Both the first and second embodiments operate in the L-band frequency range. The third embodiment is the example of coplanar structure delay line. By using the present tunable delay line in feed-forward amplifiers, accurate time delays will be easier to obtain by tuning a DC voltage. The delay time versus tuning voltage is an approximately linear relationship. In addition, high power applications can be realized by using a waveguide structure delay line. While the present invention has been described in terms of what are at present believed to be its preferred embodiments, it will be apparent to those skilled in the art that various changes may be made to the disclosed embodiments without departing from the scope of the invention as defined by the following claims.

Claims: What is claimed is: 1. A tunable delay line comprising; an input; an output; a first conductor electrically coupled to the input and the output; a ground conductor; a voltage tunable dielectric layer positioned between the first conductor and the ground conductor. 2. A tunable delay line according to claim 1, further comprising: a circuit for applying a control voltage between the first conductor and the ground conductor. 3. A tunable delay line according to claim 1, further comprising; a first DC block connected between a first end of the first conductor and the input; and a second DC block connected between a second end of the first conductor and the output. 4. A tunable delay line according to claim 3, wherein each of the first and second DC blocks comprises one of: a microstrip chip capacitor; a coupled microstrip line; and a microstrip filter. 5. A tunable delay line according to claim 1, further comprising: a first impedance matching section connected between a first end of the first conductor and the input; and a second impedance matching section connected between a second end of the first conductor and the output. 6. A tunable delay line according to claim 5, wherein each of the impedance matching sections comprises: a quarter-wave length microstrip conductor on a non-tunable low dielectric constant substrate. 7. A tunable delay line according to claim 5, wherein each of the impedance matching sections matches 50 ohms at the input and the output. 8. A tunable delay line according to claim 1, wherein the first conductor comprises: a microstrip line. 9. A tunable delay line according to claim 8, wherein the microstrip line is a metalized layer. 10. A tunable delay line according to claim 1 , further comprising: a housing containing the first conductor, the ground conductor, and the voltage tunable dielectric layer. 11. A tunable delay line according to claim 10, wherein the housing comprises: a machined aluminum waveguide. 12. A tunable delay line according to claim 1, wherein the voltage tunable dielectric material has a loss tangent in the range of 0.001 to 0.01 at frequencies in a range of 800 MHz to 40 GHz. 13. A tunable delay line according to claim 1, further comprising: a plurality of additional layers of tunable dielectric material; and a plurality of additional electrodes for applying control voltage to the plurality of additional layers of tunable dielectric material. 14. A tunable delay line according to claim 13, further comprising: a first bulk ceramic impedance matching section connected between a first end of the plurality of additional layers of tunable dielectric materials and the input; and a second bulk ceramic impedance matching section connected between a second end of the plurality of additional layers of tunable dielectric materials and the output. 15. A tunable delay line according to claim 14, wherein the first and second bulk ceramic impedance matching sections comprise: a low dielectric constant, non-tunable, quarter-wave length long, bulk ceramic. 16. A tunable delay line according to claim 1, wherein the ground conductor comprises: first and second electrodes lying parallel to the first conductor. 17. A tunable delay line according to claim 16, wherein the first and second electrodes and the first conductor are mounted on a surface of the voltage tunable dielectric layer. 18. A tunable delay line according to claim 1, wherein the tunable dielectric layer comprises a material selected from the group of: barium strontium titanate, barium calcium titanate, lead zirconium titanate, lead lanthanum zirconium titanate, lead titanate, barium calcium zirconium titanate, sodium nitrate, KNbO 3 , LiNbO 3 , LiTaO 3 , PbNb 2 O 6 , PbTa 2 O 6 , KSr(NbO 3 ), NaBa 2 (NbO 3 ) 5) KH 2 PO 4 , and composites thereof. 19. A tunable delay line according to claim 1, wherein the tunable dielectric layer comprises a barium strontium titanate (BSTO) composite selected from the group of: BSTO-MgO, BSTO-MgAl 2 O 4 , BSTO-CaTiO 3 , BSTO-MgTiO 3 , BSTO- MgSrZrTiO 6 , and combinations thereof. 20. A tunable delay line according to claim 1, wherein the tunable dielectric layer comprises a material selected from the group of: Mg 2 SiO 4 , CaSiO 3 , BaSiO 3 , SrSiO 3 , Na 2 SiO 3 , NaSiO 3 -5H 2 O, LiAlSiO 4 , Li 2 SiO 3 , Li 4 SiO 4 , Al 2 Si 2 O 7 , ZrSiO 4 , KAlSi 3 O 8 , NaAlSi 3 O 8 , CaAl 2 Si 2 O g , CaMgSi 2 O 6 , BaTiSi 3 O 9 and Zn 2 SiO 4 .

Inventors: PAO DOUGLAS, SENGUPTA LOUISE C, ZHU YONGFEI, PAO, DOUGLAS, SENGUPTA, LOUISE, C., ZHU, YONGFEI
Applicants: PARATEK MICROWAVE INC, PARATEK MICROWAVE, INC.
Application year: 2000
Main classification: H01P1
IPC codes: H01P1