HIGHLY INTEGRATED ADSL LINECARD

Abstract: An apparatus comprises a data analog channel (212) having a wire connector (201), a data channel and a transformer where the transformer couples the wire connector to a bandpass filter within the data channel. A method comprises channeling voice (211) and data (212) to a first transformer (204) and a second transformer (204), extracting the voice signals by filtering the data signals through the first transformer (204), and extracting the data signals by filtering the voice signals through the second transformer (204).

Description: HIGHLY INTEGRATED ADSL LINECARD FIELD OF INVENTION The field of invention relates generally to signal processing; and more specifically, to Asymmetric Digital Subscriber Line (ADSL) signal processing and the real estate and power consumption issues surrounding the integration of a voice and ADSL data channels onto a single line card. BACKGROUND OF THE INVENTION ADSL is a technology that allows the transfer of data and voice signals over a single telephone wire 102 (typically a single-pair twisted copper wire) to the home 101 (or small office). ADSL is usually offered as a service from a service provider. In a typical case, an edge node 111 on the service provider's network 112 implements the simultaneous voice and data communication between the home 101 and the service provider over the single telephone wire 102. The simultaneous transmission of voice and data over a single wire 102 is accomplished by a mechanism similar to that of commercial radio. In commercial radio, each radio station broadcasts over a "slot" of electromagnetic bandwidth (e.g., 1130 kHz +/- 2KHz for an A.M. station) specially reserved for that station. Since each slot is reserved solely for that station, no interference occurs between proximate stations. A radio receiver "tunes" into each station by separating and amplifying only that portion of the electromagnetic spectra that corresponds to the station's allotted slot bandwidth. ADSL operates in an analogous manner. That is, the total bandwidth of wire 102 is divided into slots of bandwidth reserved for each communication channel. There are three bandwidth slots in ADSL: 1) a Plain Old Telephone (POTS) bandwidth slot 113a (also referred to simply as a voice channel bandwidth slot 113a); 2) an upstream data channel bandwidth slot 114a; and 3) a downstream data channel bandwidth slot 115a. The voice channel bandwidth slot 113a carries bi-directional regular telephony traffic (i.e., a telephone conversation) approximately between 30Hz and 4.0 kHz. The upstream data channel bandwidth slot 114a carries data from the home 101 to the edge node 111 approximately between 30kHz and 130kHz, while the downstream data channel bandwidth slot 115a carries data from the edge node 111 to the home 101 approximately between 130kHz and l.lMhz. Typical edge node systems offering ADSL service comprise a splitter 103, a voice channel 106 and a data channel 107. High level logic 110 is responsible for translating between the voice channel 106 and data channel 107 and the service provider. The voice channel 106 of edge node 111 processes the telephony signals sent/received in the voice channel bandwidth slot 113a. The data channel 107 of edge node 111 processes the data carried over the data bandwidth slots 114a and 115a. The splitter 103 is essentially a device for: 1) integrating the data signals 104 with the voice signals 105 onto the wire 102 and 2) separating the data signals 104 and the voice signals 105 from the wire. The data channel 107 is also responsible for similarly integrating/ separating upstream channel 108 and downstream 109 channel to/from the splitter 103. A problem with current edge node systems is lack of integration. Specifically, the splitter 103, voice channel 106 and data channel 107 are each embodied within a separate line interface card (LIC or blade). Thus, each of these three functions (103, 106, 107) consume a backplane card slot. The result is real estate inefficiency within the edge node 111 and more expensive hardware costs per ADSL port. Furthermore in order to pass homologation tests, the splitter 103 function typically employs large, high energy tolerant passive elements. Homologation tests are performed to ensure the interface to the telephone wire 102, in this case the splitter 103, can safely dissipate high energy signals (such as lightning strikes and contact with high power lines). Thus integrating these components onto a single card having logic to support the data and voice traffic present difficult layout problems. Furthermore, since substantial and different forms of functionality are located on a single LIC, power consumption is an additional concern. Thus, what is needed is a ADSL solution that integrates all three functions (splitter 103, data 107 and voice 106) onto a single LIC which requires limiting the real estate and power consumed at each functional level. SUMMARY OF THE INVENTION An apparatus is described comprising a data analog channel having a wire connector, an upstream data channel and a transformer where the transformer couples the wire connector to a bandpass filter within the upstream data channel. BRIEF DESCRIPTION OF THE DRAWINGS The present invention is illustrated by way of example and not limitation in the figures of the accompanying drawings, in which like references indicate similar elements, and in which: Figure 1 is a depiction of a prior art method and apparatus for implementing ADSL service. Figure 2 is a depiction of a analog voice and analog data channels on an integrated LIC. Figure 3 is a more detailed depiction of an analog voice channel. Figure 4 is detailed depiction of an upstream data channel. Figure 5 is a detailed depiction of a downstream data channel. Figure 6 is a detailed depiction of the architecture of an integrated LIC. DETAILED DESCRIPTION An apparatus is described comprising a data analog channel having a wire connector, an upstream data channel and a transformer where the transformer couples the wire connector to a bandpass filter within the upstream data channel. This and other embodiments of the present invention may be realized in accordance with the following teachings and it should be evident that various modifications and changes may be made in the following teachings without departing from the broader spirit and scope of the invention. The specification and drawings are, accordingly, to be regarded in an illustrative rather than restrictive sense and the invention measured only in terms of the claims. As discussed, integrating the logic necessary to process all three data channels onto a single adapter card presents a significant layout challenge. The analog front end of an integrated LIC is shown in Figure 2. As shown in Figure 2, the analog front end (also referred to simply as "front end") not only comprises the splitting function but also various filters, amplifiers and other analog functional blocks. These tend to consume too much real estate in relation to the complexity of the signal processing involved. As such, the aforementioned layout challenge is best addressed by scrutinizing the design of the entire analog front end. Before discussing this, however, a description of the front end's functionality is necessary. A telephone wire typically comprises two wires labeled "Tip" and "Ring". The section of the front end that physically connects to the wire (i.e., wire connector 201) is labeled in this manner. Wire connector 201 may be comprised of BNC connectors or other connectors usually specified by the applicable industry standard. For safety and testing, a relay 202 may be coupled to the wire connector 201. The closure of the relay 202 typically signifies the final and formal recognition by the LIC's intelligence that the line is "live". Passive current limiting elements 203 are coupled to relay 202. Their purpose is to limit current introduced onto the LIC. As discussed, substantial current may be introduced onto the card from lightning, crossed power lines, etc. In order to satisfy worst case conditions, the elements 203 should be high energy tolerant components. As such they are also typically large. Although the removal of large components is desirable, in one embodiment, the use of large elements 203 is permissible because other layout efficiencies have been introduced, some of which are described below. In one embodiment, the elements 203 are in a single package and comprise large ceramic resistors with an embedded fuse. Voice and data signals exit passive current limiting elements 203 at branching node 213. Voice signals are processed in the analog voice channel circuitry 211 while data signals are processed in the analog data channel circuitry 212. Circuitry 211 and circuitry 212 may be referred to simply as analog channels. Thus, the analog front end is comprised of a voice analog channel 211 and a data analog channel 212 where each of analog channels 211 and 212 shares the current limiting element 203 and the wire connector 201. Analog channels are comprise functional blocks between and including the telephone wire connector 201 (typically found on the card edge) and the analog/digital (A/D) conversion blocks located on the card. In this embodiment, A/D conversion is performed by a CODEC chip 209 for voice and an AFIC chip 210 for data. Devices 209 and 210 are discussed in further detail below. The analog voice channel 211 is responsible for extracting/transmitting only the voice signals from/ to branching node 213 while the analog data channel 212 is responsible for extracting/ transmitting only the data signals from/ to branching node 213. Thus the relationship between the branching node 213 and the two analog channels 211 and 212 together realizes the aforementioned splitter 103 of Figure 1. The data analog channel 212 comprises an upstream datapath or channel (via data rx circuitry 207) and a downstream datapath or channel (via data tx circuitry 208) that are separate from one another up to the isolation transformer 204. Thus, upstream traffic is mostly separated from downstream traffic. Furthermore, in this embodiment, both circuitry 207 and circuitry 208 employ a differential channel approach meaning a "+" and "-" signal is associated with each datapath direction. Thus, a pair of wires is seen for each circuitry 207and circuitry 208. In comparison, the voice tx/rx circuitry 206 also has upstream traffic separated from downstream traffic. However, the voice tx/rx circuitry 206 comprises a single ended approach meaning only one wire exists per datapath direction. Differential channels have a 3dB greater signal to noise ratio than single ended channels. In one embodiment, the data analog channel 212 employs differential technology in order to account for the greater attenuation suffered by the data signals in the wire to the home (as compared to voice signals) due to their higher frequencies. Other embodiments may use wire technology that eliminates the need for differential channel technology for data signals or requires differential channeling for voice signals. Generally, the applicable industry standard determines or influences these technology choices. Second, the data analog channel 212 is protected from lightning and other high energy signals on the wire by isolation transformer 204. Isolation transformer still allows the coupling of data signals between the data analog channel 212 and the home, however. The isolating feature of the transformer is used to reduce the size of the spreading function components and therefore improve real estate efficiency. That is, the splitting function is realized by designing voice tx/rx circuitry 206, data rx circuitry 207 and data tx circuitry 208 with their respective bandwidth slots (so the three different ADSL channels are properly separated). Designing the LIC to include the two analog channels 211 and 212 processing their respective signals is accomplished by setting the bandwidth of the channels 211 and 212 to their respective slots. That is, referring to Figures 1 and 2, the voice tx/rx circuitry 206 establishes a voice channel bandwidth between 30 Hz and 4 kHz, the data rx (upstream) circuitry 207 establishes an upstream channel bandwidth between 30 kHz and 130 kHz, and the data tx (downstream) circuitry 208 establishes a downstream channel bandwidth between 130 kHz and 1.1 MHz. Thus, Figure 2 shows the organization of the signal processing (and its corresponding design) used to manage multiple ADSL channels on a single LIC with multiple POTS lines. The voice tx/rx circuitry 206, data rx circuitry 207 and data tx circuitry 208 are discussed in more detail with reference to Figures 3, 4 and 5 respectively. Nevertheless, Figure 2 indicates that the bandwidths associated with each of these channels is accomplished with various filters. As mentioned above, CODEC chip 209 encodes /decodes analog voice signals from/to higher level voice digital signals in the LIC while the AFIC chip 210 encodes /decodes analog data signals from/ to higher level data digital logic signals in the LIC. Referring back to Figure 1, the splitting function 103 is typically performed on a separate LIC connected to the wire 102. This results in little incentive to design a LIC having an efficient layout and, as such, the separation performed by the prior art splitter 103 is typically implemented with large, high energy tolerant parts. Implementing the splitter with large parts is prohibitive with a fully integrated LIC. Thus separating the data signals from the voice signals with components protected behind the isolation transformer 204 in Figure 2 allows for the spreading function to be performed with small, lower energy tolerant parts. Although current limiting elements 203 provide protection against current surges, etc., placing the filter components within data rx circuitry 207 "behind" the transformer 204 provides the best possible protection. This allows the designer to employ less energy tolerant parts, with correspondingly smaller package types, for these components. Specifically, surface mount devices such as SOIC packages for integrated circuits and chip packages for resistors, inductors, and capacitors may be used as opposed to larger pin-through-hole packages. Therefore, real estate efficiency is realized by inserting, along the datapaths, a transformer 204 between the wire connector 201 and the components that define the upstream and downstream data channel bandwidth slots (i.e., the data rx circuitry 207 and data tx circuitry 208). Furthermore, since the upstream data circuitry 207 and the downstream data circuitry 208 are communicatively coupled at the isolation transformer 204, it is possible that various downstream data signals, referred to as echoes, may possess frequencies at or near the passband of the data rx circuitry 207. As such, it is desirable to filter these echo signals before they enter that stage 207. The hybrid circuit 205, when coupled with isolation transformer 204, is a passive filter responsible for attenuating frequencies associated with echoes. Lastly, the isolation transformer 204 and capacitor 215 form a passive filter that also helps remove voice signals on the AFIC 210 side of the transformer. In one embodiment, the capacitance of capacitor 215 is 47nF. Other embodiments may employ different capacitance /transformer pairs or different size transformers. The inductance of transformer 204 is used not only for echo cancellation but also for filtering voice signals. The energy tolerance (and therefore package size) of transformer 204 may be modest in light of the surge protection provided by passive elements 203. Figure 3 shows a more detailed drawing of the voice tx/rx circuitry 206 between the CODEC chip 209 and the branching node 213 nets "ring_x" and "tip_x" of Figure 2. Referring to Figure 3, a front end low pass filter 301 that attenuates data signals. Again, a transformer is used, transformer 302, to construct a filter that attenuates unwanted signals (e.g., data signals). Integrating the specific type of transformer 302 into the front end low pass filter 301 of the voice channel allows for, as discussed presently, significant real estate savings as compared to other designs. For example, other approaches may attempt to use legacy telephone designs from pre-existing hardware in order to reduce design time and reduce the risks associated with a re-design. Nevertheless, such legacy design approaches will typically have to add a transformer on the front end in order to implement ADSL filtering. In order to keep the performance of these legacy designs unchanged as much as possible, as compared to the pre-existing hardware, the design point may be to make the new transformer substantially "transparent" to the legacy design; meaning, the series resistance of the new transformer is reduced, and may be minimized, so that its effects on the signals of the legacy design are reduced and /or minimized. However, minimizing transformer series resistance means the cross sectional area of the wires used in the transformer windings must be maximized. This results in large transformers. The approach described herein is to use the winding resistance as an integral part of the front end filter. Such filters may employ resistance values in the tens or hundreds of ohms. Thus, a transformer used in such a filter may have smaller wires than the "transparent" transformers described above resulting in a smaller transformer. For example in the embodiment of Figure 3 the windings employ 40 gauge wire. The resistances 310a and 310b are 56.68 ohms +/-5% each and the winding inductances 325 are lOmH +/- 5%. Other gauge wires and resistance values may be used, such as resistances ranging from 1-150Ω. Figure 3 does not reflect the mutual capacitance of the transformer 302. Ideally, the mutual capacitance is reduced, or even minimized, to a negligible value to increase the common mode rejection ratio of the filter. This is accomplished by using a sector wound transformer. The placement of the four windings, 320, 321, 322 and 323, relative to the wall blocks flux lines between these windings which drops the mutual capacitance substantially. Also, the resistance values of the windings should be within 0.5% to promote the common mode rejection ratio of filter 301. In other words, by separating the transformer windings into 4 separate windings, it is possible to average out the inconsistencies of the wire resistance by interleaving the four windings. This technique is used to achieve a 0.5% delta winding resistance specification and also eases difficulty of manufacturing a tight tolerance transformer. Other specifications for one embodiment of the transformer 302 include a turns ratio of 1:1 and dielectric rating of 300Vdc. In one embodiment, the package type for transformer 302 is EFD 15 0.875"x0.620" max. Passive network 323 is a "ring- trip" circuit used to detect when a ringing telephone is picked up. Passive network 323 is connected to tip_x, ring_x, and low pass (filter) 301, as well as the DT and DR inputs of SLIC 304 (via a pair of capacitors). In one embodiment, these capacitors are 220nf capacitors. A relay 315 is also connected to tip_x and ring_x via low pass filter 301. In one embodiment, relay 315 is the starting point of a design that is very similar to legacy designs. That is, once the low pass filter 301 is added, a previous hardware design (i.e., telephone circuit without ADSL) may be used for most of the analog voice channel, with the exception of passive network 305. To avoid obscuring the invention, the other half of relay 315 is not shown in Figure 3. In one embodiment, the relay 315 shows a dual single pole, single throw switch. However, consistent with most other telephony designs, a dual single throw double pole switch may be implemented. A ring generator is coupled to other poles of relay 315 to ring the telephone and to monitor the "on-hook"/ "off- hook" state of the telephone. Also connected to relay 315 is a standard tip and ring block 303. The SLIC device 304 connected to tip /ring block 303, is a commercially available device used to drive the necessary voltage levels and signal shapes associated with the voice signals the LIC transmits over the telephone wire. The SLIC 304 also is designed to receive worst case signals in the receive direction. In one embodiment, SLIC 304 is a member of the ERICCSON 386X0 ™ family, which possess the ability to provide loop start, ground start, pulse metering, built in battery switching and protection against high loop current overheating without device shutdown. Also coupled to the SLIC 304 is passive network 305. Passive network 305 is used for echo cancellation and impedance matching. Finally, in the receive direction, two cascaded low pass filters are placed between passive network 305 and the CODEC 307. The result of cascading the two low pass filters 306 is a double pole filter having 6dB drop per decade after this frequency. Figure 4 shows a detailed depiction of the data rx circuitry 207 coupled with the AFIC chip 210 of Figure 2. Referring to Figure 4, the first stage of the data rx circuitry comprises filter 401. In one embodiment, filter 401 operates as a filter and as an active differential amplifier. In one embodiment, a single pole filter having a pole at 120 kHz. The filter 401 is active, and thus this first stage is used not only to amplify weak incoming signals but also to limit the bandwidth of the channel to the appropriate high end cutoff frequency. Filter 401 may be comprised of surface mount components since they are protected by transformer 204, referring briefly back to Figure 2. In one embodiment, the operational amplifiers are made of SOIC packages. However, other small package types may be used such as DiP, SSOP, SVIC packages. The same is true for the passive components used. That is, chip packages, such as 0402, 0603, 0805, 1206, may be used for the resistors and capacitors of stage 401. Filter 402 is connected to filter 401 via a pair of windings used to elevate capacitive loading on the data tx circuitry. In one embodiment, filter 401 is a passive 5 pole high pass filter having a zero at 30 kHz. However, other filter designs such as Chebychev or Butterworth may also be used. In one embodiment, the value of the inductance is lOOOnH. Since filter 402 is passive, both real estate and power consumption are conserved. In other words, since filter 402 is protected by transformer 204 of Figure 2, surface mount components may be used, which saves space, and the active filters may comprise an integrated circuit, which tends to consume more energy than passive filters. Note also that the combination of filter 401 and filter 402 result in a band pass filter having a bandpass between 30 and 130 kHz. As such, the combination of these two stages result in the formation of the proper slot bandwidth (approximately 30 - 130 kHz) used to realize the upstream analog data channel, which is further processed in the AFIC 404. Other embodiments may employ different combinations of filter types. For example, a single bandpass filter may be used that is not easily broken down into a low pass or high pass section. Furthermore, either active or passive filters may be used at the choice of the designer. For example, the high pass filter could be active and the low pass filter could be passive. Other filter embodiments having different pole /zero values may be employed and /or different capacitor /resistor /inductor values as well. For example, the slot bandwidth could range from lOKHz to 200KHz. The AFIC 404 is an Analog Devices 6437 ™ (hereinafter, "6437") chip manufactured by Analog Devices. The 6437 is similar to the CODEC 307 of Figure 3. That is, the 6437 performs front end analog-to-digital (in the receive direction) and digital-to-analog (in the transmit direction) conversion. The 6437 also performs other signal processing tasks such as receive clock extraction. Connected to and associated with the AFIC 404 is a feedback loop 403 having a pair of 3dB non-inverting amplifiers. The pair of amplifiers results in 6dB of total gain which, for the AFIC 404, further amplifies signals on the analog data channel in the upstream direction. The data tx circuitry 208 and AFIC chip 210 of Figure 2 are shown in more detail in Figure 5. Referring to Figure 5, circuitry 208 comprises two stages: a passive high pass filter 501 and a driver 502. The passive high pass filter 501, similar to the passive high pass filter 402 of Figure 4, comprises only passive components in order to further save real estate and power consumption. In one embodiment, the high pass filter 501 is a 5 pole Chebychev filter having the low frequency zero located at 125 kHz. Thus, the high pass filter 501 sets the lower edge of the downstream analog data channel bandwidth slot. There is no upper frequency cutoff used in this embodiment. That is, unlike the receive circuitry 207 described above, a low pass filter is not cascaded with the high pass filter 501 to form a bandpass filter in the channel. In this embodiment, the downstream channel is assumed to be fully defined by the receiver circuitry in the home modem on the other end of the telephone wire. Thus, a high frequency cutoff is not necessary on the LIC's downstream data channel. Again, the passive high pass filter 501 could be replaced by a passive filter and the specific zeroes used here may be varied to 120kHz +/- 30kHz. The zero value may drop somewhat depending on the low pass cutoff of the data rx circuitry 207 (Figure 2). In one embodiment, the driver 502 includes non-inverting amplifiers having a closed loop gain of 20dB and is responsible for driving the twisted pair, referring briefly back to Figure 2. The driver 502 also introduces a real estate and power consumption savings as compared to other design choices. Specifically, most designs employ +/- 15v rails in this stage 502. However, this typically requires an additional power supply. In this embodiment, a negative supply (which is standard on most LICs) is tapped within circuitry 503 to produce a -l/2v supply reference. The -l/2v supply reference is used to center the DC bias of the differential channel at just before driver 502. This enables each driver to produce a +/-16v output swing (since the amplifiers are biased at ground and -32 volts) centered at -16v. This is comparable to the +/- 15v swing typically used at the driver stage in the prior art. Thus, the isolation transformer is driven without use of an additional supply. Figure 6 shows an architectural overview of an embodiment of an ADSL LIC that employs the circuitry referred to in Figures 2 through 5. Referring to Figure 6, the LIC has six ports: two ADSL ports 601a and 601b and four standard voice ports (POTS lines) 602a-d. Some of the circuitry discussed in relation to Figures 2 through 5 is located in ADSL front end block 603a and 603b. Since Figures 2 through 5 refer to a single port design, ADSL front end block 603b is a duplication of the circuitry within ADSL front end block 603a. The CODEC devices 606a-c employed in one embodiment support two voice ports. Thus, the CODEC function of both ADSL front end blocks 603a and 603b may be implemented with a single CODEC chip 606c. Each of the voice front end blocks 604a and 604b supports two voice ports (602a-602b and 602c-602d respectively) since the CODEC device used in each (606a and 606b, respectively) supports two voice ports. Each voice front end block 604a and 604b comprises two sets of circuitry similar to that shown back in Figure 3. Thus, the CODEC chips 606a-c and AFIC chips 605a and 605b support the analog/digital conversion of six total voice channels and two ADSL related data channels (each having an upstream and downstream channel). Voice traffic is coupled from CODECs 606a-c to voice logic block 623 through voice bus 615. In one embodiment, voice logic block 623 is responsible for managing the values within time division mutliplexing (TDM) slots associated with each port 601a-b and 602a-d transporting voice traffic. That is, voice traffic from a POTS line sent to the voice logic block 623 via CODECs 606a- c is converted into TDM format and then sent to higher levels of networking intelligence via buses 632 and 633, drivers 631 and 634, and buses 639 and 640. TDM slots destined for the POTS line arrive at voice logic block 623 via the same interface circuitry 639, 640, 631, 634, 632 and 633. The voice logic block 623 converts these TDM slots into the appropriate CODEC 606a-c input signals. In one embodiment, voice logic block 623 is implemented in a field programmable gate array (FPGA) but may also be implemented with other chip technologies such as ASICs. Random access memory (RAM) devices 624, 625 are used mostly to buffer the voice traffic in both directions. That is, RAM 624 queues traffic destined for the POTS line while RAM 625 queues traffic originating from the home. RAM 628, microprocessor 629 and ROM 630 comprise the system level circuitry associated with the LIC of Figure 6. Management software (such as diagnostics, traffic control or maintenance) is stored on RAM 628 and executed on microprocessor 629. In one embodiment, ROM 630 holds the management software, boot code and FPGA files. ADSL logic block 620 performs data link layer functions for the data channels associated with ports 601a-b having ADSL capability. Similar to the voice logic block 623, ADSL logic block 620 communicates both upstream and downstream data traffic to higher network intelligence levels via an interface that includes buses 641-642, drivers 635-637, and buses 636-638. The format the data is communicated in over interface buses 641-642 is application specific. For example, the data may be converted into ATM cells or some proprietary bus format. RAM chips 622 and 621 queue upstream and downstream traffic for the ADSL logic block 620. The ADSL chipset blocks 607a,b perform physical layer encoding/ decoding for the ADSL data channels for their corresponding ADSL ports 601a and 601b. ADSL chipset block 607b may be a duplicate of the circuitry within ADSL chipset block 607a. Note voice bus 615 is not a part of either ADSL chipset blocks 607a and 607b. In this embodiment, the ADSL chipset blocks 607a and 607b comprise two chips offered by Analog Devices™ (e.g., AD20MSP910 with DTIR 6435 and DME6436). The DME chip 610 performs physical layer modulation/ demodulation and the DTIR chip 609 wraps the raw data into /out of an ADSL frame. The control and digital signal processing support associated with DME chip 610 and DTIR chip 609 are well-known in the art and have not been shown to avoid obscuring the present invention. Whereas many alterations and modifications of the present invention will no doubt become apparent to a person of ordinary skill in the art after having read the foregoing description, it is to be understood that any particular embodiment shown and described by way of illustration is in no way intended to be considered limiting. Therefore, references to details of various embodiments are not intended to limit the scope of the claims which in themselves recite only those features regarded as essential to the invention.

Claims: CLAIMS What is claimed is: 1. An apparatus, comprising: a) a data analog channel having a wire connector and an upstream data channel; b) a transformer within the data analog channel, the transformer coupling the upstream data channel to the wire connector; and c) a bandpass filter within the upstream data channel. 2. The apparatus of claim 1 wherein the bandpass filter further comprises a surface mount component. 3. The apparatus of claim 2 wherein the surface mount component further comprises an operational amplifier. 4. The apparatus of claim 2 wherein the surface mount component further comprises a chip resistor. 5. The apparatus of claim 2 wherein the surface mount component further comprises a chip capacitor. 6. The apparatus of claim 1 wherein the bandpass filter further comprises an active filter. 7. The apparatus of claim 1 wherein the bandpass filter further comprises a passive filter. 8. The apparatus of claim 1 wherein the bandpass filter further comprises a low pass filter coupled to a high pass filter. 9. The apparatus of claim 8 wherein the low pass filter is active and the high pass filter is passive. 10. The apparatus of claim 1 wherein the bandpass of the bandpass filter is between 30 kHz and 130 kHz. 11. The apparatus of claim 1 wherein the data analog channel further comprises a downstream channel, the transformer coupling the downstream data channel to the wire connector. 12. The apparatus of claim 11 further comprising an echo cancellation circuit coupling the downstream channel output and the upstream channel input. 13. The apparatus of claim 11 wherein the downstream channel further comprises a high pass filter. 14. The apparatus of claim 13 wherein the downstream channel high pass filter is a passive filter. 15. The apparatus of claim 11 wherein the downstream channel further comprises a data driver. 16. The apparatus of claim 15 wherein the data driver is centered at -16 volts. 17. An apparatus, comprising: a) a voice analog channel having a wire connector, a CODEC chip and a low pass filter, the low pass filter coupling the CODEC chip to the wire connector; and b) a transformer, the transformer a component of the low pass filter. 18. The apparatus of claim 17 wherein the transformer further comprises 40 gauge wire windings. 19. The apparatus of claim 17 wherein the transformer further comprises a EFD15 package. 20. The apparatus of claim 17 wherein the transformer is a sector wound transformer. 21. The apparatus of claim 17 wherein the transformer has winding resistance values matched to within +/- 0.5% of one another. 22. The apparatus of claim 17 wherein the transformer has inductance of lOmH. 23. The apparatus of claim 17 wherein the transformer has very little mutual capacitance. 24. A method comprising: a) channeling voice and data signals to a first transformer and a second transformer; b) extracting the voice signals by filtering the data signals through the first transformer; and c) extracting the data signals by filtering the voice signals through the second transformer and then a band pass filter. 25. The method of claim 27 further comprising transmitting downstream data signals through the second transformer. 26. The method of claim 28 wherein the downstream data signals are within a slot bandwidth of 130kHz and 1200kHz. 27. The method of claim 27 wherein the upstream voice signals are within a slot bandwidth of .03 and 4.0 kHz. 28. The method of claim 27 wherein the upstream data signals are within a slot bandwidth of 30kHz and 130kHz.

Inventors: LEWIS RICHARD KEITH, LEWIS, RICHARD, KEITH
Applicants: ADVANCED FIBRE COMM, ADVANCED FIBRE COMMUNICATIONS
Application year: 2000
Main classification: H04J1
IPC codes: H04L5, H04L27, H04M11