IMPROVED OPERATIONAL AMPLIFIER OUTPUT STAGE

Abstract: The present invention is directed to a buffer stage for buffering and isolating a signal source from an external load. The stage has a signal input terminal for receiving an input signal from said signal source and a signal output terminal for providing an output signal (OUTPUT), corresponding to said input signal (INPUT), to said external load. The stage comprises: an input section (102) including at least two driver transistors (Q3 and Q4) each arranged so as to operate with a predetermined bias current; an output section (106) including at least two output transistors (Q1 and Q2) each arranged so as to operate with a predetermined quiescent current a voltage source, coupled to the input and output sections and constructed and arranged so as to set the quiescent currents flowing through the output transistors (Q1 and Q2) substantially independent of the size of the bias current flowing through the driver transistors (Q3 and Q4).

Description: IMPROVED OPERATIONAL AMPLIFIER OUTPUT STAGE FIELD OF THE INVENTION The present invention relates to an apparatus for and method of buffering and isolating a signal source from an external load, and more particularly to an apparatus for and method of buffering and isolating a signal source from an external load such that the buffering and isolation characteristics are substantially independent of internal bias current source fluctuations, and a voltage source for use therein. BACKGROUND OF THE INVENTION In general, the performance of a signal source is dependent upon the characteristics of the external load connected to the output of the signal source. When the external load is known to exhibit variable characteristics, it is often desirable to place a buffer between the output of the signal source and the external load. Such a buffer isolates the signal source from the external load and provides a constant, intermediate load, thus ensuring consistent signal source performance. A buffer also may provide superior drive capability relative to the signal source output. Amplifiers and operational amplifiers are examples of a load dependent signal source. An amplifier or operational amplifier is used to amplify a received signal and apply the amplified signal to an external load. An amplifier or operational amplifier typically includes two or more distinct blocks or stages connected in series. One embodiment of an operational amplifier, shown in FIG. 1, has n gain blocks and one output stage, where n is an integer greater than or equal to one. There are numerous output stage topologies and classes known in the art. A number of the more common output stage topologies are described herein. In general, a circuit designer seeks to minimize a silicon die size because a smaller die size has better production yields and results in physically smaller end products. Thus, the total area necessary to implement an output stage in silicon is a significant consideration when choosing a particular topology. Therefore, in order to measure each topology, a fair criterion is to compare the relative sizes of certain output stage topologies. Accordingly, in discussing the relative sizes in the following examples, the minimum transistor geometry of a transistor (which is usually defined by the area of its emitter) used in the output stages is defined as having a unit area of lx. It is also assumed that the maximum required output current of the output stage is 16 mA. One output stage topology includes the complementary emitter follower, which uses an NPN transistor and a PNP transistor to drive the load connected to the OUTPUT node, and is shown in FIG. 2. For this example, the output transistors Ql and Q2 are assumed to each have an area of 8x (eight times the area of the minimum geometry transistor), the minimum size of each of the input transistor Q3 and current source II is lx, and the maximum required output current is 16 mA. The maximum base current of transistor Ql determines the amount of current required from the current source II . In this example, BQl MAX where β is the transistor current gain. Typically, the minimum β at a collector current of 16 mA is around 40. The quiescent current through transistors Ql and Q2 is preferably on the order of a few hundred μA so as to minimize crossover distortion, thus the quiescent current is similar in magnitude to the bias current (II) provided by the bias current source II. For simplicity, assume that the quiescent current is equal to the current II provided by the current source. A bias voltage source VI is connected between the bases of transistors Ql and Q2 to maintain the quiescent current. Obviously, a battery is not a realistic implementation of the voltage source VI. As seen in FIG. 3, one embodiment of the voltage source VI comprises two transistors Q4 and Q5, each connected as a diode and having the same emitter area as transistors Ql and Q2 so as to provide the necessary voltage of the voltage source VI of FIG. 3. However, the embodiment shown in FIG. 3 includes four large transistors (Ql = Q2 = Q4 = Q5 = 8x), an input transistor (Q3 = lx) and a current source (II = lx) for a total area of 34x. This arrangement therefore requires a relatively large silicon area to implement in IC form. In another embodiment of the output stage shown in FIG. 4, the voltage source VI is in the form of a V BE multiplier, the latter occupying less area than that of transistors Q4 and Q5 shown in the FIG. 3 embodiment. Two common implementations of a N BE multiplier are shown in FIG. 4 A and 4B. The silicon area occupied by transistors and current sources for FIGs. 4A and 4B is 19x and 20x, respectively, which is a significant reduction as compared to the FIG. 3 embodiment. However, the Nl embodiments shown in FIG 4 A and 4B include resistors Rl and R2 that are in the tens of kΩ range, implementation of which will require from 6x to 12x of silicon area. A disadvantage common to all of the output stage embodiments shown in FIGs. 2 through 4 is that a zero volt output of the stage, which is the normal idle state of an operational amplifier without an input signal, corresponds to approximately -1.3V input voltage relative to the output voltage. This is necessary in order to properly bias transistors Q2 and Q3. The negative voltage excursion at the output is thus limited to -(|V-| - 1.3V), where V- is the voltage applied to the negative rail. FIG. 5 illustrates yet another common embodiment of an output stage circuit, which overcomes the output voltage swing limitation of the embodiments shown in FIGs. 2 through 4. However, the embodiment of FIG. 5 overcomes the output voltage swing limitation at the expense of more silicon area (34x) because all of the transistors must be the same size. Also, the embodiment of FIG. 5 requires an additional current source 12, matching current source II, in the emitter of transistor Q4. The 34x silicon area of the circuit in FIG. 5 can be reduced to 28x by using Darlington transistor pairs. FIG. 6 shows such a topology where the transistor Ql - Q4 Darlington pair replaces the transistor Ql of FIG. 5, and the transistor Q2 - Q3 Darlington pair replaces the transistor Q2 of FIG. 5. Moreover, the current sources 13 and 14 may already exist within the host operational amplifier, and the output stage could be further reduced to 26x silicon area. A variation of the circuit in FIG. 6, shown in FIG. 7, adds two resistors in the collectors of transistors Q7 and Q8, forming two "peaking" current sources, as they are known in the art. The quiescent current of the output stage of the embodiment of FIG. 7, i.e., the collector current of transistors Ql and Q2, is less dependent on the matching and/or precision of current sources II , 12, 13 and 14. The values of resistors Rl and R2 are usually small, consequently the silicon area needed is also small. Since both peaking current sources are in series, however, Rl and R2 have to match relatively well. The Darlington transistor configurations within the embodiments shown in FIGs. 6 and 7 have the advantage of adding a third level of buffering, as compared to FIG. 5, which provides only two levels of buffering. This third level of buffering adds significant isolation between the amplifier and the external load. However, the embodiments of FIGs. 6 and 7 gain the additional isolation at the expense of the maximum voltage swing available at the output of the buffer. While the output of the circuit shown in FIG. 5 exhibits a voltage swing of +/- (|V supp ι y | - 0.85V), the output voltage of the circuit in FIG. 6 can swing only +/- (|V supply | - 1.5 V), where -V supp i y l = |V+| = |V-| . The output of the circuit in FIG. 7 can swing even less because of the extra voltage drop across resistors Rl and R2. SUMMARY OF THE INVENTION The present invention is directed to an apparatus for buffering and isolating a signal source from an external load. The apparatus is in the form of an output stage performing in a similar manner to the prior art device shown in FIG. 5, but using less area. In accordance with one aspect of the invention, a buffer stage is provided for buffering and isolating a signal source from an external load. The stage has a signal input terminal for receiving an input signal from said signal source and a signal output terminal for providing an output signal, corresponding to said input signal, to said external load, comprising: an input section including at least two driver transistors each arranged so as to operate with a predetermined bias current; an output section including at least two output transistors each arranged so as to operate with a predetermined quiescent current; and a voltage source, coupled to the input and output sections and constructed and arranged so as to set the quiescent currents flowing through the output transistors substantially independent of the size of the bias current flowing through the driver transistors. In one embodiment, adjusting the voltage provided by the voltage source causes the bias currents through the two driver transistors to be split at different ratios between one path including the voltage source and one driver transistor, and a second path including the voltage source and the other driver transistor. In one embodiment, the quiescent current through the output transistors is substantially independent of the size of the emitter area of each of the driver transistors so long as the emitter area of each of the driver transistors is smaller than the emitter area of each of the output transistors. In one embodiment, in operation the sum of the output transistor base-emitter voltages is equal to the sum of the driver transistor base-emitter voltages. And in one embodiment, the difference current between the bias current and the collector current of each of the driver transistors flows through the voltage source. In one embodiment, the bases of the driver transistors are connected together and form the input of the buffer stage. In one embodiment, the emitters of the output transistors are connected together and form the output of the buffer stage. In one embodiment the stage further includes a current source for providing the bias current through each of the driver transistors. In one embodiment, the emitter of each of the of the driver transistors is coupled to a current source so that at least some of the bias current flows through the driver transistors. In one embodiment, the voltage source is connected between the emitters of the driver transistors, and between the bases of the output transistors. In one embodiment, the output transistors are of an opposite conductivity type. In one embodiment, the voltage source includes two voltage source transistors of an opposite conductivity type, and a resistor connected between the collector of one voltage source transistor and the base of the other voltage source transistor, and between the collector of the other voltage source transistor and the base of the one voltage source transistor. In one embodiment, the bias currents through the driver transistors are equal. In accordance with another aspect of the invention, all of the currents of an output stage are largely independent of bias current sources and are controlled from one source, i.e., a voltage source. In one preferred embodiment the voltage source is controlled by a single resistive element, and ultimately all of the currents in the output stage are controlled by the same resistive element. In one preferred embodiment, the voltage source for providing all of the currents is a two terminal device having one terminal connected between the output of one driver transistor and the input of one output transistor, and the other terminal connected between the output of a second driver transistor and the input of a second output transistor. In accordance with another aspect, the apparatus includes a signal input terminal for receiving an input signal from the signal source, and a signal output terminal for providing an output signal, corresponding to the input signal, to the external load. The apparatus comprises two current sources, two driver transistors, two output transistors and a control voltage source. The first current source simultaneously provides an emitter current to the first driver transistor and a bias current to the first output transistor. The second current source simultaneously receives an emitter current from the second driver transistor and a bias current from the second output transistor. The input signal provides bias to both the first driver transistor and the second driver transistor. The output terminal is electrically coupled to both the emitter of the first output transistor and the emitter of the second output transistor. The control voltage source is electrically coupled between the emitter of the first driver transistor and the emitter of the second drive transistor. The current through the control voltage source varies as a predetermined function of the control voltage, such that the quiescent collector currents of the output transistors remain substantially constant regardless of any parametric variations exhibited by the input current sources and/or the driver transistors. In accordance with one preferred embodiment of the invention, the first driver transistor includes a PNP type transistor, the second driver transistor includes an NPN type transistor, the first output transistor includes an NPN type transistor, and the second output transistor includes a PNP type transistor. In another embodiment of the invention, a supply voltage source is electrically coupled between the collector of the first output transistor and the collector of the second output transistor. In another embodiment, the predetermined function includes a substantially exponential relationship. In yet another embodiment, the control voltage source includes a resistor, a PNP type transistor, and an NPN type transistor. In this embodiment, the resistor is electrically coupled between the collector of the PNP type transistor and the collector of the NPN type transistor. The base of the PNP type transistor is electrically coupled to the collector of the NPN type transistor, the base of the NPN transistor is electrically coupled to the collector of the PNP type transistor, the emitter of the PNP type transistor is electrically coupled to the emitter of the first driver transistor, and the emitter of the NPN type transistor is electrically coupled to the emitter of the second drive transistor. BRIEF DESCRIPTION OF THE DRAWINGS The foregoing and other objects of this invention, the various features thereof, as well as the invention itself, may be more fully understood from the following description, when read together with the accompanying drawings in which: FIG. 1 illustrates a schematic view of a typical prior art operational amplifier; FIG. 2 illustrates a schematic view of a prior art complementary emitter follower output stage architecture; FIG. 3 illustrates a schematic view of a prior art output stage architecture having a common two transistor bias voltage source; FIG. 4A illustrates a schematic view of a prior art implementation of a V BE multiplier output stage architecture; FIG. 4B illustrates a schematic view of another prior art implementation of a V BE multiplier output stage architecture; FIG. 5 illustrates a schematic view of yet another common embodiment of a prior art output stage architecture; FIG. 6 shows a variation of the prior art output stage architecture shown in FIG. 5; FIG. 7 shows yet another variation of the prior art output stage architecture shown in FIG. 5; FIG. 8 illustrates a schematic view of an improved output stage architecture according to the present invention; FIG. 9 illustrates a schematic view of a preferred embodiment of the control voltage source 106 from FIG. 8; FIG. 10 shows a graphical representation of the voltage across the control voltage source of FIG. 9; FIG. 11 shows a graphical representation of the voltage error across the control voltage source of FIG. 9 when the current is varied by 50%; FIG. 12 shows the voltage error across the control voltage source of FIG. 9 when the current is varied by 100%; FIG. 13 illustrates a schematic view of the output stage of FIG. 8, modified to include the embodiment of the control voltage source of FIG. 9; FIG. 14 shows a graphical representation of the quiescent current through the output transistors of FIG. 13 as a function of the voltage source current; FIG. 15 shows a graphical representation of the quiescent current with respect to the bias current of the output transistors of FIG. 13; FIG. 16 plots the bias current source output, the control voltage source current and the current through the driver transistors against the bias current source output.; and FIG. 17 graphically illustrates the percent-error of the output transistor quiescent current with respect to the percent change in the current through the control voltage source. DETAILED DESCRIPTION OF THE INVENTION The present invention is directed to an improved output stage for providing isolation between a signal source and an external load. One preferred embodiment of an output stage 100, shown in schematic form in FIG. 8, includes an input section 102, an output section 104, and a control voltage source 106. The input section 102 receives an input signal from a signal source (not shown) and confrols the operation of the output section 104 as a function of this input signal. The output section 104 provides high current drive capability to an external load (not shown), and as will be evident hereinafter, the control voltage source 106 is a component common to the input section 102 and output section 104. In accordance with one aspect of the present invention, the control voltage source 106 fixes the base-emitter voltage sums in both the input section 102 and output section 104, and provides a common path for the current defined by the difference between the bias current and the collector current of the driver transistors Q3 and Q4 in the input section 102. The input section 102 includes a PNP bipolar transistor Q3 and an NPN bipolar transistor Q4, a first current source II and a second current source 12. The bases of transistors Q3 and Q4 are electrically coupled together, and are coupled to an input port 108 for receiving an input signal. The emitter of transistor Q3 is electrically coupled to the output of the first current source II, the collector of transistor Q3 is electrically coupled to a negative voltage rail, i.e., a first voltage supply source V-, and the input of the first current source is electrically coupled to a positive voltage rail, i.e., a second voltage supply source V+. The collector of fransistor Q4 is electrically coupled to the second voltage supply source V+, the emitter of transistor Q4 is electrically coupled to the input of the second current source 12, and the output of the second current source 12 is electrically coupled to the first voltage supply source V-. The output section 104 of the stage 100 includes an NPN bipolar transistor Ql and a PNP bipolar transistor Q2. The emitters of transistors Ql and Q2 are electrically coupled together and are electrically coupled to an output port 110 for providing an output signal to an external load. The collector of transistor Ql is electrically coupled to the second voltage supply source V+ and the collector of transistor Q2 is electrically coupled to the first voltage supply source V-. The base of transistor Ql is electrically coupled to the output of the first current source II and the emitter of transistor Q3. The base of transistor Q2 is electrically coupled to the input of the second current source 12 and the emitter of transistor Q4. The control voltage source 106 includes a positive terminal and a negative terminal. The positive terminal of source 106 is electrically coupled to the base of transistor Ql, the emitter of transistor Q3 and the output of the first current source II. The negative terminal of source 106 is electrically coupled to the base of transistor Q2, the emitter of transistor Q4 and the input of the second current source 12. In accordance with one aspect of the invention, the voltage VI across the control voltage source 106 is set such that the desired quiescent current flows through output transistors Ql and Q2. Adjusting voltage VI causes the bias currents II and 12 to be split at different ratios between the paths including transistor Q3 and source 106, and the paths including transistor Q4 and source 106, respectively. To a large and significant extent, all of the currents in the output stage 100 are independent of current sources II and 12, and can be controlled by the voltage VI across the control voltage source 106. Also, the current split between the paths including transistor Q3 and source 106, and the paths including transistor Q4 and source 106, can be controlled by changing the emitter area of each of the transistors Q3 and Q4. Changing the size of each of the transistors Q3 and Q4 and/or varying the current sources II and/or 12 does not affect the quiescent current through transistors Ql and Q2. This is a fundamental difference between the present invention and the prior art output stage shown in FIG. 5. Thus, in the FIG. 8 embodiment the emitter area of each of the driver transistors Q3 and Q4 is arbitrary and independent of the emitter area of each of the output transistors Q 1 and Q2, as long as the emitter area of each of the driver transistors Q3 and Q4 is smaller than the emitter area of each of the output transistors Ql and Q2, providing a significant degree of design freedom. If the emitter areas of the driver transistors Q3 and Q4 are smaller than the emitter areas of the output transistors Ql and Q2, the collector currents of Q3 and Q4 are less than the corresponding currents in the circuit shown in FIG. 5. The extra current flows through the control voltage source 106. Since emitter area translates directly to silicon area, the invention uses relatively less silicon area than that used to implement the prior art circuit shown in FIG. 5.. The following notation is used herein to describe the detailed operation of the output stage 100: I cl I c2 I c3; I--,, = collector current of transistor Ql, Q2, Q3 and Q4, respectively; I vl = current through voltage source VI; ISN = NPN transistor saturation current; ISP = PNP transistor saturation current; VT = thermal voltage, 25.9 mV; β = transistor current gain; x = emitter area of each of the driver transistors Q3 and Q4; and z = emitter area of each of the output transistors Ql and Q2. In general, the collector currents of all transistors Ql, Q2, Q3 and Q4 can be expressed as: where z is the emitter area of each of the transistors Ql and Q2, x is the emitter area of each of the transistors Q3 and Q4, and V τ is the thermal voltage defined as: V τ =— = 25.9mF@27°C. (6) 1 q The sum of the base-emitter voltages of the output transistors Ql and Q2 is equal to the voltage source Nl : V l = V BEl + V EB2 - ( ? > Equation (7) can be rewritten by substituting the base-emitter voltages of transistors Ql and Q2 from equations (2) and (3), as follows: The collector current of any transistor is equal to the product of its base current and its cuπent gain β. The cuπent gain factor varies from transistor to transistor and typically ranges from 40 to 300. The base currents of transistors Ql, Q2, Q3, and Q4 are consequently small relative to the corresponding collector currents, so to a first approximation, the base currents can be neglected. In this case, the collector currents of output transistors Ql and Q2 can be considered equal. Thus, the quiescent current I q may be defined as: The quiescent current is the DC idle current flowing through the output transistors (i.e., from collector to emitter of transistor Ql and from emitter to collector of transistor Q2) when no signal is applied at the input of the output stage 100. Substituting definition (9) into equation (8), the quiescent current can be calculated as: Equation (10) implies that the quiescent current is a function of the voltage source Nl and the output transistor size. Equation (10) also implies that the quiescent current is independent of the size of the driver transistors Q3 and Q4, and of the bias current sources II and 12. This independence provides a significant degree of design freedom; the driver transistor size and bias current sources can be selected independent of the output transistors quiescent current and size. The collector current of the driver transistors Q3 and Q4 can be calculated as a function of the bias control voltage source 106. The sum of the base-emitter voltages of transistors Q3 and Q4 is equal to VI as shown in equation (11). Vl = V EB3 + V BE4 <»> Equation (11) can be rewritten by substituting the base-emitter voltages of transistors Q3 and Q4 from equations (4) and (5), as follows: For most applications, the bias current sources II and 12 are equal. The case when the bias current sources are not equal is considered to be a second order effect and it is discussed in more detail hereinafter. The bias current I B may be defined as: If the base currents of all transistors are neglected, then the current through the voltage source 106 can be calculated as follows (refer to FIG. 8): / π =/2-/ c4 = / c4 (15) Comparing equations (14) and (15) shows that the collector current of transistor Q3 is equal to the collector current of transistor Q4. So, the currents I c3 and I- 4 can be calculated from equation (12) as follows: Dividing equation (10) by equation (16) provides the following relationship between the quiescent and collector cuπents: / / q - q - Z (17) 7 c3 7 c4 X Comparing equations (7) and (11) demonstrates that the sum of output transistor base-emitter voltages is equal to the sum of the driver transistor base-emitter voltages. Therefore, the ratio of the collector currents of the output transistors, Ql and Q2, to the collector cuπents of the driver transistors, Q3 and Q4, must be equal to the ratio of their respective emitter areas, which is expressed explicitly in equation (17). The same relationship between the quiescent current and the driver collector current exists in the circuit shown in FIG. 5. In the case of FIG. 5, the collector current of the driver transistors is equal to the current of the bias sources, II and 12. If the bias current sources II and 12 are equal, then I c3 = 1- 4 = I B . However, a change in the size of the driver transistor emitter area, "x", in the FIG. 5 circuit, would result in a change of the quiescent current I q . This happens because the bias current sources are connected only to the driver transistors. In the case of the FIG. 8 embodiment of the present invention, the same change to the size of the driver transistor emitter area would not modify the quiescent current I q . Instead, the collector currents of the driver transistors, I c3 and I^, change accordingly to equation (17). The "difference current" between the bias current and the collector current of the driver transistors flows through the voltage source 106. The current through the control voltage source 106 can be calculated by substituting equation (16) into equation (14), as follows: Vι As described above, the proper operation of the present invention depends upon the fact that the current I v) , that flows through the control voltage source 106, can vary. Thus, the control voltage source must be capable of maintaining a constant voltage Nl as the cuπent I V1 varies. FIG. 9 illustrates a schematic view of a prefeπed embodiment of the control voltage source 106 for use in the FIG. 8 embodiment. Transistors Q19, Q20 and resistor R form a voltage source producing a voltage VI between nodes A and B (referenced in both FIGs. 8 and 9) which can be controlled as a function of the value of resistor R. The voltage across nodes A and B is relatively constant for a wide range of currents flowing through the voltage source 106. In order to describe this embodiment of control voltage source 106, the following notations are used in addition to the notations used to describe the detailed operation of the output stage 100: NR = voltage across resistor R; IR = resistor cuπent; and e = natural logarithm base, e = 2.718. The voltage between nodes A and B, N (A . B) , can be calculated as follows: (19) V {A - B) V [EB) - V R + V [BE) } Q\ Equations (19) and (20) show that the base-emitter voltages add and the resistor voltage subtracts from the total value of N (A . B) , so if the collector cuπent increases, the base-emitter voltages go up as well. Almost all of the collector current flows through resistor R. When the collector cuπent increases, the voltage across resistor R increases as well. Since the resistor voltage is subtracted from the base-emitter voltages, they tend to cancel each other, which maintains the voltage across nodes A and B at a relatively constant value. In a more exact form, the collector and resistor currents can be defined as follows: where I is the current flowing into node A and exiting through node B. Substituting equations (21), (22) and (23) into equation (20), the voltage between nodes A and B becomes: As mentioned before, the base-emitter voltages and the resistor voltage tend to cancel; a particular cuπent exists for which the cancellation is perfect. This particular current can be calculated by equating the derivative of the voltage between nodes A and B, with respect to current, to zero. Substituting the expression (24) for N (A - B) mto equation (25), the following equation results: and solving (26) for the cuπent I provides: where I 0 is the nominal cuπent through the control voltage source for which the voltage cancellation is ideal. Substituting I 0 from equation (27) in equation (24), the voltage across nodes A and B, for which the cancellation is perfect, can be calculated as follows: Equation (28) can be simplified by noticing that the contribution of the last logarithmic term in parenthesis is very small. Assume that β is much greater than one (β » 1), and for the sake of example, β min = 10. For cuπents in the hundreds of μA, according to equation (27), resistor R is on the order of kΩ (10 3 ) or less. The order of magnitude of the transistor saturation cuπents, I SP(Ν) , is about 10 "16 . Using these numbers in equation (28), the first and last logarithmic terms in the parenthesis can be calculated. The first term is about 27 and the last one is about 0.1 . There is a difference of two orders of magnitude between the first and last logarithmic term. Therefore, the last logarithmic term can be ignored. Also, taking into account the properties of the logarithmic function, ln(e) = 1, equation (28) can be written as follows: The above equation demonstrates that the voltage between nodes A and B can be set by resistor R. Using the same approximation, i.e., neglecting the effect of the base cuπents, equation (24), that describes the dependence of the voltage across nodes A and B with respect to cuπent I, can be simplified as follows: FIG. 10 shows a plot of the voltage N (A - B) defined in equation (30). The voltage across the voltage source 106 is kept relatively constant when the current passing through it sweeps a relatively wide range. FIG. 11 and FIG. 12 show the eπor of the voltage across the voltage source 106 when the current is varied by 50% and by 100%, respectively. The circuit of FIG. 8, including the specific implementation of the voltage source of FIG. 9, is shown in FIG. 13. The control voltage source 106 is formed by transistors Q5, Q6 and resistor Rl . The emitter area of the voltage source transistors is defined as _y_ . Using the aforementioned notations and reference designators, the voltage across nodes A and B, as defined by equation (30), can be written as follows: Neglecting the base cuπents of transistors Q5 and Q6, the voltage across nodes A and B is substantially independent of the cuπent flowing through the voltage source, I V1 , when the cuπent has the following value: where 7°, is the nominal cuπent for which the voltage across nodes A and B is independent of cuπent I V1 . The voltage across nodes A and B, for which the sensitivity with respect to current I V1 is minimum, is calculated by substituting equation (32) into equation (31): The quiescent cuπent of the output transistors, Ql and Q2, is evaluated by substituting the voltage equation (31) into equation (10), as follows: The quiescent cuπent is a function of the cuπent flowing through the voltage source connected at nodes A and B. Current I V] , in the exponential function of equation (34), tends to decrease the value of the quiescent cuπent. The term I V1 multiplies the exponential function and tends to increase the value of the quiescent current. Thus, these two terms in equation (34) tend to cancel each other and maintain the quiescent current at a substantially constant value. The cuπent I q , as a function of I v „ has a maximum that can be calculated by substituting equation (32) into equation (34), as follows: FIG. 14 shows a plot of the quiescent cuπent as defined by equation (34). The resulting curve has a peak (i.e., a maximum value) that can be calculated using equation (35). Notice that while the cuπent through the voltage source sweeps a wide range, the quiescent cuπent is substantially constant, within 5%. For a meaningful comparison of the embodiment shown in FIG. 13 with the prior art circuit shown in FIG. 5, the quiescent cuπent I q can be plotted with respect to the bias current sources. The bias current source is the sum of the driver transistor collector cuπent and the current through the voltage source. In typical prior art designs, the bias cuπent sources II and 12 are equal or very close in value. Therefore, it is reasonable to assume that they are exactly equal. Under this assumption, the collector currents of the driver transistors are also equal. The relationship between the quiescent cuπent and the collector cuπents of the driver transistors is shown in equation (17). Substituting I q from equation (34) in equation (17), the collector current of driver transistor Q3 is calculated as follows: Substituting equation (38) in equation (36) results in the following equation: Equation (39) does not have an analytical solution for I V] . In order to plot the quiescent cuπent I q , versus bias cuπent I B , equation (39) is solved numerically first and then I V1 is substituted in equation (34) to finally calculate I q . In order to compare this prefeπed embodiment of FIG. 13 with the prior art of FIG. 5, the quiescent cuπent of the output transistors Ql and Q2 in FIG. 5 is also plotted in FIG. 15, which compares I q of the FIG. 5 circuit, indicated at 152 to the I q of the FIG 13 circuit, indicated at 154. In the case of the prefeπed embodiment (shown in FIG. 13), the quiescent cuπent remains substantially constant, while in the prior art circuit (shown in FIG. 5), the quiescent cuπent increases linearly with the bias cuπent. According to equation (17), the collector cuπents of the driver transistors are linearly proportional to the quiescent cuπent. Consequently, the collector cuπent of the driver transistors is fairly constant with respect to bias cuπent, and if the bias cuπent varies, the extra cuπent that flows through the control voltage source 106 (connected between nodes A and B) is linearly proportional to the bias cuπent. This dependence is shown in FIG. 16, which plots the bias cuπent source output 202, the control voltages source 204 and the cuπent through the driver transistors 206 against the bias cuπent source output. Since no analytical solution exists for the quiescent current as a function of the bias cuπent, the quiescent cuπent sensitivity with respect to bias cuπent can not be calculated. However, given the linear relationship between the bias cuπent and the cuπent through the voltage source, a good approximation can be made by calculating the quiescent current sensitivity with respect to the current through the voltage source. Substituting equation (34) into equation (40), the sensitivity is calculated as follows: The quiescent cuπent becomes independent of the cuπent through the voltage source when the sensitivity of I q with respect to I V1 equals zero. This happens when the current through the voltage source has the following value: Equation (42) is equivalent to equation (27). The same result was reached by solving the problem via two different approaches: i) minimize the dependence of the voltage across nodes A and B with respect to the cuπent flowing through the voltage source, and ii) minimize the quiescent current dependence with respect to bias cuπent source. Substituting equation (42) into equation (34) the nominal operating point for the output transistors is calculated, as indicated in equation (35). Substituting equations (35) and (42) into equation (34) , the quiescent cuπent has the following formula: Equation (43) is plotted in FIG. 17 in relative units. The x and y axes are defined as follows: Notice that, a change of +/- 30% in voltage source cuπent changes the quiescent cuπent only by 5% . Substituting equation (42) into equation (39), the bias cuπent is: The bias cuπent is usually determined by the maximum output current divided by the minimum cuπent gain factor of the output transistors. Thus, the resistor value of Rl can be calculated from equation (46) as follows: The bias current must be greater than, or equal to, the maximum base cuπent of the output transistors. Therefore, equation (46) can be written as: Solving equation (48) for transistor emitter area ratio results in: Notice from equation (35) that resistor Rl can be expressed as a function of the nominal quiescent cuπent as follows: Substituting equation (50) into equation (49) and solving for voltage source transistor emitter area, 'y', results in: The transistor area is preferably an integer. Thus, the emitter area of voltage source transistors is preferably rounded as follows (one was added because the integer function rounds down): Since the output transistor size is fixed, it is necessary to determine which is the most effective driver and voltage source transistor size. The total transistor area is: -4 tOt _. -2-{ \ x+ y s +z) t (53) Substituting equation (51) into equation (53), the total area can be calculated as a function of driver and output transistor size as follows: (54) According to equation (54), the minimum area is obtained when the driver transistor has the minimum size, lx. The transistor area necessary for the circuit in FIG. 5 is: ■ 2-(x+z) (55) FIG 5 Substituting equation (17) into equation (55), and noticing that in FIG. 5 the driver collector current is equal to the bias cuπent, equation (55) becomes: The area savings realized with the new output stage topology is: (57) sav FIG 5 min Substituting formulae (54) and (56) into equation (57), the area savings is as follows: The invention may be embodied in other specific forms without departing from the spirit or essential characteristics thereof. The present embodiments are therefore to be considered in respects as illustrative and not restrictive, the scope of the invention being indicated by the appended claims rather than by the foregoing description, and all changes which come within the meaning and range of the equivalency of the claims are therefore intended to be embraced therein.

Claims: What is claimed is 1. An apparatus for buffering and isolating a signal source from an external load, said apparatus having a signal input terminal for receiving an input signal from said signal source and a signal output terminal for providing an output signal, coπesponding to said input signal, to said external load, comprising: a first bias cuπent source providing a first emitter current to a first driver transistor and a first bias current to a first output transistor; a second bias cuπent source receiving a second emitter cuπent from a second driver transistor and a second bias cuπent from a second output fransistor, said input signal biasing said first driver transistor and said second driver transistor, and said output terminal being electrically coupled to an emitter of said first output transistor and to an emitter of said second output transistor; and, a control voltage source for providing a control voltage, electrically coupled between an emitter of said first driver transistor and an emitter of said second drive transistor, wherein said first bias cuπent and said second bias cuπent vary as a predetermined function of said control voltage. 2. An apparatus according to claim 1 , wherein said first driver transistor includes a PNP type transistor, said second driver transistor includes an NPN type transistor, said first output transistor includes an NPN type transistor, and said second output transistor includes a PNP type transistor. 3. An apparatus according to claim 1, further including a supply voltage source electrically coupled between a collector of said first output transistor and a collector of said second output transistor. 4. An apparatus according to claim 1, wherein said predetermined function includes a substantially exponential relationship. 5. An apparatus according to claim 1 , wherein a quiescent current through said first output transistor and a quiescent current through said second output transistor are substantially independent of said first current source and said second cuπent source. 6. An apparatus according to claim 1 , wherein said confrol voltage source includes a resistor, a PNP type transistor, and an NPN type transistor, said resistor being elecfrically coupled between a collector of said PNP type transistor and a collector of said NPN type transistor, a base of said PNP type transistor being electrically coupled to said collector of said NPN type transistor, a base of said NPN transistor being electrically coupled to said collector of said PNP type transistor, an emitter of said PNP type transistor being electrically coupled to said emitter of said first driver transistor, and an emitter of said NPN type transistor being electrically coupled to said emitter of said second drive transistor. 7. An apparatus for buffering and isolating a signal source from an external load, said apparatus having a signal input terminal for receiving an input signal from said signal source and a signal output terminal for providing an output signal to said external load, comprising: an output stage, including a first NPN type transistor having a first quiescent collector cuπent, and a first PNP type transistor having a second quiescent collector cuπent, a first NPN type transistor emitter being electrically coupled to a first PNP type transistor emitter, a first NPN type transistor collector being coupled to a first voltage supply source, and a first PNP type transistor collector being coupled to a second voltage supply source; an input stage, including; L a second PNP type transistor and a first cuπent source, a second PNP type transistor emitter being electrically coupled to a first cuπent source output terminal and to said first NPN type transistor base, a second PNP type transistor collector being electrically coupled to said second voltage supply source, a second PNP type transistor base being electrically coupled to said signal input terminal, and a first cuπent source input terminal being electrically coupled to a second voltage supply source; ii. a second NPN type transistor and a second current source, a second NPN type fransistor emitter being electrically coupled to said second cuπent source input terminal and to said first PNP type fransistor base, a second NPN type transistor collector being electrically coupled to said first voltage supply source, a second NPN type transistor base being electrically coupled to said signal input terminal, and a second cuπent source output terminal being electrically coupled to said second voltage supply source; and, a confrol voltage source for providing a control voltage, said control voltage source having a positive terminal and a negative terminal, said positive terminal being electrically coupled to said first NPN type transistor base and said negative terminal being electrically coupled to said first PNP type fransistor base, wherein said first quiescent collector cuπent and said second quiescent collector cuπent vary as a predetermined function of said control voltage. 8. An apparatus according to claim 7, wherein said predetermined function includes a substantially exponential relationship. 9. An apparatus according to claim 7, wherein said confrol voltage source includes a resistor, a third PNP type transistor, and a third NPN type transistor, said resistor being electrically coupled between a collector of said third PNP type fransistor and a collector of said third NPN type transistor, a base of said third PNP type fransistor being electrically coupled to said collector of said third NPN type transistor, a base of said third NPN transistor being electrically coupled to said collector of said third PNP type transistor, an emitter of said third PNP type fransistor being electrically coupled to said emitter of said first driver transistor, and an emitter of said third NPN type transistor being electrically coupled to said emitter of said second drive transistor. 10. A buffer stage for buffering and isolating a signal source from an external load, said stage having a signal input terminal for receiving an input signal from said signal source and a signal output terminal for providing an output signal, coπesponding to said input signal, to said external load, comprising: an input section including at least two driver transistors each arranged so as to operate with a predetermined bias cuπent; an output section including at least two output transistors each arranged so as to operate with a predetermined quiescent cuπent; and a voltage source, coupled to the input and output sections and constructed and arranged so as to set the quiescent currents flowing through the output fransistors substantially independent of the size of the bias cuπent flowing through the driver transistors. 11. A buffer stage according to claim 10, wherein adjusting the voltage provided by the voltage source causes the bias cuπents through the two driver transistors to be split at different ratios. 12. A buffer stage according to claim 10, wherein the quiescent cuπent through the output transistors is substantially independent of the size of the emitter area of each of the driver transistors so long as the emitter area of each of the driver transistors is smaller than the emitter area of each of the output transistors. 13. A buffer stage according to claim 10, wherein in operation the sum of the output fransistor base-emitter voltages is equal to the sum of the driver fransistor base-emitter voltages. 14. A buffer stage according to claim 10, wherein in operation the difference current between the bias current and the collector cuπent of each of the driver transistors flows through the voltage source. 15. A buffer stage according to claim 10, wherein the bases of the driver transistors are connected together and form the input of the buffer stage. 16. A buffer stage according to claim 10, wherein the emitters of the output transistors are connected together and form the output of the buffer stage. 17. A buffer stage according to claim 10, further including a current source for providing the bias cuπent through each of the driver transistors. 18. A buffer stage according to claim 10, wherein the emitter of each of the of the driver fransistors is coupled to a current source so that at least some of the bias cuπent flows through the driver fransistors. 19. A buffer stage according to claim 10 wherein the voltage source is connected between the emitters of the driver transistors, and between the bases of the output transistors. 20. A buffer stage according to claim 10, wherein the output fransistors are of an opposite conductivity type. 21. A buffer stage according to claim 10, wherein the voltage source includes two voltage source transistors of an opposite conductivity type, and a resistor connected between the collector of one voltage source transistor and the base of the other voltage source transistor, and between the collector of the other voltage source transistor and the base of the one voltage source transistor. 22. A buffer stage according to claim 10, wherein the bias currents through the driver transistors are equal.

Inventors: FLORU FRED, FLORU, FRED
Applicants: THAT CORP, THAT CORPORATION
Application year: 2000
Main classification: H03F3
IPC codes: H03F3