Driving method of semiconductor switching device and power supply apparatus operated according to said method

Abstract: A power supply apparatus includes a semiconductor switching device (Q2) for outputting power and a control circuit (CIC) for controlling the on/off operation of the semiconductor switching device. The control circuit (CIC) includes a circuit (OP4, COM4) for applying, when turning on the semiconductor switching device (Q2), a first control signal corresponding to the difference between the output voltage of the power supply apparatus (1) and a first reference value (forward voltage of a diode D6) to the semiconductor switching device (Q2) in accordance with the increase in the output voltage from the power supply apparatus (1) thereby to operate the semiconductor switching device (Q2) in a non-saturated area, so that the semiconductor switching device is turned on gradually.

Description: BACKGROUND OF THE INVENTION Field of the Invention The present invention relates to a method of driving a switching device of a power supply apparatus and the power supply apparatus driven by the method. Description of the Related Art Conventionally, in the case where a plurality of converters are operated in parallel redundancy, each converter is connected to a load through a diode for reverse-current protection. However, the diode has so high a forward voltage drop that power loss is large. As a measure against this, a semiconductor switching element such as MOSFET is used. In such a case, no problem would be posed if the MOSFET is turned on and connected in parallel to the converter added to the redundant system after the converter is fully activated and the voltage is established. In dynamic attachment and removal, however, the MOSFET is unavoidably turned on/off at a voltage lower than that of the redundant system, considering the voltage detection error of the principal converter. A large charge current instantaneously flows through the capacitor of the activated converter from the redundant system, resulting in a large variation in load voltage. Also in case the converter runs out of order when used with the MOSFET, the voltage across the converter gradually drops to such a level that the voltage across the faulty converter becomes lower than that across the redundant system, and the reverse current flows to the faulty converter through the MOSFET from the redundant system until the detection voltage for turning off the MOSFET is reached, thereby causing a large variation of the load voltage. In case the faulty power supply is replaced for activation or the power supply runs out of order, the current of the redundant system is disturbed and the load voltage undergoes a variation when the MOSFET is turned on as described above. Thus, noise is caused. JP 09 051678 A discloses a power supply apparatus with the features included in the first part of claim 4. The prior-art apparatus relates to a system with several converters connected in parallel. If one converter becomes faulty, the flow of current from another converter to a faulty converter is prevented. Similar apparatus are disclosed in US-A-5 428 523 and JP 05 161262 A. In accordance with the latter document, the semiconductor switching device is driven by pulses and a smooth start is provided at the start-up of the switching device. SUMMARY OF THE INVENTION The object of the invention is to provide a highly reliable method for driving a semiconductor switching device in a power supply apparatus at the time of preventing the reverse current, and a power supply apparatus driven by the method. This object is met by the method defined in claim 1 and the apparatus defined in claim 4. The semiconductor switching device is turned on not directly but gradually through a non-saturated state. The current is limited when the semiconductor switching device starts to be turned on, and therefore it is possible to prevent such an abrupt current increase as would cause a load variation. The reliability of the power supply apparatus is improved by using the driving method according to the invention in the control circuit for controlling the on/off operation of the semiconductor switching device for outputting the power of the power supply apparatus. Various types of semiconductor switching devices can be used, including an insulated gate transistor such as MOSFET (metal oxide semiconductor field effect transistor), an IGBT (insulated gate bipolar transistor), and a bipolar transistor. The semiconductor switching device is used for various purposes including the blocking of reverse current. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a circuit diagram according to an embodiment of the invention. Fig. 2 is a circuit diagram according to another embodiment of the invention. Fig. 3 is a circuit diagram according to still another embodiment of the invention. Fig. 4 is a circuit diagram according to a further embodiment of the invention. Fig. 5 is a circuit diagram according to a still further embodiment of the invention. Fig. 6 is a circuit diagram according to a yet further embodiment of the invention. Fig. 7 is a circuit diagram in which the invention is used for parallel operation of converters according to an embodiment. DESCRIPTION OF THE EMBODIMENTS A power supply apparatus according to an embodiment of the invention is shown in Fig. 1. This embodiment represents an internal configuration of a DC/DC convertor for parallel redundancy operation shown in Fig. 7. Fig. 7 shows an example of the parallel redundancy operation of three converters each connected to a load Lo through a reverse current blocking MOSFET Q. Further, each converter is connected to a terminal CL for controlling the current balance. In the basic configuration of the forward-type DC/DC converter 1 shown in Fig. 1, the primary winding of a transformer TF is impressed with a DC voltage Vi through a main switch Q1. The switching operation of the main switch Q1 is controlled by a control circuit CIC defined by dashed line on the secondary of the transformer TF. The secondary main circuit of the transformer includes diodes D1, D2 for rectification and smoothing, an inductance L1, a capacitor C1, a reverse current-blocking MOSFET Q2, a diode D3 (which may be a parasite diode for the MOSFET) and a current-detecting resistor Rcd. When the main switch Q1 is turned on/off by this circuit at a predetermined frequency, a voltage proportional to the duty factor which is the ratio of the turn-on time to the switching period is obtained on the secondary side of the transformer. This voltage is rectified by the diode D1 and used for charging the capacitor C1 through the inductance L1. When the main switch Q1 turns off and the primary voltage drops to zero, the secondary voltage changes to the reverse direction, and therefore the diode D1 turns off by being biased reversely. Thus, the energy that has been stored in the inductance L1 is released, so that the current continues to flow through the capacitor C1 and the diode D2. In this way, the voltage is rectified and smoothed, and the voltage across the capacitor becomes a DC voltage with a small ripple. The load Lo is driven by this voltage. Now, the reverse current-blocking operation of the control circuit CIC will be explained. The MOSFET Q2 and the diode D3 are connected in parallel to each other, and the parallel circuit is connected in series to a current-detecting resistor Rcd and further to the negative side of the output terminal of the converter 1. The two terminals of the current-detecting resistor Rcd are connected to an amplifier OP4. As shown, however, the ground GND side of the resistor Rcd is connected to the positive input terminal of the amplifier OP4, and the other side is connected to the negative input terminal of the amplifier OP4 through a resistor R9. A resistor R8 is inserted between the negative input terminal and the output terminal of the amplifier OP4 thereby to constitute an amplifier having a gain of R8/R9. Further, the positive input terminal of a comparator COM4 is connected to the output terminal of the amplifier OP4, and the negative input terminal of the comparator COM4 is connected to a reference voltage E4. The outputs of the amplifier OP4 and the comparator COM4 are connected to the gate of the MOSFET Q2 through diodes D6 and D7, respectively. When the converter 1 is activated in this configuration, the MOSFET Q2 remains off while the output voltage of the converter 1 is lower than the voltage Vo of the load being driven by the converter 1 of the other redundant system. Thus, the charge current for the capacitor C1 from the other redundant system is blocked by the diode D3. When the voltage across the converter 1 increases to the voltage Vo of the load or more with the progress of the activation, the diode D3 is biased in forward direction and the current begins to flow. This current is amplified by the amplifier OP4. When the output voltage of the amplifier OP4 increases to the forward voltage of the diode D6 constituting a first reference value, the output voltage of the amplifier OP4 increases in proportion to the magnitude of the resultant current. The output voltage of the amplifier OP4 makes up the first control signal (gate signal) for the MOSFET Q2, and the gate voltage of the MOSFET Q2 is increased. As a result, the MOSFET Q2 gradually begins to conduct while the MOSFET Q2 remains non-saturated, and the current gradually begins to transfer from the diode D3 to the MOSFET Q2. Thus, the forward voltage of the diode D3 occurs. When the activation current of the converter is further increased to such an extent that the output voltage of the amplifier OP4 reaches the second reference value E4, the output of the comparator COM4 turns on. This output signal is applied as a second control signal (gate signal) to the MOSFET Q2. The output of the comparator COM4 is set to a magnitude not smaller than the first control signal, and therefore the MOSFET Q2 is turned on to a sufficient degree. At the same time, the MOSFET Q2 operates in the saturated area, and the current transfers sufficiently from the diode D3 to the MOSFET Q2 thereby completing the activation. The aforementioned reverse current-blocking operation of the control circuit CIC limits the current when the MOSFET Q2 starts to turn on at the time of activating the converter 1, and therefore the current is prevented from being increased so abruptly as to cause a load variation. These effects are achieved also in the case where the MOSFET Q2 operates in an area slightly displaced from the non-saturated or saturated area under the control of the first and second control signals. A voltage control system for controlling the output voltage at a constant level is also required. In a configuration of this system, the resistors R1 and R2 are connected to the terminals of the capacitor C1 in order to detect the output voltage and a detection voltage Vd is obtained from the middle point thereof. This voltage is compared with a reference voltage Er in an adder Ad, and in the case where the detection voltage Vd is lower than the reference voltage Er, an error voltage proportional to the difference is input to a PWM converter PWM which outputs a pulse voltage with a duty factor increased in accordance with the error voltage. This output is applied through insulating means such as a photocoupler Phc as a control signal to the main switch Q1 on the primary side of the transformer TF thereby to drive the same switch Q1. In this way, the converter 1 is controlled so that the output voltage is increased and the reference voltage Er coincides with the detection voltage Vd. As a result, the output voltage Vo can be controlled to the desired value. The first reference value, though fixed as a voltage across the diode D6 in the case under consideration, may be rendered adjustable using an adjustable source voltage. Also, the second reference value E4 may of course be rendered adjustable using an adjustable voltage source. Further, in order to control the current balance for the parallel redundancy operation, the output of the current amplifier OP4 is connected to the positive input terminal of the amplifier OP2 and the negative input terminal of the amplifier OP3 through the resistor R10. The output of the amplifier OP2 is connected to the negative input terminal, the positive input terminal of the amplifier OP3 and the current control line terminal CL through the diode D5. The output of the amplifier OP3 is connected to the positive input terminal of the adder Ad and the resistor R11. The positive input terminal of the adder Ad is connected to the reference voltage Er, and the other negative input terminal of the adder Ad is impressed with the voltage (substantially equal to the output voltage) across the capacitor C1 of the converter 1, divided by the resistors R1 and R2. The output of the adder Ad is connected through a PWM converter PWM and a photocoupler Phc to the gate of the main switch Q1 of the converter 1. Among the converters performing the redundancy operation with this configuration, the output current value of the converter 1 producing the maximum current is obtained from the current control line terminal CL. The value of this current is compared with the current value of the principal converter 1 in the amplifier OP2, and the larger one of the currents is output to the current control line terminal CL. Therefore, the maximum current in the converters operating in parallel always exists at the current control line terminal CL. The amplifier OP3 also amplifies the difference between the current value of the principal converter 1 and the maximum current value with the gain of R11/R10, and the error output is added to the reference value Er in the adder Ad. Assuming that the current of the principal converter 1 is smaller than the maximum value, the output of the amplifier OP3 increases and so does the output of the adder Ad. Thus, the duty factor of the output of the PWM converter PWM increases, with the result that the voltage of the principal converter slightly increases for an increased current share of the principal converter 1. This method of balancing the current between the converters is called the maximum current following control for the present purpose. Now, the overcurrent protection function will be explained. The negative input of the comparator COM1 is connected to a reference voltage E3, and the positive input thereof is connected to the output of the amplifier OP4 which is the current value of the converter 1. The output of the comparator COM1 is connected through a holding circuit Hj to the PWM converter PWM. As long as the current of the converter 1 is small, the output of the comparator COM1 is at low (L) level and so is the output of the holding circuit Hj. The PWM converter, therefore, operates in accordance with the output of the adder Ad. Once the current increases abnormally for some reason to a value not less than the reference voltage E3 which is an overcurrent reference value, however, the output of the comparator COM1 becomes high (L). The output of the holding circuit Hj is also maintained at H level, so that the output of the PWM converter PWM is stopped thereby continuing to turn off the main switch Q1. The circuit is reset by a restoration switch, not shown, of the holding circuit Hj. The circuit of this configuration can also be controlled in such a manner that the MOSFET Q2 is turned on consciously to pass through the non-saturated area for a longer time after detection that the current has begun to flow in the principal converter 1, while the MOSFET Q2 is turned off so that the non-saturated area is passed for a shorter time than when the MOSFET Q2 is on, upon detection that the current of the principal converter 1 has flowed in the direction reverse to the case where the current is supplied to the load. The circuit of Fig. 1 operates as described above, and therefore can be restored to the redundant system automatically even in the case of dynamic attachment and removal during the parallel redundancy operation, thereby making it possible to reduce the voltage variation of the redundant system. Further, as shown, in the case where the MOSFET Q2 and the current-detecting resistor Rcd are arranged on the negative side of the output of the converter 1, the control circuit CIC defined by the dashed line remains at low voltage except for the photocoupler and therefore there is no need of insulation for current detection, thereby leading to the advantage that a monolithic IC can be easily produced. Also, in view of the fact that the control circuit CIC is arranged on the negative voltage side on the secondary of the transformer and therefore only the signal for driving the main switch Q1 is sufficiently insulated, the use of the photocoupler can minimize the effect of noises and can configure a simple, inexpensive circuit. Another embodiment will be explained with reference to Fig. 2. This embodiment is different from the embodiment of Fig. 1 in that the current is detected by the MOSFET. The control circuit CIC is similar to that shown in Fig. 1, and therefore Fig. 2 primarily shows the control circuit for the reverse current-blocking MOSFET, but the remaining circuit portions are not shown. The component parts designated by the reference numerals of the corresponding parts in Fig. 1 operate the same way, respectively. The MOSFET Q2 is configured with the MOSFETs Q2, Q2s having the current detection function. The MOSFET Q2s is similar in form to and smaller several tens of times than the MOSFET Q2. The current of the MOSFET Q2s is proportional to and smaller than that of the MOSFET Q2 by several tens of times. These devices are connected in parallel as shown. Specifically, they are arranged in the same semiconductor chip. The source of the MOSFET Q2s for current detection is connected to a terminal of the current-detecting resistor Rcd, and the other terminal of the resistor Rcd is connected to the source of the MOSFET Q2. A terminal of the current-detecting Rcd connected to the MOSFET Q2s is connected to the negative input of the amplifier OP4 through the resistor R9. The other terminal of the resistor Rcd and the positive input of the amplifier OP4 are connected to the ground. The output of the amplifier OP4 is connected to the anode of the diode D6 and the positive input terminals of the comparator COM4 and the COM1. The cathode of the diode D6, on the other hand, is connected to the gates of the MOSFETs Q2, Q2s, and the negative inputs of the comparators COM4, COM1 are connected to the reference voltages E4, E3, respectively. The operation of this embodiment is similar to that of the embodiment shown in Fig. 1. Specifically, the voltage is low and the diodes D3, D3s are reversely biased so that no current flows at the time of activation of the converter 1. When the voltage increases near to the load voltage Vo of the redundant system, the current begins to flow through the diodes D3, D3s. This current is detected by the resistor Rcd and amplified by the amplifier OP4. When this current is amplified by the amplifier OP4 in the same manner as in Fig. 1 and the output voltage of the amplifier OP4 increases to the forward voltage of the diode D6 providing the first reference value, the output voltage of the amplifier OP4 increases in accordance with the magnitude of the same current. As a result, the gate voltages of the MOSFETs Q2, Q2s increase. Thus, the MOSFETs Q2, Q2s gradually begin to conduct in non-saturated state, so that the current gradually begins to transfer from the diodes D3, D3s to the MOSFETs Q2, Q2s, and the forward voltage of the diodes D3, D3s also drop. When the current of the converter 1 at the time of activation is further increased and the output voltage of the amplifier OP4 reaches the second reference value E4, the output of the comparator COM4 is turned on, so that the MOSFETs Q2, Q2s are turned on sufficiently. Thus the current sufficiently transfers from the diodes D3, D3s to the MOSFETs Q2, Q2s thereby to complete the activation. When the current decreases, the output of the amplifier OP4 also decreases and the MOSFETs Q2, Q2s turn off. In the case where the reverse current flows for some reason, however, the protection circuit is turned on. According to this embodiment, the circuit configuration is simplified and resistant to noises if the control circuit CIC shown in Fig. 1 which may be configured with a single chip has built therein the MOSFETs Q2, Q2s. Still another embodiment is shown in Fig. 3. This example is for determining the control of the reverse current blocking from the voltage of the principal converter. The same reference numerals as those in Fig. 1 designate the same component parts operating the same way as the corresponding parts, respectively, in Fig. 1. The voltage control, the current balance control and the overcurrent protection functions, therefore, are the same as those shown in Fig. 1. In the control operation for the reverse current blocking, the voltage of the principal converter divided by the resistors R1, R2 is obtained from the junction point of the resistors R1, R2. The junction point of the resistors R1, R2 is connected to the positive input terminal of the amplifier OP1 through the resistor R3, and further to the output of the comparator COM2 through the diode D4. The negative input of the amplifier OP1 is connected through the resistor R4 to the reference voltage E1 on the one hand and to the output of the amplifier OP1 through the resistor R5 on the other hand. In the case where the voltage of the principal converter 1 divided by the resistors R1, R2 is not higher than the first reference value E1, the output of the amplifier OP1 is not higher than zero and the MOSFET Q2 is maintained in off state. Once the divided voltage of the principal converter 1 reaches the reference value E1 or higher, however, the output of the amplifier OP1 changes to positive direction, and the MOSFET Q2 turns on non-saturated in accordance with the output of the amplifier OP1. With the increase in the divided voltage of the principal converter 1, the MOSFET Q2 approaches the saturation, and when the divided voltage of the principal converter 1 reaches not less than the second reference value determined by the MOSFET Q2, turns on to the full. The current first flows in a greater amount in the diode D3 followed by gradual, smooth transfer to the MOSFET Q2. At a certain time, the current flows in the MOSFET Q2 for the most part. In the case where the reverse current flows in the MOSFET Q2 for some reason, the reverse current is detected by the comparator COM2 through the current detecting resistor Rcd, and the MOSFET Q2 is turned off to prevent the reverse current by shorting the positive input of the amplifier OP1 using the output of the comparator COM2 through the diode D4. Fig. 4 shows an example of the reverse current-blocking MOSFET Q2 arranged on the positive side of the output of the converter 1 according to still another embodiment. The reference numerals identical to those in Fig. 3 designate the component parts operating the same way as the corresponding parts in Fig. 3, respectively. This configuration is different from that of Fig. 3 in the provision of the comparator COM3 for comparing the voltage with the second reference value E2 for reverse current prevention control in addition to the provision of the reverse current-blocking MOSFET described above. The junction point of the resistors R1, R2 is connected to the positive input of the amplifier OP1 and the positive input of the comparator COM3 through the resistor R3. The negative input of the comparator COM3 is connected to the reference value E2 through the resistor R12 on the one hand and to the output of the comparator COM3 through the resistor R13 on the other hand. The outputs of the comparator COM3 and the amplifier OP1 are connected to the gate of the MOSFET Q2 through the diodes D7, D6, respectively. In the embodiment shown in Fig. 4, in the case where the divided voltage of the principal converter 1 is not higher than the first reference value E1, the output of the amplifier OP1 is not higher than zero, so that the MOSFET Q2 is maintained in off state. Once the divided voltage of the principal converter 1 reaches the reference value E1 or higher, the output of the amplifier OP1 turns positive in direction so that the MOSFET Q2 turns on in non-saturated state in accordance with the output of the amplifier OP1. With the increase in the divided voltage of the principal converter 1, the MOSFET Q2 approaches the on state in saturation. When the divided voltage of the principal converter further increases to the second reference value E2 or higher, the output of the comparator COM3 turns high and the MOSFET Q2 turns on to the full. According to this embodiment, the output current is detected by a current sensor CD. Also, the operation and other points with a reverse current flow are the same as those in Fig. 3. This embodiment is applicable to an ordinary converter configuration. Fig. 5 shows a further embodiment in which the reverse current-blocking MOSFET Q2 is arranged on the positive side of the output of the converter 1 and the smoothing inductance L is arranged on the negative side of the output of the converter 1. The same reference numerals as the corresponding ones in Figs. 3 and 4 designate the same component parts, respectively, performing the control operation in the same way as in Figs. 3 and 4. As a configuration for current balance control, the amplifier OP3 is omitted and doubled by the amplifier OP2 and the output of the amplifier OP2 is applied as a negative input to the adder Ad. The operation of blocking the reverse current flow according to this embodiment is similar to that of the embodiment shown in Fig. 3. Specifically, as long as the voltage of the principal converter 1 divided by the resistors R1, R2 is not higher than the first reference value E1, the output of the amplifier OP1 is not higher than zero and the MOSFET Q2 is maintained in off state. Once the divided voltage of the principal converter 1 reaches the first reference value E1 or higher, on the other hand, the output of the amplifier OP1 turns positive in direction, and the MOSFET Q2 is turned on in non-saturated state in accordance with the output of the amplifier OP1. With the increase in the divided voltage of the principal converter 1, the MOSFET Q2 approaches the on state in saturation, and is turned on to the full when the divided voltage of the principal converter 1 reaches the second reference value determined by the MOSFET Q2. The current first flows in a greater proportion in the diode D3 and smoothly transfers to the MOSFET Q2, and at a predetermined point, most of the current begins to flow to the MOSFET Q2. In the case where the reverse current flows in the MOSFET Q2 for some reason, the reverse current is detected by the comparator COM2 through the current detecting resistor Rcd and blocked by turning off the MOSFET Q2 by shorting the positive input of the amplifier OP1 using the output of the comparator COM2 through the diode D4. According to the embodiment of Fig. 5, in the case where the current flowing in the principal converter 1 is smaller than the maximum value for parallel operation, the output of the amplifier OP2 is decreased, and a less value is subtracted from the reference value Er in the adder Ad. As a result, the input to the PWM converter PWM increases and so does the duty factor of the PWM converter PWM. Thus, the voltage of the principal converter 1 slightly increases for an increased current into a balanced state. Also, the overcurrent protection circuit drives the transistor T1 through the holding circuit Mc and the resistor R1 by the output of the comparator COM and turns off by shorting the gate of the MOSFET Q1 of the main switching device thereby to block the overcurrent. As a result, the circuit is reduced in size and the reliability is improved by the distribution of the protection circuit. Fig. 6 shows a yet further embodiment in which both the reverse current-blocking MOSFET Q2 and the smoothing inductance L are arranged on the negative side. In Figs. 3, 4 and 5, the same reference numerals designate the same component parts operating the same way, respectively. Thus, the operation of blocking the reverse current is also the same. Fig. 7 shows a parallel redundancy power supply driven by the driving method according to an embodiment of the invention. Three DC/DC converters are operated in parallel redundancy. Each DC/DC converter connects a load by connecting the reverse current-blocking MOSFET Q on the load side of the smoothing capacitor C. The MOSFET Q is controlled by the control circuit and the driving method explained with reference to Figs. 1 to 6. In Fig. 7, the control circuit is not shown. Further, in each converter 1, the current is controlled by connecting the current balance control according to the maximum current following method with the current control line CL.

Claims: A method for driving a semiconductor switching device ( Q2 ) of a power supply apparatus ( 1 ) for outputting power through said semiconductor switching device ( Q2 ), characterised by applying to said semiconductor switching device ( Q2 ) a first control signal (from Q4; OP1 ) corresponding to the difference between the output voltage or output current of said power supply apparatus ( 1 ) and a first reference value (forward voltage of diode D6; E1 ) for operating said semiconductor switching device ( Q2 ) in a non-saturated area when the output voltage or current of said power supply apparatus increases; and a second control signal (from COM4 ; E2 ) for operating said semiconductor switching device ( Q2 ) in a saturated area when said output voltage or current reaches or exceeds a second reference value ( E4 ) larger than said first reference value (at D6 ; E1 ). The method of claim 1, wherein said semiconductor switching device ( Q2 ) is turned off when said output voltage or current falls to or below said first reference value (at D6; E1 ). The method of claim 2, wherein said semiconductor switching device ( Q2 ) is used for blocking reverse current. A power supply apparatus comprising a semiconductor switching device ( Q2 ) for outputting power and a control circuit ( CIC ) for controlling the on/off operation of said semiconductor switching device ( Q2 ), characterised in that said control circuit ( CIC ) includes a circuit ( OP4, COM4 ) for applying to said semiconductor switching device ( Q2 ) a first control signal (from Q4; OP1 ) corresponding to the difference between the output voltage or current of said power supply apparatus and a first reference value (forward voltage of diode D6; E1 ) for operating said semiconductor switching device ( Q2 ) in a non-saturated area when said semiconductor switching device ( Q2 ) is turned on and said output current or voltage increases, and a second control signal (from COM4; E2 ) for operating said semiconductor switching device ( Q2 ) in a saturated area when said output voltage or output current reaches or exceeds a second reference value ( E4 ) larger than said first reference value (at D6; E1 ). The apparatus of claim 4, wherein said control circuit ( CIC ) turns off said semiconductor switching device ( Q2 ) when said output voltage or current falls to or below said first reference value (at D6; E1 ). The apparatus of claim 5, wherein said semiconductor switching device ( Q2 ) is for blocking reverse current. The apparatus of claim 4, wherein said control circuit ( CIC ) includes a monolithic type one-chip integrated circuit. The apparatus of claim 4, wherein said semiconductor switching device ( Q2 ) includes a MOSFET or an IGBT. The apparatus of claim 7, wherein said control circuit ( CIC ) receives an output current detected signal, an output voltage detected signal and a current control line signal of said power supply apparatus and outputs a control output for said semiconductor switching device ( Q2 ) and a current control line signal. The apparatus of claim 4, wherein both said control circuit ( CIC ) and said semiconductor switching device ( Q2 ) are incorporated in a monolithic type one-chip integrated circuit. The apparatus of claim 8, wherein said semiconductor switching device ( Q2 ) is connected in parallel with a current detecting MOSFET ( Q2s ).

Inventors: HAYASHI KATSUNORI, ONAKA TAKESHI, ONDA KENICHI, SAGA RYOHEI, TAKAHASHI TADASHI, TOKUNAGA NORIKAZU, HAYASHI, KATSUNORI, ONAKA, TAKESHI, ONDA, KENICHI, SAGA, RYOHEI, TAKAHASHI, TADASHI, TOKUNAGA, NORIKAZU, Hayashi, Katsunori, c/o Hitachi, Ltd. et al., Onaka, Takeshi, c/o Hitachi, Ltd. et al., Onda, Kenichi, c/o Hitachi, Ltd. et al., Saga, Ryohei, c/o Hitachi Tohbu Semiconductor, Ltd, Takahashi, Tadashi, c/o Hitachi, Ltd. et al., Tokunaga, Norikazu, c/o Hitachi, Ltd. et al.
Applicants: HITACHI LTD, RENESAS E JP SEMICONDUCTOR INC, HITACHI, LTD., RENESAS EASTERN JAPAN SEMICONDUCTOR, INC.
Application year: 2000
Main classification: H02J1
IPC codes: G05F1, H02M3, H03K17, H02H11, H02H7, H02M7, H02M1