PREPARATION OF DATA FOR A REED-SOLOMON DECODER

Abstract: The present invention relates to a method and an arrangement for preparation of data for a Reed - Solomon decoder and more particularly to a method and an arrangement for an intelligent buffer (IBUF) in front of a ramless DVD Reed - Solomon decoder and further on particularly to a method and an arrangement for an intelligent buffer (IBUF) used also as a first pass correction storage of ECC- blocks.In such a way, the Reed - Solomon decoder will not get disordered ECC blocks by an intelligent buffer (IBUF) that leads to less necessary RAM and a high performance of the complete circuitry. The intelligent buffer (IBUF) is used as a first pass correction storage of the Reed Solomon decoder too.

Description: TITLE PREPARATION OF DATA FOR A REED - SOLOMON DECODER FIELD OF THE INVENTION The present invention relates to a method and an arrangement for a preparation of data for a Reed - Solomon decoder and more particulariv to a method and an arrangement for an intelligent buffer in front of a Reed - Solomon decoder that needs less RAM and ensures high performance BACKGROUND OF THE INVENTION A conventional pre-processmg buffer and Reed - Solomon use a common RAM to handle corrupted data Such an arrangement and processmg is for example used to correct data stored on an optical information media like a DVD for reproduction purposes It is desirable to avoid to feed corrupted data to the Reed - Solomon decoder or to use a RAM to store the ECC block or to read defect parts several times what decreases the speed of the data path DVD is an acronym for Digital Versatile Disc and ECC is an acronym for Error Correction Code - an electronic method of checkmg the integrity of data The data of the ECC is hierarchically organized in pieces of the data stream The highest unit is an ECC - block that is divided into a number of sectors Each sector is built up by a number of rows with a fixed length To enable a correction of the stream a number of paπty bytes are appended to each row, the number of the additional bytes determines the number of correctable faults per row In addition to this facility of hoπzontal correction the same calculation is performed vertically over all bytes of an ECC - block which are at the same position of a row. the result is organized m additional rows of the ECC - block To control the order of sectors the first bytes contain identification information The blocks in front of the buffer and Reed - Solomon part get the stream m frames two of which building a ro . an identification of the frame order is evaluated and the result made available to the buf er by appropπate sync - signals A conventional arrangement stores the data mto the common RAM with respect of the identification control results before the Reed - Solomon decoder starts to perform the correction of corrupted data bytes Replacmg the faulty data m memory would require processmg overhead that could accumulate and significantly dimmish system performance RAM is an acronym for Random Access Memory It is a temporary storage area that the processor uses to execute programs and to hold data Reed Solomon is a techmque term for a forward error correcting code that is used to offset the effects of bit error m the receiving bit stream Reed- Solomon codes are special and widely implemented because they are almost perfect in the sense that the extra redundant data added on by the encoder is at a minimum for any level of error correction, so that no bits are wasted SUMMARY OF THE INVENTION It is an object of the invention to provide a method and an arrangement for a Reed - Solomon decoder that needs less RAM and ensures high performance by avoidmg a replace of data m a memon . which would require processmg overhead, that could accumulate and significantly dimmish system performance The features mentioned m independent claims solve this problem Dependent claims disclose preferred embodiments In accordance with an aspect of the invention a method and an arrangement for an intelligent buffer in front of a Reed - Solomon decoder as for example a DVD Reed - Solomon decoder are provided m which the data are analysed based on the incoming sync - signals and the data are buffered at appropπate buffer locations as long as the incoming ECC - block can be repaired by the Reed - Solomon decoder In case that the ECC - block cannot be corrected the Reed - Solomon decoder gets a reset signal to cancel the first stage of processmg An address control block and a buffer form said intelligent buffer In case of a Reed Solomon decoder without RAM or a so-called ramless Reed Solomon accordmg to the mvention, the front-end circuit has no way to store a complete incoming ECC - block before sendmg it as a contmuous data stream to the Reed - Solomon decoder Without any precaution the Reed - Solomon decoder will get many disordered ECC - blocks which the decoder cannot correct This leads to a poor performance of the complete circuitry The intelligent buffer of m front of the Reed - Solomon - decoder accordmg to the mvention tπes to keep the organization of the data as far mtact as possible and smoothes small defects, in the case that the defects will lead to corrupted data the Reed - Solomon block and the micro controller will be informed about the corrupted data As the used ramless Reed - Solomon block has scalable parameters the Reed - Solomon buffer interface is also usable m other context The classification of data and synchronization lacks will hold true for other block codes A buffer is a little room for data storage The buffer is placed between two units, which exchange data The buffer's function give room for a temporary storage of the data coming from a unit in a situation where the other umt is not ready to receive the data The buffer holds these data for a while and delivers them as soon as the recipient is ready to receive them In case of a DVD - player for example the data commg from the acquisition part must be buffered before they can be delivered to the Reed - Solomon correction block to compensate slight defects of the PLL PLL is an abbreviation for phase locked loop For this reason the acquisition part decodes the frame header and the sector identification from the incoming HF - signal and sends this information to the buffer part together with the data In such a way a buffer is m general necessary m front of the Reed Solomon decoder, which accordmg to the mvention is advantageously used The buffer block should be able to resynchromse the data stream at frame and sector boundaries to avoid that inappropriate frame length corrupts the Reed-Solomon In case of not correctable jumps the buffer block stops the current first pass inner/outer correction of the Reed-Solomon decoder and resynchronises at the next ECC - block boundary The Reed-Solomon- buffer interface must be reset in case of physical jumps In an enhanced embodiment an intelligent buffer is used for a first step Reed Solomon correction that deals with the rows of an ECC - block Only some restπctions concerning the allowed jump area have to be respected In such a way advantageously a ramless Reed-Solomon decoder that having a high performance and requires less RAM-memory is performed BRIEF DESCRIPTION OF THE DRAWINGS The mvention will now be descπbed with reference to the accompanying drawings, m which FIGURE 1 is a block diagram for an intelligent buffer in front of a ramless DVD Reed - Solomon decoder together with some driving circuitry. FIGURE 2 is a schematic for forward jumps m case of addr_m>addr_out. FIGURE 3 is a schematic for forward jumps m case of addr_m<addr_out, FIGURE 4 is a schematic for backward jumps m case of addr_m>addr_out FIGURE 5 is a schematic for backward jumps in case of addr n>addr_out and FIGURE 6 shows mput- and output-address of the buffer in case of jumps in sector ED DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS In Fig 1 the three parts necessary to explain the function of an intelligent buffer EBUF in front of a not shown ramless Reed Solomon decoder are shown - The first part is an acquisition block ACQ that provides a clock byte clk of incoming data, the data at data line data in and synchronizing information. - the second part is an address control block ADC that creates addresses and control signals from the synchronisation signals provided from acquisition block ACQ, there are addresses for the m-going data stream at data line data in and addresses and the control-out-signal ctrl out for the outgomg data data out sent from the buffer BUF to the Reed-Solomon decoder - The third part is buffer BUF constructed as storage array with dual ports to handle mdependent time schemes for outgoing data data out and incoming data on data lme data in It may also be constructed with on IO-port if the mput- and output-data streams are appropπate decoupled The address control block ADC and the buffer BUF form the so-called intelligent buffer IBUF accordmg to the invention A further block shows a generator clk gen to generate an independent clock out_clk used for the outgoing data data out stream This task represents a part of the not shown Reed - Solomon decoder As shown m Fig 1. the generator clk_gen is connected to address control block ADC and buffer BUF for providmg the independent clock out clk . which is also used to read data from the buffer BUF to the not shown Reed Solomon block A further clock byte clk of incoming data data in is deπved from the acquisition-block ACQ and applied to address control block ADC and via an AND-gate & to the buffer BUF The other input of said AND-gate & is connected to an output of the address control block ADC providmg an buffer-mput-enable-signal m en that enables the input of the buffer BUF via said AND-gate & by a masked byte clock signal byte_clk_msk formed by said AND-gate & and applied to a corresponding input of buffer BUF A data lme data in connects a corresponding output of acquisition block ACQ with a corresponding input of buffer BUF and provides data as it is generated m the acquisition block and for entering into buffer BUF Acquisition block ACQ and address control block ADC are furthermore connected for providing several signals for address control block ADC as there are a frame start signal nxfr. a frame address sienal fr addr that has been decoded by acquisition block ACQ, a sector identifier SID that also has been decoded by acquisition block ACQ. a next sector start signal nxt SED. a valid sector identifier signal SID vahd indicating that the transferred sector identifier SID was decoded correctly by the acquisition block ACQ and a stop flag stop flag for an asynchronous stop of operation requested b> an internal micro controller in case of severe optical problems The address control block ADC is connected with buffer BUF and provides the buffer BUF with a control-in-signal ctrl in compπsmg three bits signalling ECC-. sector- and frame-start of incoming data via data lme data in. a buffer m address signal addr m for the m-going data, a buffer out address signal addr_out for outgomg data data out and an output operation enable signal out_en for readmg data data out from the buffer BUF to the not shown Reed Solomon decoder The address control block ADC provides furthermore a signal RST RS that stops or resets the Reed Solomon decoder m case of illegal jumps The buffer BUF provides a control-out-signal ctrl out compπsmg three bits signalling ECC-. sector- and frame-start of outgomg data data out provided for the Reed Solomon decoder The acquisition block ACQ as shown m Fig 1 represents the acquisition part of the channel circuit called as channel IC that has to extract the data and several control signals for synchronization From the bit stream coming for example from the optical part of a not shown DVD equipment this block decodes the data data_ιn. the byte clock byte clk. the frame address fr addr and sector number identified by sector identifier SLD In case of disorder in the frame numbers a fault- representmg - sequence is substituted like m the present version of the acquisition part A definite decoding of the sector identifier SID is classified by a valid sector identifier signal SID vahd equal to 1 - pulse independently of the frame address decoding This information is used to resynchronise the frame address to 0 even if the order was corrupted The address control block ADC as shown in Fig 1 has to do the mam work Three stages are used for generatmg the addresses for the buffer BUF lrst Stage Generatmg the expected frame address fr addr and sector identifier SLD Following the synchronization signals from acquisition block ACQ the counters for the expected frame address fr addr and for the sector identifier SID are set m address control block ADC and m cases of defects mcremented mdependently on the current mput. To follow the track of jumps also an internal expected ECC - counter is used, which m the ideal case should follow the mcommg data's ECC blocks This internal counter is mcremented or decremented when the sector number crosses 0 If the acquisition block ACQ provides only an incomplete frame address fr addr and a definite sector identifier SLD and no ECC number, the most hkeh change in the expected address is assumed when jumps occur If the full sector identifier SID is used the most significant bit can synchronise the ECC- counter too The rule how to handle jumps is In case of frame or sector disruptions do not jump a distance longer than half of the frame/ sector-length from the current location The following cases are possible to evaluate the ratio of a current length to a norm length wherem n is an appropπately chosen mteger A 0) Frame length ok. I e length/norm length =1 1 ) Frame length too long and n < length/norm length <= n-1 2 2) Frame length too long and n-ι-1 /2 < length/Norm length <= n+ 1 3) Frame length too short and 0 < length/norm length <= 1 2 4) Frame length too short and 1/2 < length/norm length < 1 B 0) Frame address ok 1 ) Frame address wrong C 0) Sector identifier SID ok 1 ) Sector identifier SID too small, m the present ECC - block 2) Sector identifier SLD too small, in the next ECC - block 3) Sector identifier SE) too large, m the present ECC - block 4) Sector identifier SID too large, m the previous ECC - block D 0) Sector ok 1 ) Sector too short 2) Sector too long If the acquisition block ACQ could not find the frame address fr addr m time it inserts one If the next valid frame address is found durmg the first half frame length no frame address indicators are sent This is why the different cases m A with a respect of ] z nominal length have been made Some of these combmations cannot occur so that the number of combmations reduces a little bit 2nd Stage Generate the buffer-in-address signal addr n for wπtmg data into the buffer BUF Based on the expected addresses for an ECC - block, sector identifier SID and frame address fr addr of the first stage a circular counter for the input address is mcremented on the range of the buffer size In case of jumps different strategies have to be performed dependmg on the direction of the jump, its size and the current address of the output stream as it will be descnbed m detail below The process has to be able to perfoπn a jump, to stop the input until an address is reached or to resynchromze the total process until a new ECC - block starts 3rd Stage Generate the output address for readmg outgoing data data out from the buffer BUF into the not shown Reed-Solomon decoder To ensure a proper addressing it is assumed that the independent output clock out clk is faster than the input clock byte_clk Input signals from data lme data in and outgomg data data out form coπespondmg streams controlled by enable - signals and the output address addr out follows the mput address addr in in some distance In an embodiment a distance of half of the buffer size has been used At the begin and in case of resynchronization the output address corresponding to buffer out address signal addr out is set to 0. in these cases and when the distance between input address addr m and output address addr out is less than the default distance the output address addr out process waits until it is reached If due to lumps the mput address addr m advances increasing the distance to the output address the addr_out is generated with full output clock out clk speed until the default distance is reached agam To handle jumps properly this process must be able to stop operation immediately or at a given address, to perform address generation by full speed and to resynchronize to 0 as it will be descπbed below The buffer BUF as shown in Fig 1 is a RAM of the specified size with dual ports so it can be asynchronously wntten and read or is alternatively constructed with one 10 - port and a control logic preventing comcident m- and out-requests, this is necessary because the two clocks - clock byte clk and clock out clk - are completely independent from each other Both, input and output, can be disabled to make the clock handling easier When the sync - data are acquired in acquisition block ACQ and transferred to address control block ADC they must be transferred to the Reed Solomon block and the following RAM address generator block, therefore they must also be stored and sent synchronously with the outgoing data data_out The generator clk gen is the generator of the mdependent clock out clk for the outgoing data data out. which must have a higher frequency than the maximum frequency of the incoming data, I e the clock byte clk The generation of independent clock out clk can be done by dividing the system clock used m the realization by a proper factor Jump Handling The address jumps listed above were sorted into categoπes with respect to the data section boundaries To find out the best strategy for the buffer addressing a different classification than above has to be used because jumps have to be regarded under the aspect • of the relation of the current m- and output buffer address. • of the jump offset that means does the jump violate the mtegπty of the buffer data. • of the amount of data sent m the meanwhile to the Reed-Solomon decoder dependent on the question whether the current ECC-block can be coπected anyway and • how fast does a following synchronization occur Forward jumps FWDJ are handled according to Figures 2 and 3 and backward jumps BKWJ accordmg to Figures 4 and 5 These figures show a data axis 1 with markers for ECC - boundaπes ECCO. ECC1, ECC2 and parallel a buffer axis 2 with the start and end address noted m the area 5 Arrows show the buffer range under output 6 and the buffer part, which is free for input 7 Furthermore, a snapshot for the mput address before a jump was requested 9 and the output address in nominal distance to the input address 8 are indicated Figure 2 and 3 illustrate the situation of a requested forward jump FWDJ under the circumstance that a buffer-m-address addr in is higher than the buffer-out-address addr_out as shown m Figure 2 and under the circumstance that a buffer-m-address addr in is lower than the buffer-out- address addr_out as shown in Figure 3 The requested first jump 3 will target to an area, which will not hurt the above-mentioned integπty of the stored data m contrast to a second jump 4 which is longer than the first one The latter case will therefore not be performed but the output must be accelerated until the next requested address is out of the forbidden range 6 or the complete ECC - block must be dropped The decision depends on the progress in completmg the ECC - block and on the jump distance Figure 4 and 5 show the configuration of backward jump BKWJ requests under the circumstance that an buffer-in-address addr m is higher than the buffer-out-address addr out as shown in Figure 4 and under the circumstance that an buffer-in-address addr in is lower than the buffer- out-address addr_out as shown m Figure 5 The shorter first jump 3 points to the allowed range and can continue the input but must stop the output until the distance between mput- and output-address is the nominal distance In case of a longer second jump 4 the requested next mput address of the buffer-in-address signal addr m points to an area that is not yet sent out from the buffer BUF. assuming that the last data were corrupted the output is stopped and the area of output data overwritten A different strategy is to stop the input and output of the buffer BUF until the input-address of buffer m address signal addr in pomts to an allowed area In both strategies the possibly corrupted data 10 are already sent out Figure 6 illustrates the behaviour of the embodiment for several jumps in the input and the behaviour of the output addresses It demonstrates that most of the jumps are smoothed out Figure 6 shows an address range AR of the buffer BUF over a time axis t The input address of the buffer in address signal addr n causes an output address of the buffer out address signal addr out following m some distance in spite of jumps like JMP which is evidently smoothed In case of physical jumps no usage of the currently read sectors will be made In this case a stop flag stop_flag is activated as shown m Fig 1 This is independent whether or not the currently read sectors have been completed or not The address - processes will be restarted completely in such a case and a signal RST RS is generated to reset the Reed Solomon operation In a second not shown embodiment the buffer BUF is used simultaneousK as correction buffer for the first step of the Reed Solomon decoder The only difference to the previously descπbed embodiment is a more restricted range for jumps because one has to take into account that the smgle output address of the buffer-out-address signal addr_out of the first embodiment is split into three addresses dedicated to • the calculation and performing of the first step inner correction of a Reed - Solomon decoder using the stored data m the buffer BUF • the calculation of syndromes of the first outer correction and • the output of the data corrected m inner mode The terms inner and outer correction are related to the known correction modes mside a Reed Solomon decoder Decisions made in the previous embodiment on the output address of the buffer-out-address signal addr out have therefore to be done now on the most limiting of these addresses The implementation needs a more restπctive time scheme dependmg on the needs of the Reed Solomon decoder In such a way, the Reed - Solomon decoder will not get disordered ECC blocks by an intelligent buffer IBUF that leads to less necessary RAM and a high performance of the complete circuitry The intelligent buffer IBUF accordmg to this embodiment is used as a first pass correction storage of the Reed Solomon decoder too The method and arrangement descnbed here are given as examples only and a person skilled m the art may realise other embodiments of the invention while remaimng in the scope of the invention The mtelligent buffer IBUF accordmg to the invention is particularly advantageous in that it may easily be used for vaπous kinds of error correction systems

Claims: PATENT CLAIMS 1 An apparatus for a preparation of data for a Reed - Solomon decoder compπsmg an mtelligent buffer (IBUF) in front of said Reed - Solomon decoder m which received data are analysed based on mcommg sync - signals and data are buffered m a buffer (BUF) at appropπate addresses as long as an mcommg ECC - block (ECC) can be repaired by the Reed - Solomon decoder and in case that the ECC - block (ECC) cannot be corrected provides a reset signal (RST RS) to cancel the first stage of processmg said ECC - block (ECC) 2 Apparatus accordmg to claim 1 , wherem said buffer (BUF) is connected via a data lme (data in) to an acquisition block (ACQ) as well as an address control block (ADC) for evaluatmg frame address signals (fr addr) and sector identifier (SID) concerning an integrity with an ECC block length (lgth) 3 Apparatus accordmg to claim 1 , wherem said mtelligent buffer (IBUF) is controlled by an mdependent clock (out_clk) having a higher frequency than a maximum frequency of incoming data at a data lme (data in) supplied to the buffer (BUF) 4 Apparatus accordmg to claim 1 , wherem said intelligent buffer (IBUF ) is a storage medium normally used in front of a Red Solomon decoder of a DVD - player 5 Apparatus accordmg to claim 1 , wherem said intelligent buffer (IBUF) can stop a current first pass inner/outer correction of the Reed-Solomon decoder and resynchronises at the next ECC block boundary (ECC1) 6 Apparatus accordmg to claim 1. wherem said mtelligent buffer (IBUF) is used for a first step Reed Solomon correction that deals with the rows of an ECC - block 7 Apparatus accordmg to claim 1. wherem said buffer (BUF) is constructed as storage array with dual ports to handle mdependent time schemes for outgomg data (data out) and mcommg data on data lme (data in) so it can be asynchronously wπtten and read or is alternatively constructed with one 10 - port and a control logic preventmg comcident m- and out-requests 8 Apparatus accordmg to claim 2, wherem a clock (byte clk) of incoming data (data_ιn) is deπved from the acquisition-block (ACQ) and applied to address control block (ADC) and via an AND-gate ([ ] & [ ]) that is also supplied by a buffer-mput-enable-signal (m_en) provided by the address control block (ADC) to the buffer (BUF) 9 Apparatus accordmg to claim 2, wherem counters for an expected frame address (fr_addr) and for sector identifier (SID) follow the synchronisation signals from the acquisition block (ACQ) and m cases of defects were incremented or decremented independently of the cuπent input 10 A method for a preparation of data for a Reed - Solomon decoder compπsmg the steps of data analysing based on the mcommg sync - signals and buffering data at appropπate addresses provided by an address control block (ADC) m a buffer (BUF) as long as the Reed - Solomon decoder is able to repair an mcommg ECC - block (ECC) and m a case that the ECC - block (ECC) cannot be coπected providing a reset signal (RST RS) to cancel the first process stage of processmg said ECC - block (ECC) 1 1 A method accordmg to claim 10. wherem said data analysing compπses frame address (fr addr), sector identifier (SID) and ECC - block number decoded by an acquisition block (ACQ) where a jump or the most likely change m the expected addresses is assumed when only an mcomplete frame address (ff_addr) and a definite sector identifier (SID) and no ECC - block number have been detected 12 A method accordmg to claim 1 1. wherem if the full sector identifier (SID) is available the most significant bits of a sector identifier (SID) are used to synchronize an internal counter within said address control block (ADC) 13 A method according to claim 10, wherem jumps of successive data in case of frame or sector disruptions do not influence the integnty of ECC - blocks (ECC) if a distance is not longer than a predetermined distance 14 A method according to claim 13. wherem said distance is not longer than half of the length of the free buffer 15 A method accordmg to claim 13. wherem no frame address mdicators are provided if a next valid frame address is found during the first half frame length 16 A method accordmg to claim 13. wherein a circular counter for input address m an address control block (ADC) is incremented/decremented on the range of the buffer size of a buffer (BUF) based on the expected addresses for an ECC- block (ECC). a sector identifier (SID) and a frame address (fr_addr) 17 A method accordmg to claim 13. wherein at the begin and m case of resynchronization the output address correspondmg to a buffer out address signal (addr out) is set to zero and m these cases and when the distance between mput address (addr in) and output address (addr out) is less than a default distance the output address (addr_out) process waits until it is reached and if due to jumps of the input address (addr_ιn) mcreasmg the distance, output addresses (addr out) are generated with full output clock (out_clk) speed until the default distance is reached agam 18 A method according to claim 13. wherem m case of a forward jump (FWDJ) if a jump (3) targets to an unblocked area of the buffer of length (lgth) the new storage does not hurt the integπty of already stored data and if m contrast a jump (4) into the blocked storage area of the buffer of length (lgth) is requested the jump will not be performed but the output is accelerated until the next requested input address is out of a forbidden range (6) 19 A method accordmg to claim 13, wherem m case of a backward jump (BKWJ) if a jump (3) targets to an unblocked area of the buffer of length (lgth) the new storage will not hurt the integrity of stored data and the input can contmue but must stop the output until the distance between input- and output-address is the nominal distance and if in contrast a jump (4) mto a blocked storage area of the buffer of length (lgth) is requested the mput address of the buffer-in-address signal (addr m) is updated but the data is not stored until the buffer-m-address signal (addr m) pomts to an allowed buffer area 20. A method accordmg to claim 10, wherem in case of physical jumps of a pickup of a player no usage of currently read sectors is made, a stop flag (stop flag) is activated mdependent whether or not currently read sectors have been completed or not, the address - processes are restarted completely and a signal (RST RS) is generated to reset the Reed Solomon operation 21 A method accordmg to claim 10 compπsmg the steps of generating an expected frame address (fr addr) and sector identifier (SID), generatmg a buffer m address signal (addr in) for wπtmg data in a buffer (BUF) based on the expected addresses for an ECC - block (ECC), sector identifier (SID) and frame address (fr addr), generatmg the output address for readmg outgoing data (data out) from said buffer (BUF) mto the Reed-Solomon decoder 22 A method for a preparation of data for a Reed - Solomon decoder compπsmg a buffering of mcommg data at appropπate addresses m a buffer (BUF) as long as an incoming ECC - block (ECC) can be repaired by the Reed Solomon decoder. 23. A method accordmg to claim 22. wherem a smgle output address of a buffer out address signal (addr out) of said buffer (BUF) is extended to three addresses dedicated to a calculation and a performmg of a first step inner correction of a Reed - Solomon decoder usmg stored data in the buffer (BUF), a calculation of syndromes of a first outer correction and an output of data corrected m said inner correction mode

Inventors: FREISSMANN LOTHAR, FREISSMANN, LOTHAR
Applicants: FREISSMANN LOTHAR, THOMSON BRANDT GMBH, DEUTSCHE THOMSON-BRANDT GMBH, FREISSMANN, LOTHAR
Application year: 2000
Main classification: H03M13
IPC codes: G06F11, G11B20, H03M13