InGaAsN/GaAs QUANTUM WELL DEVICES

Abstract: Disclosed is a semiconductor quantum well device, such as a heterojunction diode laser, in which the quantum well layer is InGaAsN grown in the presence of Sb, but with negligible incorporation of Sb in the quantum well layer. Also disclosed is a method for forming a semiconductor quantum well device having the step of growing a thin quantum well layer of InGaAsN in the presence of Sb, but with negligible incorporation of Sb in the quantum well layer. Growth of the InGaAsN quantum well layer in the presence of Sb greatly improves the quality of the quantum well layer by inhibiting island formation during layer growth. In addition, there is disclosed a novel high electron mobility transistor having an InGaAsN active channel layer, which provides a larger conduction band offset than conventional transistors having an InGaAs active channel layer. Advantageously, the InGaAsN active channel layer is formed in the presence of Sb with negligible incorporation of Sb in the layer.

Description: InGaAsN/GaAs QUANTUM WELL DEVICES SPECIFICATION BACKGROUND OF INVENTION The present invention relates to quantum well devices and, more particularly, to InGaAsN/GaAs quantum well devices. Quantum well structures have found important applications in a variety of novel semiconductor devices. In such structures, a thin region of a relatively narrow band gap semiconductor is sandwiched between layers of relatively wide band gap semiconductors or surrounded by a relatively wide band gap semiconductor. One important application of the quantum well structure is the semiconductor laser diode. Long wavelength (1.3μm or 1.55μm) laser diodes are important light sources for optical communication and optical interconnection systems due to the low transmission loss in optical fibers at such wavelengths. Although these wavelengths are readily obtainable with InGaAsP/InP-based active layers, this material system lacks sufficient refractive index contrast to form highly reflective distributed Bragg reflector mirrors necessary for the desirable vertical-cavity surface-emitting laser (VCSEL) configuration. Moreover, the performance of lasers made with this material system has been limited by a relatively low characteristic temperature (T 0 ) due to poor electron confinement resulting from a small conduction band offset. As an alternative, the InGaAsN/GaAs system, which has been achieved by both molecular beam epitaxy (MBE) and metalorganic chemical vapor deposition (MOCVD) offers a potential for long wavelength VCSEL devices with an enhanced T 0 due to the increased conduction band offset. An InGaAsN/GaAs-based VCSEL laser diode emitting at a wavelength of 1.18μm is described in M.C. Larson et al., "GalnNAs- GaAs Long- Wavelength Vertical-Cavity Surface-Emitting Laser Diodes," IEEE Photonics Technology Letters, Vol. 10 no. 2, February 1998. Edge emitting 1.3μm InGaAsN/GaAs-based devices grown by MOCVD as well as gas-source MBE have also been reported. However, the lasing thresholds of these devices remain high as a result of limitations in the quality of the InGaAsN quantum well layer due to the large miscibility gap, which causes the InGaAsN material to have a tendency to form islands rather than a continuous layer. This problem also affects other quantum well devices that use InGaAsN as the quantum well layer. With respect to the high electron mobility transistor (HEMT), the material that is in most widespread use as the active channel layer is InGaAs. However, a HEMT device having an InGaAsN active channel has a significantly larger conduction band offset than a HEMT device having an InGaAs active channel. A larger conduction band offset results in a desirable higher two-dimensional electron charge density in the channel. A HEMT having an InGaAsN active layer has not heretofore been proposed or suggested. Moreover, the same problem in growing a InGaAsN quantum well layer in a laser diode exists in growing a high quality active channel layer of the same material in a HEMT. Accordingly, a need exists for improved quantum well devices having InGaAsN as the quantum well layer, which overcomes the problems of the prior art as discussed above. SUMMARY OF THE INVENTION In accordance with the present invention, there is provided a method for fabricating a semiconductor quantum well device by first forming a layer of a semiconductor material having a relatively wide band gap. A quantum well layer of InGaAsN is formed on the first layer in the presence of Sb, but with negligible incorporation of Sb in the layer. A second layer of semiconductor material having a relatively wide band gap is formed over the quantum well layer. According to an exemplary embodiment, the quantum well device is a diode laser and there is formed on a relatively heavily doped n-type GaAs substrate a bottom distributed Bragg reflector comprising 20 to 30 pairs of alternating layers of n- type AlAs and n-type GaAs, each layer having a thickness which is equal to one- quarter the wavelength of the laser light adjusted for the index of refraction of the layer. On the top layer of the bottom distributed Bragg reflector layers is formed an n-type AlGaAs spacer layer. On top of the n-type spacer layer is formed a relatively thin GaAs first cladding layer, and directly above the first barrier layer is formed an InGaAsN quantum well layer, which is formed in the presence of Sb but with negligible incorporation of the Sb in the quantum well layer. On top of the quantum well layer is formed a second relatively thin GaAs cladding layer, and above that a p- type AlGaAs spacer layer. Directly above the p-type spacer layer is formed a top distributed Bragg reflector comprising 20 to 30 pairs of alternating layers of p-type AlAs and p-type GaAs, each layer having a thickness equal to one-quarter the wavelength of the laser light adjusted for the index of refraction of the layer. Overlying the top distributed Bragg reflector is formed a relatively heavily doped p- type phase matching layer, above which is formed a p-electrode layer. An n-electrode layer is formed over a portion of the lower surface of the substrate to complete the VCSEL structure. According to another exemplary embodiment, the quantum well device is a pseudomorphic high electron mobility transistor having a relatively thick undoped buffer layer, preferably GaAs grown on a semi-insulating substrate, which is also preferably GaAs. On the buffer layer is disposed a relatively thin InGaAsN quantum well channel layer, advantageously, but not necessarily, grown in the presence of Sb with negligible incorporation of Sb in the layer. On the channel layer is grown a relatively very thin undoped barrier layer, which is preferably AlGaAs or GalnP. On the barrier layer is grown a relatively heavily doped n-type layer, which is preferably AlGaAs or GalnP grown on the AlGaAs or GalnP barrier layer, respectively. On top of the relatively heavily doped n-type layer is formed a relatively heavily doped n- type cap layer, which is preferably GaAs. Using conventional photolithography and etching, the cap layer is separated into isolated source and drain regions and an etched back portion of the underlying relatively heavily doped n-type layer between the source and drain region of the cap layer is exposed. Source and drain contact layers are formed on the source and drain regions of the cap layer , respectively, and a gate electrode is formed on the etched back portion of the relatively heavily doped n-type layer between the source and drain regions of the cap layer. BRIEF DESCRIPTION OF THE DRAWINGS For a more complete understanding of the nature and benefits of the present invention, reference should be made to the following detailed description taken in conjunction with the accompanying drawings, in which: Fig. 1 is a diagram showing the schematic's structure of a InGaAs(N)/GaAs multiple quantum well having an InGaAsN quantum well layer formed using the method of the present invention, the structure being used for obtaining x-ray diffraction (XRD)spectra, reflection high-energy electron diffraction (RHEED) analyses and photoluminescence (PL) spectra of the multiple quantum wells; Fig. 2 shows the XRD spectra of the multiple quantum well structure of Fig. 1 where the multiple quantum well is grown with and without the presence of Sb, and a dynamical theoretical simulation of the XRD spectra of the multiple quantum wells; Fig. 3 shows the RHEED patterns of In 03 G--o 7 As 0992 N 0008 /GaAs multiple quantum well where the Irio 3 Gao 7 As 0992 N 0008 quantum well layer is grown with and without the presence of Sb; Fig. 4 shows the room temperature PL spectra of Ir-o 3 G--o 7 As 0992 N 0008 /GaAs multiple quantum wells, showing the enhancement of PL with increasing Sb beam fluxed during MBE growth of the Irig 3 Gao 7 As 0992 N 0008 quantum well layer, the inset showing variations of the PL peak intensity at full width half maximum (FWHM) with increasing Sb flux, the peak intensity being normalized with respect to a reference In 03 Ga 07 As 0992 N 0008 /GaAs quantum well grown with no Sb flux; Fig. 5 is a diagram showing the schematic structure of a vertical-cavity surface-emitting InGaAsN/GaAs single quantum well laser diode in accordance with an exemplary embodiment of the present invention; Fig. 6 is a diagram showing the schematic structure of an edge emitting single quantum well laser diode used as a test structure for three different quantum wells, including a quantum well in accordance with the present invention; Fig. 7 is a graph showing the measured light intensity versus current injection of an InGaAsN/GaAs single quantum well laser diode having the structure of Fig. 6 and fabricated in accordance with the present invention with an Sb beam flux of 1.8 x 10 "7 Torr, the measurements being made at room temperature under pulsed operation; Fig. 8 is a diagram showing the schematic structure of a AlGaAs/InGaAsN/GaAs pseudomorphic high electron mobility transistor, in accordance with the present invention; and Fig. 9 shows band diagrams of pseudomorphic HEMTs one having an Ii-o 3 G--o 7 As channel and the other having an Irio 3 G--g 7 As 099 N 001 channel in accordance with the present invention. DETAILED DESCRIPTION Referring to Fig. 1, there is shown the schematic structure of InGaAs(N)/GaAs multiple quantum wells used for XRD studies, RHEED analyses and PL studies. The InGaAsN/GaAs quantum well samples were grown on semi-insulating GaAs (100) substrates 101 by conventional molecular beam epitaxy (MBE) using a Varian Gen-II System equipped with a CTI cryopump (1500 f/s). Ultra high purity N 2 was injected through a N radical beam source operated at a frequency of 13.56 MHz to generate active N species. Ga, In and Sb were supplied from conventional Knudsen effusion cells, and As in the form As 2 was supplied from a cracker source. An undoped GaAs buffer layer 102 having a thickness of 0.5μm is grown on a semi-insulating the GaAs substrate 101. An undoped InGaAs(N) quantum well layer 103 having a thickness of approximately 6.4nm is grown on the buffer layer 102 followed by the growth of a 24nm thick undoped GaAs barrier layer 104 on the well layer 103. An undoped GaAs cap layer 105 having a thickness of 0.1 μm is grown on the barrier layer 104. The growth temperature of the InGaAsN/GaAs multiple quantum wells was 460°C. The nitrogen composition of the InGaAsN quantum well 103 was determined from XRD of the InGaAsN/GaAs multiple quantum well structure 103/104. First, a reference In 03 Gao 7 As/GaAs multiple quantum well structure was grown, from which the In composition was determined. The experimental XRD spectrum 201 and the dynamical series simulation result 202 of an In 03 G--o 7 As 0992 N 0008 /GaAs multiple quantum well structure are shown in Fig. 2. High resolution x-ray rocking curve measurements were performed using a Philips five-crystal x-ray diffractometer. The N mole fraction was determined to be 0.8%. The N composition was also calibrated by secondary ion mass spectroscopy (SIMS) analysis and absorption spectra of bulk InGaAsN grown under the same conditions as the above quantum wells. The results from absorption measurements and SIMS analysis (not shown) agree well with the results obtained by XRD. Also shown in Fig. 2 is the XRD spectrum 203 of a In 03 Ga 07 As 0992 N 0008 /GaAs multiple quantum well where 8 * 10 "8 Torr Sb beam fluxed was introduced during growth of the well. Compared with the XRD spectrum 201 of the Ir-o 3 G--o 7 As 0992 N 0008 /GaAs multiple quantum well structure grown in the absence of Sb, the better developed satellite peaks and clear diffraction fringes of the XRD spectrum 203 of the same multiple quantum well grown in the presence Sb indicate that the crystal quality and interfaces of the InGaAsN/GaAs multiple quantum well structure was improved by the introduction of the Sb flux during growth. This is consistent with the RHEED patterns observed during the growth of the quantum wells without and with Sb flux, as shown in 301 and 302 of Fig. 3, respectively. While the RHEED pattern 301 of InGaAsN grown without Sb flux becomes partly spotty, especially at high N plasma flux, the RHEED pattern 302 of InGaAsN grown with Sb flux remains streaky throughout the growth. Although adding N in InGaAs reduces the lattice mismatch between InGaAs and GaAs and an increase in critical thickness is expected, three dimensional growth was observed for InGaAsN layers of thickness less than the critical thickness predicted by J.W. Matthews and A.E. Blakeslee, J. Cryst. Growth 27, 118 (1974) (about lOnm for In 03 G-- 07 As/GaAs). It is possible that due to N having a higher surface free energy than As, the surface kinetics of growth is changed. A more plausible explanation is that Sb has a lower surface-free energy than As, which favors wetting of the overlayer. While the mechanisms of the formation of islands by InGaAsN on GaAs and the role played by Sb in the growth of InGaAsN are not completely understood, it is clear that an excess Sb flux during the growth of the strained InGaAsN layer can act in a manner that is analogous to that of a surfactant, which lowers surface-free energy and suppresses surface diffusion to inhibit the formation of islands. Referring now to Fig. 4, there is shown the results of a study of the effect of excess Sb flux on the optical properties of InGaAsN/GaAs quantum wells by PL. Room temperature PL spectra of In^Gao 7 As 0992 N 0008 /GaAs quantum wells grown with Sb beam fluxes of 3.2 * 10 8 Torr, 8.0 x 10 "8 Torr and 1.8 x 10 "7 Torr are shown as 402, 403 and 404, respectively. The PL characteristics were measured using an Ar ion laser and an InGaAs detector. A reference spectrum 401 of Ir-o 3 Gao 7 As 0992 N 0008 /GaAs grown without Sb beam flux is included for comparison. The inset of Fig. 4 shows a plot 406 of the variation of the normalized PL peak intensity and a plot 405 of FWHM of the PL spectra with increasing Sb flux, the peak intensity being normalized with respect to the referenced InGaAsN/GaAs quantum well grown without Sb beam flux. As may be seen in Fig. 4, the PL peak intensity increases and the FWHM decreases with increasing Sb flux, indicating the enhancement of PL efficiency of InGaAsN/GaAs quantum wells by the presence of Sb during growth. By comparing the PL spectrum 404 for a quantum well grown with an Sb beam flux of 1.8 x 10 "7 Torr with the PL spectrum 401 for a well grown with no Sb beam flux, there is a PL peak intensity increase by a factor of 5 and a FWHM decrease from 58 meV to 45 meV for the quantum well grown with an Sb flux of 1.8 10 ~7 Torr. It is noted that the PL peak wavelength of the InGaAsN/GaAs quantum wells does not shift for the Sb beam flux levels under consideration. This indicates that there is negligible incorporation of Sb in the InGaAsN/GaAs quantum wells, and supports the postulate that the Sb acts as a surfactant. Thus the quality of the InGaAsN layer is improved by growth of the layer in the presence of Sb but with negligible incorporation of Sb in the layer. As used in the specification and claims, "negligible incorporation" means that the amount of Sb incorporated in the InGaAsN layer causes substantially no change in the band gap of the layer. Referring now to Fig. 5, there is shown the schematic structure 500 of a VCSEL having a quantum well formed in accordance with the present invention. The device may be grown in a Varian GEN II molecular beam epitaxy (MBE) machine equipped with a CTI cryopump (1500 1/s) and using Knudsen effusion cells for In, Ga, Al, As, Sb, Si and Be. The cell temperature is 1000°C for Ga, 1200°C for Al, 900°C for In, 380°C for As, 600 °C for Sb, 1200°C for Si (used as the n-type dopant) and 850 °C for Be (used as the p-type dopant). Atomic nitrogen (N) is provided by introducing ultra high purity N 2 through a N radical beam source operated at a frequency of 13.56 MHz. An n-type bottom distributed Bragg reflector 502 is grown on an n-type GaAs substrate 501 doped with Si at a concentration of 2 10 18 /cm 3 . The bottom distributed Bragg reflector 502 consists of 20 to 30 pairs of alternating layers of n-type AlAs and n-type GaAs, each layer being doped with Si at a concentration of 2 x 10 18 /cm 3 and grown at a temperature of 600° C. The thickness of each layer is one-quarter the wavelength of the laser light (1.3μm) adjusted for the index of refraction of the layer. Accordingly, the thickness of each AlAs layer is 11 lnm, and the thickness of each GaAs layer is 95nm. On top of the last layer 510 of the bottom distributed Bragg reflector 502 is grown an n-type spacer layer 503 of Al 03 Gao 7 As having a thickness of 185nm and doped with Si at a concentration of 1 x 10 I8 /cm 3 . The n-type spacer layer 503 is grown at a temperature of 640 °C. Above the n-type spacer layer 503 is grown an IΪΪ Q 03 Gao 7 AsN/GaAs quantum well 504. The quantum well consists of first growing a lOnm lower cladding layer (not shown) of undoped GaAs on the n-type spacer layer 503 at a temperature of 580°C. Then a 7.5nm thick quantum well layer (not shown) of In 03 Gao 7 As 099 N 00 ι is grown on the lower cladding layer at a temperature of 460° C in the presence of an Sb beam flux of 1.87 10 "7 Torr. On the quantum well layer is grown a lOnm upper cladding layer (not shown) of undoped GaAs at a temperature of 580 °C. Overlying the quantum well 504 is grown a p-type spacer layer 505 of Al 03 Gao 7 As having a thickness of 180nm and doped with Be at a concentration of 2 x 10 18 /cm 3 . The p-type spacer layer 505 is grown at a temperature of 640°C. Above the p-type spacer layer 505 is formed a top distributed Bragg reflector 506 consisting of 20 to 30 pairs of alternating layers of p-type AlAs and p-type GaAs, each layer being doped with Be at a concentration of 5 x 10 18 /cm 3 and grown at a temperature of 600°C. The thickness of each layer is equal to one-quarter the wavelength of the laser light (1.3μm) adjusted for the index of refraction of the laser. As in he lower distributed Bragg reflector 502, the thickness of each AlAs layer is 1 1 lnm, and the thickness of each GaAs layer is 95nm. On the last layer 51 1 of the top distributed Bragg reflector 506 is grown a 7 lnm thick p-type phase matching layer 507 doped with Be at a concentration of 5 10 18 /cm 3 and grown at a temperature of 600 °C. A Ti/Au metal contact layer 508 is deposited on the phase matching layer 507. An In metal contact layer 509 is formed over a portion of the bottom of the substrate 501. Turning to Fig. 6, there is shown the schematic structure 600 of an edge emitting single quantum well diode laser used in three test laser diodes described below. The laser structure 600 was grown using the aforedescribed Varian Gen II MBE machine on an n + -type GaAs (100) 4° off substrate 601. A 0.5μm n + -type GaAs buffer layer 602 was grown on the substrate 601. A 1.5 μm n-type Al 03 G--o 7 As lower cladding layer 603 doped with Si to a concentration of 7 10 17 /cm "3 was grown on the buffer layer 602. A quantum well 604 consisting of a 7.5 nm quantum well layer 606 sandwiched between undoped GaAs optical confinement layers 605 and 607 were grown on the n-type cladding layer 603. A 1.5μm p-type Al„ 3 G--o 7 As upper cladding layer 608 doped with Be at a concentration 7 x 10' 7 /cm "3 was grown on the upper GaAs optical confinement layer 607. A O.lμm p + -type GaAs cap layer 609 was grown on the upper cladding layer 608. Conventional AuZn and AuGe/Ni metallization was used for the p-type contact 610 and the n-type contact 611, respectively. The structure of Fig. 6 was used with three different quantum well layers, as described below, including an InGaAsN quantum well layer grown in the presence of Sb. The latter quantum well layer was grown at a temperature of 460 °C. while an excess Sb flux of 1.8 x 10 "7 Torr was present. For this quantum well, the In and the N compositions for the InGaAsN layer were estimated from the x-ray diffraction data for the InGaAsN/GaAs multiple quantum well structure of Fig. 1. The estimates for the In and N mole fractions were estimated to be 0.3 and 0.01, respectively. In addition, the N composition was calibrated by SIMS analysis and absoφtion spectra of bulk InGaAsN. In Fig. 7 there is shown a plot 701 of the light output power versus injected current of an edge emitting Irio 3 Gao 7 As 0992 N 0008 /GaAs single quantum well laser diode having the structure of Fig. 6 measured at room temperature under pulsed operation with a pulse-width of 1.5μs and a repetition rate of IK Hz. The quantum well of the laser diode was grown with a Sb beam flux of 1.8 x 10 "7 Torr. The threshold current density and the slope efficiency of the laser diode were 520 A/cm 2 and 150 mW/A, respectively. For comparison, Table I shows the performance of three different laser diodes, which have identical structures (i.e., the structure of Fig. 6) and In composition, but the quantum well layers are Ir-o 3 Gao 7 As, Ii-o 3 G-Lo 7 As 0992 N 0008 grown in the absence of Sb beam flux, and In 03 Gao 7 As 0992 N 0008 grown with an Sb beam flux of 1.8 10 "7 Torr (Irio 3 Gao 7 As 0992 N 00 o 8 ; Sb) , respectively. TABLE I Compared with the Irio 3 Gao 7 As 0992 N 0008 /GaAs laser diode grown in the absence of Sb, the same quantum well laser diode having its quantum well layer grown in the presence of an Sb beam flux of 1.8 x 10 ~7 Torr has the same emission wavelength of 1.2 μm at room temperature, but with a much lower threshold current density. The threshold current density was reduced by a factor of 6 by having Sb present during growth of the quantum well, which verifies the improvement in properties in a InGaAsN/GaAs quantum well grown in the presence of Sb. Turning to Fig. 8, there is shown the schematic structure 800 of another exemplary embodiment of the present invention. The structure shown is that of a pseudomorphic HEMT, which may be fabricated using the aforedescribed Varian GEN II MBE machine. First a lμm thick undoped GaAs buffer layer 802 is grown on a semi-insulating GaAs substrate. The buffer layer 802 is grown at a temperature of 600°C. An 8nm thick InGaAsN quantum well channel layer 803 is then grown at a temperature of 460°C. on the buffer layer 802. In accordance with the present invention, the channel layer 803 may be grown with or without the presence of Sb. Advantageously, the channel layer is grown in the presence of Sb beam flux of 1.8 10 "7 Torr, with negligible incoφoration of Sb in the channel layer 803. A 3nm thick undoped Al 0 ^G-io 75 As barrier layer 804 is then grown at 580° C on the channel layer 803, followed by the growth at the same temperature of a 30nm thick n-type Al 025 G--o 75 As layer 805 doped with Si at a concentration of 3 10 18 /cm 3 . Alternatively, the barrier layer and the n-type layer may be Gao 5 iIno 49 P. Thereafter, a 30nm thick n-type GaAs cap layer, which is shown in two parts 806 and 807 in the figure, is grown on the Al 025 G-io 75 As layer 805. The GaAs cap layer 806 and 807 is doped with Si at a concentration level of 3 10 18 and grown at a temperature of 580°C. Using conventional photolithography and etching, the GaAs cap layer is separated into two isolated regions 806 and 807, which correspond to drain and source regions of the device, respectively, and the n-type AlGaAs layer 805 is etched back in a portion thereof between cap layer regions 806 and 807 to accommodate a gate electrode 811 formed by the deposition of TiPtAu metal and conventional photolithography and etching. A source contact 809 and a drain contact 810 are formed over the separated regions of the n-type GaAs cap layer 807 and 806, respectively, by depositing AuGeNi and patterning the metallization by conventional photolithography and etching. Referring now to Fig. 9, there are shown band diagrams for two pseudomoφhic HEMTs having the structure shown in Fig. 8. One of the band diagrams 901 is for a device having an In^Ga^As active channel, while the other band diagram 902 is for a device having an In^Gao T Aso^Noo, active channel grown in the presence of Sb in accordance with the present invention. As shown by the band diagrams, the AlGaAs/InGaAsN pseudomoφhic HEMT structure has a conduction band offset which is approximately 0.15eV larger than the AlGaAs/InGaAs heterostructure, which is currently in widespread use. A larger conduction band offset results in a higher two-dimensional electron charge density in the channel, which provides improved transistor performance. As discussed above in connection with laser diodes, growth of a high quality thin (8nm) InGaAsN channel layer is facilitated by the presence of Sb during growth, but with negligible incoφoration of Sb in the channel layer. While the present invention has been particularly described with reference to exemplary embodiments thereof, it will be understood by those skilled in the art that various modifications and alterations may be made without departing from the spirit and scope of the invention. For example, the exemplary embodiments disclosed herein may be fabricated using metal-organic chemical vapor deposition (MOCVD), in which case the InGaAsN quantum well layer may be grown in the presence of Sb by using trimethyl antimony or triethyl antimony. Accordingly, the disclosed embodiments of the invention are considered merely illustrative, and the invention is limited in scope only as specified in the appended claims.

Claims: CLAIMS 1. A semiconductor quantum well device having a quantum well layer comprising InGaAsN grown in the presence of Sb but with negligible incoφoration of Sb in the quantum layer. 2. The device according to claim 1, wherein the InGaAsN quantum well layer is disposed between first and second layers of semiconductor material each having a wider band gap than the InGaAsN of the quantum well layer. 3. The device according to claim 2, wherein the device is a diode laser for producing light of a predetermined wavelength and the first and second layers are relatively thin GaAs layers disposed adjacent respective p-type and n-type AlGaAs layers, and further comprising means for providing an electrical current path through the relatively thin GaAs layers, the InGaAsN quantum well layer and the p-type and n-type AlGaAs layers. 4. The device according to claim 3, wherein the InGaAsN quantum well layer, the relatively thin GaAs layers and the p-type and n-type AlGaAs layers are respectively disposed adjacent a relatively heavily doped p-type GaAs cap layer and a relatively heavily doped n-type GaAs buffer layer, and further comprising a relatively heavily doped n-type GaAs substrate on which the GaAs buffer layer is disposed, an n-electrode layer formed on an exposed surface of the substrate and a p-electrode layer formed on an exposed surface of the cap layer. 5. The device according to claim 4, wherein the p-electrode layer comprises AuZn and the n-electrode comprises AuGe/Ni. 6. The device according to claim 3, wherein the quantum well layer, the first and second relatively thin GaAs layers and the p-type and n-type AlGaAs are disposed between p-type and n-type distributed Bragg reflectors, the n-type distributed Bragg reflector being adjacent the n-type AlGaAs layer and comprising a multiplicity of alternating layers of n-type AlAs and n-type GaAs overlying a relatively heavily doped n-type GaAs substrate, each layer having a thickness equal to one-quarter the wavelength of the laser light within the layer, the p-type distributed Bragg reflector being adjacent the p-type AlGaAs layer and comprising a multiplicity of alternating layers of p-type AlAs and p-type GaAs, each layer having a thickness equal to one-quarter the wavelength of a laser light within the layer, and further comprising a relatively heavily doped GaAs phase matching layer disposed on the p- type distributed Bragg reflector, a p-electrode layer disposed on the phase matching layer and an n-electrode formed on an exposed surface of the substrate. 7. The device according to claim 6, wherein the p-electrode layer comprises Ti/Au amd n-electrode layer comprises In. 8. A device according to claim 3, wherein the quantum well layer comprises li-o 3 G--o 7 As 099 N 0 oi . 9. The device according to claim 3, wherein the respective p-type and n-type AlGaAs layers comprise Al 03 Gao 7 As. 10. A high electron mobility transistor comprising an InGaAsN active channel layer disposed between first and second layers of semiconductor material each having a wider bandgap than the InGaAsN active channel layer. 11. The transistor of claim 10, wherein the InGaAsN active channel layer is formed in the presence of Sb but with negligible incoφoration of Sb in the quantum layer. 12. The transistor according to claim 10, wherein the first wider band gap material layer is a relatively thick buffer layer of undoped GaAs and the second wider band gap material layer is a relatively thin barrier layer of undoped AlGaAs disposed on the active channel layer. 13. The transistor according to claim 12, wherein the undoped GaAs buffer layer is grown on a semi-insulating GaAs substrate, and further comprising a relatively heavily doped n-type AlGaAs layer disposed on the undoped barrier layer and a relatively heavily doped n-type GaAs cap layer disposed on the relatively heavily doped n-type AlGaAs layer. 14. The transistor according to claim 13, wherein a portion of the GaAs cap layer is removed to form isolated source and drain regions and to expose a portion of the relatively heavily doped n-type AlGaAs layer between the source and drain regions of the cap layer, and further comprising source and drain electrodes disposed on the source an drain regions of the cap layer, respectively, and a gate electrode disposed on the exposed portion of the relatively heavily doped n-type AlGaAs layer. 15. The transistor according to claim 14, wherein a portion of the relatively heavily doped n-type AlGaAs layer between the source and drain regions of the cap layer is removed to provide a recessed exposed surface therein, and the gate electrode is disposed on the recessed exposed surface of the relatively heavily doped n-type AlGaAs layer. 16. The transistor according to claim 14 wherein the source and drain electrodes each comprise AuGeNi and the gate electrode comprises TiPtAu. 17. The transistor according to claim 10, wherein the first wider band gap material layer is a relatively thick buffer layer of undoped GaAs and the second wider band gap material layer is a relatively thin barrier layer of undoped GalnP disposed on the active channel layer. 18. The transistor according to claim 17, wherein the undoped GaAs buffer layer is grown on a semi-insulating GaAs substrate, and further comprising a relatively heavily doped n-type GalnP layer disposed on the undoped barrier layer and a relatively heavily doped n-type GaAs cap layer disposed on the relatively heavily doped n-type GalnP layer. 19. The transistor according to claim 17, wherein a portion of the GaAs cap layer is removed to form isolated source and drain regions and to expose a portion of the relatively heavily doped n-type GalnP layer between the source and drain regions of the cap layer, and further comprising source and drain electrodes disposed on the source and drain regions of the cap layer, respectively, and a gate electrode disposed on the exposed portion of the relatively heavily doped n-type GalnP layer. 20. The transistor according to claim 19, wherein a portion of the relatively heavily doped n-type GalnP layer between the source and drain regions of the cap layer is removed to provide a recessed exposed surface therein, the gate electrode is disposed in the recessed exposed surface of the relatively heavily doped n-type GalnP layer. 21. The transistor according to claim 19, wherein the source and drain electrodes each comprise AuGeNi and the gate electrode comprises TiPtAu. 22. A method for fabricating a semiconductor quantum well device comprising the steps of: forming a first layer of semiconductor material; forming a quantum well layer of InGaAsN on the first layer of semiconductor material in the presence of Sb with negligible incoφoration of Sb in the quantum well layer; and forming a second layer of semiconductor material on the quantum well layer, wherein the semiconductor materials of the first layer and second layer each has a wider band gap than the InGaAsN of the quantum well layer. 23. The method according to claim 22, wherein the device is a diode laser for producing light of a predetermined wavelength and the first and second layers are relatively thin layers of GaAs. 24. The method according to claim 23 further comprising the steps of: forming a relatively thick heavily doped n-type GaAs buffer layer on a relatively heavily doped n-type GaAs substrate; forming an n-type layer of AlGaAs on the buffer layer, wherein the first relatively thin GaAs layer is formed on the n-type AlGaAs layer; forming a p-type AlGaAs layer on the second relatively thin GaAs layer; forming a relatively heavily doped p-type GaAs cap layer on the p-type AlGaAs layer; forming a p-electrode on the cap layer; and forming an n-electrode on the exposed surface of the susbstrate. 25. The method according to claim 24, wherein the n-electrode comprises AuGe/Ni and the p-electrode comprises AuZn. 26. The method according to claim 23 further comprising the steps of: forming on an n-type GaAs substrate a multiplicity of alternating layers of n-type AlAs and n-type GaAs, each layer having a thickness of one-quarter of the wavelength of the laser light in the layer; forming an n-type AlGaAs spacer layer on a last one of the multiplicity of n- type layers, wherein the first relatively thin GaAs layer is formed on the n-type spacer layer; forming a p-type AlGaAs spacer layer on the second relatively thin GaAs layer; and forming a multiplicity of alternating layers of p-type AlAs and p-type GaAs on the p-type spacer layer, each one of the multiplicity of p-type layers having a thickness equal to one-quarter of the wavelength of the laser light in the layer. 27. The method according to claim 26 further comprising the steps of: forming a p-type GaAs phase matching layer on a last one of the multiplicity of p-type layers; forming a p-electrode layer on the phase matching layer; and forming an n-electrode layer on an exposed portion of the substrate. 28. The method according to claim 27, wherein the p-electrode layer comprises Ti/Au and the n-electrode layer comprises In. 29. The method of claim 23, wherein the quantum well layer comprises 30. The method of claim 26, wherein the p-type and n-type spacer layers each comprise Al 03 Gag 7 As. 31. A method for fabricating a high electron mobility transistor comprising the steps of: forming a first layer of semiconductor material; forming an active channel layer of InGaAsN on the first layer of semiconductor material; forming a second layer of semiconductor material on the active channel layer, wherein the semiconductor materials of the first layer and the second layer each has a wider band gap than the InGaAsN active channel layer. 32. The method according to claim 31, wherein the step of forming an active channel layer of InGaAsN on the first layer comprises forming the active channel layer in the presence of Sb with negligible incoφoration of Sb in the quantum layer. 33. The method according to claim 31 , wherein the first layer of semiconductor material is a relatively thick undoped GaAs buffer layer formed on a semi-insulating GaAs substrate, and the second layer of the semiconductor material is a relatively thin undoped AlGaAs barrier layer, and further comprising the steps of forming a relatively heavily doped n-type AlGaAs layer on the barrier layer, and forming a relatively heavily doped GaAs cap layer on the relatively heavily doped n- type AlGaAs layer. 34. The method according to claim 33, further comprising the steps of: removing a portion of the GaAs cap layer so as to form isolated source and drain regions of the cap layer and to expose a portion of the relatively heavily doped n-type AlGaAs layer between the source and drain regions of the cap layer; forming source and drain electrode layers on the source and drain regions of the cap layer, respectively; and forming a gate electrode layer on the exposed portion of the relatively heavily doped n-type AlGaAs layer between the source and drain regions of the cap layer. 35. The method according to claim 34, further comprising the step of removing a portion of the relatively heavily doped n-type AlGaAs layer between the source and drain regions of the cap layer to form a recessed gate region on which is formed the gate electrode layer. 36. The method according to claim 35, wherein the source and drain electrode layers each comprise AuGeNi and the gate electrode layer comprises TiPtAu. 37. The method according to claim 31, wherein the first layer of semiconductor material is a relatively thick undoped GaAs buffer layer formed on a semi-insulating GaAs substrate, and the second layer of semiconductor material is a relatively thin undoped GalnP barrier layer, and further comprising the steps of forming a relatively heavily doped n-type GalnP layer on the barrier layer, and forming a relatively heavily doped GaAs cap layer on the relatively heavily doped n- type GalnP layer. 38. The method according to claim 37, further comprising the steps of: removing a portion of the GaAs cap layer so as to form isolated source and drain regions of the cap layer and to expose a portion of the relatively heavily doped n-type GalnP layer between the source and drain regions of the cap layer; forming source and drain electrode layers on the source and drain regions of the cap layer, respectively; and forming a gate electrode layer on the exposed portion of the relatively heavily doped n-type GalnP layer between the source and drain regions of the cap layer. 39. The method according to claim 38, further comprising the step of removing a portion of the relatively heavily doped n-type GalnP layer between the source and drain regions of the cap layer to form a recessed gate region on which to form the gate electrode layer. 40. The method according to claim 39, wherein the source and drain electrode layers each comprise AuGeNi and the gate electrode layer comprises TiPtAu.

Inventors: WANG WEN I, WANG, WEN, I.
Applicants: UNIV COLUMBIA, THE TRUSTEES OF COLUMBIA UNIVERSITY IN THE CITY OF NEW YORK
Application year: 2000
Main classification: H01L29
IPC codes: H01L21, H01L29, H01L33, H01S5