SYSTEM AND METHOD FOR ADDRESS BROADCAST SYNCHRONIZATION USING A PLURALITY OF SWITCHES

Abstract: A system and method providing address broadcast synchronization using multiple switches. The system for concurrently providing addresses to a plurality of devices includes a first switch and a second switch. The first switch is coupled to receive address requests from a first plurality of sources. The first switch is configured to output the address request from the first plurality of sources. The second switch is coupled to receive address requests from a second plurality of sources. The second switch is configured to receive the address request from the first plurality of sources from the first switch. The second switch is further configured to delay the address request from the second plurality of sources prior to arbitrating between ones of the address request from the second plurality of sources and ones of the address request from the first party of sources received from the first switch. The second switch selects a selected address request, and the first and the second switch are further configured to broadcast concurrently a corresponding address to the selected address request. A method is also contemplated for concurrently providing addresses to a plurality of devices. A method of arbitrating in a first switch and a second switch between requests to the first switch and the second switch is disclosed where the arbitrated outcomes in both the first switch and the second switch are identical.

Description: TITLE: SYSTEM .AND METHOD FOR ADDRESS BROADCAST SYNCHRONIZATION USING A PLURALITY OF SWITCHES BACKGROUND OF THE INVENTION 1 Field of the Invention This invention relates to cache synchronization and more particularly to address broadcast synchronization to a plurality of potentially responding devices 2 Description of the Relevant Art Maintaining cache coherency in an N-way system, where N is the number of processors in the system, is essential In a system where JN IS small (N < 4), the address buses of all cacheable devices may be physically connected together Therefore, all cacheable devices may see a cache miss address simultaneously On the other hand, when a system of N is large (N > 4), it becomes electrically unfeasible to connect the address buses of all cacheable devices together One approach for achieving cache coherency m a system with large N, is by broadcastmg the cache miss addresses to all cacheable devices simultaneously, through an address broadcast network The address broadcast network has an address-in and an address-out connection to each of the cacheable devices When a device sends a cache miss address to the address broadcast network, the address gets buffered, and then broadcast to all devices concurrently so that all devices may check or update their tags appropπately One problem with building an address network m hardware for large systems (N > 4) is that one needs a very large pm count ASIC (Application Specific Integrated Circuit) to accommodate all address-ms and address- outs for all cacheable devices to mamtain address synchronization The expense of building a large pm count ASIC to accommodate all address-ms and all address-outs for all cacheable devices limits this solution to only a very small number of computer systems Another possible solution ts to slice the address network into X (X>1) slices for a small ASIC solution The problem with address slicing is that usmg typical request and grant flow control techniques between address slices to mamtam address synchronization requires a computer system performance degradation that is unacceptable What is needed is a mechanism for achieving synchronization between address network slices without substantial performance degradation The request and grant flow control technique used should require a minimum number of control signals passing between each switch SUMMARY OF THE INVENTION The problems outlmed above are m large part solved by a system and method providmg address broadcast synchronization usmg multiple switches Each switch may be an application specific mtegration circuit (ASIC) or a separate switchmg device. By dividing address requests between more than one switch, addresses may be broadcast concurrently to a plurality of devices, which may advantageously provide for a higher system performance at a lower cost In one embodiment the svstem for concurrently providing addresses to a plurality of devices includes a first switch and a second switch The first switch is coupled to receive address requests from a first plurality of sources The first switch is configured to output the address request from the first plurality of sources The second switch is coupled to receive address requests from a second plurality of sources The second switch is configured to recen e the address request from the first plurality of sources from the first switch The second switch is further configured to delav the address request from the second plurality of sources prior to arbitrating between ones of the address request from the second plurality of sources and ones of the address request from the first party of sources received from the first switch The second switch selects a selected address request and the first and the second switch are further configured to broadcast concurrently a corresponding address to the selected address request A method is also contemplated, in one embodiment, for concurrently providing addresses to a plurality of devices In one embodiment, the method comprises receiving at a first switch a first address and a corresponding first request from a first device The method receives at a second switch a second address and a corresponding second request from a second device, with the first switch being different from the second switch The method transfers the second address and the corresponding second request to the first switch The method delays the corresponding first request in the first switch The method arbitrates in the first switch between the corresponding first request and the corresponding second request but rather the first address or the second address will comprise a first transmission The method concurrently broadcasts to a plurality of devices the first transmission from the first switch and the first transmission from the second switch where the first transmission from the first switch and the first transmission from the second switch are identical In another embodiment, a system for concurrently providing addresses to a plurality of devices includes a first switch and a second switch The first switch is coupled to receive address requests from a first plurality of sources The first switch is configured to output the address request from the first plurality of sources The second switch is coupled to receive address requests from a second plurality of sources The second switch compπses a broadcast buffer, an mcommg buffer, a delay circuit, and a broadcast arbiter The broadcast buffer is coupled to receive addresses of the address requests from the second plurality of sources The mcommg buffer is coupled to receive addresses of the output of the address requests from the first plurality of sources from the first switch The delay circuit is coupled to receive the address requests from the second plurality of sources The delay circuit is configured to delay the address requests from the second plurality of sources for a predetermined length of tune The broadcast arbiter is coupled to arbitrate between ones of the address request from the second plurality of sources and ones of the output of the address request from the first plurality of sources from the first switch for a selected address request The first switch and the second switch are further configured to broadcast concurrently a corresponding address to the selected address request selected m the broadcast arbiter In still another embodiment, a method of arbitrating m a first switch and a second switch between requests to the first switch and the second switch is disclosed The method compπses tracking which switch was most recently selected and tracking which switch is next to be selected In response to a reset, the method selects the first switch and mdicates that the second switch is next to be selected In response to only a local request to the first switch or only a remote request to the second switch, the method selects the first switch and indicates that the first switch is next to be selected In response to only a local request to the second switch or only a remote request to the first switch, the method selects the second switch and mdicates that the second switch is next to be selected In response to both a local request and a remote request concurrently, the method selects the switch which was not most recently selected, and the method mdicates that the switch not most recently selected will be the next to be selected Otherwise, the method selects the first switch and indicates the switch most recently selected as the next to be selected BRIEF DESCRIPTION OF THE DRAWINGS Other objects and advantages of the mvention will become apparent upon reading the following detailed descπption and upon reference to the accompanymg drawings in which Fig 1 is a block diagram of an embodiment of a computer system including two switches that concurrently provide addresses to a plurality of devices, Fig. 2 is a block diagram of an embodiment of the two switches shown m Fig 1, and Figs 3A and 3B are a flowchart of an embodiment of a method for arbitrating m a first switch and a second switch between request to the first switch and the second switch While the mvention is susceptible to vanous modifications and alternative forms, specific embodiments thereof are shown by way of example m the drawings and will herem be described m detail It should be understood, however, that the drawings and detailed descπption thereto are not mtended to limit the mvention to the particular form disclosed, but on the contrary, the mtention is to cover all modifications, equivalents and alternatives falling within the spiπt and scope of the present mvention as defined by the appended claims DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Similar features are designed herem usmg identical reference numerals. It is noted that the use of a reference numeral with an additional letter may designate a particular one of a group that may referenced as a while with the reference numeral by itself Fig. 1 - Computer System Including Two Switches Fig 1 is a block diagram of a computer system including two switches, switch 110A and switch 110B. As shown, the computer system mcludes CPUs 115A-115H, mput and output devices (I O) 120A-120D, and memones 125A-125D. Data signals beginning with a P have a processor 115 as a destmation, and data signals beginning with an I/O have an I/O device 120 as a destination Switches 110A and HOB are shown receiving mput from vanous groupmgs of the processors 115 and the I/O devices 120. The switches 110A and HOB are also shown outputtmg signals to vanous ones of the processors 115, the I/O devices 120, and to the memories 125 A plurality of processors (CPUs) 115A-115H (eight as shown), each receives an mput, preferably addresses, appropπately referenced as P0-P7. Each of the processors 115A-115H outputs an output, preferably an address and an address request, such as an address request packet, to one of the two switches 110A and HOB As shown, switch 110A also accepts address request packets from I/O device 120A and I/O device 120B Also as shown, switch HOB accepts address request packets from I O device 120C and I O device 120D Switch 110A outputs an output signal, preferably address signals, to the CPUs 115A-115D, the I O devices I O0-I O1, and memones 125A-125B Switch HOB outputs an output signal, preferably address signals, to processors 115E- 115H I'O devices I/02-I/03, and memories 125C-125D Switch 1 10A and switch HOB also exchange data preferably includmg addresses and address requests It is noted that while a particular number of processors 115, I/O devices 120 and memories 125 are illustrated any number of processors, I/O devices, and/or memories or other devices are contemplated It is also noted that while unidirectional data paths are illustrated, bi-directional data paths mav also be used as desired Fig 2 - Address Broadcast Synchronization Switches Fig 2 is a block diagram of one embodiment of the switches 110A and 11 OB As shown, each switch 110 mcludes a plurality of input FIFOs (First-In, First Out buffers) 205, a request arbiter 215, an mput multiplexer (MUX) 210 a broadcast FIFO 225, an incoming FIFO 230, a delay circuit 235 a broadcast arbiter 240 and an output MUX 245 The switches 110 exchange output requests from their respective request arbiters 215 and output addresses from their respective input MUXes 210 As illustrated, switch 110A accepts addresses P0-P3 and I/O0-I O1, as well as address requests P0_req- P3_req and I/O0_req and I/01_req Switch 110A outputs address signals P0-P3, I/O0-I/O1, and M0-M1 Each mcommg address P0-P3 and I O0-I/O1 is received mto an mput FIFO 205A-205F The address requests that conespond to the addresses received m the mput FIFOs 205 A-205F are received at a request arbiter 215 A In the prefened embodiment, the request arbiter 215A is a round-robin arbiter, although any other means of arbitration may be used as desired for choosmg requests received by request arbiter 215A When the request arbiter 215A chooses (or arbitrates) for a particular address request, the request arbiter 215A controls the selection at mput MUX 210A with regard to the output of the mput FIFOs 205A-205F The selected address request is output as SW0_req to delay circuit 235 A The output of mput MUX 210A, shown as signal 220A, is provided to a broadcast FIFO 225 A It is noted that output signal 220A is also provided to switch 110B, and that the address request SW0_req is also provided to switch HOB Switch 11 OA is also coupled to receive the address request SWl req from switch 110B, as well as address output signal 220B Signal 220B is received at mcommg FIFO 230A As shown, broadcast FIFO 225A and mcommg FIFO 230A each output data to output MUX 245A, broadcast FIFO 225A as '0' (zero) and mcommg FIFO 230A as ' 1 ' (one) Address request SW0_req is delayed for a period of time in delay circuit 235A before bemg provided to broadcast arbiter 240A The penod of time of the delay may be a predetermined penod of time It is noted that m a preferred embodiment, the predetermined period of tune is equal to the time required for switch 110A to receive the address request SWl req and the address output signal 220B Broadcast arbiter 240A chooses (or arbitrates) between request SW0_req and request SWl_req The broadcast arbiter 240A controls the output of output MUX 245 A choosmg between '0' and T The output of output MUX 245 A, the selected address for the first transmission, is provided concurrently to vanous groups of the processors 1 15, I/O devices 120, and/or memories 125 through signals P0-P3, 1 O0-I/O1, and M0-M1 As illustrated, switch HOB accepts addresses P4-P7 and I/02-I/03, as well as address requests P4_req- P7_req and I/02_req and I/03_req Switch HOB outputs address signals P4-P7, I/02-I/03, and M2-M3 Each mcommg address P4-P7 and I/02-I 03 is received mto an mput FIFO 205G-205L The address requests that correspond to the addresses received m the mput FIFOs 205G-205L are received at a request arbiter 215B In the preferred embodiment, the request arbiter 215B is a round-robm arbiter, although any other means of arbitration may be used as desired for choosmg requests received by request arbiter 215B When the request arbiter 215B chooses (or arbitrates) for a particular address request, the request arbiter 215B controls the selection at input MUX 210B with regard to the output of the mput FIFOs 205G-205L The selected address request is output as SWl_req to delay cucuit 235B The output of mput MUX 210B. shown as signal 220B, is provided to a broadcast FIFO 225B It is noted that output signal 220B is also provided to switch 110A, and that the address request SWl_req is also provided to switch 110A Switch HOB is also coupled to receive the address request SW0_req from switch 110A, as well as address output signal 220A Signal 220A is received at incoming FIFO 230B As shown, broadcast FIFO 225B and incoming FIFO 230B each output data to output MUX 245B, broadcast FIFO 225B as ' 1 ' (one) and incoming FIFO 230B as '0' (zero) Address request SWl_req is delayed for a period of time m delay circuit 235B before being provided to broadcast arbiter 240B The period of tune of the delay may be a predetermined period of time. It is noted that m a preferred embodiment, the predetermined period of tune is equal to the time required for switch 11 OB to receive the address request SW0_req and the address output signal 220A Broadcast arbiter 240B chooses (or arbitrates) between request SW0_req and request SWl_req. The broadcast arbiter 240B controls the output of output MUX 245B choosmg between '0' and T The output of output MUX 245B, the selected address for the first transmission, is provided concurrently to vanous groups of the processors 115, I O devices 120, and/or memories 125 through signals P4-P7, 1/02-I/03, and M2-M3. It is noted that the delay circuits 235A and 235B may include any circuit that is configured to delay the output of a received signal. In one embodiment, a delay circuit 235 delays the received signal longer than the minimum time required to propagate the received signal through delay circuit 235. In another embodiment, delay circuit 235 mcludes one or more flip-flops. It is also noted that m vanous embodiments various mcommg and outgomg signals to and from switches 110A and 110B may be buffered at mput to the switch 110 and/or on output from the switch 110 Generally speakmg, the system of Fig. 1 operates as descnbed herem The first switch 110A is coupled to receive address requests from a first plurality of sources For example, one plurality of sources may be processors 115A-115D and/or I/O devices 120A-120B The first switch 110A is configured to output a received address request from the first plurality of sources The second switch HOB is coupled to receive address requests from a second plurality of sources. For example, the second plurahty of sources may mclude processors 115E-115H and/or I O devices 120C-120D. Switch 110B is also configured to receive the address request from the first plurality of sources from the first switch 110A. The second switch is further configured to delay internally address requests from the second plurality of sources. It is noted that the length of the delay may be predetermined, and is preferably equal m length of tune to the t me delay m receiving the address request from the first plurality of sources from the first switch. The second switch HOB is further configured to arbitrate between ones of the address requests from the second plurality of sources and ones of the address request from the first plurality of sources output from the first switch The arbitration between the address requests is to determine a selected address request. Once a selected address request has been selected, the first switch and the second switch are further configured to broadcast concunently the corresponding address to the selected address request. It is noted that the corresponding address will broadcast to any or all devices, mcludmg the CPUs 115A-115H, I/O devices 120A-120B, and memones 125A-125D. In one embodiment, the second switch HOB is further configured to output the address request from the second plurality of sources, and the first sw itch 110A is further configured to receiv e this request from the second plura rv of sources First switch 110A is further configured to delay internally the address request from the first plurality of sources The tune of the delay of the address request from the first plurahty of sources may be a predetermined length of time and is preferably a length of time approximately equal to the time required for the second switch 11 OB to provide the address request in the second plurality of sources to first s itch 110A The first switch is further configured to arbitrate between ones of the address request from the first plurality of sources and ones of the address requests from the second plurality of sources from the second switch The arbitration is to determine the selected address request, as noted above for the second switch HOB It is noted that the selected address provided bv the first switch 110A and the selected address provided by the second switch HOB are the same and are concuπently provided to the de\ ices as descnbed above Fig 3A - 3B — Arbitration by a Broadcast Arbiter Figs 3A and 3B illustrate a flowchart of an embodiment of a method for operating an arbiter, such as broadcast arbiters 240A and 240B The method tracks which switch was most recently selected and the method also tracks which switch is next to be selected At decision block 305, the method checks to see if reset has been asserted If reset has been asserted in decision box 305, then an output MUX selects output '0' (l e switch 110A) and the next granted switch will be the other switch (I e switch HOB) (step 310) If reset has not been asserted m decision block 305, then the method determines if only a local request has been made to the first switch 110A or only a remote request has been made to the second switch 110B m decision block 315 If only a local request has been made to the first switch 110A or only a remote request is made to the second switch 110B, then the method selects output MUX output '0' and the next granted switch will be the same switch (step 320) If there has not been only a local request to the first switch 110A or only a remote request to the second switch HOB, then the method moves to decision block 325 If only a local request has been made to the second switch 110B or only a remote request has been made to the first switch 110A m decision box 325, then the method selects output MUX output ' 1 ' and the next granted switch will be the same switch (step 330) If only a local request to the second switch HOB or only a local request to the first switch 110A has not been made m decision block 325, then the method moves to decision block 335 In decision block 335, if both a local request and a remote request have concuπently been made, and the current granted switch is switch 110A, then the output MUX selects T and the next granted switch is switch 110A (step 340) If in decision block 335 both the local request and remote request have been made concuπently but the current granted switch is not switch 0, then the method moves to decision block 345 In decision block 345, if both the local request and a remote request have been made concuπently and the current granted switch is switch HOB, then the output MUX selects '0' and the next granted switch is switch 110A (step 350) It is noted that m decision blocks 335 and 345, an affirmative decision is made m either case when a local request and a remote request have both been made concuπently In either case the selected output MUX output is to the switch not most recently selected and the indicated switch as the next granted switch is also the switch not most recently selected The default action when all decision blocks are negative, is for the outgomg MUX to select '0 and the next granted switch is the cuπent granted switch (step 355) In various embodiments, the switches 110A and HOB mav be application specific mtegrated circuits ASICO and ASIC1 In one embodiment. ASICO and ASIC1 are location strapped via jumpers It is noted that ASICO preferably will have a pull-up resistor, while ASIC1 preferably has a pull-down resistor, both of which get latched on reset to identify which is ASICO and which is ASIC1 Note that the priority toggles between the broadcast arbiters based on the switch that had the last request granted and the cuπent outstandmg request The method disclosed may advantageously ensure that both arbiters are synchronized to each other without a need for request/grant flow control mechanisms beyond the address and the coπespondmg address request that was initially received As an example of an embodiment of the operations of switches 110A and HOB, right after a reset, both processors 115A and 115E have an outstandmg address packet m the address network The P0 address packet is received m switch HOA's mput FIFO 205 A from processor 115A, whereas the P4 address packet is received and stored m switch HOB's mput FIFO 205G from processor 115E The request arbiter 215A m switch 110A will receive the P0 request associated with the address stored m mput FIFO 205 A Similarly, request arbiter 215B receives the P4_req address request associated with the P4 address stored m mput FIFO 205G Request arbiter 215A in switch 110A controls mput MUX 210A to output the address associated with mput signal P0 as output signal 220A, which is provided to broadcast FIFO 225A and to mcommg FIFO 230B Likewise, request arbiter 215B controls mput MUX 210B to output the address from P4 as output signal 220B Output signal 220B is provided to broadcast FIFO 225B and also to incoming FIFO 230A Concuπently with the addresses bemg routed from the mput FIFO 205 to the broadcast FIFOs 225 and mcommg FIFOs 230, switch 110A has asserted SW0_req lme mdicatmg the presence of an address from switch 110A m broadcast FIFO 225A and mcommg FIFO 230B As a finite amount of time is required for the address and the request lme to be provided from one switch 110 to the other switch 110 , m this case from switch 110A to switch 1 10B, signal SW0_req is first provided to a delay circuit 235 A, before bemg provided to broadcast arbiter 240A In the prefeπed embodiment, the delay circuit 235A delays the address request SW0_req by approximately an equal amount of tune as required for switch 110A to receive the address and coπespondmg address request from switch HOB In this embodiment, broadcast arbiter 240A receives notice that an address is present m the broadcast FIFO 225A concurrently with an address bemg available m the mcommg FIFO 230A The broadcast arbiter 240A chooses (or arbitrates) for pnonty between the SWO req and SWl_req The preferred arbitration method is descnbed above with respect to Figs 3A and 3B Broadcast arbiter 240A selects either '0' or ' 1 ' denoting the address from switch 110A or switch HOB, respectively, m controlling the output of the output multiplexer 245 A It is noted that smce SW0_req and SWl req are both required to cross from one switch to the other, the signals endure a delay, such as two clock cycles m one embodiment Therefore, each switch 110A and 110B delays the address request that it sends, SW0_req and SWl_req, respectively, to the broadcast arbiter 240 of the other switch by an equivalent tune penod of 2 clock cycles This delay ensures that the broadcast arbiters 240A and 240B m each switch 110A and HOB receive the address request concuπently Switch 1 10A has the PO address placed in its broadcast FIFO 225 A and the P4 address placed in mcommg FIFO 230A Switch 110B has the PO address placed in its mcommg FIFO 230B and P4 packet placed m broadcast FIFO 225B At this time broadcast arbiter 240A has received address request SW0_req and address request SWl_req, whereas broadcast arbiter 240B has likewise received address request SW0_req and address request SWl_req The arbitration method described above with respect to Figs 3A and 3B illustrates a prefeπed embodiment of how the broadcast arbiter 245 works for each address request that it receives After a reset the last granted switch defaults to switch 11 OA, so that switch 11 OA broadcast arbiter now has the highest priority When the broadcast arbiter 240A has highest priority, then both broadcast arbiter 240A and broadcast arbiter 240B will select the '0' of the multiplexer 245B It is noted that both broadcast arbiter 240A and broadcast arbiter 240B are at decision block 345 of Fig 3B Both a local request and a remote request have been received and the cuπent granted switch is switch HOB (the default upon a reset), therefore the output MUXes 245A and 245B both select '0' and the next granted which will be switch 110A (step 350) Thus, the address from P0 is provided as output 250A and output 250B. concuπently on address lmes P0-P7, 1/O0-I/O3, and M0-M3 Contmumg, at decision block 325, as the request is now only the request from switch 1110B, the output MUXes 245 will select ' 1 ' and the next granted will be switch HOB (step 330) It is noted that broadcast arbiter 240A and broadcast arbiter 240B, following an arbitration method similar to that disclosed m Figs 3A and 3B, make selections between local and remote requests which are identical m all cases It is also noted the broadcaster arbiter 240A knows that upon a reset that it will have pnonty just as broadcast arbiter 240B knows that after a reset it will not have pnonty Numerous vanations and modifications will become apparent to those skilled m the art once the above disclosure is fully appreciated It is mtended that the following claims be interpreted to embrace all such variations and modifications

Claims: WHAT IS CLAIMED IS: 1 A system for concuπently providing addresses to a plurality of devices, comprising a first switch coupled to receive address requests from a first plurality of sources, wherein said first switch is configured to output said address requests from said first plurality of sources, and a second switch coupled to receive address requests from a second plurality of sources, wherem said second switch is configured to receive said address requests from said first plurality of sources from said first switch, wherem said second switch is further configured to delay said address requests from said second plurality of sources, wherem said second switch is further configured to arbitrate between ones of said address requests from said second plurality of sources and ones of said output of said address requests from said first plurality of sources from said first switch for a selected address request; and wherein said first switch and said second switch are further configured to broadcast concuπently a coπespondmg address to said selected address request 2 The system of claim 1, wherem said second switch is further configured to output said address requests from said second plurality of sources, and wherem said first switch is further configured to delay said address requests from said first plurality of sources, wherem said first switch is further configured to arbitrate between ones of said address requests from said first plurality of sources and ones of said address requests from said second plurality of sources from said second switch for said selected address request. 3 A system for concuπently providmg addresses to a plurality of devices, compnsmg: a first switch coupled to receive address requests from a first plurahty of sources, wherem said first switch is configured to output said address requests from said first plurality of sources; and a second switch coupled to receive address requests from a second plurality of sources, wherem said second switch comprises: a broadcast buffer coupled to receive addresses of said address requests from said second plurality of sources; an mcommg buffer coupled to receive addresses of said output of said address requests from said first plurality of sources from said first switch; a delay circuit coupled to receive said address requests from said second plurality of sources, wherem said delay circuit is configured to delay said address requests from said second plurality of sources for a predetermined length of tune; a broadcast arbiter coupled to arbitrate between ones of said address requests from said second plurality of sources and ones of said output of said address requests from said first plurality of sources from said first switch for a selected address request; wherem said first switch and said second switch are further configured to broadcast concuπently a coπespondmg address to said selected address request m said broadcast arbiter. 4 The system of claim 3, wherem said second switch is further configured to output said address requests from said second plurality of sources wherem said first switch further comprises a first broadcast buffer coupled to receive addresses of said address requests from said first plurality of sources a first incoming buffer coupled to receive addresses of said output of said address requests from said second plurality of sources from said second switch, a first delay circuit coupled to receive said address requests from said first plurality of sources wherem said delay circuit is configured to delay said address requests from said first plurality of sources for a first predetermined length of tune, and a first broadcast arbiter coupled to arbitrate between ones of said address requests from said first plurality of sources and ones of said output of said address requests from said second plurality of sources from said second switch for said selected address 5 The system of claim 4, wherem said first predetermined length of time coπesponds approximately to said length of time for said addresses of said output of said address requests from said second plurality of sources from said second switch to arnve at said first mcommg buffer 6 The system of claim 5, wherem said predetermined length of tune and said first predetermined length of time are approximately equal 7 The system of claim 4, wherem said first switch further compnses a plurality of first mput buffers coupled to receive said addresses of said address requests from said first plurality of sources, a first mput multiplexer coupled to receive said addresses of said address requests from said plurality of first mput buffers, and wherem said first mput multiplexer is further configured to output a first selected mput address to said first broadcast buffer, and a first request arbiter coupled to receive said coπespondmg request addresses of said address requests from said first plurality of sources, wherem said first request arbiter is configured to arbitrate for said first selected mput address, and wherem said first request arbiter is further configured to control said first mput muthplexer to select said first selected mput address, wherem said first request arbiter is further configured to output said coπespondmg request associated with said first selected mput address to said first delay circuit 8 The system of claim 3, wherem said predetermined length of time coπesponds approximately to a length of rune for said addresses of said output of said address requests from said first plurality of sources from said first switch to arnve at said mcommg buffer 9 The system of claim 3, wherein said second switch further comprises a plurality of mput buffers coupled to receive said addresses of said address requests from said second plurality of sources an mput multiplexer coupled to receive said addresses of said address requests from said plurality of input buffers, and wherem said mput multiplexer is further configured to output a selected input address to said broadcast buffer, and a request arbiter coupled to receive said coπespondmg request addresses of said address requests from said second plurality of sources, wherem said request arbiter is configured to arbitrate for said selected input address, and wherem said request arbiter is further configured to control said mput muthplexer to select said selected mput address, wherein said request arbiter is further configured to output said coπesponding request associated with said selected input address to said delay circuit 10 The system of claim 3, wherein said plurality of devices mcludes one or more processors and one or more memones 11 The system of claim 10, wherem said plurality of devices further mcludes one or more input/output devices 12 A method for concuπently providmg addresses to a plurality of devices, the method compnsmg receivmg at a first switch a first address and a coπespondmg first request from a first device, receivmg at a second switch a second address and a coπespondmg second request from a second device, wherem said second switch is different from said first switch, transferring said second address and said coπespondmg second request to said first switch, delaymg said coπespondmg first request m said first switch, arbitratmg m said first switch between said coπespondmg first request and said coπespondmg second request for whether said first address or said second address will compπse a first transmission, and concuπently broadcastmg to a plurality of devices said first transmission from said first switch and said first transmission from said second switch, wherein said first transmission from said first switch and said first transmission from said second switch are identical 13 The method of claim 12, further compnsmg transferring said first address and said coπespondmg first request to said second switch, delaymg said coπespondmg second request m said second switch, and arbitrating m said second switch between said coπespondmg first request and said coπespondmg second request for whether said first address or said second address will compnse said first transmission 14. The method of claim 13, further compnsmg buffering said first address at said first switch prior to said transfemng said first address; and buffermg said second address at said second switch prior to said transfemng said second address 15. The method of claim 13, further comprising: buffermg said first address at said first switch prior to said arbitratmg m said first switch; and buffermg said second address at said second switch prior to arbitratmg in said second switch 16. The method of claim 13, further compnsmg: buffermg said first address at said second switch prior to said arbitratmg m said second switch; and buffermg said second address at said first switch prior to arbitrating m said first switch. 17. The method of claim 13, further compnsmg: receivmg at said first switch another address and a coπespondmg another request from another device; buffermg said another address at said first switch pnor to said transferring said first address; and arbitratmg between said coπespondmg first request and said coπespondmg another request for whether said first address or said another address will be transfeπed first to said second switch. 18. The method of claim 17, further comprising: receivmg at said second switch an additional address and a coπespondmg additional request from an additional device; buffermg said additional address at said second switch pnor to said transferring said second address; and arbitratmg between said coπesponding second request and said coπesponding additional request for whether said second address or said additional address will be transfeπed first to said first switch. 19. The method of claim 13, wherem said delaymg said coπespondmg first request m said first switch includes delaying for approximately a length of time for said requests from said second switch to arnve at said first switch; and wherem said delaying said coπespondmg second request in said second switch includes delaying for approximately said length of time for said requests from said first switch to arnve at said second switch. 20. A system for concuπently providing addresses to a plurality of devices, the method compnsing: means for receivmg at a first switch a first address and a coπespondmg first request from a first device; means for receiving at a second switch a second address and a coπespondmg second request from a second device, wherem said second switch is different from said first switch; means for transferring said second address and said coπespondmg second request to said first switch; means for delaymg said coπesponding first request in said first switch; means for arbitratmg m said first switch between said coπespondmg first request and said coπesponding second request for whether said first address or said second address will comprise a first transmission; means for concuπently broadcasting to a plurality of devices said first transmission from said first switch and said first transmission from said second switch, wherem said first transmission from said switch and said first transmission from said second switch are identical. 21. The system of claim 20, further compnsmg: means for transferring said first address and said coπespondmg first request to said second switch; means for delaying said coπespondmg second request m said second switch; and means for arbitratmg in said second switch between said coπespondmg first request and said coπespondmg second request for whether said first address or said second address will comprise said first transmission. 22. The system of claim 21, wherem said means for delaying said coπespondmg first request m said first switch is configured to delay for approximately a length of time for said requests from said second switch to aπive at said first switch; and wherem said means for delaying said coπesponding second request m said second switch is configured to delay for approximately said length of time for said requests from said first switch to arnve at said second switch. 23. A method of arbitratmg m a first switch and a second switch between requests to said first switch and said second switch, the method compnsmg: tracking which switch was most recently selected; tracking which switch is next to be selected; m response to a reset, selecting the first switch; and indicting the second switch as next to be selected; m response to only a local request to said first switch or only a remote request to said second switch, selecting the first switch; and indicting the first switch as next to be selected; in response to only a local request to said second switch or only a remote request to said first switch, selecting the second switch; and indicting the second switch as next to be selected; in response to both a local request and a remote request concuπently, selecting a switch not most recently selected; and indicting the switch not most recently selected as next to be selected; otherwise, selecting the first switch; and indicting the switch most recently selected as next to be selected 24 The method of claim 23. further compnsmg indicating the switch next to be selected as the switch most recently selected upon a rising edge of a clock

Inventors: MARMASH NASER H, MARMASH, NASER, H.
Applicants: SUN MICROSYSTEMS INC, SUN MICROSYSTEMS, INC.
Application year: 2000
Main classification: G06F13
IPC codes: G06F15