DIGITAL DELAY LOCKED LOOP WITH OUTPUT DUTY CYCLE MATCHING INPUT DUTY CYCLE

Abstract: An I/O port can synchronize the transmission of data on both the rising edge and falling edge of a system clock signal (SCLK) by matching the duty ratio of the internal clock (MCLK) with the duty ration of the system clock SCLK. This is accomplished by individually delaying both the rising edge and falling edge of the input clock SCLK. By individually delaying both the rising edge and falling edge, the rising edge and falling edge of the system clock SCLK and internal clock MCLK are synchronized. This synchronization ensures that data can be accurately transmitted on both edges of the clock signal. To accomplish this, an I/O port for a CPU has an input port configured to receive a system clock signal, and a digital delay locked loop configured to synchronize a rising edge of an internal clock signal with a rising edge of the received system clock signal and configured to synchronize a falling edge of the internal clock signal with a falling edge of the received system clock signal. The digital delay locked loop (DLL) includes a phase generator configured to receive the system clock signal and to generate a rising edge signal indicative of the rising edge of the system clock signal and to generate a falling edge signal indicative of the falling edge of the system clock signal. The DLL may also include a first series of delay stages configured to delay the rising edge signal and a second series of delay stages configured to delay the falling edge signal, and a clock generator configured to create the internal clock signal from the delayed rising edge signal and delayed falling edge signal. One or more second clock generators configured to create intermediate signals may also be included. The intermediate signals from these second clock generators are used to determine whether the first series of delay stages is delaying the rising or falling edge signals by an excessive amount.

Description: DIGITAL DELAY LOCKED LOOP WITH OUTPUT DUTY CYCLE MATCHING INPUT DUTY CYCLE Background of the Invention Field of The Invention The present invention relates to a computer processor and, more particularly, to a computer processor having a digital delay locked loop in an input/output port interfacing the computer processor to a system bus. Related Art A central processing unit or digital signal processor is the portion of a computer that receives and executes instructions. The term "CPU" as used herein will be defined to include both central processing units and digital signal processors. In modern desktop computers, the CPU is formed on a single chip of silicon and may be provided with a variety of functional units and memory that cooperate to execute instructions. Execution of instructions in the CPU is timed by a clock, called herein the core clock. Depending on the type of instruction set running on the CPU, it may be desirable to have the core clock run at a relatively fast rate. In modern CPUs, core clocks may run as fast as 1000 MHZ. The CPU communicates with other components of the computer system, such as external memory units or disc drives, graphics accelerators, and any number of other known components. Communication with these components takes place over a system bus, such as a peripheral component interconnect (PCI) bus. Data transfers over the system bus, called transactions, are timed by a system clock. The system clock is generally different in frequency than the core clock. Typical values for the system clock are currently 66 MHZ and 100 MHZ, although the invention(s) disclosed herein and discussed below are not limited by any particular values of the core clock or system clock. A typical clock signal is a periodic square wave such as the signal illustrated in figure 4. As shown in figure 4, a clock signal has one of two states: high and low. The transition of the signal from the low level to the high level is called the "rising edge," and the transition of the signal from the high level to the low level is called the "falling edge." A complete clock cycle includes both the high portion of the signal and the low portion of the signal. The ratio of the amount of time the clock signal is high to the amount of time the clock signal is low is called the "duty cycle"; duty cycle = hi/low. An alternative way of measuring the duty cycle is as the ratio of either the amount of time of the high or low portion of the signal to a complete clock cycle time; duty cycle = hi/clock cycle, or duty cycle = low/clock cycle. Since the core clock and system clock may be operating at different rates, transmission of data between the CPU and system bus is not synchronized and cannot be passed directly. To interface the CPU and system bus, the CPU is provided with an input/output port (I/O port) that has a section running at the same rate as the system clock and circuitry for formatting the data to be read by the CPU at the core clock rate. An exemplary CPU containing a core interfaced to a system bus in a computer environment is illustrated in figure 1. As illustrated, the CPU 10 has a core 12 and an I/O port 14. The CPU 10 in figure 1 is connected to the system bus 16 to enable it to communicate with the memory 18 and other components 20. Since the I/O port 14 is interfacing with the system bus 16, it is necessary for the I/O port to have an internal clock that is operating at the same rate as the system clock. Also, if the internal clock has the same phase as that of the system clock, the CPU does not need to delay output data prior to writing the output data to the bus for access by the other components of the computer system. One easy way to ensure that the internal clock of the I/O port 14 is operating at the same rate as and in phase with the system clock is to provide the I/O port 14 with the system clock. As used herein, the system clock outside of the CPU will be referred to as SCLK and the internal clock of the I/O port 14 will be referred to as MCLK. Unfortunately, inputting the system clock to the I/O port 14 of the CPU 10 results in a phase delay between SCLK and MCLK. One conventional way to synchronize SCLK and MCLK is to use a digital delay locked loop (DLL) to eliminate this phase delay. A known I/O port using a DLL to synchronize MCLK with SCLK is illustrated diagrammatically in figure 2. As shown in figure 2, the I/O port 14 includes a DLL 22 to synchronize MCLK with SCLK, as well as known I/O circuitry 24 configured to interface the CPU 10 with the system bus 16. The transformation from the system clock SCLK to the internal system clock MCLK may be represented diagrammatically as: SCLK→DLL→MCLK Figure 3 illustrates a conventional DLL 22. As shown in figure 3, the DLL 22 receives clock signals on line SCLK, delays the input clock signals using a delay line 26 and outputs delayed clock signals on line MCLK. In this instance, the signals on line SCLK correspond to the system clock SCLK and the signals on line MCLK correspond to the system clock MCLK. Thus, the system clock MCLK has the same rate as that of the input system clock SCLK, but has been delayed in phase by the delay line 26. By adjusting the phase delay, it is possible to insure that MCLK is in phase with SCLK. To adjust the delay, the DLL 22 has a phase comparator 28 with inputs connected to SCLK and MCLK and an adjustor 30. The comparator 28 compares the input and output phases and communicates the result to the adjustor 30. The adjustor 30 adjusts the delay so that the system clock SCLK and internal clock MCLK are synchronized. The rate at which data is transferred over the system bus 16 may be a limiting factor in the rate at which the CPU 10 is able to execute instructions or at which the computer system as a whole can operate. To increase the data transfer rate, the size or speed of the system bus 16 may be increased, or the number of busses interconnecting the CPU 10 and memory 18 and components 20 may be increased. One common way of attempting to increase the speed of the system bus 16 is to try to transmit additional information during each clock cycle of the system clock SCLK. Conventionally, data is transferred only on the rising edge or the falling edge of the clock cycle. However, to increase the amount of data that may be transferred without increasing the rate of the system clock, it is possible to transfer data on both the rising edge and the falling edge of each clock cycle. Transmission of data in this manner, however, has been found to be less reliable than transmission of data on only one edge of the clock signal. Accordingly, what is needed is a method and apparatus for transmitting data accurately on both the rising edge and falling edge of a clock signal. Summary of the Invention The present invention relates to an I/O port that can synchronize the transmission of data on both the rising edge and falling edge of an input clock signal. Conventional DLLs receive the input system clock signal SCLK and form the signal MCLK by delaying either the rising edge or the falling edge of the signal SCLK by a predetermined amount. The other edge of the signal MCLK is arbitrarily formed by making an assumption about the duty cycle of the input signal SCLK. For example, if a conventional DLL delays the rising edge to form the output signal, the falling edge of the output signal would be formed by assuming that the input duty ratio is a number such as 0.5. If the duty ratio of the input signal is not 0.5, the falling edge will not be properly synchronized with the falling edge of the input signal. Also, the delay of a single delay line may be different for the rising edge and the falling edge. As the operation frequency is higher, this difference may become larger relative to the cycle time, and hence degrade performance even further. Thus, the inventors have found that if MCLK is formed by delaying the rising edge, the data transferred on the falling edge may not be synchronized properly during transmission between the CPU 10 and the system bus 16, and vice versa. Failure to synchronize transmission of data can result in data not being transmitted, or worse, being corrupted. This invention overcomes this source of error by providing a method and apparatus that can accurately transmit data on both the rising edge and falling edge of the clock signal. In one embodiment, this is accomplished by an I/O port that can synchronize the transmission of data on both the rising edge and falling edge of the input clock signal by individually delaying both the rising edge and falling edge. By individually delaying both the rising edge and falling edge, the rising edge and falling edge of the system clock SCLK and internal clock MCLK are synchronized. This synchronization ensures that data can be accurately transmitted on both edges of the clock signal. According to one aspect of this invention, an I/O port for a CPU has an input port configured to receive a system clock signal, and a digital delay locked loop configured to synchronize a rising edge of an internal clock signal with a rising edge of the received system clock signal and configured to synchronize a falling edge of the internal clock signal with a falling edge of the received system clock signal. In this aspect, the digital delay locked loop may include a phase generator configured to receive the system clock signal and to generate a rising edge signal indicative of the rising edge of the system clock signal and to generate a falling edge signal indicative of the falling edge of the system clock signal, a first series of delay stages configured to delay the rising edge signal, a second series of delay stages configured to delay the falling edge signal, and a clock generator configured to create the internal clock signal from the delayed rising edge signal and delayed falling edge signal. The digital delay locked loop may also include one or more second clock generators configured to create intermediate signals that may be used to determine whether the first series of delay stages is delaying the rising or falling edge signals by an excessive amount. Further, in this aspect the phase generator may be configured to generate a pair of rising edge signals indicative of the rising edge of the system clock signal and to generate a pair of falling edge signals indicative of the falling edge of the system clock signal. These pairs of signals may be complimentary. In this situation, the clock generator may be configured of four sets of transistors, each transistor of each of the sets being controllable by at least one of the rising edge signals or falling edge signals. According to anther aspect of this invention, a CPU, includes an I/O port configured to receive and transmit data on a rising edge and a falling edge of a system clock, the I/O port having circuitry configured to synchronize a rising edge of an internal clock with the rising edge of the system clock and to synchronize a falling edge of the internal clock with the falling edge of the system clock. According to yet another aspect of this invention, a digital delay locked loop having an output duty cycle matching an input duty cycle includes a phase generator to generate signals indicative of the input duty cycle, at least one delay line to delay the generated signals, and a clock generator to generate an output having the output duty cycle matching the input duty cycle. The digital delay locked loop may include one or more phase detectors and adjusters to provide an output signal for use in controlling the delay of the delay line. Where one phase detector and adjuster is used, the output signal may be used to control the delay line associated with both the rising edge and falling edge. Where more than one phase detector and adjuster are used, the output signals may be used to individually control the delay lines associated with the rising edge and falling edge. In another aspect of this invention, a method of delaying a signal includes delaying a rising edge of the signal to form a rising edge of an output signal and delaying a falling edge of the signal to form a falling edge of the output signal. In another aspect of this invention, a method of synchronizing transfer of data includes receiving an input clock signal, detecting a rising edge of the input clock signal, delaying the rising edge of the input clock signal to form a rising edge of an output clock signal, detecting a falling edge of the input clock signal, and delaying the falling edge of the input clock signal to form a falling edge of the output clock signal. Brief Description of the Drawings This invention is pointed out with particularity in the appended claims. The above and further advantages of this invention may be better understood by referring to the following description when taken in conjunction with the accompanying drawings, in which: figure 1 is a functional block diagram of a computer system illustrating a CPU connected via a system bus to a memory and components; figure 2 is a functional block diagram of an I/O port for use by the CPU of figure 1 ; figure 3 is a functional block diagram of a digital delay locked loop for use in the I/O port of figure 2; figure 4 is a diagram of a clock signal; figure 5 is a functional block diagram of a digital delay locked loop for use in the CPU of figure 1 according to a first embodiment of this invention; figure 6 is a functional block diagram of a delay element of the digital delay locked loop of figure 5; figure 7 is a schematical circuit diagram of a clock generator for use in the delay element of figure 6; figure 8 is a schematical circuit diagram of a delay stage for use in the delay element of figure 6; figure 9 is a timing diagram of signals in the delay stage of figure 8; figure 10 is a timing diagram illustrating signals in the delay element of figure 6; figure 11 is a functional block diagram of a digital delay locked loop for use in the CPU of figure 1 according to a second embodiment of this invention; and figure 12 is a functional block diagram of a delay element of the digital delay locked loop of figure 11. Detailed Description The present invention relates to an I/O port that is capable of synchronizing data transfer on both the rising edge and falling edge of the input clock signal SCLK. In one embodiment, this is accomplished by using a digital delay locked loop to delay the system clock signal SCLK in such a manner that the output duty cycle matches the input duty cycle. In this embodiment, the DLL delays both the rising edge and falling edge of the input signal individually, thus ensuring that both the rising edge and falling edge of the output signal are synchronized respectively with respect to the rising edge and falling edge of the input signal. One embodiment of a DLL 100 according to this invention is illustrated in figure 5. As shown in figure 5, the DLL 100 receives a clock signal (Clock In) at an input 102, and outputs a clock signal MCLK at an output 104. The DLL 100 has a delay line 106, illustrated in greater detail in figure 6, interposed between the input 102 and output 104 that serves to delay the input signals before providing the signals on the output 104. In the illustrated embodiment, the delay line delays the Clock In signal such that the Clock Out signal is delayed up to one full cycle from the Clock In signal. The DLL also includes a phase detector 108 configured to compare the phase of the input signals and output signals. To do this, the phase detector 108 is connected at a first input 110 thereof to the input of the DLL and is connected at a second input 112 thereof to the output of the DLL. In the illustrated embodiment, the phase detector 108 detects the phase delay between rising edges of the input wave forms. The phase detector 108 may alternatively detect the phase delay between falling edges of the input wave forms or may detect the phase delay according to other known methods. A delay 114 corresponding to the delay experienced by the system clock SCLK entering the CPU 10 is interposed between the output of the DLL 104 and the second input 112 to the phase detector 108. The delay experienced by the system clock SCLK entering the CPU is symbolized in figure five by phase delay 116. The amount of delay experienced by signals entering the CPU may be easily determined experimentally or computationally, and is relatively constant. By delaying the output signal using a phase delay 114 that will delay the signals in an amount equal to the amount of delay experienced by the input signals entering the CPU, it is possible to synchronize signals MCLK and SCLK. An adjuster 118 receives as its inputs, outputs from the phase detector 108, and adjusts the level of a voltage on line VC connected to delay line 106. By adjusting the voltage on line VC, the amount of delay experienced by signals traversing the delay line 106 may be adjusted as discussed in greater detail below. The adjuster 118 in the illustrated embodiment has a first capacitor 120 connected in parallel with series connected first current source 122 and first switch 124, between supply voltage VSS and line VC. The first switch 124 is controlled by a first output signal on line 126 of the phase detector 108. The first capacitor 120, first current source 122 and first switch 124 form an accumulator that serves to increase the voltage on line VC when the first switch 124 is closed. Preferably, the first switch 124 is a transistor (not shown) having its source connected to the output of current source 120, its drain connected to line VC and its gate connected to the first output 126 of the phase detector 108. The adjuster 118 in the illustrated embodiment also has a second capacitor 128 connected in parallel with series connected second switch 130 and second current source 132, between line VC and ground. The second switch 130 is controlled by a second output signal on line 134 of the phase detector 108. The second capacitor 128, second switch 130 and second current source 132 serve as an attenuator to decrease the voltage level on line VC when the second switch 130 is closed. Preferably, the second switch 130 is a transistor (not shown) having its source connected to the line VC, its drain connected to ground, and its gate connected to the second output 134 of the phase detector 108. Although one particular voltage regulator has been described in connection with formation of the adjuster, numerous other voltage regulators could be used. Indeed, any known voltage regulator controllable by the phase detector could be used in place of the described voltage regulator. Likewise, although the adjuster 30 has been described herein as a voltage adjuster, the adjuster 30 may be of any configuration suitable to adjustably control the delay line 106 in response to signals from the phase detector 28. Optionally, the adjuster 30 and the phase detector 28 may be formed integral such that the output of the combined phase detector 28 and adjuster 30 is used by the delay line 106 to control the phase delay produced by the delay line. MCLK tree is a clock tree that serves to distribute the clock signals to consumers on the chip. When the clock signals are distributed through metal lines on the chip, the delay may be different for each customer. Thus, for example, if one consumer received a clock signal with a different delay relative to the other consumers, the consumer would be operating out of phase with the others which could degrade the performance of the processor. MCKL tree thus is a set of metal wires and clock buffers which are designed to provide clock signals with the same delay in every consumer location. The delay line 106 is illustrated in greater detail in figure 6. As shown in figure 6, delay line 106 receives the signal "Clock In" at its input 200 and outputs a delayed copy of the Clock In signal "Clock Out" at its output 202. The delay line 106 has three main components: a phase generator 204, a pair of series 206, 208 of delay stages 212a-f, 214a-f and a clock generator 210. Each of these components will be discussed briefly, then treated in greater detail in connection with figures 7-9. The phase generator 204 receives the input clock and outputs two complimentary pairs of signals pi , p2 and p3, p4. The two sets of signals are used by the system to enable both the rising edge and the falling edge of the Clock In signal to be delayed independently, thus ensuring that the duty cycle of the output signal MCLK will match the duty cycle of the input signal. In this context, the term "match" will mean closely resembling, such that the signals MCLK and SCLK are sufficiently synchronized that data may be transmitted between the CPU and bus on both the rising edge and falling edge of the clock signal. By matching the duty cycle of the output signal MCLK to the duty cycle of the input signal SCLK, data may be accurately transferred on both the rising edge and falling edge of the system clock SCLK. In this embodiment, as shown in figure 10, signal pi is related to the Clock In signal in that signal pi changes from high to low or from low to high on each rising edge of the Clock In signal. Signal p2, like signal pi, changes from high to low or from low to high on each rising edge of the Clock In signal but is 180 degrees out of phase with respect to signal pi . Thus, when signal pi changes from low to high, signal p2 changes from high to low and vise versa. In figure 10, signal pi is represented by a solid line and signal p2 is represented by a dashed line. The second pair of complimentary signals, p3 and p4, are similar to the first pair of complementary signals pi and p2, but change from high to low or from low to high on each falling edge of the Clock In signal. In figure 10, signal p3 is represented by a solid line and signal p4 is represented by a dashed line. The first series 206 of delay stages 212a-f receives as inputs the first pair of complimentary signals pi and p2, and outputs a first delayed pair of complimentary signals dl and d2. Similarly, the second series of delay stages 208 receives as inputs the second pair of complimentary signals p3 and p4, and outputs a second pair of complimentary signals d3 and d4. In the illustrated embodiment, the first series 206 of delay stages 212a-f includes six delay stage 212a-f and the second series 208 of delay stages 214a-f includes six delay stage 214a-f. Although six delay stages are used in the illustrated embodiment, the invention is not limited to delay lines employing six delay stages. Rather, any appropriate number of delay stages may be used given the constraints and requirements of the system. Additionally, although in this embodiment the same number of delay stages are used in each delay line, different numbers of delay stages may be used for each delay line. The circuitry comprising an exemplary delay stage is illustrated in more detail in figure 8, and will be discussed in greater detail below. By using two separate delay lines, one for delaying the rising edge and one for delaying the falling edge of the Clock In signal, it is possible to synchronize the rising edge and the falling edge of the signal MCLK independently with the rising edge and falling edge respectively of the input signal SCLK to enhance data transfer accuracy. The clock generator 210 receives as its inputs the delayed first and second pairs of complimentary signals dl, d2 and d3, d4, and outputs the signal Clock Out. Circuitry comprising an exemplary clock generator is illustrated in figure 7 and will be discussed in greater detail below. The delay line 106 optionally includes additional clock generators 216, 218, 220, that may be used to ensure that the delay line 106 is only delaying the Clock In signal one cycle and not multiple cycles, as discussed below. Although three additional clock generators are used in this embodiment, any number of additional clock generators may be used. The additional clock generators 216, 218 and 220 in this embodiment are of common configuration to the clock generator 210. In other embodiments, the clock generators 216, 218, 220 may be differently configured, and indeed may be of any configuration suitable for generating an indication of the phase of the delay line at the point to which they are connected. In this embodiment, clock generator 216 has its inputs connected to outputs of the first delay stage 212a of the first series of delay stages 206 and to the outputs of the first delay stage 214a of the second series of delay stages 208. Similarly, the clock generator 218 has its inputs connected to outputs of the fourth delay stage 212d of the first series of delay stages 206 and to the outputs of the fourth delay stage 214d of the second series of delay stages 208. Finally, the clock generator 220 has its inputs connected to outputs of the fifth delay stage 212e of the first series of delay stages 206 and to the outputs of the fifth delay stage 214e of the second series of delay stages 208. Clock generators 216, 218 and 220 generate signals X, Y and Z, respectively. These signals are illustrated in figure 10. As shown in figure 10, signal X is delayed from the Clock In signal by a first amount, signal Y is delayed from the Clock In signal by a second amount and signal Z is delayed by the Clock In signal by a third amount. In this embodiment, signal X is delayed by the delay of the first delay stage 212a, 214a, signal Y is delayed by the sum of the delays of the first through fourth delay stages 212a-d, 214a-d and the signal Z is delayed by the sum of the delays of the first through fifth delay stages 212a-e and 214a-e. As shown in figure 10, the delay of signals X, Y and Z all do not exceed one period of the Clock In signal. Accordingly, it can be determined that the delay line 106 is appropriately delaying the incoming signal for at most up to one period. By contrast, if the delay line was delaying the Clock In signal by more than one period, the signals X, Y and Z would be much further apart than illustrated delays, and signals X, Y and Z would not all fall within a single clock cycle of the Clock In signal. Thus, provision of additional clock generators can be used to ensure that the input clock signal is only delayed by at most up to a single clock period. Although this embodiment uses three additional clock generators to ensure the input signal is only delayed by at most one clock cycle, the invention is not limited in this regard. The phase detector 108 of figure 5 is configured to receive as inputs signals on lines X, Y and Z and determine the number of periods being delayed in a known manner. If signals on lines X, Y and Z are not within one cycle of the Clock In signal, the phase detector recognizes that the delay is too great and rapidly adjusts the delay. To do this, signals on the outputs 126, 134 are adjusted so that the delay line 106 draws constant current from the capacitors 120, 128. Conversely, if the signals on the lines X, Y and Z are within one clock cycle, but the feedback clock signal input at input 110 is early by more than 0.5 ns, the capacitors 120, 128 are charged with a constant current to rapidly adjust the delay. If the clock signal input to the phase detector 108 at input 110 is early by less than 0.5 ns, the capacitors 120, 128 are charged by a charge pulse. Finally, if the feedback clock input to the phase detector 108 at the input 110 is late by less than 0.5 ns, the capacitors 120, 128 are discharged by a charge pulse. Using charge and discharge pulses allow the delay line 106 to be finely adjusted. Figure 7 illustrates an exemplary circuit that may be used to form clock generator 210, 216, 218 or 220. The description which follows will refer to clock generator 210. This description applies equally to commonly configured clock generators 216, 218 and 220 as well. As shown in figure 7, the clock generator 210 receives as its inputs the delayed first and second pairs of complimentary signals dl , d2 and d3, d4, and outputs the Clock Out signal on line clk_out. Signals dl and d2 are input to a differential amplifier 230 with Schmidt trigger inputs to produce internal signals on lines xl and x2. Likewise, signals d3 and d4 are input to a differential amplifier 232 with Schmidt trigger inputs to produce internal signals on lines yl and y2. Internal signals on lines xl , x2, y 1 , y2 are selectively input to four groups of four transistors, which together function to generate the output clock signal on line clk out. Since signals on lines xl and x2 are complimentary, the signal on line xl is low when the signal on line x2 is high, and vice versa. Likewise, since the signals on lines yl and y2 are complimentary, the signal on line yl is low when the signal on line y2 is high, and vice versa. Accordingly, the following table contains all possible logical states for the signals on lines xl, x2, yl and y2: In each of these states, the clock generator 210 will generate a particular output on the line clk out. Specifically, as discussed in more detail below, the clock generator 210 will generate a high output in state 2 and state 3 and will generate a low output in state 1 and state 4. Operation of the clock generator 210 and generation of the output signal on line clk out will now be discussed. Other clock generators may be used to generate the signal as well. Transistors Tl and T2 are p-type field effect transistors (FETs) connected in series between voltage V and line clk out. Specifically, transistor Tl has its source connected to voltage V its drain connected to node Nl and an its gate connected to line xl . Transistor T2 has its source connected to node Nl, its drain connected to line clk out, and its gate connected to line Y2. Since transistors Tl and T2 are p-type FETs, transistors Tl and T2 will both conduct when the signal on line xl is low and when the signal on line y2 is low. Thus, transistors Tl and T2 will both conduct in state 3, thus causing the signal output on line clk out to be high in state 3. Likewise, transistors T3 and T4 are p-type FETs connected in series between voltage V and line clk out. Specifically, transistor T3 has its source connected to voltage V its drain connected to node N2 and its gate connected to the gate of transistor T2, and hence to line y2. Transistor T4 has its source connected to node N2, its drain connected to line clk_out, and its gate connected to the gate of transistor Tl , and hence to line xl . Since both transistors T3 and T4 are p-type FETs, transistor T3 will conduct when the signal on line y2 is low and transistor T4 will conduct when the signal on line xl is low. Thus, transistors T3 and T4 will conduct under the same conditions that transistors Tl and T2 conduct. Accordingly, transistors T3 and T4 will both conduct in state 3, thus causing the signal output on line clk out to be high in state 3. The remaining transistors contained within figure 7 are interconnected and operate in a similar fashion. Specifically, transistors T5, T6, T7 and T8 are all p-type FETs, the pairs of which will conduct when the signal on line X2 is low and when the signal on line Yl is low. Transistors T9, T10, Tl 1 and T12 are all n-type FETs, the serially connected pairs of which will conduct when the signals on lines XI and Yl are hi. Finally, transistors T13, T14, T15 and T16 are all n-type FETs, the serially connected pairs of which will conduct when the signals on lines X2 and Y2 are high. The states in which the pairs of transistors will conduct are summarized in the table below: The circuit will also operate properly if all illustrated p-type FETs are replaced with n-type FETs and vice versa. Accordingly, the invention is not limited to the illustrated circuit. Operation of the clock generator will now be explained with additional reference to figure 10. As discussed above with respect to figure 6, the input clock signal clk in is used by the phase generator to generate signals pi, p2, p3 and p4. Signals pi and p2 are delayed to form signals dl and d2, and signals p3 and p4 are delayed to form signals d3 and d4. The delayed signals, as discussed above, are amplified by differential amplifiers to form signals xl, x2, yl, y2 respectively. Initially in figure 10, signal dl is low (xl=Low), signal d2 is high (x2=High), signal d3 is low (yl=Low) and signal d4 is high (y2=High). This corresponds to state 4. Since in state 4 transistors T13, T14, T15 and T16 conduct, line clk out is tied to ground resulting in a low signal on line clk_out. Next, signals dl and d2 change from low to high, and from high to low respectively. Thus, at this stage, signal dl= High (xl=High), signal d2=Low (x2=Low), signal d3=Low (yl=Low) and signal d4=High (y2=High). This corresponds to state 2, in which line clk_out is tied to voltage V. Next, signals d3 and d4 change from low to high, and from high to low respectively. Thus, at this stage, signal dl= High (xl=High), signal d2=Low (x2=Low), signal d3=High (yl=High) and signal d4=Low (y2=Low). This corresponds to state 1, in which line clk out is tied to ground. Next, signals dl and d2 change from high to low, and from low to high respectively. Thus, at this stage, signal dl= Low (xl=Low), signal d2=High (x2=High), signal d3=High (yl=High) and signal d4=Low (y2=Low). This corresponds to state 3, in which line clk out is tied to voltage V. Accordingly, the clock generator operates to convert the input delayed signals into an output clock signal. Since the rising edge is delayed separate from the falling edge of the input clock signal, and since the delayed signals individually contribute to determining the output of the clock generator, both the rising edge and falling edge of the input signal will be individually delayed. Thus, the output clock will have the same duty cycle as the input clock and data may be transferred accurately on both the rising edge and falling edge of the system clock signal SCLK.. Figure 8 illustrates one example of a delay stage 112, 114 that may be used in the delay line 106. As shown in figure 8 and in the signal diagram of figure 9, this delay stage 112, 114 operates to delay the input signals in_l and in_2 to form output signals out l and out_2. The delay produced by the delay stage 112, 114 is dependent on the difference between Vth(N) and VC, which is variably set by the adjuster 118. Since this delay stage is known in the art, a detailed explanation of its operation has been omitted. According to a second embodiment of this invention, the phase difference between input and output rising edges to the DLL is used to adjust the delay of the rising edge in the DLL and the phase difference between input and output falling edges to the DLL is separately used to adjust the delay of the falling edge in the DLL. By separately controlling the delay of the rising edge and falling edge in the DLL, it is possible to match the output duty cycle with the input duty cycle more accurately, and to compensate for inherent differences in the delay line stages 212a-f, 214a-f. In the illustrated embodiment, a rising edge phase detector 308 is connected at a first input 310 thereof to the input of the DLL and is connected at a second input 312 thereof to the output of the DLL. The rising edge phase detector 308 outputs signals on lines 326, 334 to adjuster 318. The rising edge phase detector 308 and adjuster 318 operate in the same manner as described above with respect to phase detector 108 and adjuster 118 and provide as an output a voltage VCup. As shown in figure 12, the voltage VCup is input to the first series of delay stage 212a-f to control the delay experienced by signals indicative of the rising edge pi, p2 passing through the first series of delay stages 212a-f. A falling edge phase detector 408 is connected at a first input 410 thereof to the input of the DLL and is connected at a second input 412 thereof to the output of the DLL. The falling edge phase detector 408 outputs signals on lines 426, 434 to adjuster 418. The falling edge phase detector 408 and adjuster 418 operate in the same manner as described above with respect to phase detector 408 and adjuster 418, and provide as an output a voltage VCdown. As shown in figure 12, the voltage VCdown is input to the second series of delay stage 214a-f to control the delay experienced by signals indicative of the falling edge p3, p4 passing through the second series of delay stages 214a-f. Figure 12 illustrates one exemplary delay line 506. The only difference between the delay line 506 in figure 12 and the delay line 106 in figure 6 is that the delay line 506 in figure 12 is configured to receive a separate voltage for the first series of delay stages 206 and the second series of delay stages 208. Enabling separate voltages to be input to each of the delay stages 206, 208 allows the delays to be adjusted independently for both the rising edge and falling edge. This is particularly advantageous for fast clock rates where even a minor difference in the delay stages 206, 208 can affect the output duty cycle significantly. It should be understood that various changes and modifications of the embodiments shown in the drawings and described in the specification may be made within the spirit and scope of the present invention. For example, in the illustrated embodiment, a single phase detector and adjustor is used to adjust both series 206, 208 of delay stages 212a-f and 214a-f. These series 206, 208 could be adjusted individually if desired to enhance the ability of the delay line to individually delay both the rising edge and falling edge of the input clock signal. Accordingly, it is intended that all matter contained in the above description and shown in the accompanying drawings be interpreted in an illustrative and not in a limiting sense. The invention is limited only as defined in the following claims and the equivalents thereto. What is claimed is:

Claims: CLAIMS 1. An I/O port for a CPU, comprising: an input port configured to receive a system clock signal; and a digital delay locked loop configured to synchronize a rising edge of an internal clock signal with a rising edge of the received system clock signal and configured to synchronize a falling edge of the internal clock signal with a falling edge of the received system clock signal. 2. The I/O port of claim 1, wherein the digital delay locked loop comprises: a phase generator configured to receive the system clock signal and to generate a rising edge signal indicative of the rising edge of the system clock signal and to generate a falling edge signal indicative of the falling edge of the system clock signal; a first series of delay stages configured to delay the rising edge signal; a second series of delay stages configured to delay the falling edge signal; and a clock generator configured to create the internal clock signal from the delayed rising edge signal and delayed falling edge signal. 3. The I/O port of claim 2, wherein the digital delay locked loop further comprises: a second clock generator configured to create an intermediate signal that may be used to determine whether the first series of delay stages is delaying the rising edge signal by an excessive amount. 4. The I/O port of claim 2, further comprising: a phase detector configured to detect a difference in phase between one edge of the internal clock signal and the same edge of the received clock signal and to output an output signal; and an adjustor configured to receive the output signal from the phase detector and adjust a control signal to thereby adjust an amount of delay experienced by signals in at least one of the first series of delay stages and the second series of delay stages. 5. The I/O port of claim 2, wherein the digital delay locked loop further comprises: a plurality of second clock generators configured to create intermediate signals that may be used to determine whether at least one of the first and second series of delay stages is delaying the respective rising edge signal or falling edge signal by an excessive amount. 6. The I/O port of claim 1 , wherein the phase generator is configured to generate a pair of rising edge signals indicative of the rising edge of the system clock signal and to generate a pair of falling edge signals indicative of the falling edge of the system clock signal. 7. The I/O port of claim 6, wherein the pair of rising edge signals are complimentary; and wherein the pair of falling edge signals are complimentary. 8. The I/O port of claim 2, wherein the clock generator comprises: four sets of transistors, each transistor of each of said sets being controllable by at least one of the rising edge signals or falling edge signals. 9. The I/O port of claim 2, further comprising: a first phase detector configured to detect a difference in phase between the rising edge of the internal clock signal and the rising edge of the received clock signal and to output a first output signal; a first edge adjustor configured to receive the first output signal from the first phase detector and adjust a first control signal to thereby adjust an amount of delay experienced by signals in the first series of delay stages; a second phase detector configured to detect a difference in phase between the falling edge of the internal clock signal and the falling edge of the received clock signal and to output a second output signal; and a second edge adjustor configured to receive the second output signal from the second phase detector and adjust a second control signal to thereby adjust an amount of delay experienced by signals in the second series of delay stages. 10. A CPU, comprising: an I/O port configured to receive and transmit data on a rising edge and a falling edge of a system clock, said I/O port having circuitry configured to synchronize a rising edge of an internal clock with the rising edge of the system clock and to synchronize a falling edge of the internal clock with the falling edge of the system clock. 11. The CPU of claim 10, wherein the I/O port comprises: an input port configured to receive a system clock signal; and a digital delay locked loop configured to synchronize a rising edge of an internal clock signal with a rising edge of the received system clock signal and configured to synchronize a falling edge of the internal clock signal with a falling edge of the received system clock signal. 12. The CPU of claim 11, wherein the digital delay locked loop comprises a phase comparator, an adjustor, and a delay. 13. The CPU of claim 12, wherein the delay comprises a first series of delay stages configured to delay the rising edge of an input waveform by a first predetermined amount, and a second series of delay stages configured to delay the falling edge of the input waveform by a second predetermined amount. 14. The CPU of claim 13, wherein the first predetermined amount equals the second predetermined amount. 15. The CPU of claim 13, wherein the phase comparator comprises: a phase detector configured to detect a difference in phase between one edge of the internal clock signal and the same edge of the received clock signal and to output an output signal; and an adjustor configured to receive the output signal from the phase detector and adjust a control signal to thereby adjust an amount of delay experienced by signals in at least one of the first series of delay stages and the second series of delay stages. 16. The CPU of claim 13, wherein the phase comparator comprises: a first phase detector configured to detect a difference in phase between the rising edge of the internal clock signal and the rising edge of the received clock signal and to output a first output signal; a first edge adjustor configured to receive the first output signal from the first phase detector and adjust a first control signal to thereby adjust an amount of delay experienced by signals in the first series of delay stages; a second phase detector configured to detect a difference in phase between the falling edge of the internal clock signal and the falling edge of the received clock signal and to output a second output signal; and a second edge adjustor configured to receive the second output signal from the second phase detector and adjust a second control signal to thereby adjust an amount of delay experienced by signals in the second series of delay stages. 17. The CPU of claim 15, wherein the adjustor comprises an accumulator configured to increase a voltage on an output line and a attenuator configured to decrease the voltage on the output line to thereby adjust the amount of delay experienced by signals in the delay stages. 18. The CPU of claim 16, wherein the first adjustor comprises a first accumulator configured to increase a first voltage on a first output line to thereby adjust the amount of delay experienced by signals in the first series of delay stages; and wherein the second adjustor comprises a second accumulator configured to increase a second voltage on a second output line to thereby adjust the amount of delay experienced by signals in the second series of delay stages. 19. A digital delay locked loop having an output duty cycle matching an input duty cycle, comprising: a phase generator to generate signals indicative of the input duty cycle; at least one delay line to delay the generated signals; and a clock generator to generate an output having the output duty cycle matching the input duty cycle. 20. A method of delaying a signal, comprising: delaying a rising edge of the signal to form a rising edge of an output signal; and delaying a falling edge of the signal to form a falling edge of the output signal. 21. A method of synchronizing transfer of data, comprising: receiving an input clock signal; detecting a rising edge of the input clock signal; delaying the rising edge of the input clock signal to form a rising edge of an output clock signal; detecting a falling edge of the input clock signal; and delaying the falling edge of the input clock signal to form a falling edge of the output clock signal.

Inventors: HOLZER REUVEN, HOLZER, REUVEN
Applicants: ANALOG DEVICES INC, ANALOG DEVICES, INC.
Application year: 2000
Main classification: G06F13
IPC codes: G06F1, G06F13, H03K5, H03L7