COMPENSATION CIRCUIT FOR LOW PHASE OFFSET FOR PHASE-LOCKED LOOPS

Abstract: A phase-locked loop circuit (200) and method for providing for compensation for an offset. A phase-locked loop circuit comprises a phase detector (115), a compensation circuit (217), a loop filter (120), and a VCO (125). The phase detector is coupled to receive a first input signal (110) and a second input signal (227). The phase detector is configured to output one or more of a plurality of output signals (116) indicative of a difference between the first input signal and the second input signal. The compensation circuit (217) is coupled to receive the output signals (218) and to reduce a voltage offset between the output signals (221). The compensation circuit is further configured to provide a plurality of compensated output signals (218). The loop filter is coupled to receive the compensated control signals (221). The loop filter is configured to output a first control signal. The VCO is coupled to receive the first control signal and to output the second input signal based on the first control signal. A method of operating a phase-locked loop circuit comprises receiving and comparing a first input signal and a second input signal and providing output signals indicative of the comparison. The method compensates for a voltage offset between the output signals (218) and provides compensated output signals indicative of the compensation. The method filters the compensated control signals and provides a control signal (221) indicative of the filtration. The method provides the second input signal based on the first control signal. Lower skew between the input and output may be achieved.

Description: TITLE: COMPENSATION CIRCUIT FOR LOW PHASE OFFSET FOR PHASE-LOCKED LOOPS Field of the Invention This invention relates to electronic circuits, and, more particularly, to compensation circuits for phase- locked loops Description of the Related Art The need to generate a local signal that is synchronized with an external reference signal is critical in many electronics applications such as frequency synthesis, clock recovery, clock generation and frequency demodulation This coherence between the reference signal and the local replica is referred to as "phase synchronization" This typically implies either that local signal either is m phase with the external reference signal or is offset from the reference signal by some phase constant At the heart of any such synchronization circuit is some form of a phase-locked loop circuit (PLL) Phase- locked loops are feedback control loops, whose controlled parameter is the phase of a locally generated replica of an incoming reference signal Phase-locked loops have three basic components a phase detector, a loop filter, and a voltage-controlled oscillator Fig 1 - Basic PLL A basic schematic diagram of a typical PLL 100 is presented in Fig 1 As shown, PLL 100 is configured to generate an output signal 126 in response to an input signal 110 PLL 100 includes a phase detector 115, a loop filter 120, and a voltage-controlled oscillator (VCO) 125 Phase detector 115 is coupled to receive input clock signal 110 and to produce output clock signal 126 Phase detector 115 measures the phase difference between signals 110 and 126 (coupled here back to the phase detector 115 as feedback signal 127), and generates a phase error signal 116, which may be a voltage indicative of this phase difference It is noted that the phase detector 115 illustrated in Fig 1 outputs a phase error signal 116 including an UP signal and a DN signal The UP signal may be interpreted as indicating that the output signal 126 should be higher in frequency to match the input signal 110 The DN signal may be interpreted as indicating that the output signal 126 should be lower in frequency to match the mput signal 110 In other embodiments, the phase error signal 116 may consist of a smgle signal or mclude more than two signals In some instances, phase detector 115 may also generate a phase error signal 116 even when there is no difference between signals 110 and 127 For example, the phase detector 115 may output a small UP signal and a large DN signal, thereby providing both an UP signal and a DN signal to the filter 120 when only a DN signal may have been an appropriate signal of the phase error As signals 110 and 127 change with respect to each other, signal 116 becomes a time-varying signal mto loop filter 120 This phase compaπson is necessary to prevent output signal 126 from driftmg with respect to reference signal 110 As shown, the feedback signal 127 is an internal part of the PLL 100 It is noted that the feedback signal 127 may be a signal external to the PLL 100 Loop filter 120 governs the response of PLL 100 to the error detected between signals 110 and 127 A well-designed loop filter 116 should be able to track changes in the phase of the mput signal 110 but should not be overly responsive to noise mixed with the input signal 110 Loop filter 120 generates an error correction signal 121, which is the mput to VCO 125 In one embodiment, a zero voltage on signal 121 causes the output of VCO 125, output signal 126, to oscillate at a predefined frequency, ω 0 , which is the "center" frequency of the oscillator On the other hand, a positive voltage on error correction signal 121 causes output signal 126 to oscillate at a frequency which is greater than ω 0 Conversely, a negative voltage on error correction signal 121 causes output signal 126 to oscillate at a frequency less than ω 0 In another embodiment, either only a positive voltage or only a negative voltage on error correction signal 121 is generated In vaπous embodiments, even when there is no difference between signals 110 and 127, an error correction signal 121 is output In still another embodiment, the error correction signal 121 is scaled such that although the error correction signal 121 is always of one sign, such as always positive, the error correction signal 121 corrects for oscillation either above or below the predefined frequency Generally speakmg, in many embodiments, the output frequency of VCO 125 is a linear function of its mput voltage over some range of input and output "Phase lock" is achieved by feeding the output of VCO 125 back to phase detector 115 so that contmual error correction may be performed It is noted that PLL 100 may not achieve phase lock if mput signal 110 is outside of some predetermined range In a simplest form, loop filter 120 is simply a conductor that receives a single phase error signal 116 from the phase detector 115 In this simplest embodiment, the phase error 116 is equal to error correction signal 121 Such a filter 120 allows PLL 100 to generate an output signal 126 which matches reference signal 110 m frequency and phase only if reference signal 110 is equal to the center frequency of VCO 125 If reference signal 110 oscillates at a different frequency from the center frequency of VCO 125, output signal 126 may match reference signal 110 in frequency but not phase This "wire filter" is an example of a first-order PLL, which means that the denommator of the loop filter transfer function has no exponent value greater than one In another embodiment of a first-order PLL, loop filter 120 includes an amplifier It is noted that PLL 100 may be fabricated on a monolithic substrate or produced from discrete components The components 115, 120, and 125 used to create the PLL 100 may not be matched in electrical properties to each other, leading to instability of the PLL 100 What is needed is a way to provide for an improved PLL circuit with greater stability SUMMARY OF THE INVENTION The problems outlined above are m large part solved by a phase-locked loop circuit and method for providmg for compensation for voltage offset In one embodiment, a voltage offset between output signals of a phase detector may be reduced by a compensation circuit The compensation circuit may advantageously allow for greater stability for the PLL, especially when the PLL is produced using discrete components A phase-locked loop circuit is contemplated compnsmg, in one embodiment, a phase detector, a compensation circuit, a loop filter, and a VCO The phase detector is coupled to receive a first mput signal and a second mput signal The phase detector is configured to output one or more of a plurality of output signals mdicative of a difference between the first input signal and the second input signal The compensation circuit is coupled to receive the output signals and to reduce a voltage offset between the output signals The compensation circuit is further configured to provide a plurality of compensated output signals The loop filter is coupled to receive the compensated control signals The loop filter is configured to output a first control signal The VCO is coupled to receive the first control signal and to output the second mput signal based on the first control signal A method of operatmg a phase- locked loop circuit is also contemplated In one embodiment, the method comprises receivmg a first mput signal and a second input signal The method compares the first mput signal and the second input signal and provides a plurality of output signals mdicative of a result of comparing the first input signal and the second mput signal The method compensates for a voltage offset between the plurality of output signals to reduce the voltage offset The method provides a plurality of compensated output signals indicative of the result of the compensatmg The method filters the plurality of compensated control signals and provides a first control signal indicative of the result of the filtering The method provides the second input signal based on the first control signal In various embodiments, the VCO may be a voltage controlled crystal oscillator (VCXO), and the loop filter may be configured as an integrator and/or as an active filter In one embodiment, the compensation circuit mcludes a pair of common-base transistors The first transistor includes a base biased by a base voltage, an emitter coupled to receive a first one of the output signals, and a collector coupled to provide a first one of the compensated control signals The second transistor includes a base biased by the base voltage, an emitter coupled to receive a second one of the output signals, and a collector coupled to provide a second one of the compensated control signals In one embodiment, the transistors are NPN transistors In another embodiment, the transistors are PNP transistors BRIEF DESCRIPTION OF THE DRAWINGS Other ob j ects and advantages of the mvention will become apparent upon readmg the folio wmg detailed description and upon reference to the accompanymg drawings in which Fig 1 is a block diagram of an embodiment of a prior art PLL circuit, Fig 2 is a block diagram of an embodiment of a generic PLL circuit including compensation circuit, Fig 3 is a block diagram of a further embodiment of a PLL circuit including a compensation circuit, and Figs 4A and 4B are circuit diagrams of embodiments of the compensation circuit While the invention is susceptible to vaπous modifications and alternative forms, specific embodiments thereof are shown by way of example m the drawmgs and will herein be described in detail It should be understood, however, that the drawmgs and detailed description thereto are not intended to limit the invention to the particular form disclosed, but on the contrary, the intention is to cover all modifications, equivalents and alternatives falling within the spirit and scope of the present invention as defined by the appended claims DETAILED DESCRIPTION OF THE INVENTION Fig 2 - Generic PLL Circuit with Compensation As shown, PLL 200 is configured to generate an output signal 226 m response to an input signal 110 PLL 200 includes a phase detector 115, a compensation circuit 217, a loop filter 120, and a voltage-controlled oscillator (VCO) 125 PLL 200 is coupled to receive mput clock signal 110 and to produce output clock signal 126 Phase detector 115 measures the phase difference between signals 110 and 226 (coupled here back to the phase detector 115 as feedback signal 227), and generates a phase error signal 116, which may be a voltage mdicative of this phase difference As shown, phase detector 115 outputs an UP signal (UP) and a DOWN signal (DN) m response to a difference between the input signal 110 and the feedback signal 227 In some embodiments, phase detector 115 may also generate an UP signal and/or a DN signal even when there is no difference between signals 110 and 227 As signals 110 and 227 change with respect to each other, signal 116 becomes a time-varying signal into compensation circuit 217 This phase comparison is necessary to prevent output signal 226 from drifting with respect to reference signal 110 This phase comparison is necessary to prevent output signal 226 from drifting with respect to reference signal 110 As shown, the feedback signal 227 is an internal part of the PLL 200 It is noted that the feedback signal 227 may be a signal external to the PLL 200 Compensation circuit 217 is designed to compensate for an offset between the UP signal and the DN signal of the phase error signal 116 The compensation circuit 217 is configured to output a compensated phase error signal 218 to the loop filter 120 In one embodiment, the compensation circuit 217 is configured to compensate for a voltage offset between the baseline voltages of the UP and the DN signals In another embodiment, the compensation circuit 217 is configured to compensate for a voltage offset between upper level voltages of the UP and the DN signals As used herem, "compensation" may refer to a reduction or removal of a non-umformity, such as a phase offset, voltage offset, or skew By way of example, without compensation, a voltage offset between the UP and DN pulses are integrated by the loop filter 120, leadmg directly to greater phase skew between input signal 110 and output signal 226 / feedback signal 227 It is noted that other embodiments are also contemplated For example, the phase detector 115 may output a short DN signal along with a long UP signal Rather than havmg the filter handle both UP and DN signals, the compensation circuit 217 may subtract the DN signal from the UP signal before providmg the compensated UP signal to the filter 120 as the compensated phase error signal 218 Other embodiments may compensate for phase error or skew, among other variables Loop filter 120 governs the response of PLL 100 to the error detected between signals 110 and 127 The loop filter 120 may be any order filter as desired The loop filter 120 outputs an error correction •signal 221 to the VCO 125 In one embodiment, the error correction signal 221 is a control voltage Other error correction signals 221 may be used as desired Generally speakmg, in various embodiments, the output frequency of VCO 125 is a linear function of its input voltage over some range of mput and output "Phase lock" is achieved by feeding the output of VCO 125 (as feedback signal 227) back to phase detector 115 so that contmual error correction may be performed It is noted that PLL 200 may not achieve phase lock if input signal 110 is outside of some predetermined range Fig 3 - PLL Circuit with Compensation As shown, PLL 300 is configured to generate an output signal 326 m response to an mput signal 110 PLL 300 includes a phase detector 315, a compensation circuit 217, an active integrating low-pass filter 320, and a voltage-controlled crystal oscillator (VCXO) 325 PLL 300 is coupled to receive mput signal 110 and to produce output signal 326 Phase detector 115 measures the phase difference between signals 110 and 326 (coupled here back to the phase detector 115 as feedback signal 327), and generates a phase error signal 116, which may be a voltage mdicative of this phase difference As shown, phase detector 115 outputs an UP signal and a DN signal in response to a difference between the mput signal 110 and the feedback signal 327 In this embodiment, phase detector 115 normally generates a minimum duration UP signal and a minimum duration DN signal even when there is no difference between signals 110 and 327 As signals 110 and 327 change with respect to each other, signal 116 becomes a time-varying signal mto compensation circuit 217 This phase comparison is necessary to prevent output signal 326 from drifting with respect to reference signal 110 This phase comparison is necessary to prevent output signal 226 from drifting with respect to reference signal 110 As shown, the feedback signal 227 is an internal part of the PLL 200 It is noted that the feedback signal 227 may be a signal external to the PLL 200 Compensation circuit 217 is configured to compensate for a voltage offset between the UP signal and the DN signal of the phase error signal 116 The compensation circuit 217 is also configured to output a compensated phase error signal 218, as UPC and DNC, to the filter 320 Filter 320 governs the response of PLL 300 to the error detected between signals 110 and 327 The filter 320 preferably comprises a unity-amplifying operational amplifier configured as an integrator The loop filter 320 outputs an mtegrated error correction signal 321 to the VCXO 125 In the illustrated embodiment, the output frequency of VCXO 325 is a linear function of its input voltage over a limited range of mput and output frequency "Phase lock" is achieved by feedmg the output of VCO 325 (as feedback signal 327) back to phase detector 115 so that contmual error correction may be performed It is noted that PLL 300 may not achieve phase lock if mput signal 110 is outside of some predetermined operating range Figs 4A/4B - DCBT Compensation Circuit Embodiments Turning now to Fig 4A, one embodiment of compensation circuit 217 is shown as a dual common-base transistor circuit 217A Two symmetrical common-base PNP transistors Tl and T2 operate as high speed switches with a threshold voltage set by bias voltage VB, through resistors Re The transistors Tl and T2 accept the phase error signal 116A and output the compensated phase error signal 218A When UP and DN are idle at a baseline voltage, the voltage between the emitter and the base is less than the turn-on voltage, through resistors Rb, so the PNP transistors Tl and T2 are turned off Both UPC and DNC are pulled to VB when the PNP transistors Tl and T2 are turned off, providmg for a voltage offset of zero when the UPC and DNC outputs are at a baseline idle state When UP and DN are active, the UP and DN signals turn on the PNP transistors Tl and T2 as the voltage of the UP and DN pulses is enough to exceed the emitter-base turn-on voltage In the illustrated embodiment, any voltage offset of the UP and DN signals at the active voltage is negligible as the integration time for the active state is much smaller than the mtegration time for the idle state Turning now to Fig 4B, another embodiment of the compensation circuit 217 is shown as a dual common- base transistor circuit 217B Two symmetrical common-base NPN transistors T3 and T4 operate as high speed switches with a threshold voltage set by bias voltage VB, through resistors Re The transistors T3 and T4 accept the phase error signal 116B and output the compensated phase error signal 218B When UP# and DN# are idle at a baseline voltage, the voltage between the emitter and the base is less than the turn-on voltage, through resistors Rb, so the NPN transistors T3 and T4 are turned off Both UPC# and DNC# are pulled to VB when the NPN transistors T3 and T4 are turned off, providmg for a voltage offset of zero when the UPC# and DNC# outputs are at a baselme idle state When UP# and DN# are active, the UP# and DN# signals turn on the NPN transistors T3 and T4 as the voltage of the UP# and DN# pulses is enough to exceed the emitter-base turn-on voltage In the illustrated embodiment, any voltage offset of the UP# and DN# signals at the active voltage is negligible as the integration time for the active state is much smaller than the integration time for the idle state It is noted that when usmg the compensation circuit 217B, the UPC# and DNC# signals must be cross connected to the filter 320 mputs For the purposes of this disclosure, all clocking signals are preferably low voltage pseudo-ECL signals (LVPECL) Other types of clocking signals may be used as desired Numerous variations and modifications will become apparent to those skilled in the art once the above disclosure is fully appreciated It is intended that the following claims be interpreted to embrace all such variations and modifications

Claims: WHAT IS CLAIMED IS: 1 A phase-locked loop circuit, compnsmg a phase detector coupled to receive a first input signal and a second mput signal, wherein said phase detector is configured to output one or more of a plurality of output signals indicative of a difference between said first input signal and said second mput signal, a compensation circuit coupled to receive said plurality of output signals, wherem said compensation circuit is configured to reduce an offset between said plurality of output signals to provide a plurality of compensated output signals, a loop filter coupled to receive said plurality of compensated output signals, wherein said loop filter is configured to output a control signal, and a voltage controlled oscillator (VCO) coupled to receive said control signal, wherem said VCO is configured to output said second mput signal based on said control signal 2 The phase-locked loop circuit of claim 1, wherem said VCO is a voltage controlled crystal oscillator (VCXO) 3 The phase-locked loop circuit of claim 1, wherein said loop filter is configured as an integrator 4 The phase-locked loop circuit of claim 1 , wherem said loop filter is configured as an active filter 5 The phase-locked loop circuit of claim 1, wherem said compensation circuit includes a first transistor havmg a first base biased by a base voltage, a first emitter coupled to receive a first signal of said plurality of output signals, and a first collector coupled to provide a first signal of said plurality of compensated output signals, and a second transistor havmg a second base biased by said base voltage, a second emitter coupled to receive a second signal of said plurality of output signals, and a second collector coupled to provide a second signal of said plurality of compensated output signals 6 The phase-locked loop circuit of claim 5, wherem said first transistor and said second transistor are NPN transistors 7 The phase-locked loop circuit of claim 5, wherem said first transistor and said second transistor are PNP transistors 8 The phase-locked loop circuit of claim 5, wherem a difference between said base voltage and an idle voltage level for said first signal of said plurality of output signals is less than a turn-on voltage of said first transistor, and wherem said difference between said base voltage and said idle voltage level for said second signal of said plurality of output signals is less than said turn-on voltage of said second transistor 9 The phase-locked loop circuit of claim 8, wherein said difference between said base voltage and an acϋve voltage level for said first signal of said plurality of output signals is greater than or equal to said turn-on voltage of said first transistor, and wherein said difference between said base voltage and said active voltage level for said second signal of said plurality of output signals is greater than or equal to said turn-on voltage of said second transistor 10 The phase-locked loop circuit of claim 1, wherem said compensation circuit includes one or more switches coupled to receive said plurality of output signals, wherein said one or more switches are configured to output compensated output signals m response to receivmg said plurality of output signals, wherem said compensated output signals have approximately no offset 11 The phase-locked loop circuit of claim 1 , wherein one or more of the phase detector, the loop filter, or the VCO are comprised of discrete components 12 A method of operatmg a phase-locked loop circuit, the method comprising receivmg a first input signal and a second mput signal, comparing said first input signal and said second input signal, providmg a plurality of output signals mdicative of a result of said comparing, compensatmg said plurality of output signals to reduce an offset between said plurality of output signals, providmg a plurality of compensated output signals indicative of the result of said compensatmg, filtering said plurality of compensated control signals, providmg a first control signal mdicative of the result of said filtering, and providmg said second input signal based on said first control signal 13 The method of claim 12, wherem said filtering includes integrating one or more of said plurality of compensated control signals 14 A phase-locked loop circuit, compnsmg means for receivmg a first mput signal and a second mput signal, means for comparing said first mput signal and said second input signal, means for providmg a plurality of output signals indicative of a result of said comparing, means for compensatmg said plurality of output signals to reduce an offset between said plurality of output signals, means for providmg a plurality of compensated output signals mdicative of the result of said compensatmg, means for filtering said plurality of compensated control signals, means for providing a first control signal mdicative of the result of said filtering, and means for providmg said second input signal based on said first control signal 15 The phase-locked loop circuit of claim 14, wherem said means for filtering mcludes means for mtegratmg one or more of said plurality of compensated control signals

Inventors: DOBLAR DREW G, WU CHUNG-HSIAO R, DOBLAR, DREW, G., WU, CHUNG-HSIAO, R.
Applicants: SUN MICROSYSTEMS INC, SUN MICROSYSTEMS, INC.
Application year: 2000
Main classification: H03L7
IPC codes: H03L7