Bus driver circuit and method for operating the same

Abstract: A bus driver circuit having a floating gate circuit for controlling voltage on the gate of the output driver and a floating well circuit for controlling voltage on the body of the output driver, comprising a well pull up circuit coupled to the output driver for applying supply voltage to the body during transmission and for floating the body during quiescence.

Description: BACKGROUND OF THE INVENTION This invention relates to an apparatus for operating an integrated circuit. In particular, it relates to a MOS output driver that is powered by a 3.3v power supply and may be occasionally connected to a higher supply, such as 5v. Complementary metal oxide semiconductors (CMOS) are in integrated circuits and systems. CMOS technology continues to shrink and as it shrinks the power supplies that operate the CMOS devices shrink accordingly. At present, many CMOS devices operate with a 3.3v power supply. However, these devices are often connected to peripheral devices in a system or even on the same chip that may operate or otherwise carry a higher voltage, such as 5v. If an output driver on a circuit is connected to a power supply that is greater than the output driver's normal power supply, the greater power supply may inadvertently turn on the driver when the system requires that the driver be off or otherwise in a quiescent state. Others have provided solutions to this problem by controlling the voltage on the gate of the driving transistor, as well as controlling the voltage on the well of the driving transistor. If either of those voltages are not properly controlled, then one or more of the two body diodes in the drive transistor may turn on or the mosfet may itself turn on. See, in particular, the specification of US-A- 5,160,855 which shows a well voltage control circuit for controlling the voltage on the well of the drive transistor. The well voltage control circuit includes at least four transistors. However, I have found that the well control circuit does not adequately control the output transistor body when the output voltage is dose to the value of the supply voltage during transmission. US-A-5,338,978, upon which the preamble portion of independent claim 1 is based, discloses a full swing CMOS output buffer circuit which isolates incompatible power supply circuits such a 3.3 V standard and 5 V standard subcircuits and further presents a high impedance to a common output bus. The circuit is due to the number of elements quite expensive. In WO-A-9802965 the application of circuitry for controlling the potential of each of the output transistors of a push-pull stage is described. It is an object of the invention to reduce the number of necessary components and to provide a bus driver circuit which is less complex and controllable. In order to accomplish the result the invention provides a bus driver circuit comprising an output MOS transistor having a source, an insulated gate, a body and a drain wherein the drain and source and body form two body diodes, a supply terminal connected to the source of the output MOS transistor for applying a supply voltage to the output MOS transistor, an output terminal connected to the drain of the output MOS transistor for generating an output voltage in response to an applied input gate voltage, a gate terminal connected to the insulated gate of the output MOS transistor for receiving a gate voltage signal, a floating gate control circuit coupled to the gate for receiving an input signal and the output signal and for connecting the greater of the two received signals to the gate terminal when the bus is quiescent, and a well pull up circuit connected to the gate terminal, to the body of the output MOS transistor and to the supply terminal for connecting the supply voltage to the well of the output MOS transistor during transmission and thereby preventing the modulation of the body voltage by charge injection during transmission and for floating the body of the output transistor during quiescence, characterized in that the well pull up circuit comprises three transistors, two of the same type as the output MOS transistor and one of opposite type, a first transistor of the same type is connected to the supply terminal and to the body of the output MOS transistor; the second transistor of the opposite type has its gate for receiving an enable signal and is connected between ground and the gate of the first transistor and the third transistor of the same type has its gate connected to the enable signal its source and drain connected between the gate of the first transistor and the output of the floating gate circuit. Further developments are subject to dependent claims 2 to 4. The bus driver circuit is less complex than known ones and solves the problem of a floating well voltage even where output voltage is close to the value of the supply voltage during transmission. The circuit comprises an output driver MOS transistor that has a source, an insulated gate, a body and a drain. This structure includes two inherent diodes. The drain and the body form one diode and the body and the source form the other. A low voltage supply terminal is connected to the source of the MOS transistor and the drain provides the output terminal. The gate terminal receives a gate voltage signal that turns the bus driver MOS transistor on or off. A floating gate control circuit is coupled to the gate and allows the gate to rise with the output voltage on the drain when the output voltage on the drain exceeds the primary supply voltage. This ensures that the normal mosfet conduction does not occur. A well pull up circuit is connected to the floating gate control circuit, the body of the MOS transistor and to the primary supply terminal. The well pull up circuit lets the well float and thereby prevents its inadvertent operation of turning on one of the body diodes of the MOS transistor. An enable control circuit controls the well pull up circuit. The enable control circuit is high during operation of the bus output driver and low when the bus is quiescent. The invention will now be described, by way of example, with reference to the accompanying drawings in which: Figure 1a is a schematic of a single bus driver transistor; Figure 1b is a schematic corresponding to 1a and shows the two inherent body diodes; Figure 2 is a schematic of a prior art bus driver circuit; Figure 3 is a further schematic of the floating gate circuit of Figure 2; Figure 4 is a schematic diagram of a bus driver circuit having a well pull up circuit; Figure 5 is a detailed schematic of a bus driver circuit having a well pull up circuit according to the invention; and Figure 6 is a schematic of a CMOS output driver that applies the invention to the NMOS and PMOS transistors. Figures 1a, 1b, 2 and 3 show the problem faced by bus drivers and how the problem is addressed by the circuit disclosed in the specification of U. S. Patent 5,160,855. Figure 1a is a simplified version of a bus driver. The driving transistor Q BUS receives an input signal V IN . Q BUS is connected between a power supply V DD and an output terminal V OUT . The transistor Q BUS is shown as a PMOS transistor. A PMOS transistor includes P-type diffusions in the surface of a substrate that substantially comprises N-type doping. As a result, the transistor Q BUS has or can be viewed as a structure with two internal diodes such as shown in Figure lb. Since the source is coupled to the body, one diode is, in effect, shorted to the drain. The other diode is controlled by V OUT . It is important that these diodes that are formed by the respective P-type diffusions and the body of the Q BUS be kept from triggering on. If V OUT exceeds V DD , the body diode D 2 will be turned on. This is undesirable since, in effect, Q BUS could be turned on at a time when V IN was high. In the ideal bus driver, Q BUS never turns on until V IN is low. Those skilled in the art will appreciate that, in a CMOS device, the output circuit of Figure 1a will have a corresponding NMOS output transistor. The circuits shown in the specification of U. S. Patent 5,160,855 and Fig. 2 include a floating gate voltage circuit (VFG) and a floating well voltage circuit (VFW). The VFG circuit is connected between the input V IN and the gate of the output transistor Q BUS . The VFW circuit is connected between the output V OUT and the body tie of Q BUS . During quiesence the input to VFG is tied to the supply voltage V DD . As long as V OUT is less than V DD the gate voltage is tied to V DD . The VFG monitors the output voltage and adjusts the gate voltage to follow the output voltage V OUT when V OUT is greater than V DD . During transmission, the input of the floating gate circuit may vary between ground and the supply voltage to turn the drive transistor on and off, respectively. In this way, the gate and the drain of the transistor Q BUS are maintained at the same potential when V OUT rises above V DD . Accordingly, the transistor Q BUS is prevented from turning on. Of course, the problem of a floating output voltage V OUT also affects the well of the output transistor Q BUS . In known solutions as shown in Figure 3, the VFW circuit attempts to adjust the voltages applied to the well of Q OUT in order to prevent unwanted operation. The prior art circuit functions acceptably for conditions when V OUT is significantly less than V DD and when V OUT is significantly greater than V DD . However, it experiences problems when V OUT is approximately the same value as V DD . When V OUT is less than V DD , transistor Q4 is on and VFW is effectively connected to V DD . Accordingly, the diode in the body tie is reverse biased and does not conduct current. That is the condition for normal transmission. When the bus is off and there is no transmission, V OUT may rise to a voltage greater than V DD . For example, V DD for a bus is normally 3.3v but elements and devices driven by the bus may be at 5v. Accordingly, V OUT may be much greater than V DD . In that case, Q4 is off and Q1 and Q2 are on and VFW follows V OUT . The same voltage of V OUT is applied across the body tie diode D 2 . Since the same voltage is across both terminals of the body tie diode, the diode remains off. However, the circuit shown in Figure 3 does not control VFW when V OUT is close to V DD . When V OUT is nearly the same as V DD , all of the transistors Q1 - Q4 are off. At that time, there is no control on VFW. Consequently the body becomes a high impedance node and is susceptible to charge injection through the drain to body capacitance during transmission. The injected charge changes the voltage on the body which then changes the threshold voltage on Q BUS Modulating the threshold voltage in such a way causes signal distortion. Turning to Figures 4 and 5, this deficiency is remedied by adding a well pull up (WPU) circuit to the circuit of Figure 3 and removing the VFW circuit. The WPU circuit (WPU) is connected to the body of Q BUS , the output of the VFG circuit, and to V DD . It receives an input enable signal that is derived from one or more of the enable signals that turn on the bus. In operation, the well pull up circuit ensures that the body of the output transistor Q BUS is tied to V DD when the bus is enabled. At all other times, the well pull up circuit allows the body of Q BUS to float electrically so that the drain diode of Q BUS can not conduct current. With reference to the invention as depicted in Figure 5, when the enable signal is high, Q5 is on which turns on Q6. Accordingly, V DD is connected to VFW through Q6 and V DD is applied to the body of Q BUS . During transmission the supply voltage V DD is connected to one end of diode D 2 and, since V OUT is less than V DD during transmission the diode is reverse biased and does not conduct. When enable is low and the bus is quiescent, Q5 and Q6 are off while Q7 is turned on. Q7 connects the VFG node to the gate of Q6. This is necessary to keep Q6 off when V OUT is backwards driven above V DD . Thus, when the circuit is not enabled, the body of Q BUS is allowed to float and can not carry current In summary, during operation, when ENABLE is high, Q5 and Q6 are on and so VFW is coupled to V DD . This prevents the body diode from floating during transmission and precludes signal distortion due to charge injection into the body. ENABLE is high when the output stage is driving a load. In order to disable the output stage and create a high impedance state, V IN is set high, i.e., to V DD and ENABLE is set low, i.e., to zero volts. This turns off Q5 and turns on Q7. The voltage VFG is used to turn off Q6. VFG, by design, will be greater than or equal to V IN . With Q6 off, the body of the output PMOS Q BUS device is allowed to float so that it cannot conduct current. With reference to Figure 6, a CMOS output driver is shown. The embodiment includes two output transistors, Q PBUS and Q NBUS . The transistors are connected in series with Q PBUS connected to V DD and Q NBUS connected to ground. The output voltage V OUT is taken from the series connection of the transistors Q PBUS and Q NBUS . The voltage on the gate of Q PBUS is monitored and controlled by a floating gate circuit, VFG/P. A corresponding floating gate circuit, VFG/N controls the voltage on the gate of Q NBUS . The voltage on the well of Q PBUS is controlled by the well pull up circuit WPU/P. In a similar manner, the voltage on the well of Q NBUS is controlled by another well pull up circuit, WPU/N. An enable control circuit 60 is coupled to WPU/P and to WPU/N. The enable control circuit 60 applies the enable signal to WPU/P and applies the signal enable bar to WPU/N. The operation of WPU/P and WPU/N of Figure 6 substantially corresponds to the operation of the WPU circuit shown in Figure 5.

Claims: A bus driver circuit comprising: an output MOS transistor (Q BUS ) having a source, an insulated gate, a body and a drain wherein the drain and source and body form two body diodes, a supply terminal (V DD ) connected to the source of the output MOS transistor (Q BUS ) for applying a supply voltage to the output MOS transistor, an output terminal (V OUT ) connected to the drain of the output MOS transistor (Q BUS ) for generating an output voltage in response to an applied input gate voltage, a gate terminal connected to the insulated gate of the output MOS transistor (Q BUS ) for receiving a gate voltage signal, a floating gate control circuit (VFG) coupled to the gate for receiving an input signal (V IN ) and the output signal (V OUT ) and for connecting the greater of the two received signals to the gate terminal when the bus is quiescent, and a well pull up circuit (Q 5 ,Q 6 ,Q 7 ) connected to the gate terminal, to the body of the output MOS transistor (Q BUS ) and to the supply terminal (V DD ) for connecting the supply voltage to the well of the output MOS transistor (Q BUS ) during transmission and thereby preventing the modulation of the body voltage by charge injection during transmission and for floating the body of the output MOS transistor (Q BUS ) during quiescence, characterized in that the well pull up circuit comprises three transistors, two (Q 6 ,Q 7 ) of the same type as the output MOS transistor (Q BUS ) and one (Q 5 ) of opposite type, a first transistor (Q 6 ) of the same type is connected to the supply terminal and to the body of the output MOS transistor; the second transistor (Q 5 ) of the opposite type has its gate for receiving an enable signal (ENABLE) and is connected between ground and the gate of the first transistors (Q 6 ) and the third transistor (Q 7 ) of the same type has its gate connected to the enable signal (ENABLE) its source and drain connected between the gate of the first transistor (Q 6 ) and the output of the floating gate circuit (VFG). A bus driver circuit as claimed in claim 1 characterized by a pull up control circuit for generating the enable signal (ENABLE) at an enable terminal. A bus driver circuit as claimed in claim 1 characterized in that the output MOS transistor (Q BUS ) is a PMOS or a NMOS transistor. A bus driver circuit as claimed in claim 1 characterized by a second output MOS transistor of a type opposite to the first output MOS transistor and corresponding floating gate and well pull up circuits for controlling the second output transistor.

Inventors: DAVIS CHRISTOPHER, SHEARON WILLIAM, DAVIS, CHRISTOPHER, SHEARON, WILLIAM
Applicants: INTERSIL CORP, INTERSIL CORPORATION
Application year: 2000
Main classification: H03K19
IPC codes: H03K19, H01L27, H01L21, H03K3