DEVICE FOR SCANNING A ROTATING INFORMATION CARRIER

Abstract: A device according to the invention for scanning a rotating information carrier (2) comprises a transducer (10) and control means (20, 22) for controlling a scanning parameter of the transducer (10), such as the radial position and the setting of a focus. The control means comprise difference signal generating means (20) for generating a difference signal (RE) which is indicative of a difference between a current value and a desired value of the scanning parameter, and correction signal generating means (22) for generating a correction signal (SC) in response to the difference signal. The correction signal generating means (22) comprise a delay loop (25) having first in first out memory means (36) for generating a delayed signal (SDL1) and feedback filter means (38) for filtering the delayed signal (SDL1). The device comprises rotation speed detecting means (8) for generating a clock signal (CL) having a frequency which is indicative of the rotation speed of the information carrier (2), the delay in the memory means (36) being proportional to a period of the clock signal.

Description: Device for scanning a rotating information earner The invention relates to a device for scanning a rotating information earner compnsmg rotating means for rotating the information earner around an axis, a transducer for converting a wnte signal into a detectable pattern at the information earner, and/or for detecting a pattern at the information earner and generating a read signal in response thereto, control means for controlling a scanning parameter of the transducer, wherein the control means compnse difference signal generating means for generating a difference signal which is indicative of a difference between a current value and a desired value of the scanning parameter, correction signal generating means for generating a correction signal in response to the difference signal, the correction signal generating means compnsing a delay loop which includes combination means for generating a combination signal out of a feedback signal and an input signal denved from the difference signal, first in first out memory means for generating a delayed signal out of the combined signal and feedback means for generating a feedback signal out of the delayed signal In a device for scanning a rotating information earner a penodic error may occur in a position of a transducer due to an unbalanced or an eccentnc information earner Likewise penodic errors may occur in other parameters, for example the accuracy with which a beam is focussed in an optical player. It has been found that such a penodic error may be substantially reduced by means of a controller compnsing a memory loop Such a controller has a relatively high gain for signals having a frequency corresponding to a basis frequency or the harmonics thereof A substantial reduction of the penodic errors is achieved if the basis frequency of the memory loop corresponds to the rotation frequency of the information earner Such a controller is known from the patent application WO 96/13898 The known controller is designed such that its transfer function has a zero slope around the basis frequency and its harmonics, so that it is relatively insensitive to variations in the rotation frequency. However the controller still is only operable within a frequency-interval around the basis frequency. This is in particular a disadvantage in a device in which the information carrier is not rotated at a constant angular velocity, such as in CLV or in quasi-CLV systems. The frequency intervals within which the gain of the loop is relatively high can not be widened unlimitedly, because that would entail the risk of instabilities in the servo loop. It is a purpose of the invention to provide a device for scanning a rotating information carrier, having a control system for controlling a scanning parameter, which control system is insensitive to variations in the angular velocity and which yet has a relatively high stability. For this purpose the device comprises rotation speed detecting means for generating a clock signal having a frequency which is indicative of the rotation speed of the information carrier, the delay in the memory means being proportional to a period of the clock signal. In a device according to the invention the basis frequency is accurately matched to the rotation frequency. This makes it possible to reduce the frequency intervals of relatively high gain. On the one hand this provides for a good suppression of periodic disturbances, while on the other hand the control system can have a high stability. These and other aspects of the invention are disclosed in more detail in the drawing. Therein: Figure 1 shows an embodiment of a device according to the invention for scanning a rotating information carrier, Figure 2 shows control signal generating means in said embodiment, Figure 3 shows rotation speed detecting means, Figure 4 shows in more detail a delay loop, Figure 5A shows the magnitude M(f) of the closed loop transfer function of the delay loop, Figure 5B shows the phase φ(f) of the closed loop transfer function of the delay loop, Figure 6 shows an implementation of a reconstruction filter, Figure 7 shows the magnitude M(f) of the closed loop transfer function of the combination of the delay loop of Figure 4 and the reconstruction filter of Figure 6, Figure 8 shows an alternative embodiment of a portion of the control signal generating means, Figure 9 shows a further embodiment of a portion of the control signal generating means, Figure 10 shows in more detail differentiating means forming part of the embodiment shown in Figure 9, Figure 11 shows in more detail first in first out memory means and feedback filter means forming part of the embodiment of Figure 9, Figure 12 shows in more detail integration means forming part of the embodiment of Figure 9. Figure 1 shows a device for scanning a rotating information carrier 2. The device comprises rotating means 4, in the form of a spindle motor, for rotating the information carrier around an axis 6. The device further comprises rotation speed detecting means 8 for generating a clock signal CL having a frequency which is indicative of the rotation speed of the information carrier 2. The rotation speed detecting means 8 may be implemented in different ways known to the skilled person. For example these means may comprise Hall sensors, or a detector for measuring the back-EMF in the motor windings. Otherwise the rotation speed detecting means may be implemented by an optical detector in combination with a rotating disc having an optical detectable pattern. The device further comprises a transducer 10 for converting a write signal Sw into a detectable pattern at the information carrier, and/or for detecting a pattern at the information carrier and generating a read signal Spin response thereto. The transducer 10 may be in the form of a magnetic head for converting an electrical signal into a magnetical pattern at the information carrier or for detecting a magnetical pattern and generating an electrical signal in response thereto. In the present embodiment the transducer 10 is an electro-optical transducer for detecting an optical pattern at the information carrier 2 and generating an electrical read signal S R . TO that end the transducer 10 maps an optical beam 12 at a scanning spot 14 at the information carrier 2 and measures the radiation reflected from that spot 14. The operation of the transducer 10 is determined by one or more scanning parameters. In casu one of the scanning parameters is the radial position RE at which the beam 12 is mapped at a scanning spot 14 at the information carrier 2. The scanning parameter is controlled by control means 20, 22. These comprise difference signal generating means 20 for generating a difference signal RE which is indicative of a difference between a current value and a desired value of the scanning parameter. In this case the difference signal is a radial error signal RE, which is indicative of the radial distance of the scanning spot to the nearest track. The control means 20, 22 further comprise correction signal generating means 22 for generating a correction signal Sc in response to the difference signal RE. In addition the correction signal generating means 22 generate a control signal S SL for a slide motor 23 which moves the transducer 10 along a slide 24. Figure 2 shows the correction signal generating means 22 in more detail. In the embodiment shown the correction signal generating means 22 comprise a cross over filter 27 for separating the difference signal RE into a high frequency S H and a low frequency component S L - The low frequency component S L forms an input signal for a Pi-controller 26, 28, 30 comprising a proportional circuit 26 and an integrating circuit 28, as well as combination means 30 to generate a combination signal S P ι out of the output signals of these circuits 26, 28. The output signal of the integrating circuit 28 also serves as a control signal S SL for the slide motor 23. The high frequency component S H forms an input of a differentiating circuit 32. The correction signal generating means 22 further comprise a delay loop 25, which comprises combination means 34 for generating a combined signal S COM out of an input signal S P j and a feedback signal S F - The input signal S I is the output signal S PI of the Pi-controller 26, 28, 30, which is derived from the difference signal S D - A first in first out memory means 36 generates a delayed signal S DLI out of the combined signal S COM - The delay in the memory means 36 is proportional to a clock period of the clock signal CL. The first in first out memory means 36 may be implemented in different ways. For example these means may be implemented as a chain of flip-flops. Otherwise these memory means may be a RAM having an address controller for cyclically changing the read and the write address. The correction signal generating means 22 also comprise feedback filter means 38 for filtering the delayed signal S DLI - The first in first out memory means 36 has a further output for providing a further delayed signal S DL2 to a reconstruction filter 40. The correction signal generating means 22 comprises further combination means 42 to generate the control signal Sc out of an output signal of the differentiating means 32, an output signal S P ι of the Pi-controller and an output signal of the reconstruction filter 40. A device for scanning a rotating record carrier usually has a seek mode in addition to a scanning mode. Generally in the seek mode, the controller used for controlling the radial position has a setting which differs from that in the scanning mode. The device shown in Figure 2 is characterized in that the delay loop 25 is coupled to the difference signal generating means 20 via the controller 26, 28. This has the advantage that when the device switches between seek mode and scanning mode, the data stored in the first in first out memory means remains relevant. On the contrary, in an embodiment wherein the controller is coupled to the difference signal generating means via the delay loop, the data in the first in first out memory means would be processed in a different way, when switching from one to the other mode. In the embodiment described above the scanning parameter which is controlled is a radial error. In a further attractive embodiment, wherein the transducer 10 comprises means for mapping a radiation beam at the information carrier, the scanning parameter is indicative of a property of a scanning spot formed by the radiation beam. Said property is for example a measure for the accuracy with which the beam is focussed at an information layer of the record carrier, or a measure for radial or tangential tilt of the beam. In this case the scanning parameter is related to the accuracy of the focus. To that end the difference signal generating means 20 also generate a focus error signal FE. The correction signal generating means 22 have a further PLD-controller and a delay loop similar to that shown in Figure 2, except that a control line analogous to the control line S SL is superfluous. Figure 3 shows an embodiment of the rotation speed detecting means 8. In that embodiment the rotation speed detecting means 8 comprise a first module 42 for generating a signal Si having a first frequency fj which is indicative of the rotation speed of the information earner 2. In this case, the first frequency f] is equal to 12 times the rotation frequency f rot . The first module 42 comprises a plurality of Hall-sensors coupled to the rotating means 4. A second module 44 is coupled to the first module 42 for generating a first intermediate signal Sji having a second frequency f 2 which is lower than the first frequency f] of the input by an integer factor. In casu f 2 = fJό. A third module 46 is coupled to the second module 44 for generating a second intermediate signal S I which is an indication of the duration D between two successive pulses of the first intermediate signal Sn. A fourth module 48 is coupled to the third module 46 for generating an output signal CL having a frequency which is dependent on the second intermediate signal Sι 2 . In the embodiment shown the fourth module 48 is coupled to the third module 46 via a fifth module 50. The fifth module 50 comprises a first input 51 for receiving the first intermediate signal Sn and a second input 52 for receiving the second intermediate signal Sι 2 . The fifth module 50 has an output 53 for providing to the fourth module 48 a third intermediate signal So which is indicative of a sum of two mutually successive values of durations D. In the embodiment shown the fifth module 50 has a first and a second delay element 54, 55 and an adder 56. The first delay element 54 has a data input D coupled to the output of the third module 46 and the second delay element 55 has a data input D coupled to the output O of the first delay element 54. Both delay elements 54, 55 have a clock input C which receives the first intermediate signal Sn The adder 56 has a first and a second input which are respectively coupled to the outputs O of the delay elements 54, 55. In said embodiment the output of the adder 56 is a signal So representing the duration of one rotation of the information earner 2 The fifth module 48 generates a pulsed signal in response to the signal S 13 provided by the adder 56. The generated signal CL compnses 64 pulses per rotation Figure 4 shows the delay loop of the circuit of Figure 2, compnsing the first in first out memory means 36 and the feedback filter means 38 in more detail. In Figure 4 it is shown that the first m first out memory means 36 compnse a chain of delay elements Xi,.. ..,τ n+2 The feedback filter means 38 is integrated with the said memory means 36 in that it is implemented as a FIR-filter having delay elements τ n 2 ,....τ n+2 which are part of the said memory means 36. The closed-loop transfer function G(z) of the delay loop formed by the first in first out memory means 36 and the feedback filter means 38 can be wntten as G{z) - —r Λ , wherein z M - H(z) H(z) is the transfer function of the FIR-filter 38 The FIR-filter 38 further compnses multiplication elements a 2 , ..., a + for respectively multiplying with a factor 5/32, 5/32, 11/32, 5/32 and 5/32, and an adder 39 for adding output signals of the multiplication elements The transfer function H(z) of said FIR-filter 38 is- rτ , , 5 _, 5 _, 11 5 5 2 H{z) = — z ~ + — z + — + — z + — z 32 32 32 32 32 The response of the delay loop corresponding to G(z) in the frequency domain is shown in Figures 5A and 5B Figure 5A shows the magnitude M(f) and Figure 5B shows the phase φ(f) of then response. From Figure 5A it is clear that the response has a high magnitude at a basis frequency equal to the rotation frequency (100 Hz in this embodiment) of the information earner 2 and at multiples of that frequency, while on the other hand the magnitude of the transfer function rapidly decays if the frequency deviates from those frequencies However, also around the clock frequency (6.4 kHz) of the clock signal CL the transfer function has a high magnitude due to aliasing effects. In order to suppress these contnbution to the transfer function, the control signal generating means 22 are provided with a reconstruction filter 40 Outputs of the delay elements τ n m , ..., τ n are coupled to respective inputs of a selection element 41. An output of the selection element 41 is coupled to the reconstruction filter 40 This makes it possible to adjust the phase of the output signal of the reconstruction filter 40 to the delay in the first in first out memory means 36. The reconstruction filter 40 is shown in more detail in Figure 6 The filter 40 shown is basically a second-order low-pass IIR filter which is controllable by a parameter p The ILR-filter 40 of Figure 6 compnses a first subtractor 60 for subtracting a feedback signal S FB from the input signal S DL2 - An output signal of the first subtractor 60 is multiplied with a parameter p in a first multiplier 61 The multiplied output signal is provided to a first input of a first adder 62. An output signal of said first adder 62, delayed by a delay element 63 is provided to a second input of the first adder 62. The output signal of the first adder 62 is further provided to a first input of a subtractor 64. The subtractor 64 has a second input for receiving the feedback signal S FB - The output signal of the subtractor 64 is amplified by a second amplifier 65 with the parameter p and the amplified signal is added to the feedback signal S FB in a second adder 66. The output signal of this adder is also the output signal of the reconstruction filter 40 The output signal is delayed by a delay element 67 so as to obtain the feedback signal S FB - The reconstruction filter shown has a transfer function F(z) defined by 2 2 F(Z) = — ^ z 2 - (2 - p - p-)z + (l - p) The magnitude M(f) of the combined response of the delay loop 34, 36, 38 and the reconstruction filter 40 is shown in Figure 7. In said response the aliasing effects are strongly suppressed Another implementation of the first in first out memory means 36 is shown in Figure 8. In that implementation the memory means 36 are the form of a RAM 70 having an address controller 71 for cyclically changing the read and the wnte address. The address controller 71 is in the form of a counter which increases the read address with 1 at each clock pulse of the clock CL. A wnte address is calculated by adding a constant n, for example 64, to the read address with an adder 72 A selection element 73, controlled by a read/wnte signal selects either the read or the wnte address. The selected address is used to read or wnte the RAM 70 Figure 9 shows an alternative embodiment of the correction signal generating means. In Figure 9, parts corresponding to those of Figure 2 have a reference number which ι< ; 100 higher. Said embodiment is charactenzed in that the correction signal generating means include differentiating means 131 via which the delay loop 125 is coupled to the difference signal generating means 20. The correction signal generating means further include integrating means 133 for integrating an output signal S DL2 of the delay loop 125. The output signal S DΓF of the differentiating means 131 can be represented by a relatively small number of bits in companson to the number of bits required for the input signal Spi. This embodiment therefore has the advantage that the delay loop 125 requires a relatively small amount of memory space, so that it can be easily integrated in a VLSI-implementation. The correction signal generating means 122 include the integrating means 133 to compensate for the differentiation. In the embodiment of Figure 9 the transducer (not shown) compnses means for mapping a radiation beam at a scanning spot of the information earner. The difference signal generating means generate a first difference signal RE indicative of the radial position of the scanning spot and a second difference signal FE indicative of a property of the scanning spot The delay loop 125 is coupled to the difference signal generating means by a multiplexer 129 which provides a multiplexed signal S PI to the delay loop 125, which is denved from the first RE and the second difference signal FE. In this case a first input signal of the multiplexer 129 is a signal S PIR , which is the output signal of a Pi-controller in response to the first difference signal RE. A second input signal of the multiplexer 129 is a signal S PIF , which is the output signal of a Pi-controller in response to the second difference signal FE More in particular the samples of the signal S PI are alternately taken from the signal S PIR and the signal S PΓF - The device further compnses a demultiplexer 141 coupled to an output of the delay loop 125 in order to generate a first output signal S DLR related to the first difference signal RE and a second output signal S DLF related to the second difference signal FE. The demultiplexer 141 is coupled to the output of the delay loop 125 via the integrating means 140. An embodiment of the differentiating means 131 is shown in more detail in Figure 10. The differentiating means 131 compnse delay elements 180, 180' for delaying the input signal S PI by two clockcycles. A subtractor 181 subtracts the delayed input signal from the input signal S P1 . As the input signal S PI is delayed by two clock cycles in the delay elements 180, 180', either two succeeding samples of the signal S PIR or two succeeding samples of the signal S PIF are subtracted from each other. An adder 182 adds a feedback signal to the output signal of subtractor 181. An output signal of adder 182 is limited by limiter 183 The output signal S DΓF of the limiter 183 is also the output signal of the differentiator 131. In a practical embodiment the limiter may generate an output signal which is limited to the values - 1,0,+1. In a subtractor 184 the output signal of the limiter 183 is subtracted from the input signal of the limiter 183 and delayed by delay element 185, 185'. The output signal of the delay element 185, 185' serves as the feedback signal. In the embodiment of Figure 10 the limiter 183 has the effect that the performance of the delay loop 125 is hardly influenced by spurious signals. Since the difference of the input and the output signal S D ι F of the limiter 183 are coupled back via the delay element 185, 185', systematic deviations as a result of the limiter 183 are prevented. The feedback filter 138 and a portion of the delay means 136 is shown in more detail in Figure 11. As compared to the embodiment shown in Figure 4 each delay element τ, is replaced by two succeeding delay elements τ, and τ,'. The multiplication elements a-2, ... a2 have an input which is respectively coupled to the outputs of the delay elements τ n-2 ', .... τ n+2 '. This has the effect that the FLR-filter alternatively calculates a feedback value related to the radial error RE and a feedback value related to the focus error FE. The integrating means 140 are shown in more detail in Figure 12. In that embodiment the integrating means 140 comprises an integrating module 140 A and a leak module 140β. The latter comprises combination means 190 for subtracting a leak signal S L from the input signal S DL2 of the integrating means. An output of the combination means 190 is coupled to an input of addition means 191 to add the output signal of the means 190 to a feedback signal S FBI - The feedback signal S FB I , which is also the output signal of the integrator, is obtained by limiting the signal provided by the addition means 191 in limiter 192 and delaying the limited signal with delay elements 193 and 193'. By subtracting the leak signal S it is prevented that a bias can occur in the integrating means. The leak signal S L is calculated from the feedback signal S FBI by the module 140 B . This module 140 B comprises combination means 194 for adding the feedback signal S FBI to a delayed error signal S DE . The output of the combination means 194 is multiplied by a factor 1/K in a multiplication element 195 so as to obtain the leak signal S L . K is a value greater than 1. Preferably K is a power of two, so that the multiplication can be implemented as a bit shift. The leak signal S L is multiplied by K in multiplier 196 and in subtractor 197 the result is subtracted from the output of combination means 194 to obtain an error signal S E . This error signal S E is delayed by delay elements 198, 198' to obtain the delayed error signal S DE - It is remarked that the scope of protection of the invention is not restricted to the embodiments described herein. For example, while an embodiment of the apparatus according to the invention is described in which a clock signal which is indicative of the rotation speed of the information carrier is derived from circuit means which are coupled to the motor, such a clock signal may also be derived from data which is read from the disc. Neither is the scope of protection restricted by the reference numerals included in the claims. The word 'comprising' does not exclude other parts than those mentioned in a claim. The word 'a(n)' preceding an element does not exclude a plurality of those elements. The invention further resides in each new feature or combination of features.

Claims: CLAIMS 1 A device for scanning a rotating information earner (2) compnsing rotating means (4) for rotating the information earner around an axis (6), a transducer (10) for converting a wnte signal (S w ) into a detectable pattern at the information earner, and/or for detecting a pattern at the information earner and generating a read signal (S R ) in response thereto, control means (20, 22) for controlling a scanning parameter of the transducer (10), wherein the control means compnse difference signal generating means (20) for generating a difference signal (RE) which is indicative of a difference between a current value and a desired value of the scanning parameter, correction signal generating means (22) for generating a correction signal (Sc) in response to the difference signal (RE), the correction signal generating means (22) compnsing a delay loop (25) which includes combination means (34) for generating a combination signal (S COM ) out of a feedback signal (S F ) and an input signal (S P denved from the difference signal (RE), first in first out memory means (36) for generating a delayed signal (S DLI ) out of the combined signal and feedback means (38) for generating the feedback signal (S F ) out of the delayed signal (SDLI), charactenzed in that the device compnses rotation speed detecting means (8) for generating a clock signal (CL) having a frequency which is indicative of the rotation speed of the information earner (2), the delay in the memory means (36) being proportional to a penod of the clock signal (CL) 2 A device according to claim 1 , charactenzed in that the scanning parameter (RE) is indicative of a radial position of a scanning spot (14) scanned at the record earner (2) 3 A device according to claim 1, charactenzed in that the transducer (10) compnses means for mapping a radiation beam (12) at a scanning spot (14) of the information earner (2) and in that the scanning parameter (FE) is indicative of a property of said scanning spot 4. A device according to claim 1, characterized in that the transducer (10) comprises means for mapping a radiation beam (12) at a scanning spot (14) of the information carrier (2) and in that the difference signal generating means generate a first difference signal (RE) indicative of the radial position of the scanning spot (14) and a second difference signal (FE) indicative of a property of the scanning spot (14), and in that the delay loop (125) is coupled to the difference signal generating means (22) by multiplexing means (129) which provide a multiplexed signal (Spi) to the delay loop (125), which is derived from the first and the second difference signal, the device further comprising a demultiplexer (141) coupled to an output of the delay loop (125) in order to generate a first output signal (S DLR ) related to the first difference signal and a second output signal (S DLF ) related to the second difference signal. 5. A device according to claim 1, characterized in that the rotation speed detecting means (8) comprise a first module (42) for generating a signal (Si) having a first frequency (fl) which is indicative of the rotation speed of the information carrier (2), a second module (44) coupled to the first module (42) for generating a first intermediate signal (Sn) having a second frequency (f2) which is lower than the first frequency by an integer factor, a third module (46), coupled to the second module (44), for generating a second intermediate signal (Sn) which is an indication of the duration D between two successive pulses of the first intermediate signal (Sn), a fourth module (48) coupled to the third module (46) for generating an output signal (CL) having a frequency which is dependent on the second intermediate signal (Sι 2 ). 6. A device according to claim 5, characterized in that the fourth module (48) is coupled to the third module (46) via a fifth module (50), which fifth module comprises a first input (51) for receiving the first intermediate signal (Sn), a second input (52) for receiving the second intermediate signal (Sn), and an output (53) for providing to the fourth module (46) a third intermediate signal (Sι 3 ) which is indicative of a sum of mutually successive values of durations D. 7. A device according to claim 1, characterized in that the correction signal generating means (22) comprises signal separating means (27) for separating the difference signal (RE) into a high frequency component (S H ) and a low frequency component (S L ), the correction signal generating means (22) comprising HF-means (32) for processing the high- frequency component (S H ) of the signal and LF-means (26, 28, 30, 25, 40) for processing the low frequency component (S L ) thereof. 8. A device according to claim 1, characterized in that the correction signal generating means include differentiating means (131) via which the delay loop (125) is coupled to the difference signal generating means (22) and in that the correction signal generating means further include integrating means (140) for integrating an output signal (S DL2 ) of the delay loop (125). 9. A device according to claim 1 , characterized in that the correction signal generating means (22) comprise a controller having an integrating unit (28) and a proportional unit (26), the delay loop (25) being coupled to the difference signal generating means (20) via the controller (26, 28).

Inventors: AKKERMANS ANTONIUS H M, DEKKER ANTHONIUS L J, AKKERMANS, ANTONIUS, H., M., DEKKER, ANTHONIUS, L., J.
Applicants: KONINKL PHILIPS ELECTRONICS NV, KONINKLIJKE PHILIPS ELECTRONICS N.V.
Application year: 2000
Main classification: G11B7
IPC codes: G11B7, G11B21