A SYSTEM FOR PROVIDING AN INTEGRATED CIRCUIT WITH A UNIQUE IDENTIFICATION

Abstract: An integrated circuit identification device (ICID) (38) to be incorporated into an integrated circuit (IC) (40) includes an array of electronic cells (46) in which the magnitude of an output signal of each cell is a function of randomly occurring parametric variations which vary from cell-to-cell. The ICID (38) also includes a circuit for measuring (50) the output of each cell and for producing output data having a value reflecting the particular combination of measured characteristics of all of the elements of the array (46). When we make the number of elements in the array (46) large enough, we insure that to a high degree of probability, the pattern of measured array cell characteristics for an ICID (38) embedded in any one IC (40) will be unique and distinguishable from such patterns measured by ICIDs (38) embedded in millions of other ICs (40). Thus the value of the output data produced by an ICID circuit (38) acts as a unique "fingerprint" for the IC (40) in which it is installed, and can be used as a unique identification (ID) for that IC (40).

Description: A SYSTEM FOR PROVIDING AN INTEGRATED CIRCUIT WITH A UNIQUE IDENTIFICATION Background of the Invention Field of the Invention The present invention relates m general to a system for uniquely identifying an integrated circuit (IC) , and m particular to a device that may be embedded m the IC which, due to randomly occurring chip-to-chip or device-to-device parametric variations, produces a unique output identification for each IC chip m which it is implemented. Description of Related Art Integrated circuits are manufactured with batch processing intended to make all integrated circuit chips identical, thereby lowering manufacturing costs and improving quality. However, it is useful to be able to distinguish each individual integrated circuit from all others, for example to track its source of manufacture, or to identify a system employing the integrated circuit. Individually identifiable integrated circuits can be used to validate transactions, route messages, track items through customs, verify royalty counts, recover stolen goods, validate software, and many other uses . It has been known to include circuits within a chip that produce a signal identifying the nature or type of the chip. U.S. Pat. No. 5,051,374, issued September 24, 1991 to Kagawa et al . , "Method of manufacturing a semiconductor device with identification pattern" , shows a technique for identifying the type of mask-programmed read-only memory (ROM) . ROMs of different types may have indistinguishable visible structures, but the special processing steps described m this patent produce a visible pattern on the ROM identifying its nature. U.S. Pat. No. 4,150,331 issued April 17, 1979 to Lacher, "Signature encoding for integrated circuits", describes an embedded system that puts a type-specific identifier on the pins of a circuit when stimulated. U.S. Pat. No. 5,079,725 issued January 7, 1992 to Geer et al . , "Chip Identification Method for use with Scan Design Systems and Scan Testing Techniques", describes a method for incorporating type specific identification into a scan test chain. These methods of identification are useful for indicating the type of component being manufactured or placed m an assembly, but they do not distinguish individual chip one from another. It has been also known to customize each individual chip as it is manufactured m order to make it uniquely identifiable. Such customization may be performed as the chip is fabricated, typically by inscribing a unique pattern on its die, or after it is fabricated, for example, by employing electrical or laser signals to alter its circuitry m some way. U.S. Pat. No. 5,642,307 issued June 24, 1997 to Jernigan, "Die Identifier and Die Identification Method" includes a non-volatile, programmable read-only memory (PROM) on a chip. After the chip is fabricated, the PROM is programmed to store a date, a lot number, a wafer number, and a wafer position, as well as other useful manuf cturing data. U.S. Pat. No. 4,419,747, issued December 6, 1983, to Jordan, "Method and Device for Providing Process and Test Information in Semiconductors", stores similar information m an extension of an existing programmable memory array. The information may be read back when an unusual combination of voltages is placed on the input pins and detected by the chip, overriding the normal function of the device. U.S. Pat. No. 5,056,061, issued October 8, 1991 to Akylas et al . , "Circuit for encoding identification information on circuit die using FET capacitors" discloses the use of high voltage signals to break down a capacitor structure within each individual chip so that some aspect of the chip's behavior is permanently altered m some identifiable way. U.S. Pat. No. 5,553,022, issued September 3, 1996 to Weng et al . , "Integrated circuit identification apparatus and method", performs a similar breakdown on the gate oxide of a MOSFET. In both cases an oxide is permanently altered, and this requires careful circuit design and process characterization to do reliably. U.S. Pat. No. 4,766,516, issued August 23, 1988 to Ozdemir et al . , "Method and apparatus for securing integrated circuits from unauthorized copying and use", teaches us to electronically alter a semiconductor die with lasers or focused ion beams. While such approaches are effective to provide each chip with an ID, the additional processing steps needed to customize each individual chip add time and cost to the chip manufacturing process. Other techniques do not result m an electrically detectable modification of the integrated circuit die. Instead, they physically inscribe a pattern onto an unused portion of the die surface, to be observed optically by a machine or by a person using a microscope. U.S. Pat. No. 5,350,715, issued September 27, 1994 to Lee, "Chip identification scheme" teaches applying a pattern of dots to electrically inactive areas on each die site on a wafer. This may be done with an additional mask step applied to the whole wafer. U.S. Pat. No. 4,510,673, issued April 16, 1985 to Shils et al . , "Laser written chip identification method", describes using an X-Y controllable laser beam to produce identification patterns on the surface of a chip. While such methods can provide each chip with a unique identification, they require special processing steps during the semiconductor manufacturing process that add cost and time to the manufacturing process. What is needed is a method for reliably and easily identifying and authenticating individual integrated circuits that does not require any additional manufacturing steps or equipment. Summary of the Invention An integrated circuit identification (ICID) circuit m accordance with one aspect of the invention produces a unique identification number or record (ID) for each chip m which it is included even though the ICID circuit is fabricated on all chips using identical masks. The ICID circuit includes a set of circuit cells and produces its output ID based on measurements of outputs of those cells that are functions of random parametric variations that naturally occur when fabricating chips. When the number of cells is large enough, each of millions of chips can be provided with a unique identifying ID without having to customize each chip. In accordance with another aspect of the invention, the cells are organized into an array and the ICID circuit also includes a circuit for selecting each cell of the array m turn, measuring that element's output, and producing the chip ID based on the pattern of measured outputs of all cells of the array. When the number of elements m the array is large enough, the pattern of measured array element characteristics for an ICID circuit of one IC chip will be unique to a high degree of probability. The identification pattern will differ from that of an ICID circuit of any other IC, even when similar ICID circuits are installed m millions of other IC chips. Thus the value of the output data produced by an ICID circuit acts as a unique "fingerprint" for the chip m which it is installed that can be employed as an easily accessed chip-unique ID. In accordance with a further aspect of the invention, m a preferred embodiment thereof, the elements of the array are suitably pairs of metal oxide semiconductor field effect (MOSFET) transistors having interconnected sources and gates. The measurable output of each MOSFET pair represents the difference between their dram currents, which is highly susceptible to fluctuations that naturally occur m chip fabrication. The ICID circuit of the present invention provides a means for enabling each of millions of chips to uniquely and reliably identify itself without having to customize each individual chip using costly and time-consuming additional processing steps during or after chip fabrication. The concluding portion of this specification particularly points out and distinctly claims the subject matter of the present invention. However, those skilled m the art will best understand both the organization and method of operation of the invention, together with further advantages and objects thereof, by reading the following descriptions m view of the accompanying drawings wherein like reference characters refer to like elements. Brief Description of the Drawing (s) FIG. 1 illustrates m block diagram form an integrated circuit having mtalled therein an identification circuit (ICID) m accordance with the invention; FIG. 2 illustrates the ICID device of FIG. 1 m more detailed block diagram form; FIG. 3 illustrates the array of identification cells of FIG. 2 m more detailed block diagram form; FIG. 4 is a schematic diagram illustrating a typical identification cell of FIG. 3; FIG. 5 is a graph illustrating the normal mismatch of dram currents found two nominally identical P channel MOSFETs; FIG. 6 is a cross section of a MOSFET, illustrating the effect of fixed bulk charges on the MOSFET voltage threshold; FIG. 7 is a graph illustrating the statistical distribution of threshold voltage mismatches for two different MOS processes; FIG. 8 is a schematic diagram illustrating five individually selectable identification cells connected to a pair of output lines and a pair of load resistors; FIG. 9 is a graph of the differential voltage output produced from the five sequentially selected identification cells of FIG. 8; FIG. 10 illustrates the measurement circuit of FIG 2 in more detailed block diagram form; FIG. 11 illustrates the load and error detection portions of the measurement circuit of FIG 10 m schematic diagram form; FIG. 12 illustrates the auto- zeroing comparator of FIG. 10 schematic diagram form; FIG. 13 is a timing diagram illustrating behavior of signals the auto- zeroing comparator of FIG 12; FIG. 14 illustrates the stimulus circuit of FIG. 2 m more detailed block diagram form; FIG. 15 illustrates the address sequencer and timing strobe generator of FIG. 14 ; m schematic diagram form; FIG. 16 is a timing diagram illustrating waveforms m the ICID circuit of FIG. 2 ; FIG. 17 illustrates a type identification cell m schematic diagram form; FIG. 18 is a pair of tables illustrating the formation of a sorted identification record; FIG. 19 plots the probability of bit errors as a function of threshold drift; FIG. 20 plots the statistical distribution of absolute norms resulting from 25 percent threshold drift for one trillion samples. Description of the Preferred Embodiment (s) The present invention relates to an integrated circuit identification (ICID) circuit 38 as illustrated m FIG. 1 that may be incorporated into an integrated circuit (IC) chip 40 along with other circuits 42. In response to control and timing data arriving via control inputs 36, ICID 38 generates an output data sequence (ID) at IC output terminal ID that uniquely identifies IC chip 40. After fabricating IC chip 40, a manufacturer may record the output ID of ICID circuit 38 an identification record 44. Thereafter that particular chip 40 can be identified whenever and wherever that chip may be found by the unique ID produced by its ICID 38 when control inputs 36 signal it to do so. It has been known to provide each of a large number of IC chips with a non-volatile memory for storing and reading out an ID uniquely identifying each chip. However such prior art chip ID systems require that a separate ID be written into each individual IC using additional processing steps during or after IC fabrication. The additional customizing steps for each IC add time and cost to the IC manufacturing process. ICID 38, on the other hand, does not have to be customized any way for each chip m which it is installed m order to ensure that its output ID is unique for each chip. Even though the same ICID 38 may be installed on millions of IC chips, the probability is low that the ICID circuits of any two chips will generate the same output ID number. The ICID circuit is therefore an improvement over prior art chip identification systems because it doesn't require any customization of individual ICs. ICID 38 achieves this feat by deriving its output ID from measurements of a set of circuit parameters that naturally vary from chip-to-chip and from circuit element-to-element. Due to natural, random parametric variations, no two ICs are really alike. For example, try as we might, it is not possible to make two identical transistors even though we may form them by similar processes, using similar masks, in adjacent areas of the same IC die. We cannot make two transistors identical because their dimensions are the result of the random accumulation of photons through the photomask and their doping levels and distributions are the result of the random distribution of doping atoms from thermal diffusion and ion implantation. Designers have long been aware of the effect of such random parametric variations on the behavior of transistors and other IC circuit elements and have taken them into account when designing ICs. A good IC design ensures that all copies of an IC behave as expected even though the transistors and other circuit elements forming the ICs exhibit a random variation in operating characteristics from element-to-element and from chip-to-chip. While such random parametric variations have been a problem that IC designers have had to overcome, ICID 38 of the present invention makes beneficial use of them. In the preferred embodiment of the invention, each ICID 38 includes an array of identically designed cells. Each cell is suitably a simple transistor circuit that produces a pair of currents whose difference is influenced by random parametric variations affecting the operating characteristics of the transistors forming the cell. ICID 38 measures the difference between the two output currents of each cell of the array and encodes the measurements for all cells into a single output ID that is unique to that particular combination of measurements. When the array is large enough, there is a very low probability that the cell array of an ICID 38 installed any one IC chip will produce the same combination of measurements as an ICID circuit installed m any of millions of other IC chips. Thus an ID generated such fashion can be used as a unique ID for each chip. ICID 38 is advantageous over prior art chip identification systems because it does not require any custom modification to each individual chip during or after its fabrication m order to make its ID unique. The acquisition and logging of a chip's ID can be easily and quickly done by an IC tester when it tests the chip's logic. ICID Architecture FIG. 2 illustrates ICID circuit 38 of FIG. 1 more detailed block diagram form. ICID circuit 38 includes an array 46 of rows and columns of cells. Each cell of array 46, when selected produces a pair of output currents IH and IL on array output lines AOH and AOL. The IH and IL currents are produced by similar transistors within the selected cell and are nearly equal. But due to differences the transistors resulting from random parametric variations, the IH and IL currents will not exactly match. The difference between the IH and IL currents will vary from cell to cell. A stimulus circuit 48 responds to the control input 36 by supplying row select data (ROW) and a column select data (COL) to array 46 to individually select and stimulate each of its cells m turn. As it selects a cell, stimulus circuit 48 sends timing signals (TIMING) to a measurement circuit 50 telling it when to measure a difference between the currents IH and IL of the selected cell . In the preferred embodiment of the invention, each cell includes P channel, metal oxide silicon field-effect transistors (MOSFETs) . Stimulus circuit 48 also produces an N-Well bias control line WELL for controlling the bias for the N-Well underneath the P channel MOSFETs m the identification cell array 46. When the ICID circuit is enabled, the N-Well is biased on, at the positive supply voltage, allowing the identification array to operate. When the ICID circuit is disabled, the N-Well is biased to the negative supply voltage, along with all the other signal lines connected to the identification cell array 46. This eliminates electrical stresses on the identification cells when the ICID circuit is not being used, helping protect the cells against drift. Measurement circuit 50, sequenced by TIMING strobes from stimulus circuit 48, measures the current difference between IH and IL for each cell and, as described in detail below, produces a serial output ID having a value that is base on the particular pattern of measured current differences for all cells of array 46. Cell Array FIG. 3 illustrates array 46 of FIG. 2 in more detailed block diagram form and FIG. 4 illustrates a typical cell 62 of array 46 in schematic diagram form. Although for simplicity FIG. 3 shows array as including a set of three rows and six columns of cells 62, the number of cells 62 that should be included in array 46 is largely a function of the number of ICs to be uniquely identified. As discussed below, when ICID 38 of FIG. 2 is to be employed in several million ICs, a larger array (for example 16x16) is required to provide the needed ID resolution. FIG. 4 shows that each cell 62 includes a pair of substantially similar P channel MOSFETs 66 and 68 having gates connected in common to one bit 60 of the ROW select data from stimulus circuit 48 of FIG. 2 and having sources connected in common to one bit 58 of the COL select data from stimulus circuit 48. A pair of output wires, AOH and AOL, connect to all the cells of array 46. The drains of all MOSFETs 66 of each given cell row connect to AOH, and the drains of all MOSFETs 68 connect to AOL. Stimulus circuit 48 of FIG. 2 selects and stimulates a particular cell 62 by pulling its COL select line 58 high, while pulling its ROW select data bit 60 to an analog bias voltage. This turns on both MOSFETs 66 and 68 of the cell, with the ROW and COL select bit line voltages adjusted to drive the two MOSFETs into the saturation region of operation. As the two MOSFETs of a selected cell 62 turn on they conduct current through their dra s, and their dram currents appear on array output lines AOH and AOL. The AOH and AOL lines are terminated with loads inside the measurement circuit 50, and are biased at a sufficiently low voltage to insure that the unselected cells elsewhere on the selected row will not conduct. If the MOSFET pair 66 and 68 m the selected cell were truly identical, they would produce identical dram currents into AOH and AOL. However since random parametric variations ensure that MOSFETS 66 and 68 will differ somewhat even though we try to make them similar, their dram currents IH and IL will be somewhat mismatched. The amount of mismatch reflects the amount of parametric variation between the two transistors. FIG. 5 plots the dram current of two MOSFETs having mismatched voltage thresholds, as the gate voltage is varied. The MOSFET producing current 72 turns on at threshold 76, while the MOSFET producing current 74 turns on at threshold 78 resulting m a threshold voltage mismatch 80. Since MOSFETs are nonlinear devices, the dra current difference between the devices can be expected to increase with voltage. However, with an equally nonlinear load m measurement circuit 50 of FIG. 2, the threshold difference between the devices can be expected to produce a nearly constant output difference voltage. MOSFETs may also vary m conductivity as well as threshold, and variations conductivity would appear m the graph of FIG. 5 as a difference of slope. Since conductivity variations may be a function of fixed pattern variations m mask features, it is important to bias the array at low currents so the threshold variations, which are not as mask dependent, can dominate. FIG. 6 illustrates a typical MOSFET 84 m simplified cross-section including a gate 86, a source 88, and a dram 90 formed on a substrate 92. The voltage threshold of the MOSFET is typically a weak function of the width and length of the channel and the doping of the gate conductor, and a strong function of the random placement of dopant atoms 94 imbedded in the semiconductor channel material of the substrate under the gate oxide. If the transistor is constructed properly, these dopant atoms are fixed in place, and do not move unless subjected to unusually high electric fields or temperatures. This means that the threshold voltage for an individual MOSFET tends to stay fixed over time, though the threshold voltage will vary from device-to-device due to variation in the position and number of dopant atoms 94 in each transistor channel. MOSFET threshold mismatch When we interconnect pairs of MOSFETs in the manner illustrated in FIG. 4, their threshold voltage mismatch typically produces a difference in their drain currents of approximately one percent of their maximum values when the two MOSFETs 66 and 68 are nominally similar. The drain current mismatch can be divided by the MOSFET transconductance gain to infer the threshold voltage mismatch, which follows a Gaussian statistical distribution. FIG. 7 shows two Gaussian distributions, a narrower distribution 104 for a 0.5 micron effective channel length and a wider distribution 102 for a 0.3 micron effective channel length, based on data from "Experimental Study of Threshold Voltage Fluctuation Due to Statistical Variation of Channel Dopant Number in MOSFETs" by Tomohisa Mizuno et al . , IEEE Transactions on Electron Devices, Vol. 41, No. 11, November 1994, pp. 2216-2221, incorporated herein by reference. The paper shows that the variation is independent of distance and uncorrelated between neighboring pairs of devices. The increase in mismatch for shorter channel processes increases the random parametric variation and thus the robustness of identification provided by the ICID circuit. See also "Intrinsic MOSFET Parameter Fluctuations Due to Random Dopant Placement" by Xinghai Tang, et al , IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 5, No. 4, December 1997, pp 369-376, also incorporated herein by reference. Sequencing through multiple identification cells FIG. 8 illustrates a single row of cells 62 of array 46 of FIG. 3 sharing a common ROW select bit line 60, and common output lines AOH and AOL, with each separately connected to positive power supply rail 106 through one of a set of source selection switches 108 that are implemented inside stimulus circuit 48 of FIG. 2. The array output lines AOH and AOL are connected to a differential pair of output load resistors 110 representing the input impedance of measurement circuit 50 of FIG. 2. A threshold voltage mismatch m the pairs of MOSFET produces a current mismatch between IH and IL, thereby developing a differential voltage VX across load resistors 110. If the transconductances of the MOSFETs and of the load devices are similar, the circuit will have unity gam; a 10 millivolt threshold mismatch will result m a 10 millivolt differential output voltage. However, mismatches m the load resistors will add a constant voltage offset to the differential voltage VX . The upper MOSFET m each cell is oriented 180 degrees to the lower MOSFET, and has a different geometric center. These two effects produce offset voltage between the devices that may exceed the random mismatch voltage. However, all pairs m the array will have the same orientation and difference m geometric centers, so this too will act as a DC offset to the whole curve, which will disappear if only the step changes are observed. FIG. 9 plots as a function of time the dram difference voltage VX across resistors 110 resulting from the difference between IH and IL when each of the five cells 62 of FIG. 8 are selected sequentially. Although a load mismatch will shift the whole curve up and down, transitions between the steps tend to remain unaffected. Thus, a more repeatable output ID results when measurement circuit 50 of FIG. 2 bases the value of the output ID on the pattern of transitions between measured voltages for successively selected cells rather than directly on the output voltage levels themselves. The measurement circuit FIG. 10 illustrates measurement circuit 50 of FIG. 2 m more detailed block diagram form. FIG. 11 shows portions of ICID circuit 50, along with relevant portions of array 46 and stimulus circuit 48 m schematic diagram form. Referring to FIGs . 10 and 11, a load circuit 114 converts the currents IH and IL from cell array 46 of FIG. 2 into a cell output voltage VX sensed by an auto-zeromg comparator 120. Auto- zeroing comparator 120 compares the value of the output voltage VX produced by the most recently selected array cell with the value of the VX voltage output of a the previously selected array cell and produces a binary output signal (BIT) indicating which of the two successive VX voltages is higher. When the ICID circuit is behaving properly, error detection circuit 118 produces a logic zero followed by a logic one on each error output ERR during a portion of every identification period. There are eight clock cycles m an identification period. During four of these clock cycles, the output ID of the output selector 122 is driven by the zero and one from the first error output ERR, then subsequently by the zero and one from the second error output ERR, delayed by two clock cycles. During the other four clock cycles, the output ID is driven by the repeated BIT output of the auto-zeromg comparator 120. Under normal circumstances, the output ID sequence for one identification is "0, 1, 0, 1, BIT, BIT, BIT, BIT". If the error detection circuit detects an error, the "0,1,0,1" output preamble will be different, indicating that the identification may not be trustworthy. Load and error detection circuits FIG. 11 is a circuit diagram illustrating various circuit elements m the ICID measurement circuit 50. FIG. 11 also illustrates a portion of stimulus circuit 48 of FIG. 2 that generates the ROW select bit line analog voltage level, along with an example identification array cell 62. In the stimulus circuit 48, each ROW select line 60 is linked through a diode-connected bias MOSFET 128 to a switch 126, which may further link the line to either a positive rail, or to a current source 124. Switch 126 is connected to current source 124 when the row is selected. The current from current source 124 flows through MOSFET 128, causing it to turn on and to produce a low analog voltage on ROW select line 60. If the row is not selected, switch 126 connects ROW select line 60 to the positive rail, turning off all the transistors in the unselected row. MOSFET 128 is suitably made similar to the MOSFETs in each cell 62, so that substantially similar currents to 124 will flow through array output AOH and AOL, and into the load circuit 114. In the load circuit 114, the IH and IL currents terminate in matching load devices 136. The load devices include series and parallel combinations of P channel MOSFETs, also. similar to the MOSFETs in each cell 62. A square array of MOSFETs connected with equal numbers of MOSFETs in series and in parallel will have substantially the same DC behavior as a single MOSFET. However, such an array will have a smaller statistical variation, so the four MOSFETs illustrated as a series-parallel composite in each half of 136 will behave like a single MOSFET, and the pair of composite MOSFETs will behave like a pair of single MOSFETs with improved matching. P channel MOSFETs are used as load devices because they have substantially the same relationship between transconductance and current as the MOSFETs of the cell, resulting in the same nonlinearities . This means that a mismatch voltage inside a cell will appear substantially the same at the loads and between the array output lines AOH and AOL and will be independent of the current. The output voltage will therefore be relatively resistant to biasing variations, or common mode noise coupled into the system. The relative sizes of the signal steps, and the resulting identification sequence, will be more constant over time. Load devices 136 act as source followers from the analog load bias voltage 130. The voltage biasing the load is generated from a current 134 across a diode-connected MOSFET 132. The current 134 is eight times the current 124. Thus the voltage on bias line 130 is lower than the voltage on ROW select line 60, and is low enough to ensure that the voltages on the array output lines AOH and AOL are always low enough to keep the MOSFETs in the selected cell 62 in saturation. Although there are many transistors connected in series, in no case is more than one voltage threshold plus a few saturation voltages necessary to bias the circuit for proper operation. As a result, with appropriate reductions in operating current and clocking frequency, the ICID circuit can be operated at very low voltages, barely exceeding the voltage threshold of a MOSFET. While other circuit topologies may be developed offering improved performance with large power supplies, this circuit topology will perform reasonably over a wide range of supplies. In addition, the voltages across the devices minimize such electrical stresses as hot carrier degradation of gate oxides, further protecting the stability of the identification cell array. Two of the drains from load transistors 136 divert current into the error detection lines 116. The diverted current is connected to the drains of N channel MOSFET current mirrors 144, which mirror the current that current source 140 outputs through diode connected N channel MOSFET 142. If the current mirror MOSFETs 144 produce more current than the error detection lines 116 get from the load devices 136, the lines are pulled low. This causes buffers 146 to produce low logic levels on error outputs ERR. If the load device currents are higher than the current mirrors 144 produce, the error detection lines 116 are pulled high, incidentally modifying the voltages on array output lines AOH and AOL. Current source 140 is controlled by TIMING signals to produce a sequence of comparison currents. For most of the identification cycle, this current is set at a high value, causing the error detection lines 116 and error outputs ERR to remain low. During one clock period out of the eight clock long identification period, the comparison current 140 is lowered to a value setting an upper threshold level for the array output line current. If AOH or AOL is pulled up too strongly, due to a defect, one of the error detection lines 116 will be pulled high, indicating the defect on one of the error outputs ERR. Otherwise, the error output will stay low during this period. During the subsequent clock period, the current 140 is lowered further to the lower threshold value for the array output line current . Under normal circumstances, this will cause both error detection lines 116 to be pulled high. However, an array defect may cause either AOH or AOL to pull up too weakly, and one or both of the error detection lines 116 will remain erroneously low. Thus, if the IH and IL currents are within an appropriate range, we will see a logic zero followed by a logic one on each of the error outputs ERR. A defect in the array causing more than one row or column to be selected, or one of the identification transistors to be egregiously large, will thus cause two logic ones on one of the error outputs ERR. If no rows or columns are being selected, or there is an open in a MOSFET or an interconnection device, we will see two logic zeros. Defects may arise from decoding or logical errors in the address sequencer. Whatever the source of error, most of them may be detected and isolated by observing the error output lines ERR for the correct sequence of pulses. Error detection circuit 118 thus adds to the trustworthiness of the ICID circuit, though due to the small size of the ICID circuit the chances of its encountering any defect at all is quite small, perhaps 100 parts per million. Auto- zeroing comparator FIG. 12 illustrates a suitable implementation of the auto-zeroing comparator 120 of FIG. 10. Comparator 120 includes two limited-gain amplifiers 174 and 182 for amplifying the array output voltage VX on array output lines AOH and AOL, and a strobed comparator 188 for converting the analog difference into a binary output on line BIT. Comparator 188 is strobed by a timing control signal (SAMP) from stimulus circuit 48 of FIG. 2. Amplifiers 174 and 182 have voltage gains of approximately five, giving them relatively high bandwidth and making them insensitive to process variation Amplifiers 174 and 182 are suitably constructed with large transistors arrayed m common centroid geometries to minimize voltage offsets and to maximize power supply noise rejection. The first amplifier 174 is coupled to amplifier 182 through coupling capacitors 176. Switches 180, controlled by control signal ZERO from stimulus circuit 48, auto-zero these capacitors. Auto-zeromg comparator 120 measures the size of the differential voltage change between two successive values of VX produced by successively selected identification cells. Amplifier 174 amplifies and inverts VX to drive the front end of coupling capacitors 176. The output of capacitors 176 drives the differential line pair 178, the input to amplifier 182. During the autozero portion of the identification period, switches 180 are closed, connecting the output of the second amplifier stage 182 back to its inverted input. This results m forcing the differential line pair 178 to a small difference voltage, approximately the residual input offset of second amplifier 182, and independent of the voltage on amplifier 174. A voltage is impressed across the capacitors 176 equal to the array output voltage VX as amplified by the first amplifier 174. Switches 180 are then opened, and the voltage at nodes 178 remains small. Subsequently, a second identification cell is selected. This produces a new voltage VX on array output lines AOH and AOL, which is amplified by the first amplifier 174 to change the voltage at the input side of the capacitors 176. Because the capacitor outputs 178 have been disconnected by the switches, they are free to follow the change of voltage on their input side, causing the differential voltage on lines 178 to change from their precharged value to a new value proportional to the change m VX multiplied by the gam of the first amplifier stage 174. This change is further amplified by the gam of the second stage amplifier 182, to produce a greatly amplified voltage change on the strobed comparator inputs 184. After the voltage step has settled on lines 184, the comparator 188 is strobed with comparator timing strobe SAMP. This causes the comparator to resolve the positive or negative voltage change into a logic one or zero on comparator output line BIT. Additional switches and control signals may be added to the auto-zeromg comparator circuit to enhance its performance. In particular, large voltage glitches at the input may occur when switching from one identification cell to the next, and switched clamps may help the comparator settle after these large voltage glitches. The stimulus circuit FIG. 14 illustrates stimulus circuit 48 of FIG. 2 m more detailed block diagram form. Stimulus circuit 48 responds to input data and control signals 36 by supplying the appropriate ROW and COL selects to sequentially select and stimulate the cells m the identification array 46, and by generating the TIMING strobes for controlling the measurement circuit 50. Stimulus circuit 48 includes a conventional sequencer 202 for providing output binary addresses and a pair of decoders 206 and 208 for decoding those addresses to produce the ROW and COL selects supplied to the cell array. Stimulus circuit also provides the N-Well bias control signal WELL. FIG. 15 illustrates a suitable implementation of sequencer 202 of FIG. 14. In this implementation, row and column addresses are generated outside the ICID circuit by circuits that may be withm or external to IC 40 of FIG. 1. These addresses are serially shifted into a shift register 216 via an INPUT of the control inputs 36. When an address is has been shifted into register 216, it is written into a latch 218 and used to address the cell array via decoders 206 and 208 of FIG. 14. Sequencer 202 includes a clock divider 220 for frequency dividing a CLOCK line of the control inputs 36 by a factor of eight to produce a binary count applied as input to a timing strobe decoder 222. Decoder 222 produces TIMING strobes for shift register 216 and address latch 218 as well as the TIMING strobes needed to control event timing m the measurement circuit 50 of FIG. 2. An ENABLE line of control inputs 36 is driven high to enable the clock divider 220 and strobe decoder 222 to initiate the measurement process. The control inputs 36 to sequencer 202 may suitably be a provided by a conventional JTAG bus driven by a conventional address counter and clock when the controller is external to the IC. Circuit Timing FIG. 16 illustrates timing of various signals of the ICID circuit illustrated m FIGS. 2, 10, 11, and 15. The top waveform illustrates the periodic behavior of the input control signal CLOCK. All activities are suitably gated off the rising edge of this clock, though the opposite edge or both edges may be used. INPUT data is captured into the input shift register 216 parallel loaded into address latch 218 once every eight clocks. An address latch 218 is strobed eight clock times after the appearance of the first bit of the address on the INPUT. The eight clock "identification period" may be longer when array 46 of FIG. 3 requires more address bits. Four bits of the latched address are decoded into one of 16 COL select lines 58. The other four bits of the latched address are decoded into one of 16 ROW select lines 60. The COL select lines 58 are asserted positive, while the ROW select lines 60 are asserted negative. For an interval around the address transition, all the COL select lines 58 are precharged low, and all the ROW select lines 60 are precharged high. This de-selects all the identification cells in the identification cell array 46. During the same precharge interval, the disconnected array output lines AOH and AOL are precharged high. When the row and column lines are asserted, one of the identification cells is selected, and the array output lines AOH and AOL change to values reflecting the difference voltage. The voltage change is measured by the auto-zeromg comparator m the measurement circuit, producing the comparator output BIT. The differential array output AOH and AOL will normally produce mid-range load currents as shown during the first segment 234 of the load current waveform. However, a defect may cause either no identification cells to be selected, as illustrated by the lower line of second segment 236, or two identification cells to be selected, as illustrated in the upper line of segment 236. This will cause the current through at least one side of the load cell 114 to be abnormally low or high. This current is compared in the load cell to the error comparison current 140, with the normal range of currents shown by the regions 238. With the error comparison current as illustrated by waveform 140, we can expect normal cells to produce a zero error output until the last clock period of the selected cycle, when the comparison current 140 is reduced below the minimum expected current to produce a one pulse on the error outputs ERR. However, an excessive current will result in the error outputs ERR pulsing high for both comparisons, and an insufficient current will result in no pulse at all. These errors could all be logically combined into a single logical signal, but in this case, all four error signals are separately multiplexed into the ICID circuit output stream ID by the output selector 122. This is done by delaying the signal from one of the pair of error outputs ERR by two clock periods before multiplexing it into the output stream, while multiplexing the signal from the other line into the output stream directly. By examining the serial bit stream, the validity of the serial output stream can be determined. This is important when the identification portion of the output stream cannot be validated with a checksum or other validating data pattern. Type Identification ICID 38 may be adapted to provide an output ID that not only uniquely identifies an IC in which it is installed but also includes a "type code" indicating aspects of the IC that it has in common with other ICs sharing the same photomask, such as its type, source of manufacture, etc. Thus an output ID of ICID 38 would include one field having a value that is unique to the IC in which it is installed and another field having a value that is common to all similar ICs. The type code may be set by replacing each of several of the "random identification" cells 62 of array 46 of FIG. 3 with "type identification" cell 242 similar to that illustrated m FIG. 17, or by adding additional type identification cells to the array. Type identification cell 242 of FIG. 17 is generally similar to the random identification cell 62 of FIG. 4 m construction and operation except that the type identification cell has upper and lower MOSFETs 244 and 246 differing substantially m size so that m each type identification cell one MOSFET will always be stronger than the other despite random parametric variations. A "logic 1" type identification cell 242 as illustrated m FIG. 17, where the upper MOSFET 244 is larger than the lower MOSFET 246 will always produce a larger dra current m its upper dram output line than m its lower dram line, and so will always produce a "positive" output voltage VX when selected. Conversely, a "logic 0" type identification cell having a smaller upper MOSFET and a larger lower MOSFET will produce a negative output voltage VX. When a series of logic 1 and logic 0 type identification cells are addressed m appropriate sequence, they produce a predictable sequence of ones and zeros m the output ID that may be used to identify the ICs type. Any error m the type identification sequence will provide an indication of defects m the ICID array. Identity records The sequence m which the array cells are addressed influences the nature and value of the ID the ICID circuit 38 produces. Four kinds of IDs will be described, but many other kinds may be readily imagined and this invention is not limited to those described here. The simplest ID is the binary ID generated by counting linearly through all array addresses m sequence, and saving the result of the comparison as a binary bit. The address count proceeds as 0,1,2, ...,N-1,N and wraps around to 0 again. The serial output bits ID from the measurement circuit directly form the 256 binary bit identity record. This simple sequence may be modified slightly to better accommodate type identification cells. Sequencing from a logic one-type to logic zero-type identification cell will always produce a deterministic "0" bit out of the auto- zero comparator Sequencing from a zero-type to a one-type identification will always produce a deterministic "1". However, sequencing between two zero-type or two one-type cells will produce a non-determmistic "mismatch" transition, useful for individual part identification, but not for type identification. Therefore, arrays with rows of type identification cells may alternately be addressed with a sequence like: 0, M, 0, M+l, 0, M+2 , ... where the type identification cells are M, M+l, and so on. This means that the first part of the bit sequence forming the output ID will have a predictable string of bits representing the type identification. FIG. 18 illustrates a "sorted value" ID, which sorts the ICID cell address m ascending order of measured cell parametric value. The address of the cell having the most negative parametric value becomes table entry zero. The address of the cell having the next most negative parametric value goes into table entry one. At the end of the process, an ICID circuit with N cells will produce a table of N integers, each integer representing an array address. FIG. 18 shows two tables, each listing cell locations and associated parametric values. The first table 254 illustrates cell parametric values that might be found in a simplified eight cell ICID. A simple binary ID for these cell parametric values would be 00110111, the result of comparing the parametric value each cell with the parametric value of the subsequent cell . The second table 256 shows the result of sorting the cells m ascending order of parametric value. The cell parametric values are in sequence, and addressing the array m the sorted order would produce a sequence of ones, if all the values were unique. However, the illustrated array has two cells with the same value, and the result of comparing those two cells will be indeterminate, and the comparator output could be either one or zero. The actual parametric values are not directly visible to a sorting process; however, all that is really needed for a sort is the ability to compare values, and this comparison is performed by the auto-zeroing comparator 120. A conventional sorting algorithm, implemented as hardware on an IC, or as software running on an external tester or comparator, may be used to perform the sorting. The sequence of sorted addresses conveys more information than the simple binary ID. A binary ID for the simplified array illustrated can have 2 to the 8th power or 256 possible values, while the sorted ID can have 8 factorial or 40320 possible values. Both ID records may be extracted from the very same ICID circuit, simply by using different control sequences and different algorithms . The sorted value ID may be used in its entirety, but a shorter subset of "reliable" values may be constructed. When a sequence of these reliable values are presented to the ICID circuit, it will tend to produce a more repeatable series of transitions and comparator outputs. This sequence may be used to query the ICID circuit and receive a deterministic response . Binary ID Analysis Due to noise and drift, the output of a cell, which happens to nearly match the previously selected cell, may randomly resolve into either a one or a zero whenever the two cells are sequentially addressed. This will make some of the bits of an ID non-repeatable, and slightly different every time it is generated. However if the ID is sufficiently long, the remaining invariant bits will still serve to identify the IC that generated it since it would be unlikely that an ID produced by any other IC would have so many bits in common. FIG. 19 shows the rate at which bits change value - the bit error rate - as a function of threshold mismatch drift, for a binary ID. A clean, modern CMOS process will have drifts of less than 10 percent of the standard deviation of voltage threshold mismatch, while the bit error rate is only 25% for drift equal to 100% of the standard deviation of voltage threshold mismatch. The bit error rate will be greater than zero for any amount of drift, but it will stay small for reasonable drift. The fraction of bits changed, or the bit error rate, is called P. The graph of P (262) asymptotically approaches 0.5 as the drift approaches infinity. Two binary IDs can be compared by computing the absolute norm between them. The absolute norm is defined as the count of the number of bits that differ between the two IDs. If two IDs are identical, they have an absolute norm of zero. If every bit is different, that is, one ID is the inverse of the other, the absolute norm is equal to N, the number of bits in the ID. The absolute norm between two different IDs generated from different arrays will have an average of N/2. A histogram of the values will follow a Gaussian curve centered around N/2, with a standard deviation of ON/2. If a 256 bit binary IDs compared to a file containing one trillion different IDs, there is likely to be less than one difference with absolute norm less than 73, and less than one difference with an absolute norm greater than 183, with most differences clustering between 120 and 136, and an average absolute norm of 128. When a binary ID is extracted from an ICID circuit with subsequent drift, perhaps due to random noise, mobile ion contamination, or redistribution of the charges in the transistor channel, the ID may change over time. The bit extraction process is resistant to these changes. If a random drift of 25% (an additional uncorrelated Gaussian with 25% of the magnitude of the original Gaussian) is added to the random values used to produce the binary identity record, the result will be about 7.8% of the bits randomly changing value. The bit error rates are statistically independent for each bit. The average absolute norm, for a given array size and bit error rate, is N'P. For the example with 256 values, 25% drift and P = 0.078, the average absolute norm will be about 20. For a trillion drifting samples, there will be less than one part with an absolute norm greater than 56. FIG. 20 shows the expected probabilities from comparing one binary ID to a database of one trillion 256 bit IDs. A logarithmic vertical scale is used order to magnify extremely tiny probabilities. If the ID has been extracted from a component that has drifted 25% since its original identification, it will nearly match its original ID with an absolute norm of less than 56, with a chance of less than one part m a trillion of exceeding this value. The absolute norm will most likely be around 20, and follow the probability distribution shown as the matching curve 264. When compared to all the other IDs the data base for different ICID circuits, another distribution is formed, following the mismatch curve 266. There is less than one chance m a trillion that the absolute norm for a different ID will be less than 73, and the average absolute norm will be around 128. The false positive and false negative rates will not be mathematically zero, but they will be immeasurably small when the array is sufficiently large, certainly better than fingerprint identification and other legally acceptable forms of identification. The ICID circuit may be practically applied to identify one part out of a database of one million parts. The IDs of one million parts are extracted, along with other identifying information such as testing date, lot number, wafer number, wafer position, process parameters, test speed, and other useful information. This information may be stored m a computer database . Assume at some later time, with the one million parts in use, that one of these parts needs to be identified. An ID is extracted from the identification circuit on the chip. Because of drift, this ID will probably not be identical to the original ID m the data base. However, if it is compared to every ID m the data base, the result will be 999,999 absolute norms that are probably greater than 90, and almost certainly greater than 73. There will also be a single absolute norm that is probably less than 44, and almost certainly less than 53, if the drift is less than 25% We can set a threshold m our test of 64, and easily distinguish the correct ID m the data base. In fact, the drift can be as high as 37% before there is more than one chance m a trillion of exceeding the threshold, and erroneously concluding the selected component is not m the database because of excessive drift . Modern semiconductor processes drift far less than this. If the part is not m the database with an absolute norm of less than 64 , the component has either been badly mistreated, it has not been logged, the identification circuit has failed, or the component is a counterfeit produced by some other manufacturer. All of these possibilities can be distinguished with further investigation, and all are of interest to a semiconductor manufacturer. A 256-cell array was employed m the example ICID illustrated herein. However with a lesser maximum drift, or when fewer chips are to be identified, or when the identification may be less reliable, then fewer array cells may be used. For example, with a 10% maximum drift, and a 1 m 1 million allowable error rate, as few as 64 cells will provide adequate identification. For a 1 m 1 quadrillion error rate (10-15) and a drift of 240%, 4096 cells may be needed. For any finite drift, an acceptable error rate may be achieved with a sufficient number of cells. Cell Array Alternatives The discussion heremabove assumed that array cells were implemented in an N-Well CMOS process of 0.5 micron or smaller lmewidth, but cell transistors may be either N channel or P channel MOSFETs, and longer channel processes may be used m some circumstances. If the CMOS process is an N-Well process, P channel MOSFETs should be chosen so that the entire array can be placed in an N-Well isolated from the substrate and the electronic noise m it . A P-Well process would use N channel MOSFETs for the same reason. While the preferred embodiment of the invention employs MOSFET pairs with common source and gate connections, with the output signals derived from the drains, it is also possible to connect transistors with common gate and dram, thereby deriving a voltage difference signal from the source. While the array cells of the preferred embodiment make use of the voltage threshold mismatch of a pair of MOSFETs, mismatches of length, width, oxide thickness, or any other parametric variables may be used m alternative embodiments of the invention. Pairs of devices are used for the preferred embodiment, but single devices may be used m applications where the ambient conditions permit it. Resistor mismatches or VBE mismatches could be used with a purely bipolar process. Identification from random parametric variation can be applied to any other semiconductor process producing devices with random but repeatable parametric mismatches. Although the device array was illustrated as a square, equally useful ICID circuits may be constructed as a rectangular array of any shape or size. To improve statistical usefulness, it is helpful to include a set of "dummy cells" at the edges of the array which are not addressed when an ID is generated. However the such dummy cells along the array edges may be omitted. Row select transistors may be added to isolate the array output lines AOH and AOL from unselected drains. With proper addressing, this allows merging of dram output lines between rows of cells, allowing for a more compact array. Operational Alternatives The ICID circuit may be addressed, for example, by a counter, rather than a shift register, generating addresses internally rather than from an input line. The external clock may also be replaced with a free-running oscillator. The enable input may be replaced with a power-on reset cell . Such an alternative design would have a single output line, and be suitable for applications where interconnect count is more important than power or synchronization. When an ID is computed, it may be stored on the chip itself as a sequence of values m an on-chip Random Access Memory (RAM) which may be non-nonvolatile. The RAM may be part of a microprocessor on-board cache, and available to software executed by that microprocessor. This arrangement allows fast access to the ID during use, and may be required to generate repeatable IDs m very noisy environments. It does, however, require additional chip area for a RAM.

Claims: Claims I claim: 1. An apparatus (ICID) installed on an integrated circuit (IC) for generating an identification number (ID) identifying the IC in which it is installed, the apparatus comprising : a plurality of identification cells formed within said IC, each having an output that is a substantial function of random parametric variations in said IC; and measurement means for monitoring the output of said plurality of identification cells and for generating said ID in response thereto, wherein said ID is also a substantial function of random parametric variations in said cells. 2. The apparatus in accordance with claim 1 wherein said measurement means establishes a value of said ID in accordance with the output of each of said plurality of identification cells. 3. The apparatus in accordance with claim 2 wherein each of said identification cells comprises at least one transistor, and wherein the output of each cell is a function of an operating characteristic of that transistor that is in turn a function of said random parametric variations in said IC. 4. The apparatus in accordance with claim 2 wherein each of said identification cells comprises two transistors having a difference in operating characteristics resulting from said random parametric variations in said IC, and wherein said output of said cell is a function of said difference in operating characteristics. 5. The apparatus in accordance with claim 4 wherein said transistors are metal oxide semiconductor field effect transistors (MOSFETs) . 6. The apparatus m accordance with claim 2 further comprising a plurality of type cells formed withm said IC, each type cell having an output that is substantially independent of said random parametric variations, wherein said measurement means also monitors the output of each of said plurality of type cells and also generates said ID m response thereto. 7. The apparatus m accordance with claim 6 wherein said ID generated by said measurement means includes a first field reflecting a pattern of monitored output s of said plurality of identification cells and a second field reflecting a pattern of monitored outputs of said plurality of type cells. 8. The apparatus m accordance with claim 1 wherein said measurement means comprises: means for sequentially comparing magnitudes of monitored outputs of said identification cells and for generating a sequence of bits, each bit of said sequence indicating a result of a comparison of outputs of said identification cells; and means for generating said ID m response to said sequence of bits. 9. The apparatus m accordance with claim 1 wherein the output of each of said cells comprises two output signals that are functions of said random parametric variations, and wherein said output monitored by said measurement means comprises a difference between said two output signals. 10. The apparatus m accordance with claim 9 wherein said measurement means comprises: means for performing comparisons of said differences between output signals of successive ones of said identification cells and for generating a sequence of bits, each bit of said sequence indicating a result of a separate one of said comparisons; and means for generating said ID in response to said sequence of bits. 11. A method for providing an integrated circuit (IC) with an identification number (ID), the method comprising the steps of : forming a plurality of identification cells within said IC, each having an output that is a substantial function of random parametric variations in said IC; and generating said ID in response to the monitored output of each cell, wherein said ID is also a substantial function of random parametric variations in said IC. 12. The method in accordance with claim 11 wherein a value of said ID is established in response to the output of each of said plurality of identification cells. 13. The method in accordance with claim 12 wherein each of said identification cells comprises at least one transistor, and wherein said output is a function of an operating characteristic of that transistor that is in turn a function of said random parametric variations in said IC. 14. The method in accordance with claim 12 wherein each of said identification cells comprises two transistors having a difference in operating characteristics resulting from said random variations in said IC, and wherein said output is a function of said difference between said operating characteristics of said transistors. 15. The method in accordance with claim 14 wherein said transistors are metal oxide semiconductor field effect transistors (MOSFETs) . 16. The method in accordance with claim 12 further comprising the step of forming a plurality of type cells within said IC, each type cell having an output that is substantially independent of said random parametric variations, and also generating said ID m response thereto. 17. The method accordance with claim 16 wherein the generated ID includes a first field reflecting a pattern of monitored outputs of said plurality of identification cells and a second field reflecting a pattern of monitored outputs of said plurality of type cells. 18. The method accordance with claim 11 wherein the step of generating said ID m response to the monitored outputs comprises the substeps of : performing comparisons of monitored outputs of pairs of said identification cells; generating a sequence of bits, each bit of said sequence indicating a result of a separate one of said comparisons; and generating said ID m response to said sequence of bits. 19. The method m accordance with claim 11 wherein each of said cells produces two output signals that are functions of said random parametric variations, and wherein said output of each cell comprises a difference between said two output signals . 20. The method accordance with claim 19 wherein the step of generating said ID m response to the monitored outputs comprises the substeps of: performing comparisons of monitored outputs of pairs of said identification cells; generating a sequence of bits, each bit of said sequence indicating a result of a separate one of said comparisons; and generating said ID m response to said sequence of bits.

Inventors: LOFSTROM KEITH, LOFSTROM, KEITH
Applicants: ICID LLC, ICID, LLC
Application year: 2000
Main classification: G06F17
IPC codes: H01L23