A SYSTEM AND METHOD FOR IMPROVING MULTI-BIT ERROR PROTECTION IN COMPUTER MEMORY SYSTEMS

Abstract: A system and method for storing error correction check words in computer memory modules. Check bits stored in physically adjacent locations within a dynamic random access memory (DRAM) chip are assigned to different check words. By assigning check bits to check words in this manner, multi-bit soft errors resulting from errors in two or more check bits stored in physically adjacent memory locations will appear as single-bit errors to an error correction subsystem. Similarly, the likelihood of multi-bit errors occurring in the same check word may be reduced.

Description: TITLE: A SYSTEM AND METHOD FOR IMPROVING MULTI-BIT ERROR PROTECTION IN COMPUTER MEMORY SYSTEMS BACKGROUND OF THE INVENTION 1 Field of the Invention This invention relates to memory within computer systems, and more specifically, to error correction systems for detecting and correcting errors that may be present in data stored or transmitted to and from system memory 2. Descπption of the Relevant Art For data transmissions occurring within a given computer system, there is always a finite chance that the transmitted data is in error. This is true when the source of the transmitted data is a dynamic random access memory (DRAM) The majority of errors that occur in a DRAM chip are soft errors, which are correctable. Hard errors may occur as well, and some hard errors may be correctable, but their occurrence is typically less frequent than the occurrence of soft errors. Two primary sources of soft errors are alpha particles and cosmic rays. Since a DRAM stores a given bit via a charge, an alpha particle or cosmic ray can alter this charge, thereby changing the contents of a given memory cell. As the amount of main memory in computer systems has contmued to increase, the frequency of soft errors has increased correspondingly. Soft errors, if left uncorrected, can have adverse effects on system performance, corrupting data and even causing system crashes. One measure of the possibility of such failure is referred to as Mean Time between Failures (MTBF). Uncorrected soft errors can reduce the MTBF of a given computer system. In order to counter the presence of errors, many computers employ error correction circuitry. Such circuitry is used to implement error correction codes (ECCs), which are used to detect and correct errors within a computer system. There are many different types of ECCs. Some of the more commonly used codes are referred to as Hamming codes, although many others have been developed In some error correction systems, a bit pattern, such as one representing an ASCII character, is recoded with redundant bits, more commonly referred to a check bits. Groups of check bits are referred to as check words, and each data block stored in a DRAM may be protected by at least one check word. Paπty is another element of many error correction codes. Even paπty is defined as adding a check bit so that the total number of logic ones m a given bit pattern is even, while odd paπty requires adding a check bit so that the total number of logic ones is odd. In a system where even parity is in use, the receipt of a word, including check bits, containing an odd number of logic ones automatically indicates the presence of an error in the data Receipt of a word containmg an even number of logic ones in an odd parity system will also indicate the presence of an error. Many error correction schemes can typically correct only one error withm a given data word Some error correction schemes allow the detection of two errors, but these schemes are usually unable to unambiguously correct both of them. As previously mentioned, many soft errors in a DRAM are caused by cosmic rays or Alpha particles. Alpha particles are localized phenomena, and in many cases, can alter the contents of multiple bits in the general area m which they occur. Similarly, cosmic rays, while not a localized phenomena, can nevertheless bombard a semiconductor memory with protons and neutrons, randomly altermg the stored bits. Since a number of error correction schemes assign physically adjacent check bits within the DRAM to a given check word, there is an increased possibility of uncorrectable multi-bit soft errors occurring within a given check word. Furthermore, data bits protected by a given check word may be altered in the same manner. The relationship between DRAM cell architecture and DRAM input output (I/O) architecture may have an affect on the manner m which given check bits are assigned to check words. For example, in some DRAM chips, the cell layout will result m cells connected to data lme D15 being physically adjacent to cells connected data line DO, although these two bits are not logically adjacent. In other DRAM chips DO may be adjacent to Dl, Dl is adjacent to D2, and so on Check bits on these data lmes are often assigned to the same check word. Figure 1 illustrates one row of an example memory array withm a DRAM, wherem check bits stored m adjacent locations are assigned to the same check words. When certain phenomena occur, such as alpha particle radiation, multiple adjacent bits stored in a memory array can be altered, causmg multi-bit errors. Multi-bit errors are generally more difficult to detect and correct than single-bit errors. A method to reduce the possibility of multi-bit soft errors from degrading system operation would be desirable It would be further desirable to make multi-bit soft eπors appear as single-bit soft errors, thereby making the errors easier to correct. SUMMARY OF THE INVENTION The problems outlined above may m large part solved by a system and method for error correction for improving multi-bit error protection in computer memory systems, in accordance with the present invention. In one embodiment, check bits formmg a check word are stored in physically non-adjacent storage cells with respect to every other check bit of the given check word. Since there is a likelihood that soft and/or hard errors will cause physically adjacent cells to provide erroneous data, associating check bits with check words m this manner results in multi-bit errors appearmg as single-bit errors to an error correction subsystem. Similarly, the likelihood of multi-bit errors occurring in the same check word may be reduced In one embodiment, a memory module includes a printed circuit board upon which a plurality of DRAM chips are mounted Some of these DRAM chips are configured to store data words, while others store check bits associated with given data words Each data word is protected by a number of check bits forming a check word These check bits are generated accordmg to a predetermined error correction scheme, such as a Hamming code. A group of check bits is referred to a check word The check bits are stored in DRAM chips m such a manner that each check bit of a given check word is stored m a physically non-adjacent memory cell with respect to every other check bit in the given check word. Typically, each check bit from a given DRAM chip will be assigned to a different check word During a memory access, a data word is accessed, and check words associated with the accessed data word are received by an error correction subsystem. The error correction subsystem will then use the check words to check for the presence of an error, according to the predetermined error correction scheme. Smce each of the check bits from a given DRAM chip is assigned to a different check word, multi-bit errors from a given DRAM chip will appear as a plurality of single-bit errors, which are generally easier to detect and correct. Furthermore, smce check bits from a given DRAM are assigned to different check words, the likelihood of multiple errors occurring m the same check word may be reduced. Thus, m vanous embodiments, the system and method for improving multi-bit error protection in computer memory systems may advantageously reduce the possibility of multi-bit errors occurring m the same check word. Furthermore, since check bits stored m physically adjacent locations within a DRAM are assigned to different check words, multi-bit errors caused by errors m check bits stored m physically adjacent locations will be appear as smgle-bit errors to the error correction subsystem Smce single-bit errors are generally easier to detect and correct, system reliability and data mtegπty may be advantageously enhanced BRIEF DESCRIPTION OF THE DRAWINGS A more thorough understandmg of the present invention can be obtained by reading and following the detailed descπption of the preferred embodiment in conjunction with the following drawings, in which Figure 1 (prior art) is a drawing illustrating one row of a memory aπay withm a dynamic random access memory (DRAM) chip m which physically adjacent check bits are assigned to the same check word, Figure 2 is a block diagram of one embodiment of a computer system, including an error correction subsystem, Figure 3 is a drawmg of a memory module as used m the computer system of Figure 2, wherein the memory module is configured for storage of check bits and data bits; Figure 4 is a block diagram illustrating the relationship of check bits to check words for DRAM chips with a data path of 16 bits; Figure 5 is a block diagram wherein four check bits from a given memory device are in error, illustrating a multi-bit error presented to an error correction subsystem as a group of single-bit errors; Figure 6 is a drawmg of one row of a memory array withm a DRAM, illustrating the manner in which physically adjacent check bits correspond to different check words; Figure 7 is a drawmg of a portion of a memory array in which the correlation of check words to check bits that are stored in physically adjacent cells, both horizontally and vertically, is illustrated. While the invention is susceptible to vanous modifications and alternative forms, specific embodiments thereof are shown by way of example in the drawings and will herein be described m detail. It should be understood, however, that the drawings and detailed description thereto are not intended to limit the invention to the particular form disclosed, but on the contrary, the mtention is to cover all modifications, equivalents, and alternatives falling withm the spiπt and scope of the present invention as defined by the appended claims DETAILED DESCRIPTION OF THE INVENTION Referring now to Figure 2, a block diagram of a computer system 100 with an error correction subsystem 105 is shown. In addition to error correction subsystem 105, the computer system includes a CPU 101, a memory controller 102, a CPU bus 103, a memory bus 104, and a plurality of memory modules 1000. Error correction subsystem 105 is contained withm memory controller 102, and is configured to detect and coπect errors during data transfers on the memory bus, including those transfers of data to and from memory modules 1000. The use of check bits and check words by the error correction subsystem will be explamed m further detail below. Error correction subsystem 105 may use one of many different error correction schemes, such as one employmg Hamming codes. Figure 3 is a drawmg of a memory module used in the computer system of Figure 2. Memory module 1000 mcludes a pπnted circuit board upon which dynamic random access memory (DRAM) chips 1001-1 through 1001-36 are mounted. Each of these DRAM chips has a data width of 16 bits In this particular embodiment, four of these DRAM chips, 1001-1 through 1001-4, are used exclusively to store check bits. The remamder of DRAM chips 1001-5 through 1001-36 are used to store data bits. Memory module 1000 also includes an edge connector 1005, with a plurality of electπcal contact pads 1015. A plurality of signal lmes 1020 couples the electrical contact pads 1015 to the DRAM chips 1001 Data signals are conveyed along signal lmes 1020 between the DRAM chips 1001 and electrical contact pads 1015. Data pin DO of each DRAM chip 1001 is shown coupled to electπcal contact pads 1015 by signal lines 1020, with the respective position of the bit m the data word (l e. DQO, DQ 16, etc.) shown The most significant bit of the data, DQ511 , is coupled to pin D 15 of a DRAM chip 1001-5. In this embodiment, 16 check bits are used to protect each data block of 128 bits, with each check word associated with one data block only. As previously stated, DRAM chips 1001-1 through 1001-4 are used exclusively to store check bits in this embodiment. Each of these DRAM chips stores four check bits of each check word. Each check word is 16 bits, and protects a data block of 128 bits. These check bits are accessed through a plurality of pms designated CBWX[y:z] For example, CBW1[3:0] shown in the drawing represents four pins of a DRAM chip through which check bits 0 through 3 of check word #1 are accessed. Similarly, CBW2[7.4] represents those pms through which check bits 4 through 7 of check word #2 are accessed. Each of these pms is connected to a respective signal line. Representative signal lines are shown in the drawing as CBW1 through CBW4 In general, these signal lines are routed on the pπnted circuit board in such a manner that physically adjacent memory cells within each DRAM chip store check bits corresponding to different check words. Turning now to Figure 4, a drawing illustrating the relationship of check bits stored in a given DRAM chip to individual check words is shown. A DRAM chip 1001-1 stores four check bits for each of four different check words 2000, which are used by the error correction subsystem 105 of Figure 2. Each of the four check bits corresponding to a given check word is stored in DRAM chip 1001-1 at a physically non-adjacent memory cell with respect to the other three check bits corresponding to the given check word. Similarly, DRAM chips 1001-2 through 1001-4 each store four check bits for each check word 2000, and each check bit is stored in a physically non-adjacent memory cell with respect to every other check bit of the given check word. Dunng memory access operations, the error correction subsystem 105 of Figure 2 will access each of the four check words 2000 in parallel. Figure 5 is a drawing that illustrates the manner in which multi-bit errors from a single DRAM chip will appear as smgle bit errors to an error correction subsystem. In the drawing, DRAM chips 1001-1 through 1001-4 each store four check bits of each check word 2000 In this case, a multi-bit error is present in DRAM 1001-1, as four check bits are in error. Each check bit in error corresponds with a different check word 2000. No other eπors are present in any check bit from the other DRAM chips 1001-2 through 1001-4. Smce each check word 2000 contains only one bit in error, the error correction subsystem detects and corrects the four single-bit errors, even though a multi-bit error is present in DRAM chip 1001-1 Referring now to Figure 6, a drawing of one row of a DRAM memory array illustrating the manner m which physically adjacent check bits are associated with different check words is shown. In this embodiment, memory array row 1050R is configured to store 16 check bits. Each check bit is associated with a check word 2000. Check bit 0 m row 1050R is associated with check word #1, while the next physically adjacent bit, check bit 1, is associated with check word #2. Similarly, check bit #3 is associated with check word #3 and check bit 4 is associated with check word #4. This pattern will repeat beginning with check bit 5, which will be associated with check word #1. The final check bit in row 105 OR will be associated with check word #4 Figure 7 is a drawmg of a memory array withm a DRAM, and further illustrates the manner in which physically adjacent check bits are associated with different check words. In this embodiment, memory array 1050 includes a plurality of rows 1050R and columns 1050C. At the mtersections of rows 1050R and columns 1050C are memory cells 1051. Each cell in this embodiment can store one check bit, and each check bit is assigned to a check word 2000. The check bits are stored such that no two check bits stored m cells 1051 that are physically adjacent, either vertically, horizontally, or diagonally, are associated with the same check word 2000. For example, the check bit stored in row 5, column 3 of memory array 1050 is associated with check word #1, while the bit directly beneath it, in row 4 column 3, is associated with check word #2. A check bit that is stored m a horizontally adjacent cell, row 5, column 4, is associated with check word #3, while a check bit stored in a diagonally adjacent cell, row 4, column 4, is associated with check word #4. This method of associating check bits to check words is repeated for all check bits stored within the given memory array. While the present invention has been described with reference to particular embodiments, it will be understood that the embodiments are illustrative and that the mvention scope is not so limited. Any vaπations, modifications, additions, and improvements to the embodiments descπbed are possible. These vaπations, modifications, additions, and improvements may fall withm the scope of the inventions as detailed withm the following claims

Claims: WHAT IS CLAIMED IS: 1 A computer system compπsmg a central processmg unit (CPU), a memory controller coupled to said CPU and a memory bus, said memory controller mcluding an error coπection subsystem, said error correction subsystem configured to generate a plurality of check words corresponding to a plurality of data blocks, a memory module coupled to said memory bus mcludmg a plurality of memory chips for stormg said plurality of check words and said plurality of data blocks, wherein each check bit formmg a given check word is stored at a physically non-adjacent memory cell of said plurality of memory chips with respect to every other check bit of said given check word 2 The computer system as recited in claim 1, wherein at least one of said plurality of memory chips is configured to receive and store multiple check bits of said given check word 3 The computer system as recited in claim 2, wherein a first subset of said plurality of memory chips is configured to receive and store a given data block corresponding to said given check word 4 The computer system as recited m claim 3, wherein a second subset of said plurality of memory chips including at least one of said plurality of memory chips is configured to receive and store said given check word, and, wherein a first memory chip of said second subset is configured to receive and store a first set of check bits of said given check word 5 The computer system as recited in claim 4, wherein said first memory chip includes an array of memory cells, and, wherein each bit of said first set of check bits of said given check word is stored at a physically non-adjacent cell within said first memory chip with respect to every other bit of said first set of check bits 6 The computer system as recited in claim 2, wherein said error coπection subsystem is configured to detect an eπor in data transferred from said memory subsystem, and, wherein said error correction subsystem is configured to, upon detection of an error in said data, to coπect said eπor 7 The computer system as recited in claim 2, wherein said memory chips are Dynamic Random Access Memory (DRAM) chips 8 A method for stormg check words m a memory module, said method compπsmg generating a plurality of check words coπespondmg to a plurality of data blocks, said check words, said check words including a plurality of check bits, stormg said plurality of check words and said plurality of data blocks m said memory module, wherem each check bit formmg a given check word is stored at a physically non-adjacent memory cell of said plurality of memory chips with respect to every other check bit of said given check word The method as recited in claim 8, wherem said check words are stored m said memory chips, and, wherein said check bits of a given check word are stored in more than one of said memory chips The method as recited in claim 8, wherein said memory chips are dynamic random access memory (DRAM) chips A memory subsystem comprising at least one memory module mcludmg a plurality of memory chips, a memory controller mcluding an eπor coπection subsystem, said eπor coπection subsystem configured to generate a plurality of check words coπesponding to a plurality of data blocks, wherein each check bit forming a given check word is stored at a physically non-adjacent memory cell of said plurality of memory chips with respect to every other check bit of said given check word The memory subsystem as recited in claim 11, wherem said memory chips are dynamic random access memory (DRAM) chips The memory subsystem as recited in claim 13, wherem each of said DRAM chips includes a memory aπay having cells, each of said cells configured to store one bit of information The memory subsystem as recited in claim 13, wherem each of said check bits is stored in a cell of said memory aπay The memory subsystem as recited in claim 11, wherein each of said memory modules includes a printed circuit board (PCB), wherein a plurality of memory chips are mounted upon said PCB A memory module for use m a system having an eπor coπection subsystem, said eπor coπection subsystem configured to generate a plurality of check words coπespondmg to a plurality of data blocks, said memory module comprising a pnnted circuit board, a plurality of memory chips mounted upon said pπnted circuit board for stormg said plurality of check words and said plurality of data blocks, wherem each check bit formmg a given check word is stored at a physically non-adjacent memory cell of said plurality of memory chips with respect to every other check bit of said given check word 7. The memory module as recited m claim 16, wherem said memory chips are Dynamic Random Access Memory (DRAM) chips. 8 The memory module as recited m claim 16, wherem said pnnted circuit board mcludes a plurality of signal lines. 9 The memory module as recited m claim 17, wherein said signal lmes are routed on said prmted circuit board such that said check bits stored in said memory cells that are physically adjacent are assigned to different of said check words. 0 The memory module as recited m claim 16, wherein a first plurality of said memory chips is configured to store data bits, and a second plurality of said memory chips is configured to store check bits.

Inventors: CARRILLO JOHN, FANG CLEMENT, KO HAN Y, SINGHAL ASHOK, WONG TAYUNG, CARRILLO, JOHN, FANG, CLEMENT, KO, HAN, Y., SINGHAL, ASHOK, WONG, TAYUNG
Applicants: SUN MICROSYSTEMS INC, SUN MICROSYSTEMS, INC.
Application year: 2000
Main classification: G06F11
IPC codes: G06F11, G06F12, G11C29