RESOURCE CONTROL IN A COMPUTER SYSTEM

Abstract: A bridge for a computer system comprising at least a first processing set and a second processing set each connected to the bridge via an I/O bus. A resource control mechanism in the bridge comprises: an interface for exchanging signals with one or more resource slots of a device bus that is capable of being connected to the bridge, each of the resource slots being capable of communicating with a system resource; and a register associated with each system resource, the register having switchable indicia that indicate an operating state of the associated system resource, the control mechanism being operable in use to direct signals to and/or from respective system resources of the computer system.

Description: TITLE: RESOURCE CONTROL IN A COMPUTER SYSTEM BACKGROUND OF THE INVENTION This invention relates to a resource control in a computer system. The invention finds application, for example, to a multi-processor system in which first and second processing sets (each of which may compπse one or more processors) communicate with an I/O device bus The invention finds particular but not exclusive application to fault tolerant computer systems where two or more processing sets need to communicate with an I/O device bus in lockstep In such a fault tolerant computer system, an arm is not only to be able to identify faults, but also to provide a structure which is able to provide a high degree of system availability and system resilience to internal or external disturbances. In order to provide high levels of system resilience to internal disturbances, such as an I/O device failure for example, it would be desirable for such systems automatically to control access to and from any device that might appear to be causing problems Automatic access control provides significant technical challenges in that the system has not only to monitor the devices in question to detect errors, but also has to provide an environment where the system as a whole can continue to operate despite a failure of one or more of the system components Accordingly, an aim of the present invention is to address these technical problems Aspects of the invention also provide significant advantages when employed in non- fault tolerant multiprocessor computing systems where the processing sets operate independently. In this situation, each independent processing set can be allocated system devices which are mounted on a common bus This arrangement enables the architecture of a multi-processor computing system to be simplified, and is made possible by the provision of a bπdge which arbitrates between processing sets for usage of the system devices whilst also providing information to the processing sets regarding which of the devices, if any, are available for use SUMMARY OF THE INVENTION Particular and preferred aspects of the invention are set out in the accompanymg independent and dependent claims Combinations of features from the dependent claims may be combined with features of the independent claims as appropnate and not merely as explicitly set out in the claims In accordance with one aspect of the invention, there is provided a bridge for a computer system The bπdge comprises at least a first processing set and a second processing set each connected to the bridge via an I/O bus A resource control mechanism in the bridge compπses an mterface for exchanging signals with one or more resource slots of a device bus that is capable of being connected to the bπdge, each of the resource slots bemg capable of communicating with a system resource; and a register associated with each system resource, the register havmg switchable indicia that indicate an operating state of the associated system resource, the control mechanism bemg operable m use to direct signals to and/or from respective system resources of the computer system. At least one of the resources may be an I/O device The register may comprise memory for storing the indicia The register may comprise a 4-bit memory unit The computer system may comprise two processmg sets, each of the processing sets comprising one or more processors. At least some of the switchable indicia may be used to mdicate whether the associated resource has been allocated to one of the processmg sets The at least some of the switchable indicia may additionally indicate which of the processmg sets the resource associated with that register has been allocated to The register may comprise a 4-bit memory unit and the computer system may compπse a first processmg set and a second processmg set, a second bit and a third bit of the unit bemg switchable to indicate whether the associated resource is owned by the first processmg set, the second processmg set or not owned by either the first processmg set or the second processmg set At least one of the switchable indicia may mdicate whether or not the associated resource has been allowed access to one of the processmg sets At least one of the switchable indicia may be selectively operable to generate indeterminate data when a read of the resource associated with that register is attempted A further aspect of the mvention provides a bridge for a computer system The computer system compπses at least two processing sets and a routmg matrix A resource control mechanism m the bridge compπses a register having a plurality of switchable indicia that each mdicate an operating state of an associated resource of the computer system The routmg matrix is capable of routmg instructions and/or data to or from a resource identified by at least one of the identifymg indicia as bemg owned by one of the processing sets A further aspect of the invention provides a bπdge for a computer system The computer system compπses a first processmg set and a second processing set A resource control mechanism in the bridge compπses a four bit register wherem two of the four bits are switchable to and/or from a first state indicating that a resource associated with the register is not allocated to either the first processmg set or the second processing set, a second state mdicatmg that the resource associated with the register is allocated to the first processmg set, and a third state indicating that the resource associated with the register is allocated to the second processmg set A first bit of a remaining two bits of the four bit register may be switchable to and/or from a first state mdicatmg that the associated resource is allowed access to one of the first and second processmg sets, and a second state mdicatmg that the associated resource is not allowed access to either of the first and second processing sets, the first state only bemg initiated when the two of the four bits of the register mdicate that the associated resource is owned by either of the first and second processing sets A second bit of the remammg two bits of the four bit register may be switchable to and/or from a first state mdicatmg that writes to the associated resource are allowed, and a second state mdicatmg that wπtes to the associated resource are to be ignored and that indeterminate date will be generated m response to any attempted writes to that associated resource A further aspect of the invention provides a method of controlling resources of a computer system The method compπses the steps of establishing a register m a bridge of the computer system, the register having a plurality of indicia switchable to indicate operatmg states of a resource associated with a slot of a bus connected to the bπdge, and controlling the resource m accordance with the operatmg states indicated by the indicia of the register The register may be implemented in random access memory The register may comprise a four bit register The method may further comprise the step of updatmg the register to reflect changes m the operatmg state of the resource A further aspect of the invention provides a method of routing signals from a first processing set or a second processing set to at least one resource provided on a resource bus selectively connectable to the first or second processing set. The method comprises the steps of; propagating signals from one of the first and second processing sets, the signals being destined for a resource of the computer system; interrogating a register to determine whether the one of the first and second processing sets is allowed access to the resource; and routing the signals to the resource if the register indicates that access to the resource for the one of the first and second processing sets is allowed. A further aspect of the invention provides a computer system comprising: a plurality of processing sets each having one or more processors and each being connected to a processor bus; a plurality of devices each associated with a slot of an I O device bus; and a bridge connected to the plurality of processor busses and to the I/O device bus, the bridge comprising a device control mechanism having an interface for exchanging signals with one or more of the slots and associated devices; and a register associated with each device, the register having switchable indicia that indicate an operating state of the associated device, the control mechanism being operable in use to direct signals to and/or from respective system resources of the computer system. A further aspect of the invention provides a bridge for a multi-processor computer system. The bridge comprises: a resource control mechanism having an interface for exchanging signals with one or more resource slots, each of the resource slots being capable of communicating with a system resource; and a register associated with each system resource, the register having switchable indicia that indicate an operating state of the associated system resource, the control mechanism being operable in use to direct signals to and/or from respective system resources of the computer system. BRIEF DESCRIPTION OF THE DRAWINGS Exemplary embodiments of the present invention will be described hereinafter, by way of example only, with reference to the accompanying drawings in which like reference signs relate to like elements and in which: Figure 1 is a schematic overview of a fault tolerant computer system incorporating an embodiment of the invention; Figure 2 is a schematic overview of a specific implementation of a system based on that of Figure 1 ; Figure 3 is a schematic representation of one implementation of a processing set; Figure 4 is a schematic representation of another example of a processing set; Figure 5 is a schematic representation of a further processing set; Figure 6 is a schematic block diagram of an embodiment of a bridge for the system of Figure 1 ; Figure 7 is a schematic block diagram of storage for the bridge of Figure 6; Figure 8 is a schematic block diagram of control logic of the bridge of Figure 6; Figure 9 is a schematic representation of a routing matrix of the bridge of Figure 6; Figure 10 is an example implementation of the bridge of Figure 6; Figure 11 is a state diagram illustrating operational states of the bridge of Figure 6; Figure 12 is a flow diagram illustrating stages in the operation of the bridge of Figure 6; Figure 13 is a detail of a stage of operation from Figure 12; Figure 14 illustrates the posting of I/O cycles in the system of Figure 1; Figure 15 illustrates the data stored in a posted write buffer; Figure 16 is a schematic representation of a slot response register; Figure 17 illustrates a dissimilar data write stage; Figure 18 illustrates a modification to Figure 17; Figure 19 illustrates a dissimilar data read stage; Figure 20 illustrates an alternative dissimilar data read stage; Figure 21 is a flow diagram summarising the operation of a dissimilar data write mechanism; Figure 22 is a schematic block diagram explaining arbitration within the system of Figure 1 ; Figure 23 is a state diagram illustrating the operation of a device bus arbiter; Figure 24 is a state diagram illustrating the operation of a bridge arbiter; Figure 25 is a timing diagram for PCI signals; Figure 26 is a schematic diagram illustrating the operation of the bridge of Figure 6 for direct memory access; Figure 27 is a flow diagram illustrating a direct memory access method in the bridge of Figure 6; and Figure 28 is a flow diagram of a re-integration process including the monitoring of a dirty RAM. DESCRIPTION OF THE PREFERRED EMBODIMENTS Figure 1 is a schematic overview of a fault tolerant computing system 10 comprising a plurality of CPUsets (processing sets) 14 and 16 and a bridge 12. As shown in Figure 1, there are two processing sets 14 and 16, although in other embodiments there may be three or more processing sets. The bridge 12 forms an interface between the processing sets and I/O devices such as devices 28, 29, 30, 31 and 32. In this document, the term "processing set" is used to denote a group of one or more processors, possibly including memory, which output and receive common outputs and inputs. It should be noted that the alternative term mentioned above, "CPUset", could be used instead, and that these terms could be used interchangeably throughout this document. Also, it should be noted that the term "bridge" is used to denote any device, apparatus or arrangement suitable for interconnecting two or more buses of the same or different types. The first processing set 14 is connected to the bridge 12 via a first processmg set I/O bus (PA bus) 24, in the present instance a Peripheral Component Interconnect (PCI) bus. The second processing set 16 is connected to the bridge 12 via a second processing set I/O bus (PB bus) 26 of the same type as the PA bus 24 (i.e. here a PCI bus). The I O devices are connected to the bridge 12 via a device I/O bus (D bus) 22, in the present instance also a PCI bus. Although, in the particular example described, the buses 22, 24 and 26 are all PCI buses, this is merely by way of example, and in other embodiments other bus protocols may be used and the D-bus 22 may have a different protocol from that of the PA bus and the PB bus (P buses) 24 and 26. The processing sets 14 and 16 and the bridge 12 are operable in synchronism under the control of a common clock 20, which is connected thereto by clock signal lines 21. Some of the devices including an Ethernet (E-NET) interface 28 and a Small Computer System Interface (SCSI) interface 29 are permanently connected to the device bus 22, but other I/O devices such as I/O devices 30, 31 and 32 can be hot insertable into individual switched slots 33, 34 and 35. Dynamic field effect transistor (FET) switchmg can be provided for the slots 33, 34 and 35 to enable hot lnsertability of the devices such as devices 30, 31 and 32 The provision of the FETs enables an mcrease in the length of the D bus 22 as only those devices which are active are switched on, reducing the effective total bus length. It will be appreciated that the number of I/O devices which may be connected to the D bus 22, and the number of slots provided for them, can be adjusted accordmg to a particular implementation in accordance with specific design requirements. Figure 2 is a schematic overview of a particular implementation of a fault tolerant computer employing a bridge structure of the type illustrated in Figure 1. In Figure 2, the fault tolerant computer system includes a plurality (here four) of bridges 12 on first and second I/O motherboards (MB 40 and MB 42) order to mcrease the number of I O devices which may be connected and also to improve reliability and redundancy Thus, m the embodiment shown in Figure 2, two processmg sets 14 and 16 are each provided on a respective processing set board 44 and 46, with the processing set boards 44 and 46 'bridging' the I O motherboards MB 40 and MB 42. A first, master clock source 20A is mounted on the first motherboard 40 and a second, slave clock source 20B is mounted on the second motherboard 42 Clock signals are supplied to the processing set boards 44 and 46 via respective connections (not shown in Figure 2) First and second bridges 12 1 and 12.2 are mounted on the first I O motherboard 40 The first bridge 12.1 is connected to the processmg sets 14 and 16 by P buses 24 1 and 26 1, respectively. Similarly, the second bπdge 12.2 is connected to the processmg sets 14 and 16 by P buses 24.2 and 26.2, respectively The bridge 12.1 is connected to an I/O databus (D bus) 22.1 and the bridge 12 2 is connected to an I/O databus (D bus) 22.2 Third and fourth bridges 12.3 and 124 are mounted on the second I/O motherboard 42 The bridge 12.3 is connected to the processmg sets 14 and 16 by P buses 24 3 and 26.3, respectively Similarly, the bπdge 4 is connected to the processing sets 14 and 16 by P buses 24 4 and 26 4, respectively The bridge 12 3 is connected to an I/O databus (D bus) 22.3 and the bπdge 12 4 is connected to an I O databus (D bus) 22 4 It can be seen that the arrangement shown m Figure 2 can enable a large number of I/O devices to be connected to the two processing sets 14 and 16 via the D buses 22 1, 22.2, 22.3 and 22.4 for either increasing the range of I/O devices available, or providing a higher degree of redundancy, or both. Figure 3 is a schematic overview of one possible configuration of a processmg set, such as the processmg set 14 of Figure 1 The processmg set 16 could have the same configuration. In Figure 3, a plurality of processors (here four) 52 are connected by one or more buses 54 to a processmg set bus controller 50 As shown in Figure 3, one or more processmg set output buses 24 are connected to the processmg set bus controller 50, each processmg set output bus 24 bemg connected to a respective bπdge 12. For example, in the arrangement of Figure 1, only one processmg set I/O bus (P bus) 24 would be provided, whereas m the arrangement of Figure 2, four such processmg set I/O buses (P buses) 24 would be provided In the processing set 14 shown m Figure 3, individual processors operate using the common memory 56, and receive mputs and provide outputs on the common P bus(es) 24 Figure 4 is an alternative configuration of a processmg set, such as the processmg set 14 of Figure 1 Here a plurality of processor/memory groups 61 are connected to a common internal bus 64. Each processor/memory group 61 mcludes one or more processors 62 and associated memory 66 connected to a internal group bus 63 An mterface 65 connects the internal group bus 63 to the common internal bus 64 Accordmgly, m the arrangement shown m Figure 4, individual processmg groups, with each of the processors 62 and associated memory 66 are connected via a common internal bus 64 to a processmg set bus controller 60 The mterfaces 65 enable a processor 62 of one processmg group to operate not only on the data m its local memory 66, but also m the memory of another processing group 61 within the processmg set 14 The processing set bus controller 60 provides a common mterface between the common internal bus 64 and the processmg set I/O bus(es) (P bus(es)) 24 connected to the bπdge(s) 12 It should be noted that although only two processmg groups 61 are shown m Figure 4, it will be appreciated that such a structure is not limited to this number of processmg groups Figure 5 illustrates an alternative configuration of a processing set, such as the processmg set 14 of Figure 1 Here a simple processing set mcludes a smgle processor 72 and associated memory 76 connected via a common bus 74 to a processmg set bus controller 70 The processmg set bus controller 70 provides an interface between the internal bus 74 and the processing set I/O bus(es) (P bus(es)) 24 for connection to the bπdge(s) 12 Accordingly, it will be appreciated from Figures 3, 4 and 5 that the processmg set may have many different forms and that the particular choice of a particular processing set structure can be made on the basis of the processing requirement of a particular application and the degree of redundancy required In the following description, it is assumed that the processmg sets 14 and 16 referred to have a structure as shown m Figure 3, although it will be appreciated that another form of processmg set could be provided The bπdge(s) 12 are operable in a number of operating modes These modes of operation will be described m more detail later However, to assist in a general understandmg of the structure of the bridge, the two operating modes will be briefly summarized here In a first, combmed mode, a bπdge 12 is operable to route addresses and data between the processmg sets 14 and 16 (via the PA and PB buses 24 and 26, respectively) and the devices (via the D bus 22) In this combined mode, I O cycles generated by the processing sets 14 and 16 are compared to ensure that both processmg sets are operatmg coπectly Comparison failures force the bridge 12 mto an error limiting mode (EState) m which device I/O is prevented and diagnostic information is collected In the second, split mode, the bridge 12 routes and arbitrates addresses and data from one of the processmg sets 14 and 16 onto the D bus 22 and/or onto the other one of the processing sets 16 and 14, respectively In this mode of operation, the processing sets 14 and 16 are not synchronized and no I/O compaπsons are made DMA operations are also permitted m both modes As mentioned above, the different modes of operation, mcludmg the combined and split modes, will be described m more detail later However, there now follows a descπption of the basic structure of an example of the bπdge 12 Figure 6 is a schematic functional overview of the bridge 12 of Figure 1 First and second processing set I/O bus interfaces, PA bus mterface 84 and PB bus interface 86, are connected to the PA and PB buses 24 and 26, respectively A device I/O bus mterface, D bus interface 82, is connected to the D bus 22 It should be noted that the PA, PB and D bus mterfaces need not be configured as separate elements but could be incorporated m other elements of the bπdge Accordmgly, within the context of this document, where a references is made to a bus mterface, this does not require the presence of a specific separate component, but rather the capability of the bridge to connect to the bus concerned, for example by means of physical or logical bridge connections for the lmes of the buses concerned Routmg (hereinafter termed a routmg matπx) 80 is connected via a first internal path 94 to the PA bus mterface 84 and via a second internal path 96 to the PB bus mterface 86 The routmg matπx 80 is further connected via a third internal path 92 to the D bus mterface 82 The routmg matπx 80 is thereby able to provide I/O bus transaction routmg m both directions between the PA and PB bus mterfaces 84 and 86 It is also able to provide routmg m both directions between one or both of the PA and PB bus mterfaces and the D bus mterface 82 The routing matrix 80 is connected via a further internal path 100 to storage control logic 90 The storage control logic 90 controls access to bridge registers 110 and to a random access memory (SRAM) 126 The routmg matrix 80 is therefore also operable to provide routing m both directions between the PA, PB and D bus mterfaces 84, 86 and 82 and the storage control logic 90 The routmg matπx 80 is controlled by bridge control logic 88 over control paths 98 and 99 The bπdge control logic 88 is responsive to control signals, data and addresses on internal paths 93, 95 and 97, and also to clock signals on the clock lme(s) 21 In the embodiment of the invention, each of the P buses (PA bus 24 and PB bus 26) operates under a PCI protocol The processmg set bus controllers 50 (see Figure 3) also operate under the PCI protocol Accordmgly, the PA and PB bus interfaces 84 and 86 each provide all the functionality required for a compatible mterface providing both master and slave operation for data transferred to and from the D bus 22 or internal memones and registers of the bridge m the storage subsystem 90 The bus mterfaces 84 and 86 can provide diagnostic information to internal bπdge status registers in the storage subsystem 90 on transition of the bπdge to an error state (EState) or on detection of an I/O error The device bus interface 82 performs all the functionality required for a PCI compliant master and slave mterface for transferring data to and from one of the PA and PB buses 84 and 86 The D bus 82 is operable during direct memory access (DMA) transfers to provide diagnostic information to internal status registers m the storage subsystem 90 of the bπdge on transition to an EState or on detection of an I/O error Figure 7 illustrates m more detail the bπdge registers 110 and the SRAM 124 The storage control logic 110 is connected via a path (e g a bus) 112 to a number of register components 114, 116, 118, 120 The storage control logic is also connected via a path (e g a bus) 128 to the SRAM 126 m which a posted write buffer component 122 and a dirty RAM component 124 are mapped Although a particular configuration of the components 114, 116, 118, 120, 122 and 124 is shown m Figure 7, these components may be configured m other ways, with other components defined as regions of a common memory (e g a random access memory such as the SRAM 126, with the path 112/128 bemg formed by the internal addressing of the regions of memory) As shown m Figure 7, the posted wπte buffer 122 and the duty RAM 124 are mapped to different regions of the SRAM memory 126, whereas the registers 114, 116, 118 and 120 are configured as separate from the SRAM memory Control and status registers (CSRs) 114 form internal registers which allow the control of various operatmg modes of the bridge, allow the capture of diagnostic information for an EState and for I/O eπors, and control processmg set access to PCI slots and devices connected to the D bus 22 These registers are set by signals from the routmg matrix 80 Dissimilar data registers (DDRs) 116 provide locations for containing dissimilar data for different processing sets to enable non-deterministic data events to be handled These registers are set by signals from the PA and PB buses Bridge decode logic enables a common wπte to disable a data comparator and allow writes to two DDRs 116, one for each processmg set 14 and 16 A selected one of the DDRs can then be read m-sync by the processing sets 14 and 16 The DDRs thus provide a mechanism enabling a location to be reflected from one processmg set (14/16) to another (16/14) Slot response registers (SRRs) 118 determine ownership of device slots on the D bus 22 and to allow DMA to be routed to the appropπate processmg set(s) These registers are linked to address decode logic Disconnect registers 120 are used for the storage of data phases of an I/O cycle which is aborted while data is in the bridge on the way to another bus The disconnect registers 120 receive all data queued m the bπdge when a target device disconnects a transaction, or as the EState is detected These registers are connected to the routmg matπx 80 The routmg matπx can queue up to three data words and byte enables Provided the initial addresses are voted as bemg equal, address target controllers deπve addresses which mcrement as data is exchanged between the bπdge and the destmation (or target) Where a wπter (for example a processor I/O write, or a DVMA (D bus to P bus access)) is wnhng data to a target, this data can be caught m the bπdge when an error occurs Accordmgly, this data is stored in the disconnect registers 120 when an error occurs These disconnect registers can then be accessed on recovery from an EState to recover the data associated with the wπte or read cycle which was m progress when the EState was mitiated Although shown separately, the DDRs 116, the SRRs 118 and the disconnect registers may form an integral part of the CSRs 114 EState and eπor CSRs 114 provided for the capture of a failing cycle on the P buses 24 and 26, with an indication of the failing datum Folio wmg a move to an EState, all of the writes mitiated to the P buses are logged m the posted write buffer 122 These may be other wπtes that have been posted m the processmg set bus controllers 50, or which may be mitiated by software before an EState mterrupt causes the processors to stop carrying out writes to the P buses 24 and 26 A dirty RAM 124 is used to mdicate which pages of the mam memory 56 of the processing sets 14 and 16 have been modified by direct memory access (DMA) transactions from one or more devices on the D bus 22 Each page (e g each 8K page) is marked by a single bit in the dirty RAM 124 which is set when a DMA write occurs and can be cleared by a read and clear cycle mitiated on the dirty RAM 124 by a processor 52 of a processmg set 14 and 16 The duty RAM 124 and the posted write buffer 118 may both be mapped mto the memory 124 m the bπdge 12 This memory space can be accessed durmg normal read and wπte cycles for testmg purposes Figure 8 is a schematic functional overview of the bridge control logic 88 shown m Figure 6 All of the devices connected to the D bus 22 are addressed geographically Accordmgly, the bndge carnes out decoding necessary to enable the isolating FETs for each slot before an access to those slots is initiated The address decoding performed by the address decode logic 136 and 138 essentially permits four basic access types- - an out-of-sync access (1 e not m the combmed mode) by one processmg set (e g processmg set 14 of Figure 1) to the other processmg set (e.g processmg set 16 of Figure 1), m which case the access is routed from the PA bus mterface 84 to the PB bus mterface 86, - an access by one of the processmg sets 14 and 16 m the split mode, or both processmg sets 14 and 16 m the combmed mode to an I/O device on the D bus 22, m which case the access is routed via the D bus mterface 82, - a DMA access by a device on the D bus 22 to one or both of the processmg sets 14 and 16, which would be directed to both processmg sets 14 and 16 m the combmed mode, or to the relevant processing set 14 or 16 if out-of-sync, and if m a split mode to a processmg set 14 or 16 which owns a slot in which the device is located, and - a PCI configuration access to devices m I/O slots As mentioned above, geographic addressmg is employed Thus, for example, slot 0 on motherboard A has the same address when referred to by processing set 14 or by processmg set 16 Geographic addressmg is used m combination with the PCI slot FET switching Durmg a configuration access mentioned above, separate device select signals are provided for devices which are not FET isolated A smgle device select signal can be provided for the switched PCI slots as the FET signals can be used to enable a correct card Separate FET switch lmes are provided to each slot for separately switching the FETs for the slots. The SRRs 118, which could be incorporated m the CSR registers 114, are associated with the address decode functions The SRRs 118 serve in a number of different roles which will be described m more detail later However, some of the roles are summarized here In a combined mode, each slot may be disabled so that writes are simply acknowledged without any transaction occurring on the device bus 22, whereby the data is lost Reads will return meaningless data, once again without causing a transaction on the device board In the split mode, each slot can be m one of three states The states are - Not owned, - Owned by processmg set A 14, - Owned by processmg set B 16 A slot that is not owned by a processmg set 14 or 16 makmg an access (this mcludes not owned or unowned slots) cannot be accessed Accordmgly, such an access is aborted When a processmg set 14 or 16 is powered off, all slots owned by it move to the un-owned state A processmg set 14 or 16 can only claim an un-owned slot, it cannot wrest ownership away from another processmg set This can only be done by powering off the other processmg set, or by getting the other processmg set to relinquish ownership The ownership bits are assessable and settable while in the combmed mode, but have no effect until a split state is entered This allows the configuration of a split system to be determined while still in the combmed mode Each PCI device is allocated an area of the processmg set address map The top bits of the address are determined by the PCI slot Where a device carπes out DMA, the bπdge is able to check that the device is using the coπect address because a D bus arbiter mforms the bridge which device is usmg the bus at a particular time If a device access is a processing set address which is not valid for it, then the device access will be ignored It should be noted that an address presented by a device will be a virtual address which would be translated by an I O memory management unit m the processmg set bus controller 50 to an actual memory address The addresses output by the address decoders are passed via the initiator and target controllers 138 and 140 to the routing matrix 80 via the lmes 98 under control of a bπdge controller 132 and an arbiter 134 An arbiter 134 is operable in various different modes to arbitrate for use of the bπdge on a first-come- first-served basis usmg conventional PCI bus signals on the P and D buses In a combined mode, the arbiter 134 is operable to arbitrate between the ln-sync processing sets 14 and 16 and any initiators on the device bus 22 for use of the bridge 12 Possible scenarios are - processmg set access to the device bus 22, - processmg set access to internal registers m the bridge 12, - Device access to the processmg set memory 56 In split mode, both processing sets 14 and 16 must arbitrate the use of the bπdge and thus access to the device bus 22 and internal bridge registers (e g CSR registers 114) The bridge 12 must also contend with initiators on the device bus 22 for use of that device bus 22 Each slot on the device bus has an arbitration enable bit associated with it These arbitration enable bits are cleared after reset and must be set to allow a slot to request a bus When a device on the device bus 22 is suspected of providmg an I/O eπor, the arbitration enable bit for that device is automatically reset by the bridge A PCI bus interface in the processing set bus controller(s) 50 expects to be the master bus controller for the P bus concerned, that is it contams the PCI bus arbiter for the PA or PB bus to which it is connected The bπdge 12 cannot directly control access to the PA and PB buses 24 and 26 The bπdge 12 competes for access to the PA or PB bus with the processmg set on the bus concerned under the control of the bus controller 50 on the bus concerned Also shown m Figure 8 is a comparator 130 and a bridge controller 132 The comparator 130 is operable to compare I O cycles from the processmg sets 14 and 16 to determine any out-of-sync events On determining an out-of-sync event, the comparator 130 is operable to cause the bridge controller 132 to activate an EState for analysis of the out-of-sync event and possible recovery therefrom Figure 9 is a schematic functional overview of the routing matπx 80 The routmg matπx 80 comprises a multiplexer 143 which is responsive to initiator control signals 98 from the initiator controller 138 of Figure 8 to select one of the PA bus path 94 , PB bus path 96, D bus path 92 or internal bus path 100 as the cuπent input to the routmg matπx Separate output buffers 144, 145, 146 and 147 are provided for output to each of the paths 94, 96, 92 and 100, with those buffers bemg selectively enabled by signals 99 from the target controller 140 of Figure 8 Between the multiplexer and the buffers 144-147 signals are held m a buffer 149 In the present embodiment three cycles of data for an I/O cycle will be held in the pipeline represented by the multiplexer 143, the buffer 149 and the buffers 144 In Figures 6 to 9 a functional description of elements of the bπdge has been given Figure 10 is a schematic representation of a physical configuration of the bπdge m which the bπdge control logic 88, the storage control logic 90 and the bπdge registers 110 are implemented m a first field programmable gate array (FPGA) 89, the routmg matrix 80 is implemented m further FPGAs 80 1 and 80 2 and the SRAM 126 is implemented as one or more separate SRAMs addressed by a address control lmes 127 The bus mterfaces 82, 84 and 86 shown in Figure 6 are not separate elements, but are mtegrated m the FPGAs 80 1, 80 2 and 89 Two FPGAs 80 1 and 80 2 are used for the upper 32 bits 32-63 of a 64 bit PCI bus and the lower 32 bits 0-31 of the 64 bit PCI bus It will be appreciated that a single FPGA could be employed for the routmg matrix 80 where the necessary logic can be accommodated withm the device Indeed, where a FPGA of sufficient capacity is available, the bπdge control logic, storage control logic and the bridge registers could be incorporated in the same FPGA as the routmg matrix Indeed many other configurations may be envisaged, and indeed technology other than FPGAs, for example one or more Application Specific Integrated Circuits (ASICs) may be employed As shown in Figure 10, the FPGAs 89, 80 1 and 80 2 and the SRAM 126 are connected via internal bus paths 85 and path control lines 87 Figure 11 is a transition diagram illustrating m more detail the vaπous opeiatmg modes of the bridge The bridge operation can be divided into three basic modes, namely an eπor state (EState) mode 150, a split state mode 156 and a combmed state mode 158 The EState mode 150 can be further divided into 2 states After initial resetting on powering up the bπdge, or following an out-of sync event, the bridge is in this initial EState 152 In this state, all writes are stored m the posted write buffer 120 and reads from the internal bridge registers (e g , the CSR registers 116) are allowed, and all other reads are treated as eπors (l e they are aborted) In this state, the individual processing sets 14 and 16 perform evaluations for determining a restart time Each processing set 14 and 16 will determine its own restart timer timing The tuner setting depends on a "blame" factor for the transition to the EState A processmg set which determmes that it is likely to have caused the error sets a long time for the timer A processmg set which thinks it unlikely to have caused the eπor sets a short time for the timer The first processmg set 14 and 16 which times out, becomes a primary processing set Accordingly, when this is determined, the bπdge moves (153) to the primary EState 154 When either processmg set 14/16 has become the primary processmg set, the bridge is then operatmg in the primary EState 154 This state allows the primary processmg set to wπte to bridge registers (specifically the SRRs 118) Other wπtes are no longer stored m the posted wnte buffer, but are simply lost Device bus reads are still aborted m the primary EState 154 Once the EState condition is removed, the bπdge then moves (155) to the split state 156 In the split state 156, access to the device bus 22 is controlled by the SRR registers 118 while access to the bπdge storage is simply arbitrated The primary status of the processmg sets 14 and 16 is ignored Transition to a combmed operation is achieved by means of a sync reset (157) After issue of the sync_reset operation, the bndge is then operable m the combmed state 158, whereby all read and wπte accesses on the D bus 22 and the PA and PB buses 24 and 26 are allowed All such accesses on the PA and PB buses 24 and 26 are compared m the comparator 130 Detection of a mismatch between any read and write cycles (with an exception of specific dissimilar data I/O cycles) cause a transition 151 to the EState 150 The various states descπbed are controlled by the bπdge controller 132 The role of the comparator 130 is to monitor and compare I O operations on the PA and PB buses m the combmed state 151 and, m response to a mismatched signal, to notify the bridge controller 132, whereby the bridge controller 132 causes the transition 152 to the error state 150 The I O operations can include all I/O operations initiated by the processmg sets, as well as DMA transfers m respect of DMA mitiated by a device on the device bus Table 1 below summarizes the various access operations which are allowed m each of the operational states TABLE 1 D Bus - Read D Bus-Write E State Master Abort Stored in Post Wπte Buffer Primary EState Master Abort Lost Split Controlled by SRR bits Controlled by SRR bits and arbitrated and arbitrated Combined Allowed and compared Allowed and compared As descπbed above, after an initial reset, the system is m the initial EState 152 In this state, neither processmg sets 14 or 16 can access the D bus 22 or the P bus 26 or 24 of the other processmg set 16 or 14 The internal bπdge registers 116 of the bπdge are accessible, but are read only A system running in the combmed mode 158 transitions to the EState 150 where there is a comparison failure detected m this bπdge, or alternatively a comparison failure is detected m another bridge m a multi- bπdge system as shown, for example, m Figure 2 Also, transitions to an EState 150 can occur in other situations, for example in the case of a software controlled event forming part of a self test operation On movmg to the EState 150, an mterrupt is signaled to all or a subset of the processors of the processing sets via an mterrupt line 95 Following this, all I/O cycles generated on a P bus 24 or 26 result in reads bemg returned with an exception and wπtes bemg recorded in the posted write buffer The operation of the comparator 130 will now be described m more detail The comparator is connected to paths 94, 95, 96 and 97 for comparmg address, data and selected control signals from the PA and PB bus mterfaces 84 and 86 A failed compaπson of ln-sync accesses to device I/O bus 22 devices causes a move from the combined state 158 to the EState 150 For processmg set I/O read cycles, the address, command, address parity, byte enables and parity eπor parameters are compared If the comparison fails durmg the address phase, the bridge asserts a retry to the processing set bus controllers 50, which prevents data leavmg the I/O bus controllers 50 No activity occurs m this case on the device I/O bus 22 On the processor(s) retrying, no eπor is returned If the compaπson fails during a data phase (only control signals and byte enables are checked), the bπdge signals a target-abort to the processmg set bus controllers 50 An eπor is returned to the processors In the case of processmg set I/O bus write cycles, the address, command, paπty, byte enables and data parameters are compared If the compaπson fails durmg the address phase, the bridge asserts a retry to the processmg set bus controllers 50, which results m the processing set bus controllers 50 retrying the cycle agam The posted write buffer 122 is then active No activity occurs on the device I/O bus 22 If the comparison fails durmg the data phase of a write operation, no data is passed to the D bus 22 The failing data and any other transfer attributes from both processmg sets 14 and 16 are stored in the disconnect registers 122, and any subsequent posted write cycles are recorded in the posted write buffer 118 In the case of direct virtual memory access (D VMA) reads, the data control and parity are checked for each datum If the data does not match, the bridge 12 terminates the transfer on the P bus In the case of DVMA writes, control and parity eπor signals are checked for coπectness Other signals in addition to those specifically mentioned above can be compared to give an indication of divergence of the processing sets Examples of these are bus grants and vaπous specific signals durmg processmg set transfers and durmg DMA transfers Eπors fall roughly into two types, those which are made visible to the software by the processing set bus controller 50 and those which are not made visible by the processmg set bus controller 50 and hence need to be made visible by an interrupt from the bridge 12 Accordingly, the bridge is operable to capture eπors reported in connection with processmg set read and write cycles, and DMA reads and writes Clock control for the bridge is performed by the bridge controller 132 m response to the clock signals from the clock line 21 Individual control lines from the controller 132 to the vaπous elements of the bridge are not shown m Figures 6 to 10 Figure 12 is a flow diagram illustrating a possible sequence of operating stages where lockstep eπors are detected during a combmed mode of operation Stage SI represents the combmed mode of operation where lockstep eπor checking is performed by the comparator 130 shown in Figure 8 In Stage S2, a lockstep eπor is assumed to have been detected by the comparator 130 In Stage S3, the cuπent state is saved m the CSR registers 114 and posted wπtes are saved m the posted write buffer 122 and/or m the disconnect registers 120 Figure 13 illustrates Stage S3 in more detail Accordmgly, m Stage S31, the bridge controller 132 detects whether the lockstep eπor notified by the comparator 130 has occurred durmg a data phase in which it is possible to pass data to the device bus 22 In this case, m Stage S32, the bus cycle is terminated Then, m Stage S33 the data phases are stored m the disconnect registers 120 and control then passes to Stage S35 where an evaluation is made as to whether a further I/O cycle needs to be stored Alternatively, if at Stage S31 , it is determined that the lockstep eπor did not occur during a data phase, the address and data phases for any posted write I/O cycles are stored in the posted wπte buffer 122 At Stage S34, if there are any further posted wπte I/O operations pending, these are also stored m the posted wπte buffer 122 Stage S3 is performed at the initiation of the initial eπor state 152 shown m Figure 11 In this state, the first and second processmg sets arbitrate for access to the bridge Accordmgly, m Stage S31-S35, the posted write address and data phases for each of the processmg sets 14 and 16 are stored m separate portions of the posted write buffer 122, and/or in the single set of disconnect registers as described above Figure 14 illustrates the source of the posted wπte I/O cycles which need to be stored m the posted write buffer 122 Durmg normal operation of the processmg sets 14 and 16, output buffers 162 m the mdividual processors contam I/O cycles which have been posted for transfer via the processing set bus controllers 50 to the bπdge 12 and eventually to the device bus 22 Similarly, buffers 160 m the processmg set controllers 50 also contam posted I/O cycles for transfer over the buses 24 and 26 to the bridge 12 and eventually to the device bus 22 Accordmgly, it can be seen that when an eπor state occurs, I/O wπte cycles may already have been posted by the processors 52, either in their own buffers 162, or already transfeπed to the buffers 160 of the processing set bus controllers 50 It is the I/O wπte cycles in the buffers 162 and 160 which gradually propagate through and need to be stored m the posted write buffer 122 As shown m Figure 15, a write cycle 164 posted to the posted write buffer 122 can comprise an address field 165 mcludmg an address and an address type, and between one and 16 data fields 166 including a byte enable field and the data itself The data is written mto the posted wπte buffer 122 in the EState unless the initiating processmg set has been designated as a primary CPU set At that time, non-primary writes m an EState still go to the posted wπte buffer even after one of the CPU sets has become a primary processing set An address pomter m the CSR registers 114 pomts to the next available posted write buffer address, and also provides an overflow bit which is set when the bπdge attempts to write past of the top of the posted write buffer for any one of the processing sets 14 and 16 Indeed, in the present implementation, only the first 16 K of data is recorded m each buffer Attempts to write beyond the top of the posted write buffer are ignored The value of the posted write buffer pomter can be cleared at reset, or by software usmg a write under the control of a primary processmg set Returning to Figure 12, after savmg the status and posted wπtes, at Stage S4 the individual processing sets mdependently seek to evaluate the eπor state and to determine whether one of the processmg sets is faulty This determination is made by the mdividual processors in an eπor state m which they individually read status from the control state and EState registers 114 Durmg this eπor mode, the arbiter 134 arbitrates for access to the bπdge 12 In Stage S5, one of the processing sets 14 and 16 establishes itself as the primary processmg set This is determined by each of the processmg sets identifymg a time factor based on the estimated degree of responsibility for the eπor, whereby the first processmg set to time out becomes the primary processmg set In Stage S5, the status is recovered for that processmg set and is copied to the other processmg set The primary processing is able to access the posted write buffer 122 and the disconnect registers 120 In Stage S6, the bridge is operable m a split mode If it is possible to re-establish an equivalent status for the first and second processing sets, then a reset is issued at Stage S7 to put the processmg sets m the combmed mode at Stage SI However, it may not be possible to re-establish an equivalent state until a faulty processing set is replaced Accordmgly the system will stay m the Split mode of Stage S6 m order to continued operation based on a smgle processmg set After replacmg the faulty processing set the system could then establish an equivalent state and move via Stage S7 to Stage SI As described above, the comparator 130 is operable m the combmed mode to compare the I/O operations output by the first and second processing sets 14 and 16 This is fine as long as all of the I/O operations of the first and second processmg sets 14 and 16 are fully synchronized and deterministic Any deviation from this will be interpreted by the comparator 130 as a loss of lockstep This is m principle coπect as even a minor deviation from identical outputs, if not trapped by the comparator 130, could lead to the processing sets diverging further from each other as the mdividual processmg sets act on the deviatmg outputs However, a strict application of this puts significant constraints on the design of the mdividual processing sets An example of this is that it would not be possible to have independent tune of day clocks m the mdividual processing sets operatmg under their own clocks This is because it is impossible to obtam two crystals which are 100% identical in operation Even small differences m the phase of the clocks could be critical as to whether the same sample is taken at any one time, for example either side of a clock transition for the respective processing sets Accordingly, a solution to this problem employs the dissimilar data registers (DDR) 116 mentioned earlier The solution is to write data from the processmg sets into respective DDRs m the bridge while disabling the comparison of the data phases of the wπte operations and then to read a selected one of the DDRs back to each processmg set, whereby each of the processmg sets is able to act on the same data Figure 17 is a schematic representation of details of the bridge of Figures 6 to 10 It will be noted that details of the bridge not shown m Figure 6 to 8 are shown in Figure 17, whereas other details of the bridge shown m Figures 6 to 8 are not shown m Figure 17, for reasons of claπty The DDRs 116 are provided m the bridge registers 110 of Figure 7, but could be provided elsewhere in the bridge m other embodiments One DDR 116 is provided for each processing set In the example of the multi-processor system of Figure 1 where two processmg sets 14 and 16 are provided, two DDRs 116A and 116B are provided, one for each of the first and second processmg sets 14 and 16, respectively Figure 17 represents a dissimilar data write stage The addressmg logic 136 is shown schematically to comprise two decoder sections, one decoder section 136A for the first processmg set and one decoder section 136B for the second processmg set 16 Durmg an address phase of a dissimilar data I/O write operation each of the processing sets 14 and 16 outputs the same predetermined address DDR-W which is separately interpreted by the respective first and second decodmg sections 136A and 136B as addressmg the respective first and second respective DDRs 116A and 116B As the same address is output by the first and second processing sets 14 and 16, this is not interpreted by the comparator 130 as a lockstep eπor The decodmg section 136A, or the decodmg section 136B, or both are aπanged to further output a disable signal 137 m response to the predetermined wnte address supplied by the first and second processing sets 14 and 16 This disable signal is supplied to the comparator 130 and is operative durmg the data phase of the write operation to disable the comparator As a result, the data output by the first processmg set can be stored in the first DDR 116A and the data output by the second processmg set can be stored m the second DDR 116B without the comparator bemg operative to detect a difference, even if the data from the first and second processmg sets is different The first decodmg section is operable to cause the routmg matrix to store the data from the first processmg set 14 m the first DDR 116A and the second decodmg section is operable to cause the routmg matrix to store the data from the second processmg set 16 m the second DDR 116B At the end of the data phase the comparator 130 is once agam enabled to detect any differences between I O address and/or data phases as indicative of a lockstep eπor Following the writing of the dissimilar data to the first and second DDRs 116A and 116B, the processmg sets are then operable to read the data from a selected one of the DDRs 116A/116B Figure 18 illustrates an alternative aπangement where the disable signal 137 is negated and is used to control a gate 131 at the output of the comparator 130 When the disable signal is active the output of the comparator is disabled, whereas when the disable signal is mactive the output of the comparator is enabled Figure 19 illustrates the readmg of the first DDR 116A in a subsequent dissimilar data read stage As illustrated in Figure 19, each of the processmg sets 14 and 16 outputs the same predetermmed address DDR-RA which is separately mterpreted by the respective first and second decodmg sections 136A and 136B as addressing the same DDR, namely the first DDR 116A As a result, the content of the first DDR 116A is read by both of the processing sets 14 and 16, thereby enablmg those processmg sets to receive the same data This enables the two processmg sets 14 and 16 to achieve deterministic behavior, even if the source of the data written mto the DDRs 116 by the processmg sets 14 and 16 was not deterministic As an alternative, the processing sets could each read the data from the second DDR 116B Figure 20 illustrates the reading of the second DDR 116B m a dissimilar data read stage following the dissimilar data wπte stage of Figure 15 As illustrated in Figure 20, each of the processmg sets 14 and 16 outputs the same predetermmed address DDR-RB which is separately mterpreted by the respective first and second decodmg sections 136A and 136B as addressmg the same DDR, namely the second DDR 116B As a result, the content of the second DDR 116B is read by both of the processmg sets 14 and 16, thereby enabling those processing sets to receive the same data As with the dissimilar data read stage of Figure 16, this enables the two processing sets 14 and 16 to achieve deterministic behavior, even if the source of the data wπtten mto the DDRs 116 by the processing sets 14 and 16 was not deterministic The selection of which of the first and second DDRs 116A and 116B to be read can be determined in any appropriate manner by the software operatmg on the processmg modules This could be done on the basis of a simple selection of one or the other DDRs, or on a statistical basis or randomly or in any other manner as long as the same choice of DDR is made by both or all of the processmg sets Figure 21 is a flow diagram summarizing the various stages of operation of the DDR mechanism described above In stage S10, a DDR write address DDR-W is received and decoded by the address decoders sections 136A and 136B durmg the address phase of the DDR write operation In stage SI 1, the comparator 130 is disabled In stage S12, the data received from the processing sets 14 and 16 durmg the data phase of the DDR write operation is stored in the first and second DDRs 116A and 116B, respectively, as selected by the first and second decode sections 136A and 136B, respectively In stage SI 3, a DDR read address is received from the first and second processmg sets and is decoded by the decode sections 136A and 136B, respectively If the received address DDR-RA is for the first DDR 116A, then m stage S 14 the content of that DDR 116A is read by both of the processmg sets 14 and 16 Alternatively, 116A if the received address DDR-RB is for the second DDR 116B, then m stage S15 the content of that DDR 116B is read by both of the processing sets 14 and 16 Figure 22 is a schematic representation of the arbitration performed on the respective buses 22, 24 and 26, and the arbitration for the bridge itself Each of the processmg set bus controllers 50 m the respective processing sets 14 and 16 mcludes a conventional PCI master bus arbiter 180 for providmg arbitration to the respective buses 24 and 26 Each of the master arbiters 180 is responsive to request signals from the associated processmg set bus controller 50 and the bπdge 12 on respective request (REQ) lmes 181 and 182 The master arbiters 180 allocate access to the bus on a first-come-first-served basis, issuing a grant (GNT) signal to the winning party on an appropπate grants line 183 or 184 A conventional PCI bus arbiter 185 provides arbitration on the D bus 22 The D bus arbiter 185 can be configured as part of the D bus interface 82 of Figure 6 or could be separate therefrom As with the P bus master arbiters 180, the D bus arbiter is responsive to request signals from the contendmg devices, including the bridge and the devices 30, 31, etc connected to the device bus 22 Respective request lmes 186, 187, 188, etc for each of the entities competing for access to the D bus 22 are provided for the request signals (REQ) The D bus arbiter 185 allocates access to the D bus on a first-come-first-served basis, issumg a grant (GNT) signal to the winning entity via respective grant lines 189, 190, 192, etc Figure 23 is a state diagram summansmg the operation of the D bus arbiter 185 In a particular embodiment up to six request signals may be produced by respective D bus devices and one by the bridge itself On a transition into the GRANT state, these are sorted by a priority encoder and a request signal (REQ#) with the highest priority is registered as the winner and gets a grant (GNT#) signal Each winner which is selected modifies the priorities m a priority encoder so that given the same REQ# signals on the next move to grant A different device has the highest priority, hence each device has a "fair" chance of accessmg DEVs The bridge REQ# has a higher weighting than D bus devices and will, under very busy conditions, get the bus for every second device If a device requestmg the bus fails to perform a transaction withm 16 cycles it may lose GNT# via the BACKOFF state BACKOFF is required as, under PCI rules, a device may access the bus one cycle after GNT# is removed Devices may only be granted access to D bus if the bridge is not m the not m the EState A new GNT# is produced at the tunes when the bus is idle In the GRANT and BUSY states, the FETs are enabled and an accessmg device is known and forwarded to the D bus address decode logic for checkmg against a DMA address provided by the device Turning now to the bridge arbiter 134, this allows access to the bπdge for the first device which asserts the PCI FRAME# signal indicating an address phase Figure 24 is a state diagram summansmg the operation of the bndge arbiter 134 As with the D bus arbiter, a pπoπty encoder can be provided to resolve access attempts which collide In this case "a collision" the loser/losers are retried which forces them to give up the bus Under PCI rules retried devices must try repeatedly to access the bπdge and this can be expected to happen To prevent devices which are very quick with their retry attempt from hoggmg the bπdge, retried mterfaces are remembered and assigned a higher pπoπty These remembered retnes are pπoπtised m the same way as address phases However as a precaution this mechanism is timed out so as not to get stuck waiting for a faulty or dead device The algorithm employed prevents a device which hasn't yet been retried, but which would be a higher priority retry than a device cuπently waitmg for, from bemg retπed at the first attempt In combined operations a PA or PB bus mput selects which P bus mterface will win a bridge access Both are informed they won Allowed selection enables latent fault checkmg during normal operation EState prevents the D bus from winning The bridge arbiter 134 is responsive to standard PCI signals provided on standard PCI control lines 22, 24 and 25 to control access to the bndge 12 Figure 25 illustrates signals associated with an I/O operation cycle on the PCI bus A PCI frame signal (FRAME#) is initially asserted At the same time, address (A) signals will be available on the DATA BUS and the appropriate command (write/read) signals (C) will be available on the command bus (CMD BUS) Shortly after the frame signal being asserted low, the initiator ready signal (IRDY#) will also be asserted low When the device responds, a device selected signal (DEVSEL#) will be asserted low When a target ready signal is asserted low (TRDY#), data transfer (D) can occur on the data bus The bridge is operable to allocate access to the bridge resources and thereby to negotiate allocation of a target bus in response to the FRAME# being asserted low for the initiator bus concerned Accordmgly, the bridge arbiter 134 is operable to allocate access to the bridge resources and/or to a target bus on a first-come- first-served basis m response to the FRAME# being asserted low As well as the simple first-come-first-served basis, the arbiters may be additionally provided with a mechanism for loggmg the arbitration requests, and can imply a conflict resolution based on the request and allocation history where two requests are received at an identical time Alternatively, a simple priority can be allocated to the vaπous requesters, whereby, m the case of identically timed requests, a particular requester always wins the allocation process Each of the slots on the device bus 22 has a slot response register (SRR) 118, as well as other devices connected to the bus, such as a SCSI mterface Each of the SRRs 118 contains bits defining the ownership of the slots, or the devices connected to the slots on the dnect memory access bus In this embodiment, and for reasons to be elaborated below, each SRR 118 comprises a four bit register However, it will be appreciated that a larger register will be required to determine ownership between more than two processmg sets For example, if three processing sets are provided, then a five bit register will be required for each slot Figure 16 illustrates schematically one such four bit register 600 As shown m Figure 16, a first bit 602 is identified as SRR[0], a second bit 604 is identified as SRR[1], a third bit 606 is identified as SRR[2] and a fourth bit 608 is identified as SRR[3] Bit SRR[0] is a bit which is set when writes for valid transactions are to be suppressed Bit SRR[1] is set when the device slot is owned by the first processmg set 14 This defines the access route between the first processmg set 14 and the device slot When this bit is set, the first processing set 14 can always be master of a device slot 22, while the ability for the device slot to be master depends on whether bit SRR[3] is set Bit SRR[2] is set when the device slot is owned by the second processmg set 16. This defines the access route between the second processmg set 16 and the device slot When this bit is set, the second processmg set 16 can always be master of the device slot or bus 22, while the ability for the device slot to be master depends on whether bit SRR[3] is set. Bit SRR[3] is an arbitration bit which gives the device slot the ability to become master of the device bus 22, but only if it is owned by one of the processmg sets 14 and 16, that is if one of the SRR [1] and SRR[2] When the fake bit (SRR[0]) of an SRR 118 is set, writes to the device for that slot are ignored and do not appear on the device bus 22 Reads return indeterminate data without causmg a transaction on the device bus 22 In the event of an I/O eπor the fake bit SRR[0] of the SRR 188 coπespondmg to the device which caused the eπor is set by the hardware configuration of the bπdge to disable further access to the device slot concerned. An interrupt may also be generated by the bridge to inform the software which oπgmated the access leadmg to the I/O eπor that the eπor has occurred The fake bit has an effect whether the system is m the split or the combmed mode of operation The ownership bits only have effect, however, m the split system mode of operation. In this mode, each slot can be in three states Not-owned, Owned by processing set 14, and Owned by processmg set 16 This is determined by the two SRR bits SRR[1] and SRR[2], with SRR[1] being set when the slot is owned by processmg set 14 and SRR[2] bemg set when the slot is owned by processmg set B If the slot is unowned, then neither bit is set (both bits set is an illegal condition and is prevented by the hardware). A slot which is not owned by the processmg set making the access (this includes un-owned slots) cannot be accessed and results in an abort A processmg set can only claim an un-owned slot; it cannot wrest ownership away from another processing set This can only be done by powermg-off the other processing set When a processmg set is powered off, all slots owned by it move to the un-owned state Whilst it is not possible for a processmg set to wrest ownership from another processmg set, it is possible for a processmg set to give ownership to another processmg set. The owned bits can be altered when m the combined mode of operation state but they have no effect until the split mode is entered Table 2 below summarizes the access rights as determined by an SRR 118. From Table 2, it can be seen that when the 4-bit SRR for a given device is set to 1100, for example, then the slot is owned by processmg set B (i.e. SRR[2] is logic high) and processmg set A may not read from or write to the device (i.e. SRR[1] is logic low), although it may read from or write to the bπdge "FAKE AT" is set logic low (i.e. SRR[0] is logic low) mdicatmg that access to the device bus is allowed as there are no faults on the bus. As "ARB EN" is set logic high (i.e. SRR[3] is logic high), the device with which the register is associated can become master of the D bus This example demonstrates the operation of the register when the bus and associated devices are operating coπectly. TABLE 2 SRR PA BUS PB BUS Device Interface [3[2][1][0] 0000 xOOx Read/Write bridge SRR Read/Write bπdge SRR Access denied 0010 Read/Wπte bπdge Read Write bridge Access Demed because Owned D Slot No access to D Slot arbitration bit is off 0100 Read/Write bridge Read/write bridge Access Denied because No access to D Slot Access to D Slot arbitration bit is off 1010 Read/Wnte bπdge, Read/Write Bridge Access to CPU B Denied Owned D Slot No access to D Slot Access to CPU A OK 1100 Read/Write bridge, Read/Write bridge Access to CPU A Denied No access to D Slot Access to D Slot Access to CPU B OK 0011 Read/Write bridge, Read/Write bridge Access Denied because Bridge discard writes No access to D Slot Arbitration bit is off 0101 Read/Wπte bridge, Read/Write bridge Access Denied because No access to D slot Bridge discards writes Arbitration bit is off 1011 Read/Write bridge, Read/Write bridge Access to CPU B Denied Bridge discard writes No access to D Slot Access to CPU A OK 1101 Read/Wnte bπdge, Read/Write bridge Access to CPU B Denied No access to D slot Bridge discards writes Access to CPU A OK In an alternative example, where the SRR for the device is set to 0101, the setting of SRR[2] logic high mdicates that the device is owned by processing set B However, as the device is malfunctionmg, SRR[3] is set logic low and the device is not allowed access to the processmg set SRR[0] is set high so that any writes to the device are ignored and reads therefrom return indeterminate data In this way, the malfunctionmg device is effectively isolated from the processmg set, and provides indeterminate data to satisfy any device drivers, for example, that might be looking for a response from the device Figure 26 illustrates the operation of the bridge 12 for duect memory access by a device such as one of the devices 28, 29, 30, 31 and 32 to the memory 56 of the processmg sets 14 and 16 When the D bus arbiter 185 receives a direct memory access (DMA) request 193 from a device (e g , device 30 m slot 33) on the device bus, the D bus arbiter determmes whether to allocate the bus to that slot As a result of this grantmg procedure, the D-bus arbiter knows the slot which has made the DMA request 193 The DMA request is supplied to the address decoder 142 m the bridge, where the addresses associated with the request are decoded The address decoder is responsive to the D bus grant signal 194 for the slot concerned to identify the slot which has been granted access to the D bus for the DMA request The address decode logic 142 holds or has access to a geographic address map 196, which identifies the relationship between the processor address space and the slots as a result of the geographic address employed This geographic address map 196 could be held as a table m the bridge memory 126, along with the posted wπte buffer 122 and the dirty RAM 124 Alternatively, it could be held as a table m a separate memory element, possibly forming part of the address decoder 142 itself The map 182 could be configured m a form other than a table The address decode logic 142 is configured to venfy the correctness of the DMA addresses supplied by the device 30. In one embodiment of the mvention, this is achieved by comparmg four significant address bits of the address supplied by the device 30 with the coπespondmg four address bits of the address held in the geographic addressmg map 196 for the slot identified by the D bus grant signal for the DMA request In this example, four address bits are sufficient to determme whether the address supplied is withm the coπect address range In this specific example, 32 bit PCI bus addresses are used, with bits 31 and 30 always bemg set to 1, bit 29 being allocated to identify which of two bridges on a motherboard is being addressed (see Figure 2) and bits 28 to 26 identifymg a PCI device Bits 25-0 define an offset from the base address for the address range for each slot Accordmgly, by comparmg bits 29-26, it is possible to identify whether the address(es) supplied fall(s) within the appropriate address range for the slot concerned It will be appreciated that m other embodiments a different number of bits may need to be compared to make this determination depending upon the allocation of the addresses The address decode logic 142 could be aπanged to use the bus grant signal 184 for the slot concerned to identify a table entry for the slot concerned and then to compare the address in that entry with the address(es) received with the DMA request as described above Alternatively, the address decode logic 142 could be aπanged to use the address(es) received with the DMA address to address a relational geographic address map and to determme a slot number therefrom, which could be compared to the slot for which the bus grant signal 194 is intended and thereby to determme whether the addresses fall within the address range appropriate for the slot concerned Either way, the address decode logic 142 is aπanged to permit DMA to proceed if the DMA addresses fall withm the expected address space for the slot concerned Otherwise, the address decoder is aπanged to ignore the slots and the physical addresses The address decode logic 142 is further operable to control the routmg of the DMA request to the appropπate processmg set(s) 14/16 If the bridge is m the combmed mode, the DMA access will automatically be allocated to all of the ln-sync processmg sets 14/16 The address decode logic 142 will be aware that the bπdge is m the combmed mode as it is under the control of the bπdge controller 132 (see Figure 8) However, where the bπdge is m the split mode, a decision will need to be made as to which, if any, of the processmg sets the DMA request is to be sent When the system is m split mode, the access will be directed to a processmg set 14 or 16 which owns the slot concerned If the slot is un-owned, then the bridge does not respond to the DMA request. In the split mode, the address decode logic 142 is operable to determine the ownership of the device onginating the DMA request by accessmg the SRR 118 for the slot concerned The appropriate slot can be identified by the D bus grant signal. The address decode logic 142 is operable to control the target controller 140 (see Figure 8) to pass the DMA request to the appropriate processmg set(s) 14/16 based on the ownership bits SRR[1] and SRR[2] If bit SRR[1] is set, the first processmg set 14 is the owner and the DMA request is passed to the first processmg set If bit SRR[2] is set, the second processmg set 16 is the owner and the DMA request is passed to the second processmg set If neither of the bit SRR[1] and SRR[2] is set, then the DMA request is ignored by the address decoder and is not passed to either of the processmg sets 14 and 16 Figure 27 is a flow diagram summarizing the DMA verification process as illustrated with reference to Figure 24 In stage S20, the D-bus arbiter 160 arbitrates for access to the D bus 22 In stage S21, the address decoder 142 verifies the DMA addresses supplied with the DMA request by accessmg the geographic address map In stage S22, the address decoder ignores the DMA access where the address falls outside the expected range for the slot concerned Alternatively, as represented by stage S23, the actions of the address decoder are dependent upon whether the bridge is m the combmed or the split mode If the bridge is in the combmed mode, then m stage S24 the address decoder controls the target controller 140 (see Figure 8) to cause the routmg matnx 80 (see Figure 6) to pass the DMA request to both processing sets 14 and 16 If the bridge is m the split mode, the address decoder is operative to veπfy the ownership of the slot concerned by reference to the SRR 118 for that slot m stage S25 If the slot is allocated to the first processing set 14 (I e the SRR[1] bit is set), then m stage S26 the address decoder 142 controls the target controller 140 (see Figure 8) to cause the routmg matrix 80 (see Figure 6) to pass the DMA request to first processing set 14 If the slot is allocated to the second processmg set 16 (I e the SRR[2] bit is set), then in stage S27 the address decoder 142 controls the target controller 140 (see Figure 8) to cause the routmg matrix 80 (see Figure 6) to pass the DMA request to the second processmg set 16 If the slot is unallocated (I e neither the SRR[1] bit nor the SRR[2] bit is set), then in step SI 8 the address decoder 142 ignores or discards the DMA request and the DMA request is not passed to the processing sets 14 and 16 A DMA, or direct vector memory access (DVMA), request sent to one or more of the processing sets causes the necessary memory operations (read or wπte as appropriate) to be effected on the processmg set memory There now follows a descnption of an example of a mechanism for enablmg automatic recovery from an EState (see Figure 11) The automatic recovery process mcludes rerntegration of the state of the processmg sets to a common status m order to attempt a restart m lockstep To achieve this, the processmg set which asserts itself as the primary processmg set as descnbed above copies its complete state to the other processmg set This mvolves ensurmg that the content of the memory of both processors is the same before trying a restart m lockstep mode However, a problem with the copymg of the content of the memory from one processmg set to the other is that durmg this copymg process a device connected to the D bus 22 might attempt to make a direct memory access (DMA) request for access to the memory of the primary processmg set If DMA is enabled, then a wπte made to an area of memory which has akeady been copied would result m the memory state of the two processors at the end of the copy not bemg the same In principle, it would be possible to inhibit DMA for the whole of the copy process However, this would be undesirable, bearing m mind that it is desirable to minimise the time that the system or the resources of the system are unavailable As an alternative, it would be possible to retry the whole copy operation when a DMA operation has occuπed during the penod of the copy However, it is likely that further DMA operations would be performed durmg the copy retry, and accordmgly this is not a good option either Accordmgly, m the present system, a dirty RAM 124 is provided m the bπdge As descnbed earlier the dirty RAM 124 is configured as part of the bndge SRAM memory 126 The dirty RAM 124 compπses a bit map havmg a dirty mdicator, for example a dirty bit, for each block, or page, of memory The bit for a page of memory is set when a wπte access to the area of memory concerned is made In an embodiment of the invention one bit is provided for every 8K page of mam processmg set memory The bit for a page of processmg set memory is set automatically by the address decoder 142 when this decodes a DMA request for that page of memory for either of the processmg sets 14 or 16 from a device connected to the D bus 22 The dirty RAM can be reset, or cleared when it is read by a processmg set, for example by means of read and clear instructions at the beginning of a copy pass, so that it can start to record pages which are dirtied since a given time The dirty RAM 124 can be read word by word If a large word size is chosen for readmg the dirty RAM 124, this will optimise the readmg and resetting of the dirty RAM 124 Accordmgly, at the end of the copy pass the bits m the duty RAM 124 will mdicate those pages of processmg set memory which have been changed (or dirtied) by DMA wπtes during the penod of the copy A further copy pass can then be performed for only those pages of memory which have been dirtied This will take less time that a full copy of the memory Accordmgly, there are typically less pages marked as duty at the end of the next copy pass and, as a result, the copy passes can become shorter and shorter As some time it is necessary to decide to inhibit DMA wπtes for a short penod for a final, short, copy pass, at the end of which the memoπes of the two processmg sets will be the same and the primary processmg set can issue a reset operation to restart the combmed mode The dirty RAM 124 is set and cleared m both the combmed and split modes This means that in split mode the dirty RAM 124 may be cleared by either processmg set The dirty RAM 124 address is decoded from bits 13 to 28 of the PCI address presented by the D bus device Eπoneous accesses which present illegal combmations of the address bits 29 to 31 are mapped mto the duty RAM 124 and a bit is dirtied on a write, even though the bridge will not pass these transactions to the processing sets When readmg the dirty RAM 124, the bridge defines the whole area from 0x00008000 to OxOOOOffff as dirty RAM and will clear the contents of any location m this range on a read As an alternative to providmg a smgle duty RAM 124 which is cleared on bemg read, another alternative would be to provide two dirty RAMs which are used m a toggle mode, with one being written to while another is read Figure 28 is a flow diagram summansmg the operation of the dirty RAM 124 In stage S41, the primary processmg set reads the dirty RAM 124 which has the effect of resetting the duty RAM 124 In stage S42, the primary processor (e.g. processmg set 14) copies the whole of its memory 56 to the memory 56 of the other processmg set (e g processmg set 16) In stage S43, the primary processmg set reads the dirty RAM 124 which has the effect of resetting the dirty RAM 124 In stage S44, the primary processor determmes whether less than a predetermmed number of bits have been wntten m the dirty RAM 124 If more than the predetermmed number of bits have been set, then the processor m stage S45 copies those pages of its memory 56 which have been dirtied, as indicated by the dirty bits read from the dirty RAM 124 m stage S43, to the memory 56 of the other processmg set Control then passes back to stage S43 If, m stage S44, it is determined less than the predetermmed number of bits have been wntten m the duty RAM 124, then m Stage S45 the primary processor causes the bndge to inhibit DMA requests from the devices connected to the D bus 22 This could, for example, be achieved by clearing the arbitration enable bit for each of the device slots, thereby denymg access of the DMA devices to the D bus 22 Alternatively, the address decoder 142 could be configured to ignore DMA requests under mstructions from the primary processor Durmg the period m which DMA accesses are prevented, the primary processor then makes a final copy pass from its memory to the memory 56 of the other processor for those memory pages coπespondmg to the bits set m the dirty RAM 124 In stage S47 the primary processor can issue a reset operation for initiating a combmed mode In stage S48, DMA accesses aie once more permitted It will be appreciated that although particular embodiments of the mvention have been descnbed, many modifications/additions and or substitutions may be made withm the spint and scope of the present mvention as defined m the appended claims For example, although m the specific descnption two processmg sets are provided, it will be appreciated that the specifically descπbed features may be modified to provide for three or more processmg sets

Claims: WHAT IS CLAIMED: 1. A bridge for a computer system comprising at least a first processing set and a second processing set each connected to the bridge via an I/O bus, a resource control mechanism in the bridge comprising: an interface for exchanging signals with one or more resource slots of a device bus that is capable of being connected to the bridge, each of the resource slots being capable of communicating with a system resource; and a register associated with each system resource, the register having switchable indicia that indicate an operating state of the associated system resource, the control mechanism being operable in use to direct signals to and/or from respective system resources of the computer system. 2. The bridge of Claim 1, wherein at least one of the resources is an I/O device. 3. The bridge of Claim 1, wherein the register comprises memory for storing the indicia. 4. The bridge of Claim 3, wherein the register comprises a 4-bit memory unit. 5. The bridge of Claim 1, wherein the computer system comprises two processing sets, each of the processing sets comprising one or more processors. 6. The bridge of Claim 5, wherein at least some of the switchable indicia are used to indicate whether the associated resource has been allocated to one of the processor sets. 7. The bridge of Claim 6, wherein the at least some of the switchable indicia additionally indicate which of the processor sets the resource associated with that register has been allocated to. 8. The bridge of Claim 5, wherein the register comprises a 4-bit memory unit and the computer system comprises a first processing set and a second processing set, a second bit and a third bit of the unit being switchable to indicate whether the associated resource is owned by the first processing set, the second processing set or not owned by either the first processing set or the second processing set. 9. The bridge of Claim 5, wherein at least one of the switchable indicia indicates whether or not the associated resource has been allowed access to one of the processing sets. 10. The bridge of Claim 5, wherein at least one of the switchable indicia is selectively operable to generate indeterminate data when a read of the resource associated with that register is attempted. 11. A bridge for a computer system having at least two processor sets and a routing matrix, a resource control mechanism in the bridge comprising a register having a plurality of switchable indicia that each indicate an operating state of an associated resource of the computer system, the routing matrix being capable of routing instructions and/or data to or from a resource identified by at least one of the identifying indicia as being owned by one of the processor sets. 12. A bridge for a computer system having a first processor set and a second processor set, a resource control mechanism in the bridge comprising a four bit register wherein two of the four bits are switchable to and/or from: a first state indicating that a resource associated with the register is not allocated to either the first processor set or the second processor set; a second state indicating that the resource associated with the register is allocated to the first processor set; and a third state indicating that the resource associated with the register is allocated to the second processor set. 13. A bridge according to Claim 12, wherein a first bit of a remaining two bits of the four bit register is switchable to and/or from: a first state indicating that the associated resource is allowed access to one of the first and second processor sets; and a second state indicating that the associated resource is not allowed access to either of the first and second processor sets, the first state only being initiated when the two of the four bits of the register indicate that the associated resource is owned by either of the first and second processor sets. 14. A bridge according to Claim 13, wherein a second bit of the remaining two bits of the four bit register is switchable to and/or from: a first state indicating that writes to the associated resource are allowed; and a second state indicating that writes to the associated resource are to be ignored and that indeterminate date will be generated in response to any attempted writes to that associated resource. 15. A method of controlling resources of a computer system, the method comprising the steps of establishing a register in a bridge of the computer system, the register having a plurality of indicia switchable to indicate operating states of a resource associated with a slot of a bus connected to the bridge; and controlling the resource in accordance with the operating states indicated by the indicia of the register. 16. The method of Claim 15, wherein the register is implemented in random access memory. 17. The method of Claim 15, wherein the register comprises a four bit register. 18. The method of Claim 15, comprising updating the register to reflect changes in the operating state of the resource. 19 A method of routing signals from a first processor set or a second processor set to at least one resource provided on a resource bus selectively connectable to the first or second processor set, the method compnsing the steps of propagatmg signals from one of the first and second processor sets, the signals bemg destined for a resource of the computer system, lnteπogatrng a register to determme whether the one of the first and second processor sets is allowed access to the resource, and routing the signals to the resource if the register mdicates that access to the resource for the one of the first and second processor sets is allowed 20 A computer system compπsmg a plurality of processmg sets each havmg one or more processors and each bemg connected to a processor bus, a plurality of devices each associated with a slot of an I/O device bus, and a bπdge connected to the plurality of processor busses and to the I/O device bus, the bridge comprising a device control mechanism havmg an mterface for exchanging signals with one or more of the slots and associated devices, and a register associated with each device, the register havmg switchable indicia that mdicate an operatmg state of the associated device, the control mechanism bemg operable m use to direct signals to and/or from respective system resources of the computer system 21 A bridge for a multi-processor computer system, the bridge compπsmg a resource control mechanism havmg an mterface for exchangmg signals with one or more resource slots, each of the resource slots bemg capable of communicating with a system resource, and a register associated with each system resource, the register having switchable indicia that mdicate an operating state of the associated system resource, the control mechanism being operable m use to direct signals to and/or from respective system resources of the computer system

Inventors: GARNETT PAUL J, OYELAKIN FEMI A, ROWLINSON STEPHEN, WILLIAMS EMRYS J, GARNETT, PAUL, J., OYELAKIN, FEMI, A., ROWLINSON, STEPHEN, WILLIAMS, EMRYS, J.
Applicants: SUN MICROSYSTEMS INC, SUN MICROSYSTEMS, INC.
Application year: 1999
Main classification: G06F13
IPC codes: G06F11, G06F13