Class-D amplifier with enhanced bandwidth

Abstract: A class-D amplifier comprising an input integrating stage (Op-Amp, R1, C), a modulating stage (PWM) of the integrated input signal output by said integrating stage, using as a carrier an alternate waveform ( Vtr ) of a frequency ( fsw ), sufficiently higher than the frequency band of the analog input signal, outputting a digital signal switching between a positive voltage (+ Vcc ) and a negative voltage ( -Vcc ), and whose average value ( Vo ) represents an amplified replica of the input analog signal, an output power stage (BUFFER), producing an output digital signal ( Vout ), a feedback line constituted by a resistor ( R2 ) connected between the output of said output power stage (BUFFER) and an input node of an operational amplifier ( Op-Amp ) constituting said integrating stage, and a low pass filter reconstructing an output analog signal ( V o), further comprises a delay stage (DELAY Td ), functionally coupled in the direct path of propagation of said digital signal from the output of said PWM stage to an input of said output power stage (BUFFER), delaying said digital signal by a delay ( Td ) whose value is defined in function of a desired broadening of the bandwidth and in consideration of the corresponding restriction of the range of variation of the duty-cycle of the output digital signal.

Description: FIELD OF THE INVENTION The present invention relates to Class-D PWM amplifiers. STATE OF THE ART Fig. 1 shows the typical scheme of a Class-D amplifier. This type of amplifier is a well-known PWM system (re: K. Nielsen, "Review and Comparison of PWM methods for analog and digital input switching power amplifiers" AES 22-25/3/97). The operation of the amplifier is depicted in Fig. 2. The input signal ( Vin ) is compared with a waveform, most often triangular ( Vtr ) having a relatively high frequency fsw much higher than the frequency band limit of the amplifier. The output ( Vout ) is a PWM (Pulse Width Modulated) signal switching between a positive voltage ( Vcc ) and a negative voltage ( -Vcc ). The average value ( Vo ) of the output digital signal represents an amplified replica of the analog input signal and may be easily calculated with the following equations: Vo = G · Vin G = Vcc Vtr where Vtr is the peak value of the reference (triangular) wave and G is the voltage gain of the amplifier. The relationship between Vo and Vin is thereby theoretically linear. In practice though this is not true because the non-idealities of the triangular wave and of the output buffer stage may produce an unacceptable amount of distortion on the output signal. Therefore, a feedback loop capable of compensating the non-idealities of the system is a must. A typical feedback circuit is shown in Fig. 3 Given that the average charge of the integrating capacitor C must be null during a switching period ( Tsw=1 / fsw ), it may be assumed that the average current on the feedback resistor R2 during a switching period is equal to the current on the input resistor R1 and therefore: Vo = G c · Vin G c = 1 + R 2 R 1 where Gc is the closed loop gain of the system. The open loop gain Gloop of the system may be easily calculated by analyzing the scheme of Fig. 4, wherein a linearized system is considered with the Vin node short-circuited to ground and the PWM stage substituted with a linear block with a gain Vcc / Vtr (re: equation 2). The input resistor R1 has been neglected because, at the frequencies of interest, the negative input of the integrator represents a virtual ground (because the integrating capacitor C represents an extremely low impedance) and therefore there is not any significative voltage drop on the input resistor R1 . The open loop gain Gloop and the unity gain frequency are thus respectively defined by: G l ( s ) = Vcc Vtr · 1 s·R 2 ·C f o = 1 2 π · Vcc Vtr · 1 R 2 ·C This system has a stability limit that limits the system's bandwidth. This limit may be calculated (by referring to Fig. 3) by considering that for a correct functioning of the system, the slope of the ripple signal ( Vr ) must be lower than the slope of the triangular wave ( Vtr ). If this condition is not met, the system may produce repeated output switchings at intervals equal to the delay of the chain delay defined by the PWM stage and by the output buffer stage. Correct and critical functioning conditions are schematically depicted in the diagrams of Fig. 5. By converting this concept into formulas: p l = 4 · Vtr · fsw (slope of triangular waveform) To obtain the limit condition the maximum slope of the ripple signal should be considered, in other words the maximum input signal Vin max . From equations (3), (4): Vin max = Vcc Gt Therefore, the maximum p2 value is given by: Therefore, the limit condition is: Considering equation (6), this condition may be rewritten as: which represents a bandwidth limit. It should be noticed that for a Ggain>10 (that is for R2 / R1>10 ), equation (12) may simplified into the following equation: f 0 < fsw π OBJECT AND SUMMARY OF THE INVENTION Confronted with these limitations and drawbacks of known amplifiers, a manner has now been found to overcome this limiting critical condition and allow for an extended bandwidth at the expense of a negligible reduction of the range of variation of the duty-cycle of the digital output signal. The amplifier of the present invention functions even when the slope of the triangular wave is lower than the slope of the ripple of the input signal without causing spurious repetitive switchings of the output signal. This important result is obtained by introducing a certain delay on the direct signal path, downstream of the PWM output stage, and in any case before the output node from which the feedback signal is derived for compensating the nonidealities of the system. The invention is defined in claim 1. The various aspects and effects of the invention are described with more details in the following description of an embodiment and with reference to the attached drawings. BRIEF DESCRIPTION OF THE DRAWINGS Figure 1 shows the basic scheme of a class-D amplifier; Figure 2 shows the characteristic waveforms of a PWM amplifier; Figure 3 is a functional block diagram of a class-D amplifier of a known type; Figure 4 is a simplified open loop analysis model of the amplifier of Fig. 3; Figure 5 shows diagrams illustrative of the stability limit of a known amplifier; Figure 6 is a functional block diagram of a class-D amplifier according to the present invention; Figure 7 is a diagram illustrating the effect of the delay introduced according to the present invention; Figure 8 is a scheme of the functioning conditions of the amplifier of the invention; Figure 9 shows the maximum allowable ratio between the slope of the ripple and the slope of the triangular waveform without causing instability problems; Figure 10 shows the characteristic of bandwidth increment in function depending of the introduced delay; Figure 11 shows the characteristic of bandwidth increment in function of the maximum duty-cycle; Figure 12 shows a possible embodiment of the delay circuit; Figure 13 shows the waveforms of the delay circuit for a duty-cycle of 50%; Figure 14 shows the waveforms for a duty-cycle close to its maximum limit. GENERAL DESCRIPTION OF THE INVENTION The functional diagram of a class-D amplifier according to the present invention is shown in Fig. 6. By way of comparison with the diagram of Fig. 3 of an amplifier realized according to know techniques, the only element that is introduced is the block DELAY Td , coupled in the direct signal path, in cascade to the output of the comparator PWM and, preferably, before the output power stage BUFFER. The functioning with and without the introduction of the delay Td is shown in Fig. 7. It may be immediately concluded that the introduction of the delay Td permits the system to function satisfactorily even with a larger slope of the ripple (p2b) than the slope of the triangular wave, without causing spurious switchings of the output. For an accurate calculation of the improvement of the bandwidth limit when using the delay block of the invention, it should be considered that the introduction of the delay changes the PWM stage gain (the larger is the introduced delay the lower is the gain). Moreover, differently from what occurs in a known system, the most critical condition for the stability of a system with a delay block, according to the present invention, coincides with that of an average duty-cycle and not with that of maximum or minimum duty-cycle as it was the case in a known system. Bandwidth calculation The starting hypothesis is the following. The PWM modulator may be considered, for bandwidth calculation, as a linear block with a voltage gain given by the ratio between the average of the output signal and the average of the ripple signal. The calculation entails three steps: 1) expressing the PWM modulator gain as a function of the delay; 2) defining the stability conditions; 3) calculating the maximum bandwidth allowed. Fig. 8 indicates the parameter notation adopted for the analysis and calculation. 1) Gain of the PWM modulator The following equations among the parameters involved area readily verified: p 1 = p · (1 - d ) p 2 = pd pt = 4 Vtr · fsw Toff = (1 - d )/ fsw p = 2 Vcc / τ where d is the duty-cycle, 2*p is the slope of the ripple for d = 0.5, pt is the slope of the triangular wave, Vtr is the peak voltage of the triangular wave, fsw is the switching frequency and τ is the time constant of the system ( τ = R2·C, re: Fig. 6). By using these equations, it is useful to express the voltages V1 and V2 of Fig. 8 with geometrical considerations and thereby the average voltage of the ripple signal. The result is that the voltage gain of the PWM modular, as defined in the starting hypothesis, is given by: where G0 is the gain in absence of delay ( G0 = Vcc / Vtr ) and Td is the delay. Therefore, the delay reduces the gain of the PWM modulation stage. 2) Stability conditions It is useful to introduce a new parameter defined by: α = p p t Therefore, 2*α represents the ratio of the calculated slope of the ripple with d = 0.5 and the slope of the triangular wave. Thus, the problem is to establish the maximum admissible value of the parameter a without generating stability problems. With reference to Fig. 8, the stability condition is given of course by the equality V2=Vtr . Upon imposing this condition, in order to guarantee the stability throughout the whole range of variation of the duty-cycle field, the ratio α must be less than the limit value αmax ., whose value is shown in the diagram of Fig. 8. For example, with a delay of 200ns, a system with a α factor of about 1.6 may be implemented without any stability problems. 3) Maximum allowed bandwidth From the starting hypothesis on the PWM modulator gain, it follows that the bandwidth of the system (that is the unity open loop gain frequency) is given by: f 0 = G PWM 2π·τ Using the equation (14), the equation (15) may be rewritten as a function of the α parameter: Since fsw /π represents the maximum bandwidth with Td = 0 , an expression of the bandwidth improvement (β factor) due to the delay introduced may be expressed as: By introducing the equation (17) the maximum value of the α factor for a certain delay Td (re: Fig. 9), the maximum bandwidth increment of the bandwidth (β max. ) for the considered delay Td may be calculated. Fig. 10 shows the bandwidth improvement factor β as a function of the delay (for a switching frequency fsw = 200KHz ). For example, with a delay of 300ns the improvement is of about 60%. In any case, the maximum usable delay is upper limited by the maximum duty-cycle at a certain switching frequency. Indeed, in order to obtain for example a duty-cycle of 90% at a switching frequency of 200KHz, the introduced delay should not be larger than 500ns, that is to say not greater than Toff=(i-d) / fsw . Beyond this limit, the system would start to skip cycles, reproducing "too high" duty-cycle situation. Thence, it may be useful to express the bandwidth increment as a function of the maximum allowed duty-cycle. This relation is shown in Fig. 11. With reference to the characteristics of Fig. 11, for example, for a delay Td = 250ns at a switching frequency fsw = 200KHz , the duty-cycle may range between 5% and 95% without skipping phenomena and with a bandwidth improvement factor of 1.5 referred to an amplifier made according to the prior art. EXAMPLE OF AN EMBODIMENT In practice, it is requested to realize a circuit that reproduces at an output a delayed replica of the PWM input signal. Given that the delay Td to be introduced may be larger than the minimum time Ton (or Toff ) of a phase of the PWM input signal, it is necessary to use two independent voltage ramps, respectively starting with the rising edge and with the falling edge of the digital input signal. Fig. 12 shows a possible circuit diagram of the delay block that is introduced in the direct signal path of the PWM signal in an amplifier realized according to the present invention. By referring to the scheme of Fig. 12, on the nodes A and A ' there exist respectively the ramp starting with the rising edge of the input signal and the ramp starting with the falling edge of the input signal. The slope of the voltage ramps is given by -I / C, where I is the discharge current of the capacitor C. In order to better comprehend the functioning of the circuit, reference may be made to the waveforms of Fig. 13, which illustrate a whole switching period with an input signal with a duty-cycle of 50%. When the input signal goes high, the FF1 flip-flop is set and the capacitor C is discharged at a constant current I . The voltage on the node A starts to decrease with a constant slope I / C . When the voltage on the node A reaches the threshold Vth of the inverter, the voltage on the node B switches high and the FF 0 input flip-flop is set. By way of simplicity, the inverters are symmetrical (that is Vth=Vs / 2, being Vs the supply voltage), therefore the delay is given by: Td = VsC 2 I Under these conditions, with the node B in a logic high state, the reset of the flip-flop FF1 takes place when the input signal goes low. The reset of FF1 determines the reset of the voltage ramp (the node A switching to a high logic state). Similarly, it may be readily comprehended also the functioning of the lower branch of the circuit, starting from a falling edge of the input signal. Fig. 14 illustrates a condition when the duration of the high input phases Ton is shorter than the delay Td. It may be observed that in this case, the reset of the FF1 flip-flop follows directly the rising edge of the voltage on the node B. Therefore the duration of the set pulse of the output flip-flop FF 0 is determined solely by the delay of the flip-flop FF1 and of the pair of inverters.

Claims: A class-D amplifier comprising an input integrating stage ( Op-Amp, R1, C ), a modulating stage (PWM) of the integrated input signal output by said integrating stage, using as a carrier an alternate waveform ( Vtr ) of a frequency ( fsw ), sufficiently higher than the frequency band of the analog input signal, outputting a digital signal switching between a positive voltage (+ Vcc ) and a negative voltage ( -Vcc ), and whose average value ( Vo ) represents an amplified replica of the input analog signal, an output power stage (BUFFER), producing an output digital signal ( Vout ), a feedback line constituted by a resistor ( R2 ) connected between the output of said output power stage (BUFFER) and an input node of an operational amplifier ( Op-Amp ) constituting said integrating stage, and a low pass filter reconstructing an output analog signal ( Vo ), characterized in that it further comprises a delay stage (DELAY Td ) functionally coupled in the direct path of propagation of said digital signal from the output of said (PWM) stage to an input of said output power stage (BUFFER), delaying said digital signal by a delay ( Td ) whose value is defined such that stable operation of the amplifier is ensured even when the slope of said integrated input signal is steeper than the slope of said carrier. The amplifier according to claim 1 characterized in that said delay stage (DELAY Td ) is constituted by a circuit defining two propagation paths of the digital input signal toward respective set and reset inputs of a bistable output circuit ( FF 0 ), a first path comprising a first bistable circuit ( FF1 ) set by the input digital signal, the output Q of which drives a first inverter ( INV1 ) charging a capacitor ( C ) discharged at a constant current ( l ), the charge ramp of said capacitor driving a second inverter ( INV2 ) whose output is coupled to a set input of said bistable output circuit ( FF 0 ) and to a first input of a logic AND gate receiving on a second input said digital input signal, inverted by a third inverter ( INV3 ), the output of said AND gate being coupled to a reset input of said first bistable circuit ( FF1 ); a second path comprising a second bistable circuit ( FF2 ) set by the inverted input digital signal, output by said third inverter ( INV3 ), the output ( Q ) of said second bistable circuit ( FF2 ) driving a fourth inverter ( INV4 ) charging a capacitor ( C ) discharged in a constant current ( I ), the charge ramp of said capacitor driving a fifth inverter ( INV5 ) whose output is coupled to the reset input of said bistable output circuit ( FF 0 ) and to a first input of a logic AND gate receiving on a second input said input digital signal, the output of said AND gate being coupled to the reset input of said second bistable circuit ( FF2 ).

Inventors: FRANCHINI LUIGI, LABBE ERIC, MASINI MARCO, FRANCHINI, LUIGI, LABBE, ERIC, MASINI, MARCO
Applicants: ST MICROELECTRONICS SRL, STMICROELECTRONICS S.R.L.
Application year: 1999
Main classification: H03F3
IPC codes: H03F3