MULTIPLEXER CIRCUIT AND ANALOGUE-TO-DIGITAL CONVERTER

Abstract: A multiplexer circuit (100) comprises at least two input channels (IN0, IN1) and an output channel (2), each input channel (IN0, IN1) comprising a first transmission gate (FT0, FT1) which can be switched by a select signal (SELECT0, <o>SELECT0</o>; SELECT1, <o>SELECT1</o>) for connecting the input channel (IN0, IN1) to the output channel (2), and wherein at least one of the input channels (IN0, IN1) comprises a bypass circuit for preventing a current flowing through the first transmission gate (FT0, FT1) from reaching the other input channel, and a second transmission gate (ST0, ST1).

Description: MULTIPLEXER CIRCUIT AND ANALOGUE-TO-DIGITAL CONVERTER The invention relates to a multiplexer circuit according to the preamble of claim 1 and to an analogue-to-digital converter (ADC) comprising such a multiplexer circuit. In monolithic IC's transmission gates can be used for multiplexer circuits. They are suitable to select one of several analogue input channels to connect the selected channel, for example, to an ADC circuit on chip. Multiplexer circuits built with transmission gates implemented in monolithic IC's with MOS (metal oxide semiconductor) type circuits are known from CMOS Digital Integrated Circuits, Analysis and Design, S.M. Kang, Y. Leblebici, McGRAW-HILL INTERNATIONAL EDITIONS, ISBN 0-07-038046-5, page 274 and from Principles of CMOS VLSI Design, A System Perspective, second edition ADDISON WESLEY, N.H.E., Weste, K. Eshraghian, ISBN 0-201-53376-6, pages 17, 304. An example of a conventional multiplexer circuit 1 comprising transmission gates is shown in Fig. 5. The multiplexer circuit 1 comprises at least two input channels INo, IN ι which are connected with a common output channel 2. Of course, a plurality of input channels INo, I i, IN 2 ,... INi ma Y be provided in the multiplexer circuit. For selecting one of said analogue input channels IN 0 , IN X the multiplexer circuit comprises transmission gates FT 0 , FTι_ between the input channel IN 0 , I^± and the output channel 2, respectively. The multiplexer can select one of the two input channels INQ, INi by select signals SELECT 0 , SELECTQ, SELECTi, SELECTi generated by a decoder circuit 10. The decoder circuit generates a select signal SELECTo, SELEC i and an inverted select signal SELECTQ, SELECTi for each input channel IN 0 , INi, respectively, which are applied to the corresponding transmission gates FTQ, FTi. The decoder circuit is a n to 2 n decoder (i = 2 n ) , which ensures that only one of the select signals SELECTQ to SELECTi becomes true while the others are false, i.e. only one channel is open while the others are closed. In the example according to Fig. 4 the channel INi is selected i. e. the transmission gate FTi is open, whereas the channel IN Q is not selected and the transmission gate FT 0 is closed. Analog voltages Ui, U 2 are applied to the input channels IN Q , INi, respectively. The voltage at the output channel 2 is indicated as U out . The transmission gates FTo, FT ι are known CMOS transmission gates comprising p channel and n channel transistors having threshold voltages V THp and V THn , respectively. The multiplexer circuit is operated with a power supply voltage V cc and V ss is the ground potential OV. The operation of the multiplexer circuit is as follows. In a normal operation condition the following input voltage conditions are applied: Ui = [V ss ; V cc ] u 2 = [v ss ; Vcc]. That means the level of the input voltages Ui, U is between the power supply voltage level V C c and V ss . Under these conditions the transmission gates FT 0 and FTi operate as ideal switches. Since the transmission gate FT 0 is closed, the voltage U out is equal to U 2 : Uout = U 2 . No current will flow in the multiplexer circuit, i.e. the current in the channels INQ and INi is 0, respectively: Iinl = 0 ϊ-out - °- In case of an over or an under voltage applied to an input channel which is not selected i. e. which is not active a current will flow through the active channel. This is the under/over voltage operation condition. The following input voltage conditions are considered as under and over voltage conditions: Under voltage: -V THn + V ss < Ui < V ss . Over voltage: Vcc < Ui < Vcc + |V T Hpl , The voltage U is: U 2 = [v ss ; v cc ]. Under these conditions the transmission gate FTo i n channel INo does not work as an ideal switch any more. Due to "weak inversion" and the pn-diode structures of the CMOS transistors a current flows between INQ and INi. I out creates a voltage drop at the resistance of the transmission gate FTi in channel INi anc ^ the output resistance of the source of U 2 . Therefore, U out is not equal to the input voltage U 2 any more. Depending on the desired accuracy of the analogue signal this will be a problem. In particular for multiplexer circuits used in ADC's a noise at the injection source leads to worse accuracy, which makes the conversion results unusable (e.g. in case of an 8-bit ADC the absolute accuracy becomes 10-11 LSB instead of +/-2 LSB) . External over/undervoltage protection circuits are required in order to be able to use such ADC ' s. It is an object of the invention to provide a multiplexer circuit and an analogue-to-digital converter having an improved accuracy with respect to the output of an analogue input signal. The object is solved by a multiplexer circuit according to claim 1 and by an analogue-to-digital converter according to claim 12. Further developments of the invention are described in the dependent claims. Embodiments of the invention will be explained with reference to the accompanying drawings. Fig. 1 shows a multiplexer circuit according to a first embodiment of the invention. Fig. 2 shows a multiplexer circuit according to a second embodiment of the invention. Fig. 3 shows a multiplexer circuit according to the second embodiment of the invention more in detail. Fig. 4 shows a multiplexer circuit according to a further embodiment of the multiplexer circuit of Fig. 2. Fig. 5 shows an example of a conventional multiplexer circuit. A first embodiment of the multiplexer circuit according to the invention is shown in Fig. 1. Parts which are the same as in the conventional multiplexer circuit according to Fig. 4 are designated with the same reference signs and the description thereof will not be repeated. The multiplexer circuit according to this embodiment comprises a first transmission gate FTo, FT ι, for each channel respectively, and a second transmission gate STQ, STI for each channel. The output of the first transmission gate FTQ, FTi in each channel is connected with the input of the second transmission gates STQ, ST I , respectively. The output of the second transmission gate STQ and STi i connected with the output channel 2. The second transmission gate STQ, STI are controlled by the same select signals SELECTQ, SELECTQ and SELECTi, SELECTi as the first transmission gates FT 0 , FTi- A bypass circuit in form of an NMOS transistor 20, 21 is provided for each analogue input channel INo, IN ι- Each NMOS transistor 20, 21 is connected with its drain to a node 30 31. Each node 30, 31 is connected with the output of the first transmission gate FT 0 , F i and the input of the second transmission gate STo, STi, respectively. The source of each NMOS transistor 20, 21 is connected with the ground potential level V ss . The gate of each NMOS transistor receives the inverted select signal SELECT 0 , SELECTi, respectively, which is generated by the channel decoder 10. In this embodiment the NMOS transistors are controlled by the same select signal as the PMOS transistor of the transmission gates. In the example according to Fig. 1 the channel I i is selected and the first transmission gate FT X and the second transmission gate STi are both open. Since the NMOS transistor 21 receives the inverted select signal SELECTi on its gate, the NMOS transistor 21 is switched off for the selected channel INi. The channel IN Q is not selected and therefore, the first transmission gate FTo n< ^ tne second transmission gate STQ are both closed. Since the NMOS transistor 20 receives the inver- ted select signal SELECTQ on its gate, the NMOS transistor 20 is switched on for the not selected channel INQ. In operation the select signals are applied to the transmission gates such that the input channel INi is selected by opening the first transmission gate FTi and the second transmission gate STi by the select signal SELECTi (SELECTi = 1) . The other input channel INQ is not selected by closing the first transmission gate FTQ and the second transmission gate STo by applying the select signal SELECTQ (SELECTQ = 0) . In case the voltage Ui applied to the first input channel INQ has an over voltage i.e. Vcc < Ui < Vcc + |V THp |, a current Ii n ι flows through the first transmission gate FTo to node 30. Since the NMOS transistor 20 is switched on by the select signal SELECTQ, the current Ii n ι is bypassed through the NMOS transistor 20 to ground. The potential at node 30 is (due to being pulled down by NMOS transistor 20) in the range of [0, V C c]. Therefore, the transmission gate ST 0 operates as an ideal switch, i.e. closes perfectly. Therefore, the selected input channel INi is not influenced by the over voltage on the first input channel INQ. The output voltage u ou t i s equal to U . Without changing the circuit in Fig. 1 the NMOS transistor 20 pulls an undervoltage -V TH N < Ui < 0 at the input to a potential in the range of [-V THfN 0] at node 30. This is enough to switch the transmission gate STi off and to avoid influence to the analogue input. Hence, the NMOS transistor is a measure against under voltage. However, the bypass behaviour of the NMOS transistor for over voltage condition is better than for under voltage condition. Fig. 2 shows an embodiment of a multiplexer circuit in order to bypass the current for over or under voltage conditions. In the embodiment according to Fig. 2 parts which are equal to parts of the embodiment according to Fig. 1 are described with the same reference signs. The multiplexer circuit according to Fig. 2 comprises a pull-down bypass circuit 50, 51 in each channel INo, IN ι and i n addition a pull-up bypass circuit 60, 61. The pull-down bypass circuit 50, 51 is connected between a node 70, 71 and V ss level and the pull-up bypass circuit 60, 61 is connected between the node 70, 71 and V cc level, respectively. The multiplexer circuit according to Fig. 2 also comprises two operation conditions: In the normal operation condition the following input voltage conditions are applied: Ui = [v ss ; v cc ] u 2 = [v ss ; v cc ]. Under these conditions the transmission gates operate as ideal switches. The voltage U out is equal to U 2 . No current will flow: Iinl = 0 lout = °- In an under/over voltage operation condition the following input voltage conditions are considered as under and over voltage conditions: Under voltage: -V T T H H n n + V v scsc < Uuiη < V V SS Over voltage: Vcc < Ui < Vcc + |v THp | (V- TH n r V THp are threshold voltages of p- and n channel transistors) The voltage U 2 is : u 2 = [v ss ; v cc ] . Under these conditions the first transmission gate FT 0 in channel INQ does not work as an ideal switch. The current I n ι is bypassed to V ss level or V C c level by using the bypass circuit 50 or 60. The second transmission gate STQ is implemented in order not to change the U out voltage. In case of an over/under voltage condition the bypass circuit 50 reduces the input voltage for the second transmission gate ST 0 , so that no over voltage condition occurs at the second transmission gate STQ and the bypass circuit 60 increases the input voltage for the second transmission gate, so that no under voltage condition occurs at the second transmission gate STQ. Therefore, the second transmission gate will work again as an ideal switch. As a result no current flows between INQ and INi and the voltage U out is equal to the input voltage U 2 , i.e. I inl I ≥ 0 | in 2 | = 0 I lout I = o Uout = U 2 . An additional circuit senses either the voltage in front of FTo or between FT 0 and STQ and switches on either the bypass circuit to V C c i n case of under voltage or the bypass circuit to V ss in case of over voltage. This is necessary to avoid a shortcut between V C c nd V ss via the two bypass circuits. The combination of the bypass circuit and the sense circuit forms a bypass and sense circuit. In a further development the bypass and sense circuit contains elements to control the potential between FTQ and STQ. Fig. 3 shows a specific embodiment of the multiplexer circuit according to Fig. 2. For each channel the pull-down bypass circuit 50 is realized with an NMOS transistor 80, 81 and the pull-up bypass circuit is realized with a PMOS transistor 90, 91, respectively. The NMOS transistor will be used as over voltage protection and the PMOS transistor will be used as under voltage protection on channels that are not selected. A control circuit for the bypass circuits comprises NOR gates 100, 101, the output of which is connected with the gate of the NMOS transistor 80, 81, respectively. The control circuit further comprises NAND gates 110, 111, the output of which is connected with the gate of the PMOS transistor 90, 91, respectively. One input of the NOR gate 100, 101 is connected with the input voltage Ui, U , respectively, and the other input of the NOR gate 100, 101 is connected with the select signal SELECTQ, SELECTi. 0ne input of the NAND gate 110, 111 is connected with the input voltage U 1# U 2 , respectively., and the other input of the NAND gate 110, 111 is connected with the inverted select signal SELECT 0 , SELECTi. Therefore, the input signals of the control circuit are the input voltage Ui, U 2 and the select and the inverted select signals which control the transmission gates. If a channel is not selected (SELECT = 0) and an under voltage condition occurs (Ui < 0 V) the PMOS transistor 90 will be switched on. If a channel is not selected (SELECT = 0) and an over voltage condition occurs (Ui > 5 V) , the NMOS transistor 80 will be switched on. Fig. 4 shows a second specific embodiment of the multiplexer circuit according to Fig. 2. A control circuit for controlling the bypass circuit comprises a sense circuit for sensing a voltage in the input channel. The sense circuit and the bypass circuit in combination form a bypass and sense circuit consisting of a sense path and a bypass path. In the bypass and sense circuit to V ss the sense path comprises a PMOS transistor 130, 131 in series with an NMOS transistor 120, 121. The source of the PMOS transistor 130, 131 is connected to said first transmission gate FTo, FTi and the source of the NMOS transistor 120, 121 is connected to ground level V ss . The drain of the PMOS transistor 130, 131 is connected with the drain of the NMOS transistor 120, 121. The bypass path is formed of NMOS transistor 160, 161 the drain of which is connected with the output of said first transmission gate FTo, FTi and the source of which is connected with V S s • The gate of NMOS transistor 160, 161 is connected with the drains of the PMOS and NMOS transistors of the sense circuit. The driveability of NMOS transistor 120, 121 is very weak compared to the driveability of PMOS transistor 130, 131. For a channel that is switched off a voltage of 0.65V DD is applied to gate of PMOS 130, 131. Both the sense path and the bypass path are switched off as long as the potential at node 70, 71 fulfils the condition U70<0.65V DD +| V THp | . When due to an over voltage at the input the voltage at node 70, 71 exceeds U70>0.65V DD +| V THp | the sense path drives a small current to V ss . Because of the big impedance of NMOS 120, 121 compared to the impedance of PMOS 130, 131 the gate voltage at the gate of bypass transistor NMOS 160, 161 increases very quickly so that this transistor changes very quickly to the conducting state. In this way a low impedance path to V S s i installed when the voltage U70 is close to V DD . The bypass and sense circuit to V ss can be associated with an ideal switch that switches on as soon as U70 approximates V DD . The pull-up bypass and sense circuit consists of NMOS 140, 141 and PMOS 150, 151 as sense path and PMOS 170, 171 as bypass path. In the bypass path, the drain of PMOS transistor 170, 171 is connected with the output 70, 71 of said first transmission gate FT 0 , FTi and the source is connected with power supply voltage level V C c. In the sense path the source of the PMOS transistor 150, 151 is connected to power supply voltage level V C c an d the source of the NMOS transistor 140, 141 is connected to an output 70, 71 of said first transmission gate FTo, Ti and the drains of the PMOS transistor 150, 151 and the NMOS transistor 140, 141 are connected to each other. The gate of the PMOS transistor 170, 171 is connected with the drains of the PMOS and NMOS transistors of the sense path. The bypass and sense circuit works in an analogue way for undervoltage. Measurements on real chips prove that a subthreshold current via closed FTQ can occur also for valid input voltages V S s<UKV DD dependent on the voltage drop between drain and source of FTo- If this voltage drop is significant leakage is likely to occur due to the fact that the V DD level in the chip (and at the gate of FTo) is a little bit less than the V DD level applied from externally and due to the big width of FTQ, which is necessary to achieve a small impedance if the input is active ADC input channel. The proposed bypass and sense circuits keep the voltage drop on FTQ as small as possible and thus limit the subthreshold current into the pad. The reason is that both bypass and sense circuits are switched off for potentials U70 in the range 0.35V DD -V THn <U70<0.65V DD +|V THp | , i.e. currents via FTQ can only flow if one of the conditions U70>0.65V DD +|V TH p| or U70<0.35V DD -V THn is fulfilled. A small pad input leakage current is an important quality criteria for the 10 circuit of an integrated circuit. Of course, each of the embodiments according to Figs. 1 to 4 may comprise not only two but a plurality of input channels and each channel may have the pull-up and/or pull-down circuits and the second transmission gates as described above. An ADC circuit according to the invention comprises a multiplexer circuit according to the embodiments of Figs. 1 to 4 where the output voltage U ouτ of the multiplexer is the input voltage for the ADC. The accuracy of such an ADC can be as good as without over/undervoltage, i.e. the over/undervoltage has no influence to the conversion result (e.g. in case of an 8-bit ADC the accuracy is +/-2 LSB with or without over/undervoltage) .

Claims: C L A I M S 1. Multiplexer circuit comprising at least two input channels (IN 0 , INi) and an output channel (2) , each input channel (IN 0 , INi) comprising a first transmission gate (FT 0 , FTi) which can be switched on by a select signal (SELECTQ, SELECTQ; SELECTi, SELECTi) for connecting the input channel (INQ, INi) to the output channel (2) , at least one of the input channels (INQ, INI) comprising a bypass circuit (20, 21; 50, 51; 60, 61; 80, 81; 90, 91; 160, 161; 170, 171) for preventing a current flowing through the first transmission gate (FT 0 , FTi) from reaching the other input channel, and a second transmission gate (ST Q , STi) , characterized in that a control circuit is provided for controlling said bypass circuit. 2. Multiplexer circuit according to claim 1, wherein said control circuit controls said bypass circuit dependent upon a voltage in the input channel (INQ; INI) • 3. Multiplexer circuit according to claim 1, or 2 , wherein said control circuit comprises a sense circuit (120, 130; 121, 131; 140, 150; 141, 151; 100, 110; 101, 111) to control said bypass circuit (80, 90; 81, 91; 160, 161; 170, 171) by sensing a voltage in the input channel (INQ; INI) • 4. Multiplexer circuit according to one of claims 1 to 3 , wherein each input channel (INo, Ni) comprises a bypass circuit (20, 21; 50, 51; 60, 61; 80, 81; 90, 91; 160, 161; 170, 171) and a second transmission gate (STo, STi) . 5. Multiplexer circuit according to claim 4 , wherein the bypass circuit (20, 21; 50, 51; 60, 61) is switched on for an input channel (INo) which is not selected and is switched off for a selected input channel (INi) . 6. Multiplexer circuit according to one of claims 1 to 5, wherein said bypass circuit comprises a pull-down circuit (20, 21; 50, 51; 80, 81; 160, 161) reducing an input voltage for the second transmission gate (STo, STi) . 7. Multiplexer circuit according to one of claims 1 to 6, wherein said bypass circuit (20, 21) is controlled by said select signal (SELECT 0 , SELECTi) . 8. Multiplexer circuit according to one of claims 1 to 7 , wherein said bypass circuit (20, 21; 50, 51) is an NMOS transistor the gate of which is controlled by said select signal (SELECT 0 , SELECTi) , the drain of which is connected with an output of said first transmission gate (FTQ, FT I ) an< ^ the source of which is connected with ground potential (V ss ) . 9. Multiplexer circuit according to one of claims 1 to 8 , wherein said bypass circuit comprises a pull-up circuit (60, 61; 90, 91; 170, 171) increasing an input voltage for said second transmission gate (STQ, S I ) • 10. Multiplexer circuit according to claim 9, wherein said pull-up circuit (60, 61; 90, 91; 170, 171) is a PMOS transistor the drain of which is connected with an output of said first transmission gate (FTo, FTi) and the source of which is connected with a power supply voltage level (V C c) • 11. Multiplexer circuit according to claims 1 to 10, wherein said control circuit controls said bypass circuit by means of said select signal (SELECT 0 , SELECTQ; SELECT I , SELECTi) and an input voltage (Ui, U 2 ) applied to said input channel (INQ, INI). 12. Multiplexer circuit according to claims 8 to 11, wherein said control circuit controls said pull-up circuit (60, 61) and said pull-down circuit (50, 51) by means of said select signal (SELECT 0 , SELECT 0 ; SELECTi, SELECTi) and an input voltage (Ui, U 2 ) applied to said input channel (INQ, INi) . 13. Multiplexer circuit according to claim 12 , wherein said control circuit comprises a NAND gate (110, 111) the output of which is connected with the gate of said PMOS transistor (90, 91) and a NOR gate (100, 101) the output of which is connected with the gate of said NMOS transistor (80, 81) . 14. Multiplexer circuit according to claim 13, wherein said NAND gate receives the input voltage and the inverted select signal (SELECT 0 , SELECTi) and said NOR gate receives the input voltage and the select signal (SELECTQ, SELECTI) • 15. Multiplexer circuit according to one of claims 2 to 10, wherein said sense circuit (120, 130; 121, 131; 140, 150; 141 151) is formed so as to sense a voltage in the input channel (INo, I i) at the input of said first transmission gate (FTQ, FTI) or between said first transmission gate (FTQ, FTI) and said second transmission gate (STo, STi) . 16. Multiplexer circuit according to claim 15, wherein a pull-down bypass circuit is formed of a NMOS transistor (160; 161) the drain of which is connected with an output (70, 71) of said first transmission gate (FTQ, FTI) and the source of which is connected with the ground level (V ss ) and wherein said sense circuit is formed of a PMOS transistor (130; 131) and an NMOS transistor (120; 121) in series the source of the NMOS transistor (120; 121) being connected to ground level (V S s) and the source of PMOS transistor (130; 131) being connected to an output (70, 71) of said first transmission gate (FTO, FTI) and wherein the drains of said PMOS transistor (130; 131) and said NMOS transistor (120; 121) are connected to each other and to the gate of the NMOS bypass transistor (160; 161) . 17. Multiplexer circuit according to claim 15 or 16, wherein said pull up bypass circuit is formed of a PMOS transistor (170; 171) the drain of which is connected with an output (70; 71) of said first transmission gate (FTQ, FTI) and the source of which is connected with power supply voltage level (V C c) and wherein said sense circuit is formed of a PMOS transistor (150; 151) and an NMOS transistor (140; 141) in series the source of the PMOS transistor (150; 151) being connected to power supply voltage level (V cc ) and the source of the NMOS transistor (140; 141) being connected to an output (70; 71) of said first transmission gate (FT 0 , FTi) and wherein the drains of the PMOS transistor (150; 151) and the NMOS transistor (140; 141) are connected to each other and to the gate of the PMOS bypass transistor (170, 171) . 18. Analogue-to-digital converter comprising a multiplexer circuit according to one of claims 1 to 17.

Inventors: GOTTSCHALK CHRISTOPH, KOHN RUEDIGER, SEIFERT MARTIN, GOTTSCHALK, CHRISTOPH, KOHN, RUEDIGER, SEIFERT, MARTIN
Applicants: GOTTSCHALK CHRISTOPH, KOHN RUEDIGER, MITSUBISHI SEMICONDUCTOR EUROP, SEIFERT MARTIN, GOTTSCHALK, CHRISTOPH, KOHN, RUEDIGER, MITSUBISHI SEMICONDUCTOR EUROPE GMBH, SEIFERT, MARTIN
Application year: 1999
Main classification: H03K17
IPC codes: H03K17