Nonvolatile memory device, in particular of flash type

Abstract: The memory device (21) has hierarchical sector decoding (24, 25). A plurality of groups of supply lines (28-32) is provided, one for each sector row, extending parallel to the sector rows. A plurality of switching stages (35) are each connected between a respective sector (15) and a respective group of supply lines (28-32); the switching stages (35) connected to sectors (15) arranged on a same column are controlled by same control signals (S0, S1) supplied on control lines (40) extending parallel to the columns of sectors. For biasing the sectors, modification voltages (NW, SB, V NEG ) are sent to at least one selected group of biasing lines (28-32), and control signals (SO, S1) are sent to the switching stages connected to a selected sector column.

Description: The present invention regards a nonvolatile memory device, in particular of flash type. As is known, the increasing demand for high density memories has led to the design of nonvolatile memory structures having an increasingly compact architecture. For this reason, nonvolatile memories that store information in binary format in floating gate memory cells are increasingly widespread. Figure 1 shows, for example, the structure of a flash memory cell 1 which has a floating gate region 2 and a control gate region 3 overlying a P-type substrate 4, where an N-type source region 5 and an N-type drain region 6 are integrated. For storing information, electric charges are injected from the substrate 4 into the floating gate region 2 (programming operations), so varying the threshold of the memory cell, i.e., the voltage to be applied between the source region 5 and the control gate region 3 to obtain turning-on of the memory cell 1 and conduction of electric current between the source region 5 and the drain region 6. The read operation detects the conductive characteristic of the cells, converting it into information. The operation of removing electric charge stored in the floating gate region 2, referred to as "erasing", is carried out differently according to the memory type. In particular, in high compactness flash memories, the source regions of the cells of one part of the memory are connected together and are erased simultaneously by biasing the source region 5 and possibly also the substrate 4 with high positive voltages (typically, of between +5 and +8 V). The portions of memory in which the cells have source regions connected together are called "sectors". Figure 2 shows the structure of a memory cell 1 formed in a triple well. As may be noted, the P-type substrate 4 houses an N-type external well 10, which in turn houses a P-type isolated well 11 (constituting the body region), where the source region 5 and drain region 6 are housed. In Figure 3, the memory cells 1 belonging to a same sector are all housed in the same isolated well 11, and the cells of two sectors 15.0 and 15.1 are housed in two separate isolated wells, 11.0 and 11.1, and two separate external wells, 10.0 and 10.1. The division of the memory array into a number of sectors and the size of these sectors, which yields the resolution of the erasing operation, depend upon the specific needs of the applications. It is evident that the higher the memory density, the greater the likelihood of having to divide the array into a large number of sectors, which are each to be erased separately. In flash memories of the multilevel type (in which each memory cell stores more than one bit), the information density per unit area grows further, just as the need to have sufficiently subdivided sectors. The division into sectors is conditioned not only by the applications, but also by the process parameters (defectiveness and management of redundancy, as well as band-to-band tunneling current if the source region 5 and the isolated well 11 are at different erasing potentials). For example, each sector may comprise between 1 and 2 Mb; in some applications, divisions into non-uniform sectors are necessary, and sectors of very small size are required (for example, 16 kb or 32 kb) to contain the bootstrap code of the microprocessor and the parameters for the bootstrap separately. Inside a flash memory, regardless of how the sectors are organized (by rows or by columns), it is essential to bias the source regions, and possibly the isolated wells 11 of the cells, as well as the respective external wells 10, in an independent way. In addition, also during programming it may be advantageous to bias the isolated well 11 of the selected sector; in fact, by biasing the isolated well 11 at a negative potential (ranging between -1 and -2 V), it is possible to obtain better performance in terms of programming speed. For instance, a triple well flash cell, as shown in Figure 2, can be biased in the way illustrated in the following Table I, using the body terminal B for the isolated well 11 and the N-well terminal W for the external well 10. OPERATION S B W Reading 0 V 0 V V CC Programming 0 V -1/-2 V V CC Erasing 5-8 V 5-8 V 5-8 V It is therefore of fundamental importance to control each sector independently of the others to prevent undesired electrical stresses on the source terminal ("source stress" or "soft erasing"). In case of large size memory arrays, this involves a considerable complexity for controlling the sectors. In fact, for each sector it is necessary to provide MOS switches to connect it to the high voltage during erasing, to connect its terminals to ground during reading, and to bias the isolated well 11 at a negative voltage during programming. For example, in case of a 64 Mb flash memory divided into 64 equal sectors of 1 Mb each, if each sector has an own enabling signal and own signals for managing the operation being carried out (programming, reading, erasing, erasing and programming verify), the following signals and switches are necessary (see in particular Figure 4): 64 sector enabling signals S-EN, one for each sector, to be decoded starting from the address vector defining them uniquely and to be supplied to a respective sector switch. Since the memory cells are arranged in a matrix (i.e., in rows and columns), the sector enabling signals must traverse areas adjacent to the rows and columns of the memory banks; at least two control signals CS, one for erasing, which controls the positive erasing biasing, and one for programming, which controls the negative biasing of the isolated well 11. Both inactive signals could represent the read condition (source terminal S and body terminal B to ground); sector switches (formed by enabling transistors or pass transistors of the PMOS and NMOS types), both positive and negative, for biasing the source terminal S, the body terminal B and the N-type well W of each sector; a control logic for each sector, which decodes the signals to be applied to the sector switches according to the operating mode; high voltage analog switches, which enable the sector switches (both PMOS and NMOS) to be turned off in presence of voltages having a higher value than the supply voltage. In fact, as is known, positive voltages greater than the supply voltage are advantageously transferred by PMOS transistors, and negative voltages are advantageously transferred by NMOS transistors. In Figure 4, the sector switches PT, the control logic LOGIC, and the analog high voltage switches HVS of each sector are gathered together in a single block 16 for simplicity. Figures 5 and 6 show, respectively, possible implementations of high voltage analog switches of positive and negative type wherein IN represents the input signal, O and ON represent the output signal and its inverted signal, respectively; V dd is the supply voltage; V pp is a positive voltage higher than the supply voltage, for example the programming voltage; and V NEG is a negative voltage, for example the body voltage during programming. It is evident that this organization requires a high use of the area necessary, above all, for arranging the interconnections of the enabling signals and the high voltage switches HVS. Even if the biasing terminals of the sectors were brought to another point of the memory device and the decoding control logic circuits were grouped together there, a considerable space would be required to implement the signal buses. In addition, these buses could not be managed with metal lines of minimal width, in that the current flowing during charging and discharging of the terminals is a few mA. In the example cited above of 64 sectors with three terminals, i.e., one body terminal, one N-well terminal, and one source terminal, for each sector three P-channel pass transistors (and corresponding positive switches) should be implemented to bring onto each terminal the high positive voltage required for erasing, and an N-channel pass transistor (and corresponding negative switch) for the negative body voltage. Consequently, 256 switching circuits would be required, which would occupy a large amount of space given that each one of them requires from 6 to 10 MOS transistors. EP-A-0 622 806 discloses a nonvolatile memory device according to the preamble of claim 1. US-A-5 818 764 describes a circuit for supplying a negative erasing voltage on the wordlines of selected block of memory cells. The aim of the invention is thus to provide an architecture enabling biasing of the sectors with a smaller area bulk. According to the present invention, a nonvolatile memory device, in particular of the flash type, and a corresponding biasing method are provided, as defined in Claim 1 and Claim 8, respectively. In practice, the invention is based upon the possibility of selecting the sectors in a unique way, using high voltage pass lines and enabling signals appropriately shared by rows and columns of sectors, for example, by getting the rows of sectors to share the high voltage lines, and the columns of sectors to share the enabling signals. For a better understanding the present invention, a preferred embodiment thereof is now described, purely to provide a non-limiting example, with reference to the attached drawings, wherein: Figure 1 shows the structure of a flash type memory cell formed in a substrate; Figure 2 shows the structure of a flash type memory cell formed in triple well; Figure 3 shows the implementation of two different sectors formed in the triple well; Figure 4 presents the organization of a memory device of a known type; Figures 5 and 6 show the electrical diagram of high voltage switches of positive and negative type, respectively; Figure 7 shows the architecture according to the present invention; Figures 8-10 show in greater detail part of the architecture of Figure 7 in three different operating conditions; and Figure 11 shows the electrical diagram of a CMOS switch. Figure 7 shows a memory device 20 comprising a memory array 21 formed by a plurality of sectors 15 arranged in rows and columns of sectors. Each sector 15 comprises, in a way not shown, a group of memory cells 1 physically arranged adjacent to one another and having a common terminal (in the embodiment shown, the source terminal; in addition, the memory cells are made in a triple well structure and each sector has an own isolated well region 11 and an own isolated well region 10, as shown in Figure 3). In Figure 7 the position of each sector 15 is identified by the row and by the column to which the sector 15 belongs. A row decoder 24 is associated to each sector row, and a column decoder 25 associated to each sector column. Each row decoder 24 receives a respective sector row enabling signal X<0>, X<1>, ..., X<m>, and each column decoder 25 receives a respective sector column enabling signal Y<0>, Y<1>, ..., Y<n>. In practice, sector row enabling signal X<0> enables the row decoder 24 connected to sectors 0-n (first sector row); sector row enabling signal X<1> enables the row decoder 24 connected to sectors (n+1)-2n, ... (second sector row); sector column enabling signal Y<0> enables the column decoder 25 connected to sectors 0, (n + 1), ...; sector column enabling signal Y<1> enables the column decoder 25 connected to sectors 1, (n + 2), ..., (first sector column), and so forth, so that decoding of sector row and column enabling signals X and Y is sufficient to identify a given sector uniquely. The operations of modifying a selected sector (erasing and programming) require the application of voltages different from the supply voltage and from the ground level to the terminals of the selected sector. These modification voltages may be supplied through biasing lines arranged parallel to first alignment lines, for example, to sector rows. Appropriate high voltage switches supply the high voltage only to the selected sector row. In practice, the sector row enabling signals X activate the high voltage switches. In this case, the sector column enabling signals Y may be used to activate the pass transistors between the high voltage line and the respective selected sector column, or else, the pass transistors connected to the sectors aligned along a second selected alignment line. In this way, only the sector that has the horizontal biasing line actually biased at the modification levels will be able to be written or erased. Obviously, also dual implementation is possible, whereby the sector column enabling signals supply the high voltage to the selected sector column and the sector row enabling signals determine biasing of the selected sector. In practice, a hierarchical sector decoding is obtained. A specific example of selection of a sector 15 with the hierarchical sector decoding described above in reading, erasing and programming modes will now be described with reference to Figures 8-10 for the simplified case in which the memory array 21 comprises only four sectors 15.0, 15.1, 15.2, and 15.3, arranged in two sector rows and two sector columns. With reference to Figure 8, for each sector row, a high voltage switch stage (HVS stages 27.0 and 27.1) is provided, which receives modification voltages V E , V B , necessary during erasing and programming; a two-bit mode signal P/E, which specifies the operation to be carried out; and an addressing signal X<0> and, respectively, X<1>. Each HVS stage 27.0, 27.1, which is moreover connected to an input supply line 33 at V dd and to a ground line 34, has five outputs connected to as many biasing lines 28.0-32.0, respectively 28.1-32.1 (hereinafter also indicated simply as biasing lines 28-32, where it is not necessary to specify the associated sector row). In detail, on NW lines 28, for positive modification of N-type wells, a voltage NW is supplied; on SB line 29, for positive modification of source and body, a voltage SB is supplied; on sector supply lines 30 the supply voltage V dd is supplied; the ground lines 31 are set at 0 V; and on NB lines 32, for negative modification of body, a voltage V NEG is supplied. Each sector 15.0-15.3, of which only the source biasing terminal S, the body biasing terminal B, and the isolated well biasing terminal W are shown, is connected to the biasing lines 28-32 through a respective sector switching stage 35.0-35.3 comprising three pairs of complementary switches 36a, 36b; 37a, 37b; 38a, 38b, made up of pass transistors as discussed hereinafter. In detail, in all sector switching stages 35.0-35.3, the switch 36a is connected between the respective source terminal S and the respective SB line 29; the switch 36b is connected between the respective source terminal S and the respective ground line 31; the switch 37a is connected between the respective body terminal B and the respective SB line 29; the switch 37b is connected between the respective body terminal B and the respective NB line 32; the switch 38a is connected between the respective N-well terminal W and the respective NW line 28; and the switch 38b is connected between the respective N-well terminal W and the respective sector supply line 30. The sector switching stages 3510-35.3 are made topologically near the respective sector 15.0-15.3. The pairs of complementary switches 36a, 36b; 37a, 37b; 38a, 38b receive respective commands from logic control stages 39.0 and 39.1 common for the sector columns. In detail, the logic control stage 39.0 sends control signals S0 to the sector switches 35.0 and 35.2 corresponding to sectors 15.0 and 15.2 with address Y<0>, and the control logic stage 39.1 sends control signals S1 to the sector switching stages 35.1 and 35.3 corresponding to sectors 15.1 and 15.3 with address Y<1>. The control signals S0, S1 sent on six lines 40.0, 40,1 for each control logic stage 39.0, 39.1 supply complementary pairs of signals, so that the switches 36a, 37a and 38a always receive signals that are complementary to the switches 36b, 37b and 38b, and are therefore closed alternately to the latter switches. The control logic stages 39.0, 39.1 receive sector column address signals Y<0> and, respectively, Y<1>, the mode signal P/E, and the modification voltages V E and V B (supplied also to the HVS stages 27.0 and 27.1) and are connected to the input supply line 33 at V dd and the ground line 34, so that the control signals S0 and S1 sent to the sector switching stages 35.0-35.3 have voltage levels corresponding to the voltages present on the biasing lines 28-32. The HVS stages 27.0 and 27.1, which in practice form the row decoders 24 of Figure 7, have the function of suitably transferring the modification voltages V E and V B , the supply voltage V dd , and the ground potential to the biasing lines 28-32, according to the selected sector row (and hence according to the logic value of the address signals X<0> and X<1>) and according to the operation to be performed (and hence according to the value of the mode signal P/E). In particular, the HVS stages 27.0 and 27.1 supply the modification voltages V E and V B to only the biasing lines 28, 29 and 32 connected to the sector which each time is to be erased or written, as explained hereinafter, and comprise high voltage analog switches of the type shown in Figures 5 and 6 according to the polarity of the voltage to be transferred, and an appropriate logic for controlling the high voltage analog switches themselves. The control logic stages 39.0 and 39.1, which in practice form the column decoders 25 of Figure 7, have the function of suitably controlling the sector switching stages 35.0-35.3 according to the addressed sector column (and hence according to the logic value of the address signals Y<0> and Y<1>) and according to the operation to be performed (and hence according to the value of the mode signal P/E) so as to suitably connect the biasing lines 28-32 to the switches 36a-38b, as explained in detail hereinafter, assuming that a read, erase, or write operation is to be performed, with reference to Figures 8, 9 and 10, respectively. In the same way as for the HVS stages, the control logic stages 39 comprise high voltage analog switches and an appropriate control logic. In all the operations, the sector supply line 30 is always set at V dd , and the ground line 31 is always connected to 0 V. Reading (Figure 8) During reading all the sectors 15.0-15.3 receive identical biasing voltages for biasing the terminals S, B, N. Consequently, the NW lines 28.0, 28.1 are here biased to V dd (NW = V dd ); the SB lines 29.0, 29.1 are grounded (SB = 0 V); and the NB lines 32.0, 32.1 are grounded (V NEG = 0 V). In addition, the control logic stages 39.0 and 39.1 generate control signals such as to keep all switches 36a, 37a and 38a open and to keep all switches 36b, 37b and 38b closed. Consequently, all the sectors 15.0-15.1 have their source terminals S connected to ground, their isolated well terminals B set at 0 V, and their N-well terminals W set at V dd . Erasing of sector 15.0 having addresses X<0> and Y<0> (Figure 9) The HVS stage 27.0 (corresponding to the first sector row) connects the NW line 28.0 and the SB line 29.0 to positive erasing voltage V E (NW, SB = V E = 5.8 V), and grounds the NB line 32.0 (V NEG = 0 V) . The HVS stage 27.1 (corresponding to the second sector row) connects the NW line 28.1 to the supply voltage V dd , and grounds the SB line 29.1 and the NB line 32.1 SB, V NEG = 0 V. In addition, the control logic stage 39.0 generates control signals such as to keep switches 36a, 37a and 38a closed and to keep switches 36b, 37b and 38b of sector switching stages 35.0 and 35.2 open, and the control logic stage 39.1 generates control signals such as to keep switches 36b, 37b and 38b closed, and to keep switches 36a, 37a and 38a of sector switching stages 35.1 and 35.3 open. Consequently, as is shown in figure 9 by thick lines which indicate the modification voltage lines, only the source terminal S, the isolated well terminal B and the N-well terminal W of the sector 15.0 receive the positive erasing voltage V E . The sector 15.1, associated to the same biasing lines 28.0-30.0 of the addressed sector 15.0, has its source terminal S and its N-well terminal W grounded, and its isolated well terminal B set at V dd . The sector switching stage 35.2 of sector 15.2 is controlled by the same control signals as the sector switching stage 35.0 associated to the addressed sector 15.0; thus sector 15.2 has its source terminal S, its isolated well terminal B, and its N-well terminal W biased as sector 15.1, given the voltages present on the biasing lines 28.1-29.1. The sector 15.3, which is neither arranged on the same row nor on the same column as the addressed sector 15.0, is biased as sectors 15.1 and 15.2. In this way, only the sector that is to be erased receives the modification voltages. Programming of sector 15.0 having addresses X<0> and Y<0> (Figure 10) The HVS stage 27.0 (corresponding to the first sector row) connects the NW line 28.0 to the supply voltage (NW = V dd ), the SB line 29.0 to ground (SB = 0V), and the NB line 32.0 to a negative potential (V NEG = -1 V) . The HVS stage 27.1 (corresponding to the second sector row) connects the NW line 28.1 to the supply voltage (NW = V dd ), and grounds the SB line 29.1 and the NB line 32.1 (SB, V NEG = 0 V). In addition, the control logic stage 39.0 generates control signals such as to keep switches 36b, 37b and 38b closed and to keep switches 36a, 37a and 38a of sector switching stages 35.0 and 35.2 open, and the control logic 39.1 generates control signals such as to keep switches 36b, 37a and 38b closed, and to keep switches 36a, 37b and 38a of sector switching stages 35.1 and 35.3 open. Consequently, as is shown in figure 10 by thick lines which indicate the modification voltage lines, only the isolated well terminal B of the sector 15.0 receives the negative voltage V NEG . The sector 15.1, associated to the same NB line 32.0 as the addressed sector 15.0, has its isolated well terminal B set at 0 V in order to prevent stresses. The sector switching stage 35.2 of sector 15.2 is controlled by the same control signals as the sector switching stage 35.0 associated to the addressed sector 15.0; thus sector 15.2 has its isolated well terminal B grounded, given the voltage present on the NB line 32.1. The sector 15.3, which is neither arranged on the same row nor on the same column as the addressed sector 15.0, is biased as sectors 15.1 and 15.2. In this way, only the sector that contains the cell to be programmed receives the negative voltage on the isolated well terminal B. In Figures 8-10, the switches 36b (which are always connected between ground and the source terminal) and the switches 38b (which are always connected between the supply and the N-well terminal W) can be made using pass transistors of an appropriate type (NMOS and, respectively, PMOS); instead, the switches 36a, 37a, 37b, and 38a are arranged between lines biased at different voltages according to whether the respective sector is or is not selected (for example, with reference to Fig. 9, during erasing switch 36a of sector switching stage 35.0 must transfer a high positive voltage V E , whilst switch 36a of sector switching stage 35.2 must transfer the ground potential). The switches 36a, 37a, 37b, and 38a are thus advantageously made as CMOS pass gates 45, as shown in Figure 11. In detail, the sector switch 45 is arranged between an input line 46 and an output line 47 to transfer the potential on the input line 46 to the output line 47. The sector switch 45 comprises an NMOS transistor 48 and a PMOS transistor 49 having first terminals connected together and to the input line 46, and second terminals connected together and to the output line 47. The gate terminal of NMOS transistor 48 is connected to a control input 50 fed with a control signal C switchable between two logic levels corresponding to the voltage values that may occur on the input line 47 (for example, in the case of the switch 36a considered previously, the control signal C is switchable between V E and 0 V). The control input 50 is moreover connected to the gate terminal of the PMOS transistor 49 via an inverter 51 so as to receive the complementary signal CN. The sector switch 45 is able to transfer the voltage present on the input line 46 to the output line 47 in the presence of a high logic level of the control signal C. In fact, when on the input line 46 a high modification voltage is present (V E , in the case considered above), and the control signal C also has the value of V E , the NMOS transistor 48 is off, but the PMOS transistor 49 (receiving the complementary signal CN at 0 V) is on; instead, when the ground potential (0 V) is present on the input line 46, the NMOS transistor 48 is on. On the other hand, when the switch 45 must be open, notwithstanding the presence of the high voltage on the input line 46, the signal C is low and keeps the NMOS transistor 48 off, and the complementary signal CN is set at the high modification voltage, so maintaining a zero voltage drop between the source terminal and gate terminal of the PMOS transistor 49, which is thus certainly off. The advantages of the memory device described are the following: first, it reduces the number of decoding components, in particular the number of high voltage switches. In fact, in the above considered case of 64 sectors, arranged in eight rows and eight columns, the present solution requires 8 x 2 = 16 positive switches and 8 negative switches inside the HVS stages (27.0 and 27.1 in Figures 8-10) to control the pass transistors that connect the V E /V B input lines to the biasing lines (28.0, 28.1, 29.0, 29.1, 32.0, and 32.1 in the example of Figures 8-10); 24 high positive voltage switches and 8 negative switches in the control logic stages (39.0 and 39.1 in Figures 8-10) for the signals (C, CN in Figure 11) for controlling the switches 36a, 36b, 37a, 37b, 38a, and 38b. Altogether, therefore, the present solution requires 56 high voltage switches, as compared to 256 switches necessary in the case discussed previously according to the prior art. In practice, a bulk reduction and an architectural simplification are obtained as compared to the known solutions. This has a considerable impact on the costs of the device, in particular in the case of large size memories. A further saving is obtained by virtue of a more compact layout of the biasing lines and the generation of a lower number of control signals. This is particularly useful in the case of triple well CMOS technologies, where three global terminals per sector must be controlled instead of one global terminal as in single well arrays, without the invention being limited to the case of triple well devices. The present solution does not require the availability of special signals for addressing the sector rows and columns (signals X and Y in Figures 7-10). In fact, in the hierarchical management of cell rows and columns of a memory array of a known type, signals are already available for selectively enabling the rows and the columns of the array. In particular, row decoder circuits and column decoder circuits are already present, which, starting from the bit vector constituting the address of a cell to be selected, suitably bias the rows and columns of the array. Usually, therefore (for example at the pre-decoding level), logic signals are already available, which identify the group to which the row and the column of the memory cell addressed belong, and these groups generally correspond to adjacent columns or rows, and hence can be gathered together in such a way that each group of columns or rows of cells refers to a same sector column or row. Instead, the partial re-use of the decoding signals reduces the number of logic circuits to be implemented. Finally, it is clear that numerous modifications and variations may be made to the memory device described and illustrated herein, all falling within the scope of the invention, as defined in the attached claims.

Claims: A memory device (21) comprising: a plurality of memory sectors (15) each comprising a plurality of memory cells (1) having source regions (5) connected to a common source terminal (S), said memory sectors (15) being mutually aligned along a plurality of first alignment lines parallel to one another and along a plurality of second alignment lines parallel to one another and perpendicular to said first alignment lines; a plurality of switching stages (35) each connected to a respective memory sector (15) and each having a respective control input; a plurality of groups of biasing lines (28-32) extending parallel to said first alignment lines, each group of biasing lines being connected to switching stages (35) connected to memory sectors (15) mutually aligned along a same of said first alignment lines; and a plurality of groups of control lines (40) extending parallel to said second alignment lines; each group of control lines being connected to said control inputs of switching stages (35) connected to memory sectors (15) mutually aligned along a same of said second alignment lines, characterized in that each said memory sector (15.0, 15.1) is formed in an own isolated well region (11.0, 11.1) isolated from adjacent isolated well regions through a triple well structure including an own external well region (10.0, 10.1) accommodating said own isolated well region, each said memory sector comprising an isolated well terminal (B) connected to said own isolated well region, and an external well terminal(W) connected to said own external well region, in that each of said groups of biasing lines (28-32) comprises at least a source and body modification voltage line (29), a well voltage modification line (28), and a negative biasing line (32); said source and body modification voltage line (29) being selectively connectable to said common source terminal (S) and to said isolated well terminal (B) through respective sector switches (36a, 37a) belonging to a respective switching stage (35), said well voltage modification line (28) being selectively connectable to said external well terminal (W) through a respective sector switch (38a) belonging to a respective switching stage (35); and said negative biasing line (32) being selectively connectable to said isolated well terminal (B) through respective sector switches (37b) belonging to a respective switching stage (35). The memory device according to Claim 1, characterized in that said first alignment lines are rows and said second alignment lines are columns. The memory device according to Claim 1 or Claim 2, characterized in that it comprises a plurality of decoding stages (27), one for each of said first alignment lines, said decoding stages (27) being connected between reference potential lines (33, 34, VE/VB) and a respective group of biasing lines (28-32), and a plurality of control logic circuits (39), one for each of said second alignment lines, said control logic circuits being connected each to a respective group of control lines (40). The memory device according to Claim 3, characterized in that said decoding stages (27) each have a respective address input (X) and a respective mode input (P/E) selectively connecting said reference potential lines to said respective group of biasing lines (33, 34, VE/VB) according to signals (X, P/E) present on said respective address and mode inputs, and in that said control logic circuits (39) each have a respective address input (Y) and a respective mode input (P/E), and are connected to said reference potential lines (33, 34, VE/VB) selectively connecting said reference potential lines to said respective group of control lines (40) according to signals (Y, P/E) present on said respective address and mode inputs. The memory device according to Claim 3 or Claim 4, characterized in that said switching stages (35) comprise pass transistors (36, 37, 38; 45). The memory device according to Claim 5, characterized in that at least some of said pass transistors (45) are CMOS pass gates. The memory device according to Claim 1, characterized in that said sector switches (36, 37, 38) comprise pairs of complementary switches (36a, 36b; 37a, 37b; 38a, 38b). In a memory device according to any of claims 1-7, a biasing method characterized in that it comprises the steps of: sending modification voltages (NW, SB, VNEG) to at least one selected group of said groups of biasing lines (28-32), and connecting memory sectors (15) aligned along at least one selected line of said second alignment lines to said groups of biasing lines (28) wherein said step of sending modification voltages comprises, selectively, at least one of the steps of: sending a source modification voltage (SB) to said common source terminal (S); sending a body modification voltage (SB; VNEG) to said isolated well terminal (B); and sending a well modification voltage (NW) to said external well terminal (W). The method according to Claim 8, characterized in that it comprises the step of sending de-selection voltages to non-selected groups of said groups of biasing lines. The method according to Claim 8 or Claim 9, characterized in that said first alignment lines are rows, and said second alignment lines are columns.

Inventors: CAMPARDO GIOVANNI, MICHELONI RINO, ZAMMATTIO MATTEO, CAMPARDO, GIOVANNI, MICHELONI, RINO, ZAMMATTIO, MATTEO
Applicants: ST MICROELECTRONICS SRL, STMICROELECTRONICS S.R.L.
Application year: 1999
Main classification: G11C16
IPC codes: G11C16, G11C8