Differential line driver

Abstract: when a driver circuit unit issues data to a receiver through a transmission line, the unit perform a matching operation to the characteristic impedance of the transmission line so that the logic level of an input signal received by the receiver is properly controlled. The unit comprises: a first push pull circuit (2) for issuing an output signal to an output terminal (5A) through resistors (2B, 2C) when transmitted data is issued to an input terminal (1A), the output signal having its logic level correspond to the transmitted data; a second push pull circuit (3) for issuing an negative-phase output signal to an output terminal (5B) through resistors (3B, 3C) when negative-phase data, which is one reversed in phase of the above transmitted data, is issued to an input terminal (1B), the negative-phase output signal having its logic level correspond to the negative-phase data; and, a resistor (4) connected between the output terminal (5A) and the output terminal (5B).

Description: The present invention relates to a driver circuit unit, and more particularly to a driver circuit unit for issuing data to a transmission line. A so-called driver circuit unit functions to issue transmitted data having been received therein to a receiver through a transmission line. Inputted to the above driver circuit unit as input signals are: positive-phase data which is the above mentioned transmitted data having been received in the driver circuit unit; and negative-phase data which is one reversed in phase of the positive-phase data. Further, issued from the above driver circuit unit to the receiver are: an output signal corresponding to the above positive-phase data; and a negative-phase output signal corresponding to the above one reversed in phase of the positive-phase data. More specifically, as shown in Fig. 4, inputted to a conventional driver circuit 101 are: positive-phase data 201 which is the above-mentioned transmitted data and a negative-phase data 202. For example, as shown in Fig. 5, when the positive-phase data 201 is constructed of a series of signals with logic levels H and L, i.e., a series of signals with high level (H), high level (H), low level (L), high level (H), low level (L) and low level (L) sequentially arranged in a row in the above-mentioned order, the negative-phase data 202 is constructed of a series of the negative-phase ones of the signals with the above-mentioned logic levels. In other words, the negative-phase data 202 is constructed of a series of low level (L), low level (L), high level (H), low level (L), high level (H) and high level (H) sequentially arranged in a row in the above-mentioned order, as shown in Fig. 5. In operation, as shown in Fig. 4, when the conventional driver circuit 101 receives the positive-phase data 201 together with the negative-phase data 202, a pair of switches 101A, 101B perform their switching operations in accordance with these two data 201, 202. In other words, in the driver circuit 101, when the positive-phase data 201 is in the high level, a resistor 101c is connected with a power supply line(+). In contrast with this, when the positive-phase data 201 is in the low level, the resistor 101C is connected to the ground. Further, in the driver circuit 101, when the negative-phase data 202 is in the low level, a resistor 101D is connected to the ground. In contrast with this, when the negative-phase data 202 is in the high level, the resistor 101D is connected with the power supply line. As a result, when the above-mentioned transmitted data is in the high level, the resistor 101C has a voltage equal to that V DD of the power supply line, and the resistor 101D is held at the ground level in voltage. On the other hand, when the transmitted data is in the low level, the resistor 101C is connected to the ground, and the resistor 101D is held at the voltage V DD of the power supply line. The resistors 101C and 101D of the driver circuit 101 are connected with coaxial cables forming transmission lines 102 and 103, respectively. At this time, in the driver circuit 101, the positive-phase data 201 and the negative-phase data 202 are transmitted from the driver circuit 101 to the transmission lines 102 and 103, respectively, provided that the resistors 101C, 101D are used to have the impedance of the driver circuit 101 matched to that of each of the transmission lines 102 and 103. In a receiver 104 shown in Fig. 4, a signal produced between a pair of the transmission lines 102 and 103 is received in a series circuit of a pair of resistors 104A, 104B. A node N interposed between the resistors 104A, 104B is connected to the ground through a capacitor 104C. In operation, in the receiver 104, when the above-mentioned transmitted data is in the high level, an electric current flows in the direction of the arrow 104E through the series circuit of the resistors 104A, 104B. On the other hand, when the transmitted data is in the low level, the electric current flows in the direction of the arrow 104F through the above series circuit of the resistors 104A, 104B. As a result, an input signal 211 is produced at a node "P" located between the resistor 104A and the transmission line 102. On the other hand, another input signal 212 is produced at a node "Q" located between the resistor 104B and the transmission line 103. The thus produced input signals 211, 212 are inputted to a differential operation portion 104D. In this differential operation portion 104D, the electric current flowing in the direction of the arrow 104E produces a high level signal which is issued from the differential operation portion 104D. Also in this differential operation portion 104D, the electric current flowing in the direction of the arrow 104F produces a low level signal which is also issued from the differential operation portion 104D. This differential operation portion 104D is shown in Fig. 6. The differential operation portion 104D shown in Fig. 6 is constructed of a two-stage circuit which is provided with both a differential amplifier 110 and an inverter 120. As shown in Fig. 6, the differential amplifier 110 is constructed of: a plurality of P (i.e., Positive) type MOS (i.e., Metal Oxide Semiconductor) transistors 111, 112, 113; and, a pair of N (i.e., Negative) type MOS transistors 114, 115. On the other hand, the inverter 120 is constructed of a P type MOS transistor 121 and an N type MOS transistor 122. Both the MOS transistors 112, 113 of the differential amplifier 110 operate upon receipt of a constant electric current supplied from the MOS transistor 111. Inputted to the MOS transistor 112 through an input terminal 131 is an input signal 211 generated at the node "P" shown in Fig. 4. On the other hand, inputted to the other MOS transistor 113 through an input terminal 132 is an input signal 212 generated at the node "Q" shown in Fig. 4. In operation, when the input signal 211 inputted to the input terminal 131 is higher in level than the input signal inputted to the input terminal 132 (in other words, when the transmitted data mentioned above is in the high level), the MOS transistor 112 is turned OFF so as to be non-conductive, while the other MOS transistor 113 is turned ON so as to be conductive. Due to this, the constant electric current issued from the MOS transistor 111 is supplied, through the MOS transistor 113, to the MOS transistor 115 which serves as a resistor, so that a node "R", through which a drain of the MOS transistor 113 is connected with a drain of the MOS transistor 115, becomes the high level. When this node "R" becomes the high level, the MOS transistor 114 is turned ON so as to be conductive, so that a node "S" through which a drain of the MOS transistor 114 is connected with a drain of the MOS transistor 112 becomes the low level. When the node "S" becomes the low level, the MOS transistor 121 is turned ON so as to be conductive, while the MOS transistor 122 is turned OFF so as to be non-conductive. As a result, an output terminal 133, which forms a node trough which a drain of the MOS transistor 121 is connected with a drain of the MOS transistor 122, becomes the high level. In contrast with this, when the input signal 211 inputted to the input terminal 131 is lower in level than the other input signal 212 inputted to the input terminal 132 (in other words, when the transmitted data described in the above is in the low level), the MOS transistor 112 is turned ON so as to be conductive, while the other MOS transistor 113 is turned OFF so as to be non-conductive. Since the MOS transistor 112 is turned ON so as to be conductive while the other MOS transistor 113 is turned OFF so as to be non-conductive as described above, the node "R" becomes the low level so that the MOS transistor 114 is turned OFF so as to be non-conductive, whereby the other node "S" becomes the high level. When the node "S" becomes the high level, the MOS transistor 121 is turned OFF so as to be non-conductive and the other MOS transistor 122 is turned ON so as to be conductive. As a result, the output terminal 133 becomes the low level. As described above, the differential operation portion 104D reproduces the above-described transmitted data of the driver circuit 101 to issue it therefrom. Problems to be solved by the present invention are inherent in the related art as follows: namely, the input signals 211 and 212, both of which are inputted to the differential operation portion 104D of the receiver 104 shown in Fig. 4, are voltages developed at the nodes P and Q, respectively. Consequently, when the logic levels representing the high and the low level of these input signals 211, 212 vary, the following problems occur. For example, when the logic levels of the input signals 211, 212 are low, a voltage developed across the gate-source of each of the MOS transistors 112, 113 shown in Fig. 6 becomes large, which makes it possible for each of the MOS transistors 112, 113 to operate in a linear region. Consequently, in contrast with the ON and OFF operations in its saturation region, each of MOS transistors 112, 113 produces at a node "S" a signal with a level corresponding to the logic level of the input signal 211. In other words, produced at the node "S" in the above is a signal with a level intermediate between the high and the low signal levels produced in ordinary ON/OFF operations. Due to this, a malfunction often occurs in the inverter 120 in its inversion operation, which makes it substantially impossible for the receiver 104 to issue a signal corresponding to the above-mentioned transmitted data of the driver circuit 101. On the other hand, when the logic level of the input signal 211 is high, the source voltage of each of the MOS transistors 112, 113 becomes high. As a result, a voltage developed across the drain-source of the MOS transistor 111 shown in Fig. 6 becomes small, which makes it possible for the MOS transistor 111 to operate in a linear region. Consequently, an electric current passing through the MOS transistor 111 is reduced. Due to this, for example, the MOS transistor 113 is turned ON so as to be conductive, which causes the MOS transistor 114 to malfunction in its ON/OFF operations since a voltage developed at the node "R" is reduced due to reduction in current supplied from the MOS transistor 111, even though such voltage at the node "R" should be kept at a high level. A driver circuit according to the preamble of claim 1 is disclosed in EP-A-0 400 908. In view of the above, it is an object of the present invention to provide a driver circuit unit, which is capable of properly controlling in logic level an input signal received by a receiver in a condition in which the diver circuit unit performs a matching operation in impedance with respect to the characteristic impedance of a transmission line through which a piece of transmitted data is transmitted to the receiver. This object is achieved by a driver circuit as defined in claim 1; the remaining claims refer to advantageous developments of the invention. In the construction according to the invention, the first circuit has the output signal issued to the first output terminal through the first and third resistors. On the other hand, the second circuit has the negative-phase output signal issued to the second output terminal through the second and fourth resistors. Further, the adjusting resistor is connected between the first and the second output terminals. With the above construction, it is possible to perform a matching operation of its output impedance to the first transmission line by using the first and third resistors of the first circuit (or the fourth and second resistors of the second circuit) together with the adjusting resistor, and also possible to perform a matching operation of its output impedance to the second transmission line by using the fourth and second resistors of the second circuit (or the first and third resistors of the first circuit) together with the adjusting resistor. The above and further objects, advantages and features of the present invention will be more apparent from the following description taken in conjunction with the accompanying drawings in which: Fig. 1 is a circuit diagram of an embodiment of the driver circuit unit of the present invention; Fig. 2 is a circuit diagram of a circuit equivalent to the driver circuit unit of the present invention shown in Fig. 1; Fig. 3 is a circuit diagram of another circuit equivalent to the driver circuit unit of the present invention shown in Fig. 1; Fig. 4 is a circuit diagram of one of the conventional driver circuits; Fig. 5 is a schematic diagram of waveforms of the transmitted signals inputted to the conventional driver circuit unit shown in Fig. 4; and Fig. 6 is a circuit diagram of the conventional differential operation portion connected with the conventional driver circuit shown in Fig. 4. A preferred mode for carrying out the present invention will be described in detail using a plurality of embodiments of the present invention with reference to the accompanying drawings. Fig. 1 shows a circuit diagram of an embodiment of a driver circuit unit of the present invention. Shown in Fig. 2 is a circuit diagram of a circuit equivalent to the driver circuit unit of the present invention shown in Fig. 1. Fig. 3 shows a circuit diagram of another circuit equivalent to the driver circuit unit of the present invention shown in Fig. 1. The driver circuit unit of the present invention shown in Fig. 1 is used in place of the conventional driver circuit 101 shown in Fig. 4. As shown in Fig. 1, the driver circuit unit of the present invention is provided with: a first input terminal 1A and a second input terminal 1B; a first push-pull circuit 2 and a second push-pull circuit 3; an adjusting resistor 4; and a first output terminal 5A and a second output terminal 5B. In the driver unit of the present invention shown in Fig. 1: inputted to the first input terminal 1A is positive-phase data 201 (shown in Fig. 4); and inputted to the second input terminal 1B is negative-phase data 202 (shown in Fig. 4). As is clear from Fig. 1, the first push-pull circuit 2 is provided with: a first switching element, i.e., first MOS transistor 2A; a second switching element, i.e., second MOS transistor 2D; a first resistor 2B with a resistance value R1; and, a fourth resistor 2C with a resistance value R2. The first MOS transistor 2A is constructed of a p-type enhancement-type MOS FET (i.e., field effect transistor). The MOS transistor 2A has its source (S) connected with the power supply line and has its drain (D) connected with the first resistor 2B. The gate (G) of this first MOS transistor 2A is connected with the first input terminal 1A. On the other hand, the second MOS transistor 2D is constructed of an n-type enhancement-type MOS FET. The second MOS transistor 2D has its source (S) connected with the ground (GND), and has its drain (D) connected with the fourth resistor 2C. The gate (G) of this second MOS transistor 2D is connected with the first input terminal 1A. The first resistor 2B has one of its opposite ends connected with the drain (D) of the first MOS transistor 2A, and the other of its opposite ends connected with one of opposite ends of the second resistor 2C. The other end of this second resistor 2C is connected with the drain (D) of the second MOS transistor 2D. The first resistor 2B is connected with the second resistor 2C through the node "A". Incidentally, as described above, in the drawings, the resistance value of the first resistor 2B is represented by the reference capital letter/numeral R1. On the other hand, the resistance value of the second resistor 2C is represented by the reference capital letter/numeral R2. As for the second push-pull circuit 3, as shown in Fig. 1, it is provided with: the third MOS transistor 3A; the fourth MOS transistor 3D; the third resistor 3B; and, the fourth resistor 3C. The third MOS transistor 3A is constructed of a p-type enhancement-type MOS FET (i.e., field effect transistor). This third MOS transistor 3A has its source (S) connected with the power supply line, has its drain (D) connected with the third resistor 3B, and has its gate (G) connected with the second input terminal 1B. On the other hand, the fourth MOS transistor 3D is constructed of an n-type enhancement-type MOS FET. This fourth MOS transistor 3D has its source (S) connected with the ground, has its drain (D) connected with the fourth resistor 3C, and has its gate (G) connected with the second input terminal 1B. The third resistor 3B has one of its opposite ends connected with the drain (D) of the third MOS transistor 3A, and has the other of its opposite ends connected with one of opposite ends of the fourth resistor 3C. The other end of the opposite ends of the fourth resistor 3C is connected with the drain (D) of the fourth MOS transistor 3D. The third resistor 3B is connected with the fourth resistor 3C through the node "B". A resistance value of the third resistor 3B is represented by the reference capital letter/numeral "R3". Further, a resistance value of the fourth resistor 3C is represented by the reference capital letter/numeral "R4". On the other hand, the adjusting resistor 4 has one of its opposite ends connected with the node "A", and has the other of its opposite ends connected with the node "B". A resistance value of the adjusting resistor 4 is represented by a reference capital letter/numeral "R5". The first output terminal 5A is connected with the node "A", while the second output terminal 5B is connected with the node "B". In the driver circuit unit of the present invention having the above construction, so-called on resistance values R M1 , R M2 , R M3 and R M4 , which correspond to the MOS transistors 2A, 2D, 3A and 3D being in conductive state, respectively, are designed to be small. Further, In the driver circuit unit of the present invention having the above construction, the following equations (1), (2), (3) and (4) must be satisfied with respect to the resistors 2B, 2C, 3B and 3C, respectively: namely, R M1 << R1 R M2 << R2 R M3 << R3 R M4 << R4 Further, in the driver circuit unit of the present invention having the above construction, the MOS transistors 2A, 2D, 3A, 3D and the resistors 2B, 2C, 3B, 3C, 4 are formed on an integrated circuit chip. Now, in operation, this embodiment of the driver circuit unit of the present invention will be described. In the first push-pull circuit 2 shown in the right half portion of Fig. 1, when the positive-phase data 201 is supplied to the first input terminal 1A and the negative-phase data 202 with a high level is supplied to the second input terminal 1B, the first MOS transistor 2A is turned ON so as to be conductive while the second MOS transistor 2D is turned OFF so as to be non-conductive. At this time, in the second push-pull circuit 3 shown in the left half portion of Fig. 1, the third MOS transistor 3A is turned OFF so as to be non-conductive. On the other hand, the fourth MOS transistor 3D is turned ON so as to be conductive. As a result, an electric current flows in the direction of the arrow 41 through the adjusting resistor 4, i.e., flows downward as viewed in Fig. 1, which causes a voltage appearing at the node "A" to be higher than a voltage appearing at the node "B". Consequently, due to the presence of the first MOS transistor 2A and the fourth MOS transistor 3D, it is possible to form a circuit (shown in Fig. 2) equivalent to the driver circuit unit of the present invention shown in Fig. 1. In this circuit shown in Fig. 2, the first MOS transistor 2A, first resistor 2B, adjusting resistor 4, fourth resistor 3C and the fourth MOS transistor 3D are connected with each other in series. Further, in the driver circuit unit of the present invention shown in Fig. 1, when the positive-phase data 201 with the high level is supplied to the first input terminal 1A and the negative-phase data 202 with the low level is supplied to the second input terminal 1B, the first push-pull circuit 2 has its first M0S transistor 2A turned OFF so as to be non-conductive and also has its second MOS transistor 2D turned OFF so as to be conductive. At this time, in the second push-pull circuit 3, the second MOS transistor 3A is turned ON so as to be conductive and the fourth MOS transistor 3D is turned OFF so as to be non-conductive. As a result, the electric current flows upward in the direction of the arrow 42 as shown in Fig. 1, which causes a voltage appearing at the node "B" to be higher than a voltage appearing at the node "A". Due to the presence of the second MOS transistor 2D and the third MOS transistor 3A both in conductive states, it is possible to form a circuit (shown in Fig. 3) equivalent to the driver circuit unit of the present invention shown in Fig. 1. In this circuit shown in Fig. 3, the third MOS transistor 3A, third resistor 3B, adjusting resistor 4, second resistor 2C and the second MOS transistor 2D are connected with each other in series. Here, in a condition in which the same transmission lines as those 102, 103 shown in Fig. 4 are used, each of the first resistor 2B, second resistor 2C, third resistor 3B and the fourth resistor 3C is selected so as to satisfy the following equation (5): namely, R1 = R2 = R3 = R4 = R Under such circumstances, when a voltage of the power supply line is represented by the reference characters V DD , a voltage appearing at a node "C" (shown in Figs. 2 and 3) at which the adjusting resistor 4 is divided into two halves is equal to a value of V DD /2. Consequently, it is possible to fix a voltage appearing at the node "C". As a result, in the circuit shown in Fig. 2, an output impedance "Z1" of the first output terminal 5A is given by the following equation (6): namely, Z1 = {(R M1 + R1) · (R5/2)}/{(R M1 + R1) + (R5/2)} On the other hand, as described above, in view of the above equation (1), the output impedance "Z1" of the first output terminal 5A is given by the following equation (7): namely, Z1 = {R·(R5/2)}/{R + (R5/2)} Similarly, in the circuit shown in Fig. 2, the output impedance "Z2" of the second output terminal 5B is given by the following equation (8): namely, Z2 = {(R M4 + R 4 ) · (R5/2) } / { (R M4 + R4) + <R5/2) } Further, in view of the above equation (4), the output impedance "Z2" of the second output terminal 5B is given by the following equation (9): namely, Z2 = Z1 Further, in the circuit shown in Fig. 2, since the equation (1) relates to the equation (4), it is possible to determine the logic level of each of the first output terminal 5A and the second output terminal 5B on the basis of the resistance values R1, R4 and R5, which values correspond to the resistors 2B, 3C and 4, respectively. In the circuit shown in Fig. 3, the output impedance Z3 of the first output terminal 5A is given by the following equation (10) : Z3 = {(R M3 + R3)·(R5/2)}/{(R M3 + R3) + (R5/2)} Further, in view of the above equation (3), it is possible to represent the output impedance "Z3" of the first output terminal 5A by the following equation (11): namely, Z3 = Z2 = Z1 Similarly, in the circuit shown in Fig. 3, the output impedance "Z4" of the second output terminal 5B is given by the following equation (12): Z4 = { (R M2 + R2) · (R5/2)}/{ (R M2 + R2) + (R5/2)} Further, since both the above equations (2) and (3) relate to the circuit shown in Fig. 3, it is possible to determine the logic level of each of the first output terminal 5A and the second output terminal 5B on the basis of the resistance values R3, R2 and R5, which values correspond to the resistors 3B, 2C and 4, respectively. As described above, in the embodiments of the present invention, it is possible to determine the output impedances Z1, Z2, Z3, Z4 of both the first output terminal 5A and the second output terminal 5B together with their logic levels on the basis of the resistance values R1, R2, R3, R4, R5 of the resistors 2B, 2C, 3B, 3C, 4. In other words, it is possible to arbitrarily determine the output impedances Z1, Z2, Z3, Z4 together with their logic levels on the basis of these resistance values R1, R2, R3, R4, R5 of the resistors 2B, 2C, 3B, 3C, 4. At the same time, these resistance values R1, R2, R3 and R4 are approximately ten times as large as the resistance values R M1 , R M2 , R M3 and R M4 of the MOS transistors 2A, 2D, 3A and 3D, respectively, provided that all of these MOS transistors 2A, 2D, 3A and 3D are in conductive state. In addition, these resistance values R1, R2, R3 and R4 satisfy the above equations (1), (2), (3) and (4). Consequently, under the above conditions, and with the condition that: in the process for fabricating the integrated circuit, with respect to variations in each of the resistance values R M1 , R M2 , R M3 and R M4 , which correspond to the MOS transistors 2A, 2D, 3A and 3D all in conductive state, respectively, variations of each of the resistance values R1, R2, R3 and R4, which correspond to the resistors 2B, 2C, 3B and 3C, respectively, are sufficiently reduced, it is possible to make the driver circuit unit of the present invention : less susceptible to variations in power supply; and, less process-dependent in its properties, with respect to the above output impedances and the above logic levels. Further, when metallic resistors made of high-melting point metal silicides, which are compounds formed by the reaction of metals or high-melting point metals and silicon, for example such as tungsten silicide, cobalt silicide, titanium silicide, molybdenum silicide and like silicides, are used as the above resistors 2B, 2C, 3B, 3C and 4, each of these resistors 2B, 2C, 3B, 3C and 4 all made of high-melting point metal silicides becomes temperature-independent in its properties. Consequently, it is possible to prevent the output impedances and the logic levels from varying even when these resistors 2B, 2C, 3B, 3C and 4 vary in temperature. Further, since the high-melting point metal silicides are larger in specific resistance than metal itself, it is possible to reduce each of the resistors 2B, 2C, 3B, 3C and 4 in its occupation area size on the chip in comparison with the resistors made of metal. Due to this, it is considerably advantageous to use the resistors made of such high-melting point metal silicides in place of the resistors made of metal. Further, in operation, when the first MOS transistor 2A and the fourth MOS transistor 3D are in their conductive states, the resistors 2B, 4 and 3C are interposed between the first MOS transistor 2A and the fourth MOS transistor 3D. On the other hand, when the second MOS transistor 3A and the second MOS transistor 2D are in their conductive states, the resistors 3B, 4 and 2C are interposed between the second MOS transistor 3A and the second MOS transistor 2D. As a result, it is possible to reduce the amount of electric current passing through each of the above MOS transistors 2A, 2D, 3A and 3D. Although the embodiments of the present invention have been described in detail with reference to the drawings in the above, the concrete construction of the driver circuit unit of the present invention is not limited to these embodiments only. In other words, various modifications and changes in design of these embodiments of the present invention may be made without departing from the scope of the present invention as defined in the claims. For example, though the MOS transistors 3A, 3B, 3C and 3D of the driver circuit unit of the present invention are of enhancement type, it is also possible to construct the push-pull circuits 2, 3 by means of MOS transistors of depletion type. Further, in the above embodiments of the present invention, though the driver circuit unit of the present invention is formed on the integrated circuit chip, it is also possible to form the driver circuit unit of the present invention by mounting resistors and switching elements on a printed board. As described above, it is possible for the driver circuit unit of the present invention having the above construction to determine its output impedance so as to match to the first transmission line by means of the resistors of the first circuit and the adjusting resistor, and also to determine its output impedance so as to match to the second transmission line by means of the resistors of the second circuit and the above adjusting resistor. Further, in the driver circuit unit of the present invention having the above construction, since its output impedance matching to the first transmission line is determined by means of the resistors of the first circuit and the adjusting resistor, and since its output impedance matching to the second transmission line is determined by means of the resistors of the second circuit and the above adjusting resistor, it is possible to make the driver circuit unit of the present invention : less susceptible to variations in power supply; and, also less process-dependent in its properties. It is thus apparent that the present invention should by no means be limited to the illustrated embodiments and various modifications and changes may be suggested without departing from the scope of the invention.

Claims: A driver circuit unit having a first and a second output terminal (5A, 5B) both connected with a receiver through a first and a second transmission line (102, 103), respectively; a first circuit (2) for issuing an output signal to said first output terminal (5A) when transmitting data is issued to a first input terminal (1A), said output signal having its logic level corresponding to said transmitting data; a second circuit (3) for issuing a negative-phase output signal to said second output terminal (5B) when negative-phase data, which is one reversed in phase of said transmitting data, is issued to a second input terminal (1B) said negative-phase output signal having its logic level corresponding to said negative-phase data; an adjusting resistor (4) connected between said first and said second output terminal (5A, 5B); a first switching element (2A) connected between a power supply line and said first output terminal (5A), said first switching element (2A) being turned ON and OFF according to said transmitting data; a second switching element (3D) connected between said second output terminal (5B) and ground, said second switching element (3D) being turned ON and OFF according to said transmitting data characterized by a first resistor (2B) interposed between said first switching element (2A) and said first output terminal (5A); a second resistor (3C) interposed between said second switching element (3D) and said second output terminal (5B); a third switching element (2D) connected between said first output terminal (5A) and ground, said third switching element (2D) being turned ON and OFF according to said transmitting data when said first switching element (2C) is turned OFF and ON, respectively; a third resistor (2C) interposed between said third switching element (2D) and said first output terminal (5A); and a fourth switching element (3A) connected between said power supply line and said second output terminal (5B), said fourth switching element (3A) being turned ON and OFF according to said transmitting data when said second switching element (3D) is turned OFF and ON, respectively; a fourth resistor (3B) interposed between said fourth switching element (3A) and said second output terminal (5B). The driver circuit unit according to claim 1, characterized in that each of said first to fourth switching elements (2A, 3D, 2D, 3A) is constructed of an insulated-gate type field effect transistor. The driver circuit unit according to claim 1, characterized in that said first switching element (2A) and said third switching element (2D) both have in conductive state a smaller resistance value than said first resistor (2B) and said third resistor (2C), respectively. The driver circuit unit according to any of claims 1 to 3, characterized in that said fourth switching element (3A) and said second switching element (3D) both have in conductive state a smaller resistance value than said fourth resistor (3B) and said second resistor (3C), respectively.

Inventors: NAKAGAWA MASASHI, NAKAGAWA, MASASHI
Applicants: NEC ELECTRONICS CORP, NEC ELECTRONICS CORPORATION
Application year: 1999
Main classification: H04L25
IPC codes: H03K19, H04L25