METHOD AND APPARATUS FOR DATA SAMPLE CLOCK RECOVERY

Abstract: A method and apparatus is described for recovering data sample clock rates from received isochronous streams of data packets including associated time stamp values, such as in an IEEE 1394 bus-interconnected system. The difference between consecutive time stamp values is determined by successively latching the time stamp values and applying them to a subtracter circuit to produce a difference value. This difference value is then successively decremented by a down counter, with the down counter then producing a signal pulse and loading a next difference value upon completion of the count. The pulsed signal is applied to a phase-locked loop to provide a frequency multiple, and a clock signal is correspondingly produced that has a frequency proportional to the difference between the consecutive time stamp values. Data input buffer levels may be monitored and the clock signal frequency adjusted accordingly.

Description: METHOD AND APPARATUS FOR DATA SAMPLE CLOCK RECOVERY CROSS-REFERENCE TO RELATED APPLICATIONS This application is related to U.S. Patent Application No. 60/085,021, filed on May 11, 1998, the disclosure of which is incorporated herein by reference. TECHNICAL FIELD The present invention relates generally to bus system architecture and, more particularly, to a method and apparatus for recovering received data sample clock rates. BACKGROUND Today's consumer electronic devices are increasingly being implemented as special-purpose computer systems, complete with processor, memory, and I/O functionality. The various companies who design and manufacture these devices may have their own particular interconnect technology and communication protocols. Consequently, compatibility problems can occur when connecting devices made by different manufacturers. In home entertainment systems, for example, a DVD player manufactured by one company may be incompatible with an audio speaker subsystem manufactured by another company. To facilitate today's increasingly complex communication between electronic devices, various standards have been developed. In particular, the IEEE 1394 standard for a High Performance Serial Bus (also known as the "FireWire" bus) has been established to facilitate the development of compatible consumer electronics devices. In addition to defining a standard bus communications protocol, the FireWire bus architecture also provides for standard connections, with each interconnected device being able to communicate with every other such device without requiring individual point-to-point connections between the various devices. The IEEE 1394 standard (IEEE 1394-1995 and IEEE 1394a supplement) is entitled "Standard for a High Performance Serial Bus," and is based on thelSO/JEC 13213 (ANSI/IEEE 1212) specification, entitled "Information technology — Microprocessor systems — Control and Status Registers (CSR) Architecture for microcomputer buses." Referring to Figure 1, a typical home entertainment system 100 is depicted. The system includes a high speed bus, such as an IEEE 1394 bus 102, that interconnects a variety of electronic devices. The particular configuration depicted is intended solely to show the functional interconnection of representative devices. Those skilled in the art understand that FireWire bus architecture supports tree and daisy chain connection configurations. A DVD player 104 is included for playing DVD disks and correspondingly outputting audio and MPEG video data streams on the 1394 bus 102. The audio and video data streams are transported over isochronous channels of the 1394 bus 102, with a surround sound decoder 106 receiving the audio data stream and a video decoder/monitor 108 receiving the MPEG video data stream. A cable or satellite set-top box 110 receives media from a cable or satellite television provider and outputs corresponding audio and MPEG video data streams on isochronous channels of the 1394 bus 102. The surround decoder 106 receives the audio data, and the video decoder monitor 108 receives the video data. The surround sound decoder 106 receives compressed audio signals from other devices connected to the 1394 Bus 102 and decodes the audio. The decoded audio data is then output on the 1394 bus 102 to an amplifier/speaker subsystem 112. The video decoder/monitor 108 decodes MPEG data streams received from various video source devices on the 1394 bus 102. Once decoded, the uncompressed video signal is then typically output to a video monitor for presentation. A controller 114 provides a point of control for all devices in the system 100. The controller 114 may also provide a user interface to configure the system when various devices are added or removed. The controller typically includes a user interface for adjusting audio volume, turning devices on and off, selecting channels on the set-top box 110, etc. Indeed, the controller may be the only device a user interacts with (other than inserting disks into the DVD player 104). Each of the interconnected devices shown in the system 100 Figure 1 includes interface circuitry connecting the 1394 Bus 102 to the particular application circuitry included in the devices. Such interface circuitry includes both the physical electrical connections (known as the PHY layer) and the data format translation interface (known as the Link layer). Such interface circuitry is well known for those skilled in the art, and the general features of such circuitry need not be described herein. For video and audio applications, which require constant data transfer rates, it is particularly important that a device receiving such data accurately recover the sample rate clock signal from the device transmitting such data. This ensures that data buffers in the system do not overflow or underflow. FireWire bus architecture supports transmission of isochronous data packets including time stamp information that can be used to recover the sample rate clock, such as in accordance with the IEC 61883 standard, entitled "Digital Interface for Consumer Audio/Video Equipment." Because there is no requirement that different data streams be frequency related (i.e., isochronous streams may have free-running sample rates), each receiving device or node must implement a separate clock recovery circuit for each received isochronous channel of the 1394 bus. Referring to Figure 2, a functional block diagram depicts the prior art approach of providing time stamps and correspondingly recovering a sample rate clock. The interface circuitry included within a transmitting device or node 200 is depicted, as is a portion of the interface circuitry included within the receiving device or node 202. The transmitting node 200 includes a latch 204 that latches a lower portion of the value stored in a cycle time register 206 included within the Link layer of the interface circuitry. The latch 204 latches the cycle time value every predetermined number of cycles of the sample rate clock (such as a digital audio word clock in the case of audio data transmission). A transfer delay value is added to the latched cycle time register value, and the resulting time stamp is inserted into the header of the corresponding isochronous data packet 208. As is known to those skilled in the art, the value of the transfer delay is determined at system initialization or bus reset. At the receiving device or node 202, the received time stamp is compared with the corresponding lower portion of the value stored in the receiving node's cycle time register 210. A comparator 212 produces a pulse signal in the event of equality, which is then input to a phase-locked loop (PLL) circuit 214 to recover the sample rate clock signal. The particular approach depicted in Figure 2 has a number of disadvantages. If the stream of time stamps is interrupted for any reason, such as during a bus reset, the pulse signal produced by the comparator 212 experiences drop outs, and the PLL 214 then temporarily loses lock and causes a glitch in the sample rate clock signal. If the isochronous data packets are so delayed that their time stamps lead the value stored in the local cycle time register 210 of the receiving node 214, one full cycle of the time stamp period (approximately two milliseconds) must then elapse before the comparator 212 can detect an equality match. This then causes an error in the time at which the audio data is presented. Further, many devices, such as personal computers, have difficulty maintaining the high degree of accuracy required to create and process the time stamps in the manner described above in connection with Figure 2. SUMMARY In accordance with the present invention, a method is provided for recoverying a data sample rate from a stream of data packets having corresponding time stamp values. The method includes determining the difference between successive time stamp values and then producing a clock signal having a frequency substantially proportional to the determined difference between successive time stamp values. Determining the difference between successive time stamp values may include latching first and second time stamp values, and then subtracting the first time stamp value from the second time stamp value to produce a difference value. Producing the clock signal may then include successively decrementing the difference value until the decremented value reaches a predetermined minimum value, at which time a signal pulse is produced. The frequency of the produced clock signal is then made proportional to the frequency of signal pulses. In accordance with another aspect of the present invention, circuitry is provided for recoverying a data sample rate from a stream of data packets having corresponding time stamp values. The circuitry includes first and second latches for respectively latching first and second time stamp values. A subtracter circuit produces a difference value corresponding to the difference between the first and second time stamp values. A down-counter successively decrements the difference value and produces a signal pulse when the decremented value equals a predetermined minimum value. A phase-locked loop receives the signal pulse and responsively produces a clock signal having a frequency proportional to the frequency of the signal pulses. BRIEF DESCRIPTION OF THE DRAWINGS Figure 1 is a functional block diagram that depicts a typical IEEE 1394 system. Figure 2 is a functional block diagram that depicts circuitry for producing time stamps by a transmitting device and circuitry for sample rate clock recovery in a prior art receiving device in an IEEE 1394 system. Figure 3 is a functional block diagram depicting a received isochronous datapath through interface circuitry in accordance with an embodiment of the present invention. Figure 4 is a functional block diagram depicting circuitry included in the interface of Figure 3 for recovering the sample rate clock signal in accordance with an embodiment of the present invention. Figure 5 is a functional block diagram depicting circuitry included in the interface of Figure 3 for recovering the sample rate clock signal in accordance with another embodiment of the present invention. DETAILED DESCRIPTION The following is a description of circuitry and methods for recovering a data sample clock from an isochronous data packet stream. The circuitry and methods are conformable to the applicable IEEE 1394, ISO/IEC 13213, and IEC 61883 standards. In this description, certain details are set forth in order to provide a thorough understanding of various embodiments of the present invention. It will be clear to one skilled in the art, however, that the present invention may be practiced without these details. In other instances, well-known circuits, circuit components, control signals, and timing and communications protocols have not been shown or described in detail in order to avoid unnecessarily obscuring the description of the various embodiments of the invention. The described subject matter relates to technology similar to that disclosed in a concurrently filed patent application, entitled "Method and Apparatus for Low Jitter Clock Recovery," the disclosure of which is incorporated herein by reference. Figure 3 shows certain circuitry included within a Link layer 300 of interface circuitry coupling the 1394 bus 102 to an application host 302. The figure also depicts the physical/electrical interface or PHY layer 304. The particular circuitry shown within the Link layer 300 is a simplified depiction of the datapath for received isochronous data, together with certain associated control/monitor circuitry. Those skilled in the art will appreciate that a wide variety of circuitry is not shown in Figure 3, such as bus management layer circuitry, transaction layer circuitry, datapath and control circuitry for transmitted isochronous data, and other link layer circuitry associated with asynchronous data protocols. Such well-known circuitry is not shown in order to avoid unnecessarily obscuring the description of embodiments of the present invention. The Link layer circuitry 300 includes a FIFO 306 for receiving incoming isochronous data packets, such as audio data packets. These data packets are passed on to a packet parser 308 that separates the audio data from the header of the packet, including the time stamp. The audio data is then passed on to another FIFO 310, and then on to the application host 302 via a digital audio interface 312. The packet parser 308 provides the time stamp values from the isochronous data packets to a sample clock recovery circuit 314. A fill-level monitor circuit 316 monitors the fill level of the packet FIFO 306 and responsively asserts a fill control signal applied to the sample clock recovery circuit 314. The sample clock recovery circuit 314 produces a sample rate clock signal corresponding to the received time stamps and fill control signal. This clock signal is applied to a clocks generator circuit 318, which in turn provides the various well-known clocking signals applied to the digital audio interface 312. With the exception of the clock recovery circuit 314, which is further described below, each of the circuits described in connection with Figure 3 is of a type well known in the art. One skilled in the art would be able to implement such circuits or their equivalent in the described or equivalent configuration to practice the present invention. Accordingly, internal and operational details of such circuits need not be provided. Figure 4 depicts certain internal details of the sample clock recovery circuit 314 included in the Link layer circuitry 300 of Figure 3. ]_ncoming time stamps are passed through a series of two latches 404 and 406. The output of latch 404 and the output of latch 406 are applied to a subtract circuit 408. The subtract circuit 408 calculates the difference between the outputs of latches 404 and 406 and provides a difference value for loading into a down counter 410. This difference value then corresponds to the difference between consecutive time stamps received by the sample clock rate recovery circuit 314. Those skilled in the art will appreciate that a series of N latches or other circuitry could be adapted to determine a difference value averaged over N isochronous cycles, thereby reducing round-off errors in the time stamps. The down counter 410 is clocked by the same 24.576 MHz clock signal that increments the cycle time registers 206, 210 Figure 2. The down counter 410 produces a pulse when it reaches zero (or other predetermined minimum value) and also loads the next difference value provided by the subtract circuit 308. Accordingly, the pulsed signal produced by the down counter 410 has a frequency that is proportional to the difference between the successive time stamps received by the sample clock rate recovery circuit 314. This pulsed signal is then input to a phase-locked loop 412 of substantially the same configuration as the phase-locked loop 214 depicted in Figure 2, and the sample rate clock is correspondingly recovered. Those skilled in the art will appreciate that an up counter or other circuit could be adapted and substituted for the described down counter 410. More generally, the down counter may be substituted with suitably adapted circuitry that successively modifies the difference value until it reaches a predetermined value, whereupon a pulse is produced. Additionally, a "nudge" control input provides an addition or subtraction to the value output by the subtract circuit 408. The nudge control input may receive the above-described fill control signal or another signal derived therefrom. By adjusting the difference value produced by the subtract circuit 408, the resulting sample rate clock signal is then nudged up or down from its otherwise nominal rate. The sample rate can then be adjusted up or down to maintain an appropriate fill level of the packet FIFO 306 (see Figure 3). This then accommodates any errors due to lost or inaccurate time stamps, and helps alleviate the prior art problems associated with the poorly generated time stamps from devices such as a personal computer. Figure 5 shows an alternative circuit configuration to that depicted in Figure 4. In this configuration, a subtract circuit 502 calculates the difference beween consecutive time stamps. The difference value produced by the substract circuit 502 is applied to a difference register 504 and a variance accumulator 506. The difference register 504 stores an initial difference between consecutive time stamps and provides this constant input to a down counter 508, which in turn applies a pulsed signal to the PLL 412 in a manner similar to that described above in connection with Figure 4. By loading a constant value in the down counter 508, the PLL 412 is referenced to a constant frequency signal and jitter is eliminated. SUBSTITUTE SHEET (RU. £ 2«) To account for variations in the received time stamp differences, the accumulator 506 keeps a running total of the variances (i.e., a sum of the differences of the time stamp differences). When this sum exceeds a first predetermined threshold, or falls below a second predetermined threshold, the accumulator 506 applies a corresponding nudge signal to the down counter 508. The down counter 508 then adjusts the next loaded difference value up or down by 1, as appropriate, to correspondingly modify the frequency of the pulsed signal applied to the PLL 412. Input buffer monitoring may still be employed, as described above in connection Figure 3, and the circuitry of Figure 5 suitably adapted to provide for such additional nudge functionality. The above described embodiments of the present invention provide several advantages over the prior art. If, for any reason, time stamps are interrupted, the last computed time stamp difference can be retained, thereby providing a means to continually compute new pulses produced by the down counter 410. This results in a clock frequency very close to the actual rate, which avoids sample rate clock glitches until the incoming time stamps resume. The nudge feature can also be used to keep the phase-locked loop 412 locked even in the absence of incoming time stamps. By monitoring FIFO fill levels and adjusting the nudge control to maintain a constant fill level, a sample rate clock signal can be provided without any future incoming time stamp values. Indeed, time stamps could be first used as a coarse control value during the beginning of data transfer, with the nudge feature then driving the sample rate clock frequency to maintain a substantially constant FIFO fill level. Also, if the difference between time stamps is constant (as is the case when the sample rate and the 1394 bus clock (24.576 MHz) frequencies are an exact integer ratio), it is sufficient to compute the time stamp difference once and then use this difference successively. Thus, the receiving node need not continually monitor SUBSTITUTE SHEET (RULE ?.«, time stamps for more than the first few packets. Indeed, the transmitting node may simply send two time stamps and then cease transmitting time stamps with subsequent data packets. Each of the circuits described above in connection with Figures 4 and 5 is of a type well known in the art. One skilled in the art would be able to implement such circuits or their equivalents in the described or equivalent configuration to practice the present invention. Accordingly, internal and operational details of such circuits need not be provided. From the foregoing, it will be appreciated that, although specific embodiments of the invention have been described above for purposes of illustration, various modifications may be made to these embodiments without deviating from the spirit and scope of the invention. While the discussion has been primarily directed to recoverying data sample clocks for audio data in IEEE 1394 bus-based systems, the inventive teachings are also applicable to other isochronous communications. Those skilled in the art will understand that any of a wide variety of circuit topologies could be employed to recover data sample rate clock signals by deteπnining the difference between time stamp values. Also, many of the functions of the above-described circuit embodiments could instead be performed in software. Indeed, numerous variations are well within the scope of the invention, and the invention is not limited except as by the appended claims. SUBSTITUTE SHEET (RULE 28)

Claims: CLAIMS 1. A method of recoverying a data sample rate from a stream of data packets including associated time stamp values, the method comprising: determ ing the difference between first and second time stamp values; and producing a clock signal having a frequency substantially proportional to the determined difference between the first and second time stamp values. 2. The method of claim 1 wherein the first and second time stamp values are associated with consecutively received first and second data packets. 3. The method of claim 1 wherein determining the difference between the first and second time stamp values comprises: latching the first time stamp value; latching the second time stamp value; and subtracting the first time stamp value from the second time stamp value. 4. The method of claim 1 wherein determining the difference between the first and second time stamp values includes producing a difference value corresponding to the difference between the first and second time stamp values, and wherein producing the clock signal comprises: successively adjusting the difference value; and when the adjusted difference value reaches a predetermined value, producing a signal pulse, the frequency of the clock signal being proportional to the frequency of successive signal pulses. 5. The method of claim 4 wherein adjusting the difference value includes decrementing the difference value, and wherein the predetermined value is a predetermined rninimum value. 6. The method of claim 1 wherein determining the difference between the first and second time stamp values includes producing a difference value, and the method further comprising modifying the difference value, the frequency of the produced clock signal being proportional to the modified difference value. 7. In a home entertainment system including an audio source coupled with an audio receiver, the audio source producing a stream of audio data packets having associated time stamp values, and the audio receiver receiving the audio data packets, a method for the audio receiver to recover a data sample rate from the audio data packets, the method comprising: extracting first and second time stamp values from respective first and second audio data packets; determining the difference between the first and second time stamp values; and producing a clock signal having a frequency substantially proportional to the determined difference between the first and second time stamp values. 8. The method of claim 7 wherein the first and second audio data packets are consecutively received by the audio receiver. 9. The method of claim 7 wherein the audio receiver receives the audio data packets in a buffer, the method further comprising: monitoring the fill level of the buffer; SUBSTITUTE SHEET (RULE 2R) if the fill level falls below a first predetermined level, then increasing the frequency of the produced clock signal; and if the fill level exceeds a second predetermined level, then decreasing the frequency of the produced clock signal. 10. The method of claim 7 wherein determining the difference between the first and second time stamp values includes producing a difference value corresponding to the difference between the first and second time stamp values, and wherein producing the clock signal comprises: successively adjusting the difference value; and when the adjusted difference value reaches a predetermined value, producing a signal pulse, the frequency of the clock signal being proportional to the frequency of successive signal pulses. 11. The method of claim 10 wherein the audio receiver receives the audio data packets in a buffer, the method further comprising: monitoring a fill level of the buffer; and modifying the difference value prior to performing the successive adjusting thereof, the modification corresponding to the monitored fill level of the buffer. 12. Circuitry for receiving a stream of data packets including associated time stamp values, the circuitry comprising: a buffer operable to receive and temporarily store the data packets; a packet parser coupled with the buffer and operable to separate the time stamp values from the data packets; and a clock recovery circuit coupled with the packet parser, the clock recovery circuit operable to receive the time stamp values and determine a difference therebetween, the sample clock recovery circuit being further operable to produce a SUBSTITUTE SHEET (RULE 2fi) clock signal having a frequency substantially proportional to the determined difference between the time stamp values. 13. The circuitry of claim 12, further comprising a monitor coupled with the buffer and with the clock recovery circuit, the monitor being operable to detect a fill level of the buffer and to responsively produce a fill control signal, the clock recovery circuit being operable to receive the fill control signal and to responsively adjust the frequency of the produced clock signal. 14. The circuitry of claim 12 wherein the clock recovery circuitry determines the difference between time stamp values associated with consecutively received data packets. 15. The circuitry of claim 12 wherein the clock recovery circuit comprises: a subtracter operable to receive first and second time stamp values and responsively produce a difference value corresponding to the difference between the first and second time stamp values; and a down-counter operable to receive the difference value and successively decrement the difference value, the down-counter operable to produce a signal pulse when the decremented difference value equals a predetermined minimum value, the clock signal being produced by the clock recovery circuit having a frequency proportional to the frequency of successive signal pulses. 16. The circuitry of claim 15, further comprising a monitor coupled with the buffer and with the clock recovery circuit, the monitor being operable to detect a fill level of the buffer and to responsively produce a fill control signal, the subtracter being operable to receive the fill control signal and to responsively adjust the produced difference value. SUBSTITUTE SHEET (RULE 28) 17. Circuitry for recoverying a data sample clock from a stream of data packets including associated time stamp values, the circuitry comprising: first and second latches operable to respectively latch first and second time stamp values; a subtracter operable to receive the latched first and second time stamp values and responsively produce a difference value corresponding to the difference between the first and second time stamp values; a down-counter operable to receive the difference value and successively decrement the difference value, the down-counter operable to produce a signal pulse when the decremented difference value equals a predetermined minimum value; and a phase-locked loop operable to receive the signal pulse and to correspondingly produce a clock signal, the frequency of the clock signal being proportional to the frequency of successive signal pulses. 18. The circuitry of claim 17 wherein the subtracter is further operable to receive a control signal and responsively modify the produced difference value. 19. The circuitry of claim 17 wherein the down counter is operable to respond to the signal pulse to receive a next difference value produced by the subtracter. 20. A home entertainment system comprising audio/video sources coupled with audio/video receivers, the sources each operable to produce a stream of data packets having associated time stamp values, and the receivers each operable to receive a selected one of the streams of data packets, at least one of the receivers including: a buffer operable to receive and temporarily store the received data packets; a monitor coupled with the buffer and operable to detect a fill level of the buffer and to responsively produce a fill control signal; a packet parser coupled with the buffer and operable to separate the time stamp values from the data packets; and a clock recovery circuit coupled with the packet parser and with the monitor, the clock recovery circuit operable to receive the time stamp values and deteπnine a difference therebetween, the clock recovery circuit also operable to receive the fill control signal, and the sample clock recovery circuit being further operable to produce a clock signal having a frequency corresponding with determined difference between the time stamp values and the fill control signal. 21. The home entertainment system of claim 20 wherein the clock recovery circuitry determines the difference between time stamp values associated with consecutively received data packets. 22. The home entertainment system of claim 20 wherein the audio/video sources are coupled with the audio/video receivers by an IEEE 1394 bus. SUBSTITUTE SKEFT (RULE ?β)

Inventors: BARTLETT GREGORY J, GOLDSTEIN ALLEN R, KARR BRIAN D, MOSES ROBERT W, BARTLETT, GREGORY, J., GOLDSTEIN, ALLEN, R., KARR, BRIAN, D., MOSES, ROBERT, W.
Applicants: BARTLETT GREGORY J, DIGITAL HARMONY TECHNOLOGIES L, GOLDSTEIN ALLEN R, KARR BRIAN D, MOSES ROBERT W, BARTLETT, GREGORY, J., DIGITAL HARMONY TECHNOLOGIES, L.L.C., GOLDSTEIN, ALLEN, R., KARR, BRIAN, D., MOSES, ROBERT, W.
Application year: 1999
Main classification: H05L12
IPC codes: G06F9, G06F13, H04J3, H04L7, H04L12, H04N5, H04N7