Apparatus and method for static random access memory array

Abstract: A static random access memory array (200) with power supplies and an array biasing scheme is disclosed. A power supply (202) has an output voltage that is applied to the bitlines (40). The output voltage pre-charges the bitlines (40) to read from the memory cells (10). An array power supply (204) has an array voltage that is applied to the memory cells. The array voltage is higher than the output voltage. The array power supply (204) is drived by boosting the output voltage of the power supply (202).

Description: TECHNICAL FIELD OF THE INVENTION The present invention relates in general to memory systems and more particularly to a static random access memory array. BACKGROUND OF THE INVENTION Memory systems are known in the art and used in nearly all micro-processor and digital equipment applications. Memory systems generally utilize different types of memory for different applications. Once such type of memory is Static Random Access Memory ("SRAM"). SRAM systems have the advantage of high speed and ease of use as compared to some other types of memory systems. In addition, SRAM systems using MOS technology exhibit extremely low standby power and do not require a refresh cycle to maintain the information stored in the SRAM system. These attributes make SRAM systems particularly desirable for portable equipment, such as laptop computers. In an integrated circuit, SRAM systems are often organized into an array of memory cells, arranged in rows and columns. Generally, memory cells are set to one of two data states when storing a bit of information. Each memory cell may be referenced by a unique memory address, which includes a row address and a column address. The term "wordline" generally refers to a row of memory cells, whereas the term "bitlines" generally refers to a set of conductors that correspond to a column of memory cells. A memory cell typically includes of pair of complementary ports, with each port connected to one of the two bitlines dedicated to that column. Memory devices commonly operate in a read mode and a write mode. When writing to a memory cell, the wordline is activated, thereby activating the entire row in the array of memory cells. A differential current is applied to the bitlines between the two complementary input/output ports of the memory cell. The memory cell is latched to a specific logic state with a logic high indicated on one port and a logic low indicated on the other port. When reading from a memory cell, the wordline is activated and the logic states on the bitlines associated with the memory cell is differentially sensed using a sense amplifier. The sense amplifier outputs an amplify signal corresponding to the logic state written to the memory cell. A typical six transistor SRAM memory cell consists of two p-ch pull-up transistors, two n-ch pull-down transistors and two access transistors which are typically n-ch. High read current, write trip voltage and static noise margin, and low standby current are desired cell characteristics of a SRAM cell. High read current and write trip voltages are needed to improve the speed at which the data can be accessed and written, respectively. High static noise margin is needed for the circuit stability. Low standby current is needed to lower the power consumption when the cell is in the standby mode. Low standby current is achieved by keeping the threshold voltages of the various transistors high so that the subthreshold leakage current can be minimized. Increasing the n-channel threshold voltages, however, reduces the drive current and, hence, the read current during a read operation. It also reduces the write voltage, which results in slower write operation. Also, increasing the p-channel threshold voltage reduces the static noise margin, which hampers cell stability. Thus, a tradeoff exists between the low standby current and the speed and stability of the cell. The problem becomes more severe for lower supply voltages when the threshold voltage is a large fraction of the supply voltage, e.g., the case when the supply voltage is approximately one volt. A conventional solution to this problem has been to increase the internal supply voltage for the SRAM array to a maximum limit determined by gate oxide thickness and the device reliability. The problem with this type of biasing scheme is that the high voltage level can be very inefficient from the power consumption point of view. Also, because this boosted voltage would be applied to the bitlines, a large amount of supply current is needed to operate the SRAM array and poses difficulties in generating the boosted power. Another conventional solution to speed up the read and write operation has been to boost the wordline voltage over the bitline and array supply. However, this approach has the disadvantage of lowering the static noise margin and hence the stability of the cell. Another conventional solution has been to step down the bitline voltage to be lower than the supply voltage. Again, this method may or may not save power depending upon the bitline voltage level and how it is step down. US 5 668 770 wherein the preamble of claim 1 is based discloses a static RAM array which has a power supply that provides the pre-charge voltage applied to the bit lines. That power supply is boosted to provide the voltage that powers the cells of the array. Boosted wordline voltages are also disclosed. SUMMARY OF THE INVENTION From the foregoing, it may be appreciated that a need has arisen for an array of memory cells with an increased static noise margin without reduced read and write capabilities and at the same time maintaining low power consumption. The present application discloses an apparatus and method for a static random access memory array that substantially eliminates or reduces disadvantages and problems associated with conventional SRAM array designs and operations. The present invention provides a static random access memory array as indicated in claim 1. The present invention also provides a method of operating a static random access memory array as indicated in claim 4. The apparatus and method of the present application increase the speed and stability of the memory cells in an array without significantly increasing the power required to operate the cells. BRIEF DESCRIPTION OF THE DRAWINGS For a more complete understanding of the present invention and its advantages thereof, references now made to the following description taken in conjunction with the accompanying drawings, wherein like reference numerals represent like parts, in which: FIGURE 1 illustrates a schematic diagram of a six transistor static random access memory cell; and FIGURE 2 is a block diagram illustrating a static random access memory array. DETAILED DESCRIPTION OF THE INVENTION The preferred embodiment of the present invention and its advantages are best understood by referring now in more detail to FIGURES 1 and 2 of the drawings, in which like numerals refer to like parts. FIGURES 1 and 2 illustrate a static random access memory array in accordance with one embodiment of the present invention. FIGURE 1 is a simplified schematic diagram of a six transistor, low voltage, low power SRAM memory cell 10. Low voltage, low power SRAM cell 10 includes a first inverter 12 having a first pull-up transistor 22 between a high end of the array voltage, V DD , node 50, and a first inverter output node 16. First invertor 12 also has a first pull-down transistor 20 connected between output node 16 and a ground voltage, V SS , node 52. SRAM cell 10 also includes a second inverter 14 having a second pull-up transistor 26 and a second pull-down transistor 24. Second pull-up transistor 26 is connected between V DD node 50 and output node 18 of second inverter 14. Second pull-down transistor 24 is connected between output node 18 and V SS node 52. Invertors 12 and 14 are cross-coupled, i.e., output node 16 of first inverter 12 is connected to an input node 19 of second inverter 14 and output node 18 of second invertor 14 is connected to an input node 17 of first inverter 12. A first access transistor 32 is connected between output node 16 of first invertor 12 and a first bitline ("Bitline") bus 40. The cell also includes a second access transistor 30 connected between output node 18 of second invertor 14 and a second bitline ("Bitline Bar") bus 42. The gates of the first accessed transistor 32 and second access transistor 30 are connected to wordline bus 43. Typically, the signal for wordline bus 43 is derived from the X-address, or row select, and the signal for the bitline buses 40 and 42 is derived from the Y-address, or column select. The bitline buses run perpendicular to the wordline bus 43. That is, if wordline bus 43 is running in the X-direction, the bitlines buses 40 and 42 run in the Y-direction. Referring to FIGURE 2, a static random access memory array 200 with power supplies and a biasing scheme is disclosed. SRAM array 200 has a power supply 202, which may be an external power source or derived on-chip. Power supply 202 creates a supply voltage, V nom , that is applied to array voltage boosting circuit 204. Array voltage boosting circuit 204 boosts array voltage, V DD , which is applied to the memory cells, as disclosed in FIGURE 1. Power supply 202 also supplies supply voltage V nom to column decoder and bitline drivers 210. Column decoder 210 receives a column address during read and write operations, which correlates to the Y-value in a 2-dimensional addressing array used in the preferred embodiment. Power supply 202 is also connected to wordline voltage boosting circuit 212. Wordline supply voltage V WL is the result of the boosted V nom . Wordline voltage boosting circuit 212 supplies the V WL voltage source to row decoder and wordline driver circuit 216. Row decoder 216 may be supplied with other voltage sources, e.g., V nom , to optimize its performance and power consumption. Row decoder 216 receives row address commands during read and write operations. These operations serve to indicate the X-value in a 2-dimensional addressing array in the preferred embodiment. Thus, when wordline 43 is activated, wordline voltage V WL may be greater than supply voltage V nom . Column decoder 210 and row decoder 216 may receive a control signal. In an embodiment, external power supply voltage V nom is used as the power supply for the bitline biasing circuity. Thus, the bitlines' voltage range is between V ss and V nom . Array supply voltage, V DD , is derived by boosting the external supply voltage using known techniques. Similarly, the wordline voltage, V wl , is also derived by boosting the external supply voltage so that the wordlines are switched between V ss , when they are non-active, and V wl , when they are active. In many applications, it may be advantageous to have only one voltage boosting circuit, such that V wl and V DD are equal. Depending upon the data (1 to 0) stored in a cell, either inverter output node 16 or 18 may be at a low (close to V ss ) voltage and the other will be at a high (close to V DD ) voltage, when wordline 43 is non-active. The current that flows from the array supply voltage V DD is determined by the off leakage currents of one of the pull-up transistors 22 and 28 and one of the pull-down transistors 20 or 24, depending upon the stored state (1 or 0). In high performance SRAM's, that off state leakage typically is determined by the sub-threshold leakage current of the transistors. The contribution from the junction leakages are much lower, and ignored. Transistors 20, 22, 24 and 26 also contribute to the array supply current because the bitline voltage is lower than the output voltage of one of the inverters, which is at V DD . These off state sub-threshold leakage currents for access transistors 30 and 32, pull-down transistors 20 and 24 and pull-up transistors 22 and 26 contribute to the array standby current. During a read operation, bitline 40 and bitline 42 are precharged to V nom before wordline 43 is activated. Wordline 43 is activated by applying voltage V wl to wordline 43. This activation results in large current flowing through a first access transistor, either 30 or 32, which pulls down the voltage of the attached bitline. The current through the second access transistor is determined by its characteristics, such as the threshold voltage, drive current, sub-threshold leakage characteristics, bias conditions, etc. The drain for the second access transistor is at V DD , with the source at V nom and the gate at V wl . The net current through the second access transistor is supplied by the boosted array supply, V DD , through the p-ch pull-up transistors 22 or 26, and is minimized to reduce the power consumption. In order to minimize this power, the difference between V wl and V nom is kept below the threshold voltage of access transistors 30 and 32. Because the source (bitline) is at voltage V nom , the threshold voltage may include its reverse bias body effect. Typically, during a write operation, either bitline 40 or bitline bar 42 is lowered to V ss with the other at V nom . Wordline 43 is activated by applying voltage V wl . Wordline 43 flips the stored state of the cell when it is different from the state being written into it. During the period the cell takes to flip, significant current may flow from array supply voltage V DD to bitline 40 or bitline bar 42, which has been pulled low. The greater the V wl and V DD voltages, the greater the peak current. Because the flipping process is over within a few tenths of a picosecond, the average current through array supply may be minimal. After the cell has finished flipping such that one inverter output node is at V SS and the other inverter output node is at V DD , the current through a first access transistor, either 30 or 32, which is attached to the bitline pulled low, is negligible. The current through the second access transistor is similar as discussed above in the read cycle with bias condition of source at V nom , drain at V DD and gate at V wl . This current may be minimized by keeping the difference between V wl and V nom below the threshold voltage of second access transistor. Because the threshold voltage for a SRAM cell is about 0.4 to 0.5v for a 1.8v 0.25µm technology node, significant performance improvement may be obtained by increasing wordline voltage and array supply voltage as illustrated in the table below. The following table depicts simulated results using SPICE (Simulation Program with Integrated Circuit Emphasis). Array supply voltage current, I dd , flows when wordline 43 is activated during the read and write cycles. The current that flows when the cell flips during the write cycle is ignored. The table also shows the cell read current (Iread), write trip voltage (Vtrip) and static noise margin (SNM) for the case of V nom =V DD =V wl =1.0V and where V nom =1.0V, V DD =1.8V and V wl =1.5V. The transistor widths and lengths were 0.40/0.27, 0.55/0.24, 0.36/0.24 (um/um) for the access, pull-down and pull-up transistors, respectively. V nom (V) V DD (V) V wl (V) Iread (µA) Vtrip (V) SNM (mV) I dd Read 1.0 1.0 1.0 27.5 220 206 pA Read 1.0 1.8 1.5 94.0 380 15 nA Write 1.0 1.0 1.0 0.26 311 pA Write 1.0 1.8 1.5 0.38 15 nA The results indicate significant improvement in the cell characteristics while keeping the I dd to a low value. The cell read current, Iread, has increased from 27.5 µA to 94 µA. The write trip voltage, Vtrip, also increased from 0.26V to 0.38V and the SNM increased from 220 mV to 380 mV. I dd per cell through the array supply increased from 206 pA during a read cycle to 15 nA, and from 311 pA during a write cycle to 15 nA with higher V wl and V DD values. For an array with 256 cells on each wordline at 50% activation, a 15nA per cell current results in about 2µA array supply current, which is easily handled by a typical voltage boosting circuit. Also, increasing the array supply voltage reduces the soft error rates of the cells. Various voltage boosting techniques may be used to boost the voltage. One is charge pump circuit. The voltage boosting circuits may be on the same chip as the SRAM, or may be off-chip. In another embodiment, array supply voltage V DD may be equal to the wordline voltage V WL . This embodiment may reduce the number of boosted supplies needed to operate array 200. Further, in a standby mode, when data is neither being read nor written into array 200, the array supply voltage V DD and the wordline voltage V WL may be the same as supply voltage V nom by turning off the voltage boosting circuitry, e.g., array voltage boosting circuit 204 and wordline voltage boosting circuit 212. Thus, it is apparent that there has been provided in accordance with the present invention, a low voltage, low power static random access memory cell array that satisfies the advantages set forth above. Although the present invention has been described in detail, it should be understood that various changes, substitutions, and alterations can be made herein. For example, all though direct connections are shown between transitions, these transistors may be coupled to each other by one or more intermediate components such as resistors, capacitors, and/or inductors while still providing a substantially similar operating capability. Other examples are readily ascertainable by one skilled in the art.

Claims: a static random access memory array comprising: a plurality of bitlines (40, 42) connected to a plurality of memory cells (10) that include access transistors (30, 32) for reading and writing to the memory cell, each access transistor having an access threshold voltage; a power supply (202) with an output voltage (V NOM ) applied to the bitlines, wherein the output voltage pre-charges the bitlines to read from the memory cells; and an array power supply (204) with an array voltage applied to the memory cells, wherein the array voltage is higher than the output voltage and the array power supply is driven by boosting the output voltage of the power supply; characterised in that the static random access memory array further comprises: a wordline bus (43) connected to the access transistors, the wordline bus having a wordline voltage (V WL ) that is greater than the output voltage (V NOM ) and less than the sum of the output voltage (V NOM ) and the access threshold voltage. The array of any of claims 1 to 3, wherein the power supply (202) comprises an external power source. The array of any of claim 1 to 3, wherein the power supply (202) comprises an on-chip power source. a method of operating a static random access memory array having a plurality of bitlines (40, 42) connected to a plurality of memory cells (12, 14), comprising the steps of; pre-charging the bitlines with a supply voltage; boosting the supply voltage to derive an array voltage; and applying the array voltage to the memory cells at a boosted level higher than the supply voltage; and reading and writing to the memory cells through access transistors (30, 32) having a threshold voltage; characterised in that the method further comprises applying a wordline voltage to the access transistors that is greater than the output voltage and less than the sum of the supply voltage and the threshold voltage of the access transistors.

Inventors: MADAN SUDHIR, STRONG BOB D, MADAN, SUDHIR, STRONG, BOB D.
Applicants: TEXAS INSTRUMENTS INC, TEXAS INSTRUMENTS INCORPORATED
Application year: 1999
Main classification: G11C11
IPC codes: G11C11