CURRENT MEASURING DEVICE AND TELEPHONE TERMINAL USING SUCH A CURRENT MEASURING DEVICE

Abstract: Current measuring device which comprises a current sense resistor (2) for generating a voltage proportional to the current to be measured. The voltage is measured by a MOS transistor (4) having its gate terminal connected to a first terminal of the current sense resistor (2), and having its source terminal connected to a second terminal of the current sense resistor (2). The drain current of the MOS transistor (4) is coupled by means of current coupling means (5) to the source terminal of a further MOS transistor (10) having its gate and source terminals interconnected. The drain current of the MOS transistor (4) causes a voltage across the further MOS transistor (10) which is proportional to the current in the current sense resistor (2). This is however only the case if the voltage across the current sense resistor exceeds the threshold voltage of the MOS transistor (4). By introducing an offset source (6, 8) an output voltage which is proportional to the current to be measured, can be obtained for all current values as long the MOS transistor (4) is conducting.

Description: Current measuring device and telephone terminal using such a current measuring device. The present invention relates to a current measuring arrangement for providing an output voltage proportional to a current to be measured on an output terminal, said current measuring device comprising a first field effect device and a second field effect device. The present invention also relates to a voltage measuring device and a telephone terminal using a current measuring device according to the invention. A current measuring device according to the preamble is known from the Unexamined Japanese Patent Application, Laid Open No. 59-221672. Such current measuring devices find widespread use in applications in which a voltage should be provided representing a current flowing in a part of an electronic circuit. An example of such an application is a telephone terminal in which it is advantageous to make several transmission parameters dependent on the line current. Examples of such parameters are the gain of microphone and earpiece amplifiers. Also the control of the side tone balance can be made dependent on the DC line current to ensure a correct side tone suppression for all line lengths. In the current measuring arrangement according to the above mentioned Japanese Patent Application the current to be measured is applied to the source of a first field effect device. The drain of the first field effect device is connected to the source of a second field effect device. The drain of the second field effect device is connected to a power supply. The gates of the first and second field effect devices are connected to a corresponding reference voltage. The voltage at the source of the second field effect device will change with the current to be measured, because the second field effect device will adjust its gate source value to a value corresponding to the input current. This source voltage is applied to a source follower circuit which makes the output signal available at the output terminal. Because the relation between the gate-source voltage and the drain current of a field effect device is non-linear, the relation between the current to be measured and the output voltage will also be non-linear. In general such a non-linear relationship is undesired in such a measuring arrangement. The object of the present invention is to provide a current measuring arrangement according to the preamble in which a linear relation between the current to be measured and the output voltage is obtained. To achieve said objective, the present invention is characterized in that the current measuring device comprises a current sensing resistor having a first terminal and a second terminal, a gate electrode of the first field effect device being coupled to the first terminal of the current sensing resistor, a source electrode of the first field effect device being coupled to a second terminal of the current sensing resistor, a drain electrode of the first field effect device being coupled to a current coupling device for causing a current dependent on the drain current of the first field effect device to flow in the second field effect device, and an output coupling device for supplying to an output terminal an output voltage derived from the voltage between a gate and a source terminal of the second field effect device. By converting the voltage over a current sensing resistor into a drain current of the first field effect device, and by converting this drain current into a source-gate voltage of a second field effect device, an output voltage is obtained which is proportional to the voltage over the current sensing resistor. The non-linearity of relation between the gate-source voltage and the drain current of the first field effect device is compensated by the same non-linearity of the second field effect device. An embodiment of the arrangement according to the invention is characterized in that the current measuring device comprises an offset voltage source for offsetting the gate voltage of the first field effect device with respect to the source voltage of the first field effect device. By offsetting the gate voltage of the first field effect device with respect to the source voltage of the first field effect device, it becomes possible to measure currents resulting in voltages across the sense resistor lower than the threshold voltage of the first field effect device. If the offset voltage is selected in a suitable way, it is possible to measure currents having values starting from 0. A further embodiment of the arrangement according to the invention is characterized in that the current measuring device comprises a further offset source for offsetting the output voltage of the current measuring device with respect to the voltage between the gate and the source terminal of the second field effect device. This additional measure enables that an output voltage is obtained which is independent on the value of the offset voltage. This makes it possible to use an offset voltage which is allowed to vary with temperature. This kind of offset voltages can be easily generated on an integrated circuit. A still further embodiment of the invention is characterized in that the current coupling device comprises a cascode field effect device coupled between the drain terminal of the first field effect device and the source terminal of the second field effect device, the gate of the cascode field effect device being coupled to a reference source. The introduction of the cascode field effect device has as result that the output impedance of the first field effect is increased drastically. This results in a reduced influence of the supply voltage on the drain current of the first field effect device. This has as consequence an improved accuracy of the measuring arrangement. The invention will now be explained with reference to the drawing figures. Fig. 1 shows a first embodiment of the current measuring device according to the present invention. Fig. 2 shows a second embodiment of the current measuring device according to the present invention having an improved accuracy. Fig. 3 shows a preferred embodiment of the current measuring device according to the invention. Fig. 4 shows an alternative embodiment of the current measuring device according to the present invention. Fig. 5 shows a block diagram of a telephone terminal according to the invention. In the current measuring device according to Fig. la first terminal VH is connected to a first terminal of a resistor 2 with value R and to a source terminal of a P-MOS transistor 4. Furthermore the first terminal of the resistor 2 is connected to the bulk terminal of the P-MOS transistor. A second terminal VL is connected to a second terminal of the resistor 2, and to a positive terminal of an offset source 6 providing an offset voltage V B . A second terminal of the offset source 6 is connected to a gate terminal of the P-MOS transistor 4. A drain terminal of the P- MOS transistor 4 is connected to an input of a current coupling device 5, which comprises here a simple interconnection. The output of the current coupling device 4 is coupled to the source electrode and the bulk electrode of a P-MOS transistor 10 and to a positive terminal of a further offset source 8. A drain terminal of the P-MOS transistor 10 and a gate terminal of the P-MOS transistor are connected to a ground terminal. The current to be measured is conveyed by the measuring resistor 2. The source-gate voltage of the P-MOS transistor 4 is equal to TR + Vβ. If it is assumed that the threshold value of the P-MOS transistor 4 is equal to Vj and that it is assumed that the P-MOS transistor 4 operates in the saturated region such that the drain current is substantially independent of the drain voltage, for the drain current Ir > of the P-MOS-transistor 4 can be written: W 7 W j ( 1 ) I D = b 0 — (V SG - V T ) 2 = b 0 — (I - R + V B -V T ) 2 ;I -R + V B > V T l I D = 0 ;I - R + V B < V T In (1) ?o is the transconductance constant of the P-MOS transistor, W is the width of the MOS transistor and L is the length of the P-MOS transistor. VQS is the gate-source voltage and Vy is the threshold voltage of the P-MOS transistor. The drain current of the P-MOS transistor 4 is forced into the source terminal of the P-MOS transistor 10. This current will cause a voltage drop VGS' across the P-MOS transistor 10. The properties of the P-MOS transistor 10 are chosen equal to the properties of the P-MOS transistor 4. For the relation between the drain current of the P-MOS transistor and the voltage drop VQS' can be found: W 2 ( 2 ) I S = 0 " ( v SG '- v τ) Because the drain current of the P-MOS transistor 4 and the source current of the P-MOS transistor 10, (1) and (2) can be equated. Consequently, for VQS' is found: (V SG '-Vτ) = (I -R + V B - V τ ) - R + V B > V τ => ( 3 ) V SG '= I -R + V B -R + V B > V τ The output voltage Vo of the current measuring circuit according to Fig. 1 is equal to VSG'-VB- Using (3) gives for Vo a value of TR if I-R+Vβ > VT. Consequently a linear relationship is found between the output voltage Vo and the current I. If Vβ is larger than VT, all values of I larger than 0 can be measured. From the above it can be seen that the output signal Vo is independent of temeperature dependent properties /? 0 and VT of both P- MOS transistors. A prerequisite for this is that the properties of the P-MOS transistors 4 and 10 are equal. This condition is met in general if both P-MOS transistors are integrated on the same die and if they are carefully matched. If it is known beforehand that TR is always larger than Vχ 5 the offset voltage sources 6 and 8 can be dispensed with. If it can be tolerated that the output voltage Vo has an offset with respect to the value TR, the offset voltage 8 can be dispensed with. If the resistor R is removed (or is given a high value) , the circuit according to Fig. 1 can also be used as a voltage measuring device for deriving a voltage which is proportional to a voltage difference between the terminals VH and VT,. In the above it is assumed that the drain current of the P-MOS transistors is independent from the drain-source voltage. In practice this is not completely true. Fig. 2 shows an embodiment of the arrangement according to the invention in which the influence of the drain source voltage of the P-MOS transistors is significantly reduced. In the arrangement according to Fig. 2 the current coupling device 13 comprises a cascode circuit for obtaining a current source with an increased output impedance. The drain of the P-MOS transistor 4 is connected to a source terminal of a P- MOS transistor 15 and to a gate terminal of a P-MOS transistor 11. A drain terminal of the P- MOS transistor 11 is connected to a gate terminal of the P-MOS transistor 15. The drain terminal of the P-MOS transistor 15 is connected to the source terminal of the P-MOS transistor 10 and to an input of a buffer 18. The output of the buffer 18 constitutes the output of the current measuring arrangement. The combination of the P-MOS transistor 11 and 15 clamps the drain voltage of the P-MOS transistor 4 to a value which is equal to the gate-source voltage of the P-MOS transistor 11. Due to the serial connection of the P-MOS transistor 15 with the P-MOS transistor 4 a current source with a high output impedance is obtained. This output impedance if further enhanced, because the combination of the P-MOS transistors 11 and 15 acts as a control circuit which tries to keep the voltage on the drain terminal of the P-MOS transistor 4 constant. In the preferred embodiment of the current measuring circuit according to Fig. 3, the offset sources 6 and 8 are introduced. The offset sources 6 and 8 are formed by the P- MOS transistors 12 and 26 which are coupled via a floating current source 31. The drain-source path of the P-MOS transistor 12 is connected between the terminal V and the gate terminal of the P-MOS transistor 4. The gate terminal of the P-MOS transistor is connected to the drain terminal of said same transistor. The offset voltage Vβ (offset source 6) is now generated between the source and gate terminal of the P-MOS transistor 12. The source of the P-MOS transistor 26 is connected to the floating current source 31 and the gate terminal and the drain terminal of the P-MOS transistor 26 are connected to ground. The floating current source 31 is constituted by a combination of two N-MOS transistors 20 and 30 and two P-MOS transistors 22 and 28. The drain terminal of the N-MOS transistor 20 is connected to the gate terminal of the N-MOS transistor 20 and to the gate terminal of the N-MOS transistor 30. The source terminal of the N-MOS transistor 20 is connected to the source terminal of the P-MOS transistor 22 and the source terminal of the N- MOS transistor 30 is connected to the source terminal of the P-MOS transistor 28. The drain terminal of the P-MOS transistor 22 is connected to the gate terminal of the P-MOS transistor 22, to the gate terminal of the P-MOS transistor 28 and to the source terminal of a P-MOS transistor 24. The P-MOS transistor 24 has its gate terminal connected to its drain terminal. Both terminals are connected to ground. A bias current I provided by a bias current source 18 is forced into a current mirror comprising P-MOS transistors 16 and 14. The output current of the current mirror delivered from the drain terminal of the P-MOS transistor 14, flows into the series connection of N-MOS transistor 20, P-MOS transistor 22 and P-MOS transistor 24. Because the transistors 30, 28 and 26 are chosen to have the same properties as the transistors 20, 22 and 26 respectively, the same voltages will be present on the terminals of the transistors 26 and 24. This will cause a same current I to flow through the series connection of the transistors 26, 28 and 30, and trough the transistor 12. Consequently over the transistors 11 and 26 a same voltage Vβ is generated. The operation of the combination of the transistors 4, 10, 12 and 14 was already explained with reference to Figures 1 and 2. The voltage across the P-MOS transistor 10 is equal to VH-V +V B . Due to the feedback loop around an operational amplifier 32 and a source follower circuit comprising an N-MOS transistor 34 and a resistor 36, it is obtained that the voltage between the input terminals of the operational amplifier is substantially 0. Because the voltage across the P-MOS transistor 26 is equal V B , the output of the source follower is equal to (V H -V L +VB)-V B = V H -V L . In the alternative embodiment of the invention according to Fig. 4, the current coupling means 5 of the circuit according to Fig. 1 are now replaced by current coupling means 41 which comprise a current mirror consisting of N-MOS transistors 40 and 42. The operation of the circuit according to Fig. 4 is similar to the operation of the circuit according to Fig. 1. The operational amplifier 32 is present to provide the circuit with adequate drive capabilities. The voltage across the resistor 2, is converted into a current by the P-MOS transistor 4. This current is mirrored by N-MOS transistor 40 into N-MOS transistor 42, which passes the mirrored current to the P-MOS transistor. In the same way as was discussed with respect to Fig. 1, a voltage which is proportional to the voltage VH-VL will develop across P- MOS transistor 10. It is observed that the output voltage V 0 with respect to ground is inverted with respect to the voltage VH-V and it comprises an offset value Vβ. If this causes problems in following circuits, a simple inverter can be used to invert the output voltage Vo- If the output signal Vo' of the circuit according to Fig. 4 is taken between the gate of the P-MOS transistor 4 and the drain of the P-MOS transistor 10, the offset voltage is completely eliminated when the P-MOS transistors 4 and 10 are matched and the P-MOS transistors 40 and 42 are matched. In the telephone terminal 50 according to fig. 5, the telephone line is connected to a full wave rectifier 52 which provides an unipolar voltage irrespective how the line is connected to the telephone terminal 50. A first output terminal of the full wave rectifier 52 is connected to a first terminal of a resistor 54 and to a source terminal of a P-MOS transistor 58. A second terminal of the resistor 54 is connected to a first terminal of an integrated circuit 60 and to a gate terminal of the P-MOS transistor 58. A drain terminal of the P-MOS transistor 58 is connected to a second input of the integrated circuit 60 and to a first terminal of a current measuring resistor 56. A second terminal of the current measuring resistor 56 is connected to a third terminal of the integrated circuit 60 and to a supply terminal of a keyboard controller 70. If the telephone terminal is off hook, the integrated circuit 60 is provided with a supply voltage via the resistor 54. If the telephone terminal goes off hook, which is detected by the closing of the hook switch 75, a controller 66 in the integrated circuit 60 causes the gate voltage of the P-MOS transistor to be lowered, causing the P-MOS transistor 58 to conduct. This causes additional elements of the integrated circuit 60 and the keyboard controller to be provided with a supply voltage. o A current measuring device 64 which is connected to the second and third terminal of the integrated circuit 60 comprises a circuit according to Fig. 1, 2 or 3 determines the line current from the voltage across the current measuring resistor 56. In response to the value of the line current, the controller 66 sets some parameters of the line interface to a corresponding value. These parameters can be the gain to be used for the microphone 74 and the gain used for the eaφiece 72, but these parameters are also used to achieve optimum side tone suppression. These gain values will increase with decreasing line current, because a lower line current indicates a longer line having more DC resistance, but also having a larger attenuation for the audio signal. The keyboard interface 70 is arranged for decoding the signals received from the keyboard and to generate DTMF signals as used for dialing and other signaling puφoses.

Claims: CLAIMS: 1. Current measuring arrangement for providing an output voltage proportional to a current to be measured on an output terminal, said current measuring device comprising a first field effect device and a second field effect device, characterized in that the current measuring device comprises a current sensing resistor having a first terminal and a second terminal, a gate electrode of the first field effect device being coupled to the first terminal of the current sensing resistor, a source electrode of the first field effect device being coupled to a second terminal of the current sensing resistor, a drain electrode of the first field effect device being coupled to a current coupling device for causing a current dependent on the drain current of the first field effect device to flow in the second field effect device, and an output coupling device for supplying to an output terminal an output voltage derived from the voltage between a gate and a source terminal of the second field effect device. 2. Current measuring arrangement according to claim 1, characterized in that the current measuring device comprises an offset voltage source for offsetting the gate voltage of the first field effect device with respect to the source voltage of the first field effect device. 3. Current measuring arrangement according to claim. 2, characterized in that the current measuring device comprises a further offset source for offsetting the output voltage of the current measuring device with respect to the voltage between the gate and the source terminal of the second field effect device. 4. Current measuring arrangement according to one of the previous claims, characterized in that the current coupling device comprises a cascode field effect device coupled between the drain terminal of the first field effect device and the source terminal of the second field effect device, the gate of the cascode field effect device being coupled to a reference source. 5. Voltage measuring arrangement for providing on an output terminal, an output voltage proportional to a voltage between a first and a second input terminal, said voltage measuring device comprises a first and a second field effect device, a gate electrode of the first field effect device being coupled to the first input terminal, a source electrode of the first field effect device being coupled to the second input, a drain electrode of the first field effect device being coupled to a source electrode of the second field effect device, a drain and a gate electrode of the second field effect device being coupled to a reference voltage, the source electrode of the second field effect device being coupled to the output terminal. 6. Voltage measuring arrangement according to claim 5, characterized in that the voltage measuring device comprises an offset voltage source for offsetting the gate voltage of the first field effect device with respect to the source voltage of the first field effect device 7. Voltage measuring arrangement according to claim 6, characterized in that the current measuring device comprises a further offset source for offsetting the output voltage of the current measuring device with respect to the source electrode of the second field effect device. 8. Voltage measuring arrangement according to one of the claims 5 to 7, characterized in that the arrangement comprises a cascode field effect device coupled between the drain terminal of the first field effect device and the source terminal of the second field effect device, the gate of the cascode field effect device being coupled to a reference source. 9. Telephone terminal comprising a current measuring device according to one of the claims 1 to 4.

Inventors: WANG ZHENHUA, WANG, ZHENHUA
Applicants: KONINKL PHILIPS ELECTRONICS NV, PHILIPS SVENSKA AB, KONINKLIJKE PHILIPS ELECTRONICS N.V., PHILIPS AB
Application year: 1999
Main classification: G01R19
IPC codes: G01R19