IMPROVED INSTRUCTION DECODING USING A PARALLEL DECODE ALGORITHM

Abstract: A predecode unit (17) is configured to predecode a fixed number of instruction bytes of variable length instructions per clock cycle. The predecode unit outputs predecode bits which identify whether any of the predecoded instruction bytes are the start byte of an instruction. An instruction alignment unit (18) then uses the start bits to dispatch the variable byte-length instructions to a plurality of decode units (20) that form fixed issue positions within a processor. In one embodiment, the predecode unit identifies a plurality of length vectors. Each length vector is associated with one of the instruction bytes predecoded in a clock cycle. The length vector identifies the length of an instruction if an instruction starts at the instruction byte corresponding to the length vector. A tree circuit (312) determines in which instruction bytes instructions start.

Description: Title: IMPROVED INSTRUCTION DECODING USING A PARALLEL DECODE ALGORITHM BACKGROUND OF THE INVENTION 1. Technical Field This invention relates to superscalar microprocessors and, more particularly, to the predecoding of vaπable byte-length computer instructions within high performance and high frequency superscalar microprocessors. 2 Background Art Superscalar microprocessors are capable of attaining performance characteristics which surpass those of conventional scalar processors by allowing the concurrent execution of multiple instructions. Due to the widespread acceptance of the x86 family of microprocessors, efforts have been undertaken by microprocessor manufacturers to develop superscalar microprocessors that execute x86 instructions. Such superscalar microprocessors achieve relatively high performance characteristics while advantageously maintaining backwards compatibility with the vast amount of existing software developed for previous microprocessor generations such as the 8086, 80286, 80386, 80486, Pentium™ , K5™, Pentium II™, and K6™ The x86 instruction set is relatively complex and is characterized by a plurality of variable byte-length instructions A generic format illustrative of the x86 instruction set is shown m Figure 1A. As illustrated in the figure, an x86 instruction consists of from one to fourteen optional prefix bytes 102, followed by an operation code (opcode) field 104, an optional addressing mode (ModR/M) byte 106, an optional scale-mdex-base (SIB) byte 108, an optional displacement field 110, and an optional immediate data field 112. The opcode field 104 defines the basic operation for a particular instruction. The default operation of a particular opcode may be modified by one or more prefix bytes For example, a prefix byte may be used to change the address or operand size for an instruction, to override the default segment used m memory addressing, or to instruct the processor to repeat a string operation a number of times The opcode field 104 follows the prefix bytes 102, if any, and may be one or two bytes in length. The addressing mode (ModR/M) byte 106 specifies the registers used as well as memory addressing modes. The register field of the ModR/M byte alternatively may be used as an opcode extension, or sub-opcode. The scale-mdex-base (SIB) byte 108 is used only in 32-bit base-relative addressing usmg scale and index factors. A base field ofthe SIB byte specifies which register contains the base value for the address calculation, and an mdex field specifies which register contains the mdex value. A scale field specifies the power of two by which the mdex value will be multiplied before being added, along with any displacement, to the base value. The next instruction field is the optional displacement field 110. which may be from one to four bytes m length. The displacement field 110 contains a constant used in address calculations. The optional immediate field 1 12, which may also be from one to six bytes in length, contains a constant used as an instruction operand. The 80286 sets a maximum length for an instruction at 10 bytes, while the 80386, 80486, Pentium™, K5™, Pentium II™. and K6™ allow instruction lengths of up to 15 bytes Referring now to Figure IB, several different vaπable byte-length x86 instruction formats are shown The shortest x86 instruction is only one byte long, and comprises a single opcode byte as shown in format (a) For certam mstructions, the byte contammg the opcode field also contams a register field as shown m formats (b), (c) and (e). Format 0) shows an instruction with two opcode bytes. An optional ModR/M byte follows opcode bytes m formats (d), (f), (h), and 0)- Immediate data follows opcode bytes m formats (e), (g), (l), and (k), and follows a ModR/M byte in formats (f) and (h). Figure IC illustrates several possible addressing mode formats (a)-(h) Formats (c), (d), (e), (g), and (h) contam ModR/M bytes with offset (i.e., displacement) information. An SIB byte is used in formats (f), (g), and (h). The complexity ofthe x86 mstruction set poses difficulties in implementing high performance x86 compatible superscalar microprocessors. One difficulty aπses from the fact that mstructions must be aligned with respect to the parallel-coupled instruction decoders of such processors before proper decode can be effectuated In contrast to most RISC mstruction formats, since the x86 mstruction set consists of vaπable byte- length mstructions, the start bytes of successive mstructions within a lme are not necessaπly equally spaced, and the number of mstructions per lme is not fixed. As a result, employment of simple, fixed- length shifting logic cannot in itself solve the problem of mstruction alignment. Superscalar microprocessors have been proposed that employ mstruction predecodmg techniques to help solve the problem of quickly aligning, decodmg and executing a plurality of vaπable byte-length instructions in parallel. In one such superscalar microprocessor, when mstructions are written withm the mstruction cache from an external mam memory, a predecoder appends several predecode bits (referred to collectively as a predecode tag) to each byte. These bits may mdicate whether the byte is the start and/or end byte of an x86 instruction, the number of microinstructions required to implement the x86 mstruction, and the location of opcodes and prefixes. Unfortunately, predecode units expeπence the same difficulties in aligning mstructions as decode units. In one implementation, a predecode unit attempts to predecode one instruction per clock cycle. A multiplexer routes instruction bytes to the predecode unit, which determines the length of the mstruction and routes the mstruction length to the multiplexer, which routes the bytes subsequent to the previously predecoded mstruction to the predecode unit to be predecoded m the next clock cycle. Because the mstruction length is vaπable, the multiplexer must be able to shift the mstruction bytes from 1 to 15 bytes, which mcreases the complexity of the multiplexer Further, the time to detect the length ofthe instruction, route the mstruction length to the multiplexer, and shift the mstruction bytes by the appropπate number of positions is a tune consuming operation that may limit the performance of the predecode unit and consequently limit the performance ofthe microprocessor. DISCLOSURE OF INVENTION The problems outlmed above are in large part solved by a predecode unit configured to predecode a fixed number of mstruction bytes of vaπable length mstructions per clock cycle. The predecode unit outputs predecode bits which identify whether any ofthe predecoded mstruction bytes are the start byte of an mstruction. An mstruction alignment unit then uses the start bits to dispatch the vaπable byte-length instructions to a plurality of decode units that form fixed issue positions withm a processor By predecodmg a fixed number of instruction bytes per clock cycle, the multiplexer that routes instruction bytes to the predecode umt shifts mstructions bytes by a fixed number, which greatly simplifies the multiplexer. Furthermore, the multiplexing operation may be performed m parallel with the predecode operation because the number of byte positions by which the multiplexer shifts the mstruction bytes is mdependent ofthe predecode operation. Both of these features accommodate very high frequencies of operation. In one embodiment, the predecode unit identifies a plurality of length vectors. Each length vector is associated with one of the mstruction bytes predecoded m a clock cycle. The length vector identifies the length of an mstruction if an mstruction starts at the mstruction byte correspondmg to the length vector. A tree circuit determines in which mstruction bytes mstructions start The length vector correspondmg to the mstruction byte in which an mstruction starts identifies the mstruction byte m which a subsequent mstruction starts (i.e., the subsequent start byte) If the subsequent start byte is outside of the fixed number of mstruction bytes predecoded durmg that clock cycle, the tree circuit stores the information until the subsequent start byte is predecoded. The length vector associated with the subsequent start byte is then used to determine the instruction byte in which the next mstruction starts. By utilizing the predecoded information from the predecode unit, the instruction alignment unit may be implemented with a relatively small number of cascaded levels of logic gates, thus accommodating very high frequencies of operation Instruction alignment to decode units may further be accomplished with relatively few pipeline stages. Broadly speaking, the present invention contemplates a predecode unit mcludmg a decode circuit, a prefix find circuit, a prefix accumulator and a tree circuit. The decode circuit is configured to decode a fixed number of instruction bytes m a clock cycle and to output a plurality of mstruction length vectors The prefix find circuit is configured to receive said fixed number of mstruction bytes and to identify which of said fixed number of mstruction bytes are prefixes The prefix accumulator circuit is coupled to said decode circuit and said prefix find circuit, and is configured to output a plurality of position length vectors which identify an instruction length for potential start bytes. The tree circuit is coupled to said prefix accumulation circuit, and is configured to output a plurality of start bits The start bits identify one or more start bytes withm said fixed number of instruction bytes. The present invention further contemplates a method of predecodmg mstruction bytes of vaπable-byte length instructions to identify start bytes of vaπable length instructions compnsmg. predecodmg a fixed number of mstruction bytes starting with an instruction byte identified by a predecode pomter, wherein said predecodmg identifies said start bytes withm said fixed number of mstruction bytes; mcrementmg said predecode pomter by said fixed number of mstruction bytes; and predecodmg said fixed number of mstruction bytes starting with an mstruction byte identified by said predecode pointer. The present invention still further contemplates a method of predecodmg mstruction bytes of variable- byte length mstructions to identify start bytes of variable length mstructions compnsmg: determining a first instruction length if a start byte is m a first byte position; determining a second mstruction length if said start byte is m a second byte position, determining a location of a first start byte based upon an mstruction byte position of a previous start byte and an mstruction length associated with said previous start position; and selecting said first instruction length if said first start byte is m said first byte position and selectmg said second mstruction byte length if said first start byte is in said second byte position. BRIEF DESCRIPTION OF DRAWINGS Other objects and advantages ofthe mvention will become apparently upon reading the following detailed descπption and upon reference to the accompanymg drawings m which: Figure 1A is a diagram that illustrates a genenc x86 mstruction set format; Figure IB is a diagram that illustrates several different vanable byte-length x86 mstruction formats; Figure IC is a diagram that illustrates several possible x86 addressing mode formats; Figure 2 is a block diagram of a superscalar microprocessor that mcludes a predecode unit and an mstruction alignment unit to forward multiple mstructions to three decode units; Figure 3 is a block diagram of a decode unit accordmg to one embodiment ofthe present mvention; Figure 4 is a block diagram of a portion of a predecode unit accordmg to one embodiment ofthe present mvention; Figure 5 is a block diagram of a prefix find circuit of a predecode unit accordmg to one embodiment of the present mvention; Figure 6 is a block diagram of a flat decode circuit of a predecode unit accordmg to one embodiment of the present mvention; Figure 6A is a diagram of a length vector accordmg to one embodiment ofthe present mvention; Figure 7 is a block diagram of a prefix accumulator of a predecode umt accordmg to one embodiment of the present mvention, Figure 8 is a block diagram of a tree circuit of a predecode unit accordmg to one embodiment of the present mvention; Figure 9 is a circuit diagram of a portion ofthe tree circuit of Figure 8 accordmg to one embodiment of the present invention; Figure 10 is a circuit diagram of an alternate design of a portion ofthe tree circuit of Figure 8 accordmg to one embodiment of the present invenuon; Figure 11 is a circuit diagram of an operand prefix decode circuit of a prefix find circuit accordmg to one embodiment ofthe present mvention; Figure 12 is a circuit diagram of an accumulate decode circuit of a prefix find circuit according to one embodiment ofthe present invention; Figure 13 is a circuit diagram of a displacement/immediate accumulator of a prefix accumulator accordmg to one embodiment of the present mvention; and Figure 14 is a computer system implementing the microprocessor of Figure 2 accordmg to one embodiment ofthe present mvention. While the mvention is susceptible to vaπous modifications and alternative forms, specific embodiments thereof are shown by way of example m the drawmgs and will herem be descnbed m detail. It should be understood, however, that the drawmgs and detailed descnption thereto are not mtended to limit the mvention to the particular form disclosed, but on the contrary, the mtention is to cover all modifications, equivalents and alternatives falling within the spiπt and scope ofthe present mvention as defined by the appended claims. MODES FOR CARRYING OUT THE INVENTION Turning now to Figure. 2, a block diagram of one embodiment of a microprocessor 10 is shown. Other embodiments are possible and contemplated. As shown m Figure 2, microprocessor 10 mcludes a prefetch unit 12, a branch prediction unit 14, an mstruction cache 16, a predecode umt 17, an mstruction alignment unit 18, a plurality of decode units 20A-20C, a plurality of reservation stations 22A-22C, a plurality of functional umts 24A-24C, a load/store unit 26, a data cache 28, a register file 30, a reorder buffer 32, and an MROM unit 34. Elements referred to herem with a particular reference number followed by a letter may be collectively referred to by the reference number alone. For example, decode units 20A-20C may be collectively refeπed to as decode units 20 Prefetch unit 12 is coupled to receive mstructions from a mam memory subsystem (not shown), and is further coupled to instruction cache 16 Branch prediction unit 14 is coupled to instruction cache 16 and predecode unit 17 Further, branch prediction unit 14 is coupled to decode units 20 and functional units 24 Instruction cache 16 is coupled to predecode unit 17, which is coupled to mstruction alignment unit 18. Instruction cache is further coupled to MROM unit 34 and mstruction alignment unit 18. Instruction alignment unit 18 is m turn coupled to decode units 20. Each decode unit 20A-20C is coupled to load/store unit 26 and to respective reservation stations 22A-22C. Reservation stations 22A-22C are further coupled to respective functional units 24A-24C. Additionally, decode units 20 and reservation stations 22 are coupled to register file 30 and reorder buffer 32. Functional units 24 are coupled to load store umt 26, register file 30, and reorder buffer 32 as well. Data cache 28 is coupled to load/store unit 26 and to the mam memory subsystem Finally, MROM unit 34 is coupled to decode units 20 Generally speakmg, predecode unit 17 predecodes a fixed number of mstruction bytes per clock cycle. In one embodiment, the predecode unit predecodes four mstmction bytes per clock cycle. The predecode unit determines a length vector for each ofthe four mstruction bytes. The length vector identifies the length of an mstruction if an mstruction starts m the mstmction byte correspondmg to the length vector. Based on the length vector of an mstmction byte m which an instruction starts, the mstruction byte m which an subsequent instruction starts may be determined. If the mstruction byte m which a subsequent mstruction starts is not withm the mstruction bytes cuπently bemg predecoded, a tree circuit stores the information until the subsequent mstmction byte is predecoded. It is noted that the predecode unit may additionally provide predecode bits which identify the end of an mst ction, the type of mstmction, and other information. Instruction cache 16 is a high speed cache memory provided to store mstructions. Instructions are fetched from mstmction cache 16 and dispatched to decode umts 20. In one embodiment, mstmction cache 16 is configured to store up to 64 kilobytes of instructions m a two-way set associative structure having 64 byte lmes (a byte comprises 8 binary bits). Instruction cache 16 may additionally employ a way prediction scheme m order to speed access times to the mstmction cache. Instead of accessmg tags identifying each line of instructions and comparing the tags to the fetch address to select a way, mstruction cache 16 predicts the way that is accessed. In this manner, the way is selected pnor to accessmg the mstruction storage. The access time of mstmction cache 16 may be similar to a direct-mapped cache. A tag companson is performed and, if the way prediction is lncoπect, the coπect mstructions are fetched and the incorrect mstructions are discarded. It is noted that mstruction cache 16 may be implemented as a fully associative, set associative, or direct-mapped configuration Instructions are fetched from mam memory and stored mto mstruction cache 16 by prefetch unit 12 Instructions may be prefetched pnor to the request thereof from mstmction cache 16 m accordance with a prefetch scheme. A vaπety of prefetch schemes may be employed by prefetch unit 12 Prefetch unit 12 stores the prefetched mstruction to mstmction cache 16 Instruction cache 16 conveys mstructions to mstmction alignment 18. If the mstructions received from instruction cache 16 have not been predecoded, the instructions are transferred to predecode unit 17 Predecode unit 17 may generate predecode bits for each byte ofthe instructions The predecode bits are conveyed to both mstmction alignment unit 18 and mstmction cache 16 Instruction alignment unit 18 uses the predecode data to align the mstruction for dispatch to decode units 20 Instruction cache 16 stores the predecode data with the mstmctions The next tune those mstmctions are conveyed to mstmction alignment unit 18, the predecode bits are conveyed with the mstmctions, and transfer to predecode unit 17 may not be required In one embodiment, predecode unit 17 generates three predecode bits per mstmction byte a start bit, an end bit, and a functional bit The predecode bits form tags indicative ofthe boundaπes of each mstmction The predecode tags may also convey additional information such as whether a given mstruction can be decoded directly by decode units 20 or whether the mstmction is executed by invoking a microcode procedure controlled by MROM unit 34, as will be descπbed m greater detail below Still further, predecode unit 17 may be configured to detect branch mstructions and to store branch prediction information coπesponding to the branch mstructions mto branch prediction unit 14 One encodmg ofthe predecode tags for an embodiment of microprocessor 10 employing a variable byte length mstmction set will next be descnbed A vaπable byte length mstruction set is an mstmction set m which different mstructions may occupy differing numbers of bytes An exemplary variable byte length mstmction set employed by one embodiment of microprocessor 10 is the x86 mstmction set In the exemplary encodmg, if a given byte is the first byte of an mstruction, the start bit for that byte is set If the byte is the last byte of an mstmction, the end bit for that byte is set Instructions which may be directly decoded by decode units 20 are referred to as "fast path" instructions The remaining x86 mstmctions are refeπed to as MROM mstructions, accordmg to one embodiment For fast path mstmctions, the functional bit is asserted for the first instruction byte Alternatively, for MROM mstructions, the functional bit is unasserted for the first instruction byte The type of mstmction may be determined by exammmg the functional bit coπesponding to the first mstmction byte Prefix bytes are identified by an asserted functional bit m the position coπesponding to the subsequent mstmction byte For example, if the first mstmction byte is a prefix byte the second functional bit is asserted The opcode of an mstmction may thereby be located withm an instruction as the byte associated with the last asserted functional bit m the mstmction For example, a fast path instruction including two prefix bytes, an opcode, a ModR/M byte, and an immediate byte would have start, end, and functional bits as follows Start bits 10000 End bits 00001 Functional bits 01100 Accordmg to one particular embodiment, early identification of an mstmction that mcludes a scale- mdex-base (SIB) byte is advantageous for MROM unit 34 For such an embodiment, if an mstmction includes at least two bytes after the opcode byte, the functional bit for the ModR/M byte indicates the presence of an SIB byte If the functional bit for the ModR/M byte is set, then an SIB byte is present Alternatively, if the functional bit for the ModR/M byte is clear, then an SIB byte is not present MROM mstmctions are mstmctions which are determined to be too complex for decode by decode units 20 MROM mstmctions are executed by invoking MROM unit 34 More specifically, when an MROM instruction is encountered, MROM unit 34 parses and issues the mstmction mto a subset of defined fast path instructions to effectuate the desired operation. MROM unit 34 dispatches the subset of fast path mstmctions to decode units 20 Microprocessor 10 employs branch prediction m order to speculatively fetch mstmctions subsequent to conditional branch mstmctions. Branch prediction unit 14 is mcluded to perform branch prediction operations. In one embodiment, up to two branch target addresses are stored with respect to each 16 byte portion of each cache lme in mstmction cache 16 Predecode unit 17 determines initial branch targets when a particular lme is predecoded. Subsequent updates to the branch targets coπesponding to a cache lme may occur due to the execution of mstructions withm the cache lme. Instruction cache 16 provides an indication ofthe mstruction address being fetched, so that branch prediction unit 14 may determine which branch target addresses to select for forming a branch prediction. Decode units 20 and functional units 24 provide update information to branch prediction unit 14 Because branch prediction unit 14 stores two targets per 16 byte portion ofthe cache lme, some branch mstmctions withm the lme may not be stored m branch prediction unit 14. Decode units 20 detect branch mstmctions which were not predicted by branch prediction unit 14. Functional units 24 execute the branch mstmctions and determine if the predicted branch direction is mcoπect. The branch direction may be "taken", m which subsequent mstructions are fetched from the target address ofthe branch mstmction Conversely, the branch direction may be "not taken", m which subsequent mstmctions are fetched from memory locations consecutive to the branch mstmction. When a mispredicted branch mstruction is detected, mstmctions subsequent to the mispredicted branch are discarded from the vaπous units of microprocessor 10 A vanety of suitable branch prediction algorithms may be employed by branch prediction unit 14 Instructions fetched from instruction cache 16 are conveyed to mst ction alignment unit 18. As mstmctions are fetched from mstmction cache 16, the coπesponding predecode data is scanned to provide information to mstruction alignment unit 18 (and to MROM unit 34) regardmg the mstmctions bemg fetched. Instruction alignment unit 18 utilizes the scanning data to align an mstmction to each of decode units 20. In one embodiment, instruction alignment unit 18 aligns mstmctions from three sets of eight mstmction bytes to decode units 20. Instructions are selected mdependently from each set of eight mstmction bytes mto preliminary issue positions The preliminary issue positions are then merged to a set of aligned issue positions coπesponding to decode units 20, such that the aligned issue positions contam the three mstmctions which are pnor to other instructions withm the prelunmary issue positions m program order Decode umt 20A receives an mstruction which is pnor to mstmctions concuπently received by decode units 20B and 20C (in program order) Similarly, decode unit 20B receives an mstmction which is pnor to the mstmction concuπently received by decode unit 20C m program order. Decode units 20 are configured to decode mstmctions received from mstruction alignment unit 18 Register operand information is detected and routed to register file 30 and reorder buffer 32. Additionally, if the mstmctions require one or more memory operations to be performed, decode units 20 dispatch the memory operations to load/store unit 26. Each mstmction is decoded mto a set of control values for functional units 24, and these control values are dispatched to reservation stations 22 along with operand address information and displacement or immediate data which may be mcluded with the mstmction. Microprocessor 10 supports out of order execution, and thus employs reorder buffer 32 to keep track of the oπgmal program sequence for register read and wnte operations, to implement register renaming, to allow for speculative mstmction execution and branch misprediction recovery, and to facilitate precise exceptions A temporary storage location withm reorder buffer 32 is reserved upon decode of an mstruction that mvolves the update of a register to thereby store speculative register states. If a branch prediction is mcoπect, the results of speculatively-executed mstmctions along the mispredicted path can be invalidated m the buffer before they are wπtten to register file 30. Similarly, if a particular mstmction causes an exception, mstmctions subsequent to the particular mstmction may be discarded. In this manner, exceptions are "precise" (i.e. mstmctions subsequent to the particular mstmction causmg the exception are not completed pnor to the exception). It is noted that a particular mstmction is speculatively executed if it is executed pnor to mstmctions which precede the particular mstmction m program order Precedmg mstructions may be a branch mstmction or an exception- causing mstmction, in which case the speculative results may be discarded by reorder buffer 32 The mstmction control values and immediate or displacement data provided at the outputs of decode units 20 are routed directly to respective reservation stations 22. In one embodiment, each reservation station 22 is capable of holdmg mstmction information (I e., instruction control values as well as operand values, operand tags and/or immediate data) for up to three pending mstmctions awaiting issue to the coπespondmg functional unit It is noted that for the embodiment of Figure 1, each reservation station 22 is associated with a dedicated functional unit 24 Accordmgly, three dedicated "issue positions" are formed by reservation stations 22 and functional umts 24. In other words, issue position 0 is formed by reservation station 22 A and functional unit 24A Instructions aligned and dispatched to reservation station 22A are executed by functional unit 24A. Similarly, issue position 1 is formed by reservation station 22B and functional unit 24B; and issue position 2 is formed by reservation station 22C and functional unit 24C. Upon decode of a particular mstmction, if a required operand is a register location, register address information is routed to reorder buffer 32 and register file 30 simultaneously. Those of skill m the art will appreciate that the x86 register file mcludes eight 32 bit real registers (i.e., typically refeπed to as EAX, EBX, ECX, EDX, EBP, ESI, EDI and ESP) In embodiments of microprocessor 10 which employ the x86 microprocessor architecture, register file 30 comprises storage locations for each ofthe 32 bit real registers. Additional storage locations may be mcluded withm register file 30 for use by MROM unit 34 Reorder buffer 32 contams temporary storage locations for results which change the contents of these registers to thereby allow out of order execution. A temporary storage location of reorder buffer 32 is reserved for each mstmction which, upon decode, is determined to modify the contents of one of the real registers. Therefore, at vaπous pomts during execution of a particular program, reorder buffer 32 may have one or more locations which contam the speculatively executed contents of a given register If following decode of a given instruction it is determined that reorder buffer 32 has a previous location or locations assigned to a register used as an operand in the given mstmction, the reorder buffer 32 forwards to the coπespondmg reservation station either 1) the value m the most recently assigned location, or 2) a tag for the most recently assigned location if the value has not yet been produced by the functional unit that will eventually execute the previous mstmction. If reorder buffer 32 has a location reserved for a given register, the operand value (or reorder buffer tag) is provided from reorder buffer 32 rather than from register file 30 If there is no location reserved for a required register in reorder buffer 32, the value is taken directly from register file 30 If the operand coπesponds to a memory location, the operand value is provided to the reservation station through load/store unit 26. In one particular embodiment, reorder buffer 32 is configured to store and manipulate concuπently decoded mstmctions as a unit. This configuration will be refeπed to herem as "lme-oπented". By manipulating several instructions together, the hardware employed withm reorder buffer 32 may be simplified For example, a lme-oπented reorder buffer mcluded in the present embodiment allocates storage sufficient for mstruction information pertaining to three instructions (one from each decode unit 20) whenever one or more mstructions are dispatched by decode units 20 By contrast, a variable amount of storage is allocated m conventional reorder buffers, dependent upon the number of mstmctions actually dispatched A comparatively larger number of logic gates may be required to allocate the vanable amount of storage When each of the concuπently decoded mstmctions has executed, the mstmction results are stored into register file 30 simultaneously The storage is then free for allocation to another set of concuπently decoded instructions Additionally, the amount of control logic circuitry employed per mstmction is reduced because the control logic is amortized over several concuπently decoded mstructions A reorder buffer tag identifying a particular mstmction may be divided into two fields a lme tag and an offset tag The line tag identifies the set of concuπently decoded mstmctions including the particular mst ction, and the offset tag identifies which mstruction withm the set coπesponds to the particular mstmction It is noted that storing mstmction results mto register file 30 and freeing the coπesponding storage is refeπed to as "retiπng" the mstmctions It is further noted that any reorder buffer configuration may be employed m vaπous embodiments of microprocessor 10 As noted earlier, reservation stations 22 store mstmctions until the mstmctions are executed by the coπespondmg functional unit 24 An mstmction is selected for execution if (l) the operands of the mstmction have been provided, and (u) the operands have not yet been provided for mstmctions which are withm the same reservation station 22A-22C and which are pnor to the mstruction m program order It is noted that when an mstmction is executed by one of the functional units 24, the result of that instruction is passed directly to any reservation stations 22 that are waitmg for that result at the same time the result is passed to update reorder buffer 32 (this technique is commonly refeπed to as "result forwarding") An mstmction may be selected for execution and passed to a functional unit 24A-24C during the clock cycle that the associated result is forwarded Reservation stations 22 route the forwarded result to the functional unit 24 in this case In one embodiment, each ofthe functional units 24 is configured to perform mteger anthmetic operations of addition and subtraction, as well as shifts, rotates, logical operations, and branch operations The operations are performed in response to the control values decoded for a particular instruction by decode units 20 It is noted that a floating point unit (not shown) may also be employed to accommodate floating point operations The floating point unit may be operated as a coprocessor, receivmg mstructions from MROM unit 34 and subsequently communicating with reorder buffer 32 to complete the mstmctions Additionally, functional units 24 may be configured to perform address generation for load and store memory operations performed by load/store unit 26 In one particular embodiment, each functional unit 24 may compnse an address generation unit for generatmg addresses and an execute unit for performing the remaining functions The two units may operate independently upon different instructions duπng a clock cycle Each ofthe functional units 24 also provides information regardmg the execution of conditional branch instructions to the branch prediction unit 14 If a branch prediction was mcoπect, branch prediction unit 14 flushes mstmctions subsequent to the mispredicted branch that have entered the mstmction processing pipeline, and causes fetch of the required mstmctions from mstmction cache 16 or mam memory It is noted that in such situations, results of mstmctions in the oπgmal program sequence which occur after the mispredicted branch instruction are discarded, mcludmg those which were speculatively executed and temporanly stored in load/store unit 26 and reorder buffer 32. It is further noted that branch execution results may be provided by functional units 24 to reorder buffer 32, which may indicate branch mispredictions to functional units 24 Results produced by functional units 24 are sent to reorder buffer 32 if a register value is bemg updated, and to load/store unit 26 if the contents of a memory location are changed If the result is to be stored in a register, reorder buffer 32 stores the result m the location reserved for the value ofthe register when the mstmction was decoded A plurality of result buses 38 are mcluded for forwardmg of results from functional units 24 and load/store unit 26 Result buses 38 convey the result generated, as well as the reorder buffer tag identifying the instruction bemg executed Load/store unit 26 provides an interface between functional units 24 and data cache 28. In one embodiment, load/store unit 26 is configured with a load/store buffer having eight storage locations for data and address information for pendmg loads or stores. Decode units 20 arbitrate for access to the load/store unit 26 When the buffer is full, a decode unit must wait until load/store unit 26 has room for the pending load or store request information. Load/store unit 26 also performs dependency checkmg for load memory operations agamst pending store memory operations to ensure that data coherency is mamtamed. A memory operation is a transfer of data between microprocessor 10 and the main memory subsystem. Memory operations may be the result of an mstruction which utilizes an operand stored m memory, or may be the result of a load/store mstmction which causes the data transfer but no other operation Additionally, load/store unit 26 may include a special register storage for special registers such as the segment registers and other registers related to the address translation mechanism defined by the x86 microprocessor architecture. In one embodiment, load/store unit 26 is configured to perform load memory operations speculatively Store memory operations are performed in program order, but may be speculatively stored mto the predicted way. If the predicted way is mcoπect, the data prior to the store memory operation is subsequently restored to the predicted way and the store memory operation is performed to the coπect way In another embodiment, stores may be executed speculatively as well. Speculatively executed stores are placed mto a store buffer, along with a copy ofthe cache lme prior to the update If the speculatively executed store is later discarded due to branch misprediction or exception, the cache lme may be restored to the value stored m the buffer. It is noted that load store unit 26 may be configured to perform any amount of speculative execution, including no speculative execution Data cache 28 is a high speed cache memory provided to temporarily store data bemg transfeπed between load/store unit 26 and the mam memory subsystem. In one embodiment, data cache 28 has a capacity of stonng up to 64 kilobytes of data m an eight way set associative stmcture. Similar to mstmction cache 16, data cache 28 may employ a way prediction mechanism It is understood that data cache 28 may be implemented in a variety of specific memory configurations, mcludmg a set associative configuration In one particular embodiment of microprocessor 10 employing the x86 microprocessor architecture, mstmction cache 16 and data cache 28 are physically addressed and linearly mdexed It is noted that a physically addressed cache stores physical address tags. Turning now to Figure 3, a block diagram of one embodiment of decode units 20B and 20C is shown Other embodiments are possible and contemplated. Each decode unit 20 receives an mstruction from mstruction alignment unit 18 Additionally, MROM unit 34 is coupled to each decode unit 20 for dispatchmg fast path instructions coπesponding to a particular MROM mstmction Decode unit 20B comprises early decode unit 40B, multiplexer 42B, and opcode decode unit 44B Similarly, decode unit 20C mcludes early decode unit 40C, multiplexer 42C, and opcode decode unit 44C Certain mstmctions m the x86 mstmction set are both fairly complicated and frequently used In one embodiment of microprocessor 10, such mstmctions mclude more complex operations than the hardware mcluded within a particular functional unit 24A-24C is configured to perform Such mstmctions are classified as a special type of MROM mstmction refeπed to as a "double dispatch" mstmction These mstmctions are dispatched to a pair of opcode decode units 44 It is noted that opcode decode units 44 are coupled to respective reservation stations 22 Each of opcode decode units 44A-44C forms an issue position with the coπespondmg reservation station 22A-22C and functional unit 24A-24C Instructions are passed from an opcode decode unit 44 to the coπespondmg reservation station 22 and further to the coπespondmg functional unit 24 Multiplexer 42B is mcluded for selectmg between the mstmctions provided by MROM unit 34 and by early decode unit 40B Duπng times in which MROM unit 34 is dispatchmg mstmctions, multiplexer 42B selects instructions provided by MROM unit 34 At other times, multiplexer 42B selects mstmctions provided by early decode unit 40B Similarly, multiplexer 42C selects between mstmctions provided by MROM unit 34, early decode unit 40B, and early decode unit 40C The mstmction from MROM unit 34 is selected during times in which MROM unit 34 is dispatchmg mstmctions Duπng times m which the early decode unit withm decode unit 20A (not shown) detects a double dispatch mstmction, the mstmction from early decode unit 40B is selected by multiplexer 42C Otherwise, the mstruction from early decode umt 40C is selected Selecting the mstmction from early decode unit 40B mto opcode decode unit 44C allows a fast path instruction decoded by decode unit 20B to be dispatched concuπently with a double dispatch mstruction decoded by decode unit 20A Accordmg to one embodiment employing the x86 mstmction set, early decode units 40 perform the following operations (I) merge the prefix bytes ofthe mstmction mto an encoded prefix byte, (n) decode source and destination flags, (in) decode the source and destination operands which are register operands and generate operand size information, and (IV) determine the displacement and/or immediate size so that displacement and immediate data may be routed to the opcode decode unit Opcode decode units 44 are configured to decode the opcode ofthe mstmction, producmg control values for functional unit 24 Displacement and immediate data are routed with the control values to reservation stations 22 Smce early decode units 40 detect operands, the outputs of multiplexers 42 are routed to register file 30 and reorder buffer 32 Operand values or tags may thereby be routed to reservation stations 22 Additionally, memory operands are detected by early decode units 40 Therefore, the outputs of multiplexers 42 are routed to load/store unit 26 Memory operations coπespondmg to mstmctions having memory operands are stored by load/store unit 26 Turning now to Figure 4, a block diagram of a portion of predecode unit 17 accordmg to one embodiment ofthe present mvention is shown In the illustrated embodiment, the circuitry for generating start bits that identify mstmction start bytes (I e , the mstmction bytes m which mstructions start) is shown Predecode unit 17 may additionally include circuitry for generatmg other predecode bits, which is not shown The illustrated portion of prefetch unit 17 includes an mstruction buffer 302, a multiplexer 304, a prefix find circuit 306, a flat decoder 308, a prefix accumulator 310, a tree circuit 312, and an output generation circuit 314. Instruction buffer 302 receives mstruction bytes from mstmction alignment unit 18 (not shown). Multiplexer 304 routes a plurality of mstmction bytes from mstruction buffer 302 to prefix find circuit 306 and flat decoder 308. Prefix find circuit 306 outputs control signals to prefix accumulator 310 indicating which mstmction bytes are prefixes and whether those prefix bytes effect the type or length of an mstruction. Multiplexer 304 additionally routes mstmction bytes to flat decoder 308. Flat decoder 308 outputs a plurality of length vectors. Each length vector coπesponds to an mstruction byte. The length vectors identify the length of an mstruction if an mstmction starts m the mstmction byte coπesponding to the length vector. In one embodiment, the length vectors output by flat decoder 308 do not take into account prefix bytes. In one particular embodiment, flat decoder 308 outputs two length vectors for each mstmction byte. A first length vector identifies the length of an mstmction if no escape prefix byte is associated with the instruction A second length vector identifies the length of an mstmction if an escape prefix byte is associated with the mstruction Prefix accumulator 310 receives the length vectors from flat decode 308 and the prefix information from prefix find circuit 306. Prefix accumulator 310 combines this information to determine the length of an mstmction takmg into account prefix bytes. Prefix accumulator 310 outputs a plurality of length vectors to tree circuit 312. Each length vector identifies the length of an mstmction if an mstmction starts m the mstmction byte coπespondmg to the length vector. Tree circuit 312 identifies mstmction start bytes based upon mstmction start bytes and the length of instructions starting at those start bytes. An mstruction start byte may be identified by a previous mstruction start byte and the length of that mstmction, or may be identified by a source external to the predecode unit, such as a branch coπecbon unit. The start byte of a subsequent mstruction may be an mstruction byte not present m the mstmction bytes cuπently bemg predecoded. In this event, tree circuit 312 stores information indicative of the location ofthe mstruction start byte and identifies that start byte when it is predecoded. Tree circuit 312 outputs a bit, called a start bit, for each mstmction byte. The start bits mdicate whether that mstmction byte is a start byte. The start bits are provided to output generation circuit 314, which performs cleanup operations such as detecting branches, illegal opcodes, page faults and muxmg of previously generated predecode bits. In the illustrated embodiment, a fixed number of mstmction bytes are predecoded each clock cycle. Decodmg a fixed number of mstmction bytes advantageously reduces the complexity of multiplexer 304 and decreases the latency ofthe predecode circuit. In one embodiment, the number of mstmction bytes predecoded per clock cycle is equal to the number of mstmction bytes prefetched per clock cycle. In a prefeπed embodiment, four mstmction bytes are predecoded per clock cycle. In one embodiment, mstruction buffer 302 mcludes a predecode pomter that identifies a first mstmction byte to be predecoded. The predecode pomter is incremented each clock cycle. Accordmgly, multiplexer 304 routes four mstmction bytes to prefix find 306 m a first clock cycle and routes the subsequent four instruction bytes to prefix find 306 m the subsequent clock cycle. In the illustrated embodiment, multiplexer 304 routes seven mstmction bytes to flat decoder 308. Flat decoder 308 receives the four mstruction bytes received by prefix find 306 and the subsequent three mstruction bytes. Flat decoder 308 uses the subsequent three mstruction bytes to determine the mstmction length if the fourth mstmction byte is the first byte of an mstruction. For example, the fourth mstmction byte may be an escape prefix, the fifth mstmction byte may be an opcode, the sixth mstmction byte may be a ModR M byte and the seventh instruction byte may be an SIB byte. In the subsequent clock cycle, flat decode circuit 308 receives that same four bytes as prefix find 306 and the subsequent three bytes. In other words, flat decoder 308 receives the last three instruction bytes it received in the previous clock cycle and the four subsequent mstmction bytes. By predecodmg a fixed number of bytes per clock cycle, multiplexer 304 is designed to shift a fixed number of byte positions, which greatly simplifies the circuitry ofthe multiplexer. Further, the multiplexing operation may occur in parallel with the predecode function because the number of bytes by which the multiplexer shifts the mstmction bytes is not dependent upon the outcome ofthe predecode. Accordingly, the operation of the predecode circuit may be performed m an expeditious manner. Turning now to Figure 5, a block diagram of prefix find circuit 306 of predecode unit 17 accordmg to one embodiment ofthe present invention is shown. Prefix find 306 mcludes four prefix ID circuits 402-408, an operand prefix sorter 410, an address prefix sorter 412, and an accumulate sorter 414. Each prefix ID circuit is configured to receive an mstmction byte and output a plurality of prefix control signals. In the illustrated embodiment, each prefix ID circuit outputs a prefix control signal mdicatmg whether the mstmction byte is a prefix byte, and if the mstmction byte is a prefix byte, what type of prefix byte it is. For example, prefix ID 402 receives instruction byte 0 from multiplexer 304. It is noted that mstmction byte 0 is earlier m program order than instruction byte 1, instruction byte 2 and mstruction byte 3. Prefix ID 402 outputs a prefix signal (P0) that mdicates whether mstruction byte 0 is a prefix byte. It is noted, that prefix ID 402 may mcoπectly identify a byte as a prefix byte. For example, a displacement or immediate byte may contam a valid prefix, such as 66 or 67. At this stage, prefix ID 402 is unable to distmguish whether the mstmction byte is a prefix byte or another byte that includes a valid prefix code. As will be apparent from the discussion below, however, incoπectly identifying a displacement or immediate byte as a prefix byte will not adversely effect the operation ofthe circuit. Prefix ID 402 further outputs an escape prefix control signal (0F0) indicates that the prefix byte contains the escape prefix OF Prefix ID 402 still further outputs an operand prefix signal (66-0) that mdicates the prefix byte contams the operand size overπde prefix 66. Prefix ID 402 additionally provide an address prefix signal (67-0) that mdicates the prefix byte contains the address size overnde prefix 67. Prefix ID circuits 404 - 408 operate m the substantially same manner as prefix ID 402. Prefix ID 404 identifies whether mstmction byte 1 is a prefix byte, and if so, whether it is an escape, address overπde or operand oveπide prefix. Prefix ID 406 receives mstruction byte 2 and identifies whether mstmction byte 2 is a prefix byte, and if so, whether it is an escape, address oveπide or operand oveπide prefix. Prefix ID 408 receives mstmction byte 3 and indicates whether instruction byte 3 is a prefix, and if so, whether mstmction byte is an escape, address oveπide or operand overnde prefix Operand prefix sorter 410 receives the prefix signals (P0 - P4) and the operand prefix signals (66-0 - 66-3), and outputs four operand overπde prefix signals (OP0 - OP3). The operand overnde prefix signals mdicate whether an mstruction byte includes an operand overπde prefix or an mstmction byte is a prefix byte in a continuous cham of prefix bytes that mcludes an operand overnde prefix. For example, OP3 is asserted if mstmction byte 3 is an operand overnde prefix byte. OP2 is asserted if either mstruction byte 2 is an operand overnde prefix or if mstruction byte 3 is an operand overπde prefix and mstmction byte 2 is a prefix byte. OP1 is asserted if mstmction byte 1 is an operand overnde prefix; mstruction byte 2 is an operand overnde prefix and mstmction byte 1 is a prefix byte; or mstmction byte 3 is an operand oveπide prefix and mstmction bytes 1 and 2 are prefix bytes. OP0 is asserted if mstmction byte 0 is an operand overπde prefix, or OP1 is asserted and mstmction byte 0 is a prefix byte. OP0 may additionally be asserted if a group of contiguous prefix bytes occupied the last mstruction positions m the previous group of mstmction bytes and the contiguous group of prefixes included an operand prefix overnde. The operation of operand prefix sorter 410 is discussed m more detail below in reference to Figure 11 Address prefix sorter 412 operates m substantially the same manner as operand prefix sorter 410. Address prefix sorter 412 receives the prefix signals (P0 - P3) and the address prefix signals (67-0 - 67-3) Address prefix sorter 412 outputs four address oveπide prefix signals (A0 - A3) which are substantially similar to the operand prefix signals except they detect the presence of an address oveπide prefix rather than an operand oveπide prefix Accumulate sorter 414 receives the prefix signals (P0 - P3) and the four start bits (SO - S3) from tree circuit 312 Accumulate sorter 414 outputs an accumulated prefix signal (AccP) that mdicates that a contiguous group of prefix bytes followed the last start byte For example, if an mstruction started m mstruction byte 1 of the previous group of mstmction bytes and instruction bytes 1, 2 and 3 were prefix bytes, accumulator sorter 414 stores this information and asserts the accumulate prefix signal m the cuπent clock cycle The accumulated prefix signal creates a false start byte m mstmction byte 0. In other words, if a group of mstmction bytes predecoded m a previous clock cycle ends with a contiguous group of mstmction bytes after a start byte, the predecode unit treats the cuπent group of mstmction bytes as if a start byte occurs at mstruction byte 0. As discussed above, if one ofthe contiguous group of prefix bytes was either an address or operand oveπide, operand prefix sorter 410 and address prefix sorter 412 output a signal that mdicates that mstruction byte 0 includes an operand or address overnde prefix. Accumulate sorter 414 is discussed m more detail below in reference to Figure 12. Turning now to Figure 6, a block diagram of flat decoder 308 of predecode umt 17, according to one embodiment of the present invention is shown Flat decoder circuit 308 includes eight decode circuits (502 - 516). In the illustrated embodiment, each predecode circuit receives three instruction bytes Each predecode circuit outputs a length vector that mcludes a root vector and a plurality of flags. The root vector identifies a preliminary estimate ofthe mstmction length and the flags provide control signals used by prefix accumulator 310 to increase the mstmction length dependmg upon the occuπence of prefix bytes and other factors For example, the root vector may mdicate that an mstruction mcludes fives mstmction bytes The flags may indicate that mstruction additionally mcludes two or four bytes of displacement data dependmg upon whether 16-bit or 32-bit addressing is selected. Accordmgly, prefix accumulator 310, which is discussed m more detail below, may increase the mstmction length by two or four bytes dependmg upon the prefix bytes and the state of the default bit Each decode circuit of flat decoder 308 computes the root vector and flags based on an assumption about which mstmction byte is a start byte and whether a previous mstruction byte is an escape prefix. For example, decoder 502 receives mstruction bytes 0, 1 and 2 (mstmction byte 0 is first m program order), and generates a root vector and flags based on the assumption that an mstmction starts at mstmction byte 0 and the previous instruction byte was not an escape prefix Decoder 504 receives mstmction bytes 1, 2 and 3, and generates a root vector and flags based on the assumption that the mstmction starts at mstmction byte 0 and instruction byte 0 is an escape prefix Decoder 506 receives mstmction bytes 1 , 2 and 3, and generates a root vector and flags based on the assumption that the mstmction starts in mstruction byte 1 and mstmction byte 1 is not an escape prefix Decoder 508 receives mstmction bytes 2, 3 and 4, and generates a root vector and flags based on the assumption that the instruction starts m mstruction byte 1 and mstmction byte 1 is an escape prefix Decoder 510 receives mstmction bytes 2, 3 and 4, and generates a root vector and flags based on the assumption that the mstmction starts in mstmction byte 2 and mstmction byte 2 is not an escape prefix Decoder 512 receives mstmction bytes 3, 4 and 5, and generates a root vector and flags based on the assumption that the mstmction starts in instruction byte 2 and mstmction byte 2 is an escape prefix Decoder 514 receives instruction bytes 3, 4 and 5, and generates a root vector and flags based on the assumption that the mstmction starts in mstmction byte 3 and mstmction byte 3 is not an escape prefix Decoder 516 receives mstmction bytes 4, 5 and 6, and generates a root vector and flags based on the assumption that the mstmction starts m mstmction byte 3 and instruction byte 3 is an escape prefix Accordmgly, flat decoder 308 outputs eight length vectors (LVA - LVH) that are provided to prefix accumulator 310 As discussed in more detail below, prefix accumulator 310 selects length vectors based on the occuπence of escape prefixes, and uses the flags, operand oveπide signals and address overnde signals to compute the actual length of an mstmction if an mstruction starts m an mstmction byte coπespondmg to the length vector Turning now to Figure 6A, a diagram of a length vector accordmg to one embodiment ofthe present invention is shown In one embodiment, the length vector includes a root vector and a plurality of flags The root vector indicates the length of the mstruction based upon the presence of an escape prefix, an opcode byte, a ModR/M byte and a number of immediate bytes In one specific embodiment, the number of immediate bytes accounted for in the root vector is 0, 1, 2, 3 or 4 Accordmgly, the root vector may identify up to seven bytes of mstmction length In the illustrated embodiment, the root vector mcludes one bit for each potential number of mstmction bytes An asserted bit of the root vector mdicates the length of the coπesponding instruction For example, if the coπespondmg instruction is one byte long (based on the above identified instruction bytes), then bit zero is asserted If the coπesponding mstmction is two bytes long, then bit one is asserted, etc The length vector additionally mcludes a plurality of flags In one embodiment, the length vector includes five flags an SIB flag (SIB), a one displacement byte flag (1DISPL), a two displacement byte flag (2DISPL), a four displacement byte flag (4DISPL), and a two immediate byte flag (2IMMED) As noted above, the root vector and flags are used in conjunction with the prefix data from prefix find circuit 306 to aπive at the final length ofthe mstmction The use ofthe flags is discussed m more detail below in reference to Figures 7 and 13 Tummg now to Figure 7, a block diagram of prefix accumulator 310 of prefetch/predecode circuit 12 according to one embodiment ofthe present invention is shown Prefix accumulator 310 includes multiplexers 602 - 614 and displacement /immediate accumulators 616A - 616D Multiplexers 602 - 608 are configured to select one of two length vectors coπespondmg to an mstmction byte As discussed above, two length vectors are generated for each mstmction byte One length vector assumes the first byte of the mstmction is an escape prefix and the other length vector assumes the first mstruction ofthe byte is not an escape prefix For example, length vector A (LVA) is generated by decoder 502 of flat decoder 308 based on the assumption that an mstmction starts in mstmction byte 0 and instruction byte 0 is not an escape prefix, and length vector B (LVB) is generated based on the assumption that the instruction starts m an mstmction byte 0 and mstmction byte 0 is an escape prefix. Multiplexer 602 selects either LVA or LVB based upon the escape prefix control signal (0F0) from prefix find circuit 306. If 0F0 mdicates that mstmction byte 0 is an escape prefix, multiplexer 602 selects LVB. Alternatively, if 0F0 mdicates that mstruction byte 0 is not an escape prefix, multiplexer 602 selects LVA. Multiplexers 604, 606 and 608 operate m substantially the same manner. The outputs of multiplexers 602 - 608 are four length vectors (LVO - LV3) that each coπespond to an mstruction byte. For example, length vector 0 (LVO) coπesponds to mstmction byte 0, length vector 1 (LVl) coπesponds to mstruction byte 1, length vector 2 (LV2) coπesponds to mstmction byte 2 and length vector 3 (LV3) coπesponds to mstmction byte 3 Multiplexers 610 - 612 shift the length vectors based upon the occuπence of prefix bytes m mstmction bytes preceding the mstruction byte coπespondmg to the length vector For example, multiplexer 610 shifts LV3 by one position if a prefix byte is detected in mstruction byte 2 As discussed above, LV3 is generated based on the assumption that the opcode or an escape prefix starts at mstmction byte 3. If mstmction byte 2 is a prefix, the mstmction is one byte longer and starts m mstmction byte 2 rather mstruction byte 3. For example, consider a two-byte mstmction starting m mstmction byte 2 Instruction byte 2 is a prefix byte and mstmction byte 3 is an opcode byte The root vector of LV3 would detect the opcode byte at mstmction byte 3 and identify the mstmction as a one-byte mstmction Because mstmction byte 2 is a prefix, multiplexer 610 will increase the length identified by the root vector of LV3 by one and couple LV3 to displacement/immediate accumulator 616C to indicate that the mstmction is actually a two-byte mstruction starting at mstmction byte 2 rather than a one-byte mstmction byte starting at mstmction byte 3 Multiplexers 612 and 614 operate m a substantially similar manner to multiplexer 610, and shift the length vector based on the number of prefix bytes preceding an mstmction It is noted, the multiplexers 610 - 614 increase the instruction length stored by the root vector when the length vector is shifted, but do not modify the flags ofthe length vector. The length vector is shifted by the number of contiguous prefix bytes preceding the mstmction. For example, if an mstruction m which the opcode starts m mstmction byte 3 is preceded by three prefixes, the length vector will be shifted three positions (I e. coupled to displacement immediate accumulator 616A) and the length identified by the root vector will be increased by 3 The case in which additional prefix bytes were present m a group of mstmction bytes predecoded m a previous clock cycle is handled by the accumulate prefix signal of accumulate sorter 414 The accumulate prefix signal causes the predecode circuit to operate as if the mstmction starts at mstmction byte 0 Accordmgly, the length ofthe instruction is determined from mstmction byte 0 and any previous prefix bytes do not need to be accounted for in the root vector. The shifted length vectors from multiplexers 610 - 614 are provided to displacement/immediate accumulators 616A - 616D (collectively refeπed to as displacement/immediate accumulator 616) Displacement/immediate accumulator 616 determines the actual mstmction length (not including prefix bytes pnor to the cuπent group of mstmction bytes) if an instruction starts in the mstmction byte coπespondmg to the shifted length vector. For example, the output of displacement/immediate accumulator 616A is a length vector that identifies the length of an instruction if mstmction byte 0 is a start byte Displacement immediate accumulator 616 accounts for an SIB byte; zero, one, two, or four displacement bytes; and two additional immediate bytes Displacement/immediate accumulator 616 A determines whether any of these bytes are present based upon the flags ofthe length vector, the operand oveπide prefix signals and address overπde prefix signals received from prefix find circuit 306, and the default bit (D), which identifies the default address and operand nodes. For example, displacement/immediate accumulator 616A may mcrease the length ofthe root vector based upon the flags ofthe length vector output by multiplexer 614, OP0, A0 and. Displacement/unmediate accumulator outputs a length vector (S 0 ) to tree circuit 312. In one embodiment, the length vector is a fifteen bit long vector (S o L[0:14]). An asserted bit of the length vector mdicates the mstmction length. For example, if the mstruction is two bytes long, the S 0 L, bit is asserted. In an alternative embodiment, the length vector may identify the last mstmction byte in an mstmction. In this embodiment, the start byte of the next mstmction is the byte subsequent to the byte identified by the length vector. Displacement immediate accumulators 616B - 616D operate in substantially the same manner. The operation of displacement/immediate accumulator 616 is discussed m more detail below m reference to Figure 13 Turning now to Figure 8, a block diagram of tree circuit 312 accordmg to one embodiment ofthe present invention is shown Generally speakmg, tree circuit 312 determines a subsequent start byte from a current start byte and the length ofthe mstmction starting at the cuπent start byte. Tree circuit 312 outputs four start bits (STO - ST3) that identify which, if any, of the predecoded mstmction bytes are start bytes. For example, assume an mstruction starts at mstmction byte 0 and the length of the mstmction starting in mstruction byte 0 is two bytes long. Accordmgly, the start zero (STO) signal of node 802 and the second bit of start vector zero (S 0 L i ) is asserted. STO and S 0 L, are provided to node 806. Node 806 and node 834 will propagate the asserted S 0 L, signal which causes ST2 to be asserted. ST2 indicates that another mstmction starts m mstmction byte 2. Further assume that the mstruction starting at mstruction byte two is five bytes long. This will cause S 2 L 4 to be asserted. The asserted ST2 and S 2 L 4 signals are stored m register 894. In the subsequent clock cycle, these signals are received by node 868 which will assert its output. Because the start three (ST3) signal is unasserted, node 882 will propagate the asserted output of node 868 to the start seven (ST7) signal. The ST7 signal is coupled to the feedback three (FB3) signal of node 864 The FB3 is signal will cause node 864 to assert the start three (ST3) signal. Accordmgly, in the subsequent clock cycle the ST3 signal is asserted Because four instruction bytes are decoded each clock cycle, the start byte coπespondmg to ST7 is predecoded in mstmction byte three m the subsequent clock cycle. In the above descπbed manner, tree circuit 312 stores information mdicative of start bytes that are predecoded in future clock cycles The identification of a start byte may be stored for several clock cycles. For example, if the mstmction m the above described example was eight bytes long rather than five, the S 2 L 7 signal is asserted. The ST2 signal and the S 2 L 7 signal are provided to node 871 in the second clock cycle In other words, the signals are stored by register 894 in a first clock cycle and register 896 m a second clock cycle. When node 871 receives the signals, it asserts its output which is propagated by node 885 Node 885 asserts the start ten (ST10) signal. The ST 10 signal is coupled to the feedback six (FB6) signal of node 881 which asserts the start six (ST6) signal. The ST6 signal is coupled to the feedback two (FB2) signal of node 834, which asserts the ST2 signal Accordmgly, the ST2 signal is asserted two clock cycles after an eight byte mstmction starting an mstmction byte two is detected. The operation of tree circuit 312 will be discussed in more detail m conjunction with Figure 9 m which the operation of nodes 802-810, 834-838, 864, 865 and 879 are discussed in more detail. Buffers 894, 896, 898 and 899 store all control signals propagated to nodes below the buffer. For example, buffer 894 stores the STO - ST4, S 0 L [7 15], S,L [5.15], S 2 L [3.15] and S 3 L [1 :15] signals. Buffer 896 stores the STO - ST4, S 0 L [11:15], S,L [9:15], S 2 L [7 15] and S 3 L [5 15] signals. Each buffer is coupled to a common clock signal. Tummg now to Figure 9, a circuit diagram of a portion of tree circuit 312 accordmg to one embodiment of the present mvention is shown Figure 9 shows more details of nodes 802-810, 834-838, 864, 865 and 879 Node 802 includes a three mput OR-gate 902 If either the force start zero (F0) signal, the accumulate prefix (AccP) signal, or the feedback zero (FB0) signal are asserted, then OR-gate 902 asserts the start zero (STO) signal The STO signal indicates that an instruction starts m mstmction byte 0 This situation may arise m three situations First, a forced start signal may indicate that an mstmction starts in an mstmction byte 0 The forced start signal may be asserted to mdicate a branch coπection For example, a branch misprediction may cause prefetch/predecode circuit 12 to fetch an instruction lme and begm execution of that line out of sequence from the previous mstmctions The force start signals identify m which byte to begm predecodmg Second, the FB0 signal may indicate that a start byte was detected in instruction byte 4 of a previous cycle Instmction byte 4 in the previous cycle becomes mstmction byte 0 m this cycle Accordmgly, if a start byte was detected in mstmction byte 4 ofthe previous cycle, this information is stored m register 894 provided to OR gate 902, which asserts STO Lastly, STO may be asserted if the accumulate prefix signal is asserted As discussed above, the accumulate prefix circuit creates a false start m mstruction byte 0 if a contiguous group of prefix bits following a start bit is detected m the previous clock cycle The STO signal provides a control mput to multiplexers 904, 906, 910 and 912 If STO is asserted, multiplexers 904-912 select the bit of length vector SO coupled to the multiplexer If STO is unasserted, the multiplexers select a logical 0 In node 804, the output of multiplexer 904 is provided to OR gate 914 OR gate 914 additionally receives mputs from the force start one (Fl) signal and the feedback one (FBI) signal FBI is coupled to the start five (ST5) signal (not shown) OR gate 914 asserts ST1 if Fl, FBI or the output of multiplexer 904 is asserted The output of multiplexer 904 is asserted if STO is asserted and bit zero of length vector SO (S 0 L 0 ) is asserted S 0 L 0 mdicates that the length of the mstruction starting at start bit zero is 1 In other words, if a one-byte mstruction starts in position 0, another instmction starts in position 1 STO also provides a control signal to nodes 812-832 (not shown) Each of these nodes receives one bit of SO For example, node 812 receives bit four of SO, node 814 receives bit five of SO, etc The ST1 signal provides a control signal to multiplexers 916, 918 and 920 If ST1 is asserted, these multiplexers select the respective bits of length vector SI Alternatively, if ST1 is unasserted, multiplexers 916, 918 and 920 propagate the outputs of multiplexers 906, 910 and 912, respectively ST1 also provides a control signal to nodes 840 - 862 (not shown) Each of those nodes receives one bit of SI The output of gate 916 is provided to OR gate 922 OR gate 922 asserts the start two (ST2) signal if the force start two (F2) signal or the feedback 2 (FB2) signal is asserted The FB2 signal is coupled to the start six (ST6) signal (now shown) OR gate 922 additionally asserts ST2 if the output of multiplexer 916 is asserted The output of multiplexer 916 is asserted m two instances First, the output of multiplexer 916 is asserted if ST1 is asserted and bit zero of length vector SI of is asserted This situation aπses when a one-byte mstruction starts m mstruction byte one Secondly, the output of multiplexer 916 is asserted if ST1 is deasserted, STO is asserted and bit one of length vector SO is asserted This situation aπses if no instruction starts in mstmction byte 1 and a two-byte mstruction starts in mstmction byte 0 The ST2 signal provides a control signal to multiplexers 924 and 926 If ST2 is asserted, the multiplexers select the respective bits of length vector S2 Alternatively, if ST2 is unasserted, multiplexers 924 and 926 propagate the output of multiplexers 918 and 920, respectively ST2 also provides a control signal to nodes 866 - 878 (not shown) Each of these nodes receives a bit of S2 OR gate 928 is coupled to the force start three (F3) signal and the feedback three (FB3) signal, and the output of multiplexer 924 The FB3 signal is the buffered version of ST7 from the previous cycle The ST3 signal is asserted if either the F3 signal, the FB3 signal, or the output of multiplexer 924 is asserted The output of multiplexer 924 is asserted if either a one-byte mstmction starts in mstmction byte 2, a two-byte mstmction starts in instmction byte 1, or a three-byte instruction starts m mstmction byte 0 The ST3 signal provides a control signal to multiplexer 930, which selects either bit zero of S3 or the output of multiplexer 926 ST3 provides a control signal to nodes 880-893 (not shown) Each of these nodes receives a bit of S3 OR gate 932 outputs a start four (ST4) signal, which is provided to buffer 894 Buffer 894 stores the state ofthe ST4 signal and provides the signal to the FBO input of node 802 m the subsequent clock cycle The ST4 signal is asserted if either the feedback four (FB4) signal is asserted or the output of multiplexer 930 is asserted The FB4 signal is coupled to the start eight (ST8) signal (not shown) The output of multiplexer 930 is asserted if a one-byte mstmction starts m mstmction byte three, a two-byte mstmction starts in mstmction byte 2, a three-byte mstmction starts m instmction byte 1, or a four-byte mstruction starts in instmction byte 0 It is noted, that nodes 880 - 893 operate in substantially the same manner as node 879 described above It is further noted, that nodes 812-832, 840-862, 866-878 operate in substantially the same manner as nodes 806- 810, 836, 838 and 865 descπbed above Tummg now to Figure 10, a circuit diagram of an optimized version of the portion of tree circuit 312 illustrated in Figure 9 accordmg to one embodiment ofthe present mvention is shown The same optimizations as illustrated in Figure 10 may be applied to the remammg portion of tree circuit 312 In Figure 10, OR gates 902, 914, 922, 928 and 932 are replaced with inverted-input AND gates 1002, 1014, 1022, 1028 and 1032 In this embodiment, the start signals implement negative logic In other words, STO - ST4 are "asserted" when they are a logical "0" rather than a logical "1" Multiplexers 1004 - 1012, 1016 - 1020, 1024 and 1030 are configured to select bits from the coπesponding length vector when STO is asserted, or logical 0 It is noted that an input of multiplexers 1004 and 1010 are coupled to logical "1" In the illustrated embodiment, inverters 1034 - 1044 are added In the illustrated embodiment, all paths propagate through the same number of gates For example, the control signal to multiplexer 1004 passes through four logic gates regardless ofthe path by which it arnved For example, the control signal may propagate through gates 1004, 1014, 1016 and 1022 Alternatively, the control signal may propagate through gates 1006, 1034, 1016 and 1022 Likewise, the inputs to multiplexer 1024 pass through four logic gates Turning now to Figure 11, a circuit diagram of operand prefix sorter 410 accordmg to one embodiment of the present invention is shown Operand prefix sorter 410 outputs four operand overnde prefix signals (OP0 - OP3) Operand prefix sorter 410 receives four operand prefix signals (66-0 - 66-3), four prefix signals (P0 - P3), and four start signals (SO - S3) The operand prefix signals identify which mstmction bytes include an operand oveπide prefix The prefix signals indicate which instruction bytes are prefix bytes The start signals indicate which mstmction bytes are start bytes OP3 is asserted if 66-3 is asserted OP2 is asserted if either 66- 2 is asserted, or OP3 and P2 are asserted OP1 is asserted if either 66-1 is asserted, or OP2 and PI are asserted OP0 is asserted if Acc66 or the output of OR gate 1112 is asserted The output of OR gate 1112 is asserted if either 66-0 is asserted, or OP1 and P0 asserted The Acc66 signal indicates that a contiguous groups of instmction bytes previous to instruction byte 0 and after a start byte are prefix bytes, and one of those prefix bytes is an operand override prefix. The signals 66-0 - 66-3, PO - P3, and SO - S3 are stored for one clock cycle by flip-flops 1140A - 1140K. The delayed version of these signals are used to generate Acc66. For example, DPO is the delay version of PO. In other words, DPO in the cuπent clock signal has the same state as PO in the previous clock cycle. Gates 1116-1138 implement the following logical equation: if DS3, then Acc66 = D66-3; else if DS2, then Acc66 = (DP2 DP3) (D66-3 + D66-2); else if DS1, then Acc66 = (DPI DP2 DP3) (D66-3 + D66-2 + D66-1); else Acc66 = (DSO) (DPO DPI DP2 DP3) (D66-0 + D66-1 + D66-2 + D66-3). Address prefix sorter 412 operates in substantially the same manner as operand prefix sorter 410. The operand prefix signals are replaced with address prefix signals (67-0 - 67-3), and address override prefix signals (A0 - A3) are output. Turning now to Figure 12, a block diagram of accumulate sorter 414 of prefix find circuit 306 according to one embodiment ofthe present invention is shown. Accumulate sorter 414 uses the delayed versions of P0 - P4 and SO - S4, discussed above in reference to Figure 12, to generate the AccP signal. The AccP signal identifies whether instmction byte 0 was preceded by a contiguous group of prefix bytes following a start byte. The illustrated circuit implements the following logical equation: ifDS3, then AccP = DP3; else ifDS2 then AccP = DP2 DP3; else if DS 1 , then AccP = DP 1 DP2 DP3 ; else AccP = DSO DPO DPI DP2 DP3. It is noted, that portions of accumulate sorter 414 replicate portions of operand prefix sorter 410 and address prefix sorter 412. Accordingly, in another embodiment, the circuits may be combined to reduce circuitry. Turning now to Figure 13, a block diagram of displacement/immediate accumulator 616 of prefix accumulator 310 according to one embodiment of the present invention is shown. Displacement/immediate accumulator 616 includes multiplexers 1302, 1304 and 1306, AND gate 1308, exclusive-or gates 1312 and 1314 and logic circuit 1310. In the illustrated embodiment, displacement/immediate accumulator 616 increases the length of a root vector of an instmction based on the flags associated with the length vector, the operand override prefix signal, the address override prefix signal and the default bit (D). The ADDR32 signal is the exclusive-or ofthe default bit and the address override prefix signal (Ax). Each displacement/immediate accumulator 616 receives the flags, operand oveπide prefix signal and address override prefix signal associated with that instruction. For example, displacement/immediate accumulator 616A of Figure 7 receives operand oveπide prefix signal 0 (OP0) and address oveπide prefix signal (A0). Displacement/immediate accumulator 616A further receives the root vector and flags associated with the length vector output by multiplexer 614. In the illustrated embodiment, multiplexer 1302 increases the length ofthe root vector, i.e. shifts the root vector, by one if the one displacement byte flag is asserted. The output of multiplexer 1302 is shifted by two if the two immediate byte flag is asserted and 32-bit operands are used. To determine whether 32-bit operands are used, the operand override prefix signal (OPx) is exclusive-ORed with the D bit. In one embodiment, the D bit is asserted if the default operand size is 32 bits and unasserted if the default operand size is 16 bits. If the operand oveπide prefix signal is asserted the output of exclusive-OR gate 1212 is the mverse of the default bit In one embodiment, the D bit is a code segment descπptor If either 16-bit operands are used or the two immediate byte flag is unasserted, multiplexer 1204 does not shift the root vector. Multiplexer 1306 shifts the output of multiplexer 1304 by zero, one, two, four, or five bytes dependmg on the output of logical circuit 1310. Logical circuit 1310 receives SIB flag, a two displacement byte flag, a four displacement byte flag, and a 32-bit address signal (ADDR32x) Based on these control signals, logical circuit 1310 determines whether the associated mstmction mcludes an SIB byte, four displacement bytes and an SIB byte, two displacement bytes, or four displacement bytes. Logic circuit 1310 outputs control signals to multiplexer 1306 to shift the root vector by the appropnate number of bits A truth table indicating the appropπate number of bits to shift the root vector based on the control signals received by logic circuit 1310 is shown m Figure 13. Tummg now to Fig. 14, a block diagram of one embodiment of a computer system 1400 mcludmg microprocessor 10 coupled to a vanety of system components through a bus bndge 1402 is shown. Other embodiments are possible and contemplated. In the depicted system, a mam memory 1404 is coupled to bus bndge 1402 through a memory bus 1406, and a graphics controller 1408 is coupled to bus bridge 1402 through an AGP bus 1410 Finally, a plurality of PCI devices 1412A - 1412B are coupled to bus bridge 1402 through a PCI bus 1414 A secondary bus bndge 1416 may further be provided to accommodate an electrical mterface to one or more EISA or ISA devices 1418 through an EISA/ISA bus 1420 Microprocessor 10 is coupled to bus bndge 1402 through a CPU bus 1424. Bus bndge 1402 provides an interface between microprocessor 10, mam memory 1404, graphics controller 1408, and devices attached to PCI bus 1414. When an operation is received from one ofthe devices connected to bus bndge 1402, bus bndge 1402 identifies the target ofthe operation (e.g. a particular device or, m the case of PCI bus 1414, that the target is on PCI bus 1414). Bus bndge 1402 routes the operation to the targeted device. Bus bndge 1402 generally translates an operation from the protocol used by the source device or bus to the protocol used by the target device or bus. In addition to providing an mterface to an ISA/EISA bus for PCI bus 1414, secondary bus bndge 1416 may further incorporate additional functionality, as desired For example, m one embodiment, secondary bus bndge 1416 mcludes a master PCI arbiter (not shown) for arbitrating ownership of PCI bus 1414. An input/output controller (not shown), either external from or mtegrated with secondary bus bndge 1416, may also be mcluded withm computer system 1400 to provide operational support for a keyboard and mouse 1422 and for various serial and parallel ports, as desired. An external cache unit (not shown) may further be coupled to CPU bus 1424 between microprocessor 10 and bus bridge 1402 in other embodiments Alternatively, the external cache may be coupled to bus bridge 1402 and cache control logic for the external cache may be integrated into bus bndge 1402 Mam memory 1404 is a memory m which application programs are stored and from which microprocessor 10 pnmanly executes A suitable mam memory 1404 compπses DRAM (Dynamic Random Access Memory), or preferably a plurality of banks of SDRAM (Synchronous DRAM) PCI devices 1412A-1412B are illustrative of a vanety of penpheral devices such as, for example, network mterface cards, video accelerators, audio cards, hard or floppy disk dnves or drive controllers, SCSI (Small Computer Systems Interface) adapters and telephony cards. Similarly, ISA device 1418 is illustrative of vaπous types of peripheral devices, such as a modem, a sound card, and a vanety of data acquisition cards such as GPIB or field bus mterface cards. Graphics controller 1408 is provided to control the rendenng of text and images on a display 1426. Graphics controller 1408 may embody a typical graphics accelerator generally known m the art to render three- dimensional data structures which can be effectively shifted into and from mam memory 1404 Graphics controller 1408 may therefore be a master of AGP bus 1410 m that it can request and receive access to a target interface withm bus bndge 1402 to thereby obtam access to mam memory 1404 A dedicated graphics bus accommodates rapid retrieval of data from mam memory 1404 For certam operations, graphics controller 1408 may further be configured to generate PCI protocol transactions on AGP bus 1410 The AGP mterface of bus bndge 1402 may thus mclude functionality to support both AGP protocol transactions as well as PCI protocol target and initiator transactions. Display 1426 is any electronic display upon which an image or text can be presented A suitable display 1426 includes a cathode ray tube ("CRT"), a liquid crystal display ("LCD"), etc. It is noted that, while the AGP, PCI, and ISA or EISA buses have been used as examples m the above descπption, any bus architectures may be substituted as desired It is further noted that computer system 1400 may be a multiprocessing computer system mcludmg additional microprocessors (e.g. microprocessor 10a shown as an optional component of computer system 1400) Microprocessor 10a may be similar to microprocessor 10. More particularly, microprocessor 10a may be an identical copy of microprocessor 10 Microprocessor 10a may share CPU bus 1424 with microprocessor 10 (as shown in Fig. 14) or may be connected to bus bndge 1402 via an mdependent bus. It is noted that the present discussion may refer to the assertion of various signals As used herein, a signal is "asserted" if it conveys a value mdicative of a particular condition Conversely, a signal is "deasserted" if it conveys a value mdicative of a lack of a particular condition A signal may be defined to be asserted when it conveys a logical zero value or, conversely, when it conveys a logical one value. Additionally, vaπous values have been descnbed as bemg discarded in the above discussion. A value may be discarded in a number of manners, but generally mvolves modifymg the value such that it is ignored by logic circuitry which receives the value. For example, if the value compπses a bit, the logic state ofthe value may be inverted to discard the value. If the value is an n-bit value, one ofthe n-bit encodmg may mdicate that the value is invalid Setting the value to the invalid encodmg causes the value to be discarded Additionally, an n-bit value may mclude a valid bit mdicative, when set, that the n-bit value is valid. Resetting the valid bit may compnse discarding the value Other methods of discarding a value may be used as well. INDUSTRIAL APPLICABILITY The mvention disclosed herem is applicable m a number of fields, mcludmg electronics such as microprocessors, microcontrollers, and digital signal processors, and other more general products such as computers, computational devices, set-top boxes and the like

Claims: WHAT IS CLAIMED IS: 1 A method of predecodmg mstmction bytes of variable-byte length mstmctions to identify start bytes of vaπable length mstmctions compnsmg predecodmg a fixed number of mstmction bytes starting with an mstmction byte identified by a predecode pomter, wherein said predecodmg identifies said start bytes withm said fixed number of mstruction bytes, incrementing said predecode pointer by said fixed number of mstmction bytes, and predecodmg said fixed number of instruction bytes starting with an instruction byte identified by said predecode pomter 2 The method of Claim 1 wherem said predecodmg compπses determining a first mstmction length if a start byte is m a first byte position, determining a second mstmction length if said start byte is in a second byte position, determining a location of a first start byte based upon an mstmction byte position of a previous start byte and an mstruction length associated with said previous start position, and selecting said first mstmction length if said first start byte is m said first byte position and selectmg said second mstmction byte length if said first start byte is in said second byte position 3 A method of predecodmg mstmction bytes of variable-byte length mstmctions to identify start bytes of vaπable length instructions compnsmg determining a first mstruction length if a start byte is in a first byte position, determining a second mstmction length if said start byte is m a second byte position, determining a location of a first start byte based upon an instruction byte position of a previous start byte and an mstruction length associated with said previous start position, and selectmg said first mstmction length if said first start byte is m said first byte position and selectmg said second mstmction byte length if said first start byte is in said second byte position The method of Claim 3 further compnsmg predecodmg a fixed number of mstruction bytes starting with an mstruction byte identified by a predecode pomter, wherem said predecodmg identifies said start bytes withm said fixed number of mstruction bytes, incrementing said predecode pomter by said fixed number of mstmction bytes, and predecodmg said fixed number of instmction bytes starting with an mstmction byte identified by said predecode pointer 5 A predecode unit (17) comprising a decode circuit (308) configured to decode a fixed number of mstmction bytes m a clock cycle and to output a plurality of instruction length vectors, a prefix find circuit (306) configured to receive said fixed number of instmction bytes and to identify which of said fixed number of instruction bytes are prefixes, a prefix accumulator circuit (310) coupled to said decode circuit and said prefix find circuit and configured to output a plurality of position length vectors which identify an mstmction length for potential start bytes, and a tree circuit (312) coupled to said prefix accumulation circuit and configured to output a plurality of start bits, wherem said start bits identify one or more start bytes within said fixed number of instmction bytes 6 The predecode unit of Claim 5 further comprising a multiplexer (304) coupled to said decode circuit and said prefix find circuit, and configured to output a fixed number of mstmction bytes to said decode circuit and said prefix find circuit each clock cycle, and an instruction buffer coupled to said decode circuit and said prefix find circuit and configured to store a plurality of mstmction bytes 7 The predecode unit of Claim 6 wherein said buffer includes a predecode pointer which identifies a first instruction byte of said fixed number of instruction bytes, wherem said predecode pointer is incremented by said fixed number of mstruction bytes each clock cycle whereby said predecode unit predecodes said fixed number of instruction byte each clock cycle 8 The predecode unit of Claim 5 wherem said prefix find circuit identifies which of said fixed number of instruction bytes are operand overnde prefixes, address overnde prefixes and escape code prefixes 9 The predecode unit of Claim 8 wherein said decode unit outputs one mstmction length vector associated with each of said fixed number of mstmction bytes, wherem each of said mstmction length vectors identifies a number of mstmction bytes if an mstmction starts at said mstmction byte associated said mstmction length vector 10 The predecode unit of Claim 8 wherem said decode unit outputs a plurality of mstruction length vectors associated with each of said fixed number of mstmction bytes, wherem said prefix accumulator selects one of said instmction length vectors for each of said fixed number of instmction bytes based upon said prefixes identified by said prefix find circuit 11 The predecode unit of Claim 10 wherem said tree circuit determines a location of said start bytes based upon an mstmction byte position of a start byte and an mstmction length vector associated with said start byte, wherein if a start byte is in an mstmction byte subsequent to the mstruction bytes predecoded m a clock cycle, said tree circuit stores information mdicative of a location of said start byte and identifies said start byte when said mstmction byte is predecoded

Inventors: AHMED SYED F, MILLER PAUL K, ZURASKI GERALD D JR, AHMED, SYED, F., MILLER, PAUL, K., ZURASKI, GERALD, D., JR.
Applicants: ADVANCED MICRO DEVICES INC, ADVANCED MICRO DEVICES, INC.
Application year: 1999
Main classification: G06F9
IPC codes: G06F9