Semiconductor memory device with redundancy

Abstract: A semiconductor memory device comprises a plurality of memory cell groups, wherein data for said plurality of memory cell groups being transmitted through mutually different buses, and a redundancy memory cell group common to said plurality of memory cell groups. The semiconductor memory device further comprises a control circuit for transmitting data for one or more memory cells of said redundancy memory cell group in place of data for one or more defective memory cells in any of said plurality of memory cell groups. Each of said plurality of memory cell groups is provided corresponding to every different input/output terminal of the memory device, or said plurality of memory cell groups are provided corresponding to a common input/output terminal of the memory device.

Description: Field of the Invention The present invention relates to a semiconductor memory device and a method for relieving defective memory cells in a semiconductor memory device. More particularly, the present invention relates to relieving defective memory cells in a plurality of memory cell arrays by using a redundancy memory cell array commonly provided for the plurality of memory cell arrays. Background of the Invention As manufacturing process of a semiconductor integrated circuit device, including a semiconductor memory device, becomes more refined, defective memory cells in a memory device are more frequently replaced with redundancy memory cells, so that it becomes necessary to increase the number of redundancy memory cells. If the number of redundancy memory cells increases, however, a chip area increases, as well. It is, therefore, of importance to elaborate a more effective method for replacing a defective memory cell with a redundancy memory cell and to enhance efficiency. According to conventional techniques, a group of redundancy memory cells is individually allotted to each of memory cell groups to be read or written through different buses, respectively. FIG. 6 is a block diagram showing a structure of a semiconductor memory device according to a conventional technique. In FIG. 6, a semiconductor memory device comprises DQ1 normal cell array 100, DQ2 normal cell array 200, DQ1 redundancy cell array 110, and DQ2 redundancy cell array 210. In this case, symbols DQ1 and DQ2 designate input/output terminals. The DQ1 normal cell array 100 and DQ1 redundancy cell array 110 correspond to the input/output terminal DQ1. Also, the DQ2 normal cell array 200 and DQ2 redundancy cell array 210 correspond to the input/output terminal DQ2. In the semiconductor memory device according to the conventional technique, one redundancy cell array is provided for each normal cell array. The semiconductor memory device of Fig. 6 further comprises an input/output circuit 41, a data amplifier 33, a write amplifier 35, a column decoder 37, an input/output circuit 42, a data amplifier 34, a write amplifier 36, a redundancy column decoder 40, a column decoder 38 and a redundancy control circuit 43. FIG. 7 is a timing chart for describing the operation of the conventional semiconductor memory device shown in Fig. 6. In the first to fourth clock cycles, wherein each clock cycle is determined by an internal clock signal ICLK produced from an external clock signal, potential level of column switch lines YSW11∼YSW1n and column switch lines YSW21∼YSW2n change in accordance with inputted column addresses YADD, as shown in Fig. 7. In each cycle, potential level of one of each of a plurality of column switch lines inputted to the DQ1 normal cell array 100 and DQ2 normal cell array 200, respectively, is activated. In sense amplifiers connected to the activated column switch line, data is transmitted to and from local input/output buses LIOBUS11∼LIOBUS1m in accordance with data signal amplified by the sense amplifiers. Assuming that the column address YADD provided in the second cycle is a column address of a column including one or more defective cells in the DQ1 normal cell array, DQ1 column redundancy selection signal YREDDQ1 becomes an active level (H). Also, assuming that the column address YADD provided in the fourth cycle is a column address of a column including one or more defective cells in the DQ2 normal cell array, DQ2 column redundancy selection signal YREDDQ2 becomes an active level (H). In this case, in the second cycle, a redundancy column switch line RYSW1 is selected in response to the DQ1 column redundancy selection signal YREDDQ1, and data is transmitted to and from redundancy local input/output buses LIOBUS11∼LIOBUS1m in sense amplifiers connected to the redundancy column switch line RYSW1 in accordance with data signals amplified by the sense amplifiers. In the fourth cycle, a redundancy column switch line RYSW2 is selected in response to the DQ2 column redundancy selection signal YREDDQ2, and data is transmitted to and from local input/output buses LIOBUS21∼LIOBUS2m in sense amplifiers connected to the redundancy column switch line RYSW2 in accordance with data signals amplified by the sense amplifiers. Accordingly, the data of global input/output buses GIOBUS1 and GIOBUS2 are transmitted to read/write buses RWBUS1 and RWBUS2, respectively in the first cycle; the data of a redundancy global input/output bus RGIOBUS1 and that of the global input/output bus GI0BUS2 are transmitted thereto, respectively in the second cycle; the data of the global input/output buses GIOBUS1 and GIOBUS2 are transmitted thereto, respectively in the third cycle; and the data of the global input/output bus GIBUS1 and that of the redundancy input/output bus RGIBUS2 are transmitted thereto, respectively in the fourth cycle. According to the conventional technique, different redundancy memory cell groups are allotted to memory cell groups to be read or written through different buses, respectively. Owing to this, the conventional technique has a disadvantage in that probability of relief greatly decreases if the number of defective memory cells increase in at least one of the memory cell groups. US-A-4 471 472 discloses a semiconductor memory device arranged in columns of bit cells, which are addressable in bit segments with a plurality of separate, redundant columns of bit cells, wherein each separate column should be capable of electronic placement at any column position within any bit segments of the memory. EP-A-377 249 discloses a semiconductor memory device comprising standard blocks and a redundant block, each of the standard blocks having a fixed number of standard sub-blocks with the redundant block having one or more redundant sub-blocks. In case of a defective standard sub-block a redundant sub-block should be selected. Summary of the Invention In these circumstances, the present invention has been made. It is therefore an object of the present invention to improve the yield of a semiconductor memory device. It is another object of the present invention to provide a semiconductor memory device capable of increasing the relief probability of defective memory cells. It is still another object of the present invention to provide a semiconductor memory device wherein redundancy memory cells are efficiently used to relieve defective memory cells. It is still another object of the present invention to provide a semiconductor memory device wherein a large number of defective memory cells can be relieved by using a small number of redundancy memory cells. It is still another object of the present invention to provide a semiconductor memory device wherein redundancy memory cells do not occupy large area on an integrated circuit memory chip and, therefore, chip area thereof can be efficiently used. These and further objects of the present invention are realised by a device according to claim 1 and a method according to claim 8. The dependent claims are further developments of the present invention. Brief Description of the Drawings These and other features, and advantages, of the present invention will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, in which like reference numerals designate identical or corresponding parts throughout the figures, and in which: FIG. 1 is a block diagram showing a general structure of a semiconductor memory device according an embodiment of the present invention; FIG. 2 is a partial block diagram showing a detailed structure of a semiconductor memory device illustrated in FIG. 1; FIG. 3 is a partial block circuit diagram showing an example of a structure of a redundancy control circuit 43 used in the semiconductor memory device of FIG. 2; FIG. 4 is a timing chart for describing the operation of the semiconductor memory device according an embodiment of the present invention; FIG. 5 is a partial block diagram showing a detailed structure of a semiconductor memory device according to another embodiment of the present invention; FIG. 6 is a block diagram showing a structure of a semiconductor memory device according to a conventional technique; and FIG. 7 is a timing chart for describing the operation of the semiconductor memory device according to the conventional technique illustrated in FIG 6. Description of the Preferred Embodiment Embodiments of the present invention will now be described with reference to the accompanying drawings. A. Structure of One Embodiment FIG. 1 is a block diagram showing a general structure of a semiconductor memory device according to an embodiment of the present invention. As shown in Fig. 1, the semiconductor memory device comprises a DQ1 normal cell array 100, a DQ2 normal cell array 200, a DQ1/2 redundancy cell array 300. DQ1 and DQ2 designate input/output terminals of the semiconductor memory device. The DQ1 normal cell array 100 corresponds to the input/output terminal DQ1. The DQ2 normal cell array 200 corresponds to the input/output terminal DQ2. The DQ1/2 redundancy cell array 300 corresponds to both the input/output terminals DQ1 and DQ2. Also, the semiconductor memory device comprises a peripheral circuit 51, a row decoder 52, a plate selection signal generating circuit 53, an address generating circuit 54, and an internal clock generating circuit (ICG) 55. The peripheral circuit 51 is an interface circuit which receives several control signals, such as a row address strobe signal RASB, a column address strobe signal CASB, a write enable signal WEB, and a chip select signal CSB, and generates internal control signals such as row system control signal RSYSC and column system control signal CSYSC. Operation, structure and function of the peripheral circuit 51 are easily understood by those of ordinary skill in the art. The address generating circuit 54 receives an external address signal ADD and generates a column address signal YADD and a row address signal XADD. The plate selection signal generating circuit 53 accepts one or more upper bits of the row address signal XADD from the address generating circuit 54 and generates plate selection signals PSEL1 through PSELm. The row decoder 52 accepts lower bits of the row address signal XADD from the address generating circuit 54 and generates word line selection signals supplied to word lines WL. The internal clock generating circuit 55 receives an external clock signal CLK, and performs buffering, timing adjustment, and the like to generate an internal clock signal ICLK. The internal clock signal ICLK are supplied to the peripheral circuit 51 and to the address generating circuit 54. The semiconductor memory device further comprises an input/output circuit 41, a data amplifier 33, a write amplifier 35, a column decoder 37, an input/output circuit 42, a data amplifier 34, a write amplifier 36, a column decoder 38, a redundancy column decoder 39 and a redundancy control circuit 43. FIG. 2 is a partial block diagram showing the detailed structure of the semiconductor memory device illustrated in FIG. 1. As shown in Fig. 2, the DQ1 normal cell array 100 comprises a plurality of (n) column switch lines YSW11∼YSW1n connected to the column decoder 37, a global input/output bus GIOBUS1 connected to the data amplifier 33 and the write amplifier 35, and a plurality of (m) plate selection signal lines PSEL1∼PSELm connected to the plate selection signal generating circuit 53 (FIG. 1). The DQ1 normal cell array 100 further comprises a plurality of sense amplifiers (SA) 13, 14, 15 and 16 each connected to the column switch lines YSW11∼YSW1n of a corresponding column, a plurality of memory cell groups 1, 2, 3 and 4 each connected to a corresponding one of the sense amplifiers (SA) via bit lines BL (Fig. 1), a plurality of (m) switch circuits 25 and 26, and a plurality of (m) local input/output buses LIOBUS11∼LIOBUS1m. Each of the switch circuits 25 and 26 is connected between the global input/output bus GIOBUS1 and a corresponding one of the local input/output buses LIOBUS11∼LIOBUS1m. Each of the switch circuits 25 and 26 is also connected to a corresponding one of the plate selection lines PSELm∼PSEL1, and is on/off controlled by a plate selection signal supplied from the corresponding one of the plate selection lines PSELm∼PSEL1. The DQ2 normal cell array 200 comprises a plurality of (n) column switch lines YSW21∼YSW2n connected to the column decoder 38, a global input/output bus GIOBUS2 connected to the data amplifier 34 and the write amplifier 36, and a plurality of (m) plate selection signal lines PSEL1∼PSELm connected to the plate selection signal generating circuit 53 (FIG. 1). The DQ2 normal cell array 200 further comprises a plurality of sense amplifiers (SA) 19, 20, 21 and 22 each connected to the column switch lines YSW21∼YSW2n of a corresponding column, a plurality of memory cell groups 7, 8, 9 and 10 each connected to a corresponding one of the sense amplifiers (SA) via bit lines BL (Fig. 1), a plurality of (m) switch circuits 29 and 30, and a plurality of (m) local input/output buses LIOBUS21∼LIOBUS2m. Each of the switch circuits 29 and 30 is connected between the global input/output bus GIOBUS2 and a corresponding one of the local input/output buses LIOBUS21∼LIOBUS2m. Each of the switch circuits 29 and 30 is also connected to a corresponding one of the plate selection lines PSELm∼PSEL1, and is on/off controlled by a plate selection signal supplied from the corresponding one of the plate selection lines PSELm∼PSEL1. The DQ1/2 redundancy cell array 300 comprises, for example, two redundancy column switch lines RYSW1∼RYSW2 connected to the redundancy column decoder 39, a common redundancy global input/output bus RGIOBUS connected to the data amplifier 33 and the write amplifier 35 and further to the data amplifier 34 and the write amplifier 36, and a plurality of (m) plate selection signal lines PSEL1∼PSELm connected to the plate selection signal generating circuit 53 (FIG. 1). Although two redundancy column switch lines is shown in Fig. 2 for the sake of simplicity, it should be noted that the number of the redundancy column switch lines, thus the number of redundancy columns, can be any number depending on the required relief probability and the like. The DQ1/2 redundancy cell array 300 further comprises a plurality of sense amplifiers (SA) 17, 18, 23 and 24 each connected to the redundancy column switch lines RYSW1∼RYSW2 of a corresponding column, a plurality of redundancy memory cell groups 5, 6, 11 and 12 each connected to a corresponding one of the sense amplifiers (SA) via bit lines BL (Fig. 1), a plurality of (m) switch circuits 27 and 28, and a plurality of (m) redundancy local input/output buses RLIOBUS11∼RLIOBUS1m. Each of the switch circuits 27 and 28 is connected between the redundancy global input/output bus RGIOBUS and a corresponding one of the redundancy local input/output buses RLIOBUS11∼RLIOBUS1m. Each of the switch circuits 27 and 28 is also connected to a corresponding one of the plate selection lines PSELm∼PSEL1, and is on/off controlled by a plate selection signal supplied from the corresponding one of the plate selection lines PSELm and PSEL1. The data amplifier 33 has data inputs connected to the global input/output bus GIOBUS1 and the redundancy global input/output bus RGIOBUS, and accepts data signal from either of these buses. The data amplifier 33 also has a signal input for receiving a DQ1 column redundancy selection signal YREDDQ1 which selects either of the data signals from the global input/output bus GIOBUS1 or the redundancy global input/output bus RGIOBUS for inputting to the data amplifier 33. An output terminal of the data amplifier 33 is connected to the read/write bus RWBUS1 to output data signal thereto. The write amplifier 35 has data outputs connected to the global input/output bus GIOBUS1 and the redundancy global input/output bus RGIOBUS, and outputs data signal to either of these buses. The write amplifier 35 also has a signal input for receiving the DQ1 column redundancy selection signal YREDDQ1 which also selects data output path of data signal into the global input/output bus GIOBUS1 or the redundancy global input/output bus RGIOBUS from the write amplifier 35. An input terminal of the write amplifier 35 is connected to the read/write bus RWBUS1 to receive data signal therefrom. The input/output circuit 41 is connected between an external input/output terminal DQ1 and a read/write bus RWBUS1 and functions as an interface circuit therebetween. The column decoder 37 receives the column address signal YADD from the address generating circuit 54 (Fig. 1) and outputs a plurality of (n) column switch signals to the column switch lines YSW11∼YSW1n. The column switch signals are obtained by decoding the column address signal YADD and are used for selecting a column of the DQ1 normal cell array 100. The data amplifier 34 has data inputs connected to the global input/output bus GIOBUS2 and the redundancy global input/output bus RGIOBUS, and accepts data signal from either of these buses. The data amplifier 34 also has a signal input for receiving a DQ2 column redundancy selection signal YREDDQ2 which selects either of the data signals from the global input/output bus GIOBUS2 or the redundancy global input/output bus RGIOBUS for inputting to the data amplifier 34. An output terminal of the data amplifier 34 is connected to the read/write bus RWBUS2 to output data signal thereto. The write amplifier 36 has data outputs connected to the global input/output bus GIOBUS2 and the redundancy global input/output bus RGIOBUS, and outputs data signal to either of these buses. The write amplifier 36 also has a signal input for receiving the DQ2 column redundancy selection signal YREDDQ2 which also selects data output path of data signal into the global input/output bus GIOBUS2 or the redundancy global input/output bus RGIOBUS from the write amplifier 36. An input terminal of the write amplifier 36 is connected to the read/write bus RWBUS2 to receive data signal therefrom. The input/output circuit 42 is connected between an external input/output terminal DQ2 and a read/write bus RWBUS2 and functions as an interface circuit therebetween. The column decoder 38 receives the column address signal YADD from the address generating circuit 54 (Fig. 1) and outputs a plurality of (n) column switch signals to the column switch lines YSW21∼YSW2n. The column switch signals are obtained by decoding the column address signal YADD and are used for selecting a column of the DQ2 normal cell array 200. The redundancy column decoder 39 receives as inputs the first column redundancy selection signal YRED1 and the second column redundancy selection signal YRED2 from the redundancy control circuit 43, and outputs redundancy column switch signals to the redundancy column switch lines RYSW1 and RYSW2. The redundancy control circuit 43 receives the column address signal YADD from the address generating circuit 54 (Fig. 1), and outputs the first column redundancy selection signal YRED1 and the second column redundancy selection signal YRED2 supplied to the redundancy column decoder 39. The redundancy control circuit 43 also outputs the DQ1 column redundancy selection signal YREDDQ1 and the DQ2 column redundancy selection signal YREDDQ2 which are supplied to the data amplifier 33 and the write amplifier 35, and the data amplifier 34 and the write amplifier 36, respectively. In FIG. 3, a block diagram depicting an example of the structure of the above-stated redundancy control circuit 43 is illustrated. As illustrated in FIG. 3, the redundancy control circuit 43 comprises redundancy address ROM's 43A and 43B which receive the column address signal YADD and generate the first column redundancy selection signal YRED1 and the second column redundancy selection signal YRED2, respectively. The redundancy addresses ROM 43A stores a column address of a defective column in the DQ1 normal cell array 100, and generates, i.e., activates the first column redundancy selection signal YRED1 when the input column address signal YADD coincides the stored column address. The redundancy addresses ROM 43B stores a column address of a defective column in the DQ2 normal cell array 200, and generates, i.e., activates the second column redundancy selection signal YRED2 when the input column address signal YADD coincides the stored column address. The redundancy address ROM is provided corresponding to each column of the redundancy memory cell array 300. Also, as anther structure, each of the column redundancy selection signals, such as the first and second column redundancy selection signals YRED1 and YRED2, may be a multi-bit address signal designating a column of the DQ1/2 redundancy cell array 300 used for replacing a defective column of the DQ1 normal cell array 100 or the DQ2 normal cell array 200. The redundancy control circuit 43 further comprises redundancy DQ ROM's 43C and 43D. The redundancy DQ ROM's 43C and 43D are used to generate the DQlcolumn redundancy selection signal YREDDQ1 and the DQ2 column redundancy selection signal YREDDQ2, indicating that a column of which normal cell array DQ1 or DQ2 is replaced by a column of the redundancy memory cell array 300. Each of the redundancy DQ ROM's 43C and 43D outputs a signal having a fixed logical level. The DQ ROM 43C corresponds to the DQ1 normal cell array 100 and the DQ ROM 43D corresponds to the DQ2 normal cell array 200. The redundancy control circuit 43 further comprises a plurality of logic gates G1 to G6. The AND logic gate G1 obtains the logical product (logical AND) of the output YRED1 of the redundancy address ROM 43A and the output of the redundancy DQ ROM 43C. The AND logic gate G2 obtains the logical product of the output YRED2 of the redundancy address ROM 43B and the output of the redundancy DQ ROM 43D. The AND logic gate G3 obtains the logical product of the output YRED1 of the redundancy address ROM 43A and the inversion of the output of the redundancy DQ ROM 43C. The AND gate G4 obtains the logical product of the output YRED2 of the redundancy address ROM 43B and the inversion of the output of the redundancy DQ ROM 43D. The OR logic gate G5 obtains the logical sum (logical OR) of the outputs of the AND logic gate G1 and the AND logic gate G2. The OR logic gate G6 obtains the logical sum of the outputs of the AND logic gate G3 and the AND logic gate 4. The outputs of the OR logic gates G5 and G6 are outputted as the DQ1 column redundancy selection signal YREDDQ1 and the DQ2 column redundancy selection signal YREDDQ2, respectively. B. Operation of the Embodiment Next, the overall operation of the semiconductor memory device in this embodiment will be described in detail with reference to the timing chart of FIG. 4. In case of a synchronous type semiconductor memory device which operates synchronously with an external clock CLK, when a mode is set to, for example, a read mode, the column address YADD is produced within the address generating circuit 54 (Fig. 1) synchronously with a rising edge of the internal clock ICLK produced from the external clock CLK in the internal clock generating circuit (ICG) 55 (Fig. 1). In the example of FIG. 4, the column addresses YADD are sequentially produced in four cycles. Among them, it is assumed that the column address YADD produced in the second cycle is a column address corresponding to a defective column in the DQ1 normal cell array 100 which should be replaced by a redundancy column of the DQ1/2 redundancy cell array 300, and that the column address YADD produced in the fourth cycle is another column address corresponding to another defective column in the DQ1 normal cell array 100 which also should be replaced by a redundancy column of the DQ1/2 redundancy cell array 300. In the first to fourth cycles, the column switch signals YSW11∼YSW1n and the column switch signals YSW21∼YSW2n change in accordance with the produced column addresses YADD. In each cycle, one of a plurality of column switch signals inputted to the DQ1 normal cell array 100 and one of a plurality of column switch signals inputted to the DQ2 normal cell array 200 are respectively activated. From the sense amplifiers connected to the activated column switch line, data are transmitted to the local input/output buses in accordance with the data written in memory cells selected by the word lines WL. Also, one of a plurality of plate selection signals PSEL1∼PSELm from the plate selection signal generating circuit 53 is activated in accordance with the row address XADD supplied from the address generating circuit 54. Due to this, one of a plurality of switch circuits of each of the DQ1 normal cell array 100 and the DQ2 normal cell array 200 is activated and the data of the local input/output bus connected to the activated switch circuit is transmitted to each of the global input/output bus GIOBUS1 and GIOBUS2. Since the column address YADD produced in the second cycle is the column address in the DQ1 normal cell array 100 to be replaced, the DQ1 column redundancy selection signal YREDDQ1 becomes an active level (H) and the first column redundancy selection signal YRED1 becomes an active level (H). In addition, since the column address YADD produced in the fourth cycle is the column address in the DQ1 normal cell array 100 to be replaced, the DQ1 column redundancy selection signal YREDDQ1 becomes an active level (H) and the second column redundancy selection signal YRED2 becomes an active level (H). Thus, in the second cycle, the redundancy column switch line RYSW1 is selected in response to the first column redundancy selection signal YRED1, and data is transmitted to the redundancy local input/output buses RLIOBUS11∼RLIOBUS1m in accordance with the data written in memory cells selected by the word lines WL from the sense amplifiers connected to RYSW1. Besides, one of a plurality of plate selection signals PSEL1∼PSELm is activated, so that the data of the redundancy local input/output bus connected to the activated switch circuit SW is transmitted to the redundancy global input/output bus RGIOBUS. Further, in the fourth cycle, the redundancy column switch line RYSW2 is selected in response to the second column redundancy selection signal YRED2, and data is transmitted to the redundancy local input/output buses RLIOBUS11∼RLIOBUS1m in accordance with the data written in the memory cells selected by the word lines WL from the sense amplifiers connected to RYSW2. Besides, the data of the redundancy local input/output bus connected to the switch circuit SW activated by the one of the plate selection signals PSEL1∼PSELm is transmitted to the redundancy global input/output bus RGIOBUS. The data amplifier 33 and write amplifier 35 are controlled such that if the DQ1 column redundancy selection signal YREDDQ1 is activated, data is not transmitted through the global input/output bus GIOBUS1 but can be transmitted through the redundancy global input/output bus RGIOBUS, and that if the DQ1 column redundancy selection signal YREDDQ1 is inactive, data is not transmitted through the redundancy global input/output bus RGIOBUS but can be transmitted through the global input/output bus GIOBUS1. The data amplifier 34 and the write amplifier 36 are controlled such that if the DQ2 column redundancy selection signal YREDDQ2 is activated, data is not transmitted through the global input/output bus GIOBUS2 but can be transmitted through the redundancy global input/output bus RGIOBUS, and that if the DQ2 column redundancy selection signal YREDDQ2 is inactive, data is not transmitted through the redundancy global input/output bus RGIOBUS but can be transmitted through the global input/output bus GIOBUS2. Accordingly, the data of global input/output bus GIOBUS1 and GIOBUS2 are transmitted to the read/write buses RWBUS1 and RWBUS2, respectively, in the first cycle; the data of the redundancy global input/output bus RGIOBUS and that of the global input/output bus GIOBUS2 are transmitted thereto, respectively, in the second cycle; the data of the global input/output buses GIOBUS1 and GIOBUS2 are transmitted thereto, respectively, in the third cycle; and the data of the redundancy global input/output bus RGIOBUS and that of the global input/output bus GIOBUS2 are transmitted thereto, respectively, in the fourth cycle. C. Another Embodiment Another embodiment of the present invention will now be explained. FIG. 5 is a block diagram showing the structure of a semiconductor memory device in another embodiment according to the present invention. In FIG. 5, elements corresponding to those in FIGs. 1 and 2 are denoted by the same reference symbols and are not explained here again. In this embodiment, the semiconductor memory device comprises the first normal cell array 100a instead of the DQ1 normal cell array 100 shown in FIGs. 1 and 2, the second normal cell array 200a instead of the DQ2 normal cell array 200, and a redundancy cell array 300a instead of the DQ1/2 redundancy cell array 300. In addition, the semiconductor memory device of Fig. 5 does not comprise an input/output circuit 42, a read/write bus RWBUS2, and an input/output terminal DQ2 shown in Figs. 1 and 2. A data amplifier 34 and a write amplifier 36 are connected to an input/output circuit 41 through a read/write bus RWBUS1. In the embodiment of Figs. 1 and 2, a common redundancy cell array 300 is used for the normal cell arrays 100 and 200 corresponding to different input/output terminals DQ1 and DQ2, whereas, in this embodiment, a common redundancy cell array 300a is used for the first normal cell array 100a and the second normal cell array 200a which are connected to different data amplifiers and write amplifiers that are connected to a single common input/output terminal DQ1. As in the case of the embodiment of FIGs. 1 and 2, data is normally transmitted through different local input/output buses and global input/output buses. After a defective cell is replaced with a redundancy cell, data is transmitted through common redundancy local input/output buses and a column redundancy global input/output bus. D. Advantages of Embodiments Next, advantages of the above-stated embodiments will be described. Consider, as an example, a case where, in the structure of Figs. 1 and 2, column address space is Y = 0 to 255, the number of normal cell arrays is two, that is, 256 column switch lines are provided for each of the DQ1 normal cell array and DQ2 normal cell array, and four redundancy column switch lines, that is four spare columns, are prepared as a whole. In the conventional technique, two spares are allotted to each of the DQ1 normal cell array and DQ2 normal cell array, in such constitution. At this time, the relief probability Q1 when there is one defective column line as a whole and the relief probability Q2 when there are two defective lines as a whole are obviously both 100%. To relieve three defective lines, one defective line and two defective lines must be allotted to DQ1 normal cell array and DQ2 normal cell array, respectively, and vice versa. Thus, in this case, the relief probability Q3 is: Q3 = (1 - 2/2 3 ) x 100 = 75 (%). Likewise, when there are four defective lines, probability Q4 is: Q4 = {1 - ( 4 C 2 )/2 4 } × 100 = 37.5 (%). Further, when there are five or more defective lines, relief probability is obviously 0%. Meanwhile, according to the present invention, four spares can be used for both DQ1 normal cell array and DQ2 normal cell array. When there is one defective line as a whole, the probability R1 is obviously 100%. As for probability R2 at which two defective lines are relieved, however, it is necessary to suppose that, if the one of the two defective lines is for DQ1 normal cell array while the other is for DQ2 normal cell array and they have the same column address, the defective lines are not relieved. This is because only one redundancy global input/output bus is prepared for DQ1 normal cell array and DQ2 normal cell array and data collide against each other when accessed simultaneously through DQ1 normal cell array and DQ2 normal cell array. Due to this, the probability R2 is: R2 = {1 - 1/(512 - 1)} × 100 = 99.998 (%). Relief probabilities R3 and R4 when there are three and four defective lines as a whole, respectively are: R3 = {1-1/(512-1)} x 3 C 1 x 100 = 99.414(%); and R4 = {1-1/(512-1)} x 4 C 2 x 100 = 98.826 (%). Needless to say, when the number of defective lines is five or more as a whole, the relief probability is 0%. As can be understood from the above, when the number of defective lines are three and four, relief probabilities are greatly improved from those of the conventional memory device. When the number of defective lines is two, the relief probability is slightly lower than the probability of the conventional memory device. However, improvements at the time of three and four defective lines are much higher and, as a whole, greater advantage can thus be expected in the present invention. As described above, according to the present invention, a common redundancy memory cell array is provided for a plurality of memory cell arrays to be read or written through different buses, and a common bus is used for reading or writing the redundancy memory cell array. Also, data for each of the plurality of memory cell arrays and data for the common redundancy memory cell array are transmitted through a common bus between, for example, the data amplifier/the write amplifier and the input/output terminal. Thus, it is possible to efficiently utilize the redundancy memory cells, and to advantageously increase the relief probability of defective memory cells. In the foregoing specification, the invention has been described with reference to specific embodiments. However, one of ordinary skill in the art appreciates that various modifications and changes can be made without departing from the scope of the present invention as set forth in the claims below. For example, in the above embodiments, one redundancy memory cell array is provided for two normal cell arrays. However, one redundancy memory cell array can be used to relief more than two normal cell arrays. Also, it is possible to provide a plurality of redundancy memory cell arrays each corresponding to a set of normal cell arrays. Accordingly, the specification and figures are to be regarded in an illustrative sense rather than a restrictive sense, and all such modifications are intended to be included within the scope of the present invention. Therefore, it is intended that this invention encompasses all of the variations and modifications as fall within the scope of the appended claims.

Claims: A semiconductor memory device having a plurality of memory cell arrays (100, 200), each memory cell array (100, 200) having a plurality of memory cell groups (1, 2, 3, 4; 7, 8, 9, 10), each of said memory cell groups (1, 2, 3, 4; 7, 8, 9, 10) being connected via a local bus (LIOBUS11 to LIOBUS1m; LIOBUS21 to LIOBUS2m) to a cell array global bus line (GIOBUS1, GIOBUS2) commonly shared by each of said memory cell groups (1, 2, 3, 4; 7, 8, 9, 10) of each memory cell array (100, 200), data for said plurality of memory cell arrays (100, 200) being transmitted through mutually different buses in a first section, said first section being a part of a path for reading or writing said plurality of memory cell arrays (100, 200), said semiconductor memory device comprising: a redundancy memory cell array (300) common to said plurality of memory cell arrays (100, 200), said redundancy memory cell array (300) having a redundancy memory cell array global bus line (RGIOBUS), said redundancy memory cell array (300) having a plurality of redundancy memory cell groups (5, 6, 11, 12), each of said redundancy memory cell groups (5, 6, 11, 12) being connected via a local bus (RLIOBUS11 to RLIOBUSS1m) to said redundancy cell array global bus line (RGIOBUS); a redundancy control circuit (43) for generating a selection control signal depending on whether or not an input column address (YADD) coincides with a defective column address of one of said plurality of memory cell arrays (100, 200) corresponding to a column including at least one defective memory cell; and a bus selecting circuit coupled to said redundancy control circuit (43) for selectively coupling, in response to said selection control signal, the cell array global bus line (GIOBUS1) in said first section for reading or writing each of said plurality of memory cell arrays (100, 200) or the redundancy memory cell array global bus line (RGIOBUS) in said first section for reading or writing said redundancy memorycell array (300) with a bus in a second section which is provided commonly to said plurality of memory cell arrays (100, 200) and said redundancy memory cell array (300), and said second section being another part of the path for reading or writing said plurality of memory cell arrays (100, 200) and said redundancy memory cell array (300). The semiconductor memory device according to claim 1, wherein said bus selecting circuit is connected to said redundancy memory cell array (300) and said plurality of memory cell arrays (100, 200) by said first section comprising said redundancy memory cell array global bus line (RGIOBUS) and said cell array global bus lines (GIOBUS1, GIOBUS2), each one of said cell array global bus lines (GIOBUS1, GIOBUS2) corresponding to one of said plurality of memory cell arrays (100, 200). The semiconductor memory device according to claim 1, wherein said second section is a path between said bus selecting circuit and an input/output terminal (DQ1, DQ2) of said semiconductor memory device. A semiconductor memory device according to claim 1, wherein each of said plurality of memory cell arrays (100, 200) is provided corresponding to every different input/output terminal (DQ1, DQ2) of said semiconductor memory device. A semiconductor memory device according to claim 1, wherein said plurality of memory cell arrays (100, 200) are provided corresponding to a common input/output terminal. A semiconductor memory device according to claim 1, wherein said plurality of memory cell arrays (100, 200) comprises the first memory cell array (100) and the second memory cell array (200), and each of said first memory cell array (100) and said second memory cell array (200) is provided corresponding to every different input/output terminal (DQ1, DQ2) of said semiconductor memory device; when memory cells of said first memory cell array (100) are replaced with memory cells of said redundancy memory cell array (300), data of said redundancy memory cells is controlled to be transmitted through a bus common to the first memory cell array (100) in said second section; and when memory cells of said second memory cell array (200) are replaced with memory cells of said redundancy memory cell array (300), data of said redundancy memory cells is controlled to be transmitted through a bus common to the second memory cell array (200) in said second section. A semiconductor memory device according to claim 1, wherein said plurality of memory cell arrays (100, 200) comprises the first memory cell array (100) and the second memory cell array (200), and said first memory cell array (100) and said second memory cell array (200) are provided corresponding to a common input/output terminal (DQ1, DQ2); when memory cells of said first memory cell array (100) are replaced with memory cells of said redundancy memory cell array (300), data of said redundancy memory cells is controlled to be transmitted through a bus common to the first memory cell array (100) in said second section; and when memory cells of said second memory cell array (200) are replaced with memory cells of said redundancy memory cell array (300), data of said redundancy memory cells is controlled to be transmitted through a bus common to the second memory cell array (200) in said second section. A method for relieving defective memory cells in a semiconductor memory device having a plurality of memory cell arrays (100, 200), each memory cell array (100, 200) having a plurality of memory cell groups (1, 2, 3, 4; 7, 8, 9, 10), each of said memory cell groups (1, 2, 3, 4; 7, 8, 9, 10) being connected via a local bus (LIOBUS11 to LIOBUS1m, LIOBUS21 to LIOBUS2m) to a cell array global bus line (GIOBUS1, GIOBUS2) commonly shared by each of said memory cell groups (1, 2, 3, 4; 7, 8, 9, 10) of each memory cell array (100, 200), data for said plurality of memory cell arrays (100, 200) being transmitted through mutually different buses in a first section, said first section being a part of path for reading or writing said plurality of memory cell arrays (100, 200), wherein said method comprises: providing the redundancy memory cell array (300) common to said plurality of memory cell arrays (100, 200), said redundancy memory cell array (300) having the redundancy memory cell array global bus line (RGIOBUS), said redundancy memory cell array (300) having the plurality of redundancy memory cell groups (5, 6, 11, 12), each of said redundancy memory cell groups (5, 6, 11, 12) being connected via the local bus (RLIOBUS11 to RLIOBUS1m) to said redundancy cell array global bus line (RGIOBUS); determining whether the input column address (YADD) coincides with a column address of a defective column in one of said plurality of memory cell arrays (100, 200); and in case said input column address (YADD) coincides with a column address of a defective column in one of said plurality of memory cell arrays (100, 200) transmitting data of said redundancy memory cell array (300) in place of the data of said defective column in one of said plurality of memory cell arrays (100, 200) through a bus common to said one of said plurality of memory cell arrays (100, 200) in a second section, said second section being another part of the path for reading or writing said plurality of memory cell arrays (100, 200). The method for relieving defective memory cells in a semiconductor memory device according to claim 8, wherein each of said plurality of memory cell arrays (100, 200) is provided corresponding to every different input/output terminal (DQ1, DQ2) of said semiconductor memory device. The method for relieving defective memory cells in a semiconductor memory device according to claim 8, wherein said plurality of memory cell arrays (100, 200) are provided corresponding to a common input/output terminal.

Inventors: KOSHIKAWA YASUJI, MINE KOUJI, NOBUTOKI TOMOKO, KOSHIKAWA, YASUJI, MINE, KOUJI, NOBUTOKI, TOMOKO, Koshikawa, Yasuji c/o NEC Corporation, Mine, Kouji c/o NEC Corporation, Nobutoki, Tomoko c/o NEC Corporation
Applicants: NIPPON ELECTRIC CO, NEC CORPORATION
Application year: 1999
Main classification: G06F11
IPC codes: G11C11, G11C29