Optical receiver module, phase-locked loop circuit, voltage-controlled oscillator and frequency response controllable amplifier

Abstract: Two sets of a high speed differential amplifier (43) and a low speed differential amplifier (44) are prepared, and frequency response speeds of these high speed/low speed differential amplifiers are different from each other. Both an oscillating frequency and a frequency modulation sensitivity of a ring oscillator type voltage-controlled oscillator circuit (1) can be separately set by adding two outputs of these differential amplifiers to each other and by varying the selection ratio of these high speed/low speed differential amplifiers in a linear manner. Thus, the setting ranges for the oscillating frequency and the frequency modulation sensitivity are enlarged. At this time, since a summation of currents flowing through the high speed/low speed differential amplifiers is continuously made constant, the oscillating frequency depending characteristic of the output amplitude of the VCO circuit can be canceled. Furthermore, since control signals are supplied in a differential structure, increasing of jitter components caused by the common mode noise can be suppressed.

Description: BACKGROUND OF THE INVENTION The present invention is related to a voltage-controlled oscillator circuit (VCO) for constituting a phase-locked loop (PLL) circuit. This phase-locked loop circuit produces a clock signal in synchronism with input data and/or an input clock in an optical transmitter module and an optical receiver module used in an optical communication. A voltage-controlled oscillator circuit (VCO) for constituting a phase-locked loop (PLL) circuit which produces a clock signal in synchronism with input data and also an input clock, corresponds to such an oscillator. An oscillating frequency of this VCO circuit is varied in response to a control voltage. In general, there are a multivibrator type VCO and a ring oscillator type VCO with respect to a VCO used in an integrated circuit (IC). In the case of a ring oscillator type VCO, since this VCO may be constructed only of transistors and resistors, this ring oscillator type VCO may be manufactured in the form of an IC. Also, in principle, since 4-phase clocks are outputted in which a phase of an oscillator signal is shifted by n/2, n, and 3π/2, this ring oscillator type VCO owns the following merit. That is, when a frequency comparator is arranged by employing such a ring oscillator type VCO, a necessary π/2-delay signal can be produced without employment of an additional circuit. In Fig. 1, a typical ring oscillator circuit is indicated. An oscillation is initiated by such a way that outputs derived from two-staged differential amplifiers are supplied as inputs to the corresponding differential amplifiers in a positive feedback manner, so that V0, V90, V180, and V270 corresponding to 4-phase clock signals can be obtained. As an item indicative of a characteristic of a VCO circuit, there are an oscillating frequency and a frequency modulation sensitivity. This frequency modulation sensitivity represents a degree of changes in the oscillating frequencies with respect to a control voltage. In this type of system, an oscillating frequency is determined by a transition (cut-off) frequency "f T " of a transistor. In general, a transition frequency of a bipolar type transistor is expressed by the below-mentioned equation (1), assuming now that a collector-to-base capacitance is "Cbc", a base-to-emitter capacitance is "Cbe", and a mutual conductance is "g m ": f T =g m /2π (C bc +C be ) where the values of "Cbc" and "Cbe" depend upon a device fabrication technology. Also, assuming now that an elementary electric charge is "q", a collector current is "Ic", the Boltzmann constant is "k", and an absolute temperature is "T", the mutual conductance "g m " may be expressed by the following equation (2), and is directly proportional to the collector current: g m = (q.I c )/(k.T) As a consequence, the oscillating frequency can be controlled by controlling the voltage "Vcont" shown in Fig. 1, and by varying an amount of a current "I1" flowing through the differential amplifier, and this ring oscillator may function as a voltage-controlled oscillator. As apparent from the above-described equation (1), the frequency modulation sensitivity indicative of a change in the oscillating frequencies with respect to a change in the control voltages will depend upon both Cbc and Cbe. Both Cbc and Cbe may be controlled in such a manner that while a plurality of transistors are employed, base, collector, and emitter terminals thereof are connected in parallel to each other. For example, when "n" pieces of transistors are connected in parallel to each other, a collector-to-base capacitance becomes "nCbc" and a base-to-emitter capacitance becomes "nCbe". In this ring oscillator circuit, the parallel element number of the transistors which constitute the differential transistor pairs is varied so as to change these capacitances "Cbc" and "Cbe", so that the frequency modulation sensitivity can be set. Such a system for controlling the oscillating frequency by controlling the currents of the differential transistor pairs is known from, for example, JP-A-9-326676. In the related ring oscillator type VCO circuit, both Cbc and Cbe are changed by the parallel element number of the transistors of the differential pairs, so that the frequency modulation sensitivity is set. However, these capacitance values Cbc and Cbe are also related to the transition frequency, and therefore may give an adverse influence to the oscillating frequency. To set the oscillating frequency, this oscillating frequency is controllable by the collector current value in accordance with the above-explained equations (1) and (2). In a practical transistor, a range capable of satisfying the above-explained equation (2) is finite, and therefore, a setting width of an oscillating frequency is also finite. As previously explained, in this system, it is practically difficult to set both the oscillating frequency and the frequency modulation sensitivity to desirable values, respectively. In other words, in this VCO circuit, as to the oscillating frequency, the transition frequency "f T " of the transistor is varied by controlling the values of the currents flowing through the differential transistor pairs so as to control the oscillating frequency, whereas as to the frequency modulation sensitivity, this frequency modulation sensitivity is set to a desirable value by varying the capacitance values. However, since the capacitance values are also related to the oscillating frequency, it is practically difficult to design both the oscillating frequency and the frequency modulation sensitivity to the desirable values at the same time. Also, in the related system, since the frequency of the oscillator is controlled by the values of the currents flowing through the differential pairs, the output amplitude of the oscillator becomes R x (I1+ΔI), assuming now that the resistance values R1 to R4 connected to the differential transistor pairs are equal to "R", and a change amount of currents is "ΔI". As a result, there are such problems that the output amplitude of the oscillator owns the current depending characteristic, and therefore, the phase detection sensitivity at the phase comparator may change due to this behavior. Furthermore, in the circuit system shown in Fig. 1, when noise is mixed with the current source control voltage Vcont, both the oscillating frequency and the output amplitude are changed, the jitter contained in the output signal are readily increased. A voltage-controlled ring-type oscillator with the features included in the first part of claim 1 is known from US-A-5,668,505 and also from S. K. Enam et al. "A 300-MHz CMOS Voltage-Controlled Ring Oscillator", IEEE Journal of Solid-State Circuits, vol. 25, No. 1, February 1990, pages 312-315. In these prior-art circuits, the differential amplifiers in either frequency-response controllable amplifier stage are connected in series, and the differential amplifiers of both amplifier stages are connected in series in forming a slow loop. SUMMARY OF THE INVENTION The present invention seeks to solve the above-described problems by providing a voltage-controlled ring-type oscillator, a phase-locked loop (PLL) circuit with an increased design flexibility and enlarged ranges for setting the oscillating frequency and the frequency modulation sensitivity. Furthermore, the output amplitude should be independent of the oscillating frequency, and jitter caused by common mode noise should be suppressed. The above objects are achieved by the voltage-controlled ring-type oscillator defined in claim 1, the phase-locked loop defined in claim 4 and the optical receiver defined in claim 5. The ring oscillator type voltage controller is arranged in such a manner that the parallel connection number of the transistors is changed; two sets of the high speed/low speed differential amplifiers having the different frequency response speeds from each other are prepared; the output signals derived from the high speed/low speed differential amplifiers are summed; and then the selection ratio of these high speed/low speed differential amplifiers is varied in a linear manner. As a result, both the oscillating frequency and the frequency modulation sensitivity can be separately set. In other words, both the oscillating frequency of the high speed differential amplifier and the oscillating frequency of the low speed differential amplifier are set in such a manner that the desirable oscillating frequency variable ranges can be obtained. The selection ratio of these high speed/low speed differential amplifiers is voltage-controlled so as to set the control sensitivities thereof. As a consequence, the desirable frequency modulation sensitivities can be obtained. Also, when the high speed differential stage and the low speed differential stage are selectively controlled, since the VCO circuit is arranged in such a manner that the summation of the current flowing through the high speed differential stage and the current flowing through the low speed differential stage is made constant, the oscillating frequency depending characteristic of the output amplitude can be canceled. Also, since the voltage used to control the oscillating frequency may be applied by the differential arrangement, increasing of the jitter caused by the common mode noise can be suppressed. BRIEF DESCRIPTION OF THE DRAWINGS For a better understanding of the present invention, reference is made of a detailed description to be read in conjunction with the accompanying drawings, in which: Fig. 1 is a circuit diagram for showing the relevant ring oscillator circuit; Fig. 2 is a block diagram for representing a ring oscillator type voltage-controlled oscillator (VCO) according to an embodiment of the present invention; Fig. 3 indicates a concrete circuit arrangement of the voltage-controlled oscillator according to the embodiment of the present invention; Fig. 4 is a schematic block diagram for showing an arrangement of an optical receiver module according to the present invention; and Fig. 5 is a schematic block diagram for indicating an arrangement of a phase-blocked loop (PLL) circuit according to the present invention. DESCRIPTION OF THE EMBODIMENT Referring now to drawings, a description will be made of a ring oscillator type voltage-controlled oscillator circuit (VCO circuit); a phase-locked loop (PLL) circuit (timing extraction circuit) which is equipped with this VCO circuit, and is constructed of a single semiconductor chip; and also a digital optical receiver module used in an optical communication and equipped with the timing extraction circuit arranged by this PLL circuit. First, a ring oscillator type voltage-controlled oscillator circuit (VCO circuit) according to an embodiment of the present invention will now be described in detail. This ring oscillator type voltage-controlled oscillator circuit is arranged as follows: First, a frequency response controllable amplifier 1 is constituted by that at least two sets of a high speed current distributor 43 and a low speed current distributor 44 are prepared, the frequency response speeds of which are different from each other. A DC current distributor 42 controlled by a voltage of "Vcont" is employed so as to vary a current ratio of a current flowing through the low speed current distributor 43 to a current flowing through the high speed current distributor 44. A summation of the currents flowing through the respective current distributors 43 and 44 becomes continuously constant by way of a DC current source 41. Then, an output signal from the high speed current distributor 43 is added to an output signal from the low speed current distributor 44 by an adder 45, and the added signal is outputted via an output buffer 46. Similarly, another frequency response controllable amplifier 2 is constituted by that at least two sets of a high speed current distributor 49 and a low speed current distributor 50 are prepared, the frequency response speeds of which are different from each other. A DC current distributor 48 controlled by the voltage of Vcont is employed so as to vary a current ratio of a current flowing through the low speed current distributor 49 to a current flowing through the high speed current distributor 50. A summation of the currents flowing through the respective current distributors 49 and 50 becomes continuously constant by way of the DC current source 41. Then, an output signal from the high speed current distributor 49 is added to an output signal from the low speed current distributor 50 by an adder 51, and the added signal is outputted via an output buffer 52. As explained above, while another frequency response controllable amplifier 2 having the same arrangement as that of the frequency response controllable amplifier 1 is prepared, the respective outputs V0 and V90 of these frequency response controllable amplifiers 1 and 2 are entered into the opposite current distributors 49/50 and 43/44 in a positive feedback manner, so that these frequency response controllable amplifiers 1 and 2 are operated as the voltage-controlled oscillator (VCO) circuit. Fig. 3 is a circuit diagram for showing an embodied example of the above-described ring oscillator type voltage-controlled oscillator circuit. In this VCO circuit, at least two sets of high speed differential stages and low speed differential stages H1, L1; H2, L2 are prepared, the frequency response speeds of which are different from each other. Also, parallel connection numbers of transistors of these differential stages H1, L1; H2, L2 are different from each other. The output signals derived from these high speed/low speed differential stages H1, L1; H2, L2 are summed to each other (namely, with respect to Vcc, collectors of transistors for constituting respective high speed/low speed differential stages H1, L1; H2, L2 are connected by resistors R1 to R4). At this stage, while a summation of currents flowing through the high speed differential stage and the low speed differential stage becomes constant, values of the currents flowing through the respective differential stages are varied in a linear manner by base voltages (Vfup and Vfdown shown in Fig. 3) of differential transistor pairs Tr1, Tr2; Tr4, Tr3 provided at lower stages of the respective differential stages, and the high speed differential stage and the low speed differential stage are selected. As a result, the oscillation frequency of the VCO circuit can be controlled. Assuming now that capacitance values of transistors of the high speed and low speed differential stages H1, L1; H2, L2 are set as (Cbc1+Cbe1) and (Cbc2+Cbe2), transition frequencies "f T 1" and "f T 2" of the respective transistors are expressed by the below-mentioned equations 3 and 4, and the oscillating frequency of the VCO circuit can be controlled in a linear manner between the oscillating frequency of the high speed differential stage and the oscillating frequency of the low speed differential stages. It should be understood that symbol "Cbc" indicates a collector-to-base capacitance of a transistor, symbol "Cbe" shows a base-to-emitter capacitance of a transistor, and symbol "gm" represents a mutual conductance: f T 1=g m /2π(C bc1 +C be1 ) and f T 2=g m /2π(C bc2 +C be2 ) Also, as to a frequency modulation sensitivity, in the differential transistor pairs Tr1, Tr2; Tr4, Tr3 for selecting the high speed differential stage and the low speed differential stage, resistors R5 to R8 are additionally provided between emitter coupling, so that a voltage control sensitivity can be set and thus a desirable frequency modulation sensitivity can be obtained. As previously explained, in the case that both the oscillating frequency and the frequency modulation sensitivity are designed, first of all, the capacitance values of both the high speed differential stage and the low speed differential stage are determined based on a desirable oscillating frequency range, and the parallel connection number of the transistors is determined. As to the frequency modulation sensitivity, since the voltage control sensitivity of the selection ratio for the high speed differential stage and the low speed differential stage is set, both the oscillating frequency and the frequency modulation sensitivity can be separately set. Also, since the constant current sources I1; I2 are used in such a manner that the summation of the current flowing through the high speed differential stage and also the current flowing through the low speed differential stage becomes constant, even when the oscillating frequency is controlled, the output amplitude is continuously equal to RxI, and therefore, there is no oscillating frequency depending characteristic of the output amplitude. Further, since the voltage for controlling the oscillating frequency may be applied by the differential circuit arrangement according to this embodiment system, increasing of the jitter caused by the common mode noise can be suppressed. It should also be noted that the respective transistors Tr5, Tr6, Tr7, and Tr8 constitute the output buffers 46 and 52. Furthermore, each of I3 to I6 is a constant current source which is connected to an emitter of each of the transistors Tr5, Tr6, Tr7, and Tr8. Next, referring now to Fig. 4 and Fig 5, a description is made of a phase-locked loop (PLL) circuit (timing extraction circuit) 15, and a digital optical receiver module 10. This PLL circuit 15 is equipped with the above-described ring oscillator type voltage-controlled oscillator circuit (VCO circuit) 23, and is constituted by a single semiconductor chip. The digital optical receiver module 10 is equipped with the timing extraction circuit 15 arranged by this PLL circuit 15, and is utilized in an optical communication. As indicated in Fig. 5, the phase-locked loop (PLL) circuit 15 is arranged by the voltage-controlled oscillator (VCO) 23, a phase and frequency comparator 21, and a loop filter 22. The VCO 23 corresponds to such an oscillator, the oscillating frequency of which is varied by the control voltage, and the oscillating frequency outputted from this VCO 23 is fed back to the phase/frequency comparator 21. In other words, the phase-locked loop (PLL) circuit 15 contains the voltage-controlled oscillator 23; the phase/frequency comparator 21 for comparing phases and frequencies with respect to the oscillating frequencies outputted from this voltage-controlled oscillator 23 and the entered data; and the loop filter 22 for rejecting a high frequency noise from the control voltage signal outputted from this phase/frequency comparator 21. Then, this phase-locked loop circuit 15 is arranged in such a way that a control voltage signal derived from this loop filter 22 is entered into the above-explained voltage-controlled oscillator 23. As indicated in Fig. 4, the digital optical module 10 which is equipped with the timing extraction circuit 15 constituted by the PLL circuit 15 and is used in the optical communication is arranged by a photo-detector 12, a pre-amplifier 13, a post-amplifier 14, the timing extraction circuit 15, and a decision and regeneration circuit 16. In an optical fiber communication, an optical signal transmitted from an optical transmitter module is transferred to the optical receiver module 10 while using an optical fiber 11, and then is converted into an original electric signal by the optical receiver module 10. In other words, the optical receiver module 10 is constituted by the photodetector 12 for receiving the transmitted optical signal, the amplifiers 13 and 14 for amplifying the signal received by this photodetector 12, the above-explained phase-locked loop circuit 15, the timing extraction circuit 15, and also the decision and regeneration circuit 16. The timing extraction circuit 15 produces a clock signal, and this clock signal is synthesized with the data signal acquired by the amplifier 14. The decision and regeneration circuit 16 decides/regenerates the data signal acquired from the amplifier 14 by employing the clock signal obtained from the timing extracting circuit 15 to thereby output the regenerated data signal. As a consequence, both the timing extraction circuit 15 and the decision/regeneration circuit 16 produce the clock signal in synchronism with the input data, and decide/regenerate the input signal with employment of this produced clock signal. The timing extract circuit and the decision/regeneration circuit can be fabricated in an integrated circuit by using the phase-locked loop (PLL) technique, so that the digital optical receiver module 10 can be made compact and in low cost. Subsequently, a digital optical transmitter module will now be explained. One of major objects to use the phase-locked loop (PLL) circuit according to the present invention in the digital optical transmitter module is to correct distortion of a pulse width. In such a case that only data signal to be transmitted is applied to the digital optical transmitter module, there are provided a phase-locked loop circuit having a similar circuit arrangement to that of the above-explained optical receiver module, an optical device driver circuit, and a flip-flop circuit at a prestage of this optical device driver circuit. Both the data signal and the clock extracted from the output signal of the phase-locked loop circuit are inputted to the flip-flop circuit, and then an output signal from the flip-flop circuit is entered into the optical device drive circuit. As a result, even when the data signal contains the pulse width distortion to some extent, the pulse width distortion can be corrected by using the extracted clock. Another major object to use the phase-locked loop (PLL) circuit according to the present invention is to suppress a jitter. In the case that both a clock signal and a data signal to be transmitted are supplied to the optical transmitter module, when this optical transmitter module is arranged by employing a similar arrangement to that for processing the clock signal, even if the clock signal contains the jitter to some extent, this optical transmitter module can suppress this jitter by using the flip-flop circuit and the extracted clock. As another application example of the digital optical transmitter module, the following optical transmitter module is conceivable. While both a data signal to be transmitted and a clock signal are applied to such an optical transmitter module, a code conversion circuit is employed, and another clock signal two times higher than the first-mentioned clock signal is required for the code conversion. If one set of a prescaler circuit is provided in a circuit loop defined from a voltage-controlled oscillator (VCO) to a phase/frequency comparator, then a clock signal having a clock frequency two times higher than that of the first-mentioned clock signal can be obtained. As this application example, for instance, the CMI (Coded Mark Inversion) code for requiring the twice frequency clock signal in the coding/decoding operation is conceivable. In accordance with the application example, other desirable clocks can be extracted. Alternatively, the twice frequency clock signal may be employed not only in the optical transmitter module, but also may be used in the decoder circuit of the optical receiver module. It should be understood that the operating speeds which can be applied to the above-explained technique according to the present invention are very wide from the low speed system defined by ITU-T (International Telecommunication Union-Telecommunication Standardization Sector) up to the high speed system. In particular, the technique according to the present invention may be advantageously applied to the layers of STM-4 (622.08 Mbit/s) and STM-16 (2.48832 Gbit/s). Apparently, this present technique may be employed even in other operating speeds. In accordance with the present invention, the below-mentioned effects can be achieved. That is, both the oscillating frequency and the frequency modulation sensitivity can be separately set. The setting ranges of the respective oscillating frequency and frequency modulation sensitivity can be effectively enlarged. As the voltage-controlled oscillator (VCO), and furthermore, as the phase-locked loop (PLL) circuit, a flexibility of designing of these circuits can be increased. Also, in accordance with the system of the present invention, when the high speed differential stage and the low speed differential stage are selectively controlled, since the VCO circuit is arranged in such a manner that the summation of the current flowing through the high speed differential stage and the current flowing through the low speed differential stage is made constant, the oscillating frequency depending characteristic of the output amplitude can be canceled. Also, in accordance with the system of the present invention, since the voltage used to control the oscillating frequency may be applied by the differential arrangement, increasing of the jitter component caused by the common mode noise can be suppressed. Furthermore, in accordance with the system of the present invention, since both the timing extraction circuit and the decision/regeneration circuit with employment of the phase-locked loop (PLL) technique can be manufactured in the IC form, the digital optical transmitter module and the digital optical receiver module can be made compact and in low cost.

Claims: A voltage-controlled ring-type oscillator comprising at least two frequency-response controllable amplifier stages incuding differential amplifiers (43, 44, 49, 50) of different frequency response speed, characterised in that each said frequency-response controllable amplifier stage includes a high speed differential amplifier (43; 49) and a low speed differential amplifier (44; 50); an adder (45; 51) for forming the sum of the outputs of said high and low speed amplifiers (43, 44; 49, 50); and a direct current distributor (42; 48) for varying the selection ratio between said high and low speed amplifiers (43, 44; 49, 50), wherein the oscillating frequency and the frequency modulation sensitivity are separately set to predetermined values. The oscillator of claim 1, wherein the sum of the currents flowing through said high and low speed amplifiers (43, 44; 49, 50) is made constant, and a characteristic of the output amplitude depending on the oscillation frequency is eliminated. The oscillator of claim 1 or 2, wherein control signals are supplied in differential fashion to said high and low speed amplifiers (43, 44; 49, 50). A phase-locked loop circuit comprising a ring oscillator type voltage-controlled oscillator according to any preceding claim. An optical receiver comprising a photodetector (12) for receiving a transmitted optical signal, an amplifier (13, 14) for amplifying the optical signal received by said photo-detector (12), a phase-locked loop (15) according to claim 4, a timing extraction circuit for producing a clock signal in synchronism with a data signal derived from said amplifier (13, 14); and a decision and regeneration circuit (16) for deciding and regenerating the data signal derived from said amplifier (13, 14) by employing said clock signal.

Inventors: AKASHI MITSUO, BABA NAOHIKO, HAYAMI AKIHIRO, IRIE HIROKI, KIKUCHI TOMONAO, YAMADA YASUHIRO, AKASHI, MITSUO, BABA, NAOHIKO, HAYAMI, AKIHIRO, IRIE, HIROKI, KIKUCHI, TOMONAO, YAMADA, YASUHIRO
Applicants: OPNEXT JAPAN INC, OPNEXT JAPAN, INC.
Application year: 1999
Main classification: H03K3
IPC codes: H04B10, H03G3, H03L7, H03K3, H04L7