APPARATUS AND METHOD FOR CLOCKING DIGITAL AND ANALOG CIRCUITS ON A COMMON SUBSTRATE TO ENHANCE DIGITAL OPERATION AND REDUCE ANALOG SAMPLING ERROR

Abstract: An apparatus and method for clocking digital and analog circuits on a common substrate is provided. The apparatus and method serves to reduce digitally derived noise at select times during which the analog input signal is sampled. Analog sampling error is thereby reduced while, at the same time, the digital clocking signal maintains maximum frequency. Digitally derived noise is substantially eliminated near the latter portion of each sampling interval to ensure an accurate sampled value exists at the culmination of that interval. During the earlier portion of each sampling interval, digital clocking pulses are maintained at a high frequency so as to enhance processing speeds. It is determined that only the latter portion of each sample interval is critical to the reduction of sampling error. Furthermore, the digital clocking pulses occur a non-power-of-two factor to ensure tonal noise is not coupled into the analog circuit frequency band of interest.

Description: TITLE: APPARATUS AND METHOD FOR CLOCKING DIGITAL AND ANALOG CIRCUITS ON A COMMON SUBSTRATE TO ENHANCE DIGITAL OPERATION AND REDUCE ANALOG SAMPLING ERROR BACKGROUND OF THE INVENTION 1 Field of the Invention This invention relates to a monolithic semiconductor substrate embodying both digital and analog circuits and, more particularly, to an apparatus and method for reducing noise transferred from digital circuits to analog circuits without limiting digital circuit performance 2 Description of the Relevant Art Integrated circuits which embody both analog and digital circuitry on the same monolithic substrate are well known. Examples of such integrated circuits include audio acquisition and/or transmission products Audio acquisition includes any device which receives and records an audio waveform, and which samples and quantizes that waveform according to discrete time intervals. Audio transmission may include digital audio reproduction — i.e., demodulation and digital processing circuits necessary to manipulate digital information. Audio acquisition can be accomplished using vaπous types of modulation schemes, such as pulse code modulation, delta-sigma modulation, etc. Regardless of the modulation scheme used, proper audio recording requires the incoming analog signal be sampled at a frequency of at least twice the incoming audio frequency to achieve error-free sampling. Sampling less than the aforesaid minimum causes aliasing problems. During each sample interim, quantization is used to preserve corresponding amplitude information While samplmg records time slices, quantization records amplitude information within each time slice. The combination of sampling and quantization for a given modulation technique thereby completely preserves the audio signal in digital form Accordingly, audio acquisition must employ analog circuitry useful in sampling (e.g., sample-and-hold circuits) and quantization (e.g., clocked comparator circuits). Once an analog audio signal is sampled and converted to digital format, the resulting digital signal can thereafter be forwarded back as an analog signal using vaπous audio reproduction techniques. Generally speaking, audio reproduction includes, for example, demodulation circuits, reproduction processing circuits, demultiplexers, digital-to-analog converters, output sample-and-hold circuits, etc. Accordingly, digital audio reproduction is necessary to present back, possibly m digitally processed form, the analog signal previously recorded through analog acquisition. Generally configured between circuits which perform digital audio acquisition and circuits which perform digital audio reproduction is a digital signal processor (DSP). A DSP is used to manipulate digitally acquired binary numbers. The ease by which digital numbers can be manipulated by a DSP adds importance to reasons why it may be desirable to convert an analog audio signal to a digital audio signal, and why the manipulated data can thereafter be converted back to analog form Once the analog audio signal is converted to digital, the DSP can easily perform rapid manipulation of that data DSP operations are prevalent in the telecommunication industry, and are usually found in modems, vocoders and transmultiplexers. etc Examples of circuits used to convert an analog audio signal to a digital signal is an analog/digital ("A/D") converter A digital-to-analog circuit is often referred to as a ("D/A") converter Placmg the DSP between the A/D and D/A converter allows manipulation of the digital information preferably in real time There may be instances in which multiple A/D and D/A converters are present with multiple DSPs and possibly multiple microprocessors on a monolithic substrate A clock manager may be used to clock the multiple digital and analog subsystems embodied upon the substrate. An unfortunate aspect of digital circuitry is the noise created whenever a digital signal transitions between logic 0 and logic 1 values If digital and analog circuits are to be used on the same monolithic substrate, steps must be taken to minimize transferal of digitally created noise to analog circuits during those transitory times Steps must also be taken to maximize DSP performance To maximize DSP performance, the digital circuits must be clocked at their highest allowable rate The faster a DSP operates, the faster it can process operations. Most DSPs perform three basic operations: multiplication, addition, and delay Those operations must be performed as quickly as possible since, in most instances, DSPs operations occur in real time. For example, digital processing of a sampled analog signal must be completed withm that sampling peπod Any technique therefore chosen to reduce transferal of noise must not deleteπously affect the speed at which the DSP or related digital circuitry operate The problems of digitally created noise imputed to the analog circuits is best explained in reference to the analog circuits and how they may be employed. Fig. 1 illustrates an example of an input stage of a typical modulator used, e.g , in a delta sigma A/D converter. Switches Ql and Q2 are activated and deactivated m rapid succession to sample differential analog mput signals +VIN and -VIN. The analog signals may be periodically sampled accordmg to the timing diagram shown m Fig. 2. Switches Ql are closed during times when "signal 1" (shown in Fig. 2) transitions to a logic high value. Likewise switches Q2 are closed durmg times when signal 2 of Fig. 2 transitions to a logic high value. More specifically, when signals 1 and 2 are high, respective switches Ql and Q2 are closed, and once a switch is closed, the capacitors Cl and C2 shown in Fig. 1 charge or discharge to the appropriate value Integrator, INT, performs analog noise-shaping, the output of which is forwarded to a quantizer (not shown) A delta sigma A/D converter generally comprises a modulator and a digital decimation filter The modulator samples the analog input at a high frequency and low resolution. The resulting quantization noise from the sampling event is shaped by the modulator so that its noise density is lowest over the frequency band of interest. For audio applications, typically the low frequencies are of interest so that quantization noise is shaped to be the lowest at low frequencies and greatest at high frequencies In a typical audio A/D, the digital decimation filter takes the noise shaped modulator output, low pass filters that output, and decimates it to the audio sample rate. The resolution of the decimation filter output is much greater than the modulator output, since the bandwidth is reduced and because the high frequency modulator noise has been low pass filtered The A/D converter therefore requests samplmg of the analog mput Similar to an A/D converter, sampling is required in a D/A converter which employs an interpolation filter An interpolation filter generally increases the sample rate, and the delta sigma (or sigma delta) modulator creates a one bit output stream which shapes the quantization noise output The D/A switched capacitor converts the one bit output to a positive or negative reference (VREF) value, and low pass filters smoothes the discrete voltage steps from the switched capacitor circuit Interpolation is generally performed in the DSP portion of the substrate, whereas the D/A switched capacitor and continuous time filters are in analog portions of the substrate The audio samplmg rate (fs) is typically 44.1kHz or 48kHz. The analog modulator samplmg rate (Fovr) is many times the audio sample rate. Typically, Fovr is 128fs or 256fs. For every one audio sample, the modulator samples 128 or 256 times. A plot of a typical delta sigma modulator operating at 128fs is shown m Fig. 3 A characteristic of sigma delta modulators which is typically not desirable, is tones which appear in the modulator output near Fovr/2. These tones are very far from the frequency band of interest, however, digital noise coupling into the modulator (i.e., A/D or D/A switched capacitor filter) at frequencies near Fovr/2 can mix with these tones to produce tones in the frequency band of interest An understandmg of where these tones come from is best explained in reference to the output of a modulator employmg a one bit quantizer. This one bit output represents a signal which switches between a positive reference voltage (i.e., "1") and a negative reference voltage (i.e., "0"). If the mput to the modulator is at a DC level, then the average of these one bit samples is equal to the DC level applied to the input. For instance, if the input voltage is zero, the output bit stream will consist of an equal number of 1 s and 0s. This could be a square wave with a frequency of Fovr/2. In this case, all the quantization noise is localized to a tone at Fovr/2. In reality, the output of a modulator will not be an exact square wave for a DC level of zero on the mput, however, it will have a significant amount of noise energy in a tone at or near Fovr/2. For time varying mput signals, the frequency of this tone will vary slightly and multiple tones may appear at and around Fovr/2. Care must be taken to prevent these tones from mixing with any digital noise at Fovr/2 and shifting down to the baseband. Digital noise on a mixed signal IC can couple mto the analog circuitry m a variety of ways. A common means is through the substrate Transistors or interconnect on an integrated circuit have some form of capacitive coupling to and from the monolithic substrate. Large amounts of digital circuits switchmg at high frequencies can capacitively couple a significant amount of energy mto the substrate causing currents to flow and the voltage to vary. Since the substrate is common between the analog and the digital portions, this energy will couple mto the analog circuitry and the analog signal path. Noise from the substrate can couple mto the analog signal path in a linear or non-linear fashion If it couples linearly (i.e. the amount of couplmg is independent of the analog signal level) then the coupling signal is seen directly in the analog signal. If it couples non-lmearly (i.e , the amount of couplmg is dependent on the analog signal level) the coupling signal will then mix with the analog signal. The sum and difference frequencies of the original analog signal and the coupling signal are seen on the resulting analog signal. Linear couplmg could occur between the substrate and the bottom plate of a poly-poly capacitor, while non-linear coupling could occur between the substrate and the source/dram of a transistor The capacitance between the substrate and the bottom plate of a poly-poly capacitor does not vary significantly with the voltage difference. The capacitance between the substrate and the source or drain of a transistor, however, does vary with the voltage difference This non-linearity causes the signal to modulate the other signal, the result of which is a sum and difference frequency m the output signal The following equation illustrates this concept sin (wl*t) * sm (w2 * t) = sιn[(wl+w2)t] + sin [(wl- w2)t], where wl and w2 are the frequencies of the two analog signals As described earlier, delta sigma modulators produces tones near Fovr/2 If there is signal energy in the substrate from the digital circuit position with a frequency of Fovr/2, this will mix with the tones and produce difference frequencies in the baseband (0 to fs/2) In order to prevent this from happening, it is important to ensure that very little digital circuitry operates at Fovr/2 It is common for digital circuitry in a mixed signal chip to operate at powers of two times the sample rate (fs) This is partially due to the ease of implementing dividers that divide a frequency by two A divide by two can occur simply using a flip-flop Digital interfaces on commonly used A/D and D/A converters and DSPs operate with clock rates that are powers of two times the sample rate The interpolation and decimation filters of sigma delta A D and D/A converters typically operate at various power of two rates, such as 64 fs, 128fs, etc Circuitry operating at a particular rate couples noise into the substrate at that rate Software running in DSPs can produce digital noise in the substrate Different instructions use different physical circuitry For instance, a multiply instruction uses the multiply unit, while a move instruction does not An operation that operates on the contents of register and stores the result back in a register does not use data memory, while memory-to-memory operations do Typically, memory-to-memory operations and multiply instructions consume the most power, while move instructions and register-to-register operations consume less The more power consumed, typically, the more noise is coupled into the substrate Software programs on DSPs typically repeat at powers of two times the sample rate This repeating produces digital noise in the substrate at that rate Converters or modulators which operate at powers of two times the samplmg rate (I e , 2 N fs) receive noise, via the monolithic substrate, from processors or DSPs operating at 2 N fs, where N is an mteger value of 1, 2, 3, 4, etc Noise imputed across the substrate from the digital circuits to the analog modulator typically affect the switched capacitors of the modulator It is commonly known that when switched capacitor circuits are integrated on the same IC with a significant amount of digital circuitry, the switches need to be turned off at a time when the digital circuitry is quiet Traditionally, this has been done by clocking the digital and analog circuitry at the same frequency, but with the digital clock delayed relative to the analog clock The digital switching occurs shortly after the switches are closed and the digital noise from the switching settles prior to the next sample event as shown m Fig 4 Switch capacitor circuits require two non-overlapping clocks derived from the analog clock of Fig 4 to control the switches Exemplary switches withm a switched capacitor network of a conventional modulator are shown in Fig 1 , and non-overlapping clocks are shown in Fig 2 In other implementations, the digital clock frequency is higher than the analog clock frequency, however, the digital clock is still delayed relative to the analog clock This implementation allows the digital circuitry to be clocked faster, which can be advantageous, at the cost of reduced quiet time Fig 5 illustrates a digital clock transitiomng at twice the speed of the analog clock It is advantageous to increase the speed of the digital clock relative to the analog clock since the digital circuitry can typically operate at a much higher frequency than the analog circuitry In the case of a DSP integrated with switch capacitor circuits operating on audio signals, the DSP can run at clock frequencies of 100 MHz and above The switch capacitor circuits are typically clocked at a few MHz To achieve maximum performance from the DSP, it is best to operate it with the fastest clock possible By simply increasing the digital clock frequency as shown in the previous example, the quiet time immediately preceding each analog transition (l e , sample) decreases to the point of significantly degrading performance of the analog modulator by providing more noise to switched capacitors The most sensitive time in which to avoid digital noise within the modulator is just before and during the time when the switches are closing (I e , the falling edges of the clocks which operate those switches) The implies that the DSP, microprocessor core logic, and various other digital circuits on the substrate can run at full speed durmg much of the time when the switches are closed However, care must be taken to modify the digital clock so the digital circuit clocks are temporarily terminated at appropnate, crucial sampling times SUMMARY OF THE INVENTION The problems outlmed above are m large part solved by an improved clockmg scheme The clockmg scheme hereof minimizes the effects of digitally created noise upon analog circuits, wherein the digital and analog circuits share a common monolithic semiconductor substrate The monolithic substrate is a semiconductor chip, compπsed essentially of silicon or gallium arsenide Clockmg of the digital circuits are controlled relative to the times in which analog circuits perform samplmg on an incoming audio (analog) input signal By deleting or suppressing digital pulses during a latter portion of each sample interval, noise transferal duπng digital clock transitions do not mterfere with the integrity of the sampled analog mput signal Smce there are no transitions durmg the latter portion of each sample interval, there can be no digitally created noise aπsing at this cπtical samplmg time The converters are advantageously operated with an oversamplmg rate (Fovr) that is not a power of two of the sample rate (fs) For instance, if the oversamplmg rate is 96fs, Fovr/2 is 48fs, which is not a power of two More specifically, 96 or 48 is not a number which can be derived by 2 N , where N is a positive, mteger number Smce it is uncommon to operate the digital circuitry at a non-power of two rate, there should be little noise power in the substrate at Fovr/2 This means the tones that exist near Fovr/2 in the delta sigma modulated signals will not be mixed mto the baseband The difference frequency between a non-power-of-two frequency (I e , 48fs) and a power-of-two frequency (I e , 32fs and 64 fs), which are the closest power of two rates, is 16fs The 16fs energy will be generated in the analog signals, however, it is far from the baseband and will be filtered by the decimation filter m the A/D converter or the switched capacitor and continuous time filters in a D/A In addition to clocking the digital circuits at non powers-of-two rate, the digital circuit is advantageously clocked at full speed, whereby one or more pulses from the clock prior to the sensitive analog sample times is/are removed This enables the DSP to operate at full speed most of the time and for the substrate to be quiet the minimum amount needed by the analog circuitry By not suppressing digital pulses during the early portions of each sample interval (I e , each logic 1 or logic 0 pulse), a substantial percentage of the original digital clocking frequency is maintained It is determined that a critical sampling time occurs primarily during the latter portions of each sample interval The early portions do not significantly affect the final sampled value provided, however, the semiconductor substrate is quiet durmg the latter portions Eliminating digital pulses only duπng the latter portions thereby minimizes the reduction in digital clocking frequency BRIEF DESCRIPTION OF THE DRAWINGS Other objects and advantages of the invention will become apparent upon reading the following detailed description and upon reference to the accompanying drawings in which Fig 1 is circuit diagram of an mput stage of a conventional modulator employed as a switched capacitor circuit, Fig 2 is a timing diagram of signals used to transition switches withm the modulator of Fig 1, Fig 3 is a graph of noise density as a function of sample frequency, Fig 4 is a timing diagram of analog and digital clockmg signals used to clock respective circuits upon a monolithic substrate, Fig 5 is a timmg diagram of a high speed digital clock used in conjunction with a slower analog clock, Fig 6 is a block diagram of a PLL, multiplexer and various clock dividers used to produce a signal having an oversampled clock frequency (Fovr) from an incoming signal (Sm) having a clock frequency (Fm), Fig 7 is a block diagram of a clock manager used m conjunction with frequency multiplier and a PLL for producmg digital (Fvco) and analog (Fovr) clockmg signals accordmg to one exemplary embodiment, Fig 8 is a block diagram of a clock suppression circuit and associated logic shown accordmg to an exemplary embodiment for producing digital (DSPCLK) and analog (ACLK1 and ACLK2) clocking signals of vanable frequency, Fig 9 is a timing diagram of digital and analog clockmg signals produced according to an exemplary embodiment from the circuits shown in Figs 7 and 8, and Fig 10 is a block diagram an integrated circuit embodying analog and digital circuits which are clocked by respective analog digital clock signals hereof While the invention is susceptible to various modifications and alternative forms, specific embodiments thereof are shown by way of example in the drawings and will herem be described in detail It should be understood, however, that the drawings and detailed description thereto are not intended to limit the invention to the particular form disclosed, but on the contrary, the intention is to cover all modifications, equivalents and alternatives falling withm the spirit and scope of the present invention as defined by the appended claims DETAILED DESCRIPTION OF THE INVENTION A PLL and clock dividers can be used to create the various clock rates which are required by a typical mixed signal integrated circuit The integrated circuit requires one timing source This timing source can be an on chip oscillator or an external clock input It can also be derived from a serial bitstream input to the chip The on-chip or external clock can be divided by M prior to being applied to the phase-locked loop ("PLL") and the feedback divider in the PLL can multiply the input to the PLL by N The output of the PLL can further be divided, if needed, by another factor P to create the oversamplmg clock (Fovr) The frequency divisor P can be a part of a clock manager (shown in Fig 7) If a serial bitstream with clock information encoded into it is applied to the PLL, no division by M is possible unless a second PLL is used The input signal Sin applied to the PLL from either an external or internal source is clocked at a frequency of Fin Din is the frequency of the clock encoded m a data timing source, Fvco is the frequency of the PLL output, and Fovr is the frequency of the converter oversamplmg clock The various signals and associated frequencies are shown in Fig 6 Fig 6 also depicts a divider 10, a multiplexer 12, a phase detector ("PD") 14, a loop filter 16, a voltage controlled oscillator ("VCO") 18 and a feedback divider 19, the latter elements of which are in a PLL Another divider 17 (with division factor P) may output a signal from the PLL clocked at an oversampled frequency Fovr The frequencies of all the signals are related as follows Fvco = (N/M) * Fm Fvco = N * Dm Fovr = (N/MP) * Fm Fovr = (N/P) * Din Fin and Dm must be rationally related to the sample rate (fs) as follows Fm = (Q/R) * fs Din = (Q/R) * fs This means Fvco and Fovr are related to the sample rate as follows Fvco = (QN/RM) * fs Fvco = (QN/R) * fs Fovr = (QN/MPR) * fs Fovr = (QN/PR) * fs Provided QN MPR has a prime factor that is not one or two, the oversamplmg clock (Fovr) will not be a power of two and will prevent digital noise at power of two frequencies in the substrate from mixing the Fovr/2 tones in the sigma delta modulated signal into the baseband For example, one mode of the present implementation accepts a 64fs input clock (Fm) multiplied by 24 (N) to create a 1536fs VCO clock (Fvco), and divides the VCO clock by 16 to create 96fs oversamplmg clock (Fovr) The means Q=64, R=l, M=l, N=24, and P=16 The ratio QN MPR is 64*24/1* 16* 1= 96 = 2*2*2*2*2*3, which is a non power-of-two factor Another example that would also work is Fm = 384fs M=3 N=16 P=24 which means Fvco = (384/3) * 16 = 2048fs, and Fovr = (2048/24) * fs = 85 333fs In this example QN/MPR = (384* 16)/(3 * 24 * 1) = 256/3, where 256 is a power of two, however, the prime factor three resides in the denominator Thus, Fvco is determined as a non power-of-two factor of fs, or as a power-of-two factor divided by a prime number of at least three Although any pnme factor greater than two in the numerator or denominator of QN/MPR fits the present cπteπa, the factor of three is typically the simplest to implement Turning now to Fig 7, a block diagram of a frequency multiplier 20 is shown according to one embodiment Frequency multiplier 20 is used to frequency multiply a clockmg signal derived either external or internal to the integrated circuit The frequency multiplied sampling frequency is a multiple of the incoming frequency Fm, and is shown as Fvco A frequency multiplier can be employed using various types of amplifiers and/or phase-locked loops For example, frequency multiplication can be carried out using a non-lmear amplifier which generates harmonics in its output cuπent and a tuned load that resonates at one of the harmonics Alternatively, frequency multiplication can be earned out using non-linear capacitance of a junction (semiconductor) diode to couple energy from the input circuit, which is tuned to the fundamental frequency of the output circuit, which is tuned to the desired harmonic Use of amplifiers and non-linear capacitance coupling represent two frequency multiplication examples, a third bemg a phase-locked loop with a frequency divider m the feedback loop These examples, mcludmg numerous others, fall withm the spiπt and scope of frequency multiplication in general Any frequency multiplier or frequency multiplication factor set forth herem below can be earned out using any one of the various types of frequency multipliers so described Accordmg to one exemplary embodiment, frequency multiplier 20 includes a phase-locked loop (PLL) PLL compnses any electronic circuit which locks an oscillator m phase with an input signal The PLL tracks a carrier or synchronizing signal whose samplmg frequency fs vanes somewhat with time The basic frequency multiplier circuit 20, employed as a PLL, mcludes a frequency divider 19, a phase detector (PD) circuit 22, a voltage controlled oscillator (VCO) circuit 24, and another frequency divider circuit 26 Phase detector 22 detects and tracks small differences m phase and frequency between the mcommg baseband signal Sin and the frequency divided signal at the output of frequency divider circuit 26 Output pulses from detector 22 are proportional to the phase differences of those incoming signals A low-pass filter comprising, e g , resistor 28 and capacitor 30, removes alternating current (AC) components The low-pass filter output is directed, as a direct current (DC) signal, mto oscillator 24 Input voltage to oscillator 24 acts to change the output frequency of oscillator 24 to that of the carrier signal The PLL shown in Fig 7 is configured as a frequency multiplier by operating oscillator 24 at N/M times the mput frequency of the incoming clockmg signal transitiomng at frequency Fm Accordingly, the output from oscillator 24 operates at a higher frequency than the incoming clocking signal Sin In the general loop, the output is driven m a direction that will minimize the eπor signal - I e , the phase difference between the output of frequency divider 26 and the sampling signal Thus, the PLL tends to drive the eπor signal back toward zero phase difference Once the two phases are made equal, the oscillator 24 will be locked to a multiple frequency of Fm, and any phase difference between the two signals will be controlled Frequency divider circuit 26 includes any electronic circuit which produces an output signal at a frequency which is an integral submultiple of the frequency of its input signal A frequency division can be conveniently accomplished in two ways digital division or division by subharmonic triggering Using the former as an example, many circuits are available to count pulses and thereby provide digital division A bistable circuit or flip-flop produces one output pulse for every two input pulses By cascading successive flip- flops, any desired degree of division can be obtained Division by power to two can be achieved simply by monitoring the output of the proper stage of the cascade However, division by other numbers beyond the power of two is required and can be achieved by gating to obtain the proper set of flip-flop conditions Frequency divider circuit 26 thereby employs any number of stages and gate logic necessary to produce an N frequency division For example, a four stage counter is necessary to produce a frequency divider N of 16, I e , 2 4 state Further included with frequency multiplier 20 is a clock manager 25 Clock manager 25 receives the frequency multiplied DCLK value and produces a coπespondmg ACLK1, ACLK2 and DSPCLK values Accordmg to one example, Fin after M division can be equal to a Nyquist samplmg rate, fs, of 48KHz, and multiplier factor N can be 1536, makmg Fvco equal to 1536fs, or approximately 67MHz The DSPCLK has one or more 1536fs clock pulses removed pnor to the falling edges of ACLK1 and ACLK2 This means that the digital noise from the DSP has settled pnor to the analog samplmg event The PLL locks to the baseband sample rate fs or some multiple of fs (e g , 1536fs), from which the analog (ACLK1 and ACLK2) clocks and DSP (DSPCLK) clocks are generated via clock manager 25 The N division factor of divider 26, or the combmation of factors M and N, produce a factor determined by a power-of-two times a pnme number equal to or greater than three Thus, N can be for example 2 9 x 3 = 512 x 3, or 1536 It is important that the frequency of F vco (e g , 1536fs) be a number which is divisible by a prune number equal to or greater than three Geneπcally, N is 2 A x B, or 2 A x C, or 2 A x D, etc , where A= an mteger number, B=3, C=5, D=7, etc The progression of B to C to D is that of prime number beginnmg with three and mcreasmg to 5, 7, etc Clock manager 25 comprises a clock divider and some logic to generate the desired clocks Referring to Fig 8, vaπous portions of the clock manager are shown In particular, a 4-bit divider (or counter) 30 is shown which receives the multiplied baseband signal Sm The frequency of Fvco is divided by factors of 2, 4, 8 and 16 to produce coπespondmg signals used by logic circuits 32, 34 and 36 to produce respective clocks for the DSP, and the modulator (l e , switched capacitor circuit) both of which are embodied on a single substrate Crrcuit 32 includes a three input AND gate 38, the output of which is fed mto a delay input of a D-type flip flop 40 The non-inverted output of flip flop 40 is then presented as a "Y" signal, which is then inverted and applied to one input of AND gate 42 The output of AND gate 42 is DSPCLK Circuit 34 includes a two input AND gate 44, the output of which is fed mto a delay input of a D-type flip flop 46 The non-inverted output of flip flop 46 is then presented to AND gate 48 The output of AND gate 48 is ACLK2 ACLK1 is produced similar to ACLK2, except ACLK1 is produced using AND gate 50, D-type flip flop 52 and AND gate 54 connected as shown m circuit 36 Frequency divider circuit 30 divides by integer to the power of two Logic 32, 34 and 36 includes any and all functionality necessary to delete at least one clock cycle of DSPCLK at regular count intervals Signal X shown in circuit 32 occurs once every eight cycles of CLK, and signal Y is delayed one cycle of CLK Signal Y thereafter defines respective clock pulses Zl and Z2 once every eight cycles of CLK Each clock pulse Z2 occurs between respective pairs of pulses Zl The DSPCLK is created by ANDing the Fvco with signal Y Signal Y is the same as signal X except delayed by one half of the VCO clock period Signal X is generated by ANDing the inverted version of Fvco/4, and the inverted version of fvco/8 Signal X goes high at the πsmg edge of Fvco just pnor to the nsmg edge of the pulse to be removed from Fvco to generate DSPCLK Since Fvco/2, Fvco/4, and Fvco/8 may transition at slightly different times, X may momentarily glitch just after rising edges of Fvco Signal Y is created to eliminate these glitches prior to gatmg with Fvco to generate DSPCLK A timing diagram of Fvco, Fvco/2, Fvco/4, Fvco/8, Fvco/16, X, Y, Zl, Z2, ACLK1, ACLK2 and DSPCLK are shown m Fig 9 The non-overlapping clocks ACLK1 and ACLK2 are created by ANDing Fovr and the inverted version of Fovr respectively with the inverted version of signals Zl and Z2 respectively The signals Zl and Z2 are created m order to remove the last half Fvco clock cycle from the high time of Fovr and the inverted version of Fovr to create ACLK1 and ACLK2 respectively The signal Zl is high one half Fvco clock cycle before Fovr goes low and one half Fvco clock cycle after Fovr goes low The signal Z2 is high one half Fvco clock cycle before Fovr goes high and one half Fvco clock cycle after Fovr goes low The signal Z2 is high one half Fvco clock cycle before Fovr goes high and one half Fvco clock cycle after Fovr goes high Zl and Z2 are created by delaymg the signals Z 1 a and Z2a by one half of an Fvco clock penod Z 1 a and Z2a are created by ANDing Y with Fovr and the inverted version of Fovr respectively Turning now to Fig 10, an mtegrated crrcuit 70 is shown which illustrates both analog and digital circuits on the same monolithic substrate Integrated circuit 70 mcludes analog circuitry which acquires an analog (audio) mput signal AIN Integrated circuit 70 further mcludes a digitally operated processor which manipulates digital representations of AIN and reproduces an analog output AOUT from those digital representations Accordingly, mtegrated circuit 70 mcludes a mechanism for samplmg and quantizing AIN accordmg to discrete time intervals The sampled AIN signal is then converted to digital format, whereby resulting digital signals are processed using various DSP algorithms Thereafter, the processed digital signals can be reproduced back as audio signals AOUT In the mteπm, the processed digital signals can, if desired, be output as DOUT' Integrated crrcuit 70 includes any crrcuit having both analog (sample/quantizer) functions and digital (digital processmg and reproduction) functions employed upon a smgle monolithic substrate Integrated crrcuit 70 mcludes an analog-to-digital (A/D) circuit 74 which receives AIN A/D circuit 74 samples AIN, and quantizes the magnitude of the sampled signal durmg each sample interval A/D circuit 74 may include an analog low pass filter, possibly employed as an mtegrator, subsequent to the samplmg function The output from A/D cncuit 74 is represented as a bit stream of digital signals, shown as DOUT A/D circuit 74 samples and quantizes accordmg to an analog clockmg signal ACLK If ACLK frequency is large, oversamplmg attributed to well known delta- sigma modulation may occur Delta-sigma modulation produces a DOUT signal having a bit stream of logic Is relative to logic 0s which is indicative of AIN voltage magnitude A/D crrcuit 74, however, encompasses a generalized modulator, and not simply an oversampled modulator A D circuit 74 includes any circuit which samples and quantizes at a rate defined by an analog clocking signals ACLK1 and ACLK2 D/A circuit 76 is clocked by ACLK1/ACKL2, whereas DSP 78 may be clocked by a digital clockmg signal DSPCLK The digital clocking signal can take on several different frequencies depending upon which frequency is selected The digital clockmg signal frequency chosen is, however, of higher frequency than the analog clockmg signal ACLK1/ACKL2 for the reasons and having the advantages stated above The D/A circuit 76 can be an oversamplmg type converter, in which an analog portion of the D/A circuit basically functions as r reference voltage selector followed by low pass filtering Either a positive or a negative reference voltage (either +VREF or - VREF) is selected by D/A circuit 76 in accordance with its receipt of a high logic level or a low logic level, respectively DSP 78 includes any unit which processes digital signals with multiply, add and or delay operations Those basic operations allow DSP 78 to perform complex digital filtering, digital scaling, decimation and/or interpolation DSP 78 includes input and output devices, an arithmetic logic unit, a control unit, memory, and interconnect buses extending therebetween Resulting from digital manipulation, DOUT is converted to a processed bit stream denoted as DOUT' Integrated circuit 70, shown in Fig 10, thereby includes A/D digital recordmg devices, D/A digital reproduction devices, and DSP digital processing devices, all upon a smgle monolithic substrate The digital clockmg signal is not only user programmable to one of many fixed frequencies, but the frequency chosen is maintained at a higher frequency magnitude than the analog clockmg signal It will be appreciated by those skilled m the art having the benefit of this disclosure that this mvention is believed to be capable of applications with any mtegrated crrcuit havmg both analog and digital portions Furthermore, it is also to be understood that the mvention shown and descnbed is to be taken as presently prefeπed embodiments Vaπous modifications and changes may be made to the recordmg, processing and reproduction devices necessary to record a digital representation of an analog signal, process the digital representation, and reproduce an analog signal, all of which would be obvious to a person skilled in the art without departmg from the spirit and scope of the invention as set forth in the claims It is mtended that the following claims be interpreted to embrace all such modifications and changes, and accordingly, the specification and drawings are to be regarded m an illustrative rather than a restrictive sense

Claims: WHAT IS CLAIMED IS: 1. An integrated circuit, comprising. an analog circuit and a digital circuit; a frequency multiplier and divider circuit adapted to modify the frequency of a clocking signal; a clock suppression circuit coupled to receive the frequency modified clocking signal and produce an analog clocking signal and a digital clockmg signal operably coupled to the analog crrcuit and the digital circuit, respectively; and wherem the clock suppression crrcuit is further coupled to delete at least one pulse of the digital clockmg signal at times when the analog clocking signal transitions between a pair of logic states. 2. The integrated circuit as recited in claim 1, wherem said analog circuit comprises a switched capacitor circuit. 3. The integrated circuit as recited in claim 1, wherem each transition of the analog clockmg signal occurs immediately subsequent to and duπng the time in which at least one pulse of the digital clockmg signal is deleted. 4. An mtegrated circuit, comprising an analog clocking signal adapted to sample a signal forwarded to an analog crrcuit, wherein the analog clocking signal transitions at a nyquist sampling rate times a prime number greater than two, and further times 2 N , where N is an integer value. 5. The integrated circuit as recited in claim 4, wherem the signal being sampled is a signal whose magnitude varies in time, and wherein the analog circuit comprises a switched capacitor circuit 6. The integrated crrcuit as recited in claim 5, wherem the switched capacitor circuit comprises a delta sigma analog-to-digital circuit. 7. The integrated circuit as recited in claim 4, wherein the signal being sampled comprises a substantially constant reference voltage, and wherein the analog circuit comprises a switched capacitor circuit. 8. The integrated circuit as recited in claim 7, wherem the switched capacitor circuit comprises a delta sigma digital-to-analog circuit 9 The integrated circuit as recited in claim 4, wherein the prime number is equal to three 10. The integrated circuit as recited in claim 4, further compnsing a digital circuit embodied upon the same monolithic substrate as the analog circuit, wherem the digital circuit is adapted to receive a digital clockmg signal having at least one pulse suppressed at tunes when the analog clockmg signal transitions between a parr of logic states. 11 The integrated circuit as recited in claim 10, wherem the pulse is suppressed during a latter portion of each one half clock cycle of the analog clocking signal. 12. The integrated cucuit as recited m claim 11, wherem said latter portion is less than fifty percent of each one half clock cycle 13. An mtegrated circuit, compnsmg an analog clocking signal adapted to sample a signal forwarded to an analog circuit, wherein the analog clockmg signal transitions at 2 N (where N is an mteger value) times a nyquist samplmg rate, the product of which is further divided by a prime number greater than two. 14. The mtegrated crrcuit as recited m claim 13, wherem the signal being sampled is a signal whose magnitude varies in time, and wherem the analog crrcuit comprises a switched capacitor circuit. 15. The mtegrated crrcuit as recited in claim 14, wherem the switched capacitor circuit compnses a delta sigma analog-to-digital circuit. 16. The integrated circuit as recited in claim 13, wherem the signal bemg sampled comprises a substantially constant reference voltage, and wherem the analog circuit comprises a switched capacitor crrcuit. 17. The mtegrated cucuit as recited in claim 16, wherem the switched capacitor circuit comprises a delta sigma digital-to-analog circuit 18. The integrated circuit as recited in claim 13, wherem the prime number is equal to three. 19. The integrated cucuit as recited m claim 13, further comprising a digital circuit embodied upon the same monolithic substrate as the analog circuit, wherein the digital circuit is adapted to receive a digital clockmg signal having at least one pulse suppressed at times when the analog clocking signal transitions between a pau of logic states. 20. The integrated circuit as recited in claim 19, wherein the pulse is suppressed during a latter portion of each one half clock cycle of the analog clocking signal. 21. The integrated circuit as recited in claim 20, wherein said latter portion is less than fifty percent of each one half clock cycle. 22 A method for minimizing eπors associated with input signal sample readings, comprising generating a digital clocking signal, modifying the frequency of the digital clocking signal to produce an analog clocking signal, samplmg an input signal with a discrete time sampling circuit during each cycle of the analog clockmg signal, removing at least one clock pulse from said digital clocking signal during a tune period immediately prior to and during a conclusion of said sampling of the input signal, and clockmg a digital cucuit with said digital clockmg signal having the removed clock pulse, wherein the digital cucuit shares a monolithic semiconductor substrate with the discrete tune samplmg cucuit 23 The method as recited in claim 22, wherein said samplmg step comprises stormg said analog mput signal durmg discrete time intervals coπespondmg to each cycle of the analog clocking signal 24 The method as recited in claim 23, wherein said stormg step comprises forwarding said analog mput signal upon one terminal of a capacitor, the opposing terminal of the capacitor bemg connected to a ground supply 25 The method as recited in claim 22, wherem said ground supply extends across said monolithic semiconductor substrate shared by the digital and analog cucuits 26 The method as recited in claim 22, wherem said samplmg occurs at a frequency equal to 2 N (where N is an mteger value) tunes a nyquist samplmg rate, the product of which is further multiplied or divided by a prime number greater than two 27 A method for minimizing eπors associated with input signal sample readings, comprising generating an analog circuit clocking signal used to sample an incoming signal, wherem the analog circuit clocking signal transitions at a frequency equal to the product of a nyquist sampling rate times 2 N (where N is an mteger value) times a prime number greater than two

Inventors: KNAPP DAVID J, KNAPP, DAVID, J.
Applicants: OASIS DESIGN INC, OASIS DESIGN, INC.
Application year: 1999
Main classification: H03K5
IPC codes: G06F1, G06F3, G10L19