PROCESSOR CONFIGURED TO SELECTIVELY FREE PHYSICAL REGISTERS UPON RETIREMENT OF INSTRUCTIONS

Abstract: A processor employing a map unit including register renaming hardware is shown. The map unit may assign virtual register numbers to source registers by scanning instruction operations to detect intraline dependencies. Subsequently, physical register numbers are mapped to the source register numbers responsive to the virtual register numbers. The map unit may store (e.g. in a map silo) a current lookahead state corresponding to each line of instruction operations which are processed by the map unit. Additionally, the map unit stores an indication of which instruction operations within the line update logical registers, which logical registers are updated, and the physical register numbers assigned to the instruction operations. Upon detection of an exception condition for an instruction operation with a line, the current look a head state corresponding to the line is restored from the map silo. Additionally, physical register numbers corresponding to instruction operations within the line which are prior to the instruction operation experiencing the exception are restored into the current lookahead state. The map unit may use the same physical register to store both a condition code result and an integer result. The physical register number identifying the physical register is recorded for both the condition code register and the integer register. The map unit pops the previous renames from the architected renames block upon retiring one or more instruction operations. The popped physical register numbers are cammed against the updated architectural state. If a cam match is detected, the popped physical register is not freed.

Description: TITLE: PROCESSOR CONFIGURED TO SELECTIVELY FREE PHYSICAL REGISTERS UPON RETIREMENT OF INSTRUCTIONS BACKGROUND OF THE INVENTION 1 Field of the Invention This invention is related to the field of processors and, more particularly, to register renammg features of processors 2 Description of the Related Art Superscalar processors attempt to achieve high performance by issumg and executmg multiple instructions per clock cycle and by employing the highest possible clock frequency consistent with the design One method for increasing the number of instructions executed per clock cycle is out of order execution In out of order execution, instructions may be executed m a different order than that specified m the program sequence (or "program order") Certain instructions near each other in a program sequence may have dependencies which prohibit their concurrent execution, while subsequent instructions m the program sequence may not have dependencies on the previous instructions Accordingly, out of order execution may mcrease performance of the superscalar processor by increasing the number of instructions executed concurrently (on the average) Unfortunately, out of order execution presents additional hardware complexities for the processor For example, a second mstruction which is subsequent to a first mstruction in program order may update a storage location which is read by the first mstruction In other words, the destmation operand of the second mstruction may be one of the source operands of the first mstruction For proper program execution, the first mstruction must receive, as a source operand, the value stored in the storage location prior to execution of the second mstruction Similarly, if the first and second instructions have a particular storage location as the destmation operand, the result of the second mstruction should be the value stored in the storage location subsequent to executmg both the first and second instructions (and prior to executing a third mstruction which updates the storage location) Generally, instructions may have one or more source operands and one or more destination operands The source operands are input values to be manipulated accordmg to the instruction definition to produce one or more results (which are the destmation operands) Source and destmation operands may be memory operands stored m a memory location external to the processor, or may be register operands stored m register storage locations included within the processor The mstruction set architecture employed by the processor defines a number of architected registers These registers are defined to exist by the instruction set architecture, and instructions may be coded to use the architected registers as source and destmation operands An instruction specifies a particular register as a source or destmation operand via a register number (or register address) m an operand field of the mstruction The register number uniquely identifies the selected register among the architected registers A source operand is identified by a source register number and a destination operand is identified by a destmation register number In addition to the architected registers, some processors define additional microarchitected registers which may be used to hold temporary results duπng mstruction execution For example, some processors use microcodmg techniques to handle the most complex mstructions Microcode routines are executed in response to the complex mstructions and include a plurality of simpler mstructions The microcode routines may generate temporary results while executmg the complex mstruction These microarchitected registers (or temporary registers) are assigned additional register numbers to identify the temporary registers uniquely from the architected registers Together, the architected registers and temporary registers are referred to herein as logical registers A processor employmg out of order execution may experience the above hazards with respect to register operands A method for handlmg these hazards is register renammg In register renammg, the processor implements a set of physical registers The number of physical registers is greater than the number of logical registers specified by the mstruction set architecture and microarchitecture of the processor As mstructions are issued, physical registers are assigned to the destmation register operands of the mstructions A physical register number identifying the assigned physical register is provided for each destmation operand, and an indication of which physical registers correspond to the logical registers is mamtamed by the processor Subsequent mstructions which have the logical registers as source operands are provided with the corresponding physical register number for readmg the appropriate source operand By assignmg different physical registers to store the destination operands of each mstruction, mstructions may freely update then destmation operands m any order, since different physical storage locations are bemg updated Unfortunately, the process of assignmg physical register numbers to destmation operands mstructions and providmg those physical register numbers to subsequent mstructions havmg the destmation operands as source operands may be complex and slow Particularly difficult m superscalar processors is the assignment of physical register numbers to destination operands of mstructions and providmg the physical register numbers to subsequent dependent mstructions which are passing through the register renammg hardware simultaneously with those mstructions A register renaming structure which may operate at higher frequency yet still handle renaming of multiple mstructions per clock cycle is desired Register renammg presents difficulties when mstructions experience exception conditions As used herem, an exception refers to an error in the execution of mstructions which requires subsequent mstructions to be discarded and mstruction fetch to be started at a different address For example, branch misprediction is an exception condition Processors may perform branch prediction to speculatively fetch, issue, and execute mstructions subsequent to conditional branch mstructions If the prediction is incorrect, the mstructions subsequent to the branch mstruction are discarded and mstructions are fetched accordmg to execution of the branch mstruction Additional exception conditions may mclude address translation errors for addresses of memory operands and other architectural or microarchitectural error conditions Because register renammg may have been applied to mstructions which are subsequently discarded due to an exception, the mappmg of logical registers to physical registers must be recovered to a state consistent with the mstruction expenencmg the exception In other words, the mappmg of logical registers to physical registers should reflect the execution of instructions prior to the instruction experiencing the exception (in program order) and not reflect the execution of mstructions subsequent to the mstruction expenencmg the exception It is desirable for the recovery of the register rename map to be rapid so that mstructions fetched in response to the exception may pass through the register renaming hardware as soon as they are available If recovery of the register rename map is still occurring when newly fetched mstructions reach the register renammg hardware, then the newly fetched mstructions must be stalled until the register rename map is recovered Performance of the processor are is thereby lost Still further, register renammg hardware generally mcludes a mechanism for reusmg physical registers previously assigned to a destination operand of a particular mstruction once the corresponding logical register has been committed to a value corresponding to a subsequent mstruction It is desnable to use the physical registers as efficiently as possible, and to also providmg accurate method for freeing the physical registers once the subsequent state has been committed to the corresponding logical register SUMMARY OF THE INVENTION The problems outlined above are m large part solved by a processor employing a map unit including register renarmng hardware Various embodiments of the map unit employ a variety of techniques to mcrease the performance and efficiency of the register renammg mechanism In one embodiment, the map unit is configured to assign virtual register numbers to source registers by scanning mstruction operations to detect lntralme dependencies If a dependency is not detected, a virtual register number mdicatmg the current lookahead state is assigned If a dependency is detected, a virtual register number mdicatmg the issue position upon which the source register is dependent is assigned Subsequently, physical register numbers are mapped to the source register numbers responsive to the virtual register numbers In one implementation, the assignment of virtual register numbers and the mappmg of virtual register numbers to physical register numbers are performed m separate pipeline stages The register renammg mechanism may thereby be operable at higher clock frequencies Performance of the processor may be mcreased to the extent that higher clock frequencies are achievable In another embodiment, the map unit stores (e g m a map silo) a current lookahead state corresponding to each lme of mstruction operations which are processed by the map unit The current lookahead state identifies the physical register numbers assigned to each logical register prior to performing register renaming with respect to the lme of mstruction operations Additionally, the map unit stores an indication of which instruction operations within the lme update logical registers, which logical registers are updated, and the physical register numbers assigned to the mstruction operations Upon detection of an exception condition for an mstruction operation with a lme, the current lookahead state corresponding to the lme is restored from the map silo Additionally, physical register numbers corresponding to mstruction operations within the lme which are prior to the mstruction operation expenencmg the exception are restored mto the cunent lookahead state Advantageously, the current lookahead state may be rapidly recovered upon detecting an exception Instruction operations fetched m response to the exception may be renamed upon arriving at the map unit, since the recovery of the current lookahead state may already be completed Performance of the processor may thereby be mcreased In yet another embodiment, the map unit may improve efficiency of physical register usage by usmg the same physical register to store both a condition code result and an integer result The physical register number identifying the physical register is recorded for both the condition code register and the mteger register In order to provide correct freemg of physical registers to be reused as renames, the map unit pops the previous renames from the architected renames block pnor to updatmg the entries correspondmg to a set of logical registers bemg committed m response to retinng one or more mstruction operations Prior to freemg the popped physical register numbers, the popped physical register numbers are cammed agamst the updated architectural state mamtamed by the architected renames block If a cam match is detected, the popped physical register is not freed Advantageously, more efficient use of the physical registers may be achieved and accurate freemg of the physical register may be achieved as well In addition to usmg the physical registers more efficiently with respect to condition code register and mteger register renammg, other optimizations may be possible using the present mechanism for freemg registers For example, register-register moves may be accomplished by copymg the source physical register number as the destmation physical register number The present mechanism may prevent inadvertent freemg of the physical register number m such a case as well A method for managmg physical registers m a processor is contemplated A first physical register is assigned to a destmation operand of an mstruction operation The destination operand identifies a logical register The mstruction operation is retired Responsive to retiring the mstruction operation, an architected renames block is updated with a first physical register number correspondmg to the first physical register Also responsive to retiring the mstruction operation, a second physical register number is read from the architected renames block The second physical register number is bemg displaced from representmg the logical register within the architected renames block by the first physical register number Freeing of the second physical register is inhibited responsive to determining that the second physical register number represents a second logical register withm the architected renames block A processor is contemplated, compnsmg a map unit and an architectural renames block The map unit is configured to assign a first physical register to a destmation operand of an mstruction operation Furthermore, the map unit is configured to mamtam a free list indicative of which physical registers are free for assignment The map unit is configured to select the first physical register from the free list Coupled to receive an indication that the mstruction operation is retiring and a first physical register number corresponding to the first physical register, the architectural renames block is configured to provide a second physical register number identifying a second physical register previously conespondmg to a first logical register identified by the destmation operand responsive to the indication that the mstruction operation is retinng The architectural renames block is configured to capture the first physical register number and retain the first physical register number as correspondmg to the first logical register responsive to the indication that the instruction operation is retiring Still further, the architectural renames block is further configured to determine if the second physical register number additionally corresponds to a second logical register The map unit is configured to inhibit addmg the second physical register number to the free list if the second physical register represents the second logical register A method for managmg physical registers m a processor is contemplated A first physical register is assigned to a destmation operand of an mstruction operation The destmation operand identifies a logical register The mstruction operation is retired Responsive to retirmg the mstruction operation, an architected renames block is updated with a first physical register number corresponding to the first physical register Also responsive to retinng the mstruction operation, a second physical register number is read from the architected renames block The second physical register number is bemg displaced from representmg the logical register within the architected renames block by the first physical register number The second physical register is freed A processor is contemplated The processor compnses a map unit and an architectural renames block The map unit is configured to assign a first physical register to a destmation operand of an instruction operation, and is further configured to mamtam a free list mdicative of which physical registers are free for assignment The map unit is configured to select the first physical register from the free list Coupled to receive an mdication that the mstruction operation is retiring and a first physical register number corresponding to the first physical register, the architectural renames block is configured to provide a second physical register number identifying a second physical register previously corresponding to a first logical register identified by the destmation operand responsive to the mdication that the mstruction operation is retiring Additionally, the architectural renames block is configured to capture the first physical register number and retam the first physical register number as corresponding to the first logical register responsive to the mdication that the mstruction operation is retinng The map unit is configured to add the second physical register number to the free list A computer system is contemplated, compnsmg a processor and an I/O device The processor compnses a map unit and an architectural renames block The map unit is configured to assign a first physical register to a destmation operand of an mstruction operation, and is further configured to mamtam a free list mdicative of which physical registers are free for assignment The map unit is configured to select the first physical register from the free list Coupled to receive an indication that the instruction operation is retiring and a first physical register number correspondmg to the first physical register, the architectural renames block is configured to provide a second physical register number identifying a second physical register previously corresponding to a first logical register identified by the destmation operand responsive to the mdication that the instruction operation is retiring Additionally, the architectural renames block is configured to capture the first physical register number and retain the first physical register number as correspondmg to the first logical register responsive to the indication that the mstruction operation is retirmg The map unit is configured to add the second physical register number to the free list Coupled to the processor, the I/O device is configured to communicate between the computer system and another computer system to which the I/O device is coupled BRIEF DESCRIPTION OF THE DRAWINGS Other objects and advantages of the invention will become apparent upon readmg the following detailed descnption and upon reference to the accompanymg drawings in which Fig 1 is a block diagram of one embodiment of a processor Fig 2 is a block diagram of a map unit, a map silo, and an architectural renames block shown m Fig 1 highlighting interconnection therebetween accordmg to one embodiment of the processor shown m Fig 1 Fig 3 is a block diagram of one embodiment of a map unit shown m Figs 1 and 2. Fig. 4 is a block diagram of one embodiment of a register scan unit shown in Fig 3. Fig. 5 is a table illustrating one encoding which may be used for virtual register numbers. Fig. 6 is a block diagram of a portion of one embodiment of a scan unit shown in Fig. 4 Fig 7 is a block diagram of another portion of one embodiment of a scan unit shown m Fig 4. Fig 8 is a block diagram of one embodiment of a virtual physical register map unit shown m Fig. 3. Fig. 9 is a table illustrating information stored m one embodiment of a map silo illustrated in Figs 1 and 2. Fig. 10 is a block diagram illustrating an exemplary lookahead register state for a logical register Fig. 11 is a flowchart illustrating restormg lookahead state accordmg to one embodiment of the map unit shown in Figs. 1, 2, and 3. Fig. 12 is a block diagram of one embodiment of a computer system mcludmg the processor shown m Fig 1. While the invention is susceptible to various modifications and alternative forms, specific embodiments thereof are shown by way of example m the drawings and will herem be described in detail It should be understood, however, that the drawings and detailed description thereto are not mtended to limit the mvention to the particular form disclosed, but on the contrary, the mtention is to cover all modifications, equivalents and alternatives falling within the spint and scope of the present invention as defined by the appended claims DETAILED DESCRIPTION OF THE INVENTION Turning now to Fig. 1 , a block diagram of one embodiment of a processor 10 is shown. Other embodiments are possible and contemplated In the embodiment of Fig 1, processor 10 mcludes a lme predictor 12, an mstruction cache (I-cache) 14, an alignment unit 16, a branch history table 18, an indirect address cache 20, a return stack 22, a decode unit 24, a predictor miss decode unit 26, a microcode unit 28, a map unit 30, a map silo 32, an architectural renames block 34, a pair of mstruction queues 36A-36B, a pair of register files 38A-38B, a parr of execution cores 40A-40B, a load/store unit 42, a data cache (D-cache) 44, an external interface unit 46, a PC silo and redirect unit 48, and an instruction TLB (ITB) 50 Lme predictor 12 is connected to ITB 50, predictor miss decode unit 26, branch history table 18, indirect address cache 20, return stack 22, PC silo and rednect block 48, alignment unit 16, and I-cache 14 I-cache 14 is connected to alignment unit 16 Alignment unit 16 is further connected to predictor miss decode unit 26 and decode unit 24 Decode unit 24 is further connected to microcode unit 28 and map unit 30 Map unit 30 is connected to map silo 32, architectural renames block 34, mstruction queues 36A-36B, load/store unit 42, execution cores 40A-40B, and PC silo and redirect block 48. Instruction queues 36A-36B are connected to each other and to respective execution cores 40A-40B and register files 38A-38B. Register files 38A-38B are connected to each other and respective execution cores 40A-40B. Execution cores 40A-40B are further connected to load/store unit 42, data cache 44, and PC silo and redirect unit 48. Load/store unit 42 is connected to PC silo and rednect unit 48, D-cache 44, and external interface unit 46. D-cache 44 is connected to register files 38, and external interface unit 46 is connected to an external interface 52 Elements referred to herem by a reference numeral followed by a letter will be collectively referred to by the reference numeral alone For example, mstruction queues 36A-36B will be collectively referred to as instruction queues 36 In the embodiment of Fig 1, processor 10 employs a variable byte length, complex instruction set computing (CISC) instruction set architecture For example, processor 10 may employ the x86 mstruction set architecture (also refened to as IA-32) Other embodiments may employ other mstruction set architectures mcludmg fixed length mstruction set architectures and reduced instruction set computmg (RISC) mstruction set architectures Certain features shown m Fig 1 may be omitted m such architectures Lme predictor 12 is configured to generate fetch addresses for I-cache 14 and is additionally configured to provide information regardmg a lme of mstruction operations to alignment unit 16 Generally, lme predictor 12 stores lmes of instruction operations previously speculatively fetched by processor 10 and one or more next fetch addresses correspondmg to each lme to be selected upon fetch of the lme In one embodiment, lme predictor 12 is configured to store IK entries, each defining one lme of mstruction operations Lme predictor 12 may be banked into, e g , four banks of 256 entries each to allow concurrent read and update without dual porting, if desired Lme predictor 12 provides the next fetch address to I-cache 14 to fetch the conespondmg mstruction bytes I-cache 14 is a high speed cache memory for stonng mstruction bytes Accordmg to one embodiment I- cache 14 may comprise, for example, a 256 Kbyte, four way set associative organization employmg 64 byte cache lmes However, any I-cache structure may be suitable Additionally, the next fetch address is provided back to lme predictor 12 as an mput to fetch information regardmg the corresponding lme of mstruction operations The next fetch address may be overridden by an address provided by ITB 50 m response to exception conditions reported to PC silo and redirect unit 48 The next fetch address provided by the lme predictor may be the address sequential to the last mstruction within the lme (if the lme terminates m a non-branch mstruction) Alternatively, the next fetch address may be a target address of a branch mstruction terminating the lme In yet another alternative, the lme may be terminated by return mstruction, in which case the next fetch address is drawn from return stack 22 Responsive to a fetch address, line predictor 12 provides information regarding a lme of mstruction operations beginning at the fetch address to alignment unit 16 Alignment unit 16 receives mstruction bytes correspondmg to the fetch address from I-cache 14 and selects mstruction bytes mto a set of issue positions accordmg to the provided mstruction operation information More particularly, lme predictor 12 provides a shift amount for each mstruction within the lme mstruction operations, and a mapping of the mstructions to the set of mstruction operations which comprise the line An mstruction may correspond to multiple mstruction operations, and hence the shift amount correspondmg to that mstruction may be used to select instruction bytes into multiple issue positions An issue position is provided for each possible mstruction operation within the lme In one embodiment, a lme of mstruction operations may mclude up to 8 mstruction operations conespondmg to up to 6 instructions Generally, as used herein, a lme of instruction operations refers to a group of mstruction operations concurrently issued to decode unit 24 The line of mstruction operations progresses through the pipeline of microprocessor 10 to mstruction queues 36 as a unit Upon bemg stored m mstruction queues 36, the individual mstruction operations may be executed m any order The issue positions within decode unit 24 (and the subsequent pipeline stages up to mstruction queues 36) define the program order of the mstruction operations within the lme for the hardware withm those pipeline stages. An mstruction operation aligned to an issue position by alignment unit 16 remams m that issue position until it is stored withm an instruction queue 36A-36B. Accordmgly, a first issue position may be referred to as bemg prior to a second issue position if an mstruction operation withm the first issue position is prior to an mstruction operation concunently withm the second issue position m program order. Similarly, a first issue position may be refened to as bemg subsequent to a second issue position if an instruction operation withm the first issue position is subsequent to mstruction operation concunently withm the second issue position m program order. Instruction operations withm the issue positions may also be refened to as bemg pnor to or subsequent to other mstruction operations withm the lme. As used herem, an mstruction operation (or ROP) is an operation which an execution unit withm execution cores 40A-40B is configured to execute as a single entity. Simple instructions may conespond to a smgle instruction operation, while more complex mstructions may conespond to multiple mstruction operations Certain of the more complex mstructions may be implemented withm microcode unit 28 as microcode routines. Furthermore, embodiments employing non-CISC mstruction sets may employ a smgle mstruction operation for each mstruction (i.e. mstruction and instruction operation may be synonymous m such embodiments) In one particular embodiment, a lme may compnse up to eight mstruction operations conespondmg to up to 6 mstructions. Additionally, the particular embodiment may terminate a lme at less than 6 mstructions and/or 8 mstruction operations if a branch mstruction is detected Additional restrictions regardmg the mstruction operations to the lme may be employed as desired The next fetch address generated by line predictor 12 is routed to branch history table 18, mdirect address cache 20, and return stack 22 Branch history table 18 provides a branch history for a conditional branch mstruction which may terminate the line identified by the next fetch address Lme predictor 12 may use the prediction provided by branch history table 18 to determine if a conditional branch instruction terminating the lme should be predicted taken or not taken In one embodiment, line predictor 12 may store a branch prediction to be used to select taken or not taken, and branch history table 18 is used to provide a more accurate prediction which may cancel the lme predictor prediction and cause a different next fetch address to be selected Indirect address cache 20 is used to predict mdirect branch target addresses which change frequently Lme predictor 12 may store, as a next fetch address, a previously generated mdirect target address Indirect address cache 20 may ovenide the next fetch address provided by lme predictor 12 if the conespondmg line is terminated by an mdirect branch mstruction. Furthermore, the address subsequent to the last mstruction withm a lme of mstruction operations may be pushed on the return stack 22 if the lme is termmated by a subroutme call mstruction Return stack 22 provides the address stored at its top to lme predictor 12 as a potential next fetch address for lmes termmated by a return mstruction In addition to providing next fetch address and mstruction operation information to the above mentioned blocks, line predictor 12 is configured to provide next fetch address and instruction operation information to PC silo and redirect unit 48. PC silo and redirect unit 48 stores the fetch address and lme information and is responsible for redirectmg mstruction fetching upon exceptions as well as the orderly retirement of mstructions PC silo and rednect unit 48 may mclude a circular buffer for stormg fetch address and mstruction operation mformation conespondmg to multiple lmes of mstruction operations which may be outstanding withm processor 10 Upon retirement of a lme of instructions, PC silo and rednect unit 48 may update branch history table 18 and indirect address cache 20 accordmg to the execution of a conditional branch and an mdirect branch, respectively Upon processmg an exception, PC silo and redirect unit 48 may purge entries from return stack 22 which are subsequent to the exception-causing mstruction Additionally, PC silo and redirect unit 48 routes an mdication of the exception-causmg mstruction to map unit 30, mstruction queues 36, and load/store unit 42 so that these units may cancel mstructions which are subsequent to the exception-causmg mstruction and recover speculative state accordmgly In one embodiment, PC silo and redirect unit 48 assigns a sequence number (R#) to each mstruction operation to identify the order of mstruction operations outstandmg within processor 10 PC silo and rednect unit 48 may assign R#s to each possible mstruction operation with a lme If a lme mcludes fewer than the maximum number of mstruction operations, some of the assigned R#s will not be used for that lme However, PC silo and redirect unit 48 may be configured to assign the next set of R#s to the next lme of mstruction operations, and hence the assigned but not used R#s remam unused until the conespondmg lme of mstruction operations is retired In this fashion, a portion of the R#s assigned to a given lme may be used to identify the lme withm processor 10 In one embodiment, a maximum of 8 ROPs may be allocated to a lme Accordmgly, the first ROP withm each lme may be assigned an R# which is a multiple of 8 Unused R#s are accordmgly automatically skipped The precedmg discussion has described line predictor 12 predicting next addresses and providmg instruction operation mformation for lines of instruction operations This operation occurs as long as each fetch address hits m lme predictor 12 Upon detectmg a miss in line predictor 12, alignment unit 16 routes the conespondmg mstruction bytes from I-cache 14 to predictor miss decode unit 26 Predictor miss decode unit 26 decodes the mstructions beginning at the offset specified by the missing fetch address and generates a lme of instruction operation mformation and a next fetch address Predictor miss decode unit 26 enforces any limits on a lme of mstruction operations as processor 10 is designed for (e g maximum number of mstruction operations, maximum number of mstructions, terminate on branch mstructions, etc ) Upon completing decode of a lme, predictor miss decode unit 26 provides the information to lme predictor 12 for storage It is noted that predictor miss decode unit 26 may be configured to dispatch instructions as they are decoded Alternatively, predictor miss decode unit 26 may decode the lme of mstruction mformation and provide it to line predictor 12 for storage Subsequently, the missing fetch address may be reattempted m lme predictor 12 and a hit may be detected Furthermore, a hit m lme predictor 12 may be detected and a miss m I-cache 14 may occur The conespondmg mstruction bytes may be fetched through external mterface unit 46 and stored m I-cache 14 In one embodiment, lme predictor 12 and I-cache 14 employ physical addressing However, upon detectmg an exception, PC silo and redirect unit 48 will be supplied a logical (or virtual) address Accordmgly, the redirect addresses are translated by ITB 50 for presentation to lme predictor 12 Additionally, PC silo and redirect unit 48 mamtams a virtual lookahead PC value for use m PC relative calculations such as relative branch target addresses The virtual lookahead PC conespondmg to each lme is translated by ITB 50 to venfy that the conespondmg physical address matches the physical fetch address produced by lme predictor 12 If a mismatch occurs, lme predictor 12 is updated with the conect physical address and the conect mstructions are fetched PC silo and redirect unit 48 further handles exceptions related to fetchmg beyond protection boundaries, etc PC silo and redirect unit 48 also maintains a retire PC value mdicatmg the address of the most recently retired mstructions Decode unit 24 is configured receive instruction operations from alignment unit 16 m a plurality of issue positions, as described above Decode unit 24 decodes the mstruction bytes aligned to each issue position m parallel (along with an mdication of which mstruction operation conespondmg to the mstruction bytes is to be generated m a particular issue position) Decode unit 24 identifies source and destmation operands for each mstruction operation and generates the mstruction operation encodmg used by execution cores 40A-40B Decode unit 24 is also configured to fetch microcode routmes from microcode unit 28 for mstructions which are implemented m microcode Accordmg to one particular embodiment, the following instruction operations are supported by processor 10 mteger, floating pomt add (mcludmg multimedia), floating point multiply (mcludmg multimedia), branch, load, store address generation, and store data Each mstruction operation may employ up to 2 source register operands and one destmation register operand Accordmg to one particular embodiment, a smgle destmation register operand may be assigned to mteger ROPs to store both the mteger result and a condition code (or flags) update The conespondmg logical registers will both receive the conespondmg PR# upon retirement of the mteger operation Certain instructions may generate two mstruction operations of the same type to update two destmation registers (e g POP, which updates the ESP and the specified destmation register) The decoded instruction operations and source and destmation register numbers are provided to map unit 30 Map unit 30 is configured to perform register renammg by assignmg physical register numbers (PR#s) to each destination register operand and source register operand of each mstruction operation The physical register numbers identify registers withm register files 38A-38B Additionally, map unit 30 assigns a queue number (IQ#) to each mstruction operation, identifying the location within instruction queues 36A-36B assigned to store the mstruction operation Map unit 30 additionally provides an indication of the dependencies for each mstruction operation by providing queue numbers of the mstructions which update each physical register number assigned to a source operand of the mstruction operation Map unit 30 updates map silo 32 with the physical register numbers and mstruction to numbers assigned to each mstruction operation (as well as the conespondmg logical register numbers) Furthermore, map silo 32 may be configured to store a lookahead state conespondmg to the logical registers pnor to the lme of instructions and an R# identifying the lme of instructions with respect to the PC silo Similar to the PC silo described above, map silo 32 may compnse a circular buffer of entries Each entry may be configured to store the information conespondmg one lme of instruction operations Map unit 30 and map silo 32 are further configured to receive a retire indication from PC silo 48 Upon retirmg a lme of mstruction operations, map silo 32 conveys the destination physical register numbers assigned to the lme and conespondmg logical register numbers to architectural renames block 34 for storage Architectural renames block 34 stores a physical register number conespondmg to each logical register, representmg the committed register state for each logical register The physical register numbers displaced from architectural renames block 34 upon update of the conespondmg logical register with a new physical register number are returned to the free list of physical register numbers for allocation to subsequent instructions In one embodiment, pnor to returning a physical register number to the free list, the physical register numbers are compared to the remammg physical register numbers withm architectural renames block 34 If a physical register number is still represented within architectural renames block 34 after bemg displaced, the physical register number is not added to the free list Such an embodiment may be employed m cases m which the same physical register number is used to store more than one result of an instruction For example, an embodiment employmg the x86 mstruction set architecture may provide physical registers large enough to store floating pomt operands In this manner, any physical register may be used to store any type of operand However, mteger operands and condition code operands do not fully utilize the space withm a given physical register In such an embodiment, processor 10 may assign a smgle physical register to store both mteger result and a condition code result of an mstruction A subsequent retirement of an mstruction which overwntes the condition code result conespondmg to the physical register may not update the same mteger register, and hence the physical register may not be free upon committing a new condition code result Similarly, a subsequent retirement of an mstruction which updates the mteger register conespondmg to the physical register may not update the condition code register, and hence the physical register may not be free upon committing the new mteger result Still further, map unit 30 and map silo 32 are configured to receive exception indications from PC silo 48 Lmes of mstruction operations subsequent to the lme mcludmg the exception-causmg mstruction operation are marked invalid withm map silo 32 The physical register numbers conespondmg to the subsequent lmes of mstruction operations are freed upon selection of the conespondmg lmes for retirement (and architectural renames block 34 is not updated with the invalidated destmation registers) Additionally, the lookahead register state maintained by map unit 30 is restored to the lookahead register state conespondmg to the exception-causmg mstruction The lme of mstruction operations, source physical register numbers, source queue numbers, and destination physical register numbers are stored mto mstruction queues 36A-36B accordmg to the queue numbers assigned by map unit 30 Accordmg to one embodiment, mstruction queues 36A-36B are symmetrical and can store any mstructions Furthermore, dependencies for a particular mstruction operation may occur with respect to other mstruction operations which are stored m either mstruction queue Map unit 30 may, for example, store a lme of mstruction operations mto one of mstruction queues 36A-36B and store a following lme of instruction operations into the other one of mstruction queues 36A-36B An mstruction operation remains m mstruction queue 36A-36B at least until the prior mstruction operations upon which the mstruction operation is dependent are executed and have updated register files 38A-38B (and the mstruction operation is scheduled for execution) In one embodiment, mstruction operations remam m mstruction queues 36A-36B until retired Instruction queues 36A-36B, upon schedulmg a particular mstruction operation for execution, determine at which clock cycle that particular mstruction operation will update register files 38A-38B Different execution units withm execution cores 40A-40B may employ different numbers of pipeline stages (and hence different latencies) Furthermore, certain mstructions may experience more latency withm a pipeline than others Accordmgly, a countdown is generated which measures the latency for the particular instruction operation (m numbers of clock cycles) Instruction queues 36A-36B await the specified number of clock cycles until the update occurs, and then mdicate that mstruction operations dependent upon that particular mstruction operation may be scheduled Each mstruction queue 36A-36B maintains the countdowns for instruction operations withm that mstruction queue, and internally allow dependent mstruction operations to be scheduled upon expiration of the countdown Additionally, the mstruction queue provides indications to the other instruction queue upon expiration of the countdown Subsequently, the other mstruction queue may schedule dependent mstruction operations This delayed transmission of mstruction operation completions to the other instruction queue allows register files 38A-38B to propagate results provided by one of execution cores 40A-40B to the other register file Each of register files 38A-38B implements the set of physical registers employed by processor 10, and is updated by one of execution cores 40A-40B The updates are then propagated to the other register file It is noted that instruction queues 36A-36B may schedule an mstruction once its dependencies have been satisfied (I e out of order with respect to its order withm the queue) Instruction operations scheduled from mstruction queue 36A read source operands accordmg to the source physical register numbers from register file 38 A and are conveyed to execution core 40A for execution Execution core 40A executes the mstruction operation and updates the physical register assigned to the destination withm register file 38A Some mstruction operations do not have destmation registers, and execution core 40A does not update a destmation physical register m this case Additionally, execution core 40A reports the R# of the mstruction operation and exception mformation regardmg the instruction operation (if any) to PC silo and redirect unit 48 Instruction queue 36B, register file 38B, and execution core 40B may operate m a similar fashion In one embodiment, execution core 40A and execution core 40B are symmetrical Each execution core 40 may mclude, for example, a floating pomt add unit, a floating pomt multiply unit, two mteger, units a branch unit, a load address generation unit, a store address generation unit, and a store data unit Other configurations of execution units are possible Among the mstruction operations which do not have destination registers are store address generations, store data operations, and branch operations The store address/store data operations provide results to load/store unit 42 Load/store unit 42 provides an interface to D-cache 44 for performing memory data operations Execution cores 40A-40B execute load ROPs and store address ROPs to generate load and store addresses, respectively, based upon the address operands of the mstructions More particularly, load addresses and store addresses may be presented to D-cache 44 upon generation thereof by execution cores 40A-40B (directly via connections between execution cores 40A-40B and D-Cache 44) Load addresses which hit D-cache 44 result m data bemg routed from D-cache 44 to register files 38 On the other hand, store addresses which hit are allocated a store queue entry Subsequently, the store data is provided by a store data mstruction operation (which is used to route the store data from register files 38A-38B to load/store unit 42) Upon retirement of the store mstruction, the data is stored mto D-cache 44 Additionally, load/store unit 42 may include a load/store buffer for stormg load/store addresses which miss D-cache 44 for subsequent cache fills (via external interface 46) and re- attempting the missing load/store operations Load/store unit 42 is further configured to handle load/store memory dependencies Turning now to Fig 2, a block diagram of one embodiment of map unit 30, map silo 32, and architectural renames block 34 is shown to highlight interconnection therebetween accordmg to one embodiment of processor 10 Other embodiments are possible and contemplated employmg additional, substitute, or less interconnect, as desired Decode unit 24 is connected to an ROP mformation bus 60 which is further connected to both map unit 30 and map silo 32 Information regardmg a lme of mstruction operations (or line of ROPs) is provided by decode unit 24 upon ROP mformation bus 60 For each ROP withm the lme, decode unit 24 provides at least the following a valid mdication, an mdication of whether the ROP writes a destmation register, an R#, a logical destination register number, and logical source register numbers (up to two) Map unit 30 assigns a destination IQ# to each ROP, and a destmation PR# to each ROP which wntes a destination register Map unit 30 provides the assigned PR# and IQ# to map silo 32 upon a destmation PR#/IQ# bus 62 Additionally, map unit 30 provides a cunent lookahead register state to map silo 32 upon a cunent lookahead register state bus 64 Generally, the term "lookahead register state" refers to identifying the state of the logical registers (l e the values stored therem) at a particular pomt m execution of a program sequence (l e subsequent to executmg each mstruction pnor to the particular pomt m the program sequence and prior to executmg each mstruction subsequent to the particular pomt in the program sequence) The cunent lookahead register state identifies the set of physical registers which conespond to the logical registers pnor to the lme of ROPs bemg processed by map unit 30 In other words, the cunent lookahead register state stores the physical register number conespondmg to each logical register Additionally, m the present embodiment, the cunent lookahead register state mcludes the IQ# of the instruction which updates the identified physical register and a valid bit mdicatmg whether or not the IQ# is still valid (l e the mstruction has not yet been retired) Map silo 32 allocates an entry for the lme of ROPs and stores the cunent lookahead register state and assigned PR#s and IQ#s provided by map unit 30 Additionally, map silo 30 may capture which ROPs are valid, which ROPs update logical registers, and which logical registers are updated by those ROPs from ROP mformation bus 60 An exemplary map silo entry is illustrated below (Fig 9) Generally, a "silo" as refened to herem is a structure for stormg information conespondmg to an mstruction, an mstruction operation, or a lme of mstruction operations The silo keeps the mformation m program order, and the mformation logically moves from the top of the silo (or the tail) to the bottom (or the head) of the silo as mstructions are retired in program order (in the absence of exception conditions) As used herem, an mstruction is retired when the result of the mstruction is committed to architectural state (e g by allowing the update of architectural renames block 34 with the physical register number assigned to the destination of the mstruction or by allowing the update of D-cache 44 with store data conespondmg to the instruction) Map silo 32 is connected to receive a retire valid signal upon a retire valid line 66 and a exception valid mdication and R# upon an exception mformation bus 68 Retire valid lme 66 and exception information bus 68 are connected to PC silo 48 In response an asserted retire valid signal, map silo 32 provides retired register mformation on a retire regιster/PR# bus 70 to architectural renames block 34 from the entry at the head of the silo More particularly, retire regιster/PR# bus 70 may convey a logical register number to be updated and the conespondmg physical register number In the present embodiment, retirement of ROPs occurs concunently for a full lme (I e PC silo 48 signals retirement once each of the ROPs m the lme at the head of PC silo 48 and map silo 32 have successfully executed) Accordmgly, a signal to retire the oldest lme may be used m the present embodiment Other embodiments may provide for partial retirement or may organize storage via individual instruction operations, m which case retirement may occur by mstruction operation, etc Architectural renames block 34, prior to updating entries conespondmg to the logical registers specified on retire regιster/PR# bus 70, reads the cunent physical register numbers conespondmg to those logical registers In other words, the physical register numbers bemg displaced from architectural renames block 34 (the "previous physical register numbers") are popped out of architectural renames block 34 Architectural renames block 34 provides the previous PR#s on a previous PR# bus 72 which is connected to map unit 30 and updates the specified logical register entries with the PR# provided on retire regιster/PR# bus 70 Generally, the previous PR# are eligible to be added to the free list of PR#s (and for assignment to the destination register of a subsequent ROP) However, m the present embodiment, processor 10 employs a physical register shanng technique to improve the efficiency of physical register usage For example, a physical register may be assigned to store both an mteger value and a condition code value (or flags value) A portion of the physical register storage stores the mteger value and another portion stores the condition code value Accordmgly, when a previous PR# is popped, for example, upon update of the mteger register to which the PR# was assigned, the PR# may still represent the condition codes stored therem (and vice-versa) Architectural renames block 34 compares the previous PR# to the updated architectural state to determine which registers are actually eligible to be freed (represented m Fig 2 by register 75 capturing the PR#s from previous PR# bus 72 and returning the captured numbers to architectural renames block 34, although other embodiments may accomplish the update and compare m one clock cycle) For example, architectural renames block 34 may employ a content addressable memory (CAM) for stormg the PR#s conespondmg to the logical registers Architectural renames block 34 may convey a cam match signal upon a cam matches bus 74 conespondmg to each PR# conveyed upon previous PR# bus 72 Map unit 30 may free the registers specified on previous PR# bus 72 if the conespondmg cam match signal is not asserted Advantageously, physical register usage may be more efficient and yet physical registers may be accurately freed It is noted that, in other contemplated embodmients, separate physical registers may be assigned to each logical register updated m response to an instruction operation It is noted that, m the event that a previous PR# is not freed upon bemg popped from architectural renames block 34, a subsequent retirement of an mstruction which updates the logical register which is still represented by the previous PR# may lead to the freemg of the previous PR# Upon the subsequent retirement, a cam match may not be detected As used herem, a physical register is "free" if it is available for assignment to the destination operand of an mstruction bemg processed by the renammg hardware In the present embodiment, a physical register is freed upon retirement of a subsequent instruction updatmg the logical register to which the physical register is assigned Other embodiments may free the register in alternative fashions It is noted that one or more instruction operations within a lme may update the same logical register Accordmgly, one of map silo 32 or architectural renames block 34 mcludes logic to scan the logical registers bemg retired to identify the oldest update to each logical register (I e the last update, in program order) and stores the physical register number coπesponding to that oldest update in architectural renames block 34. The newer updates may be freed similar to the above discussion (i.e. cammed and freed if no match occurs). Map silo 32 may receive an exception indication from PC silo 48 as well. PC silo 48 may assert the exception valid signal and provide an R# of the instruction operation experiencing the exception to map silo 34 via exception information bus 68. Map silo 32 selects the silo entry conesponding to the line of ROPs including the instruction operation experiencing the exception (using the portion of the R# which is constant for each ROP in the line). Map silo 32 provides the cunent lookahead register state stored in the selected entry to map unit 30 upon recover lookahead register state bus 76. Map unit 30 restores the lookahead register state to the recovered state. Additionally, map silo 32 provides the logical register numbers, PR#s, and IQ#s of ROPs within the line but prior to the ROP experiencing the exception. Map unit 30 updates the restored lookahead state with the provided PR#s and IQ#s. Advantageously, the lookahead state is rapidly recovered. Instructions fetched in response to the exception condition may be renamed upon reaching map unit 30 due to the rapid recovery of the renames. Additionally, in response to an exception, physical registers assigned to ROPs subsequent to the ROP experiencing the exception are freed. Map silo 32 conveys the PR#s to be freed upon a free PR# bus 78 to map unit 30. In one embodiment, map silo 32 may be configured to provide the PR#s to be freed at a rate of one line per clock cycle. Additionally, since the ROPs to which the physical registers were assigned were not retired, the physical registers need not be conveyed to architectural renames block 34 for camming. Turning now to Fig. 3, a block diagram of one embodiment of map unit 30 is shown. Other embodiments are possible and contemplated. In the embodiment of Fig. 3, map unit 30 includes a register scan unit 80, an IQ#/PR# control unit 82, a lookahead register state 84, a virtual physical register map unit 86, a free list control unit 88, and a free list register 90. Register scan unit 80 is connected to receive source and destination register numbers (and a valid indication for each) from decode unit 24 upon bus 60A (a portion of ROP information bus 60 shown in Fig. 2). Register scan unit 80 is configured to pass the destination register numbers and source virtual register numbers to virtual physical register map unit 86. IQ#/PR# control unit 82 is connected to a bus 60B (a portion of ROP information bus 60 shown in Fig. 2) to receive destination register numbers and valid indications conesponding to the destination register numbers. Instruction queues 36A-36B provide tail pointers upon tail pointers bus 92, indicating which entry in each queue is cunently the tail of the queue. Additionally, IQ#/PR# control unit 82 is connected to destination PR#/IQ# bus 62. Virtual/physical register map unit 86 is connected to recover lookahead register state bus 76 and to lookahead register state 84, which is further connected to cunent lookahead register state bus 64. Still further, virtual/physical register map unit 86 is connected to provide source PR#s, source IQ#s, destination PR#s, and an IQ# for each ROP within the line upon a source/destination PR# and IQ# bus 94 to instruction queues 36A-36B. Free list control unit 88 is connected to IQ#/PR# control unit 82 via a next free PR# bus 96 and an assigned PR# bus 99, and is connected to free list register 90. Furthermore, free list control unit 88 is connected to previous PR# bus 72, cam matches bus 74, and free PR# bus 78. In the embodiment of Fig. 3, map unit 30 performs register renaming using a two stage pipeline design. In the first stage, register scan unit 80 assigns virtual register numbers to each source register. In parallel, IQ#/PR# control unit 82 assigns IQ#s (based upon the tail pointers provided by instruction queues 36A-36B) to each ROP and PR#s to the ROPs which have a destination register. In the second stage, virtual/physical register map unit 86 maps the virtual register numbers to physical register numbers (based upon the cunent lookahead state and the assigned PR#s) and routes the physical register numbers assigned by IQ#/PR# control unit 82 to the issue position of the conesponding ROP. The virtual register numbers assigned by register scan unit 80 identify a source for the physical register number. For example, in the present embodiment, physical register numbers conesponding to source registers may be drawn from either lookahead register state 84 (which reflects updates conesponding to the lines of ROPs previously processed by map unit 30) or from a previous issue position within the line of ROPs (if the destination operand of the previous ROP is the same as the source operand...i.e. an intraline dependency exists). In other words, the physical register number conesponding to a source register number is the physical register number maintained by lookahead register state 84 unless an intraline dependency is detected. Register scan unit 80 effectively performs intraline dependency checking. Other embodiments may provide for other sources of source operands, as desired. By separating intraline dependency checking/destination physical register assignment from physical register number mapping into pipeline stages, each stage may be operated at a higher frequency. Accordingly, the embodiment of map unit 30 shown in Fig. 3 may be operable at a higher frequency than other embodiments which perform intraline dependency checking and destination physical register assignment in parallel with determining source physical register numbers. Using the virtual register numbers allows the separation of the functions and, as illustrated in Fig. 8 below, allows for a relatively simple and efficient mapping of source physical register numbers. IQ#/PR# control unit 82 assigns instruction queue numbers beginning with the tail pointer of one of instruction queues 36A-36B. In other words, the first ROP within the line receives the tail pointer of the selected instruction queue as an IQ#, and other ROPs receive IQ#s in increasing order from the tail pointer. Control unit 82 assigns each of the ROPs in a line to the same instruction queue 36A-36B, and allocates the next line of ROPs to the other instruction queue 36A-36B. Control unit 82 conveys an indication of the number of ROPs allocated to the instruction queue 36A-36B via ROP allocated bus 98. The receiving instruction queue may thereby update its tail pointer to reflect the allocation of the ROPs to that queue. Control unit 82 receives a set of free PR#s from free list control unit 88. The set of free PR#s are assigned to the destination registers within the line of instruction operations. In one embodiment, processor 10 limits the number of logical register updates within a line to four (i.e. if predictor miss decode unit 26 encounters a fifth logical register update, the line is terminated at the previous instruction). Hence, free list control unit 88 selects four PR#s from free list 90 and conveys the selected registers to control unit 82 upon next free PR# bus 96 . Control unit 82 responds with which PR#s were actually assigned via assigned PR# bus 99, and free list control unit 88 deletes the assigned physical registers from the free list. Other embodiments may employ different limits to the number of updates within a line, including no limit (i.e. each ROP may update). Free list control unit 88 is configured to manage the freeing of physical registers and to select registers for assignment to subsequent instructions. Free list register 90 may store, for example, a bit conesponding to each physical register. If the bit is set, the conespondmg register is free If the bit is clear, the conespondmg register is cunently assigned (1 e not free). Free list control unit 88 scans the free list to select registers for conveyance to control unit 82. For example, free list control unit 88 may scan for the first two free registers from each end of free list register 90 to allow for rapid selection of the four registers provided m the present embodiment. These scans may be performed as two pick one operations from each end (one performed before the other and removmg the assigned physical register from the free list). Free list control unit 88 receives the previous physical register numbers popped from architectural renames block 34 via previous PR# bus 72 Subsequently, the cam match signals conespondmg to each previous physical register number are received upon cam matches bus 74 Each previous PR# for which the conespondmg cam match signal is deasserted is added to the free list by free list control unit 88 Additionally, physical register numbers received upon free PR# bus 78 are unconditionally added to the free list. Lookahead register state 84 stores the lookahead register state prior to updates conespondmg to the line of ROPs presented to virtual/physical register map unit 86 More particularly, lookahead register state 84 stores a physical register number conespondmg to each logical register and (m the present embodiment) an instruction queue number conespondmg to the ROP having the physical register number assigned as a destmation register Each clock cycle, lookahead register state 84 conveys the cunent lookahead register state to map silo 32 upon cunent lookahead register state bus 64. Virtual/physical register map unit 86 supplies the PR# and IQ# of the conespondmg logical register as indicated by lookahead register state 84 for each source register havmg a virtual register number mdicatmg that the source of the PR# is lookahead register state 84 Source registers for which the virtual register number mdicates a prior issue position are supplied with the conespondmg PR# and IQ# assigned by contiol unit 82 Furthermore, virtual/physical register map unit 86 updates the lookahead register state 84 accordmg to the logical destmation registers specified by the lme of ROPs and the destination PR#s/IQ#s assigned by control unit 82. Virtual/physical register map unit 86 is further configured to receive a recovery lookahead register state provided by map silo 32 upon recovery lookahead register state bus 76 m response to an exception condition (as descnbed above). Virtual/physical register map unit 86 may ovenide the next lookahead register state generated accordmg to mputs from register scan unit 80 and IQ#/PR# control unit 82 with the recovery lookahead state provided by map silo 32. It is noted that, m the present embodiment, IQ#s are routed for each source operand to mdicate which mstruction queue entries the conespondmg ROP is dependent upon Instruction queues 36A-36B await completion of the ROPs m the conespondmg mstruction queue entries before schedulmg the dependent ROP for execution. Turning now to Fig. 4, a block diagram illustrating one embodiment of register scan unit 80 is shown Other embodiments are possible and contemplated In the embodiment of Fig. 4, register scan unit 80 mcludes a scan unit conespondmg to each issue position withm the line of ROPs For example, the present embodiment includes eight scan units 100A-100H conespondmg to eight issue positions (although more or fewer may be implemented). Scan units 100A-100H are connected into a serial chain for passmg virtual lookahead register state, and m parallel to receive source and destination register numbers. Each scan unit 100A-100H is connected to a portion of ROP bus 60 A shown m Fig 3 More particularly, each scan unit 100A-100H is connected to receive the source and destmation register numbers of the ROP m the conespondmg issue position Accordmgly, a bus 60AA is connected to scan unit 100 A, providmg the source and destmation register numbers for issue position zero (l e the first ROP in program order withm the lme of ROPs) Similarly, bus 60AB is connected to scan unit 100B, providmg the source and destmation register numbers for issue position one Other buses 60AC-60AH provide source and destmation register numbers conespondmg to the remammg issue positions m order, as shown Each scan unit 100A-100H is configured to provide a source virtual register number for each source register, which is subsequently passed to virtual/physical register map unit 86 Scan unit 100A is coupled to receive a virtual cunent lookahead register state The virtual cunent lookahead register state mcludes a virtual register number conespondmg to each logical register The virtual register numbers within the virtual cunent lookahead state mdicate that the source of the PR# (and IQ#) is lookahead register state 84 In one embodiment employing the x86 mstruction set architecture, for example, lookahead register state 84 mcludes 8 registers conespondmg to the architected integer registers, 3 registers conespondmg to groups of condition code bits (groupmgs are selected according to which ones are updated by various mstructions, e g the O bit may be one group, the C bit another group, and the Z, A, P, and S bits the third group), 8 registers conespondmg to the architected floating point/MMX registers, one register conespondmg to the floating pomt condition code register, and 8 registers conespondmg to temporary microcode registers Scan unit 100 A assigns source virtual register numbers from the virtual cunent lookahead register state based upon the source register numbers Additionally, if the ROP m issue position zero updates a destination register, scan unit 100A updates the virtual cunent lookahead state by inserting a new virtual register number for the conespondmg logical destination register The new virtual register number mdicates that the source of the PR# and IQ# for the conespondmg logical register is issue position zero An updated lookahead register state with the new virtual register number inserted m place of the ongmal virtual register number is passed to scan unit 100B Scan unit 100B accepts the updated lookahead register state from scan unit 100A and assigns virtual register numbers from the updated lookahead register state to the source register numbers Furthermore, scan unit 100B inserts a new virtual register number mdicatmg issue position one mto the updated lookahead register state provided by scan unit 100A if the ROP m issue position one updates a logical register Scan units 100C-100H similarly assign virtual register numbers for the source registers of ROPs m issue positions 3-8, respectively, responsive to an updated lookahead register state provided by the precedmg scan units, and updates the updated lookahead register state accordmg to the destination register number, if any Accordmgly, if a pnor ROP withm the lme updates a logical register specified by a source register number of an ROP, a virtual register number mdicatmg the prior issue position is assigned Otherwise, a virtual register number mdicatmg the cunent lookahead register state for the conesponding logical register is assigned In other words, intraline dependencies and dependencies upon previous lmes of instructions (through the cunent lookahead register state) are indicated by the virtual register numbers The updated lookahead register state provided by scan unit 100H is the virtual next lookahead register state, which is conveyed to virtual/physical register map unit 86 along with the source virtual register numbers provided by each of the scan units 100A-100H and the destination register numbers Virtual/physical register map unit 86 may then generate the next lookahead register state conespondmg to the lme of ROPs, m order to update lookahead register state 84 for the subsequent lme of ROPs It is noted that, m one embodiment, each scan unit 100A-100F includes an integer/temporary scan cncuit handlmg the mteger, temporary, and condition code registers and a floating pomt scan circuit handling the floating pomt registers and floating pomt condition code register Accordmgly, an mdication of whether each source and destination register is a floating pomt or mteger register is routed with the register number and used to determine which virtual register number to assign to the register or to replace with a new virtual register number Turning next to Fig 5, a table 102 is shown illustrating an exemplary encodmg of virtual register numbers Other encodmgs are possible and contemplated Particularly, for example, the logical state of the most significant bit (MSB) shown m table 102 may be inverted from that shown in the table Still other encodmgs are possible as well Table 102 illustrates a virtual register number encodmg m which the MSB determines whether the source for conespondmg PR#/IQ# is the cunent lookahead state mamtamed by lookahead register state 84 or the destination PR#/IQ# assigned to a prior issue position withm the lme For example, if the MSB is clear, then the virtual register number is mdicatmg the source is the cunent lookahead state and the least significant bits (LSBs) of the virtual register number are the logical register number within the cunent lookahead state If the MSB is set, then the virtual register number is indicating that the source is a prior issue position The LSBs in this case are the pnor issue position number In an embodiment employmg the encodmgs shown m table 102, the virtual cunent lookahead state provided to scan unit 100A comprises encodmgs with the MSB clear and the conespondmg logical register number provided in the LSBs New virtual register numbers inserted mto the updated lookahead register state by scan units 100A-100H comprise encodings with the MSB set and the issue position number conespondmg to the inserting scan unit provided m the LSBs Turning next to Fig 6, a portion of one embodiment of an integer/temporary scan circuit 110 is shown which may be employed withm one embodiment of each of scan units 100A- 100H Other embodiments are possible and contemplated In the embodiment of Fig 6, the destination register number of the conespondmg ROP is conveyed upon a destmation bus 112, the first source (SRCl) register number of the conespondmg ROP is conveyed upon a SRCl bus 114, and the second source (SRC2) register number of the conespondmg ROP is conveyed upon a SRC2 bus 116 Buses 112, 114, and 116 comprise a portion of bus 60A (e g , if integer/temporary scan cncuit 110 is a portion of scan unit 100A, buses 112, 114, and 116 are portions of bus 60AA) Destmation bus 112 is connected to a plurality of destmation identifier units (e g units 118A and 118B shown m Fig 6) Each destination identifier unit 118A- 118B is connected to a pass/write control unit (e g pass/write control units 120A and 120B connected to destmation identifier units 118A and 118B, respectively) Each pass control unit 120A-120B is further connected to a virtual register input provided by a preceding scan unit 100A-100H and to a virtual register output to a succeedmg scan unit 100A-100H (e g pass/write control unit 120A is connected to a virtual EAX mput bus 122A and a virtual EAX output bus 124A and pass/write control unit 120B is connected to a virtual EBX mput bus 122B and a virtual EBX output bus 124B) Additionally, SRCl bus 114 is connected to a plurality of SRCl identifier units (e g SRCl identifier units 126A and 126B shown m Fig 6) SRC2 bus 116 is similarly connected to a plurality of SRC2 identifier units (e g SRC2 identifier units 128A and 128B shown in Fig 6) Each SRC1/SRC2 identifier unit 126A-126B or 128A-128B is connected to an enable control of a conesponding switch 130A-130D as shown in Fig 6 Switches 130A-130B have mputs connected to virtual EAX mput bus 122 A, while switches 130C-130D have inputs connected to virtual EBX mput bus 122B Switches 130A and 130C have outputs connected to a SRCl virtual register bus 132A, while switches 130B and 130D have outputs connected to a SRC2 virtual register bus 132B Generally, integer/temporary scan circuit 110 assigns the virtual register numbers for integer/temporary source registers of the ROP in the conespondmg issue position and inserts new virtual register numbers for an mteger destmation register in the conespondmg issue position Each set of a destination identifier unit, pass/wnte control unit, SRCl identifier unit, and SRC2 identifier unit conesponds to one of the logical mteger, temporary, or condition code registers For example, destmation identifier unit 118 A, pass/write control unit 120A, SRCl identifier unit 126A, and SRC2 identifier unit 128A conesponds to the EAX register Similarly, destmation identifier unit 118B, pass/write control unit 120B, SRCl identifier unit 126B, and SRC2 identifier unit 128B conesponds to the EBX register Other sets of destmation identifier units, pass/write control units, SRCl identifier units, and SRC2 identifier units (not shown) conespond to other ones of the logical mteger, temporary, or condition code registers The succeedmg discussion will describe the EAX register hardware The EBX register hardware operates similarly with respect to the EBX register, and other similar hardware (not shown) operates similarly with respect to remammg registers Destmation identifier unit 118A determines if the destmation register number on destmation register bus 112 selects the EAX register Accordmgly, destmation identifier unit 118 A decodes the destmation register number to determine if EAX is selected, and the decode is qualified with a valid signal indicating that the destmation register number is valid and an integer signal mdicatmg that the destination register number is an integer/temporary/condition code register (l e not a floating point register) If the destination register is the EAX register, destination identifier unit 118A signals pass/write control unit 120A to insert the virtual register number conesponding to the issue position in which integer/temporary scan circuit 110 is employed upon virtual EAX output bus 124A Otherwise, destination identifier unit 118A signals pass/write control unit 120A to pass the virtual register number provided upon virtual EAX mput bus 122 A to virtual EAX output bus 124 A Similarly, SRCl identifier unit 126A determines if the SRCl register number on SRCl register bus 114 selects the EAX register by decodmg the SRCl register number to determine if EAX is selected, and qualifying the decode with a valid signal mdicatmg that the SRCl register number is valid and an mteger signal mdicatmg that the SRCl register number is an lnteger/temporary/condition code register If EAX is selected as SRCl, SRCl identifier unit 126A activates switch 130A to drive the virtual register number provided upon virtual EAX mput bus 122A onto SRCl virtual register bus 132A SRC2 identifier unit 128A is similar to SRCl identifier unit 126A but operates upon the SRC2 register number provided upon SRC2 register bus 116 and controls switch 130B to accordingly drive or not drive SRC2 virtual register bus 132B In this fashion, an updated lookahead state may be passed to the next scan unit (via virtual output buses such as 124A-124B), and source virtual register numbers may be assigned (via buses such as SRCl virtual register bus 132A and SRC2 register number bus 132B) It is noted that integer/temporary scan circuit 110 may be modified to handle register to register move operations by routmg each of the virtual integer/temporary mputs to pass/write control unit 120A (and other pass/write control units) Additional signalling may be provided to mdicate that the ROP m the cunent issue position is a register-register move In response to the SRCl register number and the move signal, the virtual integer/temporary mput conespondmg to the SRCl register number is routed to the virtual integer/temporary output conespondmg to the destination register Additionally, the ROP m the conespondmg issue position is inhibited from passmg to mstruction queues 36A-36B (e g its valid bit is reset), smce the move is accomplished by routing the source virtual register number as the destmation virtual register number In such an embodiment, the camming of retired physical registers prior to freemg them may prevent the inadvertent early freemg of the destmation PR# Turning now to Fig 7, a portion of one embodiment of a floatmg pomt scan circuit 140 is shown which may be employed withm one embodiment of each of scan units 100A-100H Other embodiments are possible and contemplated Scan circuit 140 receives SRCl register bus 114 and SRC2 register bus 116, similar to integer/temporary scan cncuit 110, and may drive source virtual register numbers upon SRCl virtual register bus 132A and SRC2 virtual register bus 132B The portion shown m Fig 7 receives the virtual stl mput (l e one of stO through st7 registers as defined m the x86 mstruction set architecture, hence 0<I<7) and provides the virtual stl output for the issue position in which circuit 140 is employed (the "present issue position") A SRCl identifier unit 142 A connected to SRCl register bus 114 determmes if the SRCl register number is selectmg the stl register (l e the register number is stl, the register is a floatmg pomt register, and the SRCl register is valid) If the SRCl register number is selecting the stl register, SRCl identifier unit 142 A controls switch 130E to drive the virtual register number provided upon a virtual stl mput bus 144 onto SRCl virtual register bus 132A Similarly, a SRC2 identifier unit 142B connected to SRC2 register bus 116 determines if the SRC2 register number is selectmg the stl register and selectively controls a switch 130F to drive the virtual register number provided upon virtual stl mput bus 144 onto SRC2 virtual register bus 132B Additionally, the portion of floating pomt scan circuit 114 shown in Fig 7 provides an output virtual register number conespondmg to register stl on virtual stl output bus 146 A variety of mput virtual register numbers may be selectable as the output virtual register number upon output bus 146, controlled by a vanety of control signals provided by decode unit 24 The x86 floatmg pomt mstructions treat the floating point register set as a stack StO is the register at the top of the stack, stl is next to the top, etc Certain mstructions may cause the stack to be pushed (makmg the cunent stO register stl, etc ) or popped (makmg the cunent stl register stO, etc Still further, an exchange mstruction is supported which swaps the top of stack register (stO) and one of the other registers The selection of a virtual stl output attempts to handle many of these situations by employing switches 130G-130K and a set of mput virtual register buses 144, 148, 150, 152, and 154 If the ROP in the present issue position does not affect the floating point stack or the stl register individually, the pass signal is asserted to switch 130G (connected between virtual stl input bus 144 and virtual stl output bus 146) and the virtual stl mput is provided as the virtual stl output On the other hand, if the ROP m the present issue position updates the stl register, the wnte signal is asserted to switch 130J (connected between bus 152 and bus 146), and the virtual register number conespondmg to the present issue position (conveyed upon bus 152) is transmitted upon virtual stl output bus 146 If the ROP m the cunent issue position causes a stack push or pop, conespondmg signals are asserted to switches 130K (connected between bus 154 and bus 146) and 1301 (connected between bus 152 and bus 146) respectively Virtual register numbers conespondmg to the stl-l and stl+l registers withm the updated lookahead state provided to the present issue position are thereby provided Finally, the virtual stO mput from the issue position two pnor to the present issue position is provided upon bus 148 If the present ROP is the second half of an FEXC mstruction, the EXCH signal is asserted to switch 130H and the virtual register number conespondmg to stO from the issue position two pnor to the present issue position is selected as the virtual stl output It is noted that, to handle the first half of the FEXC mstruction, the portion of floatmg pomt scan circuit 140 conespondmg to stO may mclude each of the virtual stl mputs from the previous scan unit, to arbitranly select any register as the virtual stO output It is further noted that the top of stack (TOS) field of the floating point status register and the floatmg point tag word are affected by floatmg pomt manipulations as well Lookahead values for the TOS and tag word may be propagated through pushes, pops, and exchanges as well A cunent lookahead copy of the TOS and tag word may be mamtamed m lookahead register state 84 Furthermore, the value of the TOS and tag word conespondmg to each issue position may be stored in map silo 32 for exception recovery (and the last value may be updated mto lookahead register state 84) Still further, register scan unit 80 may detect the use of a register which is mvalid (as mdicated by the tag word) and note an exception with the ROP usmg the register for later exception handlmg It is noted that integer/temporary scan cncuit 110 and floating pomt scan circuit 140 may handle mteger to floatmg pomt and floating pomt to mteger moves as well If a source register of an ROP is mdicated to be mteger, integer/temporary scan circuit 110 provides the source virtual register number On the other hand, if the source register of an ROP is mdicated to be floating point, floatmg point scan circuit 140 provides the source virtual register number If a destination register is mdicated as floatmg pomt, a new floatmg pomt virtual register number is provided mto the updated lookahead register state by floating pomt scan circuit 140 On the other hand, if a destmation register is mdicated as mteger, a new integer virtual register number is provided mto the updated lookahead register state by integer/temporary scan circuit 110 Accordmgly, an issue position having a floating pomt to mteger register move is assigned a floatmg pomt source virtual register number and the destmation register number mdicates mteger On the other hand, an issue position having an mteger to floating pomt register move is assigned an mteger source virtual register number and the destination register number mdicates floatmg pomt Turning now to Fig 8, a block diagram of one embodiment of virtual/physical register map unit 86 is shown Other embodiments are possible and contemplated In the embodiment of Fig 8, virtual/physical register map unit 86 includes a source IQ# mux 160, a next lookahead IQ# mux 162, a source PR# mux 164, a next lookahead PR# mux 168, a trap IQ# mux 170, and a trap PR# mux 172 Source IQ# mux 160 is connected to receive the cunent lookahead IQ# conespondmg to each logical register from lookahead register state 84, and to receive the destmation IQ#s assigned by IQ#/PR# control unit 82 Next lookahead IQ# mux 162 is similarly connected to receive the cunent lookahead IQ#s and destmation IQ#s The output of source IQ# mux 160 is pipelined to mstruction queues 36A-36B, while the output of next lookahead IQ# mux 162 is connected as an mput to trap IQ# mux 170 Trap IQ# mux 170 is further connected to recovery lookahead register state bus 76A (a portion of recovery lookahead register state bus 76 conveymg the IQ#s to be recovered) Source PR# mux 164 is connected to receive the cunent lookahead PR# conespondmg to each logical register from lookahead register state 84, and to receive the destmation PR#s assigned by IQ#/PR# control unit 82 Next lookahead PR# mux 168 is similarly connected to receive the cunent lookahead PR#s and the destmation PR#s The output of source PR# mux 164 is pipelined to mstruction queues 36A-36B The output of next lookahead PR# mux 168 is connected to a trap PR# mux 172, which is further connected to recovery lookahead register state bus 76B (a portion of recovery lookahead register state bus 76 conveymg the PR#s to be recovered) The source virtual register numbers assigned by register scan unit 80 are provided as selection controls to source IQ# mux 160 and to source PR# mux 164 The virtual next lookahead state is provided as selection controls to next lookahead IQ# mux 162 and next lookahead PR# mux 168 Trap controls from PC silo 48 provide selection controls for trap IQ# mux 170 and trap PR# mux 172 Generally, source IQ# mux 160 and source PR# mux 164 select the source IQ# and PR# for each source operand of each ROP responsive to the conespondmg source virtual register number provided by register scan unit 80 Mux 160 may be implemented, for example, as a parallel set of muxes (one for each source register of each ROP) connected to receive the mputs as shown for mux 160 and receivmg a conespondmg source virtual register number as a selection control Similarly, mux 164 may be implemented as a parallel set of muxes (one for each source register of each ROP) connected to receive the inputs as shown for mux 164 and receivmg a conespondmg source virtual register number as a selection control If the source virtual register number indicates that the cunent lookahead state is the source for the IQ#/PR#, then the logical register number mcluded m the source virtual register number is used to select one of the IQ# and PR# provided by lookahead register state 84 On the other hand, if the source virtual register number mdicates a prior issue position, the issue position number is used to select one of the destmation IQ#/PR# assigned by control unit 82 Control unit 82 may provide, for example a destmation IQ# and PR# conespondmg to each issue position On the other hand, control unit 82 may provide a limited number of IQ# and PR# (less than the number of ROPs in a lme) In such an embodiment, logic may be performed upon the source virtual register number and the destmation register valid indications for each ROP to select one of the destmation IQ#/PR# combmations Similarly, next lookahead IQ# mux 162 and next lookahead PR# mux 168 select the IQ# and PR# for each logical register responsive to the conespondmg virtual next lookahead state provided by register scan unit 80 Mux 162 may be implemented, for example, as a parallel set of muxes (one for each logical register) connected to receive the mputs as shown for mux 162 and receivmg a conespondmg virtual register number as a selection control Similarly, mux 168 may be implemented as a parallel set of muxes (one for each logical register) connected to receive the mputs as shown for mux 168 and receiving a conespondmg virtual register number as a selection control If the virtual register number mdicates that the cunent lookahead state is the source for the IQ#/PR# of a particular logical register, then the logical register number mcluded in the virtual register number is used to select one of the IQ# and PR# provided by lookahead register state 84 On the other hand, if the virtual register number mdicates an issue position, the issue position number is used to select one of the destination IQ#/PR# assigned by control unit 82 An advantage may be achievable by physically separating the selection of IQ#s and PR#s based on virtual register numbers as illustrated m Fig 8 A relatively large number of buses are routed to a relatively small amount of cncuitry (I e muxes represented by muxes 160, 162, 164, and 168) Accordingly, the amount of area occupied by virtual/physical register map unit 86 may be dominated by the buses from lookahead register state 84 and IQ#/PR# control unit 82 Smce the IQ# and PR# are separate values, routmg the values to separate sets of muxes may result m a reduction m area occupied by virtual/physical register map unit 86 In one embodiment, the number of bits m an IQ# and the number of bits in a PR# may be approximately the same Accordmgly, wiring the IQ# buses on one side of virtual physical register map unit 86 and wiring the PR# buses on the other side of virtual/physical register map unit 86 may result in a fairly symmetrical layout in which the wiring space on both sides is efficiently used Furthermore, instruction queues 36A-36B may be physically divided mto a schedulmg portion (which receives the IQ#s for determining when the ROPs upon which the cunent ROPs are dependent have completed and hence one of the cunent set of ROPs may be scheduled) and an mstruction storage (which stores the PR#s and other mformation used for mstruction execution, but does not store the IQ#s) Accordmgly, mstruction queues 36A-36B may physically be constructed with the schedulmg portion near the IQ# muxes and the mstruction storage portion near the PR# muxes, further enhancing area savmgs Virtual/physical register map unit 86 as shown m Fig 8 further handles the mappmg of a next lookahead register state for lookahead register state 84 m response to exception conditions Trap IQ# mux 170 is used when traps are recognized upon execution to route the IQ#s conespondmg to the recovery lookahead register state from map silo 32 to ovenide the next lookahead state provided by mux 162 PC silo 48 may signal the trap as a selection control upon mux 170 Similarly, the PR# within the recovery lookahead register state may be selected through trap PR# mux 172 responsive to the trap signal It is noted that, m other embodiments, other methods for recovermg from exception conditions may be employed For example, exception conditions may be handled upon retirement Turning now to Fig 9, a table 180 illustrating the information stored m an entry withm map silo 32 (I e an entry conespondmg to a lme of ROPs) is shown Other embodiments are possible and contemplated As shown m table 180, an R# conespondmg to the lme is stored m an R# (line portion) field The R# stored is the lme portion of the R#s assigned by PC silo 48 to the lme of ROPs The lme portion is the same for each ROP within the lme, while an offset portion of the R# identifies the issue position withm the lme of a particular ROP Accordmgly, the silo entry (which conesponds to the lme as a whole) can be associated with an ROP expenencmg an exception by comparing the lme portion of the R# for the ROP with the stored R# Additionally, an mdication of which ROPs withm the line are valid is stored m a valid ROPs within Lme field of the map silo entry For example, the mdication may be a bit per ROP If the bit is set, the conespondmg ROP withm the line is valid If the bit is clear, the conesponding ROP withm the line is not valid Still further, an mdication of which ROPs have a destmation logical register is stored m a ROP register writes field Agam, the indication may be a bit per ROP If the bit is set, the conespondmg ROP within the line updates a destmation register If the bit is clear, the conesponding ROP withm the lme does not update the destmation register The mdication of which ROPs have a destmation register is used to decide which of the assigned PR#s and assigned IQ#s become part of the recovery state in the event of an exception, as described below The PR#s and IQ#s assigned to the ROPs which have destination registers are mamtamed m assigned PR# and assigned IQ# fields of the entry, respectively Additionally, the logical register number of each destmation register is stored m a logical register numbers field The logical register numbers are used to determine which logical register withm the recovery lookahead state are to receive the assigned PR#s and assigned IQ#s, as descnbed below Additionally, upon successful retirement of the lme, the logical register numbers and conespondmg PR#s are conveyed to architectural renames block 34 for storage An mdication of which ROPs withm the lme update the condition code register is stored in a CC wntes field Each portion of the condition code which is updated separately may be represented by a bit withm the CC writes field, and a set of bits may be associated with each register wnte mdicated withm the ROP register wntes field The PR# and IQ# of the conespondmg ROP (stored m the assigned PR# and IQ# fields) may be used to recover the lookahead condition code register withm the lookahead register state upon detection of an exception Additionally, the CC wntes field mdicates which PR#s withm the assigned PR#s field conespond to the architected condition code state upon successful retirement of the lme of ROPs As mentioned above, m the present embodiment a smgle physical register is used to store both an mteger register update and conespondmg condition code updates The cunent lookahead register state stored withm lookahead register state 84 prior to dispatching the lme of ROPs conespondmg to the map silo entry is stored in a cunent lookahead register state field of the entry The cunent lookahead register state serves as a basis for recovermg lookahead register state 84 m the event of an exception withm the lme Finally, the FP TOS and valid bits conespondmg to each issue position are stored within a FP TOS and valid bits field of the entry The FP TOS and valid bits conespondmg to an ROP expenencmg an exception are restored mto the lookahead FP TOS and tag word withm lookahead register state 84 upon detectmg an exception Turning now to Fig 10, a block diagram of an exemplary lookahead register state entry 182 which may be employed by one embodiment of lookahead register state 84 for a logical register is shown Entry 182 mcludes a valid field 184, an IQ# field 186, and a PR# field 188 Valid field 184 mdicates whether or not IQ# field 186 is valid An IQ# is valid until the conespondmg ROP is completed from mstruction queues 36A-36B Accordmgly, lookahead state 84 may receive mdications from execution cores 40 and load/store unit 42 of which IQ#s are completing Upon detectmg a match, lookahead state 84 may reset the valid mdication The valid mdication may be a bit, for example, mdicatmg valid if set and mvalid if clear IQ# field 186 stores the IQ# of the ROP which most recently updated the logical register, and PR# field 188 stores the PR# of the physical register allocated as a destination register to the ROP Turning next to Fig 11, a flowchart is shown illustrating the operation of map silo 32 m response to an exception condition signalled by PC silo 48 Other embodiments are possible and contemplated While the steps shown m Fig 11 are illustrated in a particular order for ease of understanding, any suitable order may be employed Furthermore, steps may be performed m parallel m combinatorial logic employed withm map silo 32 " As illustrated at step 190, map silo 32 cams the R# provided by PC silo 48 against the R# (line portion) field of the entries stored in map silo 32. The R# provided by PC silo 48 identifies a particular ROP. However, for purposes of checking against map silo 32, the line portion of the R# is cammed. Entries which are more recent than the provided R# (i.e. instructions subsequent to the exception in program order) are cancelled within map silo 32. The PR# stored in the assigned PR# field of the cancelled entries are freed. In one embodiment, the PR#s of the cancelled entries are freed over multiple clock cycles, at the rate of one entry per clock cycle. The silo entry for which the cam indicates a match is the selected map silo entry. The cunent lookahead register state stored in the selected map silo entry (i.e. the cunent lookahead state prior to the line of ROPs including the ROP experiencing the exception is restored to the lookahead state in cunent lookahead register state 84 (step 192). Additionally, the FP TOS and valid bits in lookahead register state 84 are restored to the value stored in the selected map silo entry for the issue position of the ROP experiencing the exception (step 194). The ROP register writes field in the selected map silo entry is masked to the writes which are prior to the ROP experiencing the exception. In other words, ROP register writes which are subsequent to the ROP experiencing the exception are masked off, such that they do not appear to be writes subsequent to the masking. The remaining writes (subsequent to the masking) are scanned to detect the most recent write to each register (i.e. if two or more of the remaining writes are to the same register, the more recent write is retained). The current lookahead state is updated with the results (step 196). It is noted that step 192 and step 196 may be performed in map silo 32 prior to transmitting a recovery lookahead register state to lookahead register state 84. Alternatively, the cunent lookahead register state may be restored to lookahead register state 84 and subsequently updated with respect to step 196. Still further, the ROP register writes field in the selected map silo entry (i.e. the original value prior to the masking of step 196) is masked to the register writes which are subsequent to the ROP experiencing the exception. In other words, the register writes which are prior to the ROP experiencing the exception are masked off. The PR#s of the remaining register writes are freed (step 198). The flowchart shown in Fig. 11 may advantageously provide a rapid method for recovering the lookahead state in response to the exception. It is noted that the terms source virtual register number and virtual source register number may have been used above. It is intended that these terms have the same meaning. It is further noted that, as mentioned above, embodiments in which each instruction specified in the instruction set architecture employed by processor 10 maps to a single instruction operation are contemplated within the meaning of instruction operation as defined herein. Turning now to Fig. 12, a block diagram of one embodiment of a computer system 200 including processor 10 coupled to a variety of system components through a bus bridge 202 is shown. Other embodiments are possible and contemplated. In the depicted system, a main memory 204 is coupled to bus bridge 202 through a memory bus 206, and a graphics controller 208 is coupled to bus bridge 202 through an AGP bus 210. Finally, a plurality of PCI devices 212A-212B are coupled to bus bridge 202 through a PCI bus 214. A secondary bus bridge 216 may further be provided to accommodate an electrical interface to one or more EISA or ISA devices 218 through an EISA/ISA bus 220. Processor 10 is coupled to bus bridge 202 through external interface 52. " Bus bridge 202 provides an interface between processor 10, main memory 204, graphics controller 208, and devices attached to PCI bus 214. When an operation is received from one of the devices connected to bus bridge 202, bus bridge 202 identifies the target of the operation (e.g. a particular device or, in the case of PCI bus 214, that the target is on PCI bus 214). Bus bridge 202 routes the operation to the targeted device. Bus bridge 202 generally translates an operation from the protocol used by the source device or bus to the protocol used by the target device or bus. In addition to providing an interface to an ISA/EISA bus for PCI bus 214, secondary bus bridge 216 may further incorporate additional functionality, as desired. For example, in one embodiment, secondary bus bridge 216 includes a master PCI arbiter (not shown) for arbitrating ownership of PCI bus 214. An input output controller (not shown), either external from or integrated with secondary bus bridge 216, may also be included within computer system 200 to provide operational support for a keyboard and mouse 222 and for various serial and parallel ports, as desired. An external cache unit (not shown) may further be coupled to external interface 52 between processor 10 and bus bridge 202 in other embodiments. Alternatively, the external cache may be coupled to bus bridge 202 and cache control logic for the external cache may be integrated into bus bridge 202. Main memory 204 is a memory in which application programs are stored and from which processor 10 primarily executes. A suitable main memory 204 comprises DRAM (Dynamic Random Access Memory), and preferably a plurality of banks of SDRAM (Synchronous DRAM). PCI devices 212A-212B are illustrative of a variety of peripheral devices such as, for example, network interface cards, video accelerators, audio cards, hard or floppy disk drives or drive controllers, SCSI (Small Computer Systems Interface) adapters and telephony cards. Similarly, ISA device 218 is illustiative of various types of peripheral devices, such as a modem, a sound card, and a variety of data acquisition cards such as GPIB or field bus interface cards. Graphics controller 208 is provided to control the rendering of text and images on a display 226. Graphics controller 208 may embody a typical graphics accelerator generally known in the art to render three- dimensional data structures which can be effectively shifted into and from main memory 204. Graphics controller 208 may therefore be a master of AGP bus 210 in that it can request and receive access to a target interface within bus bridge 202 to thereby obtain access to main memory 204. A dedicated graphics bus accommodates rapid retrieval of data from main memory 204. For certain operations, graphics controller 208 may further be configured to generate PCI protocol transactions on AGP bus 210. The AGP interface of bus bridge 202 may thus include functionality to support both AGP protocol transactions as well as PCI protocol target and initiator transactions. Display 226 is any electronic display upon which an image or text can be presented. A suitable display 226 includes a cathode ray tube ("CRT"), a liquid crystal display ("LCD"), etc. It is noted that, while the AGP, PCI, and ISA or EISA buses have been used as examples in the above description, any bus architectures may be substituted as desired. It is further noted that computer system 200 may be a multiprocessing computer system including additional processors (e.g. processor 10a shown as an optional component of computer system 200). Processor 10a may be similar to processor 10. More particularly, processor 10a may be an identical copy of processor 10. Processor 10a may share external interface 52 with processor 10 (as shown in Fig. 12) or may be connected to bus bridge 202 via an independent bus. In accordance with the above disclosure, a processor has been shown which employs a register renammg scheme. In one embodiment, the renaming scheme is split into stages usmg a virtual register number Advantageously, high frequency operation may be possible using the scheme In another embodiment, a rapid recovery from exceptions is performed by siloing a cunent lookahead state conesponding to each line of ROPs, and notmg the register writes within the line. In yet another embodiment, the freemg of rename registers is managed to allow the same rename register to conespond to more than one logical register Efficient physical register usage may thereby be employed. Numerous vanations and modifications will become apparent to those skilled in the art once the above disclosure is fully appreciated. It is mtended that the following claims be interpreted to embrace all such vanations and modifications.

Claims: WHAT IS CLAIMED IS: 1 A method for managmg physical registers in a processor, the method compnsmg assignmg a first physical register to a destmation operand of an mstruction operation, said destmation operand identifying a logical register, retiring said mstruction operation, updating an architected renames block with a first physical register number conespondmg to said first physical register responsive to said retirmg, readmg a second physical register number from said architected renames block responsive to said retiring, said second physical register number bemg displaced from representmg said logical register within said architected renames block by said first physical register number, and inhibiting freemg said second physical register responsive to determining that said second physical register number represents a second logical register withm said architected renames block 2 The method as recited m claim 1 further compnsmg freemg said second physical register responsive to determining that said second physical register number does not represent said second logical register withm said architected renames block 3 The method as recited m claim 2 further compnsmg comparmg said second physical register number to said physical register numbers stored m said architected renames block subsequent to said updating to perform said determining that said second physical register number represents a second logical register withm said architected renames block 4 The method as recited m claim 3 wherem said inhibiting is performed responsive to said comparing detecting at least one match upon said second physical register number 5 The method as recited m claim 4 wherem said freemg is performed responsive to said comparing detectmg no match upon said second physical register number 6 The method as recited m claim 1 further compnsmg stormg said first physical register number m a silo responsive to said assignmg 7 The method as recited m claim 6 wherem said retirmg is performed upon said first physical register number reachmg a head of said silo 8 The method as recited in claim 1 further compnsmg retmng a second mstruction operation havmg a third physical register assigned to a destination register of said second mstruction operation, said destmation register compnsmg said second logical register, updatmg said architected renames block with a third physical register number conespondmg to said thnd physical register responsive to said retirmg, readmg said second physical register number from said architected renames block responsive to said retinng, and freemg said second physical register number 9 A processor compnsmg a map unit configured to assign a first physical register to a destmation operand of an mstruction operation, said map unit further configured to mamtam a free list indicative of which physical registers are free for assignment, wherem said map unit is configured to select said first physical register from said free list, and an architectural renames block coupled to receive an mdication that said mstruction operation is retirmg and a first physical register number conespondmg to said first physical register, wherem said architectural renames block is configured to provide a second physical register number identifying a second physical register previously conespondmg to a first logical register identified by said destmation operand responsive to said mdication that said mstruction operation is retmng, and wherein said architectural renames block is configured to capture said first physical register number and retain said first physical register number as conespondmg to said first logical register responsive to said mdication that said instruction operation is retinng, and wherein said architectural renames block is further configured to determine if said second physical register number additionally conesponds to a second logical register, wherem said map unit is configured to inhibit addmg said second physical register number to said free list if said second physical register represents said second logical register 10 The processor as recited m claim 9 wherem said map unit is configured to add said physical register number to said free list if said second physical register does not represent said second logical register 11 The processor as recited m claim 9 wherem said architectural renames block is configured to determine if said second physical register number additionally conesponds to said second logical register by comparing said second physical register number to said physical register numbers within said architectural renames block subsequent to capturing said first physical register number 12 The processor as recited m claim 11 wherein said architectural renames block compnses a content addressable memory 13 The processor as recited in claim 9 further compnsmg a silo coupled to said map unit, wherem said silo is configured to store said first physical register number upon assignment to said mstruction operation by said map unit 14 The processor as recited m claim 13 wherem said silo is further coupled to said architectural renames block, and wherem said silo is configured to provide said first physical register number upon retmng of said instruction operation 15 A method for managmg physical registers in a processor, the method compnsmg assignmg a first physical register to a destmation operand of an mstruction operation, said destination operand identifying a logical register, retinng said mstruction operation, updatmg an architected renames block with a first physical register number conespondmg to said first physical register responsive to said retinng, readmg a second physical register number from said architected renames block responsive to said retiring, said second physical register number bemg displaced from representmg said logical register withm said architected renames block by said first physical register number, and freemg said second physical register 16 A processor compnsmg a map unit configured to assign a first physical register to a destination operand of an instruction operation, said map unit further configured to mamtam a free list indicative of which physical registers are free for assignment, wherem said map unit is configured to select said first physical register from said free list, and an architectural renames block coupled to receive an mdication that said mstruction operation is retirmg and a first physical register number conespondmg to said first physical register, wherem said architectural renames block is configured to provide a second physical register number identifying a second physical register previously conespondmg to a first logical register identified by said destmation operand responsive to said indication that said instruction operation is retirmg, and wherem said architectural rename block is configured to capture said first physical register number and retain said first physical register number as conespondmg to said first logical register responsive to said mdication that said instruction operation is retirmg, wherem said map unit is configured to add said second physical register number to said free list A computer system compnsmg a processor compnsmg a map unit configured to assign a first physical register to a destmation operand of an instruction operation, said map unit further configured to mamtam a free list mdicative of which physical registers are free for assignment, wherem said map unit is configured to select said first physical register from said free list, and an architectural renames block coupled to receive an mdication that said instruction operation is retirmg and a first physical register number conespondmg to said first physical register, wherem said architectural renames block is configured to provide a second physical register number identifying a second physical register previously conespondmg to a first logical register identified by said destination operand responsive to said mdication that said instruction operation is retiring, and wherem said architectural renames block is configured to capture said first physical register number and retam said first physical register number as conespondmg to said first logical register responsive to said indication that said mstruction operation is retinng, wherem said map unit is configured to add said second physical register number to said free list, and an input/output (I/O) device coupled to said processor, wherem said I/O device is configured to communicate between said computer system and another computer system to which said I O device is coupled 18 The computer system as recited m claim 17 wherem said architectural renames block is further configured to determine if said second physical register number additionally conesponds to a second logical register, and wherem said map unit is configured to inhibit addmg said second physical register number to said free list if said second physical register represents said second logical register. 19. The computer system as recited in claim 17 further compnsmg a second processor compnsmg: a map unit configured to assign a first physical register to a destmation operand of an mstruction operation, said map unit further configured to mamtam a free list mdicative of which physical registers are free for assignment, wherem said map unit is configured to select said first physical register from said free list; and an architectural renames block coupled to receive an indication that said instruction operation is retinng and a first physical register number conespondmg to said first physical register, wherem said architectural renames block is configured to provide a second physical register number identifying a second physical register previously conespondmg to a first logical register identified by said destmation operand responsive to said mdication that said mstruction operation is retiring, and wherem said architectural renames block is configured to capture said first physical register number and retam said first physical register number as conespondmg to said first logical register responsive to said mdication that said mstruction operation is retirmg, wherem said map unit is configured to add said second physical register number to said free list

Inventors: WITT DAVID B, WITT, DAVID, B.
Applicants: ADVANCED MICRO DEVICES INC, ADVANCED MICRO DEVICES, INC.
Application year: 1999
Main classification: G06F9
IPC codes: G06F9