DEPOSITION OF OXIDE LAYER ON THE GATE

Abstract: An oxide layer is deposited to a thickness of about 100-300 ANGSTROM over a gate and active regions of a semiconductor device prior to the step of implanting the active regions. The deposition is carried out at a temperature between 750-900 DEG C, which is sufficiently high to eliminate damage caused by etching of the gate pattern. The formation of the gate bird's beak is suppressed, because silicon in the gate is not consumed during the deposition of the oxide layer.

Description: DEPOSITION OF OXIDE LAYER ON THE GATE Banre oTTNT-) OF HE T VFNTTO 1. Field of the Invention The invention relates generally to a method of providing an oxide layer to protect a gate of the semiconductor device during implantation of the active regions, and more particularly to a method of depositing the oxide layer to prevent undesired oxidation of the gate. 2. Description of the Related Art Figures 1A-1C illustrate a conventional method of protecting the gate of the semiconductor device with an oxide layer during implantation of the active regions. The gate illustrated in Figures 1A-1C is of a stacked type and includes a first polysilicon gate or floating gate 21 and a second polysilicon gate or control gate 22. The first gate 21 is separated from a semiconductor substrate 10 by a first gate oxide layer 11 and from the second gate by a second gate oxide layer 12. The gate oxide layers 11, 12 typically have a thickness of about 100 A. The first and second gates 21, 22 are patterned on a semiconductor substrate 10 by a conventional process that includes the steps of depositing photoresist, exposing the photoresist through a mask containing the desired gate pattern, developing the photoresist, etching/ and removing the developed photoresist (Figure 1A) . The semiconductor device then undergoes heating in an oxygen atmosphere at a temperature range of 800-1200 QC . The heating achieves two goals. First, a silicon oxide (Si0 2 ) layer 30 is thermally grown on the top and sides of the gate to protect the gate against implantation damage. Second, etching damage is eliminated. For example, electron traps that are undesirably formed in the gate oxides to cause shifts in the threshold voltages are annealed out. The resulting structure after the heating step is illustrated in Figure IB. Figure 1C illustrates the next step. In Figure 1C, ions are implanted into the active regions 23, 24 or are used to form the active regions 23, 24. The oxide layer 30 protects the top and sides of the gate against implantation damage during this step. In the above-described conventional process, a gate bird's beak is formed at the edges of the polysilicon gates 21, 22 during the heating step. The effect of the gate bird's beak is illustrated in Figures IB and 1C as rounded edges of the polysilicon gates 21, 22. The gate bird's beak is formed because some of the silicon in the polysilicon gates 21, 22 is consumed by reaction with oxygen in the atmosphere in forming the thermally grown oxide layer 30. The gate bird's beak is disadvantageous because it shortens the effective channel length of the gate. STTMMARY OF TTTF. T VFNTTOTNT An object of this invention is to provide an oxide layer to protect the sides and top of a gate of a semiconductor device during implantation of active regions of the semiconductor device without forming a gate bird's beak at the edges of the gate . The above and other objects of the invention are accomplished by depositing an oxide layer of a thickness of approximately 100-300 A on top and sides of a gate and active regions of a semiconductor device prior to the step of implanting the active regions. Preferably, the deposition is carried out by low pressure chemical vapor deposition (LPCVD) at a temperature between 750-900 QC, which is high enough to eliminate any damage caused by etching of the gate pattern. The deposited oxide layer is preferably a layer of Si0 2 but may be a layer of tetraethyl orthosilicate (TEOS) . With the invention, the formation of the gate bird's beak is suppressed, because LPCVD is carried out too rapidly for thermal growth to occur. Another advantage of the invention is that a consistent conformal layer of oxide can be formed by depositing the oxide layer above the gate and the active regions. By comparison, a thermally grown oxide layer is less conformal than a deposited oxide layer . Additional objects, features and advantages of the invention will be set forth in the description of preferred embodiments which follows. RRTFF D-qO T TO OF THF, nRAWTNflfi The invention is described in detail herein with reference to the drawings in which: Figures 1A-1C illustrate a conventional process for implanting active regions of a semiconductor device; and Figures 2A-2C illustrate a process of implanting active regions of a semiconductor device in accordance with the invention. The accompanying drawings, which are incorporated in and constitute a part of the specification, illustrate presently preferred exemplary embodiments of the invention, and, together with the general description given above and the detailed description of the preferred embodiments given below, serve to explain the principles of the invention. ΠFTΆTT.FΠ PFSO TPTTON OF TTF P FFF RFΠ FMPIOΓ)T F T Figures 2A-2C illustrate a method of providing an oxide layer to protect the gate of the semiconductor device during implantation of the active regions or during formation of the active regions in accordance with the invention. The gate illustrated in Figures 2A-2C is of a stacked type and includes a first polysilicon gate or floating gate 21 and a second polysilicon gate or control gate 22. The first gate 21 is separated from a semiconductor substrate 10 by a first gate oxide layer 11 and from the second gate by a second gate oxide layer 12. The gate oxide layers 11, 12 typically have a thickness of about 100 A. The first and second gates 21, 22 are patterned on a semiconductor substrate 10 by a conventional process that includes the steps of depositing photoresist, exposing the photoresist through a mask containing the desired gate pattern, developing the photoresist, etching, and removing the developed photoresist (Figure 2A) . Next, an oxide layer 31 is deposited on the structure illustrated in Figure 2A to a thickness of about 100-300 A. The deposition is carried out at a high temperature between 750-900 πc, preferably between 800-850 FJC . The temperature range of 750-900 QC is sufficiently high to eliminate any damage caused by etching of the gate pattern. The deposition of the oxide layer 31 is carried out by chemical vapor deposition (CVD) , preferably low-pressure chemical vapor deposition (LPCVD) . The oxide layer 31 is preferably a layer of Si0 2 , but may be a layer of TEOS . By depositing the oxide, several advantages are attained. First, thermal growth is suppressed because the rate of LPCVD is much faster than thermal growth and the gate is not exposed to the atmosphere for a time period that is sufficiently long for thermal growth. Consequently, the formation of the gate bird's beak is prevented and the polysilicon gates 21, 22 retain their etched profile as illustrated in Figure 2B . Second, a more conformal layer is obtained. Figure 2C illustrates the next step. In Figure 2C, ions are implanted into the active regions 23, 24 or are used to form the active regions 23, 24. The oxide layer 30 protects the top and sides of the gate against implantation damage during this step. While particular embodiments according to the invention have been illustrated and described above, it will be clear that the invention can take a variety of forms and embodiments within the scope of the appended claims.

Claims: WE CT.ATM : 1. A method of protecting a gate of a semiconductor device during implantation of active regions of the semiconductor device, said method comprising the steps of: forming a gate on a substrate of the semiconductor device; depositing an oxide layer on the gate and the active regions; and implanting the active regions through the oxide layer. 2. The method as recited in claim 1, wherein the step of forming the gate includes the step of etching. 3. The method as recited in claim 2, wherein the step of etching includes the step of etching a stacked gate including first and second polysilicon gates. 4. The method as recited in claim 2, wherein the step of depositing includes the step of depositing by chemical vapor deposition a conformal layer of oxide . 5. The method as recited in claim 2, wherein the step of depositing includes the step of depositing by chemical vapor deposition at a temperature between 750-900 [C. 6. The method as recited in claim 2 , wherein the step of depositing includes the step of depositing by chemical vapor deposition at a temperature between 800-850 [ C . 7. The method as recited in claim 2 , wherein the step of depositing includes the step of depositing by low-pressure chemical vapor deposition at a temperature between 800-850 QC. 8. The method as recited in claim 7, wherein the step of depositing includes the step of depositing the oxide layer to a thickness of about 100-300 A. 9. The method as recited in claim 8, wherein the step of_ depositing includes the step of depositing a layer of Si0 2 . 10. The method as recited in claim 8, wherein the step of depositing includes the step of depositing a layer of TEOS . 11. A method of forming an oxide layer on a gate and active regions of a semiconductor device prior to the step of implanting the active regions to protect against implantation damage during the step of implanting, said method comprising the step of depositing an oxide layer on the gate and the active regions . 12. The method as recited in claim 11, wherein the step of depositing includes the step of depositing a conformal layer of oxide on top and sides of the gate . 13. The method as recited in claim 12, wherein the step of depositing includes the step of depositing by chemical vapor deposition at a temperature between 750-900 []C. 14. The method as recited in claim 12, wherein the step of depositing includes the step of depositing by chemical vapor deposition at a temperature between 800-850 QC . 15. The method as recited in claim 12, wherein the step of depositing includes the step of depositing by low-pressure chemical vapor deposition at a temperature between 800-850 QC . 16. The method as recited in claim 12, wherein the step of depositing includes the step of depositing the conformal oxide layer to a thickness of about 100-300 A. 17. The method as recited in claim 16, wherein the step of depositing includes the step of depositing a layer of Si0 2 . 18. The method as recited in claim 16, wherein the step of depositing includes the step of depositing a layer of TEOS. 19. A method of preventing thermal oxidation of a gate region of a semiconductor device comprising: (a) positioning the device in a chemical vapor deposition apparatus ; and (b) depositing a conformal layer of oxide over said gate region by chemical vapor deposition at a temperature between 750-900 DC 20. The method as recited in claim 19, wherein the step of depositing includes the step of depositing at a temperature between 800-850 QC.

Inventors: ISHIGAKI TORU, ISHIGAKI, TORU
Applicants: ADVANCED MICRO DEVICES INC, FUJITSU AMD SEMICONDUCTOR LIMI, FUJITSU LTD, ADVANCED MICRO DEVICES, INC., FUJITSU AMD SEMICONDUCTOR LIMITED (FASL), FUJITSU LIMITED
Application year: 1999
Main classification: H01L21
IPC codes: H01L21, H01L27, H01L29