Digital phase locked loop capable of suppressing jitter

Abstract: A digital phase locked loop keeps an output signal exactly in phase and frequency with a reference signal. An oscillator has a plurality of delay elements which are connected to one another in a loop to produce the output signal. Each of the delay elements has a delay which is controlled by one of digital control signal sets supplied from a controller. A total delay of the delay elements decides a frequency of the output signal. A phase comparator is connected to the oscillator to compare the output signal with the reference signal in phase and frequency to produce an error signal. A controller is connected between the phase comparator and the oscillator to produce the digital control signal sets in response to the error signal.

Description: This invention relates to a digital phase locked loop which keeps an output signal exactly in phase and frequency with a reference signal, particularly, relates to a digital phase locked loop which is used for an LSI, such as an ASIC (application specific integrated circuit). A conventional digital phase locked loop comprises a phase comparator which compares phase and frequency of a feedback signal with those of an reference signal supplied from an outer circuit. The phase comparator produces an error signal which is representative of frequency difference between the feedback signal and the reference signal. A low pass filter is connected to the phase comparator and filters the error signal to produce an analog control signal. A voltage controlled oscillator is connected to the low pass filter and the phase comparator and produces an output signal having a frequency which depends on the analog control signal. The output signal is supplied to, for example, an inner circuit of an LSI and to the phase comparator as the feedback signal. The voltage controlled oscillator has a plurality of delay elements which are connected to one another in a ring so as to form a ring oscillator. Each of delay elements has a delay which is changed by the analog control signal. The total delay of the delay elements decides the frequency of the output signal. The conventional digital phase locked loop has a defect that the output signal is greatly influenced by noise added to the analog control signal. The noise brings jitters on the output signal. In addition, the conventional digital phase locked loop has a large size because it needs the low pass filter. Another conventional digital phase locked loop comprises a phase comparator which compares phase and frequency of a feedback signal with those of a reference signal supplied from an outer circuit. The phase comparator produces an up/down signal for increasing/decreasing the frequency of the feedback signal. A control circuit is connected to the phase comparator and produces the digital control signal in response to the up/down signal. An oscillator is connected to the control circuit and the phase comparator and produces an output signal. which has a frequency controlled by the digital control signal. The output signal is supplied to an inner circuit of an LSI and to the phase comparator as the feedback signal. The oscillator has a plurality of delay elements which are connected to one another. Each of the delay elements has a fixed delay. The delay elements are selectively activated by the digital control signal. Activated delay elements form a ring oscillator. The total delay of the activated delay elements decides the frequency of the output signal. The conventional digital phase locked loop has a fault that the frequency of the output signal is discontinuously changed by the digital control signal. This increases jitters added on the output signal. Moreover, the conventional digital phase locked loop has another fault that it is necessary to control a timing of activation/inactivation of the delay elements. In addition, the conventional digital phase locked loop uses large electricity. US-A-5687202 discloses a digital phase locked loop according to the preamble of Claim 1 including a controller and a ring oscillator. The controller produces a five bit error count in response to up/down error pulses from a phase comparator. The ring oscillator comprises a path gate and a plurality of multiplexers which are controlled by a plurality of digital control signals. US-A-5438300 discloses a digital frequency multiplier comprising a ring oscillator having a fine tuning element and a plurality of delay elements. EP-0 639 003 A1 describes a digitally adjustable delay line having a delay controlled by a control signal set. It is therefore an object of this invention to provide a digital phase locked loop which is capable of suppressing jitters on an output signal. It is another object of this invention to provide a digital phase locked loop which has a small size and uses small electricity. It is still another object of this invention to provide a digital phase locked loop that it is easy to control. These objects are achieved by a digital phase locked loop as defined in claim 1; the dependent claims are related to further developments of the invention. On describing the gist of this invention, it is possible to understand that a digital phase locked loop keeps an output . signal exactly in phase and frequency with a reference signal. According to the gist of this invention, the digital phase locked loop comprises a phase comparator which compares a feedback signal with the reference signal in phase and frequency to produce an error signal representative of frequency difference between the feedback signal and the reference signal. A controller is connected to the phase comparator to produce a plurality of digital control signal sets in response to the error signal. An oscillator has a plurality of delay elements which are connected to the controller and connected to one another in a loop. Each of the delay elements has a delay which is controlled by one of the digital control signal sets. The oscillator produces the output signal which has a frequency decided by a total delay of the delay elements. A feedback line is connected between the oscillator and the phase comparator to feed back the output signal to the phase comparator as the feedback signal. Fig. 1 is a block diagram of a conventional digital phase locked loop; Fig. 2 is a circuit diagram of a voltage controlled oscillator used in the digital phase locked loop of Fig. 1; Fig. 3 is a graph for describing relations between voltage of an analog control signal and a frequency of output signal in the digital phase locked loop of Fig. 1; Fig. 4 is a block diagram of another conventional digital phase locked loop; Fig. 5 is a circuit diagram of a delay element used in the digital phase locked loop of Fig. 4; Fig. 6 is a graph for describing a relation between the number of activated delay elements and a frequency of an output signal in the phase locked loop of Fig. 4; Fig. 7 is a block diagram of a digital phase locked loop according to a preferred embodiment of this invention; Fig. 8A through 8F are state charts for describing an operation of a delay value storing section used in the digital phase locked loop of Fig. 7; Fig. 9 is a circuit diagram of a delay element used in the digital phase locked loop of Fig. 7; Figs. 10A and 10B are truth tables for describing operations of delay elements of Fig. 9; Fig. 11 is a block diagram for describing a connection between a control digital generating section and delay elements in the digital phase locked loop of Fig. 7; Fig. 12 is a circuit diagram of another delay element used in the digital phase locked loop of Fig. 7; Fig. 13 is a block diagram of a oscillator used in the digital phase locked loop of Fig. 7; Fig. 14 is a block diagram of another oscillator used in the digital phase locked loop of Fig. 7; and Fig. 15 is a block diagram for describing another connection between the control digital generating section and the delay elements in the digital phase locked loop of Fig. 7. Referring to Figs. 1 through 3, description will be at first directed to a conventional digital phase locked loop for a better understanding of this invention. In Fig. 1, a conventional digital phase locked loop comprises a phase comparator 11 which receives a feedback signal and a reference signal supplied from an outer circuit (not shown) . The phase comparator 11 compares the feedback signal with the reference signal to produce an error signal representative of frequency difference between the feedback signal and the reference signal. A low pass filter 12 is connected to the phase comparator 11 and filters the error signal to produce the analog control signal. A voltage controlled oscillator 13 is connected to the low pass filter 12 and the phase comparator 11 and produces an output signal which has a frequency decided by the analog control signal. The output signal is supplied to an LSI (not shown), such as an ASIC, and to the phase comparator 11 as the feedback signal. In this structure, the output signal is controlled so as to reduce the frequency difference. In Fig. 2, the voltage controlled oscillator 13 has a P type transistor 21, an N type transistor 22, and a plurality of delay elements 23. Each of the delay element 23 has a P type transistor 24, an inverter 25, and an N type transistor 26. The P type transistor 21 has a source supplied with source voltage VDD, a drain, and a gate connected to the drain. The N type transistor 22 has a source connected to the ground, a drain connected to the drain of the P type transistor 21, and a gate connected to the low pass filter 12 (see Fig. 1). The P type transistor 21 and the N type transistor 22 produce an additional control signal on the drain of the P type transistor 21. In each of the delay elements 23, the P type transistor 24 has a source supplied with the source voltage VDD, a drain, and a gate connected to the drain of the P type transistor 21. The inverter 25 has a first voltage supplying terminal connected to the drain of the P type transistor 24, a second voltage supplying terminal, an input terminal connected to the preceding stage of the delay elements 23, and the output terminal connected to the following stage of the delay elements 23. Namely, the inverters 25 are connected to one another in a loop. The output signal of the voltage controlled oscillator 13 is led out from a connection between a first stage and a second stage of the delay elements 23. The N type transistor 26 has a source connected to the ground, a drain connected to the second voltage supplying terminal, and a gate connected to the low pass filter 12. Therefore, the delay elements 23 form a ring oscillator. If the analog control signal becomes large in voltage, the P type transistor 21 and the N type transistor 22 make the additional control signal small in voltage. Then, currents flowing through the delay elements 23 from the source voltage VDD to the ground increase. The increase of the currents makes delay of the delay elements 23 small. Therefore, the frequency of the output signal becomes large. If the analog control signal becomes small in voltage, the additional control signal becomes large in voltage. Then, the currents decrease and the delay becomes large. Therefore, the frequency of the output signal becomes small. The digital phase locked loop has faults as follows. The delay stages 23 have a common delay. In other words, the delay of each delay stage 23 can not be individually set. This is because, the P type transistors 24 receive the additional control signal at the gates in common and the N type transistors 26 receive the analog control signal at the gates in common. Moreover, a block size of the digital phase locked loop is large. This is because the digital phase locked loop uses the low pass filter 13 to produce the analog control signal. If the source voltage VDD becomes low, noises included in the analog control signal make jitters added on the output signal large. Fig. 3 shows three frequency characteristics of three digital phase locked loops which are the type as shown in Fig. 1. In Fig. 3, a vertical axis indicates frequency of the output signals while a horizontal axis indicates voltage of the analog control signals. In a lower voltage range 31, each of the frequencies is greatly changed by change of each of the analog control signals. In a higher voltage range 32, the frequencies are not changed greatly by change of the analog control signals. It is easily understood from Fig. 3, that the digital phase locked loop normally operates when the voltage is within the lower voltage range 31. However, in this case, the output signal is greatly influenced by the noises added on the analog control signal as mentioned above. On the other hand, the output signal is not greatly influenced by the noises added on the analog control signal when the voltage is within the large voltage range 32. However, the digital phase locked loop does not normally operate in this case. This is because devices included in the digital phase locked loop are of uneven quality. Referring to Figs. 4 through 6, description will be made about another conventional digital phase locked loop. In Fig. 4, the digital phase locked loop comprises a phase comparator 41 which compares a feedback signal with a reference signal supplied from an outer circuit (not shown) in phase and frequency to produce an error signal. The error signal is an up/down signal for increasing/decreasing the frequency of the feedback signal. In other words, the up/down signal represents that the frequency of feedback signal is lower/higher than that of the reference signal. A delay control circuit 42 is connected to the frequency comparator 41 and has an up-and-down counter 43 and a stage number controller 44. The up-and-down counter 43 produces counting signals C1 through Ch (h: natural number) in response to the error signal. The counting signals are representative of a counting value as a whole. The stage number controller 44 receives the counting signals C1-Ch from the up-and-down counter 43 to produce activating signals S1 through Sg (g: natural number). An oscillator 45 is connected to the delay control circuit 42 and the phase comparator 41 to produce an output signal in response to the activating signals S1 - Sg. The oscillator 45 includes a plurality of delay elements 46-1 through 46-g and a delay circuit 47 to form a ring oscillator. The delay elements 46-1 through 46-g are individually activated by the activating signals S1 through Sg. The number of the delay elements 46 activated by the activating signal decides delay in the oscillator 45 and decides the frequency of the output signal. The output signal supplied to an inner circuit of an LSI (not shown) and the phase comparator 41 as the reference signal. Each of the delay elements 46 is formed as shown in Fig.5. Namely, each of the delay elements 46 comprises first and second inverters 51 and 52 and first and second transfer gates 53 and 54. The first inverter 51 has a first input terminal connected to the preceding delay element 46 and has a first output terminal connected to the following delay element 46. The second inverter S2 has a second input terminal connected to the following delay element 46 and has a second output terminal connected to the preceding delay element 46 through the second transfer gate 54. The first transfer gate 53 is connected between the first output terminal and the second input terminal. The activating signals are classified into two types. A first type is for deciding the last stage of activated delay elements 46 and the second type is for deciding a middle stage of the activated delay elements 46. When the delay element 46 receives the first type of the activating signal, both of the first and the second transfer gates 53 and 54 turn on. When the delay element receives the second type of the activating signal, the first transfer gate 53 turns off and the second transfer gate 54 turns on. Returning to Fig. 4, the delay element 46-1 is connected to the delay circuit 47 instead of the preceding delay element 46. The delay circuit 47 comprises three or more inverters, which are connected to one another in serial. The number of the inverters is an odd number. A transfer gate is connected to the inverters to form a loop together with them. The transfer gate turns on when the activating signal S1 is not supplied to the delay element 46-1. The output signal of the oscillator 45 is led out from an input terminal of the inverter connected to the delay element 46-1. The delay circuit 47 decides a maximum frequency of the output signal. The frequency of the output signal depends on the number of the delay elements 46 activated by the activating signals. Namely, the frequency depends on the total delay of the delay elements 46 activated by the activating signals. When the delay elements 46 are not activated by the activating signals, the frequency is the maximum frequency. When all of the delay elements 46 are activated by the activating signals, the frequency is a minimum frequency. The frequency against the number of the delay elements 46 activated by the activating signal is shown in Fig. 6. As shown in Fig. 6, the frequency takes discontinuous values. Each frequency step is dependent on a delay of each delay element 46. The delay is equal to or larger than the total delay of the first and the second inverters 51 and 52 and the first and the second transfer gates 53 and 54. The digital phase locked loop has faults as follows. In the digital phase locked loop, it is difficult to make the output signal correspond to the reference signal and it is easy to bring jitters on the output signal. This is because the number of the activated delay elements discontinuously changes the frequency of the output signal. Moreover, it is necessary to control timing of activation or inactivation of the delay elements 46. If the timing is not controlled, pulse width of the output signal is changed and the digital phase locked loop malfunctions. In addition, the digital phase locked loop uses more electricity than that as illustrated in Fig. 1. Because the digital phase locked loop has the many delay elements. Referring to Figs. 7 through 11, the description will proceed to a digital phase locked loop according to a preferred embodiment of this invention. In Fig. 7, a digital phase locked loop comprises a phase comparator 71 which compares a feedback signal with a reference signal supplied from an outer circuit (not shown) in phase and frequency to produce an error signal. The error signal is an up/down signal which is for increasing/decreasing the frequency of the feedback signal. In other words, the up/down signal represents that the frequency of feedback signal is lower/higher than that of the reference signal. A delay control circuit 72 is connected to the phase comparator 71 to produce digital control signal sets in response to the error signal. The digital control signal sets include digital control signals S1 through Sn. The delay control circuit 72 includes a delay value storing section 73 and a control signal generating section 74. The delay value storing section 73 is connected to the phase comparator 71 and the control signal generator section 74. The delay value storing section 73 stores a delay value which is representative of a total value mentioned later and which is changed by the error signal. The delay value storing section 73 produces a delay value signal which includes a plurality of data signals D1 through Dk (k: natural number) to represent the delay value. The control signal generating section 74 receives the delay value signal to produce the digital control signal sets. An oscillator 75 is connected to the delay control circuit 72 and has a plurality of delay elements 76-1 thorough 76-m (m: natural number). The delay elements 76 are connected to one another in a loop to form a ring oscillator. In other words, each of the delay elements 76 has an input terminal connected to the preceding delay element 76 and an output terminal connected to the following delay element 76. Each of the delay elements 76 has a delay which is individually controlled by each of the digital control signal sets. The number of active delay elements 76 is unchanged. Accordingly, a timing adjustment for changing the number of delay stages is unnecessary. A total delay of the delay elements 76 is decided by the delay value stored in the delay value storing section 73 and decides a frequency of an output signal. The output signal is led out from the output terminal of the delay element 76-m and supplies to an inner circuit of an LSI (not shown) and to the phase comparator as the feedback signal. In this structure, the frequency of the output signal is controlled so that the frequency of the feedback signal accords with that of the reference signal. Because the delay of each delay element 76 can be finely changed by the digital control signal set, the digital phase locked loop can almost continuously change the frequency of the output signal by the use of a small number of the delay elements. Namely, the digital phase locked loop can make the output signal accord with the reference signal. Referring to Figs. 8A through 8F, an operation of the delay value storing section 73 is described below. It is assumed that the delay value storing section 73 is an eight bits bi-directional shift register. In Fig. 8A, the delay value storing section 73 is in an initial state. In this state, a least significant bit (or a first bit) is "1". The remaining bits are "0". If the delay value storing section 73 in the initial state receives an up signal as the error signal, a second bit becomes "1" and the first bit keeps "1" as shown in Fig. 8B. If the delay value storing section 73 in the state of Fig. 8B receives another up signal, a third bit becomes "1" and the first and the second bits keep "1" as shown in Fig. 8C. If the delay value storing section 73 in the state of Fig. 8C receives a third up signal, a fourth bit becomes "1" and the first through the third bits keep "1" as shown in Fig. 8D. If the delay value storing section 73 in the state of Fig. 8D receives a down signal as the error signal, a fourth bit becomes "0" and the first through the third bits keep "1" as shown in Fig. 8E. If the delay value storing section 73 in the state of Fig. 8E receives another down signal, a third bit becomes "0" and the first and the second bits keep "1" as shown in Fig. 8F. The delay value storing section 73 operates as mentioned above and produces the data signals D1 through D8 which are representative of states of the eight bits. When the feedback signal accords with the reference signal, the error signal is not supplied to the delay value. Accordingly, the data signals D1 through D8 are unchanged in this case and the frequency of the output signal is kept in a state that the feedback signal accords with the reference signal. Referring to Fig. 9, the delay element 76 is described in detail. The delay element 76 comprises a plurality of first P type transistors 91 which have first sources connected to source voltage VDD, first drains, and first gates connected to the delay control circuit 72. A second P type transistor 92 have a second source connected to the first drains, a second drain connected to the output terminal, and a second gate connected to the input terminal. A plurality of first N type transistors 93 have third sources connected to the ground, third drains, third gates connected to the delay control circuit 72. A second N type transistor 94 has a fourth source connected to the third drains, a fourth drain connected to the output terminal, and a fourth gate connected to the input terminal. The first P type transistors 91 and the first N type transistors 93 are used for changing the delay of the delay element 76. The second P type transistor 92 and the second N type transistor 94 are used for deciding logic of the output signal. The digital control signal set supplied from the delay controller 72 includes first and second groups of the digital control signals. If the number of the first P type transistors 91 is "t" (t≧2, t: integer), the first group includes "t" of the digital control signals. Similarly, the second group includes "u" (u≧2, u: integer) of the digital control signals when the number of the first N type transistors 93 is "u". The first P type transistors 91 and the first N type transistors 93 are selectively activated by the digital control signals. The delay changes, for example, as shown in Figs. 10A or 10B. In these cases, four P type transistors and four N type transistors are used for the first P type transistors 91 and the first N type transistors 93, respectively. The digital control signals S1 through S4 which belong to the first group are supplied to the first P type transistors 91 as they are. Moreover, the digital control signals S1 through S4 are inverted and supplied to the first N type transistors 93 as the second group. The first P type transistors 91 and the first N type transistors 93 in the case of Fig. 10A are different from them in the case of Fig. 10B in size. In Fig. 10A, the delay takes one of eight delay times. The delay times include a minimum delay time. If the minimum delay time is a criterion, the remaining delay times are represented by integer multiples of the criterion. Namely, the eight delay times have regular steps among them. The delay can be actually changed in linear between the minimum delay time and a maximum delay time. In Fig. 10B, the delay takes one of eight delay times which include a minimum delay time. If the minimum delay time is a criterion, the remaining delay times are represented by real number multiples of the criterion. Namely, the eight delay times have irregular steps among them. The delay can be actually changed in nonlinear between the minimum delay time and a maximum delay time. If the first P type transistors 91 have a first common size (or electric characteristic) and the first N type transistors 93 have a second common size (or electric characteristic), the delay of the delay element 76 is decided by both of the number of activated first P type transistors 91 and the number of activated first N type transistors 93. Namely, the delay takes one of first predetermined delay times which are decided by the first P type transistors 91 and the first N type transistors 93. Therefore, the delay is finely controlled by selective activation of the first P type and the first N type transistors 91 and 93. The delay can be changed by a minimum step which is a few picoseconds. Because the delay element 76 are controlled by the digital control signal, the output signal is not influenced by noises (having a voltage of some [mV]) added on the digital control signal. Namely, the noises do not bring jitters on the output signal. Moreover, the delay element 76 stably operates even if the source voltage is lower voltage. In Fig. 11, the control signal generating section 74 has a control signal generator 111 and a combining section 112. The control signal generator 111 produces the digital control signals S1 through the Sn in response to the data signals D1 through Dk. The combining section 112 is connected to the control signal generator 111 and the delay elements 76-1 through 76-m to produce the digital control signal sets and to supplies them to the delay elements 76. The combining section 112 divides the digital control signals S1 through S4 into m to supply them to all of the delay elements 76-1 through 76-m. In addition, the combining section 112 supplies the digital control signal S5 through S(m+4) to the delay elements 76-1 through 76-m, respectively. Each of the digital control signal sets is used for the first group of the digital control signals as they are and is inverted to form the second group of the digital control signals in each delay element 76. This inversion may be carried out in the combining section 112. The combining section 112 may selectively divide the digital control signals into m to supply them to all of the delay elements . Moreover, the combining section 112 may selectively supply the digital control signals to selected one of the delay elements 76. Referring to Fig. 12, description will be made about a delay element according to another embodiment of this invention. In Fig. 12, the delay element 120 comprises a third P type transistor 121 which has a fifth source supplied with source voltage VDD, a fifth drain, and a fifth gate connected to the input terminal. A plurality of fourth P type transistors 122 have sixth sources connected to the fifth drain, sixth drains connected to the output terminal, and sixth drains connected to the delay control circuit 72. A third N type transistor having a seventh source connected to the ground, a seventh drain, and a seventh gate connected to the input terminal. A plurality of fourth N type transistors 124 have eighth sources connected to the seventh drain, eighth drains connected to the output terminal, and eighth gates connected to the control circuit 72. The third P type transistor 121 and the third N type transistor 123 are used for deciding logic of the output signal. The fourth P type transistors 122 and the fourth N type transistors 124 are used for changing the delay of the delay element 120. The digital control signal set supplied from the delay controller 72 includes third and fourth groups of the digital control signals. If the number of the fourth P type transistors 122 is "v" (v≧2, v: integer), the third group includes "v" of the digital control signals. Similarly, the fourth group includes "w" (w≧2, w: integer) of the digital control signals when the number of the fourth N type transistors 124 is "w". The fourth P type transistors 122 and the fourth N type transistors 124 are selectively activated by the digital control signals. If the fourth P type transistors 122 have a third common size (or electric characteristic) and the fourth N type transistors 124 have a fourth common size (or electric characteristic), the number of activated fourth P type transistors 122 and the number of activated fourth N type transistors 124 decide the delay of the delay element 120. Namely, the delay takes one of second predetermined delay times which are decided by the fourth P type transistors 122 and the fourth N type transistors 124. Therefore, the delay is finely controlled by selective activation of the fourth P type and the fourth N type transistors 122 and 124. The delay element 120 is used like the delay element 76 shown in Fig. 9. In addition, the delay element 120 is used together with the delay element 76 as illustrated in Figs 13 and 14. In Fig. 13, the oscillator 75 has a first stage of the delay element 120. Each of the remaining stages is the delay element 76. In Fig. 14, the oscillator 75 has first and second stages of the delay elements 76 and the remaining stages of the delay elements 120. It is assumed that the first predetermined delay times have first regular steps and the second predetermined delay times have second regular steps and that each of the first regular steps is smaller than each of the second regular steps. In a case that the delay element 76 is used together with the delay element 120, the control signal generating section 74 decides the delay for the delay element(s) 120 at first to produce the digital control signals. Then, the control signal generating section 74 decides the delay for the delay elements 76. If the delay element 120 is used for rough adjustment of the frequency of the output and the delay element 76 is used for fine adjustment of the frequency, a time for making the feedback signal accord with the reference signal becomes short. When both of the delay element 76 and the delay element 120 are used in the oscillator 75, the delay stages are fewer than that including either of the delay element 76 or the delay element 120. Accordingly, electricity consumption of the oscillator 75 is smaller than the conventional digital phase locked loop shown in Fig. 4. While this invention has thus for been described in conjunction with preferred embodiment thereof, it will readily be possible for those skilled in the art to put this invention into practice in various other manners. For example, the delay value storing section 73 may be a shift register or a up-and-down counter. In addition, the control signal generating section 74 is structured as shown in Fig. 15.

Claims: A digital phase locked loop for keeping an output signal exactly in phase and frequency with a reference signal, said digital phase locked loop including a phase comparator (71) for comparing a feedback signal with the reference signal in phase and frequency to produce an error signal representative of a frequency difference between the feedback signal and the reference signal, a controller (72) connected to said phase comparator (71) for producing a digital control signal in response to the error signal, an oscillator (75) connected to said controller (72) for producing the output signal, said oscillator having a plurality of delay elements (76, 120) which are connected to said controller (72) and connected to one another in a loop, said oscillator producing the output signal having a frequency decided by a total delay of said delay elements, and feedback means connected between said oscillator (75) and said phase comparator (71) for feeding back the output signal to said phase comparator (71) as the feedback signal, characterizedin that said controller (72) produces a plurality of digital control signal sets, each of which includes a plurality of final control signals (S1-Sn), as the digital control signals in response to the error signal, and each of said delay elements having a plurality of transistors (91, 93) controlled by the final control signals belonging to one of the digital control signal sets, respectively, to decide a delay. A digital phase locked loop as claimed in Claim 1, characterized in that the error signal is an up/down signal for increasing/decreasing the frequency, said controller (72) comprising; delay value storing means (73) connected to said phase comparator (71) for storing a delay value which is representative of the total delay and which is changed by the up/down signal to produce a delay value signal, and control signal generating means (74) connected to said delay value storing means for producing the digital control signal sets in response to the delay value signal. A digital phase locked loop as claimed in Claim 2, characterized in that the up/down signal is an up signal or a down signal, said delay value storing means (73) being a bi-directional shift register which shifts the delay value toward a first direction when it receives the up signal and which shifts the delay value toward a second direction opposite to the first direction when it receives the down signal. A digital phase locked loop as claimed in Claim 1, characterized in that said controller (72) supplies the digital control signal sets to said delay elements at the same timing. A digital phase locked loop as claimed in Claim 1, characterized in that said digital control signal sets are first through m-th sets, wherein m is a natural number, said delay elements (76) being first through m-th delay elements which receive the first through the m-th sets, respectively, said controller (72) producing first through n-th preliminary digital control signals, wherein n is a natural number in response to the error signal to make the first through the m-th sets of the first through the n-th preliminary digital control signals. A digital phase locked loop as claimed in Claim 1, characterized in that each of said delay elements (76) has an input terminal connected to the preceding delay element and has an output terminal connected to the following delay element, each of the digital control signal sets includes first and second groups of digital control signals, each of said delay elements comprising a plurality of first P type transistors (91) having first sources supplied with source voltage (VDD), first drains, and first gates connected to said controller to receive the first group, a second P type transistor (92) having a second source connected to said first drains, a second drain connected to said output terminal, and a second gate connected to said input terminal, a plurality of first N type transistor (93) having third sources connected to ground, third drains, and third gates connected to said controller to receive the second group, and a second N type transistor (94) having a fourth source connected to said third drains, a fourth drain connected to said output terminal, and a fourth gate connected to said input terminal. A digital phase locked loop as claimed in Claim 1, characterized in that each of said delay elements (120) has an input terminal connected to the preceding delay element and has an output terminal connected to the following delay element, each of the digital control signal sets including third and fourth groups of digital control signals, each of said delay elements comprising, a fifth P type transistor (122) having a fifth source supplied with source voltage (VDD), a fifth drain, and a fifth gate connected to said input terminal, a plurality of sixth P type transistors (122) having sixth sources connected to said fifth drain, sixth drains connected to said output terminal, and sixth gates connected to said controller to receive the third group, a seventh N type transistor (123) having a seventh source connected to ground, a seventh drain, and a seventh gate connected to said input terminal, and a plurality of eigth N type transistors having eighth sources connected to said seventh drain, eighth drains connected to said output terminal, and eighth gates connected to said controller to receive the fourth group. A digital phase locked loop as claimed in Claim 1, characterized in that , said delay elements includes first and second elements, said first element receiving first and second groups of the digital control signals included in one of the digital control signal sets, said second element receiving third and fourth groups of the digital control signals included in another one of the digital control signal sets, said first element comprising; a first input terminal connected to a first preceding delay element, a first output terminal connected to a first following delay element, a plurality of first P type transistors having first sources supplied with source voltage, first drains, and first gates connected to said controller to receive the first group, a second P type transistor having a second source connected to said first drains, a second drain connected to said first output terminal, and a second gate connected to said first input terminal, a plurality of third N type transistor having third sources connected to ground, third drains, and third gates connected to said controller (72) to receives the second group, and a fourth N type transistor having a fourth source connected to said third drains, a fourth drain connected to said first output terminal, and a fourth gate connected to said first input terminal, said second element comprising; a second input terminal connected to a second preceding delay element, a second output terminal connected to a second following delay element, a fifth P type transistor having a fifth source supplied with source voltage, a fifth drain, and a fifth gate connected to said second input terminal, a plurality of sixth P type transistors having sixth sources connected to said fifth drain, sixth drains connected to said second output terminal, and sixth gates connected to said controller to receive the third group, a seventh N type transistor having a seventh source connected to ground, a seventh drain, and a seventh gate connected to said second input terminal, and a plurality of eighth N type transistors having eighth sources connected to said seventh drain, eighth drains connected to said second output terminal, and eighth gates connected to said controller to receive the fourth group. A digital phase locked loop as claimed in Claim 8, characterized in that , said first element has first steps for changing the delay in response to the first and the second groups, and said second element has second steps different from the first steps for changing the delay in response to the third and the fourth groups.

Inventors: OOTA TETSUYA, YAMAGUCHI MICHIMASA, OOTA, TETSUYA, YAMAGUCHI, MICHIMASA, Oota, Tetsuya c/o NEC IC Microcomp. Systems, Ltd., Yamaguchi, Michimasa c/o NEC IC Micro. Syst. Ltd.
Applicants: NEC ELECTRONICS CORP, NEC ELECTRONICS CORPORATION
Application year: 1999
Main classification: H03L7
IPC codes: H03K5, H03L7