A SUPERVISORY INTEGRATED CIRCUIT WITH DATA STORAGE AND RETRIEVAL OF SYSTEM PARAMETERS

Abstract: A supervisory circuit that includes the functions of monitoring, collating, storing and outputting system parameters implemented on a single, monolithic integrated circuit. The elements of the invention include system paremeter input, non-volatile memory, serial and parallel output, periodic and aperiodic control circuitry and various system power detection circuits. All elements are located on a single, monolithic integrated circuit.

Description: A SUPERVISORY INTEGRATED CIRCUIT WITH DATA STORAGE AND RETRIEVAL OF SYSTEM PARAMETERS BACKGROUND OF THE INVENTION 1. Field of the Invention: This invention relates generally to multi-function integrated circuits and specifically to incorporating the monitoring, collating, recording and outputting of system parameters on a single, monolithic integrated circuit. 2. Description of the Prior Art: The current state of the art describes devices that provide "supervisor}'" functions, that is the monitoring and recording of system parameters as "black boxes." Perhaps the most complex of such devices are those found in commercial aircraft, typically referred to as flight data recorders. These aircraft recorders have considerable size and weight to meet functional as well as environmental and survivability considerations. Other types of system parameter recording schemes found for example in automobiles and other sophisticated electronic devices rely on a CPU which periodically or when triggered by an unexpected event, writes data in non-volatile memory. Typically these schemes require several electronic components mounted on a circuit board. For example, in the periodic case a watchdog timer may be coupled to a CPU which in turn is coupled to non-volatile memory. In the aperiodic example, a supply voltage detection device is coupled a CPU which then stores system parameters in non-volatile memory. In the quest for smaller, more compact electronic devices, there exists a need for a supervisory circuit that is capable of monitoring, collating, recording and outputting system 2 parameters that is implemented on a single, integrated circuit. SUMMARY OF THE INVENTION It is an object of the present invention to provide a supervisory circuit with data storage and retrieval of system parameters on one monolithic integrated circuit. It is another object of the present invention to combine the functions of input/output, memory storage, power detection and control circuitry on one monolithic integrated circuit. It is another object of the present invention to incorporate periodic and aperiodic control circuitry on a single device for the purpose of storing or outputting system parameters. In accordance with one embodiment of the present invention a supervisory circuit with data storage and retrieval of system parameters is comprised of an array of memory cells, at least one data input, at least one output, a power detection circuit and a control circuit. In accordance with another embodiment of the present invention, an input buffer and output buffer are included as additional elements to those listed in the preceding paragraph. The foregoing and other objects, features, and advantages of the invention will be apparent from the following, more particular, description of the preferred embodiments of the invention, as illustrated in the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS Figure 1 is a block diagram of the present invention. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT Referring to figure 1. a supervisory circuit with data storage and retrieval of system parameters 1 is shown. The purpose of the supervisory circuit 1 is to monitor various system parameters and system power, to record those parameters in electronic memory and to output the recorded parameters upon command. The supervisory circuit 1 is typically utilized as a component in electronic devices or as part of a larger system where the storage and retrieval of system parameters is desirable. The supervisory circuit 1 is comprised of an array of memory cells 10, at least one data input 20, at least one output 30, a system power detection circuit 40 and a control circuit 50. The supervisory circuit 1 may also include an input buffer 60 and an output buffer 70. The present invention 10 is implemented as a single, monolithic integrated circuit. The array of memory cells 10 is typically comprised of non-volatile memory for the purpose of preserving the data stored in the array 10 should power to the system be lost. However, the array of memory cells 10 may also be comprised of volatile memory. The array of memory cells 10 is comprised of a plurality of rows and columns, the exact quantity of which is variable and determined by the specific application of the supervisory circuit 1. The array of memory cells 10 may be structured in accordance with a number of different architectures available for non-volatile memory. One such memory architecture is a first-in-first-out (FIFO) architecture which is well known to those skilled in the art. Another memory structure is last-in-first-out (LIFO), which is also well known to those skilled in the art. Furthermore, the array of memory cells 10 may be implemented with a variety of technologies. Among these technologies are electrically erasable program read only memory (EEPROM) and FLASH memory. However, the invention is not limited to either the FIFO or LIFO architecture 4 or the EEPROM and FLASH memory technologies. Those skilled in the art will recognized that there are a variety of different memory sizes, architectures, and technologies available to effectively achieve the same result as found in this device. The supervisory circuit 10 is capable of both analog and digital inputs. The analog inputs 22 are parameters transmitted by system components to the supervisory circuit 10 in analog format. The analog inputs 22 are typically connected to analog-to-digital (A/D) converters 24 for the purpose of converting the analog input to digital data for storage within the array of memory cells 10. The A/D converters 24 may be simple comparators or more sophisticated devices known to those skilled in the art. The digital inputs 26 may be in discrete format or may include all or part of a data bus. The purpose of the input buffer 60 is to stabilize the data inputs 20 prior to storage in the array of memory cells 10. The control circuit 50 will provide a control signal to latch data into the input buffer 60. Once the data is latched into the input buffer 60, it is available to be stored within the array of memory cells 10. The control signal to write the data into the memory cells 10 is generated by the control circuit 50. In other embodiments the supervisory circuit 1 may be implemented without the input buffer 60. In this case, the input data will proceed directly into the array of memory cells 10 upon command from the control circuit 50. The purpose of the output buffer 70 is two fold. First, in a parallel output embodiment, the output buffer 70 will latch the data read from the array of memory cells 10 and will make the data available at the output 30 to requesting devices external to the supervisory circuit 1. Second, in a serial output embodiment, the output buffer 70 will not only latch the data read from the array of memory cells 10, but will convert the data from parallel to serial format for output 30. Thus, in the second instance, the output buffer 70 acts as a parallel to serial converter, which is well known to those skilled in the art. The power detection circuit 40 monitors system power at input 42 for anomalous conditions. Input 42 may coincide with Vcc power for the supervisory circuit 1 or include other power buses. The power detection circuit 40 is comprised of a system power input and any combination of the following power monitors. The brown out detection (BOD) circuit 43 monitors power for gradual decay in voltage, such as in the case of a discharging battery. The low voltage detection (LVD) circuit 44 monitors system power for low voltage spikes, as can be found in a malfunctioning power supply or voltage regulator. The over voltage detection (OVD) circuit 45 monitors system power for high voltage conditions as also found in malfunctioning power supplies or voltage regulators. The power on reset (POR) circuit 46 monitors system power for reset conditions. Each of these circuits is capable of setting one or more bits when a system power anomaly occurs. That bit(s) will be transmitted to the control circuit 50 which will trigger the storage of the data at the input buffer 60 as well as the type of system power anomaly. Those skilled in the art will recognized that the supervisory circuit may have a plurality of embodiments which includes any combination of the system power detection circuits described above, various quantities of each of the system power sources to monitor a possible variety of power sources or other system power detection circuits not described here but accomplish substantially the same result. The control circuit 50 transmits signals to the input buffer 60, the array of memory cells 10 and the output buffer 70 to either input or output data. The control circuit 50 is comprised of at least one input 52, a periodic controller 54, and an aperiodic controller 56. Furthermore, the 6 control circuit 50 receives command signals from the power detection circuit 40 to store data within the array of memory cells 10. The supervisory circuit 1 may be implemented as a stand alone device, in which case the control signals are generated internally, or may be coupled to other system devices capable of sending commands to the control circuit 50. The input 52 may be either one or more discretes or connected to a data bus or other means to which at least one other system device is coupled. Data at the input 52 will be transmitted to the aperiodic controller 56. Upon command by an external source or system device the aperiodic controller 56 will execute a control sequence to send commands to the input buffer 60, the array of memory cells 10, and the output buffer 70 to either store or output system parameters. The periodic controller 54 will execute a control sequence at a predetermined time interval to send commands to the input buffer 60, the array of memory cells 10, and the output buffer 70 to either store or output system parameters. The periodic controller 54 may have either a hard coded control sequence and time interval or may be programmable by devices external to the supervisory circuit 1 via the control circuit input 52. Thus, in one embodiment, the periodic controller 54 functions similar to what is commonly referred to by those skilled in the art as a watchdog timer. Although the invention has been particularly shown and described with reference to a preferred embodiment thereof, it will be understood by those skilled in the art that changes in form and detail may be made therein without departing from the spirit and scope of the invention.

Claims: 7 CLAIMS 1. A supervisory circuit with data storage and retrieval of system parameters comprising: an array of memory cells; at least one data input coupled to the array of memory cells; at least one output coupled to the array of memory cells; a power detection circuit coupled to the array of memory cells; and a control circuit coupled to the array of memory cells and to the system power detection circuit; wherein the supervisory circuit is implemented on a single, monolithic integrated circuit. 2. The supervisory circuit in accordance with Claim 1 wherein the supervisory circuit further comprises: an input buffer coupled to the at least one data input and the array of memory cells; and an output buffer coupled to the array of memory cells and the at least one output. 3. The supervisory circuit in accordance with Claim 1 wherein the array of memory cells are non-volatile memory. 4. The supervisory circuit in accordance with Claim 1 wherein the array of memory cells are volatile memory. 5. The supervisory circuit in accordance with Claim 3 wherein the array of memory cells are a first-in-first-out (FIFO) memory. 6. The supervisory circuit in accordance with Claim 3 wherein the array of memory cells are a Last-in-first-out (LIFO) memory. 7. The supervisory circuit in accordance with Claim 3 wherein the array of memory cells are electrically erasable programmable read only memory (EEPROM). 8. The supervisory circuit in accordance with Claim 3 wherein the array of memory cells are FLASH memory. 9. The supervisory circuit in accordance with Claim 1 wherein the at least one data input is comprised of at least one analog input. 10. The supervisory circuit in accordance with Claim 1 wherein the at least one data input is a digital input. 11. The supervisory circuit in accordance with Claim 7 wherein each of the at least one analog input is coupled to an analog to digital converter. 12. The supervisory circuit in accordance with Claim 1 1 wherein the analog to digital converter comprises a comparator. 13. The supervisory circuit in accordance with Claim 1 wherein the at least one output transfers data from the array of memory cells serially. 14. The supervisory circuit in accordance with Claim 1 wherein the at least one output transfers data from the array of memory cells in parallel. 15. The supervisory circuit in accordance with Claim 1 wherein the power detection circuit comprises a system power input and at least one power monitor circuit. 16. The supervisory circuit in accordance with Claim 15 wherein the at least one power monitor circuit comprises a brown out detection (BOD) circuit coupled to the system power input. 17. The supervisory circuit in accordance with Claim 15 wherein the at least one power monitor circuit comprises a low voltage detection (LVD) circuit coupled to the system power input. 18. The supervisory circuit in accordance with Claim 15 wherein the at least one power monitor circuit comprises an over voltage detection (OVD) circuit coupled to the system power input. 19. The supervisory circuit in accordance with Claim 15 wherein the at least one power monitor 10 circuit comprises a power on reset (POR) circuit coupled to the system power input. 20. The supervisory circuit in accordance with Claim 1 wherein the control circuit comprises: at least one input; a periodic controller; and an aperiodic controller. 21. The supervisory circuit in accordance with Claim 20 wherein the control circuit receives at least one command from the system power detection circuit to store data within the array of memory cells. 22. The supervisory circuit in accordance with Claim 20 wherein the control circuit receives at least one command from at least one system device coupled to the supervisory circuit. 23. The supervisory circuit with data storage and retrieval of system parameters in accordance with Claim 22 wherein the at least one command is a command to store data within the array of memory cells. 24. The supervisory circuit with data storage and retrieval of system parameters in accordance with Claim 22 wherein the at least one command is a command to output data from the array of memory cells. 1 1 25. The supervisory circuit with data storage and retrieval of system parameters in accordance with Claim 22 wherein the at least one command is a command to program the periodic controller. 26. The supervisory circuit with data storage and retrieval of system parameters in accordance with Claim 20 wherein the periodic controller is a watchdog timer.

Inventors: SUSAK DAVID, SUSAK, DAVID
Applicants: MICROCHIP TECH INC, MICROCHIP TECHNOLOGY INCORPORATED
Application year: 1999
Main classification: G11C5
IPC codes: G11C5