A complementary push-pull CMOS source follower analog video buffer

Abstract: There is disclosed an analog video buffer which utilizes a complementary push-pull CMOS source follower video buffer with a feedback driver. The CMOS source follower provides a low impedance output node with high driving capabilities, high switching speed, and rail-to-rail linearity and the feedback driver isolates the output node from the feedback needed for the design of the video buffer to provide a transient response without ringing or overshoot.

Description: BACKGROUND OF THE INVENTION This invention relates to a video buffer of a sensor array imager and more particularly to an analog video buffer which utilizes a complementary push-pull source follower driver to provide a rail-to-rail linearity, high speed, high gain and low power consumption. A sensor array is an imager for an image input terminal of a digital copier or scanner. Any sensor array has an array of photosensing diodes to convert an image into analog signals. Based on the resolution of digital copiers which are typically in the range of 400 - 600 pixels per inch, a sensor array utilizes one photosensing diode for each pixel. For example, a sensor array can have (600 pixels per inch) x (12 inches) = 7200 diodes to cover all the pixels of a 12 inch line with 600 pixels per inch resolution. Once a sensor array is exposed to an illuminated document, each one of the diodes generates an analog signal based on the amount of the received light. The signal that each diode generates is the information (data) of its respective pixel. Each signal from each diode is sent into a signal processing circuit and subsequently transferred onto a data bus through a buffering stage. The buffering stage requires an analog video buffer to place the analog data onto the bus. For the purpose of simplicity, hereinafter, the "analog video buffer" is referred as "video buffer". A video buffer for a sensor array imager of a digital copier needs to have certain characteristics. It has to have high driving capabilities to provide high switching speed. In a digital copier, due to the high number of photosensing diodes (i.e. 7200 diodes), the data bus has a high capacitance which is the sum of all the capacitances of all the video buffers and other circuits connected to the bus. Thus, the video buffer has to be able to drive the bus. In addition, the video buffer has to have a transient response with no ringing or overshoot to produce a high quality image. The next characteristics of a video buffer is a low power consumption. Since each diode of a sensor array has a video buffer and the number of diodes in a sensor array is large, the cumulative power consumption of the video buffers is high. Therefore, it is critical to design the video buffers to have low power consumption. Finally, a video buffer has to be linear to prevent any signal distortion which affects the quality of the image. Typically, a sensor array imager utilizes a video buffer with a push-pull driver or a source follower driver. Referring to Figure 1, there is shown a prior art video buffer 10 with a push-pull driver 12. The push-pull driver 12 comprises two complementary symmetry metal oxide silicon (CMOS) field effect transistors T 1 and T 2 . Transistor T 1 is a P-channel (PMOS) transistor and transistor T 2 is an N-channel (NMOS) transistor. The source of transistor T 1 is connected to a power supply V DD1 and the source of transistor T 2 is grounded. The drains of both transistors T 1 and T 2 are connected to each other at the output node V OUT1 . The output node V OUT1 is connected to a data bus 20 which is represented by the bus capacitance C 1 . The video buffer 10 further comprises an input stage 15 with two differential input amplifiers 14 and 16. The gate of transistor T 1 is connected to the output terminal of the differential input amplifier 14 and the gate of transistor T 2 is connected to the output terminal of the differential input amplifier 16. In order to properly drive the transistors T 1 and T 2 of the driver 12, the differential input amplifiers 14 and 16 must have matching characteristics to provide compatible signals and therefore must have the same type of MOS transistors as transistors T 1 and T 2 . The non-inverting input terminals (+) of the differential input amplifiers 14 and 16 are connected to each other at node 18 and the inverting input terminals (-) are connected to each other and also to an input voltage V IN1 . In addition, the output node V OUT1 is connected to node 18. The differential input amplifiers 14 and 16 provide input voltages V I1 and V I2 to the transistors T 1 and T 2 respectively. The two signals V I1 and V I2 have the same phase. However, depending on the levels of the V I1 and V I2 , either T 1 or T 2 will take over. Usually, the drain of any MOSFET transistor has a high impedance. Since the output node V OUT1 is connected to both drains of transistors T 1 and T 2 , the output node has a high impedance. The high impedance of the output node provides a high gain which is desirable. However, high impedance in conjunction with the large capacitance C 1 of the bus and other dominant pole frequencies of the video buffer will cause an oscillation. Typically, this oscillation is observed as an overshoot or ringing on the output signal. In order to reduce the oscillation and stabilize the circuit, compensation circuitry needs to be added to the video buffer output which reduces the speed. The video buffer 10 is highly linear. However, its linearity is not rail-to-rail. Referring to Figure 2, there is shown the linearity graph of the video buffer 10 of Figure 1. The horizontal axis represents the input voltage V IN1 and the vertical axis represents the output voltage V OUT1 . Referring to both Figures 1 and 2, V IN1 changes within a range from 0 - 5 volts known as rail-to-rail where levels 0 and 5 volts define the rails of power supply range. In addition, the voltage of the output node V OUT1 follows the input voltage V IN1 . When V IN1 approaches either rail of the power supply range, since the output voltage V OUT1 follows V IN1 , the drain-to-source voltage V DS of either T 2 or T 1 will decrease depending on if V IN1 is close to 0 or 5 volts respectively. If V IN1 decreases to a level below V A , V DS2 also decreases to a level below V A . V A is a voltage at the output node V OUT1 which depends on the size and the characteristics of transistor T 2 . Once V DS2 decreases to a voltage value below the value of V A , V I2 adjusts itself to match V DS2 and transistor T 2 enters into the ohmic (triode) region in which the linearity is distorted. In the same manner, if V IN1 increases to a level above V DD1 - V B , V DS1 decreases to a voltage value below the value of V B . V B is a voltage at the output node V OUT1 which depends on the size and the characteristics of transistor T 1 . Once V DS1 decreases to a voltage value below the value of V B , V I1 adjusts itself to match V DS1 and transistor T 1 enters into the ohmic (triode) region in which the linearity is distorted. Therefore, since the video buffer 10 is linear only between V A and V DD1 - V B , it does not have a full range rail-to-rail (0 - 5 volts) linearity. The advantage of this circuit is its low power consumption. It is well know that CMOS circuits have a low power consumption. Therefore, the video buffer 10 has a lower power consumption as opposed to a source follower video buffer with two NMOS transistors. In summary, the video buffer 10 has a low power consumption, but low speed and limited range of linearity. Since in an imager sensor array, the speed and stability of switching is extremely critical, the video buffer 10 is not a proper buffer for a high speed imager sensor array. Referring to Figure 3, there is shown a video buffer 30 with a source follower driver 32. In Figure 3, an NMOS transistor T 3 is used in a source follower configuration. The drain of transistor T 3 is connected to a power supply V DD2 , its source is connected to the drain of an NMOS transistor T 4 at node V OUT2 and its gate is connected to the output terminal of a differential input amplifier 36. Transistor T 4 , which is used as an active load, has its gate connected to a bias voltage V BIAS and its source grounded. The output node V OUT2 is connected to a data bus 34 which is represented by the bus capacitance C 2 and to the inverting input (-) of the differential input amplifier 36. The non-inverting input terminal (+) of the differential input amplifier 36 is connected to an input voltage V IN2 . The differential input amplifier 36 provides an input voltages V I3 to transistor T 3 . Typically, the source of any transistor is the lowest impedance node of the transistor. Therefore, in the video buffer 30, since the output node V OUT2 is connected to the source of transistor T 3 and to the drain of transistor T 4 , the video buffer 30 has an average impedance. Thus, this video buffer provides a high speed. However, the video buffer 30 has a limited range of linearity. Referring to Figure 4, there is shown a linearity graph of the video buffer 30 of Figure 3. The horizontal axis represents the input voltage V IN2 and the vertical axis represents the output voltage V OUT2 . In Figure 4, if the input voltage is between 0 and V C , transistor T 3 is not completely ON. V C depends on the size and characteristics of the transistor T 4 . Once the input voltage V I3 reaches V C , the output voltage V OUT2 becomes linear and stays substantially linear for the input voltage between V C and V DD2 . Therefore, the video buffer 30 is linear only for the limited range of V C to V DD2 . In addition, this circuit has a high power consumption due to having two NMOS transistors which carry DC current all the time. U.S. patent no 4,371,843 discloses an input differential amplifier stage, which feeds an output stage, having a feedback loop originating at a node in one branch, for controlling a current-source transistor of that stage. The feedback loop is characterized by a direct connection to the gate electrode of a transistor which drives the output stage, while the output at another node, in the other branch of the differential amplifier stage is fed to another transistor which also drives the output stage. U.S. patent no 4,987,381 discloses a closed loop bipolar transistor driver being coupled to an open loop MOSFET output stage. The closed loop driver amplifier operates within a higher voltage range than the open loop MOSFET output amplifier. The closed loop driver stage is capable of driving the MOSFET output stage into saturation and the MOSFET output stage thereby produces a desirable vacuum tube-like sound characterized by warm, even harmonics. Feedback is used to maintain the closed loop driver circuit in a linear operating regime thereby preventing undesirable hard clipping associated with bipolar transistors when they are overdriven. U.S. patent no 5,166,635 discloses a cost-effective, low power and low distortion digital data line driver with the capability to operate from a limited voltage source while maintaining wide output voltage swings. The line driver has the noise immunity attribute of a fully differential input device without all the usual complex CMFB circuitry normally required. The line driver provides a low distortion output with a low output impedance and maintains its impedance value on the same order of magnitude at frequencies up to four times the Nyquist rate. U.S. patent no 5,117,200 discloses a wide bandwidth transconductance amplifier utilizing internal feedback is stabilized over a wide range of output currents. A compensation driver circuit senses the output current in the amplifier and feeds it back through a compensation capacitor. This keeps the bandwidth of the amplifier constant and optimally stabilized over a 16 to 1 range in output current. This compensation scheme eliminates compensation compromises that can limit the useful dynamic range of transconductnce amplifiers while offering a wide bandwidth low distortion transconductance with high output impedance over frequency. Caiulo, G., et al, Video CMOS power buffer with extended linerarity, IEEE Journal of Solid-state Circuits, 1 July 1993, vol 28, no 7, pages 845 to 848 dicloses a CMOS power buffer suitable for video applications, wherein the use of a high-speed push-pull output stage and a highly linear high-speed driver allows good linearity to be maintained even with very high input frequencies. Accordingly, it is an object of this invention to provide an analog video buffer which has high driving capabilities, high switching speed, low power consumption, a transient response with no ringing or overshoot, and rail-to-rail linearity. This object is solved by the analog video buffer as claimed in independent claim 1. Preferred embodiments of this invention are subject matters of dependent claims. In carrying out the above, there is disclosed an analog video buffer which utilizes a driver and an input stage. The driver of the analog video buffer of this invention comprises a CMOS source follower in which an NMOS transistor and a PMOS transistor are connected to each other through their sources at an output node. In accordance with another aspect of this invention, there is disclosed an analog video buffer which utilizes a driver, a feedback driver and an input stage. The driver of the analog video buffer of this invention comprises a CMOS source follower. The feedback means has a feedback node and the input means has a feedback receiving node which are connected to each other. The driver means has an output node which is isolated from the feedback node. BRIEF DESCRIPTION OF THE DRAWINGS Figure 1 shows a prior art video buffer with a push-pull driver; Figure 2 shows a linearity graph of the video buffer of Figure 1; Figure 3 shows a prior art video buffer with a source follower; Figure 4 shows a linearity graph of the video buffer of Figure 3; Figure 5 shows a video buffer of this invention; and Figure 6 shows a linearity graph of the video buffer of Figure 5. DETAILED DESCRIPTION OF THE INVENTION Referring to Figure 5, there is shown a video buffer 40 of this invention. The video buffer 40 comprises a CMOS driver 42, a CMOS feedback driver 44, and an input stage 45. The driver 42 comprises an NMOS transistor T 5 and a PMOS transistor T 6 which are used in a bi-directional push-pull CMOS source follower configuration. Contrary to the common knowledge of connecting the drains of two transistors of a push-pull driver, in this invention, the two sources of two transistors T 5 and T 6 are connected to each other at the output node V OUT3 . The drain of transistor T 5 is connected to a power supply V DD3 and the drain of transistor T 6 is grounded. The output node V OUT3 is connected to a data bus 46 which is represented by the bus capacitance C 3 . The feedback driver 44, which has a similar design to the design of the driver 42, comprises an NMOS transistor T 7 and a PMOS transistor T 8 . Again, the drain of transistor T 7 is connected to the power supply V DD3 and the drain of transistor T 8 is grounded. The sources of both transistors T 7 and T 8 are connected to each other at node 48. T 7 and T 8 can be scaled down to much smaller sizes than T 5 and T 6 , but keep the same aspect ratio. The input stage 45 comprises two differential input amplifiers 50 and 52. The non-inverting input terminals (+) of the differential input amplifiers 50 and 52 are connected to each other and to an input voltage V IN3 and the inverting input terminals (-) are connected to each other at node 54. The gates of transistors T 5 and T 7 are connected to each other and to the output terminal of the differential input amplifier 50 and the gates of transistors T 6 and T 8 are connected to each other and to the output terminal of a differential input amplifier 52. In order to properly drive the transistors T 5 and T 6 of the driver 42, the differential input amplifiers 50 and 52 must have matching characteristics to provide compatible signals and therefore must have the same type of MOS transistors as transistors T 5 and T 6 . Thus, the differential input amplifier 50 must have NMOS differential input transistors and the differential input amplifier 52 must have PMOS differential input transistors. The differential input amplifier 50 provides an input voltage V I4 to the gates of both transistors T 5 and T 7 and the differential input amplifier 52 provides an input voltage V I5 to the gates of transistors T 6 and T 8 . The two signals V I4 and V I5 have the same phase. However, depending on the levels of the V I4 and V I5 , either T 5 or T 6 will take over. In this configuration, since the source of a transistor is its lowest impedance node, the output node V OUT3 has a much lower impedance than a push-pull video buffer and therefore is more stable and faster than a push-pull video buffer of Figure 2. In addition, to further increase the speed, the video buffer of this invention is designed in two stages of driver 42 and feedback driver 44. The feedback driver 44 is added to the driver 42 to further isolate the output node V OUT3 from the feedback connection of the video buffer 40. Typically, in a conventional video buffer such as the video buffer 10 of Figure 1, the output node V OUT1 is connected to node 18 of the input stage 15 to create a dominant pole for feedback. On the contrary, in the video buffer 40, node 48 (feedback node) of the feedback driver 44 is connected to node 54 (feedback receiving node) of the input stage 45 to create a dominant pole for feedback. Also, the video buffer 40 has a rail-to-rail range of linearity. Referring to Figure 6, there is shown a graph of the linearity of the video buffer 40 of this invention. The horizontal axis represents the input voltage V IN3 and the vertical axis represents the output voltage V OUT3 . When V IN3 changes, since the output voltage V OUT3 follows V IN3 , the drain-to-source voltages V DS5 and V DS6 of either T 5 or T 6 will change and therefore V I4 and V I5 adjust themselves to match V DS5 and V DS6 . In Figure 6, both transistors T 5 and T 6 are ON for any value of the input voltage V I2 between 0 - 5 volts. In the lower portion of range M (0 - 5 volts), transistor T 5 takes over and transistor T 6 acts as an active load and in the upper portion of the range M, transistor T 6 takes over and transistor T 5 acts as an active load. Therefore, the video buffer 40 has a rail-to-rail linearity. Furthermore, since the driver 42 and the feedback driver 44 are CMOS, with a proper design of the differential input amplifiers 50 and 52, the power consumption of the video buffer 40 is low. In summary, the video buffer 40 of this invention has a high driving capabilities which provides high switching speed, rail-to-rail linearity, high stability and low power consumption. The above characteristics allow the video buffer of this invention to be used in sensor array imager of a digital copier or scanner. It should be noted that in the video buffer 40 of this invention, the feedback driver 44 is used to enhance the performance of the driver stage 42. However, if one desires, the feedback driver 44 can be eliminated and the video buffer 40 can be used without the feedback driver 44. In that case the output node V OUT3 has to be connected to node 54 to provide the necessary feedback. It should be noted that the video buffer according to the invention may be adapted in numerous ways by changing details of construction and the combination and arrangement of elements.

Claims: A video buffer comprising: an input means (45) having an NMOS differential input amplifier (50), a PMOS differential input amplifier (52), a feedback receiving node (54) and an input node (V IN3 ) for receiving an input signal to said video buffer; said NMOS differential input amplifier (50) and said PMOS differential input amplifier (52) each having an inverting input (-), a non-inverting input (+), and an output (V I4 , V I5 ); said non-inverting inputs (+) of said NMOS and PMOS differential input amplifiers (50, 52) being electrically connected to said input node (V IN3 ) of said input means (45) and said inverting inputs (-) of said NMOS and PMOS differential input amplifiers (50, 52) being electrically connected to each other at said feedback receiving node (54) of said input means (45); a feedback means (44) having a feedback node (48); said feedback means (44) being electrically connected to said input means (45) and being responsive to said input means (45); said feedback node (48) of said feedback means (44) being electrically connected to said feedback receiving node (54) of said input means (45); a driver means (42) having an output node (V OUT3 ) for sending out an output signal for said video buffer; said driver means (42) being electrically connected to said input means (45) and said feedback means (44) and being responsive to said input means (45); and said driver means (42) and said feedback means (44) being so constructed and arranged relative to each other that said output node (V OUT3 ) is isolated from said feedback node (48). The video buffer as claimed in claim 1 wherein said driver means (42) is a CMOS driver. The video buffer as claimed in claim 2 wherein: said CMOS driver comprises a first NMOS transistor (T 5 ) and a first PMOS transistor (T 6 ), each of which having a source, a drain and a gate; and said sources of said first NMOS and PMOS transistors (T 5 , T 6 ) are electrically connected to said output node (V OUT3 ). The video buffer as claimed in claim 3 wherein: said drain of said first NMOS transistor (T 5 ) is electrically connected to a power supply (V DD3 ); and said drain of said first PMOS transistor (T 6 ) is grounded. The video buffer as claimed in one of claims 1 to 4 wherein said feedback means (44) is a CMOS feedback driver. The video buffer as claimed in claim 5 wherein: said CMOS feedback driver comprises a second NMOS transistor (T 7 ) and a second PMOS transistor (T 8 ), each of which having a source, a drain and a gate; and said sources of said second NMOS and PMOS transistors (T 7 , T 8 ) are electrically connected to said feedback node (48). The video buffer as claimed in claim 6 wherein: said drain of said second NMOS transistor (T 7 ) is electrically connected to a power supply (V DD3 ); and said drain of said second PMOS transistor (T 8 ) is grounded. The video buffer as claimed in claim 6 or 7, wherein: said output (V I4 ) of said NMOS differential input amplifier (50) is electrically connected to said gates of said first and said second NMOS transistors (T 5 , T 7 ); said output (V I5 ) of said PMOS differential input amplifier (52) is electrically connected to said gates of said first and said second PMOS transistors (T 6 , T 8 ); said non-inverting inputs (+) of said NMOS and PMOS differential input amplifiers (50, 52) are electrically connected to said input node (V IN3 ) of said input means (45); and said inverting inputs (-) of said NMOS and PMOS differential input amplifiers (50, 52) are electrically connected to said feedback receiving node (54) of said input means (45).

Inventors: ZOMORRODI MEHRDAD, ZOMORRODI, MEHRDAD
Applicants: XEROX CORP, XEROX CORPORATION
Application year: 1999
Main classification: H04N5
IPC codes: H03F3, H04N5, H03F1