Method for autoaligning overlapped lines of conductor material provided in integrated electronic circuits

Abstract: An improved method for autoaligning lines (WL) of a conductive material in circuits integrated on a semiconductor substrate (2), comprising the following steps: forming, on said semiconductor substrate (2), a plurality of regions (3) projecting from the substrate (2) surface and aligned to one another; forming a fill layer (4) in the gaps between said regions (3) ; planarizing said fill layer (4) to expose said regions (3) ; removing a surface portion of said regions (3) to form holes (5) at the locations of said regions (3); forming an insulating layer (6) in said holes (5); selectively removing the dielectric layer (6) to form spacers (7) along the edges of said holes (5) ; depositing at least one conductive layer (8) all over the exposed surface; photolithographing with a mask and etching away the layer (8) to define lines (WL) and collimate them to the underlying regions (3).

Description: Field of the Invention This invention relates to a method for autoaligning overlapped lines of a conductive material in electronic circuits integrated on a semiconductor substrate. Specifically, the invention relates to an improved method for autoaligning lines of a conductive material in circuits integrated on a semiconductor substrate comprising the steps of: forming, on said semiconductor substrate, a plurality of regions projecting from the substrate surface and aligned to one another; forming a fill layer in the gaps between said regions; planarizing said fill layer to expose said regions. The invention relates, particularly but not exclusively, to a method for autoaligning the word lines of non-volatile memory matrices, and the description which follows will cover this field of application for convenience of illustration. Prior Art As is well known, electronic EPROM or Flash EPROM memory devices integrated on a semiconductor substrate comprise a plurality of non-volatile memory cells arranged in a matrix form; that is, the cells are laid into rows, or word lines, and columns, or bit lines. Each non-volatile memory cell comprises a MOS transistor whose gate electrode, located above the channel region, is floating, that is, has a high D.C. impedance to all the other terminals of the cell and the circuit in which the cell is connected. The cell also has a second electrode, said the control gate, which is coupled to the gate electrode and is driven by means of appropriate control voltages. The other transistor electrodes include the usual drain and source terminals. In recent years, considerable effort went to the development of memory devices with ever higher circuit density. This effort has resulted in electrically programmable, contactless non-volatile memory matrices with a cross-point type of structure becoming available. An example of a matrix of this kind, and of its manufacturing process, is described in EP-A-0 573 728 to this Applicant. In matrices of this type, the matrix bit lines are formed in the substrate as continuous parallel diffused strips. Following the formation of the gate regions of the matrix cells, the memory matrix appears as a series of posts (projecting elements) projecting from the semiconductor surface. At this stage, after filling the gaps which separate the various gate regions with a dielectric, the word lines of the memory matrix are formed which must be aligned to the gate regions of the cells appearing at the same row in the memory matrix. The operation for defining and aligning a polysilicon line, such as that representing a word line of a memory matrix, to a previously defined polysilicon layer underneath is critical because their dimensions are comparable. If a misalignment occurs in defining the upper word line, the underlying layer, which is usually made of the same material as the upper layer, is most likely to be etched away or damaged. There exists a physical limitation to the alignment of material layers belonging to successive lithographic levels. This limitation applies most strictly to the manufacturing of memory cell matrices, where the geometrical dimensions are carried to the lower limit of the photolithographic process. Shown in Figure 1 is a portion 1' of a matrix of memory cells wherein the gate regions 2' of the memory cells have been formed. Following the deposition of a fill layer 4', from which the gate regions 2' of the matrix will project, the polysilicon lines WL' are formed which are to be aligned to the gate regions 2'. In conformity with well-established designing rules, to collimate the lines WL' to their corresponding gate regions, a variation X is allowed which is fixed by the photolithographic limitations. Accordingly, it has become common practice to form the upper line with a width which exceeds by at least 2X the width of the underlying portion. However, this solution has some drawbacks. In fact, where the distance between two adjacent lines is exceedingly small and each line is made oversize, the lines may ultimately be too close together. On the other hand, where the line WL' formed in the upper layer is the same width as the lower line, the underlying gate regions may suffer damage in the event of a photolithographic misalignment occurring during the definition of the line WL', as highlighted by Figure 1. In this case, it would become necessary to align the upper line to the line underneath. A method to avoid extending the widths of metal lines in the vicinity of vias is described in US-A-5 904 569. The underlying technical problem of this invention is to provide a method of aligning overlapped polysilicon lines, which has such structural and functional features as to allow the lines of conductive material to be aligned, removes the need for forming oversize lines, and overcomes the limitations with which prior methods are still beset. Summary of the Invention The concept behind this invention is to provide spacers on the line to which the upper line must be aligned, so as to increase the space available on the underlying line, instead of forming an oversize upper line. Based on this concept, the technical problem is solved by a method as previously indicated and defined in Claim 1. The features and advantages of a device according to the invention will become apparent from the following description of an embodiment thereof, given by way of example and not of limitation with reference to the accompanying drawings. Brief Description of the Drawings In the drawings: Figure 1 is a top plan view of a portion of a semiconductor substrate having a series of posts formed thereon which are arranged into rows and columns and to which a series of polysilicon lines are to be aligned; Figures 2 to 6 are respective enlarged views in perspective of a portion of a semiconductor substrate during the manufacturing process according to the invention; Figure 7 shows respective enlarged view in vertical cross-section of a portion of a semiconductor substrate during the manufacturing process according to the invention. Detailed Description A method for autoaligning overlapped lines of a conductive material in electronic circuits integrated on a semiconductor substrate will be described with reference to the drawing views. The process steps discussed hereinafter describe no complete process of integrated circuit manufacturing. This invention can be practiced in combination with techniques of integrated circuit manufacturing currently employed in the industry, and only such common process steps as are necessary to an understanding of this invention will be considered herein. Those figures which illustrate schematically portions of an integrated circuit during its manufacturing are no scale drawings, but rather sketches intended to highlight major features of the invention. The following description will cover, in particular, a method for autoaligning overlapped lines of a conductive material as used in the construction of matrices 1 of memory cells, without this implying any limitations for the Applicant. In order to form memory cells comprising MOS devices with floating-gate coupling, on a semiconductor substrate 2, it is first necessary to form gate regions 3 projecting from the substrate 2 and be isolated therefrom by a first layer of gate oxide. Advantageously, these gate regions 3 consist of a stack structure comprising a first conductive layer (or POLY1), a second dielectric layer of interpoly, and a second conductive layer (or POLY CAP). The material used for the conductive layer is typically polysilicon, and the intermediate dielectric layer is a multi-layer such as ONO (Oxide-Nitride-Oxide). A protective dielectric layer, such as a top oxide layer, is then deposited over the Poly Cap layer. After forming the gate regions 3 as shown in Figure 2, a fill layer 4 is formed in the gaps between the gate regions 3. A planarizing step is subsequently carried out on the surface 10 to expose the conductive layer of the regions 3 from the fill layer 4. At this step, the invention provides for an etching step to be carried out without masking. This is a selective etching which only affects the material composing the surface portion of the regions 3 left bare from the fill layer. At the end of this etching step, the device surface will therefore exhibit a series of holes 5 at the locations of the regions 3. The holes are filled with an insulating layer 6 which is then removed, such as by anisotropic etching, in its central area only, so that a portion of the insulating layer 6 is left around the peripheries of the holes 5. Thus, spacers 7 are defined along the edges of the holes 5, as shown in Figure 5. Advantageously, a nitride layer is formed before the insulating layer 6, to act as an etch stopper for the removal of the next insulating layer 6. In a particularly advantageous embodiment, the insulating layer 6 is a dielectric layer. In this case, the spacers 7 are formed by anisotropically etching away this dielectric layer. At this step, a first conductive layer 8, and optionally a final conductive layer, are deposited conventionally over the entire exposed surface. Materials such as polysilicon and tungsten silicide (WSi 2 ) are usually employed to form the first conductive layer and final conductive layer, respectively. A photolithographic step using a mask is carried out and followed by the etching of the conductive layer 8 to define the word lines of the matrix and align them to the gate regions 3. As shown in Figure 7, where the word lines WL are drawn in positions overlying the gate regions but separated therefrom for clarity, on the occurrence of a misalignment the etching would stop at the dielectric which comprises the spacers 7. Thus, the spacers 7 provide an additional bound to the misalignment of the upper line WL from the corresponding gate regions 3. Compared to the prior art, it is therefore no longer necessary to make the upper line oversize in order to prevent the etching step for forming the line WL from damaging the underlying regions 3 on the occurrence of a misalignment. In this way, the lines WL can be formed with the same width as the regions 3, thereby affording improved integration of the cell matrix. However, the method according to the invention can also be used to align lines of a conductive material belonging to successive lithographic levels. In this case, the above-described regions 3 may be material lines extending along the same direction as the upper line.

Claims: An improved method for autoaligning lines (WL) of a conductive material in circuits integrated on a semiconductor substrate (2), comprising the following steps: forming, on said semiconductor substrate (2), a plurality of regions (3) projecting from the substrate surface and aligned to one another; forming a fill layer (4) in the gaps between said regions (3); planarizing said fill layer (4) to expose said regions (3); characterized in that it further comprises the steps of: removing a surface portion of said regions (3) to form holes (5) at the locations of said regions (3); forming an insulating layer (6) in said holes (5); anisotropically removing the insulating layer (6) to form spacers (7) along the edges of said holes (5); depositing at least one conductive layer (8) all over the exposed surface; defining a mask by photolithography and etching away the layer (8) to define lines (WL) and align them to the underlying regions (3). A method according to Claim 1, characterized in that said insulating layer (6) is a dielectric layer. A method according to Claim 1, characterized in that a nitride layer is formed before the insulating layer in the holes (5). A method according to Claim 1, characterized in that the step of removing the surface portions of the regions (3) is an unmasked etching step. A method according to Claim 2, characterized in that the spacers (7) are formed by anisotropically etching away the dielectric layer.

Inventors: BRAMBILLA CLAUDIO, CAPRARA PAOLO, CEREDA MANLIO SERGIO, BRAMBILLA, CLAUDIO, CAPRARA, PAOLO, CEREDA, MANLIO SERGIO
Applicants: ST MICROELECTRONICS SRL, STMICROELECTRONICS S.R.L.
Application year: 1999
Main classification: H01L21
IPC codes: H01L21