CMOS DELAY CIRCUIT USING SUBSTRATE BIASSING

Abstract: A delay element (DL), for delaying a signal which propagates through the delay element (DL) by a delay, comprises a field effect transistor (T>1<) having a source, a drain, a gate, and a back-gate (BG). The back-gate (BG) is arranged to receive a control voltage (V>cntrl<). The control voltage (V>cntrl<) controls a current through the field effect transistor (T>1<). As a consequence, the delay is also controlled by the control voltage (V>cntrl<).

Description: CMOS DELAY CIRCUIT USING SUBSTRATE BIASSING The invention relates to a delay element, for delaying a signal which propagates through the delay element by a delay, comprising a field effect transistor having a source, a drain, a gate, and a back-gate. Such a delay element is known from the European patent application EP 0 661 809 Al. In order to vary the delay of the delay element a voltage controlled current source is arranged in series with the source electrode of the field effect transistor. By means of the voltage controlled current source a current through the field effect transistor can be varied, which thereby varies the delay of the delay element. This makes the delay element especially suitable for use in a voltage controlled oscillator. In the known delay element the voltage controlled current source consumes a part of the supply voltage. Since nowadays there is a need for making electronic circuits which can operate at a low supply voltage, the consumption of part of the supply voltage is disadvantageous. It is an object of the invention to provide an improved delay element which eliminates the above-mentioned disadvantage. To this end, according to the invention, the delay element of the type defined in the opening paragraph is characterized in that the back-gate is arranged to receive a control voltage for controlling the delay of the delay element. Thus it is accomplished that the current through the field effect transistor can be varied by means of the control voltage. The delay element may further comprise a further field effect transistor having a source, a drain coupled to the drain of the field effect transistor, and a gate coupled to the gate of the field effect transistor. The source of the field effect transistor is connected to a first terminal of a voltage supply source for supplying a supply voltage. The source of the further transistor is connected to a second terminal of the voltage supply source. By so doing, the entire supply voltage is available for the, delay element. This is in contrast with the known delay element. The invention also relates to an oscillator including the delay element according to the invention as claimed in Claims 1 and 2. Since the oscillation frequency of the oscillator depends on the delay of the delay element, the oscillation frequency can be controlled by the control voltage which controls the delay of the delay element. It appears that the oscillation frequency is virtually linear with respect to the control voltage over a very wide frequency range. The invention also relates to a phase-locked loop (PLL) circuit including the afore-mentioned oscillator according to the invention as claimed in Claim 4. Thus a low- voltage phase-locked loop circuit is obtained which does not need a d.c./d.c. up-converter for locally increasing the supply voltage. This has the advantage that a phase-locked loop circuit according to the invention is simplified. Another advantage in case that the phase-locked loop circuit is incorporated in an integrated circuit is that it requires only a relatively small amount of chip area. The invention will be described in more detail with reference to the accompanying drawings, in which: Figure 1 is a circuit diagram of an embodiment of a delay element according to the invention; Figure 2 is a circuit diagram of a further embodiment of a delay element according to the invention; and Figure 3 is a circuit diagram of an oscillator including delay elements according to the invention. In these Figures parts or elements having like functions or purposes bear the same reference symbols. Figure 1 shows a delay element DL having an input terminal IP, an output terminal OP, and a control terminal CNTRL. The delay element DL is powered by a voltage supply source SV having a first supply terminal SVT and a second supply terminal RF. The delay element DL comprises a field effect transistor T} having a source connected to the first supply terminal SVT, a drain connected to the output terminal OP, a gate connected to the input terminal IP, and a back-gate BG connected to the control terminal CNTRL. A load impedance Z is connected between the output terminal OP and the second supply terminal RF. An input signal Uj, which is applied between the input terminal IP and the second supply terminal RF, propagates through the delay element DL and produces an output signal U 0 between the output terminal OP and the second supply terminal RF. Apart from the fact that the delay element DL as shown in Figure 1 converts the input signal Uj to the inverted output signal U 0 , the delay element DL also delays the input signal Uj. The delay inter alia depends on a current flowing through the field effect transistor T By applying a control voltage V cntr ι between the source of the field effect transistor T and the back-gate BG, the current through the field effect transistor T,, and thus the delay, can be varied by varying the control voltage V cntr i. The load impedance can, for example, be a resistor, but alternatively other components, like transistors, can be applied. Figure 2 shows a circuit diagram of a further embodiment of a delay element according to the invention. The load impedance Z (see Figure 1) is formed by a further field effect transistor T 2 . The further field effect transistor T 2 has a drain connected to the output terminal OP, a source connected to the second supply terminal RF, and a gate connected to the input terminal IP. The field effect transistor Ti and the further field effect transistor T 2 , form together an inverter stage having the special feature that the delay of the inverter (and thus of the delay element) can be varied by the control voltage V cntr ι. Instead of being applied to the back-gate BG of the field effect transistor T l 5 the control voltage V cntr i can also be applied to a back-gate of the further field effect transistor T 2 . Alternatively, both the back-gate BG of the field effect transistor Ti and the back-gate of the further field effect transistor T 2 can be controlled by control voltages. This has the advantage of a larger range of the delay. (However, in many IC CMOS-processes it is not possible to apply control voltages to both PMOSTs and N-MOSTs). Figure 3 shows a circuit diagram of an oscillator OSC including delay elements DL according to the invention. By way of example, five delay elements DL are arranged in cascade to form a so called ring oscillator in which the output terminal of the last delay element is connected to the input terminal of the first delay element of the cascaded elements. By varying the control voltage V cntr ι, the currents through the field effect transistors are varied, and thereby the delay of each delay element DL is varied. Since the oscillation frequency of the oscillator decreases as the delay increases, the oscillation frequency can be controlled by the control voltage V cntr ι.

Claims: CLAIMS: 1. A delay element (DL), for delaying a signal which propagates through the delay element (DL) by a delay, comprising a field effect transistor (T having a source, a drain, a gate, and a back-gate (BG), characterized in that the back-gate (BG) is arranged for receiving a control voltage (V cntr ι) for controlling the delay-time of the delay element (DL). 2. A delay element (DL) as claimed in Claim 1, characterized in that the delay element (DL) further comprises a further field effect transistor (T 2 ) having a source, a drain coupled to the drain of the field effect transistor (TO, and a gate coupled to the gate of the field effect transistor (TO- 3. A delay element (DL) as claimed in Claim 2, characterized in that the source electrode of the field effect transistor (TO is connected to a first terminal (SVT) of a voltage supply source (SV), and that the source electrode of the further transistor (T ) is connected to a second terminal (RF) of the voltage supply source (SV). 4. An oscillator (OSC) including a delay element (DL) as claimed in Claim 1. 5. A phase-locked loop circuit including an oscillator (DL) as claimed in Claim 4.

Inventors: MESSMER ADRIAN, SCHELLER GERD J E, MESSMER, ADRIAN, SCHELLER, GERD, J., E.
Applicants: KONINKL PHILIPS ELECTRONICS NV, KONINKLIJKE PHILIPS ELECTRONICS N.V.
Application year: 1999
Main classification: H03K5
IPC codes: H03K3, H03K5, H03L7