PLASMA PROCESS TO DEPOSIT SILICON NITRIDE WITH HIGH FILM QUALITY AND LOW HYDROGEN CONTENT

Abstract: A high-quality plasma CVD nitride layer is formed at a process temperature of between 400 DEG C and 600 DEG C from a precursor gas including silane and nitrogen. The improved nitride layer is used as an etch stop layer, a spacer, and as a lining layer for shallow trench isolation and in a pre-metal dielectric layer.

Description: PLASMA PROCESS TO DEPOSIT SILICON NITRIDE WITH HIGH FILM QUALITY AND LOW HYDROGEN CONTENT BACKGROUND OF THE INVENTION Nitride films are dielectric films that are employed in integrated circuits as insulating and passivating (protective) films, and include silicon nitride (Si 3 N 4 ) and silicon oxynitride (SiON) films. One metliod of forming nitride films is by thermal chemical vapor deposition (or thermal CVD) at relatively high temperatures (e.g. , at 700°C and above). When low pressure (LP) techniques are employed in conjunction with a high-temperature thermal CVD process, the resulting nitride films are referred to as low pressure (LP) or LPCVD nitride films. LP nitride films normally exhibit relatively good film umformity. LP nitride films are usually not deposited subsequent to the formation of metal contacts because of the relatively low melting point of the metals used in fabricating such structures (e.g., aluminum, aluminum alloys, or other low-melting- point metals). Thus, processing temperatures in subsequent steps are limited to about 450°C in order to avoid damage to the metal contacts. In addition, the high temperature associated with the deposition of LP nitride films can potentially cause . other problems, including the degradation of tungsten suicide structures, driving junctions too deeply into the substrate, and chamber contamination. Unfortunately, as indicated above, the high temperatures used in depositing LPCVD nitride films can complicate their integration into processes having a relatively low thermal budget. Other difficulties in the use of LPCVD nitride films also exist. For example, such films exhibit tensile rather than compressive stress, leading to poor film quality (e.g., cracking and the like). Such films are also difficult to integrate into a process sequence because of the increase in processing time their fabrication requires. This is due to their being deposited using a two-step process and their relatively low deposition rates. Such films also deposit a relatively large amount of residue on interior chamber surfaces, mandating more frequent chamber cleaning than might otherwise be necessary. In order to address these problems, plasma enhanced CVD (PECVD) processes have been employed to deposit protective silicon nitride films at relatively low temperatures. A typical PECVD gas flow chemistry for depositing silicon nitride comprises silane and ammonia reactants along with a diluent, e.g., nitrogen, argon, or helium as follows: SiH 4 + NH 3 + N 2 (diluent) SLN y H z One of the problems with low temperature PECVD deposition of nitride films using this chemistry is that large amounts of hydrogen are incorporated into the films due to the Si-H and N-H bonds. One reason for the high hydrogen content of the resulting PECVD nitride film is the presence of the three hydrogen atoms in each ammonia molecule. The incorporation of a large amount of hydrogen is a problem because of the adverse physical effects such high concentrations can have on circuit characteristics. For example, inclusion of hydrogen in a nitride intermetal dielectric (IMD) layer can result in a higher interconnect capacitance, reducing the circuit's maximum operating frequency. Moreover, hydrogen is chemically reactive and diffuses quickly. Thus, hydrogen in a nitride IMD film can come into contact and " react with the metal interconnect insulated by the nitride IMD film, damaging the interconnect and increasing the likelihood of device failure. A PECVD system for depositing a high-quality silicon nitride film is disclosed in U.S. Patent 4,854,263 (the '"263 patent") which is assigned to the assignee of the present application, and is incorporated herein by reference, in its entirety for all purposes. In that patent, a parallel plate RF vacuum chamber has a gas inlet manifold plate having a plurality of apertures, each aperture including an outlet at the chamber or processing side of the plate and an inlet on the gas distribution side of the plate. As depicted in Fig. 6 therein, the outlet is larger than the inlet to promote dissociation and reactivity of a process gas. A PECVD system using the RF vacuum chamber disclosed in the '263 patent is useful in forming silicon nitride films using a nitrogen chemistry that does not include ammonia. This is because the gas inlet manifold disclosed promotes the dissociation of nitrogen to facilitate the deposition of silicon nitride at relatively high deposition rates. In the '263 patent, a PECVD nitride film process was carried out at a substrate temperature of about 300-360 °C and the hydrogen content of the film described in the '263 patent was between 7-10 atomic percent (at%). Thus, by eliminating ammonia in the process gas, the concentration of hydrogen in the resulting silicon nitride film was reduced. However, a PECVD nitride film possesses certain qualities that, in certain applications (e.g., as a gate spacer or an etch stop layer), may prove less than desirable. For example, PECVD nitride films tend to exhibit tensile, rather than compressive stress, which can lead to cracking near the edges of the substrates upon which the films are deposited. Also, PECVD nitride films can suffer from poor film quality, as evidenced by poor sidewall coverage exhibited by some PECVD nitride films. Additionally, the etch selectivity of known PECVD nitride films is relatively low. For example, the etch selectivity of one nitride film deposited using a PECVD process is approximately 80 or lower. Thus, LPCVD nitride films are generally utilized in these applications. Accordingly, there is a need in the art for nitride layer deposition processes that use a relatively low thermal budget. Moreover, such films should exhibit low hydrogen content, good film quality, relatively high etch selectivity to oxide, and minimal cracking. Finally, the process for depositing such a film should integrate easily into the process sequence. SUMMARY OF THE INVENTION The present invention provides a method and apparatus for fabricating a silicon nitride film having a low hydrogen content and high quality. The present invention requires a relatively low thermal budget in the fabrication of such a film. As used herein, quality is determined as a combination of step coverage, sidewall coverage, etch selectivity to oxide, moisture resistance, and cracking resistance. Specifically, the hydrogen content and etch selectivity of the nitride film is comparable to that of LP nitride, as are such a film's step coverage and sidewall coverage. Such a film also provides good moisture resistance, as well as good cracking resistance due to the tunability of the film's compressive stress. The process of the present invention integrates easily into the process sequence than, for example, an LPCVD nitride process, because it is performed in a single step and provides a relatively high deposition rate. A film of the present invention is deposited at a relatively high temperature (hence the film is sometimes referred to herein as a "high-temperature nitride film" or "high-temperature nitride layer") as compared to prior PECVD silicon nitride processes. In one embodiment, a high-temperature nitride film according to the present invention is deposited at a process temperature of between about 400°C and about 600°C, using a process gas comprised of silane, nitrogen, and in some embodiments, ammonia. Preferably, such a film is deposited at a process temperature of between about 500 °C and about 575 °C. In another aspect of the invention, a helium precursor gas is also included in the process gas. According to another aspect of the invention, the step coverage, hydrogen content, etch selectivity to oxide, and other properties of the resulting film are controlled by varying process parameters such as pressure and power. Embodiments of the present invention include semiconductor devices fabricated using a high-temperature nitride film deposited according to the present invention. For example, such high-temperature nitride films may be employed in the fabrication of structures such as a polysilicon gate spacer, shallow isolation trench, or premetal dielectric layer, or in the fabrication of an etch stop layer. In a further aspect of the invention, the flow of silane gas is controlled to be in the range of 10 seem and about 500 seem, preferably between about 20 seem and about 100 seem; the flow of nitrogen is controlled to be in the range of about 100 seem and about 5000 seem, preferably between about 2000 seem and about 5000 seem; and, when used, the flow of ammonia is controlled to be between about 0 seem and about 1000 seem; preferably between about 10 seem and about 100 seem. The process pressure is maintained to between about 2 Torr and 8 about Torr, preferably between about 5 Torr and 7 about Torr. Other features and advantages of the invention will become apparent in view of the following detailed description and the appended drawings. BRIEF DESCRIPTION OF THE DRAWINGS Figs. IA and IB are vertical cross-sectional views of one embodiment of a chemical vapor deposition apparatus according to the present invention; Figs. 1C and ID are exploded perspective views of parts of the CVD chamber depicted in Fig. IA; Fig. IE is a simplified diagram of a system monitor and CVD system 10 in a multichamber system, which may include one or more chambers; Fig. IF is a block diagram of the hierarchical control structure of the system control software, computer program 70, according to a specific embodiment; Fig. 2A is a flow diagram depicting the steps for depositing a high-temperature nitride film according to the present invention; Fig. 2B is a set of graphs depicting the stability of a process according to the present invention with regard to film thickness, film uniformity, refractive index, and film stress; Fig. 2C is a diagram illustrating the effect of various process parameters on the characteristics of a high-temperature nitride film according to the present invention; Fig. 3 is a flow diagram depicting the steps for utilizing a high-temperature PECVD nitride film as an etch stop layer in an oxide etch process; Figs. 4A and 4B are cross-sectional views of a device showing the high-temperature PECVD nitride used as an etch stop layer in a self-align contact structure; Figs. 4C and 4D are cross-sectional views of a device showing the high-temperature PECVD nitride used as an etch stop layer in a borderless contact structure; Figs. 5 A and 5B are cross-sectional views of a device showing the formation of a high-temperature PECVD nitride layer into a spacer; Fig. 6 is cross-sectional view of a shallow isolation trench structure; Fig. 7 is a flow diagram depicting the steps of forming a high-temperature nitride lining layer in a shallow trench isolation structure; Fig. 8 is a cross-sectional view of a premetal dielectric layer; and Fig. 9 is a flow diagram depicting the step of forming a high-temperature nitride lining layer in a premetal dielectric layer. DESCRIPTION OF THE SPECIFIC EMBODIMENTS I. Exemplary CVD System Specific embodiments of the present invention may be deposited using a variety of chemical vapor deposition (CVD) or other types of substrate processing systems. One suitable CVD machine in which the method of the present invention can be carried out is shown in Figs. IA and IB, which are vertical, cross-sectional views of a chemical vapor deposition system 10, having a vacuum or processing chamber 15 that includes a chamber wall 15a and chamber lid assembly 15b. Chamber wall 15a and chamber lid assembly 15b are shown in exploded, perspective views in Figs. 1C and ID. CVD system 10 contains a gas distribution manifold 11 for dispersing process gases to a substrate (not shown) that rests on a resistively heated pedestal 12 centered within the process chamber, which is supported by, for example, a heater base (shown as part of pedestal 12 in Figs. IA, IB, and 1C). The volume between gas distribution manifold 11 and pedestal 12 is referred to herein as a deposition zone. A portion of this volume may also be referred to in this manner. During processing, the substrate (e.g. , a semiconductor substrate) is positioned on a flat (or slightly convex) surface 12a of pedestal 12. Preferably fabricated from a ceramic material with regard to the high temperatures employed in the present invention, pedestal 12 can be moved controUably between a lower loading/off-loading position (depicted in Fig. IA) and an upper processing position (indicated by dashed line 14 in Fig. IA and shown in Fig. IB), which is closely adjacent to manifold 11. A centerboard (not shown) includes sensors for providing information on the position of the substrates. Deposition and carrier gases flow into chamber 15 through perforated holes 13b (Fig. ID) of a gas distribution faceplate 13a. Preferably, a faceplate of the design disclosed in the '263 is employed in order to increase the dissociation of process gases passing therethrough, and so improve the deposition of the silicon nitride film using the process chemistry of the present invention. More specifically, deposition process gases flow (indicated by arrow 40 in Fig. IB) into the chamber through the inlet manifold 11 , through a conventional perforated blocker plate 42 and then through holes 13b in gas distribution faceplate 13a. Before reaching the manifold, deposition and carrier gases are input from gas sources 7 through gas supply lines 8 (Fig. IB) into a gas mixing block or system 9 where they are combined and then sent to manifold 11. It is also possible, and desirable in some instances, to direct deposition and carrier gases directly from supply lines 8 to manifold 11, bypassing gas mixing system 9. In other situations, any of gas lines 8 may bypass gas mixing system 9 and flow gases through passages (not shown) in the bottom of chamber 12. Generally, the supply line for each process gas includes (i) several safety shut-off valves (not shown) that can be used to automatically or manually shut off the flow of process gas into the chamber, and (ii) mass flow controllers (MFCs) (also not shown) that measure the flow of gas through the supply line. When toxic gases are used in the process, the several safety shut-off valves are positioned on each gas supply line in conventional configurations. The deposition process performed in CVD system 10 can be either a thermal process or a plasma-enhanced process. In a plasma-enhanced process, an RF power supply 44 applies electrical power between the gas distribution faceplate 13a and pedestal 12 to excite the process gas mixture to form a plasma within the cylindrical region between the faceplate 13a and pedestal 12. Constituents of the plasma react to deposit a desired film on the surface of the semiconductor substrate supported on pedestal 12. RF power supply 44 can be a mixed-frequency RF power supply that typically supplies power at a high RF frequency (RF1) of 13.56 MHz and at a low RF frequency (RF2) of 360 kilohertz (kHz) to enhance the decomposition of reactive species introduced into the vacuum chamber 15. Of course, RF power supply 44 can supply either single- or mixed-frequency RF power (or other desired variations) to manifold 11 to enhance the decomposition of reactive species introduced into chamber 15. In a thermal process, RF power supply 44 is not utilized, and the process gas mixture reacts thermally to deposit the desired film on the surface of the semiconductor substrate supported on pedestal 12, which is resistively heated to provide the thermal energy needed for the reaction. During a thermal deposition process, pedestal 12 is heated, causing heating of CVD system 10. In a hot-wall system, of the type previously mentioned, a hot liquid may be circulated through chamber wall 15a to maintain chamber wall 15a at an elevated temperature when the plasma is not turned on, or during a thermal deposition process. Fluids used to heat chamber wall 15a include the typical fluid types (i.e. , water-based ethylene glycol or oil-based thermal transfer fluids). This heating beneficially reduces or eliminates condensation of undesirable reactant products and improves the elimination of volatile products of the process gases and contaminants that might otherwise condense on the walls of cool vacuum passages and migrate back into the processing chamber during periods of no gas flow. In a cold-wall system, chamber wall 15a is not heated. This might be done, for example, during a plasma-enhanced deposition process. In such a process, the plasma heats chamber 15, including chamber wall 15a surrounding exhaust passageway 23 and shut-off valve 24. However, because the plasma is unlikely to be in equal proximity to all chamber surfaces, variations in surface temperature may occur, as previously noted. The remainder of the gas mixture that is not deposited in a layer, including reaction products, is evacuated from the chamber by a vacuum pump (not shown). Specifically, the gases are exhausted through an annular slot 16 surrounding the reaction region and into an annular exhaust plenum 17. Annular slot 16 and plenum 17 are defined by the gap between the top of chamber wall 15a (including upper dielectric lining 19) and the bottom of circular chamber lid 20. The 360° circular symmetry and uniformity of annular slot 16 and plenum 17 are important to achieving a uniform flow of process gases over the substrate so as to deposit a uniform film on the substrate. The gases flow underneath a lateral extension portion 21 of exhaust plenum 17, past a viewing port (not shown), through a downward-extending gas passage 23 , past a vacuum shut-off valve 24 (whose body is integrated with a lower portion of chamber wall 15a), and into an exhaust outlet 25 that connects to the external vacuum pump through a foreline (not shown). The substrate support platter of resistively heated pedestal 12 is heated using an embedded, single-loop heater element configured to make two full turns in the form of concentric circles. An outer portion of the heater element runs adjacent to a perimeter of the support platter, while an inner portion runs on the path of a concentric circle having a smaller radius. The wiring to the heater element passes through the stem of pedestal 12. Typically, pedestal 12 may be made of material including aluminum, ceramic, or some combination thereof. However, in high-temperature applications, high-temperature materials (e.g., some sort of ceramic material) should be used to avoid the possibility of pedestal 12 melting due to the high temperature employed, as might occur with a pedestal fabricated from aluminum. Typically, any or all of the chamber lining, gas inlet manifold faceplate, and various other processing chamber hardware are made out of material such as aluminum, anodized aluminum, or a ceramic material. Again, high- temperature materials (e.g. , some sort of ceramic material) should be used to avoid the possibility of pedestal 12 (or other chamber components maintained at a high temperature) melting due to the high temperature employed. A lift mechanism and motor 32 (Fig. IA) raises and lowers pedestal 12 and its substrate lift pins 12b as substrates are transferred by a robot blade (not shown) into and out of the body of the chamber through an insertion/removal opening 26 in the side of chamber 10. Motor 32 raises and lowers pedestal 12 between a processing position 14 and a lower substrate-loading position. Motor 32, various valves and MFCs of the gas delivery system, and other components of CVD system 10 are controlled by a system controller 34 (Fig. IB) over control lines 36, of which only some are shown. Controller 34 relies on feedback from optical sensors to determine the position of movable mechanical assemblies, such as the throttle valve and pedestal that are moved by appropriate motors controlled by controller 34. In a preferred embodiment, system controller 34 includes a hard disk drive (a memory 38), a floppy disk drive (not shown), and a processor 37. Processor 37 contains a single-board computer (SBC), analog and digital input/output boards, interface boards, and stepper motor controller boards. Various parts of CVD system 10 conform to the Versa Modular European (VME) standard that defines board, card cage, and connector dimensions and types. The VME standard also defines the bus structure as having a 16-bit data bus and a 24-bit address bus. System controller 34 controls all of the activities of CVD system 10. System controller 34 executes system control software, which is a computer program stored in a computer-readable medium such as memory 38. Preferably, memory 38 is a hard disk drive, but memory 38 may also be other kinds of memory. The computer program includes sets of instructions that dictate the timing, mixture of gases, chamber pressure, chamber temperature, RF power levels, pedestal position, and other parameters of a particular process. Other computer programs stored on other memory devices including, for example, the floppy disk or other another appropriate drive, may also be used to operate system controller 34. The interface between a user and controller 34 is via a CRT monitor 50a and light pen 50b, shown in Fig. IE, which is a simplified diagram of the system monitor and CVD system 10 in a substrate processing system, which may include one or more chambers. In the preferred embodiment, two CRT monitors 50a are used, one mounted in the clean room wall for the operators and the other behind the wall for the service technicians. CRT monitors 50a simultaneously display the same information, but only one light pen 50b is enabled. A light sensor in the tip of light pen 50b detects light emitted by CRT monitor 50a. To select a particular screen or function, the operator touches a designated area of the display screen and pushes the button on pen 50b. The touched area changes its highlighted color, or a new menu or screen is displayed, confirming communication between the light pen and the display screen. Other devices, such as a keyboard, mouse, or other pointing or communication device, may be used instead of or in addition to light pen 50b to allow the user to communicate with system controller 34. The process for depositing the film can be implemented using a computer program product that is executed by system controller 34. The computer program code can be written in any conventional computer-readable programming language: for example, 68000 assembly language, C, C+ + , Pascal, Fortran or others. Suitable program code is entered into a single file, or multiple files, using a conventional text editor and stored or embodied in a computer-usable medium, such as a memory system of the computer. If the entered code text is in a high level language, the code is compiled, and the resultant compiler code is then linked with an object code of precompiled Windows library routines. To execute the linked, compiled object code, the system user invokes the object code, causing the computer system to load the code in memory. The CPU then reads and executes the code to perform the tasks identified in the program. Fig. IF is an illustrative block diagram of the hierarchical control structure of the system control software, a computer program 70, according to a specific embodiment. Using the light pen interface, a user enters a process set number and process chamber number into a process selector subroutine 73 in response to menus or screens displayed on CRT monitor 50a. The process sets are predetermined sets of process parameters necessary to carry out specified processes, and are identified by predefined set numbers. Process selector subroutine 73 identifies (i) the desired process chamber and (ii) the desired set of process parameters needed to operate the process chamber for performing the desired process. The process parameters for performing a specific process relate to process conditions such as, for example, process gas composition and flow rates, temperature, pressure, plasma conditions such as microwave power levels or RF power levels and the low- frequency RF frequency, cooling gas pressure, and chamber wall temperature. These parameters are provided to the user in the form of a recipe and are entered utilizing the light pen/CRT monitor interface. The signals for monitoring the process are provided by the analog and digital input boards of the system controller, and the signals for controlling the process are output on the analog and digital output boards of CVD system 10. A process sequencer subroutine 75 comprises program code for accepting the identified process chamber and set of process parameters from process selector subroutine 73 and for controlling operation of the various process chambers. Multiple users can enter process set numbers and process chamber numbers, or a user can enter multiple process set numbers and process chamber number, so process sequencer subroutine 75 operates to schedule the selected processes in the desired sequence. Preferably, process sequencer subroutine 75 includes code to perform the steps of (i) monitoring the operation of the process chambers to determine if the chambers are being used, (ii) determining what processes are being carried out in the chambers being used, and (iii) executing the desired process based on availability of a process chamber and type of process to be carried out. Conventional methods of monitoring the process chambers can be used, such as polling. When scheduling which process is to be executed, process sequencer subroutine 75 takes into consideration the present condition of the process chamber being used in comparison with the desired process conditions for a selected process, or the "age" of each particular user entered request, or any other relevant factor a system programmer desires to include for determining scheduling priorities. Once it determines which process chamber and process set combination is to be executed, process sequencer subroutine 75 initiates execution of the process' set by passing the particular process set parameters to chamber manager subroutines 77a-c, which control multiple processing tasks in process chamber 15 according to the process set determined by process sequencer subroutine 75. For example, chamber manager subroutine 77a comprises program code for controlling sputtering and CVD process operations in process chamber 15. Chamber manager subroutines 77a-c also control execution of various chamber component subroutines that control operation of the chamber components necessary to carry out the selected process set. Examples of chamber component subroutines are a substrate positioning subroutine 80, a process gas control subroutine 83, a pressure control subroutine 85, a heater control subroutine 87, and a plasma control subroutine 90. Those having ordinary skill in the art will readily recognize that other chamber control subroutines can be included depending on what processes are to be performed in process chamber 15. In operation, chamber manager subroutine 77a selectively schedules or calls the process component subroutines in accordance with the particular process set being executed. Chamber manager subroutine 77a schedules the process component subroutines much like process sequencer subroutine 75 schedules the process set to be executed and the chamber in which to execute it. Typically, chamber manager subroutine 77a includes steps of monitoring the various chamber components, determining which components need to be operated based on the process parameters for the process set to be executed, and causing execution of a chamber component subroutine responsive to the monitoring and determining steps. Operation of particular chamber component subroutines will now be described with reference to Fig. IF. Substrate positioning subroutine 80 comprises program code for controlling chamber components that are used to load the substrate onto pedestal 12, to lift the substrate to a desired height in process chamber 15, and to control the spacing between the substrate and gas distribution manifold 11. When a substrate is loaded into process chamber 15, pedestal 12 is lowered to receive the substrate, and thereafter, pedestal 12 is raised to the desired height in process chamber 15, to maintain the substrate at a desired distance or spacing from gas distribution manifold 11 during processing. In operation, substrate positioning subroutine 80 controls movement of pedestal 12 in response to process set parameters, related to the support height, that are transferred from chamber manager subroutine 77a. Process gas control subroutine 83 has program code for controlling process gas composition and flow rates. Process gas control subroutine 83 controls the open/close position of the safety shut-off valves, and also ramps up/down the mass flow controllers to obtain the desired gas flow rate. Process gas control subroutine 83 is invoked by chamber manager subroutine 77a, as are all chamber component subroutines, and receives from the chamber manager subroutine process parameters related to the desired gas flow rates. Typically, process gas control subroutine 83 operates by opening the gas supply lines and repeatedly (i) reading the necessary mass flow controllers, (ii) comparing the readings with the desired flow rates received from chamber manager subroutine 77a, and (iii) adjusting the flow rates of the gas supply lines as necessary. Furthermore, process gas control subroutine 83 includes steps for monitoring the gas flow rates for unsafe rates and for activating the safety shut-off valves when an unsafe condition is detected. Pressure control subroutine 85 comprises program code for controlling the pressure in processing chamber 15 by regulating the size of the opening of the throttle valve in the chamber's exhaust system. The size of the throttle valve's opening is set to control the chamber pressure to the desired level in relation to the total process gas flow, size of process chamber 15, and pumping set-point pressure for the exhaust system. When pressure control subroutine 85 is invoked, the target pressure level is received as a parameter from chamber manager subroutine 77a. Pressure control subroutine 85 operates to measure the pressure in processing chamber 15 by reading one or more conventional pressure manometers connected to the chamber, to compare the measured value(s) with the target pressure, to obtain PID (proportional, integral, and differential) values from a stored pressure table corresponding to the target pressure, and to adjust the throttle valve according to the PID values obtained from the pressure table. Alternatively, pressure control subroutine 85 can be written to open or close the throttle valve to a particular opening size to regulate processing chamber 15 to the desired pressure. Heater control subroutine 87 comprises program code for controlling the current to a heating unit that is used to heat the substrate. Heater control subroutine 87 is also invoked by chamber manager subroutine 77a and receives a target, or set-point, temperature parameter. Heater control subroutine 87 measures temperature by measuring voltage output of a thermocouple located in pedestal 12, comparing the measured temperature with the set-point temperature, and increasing or decreasing current applied to the heating unit to obtain the set-point temperature. The temperature is obtained from the measured voltage by looking up the corresponding temperature in a stored conversion table or by calculating the temperature using a fourth-order polynomial. When an embedded loop is used to heat pedestal 12, heater control subroutine 87 gradually controls a ramp up/down of current applied to the loop. Additionally, a built-in fail-safe mode can be included to detect process safety compliance, and can shut down operation of the heating unit if process chamber 15 is not configured properly. Plasma control subroutine 90 comprises code for setting the low- and high- frequency RF power levels applied to the process electrodes in processing chamber 15, and for setting the low-frequency RF frequency employed. Plasma control subroutine 90 also includes program code for turning on and setting/adjusting the power levels applied to the magnetron or other microwave source used in the present invention. Plasma control subroutine 90 is invoked by chamber manager subroutine 77a, in a fashion similar to the previously described chamber component subroutines. The above reactor description is mainly for illustrative purposes, and other plasma CVD equipment such as electron cyclotron resonance (ECR) plasma CVD devices, induction coupled RF high density plasma CVD devices, or the like may be employed. Additionally, variations of the above-described system, such as variations in susceptor design, heater design, RF power frequencies, location of RF power connections and others are possible. In other embodiments, the process can be carried out a chamber using quartz lamps to heat the substrate. The layer and method for forming such a layer of the present invention is not limited to any specific apparatus or to any specific plasma excitation method. II. Method and Apparatus for Depositing High-Temperature Nitride Films Process recipes for depositing the PECVD high-temperature nitride film on an 8" substrate using a DxZ chamber, fitted with a ceramic pedestal and manufactured by Applied Materials, Inc., Santa Clara, California, in a preferred embodiment of the invention is set forth in Tables 1 and 2. The steps for depositing the layer are depicted in the flow diagram of Fig. 2A. Fig. 2A illustrates a process according to the present invention. At step 200, the environmental parameters within the processing chamber are set. This includes setting the pressure in processing chamber 15 and processing temperature. The pressure in processing chamber 15 is set to between about 2 torr and about 8 torr, and preferably to between about 5 torr and about 7 torr. The processing temperature is set to between about 400°C and about 600°C, and preferably to between about 500°C and about 575°C. At step 210, electrode spacing (i.e., the spacing between pedestal 12 and gas distribution faceplate 13a) is set to between about 200 mils and about 600 mils, and preferably between about 300 mils and about 600 mils. Although this is illustrated as part of the process of Fig. 2, electrode spacing may be set before any of the processes of the present invention are carried out. Next, at step 220, the deposition gases are flowed into the processing chamber. Silane (SiH 4 ) is introduced into processing chamber 15 at a rate of between about 10 seem and about 500 seem. Preferably, silane is introduced at a rate of between about 20 seem and about 100 seem, and most preferably at a rate of about 50 seem. Nitrogen (N 2 ) is introduced into processing chamber 15 at a rate of between about 100 seem and about 5000 seem. Preferably, nitrogen is introduced at a rate of between about 2000 seem and about 5000 seem, and most preferably at a rate of about 4500 seem. Optionally, ammonia (NH 3 ) and/or helium (He) may also be introduced into processing chamber 15. Ammonia may be introduced into processing chamber 15 at a rate of up to about 5000 seem. Preferably, ammonia is introduced at a rate of between about 10 seem and about 100 seem, and most preferably at a rate of about 30 seem. Helium may be introduced into processing chamber 15 at a rate of between about 500 seem and about 3000 seem. The preceding gas flow parameters are for a DxZ chamber manufactured by Applied Materials, Inc., Santa Clara, California, configured to process 8 inch substrates and fitted with a ceramic pedestal. Other chamber designs may require different flow rates to deposit a film according to the present invention, and so the preceding parameters may vary between substrate processing systems. Energy is then applied to the deposition gases (step 230) in order to begin deposition of a silicon nitride film according to the present invention. During this step, for example, RF energy is applied in order to strike a plasma from the deposition gases. An RF power level of between about 200 W and about 800 W is applied to form the plasma. In the DxZ chamber described above, this equates to an RF power density of between about 0.62 W/cm 2 and about 2.48 W/cm 2 . Preferably, an RF power level of between about 300 W and about 600 W (equating to an RF power density of between about 0.93 W/cm 2 and about 1.86 W/cm 2 ) is applied to form the plasma. These RF power levels are for a single-frequency technique using a frequency of 13.56 MHz. Mixed-frequency techniques may also be employed, using two or more separate frequencies (e.g., 2 MHz and 13.56 MHz). At step 240, the plasma is maintained for a period of time in order to deposit the film to a desired thickness, the thickness being related to the length of time the plasma is maintained. Table 1 summarizes the parameter ranges employed in the high-temperature process of the present invention. Table 2 sets forth the preferred ranges of these parameters. TABLE 1 Pressure: 2-8 Torr RF Power (density): 200-800 W (0.62-2.48 W/cm 2 ) Temperature: 400°C to 600°C Electrode Spacing: 200-600 mils SiH 4 flow rate: 10-500 seem N 2 flow rate: 100-5000 seem NH 3 flow rate: 0-5000 seem He flow rate (Optional): 500-3000 seem TABLE 2 (Preferred) Pressure: 5-7 Torr RF Power (density): 300-600 W (0.93-1.86 W/cm 2 ) Temperature: 500°C to 575°C Electrode Spacing: 300-600 mils SiH 4 flow rate: 20-100 seem N 2 flow rate: 2000-5000 seem NH 3 flo w rate : 10- 100 seem From Table 2, it is apparent that the preferred flow ratio of silane to nitrogen is between about 1:250 and about 1:20, and that the maximum preferred flow ratio of ammonia to nitrogen is about 1:20. By keeping the amount of silane within these ranges, hydrogen inclusion in the resulting film is kept to a minimum. This is because the amount of silane, which contains hydrogen, should only be enough to allow deposition of the film at an acceptable rate. Higher percentages engender hydrogen content at undesirably high levels. The maximum ratio of ammonia to nitrogen is also kept relatively low for this reason. As the amount of ammonia is increased, the hydrogen content of the resulting film increases as well. Thus, these flow ratios ensure that the hydrogen content remains low enough (e.g., at or near 10 atomic percent (at%)) to provide a good-quality silicon nitride film with the preferred characteristics outlined below. Low hydrogen content also provides higher etch selectivity with respect to oxide, which is especially important in etch stop applications. Moreover, the range of silane to nitrogen flow ratios employed herein improve plasma stability, thereby providing a more uniform film. III. Experimental and Simulation Results The high temperatures used in a process according to the present invention are critical in producing the high-quality films fabricated by that process. By using relatively high temperatures, hydrogen content is reduced. However, given contemporary thermal budgets, the maximum temperature employed in the process of the present invention is limited to about 600 °C. Conversely, film integrity begins to suffer (i.e. , delamination, cracking, and other such phenomena begin to occur) when a film of the present invention is deposited at process temperatures of below about 400°C. Thus, a temperature above about 400 °C and approaching about 600 °C is preferable. The use of such relatively high temperatures also mandates the use of a pedestal and support that are capable of withstanding such temperatures (e.g., a pedestal and support fabricated from a ceramic material). This reduction in hydrogen provides higher film quality (reduced cracking, delamination, and so on). Additionally, hydrogen content is reduced in the process of the present invention by minimizing the amount of ammonia used in the process, given that ammonia contains hydrogen and nitrogen does not. For example, experimental measurements were made using Nuclear Resonance Analysis on silicon nitride films deposited using an LPCVD process, a PECVD process, and the process of the present invention. The LPCVD process deposited a film having less than 3 at% hydrogen content. The PECVD process, at 400°C, deposited a film having a hydrogen content of about 20 at%, while at 480 °C, deposited a film having a hydrogen content of about 13 at% . A film deposited according to the process of the present invention exhibited a hydrogen content of about 10 at% . While not as low as the LPCVD process, the film's hydrogen content was significantly lower than that of the PECVD silicon nitride film, especially when the PECVD silicon nitride film was deposited at a lower temperature. The use of reduced silane flow rates is motivated by similar reasoning. Because silane also contains hydrogen, only the amount of silane required to deposit the film should be employed. However, this is in tension with the need to maximize throughput by maximizing the deposition rate. The inventors found that the flows rates described previously provided an acceptable balance between these competing concerns. The selectivity of these films with respect to oxide was also measured. A film deposited according to the process of the present invention and an LPCVD silicon nitride film had selectivities of at least 100. By contrast, the selectivity of the PECVD silicon nitride film with respect to oxide was about 80 and below, for films deposited at both 400°C and 480°C. Thus, for etch stop applications, such as self-aligned contacts and borderless contacts, a film according to the present invention will protect underlying layers better than a PECVD silicon nitride film, thereby allowing more accurate patterning of the layers involved. A film according to the present invention exhibits an etch selectivity to oxide comparable to that of an LPCVD silicon nitride film, although the etch selectivity of an LPCVD silicon nitride film may actually be higher. All etch selectivities described herein are in terms of the etch selectivity of the given nitride film with respect to oxide, as will be understood by one of skill in the art. Moreover, a process according to the present invention exhibits good process stability. For example, over a run of 5000 substrates, film thickness varied no more than 2% . For the same run, uniformity (% 1-s, 3mm EE) remained between 1 % and 1.5%, well below the 2% specified for an acceptable film of this type. The films' refractive index varied less than 0.01, remaining near 1.96. Film stress for the substrates in the run remained near 0.3xl0 9 dynes/cm 2 (compressive), varying only 0.3xl0 9 dynes/cm 2 (maximum - minimum). In another deposition process according to the present invention, the deposited film exhibited film stress on the order of lxlO 9 dynes/cm 2 to 1.5xl0 9 dynes/cm 2 (compressive). The wet etch rate (WER) of a film according to the present invention is between about 20 A/min and about 40 A/min (6: 1 BOE). Fig. 2B graphically illustrates this data. The data was generated using a DxZ chamber manufactured by Applied Materials, Inc., Santa Clara, California, configured to process 8 inch substrates and fitted with a ceramic pedestal. No wet cleaning steps, in which the vacuum seal of the chamber is broken and the processing chamber manually wiped down with cleaning fluid, or preventative maintenance operations were performed during the 5000 substrate run described herein. Certain of the film characteristics described herein may be altered by varying the process parameters used in the film's fabrication. This is illustrated in Fig. 2C, which includes a number of graphs generated by a computer simulation of a film deposited according to the present invention. These graphs show the relationship between various process parameters and various film characteristics. More specifically, the graphs show the effects of chamber pressure, RF power, electrode spacing, and various flow rates on film thickness, film uniformity, refractive index, and film stress. The following simulation results assume other parameters (e.g., deposition time) remain constant. As Fig. 2C illustrates, the simulations suggest that increases in pressure, RF power, electrode spacing, and, to a lesser extent, nitrogen flow rate cause a reduction in film thickness per unit time. Conversely, the simulations suggest that film thickness increases with an increase in the flow rate of silane or ammonia. The simulations suggest that film uniformity increase with increases in RF power, electrode spacing, and ammonia flow rate. The simulations also suggest that film uniformity decrease noticeably with increases in chamber pressure, but that it would be relatively unaffected by changes in nitrogen and silane flow rates. Increases in chamber pressure, RF power, and electrode spacing appear to cause a decrease in the resulting film's refractive index, while increases in the silane and ammonia flow rates appear to cause an increase in the refractive index. The simulations suggest that changes in nitrogen flow rate have little effect on the resulting film's refractive index, and that film stress changes little with changes in process gas flow rates. The simulations further suggest that film stress transition from tensile to compressive with increases in chamber pressure and electrode spacing, while increases in RF power cause the opposite result. These simulations support the inventors expectations and understanding of the process's characteristics. The simulations illustrate that a process according to the present invention can be expected to provide good film uniformity (variations in process parameters had little effect on film uniformity) and that such a process provides good control over film stress (evidenced by the effect of chamber pressure, electrode spacing, and RF power on film stress). These results are in accordance with the inventors' expectations and understanding of the process of the present invention. Thus, in comparison to a PECVD nitride film, a film according to the present invention provides better etch selectivity and greater control over film stress. Moreover, a film of the present invention exhibits good sidewall coverage. As to LPCVD nitride films, a film according to the present invention provides a workable thermal budget in situations where previously-formed layers are sensitive to the temperatures of subsequent processing steps. Again, a film according to the present invention provides greater control over film stress than an LPCVD nitride film, as well as compatibility with the metal layers that form interconnect. Moreover, a film according to the present invention also provides reduced backside deposition (deposition that occurs on the underside of the substrate), better process integration (due to the process's being a single step), greater mean time between cleanings, and higher deposition rates, when compared to an LPCVD nitride process. IV. Exemplary Multi-Layer Structures Because a high-temperature nitride film fabricated in accordance with the present invention has properties (e.g., etch selectivity and etch rate) that are comparable to those of LP nitride layers, such high-temperature nitride films can be substituted for LP nitride films in processes having a low thermal budget. For example, because the etch selectivity of high-temperature nitride films is comparable that of to LP nitride films, high-temperature nitride films can be substituted for LP nitride films as an etch stop layer when it is desirable to use a lower temperature nitride deposition step. Fig. 3 illustrates the use of a high-temperature nitride layer as an etch stop layer. First, the substrate to be processed is positioned within a PECVD chamber. The substrate will normally include structures requiring protection during subsequent etching steps. At step 300, a high-temperature nitride layer is deposited over the substrate utilizing the recipe described in Tables 1 and 2, and the steps depicted in Fig. 2A. Then, as shown in Fig. 3, an oxide layer is deposited over the substrate (step 310). A photoresist layer is applied over the oxide layer, and is then cured (step 320). The photoresist is then patterned (step 330), if necessary, utilizing standard photolithographic techniques. An etching apparatus is then used to etch away portions of the oxide layer (step 340). In areas where the high-temperature nitride layer underlies the oxide, etching stops when the high-temperature nitride layer is encountered because of that layer's relatively high etch selectivity to oxide. Figs. 4 A and 4B depict cross sections of a device before and after an etching step utilizing a high-temperature nitride layer 400 as an etch stop layer to create a structure referred to herein as a self-aligned contact, a structure well known to those of skill in the art. As shown in Fig. 4A, a mask 410 protects portions of a silicon oxide layer 420 during an etching operation. Prior to depositing high-temperature nitride layer 400, a polysilicon layer 430, a silicide layer 440 (protecting polysilicon layer 430), an oxide layer 445, and an oxide spacing layer (exemplified by oxide spacers 450(1), 450(2), 450(3), and 450(4)) are deposited. As the etching of the oxide layer proceeds, portions of silicon oxide layer 420 are removed. However, once reached, high-temperature nitride layer 400 inhibits further etching, thus protecting underlying layers. Fig. 4B illustrates the structure in Fig. 4 A after the etching process has completed. As noted, and as Fig. 4B illustrates, high-temperature nitride layer 400 prevents the etching of underlying layers. This allows the process to proceed until the exposed portions of silicon oxide layer 420 are completely removed, while avoiding over-etching that might damage underlying structures. An appropriate chemistry is then used to remove the now-exposed portions of high-temperature nitride layer 400. This chemistry is chosen such that structures underlying high-temperature nitride layer 400 are not affected (i.e., etched) by the etching step. Figs. 4C and 4D illustrate another use of the high-temperature nitride layer, the formation of a structure referred to herein as a borderless contact, also a structure well known to those of skill in the art. Figs. 4C and 4D depict cross sections of a device before and after an etching step utilizing a high-temperature nitride layer 455 as an etch stop layer to create a borderless contact. As shown in Fig. 4C, a mask 460 protects portions of a silicon oxide layer 470 during an etching operation. Prior to depositing high-temperature nitride layer 455, a polysilicon layer 480, a silicide layer 485 (protecting polysilicon layer 480), and an oxide spacing layer (exemplified by oxide spacers 490(1) and 490(2)) are deposited. High-temperature nitride layer 455 is also deposited over STI 495. As the etching of the oxide layer proceeds, portions of silicon oxide layer 470 are removed. However, once reached, high-temperature nitride layer 455 inhibits further etching, thus protecting regions below the nitride layer. Fig. 4D illustrates the structure in Fig. 4C after the etching process has completed. As noted, and as Fig. 4D illustrates, high-temperature nitride layer 455 prevents the etching of underlying layers. This allows the process to proceed until the exposed portions of silicon oxide layer 470 are completely removed, while avoiding over-etching that might damage underlying structures. An appropriate chemistry is then used to remove the now-exposed portions of high-temperature nitride layer 455. This chemistry would be chosen such that structures underlying high-temperature nitride layer 455 are not affected (i.e., etched) by the etching step. Yet another use of the high-temperature nitride layer is in the formation of a spacer. In processes for forming silicide electrodes in MOS or bipolar transistors, spacer layers can be utilized to precisely position the location of electrodes, lightly doped drains, or other structures. Figs. 5 A and 5B depict cross sections of a device during the formation of a spacer, for example, a logic device having a spacer formed of a high-temperature nitride material. In Fig. 5A, a polysilicon layer 500 and a silicide layer 510 are deposited over a substrate 520, in that order. Polysilicon layer 500 and silicide layer 510 may be patterned, for example, in order to form silicide electrodes. A high-temperature nitride layer 530 is deposited over the silicide electrodes. High-temperature nitride layer 530 may be deposited using a process recipe such as " that set forth in Table 1 or 2. In Fig. 5B, high-temperature nitride layer 530 is then etched by a process such as sputtering, for example. By etching anisotropically, the horizontal portions of high-temperature nitride layer 530 are removed, thus forming high-temperature nitride spacers 540(l)-540(4). Additional uses for the high-temperature nitride layer of the present invention include use as a lining layer in shallow trench isolation process and a lining layer for a premetal dielectric film. In the shallow trench isolation technique, isolation is provided by forming a recess or trench between two active areas upon which electronic devices are located. The trench is filled with an isolation material such as CVD oxide. The quality of the trench isolation process is improved if a nitride lining layer is deposited on the wall and base of the trenches prior to deposition of a conformal dielectric layer. Fig. 6 is a diagram depicting a cross-section of a substrate having a high-temperature nitride layer deposited as a lining layer for shallow trench isolation and Fig. 7 is a flow diagram depicting the steps of the process for forming such a lining layer. Referring to Figs. 6 and 7, shallow trenches 700 are first formed in a substrate 702 to isolate islands 704 between trenches 700 (step 800). A high-temperature nitride lining layer 706 is then formed. Deposition of high-temperature nitride lining layer 706 begins with the flowing of process gases into the substrate processing system's processing chamber (step 810). Such gases may include silane and nitrogen, for example. At step 820, environmental parameters within the processing chamber are set. This includes setting the pressure and temperature within the processing chamber to an acceptable level. For example, a pressure of between about 2 Torr and about 8 Torr at a temperature between about 400 °C and about 600 °C may be used to produce a film according to the present invention. At step 830, energy is applied to the process gases in order to allow the reaction forming high-temperature nitride lining layer 706 to proceed. This could be RF or microwave energy, for example, the application of which would be maintained until high-temperature nitride lining layer 706 was deposited to an acceptable thickness (step 840). Active devices are then formed over high-temperature nitride lining layer 706 (step 850). III. Exemplary Transistor Structure Fig. 8 illustrates a simplified cross-sectional view of an integrated circuit 800, which may be made in accordance with the present invention. As shown, integrated circuit 800 includes an NMOS transistor 803 and a PMOS transistor 806, which are separated and electrically isolated from each other by a field oxide region 820 formed by local oxidation of silicon (LOCOS), or other technique. Alternatively, transistors 803 and 806 may be separated and electrically isolated from each other by trench isolation (not shown) when transistors 803 and 806 are both NMOS or both PMOS. Each transistor 803 and 806 comprises a source region 812, a drain region 815 and a gate region 818. A premetal dielectric (PMD) layer 821 separates transistors 803 and 806 from a metal layer 840 with connections between metal layer 840 and the transistors made by contacts 824. Metal layer 840 is one of four metal layers, 840, 842, 844 and 846, included in integrated circuit 800. Each of metal layer 840, 842, 844, and 846 is separated from adjacent metal layers by respective inter-metal dielectric (IMD) layers 827, 828, or 829. Adjacent metal layers are connected at selected openings by vias 826. Deposited over metal layer 846 is a planarized passivation layer 830. A pre-metal dielectric layer (e.g., PMD 821) may be formed according to the present invention by depositing a dielectric layer over a high-temperature nitride layer. For example, in Fig. 8, PMD 821 comprises a boron phosphate silicon glass (BPSG) layer 850 deposited over a high-temperature nitride lining layer 851. Fig. 9 is a flow diagram depicting the steps of the process for forming such a PMD. Referring to Figs. 8 and 9, deposition of high-temperature nitride lining layer 851 is begun by flowing deposition gases such as silane and nitrogen into the processing chamber (step 1000). Environmental parameters in the processing chamber are then , set to the desired levels (step 1010). For example, a pressure of between about 2 Torr and about 8 Torr, and a temperature of between about 400 °C and about 600 °C may be maintained within the processing chamber. In a process using silane and nitrogen, such as that described in Table 2, a pressure of between about 5 Torr and about 7 Torr, and a temperature of between about 500 °C and about 575 °C are preferably maintained within the processing chamber. Energy is then applied to the process gases at step 1020 in order to initiate the chemical reaction that deposits high-temperature nitride lining layer 851. For example, RF energy may be applied to create a plasma from the process gases. The application of energy is maintained (step 1030) in order to deposit high-temperature nitride lining layer 851 to a desired thickness. A dielectric layer, such as BPSG layer 850 is then deposited over high-temperature nitride lining layer 851 (step 1040). It should be understood that simplified integrated circuit 800 of Fig. 8 is presented for illustrative purposes only. One of ordinary skill in the art could implement the present invention in relation to fabrication of other integrated circuits such as microprocessors, application-specific integrated circuits (ASICs), memory devices, and the like. Further, the present invention may be applied to fabrication of PMOS, NMOS, CMOS, bipolar, or BiCMOS devices, among others. The invention has now been described with reference to the preferred embodiments. Variations and substitutions will now be apparent to persons of skill in the art. In particular, although the process parameters have been described for a specific process chamber and substrate size the scaling of the process to different chambers and substrate sizes is well understood and the flow rate ratios described herein are easily scalable. Accordingly, it is not intended to limit the invention except as provided by the appended claims.

Claims: WHAT IS CLAIMED IS: 1. A process for depositing a silicon nitride layer in a vacuum chamber comprising: flowing process gases including a first process gas and a second process gas into the vacuum chamber, wherein said first process gas is silane and said second process gas is nitrogen; maintaining a pressure in the vacuum chamber of greater than about 2 Torr and less than about 8 Torr; generating a plasma in the vacuum chamber from said process gases; maintaining a temperature in the vacuum chamber of greater than about 400°C and less than about 600°C; and maintaining said plasma in the vacuum chamber in order to deposit a silicon nitride layer. 2. The process of claim 1 wherein the step of flowing process gases further comprises: maintaining a flow rate of said first process gas between about 20 seem and about 500 seem; and maintaining a flow rate of said second process gas between about 100 seem and about 5000 seem. 3. The process of claim 1 wherein a flow ratio between said first process gas and said second process gas is maintained at between about 1 :250 and about 1:20. 4. The process of claim 1 wherein the step of supplying process gases further comprises: maintaining a flow rate of said first process gas between about 20 seem and about 100 seem; and maintaining a flow rate of said second process gas between about 1000 seem and about 5000 seem. 5. The process of claim 1 wherein the process gases further comprise a third process gas, wherein said third process gas is ammonia. 6. The process of claim 5 wherein the step of flowing process gases into the vacuum chamber further comprises the steps of: maintaining a flow rate of said first process gas between 20 seem and 500 seem; maintaining a flow rate of said second process gas between about 100 seem and about 5000 seem; and maintaining a flow rate of said third process gas between about 1 seem and about 5000 seem. 7. The process of claim 5 wherein a flow ratio between said third process gas and said second process gas is maintained at less than about 1:20. 8. The process of claim 5 wherein the step of flowing process gases into the vacuum chamber further comprises the steps of: maintaining a flow rate of said first process gas between about 20 seem and about 100 seem; maintaining a flow rate of said second process gas between about 1000 seem and about 5000 seem; and maintaining a flow rate of said third process gas between about 1 seem and about 100 seem. 9. The process of claim 8 further comprising the steps of: maintaining said pressure between about 5 Torr and about 7 Torr; and maintaining said temperature between about 500 °C and about 575 °C. 10. The process of claim 1 wherein the process gases further comprise a third and a fourth process gas, wherein said third process gas is ammonia and said fourth process gas is helium. 11. The process of claim 10 wherein the step of flowing process gases into the vacuum chamber further comprises the steps of: maintaining a flow rate of said first process gas between about 20 and about 100 seem; maintaining a flow rate of said second process gas between about 100 and about 5000 seem; maintaining a flow rate of said third process gas between about 1 and about 5000 seem; and maintaining a flow rate of said fourth process gas between about 500 and about 3000 seem. 12. The process of claim 11 further comprising the steps of: maintaining said pressure between about 5 Torr and about 7 Torr; maintaining said temperature between about 500 °C and about 575 °C; and maintaining said plasma by applying RF energy at an RF power density of between about 0.93 W/cm 2 and about 1.86 W/cm 2 . 13. A process for fabricating a semiconductor device on a substrate having a major surface including structures to be protected from etchant solutions, the substrate disposed in a vacuum chamber, said process comprising the steps of: flowing process gases including a first process gas and a second process gas into the vacuum chamber, wherein said first process gas is silane and said second process gas is nitrogen; maintaining a pressure in the vacuum chamber of greater than about 2 Torr and less than about 8 Torr; generating a plasma in the vacuum chamber from the process gas; maintaining a temperature in the vacuum chamber of greater than about 400°C and less than about 600°C; maintaining said plasma in the vacuum chamber in order to deposit a silicon nitride layer over the major surface; forming an oxide layer over said silicon nitride layer; forming a mask over said oxide layer; patterning said mask; etching said oxide layer by exposing exposed portions of said oxide layer to an etching environment; and protecting underlying portions of the major surface by leaving at least a portion of said silicon nitride layer. 14. The process of claim 13 wherein the process gases further comprise a third process gas, wherein said third process gas is ammonia, and a flow ratio between said third process gas and said second process gas is maintained at less than about 1:20. 15. The process of claim 14 further comprising the steps of: maintaining said pressure between about 5 Torr and about 7 Torr; maintaining said temperature between about 500 °C and about 575 °C; and maintaining said plasma by applying RF energy at an RF power density of between about 0.93 W/cm 2 and about 1.86 W/cm 2 . 16. A method for forming a silicon nitride spacer on a substrate having at least one feature, the substrate disposed in a vacuum chamber, said process comprising the steps of: flowing process gases including a first process gas and a second process gas into the vacuum chamber, wherein said first process gas is silane and said second process gas is nitrogen; mamtaining a pressure in the vacuum chamber of greater than about 2 Torr and less than about 8 Torr; generating a plasma in the vacuum chamber from the process gas; maintaining a temperature in the vacuum chamber of greater than about 400°C and less than about 600°C; maintaining said plasma in the vacuum chamber in order to deposit a silicon nitride layer over at least said feature; and patterning said silicon nitride layer to form at least one silicon nitride spacer on said feature. 17. The process of claim 16 wherein the process gases further comprise a third process gas, wherein said third process gas is ammonia, and a flow ratio between said third process gas and said second process gas is maintained at less than about 1:20. 18. The process of claim 17 further comprising the steps of: maintaining said pressure between about 5 Torr and about 7 Torr; maintaining said temperature between about 500 °C and about 575 °C; and maintaining said plasma by applying RF energy at an RF power density of between about 0.93 W/cm 2 and about 1.86 W/cm 2 . 19. A process for fabricating a semiconductor device on a major surface of a substrate disposed in a vacuum chamber, said process comprising the steps of: forming at least one trench, having a bottom and sides, in said major surface; flowing process gases including a first process gas and a second process gas into the vacuum chamber, wherein said first process gas is silane and said second process gas is nitrogen; maintaining a pressure in the vacuum chamber of greater than about 2 Torr and less than about 8 Torr; generating a plasma in the vacuum chamber from the process gas; maintaining a temperature in the vacuum chamber of greater than about 400°C and less than about 600°C; and maintaining said plasma in the vacuum chamber in order to deposit a silicon nitride layer, a portion of said silicon nitride layer forming a lining layer over said bottom and said sides of said trenches. 20. The process of claim 19 wherein the process gases further comprise a third process gas, wherein said third process gas is ammonia, and a flow ratio between said third process gas and said second process gas is maintained at less than about 1:20. 21. The process of claim 20 further comprising the steps of: maintaining said pressure between about 5 Torr and about 7 Torr; and maintaining said temperature between about 500 °C and about 575 °C. 22. A process for fabricating a semiconductor device on a substrate having a major surface including an active device formed thereon, the substrate disposed in a vacuum chamber, said process comprising the steps of: flowing process gases including a first process gas and a second process gas into the vacuum chamber, wherein said first process gas is silane and said second process gas is nitrogen; maintaining a pressure in the vacuum chamber of greater than about 2 Torr and less than about 8 Torr; generating a plasma in the vacuum chamber from the process gas; maintaining a temperature in the vacuum chamber of greater than about 400 ° C and less than about 600 ° C ; maintaining said plasma in the vacuum chamber in order to deposit a silicon nitride layer over the major surface including said active device formed thereon; and forming a premetal dielectric layer over said silicon nitride layer. 23. A substrate processing system, the system comprising: a chamber; a substrate holder disposed within the chamber for holding a substrate; an electrode disposed within the chamber; a substrate heating system for heating the substrate; a gas distribution system, coupled to the chamber, for providing process gases to the chamber; an RF power supply coupled to the electrode for supplying RF energy to induce a plasma; a vacuum system for reducing the pressure in the chamber; a system controller, including a computer for controlling the gas distribution system, the RF power supply, the substrate heating system and the vacuum system; and a memory coupled to the controller comprising a computer usable medium having a computer readable program code means embodied therein for directing operation of the substrate processing system, the computer readable program code means including: computer instructions for causing the vacuum system to stabilize the pressure in the vacuum chamber to a process pressure of greater than about 2 torr and less than about 8 torr; computer instructions for causing the substrate heating system to heat the substrate to a process temperature greater than about 400 °C and less than about 600 °C; and computer instructions for causing the gas distribution system to flow a first process gas including silane and nitrogen into the vacuum chamber and to cause the RF power supply to induce the formation of a plasma to deposit a layer of silicon nitride over the substrate.

Inventors: CHEUNG DAVID, HUANG JUDY, YAU WAI-FAN, CHEUNG, DAVID, HUANG, JUDY, YAU, WAI-FAN
Applicants: APPLIED MATERIALS INC, APPLIED MATERIALS, INC.
Application year: 1999
Main classification: H01L21
IPC codes: C23C16, H01L21