TEMPERATURE COMPENSATION ARRANGEMENT AND CURRENT REFERENCE CIRCUIT

Abstract: A temperature compensation arrangement is provided for a current reference circuit. The current reference circuit has a voltage generator coupled to provide a voltage to a resistor, which generates a current in dependence upon the voltage. The arrangement includes a current source, arranged to be controlled by a control voltage from the voltage generator, and a diode arrangement coupled in series with the current source for deriving therefrom a control voltage. A compensating transitor is coupled to receive the control voltage for providing a temperature compensating supplemental current which is combined with the reference current to produce a combined current. The diode arrangement and the compensating transistor are arranged such that the combined current is substantially temperature independent.

Description: TEMPERATURE COMPENSATION ARRANGEMENT AND CURRENT REFERENCE CIRCUIT Field of the Invention This invention relates to temperature compensation arrangements and particularly but not exclusively to temperature compensation arrangements for current reference circuits. Background of the Invention A current source may be typically used in a semiconductor device such as a Metal Oxide Semiconductor (MOS) analogue device, for providing a DC current. The DC current is typically generated by providing a generated voltage to a resistor, which then derives a current in the resistor. The magnitude of the current is determined by the voltage and the properties of the resistor. There is a known problem with current sources in which the generated voltage is a constant voltage or is provided, for example, by a Bandgap reference circuit (as described in K.Kuijk: A Precision Reference Voltage Source, IEEE Journal of Solid-State Circuits, Vol. 8, No. 3. June 1973, pp. 222-6). The properties of the resistor typically define a monolithically changing current with respect to temperature, where the derivative of the current versus temperature is zero only under special conditions. If the generated voltage is described by V=kT/q where T is the absolute temperature and k and q are constants, and if the resistor is described by R=R0[1+A(T-T0)], where RO is the resistor value at room temperature and TO and A are its temperature coefficient, the current driven through the resistor will be: I=(kT/q)/{R0[l+A(T-T0)]} (1) The first derivative of the current versus temperature will be:- dI/dT-(k/qR0)( 1 - ATO)/ { [ 1 +A(T-T0)] 2 } (2) showing that at temperature TO the value of dl/dT is equal to zero only if A is equal to 1/TO. This means that to realise a temperature independent current source the temperature coefficient of the resistor has to be 1/TO, a condition which can be fulfilled only in special cases where the used technology allows for adjusting the temperature coefficient A. A known alternative approach, as described in H.Oguey, D.Aebischer: CMOS Current Reference Without Resistance, IEEE Journal of Solid-State Circuits, Vol. 32, No. 7, July 1997, pp. 1132-5, uses a MOS transistor instead of a resistor to generate the current, but again the resulting current is dependent on temperature. The present invention seeks to provide a temperature compensation arrangement and method which mitigates the above mentioned disadvantage. Summary of the Invention According to the present invention there is provided a temperature compensation arrangement for a current reference circuit having a voltage generator coupled to a resistor for generating a reference current therethrough, the arrangement comprising: a current source, arranged to be controlled by a control voltage from the voltage generator; a diode arrangement coupled in series with the current source for deriving therefrom a control voltage; and, a compensating transistor coupled to receive the control voltage for providing a temperature compensating supplemental current which is combined with the reference current to produce a combined current; wherein the diode arrangement and the compensating transistor are arranged such that the combined current is substantially temperature independent. Preferably the current source is arranged to provide a substantially constant current. The voltage generator preferably comprises a current mirror arrangement which is arranged to drive the current source. Preferably the current mirror provides a current which is proportional to the combined current. The diode arrangement preferably comprises at least two diode coupled transistors in series arrangement. In this way a current reference circuit is provided in which temperature dependent effects associated with the resistor are substantially eliminated. Brief Description of the Drawing An exemplary embodiment of the invention will now be described with reference to the single figure drawing which shows a preferred embodiment of a temperature compensation arrangement in accordance with the invention. Detailed Description of a Preferred Embodiment Referring to the single figure drawing, there is shown a current reference circuit 5, comprising a voltage generator circuit 10, a start-up circuit 20, a control circuit 30, a resistor 40 and a compensating transistor 50. The voltage generator circuit 10 has a first current mirror provided by a pair of PMOS transistors 12 and 14, having source terminals coupled to receive a supply voltage, gate terminals coupled to the drain of transistor 14 and to a mirroring node 15, the drain of transistor 12 being coupled to an intermediate node 17. The voltage generator circuit 10 also has a second pair of NMOS transistors 16 and 18, transistor 16 having its drain connected to the intermediate node 17 to receive current from the drain of transistor 12, transistors 16 and 18 having gate terminals connected to the drain terminal of transistor 16, transistor 18 having drain terminal connected to the drain terminal of transistor 14 and to the mirroring node 15 and having its source terminal connected to an output node 45. The resistor.40 is coupled between output node 45 and ground, for producing a reference current in dependence upon the voltage supplied by the source terminal of transistor 18. The start-up circuit 20 is arranged to provide a start-up current to excite the voltage generator circuit 10 from a stable quiescent state to a stable non-quiescent state. A first PMOS transistor 22 of the start-up circuit has a source terminal coupled to the supply voltage, a gate terminal coupled at least indirectly to ground and a drain terminal connected to the drain and to the gate terminals of a second NMOS transistor 24 whose source terminal is coupled to ground. A third NMOS transistor 26 of the start-up circuit 20 has a drain terminal coupled to the mirroring node 15 of the voltage generator circuit 10, a gate terminal coupled to the gate terminal of transistor 24 and a source terminal coupled to ground. In this way an initial current is supplied to the mirroring node 15 of the voltage generator circuit 10 via first, second and third transistors 22, 24 and 26, respectively. The gate terminal of transistor 22 ist connected to control node 33. In an alternative embodiment, (not shown) this terminal is connected to ground. The control circuit 30 has first and second NMOS transistors 36 and 34 both arranged in a diode configuration, transistor 36 having its source terminal coupled to ground, and having gate and drain terminals connected together and to the source of second NMOS transistor 34. The gate and drain terminals of the NMOS transistor 34 are both connected to a control node 33 and to the drain of third PMOS transistor 32 whose source terminal is coupled to receive the supply voltage and whose gate terminal is connected to mirroring node 15 of the voltage generator circuit 10. The fourth NMOS transistor 38 of the control circuit 30 has its source terminal connected to ground, its gate terminal connected to the gate terminal of transistor 36 and its drain terminal connected to the gate of second transistor 24 of the start-up circuit. In this way, once the initial current has been supplied to the mirroring node 15 of the voltage generator circuit 10, the third transistor 32 begins to conduct turning on transistors 34, 36 enabling transistor 38 to switch off transistors 24 and 26. Therefore the start-up circuit 20 acts as a choke, providing an initial current to excite the voltage generator circuit 10, the initial current being removed once the voltage generator 10 is operating. The compensating transistor 50 has a source terminal coupled to ground, a drain terminal coupled to node 45 and a gate terminal coupled to receive a supplementary control voltage from the control node 33 of the control circuit 30. Once start-up has been initiated, a current continues to flow through transistors 32, 34 and 36. The NMOS transistors 34 and 36 have large and short channels, therefore the voltage on control node 33 is approximately 2Vt, where Vt is the threshold voltage of the NMOS transistors. The control voltage of approximately 2Vt is fed to the gate terminal of the compensating transistor 50. The compensating transistor provides, in dependence upon the voltage received at its gate terminal, a temperature compensating supplemental current. This supplemental current is combined with the reference current to produce a combined current. The resistor 40 and the compensating transistor are arranged such that the combined current is substantially temperature independent. A suitable arrangement is achieved as follows:- As described by Oguey and Aebischer, the voltage on output node 45 will be V45=NkT/q where k, T and q have the meaning as defined above and where N depend on the geometry ratio of transistors 12, 14, 16, 18. The current through resistor 40 will be I40=V45/R40 where R40 is the value of resistor 40. The drain current 150 of compensating transistor 50 can be expressed by:- I50=K50(V33- Vt) 2 (3) where V33 is approximately equal to 2Vt and K50 is the current factor of transistor 50 determined by its geometry ratio and by the MOS technology. The combined current flowing through transistor 18 will be 1=140+150. The temperature dependence of the threshold voltage of MOS transistors can be described by Vt=VtO[l+B(T-TO)], that of the current factor K by K=K0(T-T0)m. Typical values for temperature coefficients are: A=0.0024, B=nl.4, m=1.83. Combining the equations describing the currents through resistor 40 and through compensating transistor 50 and taking into account temperature coefficients A, B and m, the temperature coefficient dl/dT of the combined current I at a temperature TO can be expressed as:- dl/dT | T0=k/q[(l-AT0)/R0+2K3Vt0(l-m+BT0)] (4) This equation shows that the circuit in agreement with the invention allows to chose dI/dT=0 at temperature TO even if the value of A is not equal to 1/TO. The resulting current I will now be temperature independent if:- K3=(AT0-l)/[2Vt0R0(l-m+BT0)]. (5) The resulting current factor K3=7.9E-6 A/V2 for the typical temperature coefficients shows that the value for K3 is well compatible with currently used MOS technologies. It will be appreciated that alternative embodiements to the one described above are possible. For example, the start-up circuit 20 and the voltage generator circuit 10 may differ in detail from the embodiment shown in the single figure drawing. Furthermore, the substantially temperature independent combined current could be reproduced by further current mirrors controlled by the voltages on nodes 17 or on the drain terminal of transistor 36 if NMOS transistors form the current or by the voltage on control node 15 if PMOS transistors are involved.

Claims: Claims 1. A temperature compensation arrangement for a current reference circuit having a voltage generator coupled to a resistor for generating a reference current therethrough, the arrangement comprising: a current source, arranged to be controlled by a control voltage from the voltage generator; a diode arrangement coupled in series with the current source for deriving therefrom a control voltage; and, a compensating transistor coupled to receive the control voltage for providing a temperature compensating supplemental current which is combined with the reference current to produce a combined current; wherein the diode arrangement and the compensating transistor are arranged such that the combined current is substantially temperature independent. 2. The arrangement of claim 1 wherein the current source is arranged to provide a substantially constant current. 3. The arrangement of claim 1 or claim 2 wherein the voltage generator comprises a current mirror arrangement which is arranged to drive the current source. 4. The arrangement of claim 3 wherein the current mirror provides a current which is proportional to the combined current. 5. The arrangement of any preceding claim wherein the diode arrangement comprises at least two diode coupled transistors in series arrangement. 6. A current reference circuit, comprising a temperature compensating arrangement as claimed in any preceding claim, and further comprising a start-up circuit arranged to provide a start-up current for the current reference circuit, wherein the current source and the diode arrangement form part of the start-up circuit.

Inventors: RUSZNYAK ANDREAS, RUSZNYAK, ANDREAS
Applicants: MOTOROLA INC, RUSZNYAK ANDREAS, MOTOROLA INC., RUSZNYAK, ANDREAS
Application year: 1999
Main classification: A61M15
IPC codes: G05F3