DATA CONVERSION HARDWARE SUPPORT

Abstract: To achieve a highly efficient update of software in computer based systems, there is provided a software processing system comprising two partitions (A, B) that are connected through a linking means (24). The two partitions (A, B) are adapted to update a state of new software in one memory means (12) to the sate of old software in the other memory means (32) during the execution of the old software. In particular, the transfer of data from old software to new software is supported by a data conversions support device (50) adapted to output the start address of a conversion program being related to a data variable to be converted.

Description: Data Conversion Hardware Support FIELD OF INVENTION The present invention relates to data conversion hardware support and in particular to data conversion hardware support for use in a state copying method for software upgrade. BACKGROUND OF INVENTION In performing the update of software there is usually some kind of disturbance to the operation of the system being updated. This disturbance can range from a total system shutdown during hours and possible days to a short disruption of possibly only some limited part of the total functionality of the system, e.g., a few seconds. Conceivably, there may be no disturbance at all although this is typically not the case in real existing systems. However, for systems like communication exchanges, it is of great importance that any disturbance is small and as short as possible. To achieve a disturbance-free update of software even with permanently long executing software modules it is a prerequisite that new software is updated with all necessary data from the old software while the old software is continuously executed. When data of new software has reached the same state as data of old software the new software takes over execution. The simplest method to update software is to stop the execution of old software, load new software, and finally to start the new software. Using this method no data is transferred between the old software and the new software. Further, all established software processes are lost and the execution of software is stopped during the load and start of the new software. Usually, this method is used, e.g., for workstations and personal computers. An improved approach for a communication system has been described in "Remote upgrading and updating of AXE 10 software", page 66, 67 Ericsson Review No. 2, 1996. Here, the new software is loaded while the old software is still handling establishment of services provided to subscribers. Data is transferred between old software and new software. Data variables containing data to be transferred are identified in so-called data change information and can either be of the type copy or convert. For each convert data variable a conversion program specified in the data change information is executed to achieve the transformations and to transfer the conversion output to the new software. However, during the transfer of the data necessary for already established services from the old software to the new software the establishment of additional services is stopped. A hardware structure underlying the approaches so far is shown in Fig. 16. To enable the continuous execution of old software while new software is loaded the system architecture is partitioned into an A-side and a B-side. The A-side comprises a first processing and control unit 10 and a first memory partition 12. The memory partition 12 stores data and software modules which are executed in and controlled through the processing and control unit 10. For the interchange of data and software information there is provided an address bus 14 and a data bus 16 that are controlled by a data address bus control unit 18. This data address bus control unit 18 is connected to the processing and control unit 10 via a data-address bus control line 20. Further, there is provided an update bus control unit 22 that links the address bus 14 and the data bus 16 with an external update bus 24 provided for the update of software. The update bus control unit 22 is connected to the processing control unit 10 via an update bus control line 26 for control. Also an option is to forward, copy/conversion information being related to data transferred via the update bus 24 to the update bus control unit 22 via a copy/convert data line 28. As shown in Fig. 16, the same structure as explained with respect to the A-side also applies to the B-side. Therefore, at the B-side there is provided a second processing and control unit 30 and a second memory partition 32. The second processing control unit 30 and the second memory partition 32 are connected by a second address bus 34 and a second data bus 36 both being controlled by a second data address bus control unit 38. This second data bus control unit 38 is connected to the second processing and control unit 30 via a second data/address bus control line 40. To achieve the external exchange of data there is provided a second update bus control unit 42 that is connected to the second processing and control unit 30 via a second update bus control line 44. Copy/convert data to be transferred to and from the A/B-side, respectively, is forwarded to the second update bus control unit 42 via a second copy/convert data line 46. s shown in Fig. 16, this bipartitioned architecture allows for further execution of old software while the new software is loaded and data variables containing data to be transferred are copied and converted either from the A-side to the B-side or vice versa. However, a problem with this approach is that the overall system characteristics are deteriorated during the update of the software. In particular, usually during the transfer of data, services are stopped in order to get a consistent copy of data in the old software and the new software. A further disadvantage with respect to the bipartitioned architecture shown in Fig. 16 is that there is no dedicated hardware support for data conversion. Therefore, the software based conversion of data may become time-consuming and lead to increased system downtimes and thus to a loss of revenues to the service provider using this hardware structure. To overcome this drawback in US-A-5, 155, 837 it is proposed to switch the input of data for new services to the new software in a first step. When services in progress on the basis of the old software have all been finished, the output of data from these services in progress is then switched from the old software to the new software. Therefore, services being related to the old software must be finished before the new software is operative and in consequence it is only possible to handle services with a short duration. Also, data conversion hardware support is not disclosed in US-A- 5,155,837. SUMMARY OF INVENTION In view of the above, the object of the invention is to achieve a highly efficient update of software in computer based systems. According to the present invention, this object is achieved through a software processing system of the partitioned type, comprising: a first partition with a first memory means, a second partition with a second memory means, wherein the first partition and the second partition are connected through a linking means and adapted to update a state of new software in one memory means to the state of old software in the other memory means during execution of old software, and the transfer of data from old software to new software is supported by a data conversion support device adapted to output the start address of a conversion program being related to a data variable to be converted. Therefore, the present invention provides a hardware implementation to achieve the necessary transfer and conversion of data being related to old software and new software during the update of software in computer based systems, e.g., an updating due to added functionality and/or due to correction of faults. Further according to the present invention there is provided an access means adapted to a translation storage means to determine the storage address of predetermined data values in a memory device, the data values being optionally (in a special case) stored in a sorted order at storage addresses according to a binary tree data structure of nodes, branches, subtrees and leafs, comprising a reading out means for reading out a data value at a current search address of the memory device, a comparison means for comparing the read out data value with the data value to be searched to determine whether the read out data value is greater or smaller than the data value to be searched, and determining means for determining a complete next search address to be searched for the data value on the basis of the comparison result and the current search address, wherein the reading out means, the comparison means and the determining means carry out recursively the reading out, the comparing, and the determining until the read out data value matches the data value to be searched within a predetermined tolerance. Thus the access means according to the special case differs significantly from conventional methods that use the storage intensive pointer scheme for deciding on the address of a node in the binary tree. In particular, during a traversal of the binary tree the most significant part of the address changes in every step during the traversal to the binary tree. This would be time consuming with a typical DRAM with a row/column addressing scheme, where the row corresponds to the most significant and the column to the least significant part of the address. To the contrary the present invention provides an access means and a related a method to determine the storage address of a pre-determined data value in a memory device without use of pointers for determining storage locations during the binary tree search. Also the access means can determine the storage address faster than known methods. Essentially, according to the present invention it was realized that there is no necessity to perform the frequent changes in the most significant part of the address, and that both the column part of the address and the row address part of the address are determined on the basis of the comparison result and the current address. In the present invention, the combination of the column address part of the mapping and the row address part of the mapping allows to decrease the search time until a data value is located in the memory. According to the present invention, when a leaf in a subtree is reached during the search, a new root node of another subtree is determined. If in this subtree the data value is still not found, the search procedure goes from the leaf node in the present subtree to yet another root node of another subtree - until a bottom leaf of the complete tree is arrived at. Since a search always means a traverse of the tree from the top to the bottom the search will mainly result in traverses inside subtrees. Just a minimum number of steps will result in a change of subtrees. As a result of the mapping according to the invention, only the column address changes during a traverse inside a subtree. Hence, the number of steps that result in a change of row address is minimized, i.e. the changes in the row address are kept to a minimum. Therefore, the time for a search will be reduced considerable. BRIEF DESCRIPTION OF FIGURES Preferred embodiments of the present invention will be described with reference to the appended drawing in which Fig. 1 shows the architecture of the data conversion hardware support device according to the present invention; Fig. 2 shows different steps of the state copying method being supported through the data conversion hardware support device according to the present invention; Fig. 3 shows a flow diagram according to the state copying method illustrated in Fig. 2; Fig. 4 shows the architecture of the translation table storage unit shown in Fig. 1; Fig. 5 shows a memory device of the matching unit shown in Fig. 1 in which data values are stored randomly at specific address positions; Fig. 6 shows a logical binary tree structure used for performing a binary tree search in the memory device of the matching unit shown in Fig. 1; Fig. 7 shows a binary tree structure using subtrees according to the present invention; Fig. 8 shows a memory device where each row is mapped onto a subtree shown in Fig. 7; Fig. 9 shows the organization of data in the subtree shown in Fig. 8; Fig. 10 is a flowchart illustrating the search method used by the matching unit for the special case of using a binary tree structure according to the present invention; Fig. 11 shows an example of data values stored in a memory according to a binary tree structure; Fig. 12 shows the binary tree and the respective location of nodes corresponding to the example in Fig. 11; Fig. 13 shows an embodiment of the access means according to the present invention for accessing data values stored in the translation table storing unit shown in Fig. 1; Fig. 14 shows an example for the inverse address calculation executed through the inverse address calculation unit shown in Fig. 1; Fig. 15 shows another example for the inverse address calculation executed through the inverse address calculation unit shown in Fig. 1; Fig. 16 shows an architecture for a software processing system of the partitioned type according to the technological background of the invention and Fig. 17 shows additions to the algorithm illustrated in Fig. 10 in order to get exit conditions according to eq. (13) . DESCRIPTION OF PREFERRED EMBODIMENTS Fig. 1 shows the basic architecture .for the data conversion hardware support according to the present invention. Parts resembling or being identical to those previously described with respect to Fig. 16 are denoted with the same reference numerals and their description will be omitted here. As shown in Fig. 1, the data conversion hardware support architecture differs over previously known approaches in that there is provided a dedicated conversion support unit 50. Here, the conversion support unit 50 may be a separated unit or duplicated according to the different partitions A, B of the software processing system, i.e. the A-side and B-side, respectively. The conversion support unit 50 comprises a conversion queue unit 52, a translation table storing unit 54, a matching unit 56, and an inverse address calculation unit 58. As shown in Fig. 1, addresses of data variables to be converted in the conversion support unit 50 are supplied thereto via an address input line 60 that is connected both to the A-side at a point 62 and the B-side partition at a point 64. The address supplied to the conversion support unit 50 is stored in the conversion queue unit 52. This conversion queue unit 52 buffers transferred addresses of data variables and may, e.g., be implemented with a dynamic RAM memory. Further, in case there is a need to temporarily stop the storing of new data into the queue when the conversion queue unit 52 is filled a backpressure signal is transmitted from the conversion queue unit 52 either to the first update bus control unit 22 at the A-side via a first backpressure signal line 66 or to the second update control bus unit 42 via a second backpressure signal line 68. As shown in Fig. 1, the conversion support unit 50 further comprises the translation table storing unit 54 that comprises an entry for each address that may eventually be transferred to the conversion queue unit 52. The entry allows to derive information with respect to the data structure and conversion software being related to the address in the conversion queue unit 52. Therefore, once the address is supplied to the translation table storing unit 54 the output of the translation table according to the address supplied thereto will be DWA: Start address of the data structure being related to the address supplied to the translation table storage unit 54; DINFO: Structural information about the variable necessary for inverse address calculation and/or conversion; and PA: Address to the conversion program for the variable. Therefore, a first step carried out by the conversion support unit 50 is to find an entry in the translation table storing unit 54 corresponding to an address taken from the conversion queue unit 52. To implement the search in the translation table storing unit 54 efficiently there is provided a matching unit 56 wherein the search in the translation table is realized as search for the highest DWA lower than or equal to the given address supplied from the conversion queue unit 52 via an address supply line 60. In particular, in a special case a matching unit 56 implements the search using a binary tree as will be explained in the following in more detail with respect to Fig. 5 to 12. As soon as the address of the data variable to be converted and information with respect to the related data structure is available it is supplied to the inverse address calculation unit 58 via an address supply line 70, a DWA supply line 72 and a DINFO supply line 74. Using this information the inverse address calculation unit 58 derives additional information with respect to the variable to be converted, e.g., the index in an array or the indices for a matrix. Generally, the result may consist of N indices that are supplied either to an A-side or a B-side via offset supply lines 76-1, ..., 76-N, respectively. Also, the address of the conversion program effective to actually carry out the conversion in either the first processing control unit 10 or the second processing and control unit 30 is supplied thereto via a conversion program address line 78 shown in Fig. 1. As shown in Fig. 1, the data conversion hardware support uses the update bus 24. Here, the address is transferred between the A-side and the B-side or vice versa. The address is used to write into the updated loaded memory partition 32 or 12, respectively. At each side there is provided arbitration logic (not shown) for memory partition access as there are independent users of the memory partition at the side to be updated. In case a delayed start of conversion programs is desired, according to the present invention the conversion support unit 50 may also comprise an associated buffer unit (not shown) that may be added to store the result of translation achieved through the matching unit 56 and the inverse address calculation unit 58. In this case the associated buffer unit delays the actual start of the conversion program. If the associated buffer unit never stores the same entry twice it may be guaranteed that the same conversion will not be started several times during a prespecified delay interval. Using the hardware structure described above the basic process carried out for conversion will be explained with respect to Fig. 2 and 3. Without restriction to the scope of invention for the purpose of explanation it will be assumed that data is transferred from the A-side to the B-side and that new software is loaded into the B-side memory partition. As shown in Fig. 2, in a first step 1 both sides A and B are executing a parallel synchronous modus and execute the same software. Further, step 2 shown in Fig. 2 relates to the loading of new software into the B-side while the execution of the old software is continued in the first processing and control unit 10. In step 3 the first processing and control unit 10 performs the copying of data from the A-side to the B-side. As shown in the lower part being related to step 3, data may not only be copied but also be converted during the transfer to the B-side according to the present invention in the conversion support unit 50. Here, the conversion is executed parallel to and without disturbing the execution of old software in the first processing and control unit 10 to achieve the significant speed up. As shown in Fig. 2, in step 4 the second processing and control unit 30 executes an initialization of the second memory partition 32 parallel to and without disturbance of the old software running in the first processing and control unit 10. Here, the initialization step is either carried out immediately after loading the new software to the second memory partition 32 according to step 2 or as soon as possible in case it is dependent on data copied from old software in step 3. Further, data being related to old software may be transferred only partly and special initialization steps are executed before or immediately after switch over to the B- side to perform default initialization actions not requiring complete input of data from the old software. As shown in Fig. 2, as soon as an appropriate state is achieved in the B-side in step 5 switching to the execution of new software through the second processing and control unit 30 is executed. Here, switch over may be executed according to single software modules immediately after the same state is achieved for corresponding software modules in both memory partitions 12 and 32, respectively. In case there exists data related to old software that is not transferred at the time of switch over due to only a partial transfer of data this data may still be transferred, if necessary, before the start of new software. Further, as shown in Fig. 2 with respect to steps 3 and 4 the conversion support unit 50 according to the present invention is continuously operated also during the initialization step for the B-side memory partition. The reason therefore is that software is continuously executed during the update process and may rewrite data already being transferred to the conversion support unit 50. Therefore, one or several update and conversion processes are executed repeatedly in the background until switch over to new software in order to keep track of the changing state in the first memory partition 10. This repeated process may be executed by the conversion support unit 50 parallel to the initialization step for the B-side memory partition 32. Fig. 3 shows a flowchart according to the update process explained with respect to Fig. 2. In particular, it can be seen that in connection with a preparation step new software is loaded. According to the present invention the conversion support unit 50 is operated simultaneously in a parallel mode until switch over to the B-side takes place. Therefore, according to the invention, the execution of the old software is not interrupted while the update of new software and transfer of data being related to old software is executed with hardware support in the conversion support unit 50. While in the above the basic outline of the hardware support for data conversion has been described with respect to Fig. 1 to 3, in the following further details in particular with respect to the translation table storing unit 54, the matching unit 56 and the inverse address calculation unit 58 will be described with respect to Fig. 4 to 15. Fig. 4 shows the internal structure of the translation table storing unit 54. As outlined above, for each data variable that may eventually be converted through the conversion support unit 50 there is provided an entry Vi in a set V s for all variables to be converted: v s = ( v ι ' • • • ' v ι' • • • / v s ) ( ) Each address and therefore each entry in the translation table is related to a data structure d^ : dj = {nj; DWA, ..., OCJ . ,, . . . / ... , DINFO, ... ; ..., ij_, ... jf [ 1 -- ) Here, n- j represents the number of variables in the data structure, α represents the address of the data variable in the data structure d , DINFO represents structural information with respect to the variable in the data structure dj and Pj_ represents the start address of the conversion program assigned to the respective data variable. As is shown in Fig. 4, a translation table stores only the address DWA of the first variable of the data structure dj for each entry v-j_ and address to be searched. In other words, for the different data variables of a data structure dj always the same start address DWA will be outputted by the translation table storing unit 54. Further, the entry DINFO relates to structural information for the data variable to be searched, e.g., whether it is related to a one dimensional array, a two dimensional array or matrix, and any other flexible data structure. The third item of each entry in the translation table is the start address Pj_ of the conversion program assigned to the data variable to be converted in either of the processing and control unit 10 and 30, respectively. For each address α of a data structure supplied to the conversion support unit 50 there must be found the entry V_ in the translation table having the DWA value such that v. = {v e V s I DWA- L < α Λ α < DWA j _ +1 } (13) Fig. 5 to 13 show an embodiment of the matching unit 56 and translation table storing unit 54 particularly adapted to carry out this search in the most efficient manner. Generally there is often the need of performing a fast search for a particular data value together with associated information in a memory which contains a great number of entries. One option is that the memory device containing the plurality of data values is searched sequentially for a particular data value and when the data value has been found, the associated information is read out. In case data values are stored randomly in the memory device the complete memory may however be searched to locate the data value. To avoid a searching through the memory device, the data values can also be stored in the memory device according to predetermined rules, e.g., sorted which can be used later to locate the data value during the search procedure. Fig. 5 shows an example of a two-dimensional memory where the data entries are addressed by an address having a column address part A and a row address part B, i.e. the address S = <B(X), A(X)>. X may be regarded as a node in a binary tree where the specific row address and column address intersect. As is seen in Fig. 5, the individual data values D may be stored randomly in the memory device. Another possibility would be to use a mapping of data values to storage sections according to a binary tree data structure for representing the sorted data values. For example, from WO 96/09580 the usage of a binary tree is known to perform a sorting of records . As shown in Fig. 6, in the binary tree data structure each node (the intersection point X where a data value can be entered and read from) is connected to two other nodes. The search through the binary tree (or the memory device having entries mapped thereto) is as follows. A data value Dl is read out from a node X^ (located at row address B(X) and column address A(X) ) and the data value Dl is compared with the data value I whose storage address is to be determined. If I < Dl, then the left branch L of the tree is taken and if Dl < I the right branch R is taken. The data structure (or the data values in the memory device) is - logically - organized in a way, such that the node X2 will have a data value D2 < D]_ and that the data value D3 > Dl . In fact, assuming for example a range of data [0, D max ] the data value stored at the root node DRN divides the tree into data values (0 ... DR N -1) , DRN, (DR +1 ... D max ) wherein the data first mentioned and the data last mentioned may respectively be found at nodes among the left and right branches, respectively. However, since the individual data values T> , D2, D3 may be stored randomly in the memory device, it is necessary for the binary tree search that - after having read out D;L at A(X]_) ,B (X]_) - information is provided as to the location or memory address of D2 or D3. Therefore, conventionally one solution is that each data value D]_, D2, D3 has associated (stored) two pointers, i.e. two further memory positions including addresses indicating the location of the data value which is greater (R) or smaller (L) than the read out data value. While logically there is used the binary tree structure, wherein each further sub-level the stored data value will be respectively greater and smaller than in the previous sub-level (subtree) in the memory device itself as shown in Fig. 5, there is only a logical mapping using the address pointers while in principle the data values are stored randomly in the memory device. Using the data entries with different address pointers requires the pre-definition of the root node RN which is the first node from which a data value should be read out and compared with the data value to be searched for. Such a search algorithm is described in "Data Structures and Algorithm", Aho, Hopcroft, Ullmann; ISBNO-201-00023-7, pages 155 ff. Obviously, there is a disadvantage that the memory space that is needed for storing a great variety of data values requires that with each and every data value two further pointer entries are stored indicating the branches L, R. While in Fig. 5 there is an explicit representation of the logical binary tree in the memory device, another solution is that a mapping of the binary tree data structure to fixed addresses in the memory device, i.e. to the elements of the matrix array, is used. In this case the branching addresses are known beforehand through the mapping of the binary tree nodes to pre-defined locations in the memory device and therefore pointers are not necessary here and occupy no memory space. Since the pointers do not have to be evaluated, the search time may be lower, as is disclosed in "Data Structures and Algorithms"; Aho, Hopcroft, Ullmann; ISBN-0- 201-00023-7; pp. 271 ff. Using such an implicit mapping of the individual nodes X]_, X2 X3 to specific locations in the memory device, the address of the respective "child" nodes X2, X3 within one subtree can be calculated. In fact, representing the left and right branch by the column address A, the next node address at the left branch is calculated as A(L(X)) = 2A(X) + 0 while the right branch R is calculated as A(R(X)) = 2A(X) + 1. However, using such a mapping for the complete address <B, A> would mean that after a short initial traverse of the tree the most significant partition of the address changes in every further step of the traverse. Therefore, the search time may still be considerable for large trees that have to be stored in dynamic random access memory means due to their sizes. For real applications faster methods are required that in particular reduces the number of changes of the most significant partition of the address. The method and the access means according to the invention as described in the following are based on a mapping of nodes in a binary tree to the addresses of a memory device, preferably a dynamic random access memory DRAM. DRAMs normally offer a very dense storage, however, they are rather slow with respect to randomly distributed accesses. Using a specific addressing mode according to the invention, much lower access times can be achieved. For this, certain restrictions must be met by the addresses of a sequence of consecutive accesses. The mapping according to the invention ensures that the search of a tree always results in a sequence of accesses that meet those restrictions. The reachable performance increase (time decrease) is about a factor of 10. The address bits of the DRAM, as was explained above, are commonly divided into two parts called the row-address B and the column address A (see Fig. 5) . Normally, the row and column address are equal in size. Because of the internal implementation of the DRAM, the access time is significantly shorter if consecutive accesses can be done by just changing the column address while the row address is kept unchanged as much as possible. Hence, the novel method and access means according to the invention for mapping allows a tree searching algorithm that meets the criteria of keeping the row address unchanged as much as possible. Fig. 7 shows the division of a binary tree into a number of subtrees according to the invention. The complete tree comprises a number of subtrees of which 5 subtrees 1, 2, 3, 4, 5 are shown. In Fig. 7 each subtree has a root node which is designated with "k = 1". Likewise, each leaf node of a subtree is designated with "k = K" . K is the "depth" of the subtree, i.e. there are a number of other nodes which are only sketched by dashed lines within each subtree. So actually, each sketched subtree in Fig. 7 comprises K levels which corresponds to 2 K -1 nodes in total per subtree. Once a root node has been accessed via its column- and row- address, a search is respectively carried out in a subtree having a number of levels K (in fact the number of levels K depends on the size of the rows in the memory) . Each subtree has (lowest) leaf nodes which are connected to a respective root node of the next subtree. It may be noted that in Fig. 7 only a subset of the nodes is completely drawn. For example, the leaf node LN of subtree 1 is connected directly to the root node X]_ of subtree 3. There are a number of intermediate nodes between the root node X]_ and its leaf nodes X2, X3 • The root node is located at k = 1 and the leaf node is located at k = K. The leaf node LN of subtree 5 simultaneously constitutes also a leaf node of the entire binary tree. Therefore, it is important to distinguish between roots and leaves of the total tree and root and leaves of the subtrees. In each subtree, the variable k steps from 1 to K for each traverse of a subtree, repeatedly until the value searched for is found or a leaf node of the total tree is reached. The number of levels in a subtree depends on the actual memory hardware. According to the present invention the mapping to the memory locations is performed in such a way that one row contains 2 K - 1 entries, i.e. columns. As will be seen in the following, the search within each subtree according to the invention corresponds to a search within one individual row. The memory locations along the row , e.g./ along the subtree 1 correspond (sequentially with increasing column address) to the root node, the intermediate nodes and the leaf nodes LN of the specific subtree. Each read-out data value Oι , O2 , D3 is compared with the data value I to be located and a decision is made as to whether the left or right branch within the subtree needs to be taken. As shown in Fig. 6 for a conventional binary tree, a tree is a special kind of graph that has no cycles in it; that is after traversing the tree one step, the only way to return to the previous node is by going back the same way. This is exactly in conformance to a natural tree. Further, every part of a tree that itself forms a tree is a subtree. So, a tree generally contains a lot of subtrees. The total tree according to the invention as shown in Fig. 7 is divided into subtrees in a special way such that the subtrees are exclusive and are not connected to other subtrees; that is none of the subtrees (which each contain a root node, leaf nodes and intermediate nodes which indeed may be inter-connected, as shown in Fig. 9, contain any part of the other subtrees. Of course, there exist a lot of other ways to form subtrees from the total tree. This fact is important, since just saying that the tree is divided into subtrees does not mean that it is done as is shown in Fig. 7. Hence, Fig. 7 defines the special type of subtree-division made in the invention. The organization of the data within one row (subtree) is as shown in Fig. 9. The root node RN is always mapped to the first column address A=l. Assuming a data range between D m _ n and D max , then the data value D]_ located at the root node RN divides the subtree into data values D=[D m i n , Dι_-1] being located at nodes to the left and data values D=[D]_+1, D max ] being stored at nodes to the right. It is important to note that only the ranges are given by the division not the exact values of the data. In fact, the next nodes at k=2 will again perform a subdivision according to the respective data value D 2' D 3 stored at the nodes. However, as this is seen in Fig. 9 a data value D2 < Dι_ is located at the column address A'=2A, while the data value D3 on the right branch is located at the new column address A'=2A+1. Again the data values D4, D5 are stored at column addresses 2A, 2A+1, respectively. Assuming that K=3, obviously the data values D4, D5, D6, D7 constitute the leaf nodes of the subtree as is indicated in Fig. 9. Generally a new node address on a left branch will be 2A and on the right branch it will be 2A+1. In general there will be 2 K_1 leaf nodes, while obviously the data value DR is stored at the column address 2 K -1. The number of intermediate nodes IN is 2 K_1 -2. This describes the mapping of the nodes to the individual column addresses in one row. However, once a leaf node (D4, D5, D6, D7 for K=3 or DR or the 2 K~ 1 nodes to the right end of the column) is reached in one row, the question is where the next root nodes (D^', D^ ... for K=3 and D κ ', D κ ' ' for k=K) are located in the matrix memory. As is indicated in Fig. 9, the root nodes of the next subtrees are always located at position A=l, however, not necessarily are the root nodes and the next intermediate nodes and leaf nodes stored in the next row. According to the invention the next root node of the next subtree are located at the column position A=l and the row position B(L(X)) and B(R(X)) . According to the invention the data value D4 , D^ for the left branch is stored at B (L(X) ) =2 K *B(X) +2*A(X) +0-2 K While the next root node of a subtree connected on a right branch is located at the row address B (R(X) ) =2 K *B (X) +2*A(X) +1-2 K As may also be seen from Fig. 8, the next subtree (associated row) is not necessarily located adjacent to the previous subtree. The mapping of the nodes of the binary tree to the storage positions in the memory according to Fig. 9 means that the entries are stored at nodes of a binary tree sorted according to an increasing order of values in the tree (and thus also within the subtree as is indicated with the values in Fig. 7, 8, 9) . Of course the storage of the individual data values in an increasing order in the binary tree (corresponding to a specific order in the memory row as is indicated in Fig. 9) has an influence on the search algorithm that is used in each subtree and from subtree leaf to the next subtree root node. As was explained before, the main objective is to have as little row changes as possible, i.e. to change the most significant part of the address S = <B, A> as infrequently as possible since only the columnwise direction search is very fast. The storing of the data values for one subtree in one row according to a specific order in the column-direction leads to the result that the last entries in the columnwise direction must constitute the leaf nodes LN of each subtree. How many leaf nodes LN (leaf node storage positions LN in Fig. 8) are assigned depends on the number of levels within the subtree, i.e. depends on the size of the memory in the column direction. For example a subtree having the level K=3 comprises four leaf nodes LN at the four most right-hand positions in the column direction (see also the example in Fig. 11, 12) . Throughout the description it should be noted - considering the mapping explained above - that the (logical) expression "node" is equivalent to the (physical) mapped memory location in the memory. As outlined above, the present invention provides a mapping of the binary tree into the two dimensional memory space such that each row corresponds to a subtree and a specific search strategy is used within each row or subtree. The search is stopped within each subtree if either the match between the read out value and the data value to be searched is found or if a leaf node LF is found. Therefore, while performing the search within each subtree the search algorithm must keep track of the level where it is, since a changing of the row address B will only be performed when a leaf node is arrived at. In the present invention it was found that not only can the search addresses be calculated within each subtree, but it was also found that a specific new root node address of a next subtree can be calculated only from the comparison result and the current address of a leaf node. That is, according to the invention a new complete address S = <B, A> specifying the storage address of a node where a next data value should be read out is calculated from the present address of the presently read out memory location and on the basis of the comparison result. This applies to the address of a next node within a subtree and is also valid for finding the storage address of the next root node of the next subtree to be searched through. Fig. 10 shows a flow chart according to an embodiment of the search method according to the invention. It should be noted, that for this algorithm the complete binary tree is divided into subtrees according to Fig. 7 and the left most subtree on the level below the root subtree is cut off. As explained, if the memory is predefined with m columns, the number of levels is K=ln(m)/ln2 (or the next smaller integer) and the number of bits in the column address of the actual hardware equals K, where K is the number of levels in a subtree. It is noted that in all examples in Fig. 7, 8, 9 the column address 0 is not used due to the tree formation. In fact, if m specifies the total number of columns and K specifies the number of levels in a subtree then only m-1, or 2^-1 if smaller, columns of the m columns are used (see Fig. 7, 8, 9) . Therefore, after starting the search method in step SI, the level of the first subtree 1 is set to k=l, i.e. the search is started at the root node RN of the subtree 1 (see Fig. 7) . Then, in step S3, the data value I to be searched, the number of levels per subtree K as well as the location or root address [<B(0), A(0)> = <0,1> (in binary notation)] of the root node RN is input. Therefore, the root node RN of the first subtree 1 is the entry point of the search algorithm. In step S4 the data value D and associated information at the present address <B(0), A(0)> is read from the root node RN of the subtree 1. In step S5 the read out data value D is compared with the data value I to be located. If a match D = I is established in step S5, the search comes to an end in step Sll. If in step S5 the read out data value D is greater than the data value I to be searched, step S6 determines whether a leaf node LN is reached or not. This can be decided by comparing the running number k with the given number of levels K. If in step S6, it is established that k < K steps S9, S14 are executed. In step S9 the following equation is used for calculating a new address of an intermediate as possibly a leaf node within the subtree 1 lying along the left branch (I<D) : B(L(X)) = B(X) A(L(X)) = 2*A(X) + 0 (1) Here, B(L(X)) and A(L(X)) denote the new row address and column address of the next sub-node within the subtree 1. Thereafter, the running number of the depth level k is increased in step S14. Likewise, if in step S5 it is decided that I > D a right branch from the root node RN is taken and if in step S8 it is determined that the full depth of the subtree has not been reached, i.e. k<K, steps S12, S16 are carried out analogously to steps S9, S14, wherein the equation (2) defines the storage address of the next entry or sub-node within subtree 1 as follows: B(R(X)) = B(X) A(R(X)) = 2*A(X) + 1 (2) As can be seen from step S5, steps S6, S8 and steps S9, S12, within the subtree only the column address part A is modified, i.e. it is either doubled for the left branch or doubled and moved one further column to the right for the right branch. It is important to note that the row address part B stays the same independently of the decision in step S5. If the read out data value is greater, than there is a jump of twice the column address and if the read out data value is smaller than the one to be searched I then it is twice the current column address plus one. Of course, since steps S9, S12 are only carried out for k<K (K = maximum depth or number of levels within one subtree; K being predefined) , a new data value D is read out in step S4 at the new address A, B as determined in steps S9, S12. The reference numeral R indicates this recursive running through the individual steps S4, S5, S6, S9, S14 and S4, S5, S8, S12, S16, respectively. During the recursive process, if within a subtree the data value is found (I=D) and the algorithm comes to an end in step Sll. However, after k iterations, step S6 or step S8 determine that the full depth of the allocated subtree is reached, i.e. k=K, which means that a leaf node storage position LN must have been reached. Using the mapping of data values as in Fig. 9, it is clear that the leaf nodes LN must correspond in the address space of the memory device in Fig. 8 to the last 2 K- 1 memory positions at the higher end of the column addresses A (i.e. at the right end of the row) . If such a leaf node LN in a subtree is reached, then the following equations (3) , (4) are employed in step SIO, S13 to respectively calculate a new row address and column address of a root node of a further subtree: B(L(X)) = 2 K *B(X) + 2*A(X) + 0 - 2 K A(L(X)) = 1 (3) B (R (X) ) = 2 K *B (X) + 2*A(X) + 1 - 2 K A (R (X) ) = 1 (4 ) It is seen from equations (3), (4) that in case of the occurrence of a leaf node the column address A is - independently from the decision in step S5 - set to the first column, i.e. A(L(X)) = A(R(X)) = 1. Dependent on the decision in step S5, however, a new row address B is selected. It is interesting to note from Fig. 8 and Fig. 9 where the arrows from the leaf node LN indicate the calculation according to equations (3) , (4) , that indeed the next root node of the next subtree is located in column A=l, however, it is not located on the next adjacent subtree 2 as one might have expected. By contrast, equations (3), (4) perform a kind of column-row-imaging where the new row address of the next root node of the next subtree to be searched is not the next new row address (except for the leaf node to the very left in the subtree; see, e.g., the imaging from 13 to 19 in the example in Fig. 11) . Having determined the next root node of the next subtree to be searched in step S13, k is reset to k=l in step S17, since obviously the search in the next subtree starts at level 1, i.e. at the root node address. Then again in step S4 the next data value D is read out and steps S5, S6, S9, S14 or steps S5, S8, S12, S16 are carried out recursively for the new subtree (the new row) until either a match between D and I is found or again the leaf node of the new subtree is found. Of course, it may happen that even within the next subtree (e.g. 4 or 5 in Fig. 8) the data value is not found and consequently a leaf node LN is arrived at. For example, if leaf node LN is arrived at in subtree 5, then neither equation (3) nor equation (4) may result in a row address still contained within the row address space (if the number of rows and columns is the same) . If the number of rows is larger than the number of the columns, then of course a further new calculation of a new subtree can be performed. This means that more subtrees (rows) are available. In fact, already when the algorithm arrives below subtree 2 or 3 in Fig. 7, the number of bits in the row address has to be twice the number of bits in the column address, since with each further level in the binary tree intrinsically the number of nodes double. When no further subtree root node can be determined when a leaf node is reached in subtree 4, this indicates that the data value was not found in the binary search through the subtree and consequently also in the entire binary tree. It should be noted that preferably in step S5 a certain tolerance is admitted such that a match of D and I is established within a certain tolerance value, i.e. a match is found if |D-I|<ΔD wherein ΔD denotes a certain tolerance which is prespecified. In particular, in order to get a behaviour according to equation (13) outlined above at points A and B in Fig. 10, the following steps shown in Fig. 17 are further executed. At point A, a first step S21A relates to a test whether the current node is a leaf node of the total tree or not. If this is not true, the algorithm continues to step S6 in Fig. 10. However, if the current node is a leaf node of the total tree, the last saved values of D and Info (D) should be used, whereafter the algorithm stops, as is shown in steps S22A and S23A in Fig. 17. At point B, a first step S21B relates to a test whether the current node is a leaf node of the total tree or not. If this is not true, the current values of D and Info(D) are saved for possible future use. Then the algorithm continues to step S8 in Fig. 10. However, if the current node is a leaf node of the total tree, the current values of D and Info(D) should be used, whereafter the algorithm stops, as is shown in steps S22B and S23B in Fig. 17. Figs. 11, 12 illustrate the general algorithm in Fig. 7, 8, 10 for a specific example (K=3) where a binary notation is used for the column address A and the row address B. K=3 means that 8 columns and (at least) 8 rows are in principle provided in the memory address space. Since equations (1), (2) give no change in the column address if the very first root node RN at the top of the binary tree would have an address A(0) , B (0) = (000, 000) the first column address A=000 is not used. Therefore, the first node to be looked up when step S4 in Fig. 10 is carried out for the first time will always be the top left memory location in the memory in Fig. 11, i.e. B(0)=0, and A(0)=1 for the top and first root node of the first subtree (i.e., the root node of the entire binary tree) . Using the binary representation for the address numbers of the row and column, Fig. 12 shows the subtree 1 and the subtree 2 which is located in the first two rows with addresses 000,001. The allocation of data values D within the memory device in Fig. 11 is made in accordance with Fig. 12 as was generally explained with reference to Fig. 7. In the example in Fig. 11 and Fig. 12 it is assumed that all data values belong to a given interval 0-100. Beginning with the root node the corresponding value 56 divides this interval into two new intervals, namely 0-55 (left branch) and 57-100 (right branch) . Now, all values belonging to the lower interval 0-55 are stored in the left descendent tree while all values belonging to the higher interval 57-100 are stored in the right descendent tree. This process is repeated recursively at all lower levels using a new interval on each level. For example for the left descendent of the root node the interval 0-55 is used. The value found at the next node is 27. Hence, the next division is into the interval 0-26 and 28-55 for the two descendent subtrees suspended from the node containing the data value 27. This means that all values belonging to 0- 26 are stored in the left descendent subtree and all values belonging to 28-55 are stored in the right descendent tree. It can be noted that this way of mapping data values as is shown in Fig. 12 <-» 11 is true for the complete tree and for a subtree of its own just remembering that the starting intervals may be different according to the number of levels k. Therefore, what is shown in Fig. 12 with respect to the data values is a completely balanced binary tree. This is likewise reflected with the entries in each row which, respectively, corresponds to the nodes of one subtree. The most important implication of the correct mapping is that, if a leaf node of the total tree is reached without having found the values searched for, the value cannot exist at all in the tree. A multiplication with two for a left branch L simply means a shifting of the column address part A to the left. A right branch R results in the column address part A being shifted to the left and added by "1". Thus, the individual addresses at the intermediate nodes at k=2 and at the leaf nodes at k=3=K correspond to the particular row and column where a particular data value D is located. Fig. 12 shows the data values 56, 27, 82, ... at the respective intermediate nodes and leaf nodes as was discussed with reference to Fig. 9. Obviously, the algorithm in Fig. 10 calculates a new root node address of a next subtree whenever it reaches one of the four nodes 0,100 or 0,101 or 0,110 or 0,111. There is only one branch for the calculation of a new root node which is not allowed, which is for the address 0,100 in a situation where the read out data value D=13 is larger than the data value I to be searched. In this case actually a left branch from the address 0,100 should be taken, i.e. equation (3) should be employed. However, in this case equation (3) for a left branch would yield B (L (X) ) =2 K (000) +2 (100) - 2 K =0000+1000-1000=0000. Therefore, the first left branch indicated with "cut" in Fig. 7 and Fig. 12 must not be taken since the search would start from the root node address again. In fact, the search machine itself has no test that avoids the transversal to go into the forbidden (cut) subtree. However, this can be ensured by storing a specific data value at the left leaf node of the first (root) subtree. That is, the left most node in the root subtree contains an item having a data value that guarantees that the right branch and thus the next subtree to the right (data value 19 in Fig. 12) is always selected by the search device. If the items are stored in the order in the tree, as is seen in Fig. 12, this condition will automatically be fulfilled. When the tree is cut off, the left most node in the root subtree also becomes the left most node in the total tree. Hence, this is the place to store the item with the lowest value. Every other value is to the right. However, when taking a right branch, according to equation B(R(X))=001, which means that the left most leaf node LN with the address 0,100 results in a next leaf node root address of 001, 001. As is indicated in Fig. 12 this corresponds actually to the root node of the subtree 2 located in the second row. As is seen from Fig. 11, each of the leaf nodes of the subtree 1 can be "mapped" to new root nodes of new subtrees located at position A=l at a specific row address. If the number of rows is at least the same size as the size of the column, it can be ensured that each leaf node LN of the subtree 1 can be "imaged" or "transposed" into a new root node address in the first column. As is also seen in Fig. 11, 12, if the data values are stored in the nodes of the binary tree, the search algorithm described by equations (l)-(4) makes sure that a minimum number of row address changes is employed, while the memory matrix is searched for finding a match (within a tolerance) with the data value I in a minimum time. If no match is found at the lowest leaf node then the data value was not found. Using preferably a binary representation of the column address part A and the row address part B, the search can be facilitated, since a multiplication by 2 only means the shifting of the address to the left in a shift register. As explained above, the change in row address when traversing from one subtree to the next subtree can be described by the following steps. First, the old row address is shifted K steps to the left filling with zeros. Then, there is applied the inside subtree algorithm for changing the column address (implies K+l bits in the new column address) . Then the left most one bit of this column address is dropped (implies K bits in the new column address) . Then this column address is added into the K 0 bits of the row address. Finally, the column address is set to 1. As can be seen, at each change of subtree, K more bits are needed to hold the row address, as was explained before with reference to Fig. 7, 8, 9, 11, and 12. Hence, the number of bits in the row address must be a multiple of the number of bits in the column address. This is the preferred mapping according to the invention using an embodiment of the translation table storing unit with a binary tree structure. However, a similar consideration holds for the case where the number of bits in the row address is not a multiple of the number of bits in the column address. Here, the smallest tree is first built that fulfills the above described preferable number of rows and columns. Then all subtrees are cut off, that contain nodes in the non-existent part of the row address. Thus, also a memory can be used in which the number of rows is not a multiple of the number of columns, when a cutting off of branches is employed and the allocation of the data is done correspondingly. Again, in order to avoid that the algorithm runs into forbidden subtrees that have been cut off (which are actually not present) , the specific storing of data values can be used such that there is never a need to take a path to the cut off branch. Hereinafter, a hardware realization of an embodiment of the access means according to the invention using such a search method as explained in Figs. 7 to 12 will be explained with reference to the Fig. 13. In Fig. 13 DRAM denotes the memory device 54 and the access means comprises a comparison means MC 84 for comparing a read out data value D with said data value I to be searched to determine whether said read out data value D is greater or smaller than said data value I to be searched. If a match (within a given tolerance ΔD) between D and I is found by the comparison means 84, a match signal M is output. The comparison result C indicates whether the value D is larger or smaller than the value I. A reading out means 82 (not shown in detail) reads out a data value at a current search address A, B input from two registers RA, RB which hold the intermediate column and row addresses during the traverse of the tree. The access means further comprises a determining means 86 including the registers RB, RA for determining a complete search address to be searched next for the data value on the basis of the comparison result C and said current search address A, B. The determining means 86 comprises said first and second registers and a first and second calculation circuit SMB, SMA for computing the next column and row addresses A', B' to be searched depending on the comparison result C, the current address B, A and a control signal S output by a state machine SEQ. The state machine SEQ determines the search state (in fact it monitors k and thus intrinsically carries out steps S6, S8 in Fig. 10) during the searching through the binary tree data structure and determines the control signal S on the basis of the comparison result. Essentially, the state machine SEQ comprises a counter and a state determining means STDM to generate the control signal S on the basis of the internal STATE^-. Essentially, the internal state of the state machine corresponds to the current level number k which is updated whenever a new comparison result C (indicating whether D < I or D > I) is output by the comparison means MC. That is, the state is 0 for the root node of the tree, 1 to K-l for non leaf nodes (except the root node) and K for leaf nodes. Similarly the control signal S is 0 for the root node, 1 for non leaf nodes (sub-nodes) and 2 for leaf nodes. Starting from the root node (of the complete tree) with a state 0 (for any other subtree root node it is 1), the state machine SEQ will advance according to the partitioning of the subtree when traversing the tree top down. The signal S will select the type of address computation in SMB and SMA in accordance with the mapping. Specifically, the individual items of the access means perform the following functions. The first calculation circuit SMB performs the following function (given in functional notation) where K is the number of levels in a subtree : B' = 0, if S = 0; B' = B, if S = 1; B ' = 2 K *B + 2*A + C - 2 K , if S=2 ; ( 6) wherein C (0 for D>I and 1 for D<I) denotes the comparison result, B and B' denote the current and the next row address, S denotes the control signal, K denotes said predetermined number of levels in a subtree and A denotes the current column address. The second calculation circuit SMA performs the following functions (given in functional notation) : A' = 1, if S = 0; A' = 2*A + C, if S = 1; A' = 1, if S = 2, (7) wherein C denotes the comparison result and A and A' denote the current and the next column address and S denotes the control signal. The state machine SEQ calculates the control signal S on the basis of the following equations (8) and (9) : S = 0, if STATE t = 0; S = 2, if STATE t = K; S = 1, if 0 < STATE t < K, (8) wherein a state determining means STDM of said state machine SEQ calculates an internal state STATE t (i.e. the value k in Fig. 10) of the state machine SEQ according to the following equation (9) : STATE t = °' if t=0; STATE t +i = 2, if STATE t = 0; STATE t+ i = 1, f STATE t = K; STATE t +l = STATE t + 1, if 0 < STATE t < K ( 9) wherein STATE^- and STATEt+i denotes the state at times t and t+1, and t denotes the number of comparisons counted from the beginning during the traversal of the complete tree (i.e., t is a notation of time or cycles since the start of the search in terms of comparison steps) , wherein t goes from 0 to the number of levels in the complete tree, which may in principle be an arbitrary high number but restricted to multiples of K, and wherein denotes the state when the first comparison is performed at a memory location corresponding to the root node RN of the binary tree data structure. As outlined above, the method and the access means according to the invention only use a minimum number of steps before a change in a subtree is caused. As follows from the mapping, only the column address changes during a traverse inside the subtree. When dynamic random access memories have to be used, due to the amount of the data, the invention can provide a fast search engine for a data value sorted according to a binary tree data structure. The reduction in time is an order of magnitude. Thus, the invention can be used in all technical areas where the time is critical for locating a data value in a large memory. It should be noted that in the above description, row can be exchanged with column since it will depend on the organization of the memory which storage direction is denoted row and column, respectively. As soon as the matching unit 56 described above has unveiled the entry for an address in the translation table storing unit 54, the start address DWA of the data structure dj being related to the data variable to be converted, the structural information DINFO, as well as the start address pj_ of the related conversion program are available in the conversion support unit 50 outlined above. The next step is then related to the determination of indices in accordance to the data variable to be converted. Such indices enable the access to the data variable to be converted through the conversion program using a logical and not physical addresses. During the inverse address calculation in the inverse address calculation unit 58 initially a value α lnv = α - DWA (12) is calculated. Then the value of α lnv is split into offsets 1 ... N being related to indices in a general data structure and used by a conversion program with the start address Pi to carry out an access to the data variable before actual conversion thereof using logical addressing as outlined above . Fig. 14 illustrates the calculation of the inverse address for a one-dimensional array. Here the data structure dj with the data variable α to be converted has the address DWA assigned to the initial index thereof. Therefore, after the calculation of the difference between α and DWA the structural information DINFO storing the length of each data variable in the one dimensional array is used to determine the index of the data variable. In particular, this index is derived by dividing the difference between α and DWA with the length of each data variable in the one dimensional array. Fig. 15 shows a further example being related to the inverse address calculation for of two dimensional array or matrix. It is assumed that the matrix A (I, J) is dimensioned such that I ranges from 0 to 3 and J ranges from 0 to 6. The upper part of Fig. 14 shows the conversion queue unit 52 handling an address α pointing to element A (2,3) of the matrix A. Further, as shown on the lower part of Fig. 14 the two dimensional logical representation of the matrix A(I, J) is mapped to a linear structure in the memory partitions 12, 32. Here, DWA represents a base address of the matrix A corresponding to the matrix element A(0,0). To determine the indices 2, 3 of the data variable it is necessary to know the base address DWA, the length of each data variable of the two dimensional matrix that may be stored in DINFO and also the range of indices such as first index (row) from 0 to 3 and second index (column) from 0 to 6. In case the length of each array element is known the index values may be calculated according to k = α - DWA J = k - 7 x INT(k/7) I = INT(k/7) (13) where INT(Z) is the integer part of Z, e.g., INT (12/7) = 1, and the constant 7 is derived from the range of the second index (number of columns) and the length of each element (1) . Thus, if the base address of A is 1000, the address 1017 corresponds to J = 17 - 7 x INT(17/7) = 3 I = INT(17/7) = 2, (14) i.e. the memory address 1017 corresponds to A(2,3). Using this approach the inverse address calculation can be extended to any number of indices and lengths of array elements. For instance, if the element length is two memory words, the constant 7 in the formulas for I and J should be replaced by 2 x 7 = 14. If each word of such two word array elements can be accessed, the formulas can be modified to calculate the high and low word of each element by taking REM(Z) as remainder part of Z. While in the above the present invention has been described with respect to the transfer of variables on the basis of variable addresses also a higher level address could be used as well. This higher level address could consist of the program unit number and base address of the variable and value of any indices if applicable. This option of the invention would simplify the conversion hardware as the matching unit 56 could be simpler and the inverse address calculation unit 58 would not be needed. However, the translation from the program unit number and base address of the variable to the program unit number and the start address of the conversion program would still be necessary. Nevertheless, one advantage with this higher level conversion approach is that the capacity obtainable for conversions increases . List of reference numerals 10 First processing and control unit 12 First memory partition 14 First address bus 16 First data bus 18 First data address bus control unit 20 First data address bus control line 22 First update bus control unit 24 Update bus 26 First update bus control line 28 First copy/convert data line 30 Second processing and control unit 32 Second memory partition 34 Second address bus 36 Second data bus 38 Second data address bus control unit 40 Second data address bus control line 42 Second update bus control unit 44 Second update bus control line 46 Second copy/convert data line 50 Conversion support unit 52 Conversion queue unit 54 Translation table storing unit 56 Matching unit 58 Inverse address calculation unit 60 Address input line 62 First address connection line 64 Second address connection line 66 First backpressure signaling line 68 Second backpressure signaling line 70 Address supply line 72 DWA supply line 74 DINFO supply line 76-1 to 76-N Offset supply lines 78 Conversion program address line 82 Readout unit in matching unit 84 Comparison unit in matching unit 86 Determining unit in matching unit

Claims: C l a i s 1. Software processing system of the partitioned type, comprising: a) a first partition (A) with a first memory means (12), b) a second partition (B) with a second memory means (32) , wherein c) the first partition (A) and the second partition (B) are connected through a linking means (24) and adapted to update a state of new software in one memory means (12; 32) to the state of old software in the other memory means (32; 12) during execution of old software, and d) the transfer of data from old software to new software is supported by a data conversion support device (50) adapted to output the start address of a conversion program being related to a data variable to be converted. 2. Software processing system according to claim 1, characterized in that the data conversion support device (50) outputs the start address of the conversion program to either one of a first processing and control unit (10) of the first partition (A) or a second processing and control unit (30) of the second partition (B) , respectively. Software processing system according to claim 1 or 2, characterized in that the data conversion support device (50) is adapted to output a backpressure signal either to the first partition (A) or to the second partition (B) via a first backpressure signal line (66) and a second backpressure signal line (68), respectively, in case the number of addresses for data conversion supplied to the data conversion support device (50) exceeds the maximum number of addresses allowable. Software processing system according to one of the claims 1 to 3, characterized in that the data conversion support device (50) is also adapted to output at least one logical address for the access to the data variable to be converted on a logic lievel through the conversion program to either one of the first processing and control means (10) and the second processing and control means (30) , respectively. Software processing system according to one of the claims 2 to 4, characterized in that the data conversion support device (50) comprises: a translation table sotrage means (54) adapted to store address information and structural information for data variables to be converted; and b) a matching means (56) adapted to find an entry in the translation table storage means (54) for a data variable to be converted according to the address (α) of the data variable and the start address (DWA) of the data structure being related to the data variable. 6. Software processing system according to claim 5, characterized in that the translation table storage means (54) is adapted to store for each address of a data variable to be converted the start address of the related data structure (DWA) , structural information (DINFO) , and a start address of a related conversion program, respectively. 7. Software processing system according to claim 6, characterized in that the structural information (DINFO) comprises at least information with respect to the data variable length and the organization of the data structure (d j ) being related to the data variable to be converted. 8. Software processing system according to one of the claims 5 to 7, characterized in that the matching means (56) determines the entry in the translation table storage means (54) according to VJ_ = {VJ_ e V s I DWAj_ < α Λ α < DWAi + ]_} . 9. Software processing system according to one of the claims 5 to 8, characterized in that a matching means (56) is adapted to find an entry in the translation table storage means (54) through carrying out a binary search. 10. Software processing system according to claim 9, characterized in that the matching means (56) is realized according to one of the claims 21 to 31. 11. Software processing system according to one of the claims 5 to 10, characterized in that the data conversion support device (50) further comprises an inverse address calculation means (58) adapted to use the information read from the translation table storage means (54) to identify a variable to be converted on a logical address level. 12. Software processing system according to claim 11, characterized in that the inverse address calculation means (58) is adapted to first calculate the difference between the address ( ) supplied to the data conversion support device (50) and the start address (DWA^) of the identified data structure (dj) and further to use the structural information (DINFO) provided from the translation table storage means (54) to derive at least one logical address offset according to the address to be converted. 13. Data conversion support device, comprising: a) a translation table storage means (54) adapted to store address information and structural information for data variables to be converted; and b) a matching means (56) adapted to find an entry in the translation table storage means (54) for a data variable conversion program according to the address (α) of the data variable. 14. Data conversion support device according to claim 13, characterized in that the translation table storage means (54) is adapted to store for each address of a data variable to be converted a start address of the related data structure (DWA) , structural information (DINFO) , and a start address of a related conversion program, respectively. 15. Data conversion support device according to claim 14, characterized in that the structural information (DINFO) comprises at least information with respect to the data variable length and the organization of the data structure (d j ) being related to the variable to be converted. 16. Data conversion support device according to one of the claims 13 to 15, characterized in that the matching means (56) determines the entry in the translation table storage means (54) according to v {v χ e V s I DAi < α Λ α < DWAj_ +1 } 17. Data conversion support device according to one of the claims 13 to 16, characterized in that a matching means (56) is adapted to find an entry in the translation table storage means (54) through carrying out a binary search. 18. Data conversion support means according to one of the claims 13 to 17, characterized in that the matching means (56) is implemented according to one of the claims 21 to 31. 19. Data conversion support device according to one of the claims 13 to 18, characterized in that is adapted to use the information read from the translation table storage means (54) to identify a variable to be converted on a logical address level . 20. Data conversion support device according to one of the claims 13 to 19, characterized in that the inverse address calculation means (58) is adapted to first calculate the difference between the address (α) supplied to the data conversion support device (50) and the start address (DWA) of the identified data structure (dj) and further to use the structural information (DINFO) provided from the translation table storage means (54) to derive at least one logical address offset according to the data variable to be converted. 21. Matching means for a memory device for determining the storage address (B(X), A(X)) of a predetermined data value (D) in a memory device, said data values (D) being stored at predetermined storage addresses (B(X), A(X) ) according to a binary tree data structure of nodes, branches, subtrees and leafs, comprising: a) a reading out means (R) for reading out a data value at a predetermined current search address (B(X), A(X) ) of said memory device; b) comparison means (MC) for comparing said read out data value (D) with said data value (I) to be searched to determine whether said read out data value (D) is greater or smaller than said data value (I) to be searched; and c) determining means (SEQ, SMB, SMA, RB, RA) for determining a complete next search address (B, A) to be searched for the data value on the basis of the comparison result (C) and said current search address (B(X), A(X) ; wherein d) said reading out means, said comparison means and said determining means carry out recursively said reading out, said comparing and said determining until said read out data value (D) matches (M) said data value (I) to be searched within a predetermined tolerance. 22. Matching means according to claim 21, characterized in that said data values areas stored in said memory device in a matrix arrangement of rows and columns, wherein each data value (D) is assigned a column address (A) and a row address (B) . 23. Matching means according to claim 22, characterized in that said determining means comprises: first and second register (RB; RA) for holding a next row and column address (B', A'); a first and second calculation circuit (SMB, SMA) for computing the next column and row addresses (B', A') to be searched depending on the comparison result (C) , the current address (B, A) and a control signal (S) ; and a state machine (SEQ) for determining a search state (STATE^) during the searching through the binary tree data structure and for determining said control signal (S) on the basis of the comparison result (C) . 24. Matching means according to claim 22, characterized in that the data values in said memory device are stored in a binary tree data structure having a predetermined number of levels K in each subtree, wherein said state machine (SEQ) comprises a counter (CNT) which counts the number of comparisons (t) performed by said comparison means (MC) . 25. Matching means according to claim 23, characterized in that said comparison result (C) is calculated by said comparison means (MC) according to the following equation (5) : C = 0, if I < D; C = 1, if I > D; (5) wherein C denotes the comparison result, I denotes the data value to be searched and D denotes the read out data value. 26. Matching means according to claim 25, characterized in that said first calculation circuit (SMB) calculates the next column address (B τ ) according to the following equation (6) : B' = 0, if S = 0; B' = B, if s = 1; B' = 2 K *B + 2*A + C - 2 K , if S=2 ; (6) wherein C denotes the comparison result, B and B' denote the current and the next row address, S denotes the control signal, K denotes said predetermined number of levels in a subtree (bits in the column address) , and A denotes the current column address. 27. Matching means according to claim 25, characterized in that said second calculation circuit (SMA) calculates the next column address (A' ) according to the following equation (7) : A' = 1, if S - 0; A' = 2*A + C, if S = 1; A' = 1, if S = 2, (7) wherein C denotes the comparison result, A and A' denote the current and the next column address and S denotes the control signal. 28. Matching means according to claim 23, characterized in that said state machine (SEQ) calculates said control signal (S) on the basis of the following equation (8) : S = 0, if STATE t = 0; S = 1, if 0 < STATE t < K; S = 2, if STATE t = K, (8) wherein a state determining means (STDM) of said state machine (SEQ) calculates an internal state STATEt of said state machine (SEQ) according to the following equation (9) : STATE t = °' if t=0 ' STATEt+i = 2, if STATE t = 0; STATEt+i = 1/ if STATE t = K; STATEt+l = STATE t + 1, if 0 < STATE t < K (9) wherein STATEt and STATEt+i denotes the state at times t and t+1, and t denotes the number of comparisons counted by the counter (CNT) , wherein 0 < t < K * N with N representing the number of subtree levels of the complete binary tree and wherein STATEt=o denotes the state when the first comparison is performed at a memory location corresponding to the root node of said binary tree data structure. 29. Matching means according to claim 21, characterized in that said reading out means (R) reads out information stored in said memory means in association with said matching data value. 30. Matching means according to claim 21, characterized in that said memory device is one of a DRAM or a cache memory. 31. Matching means according to claim 30, characterized in that said storage address has a row address part and a column address part and said column address part is used to select one of said sequential data entries inside a specific cache line and said row address part is used to select one specific cache line. 32. Method for determining the storage address (B(X), A(X) ) of a predetermined data value (I) in a memory device, in which data values (D) are stored at predetermined storage addresses (B(X), A(X) ) according to a binary tree data structure of nodes (X) , branches, subtrees and leafs, comprising the following steps: a) reading out a data value (D) at a current search address (B(X), A(X) ) from said memory device; b) comparing said read out data value (D) with said data value (I) to be searched to determine whether said read out data value (D) is greater or smaller than said data value (I) to be searched; and c) determining a complete next search address (B', A') to be searched for the data value on the basis of the comparison result (C) and said current address (B(X) , A(X) ) ; wherein d) steps a)-c) are recursively carried out until said read out data value (D) matches said data value (I) to be searched within a predetermined tolerance (ΔD) . 33. Method according to claim 32, characterized in that the data values are stored in a binary tree data structure having a predetermined number K of levels in each subtree, wherein in said step c) said next address is determined on the basis of said comparison result (C) , said current search address and also said predetermined number of levels (K) in each subtree. 34. Method according to claim 32, characterized in that said data values (D) are in a range of a lowest data value and a highest data value, wherein a center data value corresponding to the center value of said range is stored at a predetermined root address (B(0), A(0) = <0,1>), wherein, when step a) is carried out for the first time, said root address is used as said current address. 35. Method according to claim 32, characterized in that said data values are stored in said memory device in a matrix arrangement of rows and columns, wherein each data value (D) is assigned a column address (A) and a row address (B) . 36. Method according to claim 32 or 35, characterized in that when said comparison result (C) in step b) indicates that the read out data value is larger than said data value (I) to be searched ("branch left"), said next address in step c) is calculated by the following equation (1) : B(L(X)) = B(X) A(L(X) ) = 2*A(X) + 0 (1) where X denotes the current node defined by the current address (B(X), A(X) ) , A(X) and B(X) denote the column address and the row address of the current node X, L(X) denotes the next node where a data value is stored which is smaller than the data value stored at the current node X, and A(L(X)) and B(L(X)) denote the column address and row address of the next node L(X) . 37. Method according to claim 32 or 35, characterized in that when said comparison result in step b) indicates that the read out data value is smaller than said data value (I) to be searched ("branch right"), said next address in step c) is calculated by the following equation (2) : B(R(X)) = B(X) A(R(X) ) = 2*A(X) + 1 (2) where X denotes the current node defined by the current address (B(X), A(X) ) , A(X) and B(X) denote the column address and the row address of the current node X, R(X) denotes the next node where a data value is stored which is greater than the data value stored at the current node X, and A(R(X)) and B(R(X)) denote the column address and row address of the next node R(X) . 8. Method according to claim 32, 33 or 35, characterized in that when said comparison result in step b) indicates that the read out data value is larger than said data value (I) to be searched ("leaf left"), said next address in step c) is calculated by the following equation (3) : B(L(X)) = 2 K *B(X) + 2*A(X) + 0 - 2 K A(L(X)) = 1 (3) where X denotes the current node defined by the current address (B (X) , A(X) ) , A(X) and B(X) denote the column address and the row address of the current node X, L(X) denotes the next node where a data value is stored which is smaller than the data value stored at the current node X, and A(L(X)) and B(L(X) denote the column address and row address of the next node L(X) and 2^ is the number of columns in the memory device. 39. Method according to claim 32, 33 or 35, characterized in that when said comparison result in step b) indicates that the read out data value is smaller than said data value (I) to be searched ("leaf right"), said next address in step c) is calculated by the following equation (4) : B(R(X)) = 2 K *B(X) + 2*A(X) + 1 - 2 K A(R(X)) = 1 (4) where X denotes the current node defined by the current address (B(X), A(X) ) , A(X) and B(X) denote the column address and the row address of the current node X, R(X) denotes the next node where a data value is stored which is greater than the data value stored at the current node X, and A(R(X)) and B(R(X)) denote the column address and row address of the next node R(X) and 2 K is the number of columns in the memory device. 40. Method according to one of claims 33 and 38 or 33 and 39, characterized in that said next address is calculated according to equation (3) or (4) , respectively, if the number of comparisons performed in step b) equals a multiple of the number of levels in a subtree (K) . 41. Method according to one of claims 33 and 36 or 33 and 37, characterized in that said next address is calculated according to equation (1) or (2), respectively, if the number of comparisons performed in step b) does not equal the number of levels in a subtree (K) . 42. Method according to claim 32, characterized in that after said step d) information stored in association with said matching data value is read out from the memory location having said current address . 43. Method according to claim 32, characterized in that said memory device is one of a DRAM or a cache memory.

Inventors: GARD BENGT ERIK INGEMAR, JOHNSSON STEN EDVARD, KLING LARS-OERJAN, GARD, BENGT, ERIK, INGEMAR, JOHNSSON, STEN, EDVARD, KLING, LARS-OERJAN
Applicants: ERICSSON TELEFON AB L M, GARD BENGT ERIK INGEMAR, JOHNSSON STEN EDVARD, KLING LARS OERJAN, GARD, BENGT, ERIK, INGEMAR, JOHNSSON, STEN, EDVARD, KLING, LARS-OERJAN, TELEFONAKTIEBOLAGET LM ERICSSON (PUBL)
Application year: 1999
Main classification: G06F9
IPC codes: G06F9, G06F11