A POWER SUPPLY INTERFACE

Abstract: The present invention relates to a power supply interface for coupling a first or a second power supply (14, 15) to a processing circuit of a computing device. The processing circuit, which is normally powered by the first supply, includes a processor (3) which generates a power supply control signal when power is to be supplied by the second supply (15). The power supply interface includes first and second power supply inputs (11, 12) which are connected to the main supply and backup supply respectively. A power supply output is coupled to the processing circuit and a detector is also provided for detecting the power supply control signal. A switching device (5) responds to the detector to selectively couple the second power supply input to the power supply output.

Description: A POWER SUPPLY INTERFACE The present invention relates to a power supply interface, for coupling a selected one of a first supply or a second supply to a processing circuit of a computing device. As computers become faster and more powerful, the amount of power consumed by each computer is vastly increasing. In addition to this, computers themselves are being more widely used and as a result, the overall power consumption by computers in offices, businesses and the like is increasing rapidly. It has however been realised that for the majority of the time, computers are left idle during which time they are not performing any processing functions . In order to help alleviate the problem, the computer industry is introducing a new operating standard known as "PC99". This proposes that computers should be designed to power down when not in use. This procedure would involve reducing the clock speed and shutting down any extraneous functions. In order to achieve this, the industry has agreed to introduce a back up power supply into new PCs built in accordance with the standard. The back up power supply is then to be used for powering circuits of the computer as required, allowing the main power supply to be shut down . In addition to the PC99 standard, a system known as "Wake On LAN" has also been developed. This system is employed in local area networks and is designed to allow computers to remain idle, or powered down, with the computer being automatically reactivated upon receipt of data from the network. This system operates using a standby voltage different to that of the PC99 format. Accordingly, it is necessary for components to be developed for computers which are capable of automatically switching to a back up power supply, as required. Apparatus and a method for automatically sensing which of either of a 5V supply or a 3.3V supply is available to it on powering up is described in US-A-5534801. In this system a voltage intermediate to the 5V and 3.3V power supplies is utilized as a threshold voltage. The voltage level on a bus power line is compared to the threshold such that if it is above the threshold, then the circuit operates on the 5V power supply, whereas if it is below the threshold, the circuit operates from the 3V power supply. By using the results of the comparison, the logic level thresholds of a logic circuit can be adjusted to allow the circuit to function from either power supply. This system suffers from the draw back that the circuit does not actually switch the power supplies, but merely ensures that the circuit may function on either of two available power supplies. In accordance with a first aspect of the present invention, we provide a power supply interface for coupling a selected one of at least a first supply and a second supply to a processing circuit of a computing device, the processing circuit normally being powered by the first supply, wherein the computing device includes a processor which generates a power supply control signal when power is to be supplied by the second supply, the power supply interface comprising: first and second power supply inputs for coupling to the main supply and backup supply respectively; a power supply output coupled to the processing circuit ; a detector for detecting the power supply control signal; and, a switching device responsive to the detector to selectively couple the second power supply input to the power supply output . In accordance with a second aspect of the invention, we provide a method of operating a power supply interface for coupling a selected one of at least a first supply and a second supply to a processing circuit of a computing device, the processing circuit normally being powered by the first supply, wherein the computing device includes a processor which generates a power control signal when power is to be supplied by the second supply, the power supply interface having first and second power supply inputs for coupling to the first supply and the second supply respectively, a power supply output coupled to the processing circuit, and a switching device for selectively coupling the first or second power supply inputs to the power supply output, the method comprising: detecting the power supply control signal; and, in response thereto, causing the switching device to selectively couple the second power supply input to the power supply output . The present invention provides a power supply interface which allows a first or second power supply to be connected to a processing circuit. By using a detector coupled to the host processor, the power supply interface can detect when the computer generates a power supply control signal and respond by switching the power supply used to power a processing circuit from the first supply, to a second supply. This provides a simple technique for allowing a computer to operate processing circuitry using alternative supplies which may be of a voltage the same as, or different to that of the main supply. Typically the processor generates the power supply control signal when the computing device enters a power saving mode. However, the interface may also be used in any case in which multiple power sources are to be used as required. One example of this would be in a lap top computer, when the supply is to be switched from battery to mains operation. In this case, the processor could generate the power control signal causing the computer to automatically switch to the mains supply, when it is available. For ease, the remainder of the specification will refer to the control signal being generated when the computer enters a power saving mode, but this is not intended to be limiting to such a situation. Typically, in the case of the computing device entering the power saving mode, the first supply comprises a main supply and the second supply comprises a first backup supply. The main supply is typically a 5V PCI supply and the backup supply is, for example, a 3 volt or 5 volt back up supply. Preferably the detector is adapted to detect when the computing device exits the power saving mode, thereby causing the switching device to selectively couple the first power supply input to the power supply output. This allows the power supply interface to automatically reconfigure itself to power the processing circuit from the main power supply, should the computer exit the power saving mode . This is usually achieved by having the detector detect signals generated by the processor of the computing device. These signals may take any form such as signals causing reactivation of other components such as the hard drive, or any other processing instructions. However, alternatively, the detector may simply detect the reactivation of the main power supply or receive a specific signal from the host processor. Typically, when the computing device exits the power saving mode, the switching device is adapted to couple the first power supply input to the power supply output and subsequently decouple the second power supply input from the power supply output . This ensures that power is output from the power supply interface at all times thus ensuring that there is no interruption in power to the processing circuit. Similarly, when the processor generates the power supply control signal, the switching device preferably couples the second power supply input to the power supply output and subsequently decouples the first power supply input from the power supply output. Typically, when the back up power supply is connected to the second power supply input, the switching device is adapted to generate a supply signal which indicates to the detector that a second supply is provided. This ensures that the detector does not cause unnecessary switching events . Preferably the switching device comprises a first switching element for selectively coupling the first power supply input to the power supply output, a second switching element for selectively coupling the second power supply input to the power supply output and a controller coupled to the detector and the first and second switching elements, the controller being adapted to control the switching elements in response to the detector. This allows the connections between each power supply input and the power supply output to be controlled independently, thereby allowing the desired switching to be achieved. Alternatively, a single switching element could be used although in order to maintain the desired switching, operation would become more complex. Typically there is further provided a third power supply input for coupling to a third supply. This accommodates the use of different computer industry standards that utilize two different backup power supplies. By providing two back up power supply inputs, the system may be used with any one or both of these two back up power supplies allowing the interface to be used in any computer. Typically when a third power supply is connected to the third power supply input, the switching device is adapted to generate a further supply signal which indicates to the detector that a third supply is provided. In order for the switching device to function, it will generally include a third switching element, coupled to the controller, for selectively coupling the third power supply input to the power supply output . Typically, the first supply has a first supply voltage and the second supply has a second supply voltage. In this case, the switching device further comprises a convertor, coupled to the power supply output, wherein when the second power supply input is coupled to the power supply output, the converter converts the back up supply received at the second power supply input into modified second supply having the first voltage. This ensures that the processing circuit is always provided with a power supply having the first voltage. This is preferable to providing a second voltage to the processing circuit as it allows the processing circuit to continue operation unmodified. If the second and third power supplies are coupled to the power supply interface, the switching device is adapted to couple the third power supply input to the power supply output in preference to the second power supply input as the third power supply has an identical voltage to the main power supply. Typically, the first supply is a main power supply and the second and the third supplies are back up power supplies. However, the interface is designed to work with any suitable form of power supplies and these need not comprise specific back up supplies. The power supply interface is generally used for powering support cards, such as network interface cards, which may be required to run from a back up supply when the computer enters a power saving mode. However, it will be realised that the power supply interface is suitable for operation with any system in which a power supply is switched between alternative power supplies. Examples of the present invention will now be described with reference to the accompanying drawings, in which: - Figure 1 shows a block diagram representing the major elements of a circuit according to the present invention; Figure 2 shows a circuit diagram of a preferred embodiment of the present invention; Figure 3 is a state diagram outlining the operation of the present invention in a "Wake-On-LAN" standard personal computer having a 5V backup power supply; and, Figure 4 is a state diagram outlining the operation of the present invention in a PC99 standard personal computer using the "Wake-On-LAN" standard and having a 3V backup power supply. The example shown in Figure 1 comprises a power interface 1 coupled to a bus 2 of a computer (not shown) . Also coupled to the bus 2 is a host processor 3 which controls the operation of the computer. The power supply interface 1 includes a processing unit 4 coupled to the host processor 3 via the bus 2. The processing unit 4 is coupled, via a connection 4a, to a controller 9 of a switching device 5. The switching device 5 comprises first, second and third switching elements 6,7,8 which are coupled to the controller 9 via first connections 6a, 7a, 8a. A second connection 6b is provided from the first switching element to the controller 9. There are also provided second connections 7b, 8b from the second and third switching elements to the controller 9 and the processing unit 4. Inputs of the three switching elements 6,7,8 are connected via first, second and third power supply input ports 11,12,13 to a main power supply 14, a first back up power supply 15, and a second back up power supply 16. In this embodiment the main supply 14 and the second backup supply are 5V supplies and the first backup supply 15 is a 3V supply. The outputs of the three switching elements 6,7,8 are coupled to first and second processing circuits 18,20. In this embodiment the first processing circuit operates using a 5V supply and the second processing circuit 20 operates using a 3V supply. Accordingly, the outputs first and third switching elements 6,8 are coupled to a processing circuit 18, via an output port 17, and to a processing circuit 20, via an output port 19 and a voltage convertor 21. The output of the second switching element 7 is coupled to the output port 17, and hence the processing circuit 18, via a voltage converter 10, and to the processing circuit 20 via the output port 19. It will be realised by a person skilled in the art that the present invention is not limited to the use of 3V and 5V supplies and/or processing circuits that operate from 3V and/or 5V supplies. If alternative power supplies or processing circuits are used, an alternative voltage convertor configuration may simply be used. The processing circuits 18,20 may form part of the computer system, or at least are designed to operate in conjunction with the computer and are to be supplied with power from the main power supply 14, or one of the first or second back up power supplies 15,16. In use, when the computer is operating in normal mode, the first switching element 6 couples the main power supply 14 to the output port 17 and via the voltage converter 21 to the output port 19, thereby providing power to the processing circuits 18,20. When the computer is to enter a power saving mode, the host processor 3 generates a power supply control signal which is transferred via the bus 2 to the processing unit 4. It will be realised that the indication that the power saving mode is to be entered may also be achieved by the processor failing to generate a signal. Accordingly, the power supply control signal may be of the form of a continuous signal which is discontinued when the computer is to enter the power saving mode. Resumption of the signal could then be used to indicate that the computer is to exit the power saving mode. Once the power supply control signal has been detected, the processing unit 4 then generates a control signal which is sent to the controller via the connection 4a, indicating that a power saving mode is to be entered. The controller 9 automatically controls one of the second or third switching elements 7,8, via the first connections 7a, 8a, to couple either the first or second back up power supply 15,16 to the output ports 17,19. The controller 9 subsequently controls the first switching element 6, via the first connection 6a, to decouple the main power supply 14 from the output ports 17,19. The decision about which backup power supply is to be used is made automatically and depends on which power supplies are connected to the respective switching elements. This information is transferred to the controller 9 from the second and third switching devices via the second connections 7b, 8b. As mentioned above, the first back up power supply 15 provides a 3 volt supply whereas the second back up power supply 16 provides a 5 volt supply. If both power supplies are connected, the controller 9 will cause the third switching element 8 to close in preference to the second switching element 7, thereby coupling the 5V second backup supply 16 to the processing circuits 18,20. If the second back up power supply 16 is not present, and the first backup supply 15 is present then the second switching element 7 will close, thereby coupling the back up power supply 15 to the output ports 17,19. Finally, if the second backup supply 16 is present and the first backup supply is not present, then the third switching element 8 will close, thereby connecting the second backup supply to the processing circuits 18,20. The reason behind this is that the first back up power supply 15 only provides 3 volts, and accordingly requires the voltage converter 10 to increase the voltage from 3 volts to 5 volts to provide sufficient voltage to the processing circuit 18. The use of the voltage convertor 10 does however mean that the amount of power drawn from the backup supply 15 is more than if the second backup supply 16 was used. It will however be realised that in some circumstances, it may be preferable to use the first rather than the second backup supply, in which case operation of the controller 9 can simply be adjusted. This switch to one of the backup supplies 15,16 is performed regardless of whether the main power supply 14 continues operation or not. When the computer exits the power saving mode, the host processor 3 will begin to generate signals which will be transferred via the bus 2. Although these may not be intended for the processing unit 4, the processing unit 4 will detect the signals and send a control signal to the controller 9, via the connection 4a, indicating the power saving mode is to be exited. Accordingly, the controller 9 will cause the first switching element 6 to close coupling the main power supply 14 to the output port 17. Then either the second or third switching elements 7,8 will open, decoupling which ever back up power supply 15,16 is connected to the output port 17. Accordingly, the processing circuit 18 is then provided with power from the main power supply 14. It should be noted that the power supply interface may be designed to be incorporated into a "Wake-On-LAN" network interface card. In this case the network interface card is designed to reactivate the computer upon receipt of a specific type of data packet from the communications network. This can be achieved by having the detector generate a control signal which is transferred to the main power supply. In the case in which the system is operating on the 5V backup supply 15, as in a "Wake-On-LAN" standard computer, a LANWAKEUPEN signal is transferred via a connection 4b to the main power supply, causing the computer to exit the power saving mode. Alternatively, in a computer operating under the proposed PC99 standard, which utilises the 3V backup supply 16, a PME# (Power Management Event) signal is generated by the processing unit 4 and transferred via the connection 4c to the main power supply and the host processor 3. Operation of specific examples of such "Wake-On-LAN" operation are summarised in Figures 3 and 4, in which the network interface card is a LAN adaptor card. A specific embodiment of the present invention is shown in the circuit diagram of Figure 2. In view of the complexity of this circuit, individual portions of the circuit will be described individually. Figure 2 shows a preferred embodiment of the switching device 5 of Figure 1. In this example, the first, second and third switching elements 6, 7, 8 and the controller 9 are incorporated into a single circuit design. In this example, the power supply interface and processing circuits 18, 20 form part of a network interface card of a computer, the card being designed to operate in accordance with the "Wake ON LAN" standard. The processing unit 4 is actually implemented as part of a processor K2 which also forms part of the processing circuits 18, 20. Accordingly, there is also provided a LANWAKEUP output and a P_PMEK output from the processor K2 which is used to return the computer and power supply to normal (i.e. non- power saving mode) upon the receipt of data from a communications network (not shown) , as described later. The main power supply 14 of the computer will be a 5VPCI supply, with the first and second backup supplies 15, 16 being a 3VSTBY and a 5VSTBY supply respectively. Operation of the power supply interface according to the present invention will now be described. In order to simplify the detailed explanation of the circuit, several different sets of operating circumstances will be considered (e.g. main supply 5VPCI and second backup supply 5VSTBY only connected) . The basic operation of such a circuit when used in conjunction with the "Wake-on-LAN" standard is also outlined in Figures 3 and 4 which show state diagrams outlining the operation with a 5V backup supply and a 3V backup supply respectively. Operation with the main 5VPCI supply and the second 5VSTBY backup supply will now be described. This circuit comprises the group of 7 transistors Q10, Qll, Q3, Q2, Q12, the diode connected transistors, Q8 & Q7, the single transistor Q22, the dual diodes CR3 , and resistors R63, R36, R6 , R37, R50, R51, R7 , R9 , R5 , R32 & R17 together with capacitors C16 & C22. This part of the circuit comprises three basic functional blocks . I. Supply switching components around Q10, Qll, Q3 , Q2, Q12, the diode connected transistors, Q8 & Q7 and ONSTBY signal filtering around CR3. II. LANWAKEUPEN control around Q22. III. 5VSTBY monitoring. The ONSTBY signal is the signal supplied from the processor K2 to indicate that the computer is entering the power saving mode, and that the power supply interface should switch the power supply to the backup supply. The LANWAKEUPEN control is generated by the processor K2 to turn on the main 5VPCI supply in the computer (not shown) upon the receipt of data from a communications network (not shown) . The supply switching is carried out by two transistors Q10 and Q2. These transistors are controlled by a three transistor long tail pair comparator built around the differential pair formed from the transistors Qll, and Q3 , and the current source transistor Q12. To ensure that powering up and down is carried out without unintentional switching events occurring, ONSTBY, the control signal from processor K2 , is filtered asymmetrically by the diode, CR3 , and the RC network, R51 and C22. This filter slows the rising edge of the input signal more than the falling edge. Hence, low to high transitions of ONSTBY are more heavily filtered than low to high transitions. To ensure that powering up and down is carried out without unintentional LANWAKEUPEN events occurring, the LANWAKEUP signal from processor K2 is effectively gated with the output from this filter, by the transistor Q22. This transistor provides an open emitter follower type output to pull up an external pulldown load. The 5VSTBY input is monitored, by processor K2 , through a high value resistor, R76, to detect the presence of this supply. The presence of the 5VSTBY supply turns the transistor Q4 on due to the base current supplied to it via R12. When the transistor Q4 is turned on, it draws collector current through the resistor R15. This pulls the PWR__MODE net to ground, which indicates to the processor K2 that there is at least one standby supply available. To understand how this section of the circuit works, assume that the card is operating from the 5VPCI supply and that there is no 3VSTBY supply available. Also, assume that resistors R8 and R26 are not fitted. Lastly, assume that the collector of the transistor Q6 is returned to a positive supply of greater than 3V. The actual connection of the collector of the transistor Q6 will be described in the section on how the 5VOUT current limiting works. Under these conditions the transistor Q13 is turned on via the resistor R13 by the presence of the 5VSTBY supply. This clamps the STAIL net to ground. Hence, the transistors Q20 and Q16 are effectively unpowered and both the base emitter and base collector junctions of the transistor Q20 are reverse biased by the positive voltage that is present on the SDRV net. Because the transistor Q16 is unpowered, its collector - the 3VΞTBYCTRL net - is pulled to ground through the resistor RIO. Therefore the transistor Q5 is off because its base emitter junction is reverse biased. Hence, there is no collector current flow through the transistor Q5. The function of the transistor Q13 is explained in the section describing 3VSTBY monitoring. The emitter of the transistor Q21 is pulled to ground through the resistor R53 whilst its collector is connected to the output of the linear regulator Ul and so is at 3.3V. Therefore there can be no current flow through base of the transistor Q21. Hence there is no current flow through the transistor Q21. This maintains zero voltage across R53. The 3STBYMON input to the processor K2 is pulled to ground through the resistors R49 in series with R53. The presence of the 5VSTBY supply turns the transistor Q4 on via the resistor R12. This pulls the PWR_MODE net to ground . With the 3VSTBYCTRL net at ground, the transistor Q6 is held off, so the voltage across R20 is zero. This holds the transistor Q15 off, which therefore means that the transistor Q14 is turned on by the base current flow through the resistor R35. The collector of the transistor Q14 pulls the ZZZ net to ground and so turns the transistor Q19 on by the base current flow through R34. This base current is such that Q19 operates as a saturated switch with a very low Vce(sat) . The output of the linear regulator Ul is therefore connected to the +3V rail via the transistor Q19, and is decoupled by capacitors C23 & C24. The 3VSTBYCTRL net is also connected to the enable input, pin 4, of the LT1372 switching regulator U2 which forms part of the voltage convertor 10. Since this input is pulled to ground, this regulator is disabled, with its internal switch (at pin 8) open circuit. Hence there is no current flow through the inductor L5. The output of this regulator is connected to the card's internal +5V rail. Hence, when the card is powered from the 5VPCI or 5VSTBY supplies, CR4 is reverse biassed. This ensures that switching regulator U2 does not load the internal 5V rail . Capacitor C16 provides local input decoupling for the linear regulator Ul . In this section of the description, capacitor C30 can be considered to provide bulk decoupling for the internal +5V rail . Having established these conditions, it is now safe to assume that transistors Q13 , Q14, Q15, Q20, Q16, Q6, Q5 , Q14, Q19, & the switching regulator U2 play no further part in the description of the operation of the 5VPCI & 5VSTBY supply switching and control circuit. Supply switching components around the transistors Q10, Qll, Q3, Q2 , Q12 , Q8 & Q7 and ONSTBY signal filtering around the series connected diode CR3 will now be described. The pair of diode connected transistors, Q8 & Q7, supplies the resistor reference chain comprising R6 , R5 and R17 from the 5VPCI and/or 5VSTBY power supplies. The voltage on the 3VSWREF net at the base of transistor Q12 - set by the reference chain - of about 1.9V, together with R5 , sets the emitter current of Q12 at around 7mA. The voltage on the 5VSWREF net at the base of transistor Q3 is set by the reference chain at about 2.4V. This is just sufficient to allow transistor Q12 to operate non-saturated and so act as a constant current sink for the differential transistor pair Qll & Q3. The collectors of transistors Qll and Q3 are directly connected to the bases of transistors Q10 and Q2 respectively. This direct connection; with no bias resistors etc., is crucially important for the operation of this circuit . The transistor Q10 is the 5VSTBY supply switch, whilst the transistor Q2 is the 5VPCI supply switch. These transistors are specially chosen for their very low Vce(sat), high current capacity, and high hFE . The right hand diode of the dual series connected diode CR3 , together with the resistor R51 and capacitor C22 form a slow charge / fast discharge time constant. This is to filter out any spurious high pulses that may be present on the ONSTBY output from processor K2 during any periods when the supply to processor K2 is between zero and whatever level that is necessary to guarantee correct reset or programmed operation of this output. Since this supply condition - and device operation within it - is unspecified and can occur whenever the card is powered up or down (as opposed to switching between 5VPCI and standby power supplies) it is necessary to safeguard against these conditions. For example, if the card is connected to a standby supply but for whatever reason is allowed to power down with the 5VPCI supply, a spurious high level on the ONSTBY input could cause the card to momentarily connect to the standby supply. This could cause the card to go into a hard reset, at which point ONSTBY would be forced low and so would now disconnect the card from the standby supply and connect it back to the now removed 5VPCI . The cycle could then repeat and so set up an oscillatory state. A similar situation can arise if the card is allowed to power up without a standby supply being available. A spurious high level on the ONSTBY input could switch the card to a non-existent standby supply, forcing it to power down again, then switch back to 5VPCI and so repeat this cycle again. The resistor R37 and the other diode in CR3 serve two purposes. One is to provide a pullup to the cards internal 5V supply so that ONSTBY and the filtered version of this signal can be pulled up to above the 3.3V high level output voltage that the processor K2 can source on its own. The other is to provide a copy of this filtered signal but with a positive offset of one diode drop on the SDRV net. The purpose of this signal will be covered in the description of how the 5VPCI & 3VSTBY supply switching and control works . The filtered version of ONSTBY, 5VSTBYCTRL, is fed to the base of the transistor Qll, through the resistor R36. When 5VSTBYCTRL is more than about 0.4V below the voltage of 2.4V on the 5VSWREF net, the transistor Qll is turned off and so the transistor Q3 conducts all the tail current into the base of the transistor Q2. This is sufficient to ensure that the transistor Q2 can maintain a very low Vce(sat) for all collector currents up to about 0.5A. When 5VSTBYCTRL rises to more than about 0.4V above the voltage of 2.4V on the 5VSWREF net, the transistor Q3 is turned off and so the transistor Qll conducts all the tail current into the base of the transistor Q10. This is sufficient to ensure that the transistor Q10 can maintain a very low Vce(sat) for all collector currents up to about 0.5A. Under these conditions, the resistor R36 provides a non-zero high frequency source impedance at the base of the transistor Qll. Without this resistor, the high frequency source impedance 'seen' by the base of the transistor Qll is limited only by the ESR of the capacitor C22. Since the transistor Qll is effectively operating as an emitter follower with a high impedance emitter load (due to the constant current sink formed by the transistor Q12) , without the damping effect of the resistor R36, it can oscillate in the MHZ region. The high frequency source impedance 'seen' by the base of the transistor Q3 , due to R6, R5 & R17, is high enough to prevent oscillation when this device is turned on. Now, since all the collector current of the transistor Qll flows into the base of the transistor Q10 and all the collector current of the transistor Q3 flows into the base of the transistor Q2 , when switching takes place, it does so in a make-before-break fashion. This means that, since the rising edge of the 5VSTBYCTRL signal is changing slowly, there is a relatively long period of time where both transistor Q10 and Q2 are turned on. Consequently, if there is any potential difference between the 5VPCI and 5VSTBY supplies, there will be a current flow between them through these transistors . This does not in fact cause any problems . Any difference in supply voltages appears across both transistors in series and, at the point of maximum current flow, is shared across the two devices. The maximum current flow between the supplies occurs when the base currents to the transistors Q10 and Q2 are equal. This current flow is limited by the available base currents to the transistors Q10 and Q2. Taking a collector current of more than hFE times the base current from whichever of the transistors Q10 or Q2 is connected to the more positive of the two supplies, will cause that transistor to come out of saturation and so act as a constant current source. The current through the other transistor is therefore limited to the difference between this constant collector current and whatever the card itself is already drawing. This means that the maximum current flow between the supplies and the maximum power dissipation of both transistors are well controlled during switching. Note that this current flow during switching is from the more positive to the more negative of the supplies. Note also that due to the asymmetric rise and fall times of the 5VSTBYCTRL signal, this current flow persists for longer on switching from 5VPCI to 5VSTBY. The circuit has been designed to operate with a maximum difference between the 5VPCI and 5VSTBY supplies of 0.5V, i.e. both supplies can be 5V±5%. However, the device ratings are such that this difference is conservative. The preceding description shows one reason that the direct base current drive is important. However, direct base current drive has another important benefit. Consider the situation when a card has been switched to run from the 5VSTBY supply and the 5VPCI supply has been switched off. The emitter of the transistor Q2 would then be connected through a relatively low impedance to a voltage at or near ground. The collector of the transistor Q2 would effectively be connected, via the transistor Q10, to 5VSTBY. Any base current fed to the transistor Q2 will cause it to conduct a current from its collector to its emitter, in the reverse direction from normal PNP transistor current flow. This is due to the transistor Q2 operating in its inverse mode. The magnitude of this inverse current is unknown since the inverse α of the FMMT717 transistors is not specified. However, it is quite possible for this figure to be close to 1 and so for the transistor to have significant current gain in its inverse mode. This would cause an undesirable current flow from the 5VSTBY supply back into the 5VPCI rail. Ensuring that the only source of current to the base of the transistor Q2 is from the collector of the transistor Q3 , is the simplest way to prevent significant inverse current flow through the transistor Q2. This is also why it is important that the 5VSTBYCTRL signal rises to more than about 0.4V above the voltage on the 5VSWREF net, since then it is possible to completely cut off the transistor Q3. In the case where the card is switched to operate from 5VPCI and there is no standby supply available, it is important that there should be no inverse current flow through the transistor QIO. If this were to happen, the 5VSTBY input would be pulled up to approximately the same voltage as the 5VPCI supply. This would cause the presence of a 5VSTBY supply to be falsely indicated to processor K2 via the 5STBYMON input. Hence direct base current drive is used between the transistors Qll and QIO. Similarly this is why it is important that the 5VSTBYCTRL signal falls to less than about 0.4V below the voltage on the 5VSWREF net, in order to completely cut off the transistor Qll. The use of the LANWAKEUP control around the transistor Q22 will now be discussed. The base of the transistor Q22 is connected to the 5VSTBYCTRL signal through the resistor R50. This resistor is required to reduce the loading on the capacitor C22 and so help to preserve the maximum voltage available from this signal. The collector of the transistor Q22 is driven from the LANWAKEUP output from the processor K2 and has a pullup resistor R63, to the cards internal 5V rail. Until the card is put into a standby mode, the 5VSTBYCTRL signal will be at or somewhat below, one diode drop above ground. Therefore the base of the transistor Q22 will also be at about the same voltage. The collector of the transistor Q22 is held at a logic low by the processor K2. This means that the emitter of Q22 cannot source current into a grounded load. If, for any reason, the LANWAKEUP output from the processor K2 goes high with 5VSTBYCTRL low; then the low voltage at the base of Q22 holds LANWAKEUPEN low. Similarly, if, for any reason, the ONSTBY output from the processor K2 goes high with LANWAKEUP low; then the low voltage at the collector of the transistor Q22 holds LANWAKEUPEN low. Under these conditions, the current flowing to ground out of either the emitter or the collector of the transistor Q22 is limited by the resistor R50. This prevents the forward biased collector based junction of the transistor Q22 pulling the 5VSTBYCTRL net too far towards ground. Lastly, if, for any reason, both LANWAKEUP and ONSTBY show spurious high levels, then the 5VSTBYCTRL filter circuit maintains a low voltage at the base of the transistor Q22 and so holds LANWAKEUPEN low. The pullup resistor R63, allows the LANWAKEUP output of the processor K2 to be pulled above its normal 3.3V logic high level. Together with the effect of the pullup resistor R37, this allows a high level at the LANWAKUPEN output to rise to above the 3V rail . Without these pullup resistors, the LANWAKUPEN output could only rise to a maximum of about one diode drop below the 3V rail . Note however, that although LANWAKEUPEN can rise to an open circuit voltage of approximately one diode drop below the card's internal 5V supply, the source resistance of this output is roughly equal to the value of the resistor R63. The lower limit on the value of the resistor R63 is set by the Vol and lol limits of the LANWAKEUP output from the processor K2. A value of 3.48kΩ for the resistor R63 is considered to be a good compromise between high level output voltage vs. load current from LANWAKEUPEN and LANWKEUP low level sink current into the processor K2. Monitoring of the 5VSTBY supply will now be discussed. The presence of a 5VSTBY supply is indicated to the processor K2 , via the resistor R76, by the 5STBYMON signal. This line rises to the 5VSTBY voltage if it is connected. If this supply is not connected, 5STBYMON is pulled to ground via the resistor R76 in series with the resistor R32. If the card is allowed to power down even though 5VSTBY may be available, current will be sourced through the resistor R76 into the processor K2. A high value resistor is used for the resistor R76 to limit this current and so prevent the processor K2 going into SCR latchup when it is powered up from 5VPCI with 5VSTBY available. The presence of the 5VSTBY supply turns on the transistor Q4 due to the base current supplied to it via the resistor R12. When the transistor Q4 is turned on, it draws collector current through the resistor R15. This pulls the PWR_MODE net to ground, which indicates to the processor K2 that there is at least one standby supply available. The presence of the 5VSTBY supply also turns the transistor Q13 on via the resistor R13. This pulls the STAIL net and therefore the 3VSTBYCTRL net to ground. The function of Q13 is explained in the section describing 3VSTBY monitoring. Operation of the main 5VPCI supply and the 3VSTBY backup supply will now be discussed. This circuit comprises basically the same components as for the main 5VPCI supply and the 5VSTBY backup supply switching and control circuit but with the addition of the transistors Q13 , Q21, Q15, Q20, Q16, Q6 , Q5 , Q14 and Q19 and the switch mode boost converter based around the switching regulator U2. This part of the circuit comprises two basic functional blocks. Firstly, the 3VSTBY switching formed by the transistors Q5 & Q21 in conjunction with the transistors Q6, Q15, Q14 and Q19 and controlled by the Schmitt trigger based around the transistors Q20 & Q16, together with the switch mode boost converter based on the switching regulator U2. Secondly, the 3VSTBY backup supply monitoring. There are three basic functions to be carried out when switching from the main 5VPCI supply to the 3VSTBY backup supply. 1. Disconnect the card from 5VPCI and connect the card's internal 3V to the 3VSTBY supply; 2. Disconnect the output of the linear regulator Ul from the cards internal 3V rail to prevent undefined current flow between this output and the 3VSTBY supply. Although this current ultimately comes from the 3VSTBY supply, any drain from the output of the linear regulator Ul is sourced from the card's internal +5V rail. Any drain from this 5V supply is multiplied by the conversion ratio of the 3.3V to 5V switch mode supply based around the switching regulator U2. This multiplication represents an additional current that would increase the total current drain of the card, and so is undesirable. 3. Start up and maintain the generation of a 5V supply - using the 3.3V to 5V switch mode boost converter based around U2 - to power the 5V circuits of the card. The timing of these operations is very important. The 3VSTBY supply has to connect to the internal 3V rail just as the output of the linear regulator Ul is being disconnected from it. This is to avoid a drop in the internal 3V rail . The internal 5V supply must be brought up and be ready to be connected to the internal 5V rail just as the 5VPCI supply is being disconnected from it. This is to avoid a drop in the internal 5V rail. When switching from the 3VSTBY backup supply to the main 5VPCI supply, the actions of these three operations have to be reversed. The 3VSTBY backup supply has to disconnect from the internal 3V rail just as the output of the linear regulator Ul is being connected to it. This is to avoid a drop in the internal 3V rail . The main 5VPCI supply must be connected to the internal 5V rail just as the switch mode supply is turned off. This is to avoid a drop in the internal 5V rail. The 3VSTBY input is monitored, by the processor K2 , through a high value resistor R49 to detect the presence of this supply. The presence of the 3VSTBY backup supply turns the transistor Q4 on due to the base current supplied to it via the resistor R7. When the transistor Q4 is turned on, it draws collector current through the resistor R15. This pulls the PWR_MODE net to ground, which indicates to the processor K2 that there is at least one standby supply available . To understand how this section of the circuit works, assume that the card is operating from the main 5VPCI supply and that there is no 5VSTBY backup supply connected. In the absence of a 5VSTBY backup supply, the transistor Q13 can be ignored since it is turned off because its base is pulled to ground via the resistor R78 and the series connection of resistors R13 and R32. Under these conditions the LANWAKEUPEN signal is also not connected, and the transistors QIO, Qll and Q22 can be ignored in this description. Also, assume that the resistors R8 and R26 are not fitted. Lastly, assume that the collector of the transistor Q6 is returned to a positive supply of greater than 3V. The actual connection of the collector of the transistor Q6 will be described in the section describing how the 5VOUT current limiting works. Under these conditions, the transistor Q4 is turned on due to the base current supplied to it from the 3VSTBY supply via the resistor R7. The PWR_MODE net is pulled to ground by the collector current of the transistor Q4 through the resistor R15. When the transistor Q4 is turned on, its base emitter voltage is about 0.65V. The potential divider formed by resistors R12 and R32, together with resistors R13 and R78, prevents any possibility of this base emitter voltage turning the transistor Q13 on via the resistor R13. With the resistor values used in the schematic, and with no 5VSTBY supply connected, the voltage across the resistor R78 is kept to <10mV. The function of the transistor Q13 is explained in the section relating to 3VSTBY monitoring. The operation of switching from the main 5VPCI supply to the 3VSTBY backup supply will now be described. Disconnecting the 5VPCI supply, connecting the 3VSTBY supply and disconnecting the output of the linear regulator Ul from the internal 3V rail will be described first. Transistors Q20 and Q16 together with resistors RIO, Rll and R31, form a Schmitt trigger, with upper and lower thresholds - as seen at the SDRV net - of approximately 1.8V and 1.4V respectively. These thresholds are held independent of the external supply voltages by supplying the resistor R31 from the regulated 3.3V output of the linear regulator Ul . The input to this trigger is the SDRV signal. As described above, this signal is a copy of the 5VSTBYCTRL signal but with an additional positive offset of one diode drop. This offset together with the voltage drop in the resistor R37 due to the base current of the transistor Q20 has been set up such that, as 5VSTBYCTRL rises, SDRV crosses the upper threshold of the Schmitt trigger when 5VSTBYCTRL is approximately 0.6V below the voltage on the 5VSWREF net. This ensures that the transistor Qll is not starting to turn on by the time the Schmitt trigger changes state for a 5VPCI supply of anywhere in the range of 5V±5%. When ONSTBY is low, SDRV sits at about 1.1V. This is about 0.3V below the lower threshold, so the transistor Q20 is turned on. The voltage across the transistor Q20 is less than 50mV so the transistor Q16 is turned off. The collector voltage of the transistor Q16 is pulled to ground through R10. The emitter of the transistor Q5 is held at about 1.2V by the emitter of the transistor Q12, hence the transistor Q5 is cut off. When ONSTBY rises, 5VSTBYCTRL rises more slowly. When SDRV crosses the upper threshold of the Schmitt trigger, the transistor Q20 snaps off and the transistor Q16 snaps on. Since the base and collector currents of the transistor Q16 are of the same order of magnitude, Q16 is saturated. The voltage at the base of the transistor Q5 is therefore largely set by the regulated 3.3V output from the linear regulator, Ul , less the voltage drop across the resistor R31 due to the current flowing through it. Since the current flowing through the resistor R31 is greater when the transistor Q16 is turned on than when the transistor Q20 is turned on, the voltage drop across the resistor R31 is greater when the transistor Q16 is on than when the transistor Q20 is on: this determines how the hysteresis and trigger levels are set up. When the transistor Q16 is turned on, the voltage at the transistor Q5 base has been set up to be about 0.8V above the voltage on the 3VSWREFnet . This ensures that, when the transistor Q16 is turned on, the transistor Q5 is turned fully on and the transistor Q12 is turned completely off over the full 5VPCI supply range of 5V+5%. It is important that, when operating from the 3VSTBY, the transistor Q12 is always turned fully off to prevent any reverse current flow into the 5VPCI and / or 5VSTBY supplies due to collector currents from the transistors Q3 and Qll causing inverse transistor action in the transistors Q2 and QIO respectively. As the transistor Q5 is turned on, its emitter pulls the voltage across the resistor R9 up to about 2V. As well as cutting the transistor Q12 off, this increases the collector current of the transistor Q5 from the nominal 7mA that is set by the transistor Q12 up to a nominal 12mA. This satisfies the requirement that the base current to the transistor Q21 should be greater than that supplied to the transistors Q2 and QIO. This requirement arises because, when operating from a 3VSTBY backup supply, the card has to generate its internal 5V supply using the switch mode regulator based around the switching regulator U2. This in turn means that the card draws much more current when running from 3VSTBY than a 5V supply and so the transistor Q21 has to carry a much larger collector current than the transistors Q2 or QIO. When the transistor Q5 turns on, all its collector current is drawn through the base of the transistor Q21 and so the transistor Q21 turns on as a saturated switch with a very low Vce(sat) . Also, when the transistor Q16 turns on, the transistor Q6 is turned on. This causes its emitter voltage to rise to about 1.8V which turns Q15 on via R16. The collector of the transistor Q15 pulls the XXX net to ground, which turns the transistor Q14 off. Since the collector of Q14 is the only source of base current for the transistor Q19, this transistor turns off. This direct base drive connection ensures that, when the transistor Q14 is off, there can be no base current supplied to the transistor Q19 and so there can be no forward or inverse conduction in this device irrespective of whether the 3VSTBY backup supply voltage is above or below the output voltage of the linear regulator Ul. Hence, the output of the linear regulator Ul is disconnected from the cards internal 3V rail. Note that when the card is powered from the 3VSTBY supply and the 5VPCI supply is allowed to collapse, the voltage across the reference chain, R6 , R5 and R17 also collapses. This pulls the bases of the transistors Q3 and Q12 to ground. This causes the transistors Q3 and Q12 base emitter junctions to be reverse biased. This isolates the transistor Qll and so removes any possibility of base current being drawn by the transistors Q2 or QIO, thus ensuring that the card is fully disconnected from the 5VPCI and 5VSTBY connections. Next connecting of the internally generated 5V supply to the internal 5V rail will be described. When the transistor Q16 is off, the voltage on the enable input, pin 4, of the LT1372 switching regulator U2 , is very close to ground. This holds the regulator in the off state, with its internal switch (at pin 8) open circuit. However, when the transistor Q16 turns on, the voltage on the 3VSTBYCRL net rises to a minimum of about 2.4V. This voltage is sufficient to enable the regulator U2. The output of the boost converter based around the regulator U2 is developed across the capacitor C30. However, until the regulator U2 is enabled, the diode, CR4 , is reverse biased and so the capacitor C30 is charged up to the voltage of the internal +5V rail . During an interval of about lOOmicroseconds following the instant of switching from 5VPCI to 3VSTBY operation and enabling the regulator U2 , the 5V rail drops to about 4.4V. The voltage climbs back up to >4.75V over about the next 200 microseconds, due to the time taken for the control voltage at pin 1 of the regulator U2 to reach its normal operating point. When the regulator U2 is enabled, this control voltage is initially at a low voltage, whereas the output voltage of the converter is at approximately 5V. To begin with, the charge stored in capacitors C16, C58, C57 and C30 supplies all the load current which causes the regulator U2 to behave as though it were only operating with a very light load current. Under these conditions the regulator U2 reduces its internal switch current and so its output voltage rises quite slowly. It is not until the output voltage of the converter as determined by the control voltage, has exceeded that which the 5V rail has decayed to (and therefore has to source significant current into this rail) , that the converter settles into regulation. Once the regulator U2 has settled and is operating normally it sources all the 5V rail current. This current is about 112mA. The boost converter is boosting from a nominal 3.3V up to 4.9V and is about 83% efficient, so the current it draws from the 3VSTBY supply is about 200mA. Note the presence of the two lOmicrofarad Tantalum capacitors C23, C24 at the input to the boost converter circuit. These capacitors also form part of the output decoupling capacitance for the linear regulator Ul . It has been found that different manufacturers' versions of the LT1117-3.3 type regulators behave very differently to load current transients, if their outputs are decoupled with high value ceramic capacitors. Using two Tantalum capacitors in this location very much reduces this variability in responses to load current transients whilst keeping the ESR of the input decoupling for the boost converter at a low enough value that the switching ripple and noise across C23 & C24 is maintained at an acceptably low level . Note also that C30 is a lOmicrofarad ceramic capacitor. This type of capacitor is used to provide a very low ESR decoupling path directly across the output of the boost converter in order to minimise the switching ripple and noise introduced into the card's internal 5V rail, when it is running from the 3VSTBY supply. This completes the description of switching from the 5VPCI supply to the 3VSTBY supply. Next switching from 3VSTBY to 5VPCI will be discussed. Firstly this requires disconnecting the 3VSTBY supply, connecting the 5VPCI supply and connecting the output of the regulator Ul to the internal 3V rail. When ONSTBY goes low, SDRV falls at a rate determined by the output resistance of the ONSTBY output of the processor K2 in series with the slope resistance of both diodes in CR3 in series. When SDRV falls below the lower threshold of the Schmitt trigger based on the transistors Q20 and Q16, the transistor Q20 snaps on and so Q16 snaps off. The collector voltage of the transistor Q16 is pulled to ground through the resistor RIO. This reverse biases the base emitter junction of Q5 so it turns off. The base current to the transistor Q21 is therefore removed so it turns off. The voltage across R9 falls towards ground until the base emitter junction of the transistor Q12 is forward biased. This turns the transistor Q12 on and re-establishes the 7mA tail current for the transistors Qll and Q3. Since the base voltage of the transistor Q3 is about 2.4V and that at the base of the transistor Qll is at about IV, the transistor Q3 turns on and so the transistor Q2 turns on. This connects the 5VPCI supply to the cards internal 5V rail. Also, when the transistor Q16 turns off, the transistor Q6 is turned off. This causes its emitter voltage to fall to ground, which turns the transistor Q15 off via the resistor R16. The resistor R35 pulls the XXX net up, which turns the transistor Q14 on. The collector of the transistor Q14 then sinks base current for the transistor Q19 through R34, turning this transistor on. Hence, the output of the regulator Ul is connected to the cards internal 3V rail. Bringing down the internally generated 5V supply and disconnecting it from the internal 5V rail will now be described. When the transistor Q16 turns off, the enable input of the regulator U2 is pulled to ground through RIO. This disables operation of U2. Note that, due to an internal timer in the regulator U2 , the device actually disables anywhere between 5 microseconds and 25 microseconds after its enable input has gone low. This means that there is a short time when if the 5VPCI voltage is below the boost converters output voltage, the boost converter may attempt to hold up the cards internal 5V rail. This may result in a momentary increase in the 5VPCI current drain. However, once this time has elapsed, the 5V rail is supplied only from the 5VCPI supply and so the current drain will return to normal. Once the regulator U2 is disabled, the diode, CR4 , is reverse biased and so prevents the regulator U2 loading the 5V rail. This completes the description of switching from the 3VSTBY supply to the 5VPCI supply. Monitoring of the 3VSTBY supply will now be described. The presence of a 3VSTBY supply is indicated to the processor K2 , via R49, by the 3STBYMON signal. This line rises to the 3VSTBY voltage if it is connected. If this supply is not connected, 3STBYMON is pulled to ground via the resistor R49 in series with the resistor R53. If the card is allowed to power down even though 3VSTBY may be available, current will be sourced through R49 into the processor K2. A high value resistor is used for R49 to limit this current and so prevent the processor K2 going into SCR latchup when it is powered up from 5VPCI with 3VSTBY available. The presence of the 3VSTBY supply turns on the transistor Q4 due to the base current supplied to it via the resistor R7. When the transistor Q4 is turned on, it draws collector current through R15. This pulls the PWR_MODE net to ground, which indicates to the processor K2 that there is at least one standby supply available. This description has so far assumed that the card is in a PC where only 5VPCI and 3VSTBY supplies are available. However, if it is now assumed that the card is put in a PC where 5VPCI , 3VSTBY and 5VSTBY supplies are available then the operation of the transistor Q13 can be described. Under these conditions, the presence of the 5VSTBY supply turns on the transistor Q13 due to the base current supplied to it via the resistor R13. When the transistor Q13 is turned on, it draws collector current through the resistor R31. This pulls the STAIL net to ground. With the STAIL net clamped to ground by the transistor Q13, the 3VSTBYCTRL net is pulled to ground through RIO. This means that, if both standby supplies are available, and ONSTBY is set high, the transistors Q5 , Q6 and the regulator U2 cannot be turned on. Therefore, the supply switching reverts to operating as if only the 5VPCI and 5VSTBY supplies are available, and so the card is switched to run off the 5VSTBY supply. Note that the PWR_MODE net is still pulled to ground, which indicates to the processor K2 that there is at least one standby supply available. Note also that the presence of the 5VSTBY supply is indicated to the processor K2 via R76. Next 5VOUT current limiting will be described. The circuit effectively comprises 3 transistors, 6 resistors, and one capacitor. It provides the following functions : 1) Short circuit current limiting for a 5VOUT connection to the outside world via a connector (not shown) . This is to prevent the 5VPCI, 5VSTBY and 3VSTBY switch transistors being damaged in the event of the 5VOUT output being shorted to ground. 2) An adjustable current limit setting such that the maximum current is available when the card is running from either the 5VPCI or 5VSTBY supply whilst zero current is available if the card is running from the 3VSTBY supply. 3) An indication to the processor K2 - via the LIMITING output being pulled high - that the current drawn by the external load connected to the 5VOUT output is close or equal to the current limit setting. The transistor Ql acts as the series pass element. The load current drawn from 5VOUT is sensed by the clamp transistor Q9 which monitors the voltage across the resistor R19. The clamp transistor progressively reduces the base current to the transistor Ql in response to increasing load current. This creates a constant current limiting action at the 5VOUT output. As current limiting is approached, the voltage across R47 rises and is used to indicate to the processor K2 that the current drawn by the external load connected to the 5V0UT output is close or equal to the current limit setting. This is the LIMITING output. The transistor Q6 controls the current limit setting. It has no effect when the card is running from the main 5VPCI or backup 5VSTBY supply. However, when the card is run from the 3VSTBY backup supply, it draws current through the base of the transistor Q9, which turns this transistor on and so turns off the transistor Ql . This makes the circuit behave exactly as if the current limit has been reached but with zero load current. Hence, when the card is running from the 3VSTBY supply, the LIMITING output is always high. The circuit used to achieve this comprises 3 transistors Q6, Q9 & Ql, 6 resistors R47, R20, R43, R16, R19 & R2 and the capacitor C2. The voltage across the resistor R47 is monitored by the LIMITING input to the processor K2 and can be used to determine the state of the current limit circuit. To understand how this circuit works, first consider the case where the card is running from the main 5VPCI or 5VSTBY backup supply. Under these conditions, the transistor Q6 is off and, therefore, is drawing no collector current. Hence it has no effect on the base current of the transistor Q9. For external load currents substantially below the current limit, the transistor Ql is saturated by the base current flowing to ground through R43 in series with R47. This current is approximately 1mA and so creates a standing voltage of about 0.39V across the resistor R47. Due to the hFE of the transistor Ql, the emitter current of the transistor Ql is effectively equal to the external load current. This emitter current flows through the resistor R19. At low external load currents the voltage drop across R19 is too small to turn the transistor Q9 on. Hence there is no collector current flow in the transistor Q9. As the external load current increases, the voltage drop across R19 increases until - at about 100mA - it reaches approximately one diode drop. This is enough to make Q9 start to turn on. As Q9 turns on, it draws collector current through R47. This diverts current from R43 and so steals base current away from Ql . This then causes Ql to come out of saturation and so supply its collector current effectively from a constant current source . At the same time, as the transistor Q9 collector current increases, so does the voltage drop across R47, until when the transistor Ql is in full current limit this voltage rises to approximately 2.4V. This voltage is accounted for as the diode drop due to the voltage across the resistor R19 plus the base emitter voltage and the voltage drop across the resistor R43 due to the base current necessary to keep the transistor Ql conducting and supplying current to the load. The nominal short circuit limit current is approximately 110mA. Note that the 5VPCI (and 5VSTBY) current setting of this circuit is not precise since it is influenced by temperature and individual transistor parameters. The 5VPCI (and 5VSTBY) limit will reduce by approximately 20mA over the temperature range 0°C to 70°C. Now, consider the case where the card is running from the 3VSTBY supply. Under these conditions, the transistor Q6 is turned on. It sources an emitter current of approximately 500microamps into the resistors, R20, and, via the base of the transistors Q15, R16. Therefore, the transistor Q6 draws a collector current of approximately 500microamps through R2 and the base of the transistor Q9. This current is well in excess of that which is required to fully saturate the transistor Q9. Hence, the transistor Ql is turned off and so cannot supply any load current. At the same, the LIMITING output is pulled up to the internal 5V rail . The capacitor C2 is required to prevent high frequency oscillation of the negative feedback loop formed around the transistors Q9 and Ql when they are operating at or near the current limit. Operation of the Power Management Event (PME) output interface will now be described. This section of the circuit comprises transistors Q17 and Q18 together with resistors R27, R21, R28 and R14 and capacitor C3. Together they provide a true open collector output to the PME# pin on the PCI bus connector PI (not shown) . This output is protected from producing any spurious PME events during any card power up and power down phases. The operation of this interface is dependent upon the P_/PMEK and NOPME signals from the processor K2 obeying the following rules: 1. When the processor K2 is in reset, P_/PMEK is held in a high impedance state; 2. When the processor K2 is in reset, NOPME is held at a 3V logic high level; 3. When the processor K2 exits its reset state, P_/PMEK is held in a high impedance state except while it is required to assert a low on the PME# pin of PI (pin A19) (not shown) ; 4. When the processor K2 exits its reset state, NOPME is set to logic low until it has been decided that the card will be allowed to power down (as opposed to switching to a standby supply) ; 5. When it has been decided that the card will be allowed to power down (as opposed to switching to a standby supply) NOPME will be set to a logic high. The state of NOPME will not be permitted to change until the cards internal supplies have fallen below the level at which normal operation of the processor K2 can be guaranteed; 6. P_/PMEK will not be permitted to assert a logic low for at least 2ms after NOPME has been set to a logic low following the processor K2 exiting its reset state; 7. Note that - when it has been decided that the card will be allowed to power down (as opposed to switching to a standby supply) - from the time at which NOPME is set to a logic high until the card's internal supplies have fallen below the level at which the normal operation of the processor K2 can be guaranteed, the state of P_/PMEK shall have no effect on the PME# pin of PI (not shown) . It must be remembered that the P_/PMEK output of the processor K2 is configured as an 'open drain' output. This configuration is realised as a tristate buffer whose input is hardwired to set a logic low at its output. To understand how this section of the circuit works, assume that the card is unpowered and has been so for long enough that the voltage across the capacitor C3 has settled to zero. Assume also that NOPME is at ground and the state of P_/PMEK is undefined. When the main 5VPCI supply is applied to the card, the voltage across the capacitor C3 rises with a time constant determined by the value of C3 and the resistance of R27 in parallel with the resistance of R21 together with the load presented by the resistor R28 and the base emitter junction of the transistor Q18, towards the Thevenin equivalent voltage of approximately 1.2V set by these components. The emitter of the transistor Q18 can be pulled to ground by the low active P_/PMEK output from the processor K2. However, until the voltage across C3 reaches about 0.6V, a low on P_/PMEK will not cause collector current to flow in the transistor Q18. During power up - until the processor K2 is properly operating in its reset state and is therefore guaranteed to be holding P_/PMEK in a high impedance state - this mechanism ensures that a spurious low level on this output cannot pull the PME# pin low. While the processor K2 is in its reset state, the P_/PMEK output is held in a high impedance state and the NOPME output is held high. The high on NOPME turns the transistor Q17 on, via the resistor R14 , which discharges the capacitor C3 , and clamps the base of the transistor Q18 to ground, holding this device off. Some time after the processor K2 exits its reset state, NOPME is set to a logic low. This allows C3 to charge up and effectively enables the transistor Q18. When it is required to assert a logic low on the PME# pin, P_/PMEK is set to a logic low state. This forward biases the base emitter junction of the transistor Q18. This causes the transistor Q18 to draw collector current and so pull the PME# pin low through its external pullup resistance . With the components shown in Figure 2, the transistor Q18 can sink about 17mA if the P_/PMEK net is shorted to ground. In practice this current will be limited by the logic low level output resistance of the P_/PMEK output of the processor K2 , and by the value of the external pullup resistance connected to the PME# pin. Setting P_/PMEK back to a high impedance state cuts off the current to the transistor Q18 and allows its emitter to float. Hence, the collector of the transistor Q18 can be pulled high by the external pullup resistance on the PME# pin. With P_/PMEK set to a high impedance state, pulling the PME# pin to a voltage of between zero and about 0.6V will forward bias the collector base junction of Q18. This will cause a small current to flow out of the collector of the transistor Q18. This current is at a maximum when the PME# pin is at zero volts and is approximately equal to 0.8V/ [R28+ (R27 x R21) / (R27+R21) ] . With the components shown in Figure 2, this current is about lOOmicroamps . When it has been decided that the card will be allowed to power down (as opposed to switching to a standby supply) NOPME is set to a logic high, which turns Q17 on. This discharges C3 , and clamps the base of Q18 to ground, holding this device off. Since NOPME maintains a high enough voltage at the base of Q17 to keep it turned on at least until the card's internal supplies have fallen below the level at which normal operation of the processor K2 can be guaranteed, the capacitor C3 is held discharged for as long as possible into the power down state. If the card's internal 3V rail has not fallen below 0.6V by the time the transistor Q17 turns off, the subsequent slow charging of C3 from what is now a falling power supply should prevent any spurious low levels on P /PMEK from causing the PME# pin to be pulled low.

Claims: CLAIMS 1. A power supply interface for coupling a selected one of at least a first supply and a second supply to a processing circuit of a computing device, the processing circuit normally being powered by the first supply, wherein the computing device includes a processor which generates a power supply control signal when power is to be supplied by the second supply, the power supply interface comprising: first and second power supply inputs for coupling to the main supply and backup supply respectively; a power supply output coupled to the processing circuit ; a detector for detecting the power supply control signal; and, a switching device responsive to the detector to selectively couple the second power supply input to the power supply output . 2. A power supply interface according to claim 1, wherein the processor generates the power supply control signal when the computing device enters a power saving mode, wherein the first supply comprises a main supply and wherein the second supply comprises a first backup supply. 3. A power supply interface according to claim 2, wherein the detector is adapted to detect when the computing device exits the power saving mode and cause the switching device to selectively couple the first power supply input to the power supply output . 4. A power supply interface according to claim 3, wherein the detector is adapted to detect when the computing device exits the power saving mode by detecting signals generated by the processor. 5. A power supply interface according to claim 3 or claim 4, wherein when the computing device exits the power saving mode, the switching device is adapted to couple the first power supply input to the power supply output and subsequently decouples the second power supply input from the power supply output . 6. A power supply interface according to any of the preceding claims, wherein when the processor generates the power supply control signal, the switching device is adapted to couple the second power supply input to the power supply output and subsequently decouple the first power supply input from the power supply output . 7. A power supply interface according to any of the preceding claims, wherein when a second power supply is connected to the second power supply input, the switching device is adapted to generate a supply signal which indicates to the detector that a second supply is provided, and wherein, if no second supply is connected, the detector is adapted to inhibit the coupling of the second power supply to the power supply input . 8. A power supply interface according to any of the preceding claims, the switching device further comprising a first switching element for selective coupling the first power supply input to the power supply output, a second switching element for selective coupling the second power supply input to the power supply output, and a controller coupled to the detector and the first and second switching elements, the controller being adapted to control the switching elements in response to the detector. 9. A power supply interface according to any of the preceding claims, the switching device further comprising a third power supply input for coupling to a third supply, and wherein the switching device selectively couples the first, second or third power supply inputs to the power supply output . 10. A power supply interface according to claim 9, wherein when a third power supply is connected to the third power supply input, the switching device is adapted to generate a further backup supply signal which indicates to the detector that a third supply is provided. 11. A power supply interface according to claim 9 or claim 10, when dependent on claim 8, the switching device further comprising a third switching element, coupled to the controller, for selective coupling the third power supply input to the power supply output . 12. A power supply interface according to any of the preceding claims, wherein the first supply has a first supply voltage and wherein the second supply has a second supply voltage, the switching device further comprising a convertor coupled to the power supply output , wherein when the second power supply input is coupled to the power supply output, the convertor converts the second supply received at the second power supply input into a modified second supply having the first voltage and then transfers the modified second supply to the power supply output. 13. A power supply interface according to claim 12, when dependent on at least claim 9, the third power supply having the first supply voltage, wherein when the processor generates a power supply control signal, the switching device is adapted to couple the third power supply input to the power supply output and subsequently decouples the first power supply input from the power supply output. 14. A power supply interface according to claim 13 , when dependent on at least claim 9, the third supply comprising a second backup supply. 15. A computing system comprising a computing device having a processing circuit and a processor, a first power supply and at least a second power supply and a power supply interface according to any of the preceding claims, for coupling the main and backup supply to the processing circuit of a computing device. 16. A network interface card for coupling a computing device to a communications network, the interface card comprising: a power supply interface according to any of claims 3 to 14 when dependent on at least claim 3 , first output port for coupling to the computing device; and, second port for coupling to the communications network, wherein the second port is coupled to the detector of the power supply interface, the detector being adapted to detect data received from the network and generate a control signal which causes the computing device to exit the power saving mode . 17. A method of operating a power supply interface for coupling a selected one of at least a first supply and a second supply to a processing circuit of a computing device, the processing circuit normally being powered by the first supply the computing device including a processor, wherein the computing device includes a processor which generates a power control signal when power is to be supplied by the second supply, the power supply interface having first and second power supply inputs for coupling to the first supply and the second supply respectively, a power supply output coupled to the processing circuit, and a switching device for selectively coupling the first or second power supply inputs to the power supply output, the method comprising: detecting the power supply signal; and, in response thereto, causing the switching device to selectively couple the second power supply input to the power supply output . 18. A method according to claim 17, wherein the processor generates the power supply control signal when the computing device enters a power saving mode, wherein the first supply comprises a main supply and wherein the second supply comprises a first backup supply. 19. A method according to claim 18, the method further comprising detecting when the computing device exits the power saving mode and causing the switching device to selectively couple the first power supply input to the power supply output . 20. A method according to claim 19, wherein when the computing device exits the power saving mode, the switching device couples the first power supply input to the power supply output and subsequently decouples the second power supply input from the power supply output . 21. A method according to any of claims 17 to 20, wherein when the processor generates a power supply control signal, the method further comprises causing the switching device to couple the second power supply input to the power supply output and subsequently decouple the first power supply input from the power supply output . 22. A method according to any of claims 17 to 21, wherein if no second supply is connected, the method further comprises inhibiting the coupling of the second power supply to the power supply output when a power supply control signal is generated by the processor. 23. A method according to any of claims 17 to 21, the power supply interface further comprising a third power supply input for coupling to a third supply, the method further comprising causing the switching device to selectively couple the first, second or third power supply inputs to the power supply output. 24. A method according to claim 23, wherein the first and third supplies have a first supply voltage, and the second supply has a second voltage, the method further comprising, when the processor generates the power supply control signal, causing the switching device to couple the third power supply input to the power supply output and subsequently decouple the first power supply input from the power supply output. 25. A method according to claim 23 or claim 24, wherein the third supply comprises a second backup supply.

Inventors: FIERMAN ANDREW NEIL, FIERMAN, ANDREW, NEIL
Applicants: FIERMAN ANDREW NEIL, MADGE NETWORKS LTD, FIERMAN, ANDREW, NEIL, MADGE NETWORKS LIMITED
Application year: 1999
Main classification: G06F1
IPC codes: G06F1