MAINTAINING OBJECT SIZE INFORMATION CONCURRENT WITH DATA OPTIMIZATION FOR DEBUGGING

Abstract: A debugging environment maintains object information (e.g., object size) concurrently with data optimization operations by a write buffer of a target system. Within the target system, a system bus is coupled between a system memory and a microcontroller. A data optimization operation by the write buffer is detected by monitoring of a merge signal of the system bus by a bus monitoring device. When a data optimization operation is detected, data optimization attributes (e.g., object information, data and address) associated with the data optimization operation are captured in the form of an object information signal responsive to a capture signal from the bus monitoring device. The data optimization attributes may be stored in either a trace cache of the target system or a memory of external trace capture equipment connected to the debug port, or a memory of the bus monitoring device. In providing the data optimization attributes external to the microcontroller, the data optimization attribute may be temporarily held by trace pins of a debug port of the microcontroller. The data optimization attributes may be extracted from the object information signal and processed by the external trace capture equipment or the bus monitoring device. By processing the data optimization attributes, pre-optimization write object values may be reconstructed.

Description: APPLICATION FOR PATENT TITLE MAINTAINING OBJECT S IZE INFORMATION CONCURRENT WITH DATA OPTIMIZATION FOR DEBUGGING SPECIFICATION TECHNICAL FIELD The present invention relates to debugging of software for processor-oπented systems, and more particularly to maintaining object information concurrent with data optimization BACKGROUND ART In order to improve performance of a processor-onented system, there has been an effort to decouple processor performance from the limitations of system bus performance This effort has been pursued by providing a wπte buffer to control access to a system resource of a processor-onented system Read operations are normally given the highest pπoπty for access to a system bus Other accesses to a system bus such as wπte operations result in a delay of wπte data in a wπte buffer until the system bus becomes available A wπte buffer has mcreasmgly been provided in processor-oπented systems to perform data optimization operations such as wπte merging, wπte collapsing, and read merging for maintaining data coherency One candidate for queuing in a wπte buffer is a wπte object value As a result of data optimization operations involving wπte object values, object size information for wπte object values has been lost That is, the optimized object values no longer accompany the corresponding object size information For example, if a wπte buffer merges two consecutive byte- sized object values mto a single word-sized object value, then the wπte buffer loses the object size of the oπginal object values, as the new data object is word-sized rather than byte-sized The object size information lost as a result of data optimization operations has been a limiting factor in debuggmg a software program of a processor-oπented system A software program executed by a processor-oπented system has been used to perform wπte operations on data objects When a software program does not utilize data optimization, the software program has typically been debugged by tracing or tracking wπte object values resulting from wπte operations. Reconstruction of wπte object values m debugging a software program, however, has been constrained by data optimization operations by a wπte buffer A wπte object value resulting from a data optimization operation has lacked the object size information necessary to reconstruct pre-optimization wπte object values. DISCLOSURE OF THE INVENTION Bπefly, a debugging environment m accordance with the present mvention maintains object information concurrent with data optimization operations by a wπte buffer of a target system Within the target system, a system bus is coupled between a system memory and a microcontroller A data optimization operation by the wπte buffer is detected by monitoring of a merge signal of the system bus by a bus monitoring device When a data optimization operation is detected, data optimizanon attπbutes (e g , object information, data, and address) associated with the data optimization operation are captured m the form of an object information signal responsive to a capture signal from the bus monitoring device. The data optimization attπbutes may be stored in either a trace cache of the target system or a memory of external trace capture equipment connected to the debug port, or a memory of the bus momtonng device. In providing the data optimization attπbutes external to the microcontroller, the data optimization attnbute may be temporanly held by trace pins of a debug port of the microcontroller. The data optimization attπbutes may be extracted from the object information signal and processed by the external trace capture equipment or the bus momtonng device. By processmg the data optimization attπbutes, pre-optiitiization wnte object values may be reconstructed. BRIEF DESCRIPTION OF THE DRAWINGS A better understanding of the present invention can be obtamed when the following detailed descπption of the invention is considered m conjunction with the following drawings, in which: Figure 1 is a schematic diagram of an exemplary software debugging environment m accordance with the present invention; Figure 2 is a schematic diagram depicting a wnte buffer of Figure 1 m relation to a merge signal m accordance with the present invention; Figure 3 is a schematic illustration of the wnte buffer of Figures 1 and 2 m accordance with the present invention; Figure 4 is a logic table of an exemplary object size flag of Figure 3 m accordance with the present invention; Figure 5 is a flow chart of a data optimization attributes save process in accordance with the present invention; and Figure 6 is a flow chart of a data optimization attπbutes debug process in accordance with the present invention. MODE(S) FOR CARRYING OUT THE INVENTION RELATED APPLICATIONS The following related patent applications are hereby incorporated by reference as if set forth in their entirety: Commonly-assigned U.S. Patent Application, Seπal No 09/008,394, filed January 16, 1998, and entitled "WRITE-BUFFER FIFO ARCHITECTURE WITH RANDOM ACCESS SNOOPING CAPABILITY", Commonly-assigned U.S. Patent Application, Senal No. 08/992,610, filed December 17, 1997, and entitled "MICROPROCESSOR-BASED DEVICE INCORPORATING A CACHE FOR CAPTURING SOFTWARE PERFORMING PROFILING DATA", Commonly-assigned U.S. Patent Application, Serial No. 08/949,897, filed October 14, 1997, and entitled "TRACE CACHE FOR A MICROPROCESSOR-BASED DEVICE"; and Commonly-assigned U.S. Patent Application, Serial No 08/932,597, filed August 25, 1997, and entitled "SOFTWARE DEBUG PORT FOR A MICROPROCESSOR." Referring to Figure 1, an exemplary software debugging environment E m accordance with the present invention is shown. The software debugging environment E provides a target system T, a host system H, and a bus momtonng device BMD. In the disclosed embodiment, the target system T mcludes a microcontroller C coupled to a system memory M through a system bus SB. Alternatively, m place of the microcontroller C, the target system T may provide a different embedded processor device. The disclosed microcontroller C mcludes an execution unit 10, a trace cache 12, a trace cache control block 14, a wπte buffer 16, a debug port 18, and signal generating logic 22 for generating an object information signal (OBI) in accordance with the present mvention. Certain components of the microcontroller C which are not necessary to gam a full understanding of the present invention have been omitted. The execution unit 10 may provide a highly integrated processor 11 for executing code stored by the system memory M. The execution unit 10 m the disclosed embodiment is compatible with the Ami 86 instruction set implemented m a vaπety of microcontrollers from Advanced Micro Devices, Inc. of Sunnyvale, California. A vaπety of other execution units could be used instead of the execution unit 10. In accordance with the present mvention, the trace cache 12 and the trace cache control block 14 cooperate to capture data optimization attπbutes concuπent with a data optimization operation. Details concerning data optimization attπbutes are provided below. Data optimization attributes stored m the trace cache 12 may be provided to the host system H, or alternatively, the target system T may be configured to examine the data optimization attπbutes in the trace cache 12 internally Further, trace capture by the trace cache 12 may be selectively enabled and disabled. It is contemplated that the trace cache 12 may be a first-in, first-out (FIFO) circular cache. The trace cache is further descπbed m commonly-assigned U.S. Patent Application, Senal No. 08/992,610, entitled "MICROPROCESSOR-BASED DEVICE INCORPORATING A CACHE FOR CAPTURING SOFTWARE PERFORMING PROFILING DATA", commonly-assigned U.S. Patent Application, Senal No. 08/949,897, entitled "TRACE CACHE FOR THE MICROPROCESSOR-BASED DEVICE", and commonly-assigned U.S. Patent Application, Senal No. 08/932,597, entitled "SOFTWARE DEBUG PORT FOR A MICROPROCESSOR." The debug port 18 preferably uses an IEEE-11.49.1-1990 compliant JTAG interface or other similar standardized senal port interface. The debug port 18 is capable of utilizing the trace cache 12. The debug port 18 may include a variety of registers such as a transmitting register (TX-DATA), a receivmg register (RX-DATA), an instruction trace configuration register (ITCR), and a debug control-status register (DCSR). The transmitting register holds data to be transmitted from the microcontroller C, and the receivmg register stores data received by the microcontroller C. The mstruction trace configuration register provides for enablmg, disablmg and configuration of trace debug functions. The debug control-status register provides an indication of when the execution unit 10 has entered a debug mode. In accordance with the present mvention, the debug port 18 further provides trace pms 20 for temporarily holdmg data optimization attributes to be provided externally Like the trace cache, the debug port is further descnbed m the patent applications referenced above. The wπte buffer 16 (Figs. 1, 2, and 3) is preferably a wnte buffer with random access snooping capability. The wnte buffer 16 supports wnte mergmg, wnte collapsing, and read merging. A wnte merge or wnte collapse operation may be performed m response to assertion of a WR MERGE signal (Fig. 2). A read merge operation may be performed m response to assertion of an RD MERGE signal (Fig 2). The wnte buffer 16 mcludes a random access memory. In addition to storing a wπte address, an address rank of the random access memory may provide bits for debuggmg purposes In accordance with the present invention, bits representmg object information (e.g., object size) may be supported m the random access memory The wπte buffer is further descnbed m commonly-assigned U.S. Patent Application, Seπal No 09/008,394, entitled "WRITE-BUFFER FIFO ARCHITECTURE WITH RANDOM ACCESS SNOOPING CAPABILITY " In accordance with the present invention, object information is maintained concurrent with data optimization by the write buffer 16. Referring to Figure 5, a flow chart of a data optimization attributes save process in accordance with the present invention is shown. Beginning in step 52, it is determined if a data optimization operation has been performed. Data optimization operations (e.g., write mergmg or read merging) are detected by monitoring a MERGE signal (Figs. 1 and 2) of the system bus SB. Referring to Figure 2, the disclosed MERGE signal is an output of an OR logic gate 28 receiving the WR__MERGE signal and the RD_MERGE signal as inputs. It should be understood that other configurations of the MERGE signal are possible. If either the WR__MERGE signal or the RD__MERGE signal is asserted, then the MERGE signal is asserted to indicate detection of a data optimization operation. Returning to Figure 5, if a data optimization operation is not detected, then control remains at step 52. When a data optimization operation is detected in step 52, data optimization attributes associated with the data optimization operation are captured in step 54. Referring to Figure 3, a schematic illustration of the write buffer 16 storing exemplary data optimization attributes is shown. Data optimization attributes generally refer to information associated with a data optimization operation that may be used to reconstruct pre-optimization values. The disclosed exemplary data optimization attributes include the data resulting from a data optimization operation stored in a data field DATA, the address of the particular data stored in an address field ADDRESS, and the object size of the particular data stored in an object size flag field OSF. It is possible that object information other than object size may also be defined as data optimization attributes. In the illustrated embodiment, a data portion 40 of the write buffer 16 provides a column of data fields DATA; an address portion 42 of the write buffer 16 provides a column of address fields ADDRESS; and an object size flag portion 38 of the write buffer 16 provides a column of object size flag fields OSF. All ranks 30, 32, 34 and 36 of the write buffer 16 may include fields conesponding to the data portion 40, the address portion 42, and the object size flag portion 38. Referring to Figure 4, an exemplary logic table for an object size flag is shown. The disclosed object size flag provides two bits designated as A and B. The meaning of each bit combination AB is designated as C. The bit combination of '00' indicates a byte object size for corresponding data. The bit combination of '01 ' indicates a word object size for the conesponding data. The bit combination of '10' indicates a double word object size for the corresponding data. The bit combination of ' 11 ' is undefined. It should be understood that these bit combinations are illustrative and not exhaustive. Returning to Figure 1, the signal generating logic 22 generates an object information signal OBI for use in capturing the data optimization attributes. The signal generating logic 22 essentially combines the contents of the object size flag field OSF, the data field DATA, and the address field ADDRESS (Fig. 3) to form the object information signal OBI. In this way, the appropriate data optimization information for maintaining object information may be captured. As illustrated, the signal generating logic 22 may provide the object information signal OBI to the trace cache 12. The trace cache 12 may provide the object information signal OBI to the trace pins 20 of the debug port 18. The object information signal OBI is temporarily held by the trace pins 20. From the trace pins 20, the object information signal OBI is provided to a memory 24 of the host system H or a memory 24 of the bus monitoring device BMD. The signal generating logic 22 alternatively may provide the object information signal OBI externally through the trace pins 20 of the debug port 18. Returning to Figure 5, control next proceeds to step 56 where the data optimization attnbutes are stored. In the disclosed embodiment, the data optimization attnbutes may be stored in the trace cache 12, the memory 24 of the host system H, or the memory 24 of the bus momtonng device BMD. From step 56, the data optimization attπbutes save process is completed m step 58. In the disclosed embodiment, object information is maintained m a non-intrusive and transparent manner as detection of a data optimization operation is handled external to the target system T by the bus momtonng device BMD. The bus momtonng device BMD is capable of detectmg a data optimization operation by the wnte buffer 16 by momtonng the MERGE signal. When a data optimization operation occurs, the bus momtonng device BMD provides a CAPTURE signal to the microcontroller C to mdicate data optimization attπbutes associated with the detected data optimization operation should be captured. Responsive to the CAPTURE signal, the signal generating logic 22 generates an object information signal OBI and the trace cache control block 14 prepares the trace cache 12 to receive the object information signal OBI. Referring to Figure 6, a flow chart of a data optimization attnbutes debug process in accordance with the present mvention is shown. Beginning m step 62, the data optimization attributes are extracted from the object information signal OBI If the data optimization attπbutes are stored m the microcontroller C, then the attπbutes are provided to the host system H before extraction. In the disclosed embodiment, the host system H is trace capture equipment. Trace capture equipment H includes the memory 24 and data optimization decode logic 26. The data optimization decode logic 26 is specially configured to process wπte object values. Design and operation of general decode logic is understood in the art. As an alternative to trace capture equipment, the host system H may be other forms of software debuggmg equipment. Following step 62, the data optimization attπbutes are processed by the data optimization decode logic 26. Utilizing forward inferring or other suitable algoπthms known m the art, the decode logic 26 reconstructs the oπginal wnte object values from the data optimization attnbutes. The memory 24 and decode logic 26 may be provided by the host system H or by the bus momtonng device BMD (Fig. 1) The data optimization attnbutes debug process next terminates m step 66 Thus, a debuggmg environment in accordance with the present invention maintains object information concuπent with data optimization operations by a wnte buffer 16 of a target system T. Within the target system T, a system bus SB is coupled between a system memory M and a microcontroller C. A data optimization operation by the wπte buffer 16 is detected by momtonng of a MERGE signal of the system bus SB by a bus momtonng device BMD. When a data optimization operation is detected, data optimization attnbutes (e.g., object information, data, and address) associated with the data optimization operation are captured in the form of an object information signal OBI responsive to a CAPTURE signal from the bus momtonng device BMD. The data optimization attnbutes may be stored m either a trace cache 12 of the target system T, a memory 24 of external trace capture equipment H connected to the debug port 18, or a memory 24 of the bus momtonng device BMD. In providing the data optimization attπbutes external to the microcontroller C, the data optimization attnbutes may be temporaπly held by the trace pins 20. The data optimization attπbutes may be extracted from the object information signal OBI and processed by the external trace capture equipment H or the bus momtonng device BMD By processmg the data optimization attnbutes, pre- optimization wnte object values may be reconstructed It should be understood that the present mvention is applicable to any system m which data optimization operations may be performed. The foregomg disclosure and descnption of the invention are illustrative and explanatory thereof, and various changes in the components, circuit elements, signals, fields, buses, registers, variables, and connections, as well as in the details of the illustrated circuitry and construction and method of operation may be made without departing from the spirit of the mvention.

Claims: CLAIMS: We claim: 1. A method of mamtaimng object information concuπent with a data optimization operation by a wπte buffer of a target system, compnsmg the steps of. detecting a data optimization operation by the wnte buffer; capturing a plurality of data optimization attnbutes associated with the data optimization operation; and stormg the plurality of data optimization attπbutes. 2. The method of claim 1 , the target system mcludmg a system memory and a microcontroller, the step of detecting a data optimization operation compnsmg the step of: momtonng a merge signal of a system bus coupled between the system memory and the microcontroller. 3. The method of claim 2, further compnsmg the step of: generating the merge signal from a wnte merge signal and read merge signal of the wnte buffer. 4 The method of claim 1, a target system mcludmg a system memory and a microcontroller, the capturing step compnsmg the step of: generating an object information signal providing the plurality of data optimization attnbutes. 5. The method of claim 1 , the capturing step compnsmg the step of: providmg an object information flag m the wnte buffer 6 The method of claim 1 , the target system mcludmg a microcontroller havmg a debug port, the stormg step compnsmg the step of: holding of the plurality of data optimization attnbutes by a plurality of trace pins of the debug port. 7. The method of claim 1 , the target system mcludmg a microcontroller havmg a debug port, the debug port connecting the target system to external trace capture equipment, the stormg step compnsmg the step of: stormg the plurality of data optimization attnbutes m a memory of the external trace capture equipment. 8. The method of claim 1, the target system mcludmg a microcontroller havmg a system bus coupled to a bus momtonng device, the stormg step compnsmg the step of storing the plurality of data optimization attnbutes m a memory of the bus momtonng device. 9 A debuggmg environment for mamtaimng object information concurrent with a data optimization operation by a wnte buffer, compnsmg- a target system, compnsmg: a microcontroller, compnsmg. an execution unit; a wπte buffer coupled to the execution unit for performmg a data optimization operation; signal generatmg logic for generating an object information signal providmg a plurality of data optimization attnbutes associated with the data optimization operation; and a debug port for communicating with debug equipment; a system memory; and a system bus couplmg the microcontroller to the system memory, compnsmg: a merge signal Ime for detecting the data optimization operation; a bus momtonng device coupled to the merge signal Ime of the system bus; and a capture signal Ime coupled to the bus momtonng device for tπggenng capture of the plurality of data optimization attnbutes by the microcontroller. 10. The debugging environment of claim 9, further compnsmg debuggmg equipment connected to the debug port for stormg the plurality of data optimization attnbutes. 11 The debuggmg environment of claim 10, wherem the debuggmg equipment compπses trace capture equipment. 12 The debuggmg environment of claim 10, the debuggmg equipment compnsmg. decode logic for reconstructing pre-optimization wnte object values from the plurality of data optimization attnbutes. 13 The debuggmg environment of claim 9, the bus momtonng device compnsmg: decode logic for reconstructing pre-optimization wnte object values from the plurality of data optimization attnbutes. 14 The debuggmg environment of claim 9, the microcontroller further compnsmg: a trace cache coupled to the debug port for stormg the plurality of data optimization attπbutes. 15 The debuggmg environment of claim 9, wherem the wπte buffer is configured for performmg data optimization operations. 16. A method of debuggmg object information for a target system, the target system mcludmg a wnte buffer for performmg a data optimization operation, the target system generating an object information signal providmg a plurality of data optimization attπbutes associated with the data optimization operation, the method compnsmg the steps of. extracting the plurality of data optimization attπbutes from the object information signal; and processmg the plurality of data optimization attπbutes. 17. The method of claim 16, wherem the extracting step is performed by debuggmg equipment connected to the target system. 18. The method of claim 16, wherem the extractmg step is performed by a bus momtonng device coupled to a system bus of the target system. 19. The method of claim 16, wherem the plurality of data optimization attπbutes compπse object size information. 20. The method of claim 16, the processmg step compnsmg the step of: reconstructing pre-optimization wπte object values from the plurality of data optimization attπbutes. 21. A debuggmg environment for maintaining object information concurrent with a data optimization operation by a wnte buffer, compnsmg: a means of detecting a data optimization operation by a wnte buffer; a means of capturing a plurality of data optimization attπbutes associated with the data optimization operation; and a means for stormg the plurality of optimization attπbutes. 22. The debuggmg environment of claim 21 , further compnsmg: a means for extracting the plurality of data optimization attπbutes; and a means for processmg the plurality of data optimization attπbutes.

Inventors: GODFREY GARY M, MANN DANIEL P, GODFREY, GARY, M., MANN, DANIEL, P.
Applicants: ADVANCED MICRO DEVICES INC, ADVANCED MICRO DEVICES, INC.
Application year: 1999
Main classification: G06F11
IPC codes: G06F11, G06F15