FREQUENCY TO FREQUENCY DE-RANDOMISER CIRCUIT

Abstract: A frequency to frequency de-randomiser circuit having means for smoothing a current which comprises a diode filter configured so as to have a time constant which changes in response to changes in the current thus providing a rapidly responding, real time, fluctuation free signal which is optimised for measurement and display from a very low power circuit.

Description: Frequency to Frequency De-randomiser Circuit The present invention relates to an improved frequency to frequency de-randomiser circuit and in particular to a low power frequency to frequency de-randomiser circuit. Several types of technique are well known and commonly used in existing devices for de- randomising an input signal to provide a useable output signal. Examples of such techniques include integrating counts over a period ("store a display average") and diode pump circuits or variants. Details of the later are contained in 'Electronics for Nuclear Particle Analysis' - Herbst, p223 to 225 and Radiation Detection and Measurement' (2 nd Edition) - Knoll, p601 & 602. However, each of the known techniques has associated problems. Modification of the display driver software code to achieve a fast responding, fast settling, accurate and steady display could have been used in the circuit according to the invention. However, the circuit according to the invention is designed for power efficiency and as such the processors operate at very low clock speeds to conserve power and the complexity of the software code has had to be minimised. Thus, if the display driver software code had been used, the processors would have to operate faster and the power consumption of the device would be higher. The problem with 'store and display average' arrangements is that they are unable to function in real-time. To achieve a fast responding, fast settling, accurate and steady display, requires the use of a microprocessor running at high clock speeds. This could be fast enough to appear to be working in real time but would have high power consumption due to the processor speed. The circuit according to the invention is designed for power efficiency and as such the microprocessors operate at low speeds to conserve power and the software code is minimised. Hence, the power consumption implications associated with a microprocessor operating at high speed is unacceptable. Finally, diode pump circuits work well at high frequencies. However, at low frequencies the time-constant required within the circuitry to give an acceptable or steady reading, causes the circuit to have a slow response. This is unacceptable in a device which needs to perform well at both high and low frequencies. It is an aim of the present invention to provide a frequency- to- frequency de-randomiser circuit with reduced power consumption which can perform well at both high and low frequencies. Accordingly the present invention provides a frequency to frequency de-randomiser circuit comprising means for converting the frequency of an input signal into an output current, means for smoothing the output current and means for converting the smoothed output current into an output signal having a frequency suitable for digital processing characterised in that the means for smoothing the output current comprises a diode filter configured so as to have a time constant which changes in response to changes in the output current. The frequency- to -frequency de-randomiser circuit according to the invention is based on the same concept as the diode pump described above. However the invention utilises a logarithmic filter circuit to address the above frequency problem which is fed from a standard diode transistor pump which performs the frequency to current conversion required by the circuit. Input to the frequency- to- frequency de-randomiser circuit is in uhe form of a randomly varying ^ulsed signal. This input is then fed into a linear frequency to current converter such as a diode transistor pump. Alternatively a diode pump or a transistor pump could be used however a diode transistor pump produces both linearity in response and simplicity in the circuit. The varying current output is in turn fed into a diode filter to smooth the current and obtain a time averaged, real time smoothed output. The diode filter can comprise any number of stages dependent on the filtering required. A three stage filter comprises three resistors in parallel with three diodes which each have an associated filter capacitor ( a fourth filter capacitor can also be added to increase filtering if required) , however as little as one diode acting as the resistive element and an associated filter capacitor can be used. The more stages used, the more filtering is performed however adding more stages provides a diminishing level of filtering. The inventor has found that the optimum balance between level of filtering and number of components is reached with three stages of filtering. Diode theory shows that the effective slope resistance of a forward biased diode is proportional to the current flowing through it, such that for example at lma the resistance is 25Ω and at lOma it is 2.5Ω and so on. As such, the use of diodes in the resistive elements of this filter serves the purpose of providing a moving time constant with respect to count rate (or current) producing longer time constants at low count rates (and therefore low currents) and shorter time constants at higher count rates (and therefore high currents) as the current through the diodes increases, thus allowing the device to perform well at both high and low counting rates, keeping the response speeds high at high count rates and the fluctuations due to randomness at low count rates to a minimum. At very low count rates the resistors will dominate providing a minimum response time. The output from the filter can then be converted into an output signal at a frequency suitable for measurement and display. Such conversion can be accomplished by any known means, however, advantageously it can be accomplished by an operational amplifier feeding into a voltage controlled oscillator which produces the output signal and a second means for converting the frequency of an input signal into an output current which converts the output signal into a balancing current, the balancing current then being used to balance the input into the operational amplifier. The use of an operational amplifier / voltage controlled oscillator arrangement maintains the output of the filter at virtual earth (or other nominal voltage as required) . This prevents a build up of charge at the output of the filter, an effect which would slow the response of the circuit. The second frequency to current converter can be of any form as with the first frequency to current converter, however advantageously it can be in the form of a diode transistor pump. This diode transistor pump acts as a linear frequency to current converter. This circuit provides a rapidly responding, real time, fluctuation free signal which is optimised for measurement and display from a very low power circuit. The frequency- to -frequency de-randomiser circuit according to this invention can be used in any application requiring de- randomisation of an input however the circuit according to the present invention has been optimised for use in a radiation monitor. In particular it has been optimised for use in a portable radiation monitor which requires to meet the BASEEFA criteria and which needs no on/off switch, the power efficiency of the circuits resulting in the batteries only requiring replacement annually during planned preventative maintenance and calibration activities, as required under the Ionising Radiation Regulations, 1985. In a radiation monitor, this circuit performs the function of taking randomly occurring α/β pulses from two discriminators and converting this to a relatively fluctuation free square wave output stream suitable for input into a micro -controller system to provide a display. Two identical circuits are employed in the monitor, one each for the α and β signals. Embodiments of the invention will now be described, by way of example, with reference to the accompanying drawing, wherein Fig. 1 shows a circuit diagram of the frequency- to-frequency de- randomiser circuit. Referring to fig. 1, the frequency- to-frequency de-randomiser circuit comprises a first and second diode transistor pump 9, 11 a 3 stage filter 10, an operational amplifier 12 with associated control capacitor 30 and a voltage controlled oscillator 13. The diode transistor pumps 9, 10 consist of a capacitor 14, 29, a diode 15, 28 and a transistor 16, 27. The 3 stage filter 10 consists of 3 resistors 17,18 and 19 arranged in parallel with 3 diodes 24, 25 and 26 with 4 associated filter capacitors 20, 21, 22 and 23. The input signal is fed into the first diode transistor pump 9 which functions as a linear frequency to current converter and converts the randomly occurring input signal into a varying current output, the output is then fed into the 3 stage filter 10 which serves the requirement of providing a longer time constant at low count rates and a smaller time constant at high count rates as the current through the diode increases. The output from the filter 10 is then fed into an operational amplifier 12 which is used in conjunction with a voltage controlled oscillator 13 in order to convert the output of the filter into a frequency ideally suited to measurement by the detector. In order to balance the output current from the filter 10 the output from the voltage controlled oscillator 13 is fed, via the diode transistor pump 11, back into the operational amplifier 12 thus forming a feedback loop equalising the inputs of the operational amplifier 12. The two diode transistor pumps 9,10 can be set such that the ratio of input to output pulses is 1 to 10. As the VCO and the second diode transistor pump are in the feedback loop of the operational amplifier then for every input pulse there must be 10 output pulses in order to balance the circuit. This ratio can of course be set to any value as required by specific applications.

Claims: CLAIMS 1. A frequency to frequency de-randomiser circuit comprising means for converting the frequency of an input signal into an output current, means for smoothing the output current and means for converting the smoothed output current into an output signal having a frequency suitable for digital processing characterised in that the means for smoothing the output current comprises a diode filter configured so as to have a time constant which changes in response to changes in the output current. 2. A frequency to frequency de-randomiser circuit according to claim 1 characterised in that the means for converting the frequency of an input signal into an output current comprises a diode transistor pump. 3. A frequency to frequency de-randomiser circuit according to claim 1 or 2 characterised in that the diode filter comprises at least one diode and at least one associated filter capacitor. 4. A frequency to frequency de-randomiser circuit according to claims 1 or 2 characterised in that the diode filter comprises three resistors connected in parallel with three diodes, each diode having an associated filter capacitor. 5. A frequency to frequency de-randomiser circuit according to any of the preceding claims wherein the means for converting the smoothed output current into an output signal comprises an operational amplifier feeding into a voltage controlled oscillator which produces the output signal and a second means for converting the frequency of an input signal into an output current wherein the second means for converting the frequency of an input signal into an output current converts the output signal into a balancing current, the balancing current then being used to balance the input into the operational amplifier. 6. A radiation monitor comprising a frequency to frequency de- randomiser circuit according to any of the preceding claims. 7. A frequency to frequency de-randomiser circuit substantially as hereinbefore described with reference to figure 1.

Inventors: GARDNER JOHN, GARDNER, JOHN
Applicants: GARDNER JOHN, SECR DEFENCE, GARDNER, JOHN, THE SECRETARY OF STATE FOR DEFENCE
Application year: 1999
Main classification: H03B19
IPC codes: G01R23, G01T1, H03K5, H03K7