A digital-to-analog converter

Abstract: A digital-to-analog converter circuit (D/A) for converting a two-level, pulse-width-modulated (PWM), digital input signal (V in ) into a corresponding analog output signal (V out ) is described. The converter comprises a control circuit (12) which receives the digital signal (V in ) input to the converter as an input and supplies, at a first output (13a), an intermediate signal (V d ) produced by delaying the moments at which the input signal (V in ) switches, a circuit (14), driven by the intermediate signal (V d ), for generating a ramp signal (V r ), and a sample-and-hold circuit (16) which receives the ramp signal (V r ) at an input (38). The sample-and-hold circuit (16), which is controlled by the control circuit (12), acquires the amplitude reached by the ramp signal (V r ) each time the digital input signal (V in ) switches from a first level (l 1 ) to a second level (l 2 ). The signal (V out ) present at the output of the sample-and-hold circuit (16) thus constitutes an analog signal corresponding to the digital input signal (V in ).

Description: The present invention relates to a digital-to-analog converter circuit (D/A) according to the preamble to Claim 1 and, in particular, relates to a D/A converter for driving a two- quadrant current generator with a floating load. It is known in the art for D/A converters for converting a numerical quantity processed by a microprocessor, to be implemented simply with the use of a digital-to-analog converter circuit of known type, for example, a potentiometric or weighted-currents converter circuit, which is connected to the microprocessor externally if no integrated internal D/A converter is available. It is also known to produce D/A converters operating on the basis of a pulse-width-modulated signal (referred to below for simplicity by the usual name of PWM signal) which is supplied by a microprocessor and the duty cycle of which is proportional to the numerical quantity to be converted. These converters (commonly known as indirect converters) generally comprise a low-pass filter for extracting the mean value of the PWM signal and a circuit arranged for varying the amplitude of the signal thus obtained in a predefined manner in order to achieve the desired dynamic range at the output. The solutions currently used require expensive and complex components. To prevent these problems, the subject of the invention is a D/A converter the main characteristics of which are defined in the appended main claim. Further characteristics and advantages of the invention will become clear from the following detailed description given purely by way of non-limiting example, with reference to the appended drawings, in which: Figure 1 is a block diagram of the digital-to-analog converter circuit according to the invention, Figure 2 is a circuit diagram of a portion of the converter circuit identified by the frame II in Figure 1, and Figure 3 is a set of graphs showing the curves of the input and output signals of the circuit blocks illustrated in Figure 1 as functions of time t. In Figure 1, a microprocessor, indicated 10, is arranged for processing a numerical variable and for generating a pulse-width-modulated (PWM) signal V in the duty-cycle of which is proportional to the value of the numerical variable. The signal V in output by the microprocessor is supplied as an input to a D/A converter circuit comprising a control circuit 12 which generates an intermediate signal V d , which is also a PWM signal, at a first output 13a, on the basis of the signal V in , a circuit 14 for generating a ramp signal V r , connected to the first output 13a of the control circuit 12, and a sample-and-hold (S/H) circuit 16 to the input of which the ramp signal V r is transferred. The control circuit 12 also generates, at a second output 13b, a control signal V s , sent to the control input 18 of the S/H circuit 16. An analog signal V out corresponding to the input signal V in is output by the S/H circuit 16 at the output of the converter as a whole. This analog signal V out can be used, for example, as described in the preferred embodiment, for driving a current-generator circuit 20 of known type, to which a floating load 22 is connected. There is provision for possible feedback control of the converter by the connection of the circuit 20 to an input of the microprocessor 10 so as to cancel out any errors which may arise and be amplified during the operation of the cascaded circuits 12, 14 and 16. The operation of the circuit is now analyzed in detail below with reference to Figures 2 and 3. The first graph of Figure 3 shows a time portion of the input signal V in comprising two complete periods of equal duration, indicated T 1 and T 2 . The signal V in is a digital signal with two levels indicated as a first level l 1 and a second level l 2 , respectively, corresponding, for example, to voltage values of 0 volts and 5 volts, respectively. The numerical data processed by the microprocessor 10 is now associated with the duty cycle of the signal V in and is represented by the time intervals T a and T b in which it is at the first level l 1 , relative to the total duration of the periods T 1 and T 2 . The control circuit 12 receives the signal V in as an input and generates the corresponding intermediate signal V d at its first output 13a, as indicated in the second graph of Figure 3. The signal V d is obtained by delaying the moments at which the input signal V in switches, particularly by introducing a predetermined fixed delay T d , and by delaying the switching of the signal from the first level l 1 to the second level l 2 by a further time interval, indicated T h . These measures are adopted in order to achieve correct sampling of the ramp signal V r , as will be described further below. The ramp-signal generator circuit 14 is illustrated in detail in Figure 2 and comprises an integrator circuit 30 of known type and an electronic switch 32 connected between the output 34 of the integrator and a ground terminal GND. In this embodiment, the switch 32 is formed, for example, by an npn-type bipolar transistor. The control input of the switch 32 (the base of the transistor) receives the signal V d via a resistor R 1 . When the signal V d is at its first level l 1 , the corresponding voltage value, for example, 0 volts, is not sufficient to forward bias the base-emitter junction of the transistor 32 and this transistor operates in the cut-off condition, behaving substantially as an open switch and disconnecting the output 34 of the integrator from the ground terminal GND. The voltage signal V r provided by the integrator and having a ramp-type variable amplitude (in particular, in the embodiment described, an increasing amplitude) therefore occurs at the output terminal 36 of the circuit 14. When the input signal switches to its second level l 2 , the corresponding voltage value, for example 5 volts, is sufficient to forward bias the base-emitter junction of the transistor 32 and this transistor operates in a saturation condition, behaving substantially as a closed switch and connecting the output 34 of the integrator to the ground terminal GND. The output terminal 36 of the circuit 14 is thus forced to the constant voltage of the ground terminal. The time curve of the signal V r corresponding to the curves of the signals V in and V d is given in the fourth graph of Figure 3. The duty cycle of the signal V in regulates the maximum voltage reached by the ramp, which in any case cannot exceed the value of the saturation voltage of the operational amplifier OA of the integrator circuit 30. The signal V r appears at the input 38 of the S/H circuit 16 and is acquired at predefined short time intervals by the closure of a switch 40. These intervals, hereinafter referred to as acquisition intervals of duration T d , are determined by the signal V s (represented in the third graph of Figure 3) emitted by the control circuit 12 at the moments when the input signal V in switches from its first level l 1 to its second level l 2 . Since the signal V r is generated on the basis of the intermediate signal V d , consecutive time intervals in which the signal V r has a ramp-type variable amplitude and in which, on the other hand, it is at the voltage of the ground terminal (GND) occur with a delay relative to the corresponding time intervals in which the signal V in input to the converter is at its first level l 1 and at its second level l 2 , respectively. In the embodiment described, this delay is equal to the acquisition interval T d required by the sample-and-hold circuit 16. During the acquisition interval, the signal V r thus still has a ramp-type variable amplitude and, in particular, a value close to the maximum value which can be reached and beyond which the voltage is brought to the value of the ground potential by the connection of the output 36 of the ramp generator circuit 14 to the ground terminal (GND). The S/H circuit 16, which is implemented in accordance with known teachings, acquires the voltage reached by the signal V r and keeps this value at its output until the subsequent acquisition. To permit correct acquisition, the signal V r must be kept relatively stable even for a short period after the theoretical acquisition interval. This is again provided for by the control circuit 12 by delaying the switching of the signal V d from the first level l 1 to the second level l 2 for a further holding time interval T h after the acquisition interval so as to delay the instantaneous forcing of the amplitude of the signal V r to the value of the ground potential, preventing problems and incorrect operation due to non-controllable opening times of the switch 40. The voltage signal V out output by the S/H circuit constitutes the desired analog signal corresponding to the digital input signal V in and is represented in the last graph of Figure 3. This signal can be programmed by means of the numerical variable stored in the microprocessor 10. A current signal can be generated on the basis of the analog voltage signal V out by means of the current generator circuit 20 which is also known from the literature. The current I L supplied to the load 22 is given by the following equation: I L = V out -V rif R 2 and is independent of the impedance of the load but depends solely upon the analog voltage signal corresponding to the digital input signal V in (and hence to the value of the numerical variable), and upon a predetermined reference voltage signal V rif present at the node 42 of the circuit 20. The current I L can be made to adopt both positive and negative values by suitable selection of the signal V rif at a voltage value between the maximum and minimum values which can be reached by the signal V out and by regulating the duty cycle of the signal V in (that is, by altering the numerical variable which controls it). By feeding the signals V out and V rif back to an analog-to-digital converter circuit which is not shown because it is integrated in the microprocessor 10, it is also possible to calculate the value of the current I L numerically and to correct the duty cycle of the signal V in in order to modify it.

Claims: A digital-to-analog converter circuit (D/A) for converting a pulse-width modulated (PWM), digital input signal (V in ) with two. stages or levels (l 1 , l 2 ) into a corresponding analog output signal (V out ), characterized in that it comprises: a control circuit (12) having an input for receiving the digital input signal (V in ) and a first output (13a) by means of which the control circuit provides an intermediate signal (V d ) obtained by delaying the moments at which the input signal (V in ) switches, means (14) for generating a ramp signal (V r ), connected to the first output (13a) of the control circuit (12) and capable of being driven by the intermediate signal (V d ) in a manner such as to generate a signal (V r ) having a ramp-type variable amplitude when the intermediate signal (V d ) is at a first level (l 1 ) and a substantially constant predetermined amplitude when the intermediate signal (V d ) is at a second level (l 2 ), and a sample-and-hold (S/H) circuit (16) having an input (38) connected to the output (36) of the means (14) for generating the ramp signal (V r ) and a control input (18) connected to a second output (13b) of the control circuit (12), the sample-and-hold circuit (16) being driven by the control circuit (12) in a manner such as to acquire the amplitude reached by the signal (V r ) emitted by the generator means (14) each time the digital input signal (V in ) switches from the first level (l 1 ) to the second level (l 2 ), the signal at the output of the sample-and-hold circuit (16) constituting an analog signal (V out ) corresponding to the digital input signal (V in ). A circuit according to Claim 1, characterized in that the intermediate signal (V d ) is obtained by delaying the moments at which the input signal (V in ) switches by a predetermined time at least equal to the acquisition time (T d ) required by the sample-and-hold circuit (16). A circuit according to Claim 1 or Claim 2, characterized in that the means (14) for generating the ramp signal (V r ) comprise: an integrator circuit (30) arranged for supplying an output voltage (V r ) with an amplitude variable in accordance with a linear ramp, and an electronic switch (32) connected between the output (34) of the integrator circuit (30) and a conductor which is kept at a reference potential (GND), the intermediate digital signal (V d ) being applied to the control input of the electronic switch in operation. A circuit according to Claim 3, characterized in that the electronic switch (32) is connected between the output (34) of the integrator circuit (30) and a ground conductor (GND). A circuit according to any one of the preceding claims, characterized in that a current generator (20) with a floating load (22) is connected to the output of the sample-and-hold circuit (16).

Inventors: CARBONARO PIERO, DIACO MARCO, CARBONARO, PIERO, DIACO, MARCO
Applicants: IXFIN MAGNETI MARELLI SISTEMI, IXFIN MAGNETI MARELLI SISTEMI ELETTRONICI S.P.A.
Application year: 1999
Main classification: H03M1
IPC codes: H03M1, H03K9