Semiconductor device with conductive lines thereon and barriers against parasitic current

Abstract: A semiconductor substrate (14) is patterned to have alternating high and low conductivity areas (110,112). Metal lines (104,108) on dielectric layer (16) pass transversely over the conductive areas (110,112). The low conductivity areas (112) interrupt parasitic inductive current induced in the substrate (14).

Description: This invention relates to parasitic current barriers, which have been disclosed in the specification of U. S. Patent No. 5,717,243. Integrated circuits have one or more levels of metal formed on dielectric material that covers a semiconductor substrate. The levels of metal are separated by dielectric material. The substrate that holds the integrated circuits is made of semiconductor material. The metal levels are patterned into lines that can be characterized as either signal lines (which carry a signal), return lines (which are signal lines carrying current in the opposite direction to another signal line), or lines attached to ground (ground lines). Parasitic currents can flow in the substrate due either to capacitive coupling or to inductive coupling to these metal lines. Consider Figures 1(a) and 1(b) where one or more first metal line(s) 104 carries a signal and one or more ground lines 108 that run parallel to signal line(s) 104. The lines 104, 108 are supported on dielectric layer 16 that covers the semiconductor substrate 14. The substrate 14 is doped at around 10 to 20 ohm-cm. With this resistivity, the primary power loss is due to resistive current flow through the substrate that is capacitively generated from the signal line. The resistive current flow in the substrate caused by the signal line can be redirected by the presence of a nearby ground line which then tends to become the primary destination of this current. Without doing anything special, this will reduce the resistance somewhat but will not greatly reduce the resistive losses. This particular loss factor can be nearly eliminated by pursuing one of two strategies: The first strategy is to make the path so highly resistive that current cannot flow at all. The second strategy, pursued here, is to make the path so conductive that the resistive loss is very small even though the current is free to flow. The problem introduced by making the path conductive is that another parasitic current is formed. In many instances, this other parasitic current is worse than the eliminated parasitic current. This other parasitic current is an inductively induced image current L of the signal line in the conductive part of the substrate. This image current L is opposite to the current in the signal line and parallel in direction. The path of the capacitively generated current in the substrate from the signal line to the ground line is perpendicular to the signal line as shown by arrow C; the inductively induced current in the substrate is parallel to the signal line as shown by arrow L. The substrate resistive loss due to inductive coupling to a heavily doped layer can be calculated. In this calculation, the substrate is doped with a buried layer with a resistance of 8.1 Ohms/square. The signal line 104 is above the dopant 20(a), as shown in Figure 2(a), and is 2.5um thick, 20um wide, and 1,000um long. The power loss in the substrate, Ps, is P s = V s 2 /R s where R s is the resistance in the conductive path through the substrate and V s is the voltage difference in the substrate below the metal line caused by mutual inductive coupling from the signal line above. V s is related to the current in the metal line (I m ) by the formula V s = MωI µ where M is the mutual inductance between the signal line 104 and the conductive path in the substrate 14, and w is the frequency in radians/second. Substituting this into the formula for P s gives P s = (Mwl m ) 2 / P σ The active doped region of the substrate is assumed to be 30mms wide and 1000µms long. From analytic inductance equations, M= 8.2e-10 Henrys. R s , the resistance in the substrate below the signal line, is calculated from the sheet resistance and the geometry as R s = (8.1 Ohms)(1000µm)/(30µm) = 270 Ohms Choosing a frequency of 5GHz and substituting these values into Equation (3), we get P s = 2.50I m 2 where mks units are assumed. For comparison, the resistive loss in the metal is P m = R m I m 2 = 0.75I m 2 The above analysis shows that in the prior art structure the resistive loss through the substrate is roughly comparable to but greater than the loss in the signal line 104 (in this case, more that 3 times greater). It would be desirable to reduce such losses. The preamble of claim 1 is based on US 5717243. The prior art also comprises WO 97/45873. The present invention is defined in claim 1. The invention also includes a semiconductor device. including a structure for conducting current and reducing parasitic effects of currents generated in the semiconductor substrate comprising a substrate of semiconductor material, two or more elongated conductors over the substrate, each conductor parallel to the other(s) for at least a portion of their respective lengths and capable of capacitively and inductively inducing current in the substrate, means for intercepting and conducting capacitively generated current, located proximate to the elongated conductors and comprising a plurality of sequential regions of alternating conductivity, boundaries between adjacent said regions oriented transverse with respect to the elongated conductors, in which the means for intercepting and conducting capacitively generated current comprises semiconductor material and the regions of alternating conductivity comprise alternate regions of high and low doping in the semiconductor material. Preferably a solution to the problem of parasitic current is as follows: let the perpendicular current in the substrate flow easily and prevent the parallel flow. This result is accomplished by directionally patterning the substrate doping to achieve this result. In particular, the substrate is patterned to have sequential strips of alternating relative high and low conductivity disposed beneath the signal and ground lines such that the boundaries between adjacent strips are in the direction transverse to the signal and ground lines. The highly conductive regions allow the capacitively generated current to flow in the transverse direction. The low conductive regions interrupt the parallel flow of inductively induced current. Such a structure allows easy flow of capacitively generated current to ground and thereby improves substrate loss and provides a shielding effect that reduces coupling to other devices through the substrate-without allowing the parasitic image current to flow in the substrate parallel to the metal lines. Alternatively, other conductive layers can be patterned to replace the dopant. Instead of being in the semiconductor, the conductive layers are on or above the semiconductor layer. Each conductive layer is more conductive than the semiconductor substrate. Additionally, multiple patterned conductive layers can be used to provide a more complete shield from the capacitively generated current. One embodiment provides for isolating one current carrying line from capacitively inducing current in one or more other current carrying lines. The invention will now be described, by way of example, with reference to the accompanying drawings in which: Figure 1(a) is a cross-sectional view of prior art. Figure 1(b) is a top view of Figure 1(a). Figure 2(a) is a cross-sectional view of an alternative embodiment of the present invention. Figure 2(b) is a top view of Figure 2(a). Figure 3(a) is a cross-sectional view of an alternative embodiment of Figure 2(a). Figure 3(b) is a top view of Figure 3(a). Figure 4(a) is a cross-sectional view of an alternative embodiment of Figure 2(a). Figure 4(b) is a top view of Figure 4(a). Figure 5(a) is a partial perspective view of a structure capacitively isolating a current carrying line; Figures 5(b) and 5(c) are end and side views of the structure of Figure 5(a). Figures 2(a) and 2(b) illustrate one embodiment of the present invention. Both show a first metal line 104 that carries a signal and a ground line 108. The metal lines 104, 108 are patterned over the dielectric layer 16 and the dielectric layer 16 is over the substrate 14. Dopant 20(a) patterns the substrate 14 into a plurality of sequential, alternating highly conductive areas 110 and low conductivity or resistive areas 112. Each area 110 is beneath a portion of the first metal line 104 and a portion of the second metal line 108. Optionally, conducting contacts 66 connect each of the highly conducting areas to one or more of the lines. A gap or low conductivity region 112 separates each area 110 from other areas 110 as shown in Figure 2(b). Each region 112 keeps the resistance high for current crossing it. Each region 112 can be an undoped portion of the substrate 14 or a trench. The trench would be filled with resistive or dielectric material. Those skilled in the art understand how to mask the substrate 14 to form and fill trenches or form alternating regions of doped and undoped areas. The path of the capacitively generated current in the substrate 14 from below the first metal line 104 to the second metal line 108 is shown by arrow C. The inductively induced current in the substrate 14 is parallel to the first metal line 104. This is indicated by the arrow L. The current path C is unobstructed whereas the current path L is blocked by the undoped regions 112. The structure illustrated in Figures 2(a) and 2(b) allows the perpendicular current to flow easily, yet prevents the parallel flow. Another way to say this is that this structure allows easy flow to the ground line without allowing the image current to flow in the substrate 14. The substrate loss provided by the easy path from below the first metal line 104 to second metal line 108 illustrated in Figures 2(a) and 2(b) is not necessarily the most important benefit of doping the substrate 14. The coupling to other devices (not shown) through the substrate 14 is greatly reduced by the shielding effect of this structure. The patterning of dopant 20(a) allows us to do this by preventing the image current that would otherwise become important at these doping levels. In Figures 3(a) and (b) there are three parallel metal lines: two parallel return (or ground) metal lines 108 and a center signal metal line 104. The lines are on the dielectric layer 16 and the dielectric layer 16 is over the substrate 14. The two return lines 108 parallel and surround the first metal line 104. Dopant 20(a) patterns substrate 14 into a plurality of conductive and nonconductive areas designated 110, 112, respectively, as shown in Figure 3(b). Boundaries between adjacent areas 110, 112 run transverse to a portion of the signal line 104 and a portion of both return lines 108. The low conductive regions 112 separate each area 110 from other areas 110. A series of highly conductive regions 110, combined with contacts 66, connect the two return lines 108 in a geometry that looks like the signal line 104 is over a railroad track as shown in Figure 3(b). ' Trenches filled with resistive or dielectric material may be substituted for the nonconductive regions 112. Figures 4(a) and 4(b) illustrate a variation of Figures 2(a) and 2(b) wherein an additional patterned conductive layer 20(b) is utilized. The conductive portions 210 of the additional layer 20(b) are disposed to cover most of or overlap the low conductivity regions 112 of the original patterned layer. The idea behind this is that capacitively generated charge will be intercepted by either of the two patterned layers 20(a), 20(b) before it can get to the substrate. The main advantage of using multiple patterned layers is that coupling to other devices through the substrate is greatly reduced. The example of multiple layers in Figures 4(a) and 4(b) shows one layer in the substrate 14 and another in the insulating layer 16 between the lines and the substrate. Those skilled in the art will understand that single or multiple layers for intercepting the induced current may also be placed in layers above the lines so that the lines are between the layers and the substrate. Of course, a device may have the intercepting layers on both sides, i.e., above the lines and below the lines. In addition, a single patterned layer is not necessarily limited to the substrate, but may also be on or above the substrate. Examples of layers that could be patterned for this purpose are: doped polysilicon, the doping in the polysilicon, silicide layers, and other metal layers. In other embodiments either the silicon or the polysilicon is doped in alternate sequential regions of n-type and p-type doping. A further embodiment uses a heavily doped layer in the semiconductor that is masked and interrupted with periodic trenches filled with insulating material to form alternate sequential regions of high and low conductivity. The intercepting layer is on one side of the conductors, namely on the side between the conductors and the substrate. However, there may be multiple intercepting layers, including one or more layers on both sides of the conductors. The intercepting layers could also be made from anisotropically conductive material, i.e., material that conducts in a first direction but not in a second direction transverse to the first direction. Examples of nisotropically conductive materials include an insulating medium with metal fibers embedded in the medium and aligned in the same direction. Another example is a medium comprising long molecules aligned in one direction that preferentially conduct along their length but not from one molecule to another. A third example is graphite which bonds in sheets and conducts current preferentially within sheets but not between sheets. A fourth example is high-temperature superconductors which also display anisotropic conductivity. In each of the above examples, the anisotropically conductive material should be aligned to preferentially conduct current in the direction transverse to the metal lines rather than parallel to the metal lines. A more general application of the invention is shown in Figures 5a, 5b and 5c. There the invention provides a shielded line 204 that has reduced capacitive coupling from lines 202 and 206. The current carrying lines, 202, 204, and 206 are arranged in parallel alignment with and spaced from each other. The lines are supported in an insulating medium such as silicon dioxide or plastic (not shown). Between lines 202 and 204 there is a set of transverse strips 210, 211, 212 and between pairs 204 and 206 there is a corresponding set of transverse strips 220, 221 , 222 that carry current in a direction transverse to the current carried in lines 202, 204 and 206. The sets of transverse strips 210-212 and 220-222 are held in the insulating material (not shown) and are spaced from each of the current carrying lines. The structure 200 isolates line 204 capacitively from lines 202 and 206. The transverse strips 210-212 intercept capacitive current induced by signal lines 202 and 204. Likewise, transverse strips 220-222 intercept capacitive currents induced by currents running in lines 204 and 206. No inductively induced current will be introduced in the shield lines 210-212 nor lines 220-222 by lines 202, 204 or 206 because the shield lines carry current only in a direction transverse to the current carried in signal lines 202, 204 and 206. Additional staggered layers can be added to provide a more complete capacitive shield as shown as 210 and 212 in Figure 4(b). In an embodiment a substrate 14 is patterned to have high and low conductive areas 110, 112, respectively. Metal lines 104, 108 in dielectric layer 16 pass transversely over the areas 110, 112. The areas 112 interrupt parasitic inductive current induced in the substrate 14.

Claims: A semiconductor device including a structure for conducting current and reducing parasitic effects of currents generated in a semiconductor substrate (14), said device comprising: said substrate (14) of semiconductor material; two or more conductors (104, 108) over the substrate, each conductor being parallel to the other(s) for at least a portion of their respective lengths and capable of capacitively and inductively inducing current in the substrate (14), at least one layer proximate to the conductors (104, 108) said layer comprising a plurality of sequential and coplanar regions of alternating high conductivity (110) and low conductivity (112); wherein said conductors (104, 108) are elongated, one (104) of said conductors (104, 108) being a signal line and one (108) being a ground line, and wherein boundaries between adjacent said regions are oriented transversely with respect to the conductors (104, 108) so that said layer intercepts and conducts current capacitively generated in the substrate (14) by the conductors (104, 108) and blocks current inductively induced in the substrate by the conductors (104, 108), characterized in that each of said regions (110, 112) of high and low conductivity extends beneath said signal line (104) and said ground line (108). A device as claimed in claim 1, further comprising a second layer having sequential regions of alternating relatively high (210-212) and low conductivity for conducting capacitiveiy generated current and for blocking inductively induced current, said high conductivity regions of the first ayer being aligned with the low conductivity regions of the second layer and said low conductivity regions of the first layer are aligned with the high conductivity regions of the second layer. A device as claimed in anyone of claims 1 or 2 wherein the at least one layer (210-212, 220-222) comprises semiconductor material and the regions of alternating high and low conductivity comprise alternate regions of high and low doping (resp. 110, 112) in the semiconductor material, or the at least one layer comprises polysilicon and the regions of alternating high and low conductivity comprise alternate regions of high and low doping in the polysilicon. A device as claimed in claim 1 or 2 wherein the regions of alternating high and low conductivity comprise spaced apart strips of polysilicon and gaps between said strips, or in which the regions of alternating high and low conductivity comprise spaced apart strips of silicide and gaps between said strips, or the regions of alternating high and low conductivity comprise spaced apart strips of metal and gaps between said strips. A device as claimed in claim 1 or 2 wherein the regions of alternating high and low conductivity comprise alternate regions of highly doped silicon and isolation trenches, or the regions of alternating high and low conductivity comprise alternate regions of highly doped silicon of alternating n-type and p-type doping. A device as claimed in one of the preceding claims comprising two layers each disposed on opposite sides of the conductors wherein one layer is disposed on one side of the conductors between the conductors and the substrate and the other intercepting layer is disposed on the other side of the conductors and over the conductors. A device as claimed in any one of claims 1 to 6 wherein the layer comprises a layer of insulating material with a patterned metal comprising openings in the metal layer transverse to the elongated conductors for establishing areas of high resistivity in said openings, or the layer comprises an anisotropically conductive material that conducts current in the direction transverse to the conductors and is highly resistive to current parallel to the conductors, and the anisotropically conductive material is selected from the group consisting of: (1) conductive fibers aligned perpendicular to the direction of the conductors and encased in insulating material, (2) long molecules aligned perpendicular to the direction of the conductors that conduct current along the molecules but not between the molecules, (3) graphite aligned to preferentially conduct current in the direction transverse to the conductors, and (4) anisotropic superconducting material aligned to preferentially conduct current in the direction transverse to the conductors.

Inventors: LOWTHER REX, YOUNG WILLIAM, LOWTHER, REX, YOUNG, WILLIAM
Applicants: HARRIS CORP, HARRIS CORPORATION
Application year: 1999
Main classification: H01L23
IPC codes: H01L23, H01L21