LOW POWER DRIVERS FOR LIQUID CRYSTAL DISPLAY TECHNOLOGIES

Abstract: A drive circuit can be used to drive a matrix display device, such as a liquid crystal display, that includes a plurality of pixels (16) disposed in rows (12) and columns (14). A first switch (328) has a current path coupled between a high voltage node (e.g., Vs) and a group of pixels (16). As an example, the group of pixels (16) can be a now (12) or a column (14). A second switch (326) has a current path coupled between a low voltage node (e.g., ground) the group of pixels (16). A third switch (322) has a current path coupled between an inductive storage element (34) and the group of pixels. The inductive storage element (34) is coupled to an intermediate voltage node (e.g., Vs/2) with a voltage between the voltage at the high voltage node and the voltage at the low voltage node.

Description: Low Power Drivers for Liquid Crystal Display Technologies CROSS-REFERENCE TO RELATED APPLICATIONS The following U S patents and/or commonly assigned patent applications are hereby incorporated herein by reference Patent or Attorney Serial No Filing Date Issue Date Docket No 08/767,193 12/16/96 Rose-8001 09/111,532 07/08/98 Rose-8004 FIELD OF THE INVENTION This invention relates generally to drive circuits and specifically to low power drivers for hquid crystal display technologies BACKGROUND OF THE INVENTION The demand for Liquid Crvstal Displays (LCD) continues to exceed supply LCD's are implemented as screens on almost all types of digital devices, including watches personal computers, video momtois, portable computers (e g , laptops notebooks, handheld, palm) and projection displays The size of the display area has steadilv grown while general performance of LCD's has steadily improved in the last vears But an important issue is the power dissipation of the growing LCD's Users are steadilv looking for increased display size and higher resolution Enhancing both of these features, however consumes more and more energy New designs for portable digital devices, in particular, are aiming at lowering the power dissipation of every component and therefore increasing battery life Among the different factors contributing to the power dissipation of an LCD are the background illumination and the signal or image information transfer The background illumination can be completely eliminated m applications where the natural incident light can be used so that the LCD operates m a reflection mode In one aspect, this invention relates to the power reduction related to the signal or image information This signal information transfer is related to the charging and discharging of a matrix of capacitive LC- pixels The most popular and most widely used LCD's are based on Twisted Nematic, Super Twisted Nematics and Cholesterics Displays fabricated with these kinds of LCD-materials operate with polarizers and analyzers, hence restricting the use of back hght free operation This induces optical losses such that more power is needed for the back hght illumination or higher levels of natural incident hght are required More recently much effort has been spent m the development of Polymer Dispersed LCD's as described by Ikeno et al , "A 23-cm Diagonal Bright Reflective Guest-Host TFT-LCD", SID 1995 Digest, pp 333-336 These Polymer Dispersed LCD's do not use polarizers, thereby saving back light power or allowing a lower level of natural hght illumination Unfortunately, the driving voltages for the Polymer Dispersed LCD pixels are higher and therefore any energy saved from lower power back hght illumination is lost The present invention can drastically lower the power dissipated when driving the pixels even at extended voltage levels, such that eventually the LCD consumes less energy Several methods, or addressing schemes, have been developed for sending signals or image information to LCD's The three most important are direct addressing, and passive and active matrix addressing Direct addressing, usually used in watches and calculators is great for simple alphanumeric characters, since one signal controls one segment of pixels However, direct addressing is unrealistic for larger systems because of the large number of wires that need to be interfaced In a matrix system, the number of wires can be greatly reduced by splitting up the display into a grid of wires called rows and columns, with a pixel at the intersection of each row and column Matrix displays can be grouped into two categories, passive matrix liquid crystal displays (PMLCD) and active matrix liquid crvstal displays (AMLCD) A PMLCD is the simplest display for achieving low power, low cost and small size In a PMLCD, only a LC-pixel is located at the intersection of each column and row. PMLCD's have, m general, less performance than the AMLCD's but are much simpler to fabricate and therefore preferred for smaller, less accurate displays In an AMLCD, an extra nonlinear element is introduced at each pixel location to enhance the nonlinear behavior (i.e., contrast) of each pixel. This extra nonhnear element can be a two-terminal device or a three- terminal device The number of terminals at the pixel location influences the driving scheme. The trend toward larger, higher definition displays in notebook computers is forcing display manufacturers to seek new electrical drive methods for the integrated circuit that drives the LCD Current methods for driving the electrical signals onto these displays have been proposed to address significant issues with power dissipation and image quality. For example, Erhart et al ("Charge-Conservation Implementation in an Ultra-Low-Power AMLCD Column Driver Utilizing Pixel Inversion". SID 1997 Digest, pp 23-26) implemented a capacitively based energy recovery method for AMLCD displays At the beginning of each row time, the column busses are shorted together to a supplemental capacitor, which naturally maintains a potential halfway between average upper and average lower voltage The maximum power saving of this method is limited to 50% Okumura et al. ("Multifield driving method for reducing LCD Power dissipation", SID 1995 Digest, pp 249-252) proposed a multi-field driving method for reducing LCD power dissipation In this method, the image refresh rate is lowered without flicker occurrence by dividing the field image into an odd number of interlaced sub-field images One sub-field flicker is compensated by the other sub-field flickered images. The power reduction is here limited to 30% In another proposal formulated by Sakamoto et al ("Half-Column-Lme driver method for Low-Power and Low-Cost TFT-LCDs", SID 1997 Digest, pp 387-390), the number of column drivers is halved and the number of row drivers doubled This technique can lead again to a power reduction of 50% The driving power of the LCD's schemes for two terminal devices has been improved by increasing the number of voltage levels applied to the select line as outlined by R A Hartman ("Two-Terminal Devices Technologies for AMLCDs", SID 1995 Digest, pp 7-9) The exceUent image quality demands higher power dissipation The system of the present invention is compatible with these improved schemes but further reduces the power dissipation In some cases, panel manufacturers are returning to direct drive displays Direct drive refers to the ability of the column driver chips to "directly" provide the alternating voltage and the variable magnitude See, for example, Erhart et al ("Charge- Conservation Implementation m an Ultra-Low- Power AMLCD Column Driver Utilizing Pixel Inversion", SID 1997 Digest, pp 23-26) This early drive technique had been abandoned by many of the major LCD manufacturers due to cost concerns and replaced by common backplane node driving Although direct drive requires higher voltage driver circuits, substantial power dissipation and image qualitv improvement could be reached compared to traditional drive methods The complementary driving schemes, direct drive and common backplane node can both benefit from the driving circuit and method described herein But even the prior art methods proposed to date have not provided satisfactory reduction of power dissipation The cost of the LCD is partiallv influenced by the glass quality and the integration possibility of the peripheral driver circuits on the LCD substrate This is discussed by Stewart et al , "Circuit Design for a-sihcon AMLCDs with Integrated Drivers", SID 1995 Digest, pp 89-92 and Aoyama et al , "Inverse Staggered poly-Si and Amorphous Si Double Structure Thin Film Transistors and LCD Panels with Peripheral Driver Circuits Integration", IEEE Trans Elect Devices 43(5), pp 701-705 (1996) Drivers and nonlinear elements integrated on poly-Si substrates feature low resistances but also require expensive high-quality glass resistant to high temperature processing The technological tendency has been toward laser annealed hydrogenated amorphous silicon (a-Si H), which features low resistance values and process temperatures and therefore cheaper glass The invention proposed here can strongly benefit from these technological improvements as explained below SUMMARY OF THE INVENTION In one aspect, the present invention proposes a driving system where the pixels of a LCD or similar device are charged and discharged by constructing a LRC resonant circuit whose oscillation can be interrupted after half an oscillation period (or after an even number of full periods). The energy used for charging a pixel is partially recuperated when discharging the pixels The energy recuperation improves with the decrease of the resistance of the drivers and the nonlinear elements m the AMLCD's The proposed driving circuit and methods of this embodiment will continue to benefit from these technological tendencies In another aspect, the present invention is directed toward a novel apparatus and method for charging and discharging the pixels of a matrix- based liquid crystal display The power dissipation is reduced without sacrificing the quality of operation of the liquid crystal display matrix The present invention also provides an oscillation sensing means and a method to sense the state of the oscillation such that the oscillation can be interrupted at the appropriate time In one aspect, a row driver circuit can be used with a matrix display device that includes a plurality of pixels disposed in rows and columns The row driver circuit includes at each row a first and second switch with then' current path coupled to a positive and negative high voltage node, respectively A third switch at each row is coupled with its current path to the ground A fourth switch at each row enables or disables the oscillation of the resonant row circuit, comprising a common inductive element connected to common switches A first common switch couples the common inductive element to half the positive high voltage node A second switch couples the mductive element to half the negative high voltage node Variants on this scheme will be detailed later In another aspect, a column driver circuit can be used with a matrix display device that includes a plurality of pixels disposed m rows and columns The column driver circuit mcludes at each column a first and second switch with their current path coupled to a positive and negative high voltage node, respectively A third switch at each column connects or disconnects the said column to a common resonant circuit, consisting of a common inductive element connected at one side to ground and at the other side to the common node of the said third switches. A matrix display can use either one or both of these column driver circuits and row driver circuits Depending on the matrix technology used, the novel driving methodology can be adapted In the preferred embodiment, different driving schemes are proposed for passive matrix (PMLCD), two-terminal active matrix, and three terminal active matrix (AMLCD) Examples of these embodiments are described in the next paragraphs Columns/Passive Matrix and Three Terminal Active Matrix In this embodiment, the driving scheme allows a subset of columns of pixels to be connected together thereby reversing their polarity from plus to minus in a first step and from minus to plus in a second step In this embodiment, the polarity change for each group of pixels is established in a sequential way, by connecting them to an inductive element whose voltage node is biased at a voltage level between the opposite polarity voltage levels Energy stored in a capacitive form on one such group of connected columns is transferred to the inductive energy storage element and then back towards the capacitive pixels Snap circuits can be employed to snap the voltage to the required voltage level after the non-perfect voltage change occurs Rows/Passive Matrix, Two-Terminal and Three-Terminal Active Matrix In this embodiment, the driving scheme allows the pixels (or the gates) of each row to charge in turn from the deselecting voltage level toward the selecting voltage level via an inductive storage element whose voltage node is biased at a mid-level voltage When the capacitive energy is transferred from the pixels (or the gates) toward the inductive element and back, all the pixels (or the gates) of one row are snapped to the selecting voltage level during the select time interval Afterwards all the pixels (or the gates) are discharged again to the deselecting voltage level by means of the same inductive storage element connected to the same voltage node When the capacitive energy is again transferred from the pixels (or the gates) of one such row toward the inductive element and back, all the pixels (or the gates) of this one row are snapped to the deselecting voltage level during a frame time period After one row time, the next row of pixels is treated similarly This cycle repeats each frame time Rows/Passive Matrix and Two-Terminal Active Matrix In another embodiment for this example, the driving scheme allows a voltage pulse to be sent to each row of pixels in turn Each row is first charged from the deselecting voltage level toward about Λ/2 times the selecting voltage level and immediately back to the deselecting voltage level via an inductive storage element Again, the inductive storage element is biased at a voltage level between the select and deselect voltage levels Energy stored in a capacitive form on the connected row of pixels is transferred to the inductive energy storage element and back towards the capacitive row of pixels The energy exchange from the capacitive form towards the inductive form and back is repeated an even number of times such that at the end of the select time interval the deselect voltage level is again acquired on the selected row of pixels A snap circuit can be employed to snap the voltage to the required deselect voltage level after the voltage pulse is fed to one row of pixels After one row time the next row of pixels is treated similarly This cycle repeats each frame time Rows/Passive Matrix and Two-Terminal Active Matrix In another embodiment for this example, the mter-row transfer driving scheme allows the deselection and selection of two consecutive rows m a coupled way in turn A first row is first discharged from the selecting voltage level (±Vs) toward the deselecting voltage level via an inductive storage element In this case, the inductive storage element is biased at the deselecting voltage Energy stored in a capacitive form on the connected row of pixels is transferred to the inductive energy storage element At that moment when the first row reaches the deselecting voltage level, the next row of pixels is connected to the same side of the same inductive element while the first row of pixels is disconnected This allows the inductive energy stored in the inductor to be transformed to capacitive energy of the second row of pixels When the second row of pixels is charged up to the selecting voltage level (+ V s ) but reverse polarity with respect to the first row of pixels, the second row of pixels is also disconnected A snap - / - Circuit can be employed to snap the voltage of both rows to the required deselect voltage After one row time the next couple of rows of pixels is treated similarly This cycle repeats each frame time This embodiment implements the row inversion method in a natural way The preferred embodiment of the present invention also allows the voltage level of the common node of a three terminal active matrix liquid crystal display to change by connecting it to an inductive element biased at voltage level between the required voltage levels Various embodiments of the present invention also include oscillation- sensing circuitry (OSC) An oscillation sensing circuit is added to the different driver schemes to sense the state of the oscillation and to interrupt the oscillation at the appropriate time BRIEF DESCRIPTION OF THE DRAWINGS The above features of the present invention will be more clearly understood from consideration of the following descriptions m connection with accompanying drawings in which Figure 1 illustrates schematically the electrical equivalent scheme of a known general matrix Liquid Crystal Display Figure 2 zooms in on the three basic variants of a LCD-pixel a passive, a two- and three-terminal active device Figure 3 is a timing diagram showing an example of the driving voltages for the row and data lines of a pixel Figure 4 shows the basic circuit building block of the invention Figure 5 shows different time evolutions of voltage change of the LC- capacitance where discharging is shown for two different values of the LC- capacitance Figure 6 is a schematic diagram of a first preferred embodiment of row driving circuitry for a general LCD, including one mductive element and one oscillation sensing circuitry (OSC) Figure 6a shows three possible pixel arrangements for the circuit of Fig 6 Figure 7 shows the combmed tune evolutions of voltage and current change of one LC- row Figure 8 indicates a first preferred implementation of the OSC Figure 9 indicates a second preferred implementation of the OSC Figure 10 indicates a schematic diagram of a second preferred embodiment of row driving circuitry for a PMLCD and a two-terminal AMLCD, including one mductive element and one OSC Figure 10a shows two possible pixel arrangements for the circuit of Fig 10 Figure 11 indicates a preferred implementation of the OSC for mter-row transfer Figure 12 shows the combmed time evolutions of voltage and current change of two consecutive LC- rows of mter-row transfer Figure 13 compares the time evolution of the voltage change of a full-period oscillation and a double half-period oscillation Figure 14 indicates the expected power reduction factor of a full-period oscillation implementation with respect to a double half-period oscillation implementation Figure 15 indicates a schematic diagram of a third preferred embodiment of row driving circuitry (e g , full-period oscillation implementation) for a PMLCD and a two-terminal AMLCD including one mductive element and one Oscillation Sensmg Circuitry Figure 15a shows two possible pixel arrangements for the circuit of Figure 15 Figure 16 indicates a preferred embodiment of the OSC of the full-period oscillation implementation Figure 17 indicates a schematic diagram of a data driving circuitry for a general matrix LCD, mcluding one mductive element and one Oscillation Sensing Circuitry Figure 18 indicates a schematic diagram of a data driving circuitry for a general matrix LCD, mcluding two mutually coupled mductive elements and one Oscillation Sensmg Circuitry Figure 19 indicates a schematic diagram of a row driving circuitry for a general matrix LCD, including two mductive elements and one Oscillation Sensmg Circuitry Figure 20 indicates a schematic diagram of a common plate driving circuitry for a known three-terminal AMLCD Figures 21a and 21b compares the timing diagram of the direct drive and common plate drive implementation Figure 22 indicates a preferred embodiment for the common plate drrvmg circuitry of a three-terminal AMLCD DETAILED DESCRIPTION OF ILLUSTRATIVE EMBODIMENTS The making and use of the various embodiments are discussed below m detail However, it should be appreciated that the present invention provides many apphcable mventive concepts, which can be embodied m a wide variety of specific contexts The specific embodiments discussed are merely illustrative of specific ways to make and use the invention, and do not limit the scope of the invention The present invention will now be described with reference to the drawings After briefly discussing power dissipation m matrix displays, a first embodiment will be discussed with reference to a row driver of a general matrix LCD Variations to the circuit will then be discussed Peculiarities for three terminal AMLCDs will be highlighted After discussing the row drivers of matrix LCDs, an explanation of how the invention could be used with column drivers of matrix LCDs will be provided Finally a new circmtry for common plate driving for three- terminal AMLCDs will be proposed A classic matrix display 10 is made up of both rows 12 and columns 14 as shown schematically m Figure 1 The intersection of each row 12 and column 14 is the location of a Liquid Crystal (LC) cell 16, called a pixel 16 This general pixel presentation leads to different variations 162, 164 and 166 as shown Figure 2 In a passive matrix liquid crystal display (PMLCD) such a LC-pixel 16 is generally made from an insulated material, which can be electronically represented in its simplest way by a capacitor 162 as shown m Figure 2(b) An extra storage capacitor (not shown) can be added to the intersection points In two-terminal active matrix liquid crystal display (AMLCD) an extra nonlinear element is added to the pixel 164 in order to intensify the contrast ratio of the LC pixel (Figure 2c) and to introduce a memory like function Parasitic capacitances of such nonlinear elements at the pixel position 16 can also be included in the equivalent capacitance value of the LC-pixel In a third variant (Figure 2d) the pixel 166 consists of the LC element together with a field effect transistor Frequently the storage capacitor is added to the pixel location Returning to Figure 1 pixels 16 on the same row 12 share the same select or row driver 32 of the drivei set 18 Pixels 16 in the same column 14 share the same data or column driver 62 of the driver set 20 It is common usage that the transfer of the pixel data is accommodated through the use of a demultiplexer circuit (not shown) in order to limit the number of interconnections to the outside world With this configuration, cross talk exists between the different pixels but is attenuated by the nonlinear response of the LC pixel 16 An extra nonlinear circuit element can be incorporated at each pixel 16 to suppress cross talk as done m active matrix addressing Figure 3 illustrates a timing diagram for operating a PMLCD 10 of Figure 1 This passive matrix-addressing scheme of mean-square responding LCD's is also discussed by Alt and Pleshko (P M Alt and P Pleshko Scanning limitations of liquid-crystal displays, IEEE Trans Elec Devices ED-21, p 146, 1974) A complete frame is written m a time T., by sequentially activating the select fines during a select time Tsby means of the select voltage Vs, and simultaneously applying a voltage Vd to the data fines For black- white LCD's, Vd is a binary signal Grey scale LCD's, on the other hand, use e g multiple values for Vd The nonhnearity parameter P of a LC-pixel 16 is defined m terms of the RMS-voltages of the ON-state and OFF-state Vi and Vo respectively, relative to the optical threshold voltage Vth The optical threshold voltage Vih is the voltage level necessary to be apphed to a pixel 16 in order for that pixel 16 to be illuminated The nonhnearity parameter can be expressed as The P value determines the limit on the maximum number of addressable rows M For P«l, the expressions simplify In that case the relation between the number of addressable rows M and the corresponding data voltage Vd and select voltage Vs are deduced These equations illustrate that the data voltage Vd is much smaller than the select voltage Vs Since LCDs do not allow a DC voltage, the data and select voltages have both polarities ±V.ι and ±Vs The time evolution of the voltages applied to prior art driver circuits of a PMLCD is shown in Figure 3 The dynamic power dissipation of such a PMLCD can then be calculated P el , (PMLCD) = V C p MN(MJ tι )+ V C pιx N( Jr ) Here M and N are the number of rows and columns in the passive matrix, respectively fi- is the frame frequency, which is typically between about 50 and about 100Hz By introducing the nonhnearity parameter P in this power dissipation equation we can compare the contribution from the rows and the columns P eb (PMLCD) = V C pι J tl MN(MP" + l) If P 2 defines the maximum numbers of rows for which a particular PMLCD would still be operational, then M can be defined as M=β P 2 with β <1 This leads to the following dissipation formula P eb (PMLCD) = V C p tr MN(β + 1) The parameter β defines the distribution of the power dissipation between the rows and the columns and provides an indication of where the proposed invention can best be used, in the column or row driver or both The power dissipation in a 2-termmal AMLCD will now be discussed The nonlinear two terminal device is designed such that cross talk between pixels of different rows is strongly reduced. Hence one can calculate that the power reduces to the following expression. P Λ (IT - AMLCD) = V]C p>x N(MJ ) + V C pιx N(Mf fr ) This equation shows that the contribution of the columns to the total power dissipation decreases approximately with a factor M with respect to the PMLCD. As a consequence, power reduction for the row driving is here important When the row voltage is low, the nonlinear element is quasi nonconductive, irrespective of the column voltage. The column voltage has a value equal to or smaller than the threshold voltage of the nonlinear element In the nonconductive state, loading data by means of an inductor is usually futile because the V- os t would be intolerably high. Hence in a two terminal AMLCD it is preferably to drive only the rows adiabatically or by means of an LRC -circuit. The next type of display for which the power dissipation is discussed is the 3-termmal AMLCD In this case the nonlinear element added to the LC- pixel is a thin Film Transistor as illustrated in Figure 2d The row signals are now apphed to the gates of all the transistors of one row at a time The power dissipation reads as p eb (37 - AMLCD) = v;-c pn /J+rjς J As the gate capacitances C κ are typically smaller than the pixel capacitances and the driver voltage for the gates is of the same order as that of columns, it is clear that the row contribution to the power dissipation again is smaller than the column contribution In order to appreciate the operation principles proposed this invention for driving LCD technologies, reference is made to an RLC oscillation circuit 30 of Figure 4 to change the voltage over a LC-pixel 16 from one voltage level to another voltage level. The resistance R is the equivalent resistor of the switch 32 (labeled S.v) connecting the LC-pixel 16, representing a subset of LC-pixel capacitances (see below) to the inductor 34 (labeled L). Inductor 34 is terminated at one side to a voltage node Va/2, preferably half the value of the desired voltage level of the LC-pixel 16 In the preferred embodiment bias capacitances 36 and 38 (labeled CM and Cb 2 ) are equal to each other and much greater than the total sum of capacitances of the subset LC-pixels 16 that could be connected to the inductive element 34 First one assumes that the voltage over the capacitance 16 is zero when the switch is open (t<0) The inductance is connected to the voltage V /2 At the moment when the non-ideal switch 32 with a series resistance R is closed, a well-known oscillation, as shown in Figure 5, starts to charge the capacitance up to a voltage V ma χ, which is equal to V, when R=0 The voltage loss due to the presence of the non-ideal switch at each extremum text n can be calculated as i r The losses increase at each extremum t< n which is defined as te t n =nπ/ω The pulsation o is defined as follows In the case of a 2-termιnal AMLCD, an additional loss, howevei, is introduced This loss is equal to V-a and due to the voltage drops over the 1 5 nonhnear elements The voltage V-/2 determines the mid-voltage around which the oscillation takes place Referring now to Figure 5 when one wants to bring the voltage from a first value (0 in this example) to a second value (10 in this example) the oscillation 1 is interrupted at a maximum or local extreme voltage (preferably 20 the first maximum or local extreme voltage 5 to minimize the loss) When one wants to send a pulse the oscillation is interrupted at the second (or more general at an even) extremum 6 Figure 6 illustrates an array of LC pixels 12 and the corresponding drive circuitry When one considers the possible set of capacitors as one row 12 of 25 capacitors 16, the oscillation pulsation for each row 12 of pixels 16 connected via the row switch 322 can be considered as constant When one considers the possible set of pixel capacitor 16 as a subset of the columns 14, requiring the same voltage change, the oscillation pulsation differs for each number of columns 14 of pixels 16 as illustrated in Figure 5 for curves 2 and 3 As a consequence, the extrema 7 and 8 m time and the voltage loss depend here on the data fed to the different columns of the LC-pixels 16 In a first preferred embodiment, an inductive element 34 is connected to the mid-voltage levels V s /2 and -Vs/2 by means of two switches 40 and 42 (labeled SLA and SLB) as illustrated in Figure 6 The columns 14 are selected as described with respect to Figure 1 The mid-voltage levels Vs/2 and -Vs/2 are provided by bias capacitors 36a,b and 38a,b Each row 12 has four switches 322, 324, 326, 328 in parallel As an example, a switch 322,324,326,328 (or 40 or 42) can comprise any means for temporally connecting a first node to a second node In the preferred embodiment, the row driver 32 may comprise a set of pass transistors (e g , bipolar or FET - n-channel or p-channel), a CMOS switches or a BiCMOS switches One of the switches 322 is connected to the inductive element 34 and the other 3 switches 324, 326, 328 are connected to the -V , ground and Vs, respectively This first embodiment apphes to all kind of matrix LCDs In the case of three-terminal AMLCDs, however, the negative select voltage branch of the circuit is omitted reducing the number of switches at each row to three and eliminating one switch 42 at the inductance node The driving cycle starts with the classic switching of the data lines and consequently one of the rows 12 is connected to the inductive element 34 for a positive or negative half-period swing In the case of a positive swing the switch 40 (SLΛ) IS closed, m the other case switch 42 (SLB) IS closed Figure 5 shows the timing of the voltage changes All the other rows are tied to the ground level After half a period when the first extremum is reached, the oscillation should be interrupted Afterwards, the small voltage loss Viost can be restored by snapping the pixel 16 to the requested select voltage level Vs by means of switch 328 After the snap, the row 12 is held during the select time to the select voltage level Vs or -Vs Afterwards, the row (12) of pixels (16) swing back to the ground level The return to ground can be accomphshed by once again connecting the fine 12 to inductive element 34 and oscillating for half a period Again, reference can be made to Figure 5 After this swing, the row 12 is again grounded In the next step all the data values are again changed for the next row 12' in the same way The next row 12' will oscillate to the requested row voltage Vs or -V s Depending on the inversion method used, this -will be the same or the opposite row voltage with respect to the previous row In the frame inversion technique, the row voltage changes sign only after every frame In the row inversion method the voltage connection changes its sign at each new row operation This cycles repeats after every frame time As stated, the oscillation is preferably interrupted after the first half period Hence an oscillation sensing circuitry (OSC) 50 should be included to interrupt the oscillation at the right moment Such OSC 50 can be implemented m several different ways As the number of pixels per row is constant, the oscillation period should be almost constant The values of the inductor 34 is chosen m accordance with the available charging and discharging time of the pixels 16 of one row 12 Various circuits, which can be used for this purpose, are illustrated in Figures 8 and 9 These OSCs 50 can be easily understood with reference to Figure 7 where the current and the voltage changes are illustrated a single diagram The extrema 7 of the voltages coincide with moments of current reversal 9 in the oscillation circuit The sensing of the current reversal 9 is more adequate than the sensing of the voltage extrema 7 The OSCs described below focus on the current behavior of the oscillation In a first embodiment of an OSC 50, a current inversion detection circuit as illustrated in Figure 8, could be used An appropriate resistor 52 can be included in the oscillation circuit 50 The voltage over the resistance 52 is sensed by an operational amplifier 54, which operates in the comparator mode The two possible values of the comparator output are determined by the current direction When the current reverses its direction the output of the comparator will switch from its first to its second value The row controller 48 detects the output change and can generate a signal to open again the row switch 322 (Sri) to interrupt the oscillation As the period of the oscillation is quite large a small timing error due to offset errors of the operational amplifier 54 is not dramatic. The row controller 48 has full control over the four switches 322, 324, 326, 328 (see Figure 6) of the row driver 32 of each row 12 and the two common inductor switches 40, 42 (SA, SB). One of the switches 322 is connected to the inductive element 34 and the other three switches 324, 326, 328 are connected to -Vs, ground and +Vs, respectively. When closing one of these switches 324, 326, 328, a current path is formed between the group of pixels and the corresponding voltage node of that switch. Figure 9 illustrates a second embodiment matrix that includes an alternate embodiment OSC 50 based on the phenomenon that the current changes its direction when the pixels 16 of the selected row 12 are charged to the extremum voltage value 5, 7 or 8. In this embodiment, diodes 56 and 58 are included between each inductor switch 40 and 42 (Sa and Sb) and the common node of the inductor 34. The diodes 56 and 58 are connected in anti-parallel (that is, the anode of diode 56 is coupled to the cathode of diode 58, and vice versa). Depending on the oscillation cycle (positive or negative), switch 40 or 42 is closed. When the pixels 16 of a row 12 oscillate from the ground level to the positive select level, the switch 40 is closed causing the current to flow from the mid-level voltage node Vs/2 towards the pixel capacitances. At the moment when the extremum voltage level is reached, the current cannot reverse due to the blocking diode 56. Hence the oscillation automatically stops. This diode circuit 50 can be combined with a clocked circuit (not shown), whose period is at least equal to the maximum estimated swing period. The diode 56 (58), however, introduces extra losses. Therefore, the diode 56 (58) is preferentially used when the select voltage levels are large in comparison with the diode drop voltage. The preferred diode type is a Schottky diode. When the pixels of one row 12 change their voltage from the deselect to the select level, a particular loss can be estimated. This loss can be anticipated by increasing the voltage slightly such that the snap is not really needed, thereby simplifying the circuit. When the row of pixels is deselected after the select time, the pixel voltage swings to ground again This eventual loss is now immediately restored by grounding the pixel In an alternate embodiment, the oscillation cycle is partitioned over two consecutive rows 12 as illustrated m Figure 10 This implementation is preferably apphed to PMLCDs and two terminal AMLCDs with their basic pixel elements 162 and 164 respectively The number of switches at each row driver 32 is unchanged with respect to the first preferred embodiment (Figure 6) Each row 12 again has one switch 322, which provides the connection to the common node of the inductive element 34 The other node of the inductive element 34 is here, however, tied to the ground The driving cycle will now be described At the end of the row select time of a row 12, the row 12 is set to the deselect voltage level again This is effectuated by sending a control signal from the row controller 48 to the driver 32 The control circuit causes switch 322 to connect row 12 to the common node of the inductive element 34 Consequently the pixels 16 of row 12 will oscillate to the inverse polarity of the select voltage This oscillation should be interrupted when the ground level is reached At the moment of this interruption, all the capacitive energy of the pixels 16 of row 12 is transformed into magnetic energy of the inductive element 34 The row 12 is tied to ground by means of switch 326 of row driver 32 This inductive energy can be reused to select the next row 12' This row 12' can oscillate to the opposite polarity of the select voltage level when the row controller 48 sends a signal to connect the next row 12' to the common node of the inductive element 34 by means of switch 332 of row driver 33 This circuitry immediately features the row inversion technique The second phase of the oscillation should be interrupted when all the magnetic energy is converted m capacitive energy of the pixels 16 The timing of the interruption of both phases of the oscillation can be controlled by means of appropriate oscillation sensing circuitry 50 At the end of the oscillation, when row 12 is snapped to its extreme value 5, 7 or 8 by means of switch 334 or 338, the classic switching of the data fines is effectuated After the snap, the row 12' is held during the select time to the select voltage level Vs or -Vs Afterwards, the row 12' of pixels 16 swing again to the ground level in a two- phase oscillation cycle involving row 12' and row 12" This cycles repeats after every frame time. The time evolution of the pixel voltages on rows 12' and 12" are shown in Figure 12. A first embodiment of the oscillation sensing circuitry 50 for the mter- row transfer circuitry is illustrated in Figure 11. First a comparator 60 is added to the oscillation circuitry 50 One input of the comparator 60 is connected to the RLC circuit and the second input is connected to a small voltage ε This small voltage value ε is provided to interrupt the oscillation, started by sending a signal from the row controller 48 to close the switch 322 when the voltage reversal is almost accomplished When this comparator 60 changes its output state, the row controller 48 will disconnect row 12 and will connect row 12'. At the moment of switching from one row to another the current is maximum Hence the current should be allowed to continue to flow Secondly, an appropriate resistor 52 is added to the oscillation circuit 50 The voltage over the resistance 52 is again sensed by means of the operational amplifier 54 operating m the comparator mode When the current reverses its direction, the output of the comparator 54 will switch from its first to its second value The row controller 48 detects the output change and can generate a signal to open again the row switch Si -+ι 332 to interrupt finally the oscillation As the period of the oscillation is quite large a small timing error due to offsets errors of the operational amplifier 54 is not dramatic The row controller 48 has full control over the four switches 322, 324, 326, 328 of each row driver 32 of each row 12. The optical output of a LC pixel 16 is in accordance with the RMS- voltage imposed on the pixel 16 during a frame time The LC-pixel cannot respond to fast voltage changes As such, the classic rectangular voltage pulse imposed on the pixel during the row operation could be replaced by an equivalent sinusoidal shaped pulse It is generally known that a sinusoidal voltage is equivalent to a square voltage pulse when the amphtude of the sinus wave is equal to V sm u = 2V q In another preferred embodiment the circuit oscillates over a full-period as illustrated by the oscillation 40 m Figure 13 When one allows an oscillation over the full period instead of two half -period oscillations 42 and 44 over a very short interval of the select period, one can easily calculate that the electrical power dissipation can be further reduced The losses for both systems are compared by power reduction curve 46 in Figure 14 Because the system can oscillate longer and slower, the inductance value can be increased with a factor s Speed reduction is proportional to T Realistic values for s are between about 20 and 100 This leads to a power reduction of about a factor 3 to 7, as illustrated Typically, a full-period system is preferred since the speed of the oscillation is largely reduced and the power dissipation drastically reduced The preferred circuits are illustrated m Figures 15 and 16 This principle can be apphed to a PMLCDs and 2 -terminal AMLCDs with the elementary pixel element 16 represented by 162 and 164 The charging and discharging of the gates in a 3-termmal AMLCD is preferentially not executed m a full-period mode due to capacitive couphng between rows and the columns via the gates The bias voltage apphed to inductor 34 is now about ±Vs/V2 instead of about ±Vs/2 (In cases where the reference voltage is not zero, the bias voltage can be expressed as about the reference voltage plus one over the square root of two times the absolute value of the difference between the high voltage and the reference voltage ) This bias voltage is chosen such that the effective value seen by the pixel 16 is the same as that of an equivalent rectangular pulse In this preferred circuit, the number of switches at each row driver 32 of each row 12 can be halved with respect to the half-period swings One of the switches 327 of a row connects the row to the ground level, while the other switch 325 provides the connection to the common node of the inductive element 34. This inductive element 34 is connected at its other termination to two switches 40 and 42. Depending on the required polarity of oscillation the switches 40 and 42 provide a connection to the positive or negative bias levels provided by means of the bias capacitors 36 and 38. In order to interrupt the oscillation of the row LRC circuit, an oscillation sensing circuit 50 is provided. A first embodiment of the OSC 50, detailed in Figure 16, is again added to the oscillation circuit. The voltage over the resistance 52 is sensed by an operational amplifier 54 operating in the comparator mode. The two possible values of the comparator output are determined by the current direction. When the current reverses its direction the output of the comparator 54 will switch from its first to its second value. The row controller 48 detects the output change. In this full-period oscillation implementation the row controller 48 may only generate a signal to open again the row switch 325 (Sri) to interrupt the oscillation, after the second output change of the comparator, i.e., after the second current inversion. As the period of the oscillation in this implementation can be large a small timing error due to offset errors of the operational amplifier 54 is not dramatic. The row controller 48 has full control over the two switches 325 and 327 of each row driver 32 of each rowl2 and the two common inductor switches 40 and 42. Figure 17 illustrates another embodiment where the oscillatory driving circuit of the row driver described above is applied to data driver circuitry. In this embodiment, the oscillatory driving circuit is shown for the column only but it is understood that it could be used for both of them. A person skilled in the art can decide depending on the type and size of the LCD where the implementation of the new RLC driving circuitry is most fruitful, in the row driver, column driver or both of them. The column data swing between ±Vd. In this preferred embodiment, each column 14 has a column driver 62 consisting of three switches 622,624,626. A first switch 624 of each column 14 is connected to the common node of the inductive element 64. This inductive element 64 is terminated at the other side to the ground. The other two switches 622 and 626 provide the snap connection to ±Vd respectively. The number of columns 14 connected to the inductive element 64 is here dependent on the incoming pixel data. As a consequence the oscillation characteristics such as speed and losses are data dependent as was illustrated by the oscillation curves 2 and 3 of Figure 5. In a first preferred column driver circuitry, the sequential or two-phase version is implemented. The subset of pixels of the selected row 12, which were negative and need to become positive are connected the first phase to the common node of the inductive element The subset of pixels of the said selected row 12, which were positive and need to become negative are connected in a second phase to the inductive element Some data won't change sign and hence a subset of pixels 16 won't be connected to the inductive element 64 during this select time interval In the column driving circuitry, the oscillation period and the induced losses are data dependent as previously discussed with respect to Figure 5 The different interrupting and snapping circuits discussed above with respect to the row operations can be also be used for the columns Different combinations of the circuits can be used In other words, the row can include one embodiment interrupting circuit while the column uses a different embodiment interrupting circuit Alternatively, the same interrupting circuit could be used for each When the data are set before the rows are selected, the column oscillation is a half-period swing with its period much shorter than the data select period When the data have been loaded into the pixels capacitances, the rows 12 can be again loaded m either a half or a full-period oscillation, the full- period oscillation being preferred After the row, has been charged and discharged the data can be again loaded for the next row operation The period as well as Vio s are in general different for both phases The interruption of the oscillation tends to be important now since the oscillation time is not known in advance Hence a fixed clocked system is not preferred m this case The self -interrupting diode circuits (see e g , Figure 8) or current reversal detecting circuit (see e.g., Figure 9) can be implemented. After switching, the snapping circuit should be apphed to tie each pixel to its required voltage level The upward swinging columns and the downward swinging columns can be connected in a concurrent way as illustrated in Figure 18. In this preferred implementation two inductive elements Lai and La 2 are provided The inductive elements Lai 68 and Ld269 are mutually coupled With their common node being tied to ground The number of switches at each column driver 62 has increased by one with respect to the sequential implementation The extra switch 628 provides the connection to the second inductive element The subset of columns which need to change their voltage from positive to negative are coupled and to the first inductive element Lai 68 The subset of pixels 16 which need to change their polarity in the reverse direction are coupled to the other inductive element La 2 69 Both oscillations can occur concurrently in this way In the case when the two inductive elements Lai 68 and La 2 69 are strongly mutually coupled, the two oscillations evolve m phase even when the number of upwards switching columns differs from the number of downward switching columns The column data swing between ±Vd in this preferred embodiment, each column 14 has a column driver 62 consisting of three switches 622, 624, 626 When closing one of these switches, a current path is formed between the group of pixels and the corresponding voltage node of that switch For the case when the inductive elements are only weakly mutually coupled or m the extreme case not coupled at all, the oscillations of both subset of pixels will occur in very distinctive way Each of the concurrent oscillations shows in that case a different Vio s and oscillation period In general the concurrent operation principle is faster the sequential is less complicated and consumes less driver chip area The two inductive element concept can be implemented for the row driver system as well In that case the number of switches at each row driver 32 increases from 4 to 5 when one changes the system for one to two inductive elements as illustrated m Figure 19 The switches 40 and 42 (see Figure 6) between the bias voltages and the inductive elements 34 can be removed The inductive elements 34 do not need to be mutually coupled, as both inductive elements do not carry current simultaneously In this case, the decision to connect the row to one of the conductors is implemented m the switches of each row driver 32 When the row needs to be driven to a positive selection voltage the inductive element La is carrying current, m the charging as well as in the discharging phase of the oscillation This is accomplished by means of switch 322 In the other case when the negative selection voltage needs to be apphed to the said row, the other inductive element is carrying current and this is accomphshed by means of switch 323 Grey level implementation can be accomphshed m different ways The proposed LRC oscillation system is compatible with amphtude and pulse width modulation The column drivers load the data of the same polarity m a quasi- adiabatic way to the average value of the pixels of that polarity Afterwards each data column is snapped to the particular gray level voltage The average value is larger than the specific deviation for a particular gray scale Other combinations of adiabatic switching of the row and data fines can be deduced from this general idea One of ordinary skill in the art, with the assistance of the teachings herein, will be able to expand this system to more complicated multi-level addressing schemes of LCD's, which are used to increase the display quality of the LCD Persons skilled m the art can determine the optimum multi-level scheme (also called number of driving biases) for a LCD in accordance with the display duty cycle ratio A final illustration of the present invention deals with the common plate driving of a 3T-AMLCD (three-terminal active matrix liquid crystal display) A schematic view of a prior art 3T-AMLCD is shown m Figure 20 At each pixel location 16 the liquid crystal is connected to a common node labeled Vic This common node behaves like a common plate with a capacitance equal to the sum of all liquid crystal pixels In the common plate driving implementation, the drivers exhibit unipolar characteristics as shown in the timing diagram of Figure 21 In order to change the polarity of the pixels it is necessary to change the voltage at the common plate The alternative to common plate driving, as shown in Figure 21, is the direct drive scheme where the drivers can provide both the magnitude and the polarity Solutions to decrease the power dissipation of the direct drive scheme were previously described in preferred embodiments of the column drivers Here we describe a new method to drive the common plate The electric circuitry to drive the common plate 75 is relatively simple and shown m Figure 22 The common plate node Vic 78 is connected by means of a switch 70 to an inductive element 72 The inductive element is biased by means of two capacitors 74 and 76 to a voltage value equal to the average of VH 82 and VL 84, the high and low value of the common node 78 respectively At the beginning of each frame period the switch 70 is closed to reload the common plate from its high to its low value or vice versa The timing of the oscillation can again be controlled by means of an oscillation sensing circuitry, which is similar to the ones described the row and or column driver circuitry When the end of the oscillation cycle is sensed by the oscillation sensing circuitry, the oscillation is interrupted by opening switch 70 At the same time, the common plate voltage is snapped to the low or the high voltage level by means of switch 172 or 174, respectively By means of this new method an important disadvantage of common plate driving, I e , its power dissipation can be drastically lowered and making the common plate driving a competitive alternative for the direct drive schemes The present invention has thus far been described with examples of matrix displays that use two or three voltage levels to select pixels for display The present invention is also intended to encompass displays with one or more than three select voltage levels In a number applications, even for black-white screens without grey levels, more voltage levels are used to improve the image quality The system of Figure 6, for example, utilizes three voltage levels for the rows (Vs, ground, and -Vs) and with two voltage levels for the columns (+Vd and -Vd) Other displays may use more than three voltage levels for the rows For example, commercially available drivers, such as the HD44100R sold by Hitachi, use four voltage levels for the columns and rows While this invention has been described with reference to illustrative embodiments, this description is not mtended to be construed m a limiting sense Various modifications and combinations of the illustrative embodiments, as well as other embodiments of the invention, will be apparent to persons skilled in the art •upon reference to the description. It is therefore mtended that the appended claims encompass any such modifications or embodiments.

Claims: WHAT IS CLAIMED IS 1 A driver circuit for a matrix display device that mcludes a plurality of pixels disposed m rows and columns, the driver circuit comprising a first switch with a current path coupled between a reference voltage node and a group of pixels, a second switch with a current path coupled between a high voltage node and said group of pixels, wherem the high voltage node is at a voltage larger than the reference voltage node, and a third switch with a current path coupled between an mductive storage element and said group of pixels, the mductive storage element bemg coupled to an intermediate voltage node, a voltage at the intermediate voltage node bemg between a voltage at the high voltage node and the voltage at the reference voltage node 2 The circuit of claim 1 and further comprising a control circmt with outputs to control the conductivity of the first switch, the second switch and the third switch, the control circmt causing no more than one of the first switch, the second switch and the third switch to be conductive at a time 3 The circuit of claim 2 and further comprising an oscillation sensmg circuit coupled to the mductive storage element, the oscillation sensing circuit including an output coupled to the controller 4 The circuit of claim 3 wherem the oscillation sensmg circuit comprises a comparator with first and second inputs and an output, the output being coupled to the controller, and a resistive element coupled between the first and second mputs of the comparator, the resistive element having a current path coupled in series with the inductor and the group of pixels 5 The circuit of claim 4 wherem the comparator comprises an operational amplifier 6. The circuit of claim 3 wherem the oscillation sensing circuit comprises a diode with a current path coupled in series with the inductor and the group of pixels. 7. The circuit of claim 1 wherein the circuit further comprises: a fourth switch with a current path coupled between a fourth voltage node and the group of pixels, the fourth voltage node being held at a voltage which is less than the voltage at the reference node. 8. The circuit of claim 7 and further comprising: a fifth switch coupled between the inductive element and a fifth voltage node with a voltage level between the voltage on the fourth voltage node and the reference voltage; and a sixth switch coupled between the inductive element and the intermediate voltage node. 9. The circuit of claim 7 and further comprising a fifth switch with a current path coupled between a second inductive storage element and said group of pixels, the second inductive storage element being coupled to a fifth voltage node which is held at a voltage between the voltage at the fourth voltage node and the voltage at the reference voltage node. 10. The circuit of claim 1 wherein the group of pixels comprises a row of pixels. 11. The circuit of claim 1 wherein the group of pixels comprises at least one column of pixels. 12. A display device comprising: a plurality of pixels disposed in rows and columns; a column driver with a plurality of outputs, each column driver output coupled to a respective one of the columns; a row driver with a plurality of outputs, each row driver output coupled to a respective one of the rows, the row driver including. a first switch -with a current path coupled between a reference voltage node and the row of pixels; an inductive element coupled to a bias voltage node; and a second switch with a current path coupled between the mductive element and the row of pixels. 13. The device of claim 12 wherem the display device comprises an active matrix liquid crystal display. 14 The device of claim 13 wherem the display device comprises a passive matrix liquid crystal display. 15. A driver system for a liquid crystal display (LCD) that includes a plurality of pixels disposed as a matrix of column and row fines, the driver system for driving a group of pixels to a high voltage and a low voltage, the driver system comprising: an inductive element having first and second terminals, the second terminal of the inductive element being coupled to the group of pixels for at least some period of time; first and second bias nodes, the first bias node having a voltage bias less than the high voltage and the second bias node having a voltage bias greater than the low voltage; a first switch coupled between the first bias node and the first terminal of the inductive element; and a second switch coupled between the second bias node and the first terminal of the inductive element. 16. The system of claim 15 wherem each pixel m the group of pixels is coupled to one of the row lines 17. The system of claim 15 and further comprising a reference voltage node, a voltage at the reference voltage node being less than the high voltage and greater than the low voltage, wherein the voltage at the first bias node is about half way between the voltage at the reference voltage node and the high voltage, and wherein the voltage at the second bias node is about halfway between the voltage at the reference voltage node and the low voltage. 18. The system of claim 15 and further comprising a reference voltage node with a reference voltage, the reference voltage being less than the high voltage and greater than the low voltage, wherein the voltage at the first bias node is greater than the reference voltage by about one over the square root of two times the absolute value of the difference between the_high voltage and the reference voltage, and wherein the voltage at the second bias node has a value less than the reference voltage by about one over the square root of two times the absolute value of the difference between_the low voltage and the reference voltage. 19. The system of claim 15 wherein said group of pixels comprises at least one column of pixels, the system further comprising: a second inductive element having first and second terminals, the second terminal of the second inductive element being coupled to a row of the pixels for at least some period of time; third and fourth bias nodes, the third bias node having a voltage bias less than a high row select voltage and the fourth bias node having a voltage bias greater than a low row select voltage; a third switch coupled between the third bias node and the first terminal of the second inductive element; and a fourth switch coupled between the fourth bias node and the first terminal of the second inductive element. 20. A driver system for a liquid crystal display (LCD) that includes a plurality of pixels disposed as a matrix of column and row lines, the driver .system for driving a group of pixels to a high voltage and a low voltage, the driver system comprising: a first inductive element having first and second terminals, the first terminal coupled to a first bias node which is held at a voltage less than the high voltage; a second inductive element having first and second terminals, the first terminal coupled to a second bias node which is held at a voltage greater than the low voltage; a first switch coupled between the second terminal of the first inductive element and the group of pixels; and a second switch coupled between the second terminal of the second inductive element and the group of pixels. 21. The system of claim 20 wherein each pixel in the group of pixels is coupled to one of the row lines. 22. The system of claim 20 wherem each pixel in the group of pixels is coupled to at least one of the column lines. 23. The system of claim 22 wherein the group of pixels comprises a set of columns of pixels, the system further comprising: a third inductive element having first and second terminals, the first terminal coupled to a high row voltage node which is held at a voltage that is less than a high row select voltage; a fourth inductive element having first and second terminals, the first terminal coupled to a low row voltage node which is held at a voltage that is greater than a low row select voltage; a third switch coupled between the second terminal of the third inductive element and a row of the pixels; and a fourth switch coupled between the second terminal of the fourth inductive element and the row of the pixels. 24. A driver circuit for a matrix display device that includes a plurahty of pixels disposed in rows and columns, the driver circuit comprising: a first switch with a current path coupled between a reference voltage node and a group of pixels; an inductive element coupled to a bias voltage node; and a second switch with a current path coupled between the inductive element and the group of pixels. 25. The circuit of claim 24 wherem the mductive element is coupled to the bias voltage node through a third switch, the inductive element also being coupled to a second bias voltage node through a fourth switch. 26. The circuit of claim 24 and further comprising a third switch coupled between the group of pixels and a second reference voltage node. 27. The circuit of claim 26 and further comprising a fourth switch coupled between the group of pixels and a third reference voltage node. 28. The circuit of claim 27 wherein the mductive element is coupled to the bias voltage node through a fifth switch, the inductive element also being coupled to a second bias voltage node through a sixth switch. 29. The circuit of claim 27 and further comprising a fifth switch coupled between a second inductive element and the group of pixels, the second inductive element being coupled to a second bias voltage node. 30. A method of driving a group of pixels in a matrix display device, the method comprising: inductively coupling the group of pixels to an intermediate voltage level between a first voltage level and a second voltage level; and decoupling the group of pixels from the intermediate voltage level when the group of pixels substantially reaches a local extreme voltage level relative to the intermediate voltage level. 31. The driving method as recited in claim 30, wherein the decoupling from the intermediate voltage level is triggered by sensing a current reversal in a current path of the group of pixels. 32. The driving method as recited in claim 31 wherem the current reversal is sensed by detecting a change in voltage polarity across a resistor in series with the current path of the group of pixels. 33. The driving method as recited in claim 31, wherein the decoupling from the inductive storage element is triggered by a clock signal in combination with an oscillation sensing circuitry including current reversal blocking diodes. 34. The driving method as recited in claim 30, and further comprising snapping the group of pixels to the first voltage level after the decoupling from the intermediate voltage level. 35. The driving method as recited in claim 30, and further comprising keeping said group of pixels in a high -impedance state after the decoupling from the intermediate voltage level. 36. A method of driving a group of pixels in a matrix display device, the method comprising: dividing the group of pixels in first and second subgroups of pixels, wherein pixels belonging to the first subgroup require a first change of voltage level and wherein pixels belonging to the second subgroup require a second change of voltage level; inductively coupling the first subgroup of pixels to an intermediate voltage level between a first voltage level and a second voltage level; inductively coupling a second subgroup of pixels to the said intermediate voltage level when the first group of pixels almost reaches the intermediate voltage level; decoupling the first group of pixels from the intermediate voltage level when the first group of pixels almost reaches the intermediate voltage level; and decoupling the second group of pixels from the intermediate voltage level when the second group of pixels substantially reaches a local extreme voltage level relative to the intermediate voltage level. 37. The driving method as recited in claim 36, wherem the decoupling from the inductive storage element of the first subgroup of pixels is triggered by sensing a voltage reversal with respect to the intermediate voltage level in an oscillation circuit. 38. The driving method as recited in claim 36, wherein the decoupling from the mductive storage element of the second subgroup of pixels is triggered by sensing the current reversal in a current path of the second subgroup of pixels. 39. The driving method as recited in claim 36, wherein the first subgroup of pixels are snapped to the intermediate voltage level after the decoupling from the inductive storage element. 40. The driving method as recited in claim 36, wherein the first subgroup of pixels are kept in a high-impedance state after the decoupling from the inductive storage element. 41. The driving method as recited in claim 36, wherem the second subgroup of pixels are snapped to the first or second voltage level after the decoupling from the inductive storage element. 42. The driving method as recited in claim 36, wherein the second subgroup of pixels are kept in a high-impedance state after the decoupling from the inductive storage element.

Inventors: KUIJK MAARTEN, STIENS JOHAN, KUIJK, MAARTEN, STIENS, JOHAN
Applicants: ROSE RESEARCH L L C, ROSE RESEARCH, L.L.C.
Application year: 1999
Main classification: G09G
IPC codes: G02F1, G09G3