Ferroelectric memory device

Abstract: The semiconductor memory device of this invention includes a capacitor, a first transistor, and a second transistor, wherein the capacitor includes a first electrode, a second electrode opposing the first electrode, and a ferroelectric film sandwiched by the first and second electrodes, and stores and holds binary information utilizing a polarizing state of the ferroelectric film, the first transistor includes a first electrode, a second electrode, and a gate electrode, the second electrode being connected to the first electrode of the capacitor, and the second transistor includes a first electrode, a second electrode, and a gate electrode, the first electrode being connected to the second electrode of the capacitor.

Description: 1. FIELD OF THE INVENTION: The present invention relates to a nonvolatile semiconductor memory device for storing and holding information utilizing a polarization state of a ferroelectric film sandwiched between electrodes of a capacitor. 2. DESCRIPTION OF THE RELATED ART: A semiconductor memory device using a ferroelectric (hereinafter, referred to as a ferroelectric memory device) is a nonvolatile memory which stores data utilizing the polarization direction of the ferroelectric. Figure 6 shows an exemplary conventional nonvolatile semiconductor memory device using this type of ferroelectric. See, for example, T. Sumi et al., 1994 IEEE International Solid-State Circuits Conference, Digest of Technical Papers, pp. 268-269 The ferroelectric memory device shown in Figure 6 includes a plurality of memory cells MC each including a capacitor Cs and a MOS transistor Qc . The capacitor Cs has two opposing electrodes and a ferroelectric film sandwiched by the electrodes. One of the electrodes of the capacitor Cs is connected to one of a source electrode and a drain electrode of the MOS transistor Qc . The plurality of memory cells MC are arranged in row and column directions. A plurality of word lines WL 0 to WL 2m+1 are arranged to correspond to rows of the plurality of memory cells MC , so that each word line is connected to gate electrodes of the transistors Qc of the corresponding row of the memory cells MC . When any of the plurality of word lines WL 0 to WL 2m+1 is selected, the memory cells MC connected to the selected word line are put in a selected state. A plurality of bit lines BL 0 to BL n and a plurality of bit bar lines /BL 0 to /BL n are arranged to correspond to columns of the plurality of memory cells MC , so that each of the bit lines and bit bar lines is connected to the other of the source electrode and the drain electrode of each MOS transistor Qc of the corresponding column of the memory cells MC . A plurality of plate lines PL 0 to PL m extending in the row direction are arranged every other row of the plurality of memory cells MC , so that each plate line is connected to the other electrode of each of the capacitors Cs of the corresponding two rows of the memory cells MC which is not connected to the corresponding transistor Qc (hereinafter, such an electrode of the capacitor Cs is referred to as a plate electrode). A plurality of MOS transistors T 0 to T 2m+1 are arranged to correspond to the plurality of word lines WL 0 to WL 2m+1 so that gate electrodes of the plurality of MOS transistors T 0 to T 2m+1 are connected to the corresponding word lines WL 0 to WL 2m+1 , source electrodes thereof are connected to the corresponding plate lines PL 0 to PL m , and drain electrodes thereof are connected to a drive line DL . A plate driving signal generation circuit 1 supplies a plate driving signal to the drive line DL . The operation of the conventional ferroelectric memory device having the above configuration shown in Figure 6 will be described with reference to Figure 7 . Figure 7 is a timing chart of the ferroelectric memory device shown in Figure 6 . In a standby state before a word line (e.g., the word line WL 0 ) rises to a selected level (high level), the bit lines BL 0 to BL n , the bit bar lines /BL 0 to /BL n , and the drive line DL are in a grounding potential level. When the word line WL 0 rises to a high level, the memory cells MC connected to the word line WL 0 turn to a selected state, and the transistor T 0 is turned on, to allow the plate line PL 0 to be connected with the drive line DL . The plate driving signal then becomes a high level to provide a plate driving voltage Vp1, which is applied to the plate line PL 0 . As a result, information stored in the memory cells MC connected to this plate line is read to the bit lines BL 0 to BL n . The bit bar lines /BL 0 to /BL n , which are paired with the bit lines BL 0 to BL n , respectively, are selectively connected to reference cells (not shown) to generate a reference voltage level. The reference voltage is set at a potential just in the middle of potentials at the bit line generated when the information read from the memory cell MC is "1" and when it is "0". This setting is achieved by adjusting the size of a capacitor of each reference cell. A voltage difference between the paired ones of the bit lines BL 0 to BL n and the bit bar lines /BL 0 to /BL n is sense-amplified, to read outside the information stored in the memory cells in the selected state. Thereafter, the plate driving signal becomes a low level to provide a grounding potential, which is applied to the plate line PL 0 . This allows information to be written again in the memory cells in the selected state. In such a ferroelectric memory device, the ferroelectric film of the capacitor Cs of each memory cell MC is provided with positive and negative induced polarization, to store information in the memory cell MC . The stored information is read by detecting the state of the induced polarization. For this detection, it is required to supply a predetermined potential, such as the potential Vp1, to the corresponding plate line as described above. Since the capacitor Cs is made of a ferroelectric, the capacitance value thereof tends to be greater than that of a conventional DRAM. Moreover, the plate lines are generally made of precious metal, such as Au, Pt, and Ru, for the conformity with the dielectric of the capacitors. It is difficult to thicken such precious metal since the processability thereof is a problem. An attempt to increase the width of the interconnects (to compensate the poor thickness) will be disadvantageous for realizing miniaturization and thereby high-density construction. For these reasons, it is difficult to reduce the resistance of the interconnects. This increases the time constant of the plate lines, and thus increases the time required for driving the plate lines. As a result, high-speed operation of the conventional ferroelectric memory device is difficult. Moreover, in the conventional ferroelectric memory device, since the plate lines are charged and discharged, power consumption increases. Thus, as described above, the conventional ferroelectric memory device has a construction in which the plate lines are driven at a predetermined voltage for each access. This requires a long time for driving the plate lines, making it difficult to realize high-speed operation. Moreover, power consumption increases for charging and discharging of the plate lines. US 5 309 391 discloses a two transistor, single capacitor ferroelectric memory cell in which a stepped voltage is applied to the drive line for writing polarization states into the capacitor. US 5 357 460 discloses a semiconductor memory device with unit memory cells each with two transistors and a capacitor. SUMMARY OF THE INVENTION According to the present invention there is provided a semiconductor memory device as claimed in claim 1. Preferably, the column selection plate driving circuit includes a main drive line, a plate driving signal generation circuit for supplying a plate driving signal to the main drive line, and a plurality of MOS transistors, gates of the plurality of MOS transistors are respectively connected to a plurality of address decode signal lines, first electrodes of the plurality of MOS transistors are connected to the main drive line, and second electrodes of the plurality of MOS transistors are respectively connected to the plurality of column selection plate driving lines. A preferred embodiment of the semiconductor memory device of this invention includes: a plurality of memory cells arranged in row and column directions, a plurality of word lines extending in the row direction, a plurality of bit lines extending in the column direction, a plurality of bit bar lines extending in the column direction, a plurality of column selection plate driving lines extending in the column direction, and a plurality of second transistors, wherein each of the plurality of memory cells includes a capacitor and a first transistor, the capacitor includes a first electrode, a second electrode opposing the first electrode, and a ferroelectric film sandwiched by the first and second electrodes, and stores and holds binary information utilizing a polarizing state of the ferroelectric film, the first transistor includes a first electrode, a second electrode, and a gate electrode, each of the plurality of second transistors includes a first electrode, a second electrode, and a gate electrode, the first electrode of the first transistor is connected to one of the plurality of bit lines and the plurality of bit bar lines, the second electrode of the first transistor is connected to the first electrode of the capacitor, the plurality of memory cells are classified into a plurality of groups, the second electrodes of the capacitors of a plurality of memory cells of a group in a first row are connected to the first electrode of one of the plurality of second transistors via a plate line, the second electrode of the one of the plurality of second transistors in the first row is connected to one of the plurality of column selection plate driving lines, the gate electrode of the one of the plurality of second transistors in the first row is connected to one of the plurality of word lines, the gate electrode of the first transistor in the first row is connected to the word line to which the second transistor in the first row is connected, the second electrodes of the capacitors of a plurality of memory cells of a group in a second row are connected to the first electrode of one of the plurality of second transistors via a plate line, the second electrode of the one of the plurality of second transistors in the second row is connected to the one of the plurality of column selection plate driving lines, the gate electrode of the one of the plurality of second transistors in the second row is connected to one of the plurality of word lines, and the gate electrode of the first transistor in the second row is connected to the word line to which the second transistor in the second row is connected. Thus, the invention described herein makes possible the advantage of providing a semiconductor memory device capable of operating at high speed with reduced power consumption. In order that the present invention be more readily understood, specific embodiments thereof will now be described with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS Figure 1 is a circuit diagram of a ferroelectric memory device of Example 1 according to the present invention; Figures 2A and 2B are timing charts of the ferroelectric memory device of Example 1; Figure 3 is a circuit diagram of a ferroelectric memory device of Example 2 according to the present invention; Figure 4 is a timing chart of the ferroelectric memory device of Example 2; Figure 5 is a circuit diagram of a ferroelectric memory device of Example 3 according to the present invention; Figure 6 is a conventional ferroelectric memory device; Figure 7 is a timing chart of a conventional ferroelectric memory device of Figure 6 ; and Figure 8 is a graph showing hysterisis characteristics of applied electric field vs. polarization of a ferroelectric memory cell. DESCRIPTION OF THE PREFERRED EMBODIMENT Figure 1 is a circuit diagram of a ferroelectric memory device 100 of Example 1. Figures 2A and 2B are timing charts of the ferroelectric memory device 100 shown in Figure 1 . The ferroelectric memory device 100 shown in Figure 1 includes a plurality of memory cells MC arranged in row and column directions. Each of the memory cells MC has a capacitor Cs , a first transistor Qa , and a second transistor Qd . The capacitor Cs includes a first electrode and a second electrode opposing the first electrode, with a ferroelectric film sandwiched by the first and second electrodes. The capacitor Cs stores and holds binary information utilizing the polarization state of the ferroelectric film. Hereinafter, the second electrode of the capacitor Cs is also referred to as a plate electrode. The first transistor Qa includes source and drain electrodes (one of these electrodes is also referred to as the first electrode, while the other is also referred to as the second electrode), and a gate electrode. The second electrode of the first transistor Qa is connected to the first electrode of the capacitor Cs . The second transistor Qd includes source and drain electrodes (one of these electrodes is also referred to as the first electrode, while the other is also referred to as the second electrode), and a gate electrode. The first electrode of the second transistor Qd is connected to the second electrode of the capacitor Cs . A plurality of word lines WL 0 , WL 1 , ... are arranged to correspond to rows of the plurality of memory cells MC , so that each word line is connected to gate electrodes of the transistors Qa and Qd of the corresponding row of the memory cells MC . A plurality of bit lines BL 0 , BL 1 , ... and a plurality of bit bar lines /BL 0 , /BL 1 , ... are arranged to correspond to columns of the plurality of memory cells MC , so that each of the bit lines and bit bar lines is connected to the first electrode (one of the source electrode and the drain electrode) of each of the transistors Qa of the corresponding column of the memory cells MC . The second electrode (one of the source electrode and the drain electrode) of the transistor Qd of each of the columns of the memory cells MC is connected to corresponding one of a plurality of column selection plate driving lines CD 0 , CD 1 , .... Herein, in a memory cell located in the i-th row and the j-th column, the plate electrode of the capacitor Cs as a node is referred to as PL(i,j). The ferroelectric memory device 100 shown in Figure 1 further includes: an address buffer 2 which receives an address signal generated externally (or internally); a row decoder 3 and a column decoder 4 which receive a signal output from the address buffer 2 ; a word line driving circuit 5 which receives an address decode signal output from the row decoder 3 and drives the word lines WL 0 , WL 1 , ...; and a column selection plate driving circuit 6 which receives a column address decode signal output from the column decoder 4 and drives the column selection plate driving lines CD 0 , CD 1 , .... The column selection plate driving lines CD 0 , CD 1 , ... are made of polysilicon interconnects or normal metal interconnects (such as aluminum interconnects). The operation of the ferroelectric memory device 100 shown in Figure 1 will be described with reference to Figure 2A . In a standby state before a word line rises to a selected level (high level), the bit lines BL 0 , BL 1 , ..., the bit bar lines /BL 0 , /BL 1 , ..., and the column selection plate driving lines CD 0 , CD 1 , ... are in a grounding potential level. When a predetermined word line (e.g., a word line WL i ) rises to a selected level in response to the external address signal, the transistors Qa of the memory cells MC connected to the word line WL i are turned on, to allow the first electrode of each of the capacitors Cs of the memory cells MC to be put in the grounding potential level which is the same as the potential level of the bit lines or the bit bar lines. When the transistors Qd of the memory cells MC connected to the word line WL i are turned on, the column selection plate driving lines CD 0 , CD 1 (not shown), ... are connected to the plate electrodes PL(i,0), PL(i,1) (not shown), ..., respectively. Under the above state, when a predetermined column selection plate driving line (e.g., the column selection plate driving line CD j ) becomes a selected level in response to an external column address input, only the plate electrode PL(i,j) is put in a high level Vp1, while the other plate electrodes of the same row remain in the grounding potential level. As a result, only information stored in the memory cell MC in the i-th row and the j-th column is read to the bit line BL j . More specifically, referring to Figure 8 , by applying a negative electric field -E max between the bit line BL j and the plate electrode PL(i,j) when the transistor Qa is in the "on" state, a charge corresponding to Pmax+Pr can be read to the bit line BL j when the stored data is "1" held at point c in the hysteresis characteristics, while a charge corresponding to Pmax-Pr can be read from when the stored data is "0" held at point a . The bit bar line /BL j which is paired with the bit line BL j is put in a reference voltage level by selecting a reference cell (not shown). Information stored in the memory cell in the selected state can be read outside by sense-amplifying a potential difference between the pair of the bit line BL j and the bit bar line /BL j . In any non-selected memory cell which is not in the j-th column, no potential difference is generated between the pair of the bit line and the bit bar line. Accordingly, information stored in such a memory cell is not sense-amplified to be read outside. In other words, only the memory cell MC located in the i-th row and the j-th column is sense-amplified. Thereafter, the signal at the column selection plate driving line CD j becomes the grounding potential level, and thus the voltage at the plate electrode PL(i,j) becomes the grounding potential. This allows information to be written again in the memory cell in the selected state. In the timing chart shown in Figure 2A , a read and a rewrite are completed by one pulse of the column selection plate driving signal. Alternatively, the ferroelectric memory device 100 may be operated according to the timing chart shown in Figure 2B . In the timing chart shown in Figure 2B , while the word line is in the selected level, a read is completed by a pulse P1 of the column selection plate driving signal and then a rewrite is ensured by a subsequent pulse P2 of the column selection plate driving signal. The rewrite as used herein refers to an operation as follows. Referring to Figure 8 , in the read operation described above, the state at point c has been changed to the state at point a , resulting in breaking the data at point c . Thus, a positive electric field Emax is applied to the ferroelectric film of the capacitor, to resume the state at point c . As for any non-selected memory cell MC which is not in the i-th row, since the capacitor Cs of the memory cells MC is isolated from the bit line (or the bit bar line) by the transistors Qa and Qd , the voltage between the electrodes of the capacitor Cs does not vary, irrespective of whether or not the voltage Vp1 is applied to the column plate driving line CD x (x is an integer excluding i), preventing the polarization information from being broken. As for any memory cell MC which is connected to the selected word line WL i and connected to the column selection plate driving lines CD in a non-selected level, no sense-amplification is performed, preventing the polarization information from being broken. In the ferroelectric memory device 100 shown in Figure 1 , the column selection plate driving circuit 6 is only required to drive the plate electrode PL(i,j) of a single memory cell MC for each access operation, and thus the capacitance value and resistance value thereof are small. This reduces the time required to drive the plate electrode and thus realizes high-speed operation and low power consumption. Moreover, since only information stored in a single memory cell MC is sense-amplified, the current consumption in the sense-amplification is also greatly reduced. (Example 2) Figure 3 is a circuit diagram of a ferroelectric emory device 200 of Example 2. The ferroelectric memory evice 200 includes a plurality of memory cells MC, a lurality of word lines WL 0 , WL 1 , ..., a plurality of bit lines BL 0 , BL 1 , ..., a plurality of bit bar lines /BL 0 , /BL 1 , ..., and a column selection plate driving circuit 6' . The construction of the ferroelectric memory device 200 shown in Figure 3 is the same as that of the ferroelectric memory device 100 except for the column selection plate driving circuit 6' . In the ferroelectric memory device 200 , the same components as those of the ferroelectric memory device 100 are denoted by the same reference numerals, and the description thereof is basically omitted. The column selection plate driving circuit 6' includes a main drive line 8 , a plate driving signal generation circuit 7 which outputs a plate driving signal to the main drive line 8 , and a plurality of MOS transistors QC 0 , ... QC j , .... Gates of the plurality of MOS transistors QC 0 , ... QC j , .... are connected to address decode signal lines AD 0 , ... , AD j , ... connected to the column decoder 4, respectively. Drains or sources of the plurality of MOS transistors QC 0 , ... QC j , ... are commonly connected to the main drive line 8 . The others of the drains and sources of the plurality of MOS transistors QC 0 , ... QC j , ... are connected to the column selection plate driving lines CD 0 , ..., CD j , ..., respectively. Hereinbelow, the operation of the ferroelectric memory device 200 will be described with reference to Figure 4 . Figure 4 is a timing chart of the ferroelectric memory device 200 . In a standby state before a word line rises to a selected level (high level), the bit lines BL 0 , BL 1 , ..., the bit bar lines /BL 0 , /BL 1 , ..., and the column selection plate driving lines CD 0 , CD 1 , ... are in a grounding potential level. When an external row address signal is input into the ferroelectric memory device 200 , a word line (e.g., the word line WL i ) becomes a selected level in response to the row address signal. When the word line WL becomes a selected level, the transistors Qa of the memory cells MC connected to the selected word line WL are turned on, to allow the first electrode of each of the capacitors Cs of the memory cells MC to be put in the grounding potential level which is the same as the potential level of the bit lines or the bit bar lines. The transistors Qd of the memory cells MC connected to the selected word line WL are also turned on, to allow the second electrode of each of the capacitors Cs to be connected to the corresponding column selection plate driving line CD . The plate driving signal generation circuit 7 outputs a main drive signal MDL (a high voltage Vp1) as a plate driving signal, to the main drive line 8 . The column decoder 4 outputs address decode signals ADS 0 , ..., ADS j , ... to the column selection plate driving circuit 6' . The column selection plate driving circuit 6' selects at least one column selection plate driving line CD based on the address decode signals ADS 0 , ..., ADS j , .... The main drive signal MDL is then supplied to the selected column selection plate driving line CD . For example, when only the address decode signal ADS j is in a certain voltage level which is different from others, only the column selection plate driving signal line CD j is at the Vp1 level. This turns only the plate electrode PL(i,j) to the Vp1 level, while the other plate electrodes remain in the high impedance state. As a result, as in Example 1 described above, only information stored in the memory cell MC in the i-th row and the j-th column is read to the bit line BL j and sense-amplified. The sense-amplified information is then read outside. After the read operation, while the address decode signal AD j is still in the selected level, the main drive line 8 is returned to the grounding potential level. This turns again the column selection plate driving signal line CD j and the plate electrode PL(i,j) to the grounding potential level, to allow information to be written again in the memory cell in the selected state. (Example 3) Figure 5 is a circuit diagram of a ferroelectric emory device 300 of Example 3. The ferroelectric memory device 300 includes a plurality of memory cells MC , a plurality of word lines WL 0 , WL 1 , ..., a plurality of bit lines BL 0 , BL 1 , ..., a plurality of bit bar lines /BL 0 , /BL 1 , ..., and a column selection plate driving circuit 6" . In Example 3, the a-th to (a+j)-th columns are regarded as one unit. For example, the bit lines BL 0 to BL j and the bit bar lines /BL 0 to /BL j are regarded as one unit, while the bit lines BL j+1 to BL 2j+1 and the bit bar lines /BL j+1 to /BL 2j+1 are regarded as one unit. In a certain row, the first electrodes of the capacitors Cs of the memory cells MC which are in the 0-th to (0+j)-th rows are connected to the transistors Qa of the respective memory cells MC . In a certain row, the second electrodes of the capacitors Cs of the memory cells MC which are in the 0-th to (0+j)-th row are connected to one common transistor Qd via a certain plate line. In a certain row, the each gate electrode of the transistors Qa and Qd is connected to the word line WL . For example, the second electrodes of the capacitors Cs of the plurality of memory cells MC connected to the word line WL 0 and connected to the bit lines BL 0 to BL j are connected to the first electrode of the transistor Qd 0 via a certain plate line. The gate electrode of the transistor Qd 0 is connected to the word line WL 0 . The second electrodes of the capacitors Cs of the plurality of memory cells MC connected to the word line WL 1 and connected to the bit bar lines /BL 0 to /BL j are connected to the first electrode of the transistor Qd 1 via a certain plate line. The gate electrode of the transistor Qd 1 is connected to the word line WL 1 . The second electrodes of the capacitors Cs of the plurality of memory cells MC connected to the word line WL i and connected to the bit lines BL 0 to BL j are connected to the first electrode of the transistor Qd i via a certain plate line. The gate electrode of the transistor Qd i is connected to the word line WL i . The second electrodes of the transistors Qd 0 , ..., Qd i are connected to the common column selection plate driving line CD 0 . The first electrode as used herein is referred to as either one of the source and the drain of a transistor, while the second electrode as used herein is referred to as the other of the source and the drain. Although not shown in Figure 5 , the second electrodes of the capacitors Cs of the plurality of memory cells MC connected to the word lines WL i and connected to the bit lines BL j+1 to BL 2j+1 or the bit bar lines /BL j+1 to /BL 2j+1 are connected to the common column selection plate driving line CD 1 via the corresponding transistors. The column selection plate driving circuit 6" includes a main drive line 8 , a plate driving signal generation circuit 7 which outputs a plate driving signal to the main drive line 8 , and a plurality of MOS transistors QC 0 , ... QC j , .... Gates of the plurality of MOS transistors QC 0 , ... QC j , .... are connected to address decode signal lines AD 0 , ..., AD j , ... connected to the column decoder 4 , respectively. The first electrodes of the plurality of MOS transistors QC 0 , ... QC j are commonly connected to the main drive line 8 . The second electrodes of the plurality of MOS transistors QC 0 , ... QC j are commonly connected to the column selection plate driving line CD 0 . The first electrode as used herein is referred to as either one of the source and the drain of a transistor, while the second electrode as used herein is referred to as the other of the source and the drain. The common column selection plate driving line CD 0 is configured to transmit an output of the plate driving signal generation circuit 7 when any of the 0-th to j-th columns is selected in response to the address decode signal output from the column decoder 4 . In this example, address decode signals for the 0-th to j-th columns are input into gates of the transistors Qc 0 to Qc j , respectively. With the above construction, the number of the transistors Qd required in the ferroelectric memory device can be reduced to 1/(j+1). This reduces the area of the memory cells MC and thus reduces the production cost of the ferroelectric memory device. Thus, in the semiconductor memory device according to the present invention, the plate of the memory cells is divided into sections in row and column directions. This makes it possible to select and operate only one memory cell among the plurality of memory cells by a single access operation of the semiconductor memory device. As a result, the plate driving time can be reduced, compared with the conventional semiconductor memory device, and thus high-speed operation of the memory cells is possible. Additionally, in the semiconductor memory device according to the present invention, power consumption can be reduced.

Claims: A semiconductor memory device (100) comprising at least one memory cell (MC), wherein the or each memory cell (MC) comprises a capacitor (Cs), a first transistor (Qa), and a second transistor (Qd), wherein the capacitor (Cs) includes a first electrode, a second electrode opposing the first electrode, and a ferroelectric film sandwiched by the first and second electrodes, wherein said capacitor stores and holds binary information utilizing a polarizing state of the ferroelectric film, the first transistor (Qa) includes a first electrode, a second electrode, and a gate electrode, the second electrode being connected to the first electrode of the capacitor (Cs), and the second transistor (Qd) includes a first electrode, a second electrode, and a gate electrode, the first electrode being connected to the second electrode of the capacitor (Cs), characterised in that the memory cell (MC) further comprises a word line (WL j ), a bit line (BL j ), a bit bar line (/BL j ), and a plurality of column selection plate driving lines (CD 0 , CD 1 ...), wherein the first electrode of the first transistor (Qa) is connected to one of the bit line (BL j ) and the bit bar line (/BL j ), the gate electrode of the first transistor (Qa) is connected to the word line (WL j ), the second electrode of the second transistor (Qd) is connected to one of the plurality of column selection plate driving lines (CD 0 , CD 1 , ...), and the gate electrode of the second transistor (Qd) is connected to the word line (WL j ), the cell (MC) further comprising a column selection plate driving circuit for selecting one of the plurality of column selection plate driving lines based on a column address decode signal. A semiconductor memory device according to claim 1, wherein the column selection plate driving circuit includes a main drive line, a plate driving signal generation circuit for supplying a plate driving signal to the main drive line, and a plurality of MOS transistors, gates of the plurality of MOS transistors are respectively connected to a plurality of address decode signal lines, first electrodes of the plurality of MOS transistors are connected to the main drive line, and second electrodes of the plurality of MOS transistors are respectively connected to the plurality of column selection plate driving lines. A semiconductor memory device according to claim 1, comprising: a plurality of memory cells (MC) arranged in rows and columns, a plurality of word lines extending in the direction of the rows, a plurality of bit lines extending in the direction of the columns, a plurality of bit bar lines extending in the column direction, a plurality of column selection plate driving lines extending in the column direction, and a plurality of second transistors, wherein each of the plurality of memory cells (MC) includes a capacitor (Cs) and a first transistor (Qa), the plurality of memory cells (MC) are classified into a plurality of groups, the second electrodes of the capacitors (Cs) of a plurality of memory cells of a group in a first row are connected to the first electrode of one of the plurality of second transistors via a plate line, the second electrode of the one of the plurality of second transistors (Qd) in the first row is connected to one of the plurality of column selection plate driving lines, the gate electrode of the one of the plurality of second transistors in the first row is connected to one of the plurality of word lines (WL j ), the gate electrode of the first transistor (Qa) in the first row is connected to the word line to which the second transistor (Qd) in the first row is connected, the second electrodes of the capacitors (Cs) of a plurality of memory cells (MC) of a group in a second row are connected to the first electrode of one of the plurality of second transistors via a plate line, the second electrode of the one of the plurality of second transistors in the second row is connected to the one of the plurality of column selection plate driving lines (CD 0 , CD 1 , ...), the gate electrode of the one of the plurality of second transistors in the second row is connected to one of the plurality of word lines, and the gate electrode of the first transistor (Qa) in the second row is connected to the word line to which the second transistor in the second row is connected.

Inventors: TAKATA HIDEKAZU, TAKATA, HIDEKAZU
Applicants: SHARP KK, SHARP KABUSHIKI KAISHA
Application year: 1999
Main classification: G11C11
IPC codes: G11C11, G11C14