OPTICAL COMMUNICATIONS NETWORK

Abstract: An optical regenerator, for example at a node in an optical communications network, uses a free-running bit-asynchronous local clock source. An incoming packet may be used to gate the clock source. In some implementations, a number of gates are used with different delays on the control input, and the gate giving a correctly regenerated output is selected. In alternative embodiments, a control loop is used to adjust the phase of control signals applied to a gate.

Description: OPTICAL COMMUNICATIONS NETWORK BACKGROUND TO THE INVENTION The present invention relates to an optical communications network, and in particular to the regeneration of optical packets carried on such a network. It is well known that optical fibre has a huge potential information-carrying capacity. For example, by utilising the entire gain bandwidth of erbium-doped optical amplifiers, a single fibre could carry more than 2 Tbit/s. However in the majority of telecommunications systems in commercial use currently, the information is carried over fibre in the form of an optical signal at a single wavelength. The data transmission bandwidth of the fibre is therefore limited by the electrical bandwidth of the transmitter and receiver, and this means that only a tiny fraction (a maximum of about 1 %) of the potential bandwidth-carrying capacity of the fibre is being usefully exploited. There is therefore much interest currently in developing methods for increasing the transmission rate for point-to- point fibre links. One method is wavelength-division multiplexing (WDM), in which several data channels, at different wavelengths, are carried simultaneously on the same fibre. An alternative method for increasing the rate of information that can be carried on fibre is to use optical time-division multiplexing (OTDM) in which several data channels are multiplexed in the form of bit-interleaved return-to-zero (RZ) optical pulse trains. The WDM approach to photonic networking has some very attractive advantages: in addition to the relative simplicity and commercial availability of the devices needed, WDM networks can be created in a wide variety of architectures with great flexibility (the main restriction being merely that any pair of photonic transmission paths cannot use the same wavelength on a shared fibre link). An advantage of WDM networks is that they can, in principle, support 'signal transparency', i.e. data signals can be carried using any modulation format. However, this implies that, in effect, WDM photonic networks are based on 'analogue' transmission. As a result it is not possible for digital signal regeneration techinques in the optical domain, to be used. The inability to perform signal regeneration in the optical domain leads to practical scaling limitations for WDM networks due to noise accumulation from optical amplifiers, crosstalk and nonlinearit. These factors restrict the number of network switching nodes through which signals can pass without fatal degradation. Currently, in reported laboratory experiments the maximum number of WDM switching nodes through which , a signal can pass without regeneration is limited to around 10, which is a significant restriction in architecture and scalability. A feasible, though costly, solution currently being advocated by some equipment vendors is to sacrifice transparency, standardise the transmission format, and regenerate each wavelength channel individually at the outputs of WDM cross-connects. In effect, this is a hybrid arrangement using analogue switching together with channel-by-channel digital regeneration. In the OTDM approach to photonic networking, the signals are carried in 'digital' format in the form of RZ optical pulses, allowing the use of digital signal regeneration techniques in the optical domain such as 3R (Re-amplify, Re-time and Re-shape) regeneration [Lucek J K and Smith K.Optics Letters, 18, 1226-28 (1993)] or soliton-control techniques [ Ellis A D, Widdowson T, Electronics Letters, 31 , 1 171-72 (1995)]. These techniques can maintain the integrity of the signals as they pass through a very large number of nodes. For example, Ellis and Widdowson [ Ellis A D, Widdowson T, Electronics Letters, 31 , 1171-72 (1995)] have made a laboratory demonstration of error-free transmission of signals through an OTDM network consisting of 690 nodes in concatenation. Despite this impressive potential for scalability, however, the OTDM approach to photonic networking suffers from severe restrictions in the network architecture that can be used. This results from the need to maintain proper bit-level synchronism between all the signal sources, demultiplexers and channel add/drop multiplexers throughout the network. In complex architectures, such as one involving the merging of signal streams emanating from several widely-separated sources, fluctuations in the arrival time of signals (due to environmental effects acting on the fibres such as temperature change and mechanical strain) cannot be adequately controlled or compensated in a continuous uninterrupted fashion. This is because of the restricted range of variable optical delay lines, the limited frequency response of control systems due to the physical time of flight of signals over extended distances, and also insufficient degrees of freedom. According to a first aspect of the present invention, there is provided a method of operating a node in an optical communications network including a) receiving at the node an optical packet; and b) generating from the said optical packet received at the said node a regenerated optical packet having a phase determined by a local bit-level clock source and independent of the bit-level phase of the said packet received at the node. Throughout this document, the term 'packet' is used to mean a fixed- length or variable-length string of bits which may be routed through a network in a variety of different ways, including self-routing, store-and-forward packet routing, scheduled switched routing and circuit switching The present invention provides a new approach to operating an optical communications network which for the first time makes it possible for an optical packet network to be scaled almost without limit. This is achieved by carrying out regeneration of optical packets in a manner which is asynchronous at the bit-level relative to the packet source. This then allows digital signal regeneration to be carried out, facilitating the transmission of packets over large distances, without the extent and architecture of the network being constrained by the need to transmit a global bit-leve timing signal. Preferably the step of generating a regenerated optical packet includes gating, using the received optical packet, an optical clock signal from the local clock source. Preferably this includes passing the optical clock signal through each of a plurality of gate means; applying the received optical packet as a control signal to each of the plurality of gate means with different delays of a fraction of a bit period relative to the optical clock signal input to the gate means; and selecting the output of one of the plurality of gate means to provide the regenerated optical packet. Preferaby the difference in delays is equal to T/k where T is the bit period and k is the number of optical gate means. Preferably the width W of the gate window is not less than T/ k and not more than T, where T is the bit period and k is the number of optical gates. Alternatively, as further described below, a single gate means may be used in conjuction with means to shift the phase of the incoming packet to match that of the local free-running optical clock. It is particularly advantageous to use a free-running local optical clock which is gated by the incoming packet. The use of a free-running optical clock, as opposed to one which is phase-locked to an incoming signal, allows the source to be a high qualtiy device such as a passively mode-locked laser. A further advantage is that the clock may be used to control further optical processing devices at the local node in order, for example, to process header data carried with the packet. It is found to be particularly effective to use a plurality of optical gates which are gated by the optical packet with different respective delays. The delay in question is that of the optical packet relative to the signal from the optical clock source. In practice the different relative delays may be achieved by applying different delays to the optical clock signal, or applying different delays to the optical packet. By using a number of gates in this way, and selecting one of their outputs, it is possible to recover an appropriately regenerated optical signal whatever the phase of the incoming optical packet. The optical gate means may comprise a number of distinct physical devices, such as those described in further detail below. Alternatively the plurality of optical gate means might comprise a single device arranged to gate a plurality of distinct optical signals distinguished, e.g. by their polarisation or wavelength, and references in the description and claims to a number of gate means are to be construed accordingly. Preferably the method includes making a measurement of a parameter of an optical signal output from the gate means, and selecting the output of one of the plurality of gates to provide the regenerated optical packet depending on the results of the said measurement. The parameter may be a measure of the total energy of the output signal, and the selection may be made by comparing the energies of the signals from different optical gate means. Other parameters may also be used to make the selection. For example, the bit error level may be measured, and the output selected which has the minimum bit error level. According to a second aspect of the present invention, there is provided method of operating a communications network comprising a plurality nodes interconnected by an optical transmission medium, the method including: transmitting an optical packet and at a network node, receiving the said packet and generating from the said packet a regenerated optical packet having a phase determined by a local bit-level optical clock source and independent of the bit-level phase of the said packet received at the network node. According to a third aspect of the present invention, there is provided a regenerator for optical packets comprising: an input for receiving an optical packet; a local bit-level optical clock source comprising a free-running local oscillator; means for generating from the optical packet and from a clock signal from the local optical clock source a regenerated optical packet independent in phase from the optical packet received at the input. BRIEF DESCRIPTION OF DRAWINGS Systems embodying the present invention will now be described in further detail, by way of example only, and will be contrasted with the prior art, with reference to the accompanying drawings, in which: Figure 1 : shows the basic concept for 3R regeneration of a digital data stream consisting of a RZ pulse train encoded by on-off modulation Figure 2: shows the method of 3R regeneration used for OTDM systems in which the bit stream is continuous Figure 3: shows a method of partial regeneration of optical packets Figure 4: a simplified outline diagram showing a generator of optical packets and a bit-asynchronous packet regenerator Figure 5: a dual-gate bit-asynchronous packet regenerator Figure 6: a sequence of timing diagrams that illustrate the operation of the dual- gate regenerator Figure 7: diagram showing the probability density function of the arrival time of the th data bit at the gates, relative to the clock signal input to gate G 1 Figure 8: a plot of the expression (1 2) bit-error probability against the phase angle θ , taking the values σ = 0.018:Tand W = 0.75T Figure 9: shows a plot of the bit-error probability B against the phase angle θ , calculated according to ( 1 2), using an ideal mechanism to select the output gate /, and taking WI T = 0.75 and σl T = 0.01 8 and 0.03 Figure 1 0 shows a plot of the maximum bit-error probability B according to ( 1 2), plotted versus the bit-arrival jitter σ, and taking WI T - 0.75 . Figure 1 1 : is a plot of the expected bit-error probability for a given packet, per regenerator passed, according to ( 1 5), plotted against the rms jitter σ , with WIT = 0.65, 0.75, 0.85. Figure 1 2: shows a plot of the bit-error probability B against the phase angle θ , calculated according to ( 1 8), taking WI T = 0.75 , σ/ 7 ' = 0.018 and σ c . / r = 0.001 Figure 1 3 shows a plot of the maximum value of the bit-error probability B for the phase angle θ anywhere in the range Q < θ < 2π, calculated according to ( 1 8), plotted versus σ c I T, with WI T = 0.75 and σl T = 0.001 , 0.01 8 and 0.03. Figure 14: Diagram of a bit-asynchronous quad-gate packet regenerator Figure 1 5: plot of bit-error probability according to ( 1 9) plotted against the phase angle θ , taking σ = 0.036rand W = 0.75T Figure 1 6: a plot of the bit-error probability B against the phase angle θ , calculated according to ( 1 2), using an ideal mechanism to select the output gate / (such as the strategy (20) executed by ideal circuits without systematic or random errors) and taking σ = 0.036rand W = 0.75T Figure 1 7: Plot of the bit-error probability B against the phase angle θ , calculated according to (21 ), and assuming that WI T = 0.75 , σl T = 0.036 and σ c I T = 0.001 and 0.052. " Figure 1 8: Plot of the maximum value of the bit-error probability B for any phase angle θ in the range 0 < θ < 2π, calculated according to (21 ), plotted versus WI T, with σlT = 0.036 , and σ c /T = 0.001 and 0.05." Figure 1 9: show values for the probability that a packet suffers 'slippage' (i.e. a time displacement greater than a specified acceptable limit L T), according to (22), plotted versus N, the number of regenerators passed, for various values of LT. Figure 20: shows a version of the two-gate regenerator which uses only one optical gating device to gate simultaneously two independent clock signals which are distinguishable by their different states of polarisation. Figure 21 : Outline diagram of a bit-asynchronous packet regenerator using a single gate to modulate the output of the local source. Figure 22: Example embodiment of the bit-asynchronous packet regenerator using a single gate to modulate the output of the local source. Figure 23: Example layout of a portion of a network comprising switching nodes containing routing switches (RS) and bit-asynchronous regenerators (AR), and links between the switching nodes containing bit-synchronous regenerators (SR). Figure 24: Outline diagram of an alternative arrangement of the bit-asynchronous packet regenerator using a single gate to modulate the output of the local source. Figure 25: A further example embodiment of the bit-asynchronous packet regenerator using a single gate to modulate the output of the local source Figure 26 shows a schematic of an optical packet network. DESCRIPTION OF EXAMPLES In an ultrafast optical packet network information is transported across a network in the form of fixed-length bursts (i.e. cells or fixed-length packets) of RZ optical pulses that are encoded with payload data and control information (such as the address of the packet destination). The network may constitute, for example, the core network of a national data/telephony network, or a local area network connecting a number of computing systems, or part of the fabric of a communications switch, or may provide the connection between processors in a multi processor computer. Examples of suitable topologies for such a network are described in the present applicant's co-pending European patent application 97307224.2, the contents of which are incorporated herein by reference. The use of logical (header), rather than physical, addressing facilitates massive scalability. Every transmission path in the network carries a continuous sequence of time slots, synchronised to a packet-level global clock, and each time slot accommodates at most one packet and an appropriate time guard band. This time guard band allows the transmission path to be switched for packet-by-packet routing and also allows continuous and endless synchronisation of the packet streams and network nodes to the packet-level global clock. Thus the packet time slots are synchronised throughout the network. However, a crucial aspect of our approach is that synchronism between packets at the (picosecond) bit-level is not required. Therefore the portion of the time slot that accommodates the packet can be conveniently defined to be several bit periods longer than the packet duration. This permits a certain amount of slop in the positioning of the packet within the time slot - in other words, the positioning of the packet within the time slot is not made with bit-level precision, and generally successive packets are not bit- synchronous. For such an asynchronous network to have the same near-infinite scalability as bit-synchronous OTDM networks, it is necessary to use a bit- asynchronous digital optical packet regenerator, as is further described below. Figure 1 shows a prior art approach to 3R regeneration of a digital data stream consisting of a RZ pulse train encoded by on-off modulation ('mark' represents a bit value 1 , 'space' represents 0) . The incoming data bits from a distant source are used to modulate a continuous train of high-quality RZ pulses produced by a local source, thus regenerating the original data. The presence of a 'mark' in the incoming data stream causes the gate to open for a time of the order of the bit period, allowing a single pulse from the local source to pass through. In this way the regenerated bits have the same pulse shape, spectral quality, amplitude and timing stability as the local source. The pulse repetition rate of this local source is the same as the bit rate of the incoming data. The key problem is designing such a regenerator is to ensure that the incoming data stream and the locally-generated pulses are maintained in synchronism. Figure 2 shows a prior art method used for OTDM systems in which the bit stream is continuous. A clock recovery circuit (which may be electronic or optical) derives a clock signal in synchronism with the incoming data bits, and this clock is used to synchronise the local pulse source. The method shown in Figure 2 is less suitable for systems in which the incoming data is not continuous, but is in the form of bursts or packets which are mutually bit-asynchronous. One reason is that in this case the clock recovery must be performed on a packet-by-packet basis, and therefore the lock-up time of the clock-recovery circuit must be a fraction of the packet duration in order not to waste bandwidth. However in ultrafast systems the need for a fast lock-up time tends to conflict with the requirement for a consistent high-quality pulse train throughout the duration of the packet. Another reason for the unsuitability of the approach shown in Figure 2 for ultrafast optical systems is that the best quality pulses are obtained from passively-mode-locked lasers and mode-locked ring lasers which are not readily synchronisable to an external clock. For some processes in optical packet networks, a self-synchronising approach has been proposed in which each incoming packet contains one or more synchronisation or 'marker' pulses which may be distinguishable by their wavelength, polarisation, amplitude, position, pulse spacing, etc. Figure 3 shows the approach in which a synchronisation pulse is extracted from an incoming packet and then passively replicated to produce a regular burst or pulse pattern. This replicated pulse train can then be used in the processes of demultiplexing, packet header-address recognition. It may also be used in the process of partial regeneration as shown in Figure 3 . In this case the data bits in the incoming packet are used to gate the train of replicated synchronisation pulses. However this is not full 3R regeneration: although amplitude and timing fluctuations are suppressed in the regenerated packet, the pulse shape and spectral quality are unchanged and therefore the pulse degradation suffered during transmission cannot be corrected. In the usual approach to 3R regeneration, illustrated in Figure 2, the local pulse source is forced into frequency and phase synchronism with the incoming data stream. In the embodiments of the present invention described below, a different approach is used, in which the local pulse source is continuously free-running, with the same nominal repetition frequency as the bit rate of the incoming data, but not necessarily in frequency and phase synchronism with the incoming packet. Instead the regenerated packet simply takes up the bit rate and phase of the free- running local source. This new approach allows the data packets to be bit- asynchronous, yet avoids the difficulty of recovering a high-quality clock signal on a packet-by-packet basis. Also since the local source of RZ pulses is continuously free-running, it can be a high-quality source such as a passively-mode-locked laser or a mode-locked ring laser. A further benefit is that the regenerated packets are all in precise bit synchronism with the local source of RZ pulses, and therefore this source may be used as the continuous and regular source of pulses that is essential for the various digital optical processing schemes, such as optical memory, registers, parity-counters, examples of which are described and claimed in the present applicant's copending applications number GB9726477.4, the contents of which are incorporated herein by reference. Such circuits find application in high-speed 'on-the-fly' processing of packets for routing, signalling, error detection, etc. Bit-asynchronous optical packet regeneration Figure 4 is a simplified outline diagram showing a generator of optical packets and a bit-asynchronous packet regenerator. The packet generator creates optical data packets each with a fixed bit rate of M s f s . As shown in Figure 4, this packet generator could consist of a source of optical RZ pulses at a repetition frequency f s Hz, whose output is modulated and multiplexed in a fashion similar to that used for OTDM (i.e. the output from the pulse source is split into .parallel paths which are individually encoded with data by on-off modulation at a rate f s bit/s and then recombined by bit-interleaving to form a packet of data bits with a composite rate of M s f s bit/s) . The source of pulses at repetition frequency f s could, as shown in Figure 4, consist of an electronic microwave oscillator at f s which drives an electrically-synchronised laser (such as a gain-switched laser or an actively-mode-locked laser) . Alternatively, it could be a continuously free-running optical pulse source, such as a passively-mode-locked laser or a mode-locked ring laser, whose nominal repetition frequency is set (for example, by tuning the laser cavity length). At the distant regenerator there is an independent continuously free-running source of RZ optical pulses at a repetition frequency M R f R Hz. This pulse source could, as shown in Figure 4, consist of an independent electronic microwave oscillator at a frequency f R which drives an electrically-synchronised laser (such as a gain-switched laser or an actively-mode-locked laser), followed by a passive splitter and bit-interleaver to produce the required composite frequency M R f R Hz. Alternatively the source could be a continuously free-running optical source of pulses at the rate f R followed by the x β splitter and interleaver, or indeed the free-running source could operate at the full repetition frequency M R f R Hz directly without the need for xM R multiplication. In any case, the bit rate M s f s of the packet produced by the packet generator and the repetition frequency M R f R of the pulse source in the regenerator must lie close to the same nominal value X I T , i.e. M s f s M R f R * XI T (1 ) where 7 " is the nominal bit period in the optical packet. (For example, = 10 ps , l/ r = 100 Gbit/s , Λ = 10 , X I M S T = 10 Gbit/s .) This novel approach in which the packet source and packet regenerator contain independent free-running pulse sources works because the optical data packets can be assumed to be of short duration, and therefore any phase slippage between the two pulse sources that occurs over the duration of a single packet is negligibly small. This can be illustrated by considering the question: how close must be the bit rate of the packet and the repetition frequency of the pulse source at the regenerator? At the inputs to the gate in the regenerator, the phase of the local clock pulses (input A in Figure 4) relative to the incoming packet data bits (control input C) as a function of time t is θ(t) = 2π(M R - M s f s )t + θ 0 , (2) where θ 0 is a constant offset. The change in θ(t) over the duration of a packet of length n bits is Aθ = θ(t + (n- X)T) - θ(t) = 2π(M R f R - M s f s )(n- X)T . (3) This corresponds to a time slippage AT in the local clock relative to the packet data bits, AT = AΘ- TI2π = (M R f R - M f s )(n- X)T 2 , (4) and this time slippage can be considered negligible if \ΔT\ « T . For example, with electrically-driven sources (as shown in Figure 4),/ = 10 GHz, M it = M R = XQ , T = 10 ps , l / r = 100 Gbit/s , « = 1000 , and f R - f s < 10 kHz (< 1 in 10 6 ) results in Δr < 10 T = 10 fs . This example shows that with realistic parameters, the time slippage over the duration of a packet can be negligibly small. Throughout the remainder of this description, it will be assumed that the bit rate of the incoming data packet and the repetition frequency of the pulse train at the A input to the gate can be considered to be exactly equal, and that the phase difference θ between them can be considered to be constant over the duration of the packet. Nevertheless, for any given packet, this phase difference is an arbitrary value in the range 0 < θ < 2π . Moreover, in a packet network, successive packets arriving at a regenerator may originate from different sources and accordingly their phases θ may be entirely uncorrelated. Therefore the bit- asynchronous packet regenerator must be designed to operate correctly on each packet independently, regardless of the phase difference θ . This is achieved in preferred embodiments of this invention by providing not just one gate (as shown in Figure 4) but two or more gates, each of which can correctly regenerate a packet for only a restricted range of θ , but which together span the complete range 0 < θ < 2π, and by providing means to select the output from one of the gates in each time slot so as to choose a correctly regenerated packet. This is best explained and illustrated by examples. The next sub-section describes the structure and operation of a bit-asynchronous packet regenerator containing two gates, and the succeeding sub-sections describes regenerators with four gates. Dual-gate bit-asynchronous optical packet regenerator Principle of operation Figure 5 shows a dual-gate bit-asynchronous packet regenerator. The data bits in the incoming packet are used to control the opening of two gates, G 1 and G2. A data bit with value 1 ('mark') causes each of the two gates to open for a fixed time duration (the gate window), otherwise the gates remain closed. It is preferable, though not essential, that the widths of the time window for gates G 1 and G2 are equal. The output from the local clock (a continuous free-running source of optical RZ pulses at a repetition frequency nominally equal to the packet bit rate X I T) is applied to the inputs of the two gates, one of these inputs being delayed relative to the other by an amount TI 2. Since the phase θ of the local clock pulses relative to the packet data bits has an arbitrary and unknown value in the range 0 < θ < 2π , it is necessary that the gate window widths are chosen so that, whatever the value of θ , the clock pulses will be correctly modulated by at least one of the two gates. In the case that the window widths for gates G 1 and G2 are equal, the window width W must therefore lie in the range T 12 < W < T . The lower limit ensures that at least one clock pulse will be modulated at any value of θ , whilst the upper limit comes from the requirement that no more than one clock pulse may pass though the gate whilst the window is open. These upper and lower limits on W apply strictly in the case that the incoming data pulses and local clock pulses are sufficiently narrow that, on the time scale of a bit period, they may be represented by delta impulses. When finite pulse widths are taken into account the acceptable range of window widths is somewhat narrower than TI 2 < W < T . At present, it will be assumed that the data pulses and local clock pulses are impulses, and for the remainder of this sub-section it is taken that W = 3T/ 4 for both gates. We should note at this point, with reference to Figure 5, that there is an alternative and equally valid configuration in which the TI 2 delay line is removed from the input port A of one of the gates, and placed instead at the control port C of one of the gates. The operation of the regenerator is very similar in this case, and the predicted performance described later is the same. Throughout the remainder of this description, the configuration will be assumed to be that in which the packet data bits are connected directly to the control ports of the gates, and the input ports have certain differential delays (as illustrated in Figure 5 for a dual- gate regenerator) . The optical gates may be implemented in different ways. For ultrafast operation, the gate could be a nonlinear optical device such as a fibre loop mirror (as described, for example, by Whitaker et al in Optics Letters, vol. 1 6, page 1 840 ( 1 991 )), in which case the gate width is defined by selecting suitable fibre lengths, dispersion and birefringence. Alternatively a suitable ultrafast gating device based on the nonlinearity in semiconductor optical amplifiers could be used (as described, for example, by Kang et al in the International Journal of High Speed Electronics and Systems, vol. 7, page 1 25 (1 996)). In this case the gate width may be determined by the positioning of the amplifier in a Sagnac interferometer loop arrangement, or the relative offset of two amplifiers in a Mach-Zehnder interferometer device. Another suitable ultrafast semiconductor-based device is the ultrafast nonlinear interferometer switch described by Hall and Rauschenbach (paper PD5, Proceedings of Conference on Optical Fiber Communication OFC'98, published by the Optical Society of America, February 1 998), which has been shown to operate at a speed of 100 Gbit/s. For operation at lower speeds an optoelectronic device such as an electroabsorption modulator could be used as the gate. In that case, the incoming packet data bits must first be received by a photodetector whose output is converted to a suitable short electrical pulse to drive the modulator, and the gate width is defined by the width and amplitude of this electrical pulse. In this case, for correct operation it is necessary that the photodetector and associated electronics can fully resolve the data bits, which limits the packet data rate. If a single optical gating device is used for the purpose of gating k distinct optical clock signals {k > 1 ) then, throughout the description and analysis in this work, this will be regarded as k optical gates. The clock signals may be distinguishable, for example, by virtue of their states of polarisation, wavelength or intensity. For example, Figure 20 shows a version of the two-gate regenerator which uses only one optical gating device to gate simultaneously two independent clock signals which are distinguishable by their different states of polarisation. Figure 6 shows a sequence of timing diagrams that illustrate the operation of the dual-gate regenerator. The packet data bits (an example sequence 1 1 101 is shown) arrive at the control ports of the gates G1 and G2, and each 'mark' causes the gates to open for a time 3T/ 4. The diagrams (i-iv) illustrate various values of θ , the phase of the local clock relative to the incoming packet data bits. It is convenient to write the gate width W and phase angle θ as normalised quantities, thus: W = WI T and θ = θl 2π . Diagram (i) illustrates the case 0 < θ ≤ W - 1 /2 , in which the outputs from both gates G 1 and G2 are clock pulses that have been correctly modulated by the incoming data bits. Diagram (ii) illustrates the case W - 1/ 2 < θ < 1 /2 , in which the output from gate G 1 (but not G2) are clock pulses that have been correctly modulated by the incoming data bits. Diagram (iii) illustrates the case 1 /2 ≤ Θ ≤ W , in which again the outputs from both gates G 1 and G2 are correctly modulated. Diagram (iv) illustrates the last possibility, W ≤ θ < X , in which the output from gates G2 (but not G 1 ) is correctly modulated. Returning to Figure 5, the components shown to the right-hand side of the two gates are used to attempt to select in each time slot whichever gate output gives a regenerated packet with the minimum of bit errors. One technique, shown in Figure 5, is to make the selection in each time slot on the basis of a comparison of the total optical energy emerging from each gate, integrated over the duration of the packet. If the phase angle θ is such that the output from a gate consists of correctly modulated clock pulses then the total optical energy measured at the output of the gate, integrated over the duration of the packet, will be maximum (in effect, it is a measure of the number of 'marks' appearing in the regenerated data packet) . However if θ is such that the clock pulses arrive at the gate at a time outside the gate window, then the energy transmitted by the gate will be zero or small. The circuit shown in Figure 5 therefore makes these energy measurements and the result of the comparison is used to set the optical switch S, (for example, an optoelectronic device such as a lithium niobate switch) which performs the physical selection. The detectors, D1 and D2, are followed by electronic integrators 11 and 12, each of which provide a voltage proportional to the energy of the regenerated packet emerging from gates G 1 and G2, respectively, in each time slot. The comparator C produces a digital output according to whether or not the signal from D 1 exceeds that from D2. The global packet-level clock signal, synchronised to the time guard band between packets, is used to reset the integrators and also to clock the D-type flip-flop DT. This ensures that the switch S changes over only during the guard band, so as to avoid corrupting a packet. Notice that the detectors, switch and associated electronics operate at the packet rate (not the data bit rate) with a response time on the order of the width of the time guard band (which may be on the time scale of ~ 1 ns). An alternative method of selecting the most appropriate gate output in each time slot may be to perform a bit-error measurement on the whole or part of the packet that emerges from each gate. For example, a test pattern could be incorporated as part of each packet, and this pattern would be received and any bit errors detected and counted in each time slot at the output of each gate. In a given time slot the output having zero or the least number of bit errors would be selected. The optical delays (labelled L and L + ATI 2 in Figure 5) between the outputs of the gates and the selection switch S are used to allow sufficient time for the circuitry and switch S to operate before the packets arrive at the switch. Typically the delay L will be slightly less than one time slot in duration. Optionally, as shown in Figure 5, the optical delay between the output of gate G 1 and the switch S may be made slightly longer (by an amount T 12 ) than the delay between the output of gate G2 and the switch. The purpose of doing this is to compensate for the delay of 772 at the input of gate G2, thus equalising the delay of both optical paths from the clock source to the output of the selector switch S. One benefit of doing this is that all the regenerated packets are then in precise bit synchronism with each other and with the local clock, and as mentioned earlier, the local clock may therefore be used as a continuous and regular source of pulses for use in subsequent digital optical processing stages. A further important benefit of equalising the delay in this way is to reduce the problem of 'packet slippage' in a large network, as described in section 3.4.3. There are two main causes of bit errors that may occur in the process of regenerating a packet using the bit-asynchronous regenerator. The first cause is jitter in the arrival time of the incoming packet data bits. It is well known that in high-speed optical transmission systems, jitter in the arrival time of pulses arises from effects such as amplified spontaneous emission noise, the soliton self- frequency shift arising from the Raman effect, soliton short-range interactions, and the complex interplay of these various processes. If the time of arrival of a data 'mark' at the regenerator fluctuates relative to the local clock pulse train, the time position of the gate window opened by that data bit is shifted accordingly. This increases the probability that a clock pulse may fall outside the gate window and so may fail to be transmitted correctly as a 'mark' in the regenerated packet. The second main cause of bit errors is errors in the process used to select the output from one of the gates in each time slot. For example, when the selection is made on the basis of a comparison of the output energy from the gates, noise in the energy measurement and comparator circuits can result in incorrect selection. In the next sub-section the bit-error probability arising from timing jitter is analysed in detail under the assumption that the gate selector is perfectly noise-free and has infinitesimal resolution. In the succeeding sub-section the effect of errors in the operation of a realistic gate selector is considered. Bit-error probability when using a perfect gate selector As explained above, the bit rate of the incoming data packet and the repetition frequency of the pulse train at the A input to the gate are assumed to be exactly equal, and the phase difference θ between them is taken to be constant over the duration of the packet. However, as explained above, the arrival time of an individual packet data bits is subject to fluctuations. Figure 7 shows the probability density function of the arrival time of the Λh data bit at the gates, relative to the clock signal input to gate G 1 . We have taken the arrival time to be a normally distributed random variable with standard deviation σ (usually referred to as the rms jitter) . The mean value of the distribution occurs θT/2π before a clock pulse. Purely for illustration, in Figure 7 the width of the probability density distribution has been exaggerated so that the various regions can be clearly seen (as we shall see later, the regenerator would normally be used in a regime in which the bit- arrival jitter σ is a much smaller fraction of the bit period 7) . If the actual arrival time of a the Λh data bit is within the unshaded region defined by t, — W < t < t j (where t t is the time of the Λh clock pulse) and if the bit is a 'mark', the gate window will open and allow the Λh clock pulse to be transmitted correctly thus regenerating the data 'mark'. If the arrival time of the Λh data bit falls outside this unshaded region, then the Λh clock pulse is not correctly modulated. The probability that the actual arrival time falls within the unshaded region is given by ( ψ (ψ - Wl f\ p(ψ) = Φ ■ - - Φ ψ (5) J v σ/7 σ iτ J with ψ = ψ λ , where ψ λ = θl 2π (6) and φ(z) = exp(-z 2 ! 2) l-J2π . (8) If the actual arrival time of a the Λh data bit is within the heavily shaded region defined by t < t,_, = t,- - T and if the bit is a 'mark', the gate window will open so as to allow the (z ' - l)thclock pulse to be transmitted, with the possibility of producing an error. The probability that the actual arrival time falls within the heavily shaded region is given by with ψ = ψ λ . Similarly, if the actual arrival time of a the Λh data bit is within the other heavily shaded region defined by t > t i+l - W = t t + T - W and if the bit is a 'mark', the gate window will open so as to allow the (i + l)th clock pulse to be transmitted, again with the possibility of producing an error. The probability that the actual arrival time falls within this region is given by with ψ = ψ x . At the gate G2, the clock pulses are arranged to arrive later in time by an amount TI 2. In this case the expressions for the probabilities p, q and r are given by (5), (9) and ( 10), but with ψ = ψ 2 where ψ 2 = (θl 2π + X I2) modi (1 1 ) For both gates, the bit error probability can be calculated by considering the various combinations of values of the /th data bit with its nearest neighbours, as presented in the table below (the small differences when j = X or n, where there are n bits in the packet, are neglected). This table assumes that 0 < ψ t < Wl T . ϋ ' - l)th th C/ + l)th Bit-error probability in the /th bit position at the data bit data bit data bit output from gate / 0 0 0 0 0 0 q(ψ,)l 0 0 {X -p(ψ,)} lo- bit-error probability for the output from gate / , conditional on the phase angle θ : B(ψ) = { X - p(ψ)[ { X - q(ψ) l 2][ X - r(ψ) l 2]} l 2 ( 1 2) * { l - p(ψ)} / 2 where ψ = ψ λ or ψ 2 as appropriate. Figure 8 is a plot of the expression ( 1 2) against the phase angle θ , taking as an example the values σ = 0.0187 ' and W = 0.75T for the jitter and gate window width, respectively. It can be seen that, with these parameter values, for any value of θ in the full range 0 < θ < 2π the bit-error probability for the output from at least one of the gates is less than 10 ~12 , and therefore this bit-error probability can be achieved continuously by selecting the output from one of the gates suitably in each time slot. In this description we take 10-' 2 as the target bit-error probability (or the equivalent probability of 10 " that a packet of 1000 bits will contain an error). There will now be described an analysis of the method of gate selection based on a comparison of the integrated energies of the packets emerging from each gate, as described in the preceding. As noted earlier, the total optical energy measured at the output of a gate, integrated over the duration of the packet, is in effect a measure of the number of 'marks' appearing in the regenerated data packet. Similar to the calculation of the bit error probability given above, the expected value of the optical energy measured at the output of the Λh gate can be calculated by considering the various combinations of values of the /th data bit with its nearest neighbours, as presented in the table below. The expected value of the optical energy measured at the output of the Λh ggaattee,, \(EE /) ,, iinntteeggrraatteedd oovveerr tthhee duration of the packet, is found by summing the probabilities in the table above: / F \ - p(ψ,) + q(ψ,) + r(ψ,) p(ψ, )q(ψ,) + p(ψ,y(ψ,) + q(ψ,Xψ, ) , PJψ,)qi.ψ,)r(ψ,) 2 4 8 Here (E,) is normalised to the value nw, where n is the number of bits in the original packet and w is the energy of a pulse representing a 'mark' (a single pulse representing a bit of value 1 ) in the output. Then an appropriate strategy for selecting the gate output in each packet time slot is: if (E,) = max {(E,),(E 2 )} then select gate . (14) It is assumed, for the remainder of this sub-section, that whatever mechanism is used for selecting the appropriate gate output in each time slot, its operation is ideal; e.g. the energy measurement and comparator circuits used to make a selection on the basis of ( 14) have no systematic errors, are perfectly noise-free and have infinitesimal resolution. Figure 9 shows a plot of the conditional bit-error probability B(θ) against the phase angle θ " calculated according to ( 1 2), using an ideal mechanism to select the output gate /, and assuming for example that W I T = 0.75 . It can be seen that in the case where the jitter is σ = 0.0187\ the —12 maximum value of B is 10 (as expected from the curves plotted in Figure 8). In the other case shown, where σlT takes the larger value 0.03, the conditonal bit- error probability B(θ) reaches a maximum value of 8 x 10 " * for certain values of the phase angle θ , but there are other ranges of θ in which _5 < 10 "12 . Figure 10 shows a plot of the maximum bit-error probability B that a packet may suffer, for any phase angle θ within the range 0 < θ< 2π . The results are plotted versus the bit-arrival jitter σ, again assuming for example WIT = 0.75. When a packet travels across a network it may pass through a sequence of regenerators. The phase angle θ differs from one regenerator to the next in a random fashion, because in this invention the local oscillators at the regenerators are free-running and their phases are uncorrelated. Therefore, at each regenerator that the packet encounters, θ is a continuous uniform random variable on the interval 0 ≤θ<2π, i.e. θllπ ~ U(0, X). We assume here that the rms jitter σ in the arrival time of the data bits is the same at each regenerator. It follows that the bit-error probability after passing through N regenerators is given by N(e) = N{e\θ)) , where e denotes a random variable that takes the value 1 when a bit error occurs and the value 0 otherwise, and denotes B(θ)t e bit-error probability, conditional on the phase angle θ, for a single regenerator. By inspection, it can be seen that is a periodic, symmetrical function of #that exercises two full periods on the interval 0 ≤θ<2π. Moreover \e\θ) is continuous and differentiable on the interval WI2T < Θl2π <(2WIT + l)/4 , which represents one half-period. Therefore the expected value \\e|#)) with θl 2π ~U[0,X] is identical to the expected value ((e|x)) with x ~ U[W I2T,(2W IT + X)I4], where (e\x) is given by (12). The expected value {x) = (4W IT + X)I8 and varx = 1/(12 -4 2 ) = 1/192. Now let Y = ln(el(x> + Δ) and perform a Taylor expansion: Y = ln<e|(x» + Δ - ln(e|(x» + ^ ln(e|<x)> + 1-^ ln<e x» + ■ ■ , ax 2! ax 3! or Taking expectations, 1 cf (?) = ln(e>-ln<e|(x»+-^^ T ln(e|( » (15) 384 dx since (Δ) = 0, \Δ/ = varx and \Δ = 0. TO evaluate (15) we use the following relations: and 2 l Figure 1 1 is a plot of the expected bit-error probability for a given packet, per regenerator passed, according to ( 1 5). The curves are plotted against the rms jitter σ , for various values of the gate window width W. For example, with W = 0.757 and σ = 0.0327 , the expected bit-error probability per regenerator — 15 — 1 ~> passed is 10 , or an expected bit-error probability of 10 " after passing through 1000 regenerators. These results indicate that, for a given jitter σ, the bit-error probability for a packet after passing many regenerators can be expected to be substantially less than the maximum value for a single regenerator, as shown in Figure 10. However, this result is unduly optimistic. It ignores the fact that, although the phase θ of a data packet relative to the local oscillator at a given regenerator is a continuous uniform random variable, nevertheless the phases of successive packets arriving at the regenerator from the same source may be highly correlated. This is because the physical fluctuations that cause θ to vary (such as temperature and mechanical changes acting on an optical fibre cable) may occur on a much slower time scale than the arrival time of packets. Therefore the regenerated packet stream may contain bursts (and possibly prolonged bursts) of errors, even though the expected bit-error probability according to (1 5) is very low. Therefore it is appropriate to take the more conservative estimates of jitter tolerance indicated by equation (1 2) and plotted in Figure 9 In fact, an even more serious limitation is encountered if we drop the assumption that the gate selection is ideal (i.e. no systematic errors, noise-free, and having infinitesimal resolution), and this situation is analysed next. Bit-error probability when using imperfect gate selection If the mechanism used to perform the gate selection in each time slot is imperfect, then at certain times the incorrect gate will be selected, leading to an increase in the bit-error probability. In this sub-section the gate selection technique will be analysed based on comparison of packet energies, as described above, in the case that the energy measurement and comparator circuits are subject to noise and other imperfections. In Figure 5, the detectors D 1 and D2 followed by electronic integrators each provide a voltage, V ] and ^ respectively, in each time slot which is proportional to the energy of the regenerated packet emerging from gate G 1 and G2, respectively, in that time slot. The comparator C produces a binary output signal according to whether or not jexceeds V 2 , and this signal is used to control the operation of the selector switch S. Ideally, if the energy of the regenerated packet emerging from gate G 1 is greater or equal to the energy of the regenerated packet emerging from gate G2, then the comparator output is 0 causing the switch S to select the output from gate G 1 ; and ideally if the energy of the regenerated packet emerging from gate G2 is greater or equal to the energy of the regenerated packet emerging from gate G 1 , then the comparator output is 1 causing the switch S to select the other output. However because of systematic and random errors, the energy measurement and comparator output are non-ideal. Here we assume that systematic errors are negligible, and model the random errors by assuming that, for any given phase angle θ , the voltage V - V 2 is a normally-distributed random 2 variable with variance σ c . Here the normalisation is such that a voltage V l or V 2 equal to 1 represents the energy of a regenerated packet consisting of n 'mark' pulses, where n is the number of bits in the original packet, and the expected number of 'marks' in the original packet is 0.5. Therefore the probability R(Gl) that gate G 1 is selected (i.e. that the comparator output signal is 0) is given by and the probability that gate G2 is selected (i.e. that the comparator output signal is 1 ) is given by For a given phase angle θ , the bit-error probability is B = P(GX)B( Ψϊ ) + P(G2)B(ψ 2 ) , ( 18) where ψ x , ψ 2 nά B(ψ) are given by (6), ( 1 1 ) and (1 2), respectively. Figure 1 2 shows a plot of the bit-error probability B against the phase angle θ , calculated according to ( 1 8), and assuming for example that W I T = 0.75 , σl T = 0.018 and σ c I T = 0.001 . By comparing with Figure 9 it can be seen that the bit-error probability is very significantly increased because of the non-ideal gate selection. Figure 1 3 shows the severe degradation in bit-error probability that occurs when the gate selection is non-ideal, even if the standard deviation σ c / T is very small. The figure shows a plot of the maximum value of the bit-error probability B for any phase angle θ in the range 0 < _? < 2;r, calculated according to ( 1 8), and plotted versus σ c l T . Again the calculations assume for example that W I T = 0.75 and curves for various values of cr/ T are shown. Notice, for example, that with σl T = 0.018 , a value of σ c I Tas small as 10 is sufficient to degrade the bit-error probability by 4 orders of magnitude (maximum bit-error probability of 10 ~8 , as compared to the value 10 " shown in Figure 10 in the case of ideal gate selection with WI T = 0.75 and σl T = 0.018 ) . This limitation in the usefulness of the two-gate design for the bit-asynchronous regenerator is overcome by the quad-gate design described below. Alternatively a triple gate regenerator might be used, although this delivers a lesser improvement in performance. Quad-gate bit-asynchronous optical packet regenerator Principle of operation Figure 1 4 shows a quad-gate bit-asynchronous packet regenerator. The data bits in the incoming packet are used to control the opening of four gates, G 1 , G2, G3 and G4. A data bit with value 1 ('mark') causes each of the four gates to open for a fixed time duration (the gate window), otherwise the gates remain closed. It is preferable, though not essential, that the widths of the time window for the four gates are equal. The output from the local clock (a continuous free-running source of optical RZ pulses at a repetition frequency nominally equal to the packet bit rate X I T) is applied to the inputs of the four gates, with relative delays in steps of T 14 as shown in Figure 14. As with the dual-gate regenerator, to ensure that the clock pulses will be correctly modulated by at least one of the four gates whatever the value of θ , the window width W must lie within a particular range of values, which for the quad-gate regenerator is 774 < W < T . As previously, the incoming data pulses and local clock pulses are represented here by delta impulses. (As described below, when finite pulse widths are taken into account the acceptable range of window widths is somewhat narrower than T 1 < W < T) . As in the case of the dual-gate regenerator, we should note, with reference to Figure 14, that there is an alternative and equally valid configuration in which the relative delays in steps of Tl 4 are removed from the input ports A of the gates, and placed instead at the control ports C. The operation of the regenerator is very similar in this case, and the predicted performance described later is the same. Again, in the analysis below the configuration will be assumed to be that in which the packet data bits are connected directly to the control ports of the gates, and the differential delays are in the connections to the input ports. As in Figure 5, the technique for gate selection shown in Figure 1 4 is based on a comparison of the total optical energy emerging from each gate, integrated over the duration of the packet. In this case the optical switch S must select one of the outputs from the four gates. As shown in Figure 14 the 1 x4 switch could consist an arrangement of three 1 x2 switches, S1 , S2 and S3. The controller C measures the outputs from detectors D 1 , D2, D3 and D4 in each time slot, and sets the selector switches accordingly using the strategy described by (20) below. Other practical details are similar to those described above. In particular, the optical delays (labelled . , L + ATI 4 , L + ATI 2 and Z + 3 Δ774 in Figure 14) between the outputs of the gates and the selection switch S are used to allow sufficient time for the circuitry and switch S to operate before the packets arrive at the switch. Typically the delay L will be slightly less than one time slot in duration. Optionally, the optical delays between the outputs of the various gates and the switch S may be made to differ in steps of 774 , as shown in Figure 14. The purpose of doing this is to compensate for the delay steps at the inputs to the gates, thus equalising the delay of all optical paths from the clock source to the output of the selector switch S. As noted previously, this has the benefit that all the regenerated packets are then in precise bit synchronism with each other and with the local clock, so that the local clock may therefore be used as a continuous and regular source of pulses for use in subsequent digital optical processing stages. A further very important benefit of equalising the delay in this way is to reduce the problem of 'packet slippage' in a large network, as described below. Also as noted above, an alternative method of selecting the most appropriate gate output in each time slot may be to perform a bit-error measurement on the whole or part of the packet that emerges from each gate. In the next sub-section the bit-error probability arising from jitter in the time of arrival of the incoming data bits is analysed. Bit-error probability The bit-error probability for the output from gate / is given by (1 2) with ψ = ψ t , where ψ ι = modl, with i = 1,2,3,4 . (19) Figure 1 5 is a plot of the bit-error probability according to ( 1 2) and ( 1 9), against the phase angle θ , taking as an example the values σ = W = 0.757 for the jitter and gate window width, respectively. It can be seen that, with these parameter values, for any value of θ in the full range 0 < # < 2 r the bit-error probability for the output from at least one of the gates is less than 10 ~12 . The expected value of the optical energy measured at the output of the Λh gate, \E ( / , is given by ( 1 3). An appropriate strategy for selecting the gate output in each packet time slot, based on a comparison of the energies of the packets emerging from each gate, is: if ( E j ) = min {( E, ) } then select gate (l + (j + 1 )mod4) (20) where -j(E / denotes the set -](£, ), (E 2 ),(E 3 ),\E 4 / . Figure 1 6 shows a plot of the bit-error probability B against the phase angle θ , calculated according to ( 1 2), using an ideal mechanism to select the output gate / (such as the strategy (20) executed by ideal circuits without noise or impairments) and assuming for example that W I T = 0.75. It can be seen that a maximum bit- error probability of 10 " -1 2 is predicted when sigma/T = 0.036. By comparing this result with Figure 10, it can be seen that, compared to the dual-gate regenerator, the quad-gate regenerator can tolerate a higher level of rms jitter sigma in the arrival time of the incoming data bits. The reason for this is that with the quad- gate regenerator, the clock pulses that are modulated by the selected gate are positioned further in time from the edges of the gate window, thus reducing the probability that jitter in the arriving data may cause a clock pulse to fall outside the window resulting in a bit error in the regenerated packet. The effect of non-ideal selection of the gate output is now analysed. In Figure 14, the detectors D1 to D4 followed by electronic integrators each provide a voltage, V λ to V 4 respectively, in each time slot which is proportional to the energy of the regenerated packet emerging from gate G 1 to G4, respectively, in that time slot. The comparator circuit C produces an output signal which is used to control the operation of the selector switch S. The ideal output of the comparator is as defined by (20). However because of systematic and random errors, the energy measurement and comparator output are non-ideal. We assume here that the systematic errors are negligible, and model the random errors due to noise, etc, as follows. We assume that, for a given phase angle θ , the voltage difference V, - V / (for all / and j ≠ i ) is a normally-distributed random variable with mean V η and variance σ 2 . As before, the voltages are normalised so that V, = 1 represents the energy of a regenerated packet emerging from gate G/ consisting of n 'mark' pulses, where n is the number of bits in the original packet, and the packet is assumed to have a mark:space ratio of 1 . Then, with probability it will be determined on the basis of a measurement of the voltages V, (i = 1,2,3, 4) that = min|(E,) . Then, if the result of that determination is used in the strategy (20) to select the gate output in each time slot, the resulting bit-error probability is B = j B(ψ J ) lφ(V„ lσ c ) , (21 ) J i≠J where J = 1 + 0 ' + l)mod4 , and B(ψ) is given by (1 2). Figure 17 shows a plot of the bit-error probability B against the phase angle θ , calculated according to (21 ), and assuming for example that W I T = 0.75 , σl T = 0.036 and σ c I T = 0.001 and 0.052. In this example, only when the parameter σ c I T becomes as large as " 5% is there a significant increase in bit- error probability. This demonstrates that the quad-gate regenerator can show good tolerance to non-ideal operation of the gate-selection mechanism. This is in contrast with the dual-gate regenerator discussed earlier, where it was found that the bit-error probability is severely degraded when the gate selection is non-ideal, even if the standard deviation σ c / T is very small (Figure 13). Figure 1 8 shows a plot of the maximum value of the bit-error probability B for any phase angle θ in the range 0 < θ < 2π , calculated according to (21 ), and plotted versus WI T . The results shown are for σl T = 0.036 and σ c I T = 0.001 and 0.05 . It is found that, depending on the value of σ c I T , the optimum value of WI T lies in the range approximately 0.7-0.85. Other calculations based on (21 ) show that with σ c I T less than 4%, and σl T ≤ 0.032 , the maximum bit-error probability is less than 10 " , regardless of the phase angle θ . Thus for a packet which passes through a sequence of 1 000 — 12 regenerators of this type, the bit-error probability will be less than 10 The quad-gate regenerator, with gate selection based on packet energy comparisons, works as well as it does because of the good design of the gate selection strategy, given by (20). This strategy ensures that the clock pulse is generally positioned well inside the gate window of the selected gate (for example, with W I T = 0.75 , the minimum separation between the clock pulse and the edge of the gate window is about 7/ 4 ), and this reduces the probability of bit errors in the regenerated packet due to timing jitter in the incoming data. The quad-gate regenerator is therefore a preferred embodiment of the invention, and preferably WI T is in the range 0.7-0.85. Packet time-position slippage A side-effect of this method of bit-asynchronous regeneration is that it introduces a small non-deterministic delay; in other words, the time delay between the arrival of an incoming data packet and the emergence of the regenerated packet consists of a constant delay plus a small non-deterministic component. In the case of the quad-gate regenerator, provided all the optical paths between the clock source and the output of the selector switch S are equalised (as shown in Figure 14), to good approximation the non-deterministic delay introduced by the regenerator can be considered to be bounded on the interval (0, 7/ 4) . In the case of a single regenerator this small random time displacement of the regenerated packet may be considered negligible because it is only a fraction of the bit period T. However a packet that travels across a network through a sequence of many regenerators may accumulate a significant net time displacement. A system error may occur if the accumulated displacement exceeds some specified limit of L bit periods (such as the width of the time guard bands before and after each data packet) . This accumulated displacement in time experienced by a packet is similar to the problem of a random walk, or the Brownian motion of a particle, in one dimension. At the Λh regenerator the regenerated packet undergoes a non-deterministic time shift τ j relative to the average value of delay. To a good approximation, τ f can be considered to follow a continuous uniform random distribution on the interval (-7/ 8, 7/ 8) , with probability density function £/(r,) = 4/ 7. After a packet has passed through Q identical regenerators (with uncorrelated phases), its accumulated displacement from the average delay value is ∑ τ, , which has an expected value of zero and variance QT 2 1X92 . The probability that the magnitude of the accumulated displacement exceeds the specified limit is therefore given by where Z ~ N(0,l) is the standard normal random variable, and it is assumed that Q is large (i.e. β >~ 50 ). For small values of Q we can use the property that P ∑ > LT) is exactly zero for Q < 87 (since a directed (non-random) walk consisting of QL steps, each of length not more than 7/ 8 , cannot reach a distance greater than L T). Figure 1 9 shows values for the probability that a packet suffers 'slippage' (ie. a time displacement greater than the specified limit LT), according to (22). The packet slippage probability is plotted versus Q, the number of regenerators passed, for various values of LT. For networks in which Q ≤ XOO , 5-bit guard bands (L = 5)surrounding the data packet time slot would be sufficient to ensure a packet-slippage probability of less than 10 , whereas in larger networks with Q ∞ XOOO guard bands of at least 14 bit periods are required. For a packet size of length n = 1000 bits, say, these guard bands represent a modest overhead on the network throughput. However, the analysis leading to (22) and the results shown in Figure 1 9 are idealised, because it was assumed that all four optical paths between the clock source and the output of the selector switch S are precisely equal. These results give the minimum theoretical guard-band width in the ideal case. In practice the optical path equalisation inside each regenerator is subject to errors (errors in fabrication and assembly of the optical waveguides and components, as well as fluctuations in path lengths due to environmental effects), and so the effects of these must be considered. Let us assume that a network contains of a large number of quad-gate regenerators, as shown in Figure 1 9, in each of which the optical paths between the clock source and the output of the selector switch S differ in delay time from the average value by an amount δ , where δ is a normally-distributed random variable, δ ~ N(0,σ D ) . The standard deviation σ D is a measure of the errors in equalising the delays of the optical paths. A packet that passes through the Λh regenerator will undergo a non-deterministic time displacement _f , relative to the average value of delay, given by _/ = δ ι + τ ι , where τ t is a continuous uniform random variable on the interval (-7 / 8, 7/8) . After a packet has passed through Q regenerators, its accumulated displacement from the average delay value is ∑ d, . The expected value of ∑ d, is zero, and since δ, and r, are independent variables, var ∑ = Q(T 2 1 92 + σ 2 υ ) . The probability that the magnitude of the accumulated displacement exceeds the specified limit of L bit periods is therefore given by The probabilities calculated according to (23) produce a graph identical to Figure 1 9, except that the values of L T shown in the legend should be multiplied by a factor -JX + X92(σ D l T) . For example, if the tolerance in equalising the optical paths in the regenerators is σ D = 7, then to prevent packet slippage after 100 regenerators (Q = X00 ) a guard band of at least 5 x -JX + 192 = 70 bit periods is required, and for ( 9 = 1000 a guard band of at least 17 x VΪ + 192 = 195 bit periods is required. These examples show that the errors in equalising the optical paths in the regenerators should be minimised (preferably σ D < 7) to keep the guard bands as small as possible to avoid a costly reduction in network throughput. At a peak data rate of 100 Gbit/s (7 = 100 ps), a tolerance of ±7 on path delay represents a length tolerance of ±2 mm in glass, or approximately ±1 mm on a semiconductor substrate. If the optical components in the regenerator are in the form of an integrated monolithic semiconductor device, or discrete semiconductor devices mounted on a motherboard with planar waveguide interconnections, or discrete semiconductor devices connected by short optical fibre waveguides, these tolerances can be readily achieved. If, however, the optical gates are based on a nonlinear optical fibre device such as a fibre loop mirror, as suggested earlier, the length of fibre used in each loop mirror may be as great as 1 km in order for the required optical intensity of the input data bits to be acceptably low. To fabricate such devices to within a length tolerance of +2 mm represents a technical challenge. A practical solution would be to incorporate within each fibre loop a mechanical device to stretch a portion of the fibre so as to bring the overall length to the required value, or alternatively to incorporate an adjustable air delay line for the same purpose. In addition it would be beneficial to house all the fibre loops together in an environmentally-controlled package, incorporating temperature control. Assuming a typical expansion coefficient of 10 "6 /°C for optical fibre, the temperature control would be required to be within ±1 °C to maintain the length to within ±2 mm, for loop lengths of ~ 1 km . r-gate bit-asynchronous optical packet regenerator It will be apparent to those skilled in the art, that the packet regenerator may be realised using different numbers of gates ( for example 5 gates, or 8 gates) in addition to the 2-gate and 4-gate examples described above. Some general relations for a bit-asynchronous optical packet regenerator with k gates (k > 3) are as follows. The bit-error probability for the output from gate / is given by ( 1 2) with ψ = ψ j , and the expected value of the optical energy measured at the output of the Λh gate is given by ( 1 3), where ( θ z - r ^' = ^ + — J modl (24) and i = X,2,...,k . An appropriate strategy for selecting the gate output in each packet time slot, based on a comparison of the energies of the packets emerging from each gate, is: if (E ) = min -SE ) | then select gate ι + ι y - 1 + — ] mod& if Hs even, ( \ (25> or select gate . 1 + 1 j - H — — - mod k if ; is odd where E ( . denotes the set . Single Gate Regenerator In an alternative embodiment, the local clock pulse source is again continuously free-running, but requires only one gate to modulate the output of the clock pulse source so as to regenerate the packet. The principle of this alternative approach is shown in Figure 21 . In each time slot, the phase detector measures the phase angle θ between the free-running local pulse source and the incoming packet. This information is used to shift by an appropriate amount the phase of the control signal that is applied to the gate. The effect of the phase shifter is that when a packet data bit of value 1 causes the gate window to open, the window is located as near as possible centrally over the clock pulse (as depicted in Figure 21 ) . The phase detector and phase shifter operate once in each time slot. In the ideal case the phase detector and phase shifter operate without error and the gate window is located exactly centrally over the clock pulse. In that case the main source of bit errors in the regenerated packet is jitter in the arrival time of the packet data bits. The analysis of bit errors arising from timing jitter in this regenerator is then similar to the analysis of the effects of timing jitter in an OTDM demultiplexer given by Jinno (IEEE Journal of Quantum Electronics, vol 30, no.1 2, pp. 2842-2853, 1 994). In particular, the bit-error probability as a function of the ratio of the gate widow width 11 to the bit period 7, for various values of the rms jitter σ in the arrival time of the packet data bits, is as depicted in Figure 5 of Jinno ( 1 994). Some results of that analysis are that the minimum bit-error probability is obtained when W is equal to 7, and also σ must be less than 0.071 7 to ensure that the bit-error probability is less than 10 ~12 . In a more realistic case, noise and other imperfections in the phase detector and phase shifter cause systematic and random errors in the position of the gate window relative to the clock pulse. We neglect systematic errors and assume here that, as a result of the random errors, the position of the gate window is a normally distributed random variable with standard deviation σ w . In that case, the bit-error analysis is again similar to that of Jinno ( 1 994), and the results shown in Figure 5 of Jinno can be used, except with the parameter σ replaced by 1 σ 2 + σ w 2 . Again it is found that the minimum bit-error probability is obtained \ ι 1 when 11 is equal to 7, and -,/σ + σ w must be less than 0.071 7 to ensure that the — 12 bit-error probability is less than 10 Figure 22 shows a possible embodiment of this alternative version of the bit- asynchronous regenerator, and it is assumed that the bit rate is 100 Gbit/s. The incoming packet (at wavelength λ jn ) is first passed through an optical input stage with slowly-responding automatic level control (such as an erbium-doped fibre amplifier), and is then split into two paths, one leading to the phase detector and the other to the phase shifter. The local clock pulse source is a mode-locked ring fibre laser producing ~2 ps pulses at the wavelength λ c . The output of this clock source is also split into two paths, one leading to the phase detector and the other to the optical gate. At the input to the phase detector, the clock pulses are broadened to " 10 ps, for example by passing them through the optical bandpass filter F1 (as shown in Figure 22) or by dispersion in fibre or in a chirped grating. The phase detector could be based on four-wave mixing in a semiconductor optical amplifier SOA FWM (as described for example by O Kanatani, S Kawanashi and M Sarawutari in Electronics Letters, vol.30, no.10, p.807, 1 994) . The output from the SOA FWM is isolated using the optical bandpass filter F2, and then detected. The electronic processing stage (which could include a low noise, high linearity sample-and-hold gate triggered by the global packet-level clock) measures the photodetector output voltage immediately after the arrival of the packet in each time slot, the measured voltage being given approximately by A + Bcosθ , where A and B and constants and θ is the phase difference between the clock and the incoming packet bits. In the example implementation of the phase shifter, this signal is used to control the wavelength λ cw of the continuous-wave distributed- feedback laser DFB in the phase shifter section. The output of the DFB laser is connected to the input of a date-driven optical switch denoted UNI 1 . This device could be the ultrafast nonlinear interferometer switch described by Hall and Rauschenbach (paper PD5, Proceedings of Conference on Optical Fiber Communication OFC'98, published by the Optical Society of America, February 1 998), which has been shown to operate at a speed of 100 Gbit/s, although any data driven optical switch capable of producing approximately square switching windows with negligible variation in throughput delay would be suitable. The control signal to UNI 1 is the input data packet. The action of UNI 1 is therefore to shift the wavelength of the incoming packet from λ jn to the controlled wavelength λ . This packet with shifted wavelength is then isolated using optical filter F3, and passed through a dispersive optical delay line which imparts a time delay which depends on wavelength. This dispersive delay line could be a fibre grating device or, as shown in Figure 22, a length of optical fibre, such as a length of optical fibre of the type manufactured primarily for use in dispersion compensation. The required minimum amount of phase shift of the control pulses is ± 5 ps (i.e. ± 0.57, where 7 is the bit period). Therefore, if for example the length of dispersion compensating fibre is 20m and the fibre dispersion is 100 ps/nm/km, the required shift in the wavelength λ cw of the DFB laser is ± 2.5 nm, and this must be accomplished within the duration of the guard band between packets (say " 5 ns). Alternatively, instead of controlling the wavelength of a single DFB laser, as shown in Figure 22, the control loop may contain means to select one of a number of lasers each having a different fixed wavelength. Because the optical fibre used as a dispersive delay line is a long device subject to changes in path length due to environmental factors (temperature, strain, etc), it is convenient as in Figure 22 to pass the local clock pulses over the same fibre. This ensures that there is a negligibly small relative change in delay for the clock and control pulses. Alternatively, the error signal could be used to select one of a discrete number of optical paths. A further alternative phase shifter comprises means to select one from a number of optical delay lines each having a different fixed delay. The delay lines could consist of a silicon wafer on which is fabricated a silica-on-silicon planar lightwave circuit. This circuit may be integrated in hybrid fashion with an array of discrete or integrated semiconductor optical switching devices, such as semiconductor optical amplifiers or electroabsorption modulators. In this case the electronic processing stage selects the appropriate delay line by switching on or off the appropriate semiconductor optical switching devices. The resultant optical data bits, suitably phase shifted, are then used as the control pulses in the optical gate. The gate, denoted UNI2 in Figure 22, which is controlled by the phase-shifted packet data bits, is used to modulate the locally generated clock pulses so as to produce a regenerated packet, synchronous with the local clock. Again the device UNI2 could be the ultrafast nonlinear interferometer switch described by Hall and Rauschenbach. In the case that the regenerator is receiving inputs from a multiple number of sources, if the embodiment shown in Figure 22 is employed, the same length of dispersion- compensating fibre should be used for all inputs to provide appropriate phase shifts, so that all the regenerated packets are bit-synchronous. Figure 23 shows an example of how the bit-asynchronous regenerator may be used in an optical network. Three sources of packets are depicted (sources A, B and C), each of which have independent, uncorrelated clocks. Merely for clarity, in Figure 23 the packets that have originated from source A, B or C are coloured white, black or shaded, respectively. The link from the output of each source carries only packets from that source, and therefore those packets are bit- synchronous with the clock in the source. This means that if a regenerator is required in the link, it may be a bit-synchronous type, similar for example to that depicted in Figure 2 . By suitable adjustment of the transmitted power at the source, the power levels in any optical amplifiers used in the link, and also the power levels at any synchronous regenerators used in the link, the bits in the packets arriving at the input of a routing node (such as routing node 1 ) may conveniently have an intensity at an appropriately-defined standard 'digital' level (e.g. of the correct intensity to perform complete switching in the optical gate or gates used in the bit-asynchronous packet regenerator AR in the switching node) . The inputs to the switching nodes will, in general, be bit-asynchronous. Thus, for example in Figure 23, the packets that arrive at switching node 1 having originated from sources A and B (i.e. 'black' and 'white' packets), are bit-asynchronous because the clocks in sources A and B are uncorrelated. Each input to the routing node may pass through a bit-asynchronous packet regenerator AR, and each of these regenerators in a switching node share the same local optical clock pulse source. Each output from the routing switch may carry packets that have originated from more than one source. For example, in Figure 23, an output link from routing node 1 may contain packets that have originated from sources A and B (i.e. 'black' and 'white' packets), but the action of the bit-asynchronous packet regenerators AR in the switching node is such that all the packets carried on this output link are now in bit-synchronism with the local clock in routing node 1 , despite their different sources. Therefore if a regenerator is required in this output link, it may be a bit-synchronous type. In Figure 23, the inputs to routing node 2 are from routing node 1 and from source C, and these inputs are bit-asynchronous. Each of these inputs pass through bit-asynchronous regenerators AR that share the same local optical clock pulse source, so that an output from the routing node 2 may contain packets that originate from various sources, including sources A, B and C, but all the packets on the output links are again in bit-synchronism with the local clock in routing node 2. As is shown schematically in Figure 26, a node, such as that referenced node B, may combine an add/drop function for local traffic as well as regenerating packets for onward transmission. By using the bit-asynchronous packet regenerators in the switching nodes, we have shown that it is possible to design a network in which each individual link carries packets which are bit-synchronous (i.e. which share the same bit-level clock) and which share a standard power level. This allows simpler designs of regenerators in the links, and also removes the need for packet-by-packet power level equalisation. However, by regenerating the packets at each node in bit- asynchronous fashion, this entirely eliminates the need to maintain bit-level synchronism between the different links and routing nodes throughout the network - and thus we have eliminated the major architectural limitation of synchronous OTDM networks. There is described above with reference to Figure 21 , an alternative approach to the bit-asynchronous packet regenerator, in which the local clock pulse source is again continuously free-running, but which requires only one gate to modulate the output of the clock pulse source so as to regenerate the packet. A measurement of the phase θ was used to control a phase shifter acting on the control signal to the optical gate. This alternative approach is, in effect, a feedforward, open loop control system. There is also described, in the immediately preceding section, the use of a regenerator in a network in which incoming packets at the regenerator are bit-synchronous (i.e. they all share the same bit- level clock). Therefore in this case the phase θ is only very slowly varying from one packet to the next, and this allows another arrangement for the control of the phase shifter, as will be described with reference to Figures 24 and 25. Figure 24 shows the principle of this alternative approach. In this case the phase detector measures the phase angle θ between the free-running local pulse source and the control signal applied to the optical gate (i.e. the packet data bits after the phase shifter). The measured phase angle is then used to control the phase shifter. The control signal to the phase shifter may be either an analogue or digital signal (preferably a digital signal at the packet level), and this control signal would be gated at the rate of once per packet time slot. In contrast with the arrangement shown in Figure 21 , this is a feed-back, closed loop control system. This has the advantage that the system is free of systematic errors and drift, even if the phase detector is nonlinear. Furthermore, drifts in the phase shifter are automatically compensated for by the closed loop (because the phase shifter is inside the feedback path). Because, in a practical system, the feedback delay may be greater than the duration of a packet time slot, this closed-loop control system will not be sufficiently fast acting to track substantial variations in phase θ from packet to packet. However this is not an important limitation in certain important network applications, as described above. Figure 25 shows an example embodiment of this alternative form of the bit-asynchronous packet regenerator. The various designated components are as described previously for Figure 22. The description above includes a discussion of the allowable amount of frequency difference between the clock at the packet source and the clock in the asynchronous regenerator. The present embodiment of the asynchronous regenerator using a feed-back, closed-loop arrangement may impose a further restriction on the amount of frequency difference that can be tolerated. It is necessary that the frequency difference between the bit rate of the incoming packet and the full-rate optical clock source in the regenerator is significantly smaller than the effective bandwidth of the control loop (including the electronic bandwidth, the feedback delay and the speed of response of the phase shifter). Following normal engineering practice, the frequency offset should be at least an order of magnitude smaller than the effective bandwidth of the control loop. For example, if the determining factor for the control-loop bandwidth is an electronic bandwidth of 10 kHz, then the magnitude of the frequency offset f R - f s should be no greater than 100 Hz (where f s and/^ are the frequencies of the microwave oscillators depicted in Figure 4, and it is assumed that s = M R = 10 ). In an alternative embodiment, the phase shifter shown in Figure 25, consisting of DFB laser, switching device UNI 1 , optical filter F3 and dispersion- compensating fibre, could be replaced by a variable optical delay line. Since, in the network scenario discussed above, and illustrated by Figure 23, the packets arriving at the regenerator may be in bit-synchronism. Therefore the bit- asynchronous regenerator merely needs to track the relatively slow variations in the phase difference between the incoming packets and the local clock, rather than abrupt packet-to-packet phase variations. The control loop may therefore be relatively slow acting (much slower than on a packet-by-packet basis). However, the control loop bandwidth should not be so low as to restrict the amount of frequency offset that can be accommodated. Suppose, for example, that the delay line is a variable motor-controlled device, such as a motor-driven fibre stretcher, which is capable of changing the value of the optical delay at a maximum rate of 100 ps per second. This corresponds to 10 bit periods per second at 100 Gbit/s, for example, and so the maximum allowable frequency offset would be an order of magnitude less than that (to ensure the effective control loop bandwidth is at least 10 times faster than the fastest variations in the signal to be controlled), i.e. " 1 Hz, which is a severe restriction. Therefore a motor-controlled phase shifter may not have sufficient speed of response for this application. Another type of variable optical delay line is a fibre stretcher consisting of a length of fibre coiled tightly around a piezo-electric drum. This type of stretcher is capable of 100 μm length change at 20 kHz, or approximately 1 ps delay change in 50 ms. in order to achieve a range of ± 5 ps (i.e. ± 0.5 bit periods at 100 Gbit/s), a cascade of piezoelectric drum stretcher units ( 10-20 units) would allow a frequency offset of a few kHz between the local and distant clocks.

Claims: CLAIMS 1 . A method of operating a node in an optical communications network including a) receiving at the node an optical packet; and b) generating from the said optical packet received at the said node a regenerated optical packet having a phase determined by a local bit-level clock source and independent of the bit-level phase of the said packet received at the node. 2. A method of operating an optical regenerator comprising: a) receiving an optical packet at an input of the regenerator; and b) generating from the said optical packet a regenerated optical packet having a phase determined by a local bit-level clock source and independent of the bit-level phase of the said packet received at the node. 3. A method according to claim 1 or 2, in which the step of generating a regenerated optical packet includes gating, using the received optical packet, an optical clock signal from the local bit-level clock source. 4. A method according to claim 3, including: i)measuring the phase of the said optical packet; ii) depending on the result of step (i), modifying the phase of the optical packet; and iii) subsequently applying data signals from the optical packet as a control signal to gate means arranged to gate the said optical clock signal. 5. A method according to claim 4, in which in step (I) comprises measuring the phase difference between the incoming optical packet and the local clock source. 6. A method according to claim 4 or 5, in which the gate window is equal to the bit period. 7. A method according to any one of claims 4 to 6, in which the phase difference between the optical packet and the local optical clock is detected by means of a nonlinear interaction between the clock signal and the optical packet, 8. A method according to claim 7, in which the nonlinear interacton occurs in an optical fibre device. 9. A method according to claim 7, in which the nonlinear interaction occurs in a semiconductor device. 10. A method according to claim 9, in which the nonlinear interaction is a process of four-wave mixing. 1 1 . A method according to any one of claims 4 to 1 0, in which the phase of the optical packet is modified by passing through a wavelength converter and a dispersive optical delay line. 1 2. A method according to claim 3, including: passing the optical clock signal through each of a plurality of gate means; applying data signals from the received optical packet as a control signal to each of the plurality of gate means with different delays of a fraction of a bit period relative to the optical clock signal input to the gate means; and selecting the output of one of the plurality of gate means to provide the regenerated optical packet. 1 3. A method according to claim 1 2, in which the difference in delays is equal to T/k where T is the bit period and k is the number of optical gate means. 14. A method according to claim 1 2 or 13, in which the width W of the gate window is not less than l ' ^ and not more than T, where T is the bit period and k is the number of optical gates. 1 5. A method according to any one of claims 1 2 to 14, including making a measurement of a parameter of an optical signal output from the gate means, and selecting the output of one of the plurality of gates to provide the regenerated optical packet depending on the results of the said measurement. 1 6. A method according to claim 1 5, in which the said parameter is the energy of the optical signal. 1 7. A method according to claim 1 6, including comparing the energies of the signals from the plurality of gate means and making the said selection depending on the results of the said comparison. 1 8. A method according to claim 1 5, in which the said parameter is derived from the number of bit errors in the optical signal, and the signal with the lowest number of bit errors is selected to provide the regenerated optical packet. 1 9. A method according to any one of the preceding claims, including further processing the regenerated optical packet in optical processing means clocked by a signal from the local optical clock source. 20. A method of operating a communications network comprising a plurality nodes interconnected by an optical transmission medium, the method including: transmitting an optical packet onto the network, and at a network node, receiving the said packet and generating from the said packet a regenerated optical packet having a phase determined by a local optical clock source and independent of the phase of the said packet received at the network node. 21 . A method according to claim 20, including receiving at the network node optical packets from a pluraltiy of different sources and having different respective phases. 22. A method according to claim 20 or 21 , further comprising outputting the regenerated optical packet onto the optical transmission medium. 23. A regenerator for optical packets including a local optical pulse generator comprising a free-running oscillator independent in frequency and phase from the packet source. 24. A regenerator for optical packets comprising: a) means for receiving an optical packet; and b) means for generating from the said optical packet received at the said node a regenerated optical packet having a phase determined by a local bit-level clock source and independent of the bit-level phase of the said packet received at the node. 25. A regenerator according to claim 23 or 24, including gate means controlled by a data signal from an optical packet and connected to a local optical clock source. 26. A regenerator according to claim 25, including a plurality of gate means each arranged to receive a clock signal from a local optical source and a control signal from a packet received at the regenerator; means for generating different delays of the control signals relative to the clock signals at different respective gate means; means for selecting an output from one of the plurality of gate means. 27. A regenerator according to claim 26 including at least four gate means. 28. A regenerator according to claim 27, in which the ratio W/T of the gate window W to the bit period T lies substantially in the range 0.7 to 0.85. 29. A regenerator according to any one of claims 14 to 1 8, in which the local optical clock source is a mode-locked laser. 30. A regenerator according to claim 29, in which the mode-locked laser is passively mode-locked. 31 . A node for connection in an optical communications network and including a regenerator according to any one of claims 24 to 30 32. A node for connection in an optical communications network and arranged to operate by a method according to any one of claims 1 to 22. 33. An optical communications network including a node according to claim 31 or 32. 34. A regenerator according to claim 24 including means for measuring the phase of the optical packet, and means responsive to the said means for measuring for modifying the phase of a control signal applied to gate means, which gate means gate the optical clock signal thereby producing the regenerated optical packet. 35. A regenerator for optical packets according to claim 23, including an optical gate controlled by the data bits in the incoming packet, and in which the output of the local optical pulse generator is connected to the input of the said optical gate, and means to detect the phase difference between the incoming packet and the local optical pulse generator, and means to shift the phase of the control signal applied to the optical gate in correspondence with the said detected phase difference in such fashion as to obtain a correctly regenerated optical data packet at the output of the said optical gate. 36. A regenerator according to claim 34 or 35, in which the gate window width is equal to the bit period. 37. A regenerator according to any one of claims 34 to 36, in which the phase difference is detected by means of a nonlinear optical interaction between the local optical pulse generator and the incoming data packet. 38 A regenerator according to claim 37, in which the phase difference is detected by means of a nonlinear optical interaction between the local optical pulse generator and the incoming data packet and said nonlinear optical interaction occurs in a fibre device. 39 A regenerator according to claim 37, in which the phase difference is detected by means of a nonlinear optical interaction between the local optical pulse generator and the incoming data packet and said nonlinear optical interaction occurs in a semiconductor device. 40. A regenerator according to claim 39, in which the said nonlinear optical interaction is four wave mixing. 41 . A regenerator according to any one of claims 34 to 40, in which the means to shift the phase of the control signal includes an optical path having a variable delay. 42. A regenerator according to any one of claims 34 to 40, in which the means to shift the phase of the control signal consists of a plurality of optical delay lines having different respective delays, and means for switching the control signal through a selected one of the plurality of optical delay lines. 43. A regenerator according to any one of claims 34 to 40, in which the means to shift the phase of the control signal consists of a wavelength convertor and a dispersive optical delay line. 44. A regenerator according to claim 43, which the said dispersive optical delay line consists of an optical fibre. 45. A regenerator according to claim 43, in which the said dispersive optical delay line consists of a fibre grating device. 46. A regenerator according to any one of claims 34 to 45 including a feedforward open loop contol system in which the phase of the incoming packet is detected before passing through the phase shifter. 47. A regenerator according to any one of claims 34 to 45 including a feed-back closed loop control system in which the phase of the incoming packet is detected after passing through the phase shifter. 48. A regenerator according to claim 29, in which the mode-locked laser is a ring laser. 49. A node for an optical communications network including a regenerator according to any one of claims 34 to 48. 50. An optical communications network including a node according to claim 49, 51 . An optical network in which bit-asynchronous regenerators are located at switching nodes. 52. An optical communications network according to claim 33, or 50 or 51 in which the links between nodes carry packets in a bit-synchronous fashion. 53. A network according to claim 52, including bit-synchronous regenerators in links between nodes. 54. A method according to any one of claims 4 to 10, in which the phase of the optical packet is modified by passing the optical packet through an an optical path having a variable delay. 55. A method according to any one of claims 4 to 10, in which the phase of the optical packet is modified by passing the optical packet through a selected optical delay path. 56. An optical communications network in which nodes at different locations in the optical communications network process optical packets asynchronously at the bit-level.

Inventors: COTTER DAVID, ELLIS ANDREW DAVID, COTTER, DAVID, ELLIS, ANDREW, DAVID
Applicants: BRITISH TELECOMM, COTTER DAVID, ELLIS ANDREW DAVID, BRITISH TELECOMMUNICATIONS PUBLIC LIMITED COMPANY, COTTER, DAVID, ELLIS, ANDREW, DAVID
Application year: 1999
Main classification: H04L7
IPC codes: H04B10, H04L7