Process of manufacturing electronic virtual ground memory devices

Abstract: A process for manufacturing electronic semiconductor integrated electronic memory devices having virtual ground and comprising at least a matrix of floating gate memory cells (1), the matrix being formed on a semiconductor substrate (2) with a plurality of continuous bit lines (10) extending across the substrate (2) as discrete parallel strips, comprising at least the following steps: forming an oxide layer (3) over the matrix region; depositing the semiconductor throughout with a stack structure which comprises a first conductor layer (4), first dielectric layer (5), and second conductor layer (6); forming a second dielectric layer (7); defining floating gate regions (13) by photolithography using a mask of "POLY1 along a first predetermined direction", and associated etching, to define, in said stack structure, a plurality of parallel openings (9); implanting said parallel openings (9) to confer a predetermined conductivity on the bit line (10) regions; filling the parallel openings (12) with a photo-sensitive material (11) to protect the matrix bit lines (10).

Description: Field of the Invention This invention relates to an improved process of manufacturing semiconductor integrated electronic virtual ground memory devices. Specifically, the invention relates to a process for manufacturing semiconductor integrated electronic memory devices having virtual ground and comprising at least a matrix of floating gate memory cells, the matrix being formed on a semiconductor substrate with a plurality of continuous bit lines extending across the substrate as discrete parallel strips. The invention relates, particularly but not exclusively, to a process for manufacturing semiconductor integrated electronic virtual ground memory devices, and throughout the following description, reference will be made to that technical field for convenience of illustration. Prior Art As is well known, electronic semiconductor-integrated EPROM or Flash EPROM memory devices comprise a plurality of non-volatile memory cells organized in matrix form; that is, the cells are arranged therein into rows, or word lines, and columns, or bit lines. Each non-volatile memory cell comprises a MOS transistor whose gate electrode, located above the channel region, is floating, i.e. has a high D.C. impedance to all the other terminals of the same cell and the circuit whereto the cell is incorporated. The cell also has a second electrode, the control gate, which is driven by means of appropriate control voltages. The other transistor electrodes are, as usual, the drain and source terminals. In recent years, considerable effort went to the development of memory devices with increased circuit density. This effort resulted in electrically programmable non-volatile memory matrices of the contactless type being developed which have a so-called "tablecloth" or crosspoint structure. An example of matrices of this kind, and their manufacturing process, is described in European Patent No. 0 573 728 to this Applicant. In matrices of this type, the matrix bit lines are formed in the substrate as continuous parallel diffusion strips. These matrices are formed by memory cells which comprise floating gate capacitive coupling MOS devices. The process flow for manufacturing such memory cells includes forming, on the semiconductor substrate, mutually parallel stack strips which comprise a first layer of gate oxide, first layer of polysilicon, second interpoly oxide layer, and second layer of polysilicon. An implantation step is then carried out to provide the bit lines, and after the deposition of a planarizing layer, the matrix word lines are formed. In the prior art, the gate regions of the individual cells are then defined by self-aligned etching. This first solution has several drawbacks in that the self-aligned etch step becomes the more critical, the smaller the cell size. The underlying technical problem of this invention is to provide a process for defining memory cells, arranged into matrices of the crosspoint type, which has such structural and functional features as to avoid the need for a critical gate region defining step, thereby overcoming the limitations and drawbacks which still beset the memory cells of prior art crosspoint matrices. Summary of the Invention The concept behind the invention according to claim 1 is one of fully defining each gate region of the matrix cells by means of an oxide island, before the matrix bit lines are defined. Based on the above concept, the technical problem is solved by a process as previously indicated and defined in the characterizing portion of Claim 1. The features and advantages of a device according to the invention will become apparent from the following description of an embodiment thereof, given by way of non-limitative example with reference to the accompanying drawings. Brief Description of the Drawings In the drawings: Figures 1 to 5 are perspective views showing schematically a portion of a semiconductor in the evolution of a first embodiment of the manufacturing process according to the invention; Figures 6 to 10 are perspective views showing schematically a portion of a semiconductor in the evolution of a second embodiment of the manufacturing process according to the invention. Detailed Description An improved process for manufacturing electronic memory devices integrated in a semiconductor substrate and comprising virtual ground cell matrices will be described with reference to the drawings. The process steps discussed hereinafter do not form a complete process flow for manufacturing integrated circuits. The present invention can be used with the integrated circuit manufacturing techniques currently employed in the art, and of the process steps commonly used, only such as are necessary for an understanding of the invention will be considered. Those Figures which show in perspective portions of an integrated circuit during their manufacturing are not drawn to scale, but rather to highlight important features of the invention. Accordingly, the description which follows will be limited to the definition of the memory matrix, without this being restrictive for the Applicant. To form memory cells with floating gate capacitive coupling MOS devices on a semiconductor substrate 2, the process flow should provide for a multiple deposition onto the entire semiconductor area in order to produce a stack structure comprising a first layer 3 of gate oxide, a first conductor layer 4 (also referred to as POLY1), a second interpoly dielectric layer 5, and a second conductor layer 6 (POLY CAP). Typically, the material used for the conductor layers 4 and 6 would be polysilicon, and the intermediate dielectric layer could be ONO (Oxide-Nitride-Oxide), for example. At this step of the process, the poly cap layer 6 can be doped. A protective dielectric layer 7, e.g. a so-called top oxide, is deposited on top of the poly cap layer 6. At this step of the manufacturing process according to the invention, bit lines 10 of the cell matrix are defined. A first mask 8 of resist, referred to as a mask for defining the Polyl along a first predetermined direction, is used to define the bit lines 10. The first mask 8 is shown in Figure 1. Using a conventional photolithographic step, the unprotected stack structure by the first mask 8 is then etched away in cascade to remove the protective oxide layer 7, second conductor layer 6, intermediate dielectric layer 5, first conductor layer 4, in that order. Advantageously, the gate oxide layer 3 is not removed from the substrate 2 surface during this etching step. A plurality of openings or grooves 9 have been defined in the stack structure at this step. An arsenic ion implantation, as necessary to provide N+ electric conductivity, allows the bit lines 10 to be defined through the openings 9. The first mask is then removed. The process is continued with the deposition of a photo-sensitive layer 11, such as a photoresist, into the grooves 9 of the matrix and on the semiconductor surface. By a conventional unmasked exposition step and subsequent removal of the surface layer of exposed resin, the photoresist is caused to fill the openings 9. This can be achieved by just focusing on the surface portion of the semiconductor during the exposition step. A second resist mask 12, referred to as a mask for defining the Polyl along a second predetermined direction, is used to define the gate regions 13 of the matrix cells. The second mask is shown in Figure 4. The unprotected stack structure by the second mask is cascade etched using a conventional photolithographic step to remove the protective oxide layer 7, second conductor layer 6, intermediate dielectric layer 5, first conductor layer 4, in that order. At this point, the substrate surface will appear as formed of a plurality of gate regions 13 of the matrix memory cells. The process for manufacturing virtual ground memory matrices progresses now through knownsteps to the skilled one. A second embodiment of the process according to the invention provides for multiple deposition over the entire area of the semiconductor, in order to provide a stack structure comprising a first gate oxide layer 3, first conductor layer 4 (also referred to as POLY1), second interpoly dielectric layer 5, and second conductor layer 6 (POLY CAP). Typically, the material used for the conductor layers 4 and 6 would be polysilicon, and the intermediate dielectric layer could be ONO (Oxide-Nitride-Oxide), for example. At this step of the process, the poly cap layer 6 can be doped. A protective dielectric layer 7, e.g. a so-called top oxide, is deposited on top of the poly cap layer 6. At this step of the manufacturing process according to the invention, a first mask 14 of resist, referred to as a mask for defining the Poly1 along a first predetermined direction, is used to define the oxide layer 7. The first mask 14 is shown in Figure 6. Using a conventional photolithographic step, the oxide layer 7 is subjected to etching, followed by removal of the first mask 14. A second resist mask, referred to as a mask for defining the polyl along a second predetermined direction, is used to define the bit lines 10 of the matrix. The unprotected stack structure by the second mask 15 is cascade etched using a conventional photolithographic step to remove the protective oxide layer 7, second conductor layer 6, intermediate dielectric layer 5, first conductor layer 4, in that order. Advantageously, the gate oxide layer 3 would not be removed from the substrate 2 surface during this etching step. A plurality of openings 9 will have been defined at this location in the stack structure. An arsenic ion implantation, as necessary to provide N+ electric conductivity, allows the bit lines 10 to be defined through the openings 9. The second mask 15 is then removed. The process is continued with the deposition of a photo-sensitive layer 11, such as a photo-sensitive resin, into the grooves 9 of the matrix. By a conventional unmasked exposition step and subsequent removal of the surface layer of exposed resin, the photo-sensitive resin is caused to fill the openings 9. This can be achieved by just focusing on the surface portion of the semiconductor during the exposition step. The unprotected stack structure by the second mask is cascade etched using a conventional photolithographic step to remove the protective oxide layer 7, second conductor layer 6, intermediate dielectric layer 5, first conductor layer 4, in that order. At this point, the substrate surface will appear as formed of a plurality of gate regions 13 of the matrix memory cells. The process for manufacturing virtual ground memory matrices progresses now through knownsteps to the skilled one. To summarize, the process of the invention allows the gate regions of the matrix cells to be defined using an oxide island for masking off and protecting the underlying layers, and utilizes a layer of photo-sensitive resin to protect the bit lines of the matrix. Furthermore, compared to the prior art, the self-aligned etch step for defining the gate regions of the matrix, which step becomes fairly critical as the geometric dimensions of the cell decrease, is now eliminated.

Claims: A process of manufacturing semiconductor integrated electronic virtual ground memory devices comprising at least a matrix of floating gate memory cells (1), the matrix being formed on a semiconductor substrate (2) with a plurality of continuous bit lines (10) extending across the substrate (2) as discrete parallel strips, comprising at least the following sequential steps: forming an oxide layer (3) over the matrix region; depositing on the semiconductor substrate a stack structure which comprises a first conductor layer (4), a first dielectric layer (5), and a second conductor layer (6), forming a second dielectric layer (7) over said stack structure; defining a first dimensions of floating gate regions (13) by photolithography using a first mask which is formed on said stack structure, and etching said stack structure, to define, in said stack structure, a plurality of parallel openings (9); implanting said parallel openings (9) to confer a predetermined conductivity on the bit line (10) regions; filling the parallel openings (9) with a photoresist material (11) to protect the matrix bit lines (10), photolithographing and etching, using a second mask (12) to define a second dimension of the plurality of floating gate regions (13) in said stack structure, and removing completely said photoresist material (11) such that the semiconductor substrate (2) surface comprises said plurality of gate regions (13) of the matrix memory cells. A process according to Claim 1, characterized in that : a photolithographic process using the second mask is applied subsequently to forming the dielectric layer (7); said dielectric layer (7) is etched away to define said plurality of parallel strips in the second direction. A process according to any of the preceding claims, characterized in that said second dimension is substantially orthogonal to the first dimension. A process according to any of the preceding claims, characterized in that said dielectric layer (7) is an oxide layer.

Inventors: BRAMBILLA CLAUDIO, CAPRARA PAOLO, CEREDA MANLIO SERGIO, IRANI RUSTON, POZZONI PIERANTONIO, BRAMBILLA, CLAUDIO, CAPRARA, PAOLO, CEREDA, MANLIO SERGIO, IRANI, RUSTON, POZZONI, PIERANTONIO
Applicants: ST MICROELECTRONICS SRL, WAFERSCALE INTEGRATION INC, STMICROELECTRONICS S.R.L., WAFER SCALE INTEGRATION, INC.
Application year: 1999
Main classification: H01L21
IPC codes: H01L21