WIRELESS SPREAD-SPECTRUM DATA NETWORK AND INTERFACE BETWEEN FIXED POSITIONS

Abstract: A wireless, high-capacity spread-spectrum data network, including an interface card that can be placed in a personal computer. The interface card is a wireless transceiver (108) for IP (Internet Protocol) routing to and from the personal computer, which is a host computer. The interface includes a RAM (152, Fig 5) that has a port for access by the host computer for retrieval of received data and baseband spread spectrum processor that provides a modulated transmitted signal and that demodulates received signals over a TDMA/FDMA data link. The interface card also includes a RAM controller (212, Fig 5) and a control processor, so that the host computer is not burdened with scheduling real time data transmitting and receiving. The system includes a head end coupled to a network such as Internet. The head end includes an antenna array that subdivides space into a number of independent sectors in which frequencies can be reused efficiently with orthogonal polarizations. Packets from individual remote end stations are delayed in accordance with their distance from the head end computer, and data packets are scheduled in accordance with the amount of traffic to be communicated.

Description: WIRELESS SPREAD-SPECTRUM DATA NETWORK AND INTERFACE BETWEEN FIXED POSITIONS Background of the Invention 1. Field of the Invention This invention relates to the field of data networks, and more particularly to devices and methods for replacing high-capacity cables with wireless spread- spectrum radio links between fixed positions. 2. Description of the Prior Art In an office local area network (LAN) , a network bridge is used to connect separate local and/or wide area networks into a single logical network, much like a roadway bridge can connect two physically separate land masses. For example, this network bridge is used in network topology to connect separate LANs when users are to share information (such as files or electronic mail, by way of example) , resources (such as file servers and printers, for example) , or both. If the separate networks are in the same building, the networks can generally be bridged using a physical cable. LANs of this type may use transmission media such as unshielded twisted pair, as typified by conventional telephone wiring. Other media are shielded multiple twisted pairs, coaxial cable, twinaxial cable, and fiber optic cable. However, it is often the case that the separate networks are not in the same building. In such cases, a typical solution for providing a network bridge has been to have a leased Tl line installed by the local telephone company dedicated to the network's connection needs, at a high monthly cost. As an alternative to a Tl line, radio communication links are known. For example, a CDMA/TDMA spread spectrum radio communication link is described in U.S. Patent No. 5,410,568 to Schilling. In this system, a base station time multiplexes a synchronization code signal and a first plurality of data signals, to generate a time-multiplexed signal, and then spreads the time multiplexed signal to generate a spread-spectrum time multiplexed signal. The remote units receive this signal and demultiplex data in the data stream to recover the signal being sent to it. The remote units each send signals to the base station during specified times. The remote unit does not transmit and receive at the same time. However, the Schilling system is directed to a voice communication system, however, so there is no provision to adjust the bandwidth of the data being communicated to and from remote units. Moreover, no implementation of a computer interface card is provided, and the input and output of the system at the remote station is an analog signal rather than digital network data or IP data packets. Because the system disclosed in Schilling is directed to a mobile cellular communication system, there are no adaptations for its implementation in a wide area wireless computer network. Gold et al., U.S. Patent No. 5,488,631 describes a wireless spread spectrum time-division multiple access (TDMA) communication system providing digital communications between pairs of remote units among a plurality of remote units organized into a communication network by a master unit that authorizes, schedules, and controls all network transmissions. This system provides a transceiver device adapted for a personal computer, and the master unit and remote unit have identical circuitry. However, there is no suggestion of a segmented antenna at a head end station to serve fixed units in different regions of space, and a master unit controls communication between remote unit initiators and remote unit receivers. Once the master unit has designated a particular remote unit to become a remote unit initiator and another to become a remote unit receiver, all other network remote units continue to listen to transaction headers even though they will not be participants during a transaction cycle. It is possible for the system to be used in client- server applications, where the clients send messages to the master unit. However, whether the system is used in a client-server application or for control direct remote unit to remote unit communication, there is no provision to delay transmission from the remote units in accordance with a propagation characteristic of the master unit- remote unit wireless link, so that the master unit must synchronize each time to requests from the remote units. Furthermore, there is no polling of remote units, so two remote units could send a request for transmission time simultaneously, resulting in data collisions. Also, once a remote link is established, it is maintained and may be kept open for as long as the remote unit needs it. The bandwidth available to the remote units therefore may not be directly controlled by the master unit. Barratt et al., U.S. Patent No. 5,592,490 describes a spectrally efficient high capacity wireless communication system. The system uses antenna arrays and signal processing to separate combinations of received uplink signals, and transmits spatially multiplexed downlink signals. Capacity is increased by allowing multiple users to share the same conventional communication channel within a spatial cell without interfering with one another. The system can use frequency division or time division multiplex access. The system behaves much like a standard wireless communication system base station, except that it supports more simultaneous communications channels than it has conventional communication channels by allowing multiple spatial channels on each of the conventional channels. The system as described does not support varying the bandwidth allocated by a base station in response to polling of remote stations or the timing of such transmissions within successive TDMA/TDD frames. Instead, conventional two-way communication channels are allocated by the base station. Although there is an embodiment briefly described for applications involving data transfer of short bursts or packets of data, this embodiment is described as not requiring an uplink control channel, and the system may service requests for communication and other control functions during control time intervals that are interspersed with communications intervals. Thus, there is no orderly polling of the remote stations to determine whether there is traffic from each remote station. Instead, the remote stations must, as with the conventional two-way communications channel, compete with one another during a control time slot to send initiation requests that may possibly collide. Ahl et al., U.S. Patent No. 5,313,461, describes a scheme in which a time period, or frame, is divided into a number of shorter periods, or time slices. Each time slice is of uniform length. Channels communicating through the communications system occupy some portion of one or more time slices or slots. A control package sent from a central station to one or more peripheral stations conveys to the peripheral stations the time slot during which each channel has been allocated. When traffic on one or more channels is sparse, information associated with another channel can be transferred during the sparse channels time slot. However, it is apparently necessary for the time slices to consist of constant burst lengths. Alternately, if varying burst lengths are transmitted, no system is described for maintaining synchronization when the varying length signals are transmitted in the system. Moreover, Ahl et al. does not describe the structure of a suitable PC-based network interface card for use at the base station or remote stations of the network. Also, Fig. 24 of Ahl et al. shows that a separate signal channel may be required to request a connection, and other embodiments described in Ahl et al . seem to require analysis of the transmitted data packets on the fly to determine their bandwidth requirements. Ahl et al. does not describe a system in which orderly polling of remote units to determine their traffic needs occurs. In addition, the connection of remote continues until a number of consecutive samples indicates that information no longer has to be transferred. It would therefore be desirable to provide a PC- based radio network interface that provided real-time spread spectrum network synchronization between a head end station and at least one, but desirably multiple remote stations. It would further be desirable to provide such a network card that required little, if any, modification for use either at the head end or at the remote end, to reduce manufacturing costs. It would further be desirable to provide a wireless communication system, using such cards, that can act as a "wireless IP router, " to provide wide network connectivity at a fraction of the cost of a typical leased Tl trunk. It would also be desirable to provide a wireless communication system in which remote stations are polled in an orderly fashion to determine their bandwidth requirements. BRIEF DESCRIPTION OF THE INVENTION The wireless data communication system described herein can be viewed, in standard network terms, as a "wireless IP router." From a user point of view, the system is accessed as an IP (Internet Protocol) gateway to the wireless network. Once a connection is established, packets are routed to their final destination as with any wire-based system. In a preferred embodiment, a plurality of users' LANs (local area networks) within an approximately 20 mile radius of a central antenna system are connected to each other and/or a network such as the Internet at rates of up to 4 MBPS at a fraction of the cost of conventional "wired" technology. The system may be used, with additional head end locations in multiple cities, to connect user networks on an intercity and interstate basis in a high- speed private network. Spread spectrum and frequency agile technology is used to transmit data wirelessly and securely. At the user end, the system includes a small computer/router, data cables, and a (preferably) roof- mounted antenna. The computer/router can be attached to the user's LAN or workstation via a connection such as a standard lOBaseT connection, and establishes a TCP/IP connection to the central head end antenna. The user or remote antenna must be oriented towards the head end antenna, but a precise line-of-sight path, while desirable, is not necessary. The system is ideal for multi-location businesses within a metropolitan area to inexpensively create a high-speed wireless wide area network (WAN) . Internet access, PC-based video conferencing and document sharing, and telecommuting are but some of its possible uses. Speeds almost 3 times higher than standard Tl lines are possible in the preferred embodiment at a fraction of the cost of microwave, laser, ATM, or Tl lines, and a full- time, permanent virtual connection may be provided. Even higher speeds could be achieved in frequency bands in which different modulation formats, such as QAM (quadrature amplitude modulation) , are permitted. Standard network protocols and operating systems can easily be supported, and security is provided through digital spread spectrum modulation techniques. The system is bi-synchronous (unlike VSAT, cable, and ADSL services), and independent of existing infrastructure. Part of the hardware for the wireless communication system can be assembled using hardware as simple and common as ordinary personal computers (PCs) . In a preferred embodiment, the LINUX® operating system is to control the PC, which is configured with a typical ethernet NIC (network interface card) , which is configured as a port of the user's wired network. In addition, the PC has one or more inventive interface cards that act as a secondary NIC to the wireless network. The LINUX® operating system performs the gateway/routing service to properly route packets. The inventive interface cards each interface to an RF transceiver that is mounted at an antenna. In accordance with a first aspect of the invention, there is thus provided a digital wireless communication system for interconnecting a plurality of spatially separated, remote end computers to a head end computer, said system comprising a fixed head end computer and a plurality of fixed remote end computers, each of said computers having a transceiver for communicating digital data in spread spectrum format, said head end computer being connected to a spatially arrayed antenna through which its transceiver communicates said digital data to and from said remote end computers. The head end computer may be configured for assigning a communication bandwidth to each of the remote end computers and for controlling the transmission of data to and from the head end computer with each of the remote end computers. The spatially arrayed antenna may be segmented into a plurality of directional sectors, wherein each of the remote end computers may be located in one of the directional sectors, and the head end computer may assign a frequency, a time for commencing transmission"Of data, and an allotted time for data to be transmitted. The head end computer may also be configured to synchronize data being communicated between the head end computer and each of the remote end computers. In accordance with another aspect of the invention, there is provided a wireless interface for IP routing of data packets to and from a host computer through a wireless link, the wireless interface comprising: a wireless transceiver; a buffer memory coupled to the host computer and the wireless transceiver for receiving data packets received from the wireless transceiver and data packets from the host computer to be transmitted through the wireless transceiver; and a controller operatively coupled to the wireless transceiver and the buffer memory for timing transmission of data packets to be transmitted and the reception of data packets from the wireless transceiver in accordance with control data received from a head end computer communicating with the host computer through the wireless transceiver. The buffer memory and controller may be on an indoor unit configured for mounting in the host computer, while at least a portion of the wireless transceiver may be configured to be separable from the interface card in an outdoor unit. Both the indoor unit and the outdoor unit may comprise frequency converters; and the indoor unit and the outdoor unit may communicate the received data packets and data packets to be transmitted to and from one another over an intermediate frequency. The intermediate frequency link may be duplexed to provide a DC power path from the indoor unit to the outdoor unit. The intermediate frequency link may be a time-division duplex link so that transmission of data from the indoor unit to the outdoor unit and transmission of data from the outdoor unit to the indoor unit occur at different times. The device may also comprise a digital spread spectrum processor operatively coupled to the wireless transceiver, the buffer memory, and the controller for spreading and despreading data packets communicated through the wireless transceiver. In accordance with still another aspect of the invention, there is provided a device for communication of data via a wireless link, said device comprising a host computer and a communication interface, in which the communication interface comprises a communication processor; shared memory operatively coupled between the communication processor and the host computer so that the communication processor and the host computer can separately and asynchronously access data packets in the shared memory; and a wireless transceiver coupled to the communication processor for transmission of data packets stored in the shared memory and reception of data packets over a wireless link for storing in the shared memory and subsequent transfer to the host computer. The wireless transceiver may be a spread spectrum wireless transceiver, and may be a TDMA/TDD transceiver. The communication processor may be configured for scheduling transmission of data packets stored in the shared memory in accordance with TDMA/TDD frame timing. The communications processor may be configured to delay transmission of data packets in accordance with a propagation delay characteristic of the wireless link. In accordance with yet another aspect of the invention, there is provided a wireless transceiver interface for IP routing to and from a host computer through a wireless link, the transceiver comprising: random access memory (RAM) accessible by the host computer for retrieval of received data; a signal processor demodulating a stream of received data from the wireless link and having a data input for modulating a signal for transmission over the wireless link; a logic array configured to receive demodulated data from the signal processor and storage locations from the host computer, the logic array also being configured to store the demodulated data in the RAM in accordance with the storage locations received from the host computer; and a controller configured to receive data from the host computer and to construct transmit packets therefrom in the RAM at selected addresses therein; the logic array and signal processor also being configured to retrieve and transmit the transmit packets over the wireless link during specified time periods. The wireless transceiver may also comprise an outdoor unit coupled to the baseband digital signal processor for transmitting a signal from the baseband digital signal processor to a remote station. Also provided, in accordance with still another aspect of the invention, is a method of communicating digital data between computers comprising the steps of subdividing space around a head end computer into a plurality of independent sectors served by separate directional antennas of the head end computer; communicating data, via TDMA/FDMA channels, with remote end computers over wireless links served by the separate directional antennas; routing data received by the head end computer to a computer network; and routing data received from the computer network to the remote end computers in accordance with a specified address. The communicating step may comprise spreading communicated data with a spread spectrum modulation sequence. In addition, poll responses may be transmitted from each of the remote end computers to the head end computer, and schedules for transmitting data from each of the remote end computers to the head end computer may be transmitted from the head end computer to each of the remote end computers in response to the poll responses . It is thus an object of the invention to provide a PC-based radio network interface that provides real-time spread spectrum network synchronization between a head end station and at least one, but desirably multiple, spatially arrayed remote stations. It is a further object of the invention to provide a network card that requires little, if any, modification for use either at the head end or at the remote end, to reduce manufacturing costs. It is yet another object of the invention to provide a wireless communication system, using such cards, that can act as a "wireless IP router, " to provide wide network connectivity at a fraction of the cost of a typical leased Tl trunk. It is still another object of the invention to provide a communication system in which remote stations are polled in an orderly fashion to determine their immediate bandwidth requirements. These and other objects of the invention will become clear to those skilled in the art upon reading and studying the detailed description below in conjunction with the drawings. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a simplified block diagram representing a typical installation of a wireless data communications system in accordance with one aspect of the invention; Fig. 2 is a drawing of a multisector antenna for a typical head end unit in accordance with the invention; Fig. 3 is a representation of traffic over a communications channel showing guard bands, transmission of control data, head end transmit data, and various response slots from the remote units, Fig. 4 is a functional block diagram of an outdoor unit (i.e., RF unit) suitable for use with this invention; Fig. 5 is a functional block diagram of an indoor unit for use with the outdoor unit of Fig. 4, the indoor unit performing the function of a network interface card and suitable for use with a personal computer (PC) ; Fig. 6 is a functional block diagram of an electrically programmable logic device (EPLD) as it may be programmed for use in the indoor unit of Fig. 5 when the indoor unit is to be installed in the head end, with only minor modifications being required for use when the indoor unit is to be installed at a remote end; Fig. 7 is a flow chart of software in the head end that loads the head end driver; Fig. 8 is a flow chart of the head end driver system timing software; Fig. 9 is a flow chart of the portion of the head end driver system software that interprets and implements various IOCTL commands from the operating system; Fig. 10 is a flow chart of the portion of the head end driver system software that sends a data packet upon receipt of a command from the operating system; Fig. 11 is a flow chart of the portion of the head end driver system software that processes hardware interrupts; Fig. 12 is a flow chart of software in the remote end that loads the remote end driver; Fig. 13 is a flow chart of the remote end driver system timing software; Fig. 14 is a flow chart of the portion of the remote end driver system software that interprets and implements various IOCTL commands from the operating system; Fig. 15 is a flow chart of the portion of the remote end driver system software that sends a data packet upon receipt of a command from the operating system; Fig. 16 is a flow chart of the portion of the remote end driver system software that processes hardware interrupts; Fig. 17 is a flow chart of the head end interface card software; and Fig. 18 is a flow chart of the remote end interface software. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT As used herein, the term "cycle" is sometimes used interchangeably with "frame," in contexts in which the equivalence will be apparent to one of ordinary skill in the art. The use of the term "cycle" merely serves to emphasize that frame timing occurs on a regular, cyclical basis. Fig. 1 illustrates a typical installation of a wireless data communications system in accordance with the invention. In this particular example, two remote stations are shown at buildings Bl and B2. It should be understood, however, that two remote stations are shown only for purposes of explanation, and that one or more remote stations (up to a limit to be described later) , which may not necessarily all be located at different buildings, may be accommodated by a base station. Directional antennas AN1, AN2 of the remote stations are mounted at a point on buildings Bl, B2 in such a way that there is provided a reliable radio path, to a central station having an antenna AN3 mounted on a building B3. (The location of the base station is usually different from that of the remote stations, but it is possible to accommodate a remote station in the same building.) Antennas AN1 and AN2 are directional antennas, and AN3 preferably comprises a plurality of separately directed antennas, as is explained later. Radio signals are sent between Bl and B3, and between B2 and B3, via microwave radiation. Direct sequence spread spectrum modulation is used to send data over the air. This type of modulation is known to withstand jamming, interference, and eavesdropping, and can be used in conjunction with encryption schemes as an optional feature. In addition, the use of spread spectrum modulation makes the signal quality immune to most static, noise, and other types of common interference, including weather problems, surface reflections, and so forth. As such, the paths between AN1 and AN3, and between AN2 and AN3 need not be exact "line-of-sight" paths, although such paths may enhance the performance of the system in some cases. A multisector antenna for a typical head end unit in accordance with the invention is shown in Fig. 2. Antenna ANT comprises a plurality of individual antennas 104 that are described in more detail below. These antennas are spaced in an array that provides 30° sectors (i.e., roughly pie-shaped sectors around the antenna) to have essentially independent communications paths. The antennas are selected to allow transmission at a frequency and in a bandwidth consistent with FCC and/or other regulatory requirements, with reuse of the same frequency being possible at least within adjacent sectors by employing orthogonally polarized antenna elements in adjacent sectors. Fig. 3 is a representation of data timing across one of the communication channels, i.e., one channel out of the multiplicity of channels at different frequencies (and/or different polarizations) , which is located in one geographic sector out of the multiplicity of geographic sectors served by the head end. The times are given in microseconds. Starting at the left of the figure, the head end starts transmitting the header two microseconds from time 0. This delay allows for the set-up times necessary to allow system hardware, more specifically, an FPGA (a Field Programmable Gate Array, to be described later) , to convert data streams between serial and parallel formats. Next, 96 microseconds is used to transmit a header from the head end station to the remote end stations for synchronization and error checking purposes. The head end station then transmits control data for the next 64 microseconds. In a preferred embodiment, a 44 MHz clock provides a 22 MBPS chip rate spreading sequence, which modulates QPSK data transmitted at a 2 MBPS symbol rate. The resulting bit rate is 4 MBPS, which corresponds to a data transmission rate of one byte every two microseconds . The control data is followed by a transmission gap (or guard band) of 96 microseconds that ends 258 microseconds from the start of the head end transmit period. This gap is followed by another header of 96 microseconds, followed by data transmitted by the head end to the remote ends. This data is of unspecified length, but is not longer than 3544 microseconds in this embodiment, or more generally, not longer than to the end of the head end transmit period, because a different head end transmit period length may be selected for different embodiments. The actual data length depends upon the amount of user data that is ready for transmission. The receive window starts with a gap of 256 microseconds to account for minimum transmission delays from the head end to the subscriber, and to allow the head end receiver time to turn on following the head end transmission. This is followed transmission, from a remote end to the head end, of a header of 96 microseconds, followed by data of unspecified length, but no longer than 3574 microseconds in this embodiment. The actual amount of data will vary depending upon the amount of traffic to be sent from a subscriber to the network. This data is followed by a gap until a time 7824 microseconds from the beginning of the head end transmit period is reached. The remaining time before 7992 microseconds after the beginning of the head end transmit period is used for transmission of a header from the remote end station (96 microseconds long) followed by a poll response from the remote end station to the head end. The poll response in this embodiment is 32 bytes long. Finally, a 40 microsecond gap occurs before the end of the head end receive period, and the beginning of the next head end transmit period. The reader should note that the data and poll responses in any particular frame need not necessarily be from the same remote user, and no such constraint is imposed by the system. It should be noted that, while the lengths of the headers may be dictated by the requirements of the hardware and synchronization systems used in the system, it is possible to vary the data periods over rather wide ranges to accommodate various system requirements for any particular installation. For example, either or both of the head end transmit periods and the head end receive period could be shortened or lengthened, depending upon the expected system traffic and acceptable time delays. Also, the gap lengths could be adjusted, provided that there is sufficient guard band space to accommodate the range of distances and propagation delays to and from the various remote end stations. However, an important feature of the system is that it is a TDD/TDMA system (time division duplex/time division multiple access system) dividing an arbitrary length of time into outbound and inbound time windows that do not vary from cycle to cycle. The windows can be optimized for the number and sizes of packets to be communicated, the distances of the stations from one another, etc. The return path to the head end (i.e., the inbound time window) is a TDMA return path that is or can be shared by a number of different stations. It is even possible, but not necessary, for each head end receive period to be divided so that more than one remote end station transmits headers followed by data to the head end station. Data packet lengths may be variable within the selected system limits, while control packet sizes will vary depending upon the number of users. However, every packet will require at least about 42 bytes of data to accommodate system overhead if the preferred hardware is used, except for "dummy" data packets, which in the preferred embodiment are only 12 bytes, with no overhead required. In any event, it is preferred (and required, for synchronization purposes, in the preferred embodiment described herein) that only one poll response be sent by a remote end station per head end receive period, and that the poll responses be sent by remote end stations in "round robin" sequence, from station to station. Also, if there is no other data to be transmitted by the head end during any head end transmit period, the system requires that a "dummy" packet be transmitted so that the remote end stations can maintain synchronization. Also, gaps in the head end receive period are required to accommodate propagation delays for subscribers of varying distances from the head end, so that each subscriber (i.e., remote end transmitter) appears, at the head end, to respond at the same time. To accommodate propagation delays, the remote end has a fixed delay programmed into its radio interface card that depends upon the distance of its antenna from the head end transmitter antenna. The fixed delay is programmable on a user-by-user basis, and is, in a preferred embodiment, programmable via the wireless links. Once programmed, unless system timing is changed, a user's fixed propagation delay need not be programmed again unless the distance between the remote unit and the base station changes. The total propagation delay must take into account the total round trip distance. In a preferred embodiment of the inventive system, a remote unit co-located with the head end transmitter would insert a response delay of 256 microseconds. As the remote end unit is placed further away from the head end transmitter, more of this delay would be used in the propagation path, so the remote end unit would be programmed with a corresponding fixed delay that was 256 microseconds minus the round-trip propagation delay. This system could accommodate remote units up to almost 24 miles distant from the head end. Propagation delays are handled by determining the distance between the head end and each remote end station, and accounting for the transmission delays by building in fixed delay values that vary from remote station to remote station. These delay values, together with the guard bands that are provided, provide an orderly flow of data over the radio channels. It should be understood that although exact times, bit rates, and byte counts are given here, the selected values are for a preferred embodiment operating at approximately 2.5 GHz, with data rates selected for presently-available off-the-shelf spread spectrum integrated circuit components, and networks of the type commonly used today. Those skilled in the art would be able to select somewhat different parameters and yet still construct a working system. In particular, it is anticipated that at least data rates may increase in the future, and that off-the-shelf spread spectrum components will improve in the future. The timing shown in Fig. 3 should also be suitable for wider bandwidth and higher data rate systems, although it could be adjusted as needed. However, the propagation delay is set by physical laws for which there are no known methods of circumvention at present. One important feature of the invention is that variable transmission packet sizes are provided for, in this combined TDMA/FDMA data system. In a preferred embodiment, a head end station may be controlled by an application program running on a computer, such as a typical personal computer. Because there is no special requirement that the controlling application program be written in any particular programming language, flow charts are provided here to explain the functions of this program. A programmer having ordinary skill in the art and using ordinary programming techniques, without any undue experimentation or any inventive capacity, may select a suitable language, such as the C programming language, and write the code needed in that language to implement the program by referencing these flow charts. It will be observed that certain features of the program are expressed in the flow charts in a manner particularly appropriate for implementation on a PC (personal computer) or PC- compatible computer system running the LINUX® operating system. (LINUX® is a registered trademark of Mr. Linus Torvalds, Santa Clara, California.) The LINUX® operating system is a freely redistributable operating system similar to the UNIX® operating system. (UNIX® is a registered trademark of Novell, Inc. of Provo, Utah.) However, the LINUX® operating system is freely available by downloading over the Internet. Several commercially supported versions of the LINUX® operating system are also available, such as RED HAT® LINUX® software from Red Hat Software, Research Triangle Park, NC. (RED HAT® is a registered trademark of RED HAT SOFTWARE, INC., DURHAM, NC.) The commercial versions also include much additional software and other materials that are not necessary to practice this invention. The RED HAT® LINUX® operating system versions 4.2 and 5.1 have been successfully tested for this application. A hardware platform that is more than sufficient for the head end driver software is a 75 MHz PENTIUM® processor-based PC-compatible computer having at least 4 MB of RAM and sufficient hard disk memory to hold the operating system, the driver program, and optionally, either or both of an error log or an accounting log. (PENTIUM® is a registered trademark of Intel Corporation, Santa Clara, CA. ) Optionally, error log and/or accounting log entries may be sent through a network or via modem or other connection to another computer, or to a local or remote printer or display. All or a portion of the head end driver and operating system may also be placed in ROM, thereby reducing or eliminating the need for hard disk memory. It will be apparent to a programmer that most modern operating systems, including the popular WINDOWS® operating systems of Microsoft Corp., Redmond WA could serve as a suitable platform for the control program as an alternative to the LINUX® operating system. Any minor modifications needed for the control program to accommodate such alternate operating systems would be well within the range of skill of a typical programmer familiar with the target operating system. However, the LINUX® operating system has proven reliable. Also, source code for the LINUX® operating system is freely available and widely distributed, facilitating debugging and maintenance of the application, and allowing portions of the operating system not required for the head end driver to be stripped out. It is ' estimated that the entire head end driver system software could be reduced to fit into about 20 MB of ROM if the operating system were stripped in this manner. The outdoor unit includes an antenna and certain radio receiving and transmitting functions. Other radio receiving and transmitting functions are performed on an interface card that is installed in the remote unit or at the head end. Because of the design of the system, the interface card for the head end and the remote unit can be identical, to save costs, simplify the system, and reduce inventory maintenance requirements. The names "outdoor unit" and "indoor unit" should be taken as descriptive rather than limiting. The term "outdoor unit" derives from the fact that this unit is preferably mounted outdoors for the best line-of-sight communication path between buildings. However, it will be recognized that indoor mounting may be sufficient in at least some cases, depending upon propagation conditions and distances. Also, although the "indoor unit" most likely will be located indoors, it could conceivably be placed outdoors. A functional block diagram of an outdoor unit 100 suitable for use with the invention is shown in Fig. 4. Detailed design at the component level based upon this diagram and the accompanying description would be a routine task for one skilled in the art, as would detailed design based upon the other functional block diagrams and descriptions. To the extent that they are not described herein, such low level implementation details are not considered part of the invention. Outdoor unit 100 includes a directional, polarized antenna 104, which, in a preferred embodiment, may be a CONIFER® QD5430 Microscepter Antenna available from Conifer Corporation, Burlington, IA. This antenna is a linearly polarized, planar array providing 16 dB gain, a 3 dB beamwidth of 30°, and 30 dB crosspolarization isolation at (approximately) 2.455 GHz, which is a suitable center frequency for this system. Because the antenna provides narrow beamwidth and high crosspolarization isolation, it is possible and practical to reuse the same frequency at different polarizations in adjacent 30° sectors. It is more difficult, but not impossible, to reuse the same frequency even in the same sector, through the use of orthogonal polarizations. However, the interfering signals will then be in the main beam of the affected antennas, and distances between the stations and power levels will have to be more carefully coordinated to avoid interference and measurable increases in bit error rate. Antenna 104 is connected to an LNA/PA (low noise amplifier/power amplifier) 108 though a band pass filter 106. Band pass filter 106 is, in a preferred embodiment, a 100 MHz, 3-pole filter having a 2.455 GHz center frequency. This bandwidth is sufficiently wide to pass the entire 86 MHz bandwidth of interest without significant distortion. LNA/PA 108 is preferably a CAS2403AN 2.4 to 2.5 GHz Power Amplifier-T/R Switch available from Celeritek, Inc., Santa Clara, CA. This device includes a low noise receiver preamplifier 110, a transmitter power amplifier 112, and a transmit/receive switch 114 for connecting the antenna to an appropriate one of preamplifier 110 and power amplifier 112. The output of low noise amplifier 110 is filtered by band pass filter 114, which in a preferred embodiment has the same characteristics as band pass filter 106 to thereby provide further selectivity without degrading the receiver noise figure or bit error rate. The input to power amplifier 112, i.e., signals to be amplified and transmitted over the radio link, is also filtered through a separate filter 116 that also preferably has the same characteristics as band pass filter 106. The LNA/PA provides a switched function allowing the weak signal received by the antenna to be amplified to a suitable level. When transmission is desired, LNA 110 is switched off and the PA 112 is turned on to amplify the signal to a level of 4 watts EIRP, including an antenna gain of about 17 dB. Working backwards in the receive path, a mixer 120 converts the received signal down to a suitable intermediate frequency, which, in a preferred embodiment, is approximately 280 MHz. The frequency of the local oscillator 126 is thus approximately 2.2 GHz in this embodiment, but this varies depending upon which of the channels within the total system bandwidth is selected for communication. The frequency of this oscillator can be controlled using a PLL controller (i.e., frequency synthesizer) 136, such as a MOTOROLA® MC12210 2.5 GHz bipolar monolithic serial input phase locked loop (PLL) synthesizer, available from Motorola, Inc., Schaumburg, IL. The implementation details of PLL frequency synthesis are by now well-known and are adequately described in manufacturers' application notes and other publications. Therefore, these details are omitted from the block diagram of Fig. 4. However, it is noted that the PLL controller receives serial data from the ISA card (i.e., indoor unit 102 of Fig. 5, to be described below), and directs the on-board oscillator 126 to a desired frequency. This PLL makes use of a 16.384 MHz reference as its time base, and receives serial frequency data on line FRS from the indoor unit. (Control for switching switches 114 and 132 are also received over a line SWC from the indoor unit.) The output of the mixer is filtered in a preferred embodiment through a 280 MHz center frequency band pass filter 128 having a 3 dB band width of 20 MHz (i.e., the passband is 280 MHz ± 10 MHz.) A transmit/receive switch (T/R switch) 132 sends the output of filter 128 back to indoor unit 102 during receive time intervals. It is a coaxial cable with suitable connectors may be used as a transmission line 134 for this purpose. The same transmission line 134 is used to transfer signals from indoor unit 102 to outdoor unit 100 during transmission times, using T/R switch 132. When this occurs, T/R switch 132 causes the signal sent from indoor unit 102 to outdoor unit 100 to be sent through band pass filter 130 and up-converted by mixer 124 using local oscillator 126. Band pass filter 130 preferably has the same characteristics as band pass filter 128. By using the same mixer 126 for up-conversion of the transmitted signal as is used for down-converting the received signal, transmission and reception on the same selected band of frequencies within the system bandwidth is accomplished automatically. The output of mixer 124 is fed into a driver amplifier 122, and the output of the driver amplifier is fed into band pass filter 116 to remove unwanted mixing components. The remaining circuit path to the antenna includes power amplifier 112, T/R switch 114, band pass filter 106, and antenna 104, all of which have been described above. Mixers 120 and 124, along with driver amp 122, may be provided as a single up/down converter component, the CCV2501AN 2.4 to 2.5 GHz Integrated Converter, available from Celeritek, Inc., Santa Clara, CA. The up/down converter translates the 280 MHz signal to the desired final output frequency in the 2.4 GHz ISM band. This is a single conversion operation and is half-duplex in nature due to the TDD format. It thus will be seen that the outdoor unit provides at least part of the functions of a wireless transceiver. The functional features of indoor unit 102 will now be described. A functional block diagram of indoor unit 102 is shown in Fig. 5. Unit 102 functionally comprises a PC ISA interface that maps the proper signals from the ISA card to the PC's ISA bus 194. In a preferred embodiment, the indoor unit card 102 occupies 32 locations of I/O address space and 8 K bytes of memory space. An example of I/O mapping is 300H - 31FH for I/O and 0D000H to 0D7FFH for memory space. In a preferred embodiment, the PC ISA interface is part of a Field Programmable Gate Array (FPGA, also known as an Electrically Programmable Logic Device or EPLD) 154. Some of the logical functions of FPGA 154 are shown in Fig. 5, but a more detailed view is shown in Fig. 6, to be described below. Returning to Fig. 5, a shared RAM controller 212 is also shown, and this is also preferably part of FPGA 154. Shared RAM controller 212 formats serial data received from a spread spectrum signal processor 156 into a shared RAM 152 in byte format. Although the system driver specifies the location for this data, the actual storage is controlled by the shared RAM controller 212. Since the shared RAM 152 is a dual- port device, simultaneous reading and writing can occur by the shared RAM controller as well as the PC through the ISA bus. The shared RAM 152 is controlled by a controller 212, which is preferably part of EPLD 154. Various registers in the spread spectrum processor 156 as well as the I/O and memory mapping locations are programmed by an on-board processor or controller 150. This processor also receives frequency change information and programs PLL synthesizer 136 in the outdoor unit 100 accordingly, through frequency select line FRS. Since the header messages in the serial data stream contain type and length messages, processor 150 monitors realtime activity and pre-loads these values into the spread spectrum processor 156 to relieve this function from the PC. The data flow will be explained in more detail in a later section describing Fig. 6. Indoor unit 102 also includes IF amplifiers and filters, shown in an integrated unit 158. The 280 MHz signal received from outdoor unit 100 is filtered and amplified on the indoor unit 102 ISA card. Since the signal transmits for a period of time and receives for a period of time (i.e., it is time-division duplexed, or TDD) , the IF amplifiers include transmit and receive paths that either drives or is driven by a switch 160, which is controlled by line SWC from DSP 156. An IF to baseband converter within integrated unit 158 takes the 280 MHz signal and down-converts the signal to baseband using identical active mixers and switched capacitor filters. The local oscillator (LO) 164 is derived from a 2 x 280 = 560 MHz source, and phase locked to a 44 MHz reference that also drives the spread spectrum processor 156. The LO 164 is divided and split to provide a quadrature source for the downconversion. Indoor unit 102 also provides a data formatter/timing generator as part of EPLD 154. A time reference is established, and the driver program preloads the time values, length and memory locations for the data packets so that all real time functions are removed from the driver program. Indoor unit 102, described in greater detail, thus comprises a controller 150, random access memory (preferably static RAM) 152, an electrically programmable logic device 154, a base band spread spectrum processor 156, and an intermediate frequency (IF) amplifier/downconverter and upconverter/modulator 158. Controller 150 may be an INTEL® 80C196 microcontroller, available from Intel Corp., Santa Clara, CA. This processor includes 256 bytes of internal static RAM. Logic element 154 may be a XILINX® XCS40 FPGA (Field Programmable Gate Array) available from Xilinx, Inc., San Jose, CA. The functionality and programming of logic device 154 varies slightly depending upon whether the indoor unit 102 is to be placed inside a remote unit or a head end unit. The required functionality of this device is shown in detail in Fig. 6. Slight differences may exist from this figure, depending upon whether the indoor unit 102 is intended to be installed at the head end or at a remote end, respectively, as will be explained in a subsequent section. Returning to Fig. 4, base band spread spectrum processor 156 is preferably a HARRIS® HFA3824A or HFA3860 Direct Sequence Spread Spectrum Baseband Processor, available from Harris Semiconductor, Melbourne, FL. These devices contain all the functions necessary for a full or half duplex packet base band transceiver. Intermediate frequency (IF) amplifier/downconverter and upconverter/modulator 158 is preferably a HARRIS® HFA3724 400 MHz Quadrature IF Modulator/Demodulator, available from Harris Semiconductor, Melbourne, FL. Considering first, and tracing the path of the received signal from outdoor unit 100, a T/R switch 160 connected to transmission line 134 from outdoor unit 100 routes received signals through IF amplifier 162 of IF amplifier/downconverter and upconverter modulator 158, which hereinafter shall be referred to as IF modem 158. An oscillator 164, which in this implementation operates at precisely 560 MHz, and which is set by frequency synthesizer 190 under control of controller 150 (using a synthesizer interface 196) for the sake of economy. This synthesizer also provides a 44 MHz reference 192, which is used by spread spectrum processor 156. This use is adequately described in the documentation of the preferred HARRIS® integrated circuits, and is neither shown nor described here. The output of IF amplifier 162 is downconverted by mixers 168 and 170, which receive in-phase (I) and quadrature (Q) frequency components of the oscillator from phase shifter 166. The I and Q components of the converted signals are filtered by base band filters 172 and 174, respectively, which are internal to the HARRIS® IF modem 158, as indicated by the dashed lines. The filtered I and Q signals are applied to base band spread spectrum processor 156 for further input processing. Spread spectrum output signals are provided by base band spread spectrum processor 156 as I and Q signals, which are amplified by amplifiers 176 and 178, respectively, and filtered by base band filters 180 and 182 respectively. The signals are then up-converted by mixers 184 and 186, respectively, combined, and then amplified by IF amplifier 188, which sends the IF signal back up to the outdoor unit 102 through transmission line 134 when T/R switch 160 is set for transmission in that direction. It will be observed that transmission line 134 carries only relatively low intermediate frequency (IF) signals, rather than the higher frequencies actually transmitted and received. This allows longer separations between the indoor and outdoor units than would otherwise be possible if the transmission between the units were at the actual transmit/receive frequency. The use of the IF frequency for this purpose also avoids the need for a pair of cables that would otherwise be required for the I and Q channels if the transmission between the indoor and outdoor units were at base band. Also, the use of IF signals rather than base band signals permits the single cable 134 to supply DC power supply voltages to the outdoor unit using a simple diplexor to remove DC voltages from the IF signal paths. Fig. 6 is a functional block diagram of an electrically programmable logic device (EPLD) as it may be programmed for use in the indoor unit portion of Fig. 4 when the indoor unit is to be installed in the head end. (As noted earlier, the EPLD may be programmed differently when installed in the remote end. The difference between the two versions is that the remote end EPLD unit recovers the time base with the aid of the received signal rather than generating it solely from an internal time base. Recovery of timing data from the received signal is conventional, except insofar as the time delays and guard bands are concerned. These unconventional features will be described later.) The EPLD 154 in a preferred embodiment provides a microprocessor bus interface 210 to the on-board controller 150, an ISA bus interface 208 to ISA bus 200 into which the controller card connects in the head end unit (or the remote end unit, as the case may be) , an SRAM interface 212, a DSP interface 206, a synthesizer control interface 196, two internal address decoders 214, 218, a dual port register 216, an external address decoder 220, a timing generator 204, and a data formatter 222. Microprocessor bus interface 210 receives information on data locations, media access controller (MAC) hardware addresses, and similar information, and provides this information to the dual port register 216 through internal address decoder 214. Register 216 holds this information, which thereby configures the card with a unique "personality" to operate within the PC bus architecture. Internal address decoder 214 also sends data and addresses to the DSP 156 through DSP interface 206, which is configured with different register addresses, and also configures the synthesizer through synthesizer control interface 196. Address decoder 214 controls the reading and writing of data into dual port register 216 through microprocessor bus interface 210. Dual port register 216 may also be read from and written to by PC ISA bus interface 208, under control of internal address decoder 218. External address decoder 220 allows the shared random access memory (SRAM) 152, which is accessed by the EPLD through SRAM interface 212, to have a base address set in the PC's memory. This allows multiple cards to be resident in one computer. Decoder 220 decodes the addresses on the PC bus and enables write into the shared RAM. SRAM 152 is required to hold data sufficient to buffer about the length of a transmit and receive TDMA/TDD frame. Thus, in the present embodiment, about 2 kilobytes of SRAM suffices. Data formatter 222 acts as a combined DMA controller with a parallel to serial and serial to parallel data converter. Formatter 222 also receives a block address, which, relative to the base address, provides an absolute address to which to send or from which to access data in shared RAM 194. The data is sent to and received from DSP interface 206. Timing generator 204 is used to provide timing for the DSP 154. However, when the EPLD is used in a remote end station, timing must also be coordinated with the received data. This is provided by a connection DL (shown in dashed lines) to DSP interface 206, which is present only in the remote end units. This is the only difference between the head end unit and remote end unit interface card. A reset function is also provided by providing connectivity between the microprocessor bus interface 210 and timing generator 204 through internal address decoder 214. (This reset function is described below in conjunction with Fig. 18.) In operation, the ISA interface 208 receives timing and location information, preferably in the form of instructions such as, "at time X, transmit Y data bytes at starting address Z in shared dual-port RAM 152." It is the job of data formatter 206 to retrieve the data requested in real time and send it to DSP 156 for transmission. In addition, serial data from DSP 156 is routed to the data formatter 222, which formats the data into parallel bytes. This data is sent to a specific address in SRAM 152 so that it can be made available to the head end unit (or the remote end unit, if indoor unit 102 is installed in a remote end instead of a head end) . Transmission of data is controlled by a time specification loaded into an internal register in data formatter 222. It will thus be observed that the indoor unit includes a controller for the wireless transceiver (as well as portions of the transceiver function in the described embodiment) and the shared RAM. The head end driver operation is described in the flow charts of Fig. 7 to Fig. 11, inclusive. Referring first to Fig. 7, the loading of the driver software (indicated by block 1000) will now be described. When the driver software is loaded either manually or automatically as part of a boot-up procedure, it attempts to register with the operating system as a network interface. This step is indicated at block 1002. At block 1004, a check is performed by the software to determine whether the registration was successful. Normally, the registration attempt will succeed. However, there may be circumstances present (e.g., lack of memory resources in an overloaded system) that might result in the registration attempt to fail. While not normally expected, a registration failure would cause execution to proceed to block 1006, where any system resources (e.g., memory) that were allocated during the registration attempt would be released back to the system. Optionally, an error report might also be sent to an error log by either the operating system or the driver software, or both. The registration process would then end unsuccessfully at block 1016. Normally, registration would be successful, and execution would continue from block 1004 to block 1008. An empty database is built for remote end subscribers at block 1008. Next, at block 1010, the ISA cards are probed to identify the radio interface cards, and at block 1012, each such card detected is added to the database and its resources are registered with the operating system. (Registration details vary in accordance with the operating system used, as would be known by those skilled in the art.) For systems of this sort, a watchdog timer is highly desirable feature to ensure that the driver code operates properly. Therefore, a watchdog timer is initialized and activated at block 1014 before the loading process terminates successfully at block 1016. It is to be understood that a head end computer will most likely be equipped with multiple indoor units, each communicating with a corresponding outdoor unit, the antenna for which comprises a sector of a sectored antenna. Thus, multiple cards would most likely be added to the head end database. Fig. 8 is a flow chart of the head end driver system timer function 1100, which is entered every 0.01 seconds, in one embodiment of the invention. Execution then proceeds to block 1102, where a pause timer and the watchdog timer are decremented, if they are active and have not yet expired. (Although the timers described here are implemented by decrementing counters, those skilled in the art will understand that there are many alternative ways to implement suitable timers for this application.) If a request for a change of frequency (or the first frequency assignment) for the radio interface card is pending in a request queue at block 1104, the pause counter is set to a value that corresponds to approximately 0.02 seconds. Meanwhile, the frequency of the radio transmitter controlled by the interface card is changed to the requested frequency, and the request for the change is cleared from the request queue. The frequency request change is communicated from the IOCTL path. The significance of setting the pause counter is that, while the pause counter is counting down, the watchdog timer is extended, as will become clear below. Furthermore, all data transmission is suspended during the pause time period to prevent transmission while the frequency of the transmitter is changing. After block 1106 is executed (or immediately after the test in block 1104, if there is no frequency request pending) , block 1108 is executed to determine whether the watchdog timer has expired. Normally, it will not have expired, so the system timer routine will return at block 1112. However, if the watchdog timer has expired, an attempt is made to reboot the interface card at block 1110 before returning. This can be done by building and sending a "dummy packet" to "kick start" the card, or by any other suitable method as would be known to those skilled in the art. The watchdog timer is reset after this kick start to a value corresponding to approximately 1.0 second. Fig. 9 is a flow chart of the IOCTL handling routine in the head end driver. It should be understood that the term "IOCTL" is an operating system-specific term that refers generally to device input/output control commands in the LINUX® operating system. Many other operating systems have analogous device control capability, although different terminology and software conventions may be used. One skilled in the art would be able to recognize the necessary functionality described herein. If necessary, such a skilled person would also be able to adapt the software code implementing the flow chart procedures to the software conventions required for the selected operating system platform. When an IOCTL command is received from the operating system at 1200, the head end driver software first determines what kind of command it is. That task is shown here as a sequence of steps 1202, 1208, 1212, 1216, 1220, 1224, 1228, 1232, with execution of the appropriate command occurring immediately after the first match occurring in the sequence. However, the order of the matching steps in this sequence is not critical. Also, other programming techniques may be used to accomplish the same purpose, such as replacing the sequence of comparison steps with a table of function pointers indexed by the corresponding command codes. Whichever method is chosen by a programmer to implement the functionality illustrated in this flow chart, if the IOCTL command is a request to add a new user, data for the new user contained in the IOCTL function arguments is added to the database at 1204. If the IOCTL command is a request to update an existing user, the data in the table corresponding to the existing user is modified at 1210. If the IOCTL command is a request to delete a user, the specified user is deleted from the database at 1214. An IOCTL command is also provided to change frequencies. Such a request may be necessary to provide load sharing, in the event one frequency is carrying excess traffic, or if there is radio interference or a hardware failure. If this is the case, traffic on the specified channel is paused, and a frequency change is scheduled at block 1230. The other remaining IOCTL requests are optional administrative tasks. These include returning a list of users defined in the database at 1218, returning statistics for a specified interface card at 1222, resetting statistics for a specified interface card at 1226, and returning database information for a specified user at 1234. These and any additional administrative functions may be provided for either automatic or manually-assisted confirmation of proper operation of the head end system, and to facilitate any adjustments that may be required or that may be deemed advantageous. After execution of the IOCTL command, the process to execute the IOCTL command ends at block 1206, to be restarted when another IOCTL command is received from the operating system. The process also returns without performing any action if the IOCTL command received does not correspond to one implemented in the head end driver. One skilled in the art could optionally add integrity checks to report, signal, correct, and/or log invalid, illegal, or spurious IOCTL commands. Fig. 10 is a flow chart of a process that handles requests from the operating system to send a packet of data over a radio link. This process is the normal way in which data transfer occurs from the Internet (for example) to a subscriber. Data transfers between subscribers are also handled by this routine, although it is expected, but not required, that such transfers will be relatively rare in most systems because subscribers will not often need to send messages to one another. When a packet is received at 1300, the packet destination address is compared to the addresses assigned to the interface card at step 1302. Step 1302 differs from the steps normally taken by other types of network cards, such as ethernet cards, because each card has a predefined list of units with which it communicates. If the packet received from the operating system is to be sent to a unit that is defined in this list of units at 1304, the packet is linked to the transmit packet list for the specified destination address at block 1306. The process then terminates at 1310, to be restarted when the operating system provides another packet to be sent. The branch leading from block 1304 to block 1308 represents an error condition. Such an error may result from a packet for a non-paying customer being received, a communications error having occurred, or a mistyped address being entered. If, at step 1304, the unit to which the packet is to be sent is not present in the list of defined units assigned to the interface, the packet buffer containing the packet is released at 1308, the transmit request is ignored, and the packet handling process ends at 1310. Optionally, information about the error could be recorded in a system log or displayed on a display unit. The final head end flow chart is presented in Fig. 11, which is a flow chart of the hardware interrupt procedure. In a preferred embodiment, hardware interrupts occur at approximately 8 millisecond intervals, and it is preferred that the interface cards be synchronized to generate interrupts at the same time. Although it is not considered preferable for hardware interrupts from different interface cards to occur at different times, a system operating in accordance with this flow chart will be able to operate properly under such conditions. When a hardware interrupt occurs at block 1400, a loop is entered whereby each interface card is checked to determine which ones are requesting service. Blocks 1402, 1404, 1406, and 1408 represent one suitable implementation of this loop. When a card requesting service is found, the type of request is then determined. One suitable method for doing this is represented by the sequential check shown by blocks 1412, 1426, and 1434. However, the illustration of one method is not to be construed as implying that other methods, such as using the function request as to a pointer into a table of function addresses, would not be suitable alternatives. Also in a preferred embodiment, control headers indicating the type of interrupt precede the accompanying data packet. A receive data interrupt occurs when data is received at the head end from a remote user. If the interrupt request is a receive data interrupt, execution proceeds at block 1414, where the interrupt request on the interface card is cleared. Next, at block 1416, a search is performed for received data in the received data buffer of the requesting card, and the received data packet header is searched and parsed. The syntax of the packet and its checksum are also checked. If, at block 1418, the header is determined to be invalid, nothing is done with this packet, and the process proceeds to block 1426 in this implementation to determine whether any other types of interrupts are pending for this card. Otherwise, if the header is valid, block 1420 checks to determine whether the packet is a poll response. If it is not a poll response, the head end driver requests a system buffer and passes the packet to the operating system in the requested system buffer at block 1422. Then, execution proceeds to block 1416, repeating the searching, parsing, and passing of packets to the operating system until either an invalid header is found at block 1418 or a poll response is found at block 1420. In this embodiment, poll responses are guaranteed to be the last packet in a buffer under normal circumstances. This is because the head end requests poll responses from a customer in each cycle to confirm the presence of the communications path with that customer and to get data from that customer's buffer in a subsequent frame. Poll responses from other customers are requested in other cycles. Therefore, once a poll response is found at block 1420, the response history and amount of data pending for the responding user is updated at block 1424, including any reallocation and assignment of appropriate radio time on the radio link, thereby effecting the allocation of variable bandwidth to each remote end computer via a later transmission of a control data packet to the remote end station (see blocks 1432 and 1440, for example) . This allocation could include allocations to multiple remote end computers during portions of a single TDMA/TDD frame on a single channel. The allocations could also refer to, and be limited by, user limits in a head end database. (It is to be understood that variable "bandwidth" is meant in the sense of variable throughput, inasmuch as the radio frequency (RF) links are always operated at a fixed spreading chip rate.) Execution then proceeds at block 1426 to determine whether any additional interrupts for this card need processing. If a valid header is not found at block 1418, this may indicate that the end of a buffer has been reached without having received an appropriate poll response, or that a header error has occurred. Such errors are not uncommon, and are tolerated by the TCP/IP protocol, which calls for retransmission of dropped packets. Therefore, the "no" branch from block 1418 aborts any further checking, buffering, and processing of the received data and any dependent system updating. Instead, execution merely continues at block 1426 to provide processing of any additional hardware interrupts from the interface card. A header interrupt occurs when an interface card has successfully sent control data to all the users. Such control data may include, for example, the frequency to transmit, propagation delays, etc. If a header interrupt is received, the interrupt request on the interface card is cleared at block 1428. Next, the pause timer is checked at block 1430 to see whether it is active. If the pause timer is active, no further processing of the header interrupt is done during this cycle. Otherwise, control data and broadcast data are built in a buffer, for transmission during the next transmit cycle. (Broadcast data includes data transmitted to all network addresses, similar to broadcast messages on an ethernet network. Control data may include lists of users, assigned frequencies, propagation delays, and link time assignments.) In either case, in the embodiment described herein, processing continues at block 1434. A transmit data interrupt occurs when data is received at the head end that is to be sent to a remote user. If a transmit data interrupt is received, the interrupt request on the interface card is cleared at block 1436. If it is then determined that the pause timer is active, no further processing of the transmit data interrupt is done during this interrupt cycle, and in this embodiment, control returns to block 1406 to loop to the next interface card. Otherwise, control data and broadcast packets that were built in buffers during a previous execution of block 1432 are copied into the interface card. If there is user data to send at block 1442, user data packets are copied into the interface card at block 1444 until the transmit buffer is full, or there are no more user data packets to send. Next, the transmit timing parameters are set on the interface card and the watchdog timer is reset at block 1446, and the loop is incremented to the next interface card, if there is another to check. Operation of an embodiment of the remote end driver is described in Fig. 12 to Fig. 16, inclusive. The operation of the remote end driver is similar, to a large extent, to the operation of the head end driver, so Fig. 12 through Fig. 16 may be compared to Fig. 7 to Fig. 11, respectively. Similarities between steps within the comparable figures have been highlighted by the use of reference numerals having the same two-digit endings. Thus, step 1502 in Fig. 12 corresponds to step 1002 in Fig. 7. Where differences arise, they are explained in detail below. Fig. 12 is a flow chart of the loading of the remote end driver. This process is essentially the same as that shown in Fig. 7, other than that it occurs at the remote end. In addition, whereas the head end loader has to probe each card, add all the detected cards to the database and register their resources with the operating system, the remote end driver does not have to probe multiple cards. Therefore, a step corresponding to block 1012 of Fig. 7 does not occur in the loading routine of Fig. 12, and thus does not appear in Fig. 12. Fig. 13 is a flow chart of the remote end system timer process. This flow chart is very similar to the head end system timer flow chart of Fig. 8, and is also performed at intervals of about 0.01 seconds. Block 1606 of Fig. 13 is similar in function to block 1106 of Fig. 8, and also sets the pause counter to a value corresponding to about 0.02 seconds. Block 1610 differs somewhat from block 1110, however. Although block 1610 resets the watchdog counter, as does block 1110, block 1610 does not build and send a dummy packet to kick start the interface card. Instead, the pause counter is set and the card steps to the next frequency in an attempt to restore normal operation. Fig. 14 is a flow chart showing the processing of IOCTL commands from the operating system at the remote end. This flow chart is similar to that shown in Fig. 8 for the head end, except that the remote end does not handle and does not need to process requests to add a new user or to delete a user. Fig. 15 is a flow chart of the process that processes a call from the operating system to send a data packet. This process corresponds to, but is simpler than that shown in Fig. 10 of the head end. At the remote end, there is no need to compare packet destination addresses to those assigned to the interface, because the path back to the head end is usually assigned as the default route for all customers when the destination address of a data packet does not correspond to a local network address. All checking is done at the head end to see whether the head end represents a valid path for this message and for the remote site. Therefore, in Fig. 15, there are no steps corresponding to 1304 and 1308 in Fig. 10. Referring to the flow chart of Fig. 16, it will be observed that the hardware interrupt processing at the remote end has some similarities with hardware interrupt processing at the head end, the latter being represented by the flow chart in Fig. 11. However, there are sufficient differences to warrant a more detailed discussion of Fig. 15. Hardware interrupts arrive at approximately 8 millisecond intervals at block 1900, as at the head end. However, there is no loop required for processing a plurality of cards, because only one interface card is required at the remote end. Therefore, with each interrupt, a check is made to determine whether the interface card is requesting service at block 1904. If not, the process terminates at block 1910, to be restarted when the next hardware interrupt arrives. Otherwise, a check is made at block 1912 to determine whether the interrupt is a receive data interrupt, which occurs when data is received from the head end at the card requesting service. If not, processing continues to determine whether a header interrupt is pending at block 1926. If so, the header interrupt is cleared on the interface card at block 1928, and processing continues in any event at block 1934. At that block, it is determined whether a transmit data interrupt is pending. If so, the interrupt is cleared at block 1936, and processing continues in any event at block 1904 to determine whether additional services may have been requested by the interface card. Returning to block 1904 is desirable because multiple interrupts may occur if the system is still processing an interrupt when the next interrupt occurs. Note that the processing of header interrupts and transmit data interrupts are not actually required at the remote end. Instead, these interrupts are ignored and cleared. However, by having steps that clear these interrupts, it is possible to use the same hardware at both the head end and at the remote end. Returning to block 1912, if there is a receive data interrupt, that request is cleared on the interface card at block 1914. At block 1950 (so numbered because there is no general equivalent to this block in Fig. 11), a check is performed to determine whether the interrupt is signaling that the receive data interrupt is requesting service for a control packet. If this is the case, the control data is checked to determine whether it is valid at block 1952. If the data is not valid, then an error is presumed to have occurred, and all transmission for this hardware interrupt cycle is disabled. It is expected that this type of error routinely occurs from time to time, because digital radio links are not entirely free from transmission errors. Disabling transmission until a correctly received control data packet is normally sufficient to handle this type of error. If the control data is valid at block 1952, a data/poll response is built in a hardware buffer on the interface card. The timing and frequency for transmission are also set as specified in the control packet. Preferably, the hardware then automatically sends the data built in the hardware buffer to avoid placing this burden on the operating system. After the actions specified in block 1956 are performed, header and transmit data interrupts are preferably cleared at 1926, 1928, 1934, and 1936, if any are pending, and the hardware interrupt process terminated at block 1910 until the next hardware interrupt occurs. If the data at block 1950 is not a control packet, the packet header is searched for and parsed, and the syntax and checksum is checked for validity at block 1916. If the header is not valid, it is sufficient to assume that the end of the packet has been reached. Preferably, any header interrupts and transmit data interrupts that may be pending are cleared, and the interrupt process terminates as above, until the next hardware interrupt occurs. If the packet header at block 1918 is valid, the next check at block 1958 determines whether the packet address is for this unit. This check is made because the head end will fill whatever transmission time is available to it with packets, when packets are available for transmission. These packets are visible to any card capable of receiving the transmission. Each interface card that receives the data is responsible for selecting data that is addressed to that particular interface card or that is a broadcast message to all interface cards. If the packet address is not for the unit, execution loops back to block 1916 to find the next packet header. Otherwise, a system buffer is requested at block 1922, and the packet is passed to the operating system for routing to the recipient at the local network. Fig. 17 is a flow chart of the head end interface card software. At boot time, the head end software is entered at block 2100. Various housekeeping and initialization tasks are then performed. At block 2102, the registers of the phase locked loops (136 and 190 in Fig. 1) are initialized. Block 2104 initializes the EPLD 154, such as the timing, hardware address, I/O location, and memory location registers. Block 2106 initializes DSP 156, including spreading code selection, format of signal (DPSK, QPSK, etc.) and the formats of headers. Then a loop is entered at block 2108. The loop executes "forever," i.e., as long as the interface card is operating, unless brought down for testing or if the power fails, for example. Starting at block 2108, operations within the loop first check whether a frequency change has been requested. If so, the PLL is programmed with the correct data input to select the selected frequency at block 2112. Then, a check is made to determine whether a request has been made to transmit a header at block 2114. If so, the DSP is programmed to transmit a header flag and the appropriate data length at block 2116. Finally, a check is made to determine whether a data transmit request was requested at block 2118. If so, the data flag in the DSP is set, and the data length in the DSP is also set. The loop then returns back to block 2108. Fig. 18 is a flow chart of the remote end interface card software. This software is similar to that of the head end interface card software, up to block 2214 (i.e., blocks 2200, 2202, 2204, 2206, 2208, 2210, 2212, and 2214 correspond to blocks 2100, 2102, 2104, 2106, 2108, 2110, 2112, and 2114 in Fig. 17, respectively) . However, block 2114 checks whether a header has been received, rather than whether one has been transmitted. If so, block 2250 checks whether the packet placement is correct, i.e., whether a header rather than data is being correctly received in sequence. If not, the time base is reset at block 2254 and the loop restarts. Otherwise, the next packet length is programmed at block 2252. Next, a check is made at block 2218 to determine whether data has been received. If so, a check is made to determine whether a data packet is expected, i.e., received in the proper sequence. If not, the time base is reset at block 2260 and the loop is reentered at block 2208. Otherwise, the next packet length is programmed at block 2258. Then, the loop is reentered at block 2208. It will be understood that one having ordinary skill in the art would recognize many modifications and variations within the spirit of the invention that may be made to the particular embodiments described herein. Therefore, the scope of the invention is not intended to be limited solely to the particular embodiments described herein. Instead, the scope of the invention should be determined by reference to the claims below in view of the specification and figures, together with the full scope of equivalents permitted under applicable law.

Claims: WHAT IS CLAIMED IS: 1. A digital wireless communication system for interconnecting a plurality of spatially separated, remote end computers to a head end computer, said system comprising a fixed head end computer and a plurality of fixed remote end computers, each of said computers having a transceiver for communicating digital data in spread spectrum format, said head end computer being connected to a spatially arrayed antenna through which its transceiver communicates said digital data to and from said remote end computers. 2. The system of claim 1 wherein said head end computer is configured for assigning a communication bandwidth to each of said remote end computers. 3. The system of claim 2 wherein said head end computer is configured for controlling the transmission of data to and from said head end computer with each of said remote end computers . 4. The system of claim 3 wherein said spatially arrayed antenna is segmented into a plurality of directional sectors, each of said remote end computers being located in one of said directional sectors, and said head end computer assigns a frequency, a time for commencing transmission of data, and an allotted time for data to be transmitted. 5. The system of claim 4 wherein said head end computer is configured to synchronize data being communicated between said head end computer and each of said remote end computers . 6. The system of claim 5 wherein each of the remote end computers are configured to delay transmission of data from the remote end computer to the head end computer in accordance with the distance of the remote end computer from the head end computer. 7. The system of claim 5 wherein the remote end computer include network routers configured to route packets between computers within local networks, and the network routers are configured to route packets for computers outside the local networks to the head end computer through the spatially arrayed antenna. 8. The system of claim 1 wherein the head end computer is in communication with a computer network, and the head end computer is configured to selectively route data received from the computer network to the remote end computers via the spatially arrayed antenna in accordance with a specified routing address for the received data. 9. The system of claim 8 wherein said head end computer is configured to route data packets communicated to it via the spatially arrayed antenna from the remote end computers to a computer network. 10. A wireless interface for IP routing of data packets to and from a host computer through a wireless link, the wireless interface comprising: a wireless transceiver; a buffer memory coupled to the host computer and the wireless transceiver for receiving data packets received from the wireless transceiver and data packets from the host computer to be transmitted through the wireless transceiver; and a controller operatively coupled to the wireless transceiver and the buffer memory for timing transmission of data packets to be transmitted and the reception of data packets from the wireless transceiver in accordance with control data received from a head end computer communicating with the host computer through the wireless transceiver. 11. The interface of claim 10 wherein: the buffer memory and the controller are on an indoor unit configured for mounting in the host computer; at least a portion of the wireless transceiver is configured to be separable from the interface card in an outdoor unit; both the indoor unit and the outdoor unit comprise frequency converters; and the indoor unit and the outdoor unit communicate the received data packets and data packets to be transmitted to and from one another over an intermediate frequency link. 12. The interface of claim 11 wherein the intermediate frequency link is duplexed to provide a DC power path from the indoor unit to the outdoor unit. 13. The device of claim 12 wherein the intermediate frequency link is a time-division duplex link, so that transmission of data from the indoor unit to the outdoor unit and transmission of data from the outdoor unit to the indoor unit occur at different times. 14. The device of claim 13 and further comprising a digital spread spectrum processor operatively coupled to the wireless transceiver, the buffer memory, and the controller for spreading and despreading data packets communicated through the wireless transceiver. 15. The device of claim 14 wherein the controller of the interface is a first controller, and the host computer comprises a second controller and an address and data bus operatively coupled to the second controller, the buffer memory is a dual port memory having a both a first port operatively coupled to the first controller and a second port operatively coupled to the second controller for asynchronous access to the contents of the buffer memory. 16. A device for communication of data via a wireless link, said device comprising (a) a host computer; (b) a communication interface, the communication interface comprising: (i) a communication processor; (ii) shared memory operatively coupled between the communication processor and the host computer so that the communication processor and the host computer can separately and asynchronously access data packets in the shared memory; and (iii) a wireless transceiver coupled to the communication processor for transmission of data packets stored in the shared memory and reception of data packets over a wireless link for storing in the shared memory and subsequent transfer to the host computer. 17. The device of claim 16 wherein the wireless transceiver is a spread spectrum wireless transceiver. 18. The device of claim 17 wherein the wireless transceiver is a TDMA/TDD transceiver. 19. The device of claim 18 wherein the communication processor is configured for scheduling transmission of data packets stored in the shared memory in accordance with TDMA/TDD frame timing. 20. The device of claim 19 wherein the communication processor is further configured to delay transmission of data packets in accordance with a propagation delay characteristic of the wireless link. 21. The device of claim 16 wherein the device further comprises a sectored antenna configured for communication over wireless links with a plurality of remote computers, a data base of remote computers, and a plurality of 5 communication interfaces each coupled between the CPU and a sector of the sectored antenna. 22. The device of claim 21 wherein the computer further comprises means for polling the plurality of remote computers, means for analyzing poll responses to determine an amount of data to be transmitted by > responding remote computers, and means for transmitting transmission schedules to the remote computers in accordance with the determined amounts of data to be transmitted. 23. The device of claim 22 and further comprising means to limit transmission schedules of the remote computers in accordance with values stored in the database of remote users. 24. The device of claim 21, wherein the wireless transceivers of a plurality of communication interfaces operate on a single frequency channel, said plurality of communication interfaces each being operatively coupled 5 to sectors of the sectored antennas communicating with remote computers in different spatial regions. 25. The device of claim 24, wherein sectors of the sectored antenna directed to different spatial regions include sectors having orthogonal polarizations. 26. A wireless transceiver interface for IP routing to and from a host computer through a wireless link, the transceiver comprising: random access memory (RAM) accessible by the host 5 computer for retrieval of received data; a signal processor demodulating a stream of received data from the wireless link and having a data input for modulating a signal for transmission over the wireless link; a logic array configured to receive demodulated data from the signal processor and storage locations from the host computer, the logic array also being configured to store the demodulated data in the RAM in accordance with the storage locations received from the host computer; and a controller configured to receive data from the host computer and to construct transmit packets therefrom in the RAM at selected addresses therein; the logic array and signal processor also configured to retrieve and transmit the transmit packets over the wireless link during specified time periods. 27. The wireless transceiver of claim 26 wherein the controller is configured to communicate storage addresses of transmit packets to the signal processor. 28. The wireless transceiver of claim 27 and further comprising an outdoor unit coupled to the signal processor for transmitting a signal from the signal processor to a remote station. 29. The wireless transceiver of claim 28 wherein the outdoor unit comprises: an antenna; an up/down converter coupled between the antenna and the signal processor; and an oscillator coupled to the up/down converter to convert received signals to an intermediate frequency for communication to the wireless transceiver and to convert an intermediate frequency signal from the signal processor into a radio frequency transmitted over the wireless link. 30. The wireless transceiver of claim 29 and further comprising a frequency synthesizer coupled to the oscillator and the controller, the frequency synthesizer controlling the frequency of the oscillator in accordance with commands received from the controller. 31. The wireless transceiver of claim 30 and further comprising a time base generator coupled to the signal processor and controlling transmission of transmit packets . 32. The wireless transceiver of claim 31 wherein the time base generator is coupled to the host computer bus and derives a time base from the host computer bus. 33. The wireless transceiver of claim 31 wherein the time base generator derives a time base from a signal received over the wireless link. 34. The wireless transceiver of claim 31 and further comprising transmit/receive switches configured to provide time division duplexing of transmit and receive signals . 35. The wireless transceiver of claim 34 wherein the controller is configured to process sequencing between header packets and data packets in the demodulated data and to reset the time base if they are not. 36. The wireless transceiver of claim 34 and further comprising means for delaying transition between receive and transmit modes in accordance with a distance from a station communicating with the wireless transceiver over the wireless link. 37. A computer/router comprising: a personal computer including an internal bus; and the wireless transceiver of claim 26 wherein the RAM and the controller are each coupled to and communicating with the internal bus. 38. The computer/router of claim 37 wherein the personal computer is configured to parse packet headers in received data in the RAM, schedule transmission time for a remote user based upon demodulated data received over the wireless link, and copy user data packets to a transmit buffer in the wireless transceiver RAM until the transmit buffer is full. 39. The computer/router of claim 38 having a plurality of the wireless transceivers coupled to different directional antennas, and the different directional antennas include antennas directed to separate sectors of space. 40. The computer/router of claim 39 wherein the plurality of wireless transceivers include transceivers operating on different frequencies and having antennas directed to the same sector of space. 41. The computer/router of claim 40 wherein the antennas include antennas having orthogonal polarizations and operating on the same frequency but directed to different sectors of space. 42. The computer/router of claim 37, wherein the host computer is configured to recognize control data received over the wireless link and to set timing and frequency as specified in the control packet. 43. A method of communicating digital data between computers comprising the steps of: subdividing space around a head end computer into a plurality of sectors served by separate directional sectors of a sectored antenna coupled to the head end computer; communicating data, via radio channels, between the head end computer and fixed remote end computers over bidirectional wireless links via the separate directional sectors of the sectored antenna; routing data received by the head end computer over the radio channels to a computer network; and routing data received from the computer network to the remote end computers over the radio channels in accordance with a routing address specified for the received data. 44. The method of claim 43 wherein the step of communicating data comprises communicating data over TDMA/TDD channels between the head end computer and the fixed remote end computers. 45. The method of claim 43 wherein the communicating step comprises spreading communicated data with a spread spectrum modulation sequence. 46. The method of claim 45 and further comprising transmitting poll responses from each of the remote end computers to the head end computer, and transmitting, in from the head end to the remote end computers and in response to the poll responses, schedules for transmitting data from each of the remote end computers to the head end computer. 47. The method of claim 46 wherein transmissions occur within TDMA/TDD frames, each having a specified head end receive period length and a head end transmit period length, wherein poll responses terminate data transmission from the remote end computers during each TDMA/TDD head end receive period. 48. The method of claim 47 wherein transmission from the remote end computers in each TDMA/TDD head end receive period terminates with a poll response. 49. The method of claim 48 wherein only one poll response is transmitted during each TDMA/TDD head end receive period, and each remote end computer communicating with the head end computer transmits a poll response in round robin fashion during successive TDMA/TDD head end receive periods. 50. The method of claim 49, including a step of providing a plurality of frequency bands for separate TDMA/TDD channels. 51. The method of claim 49, including a step of providing a plurality of spatial regions around the head end computer for separate TDMA/TDD channels, including frequency reuse between spatial regions. 52. The method of claim 46 and further comprising delaying transmissions during assigned TDMA periods from each of the remote end computers in accordance with their respective distances from the head end computer. 53. The method of claim 52 and further comprising reusing frequencies in different sectors with orthogonal polarizations of the reused frequencies in the different sectors . 54. The method of claim 52, and further comprising scheduling and transmitting different packet lengths from the remote end computers to the head end computer in accordance with an amount of data requested for network i transmission by respective ones of the remote end computers . 55. The method of claim 54, and further comprising limiting transmissions from said remote end computers in accordance with bandwidth limitations contained in a head end database. 56. The method of claim 54, wherein transmission occur in TDMA/TDD channels having frames each having a selected head end transmission period length and a selected head end receive period length, and further comprising > scheduling, during the head end transmission period, remote end transmissions to be made to the head end during the head end receive period, and transmitting a poll response from a selected remote end computer during the head end receive period to terminate transmissions from the remote stations during each head end receive period. 57. The method of claim 56 and further comprising transmitting poll responses from a plurality of remote end computers during successive TDMA/TDD head end receive periods, in round robin fashion.

Inventors: BORGER ROBERT M, HORTON EDWIN T, BORGER, ROBERT, M., HORTON, EDWIN, T.
Applicants: WORKNET COMMUNICATIONS
Application year: 1999
Main classification: H04J3
IPC codes: H01Q1, H04H1, H04J13, H04L12