A circuit for compensating for the difference between the Vgs voltages of two MOS transistors

Abstract: The difference between the Vgs voltages of a first MOS transistor (Mp) and a second MOS transistor (Mn) of an integrated circuit due to variations in the production process and/or to variations of other parameters is compensated by a circuit (10) comprising a third MOS transistor (Mp1) and a fourth MOS transistor (Mn1) which are of the same type as the first transistor (Mp) and the second transistor (Mn), respectively, and are formed in the same integrated circuit, means (VDD, Mp2, Mp3) for biasing the third transistor (Mp1) and the fourth transistor (Mn1), means (Mp4-Mp7) for measuring the difference between the Vgs voltages of the third transistor (Mp1) and the fourth transistor (Mn1), means (R1) for generating a compensation current (Io) which is a predetermined function of the difference measured, and means (Sp1-Sp3, Ro) for modifying the biasing of the first MOS transistor (Mp) and of the second MOS transistor (Mn) with the use of the compensation current (Io).

Description: The present invention relates to a circuit for compensating for the difference between the gate-source voltages (Vgs) of two MOS transistors of a device in an integrated circuit as defined in the preamble of Claim 1. The expression "MOS transistors" defines field-effect transistors which are produced by MOS (metal-oxide semiconductor) technology and are commonly used as basic components of devices in analog and digital integrated circuits. However, the invention also applies, in general, to circuits which use field-effect transistors of different types. This, is however not claimed. It is known that the characteristics of the components of integrated circuits are liable to vary relative to the design characteristics to a greater or lesser extent because of the variability of the production processes. MOS transistors of different types or dimensions formed in the same circuit may respond differently to process variations. In many applications, particularly in analog circuits, this different behaviour of MOS transistors causes imbalances in the operation of the circuits or undesired deviations from the operation provided for at the design stage. An example of such an application is the input stage of an amplifier. As shown in Figure 1, a stage of this type comprises an n-channel transistor Mn and a p-channel transistor Mp having their source electrodes connected to the terminals of a supply, indicated by the ground symbol and VDD, and their gate electrodes connected to respective biasing circuits comprising, in this example, two identical current generators Go connected, as shown, to an input node N of the stage, each by means of a resistor Ro. The drain electrodes of the two transistors constitute two outputs of the stage and are connected to other components of the amplifier, not shown. If the stage is required to have a symmetrical response to an input signal applied to the input node N, the generators Go must generate identical currents, the resistors Ro must have the same resistance, and the voltages Vgsn and Vgsp between the gates and sources of the two transistors Mn and Mp must be identical. The first two conditions can be satisfied by sufficient precision but the third cannot generally be satisfied because the two transistors are structurally different from one another and therefore have different characteristic curves. Moreover, the two transistors respond differently to temperature variations in operation. In this example, two complementary MOS transistors are considered, but similar problems also arise with the use of pairs of MOS transistors of which both are n-channel transistors or both are p-channel transistors, but which have different dimensions or are biased in a manner such that different currents pass through them. Document US-A-4.442.398 discloses a current generator for generating a current being proportional to the difference in threshold voltages of two differently desiged MOS-FETs. The object of the present invention is to propose a circuit which compensates for the difference owing to variations in the production process and/or to variations of other parameters, such as temperature, between the gate-source voltages of two MOS transistors of different types. This object is achieved by the provision of a compensation circuit as defined and characterized in Claim 1. The invention will be understood better from the following detailed description of an embodiment thereof which is given by way of non-limiting example with reference to the appended drawings, in which: Figure 1 is a simplified circuit diagram of an input stage of an amplifier, Figure 2 is a diagram similar to that of Figure 1, modified by the addition of a circuit according to the invention, Figure 3 is a diagram of a circuit according to the invention, Figures 4a and 4b show two possible applications of the circuit according to the invention, and Figure 5 shows a variant of the circuit according to the invention of Figure 3. Figure 2 shows schematically the amplifier stage of Figure 1, to which a circuit for compensating for the difference between the voltages Vgsn and Vgsp has been added. As will be explained below, the compensation circuit, represented by a block 10, generates a compensation current Io which is injected into the node N. As can be seen in Figure 3, the compensation circuit 10 comprises two MOS transistors, a p-channel transistor indicated Mp1, and an n-channel transistor indicated Mn1, which are of the same type as the transistors Mp and Mn of Figure 2, that is, which are manufactured in the same device and by the same process stages. In this embodiment, the transistors Mp1 and Mn1 have the same dimensions as the transistors Mp and Mn, respectively but, in general, they could have different dimensions. Each of the two transistors Mp1 and Mn1 has its gate and drain electrodes connected to one another and the transistors Mp1 and Mn1 are connected between the supply terminals, each by means of a constant current generator. In this embodiment, the constant current generators are constituted by two p-channel transistors Mp2 and Mp3 of which the source electrodes are connected together to the terminal VDD, the gate electrodes are connected together to a terminal VB2 of a constant voltage supply, one has its drain electrode connected to the source electrode of the transistor Mp1 at a node A1, and the other has its drain electrode connected to the drain electrode of the transistor Mn1 at a node A2. The transistor Mp1 has its body region connected to its source electrode. Each of the nodes A1 and A2 is connected to the input of a decoupling stage the outputs of which are connected to one another by means of a resistor R1. In this embodiment, the decoupling stages are constituted by two p-channel MOS transistors Mp4 and Mp5 having their gate electrodes connected to the nodes A1 and A2, respectively, their source electrodes connected to the terminal VDD via respective constant current generators, and their drain electrodes connected to ground via the input branches of respective current mirrors Sp1 and Sp3. The constant-current generators are constituted, respectively, by two p-channel transistors Mp6 and Mp7 having their source electrodes connected together to the terminal VDD, their gate electrodes connected together to a terminal VB1 of a constant-voltage supply, and their drain electrodes connected to the source electrodes of the transistors Mp4 and Mp5, respectively. The output branches of the mirrors Sp1 and Sp3 are in series with the input and output branches, respectively, of a further current mirror Sp2, as shown in Figure 3. The circuit combination comprising the transistors Mp2 and Mp3 has the function of biasing the transistors Mp1 and Mn1, and the circuit combination comprising the decoupling stages Mp4 and Mp5 and the respective current generators Mp6 and Mp7 has the function of measuring the difference between the gate-source voltages Vgsp and Vgsn of the two transistors Mp1 and Mn1. The voltages of the nodes A1 and A2 relative to ground, that is, the voltages Vgsp and Vgsn, are reproduced substantially unchanged, by means of the decoupling stages, at the terminals of the resistor R1, so that a current Id proportional to the difference between the voltages Vgsn and Vgsp flows through this resistor. Upon the assumption that all of the mirrors have a gain equal to 1, a current Io=2Id is supplied to a load RL, shown in broken outline in Figure 3, connected between the connection node between the output branches of the mirrors Sp2 and Sp3 and ground. This can easily be confirmed, bearing in mind that the current passing through the resistor R1 is Id = (Vgsn-Vgsp)/R1 , where R1 is the resistance of the resistor R1, that the currents Ip4 and Ip5 passing through the transistors Mp4 and Mp5, respectively, differ from one another by 2Id, that the currents in the input and output branches of the mirror Sp2 are equal to Ip4, and that the current in the output branch of the mirror Sp3 is equal to Ip5. The injection of the current thus obtained into the node N of the circuit of Figure 2 with the use, as compensation-voltage generators, of two resistors Ro having the same resistance as the resistor R1, adds to or subtracts from the voltages Vgs of the two transistors Mn and Mp a voltage such as to render the drain currents of the two transistors equal to one another. In other words, this compensates for any differences between the Vgs voltages of the two transistors. Clearly, if the transistors Mp1 and Mn1 are not identical to the transistors Mp and Mn to be compensated but, for example, have different dimensions, it is necessary, in order to achieve the desired compensation, to select resistors Ro having resistances proportional to that of the resistor R1 with a proportionality factor dependent on the ratios between the dimensions of the transistors to be compensated and those of the transistors Mn1 and Mp1 of the compensation circuit 10, also taking account of the currents and the current ratios of the current mirrors. With the same circuit 10 or with a circuit similar thereto, it is also possible to compensate the gate-source voltages of n-channel and p-channel transistors in circuit configurations other than that shown in Figure 2. For example, as shown in Figures 4a and 4b, the transistors Mn' and Mp' may have their gate electrodes connected to their drain electrodes and may be biased by respective generators Gn and Gp connected between their drain electrodes and respective supply terminals Vdd and ground. The compensation current Io is injected into the drain electrode of the respective transistor Mn', Mp' via a resistor Ro'. If the transistors Mn' and Mp' are identical to the transistors Mn1 and Mp1, respectively, compensation is achieved with the use of resistors Ro' having the same resistance as the resistor R1; otherwise, the resistance value is selected so as to be proportional to that of the resistor R1 with a proportionality factor which depends on the ratio between the dimensions of the transistors Mn' and Mp' to be compensated and those of the transistors Mn1 and Mp1 of the circuit 10. The compensated voltages Vn and Vp are given by the sum of the gate-source voltages Vgsn and Vgsp of the transistors Mn' and Mp', respectively, and by the voltage drop in the resistors Ro'. It is intended that, if the transistors to be compensated belong to separate circuits, as shown in Figures 4a, and 4b, the mirrors Sp2 and Sp3 should have two separate output branches, as shown in Figure 5. Moreover, if there are more than two transistors to be compensated it may clearly be necessary to modify the mirrors Sp2 and Sp3 in a manner such that they have as many output branches as there are transistors to be compensated independently of one another. Although only one embodiment of the invention has been described and illustrated, clearly many variations are possible within the scope of the same inventive concept as defined by the appended claims. For example, instead of a resistor, another component such as a MOS transistor biased to the linear zone may be used as the compensation current generator.

Claims: A circuit for compensating for the difference between the gate-source voltages of a first MOS transistor (Mp) and a second MOS transistor (Mn) of an integrated circuit device, characterized in that it comprises: a third MOS transistor (Mp1) and a fourth MOS transistor (Mn1) which are of the same type as the first transistor (Mp) and the second transistor (Mn), respectively, and are formed in the same device, means (VDD, Mp2, Mp3) for biasing the third transistor (Mp1) and the fourth transistor (Mn1), means (Mp4-Mp7) for measuring the difference between the gate-source voltages of the third and fourth transistors (Mp1, Mn1), means (R1) for generating a compensation current (Io) which is a predetermined function of the difference measured, and means (S1-Sp3, Ro) for modifying the biasing of the first MOS transistor (Mp) and the second MOS transistor (Mn) with the use of the compensation current (Io). A circuit according to Claim 1, in which the means for biasing the third transistor (Mp1) and the fourth transistor (Mn1) comprise a first current generator (Mp2) and a second current generator (Mp3) connected in series with the third MOS transistor (Mp1) and with the fourth MOS transistor (Mn1), respectively, and the difference measuring means comprise a first decoupling stage (Mp4) and a second decoupling stage (Mp5) having their respective inputs (A1, A2) connected between the source and drain electrodes of the third MOS transistor (Mp1) and of the fourth MOS transistor (Mn1), respectively, and their respective outputs connected to the means (R1) for generating a compensation current (Io). A circuit according to Claim 2, in which the means for modifying the biasing comprise a first current mirror (Sp1), a second current mirror (Sp2), and a third current mirror (Sp3) and means (Ro, Ro') for generating a compensation voltage, the first mirror (Sp1) having an input branch connected to one (Mp4) of the decoupling stages and an output branch in series with an input branch of the second mirror (Sp2), the third mirror (Sp3) having an input branch connected to the other (Mp5) of the decoupling stages and an output branch in series with an output branch of the second mirror (Sp2), the means (Ro, Ro') for generating a compensation voltage being connected between the output branch of the third mirror (Sp3) and a predetermined electrode of each of the first and second MOS transistors (Mp, Mn). A circuit according to Claim 3, in which the first and second MOS transistors are a p-channel MOS transistor (Mp) and an n-channel MOS transistor (Mn) of the input stage of an amplifier, in which the third and fourth MOS transistors are a p-channel MOS transistor (Mp1) and an n-channel MOS transistor (Mn1), in which the means for generating a compensation voltage comprise two resistors (Ro), and in which the predetermined electrode is the gate electrode. A circuit according to Claim 3, in which the first and second MOS transistors are a p-channel MOS transistor (Mp') and an n-channel MOS transistor (Mn') each having its gate and drain electrodes connected to one another, in which the means for generating a compensation voltage comprise two resistors (Ro'), and in which the predetermined electrode is the drain electrode.

Inventors: GUINEA JESUS, TOMASINI LUCIANO, GUINEA, JESUS, TOMASINI, LUCIANO
Applicants: ST MICROELECTRONICS SRL, STMICROELECTRONICS S.R.L.
Application year: 1999
Main classification: H03F1
IPC codes: H03K19, H03F3, H03F1