METHOD AND APPARATUS FOR ACCESSING A COMPLEX VECTOR LOCATED IN A DSP MEMORY

Abstract: A method and apparatus for efficiently accessing the real parts and the imaginary parts of complex vector components in a digital signal processor memory is implemented through the incorporation of a new processor addressing, the fixed displacement mode. An additional register, the fixed displacement register, and an additional control flag, the fixed displacement configuration bit are needed. The method of employment requires only a single address register, and does not require use of the normal offset register used for indexed addressing, leaving the offset register to be used for simultaneous post modification and/or bit reversal. Dual memory spaces sharing a common address space are not required, thereby simplifying memory management, and the method and apparatus are compatible with all addressing.

Description: Title METHOD AND APPARATUS FOR ACCESSING A COMPLEX VECTOR LOCATED IN A DSP MEMORY FIELD AND BACKGROUND OF THE INVENTION The present invention relates to a method of processor memory addressing and memory address generation, and, more particularly, to a method of accessing complex vectors stored in the memory of a digital signal processor (DSP) Figure 1 illustrates a typical pπor art address generation unit (AGU) 102 of a processor such as a digital signal processor. The term "processor" herein denotes any data processing device, such as, but not limited to a digital signal processor AGU 102 generally contains register sets for memory data access. Each register set 110 typically includes three registers: 1 an address register (pointer) 104, denoted as Rn; 2. an offset register 106, denoted as Nn; and 3 a buffer length register 108, denoted as Mn, where n = 1 ... K is the set index and K is the number of existing sets m the processor address generation unit. The term "array" herein denotes any plurality of locations in processor memory such that every individual location thereof may be accessed m terms of an index relative to a fixed base address, wherein the indices are all multiples of a constant. The term "vector" herein denotes any plurality of data values stored in such an array, and the term "component" herein denotes any data value of such a vector The term "complex number" herein denotes any pair of data values herein denoted as a 'first part" and a "second part", including, but not limited to, a pair of numbers consisting of a "real part" and an "imaginary part" in the usual mathematical sense The term "complex vector" herein denotes any pair of vectors which have the same number of components The term "first array" herein denotes any array in processor memory containing the first part (or vector) of a vector pair of a complex vector, and the term "second array" herein denotes any array in processor memory containing the second part (or vector) of a vector pair of a complex vector A complex vector may consist of a vector of complex numbers in the usual mathematical sense, wherein the real numbers of the complex vector are stored in the first array and the imaginary numbers of the complex vector are stored in the second array Alternatively, a complex vector may consist of a vector of complex numbers in the usual mathematical sense, wherein the real numbers of the complex vector are stored in the second array and the imaginary numbers of the complex vector are stored in the first array As a further alternative, a complex vector according to the present invention may consist of two vectors of arbitrary data values which do not necessaπly represent complex numbers in the usual mathematical sense Furthermore, the terms "access" and "accessing" with regard to processor memory herein denote the generation of addresses in the processor memory, and relate to both the stoπng of data values in the processor memory as well as to the retrieving of stored data values from the processor memory When working with complex vectors, the first array and the second array are usually placed in different addresses in the memory or in different memory space, depending on the piocessor memory architecture In order to access a complex vector in indirect addressing two different address registers are needed, an address register for the first array and an address register for the second array A limitation of this approach is that address registers are a very expensive resource in digital signal processor applications. In cases where the first array and the second array are located in the same memory, a single address register and an offset register could be used for access. This approach can be used if the address register itself points to the first array and the offset register contain the offset between the first array and the second array. In such a case it is possible to access the first array by an indirect addressing using the address register, (Rn), and to access the second array by an indexed indirect addressing using the address register and its offset register (i.e., Rn + Nn). However, in bit-reversal and post-modification-by-step addressing, the offset register is in use and is not available for an indexed indirect addressing. Therefore, when using an indexed indirect addressing, two address registers are needed for complex vector access. Such situations arise in FFT algorithms where the bit-reversal addressing is in use, decimation of complex signals where post modification by step addressing is in use, and so forth. (An overview of the field and description of existing, digital signal processor architectures may be found in Buyer 's Guide to DSP Processors, Berkeley Design Technology Inc., 1995). Most of the existing digital signal processors do not solve this memory access problem, and thus two different address registers are usually needed to access a complex vector when the offset register is in use. One existing solution, used in Motorola DSP56xxx processor series, is illustrated in Figure 2. This approach uses two data memories, an X-memory 202 and a Y-memory 204 having the same address space 206. Also required are a dedicated assembly language syntax (not shown in Figure 2) and an address generation unit (as shown in Figure 1). A complete description of this architecture is given in DSP56000 24-Bit Digital Signal Processor Family Manual. Motorola, Inc. (Semiconductor Products Sector, DSP Division, Austin, Texas), which is incorporated by reference for all purposes as if fully set forth herein. In this pπor art solution, the address generation unit architecture is such that address register 208 (RO) points to the same address of both X-memory 202 and Y- memory 204. Therefore, locating the first array and the second array for the complex vector in different memory space but at the same address enables the use of address register 208 (RO) alone to access both the first array and the second array simultaneously. As shown in Figure 2, address register 208 (R0) points to address 0x0002 but without a specific relationship to memory space. The direction to a particular memory space is done in the assembly language opcode. For example if the first array is located in X-memory 202 and the second array is located in Y-memory 204, and if the first array stores the real part of a complex vector and the second array stores the imaginary part of a complex vector, then moving the real part of address 0x0002 to register A and the imaginary part to register B is done by the following assembly code: move X : (R0 ) , A ; move Y : (R0 ) , B ; This solution suffers from two drawbacks: First, the two parts of the vector (pointing to the first array and the second array, respectively) have to be located in different memories but at the same addresses. This can lead to inefficient memory utilization (holes in memory) and make it difficult to perform a memory relocation if needed. For example, if it is necessary to relocate the first array in X-memory 202, it is also necessary to relocate the second array in Y-memory 204 in order to keep the two arrays at the same address. There is thus a widely recognized need for, and it would be highly advantageous to have, an efficient way of accessing a complex vector in a processor memory, which requires only a single address register, which does not require the use of the offset register, and which also does not require the use of multiple memoπes sharing a single address space. This goal is met by the present invention. SUMMARY OF THE INVENTION The present invention is a method and apparatus for efficient memory address generation and access to a complex vector located in a processor memory using a single address register (pointer) in any addressing. This is done by incorporating a new register into the address generation unit, which is termed the "fixed displacement register" and is denoted by Rf . This fixed displacement register is used for indexed indirect addressing only, and provides a memory offset in this addressing. By this method it is possible to have a post-increment by step and access to two different arrays with the same address register without reprogramming the address generation unit. Thus, the present invention successfully addresses the shortcomings of the presently known configurations and methods. First, the present invention enables accessing a complex vector with one address generation umt register set using any kind of addressing. Second, the present invention places no restrictions on the memory allocation of the real parts and imaginary parts of a complex vector (for example, the first array and the second array), nor on the memory space, nor on the addresses. Therefore, according to the present invention there is provided an address generation unit for computing the addresses for memory access to a complex vector by a processor, the address generation unit including: (a) an address register; (b) an offset register; (c) means for effecting an indexed indirect addressing capability; (d) a fixed displacement register; (e) means for effecting a fixed displacement mode having a state selectable from the group consisting of an enabled state and a disabled state; and (0 a fixed displacement configuration bit for indicating the state of the fixed displacement mode. Furthermore, according to the present invention there is also provided a method for implementing a fixed displacement mode in a processor having an address register, a fixed displacement register, a fixed displacement configuration bit, the processor having types of addressing including an indexed indirect addressing, the processor executing a current instruction, the method including the steps of: (a) loading a base address into the address register and a fixed displacement into the fixed displacement register; (b) checking the current instruction for an indexed indirect addressing; (c) checking the fixed displacement configuration bit; and (d) generating a memory address equal to the sum of the base address and the fixed displacement if and only if the current instruction includes an indexed indirect addressing and the fixed displacement configuration bit is set. BRIEF DESCRIPTION OF THE DRA WINGS The invention is herein described, by way of example only, with reference to the accompanying drawings, wherein: Figure 1 shows a prior art address generation unit for a digital signal processor. Figure 2 shows the memory configuration of a prior art digital signal processor. Figure 3 shows new features of an address generation unit for a digital signal processor according to the present invention. Figure 4 is a flowchart of an algorithm for fixed displacement address generation. Figure 5 shows an example of memory status. Figure 6 illustrates a two-data memory space architecture. DESCRIPTION OF THE PREFERRED EMBODIMENTS The principles and operation of a method and apparatus according to the present invention may be understood with reference to the drawings and the accompanying description. Important aspects of the address generation unit of apparatus according to the present invention are illustrated in Figure 3. The steps of the method of the present invention as executed during operation of the digital signal processor or other processor according to the present invention are illustrated in the flowchart of Figure 4. These steps implement the fixed displacement mode, which is a new processor mode according to the present invention. As illustrated in Figure 3, it is first necessary to provide certain additional hardware capabilities. In particular, The processor must have a fixed displacement register 310, denoted by Rfl, in address generation unit 302. Fixed displacement register 310 should be software-programmable, just as are all other registers of address generation unit 302. It is also possible, but not necessary, to use more than one fixed displacement register, wherein the additional multiple fixed displacement registers 312, 314, and 316 are denoted by Rf 2, Rf 3, ..., Rfn, respectively, which are shown in dashed outline. The ellipsis ... indicates that further additional fixed displacement registers may be incorporated. A register set 322 includes Rn, Nn, Mn, and Rfl. The present invention requires that the processor have an indexed indirect addressing capability, which can be implemented through any of the means well- known in the art. Note that fixed displacement register 310 is distinct from offset register 306. Fixed displacement register 310 and offset register 306 perform different functions and are used independently of one another. In addition, it is necessary that the processor have a new mode, denoted herein as the "fixed displacement mode". The fixed displacement mode has two states, an enabled state and a disabled state, which can be controlled by incorporating a fixed displacement configuration bit, 320 into -a control register 318. The fixed displacement configuration bit thereby serves as a control flag. The operation of the fixed displacement mode is described in the method according to the present invention, as detailed below. Control register 318 may be an existing control register in an existing processor design that is being modified, or it may be a new control register. Furthermore, it is necessary that the processor be provided with the hardware as necessary to implement the steps (below) of the fixed displacement mode during execution. Hardware facilities to execute the steps below can be implemented through various techniques that are well known in the art. The steps of the method as executed by the processor to implement the fixed displacement mode for memory address generation according to the present invention are as follows and as illustrated in Figure 4. 1. Load register set 322 (Figure 3) into address generation unit 302 (Figure 3) in a loading step 402. This step loads the base address into address register 304, the address offset into offset register 306, the buffer length into buffer length register 308, and the fixed displacement into fixed displacement register 310. 2. Check to see if the current instruction uses indexed indirect addressing in a decision point 404. 3. If indexed indirect addressing is not being used, generate the address in a conventional manner, as is well-known in the art, in an address-generation step 408. 4. If, however, indexed indirect addressing is being used, check to see if fixed displacement configuration bit 320 (Figure 3) is set in a decision point 406. 5. If fixed displacement configuration bit 320 is not set, the fixed displacement mode is in a disabled state, and address generation unit 302 operates in the conventional manner in a memory address generation step 410. That is, the new features described herein are not operational and accesses to address Rn + Nn are made without changing the value of Rn register 304 (Figure 3). When fixed displacement configuration bit 320 is cleared, offset register Nn 306 (Figure 3) is the source for all the post modification and indirect indexed addressing. 6. If fixed displacement configuration bit 320 is set, however, the fixed displacement mode is in an enabled state, and the offset source for all the indexed indirect addressing memory address generation is fixed displacement register 310 (Rfn) , instead of offset register Nn 306, in a memory address generation step 412. The generated address is the sum of the contents of fixed displacement register 310 and the contents of address register 304. Accesses to address Rn + Rf are made without changing the value of Rn register 304 (Figure 3). The memory address generation method according to the present invention terminates in a return step 414. The fixed displacement configuration bit serves as a control flag in that the fixed displacement configuration bit puts the fixed displacement mode into the enabled state when set, and puts the fixed displacement mode into the disabled state when clear. However, the fixed displacement mode is active only if the current instruction uses indexed indirect addressing. If the current instruction uses an addressing other than indexed indirect addressing, the fixed displacement mode will not be active, even when in the enabled state. As is well-known in the art, there are addressing capabilities other than indexed indirect addressing, including, but not limited to direct addressing and post-modification addressing. It is possible to include any of these various types of addressing in an instruction. The term "non-indexed indirect addressing" herein denotes any such addressing which does not involve indexed indirect addressing. Note also that the assembly syntax can, but does not have to support fixed displacement register 310 (Rfl) in memory address generation commands. The term "assembly syntax" herein denotes both assembly language syntax as well as the resulting machine instruction configuration. If the assembly syntax supports the fixed displacement register, then the assembly syntax activates the fixed displacement as a qualifier for an individual instruction rather than as a processor mode with an enabled state and a disabled state. In cases where the assembly syntax does not support the fixed displacement register, it is sufficient to define commands with offset register 306 (Nn) only, because this defines the addressing. The hardware automatically takes offset register 306 or fixed displacement register 310 for the memory address generation according to the status of fixed displacement configuration bit 320. Note also that the designation of the different memory arrays as "first array" versus "second array" is arbitrary and their contents are completely arbitrary. It is readily seen that the method according to the present invention allows the processor to access both parts of a complex vector efficiently. For example, assume the following status of the address generation unit and memory: Rl = 1000 (address register 304 as in Figure 3) Nl = 2 (offset register 306 as in Figure 3) Ml = programmed for linear addressing (buffer length register 308 as in Figure 3 — the actual programming is manufacturer-dependent) Rfl = 50 (fixed displacement register 310 as in Figure 3) And execute the following assembly (pseudo) code Move (R1) +N1 , A ; Move (Rl+Nl) , B ; where A and B are general registers of the processor (not registers of address generation unit 302). Note that (Rl) +N1 is a post modification addressing, meaning that the memory access is to the location Rl, and that Rl is incremented by Nl after the memory access. Note also that (Rl+Nl ) is indirect indexed addressing, meaning that the memory access is to the location Rl+Nl, and that Rl remains unmodified during and after the memory access. Figure 5 illustrates the situation for two scenarios for the two different values of fixed displacement configuration bit 320, for an area of memory 502 having addressing 504. In Figure 5 and the example below, all data values and address locations are shown in decimal notation. In both scenarios, the following holds: • The area in memory from address location 1000 onwards to 1049 is designated as a first array 518. and the area in memory from address location 1050 onwards-is designated as a second array 518. • Prior to execution, there is an initial value 506 for address register Rl, equal to 1000. That is, Rl initially points to a location 512 in memory having an address 1000 that contains the data value -348 . • After the first instruction has completed register A contains the data value -348 and address register Rl equals 1002. That is Rl points to a location 514 in memory having an address 1002 that contains the data value 4391. • After execution is complete, there is a final value 510 for address register Rl, equal to 1002. This is because the second instruction contains indexed addressing only, and indexed addressing does not change the value of an address register. The content of register B after the execution of the second instruction depends on the fixed displacement mode. Below, the two cases of fixed displacement mode set and cleared are described: Fixed Displacement Configuration Bit Not Set In this scenario, the fixed displacement configuration bit is cleared (not set). Consequently, the fixed displacement mode is in a disabled state. Memory address generation is done in a conventional way, and after the second instruction executes the register B contains the value 4391 from memory location 514 in first array 518. Fixed Displacement Configuration Bit Set In this scenario, the fixed displacement configuration bit is set. Consequently, the fixed displacement mode is in an enabled state. Because the first instruction does not use indexed indirect addressing, memory address generation for the first instruction is done in a conventional way. The second instruction, however, does use indexed indirect addressing, and because the fixed displacement configuration bit is set (and hence the fixed displacement mode is in the enabled state), the memory address generation offsets the memory lookup by Rfl to access a memory location 516 containing the value -819. Therefore, in this scenario after the second instruction executes the register B contains the data value -819 from memory location 516 in second array 520. Thus, it is possible to efficiently access both the real parts and the imaginary parts of a complex vector. For example, if the real parts are stored in second array 520 and the imaginary parts are stored in first array 518, then by initially setting the fixed displacement configuration bit, after the execution of the two above instructions, register A will contain the imaginary part of one of the components of the complex vector, and register B will contain the real part of the component of the complex vector. In the above example the method according to the present invention has been presented within the context of a simple memory architecture, namely a single memory space architecture. Today, advanced DSP algoπthms require more elaborate memory architectures and therefore modem digital signal processors have a dual memory space architectures. Figure 6 illustrates an example of the method according to the present invention for a complex vector whose first array and second array are located in different memory spaces. The addresses 606 correspond to the data value contents 608. In Figure 6 and the example below, all address locations are shown in hexadecimal notation. In order to apply the method accordmg to the present invention to a dual memory space architecture, the memory arrangement must be sequential. There is a memory space 602 denoted as "X memory address space" for a first array 610 starting at location 0x0000, and there is a memory space 604 denoted as "Y memory address space" for a second array 612 starting at location 0x8000. As required, these addresses are sequential as shown in Figure 6. Note that in this example the most significant bit (MSB) of the address identifies which memory space is being used. In this configuration the base address of the real part of the complex vector can be located, for example, in X space 602, such as at address 0x0002, and the base address of the imaginary part can be located m Y space 604, such as at address 0x8008. In order to work in fixed displacement mode it is necessary to set the fixed displacement register, Rf, to 0x8006 (0x8008 - 0x0002), and to set fixed displacement configuration bit 320 in control register 318 (Figure 3). While the invention has been described with respect to a limited number of embodiments, it will be appreciated that many vaπations, modifications and other applications of the invention may be made.

Claims: WHAT IS CLAIMED IS: 1. An address generation unit for computing the addresses for memory access to a complex vector by a processor, the address generation unit comprising: (a) an address register; (b) means for effecting an indexed indirect addressing capability; (c) a fixed displacement register; (d) means for effecting a fixed displacement mode having a state selectable from the group consisting of an enabled state and a disabled state; and (e) a fixed displacement configuration bit for indicating the state of said fixed displacement mode. 2. The address generation unit of claim 1, furthermore comprising an offset register, wherein said fixed displacement register is distinct from said offset register. 3. An address generation unit for computing the addresses for memory access to a complex vector by a processor having an assembly syntax with a fixed displacement qualifier, the address generation unit comprising: (a) an address register; (b) means for effecting an indexed indirect addressing capability; (c) a fixed displacement register; and (d) means for effecting a fixed displacement; (e) means for detecting the fixed displacement qualifier; and (f) means for activating said fixed displacement upon said detecting the fixed displacement qualifier 4 The address generation unit of claim 3, furthermore compnsing an offset register, wherein said fixed displacement register is distinct from said offset register. 5 An- improvement to an address generation unit for computing the addresses for memory access to a complex vector by a processor, the address generation unit including an address register and an offset register, the improvement compnsing: (a) means for implementing a fixed displacement mode, said fixed displacement mode having a state selectable from the group consisting of an enabled state and a disabled state; (b) a fixed displacement register, distinct from the offset register, for containing an offset to the address register when employing said fixed displacement mode; and (c) a fixed displacement configuration bit for indicating the state of said fixed displacement mode. 6 A method for implementing a fixed displacement mode in a processor having an address register, a fixed displacement register, a fixed displacement configuration bit, the processor having instructions capable of using indexed indirect addressing, the processor executing a current instruction, the method compnsing the steps of (a) loading a base address into the address register and a fixed displacement into the fixed displacement register; (b) checking the current instruction for indexed indirect addressing; (c) checking the fixed displacement configuration bit; and (d) generating a memory address equal to the sum of said base address and said fixed displacement if and only if the current instruction uses indexed indirect addressing and the fixed displacement configuration bit is set. 7. A method for accessing a component of a complex vector by a processor having an address register and a fixed displacement mode with a fixed displacement register, the component having a first part with a base address and having a second part offset from the base address by a fixed displacement, the fixed displacement mode having a state selectable from the group consisting of an enabled state and a disabled state, the instructions for the processor having an addressing selectable from the group consisting of indexed indirect addressing and non-indexed indirect addressing, the method comprising the steps of: (a) loading the base address into the address register; (b) loading the fixed displacement into the fixed displacement register; (c) selecting the enabled state for the fixed displacement mode; (d) accessing the first part with an instruction having non-indexed indirect addressing; and (e) accessing the second part with an instruction having indexed indirect addressing. 8. The method as in claim 7, the processor furthermore having a settable fixed displacement configuration bit and an indexed indirect addressing, wherein said selecting the enabled state for the fixed displacement mode comprises the steps of: i) setting the fixed displacement configuration bit; and ii) using the indexed indirect addressing.

Inventors: NAVEH GIL, WEINGARTEN ERAN, NAVEH, GIL, WEINGARTEN, ERAN
Applicants: SIEMENS AG, SIEMENS AKTIENGESELLSCHAFT
Application year: 1999
Main classification: G06F9
IPC codes: G06F9, G06F12, G06F17