Oscillator

Abstract: According to the present invention, while maintaining a constant ratio between a bias current supplied to field effect transistors of transconductors 4, 5 and a bias current supplied to field effect transistors of amplifier 3, by controlling oscillation frequency through adjustment of values of bias currents, frequency control can be carried out in much wider range.

Description: The present invention relates to a MOS type semiconductor integrated circuit, in particular relates to an oscillator to be basis when carrying out analogue signal processing. In recent years, due to the increase of digital devices and advancements in digital signal processing technology, CMOS integrated circuits suitable for digital signal processing has gained a large share of the semiconductor market. However, since video or audio signal is inputted/outputted in analogue form, analogue processing is more readily carried out, or, even when being digitally processed, analogue circuits are necessary for A/D, D/A conversion, filtering processing carried out before and after that, oscillators for clock generation and the like. It has been said that, for analogue circuits, bipolar technology is suitable, whereas CMOS technology is unsuitable except for some circuits such as analogue switches and sample holders. However, in addition to that bipolar and BiCMOS processing are rather expensive, demand for one chip CMOS structure achieved by digital/analogue consolidation is strong, and there has been an increase in the development of circuits for processing analogue signal with CMOS circuitry. The "oscillator" with the CMOS has been used much as clock generators or element circuits of PLL in digital signal processing. As representative oscillators as such, there are "ring oscillators" in which CMOS inverters are arranged in multi-stages to form a ring. Among them, one example of oscillators capable of controlling oscillation frequency is disclosed in Japanese Patent Laid-open Application No. Hei-4-188910, principal oscillator portion thereof is constituted as such shown in Figs. 14A and 14B. In this ring oscillator, as shown in Fig.14A, inverter circuits of I1, I2...In are connected in turn in multi-stages, and output of the final stage of the inverter circuit In is returned to the input of the first inverter circuit I1, thereby a loop of ring is formed. Each of the inverter circuits I1, I2...In, as shown in Fig.14B, is constituted of 4 pieces of field effect transistors M41 to M44. Transistors M41 and M42 are formed of MOS transistors of N channels, while transistors M43 and M44 are formed of MOS transistors of P channels. Gates of transistors M42 and M43 are connected to be used as an input terminal, while drains of transistors M42 and M43 are connected to be used as an output terminal. Further, drain of transistor M44 and source of transistor M43, source of transistor M42 and drain of transistor M41 are connected respectively, at the same time, source of transistor M44 is connected to a terminal of power source, and source of transistor M41 is connected to earth point. Each gate of transistors M41 and M44 of each of the inverter circuits I1, I2...In is connected to frequency control terminals T1 and T2, respectively. Output can be extracted from any one output of each inverter circuit of I1, I2...In, and is produced through an output inverter disposed separately outside the loop. In this ring oscillator, a pair of transistors M41, M42 and a pair of transistors M43, M44 of each inverter circuit are made on/off in a complementary manner depending on signal level supplied to the input terminal IN. Therefore, signal levels at the input terminal In and the output terminal OUT in each inverter circuit are to be inverted. Since inverter circuits are connected in a series of multiple stages, such inversions are propagated successively. Due to its ring structure, by returning to its starting point and further enhancing inversion, finally the inversion motion results in oscillation of a whole loop. Frequency of such an oscillation is determined by the delay time of inversion between input and output of each inverter circuit. When a delay time for an inverter is td, oscillation frequency fosc is fosc = 1/(Ntd) Respective gate voltages T2, T1 of transistors M41 and M44 restrict current supplied to these field effect transistors. Thereby, current supplied from transistor M44 to M41 during inversion of inverter circuit is also restricted, thus delay time td also varies. Therefore, if voltages supplied to control terminals T1, T2 are varied, delay times of inversion in respective inverter circuits will change all at once. Thus, when the delay time of inversion varies, since the time at which propagation of inversion returns after one round of the loop also varies, the oscillation frequency also varies according to equation (1). That is, when the delay time a stage td is made fast, the frequency becomes high, and when the delay time td is made slow, the oscillation frequency becomes low, thus the control of frequency is realized. A ring oscillator comprising of such an inverter circuit, when employed in a CMOS LSI which consolidates analogue/digital circuitry, has following disadvantages such as 1. The ring oscillator itself generates a noise like pulse to be liable to adversely affect on the other analogue circuits. 2. Since it is likely to be influenced by the noise of the power source and the like, there is much jitter (phase noise). In the inverter circuit, only at the instance of inversion, a relatively large current flows between the power source and ground. Therefore, each time when the inverter reverses, according to resistances of power source line and ground line, pulse voltages are generated at power source and ground. When LSI contains analogue circuits, even if a measure is taken such as separation of power source line and the like, this pulse voltage goes around to analogue circuit side due to common impedance of the power source line or capacitive coupling according to substrate and the like. This gives some influence to analogue circuits, thereby pulse noise is added to analogue signal to inevitably deteriorate its quality to some degree. In particular, when oscillator output is employed as a certain reference signal in processing of analogue signal, since ratio of frequency of this reference signal and that of the aforementioned pulse voltage has integer ratio, beat component is added on the signal and may be noise incapable of being separated by filter and the like. Further, wave form of inverter circuit constituting a ring oscillator becomes rectangular wave which swings fully between the power source and ground. Since this has spurious component (harmonic component) with high energy, if there is a part of high impedance in an analogue circuit, by plunging in as radiation, the signal quality tends to be deteriorated. On the contrary, even in digital circuit, at the instance when state transits, relatively large penetrating current flows between the power source and ground. Therefore, when an LSI contains digital circuits, for a whole digital circuit, various inversions occur with timings of the edge of clock signal, and a noise like pulse due to this is added on power source line or ground line. As described above, even if a measure such as a separation of power source line and the like is taken, this pulse voltage, due to common impedance of the power source line and due to capacitive coupling according to substrate, can not be avoided to go around to the power source/ground line of oscillator. In the ring oscillator, because of oscillation with amplitude of voltage between power source and ground, the noise added on the source voltage induces temporary variation of amplitude, and gives fluctuation to the delay times of the inverter which determines frequency. This finally becomes the phase noise of oscillation frequency and deteriorates spectral purity of oscillation. Further, penetrating current like the pulse which is generated by the inverter circuit itself constituting the ring oscillator during inversion causes to generate pulse voltage on the power source/ground line which the inverter circuit itself is using, thereby that results in enhancement of the phase noise of oscillation frequency. US-A-4 818 952 discloses an oscillator comprising a feedback loop including first and second tranconductors, each having a certain transconductance. The circuit of D1 includes additionally first and second capacitors connected to the first and second transcunductors so as to form a band-pass filter. The output of the band-pass filter is feed back to the input of the filter. Additionally there is provided an amplifier connected between the output of the second transconductor and one end of the first capacitor. A similar structure is disclosed in US-A-5 420 547 An object of the present invention is to provide an oscillator suitable for a CMOS-LSI containing highly accurate analogue circuits, wherein the oscillator itself is not likely to generate noise, and is not likely to be influenced by source noise and the like. According to the present invention the above object is achieved by an oscillator according to claim 1 or 7. The dependent claims are related to further advantageous aspects of the invention. Preferably, an oscillator of the present invention has a means of controlling oscillation frequency by varying values of the bias currents while maintaining at a constant value the ratio of bias current which is supplied to field effect transistors constituting the transconductor, and bias current which is supplied to field effect transistors of the amplifier, and that results in controlling the frequency in wider range. Thus, since most of the elements operate in linear region and do not operate in complete switching region, noise like pulse does not occur. In addition, since oscillation amplitude is determined independently of source voltage and the value of amplitude can be suppressed small, less spurious occurs, not resulting in jitter (phase noise) as a result of fluctuation of oscillation amplitude due to source noise. From such reasons, oscillators in accordance with the present invention is the most suitable ones for CMOS-LSI including highly accurate analogue circuits. Fig.1 is a diagram depicting a circuit configuration explaining a first embodiment of the present invention; Fig.2 is a diagram depicting a circuit configuration explaining a modification example of the first embodiment of the present invention; Fig.3 is a circuit diagram explaining concretely a transconductor of Fig. 1; Fig.4 is a circuit diagram explaining a specific example of an amplifier of Fig. 1; Fig.5 is a diagram depicting a circuit configuration explaining another modification example of the first embodiment of the present invention; Fig.6 is a circuit diagram explaining a specific example of Fig.5; Fig.7 is a diagram depicting a circuit configuration explaining a second embodiment of the present invention; Fig.8 is a diagram depicting a circuit configuration explaining another modification example of the second embodiment of the present invention; Fig.9 is a circuit diagram explaining concretely a transconductor used in the second embodiment of the present invention; Fig.10 is a circuit diagram explaining concretely an amplifier employed in the second embodiment of the present invention; Fig.11 is a gain characteristic diagram of BPF of Fig. 1; Fig.12 is a phase characteristic diagram of BPF of Fig.1; Fig.13 is a diagram depicting a circuit configuration explaining a modification example of Fig. 1; Fig.14A and Fig. 14B are diagrams depicting a circuit configuration explaining a conventional oscillator. In the following, details of embodiments for carrying out the present invention will be described with reference to the drawings. A first embodiment of the present invention will be described with a diagram depicting circuit configuration shown in Fig.1. In the figure, a portion enclosed by a dotted line shows a BPF (band-pass filter) of second-order. Output voltage of an amplifier 3 is connected to an output terminal Vout which is output of the BPF. Further, output voltage of an amplifier 3 has a high negative gain for input voltage, and is supplied to input of a transconductor 4 which has a certain transconductance. Current output of a transconductor 4 is supplied to an output terminal Vout through a capacitor C1, and is supplied to input of a transconductor 5 which has high negative gain for the input voltage and has a certain transconductance. Output of the transconductor 5 is earthed through a capacitor C2, and is supplied to input of an amplifier 3 having smaller negative gain than those of transconductors 4, 5 for the input voltage. The left terminal of capacitor C1 in the figure is an input terminal IN of the BPF, while output point A of an amplifier 3 is an output terminal OUT of the BPF. The input terminal IN of this BPF and an output terminal OUT are directly connected and constitute an oscillator. A general transfer function of thus constituted BPF of second order can be expressed by a following equation. H(s) = (ωo·s/{s 2 + ωo·s/Q + ωo 2 } Here, s denotes a complex frequency, ω denotes an angular frequency, ωo denotes a central frequency of the BPF, and Q denotes sharpness of BPF characteristic. Under a steady state, being s = jω(ω = 2πf), by substituting this in equation (2), the following equation can be obtained. H (jω) = jωo · ω/ {(ωo 2 - ω 2 ) + jωo · ω/Q} If gain and phase characteristics of BPF are drawn on the basis of this, frequency characteristic of gain, frequency characteristics of phase becomes as shown in Fig.11, Fig.12, respectively. That is, at the central frequency ωo, the gain becomes the maximum of Q, and the phase becomes 0°. When a BPF is short-circuited between input and output, the gain and phase characteristics of Fig.11 and Fig.12 become loop characteristics of oscillator as they are. At the central frequency, the phase being 0°, it becomes positive feedback, since the loop gain becomes 1 or more if Q is 1 or more, it satisfies oscillation conditions and oscillates. In the circuit of Fig.1, ωo becomes ωo = Gm/ ( C 1 C 2) , Q = ∞, when the frequency is in the neighborhood of ωo/2π, it oscillates strong. The oscillation occurs in a loop of A point → B point → C point → A point, since, at respective points, oscillation wave forms with different only phases but same frequency appear, basically at any points output can be drawn out. However, because of relatively low impedance, the A point which is output of the amplifier 3 is desirable as drawing out point. Constituent elements of each stage of this circuit are either transconductor or amplifier, and their relations between input voltages and output voltages are all inverted one. Constituent element 4 and constituent element 5 in the figure are transconductors with voltage input and current output, and, since output terminals are high impedance, voltage gain between input and output are very high. That is, it is a negative amplifier having high gain with respect to direct current. The constituent element 3 is an amplifier having voltage input and voltage output, and voltage gain of around 1 (in the range of 0.1 to 10) is employed. That is, it is a negative amplifier having low gain with respect to direct current. When a circuit illustrated in Fig.1 is constituted with such constituent elements, as to direct current, each constituent element of 3 to 5 is in an inverted relation between input and output, and, since the number of constituent elements which constitute loop is 3, after one round of the loop, it becomes negative feedback (phase shift of 180°) as to direct current. Thus, the respective nodes constituting the loop have stable operating points at intermediate voltages between power source and ground. Next, when the loop is considered as an alternating current, thereto capacitors C1 and C2 are added, there occurs a situation where, as a total loop, oscillation condition is satisfied at around angular frequency ωo, resulting in oscillation with this frequency. Fig.2 is a modification example of the first embodiment. Since it is a slight modification in which only the order of constituent elements is changed, to the constituent elements identical with Fig.1, the same reference numerals are given to establish correspondence therebetween. This example shows a circuit in which a combination of a transconductor 4 and a capacitor C1 and a combination of a transconductor 5 and a capacitor C2 in Fig.1 are only interchanged. However, since impedance at C point is high, when output of transconductor 5 is connected to input of the transconductor 4 and capacitor C1 as they are, the capacitor C1 becomes a load of the transconductor 5, and condition changes drastically from that of Fig.1. Therefore, by addition of a buffer circuit 3' having gain 1 to convert impedance, matching for this portion is attained. By implementing like this, since the total loop characteristic does not vary even when order of the constituent elements is interchanged, as a whole it operates in an utterly identical manner with Fig.1, and oscillates at the central frequency ωo of the BPF. If the buffer circuit 3' is changed to a negative amplifier having gain -1 identical with an amplifier 3, though the amplifier 3 can be removed, resultantly it becomes a circuit utterly identical with Fig.1. Actual circuits of transconductor and amplifier which are employed in the first embodiment and its modification example shown in Fig.1 and Fig.2 are shown in Fig.3 and Fig.4, respectively. The transconductor, as shown in Fig.3, is constituted of a MOS transistor M1, source thereof is connected to ground, gate thereof is used as input, and constant current Io is supplied from a power source to drain, which is used as an output terminal. This circuit satisfies a condition that this circuit is one that has high negative gain as input/output characteristic of direct current. An amplifier is constituted of MOS transistors M2, M3 as illustrated in Fig.4, source of transistor M2 is connected to ground, gate thereof is used as input, drain thereof is connected to source of M3 to be an output terminal, and gate of transistor M3 is connected to bias voltage VB, drain thereof is connected to power source, respectively. The gain of this circuit is determined by square root of ratio of gate size W/L of the transistor M2 to gate size W/L of the transistor M3. The ratio of the gate sizes between elements can not be set so large that the gain can be varied only in the range of one digit around 1 (0.3 to 3 = -10dB to 10dB). Therefore, the gain is far smaller than that of transconductor. As to input/output characteristic of direct current, it satisfies a condition of the circuit having far smaller negative gain than that of transconductor. Incidentally, in the examples of Fig.1 and Fig.2, the sizes of transistors M2, M3 are made identical to make the gain of direct current "-1". Fig.5 is another modification example of the first embodiment. This modification example is derived from Fig.1 by modifying the circuit in it, that is, two transconductors shown by 12 and 13 are added to Fig.1. The transconductor 12 compensates shift of oscillation condition caused by capacitor C1 which newly becomes load of amplifier 9 when an oscillation loop is constituted by connecting input and output of the BPF. When such an amplifier that is illustrated in Fig.4 is constituted with a CMOS device, output impedance can not be made so low. Therefore, when the capacitor C1 becomes a new load, the oscillation condition shows a relatively large shift. There, by supplying the whole alternating current supplied to capacitor C1 from the transconductor 12, impedance at A point seen from an output of the amplifier 9 is caused to be zero. An alternating current supplied to the capacitor C1 is wholly supplied from transconductor 10. Negative voltage of A point which is input thereof, being C point, by using this as input and converting into current with a conversion factor "-Gm" identical as that of transconductor 10, is supplied to A point which is an opposite electrode of the capacitor C1. Thereby, though current supplied to the capacitor C1 does not vary, at A point, the alternating current supplied through the capacitor C1 is cancelled out by the current which transconductor 12 supplies. Thus, there is no alternating current which the amplifier 9 has to supply, and, even when the input and output of the BPF are connected, oscillation condition does not shift, resulting in obtaining desired oscillation frequency. Transconductor 13 is designated for setting value of Q of the BPF. If there is no transconductance circuit 13, the value of Q becomes infinity to induce rather strong oscillation. When the value of Q is too large, the amplitude of oscillation also becomes large, wave form thereof becomes almost rectangular, and it approaches oscillation of a ring oscillator. Therefore, as described above, there is such a problem that leakage to analogue signal due to the pulse current or spurious occurs. There, this problem is alleviated through reduction of the value of Q of the BPF with transconductor 13. If the value of transconductance is set "-Gm/Q", sharpness of the BPF can be suppressed to Q. The transconductor of Fig.3 and the amplifier of Fig.4 are applied in Fig.5 to rewrite into circuit of element level, which is shown in Fig.6 for explanation. In this circuit, all the NMOS elements are of the same shape and the same size except for transistors M11 and M14, and all the PMOS elements are of the same shape and the same size except for transistor M22. W/L of transistor M11 is twice as large as the principal size of NMOS, and W/L of transistor M14 is one half as large as the principal size of NMOS. W/L of transistor M22 is 3 halves as large as the principal size of PMOS. In Fig.5, an amplifier 9 is constituted of transistors M11 and M15, a transconductor 10 of transistors M12 and M21, a transconductor 11 of transistors M13 and M22, a transconductor 12 of transistors M11 (used in common with the amplifier 9) and M20, a transconductor 13 of transistor M14. As bias voltage of an amplifier, to a circuit which connects the transistors M16 and M17 in series as shown in Fig.6, reference current Ic is supplied by branching at transistor M19, thus obtained voltage is supplied to the gate of the transistor M15. By implementing like this, the bias currents proportional to the gate sizes can be supplied to all NMOS transistors, and current densities at gate regions of all elements can be made equal. At this time, all the operating voltages at the respective nodes of A, B and C constituting the oscillation loop in the figure become equal. Further, if drain currents of transistors M11 to M14 are expressed by Id = k(Vgs - Vth) 2 Gms of the respective transistors of M11 to M14 can be expressed by Gm = δ Id/δ Vgs = 2 ( klc ) As mentioned above, the oscillation frequency fosc becomes fosc = ωo/2π = Gm/{2π C 1 C 2 } = ( klc ) / {π C 1 C 2 } This means that the oscillation frequency can be varied in proportion to the square root of bias current Ic. Thus, by varying the bias current Ic, the oscillation frequency can be readily controlled. In an actual circuit, since a loop gain of an oscillation loop becomes more than 1, the amplitude gradually increases to result in swinging to an operation limit of a transistor. Though not so large as the conventional ring oscillator, it becomes a rather large amplitude and the wave form distortion also becomes large. Thus, normally, in an example of an oscillator shown in Fig.1, a limiter circuit is inserted between A point which is an output of a band-pass filter and the input IN to limit the amplitude. Even in the oscillator shown in Fig.5, a limiter circuit is inserted between A point which is an output of a band-pass filter and the input IN, in this case, however, the output of the transconductance circuit 12 is not the A point, accordingly it is connected to the input IN of the band-pass filter. By thus implementing, the oscillator does not swing to the full source voltage like a ring oscillator which employs the conventional inverter circuit but it can be limited to the amplitude which the limiter circuit restricts. In addition, since it operates not in a complete switching manner but in an approximately continuous area, it does not occur that pulse noise is added to source line. The wave forms at A to C points are small in their amplitudes and close to triangular wave or sinusoidal wave, accordingly harmonic component is slightly contained. Therefore, even if there is an analogue circuit sensitive to harmonic noise in the neighborhood, noise due to leakage through common impedance of source line or due to plunging via space is small. Further, since the oscillation frequency can be made completely independent of the source voltage, even when digital circuit exists together, the pulse noise which is generated in the digital circuit and added on the source line is not likely to interfere to increase jitter (phase noise). Thus, when used in a CMOS-LSI which consolidates analogue/digital circuits including highly accurate analogue signal processing, it is very effective. The second embodiment of the present invention will be described with reference to a diagram depicting circuit configuration of Fig.7. In this embodiment, all the respective constituent elements of the embodiment illustrated in Fig.5 of the first embodiment are converted to differential circuits to be differential as a whole. The transconductor is operated with differential voltage input and differential current output, and, since the output terminal is of high impedance, common voltage gain between input and output is very high. For direct current common voltage, it becomes a negative amplifier having high gain. Though an amplifier is operated with differential voltage input and differential voltage output, the voltage gain of around 1 (at most from 0.1 up to 10) is used for differential gain and common gain. For direct current common voltage, it becomes a negative amplifier having low gain. When a circuit of Fig.7 is constituted with such constituent elements, as common direct current characteristics, respective constituent elements are in inverted relation between input and output, and since the number of constituent elements which constitute loop are 3 of 22, 23, 25, after one round of loop, it becomes negative feedback (phase circulation of 180°) as to direct current. Respective nodes constituting common loop have stable operating points at an intermediate voltage between power source and ground. As to differential operation, primarily respective constituent elements are connected between terminals of the identical polarity, and at only one point the polarity thereof is interchanged to form a loop. In Fig.7, at the point where output of element 25 is inputted in element 22, the polarity thereof is changed. By connecting like this, as to differential direct current characteristics, all the "+ side terminals" and "- side terminals" of respective differential inputs and respective differential outputs are operated to be same voltage. Incidentally, though all the oscillators of Fig.7 are constituted of ones being in inverted relation between input and output, whatever number of circuits which are not in an inverted relation between input and output are inserted to the feedback loop, it is obvious that the function as an oscillator is not changed. Therefore, as elementary circuits constituting the loop, only the circuits which are in an inverted relation between input and output are referred to, whatever number of elementary circuits which are not in an inverted relation can be included. In Fig.7, principal BPF portion is a feedback loop constituted of transconductor 23, transconductor 25 and amplifier 22. The transconductor 23 corresponds to 10 of Fig.5, and the transconductor 25 corresponds to 11 of Fig.5. The amplifier 22 corresponds to 9 of Fig.5, however, it is only for common voltage, and as to differential voltage, the transconductor 25 and the amplifier 22 are connected by changing polarity, thereby "-1" is realized. The role of transconductors 28 and 29 shown by dotted lines in the figure is utterly the same with those of 13 and 12 of Fig.5, respectively. That is, the transconductor 29 compensates shift of oscillation conditions due to capacitive load upon connection of input and output of the BPF, and the transconductor 28 reduces the value of Q of the BPF. Fig.8 is a modification example of the embodiment shown in Fig.7. When the amplifier 22 of Fig.7 is transferred to a position of 26 of Fig.8, in order that the feedback loop of the BPF is to be common negative feedback, an amplifier 24 has to be added to make 3 pieces the number of elements of common inversion on the feedback loop. Actual circuits of transconductor and amplifier being employed in the second embodiment of Fig.7 and Fig.8 are shown in Fig.9 and Fig.10, respectively. The transconductor is constituted of MOS transistors M31 and M32 as shown in Fig.9, source pair thereof being connected to ground, gate pair thereof being used as differential input terminals, a constant current Io being supplied to drain pair thereof from respective power sources, the drain pair being used as differential output terminals. Such a circuit satisfies a condition that it is a circuit having high negative gain for common voltage of direct current. The amplifier is constituted of MOS transistors M33 to M36 as shown in Fig.10, sources of the transistors M33 and M34 being connected to ground, the gate pair being used as differential input terminal, drains being connected to sources of transistors M35 and M36, respectively, to be used as differential output terminals, gates of transistors M35 and M36 being connected to bias voltage VB, drains being connected to source, respectively. The differential gain and common gain of this circuit are determined by square root of ratio of gate size W/L of transistors M33, M34 to gate size W/L of transistors M35, M36. The ratio of gate sizes between elements can not be set so large that the gains can be varied at most in the range of one digit around 1 (0.3 to 3 = -10dB to 10dB). In the embodiments of Fig.7 and Fig.8, all the sizes of transistors M33 through M36 are set identical to obtain common gain of "-1", and differential gain of "1" for direct current. Therefore, the common gain becomes a value far smaller than that of the transconductor, and it satisfies a condition that, for common voltage of direct current, the circuit has a negative gain much smaller than that of the transconductor. In the cases of the oscillators of fully differential type of Fig.7 and Fig.8, another operation of common has to be considered. This circuit is an oscillator, however it should oscillate only in differential mode, but should not oscillate in common. Upon considering common, with ground as reference, average voltage of AA', average voltage of BB' and average voltage of CC' need only to be considered. Capacitance values with respect to ground attaching to output terminals of respective constituent elements, when parasitic capacitance of capacitor is neglected, become C1A//C1B at BB' points, 0 at AA' points, and also 0 at CC' points. That is, in the loops forming a ring of circuits of Fig.7 and Fig.8, a dominating pole appears at BB' point in low frequency, while poles corresponding to AA' point and CC' point appear only in far distant high frequency region. Therefore, at frequency where phase start circulating under influence of poles of AA' point and CC' point, the amplitude attenuates sufficiently due to the dominating pole of BB' point, and the loop gain becomes 1 or less to be able to avoid oscillation. Thus, for common operation, C1A and C1B function as phase compensating capacitors, since phase compensation is carried out as a common loop, accordingly common oscillation does not occur. This is due to insertion of capacitor C2 between terminals of differential output not to attach capacity to ground. Incidentally, even in the case of the second embodiment of Fig.7 and Fig.8, as identical as the case of the first embodiment, the oscillation frequency as an oscillator varies in proportion to the square root of the bias current Ic. By varying the bias current Ic like this, the oscillation frequency can be controlled readily. In addition, in an actual circuit, a limiter circuit is inserted between the output and the input of the band-pass filter to limit the oscillation amplitude. That is, this limiter circuits are inserted between A point and an output terminal out-, and between A' point and an output terminal out+, respectively, in Fig.7, and at the positions of the A point and a +output terminal of the amplification circuit 26, and the A' point and -output terminal of the amplification circuit 26 in Fig.8, respectively. Thus, a circuit configuration according to the second embodiment is less generative of harmonic noise by itself, and is likely to be less influenced by noise added on a power source and the like. Furthermore, since being a fully differential circuit, if outputted differentially, harmonic noise of even order can be suppressed, and jitter due to source noise can be further alleviated. Thus, oscillation signal of high quality can be obtained. The present invention is not restricted to the aforementioned embodiments. For instance, only in a limited amplitude range, the BPF characteristic illustrated in Fig.11 can be obtained. Therefore, in order to oscillate at central frequency of the BPF with stability, the oscillation amplitude is required to be restricted at least to one point on the loop. For this, as shown in Fig.13, a limiter circuit 131 is disposed between output and input of the BPF to restrict oscillation amplitude. Thereby, stable oscillation at the central frequency of the BPF can be obtained. This works as well even in the differential configuration such as described in Fig.7 by restricting oscillation amplitude at least to one point of respective loops. As described above, according to an oscillator being constituted by a CMOS involving the present invention, an oscillator being less generative of noise by itself, and being less influenced by source noise and the like, and of less jitter when analogue/digital consolidated CMOS-LSI is used, can be materialized. Moreover, it can be operated at low voltage, and frequency control over a wide range can be readily carried out only by varying bias current.

Claims: An oscillator suitable for CMOS-LSI, comprising: first and second transconductors (4,5; 10, 11; 23,25), each of which has a voltage/voltage gain of amplification, an inverted voltage/voltage phase, and a certain current/voltage transconductance; an inverter (3; 9; 22+-2i); a first capacitor (C1; C1A, C1B); and a second capacitor (C2); wherein an output end of each constituent element including the first and second transconductors (4,5; 10,11; 23,25) and the inverter (3; 9; 22; 24) is connected to an input end of another constituent element including the first and second transconductors (4, 5 ; 10, 11 ; 23,25) and the inverter (3; 9; 22 ; 24) to form a loop comprising a series connection of the first and second transconductors (4,5; 10,11: 23,25) and the inverter (3 ; 9 ; 22 ; 24), wherein an output end of the first transconductor (4; 10 ; 23) is further connected with one end of the first capacitor (C1; C1A, C1B), and an output end of the second transconductor (5; 11; 25) is further connected with one end of the second capacitor (C2) whose other end is connected to a constant voltage point, to form a band-pass filter whose input end is the other end of the first capacitor (C1 ; C1A.C1B) and whose output end is an input end of the first transconductor (4; 10; 23), the output end of the band-pass filter being connected to the input end of the band-pass filter, and wherein there is an output terminal of the oscillator on the loop. The oscillator as set forth in claim 1, wherein the loop is constituted by connecting the output end of the first transconductor (4) to an input end of the second transconductor (5), the output end of the second transconductor (5) to an input end of the inverter (3), and an output end of the inverter to the input end of the first transconductor (4). The oscillator as set forth in claim 2, further comprising a third transconductor (13), wherein the output end of the second transconductor (11) is further connected to the third transconductor (13) whose input and output ends are short circuited. The oscillator as set forth in claim 2, further comprising a fourth transconductor (12), wherein the input and output ends of the inverter (9) are further connected to the input and output ends of the fourth transconductor (12), respectively, and wherein ratio of a transconductance of the fourth transconductor (12) to the transconductance of the first trans conduct (10) is equal to absolute value of a voltage/voltage gain of the inverter (9). The oscillator as set forth in claim 1; wherein the first and second transconductors (4, 5 ; 10, 11) are each constituted of one first field effect transistor (M1 ; M12, M13) having a source, a gate, and a drain, the sources being connected to a first constant voltage point, the gates being used as input ends of the first and second transconductors (4,5; 10,11), the drains being used as the output ends of the first and second transconductors (4, 5; 10,11), the output ends being further connected to constant current sources (10; M21--M22), and wherein the inverter (3; 9) is constituted of an input side field effect transistor (M2; M11) and an output side field effect transistor (M3; M15), the input side and output side field effect transistors (M2, M3 ; M11, M15) are of the same conductive type as the first field effect transistor (M1; M12,M13) and have a source, a gate and a drain, the source of the input side field effect transistor (M2; M11) being connected to a second constant voltage point, the gate of the input side field-effect transistor (M2; M11) being used as an input end of the inverter (3; 9), the drain of the input side field effect transistor (M2; M11) being connected to the source of the output side field effect transistor (M3; M15) to be an output end of the inverter (3; 9), the gate and the drain of the output side field effect transistor (M3; MIS) being connected to third and fourth constant voltage points, respectively. The oscillator as set forth in claim 5, further comprising: a means (IC) for controlling an oscillation frequency by varying values of first bias currents supplied to the first field effect transistors (M12, M13) of the first and second transconductors (4,5; 10, 11) and second bias currents supplied to the input side and output side field effect transistors (M11; M15) of the inverter (3; 9), while maintaining a ratio of the first bias currents to the second bias currents at a constant value. An oscillator suitable for CMOS-LSI, comprising: first and second-transconductors (23,25), each of which has a pair of differential input ends and a pair of differential output ends, and has a voltage/voltage gain of amplification, an inverted voltage/voltage phase, and a certain current/voltage transconductance; a first inverter (22 ; 24) which has a pair of differential input ends and a pair of differential output ends, and, for a differential voltage, has a certain voltage/voltage gain, and, for a common voltage, has the certain voltage/voltage gain and an inverted voltage/voltage phase; a pair of first capacitors (C1A, C1B); and a second capacitor (C2), wherein a pair of output ends of each constituent element including the first and second transconductors (23, 25) and the first inverter (22 ; 24) are connected to a pair of input ends of another constituent element including the first and second transconductors (23,25) and the first inverter (22 ; 24.) to form a loop comprising a series connection of the first and second transconductors (23,25) and the inverter (22 ; 24), wherein each of the output, ends of the first transconductor (23) are further connected with one end of each of first capacitors (C1A, C1B) respectively, and the second capacitor (C2) is connected between the output ends of the second transconductor (25), to form a band-pass filter which has differential output ends and whose differential input ends are other ends of the first capacitors (C1A, C1B), wherein the output ends of the band-pass filter are connected to the input ends of the band-pass filter, and wherein there is an output terminal of the oscillator on the loop. The oscillator as set forth in claim 7, wherein the loop is constituted by connecting the output ends of the first transconductor (23) to the input ends of the second transconductor (25), the output ends of the second transconductor (25) to the input ends of the first inverter (22), and the output ends of the first inverter (22) to the input ends of the first transconductor (23), and wherein the output ends of the first inverter (22) are used as the output ends of the band-pass filter. The oscillator as set forth in claim 7, further comprising: a second inverter (26) ; wherein the loop is constituted by connecting the output ends of the first transconductor (23) to the input ends of the first inverter (24), the output ends of the first inverter (24) to the input ends of the second transconductor (25), and the output ends of the second transconductor (25) to the input ends of the first transconductor (23), and wherein the output ends of the second transconductor (25) are further connected to input ends of the second inverter (26), and output ends of the second inverter (26) are used as the output ends of the band-pass filter. The oscillator as set forth in claim 8 or claim 9, further comprising a third transconductor (28) having a pair of input ends and a pair of output ends, wherein the output ends of the second transconductor (25) are further connected to the third transconductor (28) whose input and output ends are short circuited in opposite polarities. The oscillator as set forth in claim 8 or claim 9, further comprising a fourth transconductor (29) having a pair of input ends connected to the input ends of the first transconductor (23) and a pair of output ends connected to the input ends of the band-pass filter, wherein either the input connections or the output connections of the fourth transconductor (29) becomes opposite polarity with respect to polarity of the input or output ends respectively of the first transconductor ( 23 ) ; and wherein the ratio of a transconductance of the fourth transconductor (29) to the transconductance of the first transconductor (23) is equal to absolute value of the voltage/voltage gain of the first inverter (22). The oscillator as set forth in claim 7, wherein each of the first and second transconductors (23,25) is constituted of a pair of first field effect transistors (M31, M32) each having a source, a gate, and a drain, the sources being connected to a first constant voltage point, the gates being used as the pair of input ends of the first and second transconductors (23,25), the drains being used as the pair of output ends of the first and second transconductors (23,25), the pair of output ends each being further connected to a constant current source (Io), and wherein the first inverter (22; 24) is constituted of a pair of input side and a pair of output side field effect transistors (M33,M34, M35, M36), the pairs of input side and output side field effect transistors (M33, M34 ; M35,M36) are the same conductive type as the first field effect transistors (M31, M32) and each have a source, a gate, and a drain, the sources of the input side field effect transistors (M33,M34) being connected to second constant voltage points, the gates of the input side field effect transistors being used as the pair of input ends of the first inverter (22; 24), the drains of the input side field effect transistors (M33,M34) being connected respectively to the sources of the-output side field effect transistors (M35,M36) to be used as the pair of output ends of the first inverter (22; 24), the gates and the drains of the output side field effect transistors (M35,M36) being connected respectively to third and fourth constant voltage points. The oscillator as set forth in claim 12, further comprising: a means (14) for controlling an oscillation frequency by varying values of first bias currents supplied to the pairs of first field effect transistors (M31,M32) of the first and second transconduntors (23, 25) and second bias currents supplied to the paid of input side and output side field effect transistors (M33,M34, M35,M36) of the first inverter {22; 24}, while maintaining a ratio of the first bias currents to the second bias currents at a constant value. The oscillator as set forth in claim 1, 2, 7, or 8, further comprising: a limiter circuit, inserted between the output end of the band-pass filter and the input end of the band-pass filter, which limits an amplitude.

Inventors: YAMAMOTO TAKESHI, YAMAMOTO, TAKESHI, Yamamoto, Takeshi c/o Toshiba K.K. Intel.Prop.Div.
Applicants: TOSHIBA KK, KABUSHIKI KAISHA TOSHIBA
Application year: 1999
Main classification: H03B5
IPC codes: H03K3, H03B1, H03B5