Method for programming EEPROM memory devices with improved reliability, and corresponding EEPROM memory device

Abstract: The programming method comprises supplying a turnoff voltage to the source terminal of the selected cells when writing the cells. The turnoff voltage is a positive voltage of greater amplitude than the absolute value of the threshold voltage of the most written cell, i.e., the most depleted cell, taking into account the body effect. For example, the turnoff voltage may be 1 V greater than the absolute value of the threshold voltage of the most written cell. Advantageously, the turnoff voltage may be 5-6 V; to take into account the process, supply, and temperature variations, the turnoff voltage may be 7-8 V. The programming method is advantageously applicable to EEPROM memory devices with divided source lines, so as to apply the turnoff voltage only to the addressed byte or bytes, or to the page containing the addressed byte.

Description: The present invention refers to a method for programming EEPROM memory devices with improved reliability, and to a respective EEPROM memory device. As is known, floating gate EEPROM memory cells are programmed (written and/or erased) by the Fowler-Nordheim effect by injecting charges through a thin tunnel oxide region by applying appropriate voltages between the terminals of the cells. For greater clarity, reference is made to Figure 1, showing a known architecture of an EEPROM memory array 1 belonging to a memory device 10. The memory array 1 comprises a plurality of cells 2 arranged on rows and columns and each formed by a memory transistor 3 and selection transistor 4. The cells 2 are connected in groups so as to form memory bytes (each comprising, for example, eight cells 2). In detail, the control gate terminals of the memory transistors 3 of the cells 2 belonging to a same byte are connected, by a respective gate line 5, to a source terminal of a respective byte enabling transistor 6; the source terminals of all memory transistors 3 are connected to a common source line S by local source lines 8a and source connection lines 8b. The drain terminal of each memory transistor 3 is connected to the source terminal of the respective selection transistor 4. The gate terminals of the selection transistors 4 of the cells 2 arranged on a same row are connected to a same word line 15. The drain terminals of the selection transistors 4 of the cells 2 arranged on a same column are connected to a same bit line 16. The drain terminals of the byte enabling transistors 6 arranged on a same column are connected to a same control gate line 17; and the gate terminals of the byte enabling transistors 6 arranged on a same row are connected to the same word line 15 connected to the selection transistors 4 in the same byte. Figure 1 shows only one portion of the memory array 1 corresponding to four complete bytes and part of another two bytes; Figure 1 shows two word lines 15, indicated by WLm and WLm+1, two bit lines 16 of each byte, corresponding to bit 0 and to bit 7, indicated by BL0 and BL7, and three control gate lines 17, indicated by CGn, GCn+1, CGn+2. The word lines 15 generally extend for the entire width of the memory array 1; the bit lines 16 and control gate lines 17 generally extend for the entire height of the memory array 1. The local source lines 8a are shared by the cells 2 belonging to two adjacent and superposed bytes and are formed preferably by diffusions in the substrate. The source connection lines 8b are common to all memory cells belonging to bytes arranged along two adjacent columns. The source connection lines 8b are formed preferably by metal lines and extend for the entire height of the memory array 1. The typical biasing conditions of the memory array 1 during erase (when electrons are injected into the floating gate regions or positive charges are extracted from the floating gate regions of the memory transistors selected), writing (when electrons are extracted from the floating gate regions or positive charges are injected into the floating gate regions of the memory transistors selected), and reading (when the charge stored in the floating gate regions of the selected memory transistors are sensed) are shown in Table I below. V cg V d V st V s ERASE V PP 0 V ≥ V PP floating WRITE 0 V V PP ≥ V PP floating READ V R 1 V V CC 0 V In Table I, V cg is the voltage applied to the control gate lines 17, V d is the voltage applied to the bit lines 16, V st is the voltage applied to the word lines 15, and V s is the voltage applied to the common source line S. The voltage V PP applied during writing may be different from the voltage V PP applied during erasing, and the voltage V CC is the supply voltage. During programming, the threshold voltage of the cells is modified with respect to the threshold voltage of the virgin cells (not yet written or erased). Preferably, programming is carried out so that the programming window (the limits of which are defined by the threshold voltage of the written cells and by the threshold voltage of the erased cells) is centred with respect to the threshold voltage of the virgin cells, for minimizing the electric field generated by the charges stored in the floating gate region during the operating life of the memory device, and so increasing the reliability of the memory transistors. In particular, writing is performed by applying a high voltage to the drain terminal of the addressed cells and leaving the source terminal floating, as represented schematically in Figure 1 by a two-position selector 12 which selectively connects the common source line S to ground (during reading) or leaves it floating (during writing and erasing). Before writing, the threshold voltage of the addressed cells is greater than that of the virgin cells (because of the negative charges stored in the floating gate region). During writing, the threshold voltage becomes smaller than zero, so that the written memory transistors turn on even with the control gate region grounded (depleted memory transistor), as shown in Figure 2, which presents the characteristics of an EEPROM cell during writing and erasing. In particular, Figure 2 shows the plot of the threshold voltage versus time in case of write pulses of different amplitude and erase pulses of the same amplitude. When, during writing, the memory transistor turns on, it conducts current and charges the capacitive load associated to its own source terminal. Since the source line S is common to the entire memory array 1, its capacitance is not negligible (for example, it is greater than 1 nF for a 1-Mb memory array), and the source terminal may be considered essentially connected to ground, at least in the transient phase. During this short time interval, the cells that are written more quickly (i.e., the cell or cells that get depleted before the others) conduct a high current. This current is interrupted when the voltage on the source terminal, and hence on the common source line S, is such that all the addressed cells are off (V GS < V T , where V T is the threshold voltage of the addressed cells and V GS is the voltage drop between the control gate and source regions of the cells). In practice, during writing, the common source line S is charged by the current of the cells as soon as the latter turn on. This transient current is undesired, in that it reduces the reliability of the concerned memory cells. In addition, it causes the charge pump circuits used for generating the high write voltage V PP to be oversized, in that they must withstand not only the tunnel current (and the current of the drain diode, which is reverse biased), but also the current required for charging the source capacitance. In addition, during each programming operation, the source voltage increases (up to 5-6 V), thus inducing a possible source disturbance for the entire memory array 1. US-A-5 790 460 discloses an erase method for a flash-EEPROM, that has no selection transistor and is biased so as not to go depleted. In this document, erasing is erased by FN effect so as to extract electrons from the floating gate and discharge them to the source region. The drain is kept floating or connected to the source. EP-A-646 933 discloses a flash memory programming method using the CHE (channel hot electron) injection mechanism requiring a high channel current (between source and drain) so that some carriers may be accelerated and injected into the floating gate. The aim of the present invention is to provide a programming method free from the above described drawbacks. According to the present invention, a programming method for EEPROM memory devices, and an EEPROM memory device are provided, as defined in Claims 1 and 7, respectively. For a better understanding of the invention, embodiments thereof will now be described, purely to provide nonlimiting examples, with reference to the attached drawings, wherein: Figure 1 illustrates the architecture of a known EEPROM memory cell; Figure 2 shows the characteristics of EEPROM cells during programming; Figure 3 shows a first embodiment of the EEPROM memory according to the invention; Figure 4 shows a second embodiment of the EEPROM memory according to the invention; and Figure 5 shows a third embodiment of the EEPROM memory according to the invention. The programming method according to the invention applies a turnoff voltage at the source terminals of the cells to be written, according to Table II shown below. V cg V d V st V s ERASE V PP 0 V ≥ V PP floating WRITE 0 V V PP ≥ V PP V OFF READ V R 1 V V CC 0 V In-Table II, the given quantities have the same meaning as in Table I, and the voltage V OFF is a positive voltage of greater amplitude than the absolute value of the threshold voltage V T of the most written cell, i.e., the most depleted cell (obtainable, for example, from the characteristics of Figure 2), taking into account the body effect. For instance, V OFF may be 1 V higher than the absolute value of the threshold voltage of the most written cell. Advantageously V OFF may be 5-6 V. In order to take into account the process and/or supply and/or temperature variations, it is, however, preferable to have a sufficient margin with-respect to the worst case of the most depleted cell, and in this case V OFF may be 7-8 V. Alternatively, V OFF may be also set at V PP so as to reduce the number of controlled voltages to be generated and managed within the memory device 10. In this source biasing condition, none of the addressed memory transistors 3 may turn on during writing; consequently, no source-to-drain current flows in their channels. As a result, the reliability of the cells 2 increases. The requisites set for the charge pump circuits are less stringent and well defined in all the conditions -also in the global modalities during final electrical wafer sorting (EWS) tests. The biasing method according to the invention, as described above, can be implemented in different ways. The simplest solution is illustrated in Figure 3, showing a memory device 10 including a memory array 1 having the same architecture as in Figure 1 and described above. Unlike Figure 1, however, the common source line S is connected to a three-position selector 20: the first position enables connection of the common source line S to ground; the second position causes the common source line S to float; and the third position connects the common source line S to a turnoff voltage generator 21. During writing, the bit line 16 of the addressed memory cells is biased at V PP ; the word line 15 of the addressed words is biased at a voltage higher than V PP ; and the common source line S is biased at V OFF , as described above. Consequently, the memory transistors 3 of the addressed cells 2 have their respective gate terminals grounded, their drain terminals biased at V PP , and their source terminal biased at V OFF , and they are off during the entire writing phase. In the shown example, the voltage V OFF is generated internally. Alternatively, it can be supplied from outside; if necessary, it may be equal to V PP . The V OFF voltage may be supplied to the common source line S before or simultaneously with the start of the programming pulse (when the bit line of the cell to be written is biased). Optionally, a shaping circuit may be used, similar to the one used for V PP . In this case, it must, however, be ensured that the local source lines 8a reach the voltage V OFF before any memory cell becomes depleted. Figure 4 illustrates a different embodiment of the memory device 10, wherein the memory array 1 has an organization such as to supply the turnoff voltage V OFF only to the source lines of the addressed cells; namely, the source terminals of the cells 2 are addressable only at a byte level via the word line switch and the column switch (neither shown). In detail, in Figure 4 the cells 2 have the same connection described above with reference to Figure 3, except for the fact that each local source line 8a (connected to the memory transistors 3 of two superimposed bytes) is connected to the source terminals of two source biasing transistors 25, one for each byte. Each source biasing transistor 25 is horizontally aligned with the selection transistors 4 belonging to the same byte and has its gate terminal connected to the word line 15 that biases the respective byte. In addition, each source biasing transistor 25 has its drain terminal connected to a divided source line 26. The divided source lines 26 extend for the entire height of the memory array 1. Each divided source line 26 is connected to an own selector 20, which is similar to the one shown in Figure 3 and has three positions: the first position grounds the respective divided source line 26; the second position causes the respective divided source line 26 to float; and the third position connects the respective divided source line 26 to the turnoff voltage generator 21. The selectors 20 are arranged outside the memory array 1. The source biasing transistors 25 are then controlled by the voltage V st applied on the word lines 15 and are turned on only when the respective row is addressed. In this case, they transfer the voltage present on the respective divided source line 26 to the local source line 8a connected to them. Only the divided source lines 26 connected to the addressed bytes receive the voltage V OFF from the turnoff voltage generator 21, so that only the local source lines 8a connected to the addressed byte (and to the byte coupled to it) receive the voltage V OFF . Advantageously, the selectors 20 are controlled by signals ..., cn, cn + 1, ... generated by the decoder that determines biasing of the control gate lines 17 during the write pulse, as represented schematically in Figure 4 by the decoder 28, of which only the pass transistors 29 connected to the control gate lines CGn, CGn + 1, and CGn + 2 are shown. As may be noted, the control terminals of pass transistors 29 are controlled by the same control signals ..., cn, cn + 1, ... of the selectors 20. This solution has the advantage of reducing the capacitance associated to each local source line, since only one portion of the memory array 1 is connected to the addressed byte or bytes. In this way, the peak current and the total charge flowing through the fastest cells in the writing phase are limited. Consequently, the overall reliability is improved, the source noise is reduced, and the capacitance of the charge pump circuits may be lower. The complexity of the circuitry is not, on the other hand, worsened, since the control signals of the selectors 20 are already present in the memory device 10. Figure 5 shows a third embodiment, wherein each page (i.e., the cells 2 connected to a same word line 15) has the source line separated from the other pages; namely, the source terminals of the cells 2 are addressable at page level. In detail, in Figure 5 the cells 2 have the same arrangement as described above with reference to Figure 1, except for the fact that one page source line 30 is provided every two word lines 15. Specifically, all the memory transistors 3 belonging to cells 2 arranged on two adjacent rows (connected to two adjacent word lines 15) have respective source terminals connected to the same page source line 30. The page source lines 30 extend for the entire width of the memory array 1 and are connected to a respective switch 31, which, together with a similar switch 32 arranged between the page source line 30 and ground, implements a selector similar to selectors 20 of Figures 3 and 4. Advantageously, the switches 31 are arranged outside the memory array 1 where space requirements are less critical. This solution, which is particularly suited to memory arrays of the PEROM (ROM memories programmable at a page level) type, enables a reduction in the total area of the memory array 1, since the source connection lines 8b, which extend vertically between horizontally adjacent bytes, are eliminated (see Figures 1 and 3). The advantages of the described method and memory device are clear from the above description. In particular, it is emphasized that the current consumption during programming is considerably reduced. In addition, when the source line is divided at the byte or page level, the performance in user mode during programming is improved, in so far as the charge pump circuits have a smaller capacitive load to be charged. Finally, it is evident that modifications and variations may be made to the above described method and memory device, without thereby departing from the scope of the present invention. In particular, in the solutions with divided source line (Figure 4 or Figure 5), the source switches can be arranged in any suitable position; for example, in the embodiment of Figure 4, they can be arranged near to the control gate lines 17 or between the bit lines associated to adjacent bytes, if the layout so permits.

Claims: A method for programming EEPROM memory devices by Fowler-Nordheim effect, the memory device comprising a memory array (1) including a plurality of memory cells (2), each memory cell comprising a memory transistor (3) and a selection transistor (4), the memory transistor having a floating gate region, a drain terminal and a source terminal, the method comprising the step of generating a tunnel current between said floating gate region and said drain terminal of at least one selected cell, characterized by supplying a turnoff voltage to said source terminal of said selected cell during the step of generating a current, the turnoff voltage maintaining the selected cell off and preventing source-to-drain current from flowing. The method according to Claim 1, characterized in that said step of generating a tunnel current is a write step and comprises extracting negative charges from said floating gate region of said selected cell. The method according to Claim 1 or Claim 2, characterized in that said turnoff voltage is greater than the absolute value of the threshold voltage of said selected cell. The method according to Claim 3, characterized in that said turnoff voltage is greater than 5-6 V. The method according to Claim 4, characterized in that said turnoff voltage is greater than 7-8 V. The method according to Claim 3, characterized in that said step of generating comprises the step of programming said drain terminal of said memory transistor and in that said turnoff voltage is equal to said programming voltage. An EEPROM memory device of the type programmable by Fowler-Nordheim effect, comprising a memory array (1) including a plurality of memory cells (2), each memory cell comprising a memory transistor (3) and a selection transistor (4), the memory transistor having a floating gate region, a drain terminal and a source terminal, means (15-17) for causing a tunnel current between said floating gate region and said drain terminal of at least one selected cell, characterized by means (20, 21, 26, 30, 31, 8a, 8b) for supplying a turnoff voltage to said source terminal of said selected cell, said means for supplying said turnoff voltage being activated at the same time as said means for causing a tunnel current, maintaining the selected cell off and preventing source-to-drain current from flowing. The device according to Claim 7, characterized in that said means (20, 21, 26, 30, 31, 8a, 8b) for supplying a turnoff voltage comprise a switch (20, 31) arranged between a turnoff voltage generator (21) and said source terminal. The device according to Claim 8, characterized in that said means (20, 21, 26, 30, 31, 8a, 8b) for supplying a turnoff voltage further comprise a common source line (8b) connected to said source terminals of said memory transistors (3) through local source lines (8a). The device according to Claim 7 or Claim 8, characterized in that said means (20, 21, 26, 30, 31, 8a, 8b) for supplying a turnoff voltage further comprise a plurality of divided source lines (26), a plurality of local source lines (8a), and a plurality of control gate lines (5); in that said memory array (1) comprises a plurality of groups of said cells (2), each group of cells forming a byte; in that the memory transistors (3) of the cells (2) of a byte have source terminals connected to a same local source line (8a) and control gate regions connected to a same control gate line (5); and in that said divided source lines (26) are connected to said local source lines (8a) through source biasing transistors (25). The device according to Claim 10, characterized in that it comprises a plurality of word lines (15), a plurality of local byte enabling transistors (6), each transistor being arranged between a respective control gate line (5) and a respective word line (15); in that it comprises one said source biasing transistor (25) for each byte; and in that each said source biasing transistor has a control terminal connected to a respective word line (15) and is aligned to a respective byte enabling transistor (6). The device according to Claim 8, characterized in that said memory cells (2) extend along a plurality of rows; in that said means (20, 21, 26, 30, 31, 8a, 8b) for supplying a turnoff voltage further comprises a plurality of divided source lines (30); in that the memory cells arranged on a same row have source terminals connected to a the same divided source line; and in that said divided source lines are connected to said turnoff voltage generator (21) through a respective switch (31).

Inventors: GOMIERO ENRICO, PIO FEDERICO, GOMIERO, ENRICO, PIO, FEDERICO
Applicants: ST MICROELECTRONICS SRL, STMICROELECTRONICS S.R.L.
Application year: 1999
Main classification: G11C16
IPC codes: G11C16