POWER AMPLIFIER

Abstract: To provide a variable gain power amplifier with wide dynamic range of transmission power, wherein power efficiency is high, distortion in the linearity is low. In an amplifier with a plurality of transistors connected with cascade, the source of transistor (103) is grounded, the gate of transistor (108) of an output stage is grounded. Further, source bias terminal (109) and drain bias terminal (110) is provided for applying prescribed voltages to the source and drain of transistor (108) of the output stage, respectively. The electric power inputted into transistor (108) of the output stage is passed through without being amplified by applying the prescribed voltages to source bias terminal (109) and drain bias terminal (110), respectively, when the electric power outputted from the output stage is made smaller than a prescribed threshold.

Description: Technical Field The present invention relates to a power amplifier which amplifies UHF, micro wave and millimeter wave signals with a wide dynamic range. Background Art Recently, there is an increasing demand for power amplifiers as one of the key device of pocket telephone in a mobile communication system. A high gain, high output power, and high efficiency are required for such a power amplifier. Figure 12 is a block diagram of one of the examples of conventional power amplifiers. As shown in Figure 12, FET 403 and FET 408 are connected in cascade with their sources grounded. The gates of FETs 403 and 408 are connected both with input matching circuits 402 and 407 and with gate bias terminals 404 and 409, respectively, while the drains of FETs 403 and 408 are connected both with draun bias terminals 405 and 410 and with output matching circuits 406 and 411, respectively. Further, the drain of FET 403 is connected with the gate of FET 408 through output matching circuit 406 and input matching circuit 407. Further, in order to improve a spectral efficiency of the pocket telephones, code division multiple access (CDMA) using spread spectrum is being put into practical use. It is required in the CDMA that transmission output power be controlled within 80 dB to cope with the near-far problem, and that an envelope be detected precisely. Accordingly, the linearity of the amplifier for CDMA should be more strictly guaranteed than the conventional amplifiers. Figure 13 is a block diagram of one of the conventional transmission output power controller. The conventional power controller as shown in Figure 13, which controls the power inputted into power amplifier 416 by using variable gain amplifier 415, comprises radio frequency signal generator 413, modulator 414 for modulating the output from radio frequency signal generator 413, power amplifier 416 for amplifying the output from modulator 414, variable gain amplifier 415 for controlling power amplifier 416, antenna duplexer, and antenna 418. As mentioned above, the amplifier for CDMA should be a low distortion, high power, and linear amplifier. However, the conventional amplifiers have a disadvantage that the electric power is consumed vainly, because the power efficiency by the combination of the variable gain amplifier and the power amplifier is much smaller for the minimum power input than for the maximum power input. Therefore, an object of the present invention is to provide a power amplifier with high power efficiency, low distortion, and variable gain in wide dynamic range. Disclosure of the Invention In short, the power input into the output stage of the power amplifier is passed through without amplification, when the desired output power of the power amplifier of the present invention is smaller than a prescribed threshold. Therefore, the power efficiency becomes high, even when the transmission power is small. Brief Explanation of the Drawings Figure 1 is a block diagram of a power amplifier of the first mode of embodiment of the present invention. Figure 2 is a graph indicating an input-output relation and power efficiency of the input stage FET as shown in Figure 1. Figure 3 is a graph indicating an input-output relation and power efficiency of the output stage FET as shown in Figure 1. Figure 4 is a graph indicating an input-output relation, when the transmission output power is small in the output stage FET as shown in Figure 1. Figure 5 is a block diagram of a power amplifier of the second mode of embodiment of the present invention. Figure 6 is a block diagram of a power amplifier of the third mode of embodiment of the present invention. Figure 7 is a graph indicating an input-output relation and power efficiency of the input stage FET as shown in Figure 6. Figure 8 is a graph indicating an input-output relation and power efficiency of the output stage FET as shown in Figure 6. Figure 9 is a block diagram of a power amplifier of the forth mode of embodiment of the present invention. Figure 10 is a graph indicating an example of the input-output relation of the input stage FET. Figure 11 is a graph indicating an example of the input-output relation of the output stage FET. Figure 12 is a block diagram of one of the conventional power amplifiers. Figure 13 is a block diagram of one of the conventional circuit for transmitting variable power output wave. The Best Mode for Carrying out the Invention In the following, the modes of embodiment of the present invention are explained, referring to the drawings. (First Mode of Embodiment) Figure 1 is a block diagram of the power amplifier of the first mode of embodiment of the present invention. As shown in Figure 1, FET 103 with grounded source is connected in cascade with FET 108 with grounded gate. The gate of FET 103 is connected with both of input matching circuit 102 and gate bias terminal 104, while the drain of FET 103 is connected with both of drain bias terminal 105 and output matching circuit 106. The source of FET 108 is connected with both of input matching circuit 107 and source bias terminal 109, while the drain of FET 108 is connected with both of drain bias terminal 110 and output matching circuit 111. Further, the drain of FET 103 is connected through output matching circuit 106 and input matching circuit 107 with the source of FET 108. In the following, the operation of the amplifier of the first mode of embodiment is explained. Figure 2 is a graph indicating input-output characteristic and power efficiency of FET 103 at 950 MHz. In the linear amplification region of FET 103 as shown in Figure 2, 15 dBm output power and 50 % power efficiency are obtained for - 5 dBm input power. Figure 3 is a graph indicating input-output characteristic and power efficiency of FET 108 as shown in Figure 1 of which gate is five times wider than that of FET 103 to output greater power. In the linear amplification region of FET 108 as shown in Figure 3, 25 dBm output power and 40 % power efficiency are obtained for 15 dBm input power. By using FET 103 and FET 108 of which characteristics are shown in Figures 2 and 3, respectively, 25 dBm output power and 40 % power efficiency are obtained for -5 dBm input power. Here, in FET 103, the gate bias voltage is, for example, -1 V and the drain bias voltage is, for example, 5 V. Further, in FET 108, the gate bias voltage is, for example, 0 V, the source bias voltage is, for example, -1 V, and the drain bias voltage is, for example, 5 V, although biasing voltages of FET 108 may be arbitrary, when the gate of FET 108 is AC grounded in the operating frequency. On the other hand, the input power goes through FET 108 without being amplified, when the source voltage and the drain voltage become, for example, 0 V, if variable gain control voltage VC is applied to source bias terminal 109 and drain bias terminal 110 in order to operate the amplifier of the present invention in a smaller output region, for example, 0 dBm output power. Figure 4 is a graph indicating the input-output relation of FET 108 in a smaller output power region. As shown in Figure 4, 0 dBm output power is obtained for 0 dBm input power. When - 20 dBm is inputted into FET 103, the output from FET 108 becomes 0 dBm, and total power efficiency becomes 30 % which depends only upon FET 103. Thus, the input power passes through FET 108 without amplification, when variable gain control voltage VC is applied to source bias terminal 109 and drain bias terminal 110 in a smaller output region of the amplifier of the present invention. Thus, the amplifier of the present invention operates under a higher power efficiency. More than 2 transistors may be employed, although only two transistors 103 and 108 are illustrated in Figure 1. (Second Mode of Embodiment) Bipolar transistors are employed in place of FETs 103 and 108 as shown in Figure 1. Figure 5 is a block diagram of the second mode of embodiment of the present invention. As shown in Figure 5, bipolar transistor 113 with grounded emitter is connected in cascade with bipolar transistor 116 with grounded base. The base of bipolar transistor 113 is connected with both of input matching circuit 102 and base bias terminal 114, while the collector of bipolar transistor 113 is connected with both of collector bias terminal 115 and output matching circuit 106. The emitter of bipolar transistor 116 is connected with both of input matching circuit 107 and emitter bias terminal 117, while the collector of bipolar transistor 116 is connected with both of collector bias terminal 118 and output matching circuit 111. Further, the collector of bipolar transistor 113 is connected through output matching circuit 106 and input matching circuit 107 with the emitter of bipolar transistor 116. The input power goes through bipolar transistor 116 without being amplified, when variable gain control voltage VC is applied to emitter bias terminal 117 and collector bias terminal 118 in a smaller output region of the amplifier of the present invention. Thus, the amplifier of the present invention operates under a higher power efficiency. (Third Mode of Embodiment) Figure 6 is a block diagram of the third mode of embodiment of the present invention. As shown in Figure 6, FET 203 with grounded gate is connected in cascade with FET 208 with grounded gate. The source of FET 203 is connected with both of input matching circuit 202 and source bias terminal 204, while the drain of FET 203 is connected with both of drain bias terminal 205 and output matching circuit 206. The source of FET 208 is connected with both of input matching circuit 207 and source bias terminal 209, while the drain of FET 208 is connected with both of drain bias terminal 210 and output matching circuit 211. Further, the drain of FET 203 is connected through output matching circuit 206 and input matching circuit 207 with the source of FET 208. In the following, the operation of the amplifier of the third mode of embodiment is explained. Figure 7 is a graph indicating input-output characteristics and power efficiency of FET 203 as shown in Figure 6 at 950 MHz. In the linear amplification region of FET 203 as shown in Figure 7, 15 dBm output power and 40 % power efficiency are obtained for 0 dBm input power. Figure 8 is a graph indicating input-output characteristics and power efficiency of FET 208 as shown in Figure 6 of which gate is five times wider than that of FET 203 to output greater power. In the linear amplification region of FET 208, 25 dBm output power and 40 % power efficiency are obtained for 15 dBm input power, as shown in Figure 8. By connecting, in the manner as shown in Figure 6, FET 203 with FET 208 of which characteristics are shown in Figures 7 and 8 respectively, 25 dBm output power and 40 % power efficiency are obtained for 0 dBm input power. Here, in FETs 203 and 208, the gate bias voltage is, for example, 0 V, the source bias voltage is, for example, - 1 V and the drain bias voltage is, for example, 5 V. On the other hand, the input power goes through FET 208 without being amplified, when the source voltage and the drain voltage become, for example, 0 V, if variable gain control voltage VC is applied to source bias terminal 209 and drain bias terminal 210 in order to operate the amplifier of the present invention in a smaller output region, for example, 0 dBm output power. The input-output characteristic of FET 208 in a small output region is similar to that as shown in Figure 4. 0 dBm output power is obtained for 0 dBm input power. When - 15 dBm is inputted into FET 203, the output from FET 208 becomes 0 dBm, and total power efficiency becomes 30 % which depends only upon FET 203. Further, the power inputted into FET 203 goes through FET 208 without being amplified, when variable gain control voltage VC is applied to source bias terminal 209 and drain bias terminal 210 in a smaller output region of the amplifier of the present invention. Therefore, the power consumed by the amplifier of the present invention is very small in the small input-output region. Thus, the input power goes through FET 208 without being amplified, when variable gain control voltage VC is applied to source bias terminal 209 and drain bias terminal 210 in a smaller output region of the amplifier of the present invention. Thus, the amplifier of the present invention operates under a higher power efficiency. More than 2 transistors may be employed, although only two transistors 203 and 208 are illustrated in Figure 6. (Forth Mode of Embodiment) Bipolar transistors are employed in place of FETs 203 and 208 as shown in Figure 6. Figure 9 is a block diagram of the forth mode of embodiment of the present invention. As shown in Figure 9, bipolar transistor 213 with grounded base is connected in cascade with bipolar transistor 216 with grounded base. The emitter of bipolar transistor 213 is connected with both of input matching circuit 202 and emitter bias terminal 214, while the collector of bipolar transistor 213 is connected with both of collector bias terminal 215 and output matching circuit 206. The emitter of bipolar transistor 216 is connected with both of input matching circuit 207 and emitter bias terminal 217, while the collector of bipolar transistor 216 is connected with both of collector bias terminal 218 and output matching circuit 211. Further, the collector of bipolar transistor 213 is connected through output matching circuit 206 and input matching circuit 207 with the emitter of bipolar transistor 216. The input power goes through bipolar transistor 216 without being amplified, when variable gain control voltage VC is applied to emitter bias terminal 217 and collector bias terminal 218 in a smaller output region of the amplifier of the present invention. Thus, the amplifier of the present invention operates under a higher power efficiency. (Fifth Mode of Embodiment) The power amplifier of the fifth mode of embodiment is explained, wherein the gate widths of FETs 203 and 208 as shown in Figure 6 are almost the same. The power amplifier of the fifth mode of embodiment comprises a first amplifier and a second amplifier, wherein the first amplifier is connected with the first input-output matching circuit which allows the linear gain of the first amplifier to be greater than that of the second amplifier, while the second amplifier is connected with the second input-output matching circuit which allows the output power from the second amplifier to be greater than that of the first amplifier. Figure 10 is a graph indicating an example of the input-output characteristic of the first amplifier at 950 MHz. Figure 11 is a graph indicating an example of the input-output characteristic of the second amplifier. As shown in Figure 10, the first amplifier has a linear gain 15 dB, which is greater than that of the second amplifier, for -5 dBm input and can output 10 dBm output power. However, the output from the first amplifier saturates at the input power 10 dBm. On the other hand, the second amplifier maintains the linearity even at the input power 10 dBm and can output 20 dBm output power which is greater than that of the first amplifier. As explained above, the FETs with grounded gates in the fifth mode of embodiment have different, although their sizes are the same. These FETs are connected with each other, in the manner as shown in Figure 6. The source and drain of these FETs with grounded gates in the input stage and output stage are controlled by variable gain control voltage VC. For example, when the source bias voltage and the drain bias voltage of the first amplifier provided in place of FET 203 become 0 V, the power inputted into the first amplifier goes through without being amplified and is transferred to the second amplifier. Further, for example, when the source bias voltage and the drain bias voltage of the second amplifier provided in place of FET 208 become 0 V, the power inputted into the second amplifier goes through without being amplified. Thus, the power efficiency and the linearity is optimized for the levels of the input power and the output power. More than 2 transistors may be employed, although only two transistors are employed in the above-mentioned explanation of the fifth mode of embodiment. The FETs may be replaced by bipolar transistors with grounded bases, whereby the input power goes through one of the bipolar transistors or both of the bipolar transistors without being amplified, when variable gain control voltage VC is applied to the bipolar transistors in a smaller output region of the amplifier. Thus, the amplifier of the present invention operates under a higher power efficiency.

Claims: A power amplifier with a plurality of transistors connected in cascade which comprises: an input stage including one or more FETs (103) with grounded sources; an output stage including one or more FETs (108) with grounded gates; and a plurality of bias terminals connected with the sources and drains of said transistors in said output stage, characterized in that the power inputted into said output stage passes through said output stage without being amplified by applying a corresponding control voltage to said bias terminals when the desired output power from said output stage is smaller than a prescribed threshold. A power amplifier with a plurality of transistors connected in cascade which comprises: an input stage including one or more bipolar transistors (113) with grounded emitters; an output stage including one or more bipolar transistors (116) with grounded bases; and a plurality of bias terminals connected with the sources and drains of said transistors in said output stage, characterized in that the power inputted into said output stage passes through said output stage without being amplified by applying a corresponding control voltage to said bias terminals when the desired output power from said output stage is smaller than a prescribed threshold. A power amplifier with a plurality of transistors connected in cascade which comprises: an input stage including a first FET (203) with grounded gate; an output stage including a second FET (208) with grounded gate; and a plurality of bias terminals connected with the sources and drains of said FETs, characterized in that the power inputted into said output stage passes through said output stage without being amplified by applying a corresponding control voltage to said bias terminals when the desired output power from said output stage is smaller than a prescribed threshold. A power amplifier with a plurality of transistors connected in cascade which comprises: an input stage including a first bipolar transistor (213) with grounded base; an output stage including a second bipolar transistor (216) with grounded base; and a plurality of bias terminals connected with the emitters and collectors of said bipolar transistors, characterized in that the power inputted into said output stage passes through said output stage without being amplified by applying a corresponding control voltage to said bias terminals when the desired output power from said output stage is smaller than a prescribed threshold. The power amplifier according to Claim 3, wherein which further comprises: a first input output matching circuit which is connected with said FET with grounded gate of said input stage, and which makes a linear gain of said FET with grounded gate of said input stage greater than a linear gain of said FET with grounded gate of said output stage; and a second input output matching circuit which is connected with said FET with grounded gate of said output stage, and which makes an output power of said FET with grounded gate of said output stage greater than an output power of said FET with grounded gate of said input stage. The power amplifier according to Claim 4, wherein which further comprises: a first input output matching circuit which is connected with said bipolar transistor with grounded base of said input stage, and which makes a linear gain of said bipolar transistor with grounded base of said input stage greater than a linear gain of said bipolar transistor with grounded base of said output stage; and a second input output matching circuit which is connected with said bipolar transistor with grounded base of said output stage, and which makes an output power of said bipolar transistor with grounded base of said output stage greater than an output power of said bipolar transistor with grounded base of said input stage.

Inventors: SUZUKI YASUYUKI, SUZUKI, YASUYUKI
Applicants: NIPPON ELECTRIC CO, NEC CORPORATION
Application year: 1999
Main classification: H03F1
IPC codes: H03F1, H03G1, H03F3