METHOD FOR FORMING SILICIDE REGIONS ON AN INTEGRATED DEVICE

Abstract: The invented method can be used to form silicide contacts to an integrated MISFET device. Field isolation layers (20) are formed to electrically isolate a portion of the silicon substrate (1), and gate (22), source and drain regions (24, 25) are formed therein. A polysilicon runner(s) (23) that makes an electrical connection to the integrated device, is formed on the isolation layers (20). The structure is subjected to ion implantation to amorphize portion of the silicon gate (22), source (24), drain (25) and runner regions (23). A metal layer (34) is formed in contact with the amorphized regions, and the metal layer overlying the active region of the integrated device is irradiated using a mask (35). The light (36) melts part of the gate, and amorphized source and drain regions while the remaining portions of the integrated device and substrate remain in their solid phases. Metal diffuses into the melted gate, source and drain regions which are thus converted into respective silicide alloy regions (37, 38, 40, 42). Preferably, during selective irradiation, a portion of the gate region is not exposed to light so that it is relatively cool and acts as a heat sink to draw heat away from the irradiated portion of the gate region. The heat sink effect causes the gate silicidation rate to more closely correspond with the relatively slow source and drain silicidation rates. The method further includes a blanket irradiation step to diffuse metal into the runner regions to form silicide alloy regions which are then treated to form silicide regions.

Description: METHOD FOR FORMING SILICIDE REGIONS ON AN INTEGRATED DEVICE Cross-Reference to Related Applications Thispatent application is a continuation-in-part of applicationno.08/791,775 filed January 29, 1 97, in which the named inventors and assignee entity are the same. Background of the Invention 1. Field of the Invention This invention is directed to a method for forming silicide regions for low- resistance electrical connections to integrated devices formed on silicon substrates. The reduced contact resistances provide the devices with the capability to operate at relatively high speeds. 2. Description of the Related Art Many techniques have been developed for forming silicide regions for integrated device contacts, particularly for metal-oxide-semiconductor (MOS) devices formed on silicon substrates. Most of these techniques invob/e the formation of a metal layer over gate, drain or source regions upon which the silicide is desired to be formed. These techniques then usethermal treatment for extended periods of time to react the metal with the silicon composing the gate, drain and/or source regions, to form the low*resistivity siKcideregiotts. Thesubstrate is f rtherprocessed by removing the unreacted metal layer. Techniques for forming suicides are subject to several stringent process constraints that must be met in order for such techniques to be effective. These constraints include: ( 1 ) the metal used to form the silicide and the temperature at which the silicide is formed must be carefuhy selected so that the metal diffuses into the silicon, to avoid the formation of leakage paths between the source, drain and gate of an integrated device; (2) for self-aligned silicidation techniques, the metal layer must not react with the insulating material composing the side walls of the gate; (3) the dopants must not segregate appreciably into the silicide regions so that low contact resistance can be achieved; (4) the technique should have a process window that allows the silicide region to be formed on_ both c-silicon and poly-silicon; (5) the sihcide formation should be insensitive to dopants present in the silicon; and (6) the metal atoms should not diffuse beyond the sihcide regions to prevent increase injunction leakage. The simultaneous achievement of all of the above- stated criteria is at best difficult for most conventional silicidation techniques, especially those that use relatively extensive thermal treatments. Most often, a failure to perform the conventional technique within its relatively narrow process margins manifests itself in the occurrence of defects due to thermal drift of the metal atoms beyond desired boundaries during the relatively prolonged thermal treatment periods required by such techniques. If the sihcide region extends beyond its design dimensions, it can cause leakage paths between the gate, source drain and the substrate. There is therefore a great need for a technique that enhances silicidation process margins beyond those conventionally available. In addition to conventional techniques that use prolonged thermal treatments, some conventional silicidation techniques use ion implantation to achieve formation of the sihcide regions. These ion-implantation siKcidation techniques use either ion beam mixing of different ion types to produce a sihcide of a desired composition, or implantation of a desired species of metal ions in a proportion needed to achieve proper stoichiometry. In either of these two types of techniques, the ion-implantation is so extensive as to be extremely time-consuming, especially if a stoichiometric proportion of ions needed to make the sihcide must be implanted into the silicon substrate. In addition, extensive ion implantatiott will eventually lead to • knock-on', a phenomenon in which moving ions strike ions previously implanted, driving them further than desired into the silicon substrate. The occurrence of knock-on leads to increased junction leakage. Thus, there is a significant need for a technique that can overcome the above-noted disadvantages of conventional siKcidation techniques. A constraint of the siKcidation techniques discussed above is that the silicide thickness over the gate and the polysiKcon runners is the same as that over the source/drain regions. As source/drain junctions are scaled to shaUower depths, the sihcide thickness over the source/drain also needs to be lowered to prevent leakage. However, sihcide thickness scaring is not necessary over the gate region and it is in fact advantageous to have thicker siKcide over the gate than the source/drain. Such a sihcide can be formed either by depositing a thicker metal layer over the gate than the_ source/drain, or by subjecting the gate to a higher thermal budget. Neither of these two options are feasible using conventional silicide formation techniques. Summary TWsinverrtionovercomestheabove-noted disadvantages. Apreferred embodiment of the invented method includes a step of producing amorphous regions on the gate, source, drain and runnerfs) of an integrated device formed on a sihcon substrate. The method also includes a step of forming a metal layer in contact with the amorphous regions, and a stepof setectrvely irradiating the metal layer with Kght to diffuse metal into the gate, and amorphous source and drain regions to form respective alloy regions of sfficide composition. The method further includes a step of blanket irradiating the metal layer with Kght to diffuse metal into the runners to form an ahoy region therein. Through two-step irradiatiott, high-quaKty siKcides earrbeproducetronthe gate, source, drain and runner regions despite the typicaUy large differences in laser fluence required to form siKcide over the gate, source and drain relative to the runner(s). In general, siKcidation proceeds more rapidly in the gate region as compared to the source and drain regions because the gate region is more thermaKy insulated as compared to the source and drain regions which are integral with the substrate that acts as a heat sink. Witk the invented method, however, the fluence required for siKcidation in the gate is raised if the gate region extends beyond, and/or is coupled to a runner situated outside of, the selectively irradiated area. The portion of the gate region and/or coupled runner that is not irradiated is relatively cool and thus acts as a heat sink to draw heat away from the gateregrøn. Accordingly, the fluence required for siKcidation of the gate can be raised to more closely correspond to the fluence required for siKcidation in the source and drain. By forcing the respective fluenees for siKcidation required in the gate, source and drain closer to one another in the invented method, relatively high-quaKty siKcides can be formed together in the gate, source, and drain of the integrated device. Preferably, the Kght fluence used in the selective radiation step is determined so that sufficient energy is absorbed by the metal layer to melt the amorphous regions of the source/drain and part of the gate region until the metal layer overlying the gate region is consumed, at whichpoint theincreased reflectivity of the gate ahoy (especiahy in its Kquid state) is sufficient to prevent further melting of the gate ahoy region. By preventing further significant melting beyond the alloy region, the siKeide in the gate region is_ relatively stoichiometric and has a low sheet resistance. Also, if desired, the selective irradiation step can be continued to aKow further growth of the siKcide regions in the source and drain without adversely impacting the gate region due to its increased reflectivity upon expβsureof the alloy region resulting from consumption of the overlying metal. Similarly, the blanket irradiatiott step can be performed at least until the metal layer overlying the runner is consumed. The fluence of the blanket irradiation step is preferably selected so that, upon consumption of the metal layer overlying the runner, the exposed siKcide aUoy region, especiaKy in its Kquid state, reflects sufficiently more Kght as compared to themetal layer tσ prevent further melting of the runner region. Because the runner is generally located on a field isolation layer that has relatively poor thermal conductivity, the silicide growth rate in the runner region is relatively rapid as compared to those of the gate, source and drain regions. Therefore, the fluence of the light used to perform blanket irradiation is determined to be sufficiently low to prevent any significant adverse impact to the gate, source or drain regions. On the other hand, the fluence of the Kght used to perform blanket irradiatiott is also sufficiently high to form a high-quality siKcide region on the runner. The step of producing the amorphous region in the siKcon body is preferably performed through ion implantation. The depth to which the amorphous region is formed in the siKcon body is determined and controlled with high accuracy by selection of the atomic weight of the ion species used for implantation, the implantation energy, and the dosage of ions implanted in the siKcon body. Knock-on of metal is not an issue because the amorphization implant is performed prior to metal deposition. The step of forming or positioning the metal layer on the amorphous region is preferably performed by sputtering, evaporating or depositing the metal onto the siKcon body. The metal can be one of a large variety of metals, including titanium, cobalt and nickel. The step of irradiating the metal layer is preferably accomplished with pulsed laser light with a power sufficient to render part of the gate and the amorphous region in the source/drain molten while the metal layer, the siKcon substrate and other components of the integrated device and its runner(s)remaitt in their soKd states. Metal diffuses into the molten regions so that such regions become afloy regions with siKcide composition. To melt part of the gate and the amorphous source draitt regions while not melting the metal layer, the siKcon. substrate, or other integrated device components, the fluence of the laser light used to irradiate the metal layer is preferably in a range from 0.1 to 1.0 Joules per square centimeter. The invented method can also include a step of treating the aUoy region to convert it into a siKcide region with a lower resistivity structure. Preferably, the treating step is performed by rapid thermal annealing. The invented method provides several advantages over conventional siKcidation techniques. The siKcide depth in the invented method can be precisely controlled in the source and drain region by controKing the depth of the amorphous region. Thickness of the siKcide on the gate and the runners can be independently controlled by the thickness of the deposited metal layer, fit the invented method, metal is always the diffusing species which prevents the formation ofleakage paths and avoids other problems that would adversely impact the electronic characteristics of the integrated device. Localized surface heating helps to reduce the thermal budget and its resulting impact on the integrated device. Upon consumption of the metal layer overlying the gate or runner regions in a preferred embodiment of the invented method, the reflectivity of the gate or runner region (especially in the molten state) increases and thus reduces thermal loading of such regions. Irradiation of the metal layer overlying the source and drain regions can thus continue without adversely impacting the gate regions so that relatively low- resistance siKcides can be formed in the source and drain regions as weK as in the gate regions. With the reduced gate, source, dram and runner siKcide resistivities made possible with the invented method, the resulting transistor device is capable of relatively high-speed operation. Another advantage of the invented method is that it provides independent control of siKcide thickness over the source and drain, and gate and runner regions. Hence, lower resistance is possible over the gate and runners for a given siKcide thickness over the source and drain, a feature made possible because the method allows for the formation of thicker siKcides over the gate and runner as compared to the source and drain. These together with other features and advantages, which wiU become subsequently apparent, reside in the details of construction and operation of the invention as more fuHy hereinafter described and claimed, reference being made to the accompanying drawings, forming a part hereof wherein like numerals refer to Kke parts 5 throughout the several views. _ Brief Description of the Drawings Figs. 1A through IL are cross-sectional diagrams of a siKcon substrate showing steps of the invented method as applied to self-aKgned siKcidation of the contacts for the gate, drain and source of an integrated MISFET device; lfr Fig. 2 is a top plan view of the MISFET device; and Fig. 3 is a graph of gate siKcide resistivity versus line width for selected energy faiences. Descriptioπr of the Preferred Embodiments Figs. 1A through IL are cross-sectional diagrams of the invented method as 15 appKed to self-aKgned siKcidation of the contact regions for the gate, source, drain, and connection runners of an integrated MISFET device formed on a siKcon substrate 1. Although the siKcon substratedisclosed herein is a siKcon wafer, the invented method can be readily appKed to other types of substrates such as a siKcon-on-insulator (SOI) substrate, a siKcon epitaxial layer, or a layer of c- siKcon or polysiKcon. In Fig. LA, using 20 techniques and materials that are weU-known, field insulator layers 20 (preferably composed of siKeon-oxide, for example) are formed to electrically isolate an area of the siKcon body in which the MISFET device is to be formed. A gate insulator layer 21 is formed on the surfaee of the siKcon substrate 1. The gate msulator layer 21 can be a siKcon oxide layer, for example, in which case the resulting device is a MOSFET. Pory- 25 siKcon or amorphous siKcon layers 22, 23 are then deposited by low pressure chemical vapor deposition, for example, on the gate insulator layer 21 and the field msulator layers 20, respectively. The silicon layer and gate msulator layer are patterned using at least one resist layer, to selectively form or etch the siKcon layer and the gate insulator layer to form the siKcon gate region 22, the runners 23, and the gate insulator layer 21 , as shown in Fig. 30 1A. Suitable resists and etching techniques are weU-known to persons of average skifl in this technology. Dram and source regions 24, 25 are then doped with appropriate n-type or p-type dopants. If the siKcon body 1 is n-type, the drain and source regions are doped with p-type dopants. On the other hand, if the siKcon body 1 is n-type, the drain and source regions are doped with p-type dopants. In Fig. IB, an insulator layer 26 is formed over the siKcon body 1 , the siKcon gate region 22 and the runners 23. The insulator layer can be composed of siKcon oxide, for example. The insulator layer 26 is then selectively etched to form insulator side waKs 27,_ 28 on the sides of the siKcon gate region 22 and the runners 23, respectively, as shown in Fig. lC. ThesidewaJls 27, 28 herpt aclrieveself-aKgnment ofthe position of the siKcide regions yet to be formed. In Fig. ID, ions 29 are implanted to form the amorphous regions 30, 31, 32, 33 overthe source, drain, gate and runner regions, respectively. The implanted ions destroy the chemical bonds between siKcon atoms in localized areas of the source and drain portions ofthe substrate, and the gate and runners so that the atomic structure is made relatively disordered and random compared with the portions ofthe silicon substrate that are not affected by ion bombardment. The melting temperature ofthe amorphous regions is considerably lower than mat for crystaHme siKcon, a featurewhich is used to advantage in the invented method. Preferably, the ion species, the implantation energy and the siKcidation is desired in the source/drain regions. In general, selecting an ion species with a relatively Kght atormc weight, increasing therøn implantation energy, or increasing the ion dosage, wiU each have the effect of increasing the depth to which the amorphous regions extend. Conversely, selecting anion species with relatively heavy atomic weight, decreasing the ion implantation energy, or decreasing the ion dosage, wiK each have the effect of decreasing the depth to which the amorphous regions extend. A number of ion species can be used to produce the amorphous regions. For example, the ion species can include siKcon, argon, arsenic, or germanium. The ion implantation energy can be in a range from 2 to 100 kilo-electronVolts (keV) at a dosage in a range from 10 13 to 10 15 ions per square centimeter. In thepreferred embodiment, the depth to which the amorphized regions extend into the source and drain regions ofthe siKcon substrate, and the gate region and runners, is predetermined to be about 400 A. To produce the amorphized region to a depth of 400 A, the inventors have determined that arsenic ions implanted at an energy of about 30 keV with a dosage of about 3 X 10 14 atoms per square centimeter wiK achieve amorphization ofthe sihcon body to this depth. The ion implantation can be performed with a device such as the 9500 XR Ion Implanter commerciahy available from AppKed Materials, Inc. of San Jose, California. If the siKcon substrate is removed from the vacuum chamber in which ion implantation is performed, the substrate may be exposed to the atmosphere and thus to a degree of oxidation due to the atmosphere's oxygen content. The oxidation forms a so-^ caKed 'native' oxide layer over the surface ofthe siKcon substrate. So that such native oxide layer wiH not adversely affect subsequent processing in accordance with the methods of this invention, the native oxide layer can be stripped with an acidic solution. For example, a solution of 1:100 ratio of HF to H 2 O strips oxide at a rate of 20 A per minute. A sixty second treatment of the substrate with the acidic solution is sufficient to remove the native oxide layer. In the alternative, the invented method can be practiced in an air-tight chamber so mat the amorphous region is not exposed to an oxidizing environment before the formation ofthe metal layer thereon, thus altogether avoiding the formation of an oxide layer that would require removal. In Fig. IE, a metal layer 34 is formed over the surface ofthe amorphous regions 30, 31, 32, 33. The metal layer supp es the metal atoms needed to form the desired siKcide compound for electrical contact with the integrated device and its connection runners. With the invented method, a number of metal speeies can be used to form the siKcide compound. For example, the metal layer can include titanium, cobalt or nickel used to formthe siKcides TiSi 2 , CoSi 2 , or NiSi with resistivities of 15-20 μΩ-cm, 17-20 μΩ-cm, and 12-15 μΩ-cm, respectively. The metal layer is formed preferably by sputtering, but evaporation or chemieal vapor deposition can also be used. For example, to form the metal layer, a suitable sputtering chamber is the Endura VHPPVD commercial available from AppKed Materials, Inc. of San Jose, California. Preferably, the metal layer is formed in a thickness that is determined based upon the desired siKcide tmekness or depth and the stoichiometric proportion of siKcon and metal consumed to form the siKcide. More specifically, the metal layer's thickness should be at least the amorphized siKcon depth divided by the ratio of siKcon to metal consumed to form stoichiometric siKcide. Thus, to reacttitarrium with 400 A of amorphous siKcon to form approximately 440 A of silicide, due to the atomic structure of this siKcide, 2.27 A thickness of siKcon is consumed per 1 A of titanium (Le., a consumption ratio of 2.27), the thickness ofthe metal layer should be about 400 A /2.27 * 175 A to ensure that a stoichiometric siKcide of desired depth can be formed. In Fig. IF, a mask 35 is positioned over the substrate. The mask 35 is patterned so that it has regions that are substantially Kght-transmissive overlying the active area of the substrate winch includes the gate, drain and source, but that has substantiaKy non- transmissive regions overlying the isolation layers 20. The mask 35 can be patterned by. selectively etehing a dieleetrie-staek-ott-glass blank as is weU-known in this technology. The blank is etched to remove the dielectric stack from hght-transmissive regions that are to be positioned over the active areas ofthe substrate. The mask 35 can be positioned over the active region of the substrate using conventional Kthography ahgnment equipment and teelmiqttes. Themetal layer is irradiated with Kght designated numera 36' to diffuse metal from the layer 34 into regions 30, 31, 32, 33. Preferably, the Kght is generated by a htserwith a fluence sufficient to render the amorphous regions and part of the gate regions molten, and yet with insufficient power to melt the silicon substrate 1 , the gate insulator layer 21, the side waHs 27, 28, the field msulator regions 20 or the metal layer 34. It has been determined that α-sihcon melts at 200 - 600° C lower than crystalline siKcott, so that the temperature window for selective melting ofthe amorphous regions is relatively large. Due to the relatively high diffusivity ofthe metal in Kquid siKcon, the molten amorphous regions become respective aHoy regions of siKcide composition. In general, it has been determined that the laser Kght must be appKed over several pulses to ensure complete mixing of the metal in the siKcon. Between laser pulses, the substrate is aKowed to cool to room temperature. To ensure that the irradiation step is performed within the process margm ofthe invented method in which the amorphous regions and part ofthe gate regions are rendered molten and the siKcon substrate 1, the gate insulator layer 21, the sidewalk 27, 28, the field insuhrtorregions 20 and the metal layer 34 remain in their soKd phases, the laser Kght should have a fluence in a range from 0.1 to 1.0 Joules per square eentimeter delivered in a series of 3 to 10 shots of 10 to 100 nanoseconds in pulsewidth at a repetition rate of from 1 to 1000 Hertz to form siKcide to a depth of about 1000 A in the gate regions and 400 Ainthe source/drain regions. The exact laser fluence, number of shots, shot duration and repetition rate that wiU be needed to operate within the process margin for the invented method wiU vary between different kinds of laser deviees and the desired siKcide thickness. For the Model No. 4308 laser commerciaKy available from Lambda Physik, Inc. of Fort Lauderdale, Florida, the preferred fluence is 0.3 - 0.5 Joules per square centimeter, deKvered in 1 shots of 20 nanosecond pulsewidth at a repetition rate of 300 Hertz. The irradiation of the metal layer 34 is preferably performed in a chamber with an inert atmosphereof nitrogen, argon or heKum. A suitable chamber is the P-GILA machine commercially available from Ultratech Stepper, Inc. The inventors have determined that, with proper deKvery ofthe laser Kght in accordance with, the above-described guidelines and principles, the temperature window over which the amorphous regions and part of the gate regions are molten while the other regions of the structure shown in Fig. IF remain in their soKd phases, occurs over a relatively large rangefrom ll5ø°to 1410° Celsius, andthus over a range of about 260° Celsius. Thus, the invented methods greatly enhance the process margin available for successfulperformance of he invented method relative to conventional siKcidation techniques. Importantly, the process margin is further enhanced by an additional feature ofthe invented method. In general, siKcide in the gate region tends to form at lower fluences compared to the siKcides in the source and drain. This phenomenon occurs because the gate region is thennaKymsulated by the insulator layer 21 and the side walls 27 whereas the source and drain regions 30, 31 are integral with the substrate which acts as a heat sink for thermal energy generated by irradiatiott with the Kght 36. In the invented method, by selectively irradiating only the active gate, source and drain areas, the gate region 22 extending outside ofthe active area onto the field isolation layers 20 is not subjected to significant heating. The relatively cool portions ofthe gate region 22 sink heat away from the irradiated portion of the gate region, and thus lower its silicide growth rate to more closely correspond to the siKcide grow rates ofthe source and drain. Thus, because the gate, souree and dram siKcide growth rates are closer together, due to the selective irradiation ofthe active area ofthe substrate, relatively stoichiometric siKcides can be grown together on the gate, sourceand dram of theitttegrated MISFET device. As metal diffuses into the regions 30, 31, 32 due to the heating action induced by the Kght 36, the regions 30, 31, 32 become respective aKoy regions 37, 39, 40, as shown in Fig. 1G. In Fig. 1G, irradiation ofthe Kght 36 onto the amorphous regions 30, 31, 32 preferably continues until the metal layer overlying the gate si con body 22 is completely consumed and the resulting gate aKoy region 37 is exposed. At this point, the gate ahoy region 37, especially any molten portion thereof, is more reflective than the metal layer 34, and so reflects an increased amount of Kght denoted as '38' in Fig. 1G. With proper selection of the fluence of the Kght 36, the increased reflection ofthe Kght 38 from the exposed gate aKoy region 37 can be such that it prevents absorption of enough Kght energy to arrest or at least significantly inhibit further migration ofthe metal atoms in the gate region beyond the aKoy region existing upon complete consumption ofthe overlying metal. Further irradiatiott of the aetive area of the substrate in Fig. 1 G will thus allow. siKcide growth to continue in the typically slow-growth source and drain regions 24, 25 without causing further migration of metat atoms through melting in the gate region 22. This feature aKows for relatively stoichiometric (and thus low-resistivity), ghfy-defined siKάdestobegrowttβttthegate source and dram of theMISFET device. The operational speed attainable with the low-resistivity contacts ofthe MISFET device is thus relatively high. After irradiatiβn with the Kght 36, the aKoy regions cool to a chemical form that is at least partially crystalline. IttFig. 1H, themask 35 is removed from its posrtion overlying the substrate 1, and the metal layer is blanket irradiated with Kght 41. The Kght 41 preferably has a lower fluence than that of the Kght 36 used m theirradiation steps of Figs. IF and 1G. Due to the positioning ofthe runners 23 on the isolation layers 20 which are relatively poor thermal conductors, the siKcide growth ratemthealloy regions 42 is significantly higher than for the active aKoy regions 39, 40. The fluence ofthe Kght 41 is preferably selected so that it has no significant impact on the siKeide afiβy regions 37, and yet is sufficient to cause metal atoms to diffuse from the layer 34 into the aKoy regions 39, 40, 42 and portions of the gate region 32 positioned ott the field isolation layers 20 (not shown in Figs. 1A - IL, but shown in Fig. 2). Thus, the Kght 41 promotes siKcide growth in the alloy regions 39, 40, 42, while the reflectivity of the aKoy region 37 is sufficiently high (especially in its molten state) to reflect enough Kght 43 to prevent any further melting of mesiKeottregiott22 uttderlymgthealloyregiott37. In general, the desired Kght fluence is in a range from 0.1 to 1.0 Joules per square centimeter delivered in a series of 3 to 10 shots of 10 to 100 nanoseconds in pulsewidthr at a repetition rate of from 1 to 1000 Hertz to produce siKcide to a depth of about 1000 Ainthe regions 42. The exact laser fluence, number of shots, shot duration and repetition rate that wfll be needed to operate within the process margin for the invented method wiK vary between different kinds of laser devices and the desired silicide thickness. For the Model No. 4308 laser commerciaKy available from Lambda Physik, Inc. of Fort Lauderdale, Florida, the preferred fluence for blanket irradiatiott is in a range from 0.1 to 0.35 Joules per square centimeter, delivered in 10 shots of 30 nanosecond pulsewidth at a repetition rate of 300 Hertz. As metal atoms diffuse into the regions 33 due to heating produced by blanket irradiation, the regions 33 become aKoy regions 42. Irr Fig. II, irradiation ofthe regions 23 on the isolation layers 20 continues until_ the overlying metal layer 34 is completely consumed to expose the aKoy regions. The fluence ofthe Kght 41 is such that it has enough energy to melt the regions 42 situated on the isolation layers 20 if the metal layer 34 is unconsumed over these regions, but has an insufficient amount of energy to melt the regions 23 if the overlying metal layer is consumed due to the higher reflectivity ofthe a oy regions relative to the metal layer 34. Themcreased reflectivity upon cottsumptiott of theoveriymg metal layer and exposure of the regions 42 prevents further melting ofthe regions 23, thus arresting further significant migration of the metal atoms through merting beyond the desired contours ofthe sihcide regions. Upon cooling after Kght irradiation, regions 42 become aKoy regions with a partia -crystallized state in winch theatoms of thesiKcide are relatively ordered, yet not entirely so. After performance of the irradiatiott stepmFig. II, the unconsumed portion ofthe metal layer 34 is stripped from the siKcon substrate. The stripping ofthe metal layer can beperformed with tc 4: 1 solution of suHuric acid (H 2 SO 4 ) and hydrogen peroxide (H 2 0 2 ) heated to 180° Celsius. TypicaKy, immersion ofthe siKcon body for about ten minutes is sufficient t removethe metal layer, although the time and chemical substance necessary to strip the metal layer can vary to a degree depending upon the type of metal and its thickness. Immersion can beperformed in spray etch tool Kke the Equinox™ made by SEMTTOOL™ of Kalispell, Montana. Fig. 1 J shows the substrate after stripping ofthe uttcottsumed portion ofthe metal layer 34. In Fig. IK, the aKoy regions 37, 39, 40, 42 can be subjected to treatment to change the crystal structure of the aKoy regions into form which have desired low- resistivity characteristics. The siKcide regions 37, 39, 40, 42 are indicated by 'x' hatching hrFig. IK PreferaWy,tlιetreatmerf ofthealloyregionstoformrespectjVe low-resistance siKcide regions is performed with rapid thermal anneahng. The rapid thermal anneahng can be performed by subjecting the siKcon body to a temperature of 500° - 900° Celsius for a time duration ranging from 1 hour down to 10 seconds. Preferably, for TiSi 2 siKcide, the siKcon body is subjected to rapid thermal annealing at a temperature of 850° Celsius for 20 seconds to convert the aKoy region into the desired siKcide. The atmosphere in which the siKcon body is placed during rapid thermal annealing should be inert. Accordingly, for example, the rapid thermal annealing should be performed in a chamber cotttaittittg a nitrogett atmosphere. The rapid thermal annealing can be performed in a_ Rapid Thermal Processing tool designated Centura that is commerciaKy available from AppKed Materials, Inc. of San Jose, California. Fig. IL is an exemplary diagram illustrating how the terminals ofthe integrated device or runners might be connected to other components of an integrated circuit. Of course, persons of ordinary skiK in the art wiK readily understand that numerous variations other than theparticular configuration shown in Fig. IL arepossible, and that a particular integrated circuit implementation generally depends upon the specific circuit desired to be formed, fit Fig. IL, an msulator layer 44 composed of siKcon-oxide, for example, is formed on the field insulator regions 20, the siKcide regions 37, 39, 40, 42, and the side waKs 27, 28. The msulator layer 44 is selectively patterned to expose portions ofthe siKcide regions 37, 39, 40, 42 (the exposed portion ofthe region 32 is not shown in Fig. IL, but is shown in Fig. 2). Cottductiveleads or contacts 45, 46, 47, 48 (only lead 45 and contact 46 are shown in Fig. IL) composed of aluminum or other conductive metal, are formed and patterned so as to make electrical contact with the siKcide regions 37, 39, 40, 42 ofthe MISFET device. More specificaKy, the lead 45 electricaKy connects the runner siKcide 42 on the right-hand side of Fig. IL to the source siKcide 39. The contact 46 can be used to form an electrical connection to a lead situated on an insulator layer at a higher level ofthe structure (not shown). Theleads 45, 46, 7, 48 and runners can thus be used to transmit electric signals to and from the gate, source and drain terminals of the MISFET device. Air msulator layer 49 composed of sihcott oxide, for example, is formed over the conductive leads 45, 46, 47, 48 to electricaKy insulate and protect the conductive leads and contacts, and the MISFET device. At respective ends opposite those in contact with the siKcide regions 37, 38, 40, 42, the leads 45, 46, 47, 48 are generaUy coupled to other electronic components, and or power or signal sources. Fig. 2 is a top plan view ofthe MISFET device of Fig. IL with the insulator layer 49 removed for more clear iHustration ofthe MISFET device. The views of Figs. 1A - IL are taken along a cross-section denoted by the section lines 100 - 100' in Fig. 2. In Fig. 2, connections between the conductive lead or contacts 45, 46, 47, 48 and the siKcide regions 37, 39, 40, 42 are denoted by crossed squares at which the insulator layer 44 is selectively etched or formed to aKow electrical contact to be made to the siKcide regions. Also noteworthy in Fig. 2 is the extension ofthe gate region 22 and its siKcide layer 37 beyond the active region 50 that is selectively irradiated in Figs. IF and 1G. The_ extension ofthe ends ofthe gate region 22 and its overlying siKcide layer 37 onto the field isolation layer 20 that is outside ofthe area selectively irradiated aKows these relatively cool portions ofthe gate region to dissipate heat away from the gate region so that the fluence required to form silicide in the gate region corresponds more closely to that necessary to form suicides in the source and drain regions. As is weK-known in this technology, the relatively large squarepad at theends ofthe gate region 32 and the right- side runner region 33 faciKtate proper connection to the overlying contacts 47, 48. The left- side runner 33 is used to form a connection between an integrated device(s), and signal or power sources other than the integrated transistor of Fig. 2. Fig. 3 is a graph of gate lesistivity versus Kne width for a titanium siKcide gate region of an integrated MISFET device made using the invented method. As can be seen in Fig. 3, the value of the resistivity of thesiKcide gate region formed with a fluence of 0.35 J/cm 2 depends to a degree upon the lateral width ofthe gate. In contrast, at energy fluences of ø.40 and 0.45 J/cm 2 ; the resulting gate siKcide resistivities are relatively constant and low, about 1 ohm per square centimeter, over a broad range of gate widths. Thus, in applications in which it is desired to produce titanium siKcide with a relatively low and substantiaKy gate- width-independent resistivity, the fluence for siKcide formation should be maintained in r range from 0.3 to 0.5 J/cm 2 . The many features and advantages ofthe present invention are apparent from the detailed specification and thus, it is intended by the appended claims to cover aK such features and advantages ofthe described method which foKow in the true spirit and scope of the invention. Further, since numerous nrodificatiotts and changes wiK readKy occur to those of ordinary skiU in the art, it is not desired to limit the invention to the exact construction and operation iHustrated and described. Accordingly, aK suitable modifications and equivalents may be resorted to as falling within the spirit and scope of the claimed mvention.

Claims: Oaims 1. A method comprising the steps of: a) producing amorphous regions on a gate, source, drain and connection 5 runner for an integrated device formed on a siKcon substrate; _ b) forming a metal layer in contact with the amorphous regions; c) selectively irradiating the metal layer with Kght to diffuse metal into at least the amorphous gate, source and drain regions to form respective aKoy regions of siKcide composition; and lø d)blanket irradiating themetal layer with light to diffuse metal into at least the connection runner to form an aKoy region with a siKcide composition. 2. A method as claimed m claim 1, further comprising the step of: e) treating the aKoy regions to convert the aKoy regions into low-resistivity 15 siKcide regions. 3. A method as claimed in claim 2, wherein said step (e) is performed by rapid thermal annealing. 20 4. A method as elaimed in claim 2, further comprising the step of: f) patterning an insulator layer and a conductive layer to form a conductive path that contacts at least one siKcide region. 5. A method as claimed in claim 1, wherem said step (a) includes a substep of 25 implanting ions into the source and dram regions o the siKcon substrate and the gate and runner regions to form respective amorphous regions. 6. A method as claimed in claim 5, wherein theioπsinchide at least one of siKcon, argon, arsenic and germanium. 30 7. A method as claimed in claim 5, wherem the ions are implanted with an energy in a range from 2 to 100 kflo-electrottVolts (keV). 8. A method as claimed in claim 5, wherem the substep of implanting is performed with a dosage in a range from 10 13 to 10" atoms per square centimeter. 9. A method as claimed in claim 5, further comprising the step of: e) selecting at least one of ion species, ion energy and ion dosage to form_ theamoipliousregionstoapredeterrmhed depth, said irrj hmting substep performed based on said step (e). 10. A method as elaimedin claim 1, further comprising the step of: e) stripping an oxide layer from the siKcon substrate after perfoπning said step (a) and before performing said step (b). 11. A method as claimed in claim 10, wherein said step (e) includes a substep of immersing the siKcon substrate in an acidic bath. 12. A method as elaimedin claim 1, wherein said step (b) includes a substep of sputtering metal onto the amorphous region to form the metal layer. 13. A method as claimed in claim 12, wherem the metal includes at least one of titanium, cobalt, and nickel. 14. A method as claimed in elaim 1, wherein said step (b) includes a substep of evaporating metal onto the amorphous regions to form the metal layer. 15. A method as elaimed itt claim 1, wherein said step (b) includes a substep of forming the metal layer on the amorphous regions by chemical vapor deposition. 16. A method as claimed in claim 1, wherem the metal layer is formed with a thickness at least equal to the predeteπnined depth to which the amorphous regions are formed in the siKcon substrate, divided by a consumption ratio of sihcon to metal. 17. A method as claimed in claim 1, wherem the Kght fluence used in said step (c) is greater than the light fluence used in said step (d). 18. A method as claimed in elaim 1 , wherem the Kght fluence used in said step (c) is 0.1 to 0.5 Joules per square centimeter. 1 . A method as claimed in elaim 18, wherein the light fluence used in said step (d) is 0.1 to 0.35 Joules per square centimeter. 20. A method as claimed in claim 1, wherem the Kght fluence used in said step (d) is 0.1 to 0.35 Joules per square centimeter. 21. A method as claimed in claim 1, wherem the selective irradiation of said step (c) is performed with Kght of a fluence that is sufficiently large to render the source and drakr amorphous regions and part of thegate region molten, yet insufficient to melt the substrate and metal layer, so that metal atoms diffuse from the metal layer into the molten regions of he gate, source and drain. 22. A method as daimed in claim 1, wherein the Kght used in the performance of the selective radiation of said step (c) has a fluence that is sufficient to consume the metal layer overrying the gate regioir so that the gateregion is exposed, but that is sufficiently limited so that the increased reflectivity of the gate region relative to the metal layer reflects sufficient Kght energy upon exposure ofthe gate region to prevent substantial melting ofthe gate region beyond the siKcide boundaries existing upon consumption of the overlying metal layer. 23. A method as ehtimed elaim 1, wherein a non-irradiated portion ofthe gate region extends outside ofthe substrate area selectively irradiated in said step (c) so that the nott-irradiated portion is relatively cool and draws heat away from the irradiated portion ofthe gate region. 24. A method as claimed in claim 1, wherein the selective irradiation of said step (d)is performed with Kght of a fluence that is sufficiently large to render part ofthe runner region molten, yet insufficient to melt the substrate and metal layer, so that metal atoms diffuse from the metal layer into the runner. 25. A method as claimed in elaήriT, wherem thelight used in the irradiation of said step (d) has a fluence that is sufficient to consume the metal layer overlying the runner_ regiott so that the runner region is exposed, but that is sufficiently Knήted so that the increased reflectivity ofthe runner aKoy region relative to the metal layer reflects sufficient Kght energy upon exposure of the runner aKoy region after consumption ofthe overlying metal layer, to prevent further melting ofthe runner region. 0 26. A method as claimed in claim 1, wherein the Kght irradiation of said steps (c) and (d) is performed with laser Kght. 27. A method as claimed in claim 1, wherein the fluence ofthe Kght irradiation in 5 each of said steps (c) and (d) is in a range from 0.1 to 1.0 Joules per square centimeter. 28. A method as aimed hr elaim 1, wherein the metal layer is irradiated by the Kght in a series of shots in said steps (c) and (d). ø 29. A method as claimed in claim 1, wherein the siKcon substrate is situated in an ambient medium including at least one of argon, helium and nitrogen during performance of said steps (c) and (d). 30. A method as eføime ifr elaim I, wherem the gate aKoy region is thicker than 5 the source and drain aKoy regions. 31. A method comprising the steps of: a) forming a field isolation layer on a siKcon substrate; b) forming a gate insulator layer on the siKcon substrate; c) forming at least one siKcon πmner regioir over the field isolation layer; 5 d) foπning a siKcon gate region over the gate insulator layer; _ e) doping at feast regions ofthe silicon substrate adjacent the gate region to form source and drain regions on the siKcon substrate; f) foπning a secondinsulator hryerover thegate region, the runner and the siKcon substrate; lø g) etching the seeond insulator layer to form side waKs in contact with respective sides ofthe gate region and the runner; h) producing amorphous regions in the gate, source, drain and runner regions; i) fbπning a metaHayer in contact with the amorphous regions; 15 j ) selectively irradiating the metal layer overlymg the gate, source and drain amorphous regions with Kght to convert the gate, source and drain amorphous regions into respective aKoy regions of siKcide composition; k) blanket irradiating the metal layer with Kght to convert part of the runner regions into respective siKcide aKoy regions; 20 1) removing an unconsumed portion ofthe metal layer; and m) treating the aKoy regions to form siKcide regions. 32. A method as claimed in cteim31, further comprising the steps of: n) foπning a third msulator layer over the siKcon substrate; 25 o)patteπιmgthetlnrdittsutetor layer to setectively expose the gate, source, drain and runner regions; and p) forming conductive leads oir the third insulator layer that contact the gate, source, drain and runner regions. 30 33. A method as etehned in claim 31 , wherein said step (h) includes a substep of implanting ions to form the amorphous regions. 34. A method as claimed in claim 31, wherein said step (i) includes a step of sputtering the metal layer onto the amorphous regions. 35. A method as claimed in claim 31, wherein the metal layer is formed in said step (i) with a thickness that is approximately sufficient to produce a stoichiometric aKoy_ region in at least the amorphized regions o the gate, source and drain. 36. A method as claimed in claim 31, wherem the Kght used to irradiate the substrate in said steps (j) and (k) is laser Kght. 37. A method as claimed in claim 31, wherem a portion ofthe runner coupled to the gate is not irradiated with Kght in the performance of said step (j) so that the runner draws heat generated by Kght absorption away from the gate region. 38. A method as claimed in claim 31, wherem the fluence ofthe Kght used to irradiate the substrate in said step (j is sufficient to render part ofthe gate, source and drain amorphous regions molten, yet insufficient to melt the substrate and metal layer so that metal atoms from the metal layer diffuse into the gate, source and drain amorphous regions to form respective aKoy regions of siKcide composition, said step (j) continuing atleastuntKώemetalkyeroverlymgthegateaHoyregiottiseonsumedto exposethegate aKoy region, the Kght fluence used in said step (j) being insufficient to melt the aKoy regiott upon exposure of the gate aKoy regkm due to the increased reflectivity ofthe gate aKoy region relative to the metal layer. 39. A method as claimed in elaim 31, wherein the fluence of the Kght used to irradiate the substrate in said step (k) is sufficient to render the runner regions molten, yet insufficient to melt the substrate and metal layer so that metal atoms from the metal layer diffuse into the runner region to form a respective aKoy region of siKcide composition, the Kght fluence used in said step (k) insufficient to melt the runner aKoy region upon consumption ofthe overlying metal layer and exposure ofthe runner aKoy region due to the increased reflectivity ofthe πmner aKoy region compared to the metal layer. 40. A method comprising the steps of: a) foπrήng a gate, source and drain of an integrated device and at least one runner coupled to the integrated device, on a siKcon substrate; b) amorphizittg regions of the gate, source, drain and runner; c) forming a metal layer in contact with the amorphized regions; _ d) selectively irradiating the gate, source and drain regions with Kght of an energy fluence sufficient to melt part ofthe gate, and the amorphized source and drain regions, yet msufficient to melt the metal layer, sineon substrate and non- amorphized portions of the source and drain regions, so that metal diffuses into the gate, and amorphized source and drain regions to form respective aKoy regions of siKcide composition; and e) blanket irradiating the runner regiott with Kght of an energy fluence sufficient to melt part ofthe runner region, yet insufficient to melt the gate, source, and drain regions, the metal layer, and the siKcon substrate. 41. A method as claimed m claim 40, wherem the irradiation of said step (d) is performed until the metal layer overlying the gate region is consumed so that the increased reflectivity ofthe gate aKoy region relative to the metal layer prevents the gate region from further meltmg. 42. A method as claimed in elaim41, wherein the selective irradiation of said step (d) is continued after the consumption ofthe metal layer overlying the gate region to cause additional diffusion of metal from the metal layer into the source and drain regions. 43. A method as claimed in claim 40, wherein the gate region extends beyond the area selectively irradiated in said step (d)so that there tively cool, non-irradiated portion ofthe gate region draws heat away from the irradiated portion ofthe gate region during the performance of said step (d). 44. A method as claimed in claim 40, further comprising the steps of: f) siKcon substrate; and g) treating the aKoy regions to convert the aKoy regions into low-resistivity siKcide regions. 45. A method as claimed in claim 44, wherein said step (g) includes a substep of rapid thermal annealing ofthe aKoy regions to produce the low-resistivity siKcide regions. 46. A method as claimed in claim 40, wherein said step (b) includes a substep of implanting ions into the siKcon substrate to produce the amorphized regions. 47. A method as claimed in claim 40, wherem said step (c) includes a substep of sputtering the metal layer onto the amorphized regions. 48. A method as claimed in claim 40, wherem said step (c) includes a substep of evaporating the metal layer onto the amorphized regions. 49. A method as claimed in claim 40, wherein said step (c) includes a substep of forming the metal layer in contact with the amorphized regions using chemical vapor deposition. 5ø. A method as claimed in claim 40, wherein said step (d) includes a substep of irradiating the metal layer with laser Kght having a fluence in a range from 0.1 to 1.0 Joules per square centimeter. 51. A method as daimed in claim 40, wherein the irradiation is performed in said step (d) in a series of shots. 52. A method as daimed in churn 40, wherein the irradiation of said step (d) is performed with 3 to 10 shots of 10 to 100 nanoseconds in duration. 53. A method as daimed in churn 40, wherein said step (e) includes a substep of irradiating the metal layer with laser Kght having a fluence in a range from 0.1 to 1.0 Joules per square centimeter. 54. A method as claimed in claim 40, wherem the irradiation in said step (e) is performed in a series of shots. 55. A method as claimed in claim 40, wherein the irradiation in said step (e) is performed with 3 to 10 shots of 10 to 100 nanoseconds in duration. _ 56. A method as claimed in claim 40, wherem the fluence ofthe Kght used in the performance of said step (d) is greater than the fluence ofthe Kght used in the performance of said step (e). 57. A method as claimed in claim 56, wherein the fluence ofthe light used in the performance of said step (d) is in a range from 0.1 to 0.5 Joules per square centimeter, and wherem the fluenceof Kght used in the performance of said step (e) is in a range from 0.1 to 0.35 Joules per square centimeter. 58. A method as claimed in dai 40, further comprising the step of: f) aKgning a mask for use in the selective irradiation ofthe gate, source and drain amorphous regions in said step (d). 59. A method as claimed in claim 40, wherem the gate and runner aKoy regions are thicker than the source and dram aKoy regions.

Inventors: KRAMER KARL-JOSEPH, TALWAR SOMIT, VERMA GAURAV, WEINER KURT, KRAMER, KARL-JOSEPH, TALWAR, SOMIT, VERMA, GAURAV, WEINER, KURT
Applicants: ULTRATECH STEPPER INC, ULTRATECH STEPPER, INC.
Application year: 1999
Main classification: H01L
IPC codes: H01L21, H01L23, H01L29