Delta-sigma modulator with improved full-scale accuracy

Abstract: The invention provides methods and apparatus for improving the full-scale accuracy of an oversampling analog-to-digital converter. In particular, an improved switched-capacitor subtractor/integrator circuit is described that effectively provides a desired capacitor ratio by using N + M distinct unit capacitors that each sample an input signal a first predetermined number of times and sample one or more reference signals a second predetermined number of times, where the ratio of the first predetermined number to the second predetermined number is the desired capacitor ratio N / M .

Description: present invention relates to oversampling analog-to-digital converters. More particularly, the present invention relates to methods and apparatus for improving the full-scale accuracy of a delta-sigma modulator in an oversampling analog-to-digital converter. Converting a continuous-time analog signal to a discrete-time digital representation typically requires anti-alias filtering, sampling and quantization. An anti-aliasing filter ensures that analog input signal is properly band-limited prior to sampling. A sampler captures samples of the filtered input signal at discrete time intervals, typically T = 1/ F s , where F s is the sampling frequency. The sampling frequency F s typically is selected as twice the bandwidth of the filtered analog input signal. Finally, a quantizer converts the samples to a discrete set of values. Conventional analog-to-digital (A/D) converters typically perform sampling and quantization, whereas separate discrete components or integrated circuits perform anti-aliasing. Oversampling A/D converters, in contrast, sample an analog input signal at a rate DF s that exceeds twice the bandwidth of the analog input signal. An oversampling converter typically includes an anti-alias filter, a sampler and modulator (quantizer) that operate at the elevated rate DF s , and a digital filter. The digital filter, typically called a decimator, provides low-pass filtering to suppress signals above F s /2, and sample-rate reduction to lower the sample rate to the desired rate F s . As a result of the higher input sampling rate, over-sampling converters have less stringent anti-alias filter requirements than traditional converters. In addition, oversampling converters permit lower quantization noise power, and hence improved signal-to-noise ratio compared to traditional converters. A/D converters typically operate over a specified maximum and minimum input signal range. The maximum input signal typically is referred to as the converter's full-scale input value. Under ideal conditions, if a full-scale input is applied to the converter, the converter provides a full-scale output. In reality, however, the converter's actual output differs from the ideal result, and the difference between the actual output and the ideal output is the full-scale error. A full-scale accurate converter has zero full-scale error. A full-scale accurate oversampling converter has significant practical importance in such fields as data acquisition, test and measurement instrumentation, industrial control, etc., because the converter provides a DC-accurate conversion result, exceptional unwanted signal rejection capabilities and simple anti-alias requirements. Referring to FIG. 1, a common implementation of a delta-sigma oversampling converter is described. Converter 10 includes subtractor circuit 12, integrators 14, 16 and 18, output adder 20, comparator 22, clock generator 24 and digital filter 26. Based on the state of clock signal CLKA and digital signal Y, subtractor circuit 12 subtracts analog reference signal V REF from analog input signal V INPUT . Integrator 14 integrates the resultant error signal E during each cycle of clock signal CLKB and generates output signal IE1. Integrator 16 integrates IE1 during each cycle of clock signal CLKC and generates output signal IE2. Integrator 18 integrates IE2 during each cycle of clock signal CLKD and generates output signal IE3. Output adder 20 produces the algebraic sum of output signals IE1, IE2 and IE3 to create the third-order integrated and feed-forward compensated error signal IE. Comparator 22 compares error signal IE with an internal reference (not shown) and generates digital output signal Y for every cycle of clock signal CLKE. Digital output Y only has two possible states, and thus can be represented in binary form by a single bit. Clock generator 24 generates clock signals CLKA, CLKB, CLKC, CLKD and CLKE from external control signal CLK, with appropriate relative phase relations for specific implementations of the modulator blocks. Digital stream Y contains a digital representation of the ratio R between input signal V INPUT and reference signal V REF . Output Y may be extracted and further transformed through digital processing in decimation filter 26. Output D of digital filter 26 is the conversion result. The full scale output of converter 10 equals the converter's output D FSI when full-scale signal V FSI is applied at the converter's input V INPUT . Under ideal conditions, the ratio of the full-scale input signal V FSI to V REF is defined as: k = V FSI V REF Generally, k is a non-zero proportionality constant, whose value depends upon the convertor's operating range. As a result of component tolerances and operating condition variations, however, the converter's actual output does not equal D FSI when V FSI is applied to the converter's input. Instead, the actual output of the converter equals D FSI when input signal V FSA is applied to the converter's input. The ratio between V FSA and reference signal V REF . is given by: R FS = V FSA V REF The relative full-scale error is defined as: E FS = 1 - R FS K Under ideal conditions, R FS = k , and E FS = 0 . Prior art oversampling A/D converters have used digital calibration to compensate for full-scale error. The AD7714 oversampling A/D converter, for example, manufactured by Analog Devices Inc., Norwood, Massachusetts, implements such an approach. In particular, the AD7714 performs a dedicated full-scale self-calibration conversion during which an internally-generated signal V FSI is applied to the converter input. Ideally, the converter output is D FSI . The actual output D FSA is compared to the desired output D FSI , and a digital computer determines the error E FS and an appropriate correction factor K c . Subsequently, the digital computer applies K c to all converter results D. The approach used in the AD7714 requires complex circuits that increase converter's size, power consumption and internally-generated noise. Further, a change in environmental conditions invalidates the previously calculated correction coefficient K c , and requires a new full-scale calibration cycle. Because digital calibration cycles decrease converter throughput, frequent digital calibration results in a reduced equivalent conversion rate. The full-scale accuracy of converter 10 primarily depends on the accuracy of input subtractor circuit 12. In typical circuit implementations, subtractor circuit 12 and integrator 14 are combined in a single switched-capacitor circuit, and the accuracy of the subtraction function depends on a ratio of two input sampling capacitors. Prior art circuits have attempted to control this critical ratio using well-known integrated circuit layout techniques. Although these layout techniques eliminate the disadvantages related to digital calibration, circuit layout approaches have not achieved the desired level of accuracy. US 5,134,401 shows a similar converter to that of AD 7714. It therefore would be desirable to provide a delta-sigma analog-to-digital converter that has reduced full-scale error without requiring digital calibration. It also would be desirable to provide a delta-sigma analog-to-digital converter that has reduced full-scale error without depending on critical capacitor ratios. US 5,729,232 discloses a combination shared capacitor integrator and digital-to analog converter circuit with data dependency cancellation, wherein a single shared capacitor configuration is used. Accordingly, it is an object of this invention to provide a delta-sigma analog-to-digital converter that has reduced full-scale error without requiring digital calibration. It also is an object of this invention to provide a delta-sigma analog-to-digital converter that has educed full-scale error without depending on critical capacitor ratios. In accordance with these and other objects of the present invention, a subtractor/integrator circuit is provided that effectively has input sampling capacitors C IN and C RE F having a ratio that may be expressed as a rational number N / M , where N and M are relative prime integers. The circuit provides this ratio using N+M distinct unit capacitors C U1 , C U2 , . . . C U(M+N) under the control of a state machine. The state machine causes each distinct unit capacitor C U1 , C U2 , . . . C U ( M+N ) to sample an input signal a first predetermined number of times to effectively construct an equivalent input capacitor C IN , and causes each distinct unit capacitor C U1 , C U2 , . . . C U(M+N) to sample one or more reference signals a second predetermined number of times to effectively construct an equivalent reference capacitor C REF . The ratio of the first predetermined number and the second predetermined number equals the desired ratio N / M. As a result, the ratio between the effective capacitances C IN and C REF . depends only on the state machine states, which can be controlled with practically unlimited accuracy. The above-mentioned objects and features of the present invention can be more clearly understood from the following detailed description considered in conjunction with the following drawings, in which the same reference numerals denote the same structural elements throughout, and in which: FIG 1 is a schematic block diagram of a previously known delta-sigma analog-to-digital data converter; FIG. 2A is a schematic block diagram of a previously known subtractor/integrator block and FIG. 2B is a timing diagram for the circuit of FIG. 2A; FIG. 3A is an illustrative diagram of a prior art integrated circuit capacitor, and FIG. 3B is a diagram of two capacitors formed from the integrated circuit capacitor of FIG. 3A FIG. 4 is schematic diagram of an illustrative embodiment of a subtractor/integrator block and state machine of the present invention; FIG. 5 is a timing diagram for the circuit of FIG. 4; FIG. 6 is a schematic diagram of an illustrative embodiment of an alternative embodiment of a subtractor/integrator block and state machine of the present invention; and FIG. 7 is a timing diagram for the circuit of FIG. 6. To provide background for the present invention, this written description first sets forth a previously known subtractor/integrator circuit and describes the circuit components that affect full-scale error. Then, the modification of such previously known subtractor/integrator circuits is described and alternative embodiments are disclosed. A. Prior Art Subtractor/Integrator Circuit Referring to FIG. 2, a previously known circuit that combines the function of subtractor 12 and integrator 14 of FIG. 1 is described. Circuit 30 includes amplifier 32 having inverting input V IN , non-inverting input V IP and output V OUT . Integrating capacitor C F is coupled between V IN and V OUT . Capacitor C REF is coupled between reference node - V REF and V IN through switches S1 and S2, and is coupled to bias node V BIAS through switches S3 and S4. Capacitor C IN is coupled between input signal node V INPUT and V IN through switches S7 and S8, and is coupled to V BIAS through switches S5 and S6. Switch S1 is controlled by clock signal  1 . Switches S4, S6 and S7 are controlled by clock signal  2 , and switches S2, S3, S5 and S8 are controlled by clock signal  3 . State machine 34 receives as inputs CLKA and Y (of FIG. 1), and generates clock signals  1 ,  2 and  3 . FIG. 2B shows the timing relationship between CLKA, Y,  1 ,  2 and  3 . Y only may change on the rising edge of CLKA. Circuit 30 receives input signal V INPUT and signal -V REF and produces the intermediary signal IE1 (FIG. 1) at V OUT . Internally-generated bias signal V BIAS (which may or may not be circuit ground) is used as a reference for charging and discharging charge transfer capacitors C IN and C REF and integrating capacitor C F . When Y and CLKA are both HIGH, capacitor C REF samplers - V REF and capacitor C IN samples V INPUT . When Y is LOW and CLKA is HIGH, capacitor C REF remains discharged (i.e., effectively samples 0 volts) and capacitor C IN samples V INPUT . In both cases, when CLKA changes from HIGH to LOW, the charges stored on capacitors C REF and C IN are transferred to integrating capacitor C F . For circuit 30, the full-scale accuracy primarily depends on the ratio accuracy of C REF and C IN . In particular, when clock signals ϕ 1 and ϕ 2 are both HIGH, an electrical charge Q REF proportional to reference signal - V REF ( Q REF = -C REF * V REF ) is stored on capacitor C REF , and an electrical charge Q IN proportional to input signal V INPUT (Q IN = C IN * V INPUT ) is stored on capacitor C IN . On the next pulse of  3 (i.e., when  2 goes LOW and  3 goes HIGH), electrical charges Q IN and Q REF are transferred to integrating capacitor C F . Amplifier 32 facilitates the charge transfer. Various methods for constructing amplifier 32 are well-known. A complete cycle of state machine 34 is defined as one complete cycle of CLKA, which includes one complete cycle of clocks ϕ 2 and ϕ 3 . At the end of one complete cycle of CLKA when Y is HIGH, the total charge Q TOT (HIGH) transferred to integrating capacitor C F equals the sum of the charges stored on C REF and C IN during the cycle: Q TOT (HIGH) = C IN * V INPUT - C REF * V REF At the end of one complete cycle of CLKA when Y is LOW, the total charge Q TOT (LOW) transferred to integrating capacitor C F equals the sum of the charges stored on C REF (which has zero charge) and C IN during the cycle: Q TOT (LOW) = C IN *V INPUT The ratio of Q TOT (LOW) to Q TOT (HIGH) depends on the ratio of C IN to C REF and on the relative voltage ratio of V INPUT to reference signal V REF . Accordingly, the full-scale accuracy of the modulator depends on the ratio of C IN to C REF . In integrated circuit technology, capacitor value is proportional to the area of the capacitor top and bottom plates, and inversely proportional to the thickness of dielectric between the two plates. Assuming that the dielectric thickness for capacitors within an integrated circuit is uniform, the ratio of two capacitors depends solely on their area ratios. As a result, prior art integrated circuit techniques typically seek to improve the accuracy of the ratio of C IN to C REF by controlling the accuracy of the ratio of the areas of the two capacitors. To improve area ratio accuracy, integrated circuit capacitors typically are constructed using arrays of identical "unit" capacitors that are connected to provide specific capacitor values. FIG. 3 shows an example of a typical prior art technique for constructing capacitors C IN and C REF , whose ratio is 1:2. FIG. 3A shows unit capacitor 40 having top plate 42, bottom plate 44, conductor 46 connected to bottom plate 44 by contact 50, and conductor 48 connected to top plate 42 by contact 52. FIG. 3B shows capacitors C IN and C RE F formed from unit capacitor 40. In particular, C REF is formed from two unit capacitors, and includes top plates 66 joined by conductor 60, and bottom plate 62. C IN is constructed from a single unit capacitor, and consists of top plate 68 and bottom plate 64. Although such prior art layout techniques improve ratio accuracies, the techniques by themselves do not permit very low full-scale error in oversampling delta-sigma analog-to-digital converters. B. The Invented Subtractor/Intgrator In accordance with principles of the present invention, a subtractor/integrator circuit is provided for oversampling delta-sigma A/D converters that effectively provides input sampling capacitors C IN and C REF having a ratio that may be expressed as a rational number N / M , where N and M are relative prime integers. The circuit provides this ratio using N + M distinct unit capacitors C U1 , C U2 , ... C u ( M + N ) , under the control of a state machine. In particular, the state machine controls how each distinct unit capacitor C U1 , C U2 , . . . C U ( M + N ) is used to sample the signals V INPUT and -V REF . During one complete cycle of the new state machine (i.e., one cycle of CLKA in FIG. 1), each unit capacitor C U1 , C U2 , . . . C U ( M + N ) samples V INPUT a first predetermined number of times to effectively construct an equivalent input capacitor C IN . Similarly, during one complete cycle of the new state machine, depending on whether Y is LOW or HIGH, each unit capacitor C U1 , C U2 , ... C U(M+N) samples - V REF (or + V REF ) a second predetermined number of times to effectively construct an equivalent reference capacitor C REF . The first predetermined number of times is equal to C (M + N -1, N -1), where C( i , j ) is the well-known binomial coefficient: C ( i , j ) = i ! ( i - j ) ! j ! The second predetermined number of times is equal to C( M + N -1, M -1). One state machine cycle corresponds to one cycle of CLKA (FIG. 1). However, the state machine operates C(M+N,N) times the frequency of CLKA. The result of the state machine cycle is an equivalent input capacitor C IN = N*C(M+N,N)* C UNIT and an equivalent reference capacitor C REF = M*C (M+N, N) *C UNIT , where C UNIT is the unit capacitor value. Each unit capacitor C U1 , C U2 , ... C U(M+N) is used to construct the equivalent C IN capacitor exactly C( M + N -1, N -1) times and to construct the equivalent C REF , capacitor exactly C( M + N -1, M -1) times. Hence, the ratio of the equivalent capacitors C IN to C REF becomes exactly N/M, independent of the actual value of the M + N distinct unit capacitors C U1 , C U2 , ... CU ( M+N ) . Referring to FIG. 4, an exemplary embodiment of a subtractor/integrator of the present invention is described in which N = 1 and M = 2. Subtractor/integrator circuit 70 includes amplifier 72 having inverting input V IN , non-inverting input V IP and output V OUT . Integrating capacitor C F is coupled between V IN and V OUT · C REF and C IN from FIG. 2A have been divided into 3 unit capacitors C U1 , C U2 and C U3 . Capacitor C U1 is coupled between reference node - V REF and V INPUT and V IN through switches S11-S13, and is coupled to bias node V BIAS through switches S20 and S21. Capacitor C U2 is coupled between reference node - V REF and V INPUT and V IN through switches S14-S16, and is coupled to bias node V BIAS through switches S22 and S23. Capacitor C U3 is coupled between reference node - V REF and V INPUT and V IN through switches S17-S19, and is coupled to bias node V BIAS through switches S24 and S25. Switches S11, S13, S14, S16, S17 and S19 are controlled by clock signals ϕ 3a' ϕ 3d , ϕ 3b' ϕ 3e' ϕ 3c and  3f , respectively. Switches S12, S15, S18, S20, S22 and S24 are controlled by clock signal  4a , and switches S21, S23 and S25 are controlled by clock signal  5a . State machine 74 receives as inputs CLKA' and Y, and generates clock signals ϕ 3a , ϕ 3b , ϕ 3c , ϕ 3d , ϕ 3e , ϕ 3f , ϕ 4a and  5a in accordance with techniques that are well-known. FIG. 5 shows the timing relationship between CLKA, Y, CLKA', ϕ 3a , ϕ 3b , ϕ 3c , ϕ 3d , ϕ 3e , ϕ 3f , ϕ 4a and  5a . Y only may change on the rising edge of CLKA. Circuit 70 receives signals V INPUT and - V REF and produces the intermediary signal IE1 (FIG. 1) at V OUT . Bias signal V BIAS is used as a reference for charging and discharging charge transfer capacitors C U1 , C U2 and C U3 and integrating capacitor C F . The implementation of amplifier 72 that facilitates the charge transfer from the sampling capacitors C U1 , C U2 and C U3 to integrating capacitor C F is well-known. The frequency of clock signal CLKA' is three times (i.e, C( M + N , N )) the frequency of CLKA. Accordingly, three cycles of CLKA' occur during a single cycle of CLKA. If Y is HIGH during a cycle of CLKA, subtractor/integrator 70 operates as follows. During the first cycle of CLKA', when clock signals 3a ,   3b ,  3f and  5a are all HIGH, an electrical charge Q 1 proportional to reference signal -V REF ( Q 1 = -C U 1 * V REF ) is stored on capacitor C U 1 , an electrical charge Q 2 proportional to reference signal - V REF ( Q 2 = - C U 2 * V REF ) is stored on capacitor C U2 , and an electrical charge Q 3 proportional to input signal V INPUT ( Q 3 = C U 3 * V INPUT ) is stored on capacitor C U3 . On the next pulse of  4a (i.e., when  5a goes LOW and  4a goes HIGH), electrical charges Q 1 , Q 2 and Q 3 are transferred to integrating capacitor C F . During the second cycle of CLKA', when clock signals  3b ,  3c ,  3d and  5a are all HIGH, an electrical charge Q 1 proportional to input signal V INPUT ( Q 1 = C U 1 * V INPUT ) is stored on capacitor C U 1 , an electrical charge Q 2 proportional to reference signal - V REF ( Q 2 = - C U 2 * V REF ) is stored on capacitor C U 2 , and an electrical charge Q 3 proportional to reference signal - V REF ( Q 3 = - C U 3 * V REF ) is stored on capacitor C U 3 . On the next pulse of  4a (i.e., when  5a goes LOW and  4a goes HIGH), electrical charges Q 1 , Q 2 and Q 3 are transferred to integrating capacitor C F . During the third cycle of CLKA', when clock signals  3a ,  3c ,  3e and  5a are all HIGH, an electrical charge Q 1 proportional to reference signal - V REF ( Q 1 = - C U 1 * V REF ) is stored on capacitor C U 1 , an electrical charge Q 2 proportional to input signal V INPUT ( Q 2 = C U 2 * V INPUT ) is stored on capacitor C U 2 , and an electrical charge Q 3 proportional to reference signal -V REF (Q 3 = - C U3 * V REF ) is stored on capacitor C U3 . On the next pulse of  4a (i.e., when  5a goes LOW and  4a goes HIGH), electrical charges Q 1 , Q 2 and Q 3 are transferred to integrating capacitor C E . Thus, when Y is HIGH during a complete cycle of CLKA, the total charge Q TOT (HIGH) transferred to integrating capacitor C F equals the sum of the charges stored on C U1 , C U2 and C U3 during the cycle: If C U1 + C U2 + C U3 = C X , equation (7) may be re-written as: Q TOT (HIGH) = C X *V INPUT - 2 * C x * V REF Equation (8) is identical to equation (4), where C x = C IN and C REF = 2* C IN . If Y is LOW during a cycle of CLKA, subtractor/integrator 70 operates as follows. During the first cycle of CLKA', when clock signals  3f and  5a are both HIGH, an electrical charge Q 3 proportional to input signal V INPUT (Q 3 = C U3 *V INPUT ) is stored on capacitor C U3 . On the next pulse of  4a (i.e., when  5a goes LOW and  4a goes HIGH), electrical charge Q 3 transfers to integrating capacitor C F . During the second cycle of CLKA', when clock signals  3d and  5a are both HIGH, an electrical charge Q 1 proportional to input signal V INPUT ( Q 1 = C U1 * V INPUT ) is stored on capacitor C U1 . On the next pulse of  4a . (i.e., when  5a goes LOW and  4a goes HIGH), electrical charge Q 1 transfers to integrating capacitor C F . During the third cycle of CLKA', when clock signals  3e and  5a are both HIGH, an electrical charge Q 2 proportional to input signal V INPUT (Q 2 = C U2 * V INPUT ) is stored on capacitor C U2 . On the next pulse of  4a (i.e., when  5a goes LOW and  4a goes HIGH), electrical charge Q 2 transfers to integrating capacitor C F . Thus, when Y is LOW during a complete cycle of CLKA, the total charge Q TOT (LOW) transferred to integrating capacitor C F equals the sum of the charges stored on C U1 , C U2 and C U3 during the cycle: If C U1 + C U2 + C U3 = C X , equation (9) may be re-written as: Q TOT (LOW) = C X * V INPUT Equation (10) is identical to equation (5), where C X = C IN . Thus, at the end of a complete cycle of CLKA, each unit capacitor C U1 , C U2 , and C U3 has been used once (i.e., a first predetermined number of times C( M + N -1, N -1)) to construct the equivalent input capacitor C IN and twice (when Y is HIGH) (i.e., a second predetermined number of times C( M + N -1, M -1)) to construct the equivalent reference capacitor C REF . Hence, the ratio between the equivalent capacitance of C IN and C REF is 1:2, independent of the actual value of unit capacitors C U1 , C U2 and C U3 . Referring now to FIG. 6, an alternative embodiment of a subtractor/integrator of the present invention is described in which N = 1 and M = 2, and the input signal V INPUT may have both positive and negative polarities. Subtractor circuit 80 includes amplifier 82 having inverting input V IN , non-inverting input V IP and output V OUT . Integrating capacitor C F is coupled between V IN and V OUT . C REF and C IN from FIG. 2A have been divided into 3 unit capacitors C U1 , C U2 and C U3 . Capacitor C U1 is coupled between reference nodes + V RE F , - V REF and V INPUT and V lN through switches S31-S34, and is coupled to bias node V BIAS through switches S43 and S44. Capacitor C U2 is coupled between reference node + V REF , - V REF and V INPUT and V IN through switches S35-S38, and is coupled to bias node V BIAS through switches S45 and S46. Capacitor C U3 is coupled between reference nodes + V REF , - V REF and V INPUT and V IN through switches S39-S42, and is coupled to bias node V BIAS through switches S47 and S48. Switches S31, S32, S33, S35, S36, S37, S39, S40 and S41 are controlled by clock signals  3ah ,  3al ,  3d  3d ,  3bh ,  3b1 ,  3e ,  3ch ,  3c1 and  3f , respectively. Switches S34, S38, S42, S43, S45 and S47 are controlled by clock signal  4a , and switches S44, S46 and S48 are controlled by clock signal  5a . State machine 84 receives as input CLKA' and Y, and generates clock signals  3ah ,  3al ,  3bh ,  3bl ,  ch ,  cl ,  3d ,  3e ,  3f ,  4a and  5a in accordance with techniques that are well-known. FIG. 7 shows the timing relationship between CLKA',  3ah ,  3al ,  3bh ,  3bl ,  3ch ,  cl ,  3d ,  3e ,  3f ,  4a and  5a . Clock signals CLKA,  3d ,  3e ,  3f'  4a and ϕ 5a are the same as shown in FIG. 5, and Y only may change on the rising edge of CLKA. Circuit 80 receives signals V INPUT and + V REF and - V REF and produces intermediary signal IE1 (FIG. 1) at V OUT . Bias signal V BIAS is used as reference for charging and discharging charge transfer capacitors C U1 , C U2 and C U3 and integrating capacitor C F . The implementation of the amplifier 82 that facilitates the charge transfer from the sampling capacitors C U1 , C U2 and C U3 to integrating capacitor C F is well-known. If Y is HIGH during a cycle of CLKA, subtractor/integrator 80 operates as follows. During the first cycle of CLKA', when clock signals  3ah ,  3bh ,  3f and  5a are all HIGH, an electrical charge Q 1 proportional to reference signal -V REF (iQ 1 = - C U1 * V REF ) is stored on capacitor C U1 , an electrical charge Q 2 proportional to reference signal -V REF ( Q 2 = - C U2 * V REF ) is stored on capacitor C U2 , and an electrical charge Q 3 proportional to input signal V INPUT ( Q 3 = C U3 * V INPUT ) is stored on capacitor C U3 . On the next pulse of  4a (i.e., when  5a goes LOW and  4a goes HIGH), electrical charges Q 1 , Q 2 and Q 3 are transferred to integrating capacitor C F . During the second cycle of CLKA', when clock signals  3bh'  3ch'  3d and 5a are all HIGH, an electrical charge Q 1 proportional to input signal V INPUT ( Q 1 = C U1 * V INPUT ) is stored on capacitor C U1 , an electrical charge Q 2 proportional to reference signal -V REF ( Q 2 = - C U2 * V REF ) is stored on capacitor C U2 , and an electrical charge Q 3 proportional to reference signal -V REF ( Q 3 = - C U3 * V REF ) is stored on capacitor C U3 . On the next pulse of  4a (i.e., when  5a goes LOW and  4a goes HIGH), electrical charges Q 1 , Q 2 and Q 3 are transferred to integrating capacitor C F . During the third cycle of CLKA', when clock signals  3ah,  3ch,  3e and  5a , are all HIGH, an electrical charge Q 1 proportional to reference signal - V REF ( Q 1 = - C U1 * V REF ) is stored on capacitor C U1 , an electrical charge Q 2 proportional to input signal V INPUT ( Q 2 = C U2 * V INPUT ) is stored on capacitor C U2 , and an electrical charge Q 3 proportional to reference signal - V REF (Q3 = - C U3 * V REF ) is stored on capacitor C U3 . On the next pulse of  4a (i.e., when  5a goes LOW and  4a goes HIGH), electrical charges Q 1 , Q 2 and Q 3 are transferred to integrating capacitor C F . Thus, when Y is HIGH during a complete cycle of CLKA, the total charge Q TOT (HIGH) transferred to integrating capacitor C F . equals the sum of the charges stored on C U1 , C U2 and C U3 during the cycle: If Y is LOW during a cycle of CLKA, subtractor/integrator 80 operates as follows. During the first cycle of CLKA', when clock signals  3al ,  3bl ,  3f and  5a are all HIGH, an electrical charge Q 1 proportional to reference signal +V REF ( Q 1 = + C U1 * V REF ) is stored on capacitor C U1 , an electrical charge Q 2 proportional to reference signal +V REF (Q 2 = + C U2 * V REF ) is stored on capacitor C U2 , a nd an electrical charge Q 3 proportional to input signal V INPUT (Q 3 = C U3 * V INPUT ) is stored on capacitor C U3 . On the next pulse of Φ 4a (i.e., when  5a goes LOW and  4a goes HIGH), electrical charges Q 1 , Q 2 and Q 3 are transferred to integrating capacitor C F . During the second cycle of CLKA', when clock signals Φ 3bl , Φ 3cl , Δ 3d and Φ 5a are all HIGH, an electrical charge Q 1 proportional to input signal V INPUT ( Q 1 = C U1 * V INPUT ) is stored on capacitor C U1 , an electrical charge Q 2 proportional to reference signal + V REF ( Q 2 = + C U2 * V REF ) is stored on capacitor C U2 , and an electrical charge Q 3 proportional to reference signal +V REF ( Q 3 = + C U3 * V REF ) is stored on capacitor C U3 . On the next pulse of  4a (i.e., when  5a goes LOW and  4a goes HIGH), electrical charges Q 1 , Q 2 and Q 3 are transferred to integrating capacitor C F . During the third cycle of CLKA', when clock signals  3a1'  3c1'  3a , and  5a , are all HIGH, an electrical charge Q 1 proportional to reference signal + V REF ( Q 1 = + C U1 * V REF ) is stored on capacitor C U1 , an electrical charge Q 2 proportional to input signal V INPUT . ( Q 2 = C U2 * V INPUT ) is stored on capacitor C U2 , and an electrical charge Q 3 proportional to reference signal +V REF (Q 3 = + C U3 * V REF ) is stored on capacitor C U3 . On the next pulse of Φ 4a (i.e., when Φ 5a goes LOW and Φ 4a goes HIGH), electrical charges Q 1 , Q 2 and Q 3 are transferred to integrating capacitor C F . Thus, when Y is LOW during a complete cycle of CLKA, the total charge Q TOT (LOW) transferred to integrating capacitor C F equals the sum of the charges stored on C U1 , C U2 and C U3 during the cycle: If C U1 + C U2 + C U3 = C X , equations (11) and (12) may be re-written, respectively, as: Q TOT (HIGH) = C x *V INPUT - 2*C x * V REF Q TOT (LOW) = C X * V INPUT + 2* C x * V REF Thus, at the end of a complete cycle of CLKA, when Y is HIGH or LOW, each unit capacitor C U1 , C U2 and C U3 has been used once (i.e., a first predetermined number of times C(M+N-1, N-1)) to construct the equivalent input capacitor C IN and twice (i.e., a first predetermined number of times C( M + N -1, M-1)) to construct the equivalent reference capacitor C REF . Hence, the ratio between the equivalent capacitance of C IN and C REF is 1:2, independent of the actual value of unit capacitors C U1 , C U2 and C U3 . Persons skilled in the art further will recognize that the circuitry of the present invention may be implemented using circuit configurations other than those shown and discussed above. For example, the circuits of FIGS. 4 and 6 may be implemented as fully-differential circuits. All such modifications are within the scope of the present invention, which is limited only by the claims that follow.

Claims: A subtractor/integrator circuit that generates at an output node an output signal proportional to the sum of (a) an input signal multiplied by a predetermined scale factor N / M , where N and M are relative prime integers and (b) a reference signal, the subtractor/integrator circuit comprising: an input signal node to which the input signal is applied; a reference signal node to which the reference signal is applied; a bias signal node to which a bias signal is applied; an output circuit coupled to the bias signal node, the output circuit having an output coupled to the output node; and characterized by : N+M switched-capacitor circuits coupled to the input signal node, the reference signal node, the bias signal node and the output circuit; and control circuitry (74) coupled to the N+M switches capacitor circuits (C u1, 2, 3 ) the control circuitry causing each of the N + M switched capacitor circuits to sample the input signal a first predetermined number of times and to sample the reference signal a second predetermined number of times, wherein the ratio of the first predetermined number to the second predetermined number equals the scale factor N / M . The circuit of claim 1, comprising a first reference signal node to which a first reference signal is applied, and a second reference signal node to which a second reference signal is applied; wherein the N+M switched-capacitor circuits are coupled to the input signal node, the first reference signal node, the second reference signal node, the bias signal node and the output circuit; and the control circuitry causes each of the N + M switched capacitor circuits to sample the input signal a first predetermined number of times and to sample either the first or second reference signals a second predetermined number of times, wherein the ratio of the first predetermined number to the second predetermined number equals the scale factor N / M . The circuit of claim 1 or 2, wherein the N + M switched capacitor circuits each comprise a capacitor. The circuit of claim 3, wherein each capacitor comprises a top plate and a bottom plate. The circuit of claim 1, 2, 3 or 4, wherein: the output circuit comprises an amplifier having an inverting input node coupled to the N + M switched-capacitor circuits, a non-inverting input node coupled to the bias signal node, and an output signal node coupled to the output node; and the subtractor/integrator circuit further comprises a feedback capacitor coupled between the inverting input node and the output node. The circuit of claim 5, wherein the N + M switched capacitor circuits..each further comprise first and second inputs, and first and second outputs, the first input coupled to the reference signal node, the second input coupled to the input signal node, the first output coupled to the inverting input node and the second output coupled to the non-inverting input node The circuit of claim 6, wherein the N + M switched capacitor circuits each further comprise: a first switch coupled between the reference signal node and the top plate of the capacitor; a second switch coupled between the bottom plate of the capacitor and the inverting input node; a third switch coupled between the input signal node and the top plate of the capacitor; a fourth switch coupled between the top plate of the capacitor and the non-inverting input node; and a fifth switch coupled between the bottom plate of the capacitor and the non-inverting input. The circuit of claim 4, 5, 6, or 7, wherein: the control circuitry provides at a plurality of outputs a plurality of control signals; the N + M switched capacitor circuits each further comprise first, second, third and fourth control inputs coupled to the plurality of control signals; and the plurality of control signals cause each of the N + M switched capacitor circuits to sample the input signal the first predetermined number of times and to sample the reference signal the second predetermined number of times The circuit of claim 8 when dependent on claims 4, 5 or 6, wherein the N+M switched capacitor circuits each further comprise: a first switch coupled between the reference signal node and the top plate of the capacitor, the first switch comprising a switch control input coupled to the first control input; a second switch coupled between the bottom plate of the capacitor and the inverting input node, the second switch comprising a switch control input coupled to the second control input; a third switch coupled between the top plate of the capacitor and the input signal node, the third switch comprising a switch control input coupled to the third control input; a fourth switch coupled between the top plate of the capacitor and the non-inverting input node, the fourth switch comprising a switch control input coupled to the second control input; and a fifth switch coupled between the bottom plate of the capacitor and the non-inverting input, the fifth switch comprising a switch control input coupled to the fourth control inputs. The circuit of claim 5, wherein the N + M switched capacitor circuits each further comprise first, second and third inputs, and first and second outputs, the first input coupled to the first reference signal node, the second input coupled to the second reference signal node, and the third input coupled to the input signal node, the first output coupled to the inverting input node and the second output coupled to the non-inverting input node. The circuit of claim 10, wherein the N + M switched capacitor circuits each further comprise: a first switch coupled between the first reference signal node and the top plate of the capacitor; a second switch coupled between the bottom plate of the capacitor and the inverting input node; a third switch coupled between the second reference signal node and the top plate of the capacitor; a fourth switch coupled between the top plate of the capacitor and the non-inverting input node; a fifth switch coupled between the bottom plate of the capacitor and the non-inverting input; and a sixth switch coupled between the input signal node and the top plate of the capacitor. The circuit of claim 4, 5, 10 or 11, wherein: the control circuitry provides at a plurality of outputs a plurality of control signals; the N + M switched capacitor circuits each further comprise first, second, third, fourth and fifth control inputs coupled to the plurality of control signals; and the plurality of control signals cause each of the N + M switched capacitor circuits to sample the input signal the first predetermined number of times and to sample either the first reference signal or the second reference signal the second predetermined number of times. The circuit of claim 12, wherein the N + M switched capacitor circuits each further comprises: a first switch coupled between the first reference signal node and the top plate of the capacitor, the first switch comprising a switch control input coupled to the first control input; a second switch coupled between the bottom plate of the capacitor and the inverting input node, the second switch comprising a switch control input coupled to the second control input; a third switch coupled between the second reference signal node and the top plate of the capacitor, the third switch comprising a switch control input coupled to the third control input; a fourth switch coupled between the top plate of the capacitor and the non-inverting input node, the fourth switch comprising a switch control input coupled to the second control input; a fifth switch coupled between the bottom plate of the capacitor and the non-inverting input, the fifth switch comprising a switch control input coupled to the fourth control input; and a sixth switch coupled between the input signal node and the top plate of the capacitor, the sixth switch comprising a switch control input coupled to the fifth control input. The circuit of claim 9, 10, 11, 12 or 13, wherein: N = 1 and M = 2, and the N + M = 3 switched capacitor circuits comprise first, second and third switched capacitor circuits; and the second control input of each of the first, second and third switched capacitor circuits are coupled together, and the fourth control input of each of the first, second and third switched capacitor circuits are coupled together. A method for generating an output signal proportional to the sum of (a) an input signal multiplied by a predetermined scale factor N / M and (b) a reference signal, the method characterized by comprising : storing a first charge proportional to the input signal on each of N + M capacitors (C u 1, 2, 3 ) a first predetermined number of times; storing a second charge proportional to the reference signal on each of N + M capacitors a second predetermined number of times, wherein the ratio of the first predetermined number to the second predetermined number equals the scale factor N / M ; and transferring the first charge and the second charge to an integrating capacitor, wherein the voltage across the integrating capacitor comprises the output signal. The method of claim 15, comprising storing a second charge proportional to either the first or the second reference signal on each of N + M capacitors a second predetermined number of times, wherein the ratio of the first predetermined number to the second predetermined number equals the scale factor N / M .

Inventors: OPRESCU FLORIN A, OPRESCU, FLORIN A.
Applicants: LINEAR TECHN INC, LINEAR TECHNOLOGY CORPORATION
Application year: 1999
Main classification: H03M3
IPC codes: H03M3