Arbitrary waveform generator

Abstract: A method of waveform generation using a VLSI digital tester unit without an arbitrary waveform generator. A software application (328-338) produces a series of vectors to drive a digital tester unit from a set of datapoints which defines a waveform needed in the test program. The set of datapoints can be generated in a test simulator such as SPICE or can be generated by digitizing the arbitrary waveform needed in a test program. The vectors describe the number of resistors of a pseudo arbitrary waveform generator (PAWG) circuit to be driven high in order to reproduce the desried waveform for input into the device under test. The software also determines the resolution, e.g., 5ns, of the waveform.

Description: Background and Summary of the Invention The present invention relates to the field of electronic design and testing, and specifically to the field of generation of analog test signals for device testing. Background: Linear and Mixed-Signal Devices Mixed-signal devices require synchronized analog and digital signals to be sourced to the Device-Under-Test ("DUT") for comprehensive test coverage. Linear DUTs also require analog signals to be sourced as input for complete test coverage. These mixed analog and digital signals are known as test stimuli. Both types of devices require input waveforms which are extremely difficult to generate. The problem is increasingly difficult when attempting to test such devices with a VLSI digital tester. The analog signal and mixed signal (digital patterns that work in combination with analog signals) portions of test programs are typically generated by a test engineer. The test engineer uses mostly manual processes to create and measure sine waves, current, DC voltages, and digital patterns to exercise the analog and mixed-signal portions of the DUT. Consequently, generation of analog and mixed-signal test programs is still a laborious and manual process. Background: Arbitrary Waveform Generators The traditional solution to generating the waveforms needed to fit the analog portion of a test program is to add an expensive Arbitrary Waveform Generator (or "AWG"), such as the HP E1441A by Hewlett Packard, to a digital tester unit. Typically, an AWG such as the HP E1441A can output standard waveforms: sine, square, triangle, ramp, and noise. The AWG also allows custom design of waveforms. Any waveform generated can be modulated using AM, FM, FSK, or other forms of modulation. Frequency sweeping is also typically available. The number of datapoints defined in the waveform (or "the resolution of the waveform") is also subject to user control in the AWG. Figure 2 depicts the connection of a digital tester unit to both an AWG and a DUT. The VLSI Digital Tester initiates and controls the generation of waveforms needed to test the DUT. Communication of the VLSI Digital Tester unit with the DUT depends upon the design of the DUT. Generally, an electronic interconnection, such as Testhead 102 is constructed as the interface between the output pins of the VLSI Digital Tester unit and the input pins of the DUT. The interface can include additional hardware which further modifies the output of the digital tester unit. A device interface board 104 is used to connect the Testhead 102 to the DUT. The Tester Control Computer controls both the AWG and the VLSI Digital Tester while a test program is administered. The AWG must also be in communication with the VLSI digital tester unit. The VLSI digital Tester and the AWG are connected in order to synchronize the output of the AWG (input to the DUT) with the VLSI Digital Tester. As Figure 2 reveals, one source of problems for the test engineer in utilizing an AWG is cabling. When setting up a test of a device type that uses AWG output, the test engineer must install cables to the testhead, the VLSI Digital Tester, and the Tester Control Computer. When a device type that does not use the AWG is setup for testing, the cables must be removed. Aside from interface issues, another disadvantage of using an AWG is cost. The cost of an AWG usually depends on the resolution of the waveform (or the number of samples per second) which it can process. The rise in costs of AWGs is often disproportional to the resolution of the waveform generated. The result can be a digital tester/AWG combination with a 1998 price tag of $1 million connected to a DUT priced at $2. Pseudo Arbitrary Waveform Generator The present application discloses a method which allows an inexpensive circuit of resistors and capacitors to convert the output of digital tester drivers to a finite range of arbitrary waveforms. The generation of arbitrary waveforms takes place without an AWG. A software application receives a set of datapoints which defines a waveform needed in the test program. The set of datapoints can be generated in a test simulator such as SPICE or can be generated by digitizing the arbitrary waveform needed in the test program. The software, based on the set of datapoints, determines how many resistors of a pseudo arbitrary waveform generator (PAWG) circuit need to be driven high in order to reproduce the waveform for input into the DUT. The software also determines the resolution, e.g., 5ns, of the waveform. Once these calculations are complete, a set of digital vectors is created which describes to the VLSI digital tester how and when to drive the resistors. The vector set generated must be in a language accepted by the target VLSI tester. As the vector set is processed, the resistors of the PAWG circuit cause the voltage at the output of the circuit to modulate. A capacitor connected to the resistors smooths the modulation creating a waveform substantially similar to that described by the set of datapoints. The output of the circuit (the test stimulus) is then applied to the DUT. Brief Description of the Drawings The disclosed inventions will be described with reference to the accompanying drawings, which show important sample embodiments of the invention and which are incorporated in the specification hereof by reference, wherein: Figure 1 depicts the PAWG circuit. Figure 2 depicts the connection of an AWG to both a VLSI Digital Tester and a DUT. Figures 3A and 3B are a flowchart of the PAWG. Detailed Description of the Preferred Embodiments The numerous innovative teachings of the present application will be described with particular reference to the presently preferred embodiment. However, it should be understood that this class of embodiments provides only a few examples of the many advantageous uses of the innovative teachings herein. In general, statements made in the specification of the present application do not necessarily delimit any of the various claimed inventions. Moreover, some statements may apply to some inventive features but not to others. Pseudo Arbitrary Waveform Generator Software In the presently preferred embodiment, the generation of pseudo-arbitrary waveforms is accomplished using a software application, a vector set, a VLSI digital tester, and a discrete time to continuous time conversion circuit. Many different digital testers are currently available. For example, V-series or Polaris testers can be acquired and used with the pseudo arbitrary waveform generator (or "PAWG") described. From the perspective of the PAWG, the digital testers differ only in the vector set required to properly drive the resistor divider of the PAWG circuit. A VLSI digital tester typically has a pattern generator which will take fixed data and apply new data at an accurately fixed rate, such as every 5ns. At such a rate, logic data supplied to any of inputs R 1 -R n (the resistors of the resistor divider of the PAWG circuit) are capable of changing from a preprogrammed high voltage e.g., 1 in the presently preferred embodiment, to a preprogrammed low voltage e.g., -1 in the presently preferred embodiment (or vice versa) every 5ns. The PAWG results in simplified generation of analog test stimuli, including unusually shaped waveforms, with relatively few components and at a reduced cost. A software application is used to create the vector set. Prior knowledge of the digital tester which will be used in the PAWG process is needed so that an accurate vector set can be generated. The software code used to generate all information needed to produce the vector set is generic. Only the vector set routine must be altered for each VLSI digital tester. Figures 3A and 3B are a flowchart of the PAWG software. In the presently preferred embodiment, the PAWG software reads a file of time/voltage pairs 302 which define a waveform in discrete time intervals (Step 304). A simulator, e.g., SPICE or a digitized waveform, can be used to produce such a file. In an actual test case, an analog waveform can be generated, digitized, and then used in a test program. As the datapoint (time/voltage pair) is read, it is stored in a pair of arrays (time and voltage) (Step 306). Once at least two datapoints are read, a determination can be made as to the slope of the curve described by the datapoints can be made (Step 308). Datapoints are processed until 2 endpoints to the RC curve are found (the slope of the curve changes). The beginning of the slope is referred to in the software code as FNR. If a change of slope has occurred or the voltage was decreasing and is now increasing or vice versa, an endpoint of the present curve is indicated. The curve (or RC curve) is the capacitive charge or decay curve which is an arc when voltage is plotted against time). The shape (or angle) of the RC curve is dependent on many factors including the RC constants in the software: RCa is the resistance/capacitance time constant for R 1 -R n and C 1 of Figure 1. RCb is the resistance/capacitance time constant for R s and C s of Figure 1. res is the resolution of the waveform. That is, the minimum time space between changes in the waveform. In the presently preferred embodiment, the resolution of the waveform is 5ns. RPV is the resolution per vector. In a 10ns time period, RPV is 2. That is, there are 2 changes per period. The goal of this section of the PAWG software is to find the datapoints of the arc that make up the endpoints of the curve which will be generated as analog test stimuli. Once endpoints to the curve are found, a curve fit routine is called (Step 310). Curve Fit Routine If the curve fit routine is called because of a change in direction, the routine receives a 0. If the curve fit routine is called because of a change in slope, the routine receives a 1. The routine first calculates the change in voltage (ΔV) and the change in time (ΔT) values based on the datapoints found as the two endpoints of the RC curve (Step 312). ΔV is the difference between the voltage applied at the beginning of the curve and what voltage is desired at the end of the curve. ΔT is the difference in time for the beginning of the curve to the end of the curve, rounded to the nearest resolution time period (5ns in the presently preferred embodiment). That is ΔT=res*time. The curve fit function calculates an ideal Vapp that will achieve the endpoint voltage desired (Step 314). VAend is the voltage that should be applied at the endpoint of the curve. Vapp then is a function of the voltage to the resistor divider (R 1 -R n ) vs. RCa. That is, the function calculates the initial voltage needed at R 1 -R n to achieve ΔV within ΔT with a capacitance of C 1 . The formula used in the presently preferred embodiment is: Vapp=ΔV/(1-exp(-1*ΔT/RCa))+VAnow where: Vapp is the voltage to be applied to R 1 -R n of the resistor divider; and VAnow is the voltage that would result at C 1 . VAnow is tracked as the time and voltage values change over the datapoints of the curve. The result of the calculation determines how many of resistors R 1 -R n to drive high (+1v) and how many to drive low (-1v) (Step 316). The voltage that would be obtained by driving the resistor divider in this manner is calculated as VAnew and the voltage expected at the end of the curve is predicted upon the basis of previous calculations (the number of resistors driven high and low vs. the voltage at the beginning of the curve) (Steps 318 and 320). If VAnew is not equal to VAend, the number of resistors driven high must be adjusted (Step 322). If VAnew is lower than the ideal Vapp then the pattern data (data indicating how many resistors to drive high and low) is adjusted to drive more resistors high (Step 324). If the voltage that would be obtained is higher than the ideal VAend then the pattern data is adjusted to drive more resistors low (Step 324). This adjustment is made only to a few datapoints at the beginning of the curve (Step 324). This small adjustment window is due to an acceleration factor on C1. That is, for significant changes on the resistor divider there may initially be little change at C 1 . However, applying excessively high or low voltages at the beginning of the curve can grossly exaggerate the waveform output by the end of the curve. Therefore, in the presently preferred embodiment, only the first 20ns of the resolution of the curve are adjusted. This timing is sufficient to effect the curve without distorting the waveform. In the software, the adjustment of Vapp is an iterative process. The iterative process completes when the adjustments bring the VAnew value above VAend (for the case in which the voltage obtained is lower than the ideal Vapp) or below VAend (for the case in which the voltage obtained is higher than the ideal Vapp) (Step 322). Once an adjusted and a non-adjusted curve are obtained, a comparison is made to determine which curve offers a better fit based on the incoming datapoints, the original prediction or the prediction as adjusted through the iterative process described above (Step 326). The information (a pattern set) describing the better fit (number of resistors to drive high and drive duration) is then saved into an array. Pattern Generation Routine After all datapoints describing the waveform of a particular curve are read and the curve fit function has completed for each change of direction or slope a file is created (the "Expected" file 336) which will contain the time and voltage data computed in the curve fit function. The data written conforms to the resolution of the software driver. The expected file is used as an accuracy check by overlaying a plot of the input time-voltage pairs with a plot of the expected time-voltage pairs. The pattern array result determined by the curve fit function is converted to the voltage value to be applied to the resistor divider at each step of the timing resolution for the given curve (Step 328). The timing value and voltage value are written to the Expected file (Step 330). The voltage value indicates the new voltage to be applied at each step in the timing resolution. Vector data which conforms to the input needed for the particular VLSI tester to be used must now be created. Vector data is determined based on the pattern result of the curve fit routine. In the presently preferred embodiment, the software drives a Multi-Level Tone 3 (mlt3) waveform VLSI digital tester. mlt3 is a waveform used for ethernet interfacing with a computer. In mlt3 testing the waveform used is distorted as though it has travelled through 100 meters of 10/100T cabling. Testing of the DUT takes place to ensure that it can accurately read the signal. This digital tester uses a V-series MZDI circuit which must be programmed on a vector basis. The vector duration for the V-series MZDI is 10ns. Therefore, 2 steps (of 5 ns each) fit into each vector. Programming data for the vector data is based on the current data (number of resistors to drive high) and the previous data (Step 332). A set number is assigned on this basis and saved to a second file (the "Pattern" file 338) (Step 334). The MZDI circuit also requires another file for programming which is constant (does not change despite the input vector sets). The input sets are specific to the test generator used. Software code has also been generated to drive a Polaris VLSI digital tester. Waveform Generation Figure 1 depicts the PAWG circuit. The analog test stimulus is created by the PAWG circuit receiving input from a VLSI digital tester. The Pattern file created by the PAWG software is used as input to a VLSI digital tester. The vectors described in the Pattern file are read by the VLSI digital tester. In turn, the digital tester drives the resistor divider inputs (R 1 -R n ) to the circuit. In the presently preferred embodiment, the resistor divider consists of 8 resistors. A change in the number of resistors of the divider can increase or decrease the voltage resolution of the resulting curve. The software is written to produce vectors for driving an 8 resistor divider. Therefore, any change in the number of resistors used in the resistor divider requires a change in the software. Capacitor C 1 is connected to the output of the resistor divider and tied to ground. The rate of rise or fall in voltage is determined by C 1 (or the RCa constant). Capacitor C 1 impedes a rapid change in voltage to transistor T 1 . Transistor T 1 buffers the RC circuit from the DUT to prevent the input impedance of the DUT from affecting its time constant. R s and C s are used if a secondary, lower frequency slope is desired. A secondary, lower frequency slope is usually employed when generating mlt3 waveforms. In mlt3 waveforms, a transmission line affect known as "base line wander" causes a low frequency triangle wave to be modulated with the high frequency waveform of the data transmission. As a result of this modulation, the center reference line, or base line, of the already distorted high frequency waveform received by the DUT slopes slowly upward then downward. To verify that the DUT can compensate for the base line wander R s and C s are used to cause the base line of the high frequency waveform to slope upward, simulating one half cycle of base line wander. In an alternative embodiment, if simulation of a full cycle of base line wander is desired, then C s would be terminated to a tester driver instead of ground and the driver would be switched from a high voltage to a low voltage, or vise versa, whenever a change in slope is desired. Capacitor C 1 serves to integrate the discrete time inputs (datapoints of initial file and input to resistors of the resistor divider) resulting in a discrete time to continuous time conversion of the simulated waveform. The resulting output of the circuit is an analog output corrected for the resolution of the device under test. Code The following code provides a sample implementation of the disclosed technique. Of course, alternate implementations are well within the abilities of one skilled in the art and this code is therefore presented only as an example of how these functions may be accomplished and is not meant to limit the disclosed technique in scope or embodiment in any way. According to a disclosed class of innovative embodiments, there is provided: a method of generating arbitrary waveforms, comprising the actions of: receiving a set of datapoints which describes a waveform to be generated; generating a set of vectors from said set of datapoints which drives a digital tester unit; and driving said digital tester unit with said set of vectors; whereby said digital test unit drives the resistors of a resistor divider according to said set of vectors to produce a test stimulus substantially similar to said waveform, which is applied to a device under test. According to another disclosed class of innovative embodiments, there is provided: a method for generating arbitrary waveforms, comprising the actions of: receiving a set of datapoints which describes a waveform to be generated; identifying slope or voltage changes in said set of datapoints as endpoints; calculating voltages which will result in said endpoints; determining the number of resistors of a pseudo-arbitrary waveform generator circuit to drive high based on the results from said calculating step; converting the result of said determining step to voltage values to be applied to said resistors; and generating a set of vectors from the result of said converting step which can drive a digital tester unit; whereby said digital test unit drives the resistors of said circuit according to said set of vectors to produce a test stimulus substantially similar to said waveform which is applied to a device under test. According to another disclosed class of innovative embodiments, there is provided: a system for generating arbitrary waveforms, comprising: a set of datapoints which describes a waveform to be generated; a computer system configured to receive said set of datapoints and which generates from said set of datapoints a set of vectors which drives a digital tester unit; a digital tester unit connected to receive said set of vectors; and a circuit comprising a resistor divider, connected to be driven by the output of said digital tester unit and to produce a test stimulus substantially similar to said waveform, which is applied to a device under test. Modifications and Variations As will be recognized by those skilled in the art, the innovative concepts described in the present application can be modified and varied over a tremendous range of applications, and accordingly the scope of patented subject matter is not limited by any of the specific exemplary teachings given, but is only defined by the issued claims. The presently preferred embodiment is described as software capable of driving and a circuit having a resistor divider of 8 resistors. However, the resistor divider can be constructed of a greater or fewer number of resistors and the software can be written accordingly. The presently preferred embodiment is described as software driving the resistors of a resistor divider at 1 volt. However, the voltages determining high and low can be adjusted depending on the type of test stimuli desired. The presently preferred embodiment describes software routines for creating circuit drivers for both V-series and Polaris type test generators. However, the software for both is similar and the code can be easily modified to create driver files for other types of testers which can in turn drive the described circuit. Any VLSI tester that does not include a self-contained high-speed AWG, including such testers as the Teradyne J-97x series can be used with the PAWG described.

Claims: A method of generating arbitrary waveforms, comprising the actions of: receiving a set of datapoints which describes a waveform to be generated; generating a set of vectors from said set of datapoints which drives a digital tester unit; and driving said digital tester unit with said set of vectors; whereby said digital test unit drives the resistors of a resistor divider (R 1 →R n ) according to said set of vectors to produce a test stimulus, substantially similar to said waveform, which is applied to a device under test. The method of claim 1 wherein said set of datapoints is generated by digitizing a desired waveform. The method of claim 1 or claim 2, wherein said set of vectors is dependent on the resolution of said test stimulus. The method of claim 1, claim 2, or claim 3, wherein a capacitor connected to said resistor divider converts the discrete time output of said resistor divider to a continuous time output. A method as claimed in any preceding claim, comprising the actions of: identifying slope or voltage changes in said set of datapoints as endpoints; calculating voltages which will result in said endpoints; determining the number of resistors of a pseudo-arbitrary waveform generator circuit to drive high based on the results from said calculating step; and converting the result of said determining step to voltage values to be applied to said resistors. The method of claim 5 wherein said determining step further comprises the steps of calculating the expected voltage from driving said determined number of resistors high, predicting an expected voltage after a given time, adjusting said number of resistors to drive high based on said predicted expected voltage, adjusting said number of resistors to drive high and repeating said further steps until desired accuracy is achieved. A system for generating arbitrary waveforms, comprising: means for receiving a set of datapoints which describes a waveform to be generated; a computer system configured to receive said set of datapoints and which generates from said set of datapoints a set of vectors which drives a digital tester unit; a digital tester unit connected to receive said set of vectors; and a circuit comprising a resistor divider (R 1 -R n ), connected to be driven by the output of said digital tester unit and to produce a test stimulus, substantially similar to said waveform, which is applied to a device under test. The system of claim 7 wherein a capacitor connected to said resistor divider converts the discrete time output of said resistor divider to a continuous time output.

Inventors: COLBY DAVID D, COLBY, DAVID D.
Applicants: TEXAS INSTRUMENTS INC, TEXAS INSTRUMENTS INCORPORATED
Application year: 1999
Main classification: G01R31
IPC codes: G01R31