METHOD AND APPARATUS FOR TRUNKING MULTIPLE PORTS IN A NETWORK SWITCH

Abstract: A network switch configured for switching data packets across multiple ports uses an address table to generate frame forwarding information. A decision-making engine checks the frame forwarding information to determine whether the frame is to be forwarded on a port that is part of a trunk. When the frame is to be output on a trunk port, the decision-making engine determines the port on which to transmit the frame.

Description: METHOD AND APPARATUS FOR TRUNKING MULTIPLE PORTS IN A NETWORK SWITCH TECHNICAL FIELD The present invention relates to network communications and more particularly, to trunking multiple ports in a network switch to provide high speed network links. BACKGROUND ART In computer networks, a plurality of network stations are interconnected via a communications medium. For example, Ethernet is a commonly used local area network scheme in which multiple stations are connected to a single shared serial data path. These stations often communicate with a switch located between the shared data path and the stations connected to that path. Typically, the switch controls the communication of data packets on the network. The network switch includes switching logic for receiving and forwarding frames to the appropriate destinations. One arrangement for generating a frame forwarding decision uses a direct addressing scheme, where the network switch includes a fixed address table storing switching logic for the destination addresses. For example, a frame may be received by the network switch with header information indicating the source address and destination address of the frame. The switching logic searches the fixed address table using the source address and destination address as lookups to find the appropriate frame forwarding information. The switch uses this information and sends the frame to the appropriate port(s). When all of the stations connected to the network are simultaneously operating, packet traffic on the shared serial path can be heavy with little time between packets. Additionally, due to network throughput requirements, increasing the speed with which data is transmitted to its destination is becoming increasingly important. One arrangement for increasing the speed with which data is transmitted between stations uses "trunking", also referred to as link aggregation, to combine a number of links to form a trunk between two stations. For example, suppose two individual ports on the switch are each configured to support 100 Mb/s data transmission rates. The trunking scheme links the two -- ports together and transmits/receives data via these two ports, resulting in one 200 Mb/s link between the two stations. A drawback with such a trunking scheme is that the address table must store the appropriate trunking information, including the particular trunk port on which to transmit the data. That is, the address table must store information indicating whether a particular port is part of a trunk, in addition to storing information indicating which port of the trunk on which to transmit the data when the data forwarding information indicates that the output port is part of a trunk. Storing this trunking information in the address table significantly increases the physical size of the address table and also significantly increases the complexity of the switching logic, thereby increasing the time spent searching for the frame forwarding information. Additionally, when changes to the stored trunking information are required, e.g., when the network configuration is changed, the address table must be correspondingly changed to reflect the new trunking configuration. This process of reconfiguring the address table is time-consuming and costly, potentially resulting in network downtime. SUMMARY OF THE -INVENTION There exists a need for a switching device that supports trunking without storing trunking information in an address table. There is also a need for a switching device that supports trunking and enables trunking changes to be made without reprogramming an address table. These and other needs are met by the present invention, where a multiport switch includes an address table that stores address entries used by a decision making engine to make frame forwarding decisions. The decision making engine includes a trunking function whereby the frame forwarding information is checked to determine whether the frame is to be transmitted via an output port that is part of a trunk. When the output port is part of a trunk, the decision making engine performs a trunk mapping function to determine the particular port on which to transmit the frame. According to one aspect of the invention, a network switch is configured to control the communication of data frames between stations and to support trunking. The switch includes a table for storing address information and data forwarding information. The switch also includes a decision making engine configured to search the table and generate data forwarding information for a data frame. The decision making engine is also configured to determine whether the data frame is to be transmitted through a port that is a part of a trunk and when the port is part of a trunk, to determine the forwarding port on which to transmit the data frame. Another aspect of the present invention provides a method for generating data forwarding information in a multiport switch that controls communication of data frames between stations. The method includes receiving information from a data frame and searching an address table for data forwarding information based on the received information. The method also includes determining whether the data frame is to be transmitted through a port that is part of a trunk. The method further includes generating, when the frame is to be transmitted through a port that is part of a trunk, a value representing a forwarding port on which to transmit the data frame. Other advantages and features of the present invention will become readily apparent to those skilled in this art from the following detailed description. The embodiments shown and described provide illustration of the best mode contemplated for carrying out the invention. The invention is capable of modifications in various obvious respects, all without departing from the invention. Accordingly, the drawings are to be regarded as illustrative in nature, and not as restrictive. BRIEF DESCRIPTION OF THE DRAWINGS Figure 1 is a block diagram of a packet switched network including a multiple port switch according to an embodiment of the present invention. Figure 2 is a block diagram of the multiple port switch of Figure 1. Figure 3 is a detailed block diagram illustrating the switching subsystem of Figure 2. Figure 4 is a block diagram of a system including the internal rules checker of Figure 2 in accordance with an embodiment of the present invention. Figure 5 illustrates the composition of the IRC address table of Figure 4. Figure 6 illustrates the format of an IRC address table entry of the IRC address table of Figure 5. Figure 7 illustrates linked list chains for identifying table entries relative to a selected bin. Figure 8 illustrates a hash function circuit used with the internal rules checker of Figure 2. Figure 9 illustrates the composition of the forwarding descriptor in accordance with an embodiment of the present invention. Figure 10 illustrates trunk membership combinations according to an embodiment of the present invention. Figure 11 is a flow diagram illustrating a method of generating frame forwarding information in connection with trunking according to an embodiment of the present invention. Figure 12 is a diagram illustrating trunk mapping logic according to an embodiment of the present invention. BEST MODE FOR CARRYING OUT THE INVENTION The present invention will be described with the example of a switch in a packet switched network, such as an Ethernet (IEEE 802.3) network. It will become apparent, however, that the present invention is also applicable to other packet switched systems, as described in detail below, as well as to other types of systems in general. Switch Architecture Overview Figure 1 is a block diagram of an exemplary system in which the present invention may be advantageously employed. The exemplary system 10 is a packet switched network, such as an Ethernet (IEEE 802.3) network. The packet switched network includes integrated multiport switches (IMS) 12 that enable communication of data packets between network stations. The network may include network stations having different configurations, for example twelve (12) 10 megabit per second (Mb/s) or 100 Mb/s network stations 14 (hereinafter 10/100 Mb/s) that send and receive data at a network data rate of 10 Mb/s or 100 Mb/s, and a 1000 Mb/s (i.e., 1 Gb/s) network node 22 that sends and receives data packets at a network speed of 1 Gb/s. The gigabit node 22 may be a server, or a gateway to a high-speed backbone network. Hence, the multiport switches 12 selectively forward data packets received from the network nodes 14 or 22 to the appropriate destination based upon Ethernet protocol. Each multiport switch 12 includes a media access control (MAC) module 20 that transmits and receives data packets to and from 10/100 Mb/s physical layer (PHY) transceivers 16 via respective reduced media independent interfaces (RMII) 18 according to IEEE 802.3u protocol. Each multiport switch 12 also includes a gigabit MAC 24 for sending and receiving data packets to and from a gigabit PHY 26 for transmission to the gigabit node 22 via a high speed network medium 28. Each 10/100 Mb/s network station 14 sends and receives data packets to and from the corresponding multiport switch 12 via a media 17 and according to either half-duplex or full duplex Ethernet protocol. The Ethernet protocol ISO/IEC 8802-3 (ANSI/IEEE Std. 802.3, 1993 Ed.) defines a half-duplex media access mechanism that permits all stations 14 to access the network channel with equality. Traffic in a half-duplex environment is not distinguished over the medium 17. Rather, each half-duplex station 14 includes an Ethernet interface card that uses carrier-sense multiple access with collision detection (CSMA/CD) to listen for traffic on the media. The absence of network traffic is detected by sensing deassertion of a receive carrier on the media. Any station 14 having data to send will attempt to access the channel by waiting a predetermined time, known as the interpacket gap interval (IPG), after deassertion of the receive carrier on the media. If a plurality of stations 14 have data to send on the network, each of the stations will attempt to transmit in response to the sensed deassertion of the receive carrier on the media and after the IPG interval, possibly resulting in a collision. Hence, the transmitting station will monitor the media to determine if there has been a collision due to another station sending data at the same time. If a collision is detected, both stations stop, wait a random amount of time, and retry transmission. The 10/100 Mb/s network stations 14 that operate in full duplex mode send and receive data packets according to the Ethernet standard IEEE 802.3u. The full-duplex environment provides a two-way, point-to-point communication link enabling simultaneous transmission and reception of data packets between each link partner, i.e., the 10/100 Mb/s network station 14 and the corresponding multiport switch 12. Each multiport switch 12 is coupled to 10/100 physical layer (PHY) transceivers 16 configured for sending and receiving data packets to and from the corresponding multiport switch 12 across a corresponding reduced media independent interface (RMII) 18. In particular, each 10/100 PHY transceiver 16 is configured for sending and receiving data packets between the multiport switch 12 and up to four (4) network stations 14 via the RMII 18. A magnetic transformer 19 provides AC coupling between the PHY transceiver 16 and the corresponding network medium 17. Hence, the RMII 18 operates at a data rate sufficient to enable simultaneous transmission and reception of data packets by each of the network stations 14 to the corresponding PHY transceiver 16. Each multiport switch 12 also includes an expansion port 30 for transferring data between other switches according to a prescribed protocol. Each expansion port 30 enables multiple multiport switches 12 to be cascaded together as a separate backbone network. Figure 2 is a block diagram of the multiport switch 12. The multiport switch 12 contains a decision making engine 40 that performs frame forwarding decisions, a switching subsystem 42 for transferring frame data according to the frame forwarding decisions, an external memory interface 44, management information base (MIB) counters 48a and 48b (collectively 48), and MAC (media access control) protocol interfaces 20 and 24 to support the routing of data packets between the Ethernet (IEEE 802.3) ports serving the network stations 14 and the gigabit node 22. The MIB counters 48 provide statistical network information in the form of management information base (MIB) objects, to an external management entity controlled by a host CPU 32, described below. The external memory interface 44 enables external storage of packet data in an external memory 36 such as, for example, a synchronous static random access memory (SSR-AM), in order to minimize the chip size of the multiport switch 12. In particular, the multiport switch 12 uses the external memory 36 for storage of received frame data and memory structures. The external memory 36 is preferably either a Joint Electron Device Engineering Council (JEDEC) pipelined burst or Zero Bus Turnaround™ (ZBT)-SSRAM having a 64-bit wide data path and a 17-bit wide address path. The external memory 36 is addressable as upper and lower banks of 128K in 64-bit words. The size of the external memory 36 is preferably at least 1 Mbytes, with data transfers possible on every clock cycle through pipelining. Additionally the external memory interface clock operates at clock frequencies of at least 66 MHz, and, preferably, 100 MHz and above. The multiport switch 12 also includes a processing interface 50 that enables an external management entity such as a host CPU 32 to control overall operations of the multiport switch 12. In particular, the processing interface 50 decodes CPU accesses within a prescribed register access space, and reads and writes configuration and status values to and from configuration and status registers 52. The internal decision making engine 40, referred to as an internal rales checker (IRC), makes frame forwarding decisions for data packets received. The multiport switch 12 also includes an LED interface 54 that clocks out the status of conditions per port and drives an external LED logic. The external LED logic drives LED display elements that are human readable. The switching subsystem 42, configured for implementing the frame forwarding decisions of the IRC 40, includes a port vector first in first out (FIFO) buffer 56, a plurality of output queues 58, a multicopy queue 60, a multicopy cache 62, a free buffer queue 64, and a reclaim queue 66. The MAC unit 20 includes modules for each port, each module including a MAC receive portion, a receive FIFO buffer, a transmit FIFO buffer, and a MAC transmit portion. Data packets from a network station 14 are received by the corresponding MAC port and stored in the corresponding receive FIFO. The MAC unit 20 obtains a free buffer location (i.e., a frame pointer) from the free buffer queue 64, and outputs the received data packet from the corresponding receive FIFO to the external memory interface 44 for storage in the external memory 36 at the location specified by the frame pointer. The ER-C 40 monitors (i.e., "snoops") the data bus to determine the frame pointer value and the header information of the received packet (including source, destination, and VLAN address information). The IRC 40 uses the header information to determine which MAC ports will output the data frame stored at the location specified by the frame pointer. The decision making engine (i.e., the IRC 40) may thus determine that a given data frame should be output by either a single port, multiple ports, all ports (i.e., broadcast) or no ports (i.e., discarded). For example, each data frame includes a header having source and destination address, where the decision making engine 40 may identify the appropriate output MAC port based upon the destination address. Alternatively, the destination address may correspond to a virtual address that the appropriate decision making engine identifies as corresponding to a plurality of network stations. In addition, the frame may include a VLAN tag header that identifies the frame as information destined to one or more members of a prescribed group of stations. The IRC 40 may also determine that the received data packet should be transferred to another multiport switch 12 via the expansion port 30. Hence, the internal rules checker 40 will decide whether a frame temporarily stored in the external memory 36 should be output to a single MAC port or multiple MAC ports. The internal rules checker 40 outputs a forwarding decision to the switch subsystem 42 in the form of a forwarding descriptor. The forwarding descriptor includes a priority class identifying whether the frame is high priority or low priority, a port vector identifying each MAC port that should transmit the data frame, receive port number, an untagged set, VLAN information, vector identifying each MAC port that should include VLAN information during transmission, opcode, and frame pointer. The format of the forwarding descriptor will discussed further with respect to Figure 9. The port vector identifies the MAC ports to receive the data frame for transmission (e.g., 10/100 MAC ports 1-12, Gigabit MAC port, and/or Expansion port). The port vector FIFO 56 decodes the forwarding descriptor including the port vector, and supplies the frame pointer to the appropriate output queues 58 that correspond to the output MAC ports to receive the data frame transmission. In other words, the port vector FIFO 56 supplies the frame pointer on a per-port basis. The output queues 58 give the frame pointer to a dequeuing block 76 (shown in Fig. 3) which fetches the data frame identified in the port vector from the external memory 36 via the external memory interface 44, and supply the retrieved data frame to the appropriate transmit FIFO of the identified ports. If a data frame is to be supplied to a management agent, the frame pointer is also supplied to a management queue 68, which can be processed by the host CPU 32 via the CPU interface 50. The multicopy queue 60 and the multicopy cache 62 keep track of the number of copies of the data frame that are transmitted from the respective ports, ensuring that the data frame is not overwritten in the external memory 36 until the appropriate number of copies of the data frame have been output from the external memory 36. Once the number of copies output corresponds to the number of ports specified in the port vector FIFO 56, the frame pointer is forwarded to the reclaim queue 66. The reclaim queue 66 stores frame pointers that need to be reclaimed and walks the linked list chain to return the buffers to the free buffer queue 64 as free pointers. After being returned to the free buffer queue 64, the frame pointer is available for reuse by the MAC unit 20 or the gigabit MAC unit 24. Figure 3 depicts the switch subsystem 42 of Figure 2 in more detail according to an exemplary embodiment of the present invention. Other elements of the multiport switch 12 of Figure 2 are reproduced in Figure 3 to illustrate the connections of the switch subsystem 42 to these other elements. As shown in Figure 3, the MAC module 20 includes a receive portion 20a and a transmit portion 24b. The receive portion 20a and the transmit portion 24b each include 12 MAC modules (only two of each shown and referenced by numerals 70a, 70b, 70c, and 70d) configured for performing the corresponding receive or transmit function according to IEEE 802.3 protocol. The MAC modules 70c and 70d perform the transmit MAC operations for the 10/100 Mb/s switch ports complementary to modules 70a and 70b, respectively. The gigabit MAC port 24 also includes a receive portion 24a and a transmit portion 24b, while the expansion port 30 similarly includes a receive portion 30a and a transmit portion 30b. The gigabit MAC port 24 and the expansion port 30 also have receive MAC modules 72a and 72b optimized for the respective ports. The transmit portions 24b and 30b of the gigabit MAC port 24 and the expansion port 30a also have transmit MAC modules 72c and 72d, respectively. The MAC modules are configured for full-duplex operation on the corresponding port, and the gigabit MAC modules 72a and 72c are configured in accordance with the Gigabit Proposed Standard IEEE Draft P802.3z. Each of the receive MAC modules 70a, 70b, 72a, and 72b include queuing logic 74 for transfer of received data from the corresponding internal receive FIFO to the external memory 36 and the rules checker 40. Each of the transmit MAC modules 70c, 70d, 72c, and 72d includes a dequeuing logic 76 for transferring data from the external memory 36 to the corresponding internal transmit FIFO, and a queuing logic 74 for fetching frame pointers from the free buffer queue 64. The queuing logic 74 uses the fetched frame pointers to store receive data to the external memory 36 via the external memory interface controller 44. The frame buffer pointer specifies the location in the external memory 36 where the received data frame will be stored by the receive FIFO. The external memory interface 44 includes a scheduler 80 for controlling memory access by the queuing logic 74 or dequeuing logic 76 of any switch port to the external memory 36, and an SSRAM interface 78 for performing the read and write operations with the external memory 36. In particular, the multiport switch 12 is configured to operate as a non-blocking switch, where network data is received and output from the switch ports at the respective wire rates of 10, 100, or 1000 Mb/s. Hence, the scheduler 80 controls the access by different ports to optimize usage of the bandwidth of the external memory 36. Each receive MAC stores a portion of a frame in an internal FIFO upon reception from the corresponding switch port; the size of the FIFO is sufficient to store the frame data that arrives between scheduler time slots. The corresponding queuing logic 74 obtains a frame pointer and sends a write request to the external memory interface 44. The scheduler 80 schedules the write request with other write requests from the queuing logic 74 or any read requests from the dequeuing logic 76, and generates a grant for the requesting queuing logic 74 (or the dequeuing logic 76) to initiate a transfer at the scheduled event (i.e., slot). Sixty-four bits of frame data is then transferred over a write data bus 69a from the receive FIFO to the external memory 36 in a direct memory access (DMA) transaction during the assigned slot. The frame data is stored in the location pointed to by the buffer pointer obtained from the free buffer pool 64, although a number of other buffers may be used to store data frames, as will be described. The rules checker 40 also receives the frame pointer and the header information (including source address, destination address, VLAN tag information, etc.) by monitoring (i.e., snooping) the DMA write transfer on the write data bus 69a. The rules checker 40 uses the header information to make the forwarding decision and generate a forwarding instruction in the form of a forwarding descriptor that includes a port vector. The port vector has a bit set for each output port to which the frame should be forwarded. If the received frame is a unicopy frame, only one bit is set in the port vector generated by the rules checker 40. The single bit that is set in the port vector corresponds to a particular one of the ports. The rules checker 40 outputs the forwarding descriptor including the port vector and the frame pointer into the port vector FIFO 56. The port vector is examined by the port vector FIFO 56 to determine which particular output queue should receive the associated frame pointer. The port vector FIFO 56 places the frame pointer into the top of the appropriate queue 58 and/or 68. This queues the transmission of the frame. As shown in Figure 3, each of the transmit MAC units 70c, 70d, 72d, and 72c has an associated output queue 58a, 58b, 58c, and 58d, respectively. In preferred embodiments, each of the output queues 58 has a high priority queue for high priority frames, and a low priority queue for low priority frames. The high priority frames are used for frames that require a guaranteed access latency, e.g., frames for multimedia applications or management MAC frames. The frame pointers stored in the FIFO-type output queues 58 are processed by the dequeuing logic 76 for the respective transmit MAC units. At some point in time, the frame pointer reaches the bottom of an output queue 58, for example, output queue 58d for the gigabit transmit MAC 72c. The dequeuing logic 76 for the transmit gigabit port 24b takes the frame pointer from the corresponding gigabit port output queue 58d, and issues a request to the scheduler 80 to read the frame data from the external memory 36 at the memory location specified by the frame pointer. The scheduler 80 schedules the request, and issues a grant for the dequeuing logic 76 of the transmit gigabit port 24b to initiate a DMA read. In response to the grant, the dequeuing logic 76 reads the frame data (along the read bus 69b) in a DMA transaction from the location in external memory 36 pointed to by the frame pointer, and stores the frame data in the internal transmit FTFO for transmission by the transmit gigabit MAC 72c. If the forwarding descriptor specifies a unicopy transmission, the frame pointer is returned to the free buffer queue 64 following writing the entire frame data into the transmit FIFO. A multicopy transmission is similar to the unicopy transmission, except that the port vector has multiple bits set, designating the multiple ports from which the data frame will be transmitted. The frame pointer is placed into each of the appropriate output queues 58 and transmitted by the appropriate transmit MAC units 20b, 24b, and or 30b. The free buffer pool 64, the multicopy queue 60, the reclaim queue 66, and the multicopy cache 62 are used to manage use of frame pointers and re-use of frame pointers once the data frame has been transmitted to its designated output port(s). In particular, the dequeuing logic 76 passes frame pointers for unicopy frames to the free buffer queue 64 after the buffer contents have been copied to the appropriate transmit FIFO. For multicopy frames, the port vector FIFO 56 supplies multiple copies of the same frame pointer to more than one output queue 58, each frame pointer having a unicopy bit set to zero. The port vector FIFO 56 also copies the frame pointer and the copy count to the multicopy queue 60. The multicopy queue 60 writes the copy count to the multicopy cache 62. The multicopy cache 62 is a random access memory having a single copy count for each buffer in external memory 36 (i.e., each frame pointer). Once the dequeuing logic 76 retrieves the frame data for a particular output port based on a fetched frame pointer and stores the frame data in the transmit FIFO, the dequeuing logic 76 checks if the unicopy bit is set to 1. If the unicopy bit is set to 1, the frame pointer is returned to the free buffer queue 64. If the unicopy bit is set to zero indicating a multicopy frame pointer, the dequeuing logic 76 writes the frame pointer with a copy count of minus one (-1) to the multicopy queue 60. The multicopy queue 60 adds the copy count to the entry stored in the multicopy cache 62. When the copy count in multicopy cache 62 for the frame pointer reaches zero, the frame pointer is passed to the reclaim queue 66. Since a plurality of frame pointers may be used to store a single data frame in multiple buffer memory locations, the frame pointers are referenced to each other to form a linked-list (i.e., chain) of frame pointers to identify the stored data frame in its entirety. The reclaim queue 66 traverses the chain of buffer locations identified by the frame pointers, and passes the frame pointers to the free buffer queue 64. The foregoing description of the switch architecture provides an overview of the switch operations in a packet switched network. A more detailed description of the features of the present invention as embodied in the multiport switch 12 are described below. INTERNAL RULES CHECKER The present invention is directed to providing a trunking function in a network switch and more particularly to trunking multiple ports to form a single network link. A description will first be given of the IRC 40, followed by the detailed description of the method and apparatus for trunking in the multiport switch 12. As described previously, the switch subsystem 42 provides the switching logic for receiving and forwarding frames to the appropriate output ports. The forwarding decisions, however, are made by the IRC 40 located on the multiport switch 12. According to an embodiment of the invention illustrated in Figure 4, the IRC 40 includes four functional logic blocks, an ingress rules engine 200, a source address (SA) lookup engine 210, a destination address (DA) lookup engine 220 and an egress rules engine 230. In the exemplary embodiment, the four engines 200, 210, 220 and 230 are shown as separate logic devices. However, in alternative configurations, these engines may be combined into a single logic device. In the exemplary embodiment illustrated in Figure 4, the IRC 40 includes address table 82. In alternative embodiments, the address table 82 may be located outside the IRC 40 within another part of the multiport switch 12 or even external to the multiport switch 12. According to the exemplary embodiment, the address table 82 supports 4096 user addresses and capabilities for 64 unique virtual local area networks (VLANs). However, the number of addresses and VLANs supported may be increased by expanding the table size. VLANs provide "broadcast domains" whereby broadcast traffic is kept "inside" the VLAN. For example, a specific VLAN may contain a group of users at a high level of an organization. When sending data to this group of users, the data may include a specific VLAN identifier associated with this particular group to ensure that only these users receive the data. These VLAN groupings can be thought of as "sub-networks" within a larger network. Figure 5 illustrates the organization of the IRC address table 82. The IRC address table 82 contains an array of 4096 entries. The first "n" entries 92 are referred to as "bin entries" and have addresses from "0" to "n-1". The remaining entries 94 are referred to as "heap entries" and have addresses from "n" to "4095". Each of the table entries includes a 72-bit address entry field and a 12-bit "next pointer" field. Figure 6 illustrates the composition of each 84-bit table entry shown in Figure 5. The hit bit is used for address entry "aging" to delete entries from the address table 82 that have not been used in a predetermined amount of time. The static bit is used to prevent deletion of an address entry. The traffic capture bit identifies traffic capture source and destination MAC addresses for mirroring MAC conversations to the management queue 68. The VL-AN index field is a 6-bit field used to reference a 12-bit VLAN identifier (ID). The VLAN index-to- VLAN ID table 86, shown in Figure 4, contains the mapping associations. The switch 12 receives both tagged and untagged frames. When the switch 12 receives untagged data frames, i.e., without VLAN tag information, the IRC 40 assigns a VLAN index from the VLAN port-to-index table 88, shown in Figure 4, based on the receive port on which the frame is received. The VLAN index-to- ID table 86 and the VLAN port-to-index table 88 are located with the configuration and status registers 52. However, in alternative configurations, the tables 86 and 88 may be located within the IRC 40. The port vector is a 15-bit field that provides a forwarding descriptor with a vector identifying the port(s) to which the frame should be forwarded. The MAC address field is a 48-bit field that includes addresses for both source addresses and destination addresses. The addresses can be unicast, multicast or broadcast. An individual/group (I/G) bit is also included in the MAC address field. In the exemplary embodiment of the present invention, the host CPU 32 functions as the management entity and is connected to the IRC 40 via the CPU IF 50. Alternatively, a management MAC may be connected to the CPU IF 50 to function as the management entity. The host CPU 32 is responsible for initializing the values in the address table 82. Upon power- up, the host CPU 32 loads values into the address table 82 based on the network configuration, including VLAN configurations. The IRC 40 uses the specific fields of the address table 82 to make frame forwarding decisions when frames are received in the switch 12. More specifically, the IRC 40 uses engines 200-230 to search the address table 82 for frame forwarding information and creates a forwarding descriptor for output to the port vector FIFO 56. As discussed previously, engines 200-230 are separate logic engines and therefore are able to process data frames independently, thereby increasing data throughput as compared to systems which process a single frame at a time. In other words, each logic engine is able to perform its respective processing on a different data frame simultaneously with the other respective logic engines. The operation of each logic engine will be described briefly below. The ingress rules engine 200 performs a variety of pre-processing functions for incoming data frames. For example, ingress rules engine 200 checks to see if the corresponding MAC detected any transmission errors when the frame was received. The ingress rules engine 200 also checks the source address of the received frame to determine whether the Individual/Group (I/G) bit is set. If the I/G bit is set, the ingress rules engine 200 handles the frame as if the frame was received with errors. That is, when a received error has occurred, the ingress rules engine 200 creates a forwarding descriptor with a null port vector that causes the frame to be discarded. Alternatively, the ingress mles engine 200 may forward the error frame to the host CPU 32 for diagnostic purposes. The ingress mles engine 200 also checks the MAC DA of the frame to determine if the frame should be sent to the management entity, e.g., host CPU 32. Specifically, the ingress mles engine 200 looks for Bridge Protocol Data Units (BPDUs), Generic Attribute Registrations Protocol (GA-RP) frames, MAC Control Frames and Physical MAC Addresses. The ingress mles engine 200 identifies these types of frames based on their specific destination address information. Optionally, the ingress mles engine 200 performs VLAN ingress filtering to prevent the multiport switch 12 from forwarding a frame that does not belong to a VLAN associated with the receiving port. The ingress mles engine 200 accesses a VL-AN member set table, which indicates which VLANs are associated with each port, and determines whether a particular frame belongs to a VLAN associated with the receiving port. When a frame fails the ingress filtering, the ingress mles engine 200 generates a forwarding descriptor with a null port vector, without performing SA or DA lookups, or egress mles operations. After processing by ingress mles engine 200, the IRC 40 performs SA and DA searches of address table 82. The multiport switch 12 needs to make frame forwarding decisions relatively quickly, since multiple data frames may be received by the multiport switch 12 simultaneously. Hence, in the exemplary embodiment of the present mvention, a hashing scheme is used to search only a subset of the address entries, as described below. The memory structure of Figure 5 provides an indexed arrangement, where a given network address will be assigned to a corresponding bin. In other words, each bin entry 96 is configured to reference a plurality of table entries (i.e., heap entries) 98. Hence, the SA lookup engine 210 performs a search of the address table 82 by first accessing a specific bin 96 pointed to by a hash key, and then searching the entries within (i.e., referenced by) the corresponding bin to locate the appropriate match. Each bin entry 96 is the starting point for the search by the SA lookup engine 210 for a particular address within the address table 82. A bin entry may reference no addresses (i.e., be empty), may reference only one address within the bin entry location, or may reference a plurality of addresses using a linked list chain structure. Figure 7 is a diagram illustrating bin entries referencing a different number of table entries. Each of the bin entries 96 and heap entries 98 includes the 72-bit address entry and a 12-bit "next pointer" field. The "next pointer" field associated with the bin entry 96 identifies the location of the next entry in the chain of linked list addresses. For example, Bin 3, 96d, of Figure 7 does not have any associated table entries. In such a case, the contents of the 72-bit address entry are immaterial and the bin's corresponding "next pointer" field will have a value of "1", indicating no entries for the corresponding bin. If a bin such as Bin 1, 96b, contains a single table entry, the bin entry will store the switching logic data for that single address in its address entry field, and store the value "zero" in the "next pointer" field, indicating there are no further address entries in the chain. Bin 0, 96a, however, references four addresses by using the "next pointer" field to identify the location of the next entry in the chain. The additional entries 96b-96d in the bin are linked in a linear list, as shown in Figure 7. Thus, the first entry of Bin 0 is stored in the address entry field of the bin entry 96a and the next entry (heap entry 98a) is referenced by address entry "a" in the next pointer field of the bin entry 96a. The SA lookup engine 210 performs hash searches of the IRC address table 82 to find entries associated with the source address and VLAN index of a received data frame. Figure 8 is a block diagram illustrating an exemplary hash function circuit 100 used in conjunction with the SA lookup engine 210 in accordance with an embodiment of the present invention. The hash function circuit 100 includes a series of AND gates 102, a series of exclusive OR (XOR) gates 104, and a shift register 106. A user-specified hash function, stored in a user-programmable register (HASHPOLY) 108, includes a 12-bit value defining the hash polynomial used by the hash function circuit 100. Exemplary hash polynomials for the hashing function of the present invention are x + x + x + x + x" + l, which has a HASHPOLY of 0100 1000 1101, x 12 + x 10 + x 5 + x 3 +1, which has a HASHPOLY of 0100 0010 1001 and x 12 + x 10 + x 8 + x 7 + x 4 + x 2 +1, which has a HASHPOLY of 0101 1001 0101. The x 12 term is assumed to always equal "1", and therefore is not stored in the HASHPOLY register 108. Other polynomials may also be used for HASHPOLY based on the particular design requirements. The hash function circuit 100 generates the hash key using the source address of the data packet according to a user-specified hash function. Initially, the IRC controller 82 concatenates the 16 least significant bits of the source address of the data packet with the VLAN index to create a search key. After the entire search key has been processed, the hash function circuit 100 outputs a 12-bit hash key. From the 12-bit hash key, the SA lookup engine 210 calculates a bin number for searching the appropriate bin list in address table 82. More particularly, the SA lookup engine 210 uses the lower POL YEN bits of the hash key to generate the bin number. The bin number falls in the range of [0, n-1] where n = 2 POLYEN and the value of POL YEN is programmed by the host CPU 32 and stored in register 110. The hash key output by the hash function circuit 100 is provided to a logic circuit, for example a 12-bit parallel AND gate 111, that selectively outputs the lower significant bits of the hash key based upon a polynomial enable value (POL YEN) stored in register 210. The field "POL YEN" defines how many bits of the hash key are used to create the bin number. For example, if POL YEN = 5, then the SA lookup engine 210 uses the lower five bits of the hash key. Hence, the hash key output by the logic circuit 100 is based upon masking the 12-bit hash key using the stored register value POL YEN in register 110. After the bin number is calculated, the SA lookup engine 210 searches the bin list of the particular bin for an address entry whose address and VLAN index match the source address (SA) and VLAN index of the received frame. If the SA lookup engine 210 finds an address entry whose address and VLAN index match the SA and VLAN index of the frame, the SA lookup engine 210 sets the hit bit for that address entry. If the SA lookup engine 210 does not find a match and "learning", i.e., adding new entries to the address table 82, is enabled, the SA lookup engine 210 constructs a new entry in the IRC address table 82 using the information from the received frame. After the SA lookup engine 210 completes the search and adds a new entry, if necessary, the DA lookup engine 220 searches the address table 82 for an address entry whose address and VLAN index match the destination address (DA) and VLAN index of the frame. The DA lookup engine 220 uses the 12-bit hash function circuit 100, illustrated in Figure 8, to generate a 12-bit hash key. The DA lookup engine 220 generates the hash key in a similar manner as discussed for the SA lookup engine 210, with the difference being that the hash function circuit 100 uses the destination address information to generate the search key and hash key. The DA lookup engine 220 then uses the lower POL YEN bits of the hash key to calculate the bin number in the address table 82. The DA lookup engine 220 then searches the appropriate bin list for a DA/VLAN index match in the address table 82. If a match is found, the DA lookup engine 220 uses the port vector field of the address entry and passes the port vector field information to the egress mles engine 230. When the DA lookup engine 220 cannot find a DA/VLAN index match, the frame must be "flooded" to all members of the VLAN. In this case, the DA lookup engine 220 sets the port vector to indicate that all ports are to transmit the frame. After the DA lookup engine 220 generates the port vector, the egress mles engine 230 receives the port vector information along with the receive port number and VLAN ID information. The egress mles engine 230 then creates a forwarding descriptor for the frame. Figure 9 illustrates the composition of the forwarding descriptor according to an embodiment of the present invention. Referring to Figure 9, the priority class field is a one-bit field that indicates the output priority queue in which the frame pointer should be placed, e.g., high priority or low priority. The port vector field is a 15 -bit field that identifies each port(s) that should receive the data frame for transmission to its destination address. Bit 0 of the port vector field corresponds to Port 0 (the management port), bits 1-12 correspond to MAC ports 1-12 respectively (the 10/100 Mb/s ports), bit 13 corresponds to the gigabit port 24 and bit 14 corresponds to the expansion port 30. The untagged set field is a four-bit field that indicates which ports should remove VLAN tag headers before transmitting frames. The untagged set is obtained from an untagged set table. The Rx port is a four-bit field that indicates the port from which the frame was received. The VLAN ID field is a 12-bit field that includes the VLAN identifier associated with the frame. The opcode is an 11-bit field that contains instructions about how the frame should be modified before transmission and information that the host CPU 32 can use for processing frames from the management queue. The frame pointer is a 13-bit field that contains the location of the frame stored in external memory 36. Once the necessary forwarding information has been obtained, the egress mles engine 230 outputs the forwarding descriptor to the port vector FIFO 56 for queuing, as shown in Figure 3. TRUNKING FUNCTION As discussed previously, the multiport switch 12 includes twelve ports that are enabled for 10/100 Mb/s operation. Trunking is a technique which treats two or more point-to-point connections between the same two devices as a single network link. Trunking enables the multiport switch 12 to obtain a higher bandwidth path between two devices, e.g., two network stations, two switches or a server and a switch, by linking multiple ports to form a tmnk transmission path between the two end devices. For example, suppose four ports on the multiport switch 12 are designed for 100 Mb/s data transmission rates and the trunking scheme links the four ports together to form a single tmnk. The resulting tmnk is able to transmit/receive data via these four ports, resulting in one 400 Mb/s link between the two end devices. According to an exemplary embodiment of the invention, the multiport switch 12 supports up to three independent tmnks, each of which is able to support two to four ports. In the exemplary embodiment, the twelve 10/100 Mb/s ports on the multiport switch 12 are divided into three trunk blocks, as shown in Figure 10. Referring to Figure 10, the first trunk block, tmnk 1, includes ports 1-4, the second trunk block, tmnk 2, includes ports 5-8 and the third tmnk block, trunk 3, includes ports 9-12. Within a tmnk block, any two to four adjacent ports may be combined into a single tmnk. Figure 10 illustrates the trunk membership combinations for the twelve 10/100 Mb/s ports according to the exemplary embodiment of the invention. In Figure 10, a "T" indicates that the port is included in a trunk and a "-" indicates that the port is not included in a trunk and can therefore be used as an independent port. As discussed above in the exemplary embodiment, any two to four adjacent ports may be combined to form a single tmnk. For example, with reference to Figure 10, ports 1 and 2 can be combined to form a two-link tmnk illustrated at entry A. However, ports 1 and 3 cannot be combined to form a two-link tmnk because they are not adjacent to each other. In alternative embodiments, the multiport switch 12 may include fewer ports in a single tmnk block or more ports, up to the maximum number of ports of the multiport switch 12. Additionally, in alternative embodiments, the multiport switch 12 may be configured without limitation as to which ports are capable of being linked together. For example, ports 1, 3, 5, 7 and 9 could be combined in a five- link tmnk. The host CPU 32 sets the particular trunk configuration based on the particular network requirements, e.g., which end devices require a data link having a bandwidth greater than 100 Mb/s. Initially, the host CPU 32 assigns ports to specific tmnks by setting tmnk control bits in the respective port IRC control register 114a-l, illustrated in Figure 4. According to the exemplary embodiment of the invention, the multiport switch 12 includes one port IRC control register 114 for each of the twelve 10/100 Mb/s ports. In alternative configurations, a single register could be used to store the appropriate control information for the twelve 10/100 Mb/s ports. Referring to Figure 4, each port IRC control register 114 includes two tmnk control bits: a tmnk bit and a tmnk_act bit. A set tmnk bit indicates that the corresponding port is a member of the tmnk. A set trunk_act bit indicates that the corresponding port is an active member of the tmnk. Table 1 below summarizes the various combinations of trunk control bits and how frames are to be forwarded based on these combinations. Table 1 Summary of Trunk Control Bits Referring to Table 1, when the trunk bit is "0", the corresponding port is not a member of a trunk and frames destined for this port will not be redirected to another port, regardless of the trunk_act bit. When the trunk bit is "1" and trunk_act bit is "0", the corresponding port is part of the trunk, but is inactive, possibly due to a link failure. Frames destined for this port will be redirected to another port in the trunk. When the tmnk bit is "1" and the trunk_act bit is "1", the corresponding port is an active part of the trunk and frames can be transmitted from this port, as described in more detail below. Advantageously, using the port IRC control registers 114a-l to store tranking information enables the present invention to support trunking without storing specific tranking information in the IRC address table 82. Additionally, the use of two bits per port, i.e., trunk and trunk_act bits, to indicate tmnk membership allows the host CPU 32 to reconfigure the trunk without changing the IRC address table 82 when a link is broken/restored or when the host CPU 32 changes the network tranking configuration. For example, suppose the host CPU 32 is to remove port 2 as an active port on trunk 1. The host CPU 32 accomplishes this by clearing the trank_act bit in the port IRC control register 114b. As discussed previously, when a frame is received, the IRC 40 processes the frame in four stages via ingress rales engine 200, SA lookup engine 210, DA lookup engine 220 and egress rules engine 230, respectively. After the DA lookup engine 220 completes the DA lookup, the egress mles engine 230 receives and examines the port vector information and determines from the port IRC control register 114 whether the frame is to be transmitted through a port that is part of a trunk. When the frame is to be transmitted through a trank port, the egress rales engine 230 determines the specific forwarding port in the trunk through which the frame will be transmitted. Figure 11 is a flow diagram illustrating the method of generating frame forwarding information in connection with trunking. Referring to Figure 11 at step 200, the egress mles engine 230 receives the port vector information and the receive port information from the DA lookup engine 220. Next, at step 202, the egress mles engine 230 compares the port vector information with the information stored in the corresponding IRC port control register(s) 114. The egress mles engine 230 then determines whether a forwarding port is part of a tmnk. That is, the egress mles engine 230 examines the tmnk bit in each port IRC control register 114 corresponding to a port(s) identified by the port vector. When all forwarding ports are not part of a trank, i.e., the trank bits are "0", the egress rales engine 230 outputs the forwarding descriptor to the port vector FIFO 56, at step 204. However, when a forwarding port is part of a tmnk, i.e., the trank bit is "1", the egress rules engine 230 masks out all bits in the port vector that correspond to the trunk ports, at step 206. Next, at step 208, the egress rales engine 230 performs a trunk mapping operation to determine the port through which the frame will be transmitted. According to the exemplary embodiment illustrated in Figure 12, the trank mapping logic includes an exclusive OR (XOR) gate 120. Referring to Figure 12, the trunk mapping logic receives the two least significant bits of the frame's SA and DA and sequentially XORs these bits to generate a two bit output. That is, the trunk mapping logic XORs the least significant bit of the frame's SA and DA and then XORs the second least significant bit of the frame's SA and DA. The egress mles engine 230 then selects one of the ports in the trank to transmit the data, based on the two bit output. According to the exemplary embodiment illustrated in Figure 12, an output bit pattern of "00" from XOR gate 120 corresponds to the first port in the trunk block. Output bit patterns "01", "10" and "11" correspond to the second through fourth ports in the trunk block, respectively. For example, assume that the port vector includes information indicating that the frame is to be transmitted on port 2, i.e., bit 2 of the 15-bit port vector is set, and port IRC control register 2, 114b, indicates that port 2 is an active member of trank 1, i.e., both tmnk and trunk_act are "1". Further assume that the two least significant bits (LSB) of the source address of the received frame are "01" and the two least significant bits of the destination address of the received frame are "10". Referring to Figure 12, the egress rales engine 230 XORs "1" and "0", i.e., the LSBs of the SA and DA, respectively, via XOR gate 120 and outputs "1". The egress rales engine 230 then XORs "0" and "1", i.e, the second LSBs of the SA and DA, respectively, via XOR gate 120 and outputs "1". Therefore, the output of the XOR gate 120 in this example is "11". In this scenario, the egress rales engine 230 chooses the fourth port in trunk 1, shown in Figure 10, i.e., port 4. In alternative configurations, other trunk mapping functions may be used to determine the forwarding port from which to transmit a data frame. Advantageously, the particular trunk mapping function used in the present invention optimizes the effective data transmission rate between the two end devices by distributing the transmission of data frames relatively equally among the ports in the trunk. Additionally, in configurations where more than four ports are included in a single trunk, the trunk mapping function utilized would require more than a two bit output to choose the trunk port. For example, if eight ports were included in a trunk, a three bit output would be required to choose the output port from among the eight ports. Next, at step 210, the egress mles engine 230 determines whether the port chosen at step 208 is an active port of the tmnk. That is, the egress rales engine 230 determines whether both the trank bit of the port IRC port control register 114 for the port chosen at step 208, is "1", indicating the port is part of the trunk, and the trank_act bit is "1", indicating that the port is an active link in the trunk. When the determination at step 210 is "no", the egress mles engine 230 chooses an alternative port in the same trunk, at step 212. According to the exemplary embodiment, the egress mles engine 230 chooses the next higher port in the tmnk block, as indicated by the arrows in Figure 12. For example, if the third port in the trunk is chosen at step 208 and the egress rales engine 230 at step 210 determines that the chosen port is not an active member of the trunk, the egress mles engine 230 chooses the fourth port in the tmnk. The egress rales engine then returns to step 210 and repeats the process until the chosen port is an active member of the tmnk. For example, if the fourth port of the trank block is chosen at step 212 and the fourth port is not an active member of the trank, the egress rales engine 230 would then choose the first port of the trank block. In alternative embodiments of the present invention, other methods of choosing an alternate port can be employed, e.g., choose the next lower port in the trunk block when the chosen port is not an active link in the trank. After an active port in the trunk is chosen, the egress rales engine 230, at step 214, then checks whether the data frame was received on a trunk port that is part of the same trank on which the frame is to be transmitted. That is, the egress rales engine 230 checks the contents of the port IRC control register 114 corresponding to the receive port on which the frame was received to determine whether the trank bit is set. When the determination at step 214 is "no", the egress mles engine 230 outputs the forwarding descriptor to the port vector FIFO 56, at step 218. When the determination at step 214 is "yes", the egress rales engine 230, at step 216, masks out all bits in the port vector that correspond to port(s) included in the same trunk as the receive port. In this manner, the egress mles engine 230 ensures that data frames that are received on a trunk port will not be forwarded on the same tmnk. Advantageously, this saves processing time associated with transmitting a data frame back to its source. Next, at step 218, the egress rales engine 230 outputs the forwarding descriptor, including the port vector, to the port vector FIFO 56. The flow diagram illustrated in Figure 11 is applicable for data frames received by multiport switch 12. However, when the host CPU 32 originates a transmission, the IRC 40 does not modify the port vector information generated by the host CPU 32, thereby bypassing the tranking algorithm illustrated in Figure 11. Described has been a system and method for trunking in a network interface device. An advantage of the invention is that the multiport switch 12 supports tranking without storing the particular trunking information in the address table 82, thereby reducing the size of the address table 82 as well as reducing the time spent searching the address table 82. Another advantage of the invention is that tranking changes are made in a quick, efficient manner without reconfiguring the address table 82, thereby reducing potential network downtime. In this disclosure, there is shown and described only the preferred embodiments of the invention, but, as aforementioned, it is to be understood that the invention is capable of use in various other combinations and environments and is capable of changes or modifications within the scope of the inventive concept as expressed herein.

Claims: What is Claimed Is: 1. A multiport switch configured for controlling communication of data frames between stations and to support trunking, comprising: a table for storing address information and data forwarding information; and a decision making engine configured to: search the table and identify a port through which a data frame is to be transmitted, determine, without reference to the table, whether the identified port is a part of a trank, and determine, when the identified port is a part of a trunk, a forwarding port on which to transmit the data frame. 2. The multiport switch of claim 1, wherein the decision making engine is configured to: perform a trunk mapping function and output a value representing the forwarding port. 3. The multiport switch of claim 2, wherein the decision making engine is configured to: generate data forwarding information; and modify the data forwarding information based on the output from the trank mapping function. 4. The multiport switch of claim 2, wherein the trunk mapping function comprises: an exclusive OR gate configured to receive a predetermined number of the least significant bits of both the source address and destination address of a data frame and output a result. 5. The multiport switch of claim 4, wherein the decision making engine is configured to: mask out bits in the data forwarding information that correspond to ports that are part of the trunk; and set a bit in the data forwarding information representing the forwarding port. 6. The multiport switch of claim 5, wherein the decision making engine is configured to: modify the data forwarding information, when the data frame is received on a trunk port, to ensure that the data frame is not transmitted on a port that is in the same trunk as the trank port. 7. The multiport switch of claim 1, comprising a memory configured to store trunking information for each of the respective ports, wherein the decision making engine is configured to determine whether the identified port is part of a trunk based on the contents of the memory. 8. The multiport switch of claim 7, wherein the memory includes: a trunk field for indicating whether a port is a trunk port; and a trunk active field for indicating whether the port is an active part of a trunk. 9. In a multiport switch that controls communication of data frames between stations and is configured to support trunking, the multiport switch including an address table for storing address entries, a method of generating data forwarding information, comprising: receiving information from a data frame; searching the address table for data forwarding information based on the received information; determining whether the data frame is to be transmitted through a port that is part of a trunk; and generating, when the frame is to be transmitted through a port that is part of a trunk and without reference to the address table, a value representing a forwarding port on which to transmit the data frame. 10. The method of claim 9, wherein the generating step comprises: performing a trunk mapping function and outputting the value representing the forwarding port. 11. The method of claim 10, comprising: modifying the data forwarding information based on the output from the trunk mapping function. 12. The method of claim 10, wherein the trunk mapping function comprises: XORing a predetermined number of the least significant bits of both the source address and destination address of the data frame and outputting a result; and mapping the result to the value representing the forwarding port. 13. The method of claim 12, comprising: masking out bits in the data forwarding information that correspond to ports that are part of the trank; and setting a bit in the data forwarding information representing the forwarding port. 14. The method of claim 13, comprising: modifying the data forwarding information, when the data frame is received on a trunk port, to ensure that the frame is not transmitted on a port that is in the same tmnk as the trank port. 15. A multiport switch configured to control communication of data frames between stations and to support trunking, comprising: a table for storing address information and data forwarding information; a plurality of programmable registers corresponding to ports of the multiport switch, each of the programmable registers configured to store trunking information for one of the respective ports; and a decision making engine configured to: search the table and generate data forwarding information for a data frame, determine, based on the data forwarding information and the contents of the plurality of programmable registers, whether the data frame is to be transmitted via a trunk port, and generate, when the frame is to be transmitted via a trunk port, a value representing a forwarding port on which to transmit the data frame. 16. The multiport switch of claim 15, comprising: an exclusive OR gate configured to receive the two least significant bits of both the source address and the destination address of the data frame and generate a two-bit output, and wherein the decision making engine is configured to generate the value representing the forwarding port based on the two-bit output. 17. The multiport switch of claim 16, wherein the decision making engine is configured to: mask out bits in the data forwarding information that correspond to ports that are part of the trunk, and set a bit in the data forwarding information representing the forwarding port. 18. The multiport switch of claim 15, wherein the trunking information comprises: a tmnk field for indicating whether a port is a trunk port; and a trank active field for indicating whether the port is an active part of a tmnk.

Inventors: CHIANG JOHN M, MERCHANT SHASHANK, WILLIAMS ROBERT, CHIANG, JOHN, M., MERCHANT, SHASHANK, WILLIAMS, ROBERT
Applicants: ADVANCED MICRO DEVICES INC, ADVANCED MICRO DEVICES, INC.
Application year: 1999
Main classification: H04L12
IPC codes: H04L12, H04L29