ARRANGEMENT FOR READING INFORMATION FROM A RECORD CARRIER

Abstract: An arrangement is disclosed for reading information from a record carrier, such as in a HDD. The arrangement comprises a read head (Rmr1), an amplifier (74) for amplifying the signal read by the read head, an equalizer (76) for equalizing the signal read by the read head, and a bit detector (80) for detecting bits in the signal read by the read head. In accordance with the invention, the arrangement further comprises a DC correction unit (78) for subtracting a correction value from an input signal in response to an error signal so as to obtain a DC corrected output signal. The bit detector (80) is adapted to detect a sequence of bits based in the DC corrected output signal. Further, an error signal generating unit (82, 83, 85) is present for generating the error signal in response to the DC corrected output signal and the sequence of bits.

Description: Arrangement for reading information from a record earner The invention relates to an arrangement for reading information from a record earner, the arrangement compnsmg - amplifier means (74) for amplifying the signal read by the read head, - equalizer means (76) for equalizing the signal read by the read head, bit detector means (80) for detecting bits in the signal read by the read head and to a hard disk dnve provided with the arrangement Such arrangement is known from USP 5,559,646 and is used for reading information from e g a hard disk It should however be noted that the invention is not restncted to an application m the magnetic field The invention is equally well applicable in the optical field Therefore, m such application m the optical field, under a read head can be understood a photo diode, as is used m optical recording and where the signal shift, to be discussed hereafter, could have been caused by a fingerpnnt on the optical disk, as an example Amplifiers for magneto-resistive (MR) heads sense very small vanations in the MR resistance (typically 1 %) and amplify these signals MR elements are biased by either a voltage or a current Vanations in the resistance of the MR heads, due to a magnetic field, result in small signal voltages and/or currents which can be detected by the sense amplifiers The biasing of the MR heads causes a DC voltage across the head MR sense amplifiers must be AC coupled to the heads To avoid filtenng at the low end of the data frequency spectrum, which results m data distortion, the AC coupling has a long time constant, typically at 1 μs Large transients, such as those caused dunng thermal aspenties, pass the AC coupling and can cause the amplifier to overload, resulting in loss of data dunng long penods The invention aims at providing an improved anangement for reading information from the record earner In accordance with the invention, the arrangement is charactenzed in that the arrangement further compnses - DC correction means (78) for subtracting a correction value from an input signal in response to an error signal so as to obtain a DC corrected output signal, the bit detection means (80) being adapted to detect a sequence of bits based in the DC corrected output signal, - error signal generating means (82,83,85) for generating the error signal in response to the DC corrected output signal and the sequence of bits. The invention is based on the following recognition. The MR heads fly above the disk at very low heights (typically 10 nm). When a collision with a particle on the disk takes place, kinetic energy is transferred to heat. The resistance of the MR elements increases (maximally some 10-20 %). As the bias current remains constant, the baseline voltage (that is: the low frequency component of the output signal) increases rapidly. Further, the signal amplitude of the wanted signal changes by not more than the same 10-20 %. After the thermal asperity, the MR element cools down slowly. These large unwanted baseline shifts can saturate the read amplifier during long periods. Although the saturation can be avoided by using nonlinear control loops in the input stage(s) of the preamplifier, see earlier filed but not yet published European patent application no. 98402802.7, having a filing date 12-11-1998 (PHN 17177), the residual baseline shifts can still cause loss of data over long periods of time. By canying out additional (fast) baseline correction, the effects of the thermal asperities can be further suppressed. In addition, it may be required to add a detection circuit to detect thermal asperities, e.g. so as to freeze the control circuits in the read out circuit, in the event that the thermal asperities would otherwise severely distort the read out circuit. This thermal asperity detection is the subject of claim 4. These and other aspects of the invention will be discussed in more detail hereinafter with reference to the disclosure of preferred embodiments in the figure description, in which figure 1 shows a read amplifier circuit comprising a non-linear transconductance amplifier, figure 2 shows amplifier characteristics of the non-linear transconductance amplifier of the arrangement for generating the control currents, figure 3 shows an input signal for the read amplifier circuit as a function of time, distorted by an asperity, figure 4 shows two output signals as a function of time, one for a read amplifier provided with a linear transconductance amplifier and one for a read amplifier provided with a non-linear transconductance amplifier, figure 5 shows an embodiment of the arrangement m accordance with the invention, provided with a DC correction circuit for (further) correcting the thermal aspenty, figure 6 shows an elaborated version of the DC correction circuit of figure 5, and figure 7 shows a detector circuit for detecting the thermal aspenties. First, a short descnption will be given of an amplifier circuit compnsmg a nonlinear transconductance amplifier, descnbed in European patent application no 98400243 6 filed on 05-02-1998 (PHN 16750), that could be used as an input amplifier for the reading arrangement in accordance with the present invention The amplifier circuit of figure 1 has inputs 1' and 1" for coupling to a magneto- resistive read head (not shown) having a magneto-resistive element 1, having a resistance value R mr A first transistor Ti of the npn type is available having a collectoi terminal coupled to a first point of constant potential (+) via a resistor R \ and having an emitter terminal coupled to a second point of constant potential (-), via a bias current source 4 The emitter terminal is also coupled to one terminal of the magneto-resistive element 1 A second transistor T 2 of the npn type is available having a collector terminal coupled to the first point of constant potential (+) via a resistor Ri and an emitter terminal coupled to the other terminal of the magneto- resistive element 1, as well as to a bias current source 16 The base terminal of the transistor Ti is coupled to the emitter electrode of the transistor T 2 via a first capacitive element 6, having a capacitance value C The base terminal of the transistor T 2 is coupled to the emitter electrode of the transistor Ti via a second capacitive element 8 having a capacitance value C The terminals 10,12 form the output terminals of the amplifier circuit A non-linear transconductance amplifier 14 is provided which has a first and a second input coupled to the output terminals 10 and 12, respectively, of the amplifier circuit The amplifier 14 has first and second outputs coupled to the base terminal of the transistor Ti and T 2 , respectively The transconductance amplifier 14 is designed to supply control c rents at its first and second outputs in response to a voltage V ιn More specifically, figure 2 presents two possible charactenstics of the transconductance amplifier 14 for generating the control currents iι and ι Figure 2 shows the control cmrents iι and ι 2 as a function of the input voltage V ιn . The non-lmear charactenstic is clearly visible in the figure. Figure 2 shows a gradual increase in the slope (apart from its sign) for increasing input voltage level. Instead of this, it is also possible to have at least two regions with each a linear charactenstic, where the slope of the charactenstic m the region of higher input voltages is steeper than in the lower region. Figure 2 shows a gradual increase in slope for increasing input voltage level. The bias curcent source 4 generates a current I m - + I a and the cunent source 16 generates a curcent l m - I a . I a is the quiescent current that flows through the transistors Ti and T 2 and l m is the bias current that flows through the MR element 1. It should be noted in this respect that the embodiment of figure 1 is only a schematic embodiment in the sense that it only shows the elements that are essential for explaining the invention. More specifically, figure 1 does not show all the elements that are needed to realize the common mode setting of the read amplifier. Those elements are however well known for the skilled person The functioning of the amplifier circuit is as follows. The amplifier circuit is based on a cross coupled architecture, as is known from USP 5,559,646. This is optimum for noise and bandwidth. The AC coupling, formed by the capacitors 6 and 8 are biased by feedback from output to input (the bases of the transistors Ti and T 2 ) to output (the terminals 10,12), via the transconductance amplifier 14. In the pnor art, the transconductance 14 exhibits a linear charactenstic. The AC coupling time constant is therefore fixed and large. The AC coupling time constant can be expressed as. C * (Rmr + R ) / 2 * G m *Rι, where R, n equals k * T / q * I a .The non-lmear transconductance 14 therefore provides a large time constant for small input signals, but provides a small time constant for larger signals In fact, the resultant behaviour is that the low frequency cutoff of the amplifier is shifted to higher frequencies for higher input signal levels. The embodiment of figure 1 shows a single stnpe magneto-resistive element. An embodiment of an amplifier circuit for a dual-stnpe magneto-resistive head has been disclosed in the above mentioned earlier filed European patent application no. 98400243 6 Figure 3 shows an input signal applied to the amplifier circuit of figure 1. The aspenty accounts for the sharp increase m the input signal. Figure 4 shows two output signals One denoted 'linear' , is obtained with a read amplifier circuit exhibiting a linear control charactenstic and the output signal denoted "non-lmear' is obtained with the read amplifier circuit of figure 1 Clearly visible is that the wanted signal, which is the sinusoid supenmposed on the aspenty signal remains visible through the aspenty, whilst the peak value of the asperity signal is reduced The read amplifier circuit descnbed above can be followed in a later stage by a DC conection circuit. This DC conection circuit can function on signals having a higher amplitude, so that a further aspenty reduction can be obtained this conection circuit. Figure 5 shows an embodiment of the reading arrangement in accordance with the invention, provided with this DC conection (or baseline conection) circuit. The magneto- resistive head R^ is coupled to a block 70 which denotes the non-linear amplifier circuit as descnbed above with reference to figure 1. The output of the block 70 is coupled to an input of a block 72 which realizes an AC coupling and can be in the form of a highpass filter circuit, or a capacitor. The output of the block 72 is coupled to an input of a block 74 which compnses a vanable gain amplifier, which has an output coupled to a block 76, which is in the form of an equalizer filter The output of the equalizer filter 76 is coupled to a block 78 which carnes out a DC conection on its input signal An output of the block 78 is coupled to inputs of a bit detection block 80 and a subtractor unit 82, to the latter via a delay unit 83. An output of the bit detection block 80 is coupled to an output terminal 88 as well as, via a filter unit 85, to a second input of the subtractor unit 82 An output of the subtractor unit 82 is coupled via a connection denoted by A to a control input of the conection unit 78. The function of the non-lmear amplifier circuit 70 was to suppress the thermal aspenties to avoid overflow of the preamplifier. Suppose, as an example, that the amplitude ratio R, defined as the ratio of the amplitude of the thermal aspenty V TA and the peak-peak amplitude V PP of the information signal, in the output signal of the read head Rmr is at maximum 20, then the amplifier 70 might, in unfavourable conditions, result in a ratio in its output signal of around 10. Under the influence of the AC coupling in the block 72 and the signal processing in the blocks 74 and 76, the ratio R is further decreased, for example to a value of 3. Now, in this situation, it is possible to further suppress the influence of the thermal aspenties by carrying out a DC or baseline conection If the target of the baseline correction would be to zero the mean value of the input signal to the bit detector, the performance of the control loop would depend on the specific data pattern, in particular when the loop reacts fast (as is desired to corcect thermal aspenties) Therefore, first all data parts (the data itself and filtered data, which is fed back to compensate ISI in the signal) are removed in the subtractor 82. The resulting signal, the error signal, consists of the baseline and the noise. The control, in pnnciple, becomes data independent and can be fast. In order to realize a conect error signal in the subtractor 82, it is required to filter the detected data signal at the output of the bit detector unit 80, in the filter unit 85. The filter unit 85 has such a filter response H(f), that it replicates the ISI-structure at the input of the bit detector unit 80. The impulse response function of the filter H(f) equals in principle the 'target' response of the detector 80 (although other choices for the impulse response are also possible and useful, especially when the DC conection loop is asynchronous). Further, delays occurring in the bit detector unit 80 and the filter unit 85 can be corrected for by the delay unit 83. For a bit detector unit 80 in the form of a slicer, the circuit simplifies for the reason that the blocks 83 and 85 can be dispensed with. Figure 6 shows the complete circuit that realizes the DC correction in more detail. An enor signal is generated which is the difference between the input signal to the bit detector unit 80 and the (possibly filtered) output signal of the bit detector unit 80, that is: the actual data signal and possibly ISI. The bit detector unit 80 can be asynchronous, or can include a sampler. The enor signal obtained by the subtractor unit 82 is fed via the line denoted A to an integrating circuit 84 included in the DC conection unit 78. The output signal of the integrating circuit 84 is a measure of the DC value in the input signal of the subtractor unit 86, which is again a measure of the remaining influence of the asperities at this stage in the read out circuit. The functioning of the DC correction is thus such that the enor signal on the line denoted A is controlled towards zero. The DC conection is based on the enor signal. Because the data is already removed from the enor signal in the block 82, in principle, only the DC offset or baseline enor is fed back, not the data. Therefore, the DC conection does not distort the data. This is contrary to prior art ways of solving this problem, such as the switching of the cut-off frequency of the AC coupling temporarily to a higher value when an asperity is detected. Also the non-linear control of the AC coupling in the block 72 influences the data. For this reason the nonlinear control in the amplifier input only avoids overloading of the amplifier stages. The rest of the conection is done by the baseline correction which is based on the enor signal. By making the DC correction fast (by increasing the loop gain), the data can be read, even though aggressive asperities, without making lots of errors. With the further use of ECC techniques, it is possible to read through most asperities, without unconectable enors. Fast detection requires a short loop delay. Preferably, the equalizer should not be in the loop (as in figure 5) and the delay of the bit detector should be short. Often, the latter delay can be reduced by using preliminary bit decisions for the control loop, instead of final ones. The DC conection control loop can be non-linear, in the sense that for small amplitude asperities, the time constant of the loop is relatively large and that for large amplitude asperities, the time constant is smaller. Making the time constant in the loop smaller can be realized by increasing the loop gain. This can be done in an automatic fashion by inserting a suitable nonlinear block 87 between blocks 82 and 84. The nonlineanty should be odd, and should basically provide a ga that increases with input signal amplitude. For sufficiently large signal amplitudes the gain may level off again so as to restnct dynamic range of the resulting output signal and simplify implementation. The nonlineanty provides extra loop gain and hence faster response to large deviations from the wanted situation. By introducing some hysteresis, the increased loop gam can be maintained for a somewhat longer time so as to reduce the duration of the tail of the loop-settling response. Figure 7 shows a circuit anangement for detecting residual aspenties, i.e. for detecting any aspenty effects in front of the bit detector, possibly after application of the aforementioned suppression and compensation techniques. The circuit anangement of figure 9 compnses a lowpass filter unit 90, which has an output coupled to inputs of comparator circuits 92 and 94. Outputs of the comparator circuits are coupled to conesponding inputs of a combiner circuit 96, which has an output coupled to a one-shot circuit 98. A thermal aspenty detector is needed in order to improve the reliability of the read anangement It can warn the read anangement that there can be a problem with the conesponding part of the data signal. Precautionary actions can be taken, so that the overall performance of the read out anangement can be improved. A pnor art way of detecting aspenties is to detect the peak values of the read out signal and check whether they remain within certain limits. This procedure is data (PW50) dependent and is affected by DC-offset. In pnnciple, a thermal aspenty detector should follow the baseline of the signal and it should detect anomalies Thermal aspenty detection m the preamplifier and in the channel IC does not need to be the same In the pre-amphfier, thermal aspenties are detected, independent of whether they are conected in the read channel path, that could have been incorporated in a channel IC. This path can be identified by the blocks 72 to 82 in figure 5, although it should be stressed that the read channel path may compnse other circuits. In the present invention, thermal aspenty detection is earned out in the channel IC, by detecting any aspenties that remain m front of the bit detector possibly after application of the aforementioned suppression and compensation techniques. These residual aspenty effects manifest themselves in the form of short-term DC-offsets in the enor signal present at the output of subtraction circuit 82 in figs. 7 and 8. To detect this offset in the presence of additional disturbances that are contained in the enor signal, such as residual mtersymbol interference and noise, the enor is first applied to a low-pass filter. It is then compared to positive and negative threshold values +Vth and -Vth, respectively. When the signal applied to the comparators 92 and 94 exceeds one of the threshold values, a residual thermal aspenty-effect is detected. The output signals of the comparator units 92 and 94 are combined in the combiner 96 and a one shot 98 may be provided to lengthen the detection pulse that indicates the occunence of a residual aspenty-effect. The output signal of the one shot 98 can be used, for example, as an "erasure' indicator for the error correction circuitry outside the channel IC, or as a control signal for circuits within channel IC. This control signal can be used, for example, to command the read PLL withm the channel IC to coast, or the AGC within the channel IC to freeze Whilst the invention has been descnbed with reference to prefened embodiments thereof, it is to be understood that these are not limitative examples. Thus, vanous modifications may become apparent to those skilled in the art, without departing from the scope of the invention, as defined by the claims As an example, the measure of the DC conection earned out and the measure to generate an aspenty detection signal, as explained with reference to the figures 5, 6 and 7, can be applied separately from the measure to use the non-linear read amplifier descnbed with reference to the figures 1 to 4. Also the thermal aspenty detector can be used without application of baseline conection based on an enor signal Further, the invention lies in each and every novel feature and combination of features

Claims: CLAIMS: 1. Arrangement for reading information from a record earner, the arrangement compnsmg: - amplifier means (74) for amplifying the signal read by the read head, - equalizer means (76) for equalizing the signal read by the read head, bit detector means (80) for detecting bits in the signal read by the read head, charactenzed in that the anangement further compnses - DC conection means (78) for subtracting a conection value from an input signal in response to an enor signal so as to obtain a DC conected output signal, the bit detection means (80) being adapted to detect a sequence of bits based in the DC conected output signal, - enor signal generating means (82,83,85) for generating the error signal m response to the DC conected output signal and the sequence of bits. 2. Anangement as claimed in claim 1, charactenzed in that the enor signal generating means compnses subtraction means (82) for subtracting the sequence of bits from the DC conected output signal or a filtered version thereof, and wherein the DC conection means compnses integrating means (84) for integrating the enor signal so as to obtain a conection signal, and subtraction means (86) for subtracting the conection signal from the input signal 3 Anangement as claimed in claim 1, charactenzed m that the arrangement further compnses non-lmear amplifying means (87) for non-lmearly amplifying the error signal pnor to applying the enor signal to the DC conection means. 4 Arrangement as claimed in claim 1 , charactenzed in that it further compnses - comparator means (92) for companng a lowpass filtered version of the enor signal with a threshold value, - means for generating an aspenty detection signal (98) in response to the filtered version of the enor signal exceeding the threshold value. 5. Hard disk drive, provided with the arrangement as claimed in anyone of the preceding claims. 6. Anangement for reading information from a record carrier, the anangement comprising: - amplifier means (74) for amplifying the signal read by the read head, - equalizer means (76) for equalizing the signal read by the read head, bit detector means (80) for detecting bits in the signal read by the read head, characterized in that the anangement further comprises - comparator means (92) for comparing a lowpass filtered version of the enor signal with a threshold value, - means for generating an asperity detection signal (98) in response to the filtered version of the enor signal exceeding the threshold value.

Inventors: BERGMANS JOHANNES W M, VOORMAN JOHANNES O, BERGMANS, JOHANNES, W., M., VOORMAN, JOHANNES, O.
Applicants: KONINKL PHILIPS ELECTRONICS NV, KONINKLIJKE PHILIPS ELECTRONICS N.V.
Application year: 1999
Main classification: G11B20
IPC codes: G01R33, G11B5, G11B7, G11B20, G11B33