MULTI-FREQUENCY VOLTAGE REGULATING CIRCUIT INCORPORATING A MAGNETIC FIELD POWER SENSOR AND PROGRAMMABLE MAGNETIC FIELD DETECTION

Abstract: The highly efficient multi-frequency voltage regulating circuit is capable of converting magnetic field energy to electrical energy for charging either a battery or an energy storage device such as a capacitor. The invention provides a magnetic field sensor circuit that measures the strength of incoming magnetic field energy with respect to a reference current. The invention also provides for a programmable magnetic field detection circuit which is used to adjust the detection level of the inductor-capacitor magnetic field converter circuit. A discharge expediter circuit is provided to improve the efficiency of the magnetic field converter circuit by discharging excess energy.

Description: MULTI-FREQUENCY VOLTAGE REGULATING CIRCUIT INCORPORATING A MAGNETIC FIELD POWER SENSOR AND PROGRAMMABLE MAGNETIC FIELD DETECTION RELATED APPLICATIONS This U.S. Patent Application is related to U.S. Patent Application entitled "A ROBUST LC FULL- WAVE BRIDGE RECTIFIER INPUT STRUCTURE," Serial No. 09/007,485 and a filing date of January 15, 1998, in the name of Pieter Schieke was assigned to the same assignee as the present U.S. Patent Application, and is incorporated by reference. BACKGROUND OF THE INVENTION 1. Field of the Invention: This invention relates generally to devices which convert magnetic field energy to regulated electrical energy. Specifically, the present invention regulates direct current electrical energy which has been converted from magnetic field energy, measures the strength of the incoming magnetic field energy, adjusts the detection level of the incoming magnetic field and discharges excess energy from the magnetic field converter circuitry. 2. Description of the Prior Art: Electrical current rectification circuits and voltage regulator circuits are well known to those skilled in the art of electronic design. To a lesser extent, electronic circuits which convert magnetic field energy to electrical energy, then subsequently rectify and regulate the resulting direct current voltage are also known. The problem not previously addressed by prior art is the ability of an electronic circuit to determine the strength of an incoming magnetic field as measured by electrical power for the purpose of enhancing electro-magnetic communication between devices. The present invention has the ability to determine the strength of an incoming magnetic field as measured by electrical power, to adjust the detection level of the input converter circuitry and discharge excess energy based on the measured magnetic field strength and to interpret changes in the measured magnetic field strength as a method for communicating digital data. SUMMARY OF THE INVENTION It is an object of the present invention to provide an electrical circuit which can measure the strength of the incoming magnetic field energy. It is another object of the present invention to use the incoming magnetic field energy measurement to program the detection level of the programmable magnetic field detection circuit. It is still another object of the present invention to measure incoming magnetic field energy variations for the purpose of receiving digital data from a magnetic field transmitter. In accordance with one embodiment of the present invention, a highly efficient multi- frequency voltage regulating circuit is disclosed which comprises a magnetic field power sensor circuit, a programmable magnetic field detection circuit coupled to the magnetic field power sensor circuit, a discharge expediter circuit coupled to the programmable magnetic field detection circuit, a magnetic field converter circuit coupled to the discharge expediter circuit, a rectifier circuit coupled to the magnetic field converter circuit, a voltage clamping circuit coupled to the magnetic field power sensor circuit, and a charging circuit coupled to the voltage clamping circuit. In accordance with another embodiment of the present invention, a highly efficient multi-frequency voltage regulating circuit is disclosed where the programmable magnetic field detection circuit may be controlled by an analog reference current. In accordance with another embodiment of the present invention, a highly efficient multi-frequency voltage regulating circuit is disclosed where the programmable magnetic field detection circuit may be controlled by selection of a discrete reference current. In accordance with another embodiment of the present invention, a highly efficient multi-frequency regulating circuit is disclosed where the selection of a particular discharge path within the discharge expediter circuit is programmable. In accordance with another embodiment of the present invention, a highly efficient multi-frequency voltage regulating circuit is disclosed which comprises a magnetic field power sensor circuit that measures incoming magnetic field energy variations for the purpose of communicating digital data over a magnetic field. The foregoing and other objects, features, and advantages of the invention will be apparent from the following, more particular, description of the preferred embodiments of the invention, as illustrated in the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS Figure 1 is an electrical schematic of a magnetic field converter circuit, a discharge expediter circuit, a rectifier circuit, a magnetic field power sensor circuit, a programmable magnetic field detection circuit, a voltage clamping circuit, and charging circuit. Figure 2A is a waveform diagram of a typical sinusoidal waveform as seen by the LC magnetic field converter circuit. Figure 2B is a waveform diagram of the digital output of the magnetic field power sensor circuit for the sinusoidal waveform of figure 2A. Figure 2C is a waveform diagram of a pulse waveform of varying amplitudes as seen by the LC magnetic field converter circuit. Figure 2D is a waveform diagram of the digital output of the magnetic field power sensor circuit for the pulse waveform of figure 2C. Fig. 3 is a simplified electrical schematic of a prior art, idealized FWBR input structure implemented in an integrated circuit. Fig. 4 is a simplified electrical schematic of a prior art FWBR input structure having parasitic BJTs implemented in an integrated circuit. Fig. 5 is a simplified electrical schematic of a new FWBR input structure having parasitic BJTs of minimized gain in an integrated circuit. Fig. 6 is a simplified electrical schematic of another version of a new FWBR input structure having parasitic BJTs of minimized gain in an integrated circuit. Fig. 7 is a simplified drawing showing one possible manner of physically implementing a portion of the FWBR input structure of Figure 6. Note that the portion shown here equates to the portion of Figure 6 having the same reference numbers as those shown in Figure 7. Fig. 8 is a cross-sectional view of the physical implementation from Figure 7 taken along line 6-6. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT Referring to Figure 1, a highly efficient multi-frequency voltage regulating circuit 200 is disclosed which comprises a magnetic field power sensor circuit 220, a programmable magnetic field detection circuit 250 coupled to the magnetic field power sensor circuit 220, a discharge expediter circuit 210 coupled to the programmable magnetic field detection circuit 250, a magnetic field converter circuit 280 coupled to the discharge expediter circuit 210, a rectifier circuit 290 coupled to the magnetic field converter circuit 280, a voltage clamping circuit 260 coupled to the magnetic field power sensor circuit 220, and a charging circuit 270 coupled to the voltage clamping circuit 260 for charging a battery and an energy storage device. The LC magnetic field converter circuit 280 and the rectifier circuit 290 are described in copending U.S. Patent Application entitled "A ROBUST LC FULL- WAVE BRIDGE RECTIFIER INPUT STRUCTURE," Serial No. 09/007,485 and a filing date of January 15, 1998, and is incorporated by reference as noted above under "Related Applications". The clamping circuit 260 is a simple capacitor 262 coupled in parallel to a zener diode 264 and is well known to those skilled in the art. The charging circuit 270 is comprised of a biasing resistor 272 coupled to the gate connector of a NMOS FET switch 274, a diode 276 and resistor 275 in parallel coupled to a source connector of the NMOS FET transistor switch 274, a battery 278 coupled to the diode 276 and resistor 275, and a energy storage device 279 coupled to the diode 276 and resistor 275. The charging circuit 270 permits charging of the energy storage device 279 and recharging of the battery 278. The charging circuit 270 has also been disclosed by prior art. The magnetic field power sensor circuit 220 provides the capability of determining the strength of the incoming electro-magnetic field. The magnetic field power sensor circuit is comprised of an input current (Iz) 222, an input current divider circuit 230 coupled to Iz 222, an input current multiplier circuit 240 coupled to the input current divider circuit 230, a reference current (I REF ) 224 coupled to the input current multiplier circuit 240, and a comparator 248 coupled to the input current multiplier circuit 240. Iz 222 is the same as the output current of the clamping circuit 260. IREF 224 is generated external to the present invention. The purpose of IREF 224 is to establish an equilibrium point at the negative node of the comparator 248. The positive node of the comparator is coupled to a bias voltage. Disregarding the input current divider circuit 230 and the input current multiplier circuit 240 for a moment, if Iz 222 is less than IREF 224, the output of the comparator will be 0. However, if Iz 222 is larger than I REF 224, the comparator 248 will give a positive output which yields two results. First, a positive output of the comparator 248 indicates that the rectified voltage is above the breakdown voltage of the zener diode 264. Second, the incoming magnetic signal has enough power to subsequently maintain an input current through the zener diode 264. Thus, the positive output of the comparator 248, which is reached only when Iz becomes greater than IREF, enables the determination of whether a certain induced voltage level has been exceeded and what nominal power level is present in the electromagnetic field received by the voltage regulating circuit 200. The operation of the input current divider circuit 230 and the input current multiplier circuit 240 is described. The purpose of the current divider and multiplier circuits (230 & 240) is to have Iz mirror IREF by a combination of the divider circuit 230, which effectively reduces Iz, and the multiplier circuit 240, which effectively increases Iz. Thus, by having two circuits which in combination permit Iz to mirror IREF, the equilibrium point at the negative node of the comparator 248 is evaluated with respect to variations in Iz and thus to incoming magnetic field strength. First, the effects of the input current divider circuit 230 are considered on the current equilibrium point at the negative node of the comparator 248. The input current divider circuit 230 is comprised of at least one NMOS transistor 232. The at least one NMOS transistor 232 is configured such that the gate and drain connectors of each of the at least one NMOS transistors 232 is coupled to the input current 222. Furthermore, the source connectors of each of the at least one NMOS transistors 232 are coupled to a ground reference. The effect of this input current divider circuit 230 is to mirror an Iz that is divided by the number of NMOS transistors 232 in the circuit. For example, suppose there were two transistor as part of the input current divider circuit 230 and IREF 224 were set at 10 uA, the zener diode breakdown voltage is 5 volts, the threshold voltage of the input current divider circuit 230 is 0.7 volts and the magnetic field power is increased until the output of the comparator 248 becomes positive. The power of the magnetic field signal = (10 uA * 5.7 volts)/2 = 28.5 uW and Iz = 5 uA(= lOuA/2). Next the effects of the input current multiplier circuit 240 are considered on the current equilibrium point at the negative node of the comparator 248. The input current multiplier circuit 240 is comprised of a second at least one NMOS transistor 242. The second at least one NMOS transistor 242 is configured such that the gate connectors of each of the second at least one NMOS transistors 242 are coupled to Iz 222 and the input current divider circuit 230. The second at least one NMOS transistor 242 is further configured such that the drain connectors of each of the second at least one NMOS transistors 242 are coupled to the reference current 224 and also to the negative node of the comparator 248. Lastly, the second at least one NMOS transistor 242 is configured such that the source connectors of each of the second at least one NMOS transistors 242 are coupled to a ground reference. The effect of this input current multiplier circuit 240 is to multiply Iz by the number of NMOS transistors 242 in the circuit. For example, suppose there were three transistor as part of the input current multiplier circuit 240, I RE F 224 was set at 10 uA, the zener diode breakdown voltage is 5 volts, the threshold voltage of the input current multiplier circuit 240 is 0.7 volts and the magnetic field power is increased until the output of the comparator 248 becomes positive. Then the power of the magnetic signal = (10 uA * 5.7 volts)*3 = 171 uW and Iz = 30 uA(= lOuA * 3). In summary, the input current 222 is mirrored by a factor of 1/m for the input current divider circuit 230 and by a factor of n for the input current multiplier circuit 240. Where m equals the number of NMOS transistors in the input current divider circuit 230 and n equals the number of NMOS transistors in the input current multiplier circuit 240. The ratio of m:n is defined as the current mirror ratio. Thus, the power of the incoming magnetic field can be determined at the point that the output of the comparator transitions from low to high by varying IR EF 224, the current mirror ratio and/or the zener diode 264 breakdown voltage. Throughout this specification reference is made to a magnetic filed sensor circuit 220 comprised of NMOS FETs, which reflects the preferred embodiment. However, those skilled in the art will recognize that PMOS or CMOS FETs may be implemented with minor modification to the circuit to acheive substantially, if not identical, results. The programmable magnetic field detection circuit 250 permits the screening of incoming magnetic field energy by the adjustment of comparator bias voltage. Thus, only magnetic field induced voltage signals that meet or exceed bias voltages will be processed. The programmable magnetic field detection circuit 250 is comprised of at least two comparators 252 & 254 and a multiplexer 256. In one embodiment, the output of the LC magnetic field converter circuit 280 is connected to each of the positive nodes of the 5 comparators 252 & 254. The negative node of one comparator 252 is connected to a bias voltage. The negative node of the second comparator 254 is connected to the voltage induced by I REF 224. The outputs of the comparators 252 & 254 are connected to the inputs of the multiplexer 256. The output of the comparator 248 of the magnetic field sensor circuit 220 is connected to the input select for the multiplexer 256. The output of the multiplexer 256 is l o connected to logic beyond the scope of the present invention such as signal processing. The programmable magnetic field detection circuit 250 operates as follows. The biasing voltage for the first comparator 252 is typically set at a threshold level to allow the output of the LC magnetic field converter circuit 280 to pass through the first comparator 252 to an input of the multiplexer 256. The biasing voltage for the second comparator 254 is set to the 15 corresponding voltage for the reference current 224. Only incoming magnetic field signals with an amplitude that exceeds that of the voltage induced by IREF 224 will pass through the second comparator 254. The output of the comparator 248 of the magnetic field sensor circuit 220 is connected to the input select of the multiplexer 256. In a typical application, the output of the comparator 20 248 is interpreted by the multiplexer 256 to select the output of either the first comparator 252 or the second comparator 254. Thus, the sensitivity of the circuit 250 is adjustable by varying the amplitude of the reference current 224 and the selection of the second comparator 254 by the output of the magnetic field sensor circuit 220. Described above is a programmable magnetic field detection circuit 250 which is comprised of two comparators 252 & 254. Those skilled in the art will recognize that the present invention is not limited to two comparators. Additional comparators can be incorporated into the programmable magnetic field detection circuit 250 to allow for greater flexibility. Similarly, the multiplexer 256 which is disclosed as having two inputs may also be expanded to include additional inputs. The amplitude of the reference current may be varied by analog means such as a sinusoidal, triangle, sawtooth or other known wave generators. Furthermore, the amplitude of the reference current may be varied by discrete means well known to those skilled in the art. For example, selection logic can be incorporated into the present invention to select as between a plurality of available discrete reference currents. This selection may be accomplished either dynamically or may be preset. The discharge expediter circuit 210 provides a programmable discharge path for excess energy stored by the magnetic field converter circuit 280. In the preferred embodiment, the discharge expediter circuit 210 is comprised of a decoder 219 and four discharge paths, i.e. two discharge paths for each node of the magnetic field converter circuit 280. However, those skilled in the art will recognize that the present invention is not limited to four discharge paths. The first pair of discharge paths are connected to a first common node of the magnetic field converter circuit 280. The first discharge path is formed by the combination of resistor 211 and transistor 215. The second discharge path is formed by the combination of resistor 212 and transistor 216. In the preferred embodiment, the impedance value of resistor 211 is distinct from the impedance value of resistor 212. As those skilled in the art will recognize, the discharge paths can be designed to operate efficiently with magnetic fields of varying strengths by having resistors with unique impedance values to control the rate of discharge. The second pair of discharge paths are connected to a second common node of the magnetic field converter circuit 280. The third discharge path is formed by the combination of resistor 213 and transistor 217. The fourth discharge path is formed by the combination of resistor 214 and transistor 218. In the preferred embodiment, the impedance value of resistor 213 approximates that of resistor 211 and the impedance value of resistor 214 approximates that of resistor 212. Efficiency is enhanced by matching the impedance values of analogous discharge paths for each node of the magnetic field converter circuit 280. The decoder 219 activates the selected discharge path(s). The C (control) input to the decoder 219 is coupled to a programming source that is beyond the scope of the present invention. The D (decode) input to the decoder 219 is coupled to the data source to be decoded. In the preferred embodiment, the D input is coupled to the output of the comparator 248. The Oi output of the decoder 219 is coupled to the control electrodes of the transistors 215 & 217. The O 2 output of the decoder 219 is coupled to the control electrodes of the transistors 216 & 218. Thus, by programmably asserting a specific output of the decoder 219, discharge paths with common characteristics are selected for each of the two nodes of the magnetic field converter circuit 280. The selected discharge path permits discharge of pent up energy in the magnetic field converter circuit 280. Those skilled in the art will recognize that certain impedance values of the resistors 211, 212, 213 «& 214 will optimize the efficiency of the discharge paths for specific magnetic field strengths. Referring to Figures 2A-2D, waveform diagrams of the conversion of the incoming magnetic field to digital data are disclosed for the purpose of illustrating digital communication over a magnetic field. For all the diagrams, the abscissa is time and the ordinate is power. Two variations of an incoming magnetic field waveforms are shown. Figure 2A reflects a typical sinusoidal waveform as seen by the LC magnetic field converter circuit 280 (figure 1). Figure 2B reflects the digital output of the comparator 248 (figure 1) for the sinusoidal waveform of Figure 2A. Figure 2C reflects a pulse waveform with varying amplitudes at the LC magnetic field converter circuit 280 (figure 1). Figure 2D reflects the digital output of the comparator 248 (Figure 1) for the pulse waveform of Figure 2C. Those skilled in the art will note that the trigger point for the digital output of the comparator 248 is determined by the power of the incoming magnetic signal and the parameters described for the voltage regulating circuit 200 (Figure 1). Those skilled in the art will further note that the digital output of the comparator 248 can be used to receive digital communication from a magnetic transmitter. Referring to Figure 3, simplified electrical schematic is shown of a prior art, idealized FWBR input structure implemented in an integrated circuit. The FWBR input structure is generally designated by reference number 10. It includes an inductor 12 coupled in parallel to a capacitor 14 about input nodes 16 and 18. From input nodes 16 and 18, there are resistors 20 and 22, respectively, before reaching the cathode junction of a pair of diodes 24 and 26, respectively. The anode junctions of diodes 24 and 26 are tied to ground. The node at the cathode junction of diode 24 is connected to the source of a PMOS transistor 28, and to the gate of PMOS transistor 30. Similarly, the node at the cathode junction of diode 26 is connected to the source of a PMOS transistor 30, and to the gate of PMOS transistor 28. Lastly, the drain of PMOS transistor 28 is tied to the drain of PMOS transistor 30 at the output node 32 for the FWBR input structure 10. Nothing more needs to be disclosed with respect to the FWBR input structure 10, since it is well known, other than to say something about why it is called here, an "idealized" FWBR input structure 10. This is because the diodes 24 and 26 are the ideal or desired components for the FWBR input structure 10; however, as discussed in the section entitled "Description of the Related Art," the ideal FWBR input structure 10, when implemented in an integrated circuit, takes on a different form. Specifically, as disclosed in the "Description of the Related Art," a pair of parasitic BJTs 48 and 50 (see Figure 4) are formed, which are detrimental to operation of the FWBR input structure 10. Thus, these BJTs 48 and 50 are called parasitic (i.e., unwanted, but unavoidable) BJTs. Referring to Figure 4, a simplified electrical schematic is shown of a prior art FWBR input structure having parasitic BJTs implemented in an integrated circuit. As mentioned before, implementation of the ideal, prior art FWBR input structure 10 of Figure 3 into an integrated circuit effectively results in the creation of parasitic BJTs 48 and 50, rather than the ideal diodes 24 and 26 (see Figure 3) by themselves. Otherwise, Figures 3 and 4 are the same. The FWBR input structure of Figure 4 is generally designated by reference number 34. It includes an inductor 36 coupled in parallel to a capacitor 38 about input nodes 40 and 42. From input nodes 40 and 42, there are resistors 44 and 46, respectively, before reaching the emitter junctions of a pair of parasitic BJTs 48 and 50, respectively. The base junctions of parasitic BJTs 48 and 50 are tied to ground, and their collector junctions are tied to a supply voltage VDD through a resistor 52. The node at the emitter junction of parasitic BJT 48 is connected to the source of a PMOS transistor 54, and to the gate of a PMOS transistor 56. Similarly, the node at the emitter junction of parasitic BJT 50 is connected to the source of PMOS transistor 56, and to the gate of PMOS transistor 54. Lastly, the drain of PMOS transistor 54 is tied to the drain of PMOS transistor 56 at the output node 58 for the FWBR input structure 34. Nothing more needs to be disclosed with respect to the FWBR input structure 34, since it is well known, other than to reiterate the problem caused by the creation of parasitic BJTs 48 and 50. The flow path for the FWBR input structure 34, which is analogous to that for the FWBR input structure 10 of Figure 3, is as follows: 1) an electromagnetic field is applied across the tuned LC input (i.e. inductor 36 and capacitor 38) to create alternating complementary current at input nodes 40 and 42; 2) assuming a positive potential at node 40, current flows through resistor 44; 3) since a negative potential is applied to the gate of PMOS transistor 54, it will be on to conduct current to the output load via node 58; and 4) the return path encompasses current flow via ground, through the base-to-emitter junction of parasitic BJT 50, and through the resistor 46. When the polarity of the input nodes 40 and 42 shifts, the analogous flow path for the corresponding portions of the FWBR input structure 34 are used. In either case though, the forward biasing of the base-to-emitter junction (i.e., the "ideal" diode 24 or 26 of Figure 3) for either parasitic BJT 48 or 50, causes a resultant current draw on the subject parasitic BJT's collector via VDD, and ultimately some power storage device such as a battery, capacitor, or the like. Since the parasitic BJTs such as 48 and 50 are unavoidable, it was desirable to minimize their gain, and their resultant drain on the power storage device — this was one of the primary aims of the instant invention shown in Figures 5 and 6. Now referring to Figure 5, a simplified electrical schematic is shown of a new FWBR input structure, generally designated by reference number 60, and having parasitic BJTs of minimized gain in an integrated circuit. Note that the term "FWBR input structure" generally refers to all that is shown in Figure 5; however, it will become apparent that the portion of primary concern is shown in the dashed-line box labelled by reference number 62. Nonetheless, the FWBR input structure 60 comprises, in combination, a pair of input nodes 68 and 70, and a pair of parasitic BJTs 76 and 88 coupled in parallel with the pair of input nodes 68 and 70 wherein each parasitic BJT 76 and 88 has more than one collector. Note that the FWBR input structure 60 includes an inductor 64 and a capacitor 66 connected in parallel across the pair of input nodes 68 and 70. The inductor 64 and capacitor 66 are tuned to a resonant frequency of an electromagnetic transmission, which provides power and/or data to circuitry downstream of the LC pair (i.e., 64 and 66). The LC pair therefore acts, in essence, as an "antenna" for the FWBR input structure 60, and circuitry located downstream of output node 116. Note that the LC pair 64 and 66 is shown comprising single components; however, those skilled in the art recognize that other tuned frequency "antennas" well known to those skilled in the art could be implemented, if desired. For example, the "antenna" could be implemented by using the LC pair, one or more inductors, one or more capacitors, a transformer, or the like. Also, note that each parasitic BJT 76 and 88 comprises an NPN-type parasitic BJT; however, those skilled in the art realize that other BJTs such as PNP-type parasitic BJTs could, in a slightly different situation, be implemented, if desired. A first parasitic BJT 76 has a first collector 80 connected to ground and a second collector 82 coupled to VDD through resistor 84. Similarly, a second parasitic BJT 88 has a first collector 92 connected to ground and a second collector 94 coupled to VDD through resistor 96. The first parasitic BJT 76 has an emitter 78 connected to a first node 68 of the pair of input nodes 68 and 70. The second parasitic BJT 88 has an emitter 90 connected to a second node 70 of the pair of input nodes 68 and 70. Each emitter 78 and 90 has an area smaller than its corresponding collector 82 and 94, respectively, coupled to VDD. Additionally, the first parasitic BJT 76 has a base 85 coupled to ground through a resistor 86, and the second parasitic BJT 88 has a base 97 coupled to ground through a resistor 98. The FWBR input structure 60 further includes a first plurality of zener diodes 100- 104 connected in series having a first end connected to ground and having a second end connected to the first node 68 through a resistor 72. Additionally, a second plurality of zener diodes 106-110 are connected in series. The second plurality of zener diodes 106-110 have one end connected to the first end of the first plurality of zener diodes 100-104, and have another end connected to the second node 70 through a resistor 74. From the output nodes of the dashed- line box labelled 62, there are a number of different combinations of circuit elements well known to those skilled in the art to complete the FWBR input structure 60; however, only one such combination is shown here for the sake of simplification of the drawings. The combination of such circuit elements shown in Figure 5 (and in Figure 6) includes first 112 and second 114 MOS transistors wherein the second end of the first plurality of zener diodes 100-104 is connected to a source of the first MOS transistor 112 and to a gate of the second MOS transistor 114. The other end of the second plurality of zener diodes 106-110 is connected to a source of the second MOS transistor 114 and to a gate of the first MOS transistor 112. The drain of the first MOS transistor 112 is connected to a drain of the second MOS transistor 114 to form an output node 116. Also, note that the first 112 and second 114 MOS transistors are preferably PMOS-type transistors; however, in situations well known to those skilled in the art, NMOS-type transistors could be implemented. Other such well known combinations of circuit elements that could be implemented with the circuitry in the dashed-line box labelled 62, in lieu of elements 112 and 114 as shown in Figures 5 and 6, are now set forth. Note also that these other well known combinations could be used with the FWBR input structure 118 of Figure 6. First, one could have more than two MOS transistors. For example, one could include two or more series- connected PMOS-type transistors, in lieu of the single PMOS transistor 112, and these two (or more) series-connected PMOS-type transistors would be hooked up just like PMOS transistor 112. In this case, there would also be two or more series-connected PMOS-type transistors, in lieu of the single PMOS transistor 114, which would be hooked up just like PMOS transistor 114. A second alternative would use two NMOS transistors in place of PMOS transistors 112 and 114. Here, one NMOS transistor would have its drain and gate tied to the upper output node of 62 (or 120 in Figure 6), and its source tied to the source of the other NMOS transistor for forming the output node 116 for the FWBR input structure 60 or 118. The second NMOS transistor would have its gate and drain tied to the other output node of 62 (or 120 in Figure 6). In summary, the configuration of MOS transistors 112 and 114 in Figures 5 and 6 is shown only as one possible way of completing the FWBR input structures 60 and 118. Those skilled in the art will fully realize that there are numerous ways of taking the signals at the output nodes from the dashed-line box 62 (or 120 in Figure 6) and processing them to complete the full-wave rectification. It is considered within the scope of the invention here to take any one of the many different combinations of elements, well known to those skilled in the art, and incorporate them in place of transistors 112 and 114. Thus, one can envision use of PMOS transistors alone, NMOS transistors alone, PMOS and NMOS transistors together, in series, in parallel, or in some combination thereof. In short, any well known circuitry that could be implemented in lieu of PMOS transistors 112 and 114 is considered well within the scope of the invention here. Figure 6 shows a simplified electrical schematic of another version of the new FWBR input structure, generally designated by reference number 118, and having parasitic BJTs of minimized gain in an integrated circuit. The FWBR input structure 118 of Figure 6 is identical to that shown in Figure 5, with one modification, and therefore the FWBR input structure 118 will not be discussed in detail. In the dashed-line box 120, each of the parasitic BJTs 76 and 88 have an MOS device coupled to them — this is the modification. In particular, the FWBR input structure 118 includes a first MOS transistor 122 having its source 128 connected to the first collector 80 of the first parasitic BJT 76, and having its drain 126 and gate 124 connected to the emitter 78 of the first parasitic BJT 76. 19. A second MOS transistor 130 is also included having its source 136 connected to the first collector 92 of the second parasitic BJT 88, and having its drain 134 and gate 132 connected to the emitter 90 of the second parasitic BJT 88. In the preferred embodiment, the first 122 and second 130 MOS transistors are NMOS-type transistors; however, those skilled in the art realize that under different circumstances, PMOS-type transistors could be implemented. Referring to Figures 7 and 8, one possible manner of physically implementing the instant invention into silicon is shown; however, note that only a portion of the instant invention is shown in Figures 7 and 8 (i.e., that portion corresponding to like numbers in Figures 5 and 6). Nonetheless, those skilled in the art of implementing electrical devices, systems, and the like into silicon understand what the remainder of the instant invention would look like in Figures 7 and 8. Moreover, those skilled in the relevant art also understand that the manner shown in Figures 7 and 8 for physically implementing the instant invention into silicon comprises but one of the many possible manners of implementation. More specifically, the NFET device 122 and the parasitic npn BJT 76 of Figure 6 are shown in Figures 7 and 8 on a p-type silicon substrate. Figure 7 shows a top view, without metallization, while Figure 8 shows a side cross-sectional view taken along line 6-6 of Figure 7. The NFET device 122 is located between nodes 128, 126, and 124, where node 126 forms the drain and node 128 the source for device 122. The parasitic npn BJT 76 is located between nodes GB, 82, 80, and 78. The emitter of parasitic npn BJT 76 is formed by node 78, its base comprises node 85, and the grounded base contact is formed by node GB. Note that the abbreviation "GB" stands for grounded base, which is situated (as viewed in Figure 6) between resistors 86 and 98. The base resistance 86 is associated with the distance from the actual base (85 in Figure 6) of the parasitic npn BJT 76 to the GB node. Note that the base contact GB, and therefore the base resistance 86, may be distributed depending on the layout of the surrounding circuitry. The grounded collector 80 of the parasitic npn BJT 76 completely surrounds emitter 78 in this implementation. The high voltage collector 82 is situated some distance away from the base 85 of the parasitic npn BJT 76 and has an implied resistance 84. The high voltage collector 82, and therefore the resistance 84, may also be distributed as the layout of the surrounding circuitry dictates. Note that where an area of the Figures is labelled with more than one reference number, this is meant to indicate that the area is shared. For example, the area labelled 124 and 85 is shared between the corresponding components labelled in Figure 6, and the area labelled 128 and 80 is shared between its corresponding components from Figure 6. Additionally, note that the base 86 and collector 84 resistances are the sum of more than one leg in Figure 7. Lastly, note that an even more detailed description of Figures 7 and 8 is not required here, as those skilled in the art, after a comparison of the full patent disclosure including all of the Figures, understand the finer details demonstrated by Figures 7 and 8. OPERATION Again, recall that Figures 3 and 4 show previous art, and therefore the operation of these Figures need not be discussed. Turning the focus to Figure 5, one begins with the assumption that the LC time constant associated with inductor 64 and capacitor 66 has been chosen to be tuned to a frequency of an electromagnetic transmission. Here, that frequency is in the vicinity of 125 KHz; however, other frequencies could be used with other LC time constants. Again note however that the "antenna" can be implemented using the LC pair, one or more inductors, one or more capacitors, a transformer, or the like. The LC pair (i.e., 64 and 66) acts like an "antenna" for inputting power and/or data to circuitry downstream of output node 116. The FWBR input structure 60 (or 118 of Figure 6) simply provides a rectified signal for use by downstream loads (not shown). The electromagnetic signal input to the LC pair (i.e., 64 and 66) causes alternating complementary current at input nodes 68 and 70. In other words, when the potential at node 68 is positive, it is negative at node 70, and vice versa. In order to understand the FWBR input structure's flow path, consider the example where node 68 is positive and node 70 is negative. Here, the gate of transistor 112 is low, so it conducts current from node 68, through resistor 72, through transistor 112, through the output node 116, and to the downstream load. To complete the return flow path, current flows from ground, through resistor 98, through the base-to-emitter junction of parasitic BJT 88, and to node 70. The return flow path also includes current flow from the grounded collector 92 to the emitter 90, and to the node 70. When polarity of the input nodes 68 and 70 shifts, the supply flow path will be similar. Namely, the gate of transistor 114 is low, so it conducts current from node 70, through resistor 74, through transistor 114, through the output node 116, and to the downstream load. To complete the return flow path, current flows from ground, through resistor 86, through the base-to-emitter junction of parasitic BJT 76, and to node 68. The return flow path here also includes current flow from the grounded collector 80 to the emitter 78, and to the node 68. In the past, current flow through the base-to-emitter junctions of parasitic BJTs (e.g., 48 and 50 in Figure 4) caused current draw on the downstream power supply (not shown, but which supplies VDD) via the collector tied to VDD. The parasitic BJTs here 76 and 88 have been modified to minimize their gain, and thereby minimize the amount of current drawn from the downstream power supply whether it be a battery, a capacitor, or some other power storage device. A number of features have been built into parasitic BJTs 76 and 88 to minimize their gain. By way of example, these features will be discussed for parasitic BJT 76; however, note that similar changes are also included for parasitic BJT 88. First, in a manufacturing manner well known to those skilled in the art, the area of emitter 78 is purposefully made smaller than the area for collector 82. There is no magic number for how small the emitter 78 should be or how small it should be relative to the collector 82 other than to say that the emitter's area should be smaller than the area for collector 82. Ideally, the area for emitter 78 should be no larger than the area required to support the anticipated current that will be drawn through the emitter's return flow path. In the preferred embodiment, that return flow path current typically falls in the range of 10-50 ma; however, this range is not considered limiting. Rather, in general, the emitter's area should be no larger than that required to support the anticipated return flow path current, and in any case, not larger than the area of collector 82. A second feature is the addition of a second large area collector 80 connected to ground. The area of collector 80 is certainly larger than the area of the emitter 78, and for optimum operation, the larger the area for collector 80, the better; however, design space constraints may limit the area for collector 80 to a reasonably large size. A third feature implemented in the parasitic BJT 76 comprises adding a resistor 86 between its base 85 and ground. A fourth feature added to parasitic BJT 76 was increasing the resistance 84 between VDD and the collector 82. Note that the fourth feature is represented by including a separate resistor 84 and 96 for each BJT's second collector 82 and 94 (instead of a single, shared resistor like 52 in Figure 4). These four features, whether taken singly, or in combination, act to minimize the gain of the parasitic BJTs 76 and 88 in a way that reduces the draw by these devices on the downstream power supply. To exemplify the success of this new implementation, consider the following data. In prior FWBR input structures like 34 (see Figure 4), a design 1 ma output through the base-to-emitter return flow paths of the parasitic BJTs 48 and 50 caused an approximate draw of .5 ma out of a downstream battery. With the new FWBR input structure like 60 or 118, a similar design 1 ma output, draws only 100 micro-amps out of the battery. The parasitic BJTs 76 and 88 are also put to constructive use by having them act as "fold-back devices" (a term well known to those skilled in the art) during Electro-Static Discharge (hereafter "ESD") conditions. An ESD condition occurs when a very high, momentary pulse of voltage is applied to the input nodes 68 and 70. Such a condition may occur from the unintentional touching of the FWBR input structure 60, causing a spark which could result in a pulse of high voltage at the input nodes 68 and 70 ~ such a pulse could attain 4-5 KVolts for example. At such a high voltage, the parasitic BJTs 76 or 88 transmute into a low resistance, fold-back or snap-back mode of operation. By way of example, assume that an ESD condition causes a high voltage spike at input node 68. Here, the zener diodes 100- 104 will clamp the downstream voltage at approximately 15 volts, thereby protecting downstream circuitry. If the voltage spike exceeds this value, then the parasitic BJT 76 will go into fold-back mode. Per the standard operation of a BJT like parasitic BJT 76, when VCE attempts to exceed a certain snap-back value for the transistor, the VCE curve drops off significantly. What this means can be shown by way of example. Assume that the ESD condition creates 4 amps to be dissipated. Without fold-back operation of the parasitic BJT 76, the 4 amps would be dissipated by the zener diode group 100-104 at 15 volts, thereby dissipating 60 watts (i.e., 4 Amps X 15 Volts = 60 Watts). However, when the VCE of the parasitic BJT 76 attempts to exceed the snap-back level, the VCE for parasitic BJT 76 will drop off to a relatively low level, like 5 volts, for example. Therefore, only 20 Watts will be dissipated (i.e., 4 Amps X 5 Volts = 20 Watts). This is just standard BJT operation, and either parasitic BJT 76 or 88 can operate in snap-back or fold-back mode in response to an ESD condition. During ESD conditions, when a high pulse is applied to the LC pair (i.e. 64 and 66), the emitter 78 or 90 of one of the parasitic BJTs 76 or 88 will act as a collector, while the grounded collector 80 or 92 acts as an emitter. The base 85 or 97 of the affected parasitic BJT 76 or 88 floats, and as soon as the voltage difference between the acting collector and the acting emitter is high enough, the parasitic BJT 76 or 88 will fold back into a low resistance mode, absorbing all of the unwanted energy from the ESD pulse. Again, either parasitic BJT 76 or 88 can operate in the fold-back mode per standard BJT operation. The zener diode groups 100-104 and 106-110 ensure that the voltage down stream of the resistors 72 and 74, respectively, don't exceed a pre-determined level, thereby protecting circuitry downstream of resistors 72 and 74. In the preferred embodiment, the zener diode groups 100-104 and 106-110 limit the downstream voltage to approximately 15 volts; however, those skilled in the art realize that more or less than groups of three zener diodes, or zener diodes with a different rating (i.e., other than approximately 5 volts each), could be used to achieve different downstream voltage limitations. The addition of the two groups of zener diodes 100-104 and 106-110 further enhanced the robustness of the FWBR input structure 60. They ensure that the input voltage is clamped at a certain level, but when an ESD pulse is experienced, the voltage level on the BJT side of resistors 72 or 74 will rise high enough to have the parasitic BJTs 76 or 88 go into a low resistance, fold-back mode to absorb the energy associated with the ESD pulse. Referring to Figure 6, a simplified electrical schematic is shown of another embodiment of the new FWBR input structure, generally designated by reference number 118. It is essentially identical to the FWBR input structure 60 from Figure 5, with the exception that the dashed-line box labelled 120 includes some supplemental circuitry. In particular, MOS transistors 122 and 130 have been added. These thick oxide field NMOS transistors 122 and 130 are connected between the grounded collector and the emitter or their respective parasitic BJTs 76 and 88. This addition implies that an additional conductive path may be formed during high voltage conditions (e.g., ESD conditions) when the threshold voltage of the thick oxide over the base of the respective parasitic BJT 76 or 88 is exceeded. When the threshold voltage of the thick oxide over the base of one of the parasitic BJTs 76 or 88 is exceeded, the respective thick oxide field NMOS transistor 122 or 130 creates a short circuit to assist during the ESD condition. For example, if a positive potential is applied at the input node 68 during an ESD condition, the gate 124 of transistor 122 will be forward biased, causing the drain 126 and the source 128 to be tied together. This puts the collector 80 and the emitter 78 of the parasitic BJT 76 at the same potential, which form a low resistance path, and the ESD pulse will be further assisted in its dissipation to ground. Note that the other thick oxide field NMOS transistor 130 operates identically. Although the invention has been particularly shown and described with reference to a preferred embodiment thereof, it will be understood by those skilled in the art that changes in form and detail may be made therein without departing from the spirit and scope of the invention.

Claims: WHAT IS CLAIMED IS: 1. A multi-frequency voltage regulating circuit comprising a magnetic field power sensor circuit. 2. The circuit in accordance with Claim 1 further comprising a programmable magnetic field detection circuit coupled to the magnetic field power sensor circuit. 3. The circuit in accordance with Claim 2 further comprising a discharge expediter circuit coupled to the programmable magnetic field detection circuit. 4. The circuit in accordance with Claim 3 further comprising: a magnetic field converter circuit; a rectifier circuit coupled to the magnetic field converter circuit; a voltage clamping circuit coupled to the magnetic field power sensor circuit; and a charging circuit coupled to the voltage clamping circuit. 5. The circuit in accordance with Claim 1 wherein the magnetic field power sensor circuit comprises: an input current; an input current divider circuit coupled to the input current; an input current multiplier circuit coupled to the input current divider circuit; a reference current coupled to the input current multiplier circuit; and a comparator coupled to the input current multiplier circuit. 6. The circuit in accordance with Claim 5 wherein the source of the input current is the output of the voltage clamping circuit. 7. The circuit in accordance with Claim 5 wherein the input current divider circuit comprises at least one NMOS transistor. 8. The circuit in accordance with Claim 7 wherein: the gate and drain connectors of each of the at least one NMOS transistor are coupled to the input current; and the source connectors of each of the at least one NMOS transistor are coupled to a ground reference. 9. The circuit in accordance with Claim 5 wherein the input current multiplier circuit comprises a second at least one NMOS transistor. 10. The circuit in accordance with Claim 9 wherein: the gate connectors of each of the second at least one NMOS transistor are coupled to the input current divider circuit and to the input current; the drain connectors of each of the second at least one NMOS transistor are coupled to the reference current; and the source connectors of each of the second at least one NMOS transistor are coupled to a ground reference. 11. The circuit in accordance with Claim 5 wherein one input of the comparator is coupled to a voltage induced by the reference current and a second input of the comparator is coupled to a bias voltage source. 12. The circuit in accordance with Claim 2 wherein the programmable magnetic field detection circuit comprises: 0 a plurality of comparators; and a multiplexer. 13. The circuit in accordance with Claim 12 wherein one input of each of the plurality of comparators is coupled to an output of an inductor-capacitor magnetic field converter circuit. 5 14. The circuit in accordance with Claim 13 wherein each output of the plurality of comparators are coupled to inputs of the multiplexer. 15. The circuit in accordance with Claim 13 wherein a second input of at least one of the o plurality of comparators is coupled to a voltage induced by the reference current. 16. The circuit in accordance with Claim 13 wherein a second input of at least one of the plurality of comparators is coupled to a bias voltage source. 17. The circuit in accordance with Claim 12 wherein an output of the comparator of the magnetic field sensor circuit is coupled to an input select of the multiplexer. 18. The circuit in accordance with Claim 3 wherein the discharge expediter circuit is comprised of: a decoder; and at least one discharge path. 0 19. The circuit in accordance with Claim 18 wherein the at least one discharge path is comprised of: a transistor; and a resistor coupled to the transistor. 5 20. The circuit in accordance with Claim 18 wherein the expediter circuit provides the at least one discharge path for discharging excess electrical energy induced by a magnetic field. 21. The circuit in accordance with Claim 19 wherein an impedance value of the resistor o optimizes the efficiency of the at least one discharge path for a specific magnetic field strength. 22. The circuit in accordance with Claim 19 wherein the decoder provides a programmable signal to the transistor for activating the at least one discharge path. 23. The circuit in accordance with Claim 4 wherein the charging circuit comprises: a transistor switch; a transistor biasing resistor coupled to a gate connector of the transistor switch; a diode and resistor in parallel coupled to a source connector of the transistor switch; a battery coupled to the diode and resistor; and an energy storage device coupled to the diode and resistor. 24. The circuit in accordance with Claim 4 wherein the voltage clamping circuit comprises: a zener diode; and a capacitor coupled in parallel to the zener diode. 25. The circuit in accordance with Claim 4 for communicating digital data over a magnetic field. 26. The circuit in accordance with Claim 5 for determining an energy level of an incoming magnetic field by varying at least one of the following parameters: the reference current; a current mirror ratio; and a zener diode breakdown voltage. 27. The circuit in accordance with Claim 5 wherein the reference current is varied by analog means. 28. The circuit in accordance with Claim 5 wherein the reference current is varied by discrete means. 29. A multi-frequency voltage regulating circuit comprising: a magnetic field power sensor circuit; a programmable magnetic field detection circuit coupled to the magnetic field power sensor circuit; and a discharge expediter circuit coupled to the programmable magnetic field detection circuit. 30. The circuit in accordance with Claim 29 further comprising: a magnetic field converter circuit; a rectifier circuit coupled to the magnetic field converter circuit; a voltage clamping circuit coupled to the magnetic field power sensor circuit; and a charging circuit coupled to the voltage clamping circuit.

Inventors: SCHIEKE PETER, SMIT WILLEM, SCHIEKE, PETER, SMIT, WILLEM
Applicants: MICROCHIP TECH INC, MICROCHIP TECHNOLOGY INCORPORATED
Application year: 1999
Main classification: H04B5
IPC codes: G01R33, H02J7, H02M7, H04B5