Image sensor

Abstract: This invention has as its object to provide an image sensor chip and an image sensor using the image sensor chip capable of reducing random noise in the image sensor chip to obtain a high-quality image. An image sensor chip having a plurality of light-receiving element includes a noise reduction circuit for reducing random noise contained in an output signal from the light-receiving element in the ON state and outputting the random noise contained in the output signal from the light-receiving element without any processing in the OFF state, a first control circuit for controlling the ON/OFF state of the noise reduction circuit, a clamp circuit for clamping an output signal output through the noise reduction circuit to a reference potential, and a second control circuit for controlling an ON/OFF state of the clamp circuit. An image sensor chip and an image sensor formed by arraying a plurality of image sensor chips are also provided.

Description: Conventionally, a contact-type image sensor (linear image sensor) constituted by arraying light-receiving elements such as photodiodes on a line to directly read image information of an original or the like is often used in an image reading apparatus such as a facsimile apparatus, a digital copying machine, or a scanner. A plurality of image sensor chips serially arrayed in the contact-type image sensor are formed from silicon wafers. For this reason, the sensor length is limited by the wafer size, so an image sensor chip having the same length as the read original width can hardly be manufactured. Hence, conventionally, an imaging optical system is used to form a reduced image of a read original and read the image of the original. However, an apparatus using the reduction imaging optical system requires a space for the optical system and can hardly be made compact. In addition, it is difficult to obtain a sufficient resolution. To solve the above problems, a so-called contact-type image sensor formed by linearly arraying a plurality of image sensor chips is popularly used. Conventional contact-type image sensors are disclosed in, e.g., European Patent Application Nos. EP-A-0 382 540 and EP-A-0 382 568 or "High-Speed, High-Gradation Contact-type Linear Sensor (BASIS Type) Multi-chip Contact Sensor", Journal of Television Society, Vol. 16, No. 58, September 25, 1992. Fig. 1 is a schematic view showing a conventional image sensor. Referring to Fig. 1, each of image sensor chips 1-1 to 1-m has n light-receiving elements 2-1-1 to 2-1-n arrayed on a line in the x direction. The chip 1-1 also has a selection circuit 3-1 for sequentially selecting the outputs from the light-receiving elements 2-1-1 to 2-1-n, i.e., reading light signals by the light-receiving elements. The chip 1-1 also has a delay circuit 11-1 for delaying the start signal for the read operation of the light-receiving elements. The chip 1-1 also has a clamp circuit 4-1 for clamping the output signal line of the selection circuit 3-1 to a reference potential Vref after the start signal is input and until the selection circuit 3-1 starts the light signal read operation by the light-receiving elements 2-1-1 to 2-1-n. The image sensor also has an amplification circuit 12-1 which is operated by the start signal to amplify the output from the clamp circuit 4-1. The output from the amplification circuit is output from the chip through an output signal line 5-1. The delay circuit 11-1 is driven by an external driving circuit through an input signal line 8-1. A control circuit 6-1 for outputting an ON/OFF switch control signal to the clamp circuit 4-1 is driven by an external driving circuit through the input signal line 8-1. A control circuit 13-1 for outputting an ON/OFF switch control signal to the amplification circuit 12-1 is driven by an external driving circuit through the input signal line 8-1. The reference voltage Vref is supplied from an external bias circuit through a reference voltage input line 10-1. The reference voltage input lines 10-1 to 10-m are short-circuited outside the chips, so the common reference voltage Vref is supplied to all chips. Each of the image sensor chips 1-2 to 1-m has the same arrangement as that of the image sensor chip 1-1, and the same reference numerals as in the image sensor chip 1-1 denote the same parts in these image sensor chips. The image sensor chips 1-1 to 1-m are arrayed on a line in the x direction, so a total of n x m light-receiving elements are arrayed on a line in the x direction to form a contact-type image sensor. In reading an image, an original holding the read image is conveyed in the y direction relative to the contact-type image sensor while making the original correspond to the light-receiving elements in units of lines. The outputs from all light-receiving elements of the image sensor chip 1-1 are sequentially selected by the selection circuit 3-1, and externally output from the output signal line 5-1 through the clamp circuit 4-1 and amplification circuit 12-1. Subsequently, the outputs from all light-receiving elements of the chip 1-2 are sequentially selected by a selection circuit 3-2 and externally output from an output signal line 5-2. In this manner, outputs from all light-receiving elements are time-serially output. In the conventional so-called contact-type image sensor formed by arraying a plurality of image sensor chips on a line, random noise is generated in the section from each light-receiving element to the clamp circuit of each chip, and a variation in clamp level in units of linearly arrayed image sensor chips appears as shade on the image. The image sensor of the type considered herein, is of a type such as disclosed in European Patent Application EP-A-0382568 which includes: an array of image sensor chips each having a plurality of light-receiving elements, and a clamp circuit to clamp an output signal of said plurality of light-receiving elements to a reference potential; and control means to control the reading operation of the light-receiving elements of each image sensor chip, and to control the ON/OFF state of the clamp circuit of each image sensor chip. It is now sought to reduce the shade on an image that is due to a variation in clamp level from image sensor chip to image sensor chip so as to improve image quality. The image sensor is, in accordance with the present invention, characterised in that: each image sensor chip includes a noise reduction circuit interposed between the respective plurality of light-receiving elements and the respective clamp circuit to reduce noise generated between the respective light receiving elements and the respective clamp circuit, which noise reduction circuit is operable in an ON state to reduce the noise and output an output signal with a reduced noise content, and is operable in an OFF state to output an output signal from the light receiving elements without performing noise reduction; and said control means includes means to control the ON/OFF state of the noise reduction circuit of each respective image sensor chip, and is operable to control the reading operation of the light-receiving elements of the respective image sensor chips, the ON/OFF states of the respective clamp circuits, and the ON/OFF states of the respective noise reduction circuits whereby the noise reduction circuit of one of the image sensor chips is operated by being switched ON for a predetermined period of time before being switched OFF, and the clamp circuit of the same one of the image sensor chips is operated only while the noise reduction circuit is ON, while reading operation is still being performed for the light receiving elements of the preceding image sensor chip and before the reading operation of the light receiving elements of said one of the image sensor chips is started. In the image sensor aforesaid, each image sensor may include both a first control circuit to control the ON/OFF state of its noise reduction circuit, and a second control circuit to control the ON/OFF state of its clamp circuit, each as part of said control means. Examples of noise reduction circuit that can be employed in the image sensor aforesaid include either a low pass filter that comprises means of limiting the frequency band of the output signals of the light receiving elements, or an averaging circuit that comprises sampling means for sampling the output signal from one of the light-receiving elements a plurality of number of times, and averaging means for outputting an average value of sample values obtained by said sampling means. With regard to the prior art it is acknowledged that image sensor chips including functional means for performing noise reduction and for performing signal clamping, have been known previously. Of particular note, Patent Abstract of Japan vol. 1997 No. 09, 30 September 1997 and Japanese Laid Open Patent Application No. JP-A-09 116757 discloses an image sensor chip that has a correlated double sampling circuit (CDS) for performing noise reduction and a frequency divider circuit to generate and apply a clamp signal to the CDS circuit. When no clamp signal is provided, the CDS circuit outputs a raw image signal from a CCD sensor, whilst when the clamp signal is provided, a signal of reduced noise content is output. In the accompanying drawings:- Fig. 1 is a schematic view showing a conventional image sensor; Fig. 2 is a schematic view showing an image sensor according to the first embodiment of the present invention; Fig. 3 is a timing chart for explaining the operation of the first embodiment; Fig. 4 is a circuit diagram showing an image sensor and, more particularly, a noise reduction circuit and clamp circuit according to the second embodiment of the present invention; Fig. 5 is a timing chart for explaining the operation of the second embodiment; Fig. 6 is a block diagram showing an image sensor and, more particularly, a noise reduction circuit and clamp circuit according to the third embodiment of the present invention; Fig. 7 is a timing chart for explaining the operation of the third embodiment; and Fig. 8 is a view showing an image input apparatus using an image sensor. DESCRIPTION OF THE PREFERRED EMBODIMENTS Fig. 2 is a schematic view showing an image sensor according to the first embodiment of the present invention. Referring to Fig. 2, an image sensor chip 1-1 has n light-receiving elements 2-1-1 to 2-1-n as photoelectric conversion elements such as photodiodes or phototransistors arrayed on one line in the x direction. The chip 1-1 also has a selection circuit 3-1 for sequentially time-serially selecting the outputs from the light-receiving elements 2-1-1 to 2-1-n, i.e., reading light signals by the light-receiving elements. A transfer switch for transferring optical charges detected by a light-receiving element, a source follower amplification circuit for converting the transferred optical charges into a voltage and outputting the voltage to the selection circuit, and a selection switch for activating the amplification circuit and selectively outputting the voltage may be inserted into the path from the light-receiving element to the selection circuit to output a signal voltage corresponding to the optical charges from the light-receiving element. A capacitor for temporarily storing the signal voltage is used for the selection circuit 3-1, so a time-series signal voltage can be obtained by a scanning switch for outputting the voltage to the signal output line using a shift register (not shown). The image sensor chip 1-1 has a delay circuit 11-1 for delaying the start signal for the read operation by the light-receiving elements. The delay time of the start signal corresponds to the time until noise is reduced and a level to be clamped is detected. The chip 1-1 also has a noise reduction circuit 7-1 for reducing random noise contained in the output signal line of the selection circuit 3-1 after the start signal is input and until the selection circuit 3-1 starts light signal reading by the light-receiving elements. Also, a clamp circuit 4-1 is formed to clamp the signal voltage from the output signal line connected to the noise reduction circuit 7-1 to a reference potential Vref supplied from an external circuit of the chip during the operation of the noise reduction circuit 7-1. An amplification circuit 12-1 which is activated by the start signal to amplify the output from the clamp circuit 4-1 is also formed. The output from the amplification circuit 12-1 is output from the chip through an output signal line 5-1. The delay circuit 11-1 is driven by an external driving circuit through an input signal line 8-1. A control circuit 9-1 for outputting an ON/OFF switch control signal to the noise reduction circuit 7-1 is driven by an external driving circuit through the input signal line 8-1. A control circuit 6-1 for outputting an ON/OFF switch control signal to the clamp circuit 4-1 is driven by an external driving circuit through the input signal line 8-1. A control circuit 13-1 for outputting an ON/OFF switch control signal to the amplification circuit 12-1 is driven by an external driving circuit through the input signal line 8-1. The reference voltage Vref is supplied from an external bias circuit through a reference voltage input line 10-1. The reference voltage input lines 10-1 to 10-m to which the reference voltage Vref is supplied are short-circuited outside the chips, so the common reference voltage Vref is supplied to all chips. Each of the image sensor chips 1-2 to 1-m has the same arrangement as that of the image sensor chip 1-1, and the same reference numerals as in the image sensor chip 1-1 denote the same parts in these image sensor chips. The image sensor chips 1-1 to 1-m are arrayed on a line in the x direction, so a total of n x m light-receiving elements are arrayed on a line in the x direction. In reading an image, an original bearing the read image is conveyed in the y direction relative to the image sensor while making the original correspond to the light-receiving elements in units of lines. Assume that one line corresponds to the A4 width of 210 mm, the image read resolution is 600 dpi, and the number of chips is 15. One light-receiving element is present in a width of 42.3 µm, so about 333 light-receiving elements are arrayed in a one chip width of 14 mm. The outputs from all light-receiving elements of the image sensor chip 1-1 are sequentially selected by the selection circuit 3-1 one by one in units of light-receiving elements and output from the chip through the output signal line 5-1. Subsequently, the outputs from all light-receiving elements of the next chip 1-2 are sequentially selected by a selection circuit 3-2 one by one in units of light-receiving elements and output from the chip through an output signal line 5-2. In this manner, the outputs from all light-receiving elements of one line are time-serially output. Fig. 3 is a timing chart for explaining the operation of this embodiment. Referring to Fig. 3, 8-1 is a start signal of the input signal line 8-1, 1-1 is an output control signal from the delay circuit 11-1 in the image sensor chip 1-1, 2-1 is an output control signal from the first control circuit 9-1 in the image sensor chip 1-1, 3-1 is an output control signal from the second control circuit 6-1 in the image sensor chip 1-1, 4-1 is an output control signal from the third control circuit 13-1 in the image sensor chip 1-1, and Voutl is an output from the noise reduction circuit 7-1 in the image sensor chip 1-1. The output control signal 1-1 is generated by the delay circuit 11-1 driven by the input signal line 8-1, i.e., output with a predetermined delay time after the input of the start signal. During only this period, light signals are read by the light-receiving elements. The output control signal 2-1 from the first control circuit 9-1 is output in synchronism with the start signal of the input signal line 8-1, i.e., output during only a specific period after the start signal is input and until the selection circuit 3-1 starts light signal reading by the light-receiving elements. During only this period, the noise reduction circuit 7-1 is activated to output Voutl whose noise is reduced by, e.g., a noise filter for removing high-frequency noise. The output control signal 3-1 from the second control circuit 6-1 is output in synchronism with the start signal of the input signal line 8-1 or in synchronism with the start signal with a short delay, i.e., during only a specific period in the ON period of the noise reduction circuit 7-1. During only this period, the clamp circuit 4-1 is activated to clamp the output Voutl after noise reduction to the reference potential Vref. When the output Voutl is clamped to the reference potential Vref, a light reception voltage is read from each light-receiving element in the chip on the basis of the sum of the output Voutl and reference potential Vref. The output control signal 4-1 from the third control circuit 13-1 is output in synchronism with the start signal of the input signal line 8-1. That is, the amplification circuit 12-1 is activated simultaneously with input of the start signal. As shown in Fig. 3, output of the signal 3-1 is ended when or before output of the signal 2-1 is ended. Subsequently, in the image sensor chips 1-2 to 1-m, output control signals 2-2 to 2-m from first control circuits 9-2 to 9-m and output control signals 3-2 to 3-m from second control circuit 6-2 to 6-m are output in synchronism with the start signals of input signal lines 8-2 to 8-m, respectively, clamp circuits 4-2 to 4-m are activated during the ON period of noise reduction circuits 7-2 to 7-m, respectively, and outputs Vout2 to Voutm after noise reduction are clamped to the reference potential Vref. The operation of each noise reduction circuit and clamp voltage detection are completed before the read of the final light-receiving element in the preceding image sensor chip is ended. Subsequent to the read of the final light-receiving element in the preceding chip, the first light-receiving element in the next image sensor chip is read using the clamp voltage of this chip. Hence, the read timings for a series of light-receiving elements suffer no delay. In the above-described manner, in each image sensor chip, the noise reduction circuit is activated during a specific period after the start signal is input and until the light-receiving elements start reading light signals, and the output signal after noise reduction is clamped to the reference voltage by the clamp circuit. With this operation, a variation in clamp level in units of linearly arrayed image sensor chips due to random noise contained in the section from each light-receiving element to the clamp circuit is reduced, so shade differences in light amount between the chips can be decreased. Fig. 4 is a circuit diagram showing an image sensor and, more particularly, a noise reduction circuit and clamp circuit according to the second embodiment of the present invention. This embodiment is different from the first embodiment in a block A represented by a dotted line in the first embodiment, and Fig. 4 shows only a corresponding block of the second embodiment. Referring to Fig. 4, a noise reduction circuit 7-1 is constructed by a low-pass filter circuit 14-1 comprising a first analog switch circuit SW1, a resistor R1, a capacitor C1, and an output buffer circuit B1, and second and third analog switches SW2 and SW3. The transfer path, in the noise reduction circuit, of the signal time-serially output from each light-receiving element through a selection circuit 3-1 is controlled by the second and third analog switches. More specifically, when the first and second analog switches are in a conducting state (ON), and the third analog switch is in an unconducting state (OFF), the output signal from the selection circuit 3-1 is output from the noise reduction circuit through the low-pass filter circuit. On the other hand, when the first and second analog switches are OFF, and the third analog switch is ON, the output signal from the selection circuit is output from the noise reduction circuit through the third analog switch without any processing. A clamp circuit 4-1 is comprised of a coupling capacitor C2, a fourth analog switch circuit SW4, and an output buffer circuit B2. The output signal from the noise reduction circuit is input to one terminal (point A) of the coupling capacitor C2 of the clamp circuit 4-1, so only the AC component of the output signal is output from the other terminal (point B). The fourth analog switch circuit is connected between the point B and a reference potential input line 10-1. When the fourth analog switch is ON, the potential at the point B is short-circuited to a reference potential Vref. When the fourth analog switch is OFF, the point B is open to the reference potential Vref. That is, the potential at the point B can be clamped to the reference potential Vref by turning on the fourth analog switch and then turning off the fourth analog switch. A control circuit 9-1 for outputting an ON/OFF switch control signal to the first, second, and third analog switches in the noise reduction circuit 7-1 is driven by an external driving circuit through an input signal line 8-1. A control circuit 6-1 for outputting an ON/OFF switch control signal to the fourth analog switch in the clamp circuit 4-1 is driven by an external driving circuit through the input signal line 8-1. The reference voltage Vref is supplied from an external bias circuit through the reference voltage input line 10-1. The reference voltage input lines 10-1 to 10-m are short-circuited outside the chips, so the common reference voltage Vref is supplied to all chips. Fig. 5 is a timing chart for explaining are example of the operation of the second embodiment. Referring to Fig. 5, 1-1 is an output control signal output from the first control circuit 9-1 in an image sensor chip 1-1 to control the ON/OFF state of the first and second analog switches, 2-1 is an output control signal output from the first control circuit 9-1 in the image sensor chip 1-1 to control the ON/OFF state of the third analog switch, 3-1 is an output control signal output from the second control circuit 6-1 in the image sensor chip 1-1 to control the fourth analog switch, and Voutl is an output from the noise reduction circuit 7-1 in the image sensor chip 1-1. The signals 1-1 and 2-1 are output in synchronism with the start signal of the input line 8-1, i.e., output during only a specific period except a period when the light-receiving elements of the chip 1-1 read light signals. The first and second analog switches are turned on, and the third analog switch is turned off. The noise reduction circuit 7-1 is activated to obtain an output Voutl whose noise is reduced. The signal 3-1 is output in synchronism with the start signal of the input line 8-1 or in synchronism with the start signal with a short delay, i.e., during only a specific period in the ON period of the noise reduction circuit 7-1. When the fourth analog switch is turned on and then turned off, the output Voutl after noise reduction is clamped to the reference potential Vref. As described above, when the low-pass filter circuit 14-1 built by a resistor and a capacitor is used in the noise reduction circuit 7-1, the band of the output signal from the selection circuit 3-1 is limited. When the output signal after noise reduction is clamped to the reference potential by the clamp circuit, a variation in clamp level in units of linearly arrayed image sensor chips due to random noise contained in the section from each light-receiving element to the clamp circuit can be reduced. In this embodiment as well, the operation of each noise reduction circuit and clamp voltage detection are completed before the read of the final light-receiving element in the preceding image sensor chip is ended. Subsequent to the read of the final light-receiving element in the preceding chip, the first light-receiving element in the next image sensor chip is read using the clamp voltage of this chip. Hence, the read timings for a series of light-receiving elements have no delay. Fig. 6 is a circuit diagram showing an image sensor and, more particularly, a noise reduction circuit and clamp circuit according to the third embodiment of the present invention. This embodiment is different from the first embodiment in a block A represented by a dotted line in the first embodiment, and Fig. 6 shows only a corresponding block of the third embodiment. Referring to Fig. 6, a noise reduction circuit 7-1 is constituted by an averaging circuit 15-1 comprising first and second analog switch circuits SW1 and SW2, first and second capacitors C1 and C2, and an output buffer circuit B1, and third and fourth analog switch circuits SW3 and SW4. In the averaging circuit 15-1, first, the first and second analog switches are simultaneously turned on to send the output signal from a selection circuit 3-1 to the first and second capacitors. Then, the first and second analog switches are turned off to store a potential V1 of the output signal in the first and second capacitors. After this, the first analog switch is turned on, and the second analog switch is turned off to send the output signal from the selection circuit to the first capacitor. Subsequently, the first analog switch is turned off to store a potential V2 of the output signal in the first capacitor. Next, the first analog switch is turned off, and the second analog switch is turned on to short-circuit the first and second capacitors, so the potential V2 of the output signal stored in the first capacitor and the potential V1 of the output signal stored in the second capacitor are averaged. Finally, the second analog switch is turned off to store the average value of the potentials V1 and V2 of the output signals in the first and second capacitors. In the above-described manner, potentials V3 to Vk of output signals are stored in the first capacitor at the OFF timing of the first analog switch, and the average value of each potential and the potential of the second capacitor is stored. With this operation, the average value of the potentials stored in the first capacitor at the respective timings is stored in the second capacitor. The transfer path, in the noise reduction circuit, of the signal output from the selection circuit is controlled by the third and fourth analog switches. More specifically, when the third analog switch is ON, and the fourth analog switch is OFF, the output signal from the selection circuit is output from the noise reduction circuit through the averaging circuit. On the other hand, when the third analog switch is OFF, and the fourth analog switch is ON, the output signal from the selection circuit is output from the noise reduction circuit through the fourth analog switch without any processing. A clamp circuit 4-1 is composed of a coupling capacitor C3, a fifth analog switch circuit SW5, and an output buffer circuit B2. The output signal from the noise reduction circuit is input to one terminal (point A) of the coupling capacitor of the clamp circuit, so only the AC component of the output signal is output from the other terminal (point B). The fifth analog switch circuit is connected between the point B and a reference potential input line 10-1. When the fifth analog switch is ON, the potential at the point B is short-circuited to a reference potential Vref. When the fifth analog switch is OFF, the point B is open to the reference potential Vref. That is, the potential at the point B can be clamped to the reference potential Vref by turning on the fifth analog switch and then turning off the fifth analog switch. A control circuit 9-1 for outputting an ON/OFF switch control signal to the first, second, third, and fourth analog switches in the noise reduction circuit 7-1 is driven by an external driving circuit through an input signal line 8-1. A control circuit 6-1 for outputting an ON/OFF switch control signal to the fifth analog switch in the clamp circuit 4-1 is driven by an external driving circuit through the input signal line 8-1. The reference voltage Vref is supplied from an external bias circuit through the reference voltage input line 10-1. The reference voltage input lines 10-1 to 10-m are short-circuited outside the chips, so the common reference voltage Vref is supplied to all chips. Fig. 7 is a timing chart for explaining one example of the operation of the third embodiment. Referring to Fig. 7, 1-1 is an output control signal output from the first control circuit 9-1 in an image sensor chip 1-1 to control the ON/OFF state of the first analog switch, 2-1 is an output control signal output from the first control circuit 9-1 in the image sensor chip 1-1 to control the ON/OFF state of the second analog switch, 3-1 is an output control signal output from the first control circuit 9-1 in the image sensor chip 1-1 to control the ON/OFF state of the third analog switch, 4-1 is an output control signal output from the first control circuit 9-1 in the image sensor chip 1-1 to control the ON/OFF state of the fourth analog switch, 5-1 is an output control signal output from the second control circuit 6-1 in the image sensor chip 1-1 to control the ON/OFF state of the fifth analog switch, Vin is an input to the noise reduction circuit 7-1 in the image sensor chip 1-1, V c2 is a potential of the second capacitor of the noise reduction circuit 7-1 in the image sensor chip 1-1, and Voutl is an output from the noise reduction circuit 7-1 in the image sensor chip 1-1. The signals 1-1 and 2-1 are output in synchronism with the start signal of the input signal line 8-1, i.e., output during only a specific period except a period when the light-receiving elements of the chip 1-1 read light signals, to operate the averaging circuit. The potentials V1 to Vk of the output signals are stored in the first capacitor at the OFF timing of the first analog switch. The average value of each of the potentials V1 to Vk stored in the first capacitor at the respective timing and the potential of the second capacitor is input, so the average value of the potentials stored in the first capacitor at the respective timings is stored in the second capacitor. The signals 3-1 and 4-1 are output in synchronism with the start signal of the input signal line 8-1, i.e., output during only a specific period except a period when the light-receiving elements of the chip 1-1 read light signals. The third analog switch is turned on, and the fourth analog switch is turned off. The noise reduction circuit 7-1 is activated to obtain an output Voutl whose noise is reduced. The signal 5-1 is output in synchronism with the start signal of the input signal line 8-1, i.e., during only a specific period in the ON period of the noise reduction circuit 7-1. When the fifth analog switch is turned on and then turned off, the output Voutl after noise reduction is clamped to the reference potential Vref. In this way, the averaging circuit built by the first and second analog switch circuits, first and second capacitors, and the output buffer circuit is used to sample the potential of the output signal from the selection circuit 3-1 a plurality of number of times. The average value of the sample values is calculated to reduce noise of the output signal. When the output signal after noise reduction is clamped to the reference potential by the clamp circuit, a variation in clamp level in units of linearly arrayed image sensor chips due to random noise contained in the section from each light-receiving element to the clamp circuit can be reduced. Shade differences in image signal amount between the chips can be decreased, and a uniform image signal can be obtained for one line. Hence, a high-quality image signal without any variations can be obtained as an entire two-dimensional image by the image sensor. As described above, according to the first to third embodiments, while the clamp circuit for clamping the output signal from a light-receiving element in each image sensor chip is in operation, the noise reduction circuit for reducing random noise contained in the output signal from the light-receiving element is activated. With this arrangement, any shade on the image due to a variation in clamp level in units of linearly arrayed image sensor chips can be reduced. In addition, shade differences in image signal amount between the chips can be decreased, and a uniform image signal can be obtained for one line from the image sensor chip string formed by linearly arraying a plurality of chips. Hence, a high-quality image signal without any variations can be obtained as an entire two-dimensional image by the image sensor. In the first to third embodiments, instead of forming the first control circuit 9-1, second control circuit 6-1, and third control circuit 13-1 in the image sensor chip, the noise reduction circuit 7-1, clamp circuit 4-1, and control circuit 13-1 may be controlled by external control signals. The noise reduction circuit is not limited to the circuit arrangement of the second or third embodiment and may have another circuit arrangement capable of reducing random noise. An image input apparatus using the image sensor described in any one of the first to third embodiments will be described as the fourth embodiment of the present invention. An image input apparatus shown in Fig. 8 comprises a transparent supporter 36, an LED light source 35 for irradiating the supporter 36 with red, green, and blue light beams, a lens array 34 for focusing the light reflected by an original and forming the image of light on the surface of a light-receiving element, an image sensor 31 arranged on a ceramic substrate 32 to photoelectrically convert the reflected light focused by the lens array 34, and a chip coat agent 33 such as silicone resin for protecting the image sensor 31. These members are assembled into an image input apparatus. When the LED light source 35 emits only red light, the image sensor 31 is driven to read red information. Subsequently, green and blue information are read. When the pieces of color information of the original are synthesized by image processing, the color original can be read without using any color filters. In this embodiment, as a signal for controlling the start of emission of the LED light source 35, the start signal for the first chip of the image sensor described in any one of the first to third embodiments is used. As a signal for controlling the end of emission of the LED light source 35, a signal output from a selection circuit 3-m for reading a signal from the final light-receiving element of the mth chip is used. With this arrangement, only when all image sensor chips 1-1 to 1-m on the mounting substrate 32 are in operation, the LED light source 35 is turned on. Many widely different embodiments of the present invention may be constructed without departing from the scope of the present invention. It should be understood that the present invention is not limited to the specific embodiments described in the specification, except as defined in the appended claims.

Claims: An image sensor including: an array of image sensor chips (1-1,1-2,...1-m) each having a plurality of light-receiving elements (2-1-1 to 2-1-n, 2-2-1 to 2-2-n, ... 2-m-1 to 2-m-n), and a clamp circuit (4-1, 4-2, .... 4-m) to clamp an output signal of said plurality of light-receiving elements to a reference potential (V ref); and control means (-,6-1,8-1,11-1,13-1; 6-2, 8-2, 11-2,13-2; ...6-m,8-m,11-m,13-m) to control the reading operation of the light-receiving elements of each image sensor chip, and to control the ON/OFF state of the clamp circuit of each image sensor chip; which image sensor is characterised in that : each image sensor chip (1-1,1-2,...1-m) includes a noise reduction circuit (7-1,7-2,...7-m) interposed between the respective plurality of light-receiving elements (2-1-1 to 2-1-n, 2-2-1 to 2-2-n, ...2-m-1 to 2-m-n) and the respective clamp circuit (4-1,4-2, ...4-m) to reduce noise generated between the respective light receiving elements (2-1-1 to 2-1-n, 2-2-1 to 2-2-n,...2-m-1 to 2-m-n) and the respective clamp circuit, which noise reduction circuit is operable in an ON state to reduce the noise and output an output signal with a reduced noise content, and is operable in an OFF state to output an output signal from the light receiving elements without performing noise reduction; and said control means (-,6-1,8-1,11-1,13-1; 6-2,8-2,11-2,13-2;...6-m,8-m,11-m,13-m) includes means (9-1,9-2,...9-m) to control the ON/OFF state of the noise reduction circuit of each respective image sensor chip, and is operable to control the reading operation of the light-receiving elements of the respective image sensor chips, the ON/OFF states of the respective clamp circuits, and the ON/OFF states of the respective noise reduction circuits whereby the noise reduction circuit (7-2,...7-m) of one of the image sensor chips (1-2,...1-m) is operated by being switched ON for a predetermined period of time before being switched OFF, and the clamp circuit (4-2,...4-m) of the same one of the image sensor chips is operated only while the noise reduction circuit is ON, while reading operation is still being performed for the light receiving elements (2-1-1 to 2-1-n) of the preceding image sensor chip (1-1,...) and before the reading operation of the light receiving elements (2-2-1 to 2-2-n) of said one of the image sensor chips is started. An image sensor according to claim 1 wherein each image sensor chip (1-1,1-2,...1-m) includes both a first control circuit (9-1,9-2,...9-m) to control the ON/OFF state of its noise reduction circuit (7-1,7-2,...7-m), and a second control circuit (6-1,6-2,...6-m) to control the ON/OFF state of its clamp circuit (4-1,4-2,...4-m), each as part of said control means. A sensor according to either preceding claim wherein each image sensor chip (1-1,1-2,...1-m) includes a respective selection circuit (3-1,3-2,...3-m) for sequentially selecting output signals from the respective plurality of light receiving elements (2-1-1 to 2-1-n, 2-2-1 to 2-2-n,...2-m-1 to 2-m-n) and inputting the signals to the respective noise reduction circuit (7-1,7-2,...7-m). A sensor according to any preceding claim wherein each noise reduction circuit comprises means of limiting the frequency band of the output signals of the light receiving elements. A sensor according to any preceding claim 1 to 3 wherein each noise reduction circuit comprises: sampling means for sampling the output signal from one of the light-receiving elements a plurality of number of times, and averaging means for outputting an average value of sample values obtained by said sampling means.

Inventors: INUI FUMIHIRO, KOZUKA HIRAKU, SAKURAGI TAKAMASA, INUI, FUMIHIRO, KOZUKA, HIRAKU, SAKURAGI, TAKAMASA
Applicants: CANON KK, CANON KABUSHIKI KAISHA
Application year: 1999
Main classification: H04N1
IPC codes: H04N5, H01L27, H04N1