A RECEIVER AND A VARIABLE FREQUENCY SIGNAL GENERATING CIRCUIT FOR THE RECEIVER

Abstract: A narrow band radio receiver (1) comprises a signal mixer (5) which mixes the received signal with a variable frequency output signal received from a variable frequency signal generating circuit (6). A signal, the frequency of which is the difference between the frequencies of the received signal and the variable frequency output signal is relayed to an intermediate filter (10) which filters out signals of frequencies other than an intermediate frequency, which is similar to the difference frequency. The filtered signal is amplified and demodulated through an amplifier (12), demodulator (14) and is passed through an output circuit (15) where it is read by a microprocessor (16). On the microprocessor (16) determining that the signal is in valid format the signal is outputted through a gate (18). The circuit (6) is in the form of a phase locked loop circuit and a voltage controlled oscillator (23) generates the variable frequency output signal. A phase comparator (25) compares the signal frequency outputted by the voltage controlled oscillator (23) with a constant frequency signal from a signal generator (20) and applies a signal proportional to the phase difference to a control input port (28) of the voltage controlled oscillator (23) through an adder (30). A first switch (SW1) breaks the feedback loop (27) when the circuit has locked-up and a capacitive circuit (36) retains the DC voltage on pin (1) of the adder (30) at the locked-up voltage. The microprocessor (16) through a digital to analogue converter (32) applies a stepped staircase voltage to a pin (2) of the adder (30) which is added to the locked-up voltage which in turn causes the voltage controlled oscillator (23) to sweep the frequency of the variable frequency output signal through incremental frequency steps in a staircase fashion.

Description: "A receiver and a variable frequency signal generating circuit for the receiver" The present invention relates to a receiver, and in particular to a variable frequency radio receiver for receiving, for example, signals of the type transmitted by a keyfob or other such transmitter for use in a remote keyless entry system of a vehicle, for example, a motor vehicle such as, a car, van, truck and the like. The invention also relates to a variable frequency signal generating circuit for providing a variable frequency output signal, and in particular, though not limited to such a variable frequency signal generating circuit for providing a variable frequency output signal to the radio receiver. Remote keyless entry systems, in general, comprise an electronic control unit which controls various components in a motor vehicle, for example, an alarm circuit, a vehicle immobiliser unit, the central locking system of the vehicle and other security aspects of the vehicle which protect the vehicle when unattended. A radio receiver which may be incorporated in the electronic control unit, or may be a stand alone receiver communicating with the electronic control unit receives remotely transmitted signals which are typically transmitted from a remote transmitter, for example, a keyfob transmitter. The transmitted signals, in general, comprise a preamble code followed by a unique code embedded in the signal. The preamble code typically is common to a number of electronic control units of similar type, and the unique code is unique to one specific electronic control unit. On reception of a valid signal with a unique code specific to the electronic control unit the electronic control unit changes the state of the various components of the vehicle which it controls. For example, in the case of an alarm circuit, if the alarm circuit is armed, on reception of a valid unique signal the electronic control unit disarms the alarm circuit, and vice versa. In the case of the vehicle immobiliser unit if the vehicle is immobilised by the immobiliser unit, on reception of the valid unique signal the vehicle immobiliser unit is deactivated from mobilising the vehicle, and vice versa. Similarly, in the case of the central locking system if the doors of the vehicle are locked, on reception of a valid unique signal the electronic control unit operates the central locking system for unlocking the doors, and vice versa. In order to avoid jamming of the transmitted signal it is now common for keyfob transmitters to transmit the signal on two frequencies either simultaneously or sequentially, and furthermore, it is known to vary the frequencies at which the signal is transmitted from transmission to transmission. Accordingly, the radio receiver must be capable of receiving signals over a range of frequencies, and furthermore the radio receiver must be capable of sweeping the frequency range. In general, the frequency range is relatively narrow, however, it is still essential that the radio receiver should be capable of sweeping the frequency range, and in general, it is necessary that the frequency range should be continuously swept. While radio receivers for sweeping through a range of frequencies are known, in general, they suffer from a number of disadvantages. For example, in general, they tend to be of relatively high cost, since in general, it is necessary to provide a relatively accurate frequency source, and a relatively tight tolerance is required on the intermediate frequency filter components. Additionally, in many cases manual fine tuning of the receiver is often necessary during production test. Furthermore, in general, the transmitter must also be provided with a relatively accurate frequency source. There is therefore a need for a variable frequency radio receiver for a remote keyless entry system of a motor vehicle, and there is also a need for a variable frequency radio receiver for other purposes. There is also a need for a variable frequency signal generating circuit for providing a variable output frequency for a radio receiver, and for other purposes. The present invention is directed towards providing such a radio receiver and a variable frequency signal generating circuit According to the invention there is provided a variable frequency signal generating circuit for outputting a variable frequency output signal at a plurality of frequencies within a predetermined frequency range between a predetermined lower frequency and a predetermined upper frequency, wherein the circuit is in the form of a phase locked loop circuit and comprises a variable frequency signal generating means for generating and outputting the variable frequency output signal, the variable frequency signal generating means having a control input port for receiving a control signal for determining the frequency of the variable frequency output signal, a constant frequency signal generating means for generating a constant frequency signal, a phase comparing means for comparing the variable frequency output signal with the constant frequency signal and for outputting a signal indicative of the phase shift between the two signals, a feedback loop for feeding back the signal from the phase comparing means to the control input port of the variable frequency signal generating means for completing the phase locked loop circuit, a first isolating means in the feedback loop for isolating the control input port of the variable frequency signal generating means from the phase comparing means when the circuit has locked-up, a retaining means for holding the signal from the phase comparing means on the control input port of the variable frequency signal generating means after the first isolating means has isolated the control input port from the phase comparing means, a signal varying means for selectively varying the signal on the control input port of the variable frequency signal generating means while the control input port is isolated from the phase comparing means for in turn selectively varying the frequency of the variable frequency output signal, and a control means for operating the first isolating means for isolating the control input port from the phase comparing means and for operating the signal varying means for selectively varying the signal on the control input port when the control input port is isolated from the phase comparing means. In one embodiment of the invention the control means controls the signal varying means for selectively and sequentially incrementing or decrementing the value of the signal on the control input port over a predetermined range of signal values between a predetermined lower signal value and a predetermined upper signal value for sweeping the frequency of the variable frequency output signal through the predetermined frequency range. In another embodiment of the invention the control means controls the signal varying means for holding the signal value on the control input port of the variable frequency signal generating means constant at each signal value within the predetermined range of signal values for a first predetermined time period. Preferably, the control means controls the signal varying means for holding the value of the signal on the control input port of the variable frequency signal generating means constant at selected signal values within the predetermined range of signal values for a second predetermined time period, the second predetermined time period being greater than the first predetermined time period. Advantageously, the control means controls the signal varying means for selectively and sequentially incrementing the signal on the control input port of the variable frequency signal generating means through a plurality of incremental signal value steps from the lower predetermined signal value to the upper predetermined signal value for sweeping the variable frequency output signal through the predetermined frequency range. Ideally, the control means controls the signal varying means for returning the signal value on the control input port to one of the predetermined lower and upper signal values when the signal value on the control input port is at the other of the predetermined lower and upper signal values. In one embodiment of the invention the variable frequency signal generating means comprises a voltage controlled oscillator, and the signal outputted from the phase comparing means is a DC voltage signal when the phase lock loop has locked-up. In another embodiment of the invention the signal varying means comprises a means for selectively and sequentially generating a variable DC voltage, and an adding means for adding the variable DC voltage to the voltage signal from the phase comparing means held on the control input port of the variable frequency signal generating means. In a further embodiment of the invention the adding means comprises a voltage adder. In another embodiment of the invention the signal varying means comprises a digital to analogue converter operating under the control of the control means for outputting the variable DC voltage to the control input port of the variable frequency signal generating means. Preferably, the first isolating means comprises a first switch means operable under the control of the control means, the first switch means being located in the feedback loop between the phase comparing means and the signal varying means. Advantageously, the retaining means is provided by a capacitive retaining circuit connected to the feedback loop between the first isolating means and the signal varying means. Preferably, the capacitive retaining circuit comprises a capacitor connected between the feedback loop and ground. In one embodiment of the invention a first impedance means is provided in the capacitive retaining circuit for smoothing charging of the capacitor during periods when the control input port of the variable frequency signal generating means is communicating with the phase comparing means. In another embodiment of the invention a second isolating means operable under the control of the control means is provided in the capacitive circuit for switching out the first impedance means when the control input port of the variable frequency signal generating means is isolated from the phase comparing means. Preferably, the second isolating means is provided by a second switch means. Advantageously, the control means operates the second isolating means for switching out the first impedance means when the first isolating means is isolating the control input port of the variable frequency signal generating means from the phase comparing means, and vice versa. In one embodiment of the invention a low pass filter for filtering the signal from the phase comparing means to the control input port of the variable frequency signal generating means is provided in the feedback loop. In another embodiment of the invention the comparing means comprises a phase comparator. In a further embodiment of the invention the constant frequency signal generating means comprises a constant frequency generator. In a still further embodiment of the invention the constant frequency generator is provided by a crystal generator. Advantageously, the control means operates the first isolating means periodically for closing the feedback loop for communicating the control input port of the variable frequency signal generating means with the phase comparing means for permitting periodic lock-up of the phase locked loop circuit for avoiding deterioration of the signal on the control input port. Additionally, the invention provides a variable frequency receiver for receiving a remotely transmitted signal with a predetermined reception frequency range, the receiver comprising a receiving means for receiving the remotely transmitted signal, a variable frequency signal generating circuit according to the invention for outputting the variable frequency output signal at a plurality of frequencies within the predetermined frequency range, a mixing means for mixing the received signal with the variable frequency output signal and for outputting the mixed signal at a frequency dependent on the frequency of the variable frequency output signal and the frequency of the received signal, and a means for reading a signal derived from the mixed signal and for determining from the signal derived from the mixed signal if the received signal is a valid signal. In one embodiment of the invention the control means of the variable frequency signal generating circuit acts as the means for reading and determining the validity of the received signal. In another embodiment of the invention the control means of the variable frequency signal generating circuit is responsive to the presence of a valid received signal for controlling the signal varying means for holding the signal value on the control input port of the variable frequency signal generating means constant for in turn holding the frequency of the variable frequency output signal constant for the second predetermined time period for facilitating reception of the received signal. In a further embodiment of the invention the second predetermined time period is of sufficient duration for facilitating reception of at least one valid received signal. In one embodiment of the invention an intermediate filter means is provided for filtering the mixed signal and for outputting a signal filtered from the mixed signal the frequency of which is a predetermined value derived from the difference between the frequencies of the variable frequency output signal and corresponding frequencies at which it is desired to receive the remotely transmitted signal. In another embodiment of the invention a demodulating means is provided for demodulating the signal outputted by the intermediate filter means for extracting data therefrom. In a further embodiment of the invention a gate means is provided for outputting the data extracted from the received signal by the demodulating means, the gate means being operable under the control of the control means for outputting the data in response to the control means determining that the received signal is a valid signal. Preferably, the control means reads the data signal from the demodulating means and the time period between the edges of the demodulated signal for determining if the received signal is of a valid format. Advantageously, the control means controls the gate means for outputting the demodulated signal in response to the control means determining that the data signal is in valid format. In one embodiment of the invention the predetermined frequency range through which the variable frequency output signal from the variable frequency signal generating circuit is swept is such as to facilitate reception of a received signal over the predetermined reception frequency range. In another embodiment of the invention the predetermined reception frequency range is in the order of 400KHz. In a further embodiment of the invention the predetermined upper and lower frequency values of the variable frequency output signal from the variable frequency signal generating circuit is such as to facilitate reception of a received signal between a predetermined lower reception frequency of 433.72MHz and a predetermined upper reception frequency of 434.12MHz. In a still further embodiment of the invention the predetermined frequency range of the variable frequency output signal of the variable frequency signal generating circuit is in the order of 400KHz. In a further embodiment of the invention the predetermined lower frequency of the variable frequency output signal of the variable frequency signal generating circuit is in the order of 423.02MHz and the predetermined upper frequency of the variable frequency output signal is in the order of 423.42MHz. In one embodiment of the invention the intermediate filter means filters out signals of frequencies other than frequencies in the order of 10.7MHz. Preferably, a saw filter is provided for filtering the received signal to the mixing means, and for filtering out signals of frequency outside the predetermined reception frequency range. The invention also provides a remote keyless entry system for a motor vehicle comprising the variable frequency receiver according to the invention. Further the invention provides a variable frequency receiver for receiving a remotely transmitted signal within a predetermined reception frequency range, the receiver comprising a receiving means for receiving the remotely transmitted signal, a variable frequency signal generating means for outputting a variable frequency output signal, a mixing means for mixing the received signal with the variable frequency output signal and for outputting the mixed signal at a frequency dependent on the frequency of the variable frequency output signal and the frequency of the received signal, a gate means for outputting a signal derived from the mixed signal, and a control means for reading the signal from the mixed signal and for determining if the received signal is a valid signal, the control means controlling the gate means for outputting the signal derived from the mixed signal in response to the received signal being a valid signal, the control means controlling the variable frequency signal generating means for holding the frequency of the variable frequency output signal constant until the signal derived from the mixed signal has been outputted through the gate means. In one embodiment of the invention the control means operates the variable frequency signal generating means for selectively and sequentially varying the frequency of the variable frequency output signal for sweeping the variable frequency output signal through a predetermined frequency range between a predetermined lower frequency and a predetermined upper frequency. In another embodiment of the invention the predetermined upper and lower frequencies of the variable frequency output signal are selected for facilitating reception of received signals within the predetermined reception frequency range. In a further embodiment of the invention the control means monitors the time between data edges of the received signal for determining if the received signal is of a valid signal. The advantages of the invention are many. The variable frequency signal generating circuit provides a relatively simple and low cost circuit which provides a relatively accurate variable frequency output signal, and the variable frequency signal generating circuit does not require relatively high precision and high cost components for providing the relatively accurate variable frequency output signal. In particular, a relatively accurate constant frequency signal generating source is not required. Furthermore, the radio receiver according to the invention also provides a relatively low cost and accurate receiver, and where the receiver is provided with the variable frequency signal generating circuit manual fine tuning of the receiver is unnecessary. The invention will be more clearly understood from the following description of some preferred embodiments thereof which are given by way of example only with reference to the accompanying drawings, in which: Fig 1. is a block representation of a variable frequency receiver for a remote keyless entry system of a motor vehicle, Fig 2. is a block representation of a variable frequency signal generating circuit also according to the invention of the receiver of Fig 1 , Fig. 3 is a graphical representation of a variable frequency signal generated by the variable frequency signal generating circuit of Fig. 2, and Fig. 4 is a block representation of a variable frequency receiver according to another embodiment of the invention for a remote keyless entry system of a motor vehicle. Referring to the drawings and initially to Figs. 1 to 3 thereof, there is illustrated a narrow band variable frequency radio receiver according to the invention indicated generally by the reference numeral 1 , which is particularly suitable for use in connection with an electronic control unit (not shown) of a remote keyless entry system of a motor vehicle (also not shown). The electronic control unit although not illustrated will be well known to those skilled in the art, and the receiver 1 may be provided internally within the electronic control unit or may be a stand alone receiver communicating with the electronic control unit. The electronic control unit may control various components in the motor vehicle, for example, an alarm circuit, a vehicle immobiliser unit, the central locking system of the vehicle and other security aspects of the vehicle which protect the vehicle when unattended. As will be described below on reception of a signal in valid format the radio receiver 1 outputs a demodulated form of the received signal which contains the data embedded in the signal to the electronic control unit, and on the electronic control unit determining that the signal is a unique valid signal unique to the electronic control unit, the electronic control unit appropriately operates the various components in the motor vehicle which are controlled by the electronic control unit. For example, in the event that the alarm circuit of the vehicle is in a disarmed state, on reception of a valid unique signal the electronic control unit arms the alarm circuit, and typically, operates the immobiliser unit for immobilising the vehicle, and the central locking system for locking the vehicle. On reception of a valid unique signal when the alarm circuit is in an armed state, the electronic control unit disarms the alarm circuit, and typically, operates the immobilising unit for mobilising the vehicle, and the central locking system for unlocking the vehicle. The receiver 1 is adapted for receiving radio signals, typically, transmitted by a keyfob transmitter (not shown) within a predetermined narrow band frequency range of 400KHz between a predetermined lower reception frequency of 433.72MHz and a predetermined upper reception frequency of 434.12MHz. The transmitted signals, typically, comprise a preamble code followed by a unique code, both of which are embedded in the transmitted signal. The preamble code typically is common to a number of electronic control units of similar type, and the unique code is unique to one specific electronic control unit. The frequency of the transmitted signals are randomly selected within the predetermined frequency range of 433.72MHz and 434.12MHz in thirty-two 12.5KHz steps for each transmission, and two or more transmission frequencies may be selected for each transmission. An antenna 3 at the front end of the receiver 1 receives the remotely transmitted radio signals from the keyfob transmitter (not shown) or other suitable transmitter, and feeds the received signals to a saw filter 4 which filters out signals of frequencies outside the predetermined reception frequency range of 433.72MHz to 434.12MHz. Received frequencies within the reception frequency range of 433.72MHz to 434.12MHz are fed from the saw filter 4 to a mixing means, namely, a mixer 5 which mixes the received signals with a variable frequency output signal generated by a variable frequency signal generating circuit also according to the invention and indicated by the reference numeral 6. The circuit 6 which is described in detail below with reference to Fig. 2 feeds the variable frequency output signal on a line 8 to the mixer 5, and the frequency of the variable frequency output signal is swept through a predetermined frequency range of 400KHz from a predetermined lower frequency of 423.02MHz to a predetermined upper frequency of 423.42MHz in thirty-two incremental steps of 12.5KHz. This is described in detail below. The mixer 5 outputs two signals, one of which is at a frequency equal to the sum of the frequencies of the received signal and the variable frequency output signal, and the other is at a frequency equal to the difference of the frequencies of the received signal and the variable frequency output signal from the circuit 6. By selecting the lower and upper frequencies of the variable frequency output signal at 423.02MHz and 423.42MHz, respectively, the frequency difference between the received signal and the variable frequency output signal for corresponding values of the received signal and variable frequency output signal will always be 10.7MHz if the received signal is within the predetermined lower and upper reception frequencies of 433.72MHz and 434.12MHz, respectively. In other words, the difference between the predetermined upper reception frequency of 434.12MHz and the predetermined upper frequency of the variable frequency output signal of 423.42MHz is 10.7MHz, and similarly in the case of the respective predetermined lower reception frequency and the predetermined lower frequency of the variable frequency output signal, and in turn the respective thirty-two intermediate frequency values of the reception frequency and the variable frequency output signal. An intermediate filter means, namely, an intermediate filter 10 receives the output from the mixer 5 and filters out all signals other than those at an intermediate frequency of 10.7MHz, namely, the difference between the frequency of a valid received signal at one of the reception frequencies within the reception frequency range, and the corresponding frequency of the variable frequency output signal within the predetermined frequency range. An amplifying means provided by an amplifier 12 amplifies the intermediate frequency signal, which in turn is fed to a demodulating means, namely, a demodulator 14. The demodulator 14 demodulates the signal from the amplifier 12 and relays the data part of the received signal to an output circuit 15. A control means in this embodiment of the invention provided by a microprocessor 16 reads the data signal relayed to the output circuit 15 on a line 17 for determining if the data signal is of valid format. If so, a gate means, namely, a gate circuit 18 operated under the control of the microprocessor 16 through a line 21 outputs the data signal on an output line 19 to the electronic control unit (not shown) where suitable analysing circuitry (also not shown) in the electronic control unit determines if the received signal is a unique signal unique to the electronic control unit. The microprocessor 16 under the control of suitable software reads the data signal from the output circuit 15 and monitors the time between data edges of the signal for determining if the data signal is of the valid format. Referring now to Figs. 2 and 3 the variable frequency signal generating circuit 6 will now be described. The circuit 6 is operated under the control of the microprocessor 16 for generating and sweeping the variable frequency output signal through the frequency range of 400KHz from the predetermined lower frequency of 423.02MHz to the predetermined upper frequency of 423.42MHz in the form of a staircase signal in thirty-two incremental steps of 12.5 KHz each. Typical sweeps of the variable frequency output signal are illustrated in Fig. 3. In this embodiment of the invention each time the variable frequency output signal reaches the predetermined upper frequency of 423.42MHz the frequency of the variable frequency output signal is returned to the predetermined lower frequency of 423.02MHz. The frequency of the variable frequency output signal is maintained constant during each incremental step for a first predetermined time period sufficient to allow the microprocessor 16 determine if a signal has been received, and if so, if the received signal is of valid format. In this embodiment of the invention each incremental frequency step is maintained for a first predetermined time period of approximately one millisecond. On determining the existence of a received signal of valid format the microprocessor 16 operates the variable frequency signal generating circuit 6 to maintain the frequency of the variable frequency output signal constant at the frequency corresponding to that at which the received signal was received for a second predetermined time period sufficient to allow a series of received data signals to be outputted through the gate circuit 18 on the output line 19 to the electronic control unit (not shown). In this embodiment of the invention the second predetermined time period is 250 milliseconds. As can be seen from Fig. 3 during the time period A the variable frequency output signal was swept through two sweeps without a signal in valid format having been received. During the third sweep after a time period B a signal of valid format was received and the frequency of the variable frequency output signal is held constant for the second predetermined time period C to allow a series of the data signals to be received and outputted to the electronic control unit (not shown). At the end of the second predetermined time period C the variable frequency signal generating circuit 6 under the control of the microprocessor 16 again continues the frequency sweep by incrementing the variable frequency output signal by the next step of 12.5KHz. Referring now in particular to Fig. 2, the variable frequency signal generating circuit 6 is in the form of a phase locked loop control circuit and comprises a constant frequency signal generating means, which in this embodiment of the invention is provided by a crystal frequency signal generator 20 for generating a constant frequency signal at 6.6086 MHz. A variable frequency signal generating means provided by a voltage controlled oscillator 23 generates the variable frequency output signal which is outputted from the circuit 6 on the line 8 to the mixer 5. The variable frequency output signal from the voltage controlled oscillator 23 is also fed to a frequency divider circuit 24 which divides the frequency from the voltage controlled oscillator 23 by a factor of 64 so that the frequency of the signal from the frequency divider circuit 24 is more appropriately matched to that of the constant frequency signal outputted by the signal generator 20. A phase comparing means, namely, a phase comparator 25 compares the respective signals received from the signal generator 20 and the frequency divider circuit 24 and outputs a signal, which is indicative of, and in this case proportional to the phase difference of the respective signals from the signal generator 20 and the frequency divider circuit 24. The signal from the phase comparator 25 is fed through a feedback loop 27 to a control input port 28 of the voltage controlled oscillator 23. A low pass filter 29 in the feedback loop 27 filters out high frequencies from the signal from the phase comparator 25. The signal from the phase comparator 25 becomes a DC voltage signal when the phase lock loop has locked-up. A signal varying means for varying the voltage of the signal applied to the control input port 28 of the voltage controlled oscillator 23 for in turn varying the frequency of the variable frequency output signal from the voltage controlled oscillator 23 comprises a voltage adding means, namely, a voltage adder 30. The voltage adder 30 adds a variable DC voltage signal under the control of the microprocessor 16 to the value of the DC voltage signal from the phase comparator 25 when the circuit is locked-up and the feedback loop 27 is open by a first isolating means, namely, a first analogue switch SW1, as will be described below. In this way the voltage value of the signal applied to the control input port 28 of the voltage controlled oscillator 23 is the sum of the voltage of the DC signal from the phase comparator 25 when the circuit locked-up and the variable DC voltage applied by the microprocessor 16. The variable voltage signal is derived from the microprocessor 16 through a digital- to-analogue converter 32. The microprocessor 16 generates a five bit word which is fed to the digital-to-analogue converter 32 on a bus 33 for controlling the digital-to- analogue converter 32 for outputting the variable DC voltage signal as a stepped voltage in the form of a staircase in thirty-two incremental steps for sweeping the variable frequency output signal through the corresponding thirty-two incremental frequency steps. The microprocessor 16 controls the digital-to-analogue converter 32 for sequentially incrementing the voltage of the variable DC voltage signal through the thirty-two incremental steps from a lower voltage value to an upper voltage value, and on the voltage of the variable DC voltage signal reaching the upper voltage value, the voltage is returned to the lower voltage value for in turn generating the variable frequency output signal as illustrated in Fig. 3. A voltage divider circuit 35 attenuates the voltage signal from the digital-to-analogue converter 32 and applies the attenuated voltage signal to a pin 2 of the adder 30. The attenuated voltage signal is of such a value that when summed with the voltage signal from the phase comparator 25 on a pin 1 of the adder 30, and applied to the control input port 28 of the voltage controlled oscillator 23, the variable frequency output signal from the voltage controlled oscillator 23 is swept between the predetermined lower and upper frequencies. The first switch SW1 which is located in the feedback loop 27 under the control of the microprocessor 16 isolates the control input port 28 of the voltage controlled oscillator 23 from the phase comparator 25 when the circuit is locked-up for facilitating the voltage on pin 1 of the adder 30 to be maintained substantially constant at the voltage of the signal outputted by the phase comparator 25 when the circuit has locked-up. A retaining means for retaining the voltage on the pin 1 of the adder 30 substantially constant while the first switch SW1 is open comprises a capacitive retaining circuit 36 which comprises a capacitor C1 which is connected to ground through a first impedance means provided by a high impedance means, namely, a resistor R1 for facilitating charging of the capacitor C1 during periods when the first switch SW1 is closed as the circuit is being brought to its locked-up state. A second isolating means, namely, a second analogue switch SW2 bridges the resistor R1 for connecting the capacitor C1 to ground for maintaining the voltage on the pin 1 of the adder 30 substantially constant at the locked-up voltage after the circuit has locked-up and the first switch SW1 has been opened. The first and second switches SW1 and SW2 are operated under the control of the microprocessor 16 through control lines 37 and 38, respectively, and when the first switch SW1 is opened on the circuit being locked-up the second switch SW2 is closed for maintaining the voltage on the input pin 1 of the adder 30 substantially constant. When the first switch SW1 is closed for allowing the circuit to lock-up, the second switch SW2 is open for facilitating charging of the capacitor C1 through the resistor R1. A high impedance voltage follower 39 in the feedback loop 27 between the adder 30 and the capacitive retaining circuit 36 minimises leakage through the pin 1 of the adder 30. Operation of the circuit 6 will now be described. Initially, with the first switch SW1 closed and the second switch SW2 open and the voltage outputted by the digital-to- analogue converter 32 at zero volts, the circuit 6 operates as a phase locked loop circuit with the signal from the phase comparator 25 being applied to the control input port 28 of the voltage controlled oscillator 23. After a short lock-up time the phase locked loop circuit becomes locked-up, in other words, locked in frequency and phase to a multiple of the frequency of the signal generator 20, depending on the frequency divider circuit 24. After the phase locked loop circuit has become locked and the capacitor C1 has fully charged, the microprocessor 16 through the control lines 37 and 38 simultaneously opens the first switch SW1 and closes the second switch SW2, and the capacitor C1 holds the voltage on the pin 1 of the adder 30 substantially constant at the value at which it was prior to opening of the first switch SW1. The microprocessor 16 sequentially increments the five bit word on the bus 33 at intervals corresponding to the first predetermined time period, and outputs the five bit word to the digital to analogue converter 32, which in turn, outputs the stepped DC voltage which is in turn attenuated and applied to the pin 2 of the voltage adder 30. The voltage adder 30 sums the stepped voltage to the voltage being maintained on the pin 1 of the adder 30 by the capacitor C1 , and the summed voltage is applied to the control input port 28 of the voltage controlled oscillator 23. The staircase voltage on the control input port 28 causes the voltage controlled oscillator 23 to output the staircase variable frequency output signal of Fig. 3. Due to the fact that some leakage occurs from the capacitor C1 while the first switch SW1 is open, periodically the microprocessor 16 simultaneously closes the first switch SW1 and opens the second switch SW2 for allowing the circuit 6 to again operate as a phase locked loop circuit for locking up of the circuit, and in turn charging the capacitor C1. After a short lock-up period and when the capacitor C1 has been charged, the microprocessor 16 simultaneously opens the first switch SW1 and closes the second switch SW2. Typically, the capacitor C1 will require charging between the respective staircase cycles of the variable frequency output signal, and the circuit is operated in its phase locked loop form when the voltage on pin 2 of the adder 30 from the digital to analogue converter 32 is zero volts. In the event that the microprocessor 16 determines the presence of a received signal of valid format in the output circuit 15, the microprocessor 16 holds the voltage output of the digital to analogue converter 32 constant for the second predetermined time period corresponding to the period C in Fig. 3 so that the valid signal can be gated through the gate circuit 18 to the electronic control unit (not shown). After the received signal has been outputted to the electronic control unit (not shown) the microprocessor 16 again controls the digital to analogue converter 32 for incrementing the voltage to the pin 2 of the adder 30 to the next voltage value and so on to produce the staircase frequency output signal of Fig. 3. Referring now to Fig. 4 there is illustrated a narrow band variable frequency radio receiver according to another embodiment of the invention indicated generally by the reference numeral 50. The radio receiver 50 is substantially similar to the radio receiver 1 and similar components are identified by the same reference numerals. The main difference between the receiver 50 and the receiver 1 is that the variable frequency output signal on the line 8 to the mixer 5 instead of being derived from the variable frequency signal generating circuit 6 of the receiver 1 is derived from a local oscillator 51 which in this embodiment of the invention is also provided by a voltage controlled oscillator under the control of a local oscillator controller 52, which in turn is operated under the control of the microprocessor 16. The oscillator controller 52 provides a swept stepped DC voltage to a control input port 53 of the local oscillator 51 which is similar to that which is applied to the control input port 28 of the voltage controlled oscillator 23 of the receiver 1. This, thus, controls the local oscillator 51 for outputting the variable frequency output signal in the form of a staircase identical to that illustrated in Fig. 3. As well as the oscillator 52 being operated under the control of the microprocessor 16 for providing the stepped staircase DC voltage to the control input port 53 of the local oscillator 51, the oscillator controller 52 is also controlled by the microprocessor 16 for maintaining the voltage on the control input pin 53 of the local oscillator 52 for the second predetermined time period in the event of the microprocessor 2 determining the existence of a received signal of valid format so that a series of the received signals can be outputted through the gate circuit 18 to an electronic control unit of a motor vehicle as already described with reference to Figs. 1 to 3. While in the embodiments of the invention described with reference to Figs. 1 to 4 the receivers have been described as comprising respective microprocessors, it is envisaged in certain cases that the receivers may form part of the electronic control unit of the motor vehicle, and in which case, the microprocessors of the receivers described with reference to Figs. 1 to 4 may be replaced with the microprocessors of electronic control units.

Claims: Claims 1. A variable frequency signal generating circuit (6) for outputting a variable frequency output signal at a plurality of frequencies within a predetermined frequency range between a predetermined lower frequency and a predetermined upper frequency, characterised in that the circuit (6) is in the form of a phase locked loop circuit and comprises a variable frequency signal generating means (23) for generating and outputting the variable frequency output signal, the variable frequency signal generating means (23) having a control input port (28) for receiving a control signal for determining the frequency of the variable frequency output signal, a constant frequency signal generating means (20) for generating a constant frequency signal, a phase comparing means (25) for comparing the variable frequency output signal with the constant frequency signal and for outputting a signal indicative of the phase shift between the two signals, a feedback loop (27) for feeding back the signal from the phase comparing means (25) to the control input port (28) of the variable frequency signal generating means (23) for completing the phase locked loop circuit, a first isolating means (SW1) in the feedback loop (27) for isolating the control input port (28) of the variable frequency signal generating means (23) from the phase comparing means (25) when the circuit has locked-up, a retaining means (36) for holding the signal from the phase comparing means (25) on the control input port (28) of the variable frequency signal generating means (23) after the first isolating means (SW1) has isolated the control input port (28) from the phase comparing means (25), a signal varying means (32) for selectively varying the signal on the control input port (28) of the variable frequency signal generating means (23) while the control input port (28) is isolated from the phase comparing means (25) for in turn selectively varying the frequency of the variable frequency output signal, and a control means (16) for operating the first isolating means (SW1) for isolating the control input port (28) from the phase comparing means (25) and for operating the signal varying means (32) for selectively varying the signal on the control input port (28) when the control input port (28) is isolated from the phase comparing means (25). 2. A circuit as claimed in Claim 1 characterised in that the control means (6) controls the signal varying means (32) for selectively and sequentially incrementing or decrementing the value of the signal on the control input port (28) over a predetermined range of signal values between a predetermined lower signal value and a predetermined upper signal value for sweeping the frequency of the variable frequency output signal through the predetermined frequency range. 3. A circuit as claimed in Claim 2 characterised in that the control means (16) controls the signal varying means (32) for holding the signal value on the control input port (28) of the variable frequency signal generating means (23) constant at each signal value within the predetermined range of signal values for a first predetermined time period. 4. A circuit as claimed in Claim 2 or 3 characterised in that the control means (16) controls the signal varying means (32) for holding the value of the signal on the control input port (28) of the variable frequency signal generating means (23) constant at selected signal values within the predetermined range of signal values for a second predetermined time period, the second predetermined time period being greater than the first predetermined time period. 5. A circuit as claimed in any of Claims 2 to 4 characterised in that the control means (16) controls the signal varying means (32) for selectively and sequentially incrementing the signal on the control input port (28) of the variable frequency signal generating means (23) through a plurality of incremental signal value steps from the lower predetermined signal value to the upper predetermined signal value for sweeping the variable frequency output signal through the predetermined frequency range. 6. A circuit as claimed in any of Claims 2 to 5 characterised in that the control means (16) controls the signal varying means (32) for returning the signal value on the control input port (28) to one of the predetermined lower and upper signal values when the signal value on the control input port (28) is at the other of the predetermined lower and upper signal values. 7. A circuit as claimed in any preceding claim characterised in that the variable frequency signal generating means (23) comprises a voltage controlled oscillator, and the signal outputted from the phase comparing means (25) is a DC voltage signal when the phase lock loop has locked-up. 8. A circuit as claimed in Claim 7 characterised in that the signal varying means (32) comprises a means for selectively and sequentially generating a variable DC voltage, and an adding means (30) for adding the variable DC voltage to the voltage signal from the phase comparing means (25) held on the control input port (28) of the variable frequency signal generating means (23). 9. A circuit as claimed in Claim 8 characterised in that the adding means (30) comprises a voltage adder. 10. A circuit as claimed in Claim 8 or 9 characterised in that the signal varying means (32) comprises a digital to analogue converter (32) operating under the control of the control means (16) for outputting the variable DC voltage to the control input port (28) of the variable frequency signal generating means (23). 11. A circuit as claimed in any preceding claim characterised in that the first isolating means (SW1 ) comprises a first switch means (SW1 ) operable under the control of the control means (16), the first switch means (SW1) being located in the feedback loop (27) between the phase comparing means (25) and the signal varying means (32). 12. A circuit as claimed in any preceding claim characterised in that the retaining means (36) is provided by a capacitive retaining circuit (36) connected to the feedback loop (27) between the first isolating means (SW1) and the signal varying means (32). 13. A circuit as claimed in Claim 12 characterised in that the capacitive retaining circuit (36) comprises a capacitor (C1 ) connected between the feedback loop (27) and ground. 14. A circuit as claimed in Claim 13 characterised in that a first impedance means (R1 ) is provided in the capacitive retaining circuit (36) for smoothing charging of the capacitor (C1 ) during periods when the control input port (28) of the variable frequency signal generating means (23) is communicating with the phase comparing means (25). 15. A circuit as claimed in Claim 13 characterised in that a second isolating means (SW2) operable under the control of the control means (16) is provided in the capacitive circuit (36) for switching out the first impedance means (R1 ) when the control input port (28) of the variable frequency signal generating means (23) is isolated from the phase comparing means (25). 16. A circuit as claimed in Claim 15 characterised in that the second isolating means (SW2) is provided by a second switch means. 17. A circuit as claimed in Claim 15 or 16 characterised in that the control means (16) operates the second isolating means (SW2) for switching out the first impedance means (R1 ) when the first isolating means (SW1 ) is isolating the control input port (28) of the variable frequency signal generating means (23) from the phase comparing means (25), and vice versa. 18. A circuit as claimed in any preceding claim characterised in that a low pass filter (29) for filtering the signal from the phase comparing means (25) to the control input port (28) of the variable frequency signal generating means (23) is provided in the feedback loop (27). 19. A circuit as claimed in any preceding claim characterised in that the comparing means (25) comprises a phase comparator. 20. A circuit as claimed in any preceding claim characterised in that the constant frequency signal generating means (20) comprises a constant frequency generator. 21. A circuit as claimed in Claim 20 characterised in that the constant frequency generator (20) is provided by a crystal generator. 22. A circuit as claimed in any preceding claim characterised in that the control means (16) operates the first isolating means (SW1) periodically for closing the feedback loop (27) for communicating the control input port (28) of the variable frequency signal generating means (23) with the phase comparing means (25) for permitting periodic lock-up of the phase locked loop circuit for avoiding deterioration of the signal on the control input port (28). 23. A variable frequency receiver (1 ) for receiving a remotely transmitted signal with a predetermined reception frequency range, the receiver (1) comprising a receiving means (3,4) for receiving the remotely transmitted signal, a variable frequency signal generating circuit (6) as claimed in any preceding claim for outputting the variable frequency output signal at a plurality of frequencies within the predetermined frequency range, a mixing means (5) for mixing the received signal with the variable frequency output signal and for outputting the mixed signal at a frequency dependent on the frequency of the variable frequency output signal and the frequency of the received signal, and a means (16) for reading a signal derived from the mixed signal and for determining from the signal derived from the mixed signal if the received signal is a valid signal. 24. A receiver as claimed in Claim 23 characterised in that the control means (16) of the variable frequency signal generating circuit (6) acts as the means for reading and determining the validity of the received signal. 25. A receiver as claimed in Claim 23 or 24 characterised in that the control means (16) of the variable frequency signal generating circuit (6) is responsive to the presence of a valid received signal for controlling the signal varying means (32) for holding the signal value on the control input port (28) of the variable frequency signal generating means (23) constant for in turn holding the frequency of the variable frequency output signal constant for the second predetermined time period for facilitating reception of the received signal. 26. A receiver as claimed in any of Claims 23 to 25 characterised in that the second predetermined time period is of sufficient duration for facilitating reception of at least one valid received signal. 27. A receiver as claimed in any of Claims 23 to 26 characterised in that an intermediate filter means (10) is provided for filtering the mixed signal and for outputting a signal filtered from the mixed signal the frequency of which is a predetermined value derived from the difference between the frequencies of the variable frequency output signal and corresponding frequencies at which it is desired to receive the remotely transmitted signal. 28. A receiver as claimed in Claim 27 characterised in that a demodulating means (14) is provided for demodulating the signal outputted by the intermediate filter means (10) for extracting data therefrom. 29. A receiver as claimed in Claim 28 characterised in that a gate means (18) is provided for outputting the data extracted from the received signal by the demodulating means (14), the gate means (18) being operable under the control of the control means (16) for outputting the data in response to the control means (16) determining that the received signal is a valid signal. 30. A receiver as claimed in Claim 28 or 29 characterised in that the control means (16) reads the data signal from the demodulating means (14) and the time period between the edges of the demodulated signal for determining if the received signal is of a valid format. 31. A receiver as claimed in Claim 30 characterised in that the control means (16) controls the gate means (18) for outputting the demodulated signal in response to the control means (16) determining that the data signal is in valid format. 32. A receiver as claimed in any of Claims 23 to 31 characterised in that the predetermined frequency range through which the variable frequency output signal from the variable frequency signal generating circuit (6) is swept is such as to facilitate reception of a received signal over the predetermined reception frequency range. 33. A receiver as claimed in any of Claims 23 to 32 characterised in that the predetermined reception frequency range is in the order of 400KHz. 34. A receiver as claimed in any of Claims 23 to 33 characterised in that the predetermined upper and lower frequency values of the variable frequency output signal from the variable frequency signal generating circuit (6) is such as to facilitate reception of a received signal between a predetermined lower reception frequency of 433.72MHz and a predetermined upper reception frequency of 434.12MHz. 35. A receiver as claimed in any of Claims 23 to 34 characterised in that the predetermined frequency range of the variable frequency output signal of the variable frequency signal generating circuit is in the order of 400KHz. 36. A receiver as claimed in any of Claims 23 to 35 characterised in that the predetermined lower frequency of the variable frequency output signal of the variable frequency signal generating circuit (6) is in the order of 423.02MHz and the predetermined upper frequency of the variable frequency output signal is in the order of 423.42MHz. 37. A receiver as claimed in any of Claims 23 to 36 characterised in that the intermediate filter means (10) filters out signals of frequencies other than frequencies in the order of 10.7MHz. 38. A receiver as claimed in any of Claims 23 to 37 characterised in that a saw filter (4) is provided for filtering the received signal to the mixing means (5), and for filtering out signals of frequency outside the predetermined reception frequency range. 39. A remote keyless entry system for a motor vehicle comprising the variable frequency receiver (1 ) as claimed in any of Claims 23 to 38. 40. A variable frequency receiver (50) for receiving a remotely transmitted signal within a predetermined reception frequency range, the receiver comprising a receiving means (3) for receiving the remotely transmitted signal, a variable frequency signal generating means (51) for outputting a variable frequency output signal, a mixing means (5) for mixing the received signal with the variable frequency output signal and for outputting the mixed signal at a frequency dependent on the frequency of the variable frequency output signal and the frequency of the received signal, a gate means (18) for outputting a signal derived from the mixed signal, and a control means (16) for reading the signal from the mixed signal and for determining if the received signal is a valid signal, the control means (16) controlling the gate means (18) for outputting the signal derived from the mixed signal in response to the received signal being a valid signal, the control means (16) controlling the variable frequency signal generating means (51) for holding the frequency of the variable frequency output signal constant until the signal derived from the mixed signal has been outputted through the gate means (18). 41. A receiver as claimed in Claim 40 characterised in that the control means (16) operates the variable frequency signal generating means (51) for selectively and sequentially varying the frequency of the variable frequency output signal for sweeping the variable frequency output signal through a predetermined frequency range between a predetermined lower frequency and a predetermined upper frequency. 42. A receiver as claimed in Claim 41 characterised in that the predetermined upper and lower frequencies of the variable frequency output signal are selected for facilitating reception of received signals within the predetermined reception frequency range. 43. A receiver as claimed in any of Claims 40 to 42 characterised in that the control means (16) monitors the time between data edges of the received signal for determining if the received signal is of a valid signal.

Inventors: LYONS PATRICK JOHN, LYONS, PATRICK, JOHN
Applicants: HI KEY LTD, LYONS PATRICK JOHN, HI-KEY LIMITED, LYONS, PATRICK, JOHN
Application year: 1999
Main classification: H03J7
IPC codes: G07C9, H03B23, H03C3, H03J1