Single supply voltage nonvolatile memory device with hierarchical row decoding

Abstract: The memory device (10) comprises a memory array (2) having an organisation of the type comprising global word lines (4) and local word lines (6), a global row decoder (8) addressing the global word lines (4), a local row decoder (12) addressing the local word lines (6), a global power supply stage (22) supplying the global row decoder (8), and a local power supply stage (24) supplying the local row decoder (12).

Description: The present invention regards a single supply voltage nonvolatile memory device with hierarchical row decoding. As is known, memory devices are typically organized as an array, in which word lines connect gate terminals of the memory cells located on the same row, and bit lines connect drain terminals of the memory cells located on the same column. The rows of the memory array are addressed by means of a row decoder, which receives at an input a coded address and has the purpose of biasing the word line of the row each time addressed at a stable and precise voltage, the value of which depends upon the type of operation carried out on the memory cells of that particular row (reading, programming, verifying, erasing). In some memory devices, the memory array has an organisation of the type comprising global word lines and local word lines. In particular, the memory array comprises global word lines and a plurality of local word lines for each global word line, the local word lines being connected to the corresponding global word line through respective switching stages which, when they are turned on, have the purpose of enabling transfer of the voltage present on the global word line to the respective local word line and to which the memory cells are then physically connected. A global row decoder addresses the global word lines and a local row decoder addresses the local word lines. In particular, the global row decoder is directly connected to the global word lines and each time biases the line or lines selected, whilst the local row decoder controls the switching stages so as to enable selective connection between the local word lines and their respective global word line. A switching stage of the type referred to above is, for example, described in the European Patent Application No. 98830570.2, filed on September 30, 1998 in the name of the present applicant, and published as EP-A-0 991 075 and its circuit diagram is shown in Figure 1. In particular, the switching stage, designated as a whole by 1, is connected between a global word line 4, driven by a respective output global driving stage 5 forming part of the global row decoder (not illustrated), and a local word line 6, presents a CMOS type structure, and comprises a PMOS transistor 7 and an NMOS transistor 9 having source terminal and, respectively, drain terminal connected together to the global word line 4, drain terminal and, respectively, source terminal connected together to the local word line 6, and gate terminals receiving respective mutually complementary control signals PCH and NCH, one of which is supplied by a respective local output driving stage (not shown) forming part of the local row decoder (not shown either), whilst the other is obtained from the former via an inverter. The NMOS transistor 9 further has a bulk terminal biased at a voltage V NEG , which is equal to a ground voltage during the reading and programming phases of the memory cells and is equal to a negative erasing voltage, for example -8V during the erasure phase, whilst the PMOS transistor 7 has a bulk terminal biased at a voltage V PCX , which typically assumes a value of approximately 6 V during the reading phase and a value of approximately 1.5 V during the erasing phase, and presents a staircase waveform with a preset step during the programming phase, in which the initial value and the final value of the staircase depend upon the type of memory cells used; for example, for four level memory cells (i.e., memory cells capable of storing 2 bits per cell), the programming voltage varies between 1.5 and 9 V with a step of approximately 300 mV. Moreover connected to the local word line 6 is a drain terminal of a discharging NMOS transistor 11 having source terminal connected to ground, bulk terminal biased at the voltage V NEG , and gate terminal receiving a control signal DSC, and having the purpose, when it is on, of keeping the local word line 6 at the ground voltage. In addition, during the reading and programming phases, the global word lines 4 and the local word lines 6 selected must also be biased at the voltage V PCX , which is therefore supplied at an input, as supply voltage, both to the global row decoder and to the local row decoder in order to bias the respective internal circuitries. It is also known, however, that memory devices are typically of the single supply voltage type; i.e., they receive from outside a single supply voltage V CC having a value of, for example, between 2.5 and 3.8 V. Consequently, the voltage V PCX referred to above, assuming values even greater than the supply voltage V CC , is generated inside the memory device by means of a voltage elevator circuit, generally referred to as "voltage booster" or "charge pump", supplied by the supply voltage coming from outside and supplying at an output a boosted voltage higher than the supply voltage, which, since it is not very stable in voltage, is supplied at an input of a voltage regulator, which in turn supplies at an output the voltage V PCX referred to above, which is stable in voltage and presents the above mentioned values. From an electrical point of view, connected to the output of the voltage regulator is a very high parasitic capacitive load, which cannot be reduced substantially in that it is due to components that are physically required for carrying out both global and local row decoding and for biasing the bulk terminals of the PMOS transistors of the switching stages. Note, for example, that in a flash multilevel 64 bit memory, the parasitic capacitance connected to the output of the voltage regulator is of the order of 500 pF. The presence of a high capacitive load connected to the output of the voltage regulator brings about a noticeable slowing down in the operation of the voltage regulator. In fact, when a row of the memory array is not addressed, the corresponding word line is connected to ground, so that the capacitance associated to it is discharged; when, however, this row is addressed, the corresponding global word line is in fact connected to the output of the voltage regulator, the output voltage of which undergoes a sudden decrease caused by the well known phenomenon of charge sharing, which takes place between the overall capacitance connected to the output of the voltage regulator and the capacitance of the word line. This situation is further aggravated by the dynamic consumption of the local output driving stages of the local row decoder, which, since they must necessarily be of reduced dimensions to be physically positioned between two adjacent local word lines, have a simple structure and require a switching current (crowbar current) that is rather high, unlike the output global driving stages of the global row decoder, which, since they are not subject to such stringent dimensional constraints, have a more complex structure and larger dimensions, and hence have a smaller dynamic consumption. Consequently, the presence of such a high capacitive load connected to the output of the voltage regulator causes a considerable slowness in the recovery of the output voltage supplied by the voltage regulator, i.e., a considerable slowness in the restoration of the voltage supplied by it within an interval that may enable optimal reading of the memory cells; this slowness may lead, in certain cases, to a degradation of the time of access to the memory and,' above all, the carrying out of wrong readings. The presence of such a high capacitive load connected to the output of the voltage regulator has unfavourable consequences also in the programming phase of the memory cells, during which, as is known, in order to guarantee adequate accuracy in the programmed levels, a staircase voltage is applied to the word line. In particular, the high capacitive load causes the overall time for charging the word line, i.e., the time necessary for biasing the word line to each one of the levels of the staircase voltage, proves rather long. EP-A-0 665 555 discloses a semiconductor memory device of the partial-decoding type, comprising a plurality of word lines, a plurality of main row decoders, a plurality of partial decoders, and a plurality of PMOS transistors, one for each word line and each having a gate connected to the output of a main row decoder, a source connected to the output of a partial decoder, and a drain connected to a word line. The aim of the present invention is to provide a memory device without the drawbacks described above. According to the present invention, a memory device is provided, as defined in Claim 1. For a better understanding of the present invention, a preferred embodiment thereof is now described, purely to provide a non-limiting example, with reference to the attached drawings, in which: Figure 1 shows a circuit diagram of a known switching stage; and Figure 2 shows a circuit structure of the memory array and of the corresponding global and local row decoders made according to the present invention. In particular, for reasons of simplicity of illustration, just one of the global word lines and some of the local word lines associated to it are shown in Figure 2, which regards solely the generation of the high positive voltages necessary for biasing the word lines during the reading and programming phases of the memory cells. Furthermore, in Figure 2, parts that are identical to those illustrated in Figure 1 are identified by the same reference numbers. According to the illustration of Figure 2, the memory device, designated as a whole by 10, comprises a memory array 2 having an organisation of the type comprising global word lines 4 and local word lines 6 and including a plurality of memory cells 3, in particular multilevel memory cells, in turn organized in rows and columns, where the global word lines 4 are addressed by a global row decoder 8, and the local word lines 6 are addressed by a local row decoder 12. In particular, associated to each global word line 4 is a plurality of local word lines 6, which are connected to the respective global word line 4 through respective selection PMOS transistors 7, each having source terminal connected to the global word line 4, drain terminal connected to the local word line 6, and gate terminal connected to the local row decoder 12 through a respective control line 13 distinct from the control lines 13 to which the other PMOS transistors 7 are connected and on which it receives a control signal. In detail, the global row decoder 8 comprises a global decoding circuitry 14 designed to identify the global word line 4 to be addressed, and a plurality of output global driving stages 5, one for each global word line 4 (only one is shown in the Figure), which are arranged between the global decoding circuitry 14 and the global word lines 4 and are designed to bias the global word lines 4 at the voltages that are required each time. Likewise, the local row decoder 12 comprises a local decoding circuitry 18 designed to identify the local word line 6 to be addressed, and a plurality of output local driving stages 20, one for each local word line 6, which are arranged between the local decoding circuitry 18 and the respective control lines 13 connected to the gate terminals of the PMOS transistors 7 and which are designed to control turning on and turning off of the PMOS transistors 7, so as to enable or otherwise transfer of the voltage present on the global word line 4 to the local word lines 6. Addressing of the global word lines 4 may be alternatively performed by means of a single global row decoder 8 or by means of a number of global row decoders 8 distinct from one another, just as addressing of the local word lines 6 may be alternatively performed by a single local row decoder 12 or by a number of local row decoders 12 distinct from one another. In addition, according to the present invention, the memory device 10 comprises a global supply stage 22 supplying solely the global row decoder 8, and a local supply stage 24 distinct from the global supply stage 22 and supplying solely the local row decoder 12. In particular, the global supply stage 22 comprises a global charge pump 26 having an input connected to a supply line 30 set at the supply voltage V CC (supplied from outside to the memory device 10) and an output on which it supplies a global boosted voltage V HG having an amplitude greater than that of the supply voltage V CC (for example, 10 V) and a global voltage regulator 32 having an input connected to the output of the global charge pump 26 and an output connected to a global supply line 36 and on which it supplies a global voltage V PCXG , which is stable in voltage and assumes a value V R (reading voltage) of approximately 6 V during the reading phase, and instead presents a staircase waveform with a fixed step of approximately 300 mV during the programming phase, in which the initial and final values of the step depend upon the type of memory cells used; for example, for four level memory cells (i.e., memory cells capable of storing 2 bits per cell), the programming voltage varies between 1.5 and 9 V with a step of approximately 300 mV. Connected to the global supply line 36 are both the global decoding circuitry 14 and the output global driving stages 5, from which they receive the global voltage V PCXG . Also connected to the global supply line 36 are all the bulk terminals of the PMOS transistors 7, so that they are biased at the highest voltage in order to prevent both temporary direct biasing of the PN junctions (latch up phenomenon) and the so-called "body effect". The local supply stage 24 presents a structure altogether identical to that of the global supply stage 22 and comprises a local charge pump 28 having an input connected to the supply line 30 and an output on which it supplies a local boosted voltage V HL having an amplitude greater than that of the supply voltage V CC , and a global voltage regulator 32 having an input connected to the output of the local charge pump 26 and an output which is connected to a local supply line 38 and on which it supplies a local voltage V PCXL , which is stable in voltage and assumes a value a little higher than V R during the reading phase, and two distinct values during the programming phase, namely, a value smaller than V R if the amplitude of the programming pulse is lower than that of V R , and approximately 9 V if the amplitude of the programming pulse is greater than that of V R . Connected to the local supply line 38 are both the local decoding circuitry 18 and the output local driving stages 20; from the local supply line 38 the local decoding circuitry 18 and the output local driving stages 20 receive the local voltage V PCXL . Operation of the memory device 10 is as follows. When the memory device turns on, the capacitances associated to the gate terminals of the PMOS transistors 7 are all precharged to bring the gate terminals of the PMOS transistors 7 to the local voltage V PCXL . Consequently, when a local word line 6 is addressed, the global word line 4 to which the local word line 6 is connected is biased by the corresponding output global driving stage 5 at the global voltage V PCXG , whilst the gate terminal of the PMOS transistor 7 to which the local word line 6 is connected is brought, by the output local driving stage 20, to the ground voltage, discharging the capacitances associated to it. In this way, the PMOS transistor 7 connected to the local word line 6 addressed, is turned on and guarantees complete transfer of the voltage present on the global word line 4 to the local word line 6 that is addressed, whilst the PMOS transistors 7 connected to the local word lines 6 which are not addressed are turned off, and these local word lines 6 are kept at the ground voltage through respective discharging NMOS transistors of the type illustrated in Figure 1. In this way, addressing of a local word line 6 is particularly fast, in that, to bring to the ground voltage the gate terminal of the PMOS transistor 7 to which the word line is connected, it is sufficient to discharge the small parasitic capacitance associated to this gate terminal. Consequently, according to the present invention, the global supply stage 22 is destined to the biasing of the global row decoder 8 and of the global word lines 4 and local word lines 6 in the-reading and programming phases, whereas the local supply stage 24 is destined only to the biasing of the local row decoder 12 and to the supply of the current necessary for causing the output local driving stages 20 to switch. As a result, the separation of the supplying of circuitry dedicated to global decoding from the supplying of the circuitry dedicated to local decoding enables splitting of the capacitive load, which, in the known art, is connected to the output of the voltage regulator, into two distinct capacitive loads, each connected to the output of a respective voltage regulator 32, 34, so enabling a considerable reduction, during the reading phase, in the time for recovery of the said voltage regulators, and, during the programming phase, the time for charging the global word line addressed. Finally, it is clear that modifications and variations may be made to the memory device described and illustrated herein, without thereby departing from the sphere of protection of the present invention. For example, an NMOS transistor could be connected in parallel to each PMOS transistor 7, so as to create a CMOS switching stage of the type illustrated in Figure 1.

Claims: A memory device (10) comprising a memory array (2) having an organisation of the type comprising global word lines (4) and local word lines (6); global row decoding means (8) addressing said global word lines (4); local row decoding means (12) addressing said local word lines (6); and power supply means (22, 24) supplying said global row decoding means (8) and said local row decoding means (12); characterized in that said power supply means (22, 24) comprise global power supply means (22) supplying said global row decoding means (8) and local power supply means (24) supplying said local row decoding means (12). The memory device according to Claim 1, characterized in that said global power supply means (22) and said local power supply means (24) are distinct from one another. The memory device according to Claim 1 or 2, characterized in that said global power supply means (22) and said local power supply means (24) each comprise voltage elevating means (26, 28) having an input connected to a supply line (30) set at a first reference potential (Vcc) and supplying on an output a respective second reference potential (V HG , V HL ), and voltage regulating means (32, 34) having an input connected to the output of the respective voltage elevating means (26, 28) and supplying on an output (36, 38) a respective third reference potential (V PCXG , V PCXL ). The memory device according to any one of the foregoing Claims, characterized by comprising a plurality of said local word lines (6) for each of said global word lines (4), and a plurality of selection means (7) each arranged between a local word line (6) and a respective global word line (4); said selection means (7) being connected to said local row decoding means (12) through respective control lines (13) that are distinct from one another. The memory device according to Claim 4, characterized in that each of said selection means comprises at least one selection transistor (7) having a control terminal connected to said local row decoding means (12) through a respective said control line (13).

Inventors: KHOURI OSAMA, MICHELONI RINO, PICCA MASSIMILIANO, SACCO ANDREA, KHOURI, OSAMA, MICHELONI, RINO, PICCA, MASSIMILIANO, SACCO, ANDREA
Applicants: ST MICROELECTRONICS SRL, STMICROELECTRONICS S.R.L.
Application year: 1999
Main classification: G11C8
IPC codes: G11C16, G11C5, G11C8