Amplifier for cancelling distortion by combining hyperbolic tangent and hyperbolic sine transfer functions

Abstract: A differential amplifier (10) receives a differential input signal (V IN ). The input signal is attenuated by a first attenuator (12) and applied to a tanh amplifier (16). The input signal is also attenuated by a second attenuator (14) and applied to a sinh amplifier (18). The input signals to the tanh amplifier and sinh amplifier are independently attenuated. The transfer functions of the tanh amplifier and the sinh amplifier each have a linear region and a non-linear region. The output of the tanh amplifier and the sinh amplifier are summed (26) so that the non-linear region of the tanh amplifier cancels with the non-linear region of the sinh amplifier. The overall transfer function of the differential amplifier is linear over a wide range of input signal amplitudes by the cancellation of the non-linear regions.

Description: Background of the Invention The present invention relates in general to amplifiers and, more particularly, to an amplifier which combines a hyperbolic tangent transfer function with a hyperbolic sine transfer function to cancel distortion. Amplifiers are commonly used in a myriad of applications to amplify an input signal and provide an amplified output signal. Amplifiers are often differential in operation. Typically end applications for differential amplifiers include radio frequency (RF) transceivers, cellular telephones, pagers, cordless telephones, filters, and other wireless communication equipment. An important feature of differential amplifiers is to maintain linear operation over a wide range of input signal amplitudes. When operating in its linear range, a differential amplifier provides an output signal proportional to the input signal, where the proportionality is determined by the gain of the amplifier. Most prior art differential amplifiers operate linearly over a narrow range of input signal amplitudes. If the amplifier operates outside its linear range, then the output signal is subject to non-linear distortion and noise. One prior art technique of increasing the linear range of the differential amplifier involves placing degeneration resistors in the emitters of the differential transistor pair. Unfortunately, the degeneration resistors also have the undesirable effect of decreasing the gain of the differential amplifier and increasing the noise figure. Hence, a need exists for a differential amplifier having linear operation over a wide range of input signals with high gain and low noise figure. An amplification circuit according to the preamble portion of claim 1 is known from document US-A-4 247 825. Brief Description of the Drawings FIG. 1 illustrates a block diagram of an amplifier combining a hyperbolic tangent and hyperbolic sine transfer functions; FIG. 2 is a waveform plot useful in the explanation of the functioning of the Fig.1 circuit; and FIG. 3 is a schematic diagram of a differential amplifier according to the invention. Detailed Description of the Preferred Embodiment Referring to FIG. 1, an amplification circuit 10 is shown suitable for manufacturing as an integrated circuit using conventional integrated circuit processes. An input signal V IN is applied to attenuators 12 and 14, which in turn provide attenuated input signals V 12 and V 14 . The input signals V 12 and V 14 are thus independently attenuated. The attenuated input signal V 12 is processed through hyperbolic tangent (tanh) amplifier 16. The transconductance transfer function of amplifier 16 is shown as waveform 20 in FIG. 2 following a tanh function with a linear region and a non-linear region. The attenuated input signal V 14 is processed through hyperbolic sine (sinh) amplifier 18. The transconductance transfer function of amplifier 18 is shown as waveform 22 in FIG. 2 following a sinh function with a linear region and a non-linear region. The output current I 16 of tanh amplifier 16 and the output current I 18 of sinh amplifier 18 flow into the inputs of summation node 26. Summation node 26 combines or sums the output currents of amplifiers 16 and 18 and provides output current I OUT = I 16 + I 18 . The overall transconductance transfer function of amplification circuit 10 is shown as waveform plot 28 in FIG. 2 as the sum of waveform plot 20 and waveform plot 22. The non-linear region of waveform plot 20 cancels with the non-linear region of waveform plot 22. The transconductance gain I OUT /V IN of amplification circuit 10 which combines the output of a tanh amplifier and the output of a sinh amplifier is linear over a wider range of input signals V IN than can be obtained with a tanh amplifier, or a sinh amplifier alone. In an alternate embodiment, the combination of output currents I 16 and I 18 could be accomplished by other means provided the non-linear region of the tanh transfer function cancels with the non-linear region of the sinh transfer function. Also, as discussed below, it is desirable in some applications to have attenuators 12 and 14 be adjustable. Turning to FIG. 3, further detail of attenuators 12 and 14 and tanh amplifier 16 and sinh amplifier 18 are shown in a differential configuration. The differential input signal V IN , on the order of 1 volt, is applied to resistor divider network 30, 31, 32, 33, and 34. The voltage across resistor 34 represents attenuated voltage V 12 and the voltage across resistors 32, 33, and 34 represents attenuated voltage V 14 . Other attenuator circuits which attenuate an input signal may be substituted for resistor divider network 30-34. Amplifier 16 has a hyperbolic tangent transconductance transfer function. Tanh amplifier 16 includes differential transistors 36 and 38. Current source 40 is referenced to power supply conductor 42 operating at ground potential. The collector of transistor 36 is coupled to node 44, and the collector of transistor 38 is coupled to node 46. Nodes 44 and 46 are the combination circuit or summation nodes at the first and second outputs of the differential amplifier 10 which combine the input currents flowing into the summation nodes. As the voltage at the base of transistor 36 increases and the voltage at the base of transistor 38 decreases differentially, the current I 36 increases and the current I 38 decreases. Alternately, as the voltage at the base of transistor 36 decreases and the voltage at the base of transistor 38 increases differentially, the current I 36 decreases and the current I 38 increases. The sum of currents I 36 and I 38 remains equal to current I 40 . Tanh amplifier 16 has a transconductance transfer function as shown in waveform 20 in FIG. 2 and given as: I DIFF1 = I 40 * tanh (V IN /2V t ) where: I DIFF1 = I 36 - I 38 Vt is the transistor thermal threshold voltage (25 millivolts at 25°C.) The current I 40 is adjustable to control the slope of waveform plot 20 and associated gain of amplifier 16. Amplifier 18 has a hyperbolic sine transconductance transfer function. Sinh amplifier 18 includes transistors 50 and 52. The collectors of transistors 50 and 52 are coupled to summation nodes 44 and 46, respectively. As the voltage at the base of transistor 50 increases, the emitter voltage of transistor 50 at node 54 increases accordingly. Transistor 56 conducts a current I 58 determined by current source 58. As the voltage at node 54 increases, the voltage on the base of transistor 56 must increase to maintain the base-emitter voltage (V be ) of transistor 56 such that transistor 56 continues conducting current I 58 . The voltage at the base of transistor 52 is decreasing as the voltage at the base of transistor 50 is increasing. The emitter voltage of transistor 52 at node 64 decreases accordingly. Transistor 62 conducts a current I 70 determined by current source 70. As the voltage at node 64 decreases, the voltage on the base of transistor 62 must decrease to maintain the V be of transistor 62 such that transistor 62 continues conducting current I 70 . With the base voltage of transistor 72 increasing and the base voltage of transistor 74 decreasing, transistor 72 conducts less current and transistor 74 conducts more current. Transistor 50 conducts current I 50 equal to current I 58 plus the current flowing through transistor 74. Transistor 52 conducts current I 52 equal to current I 70 plus the current flowing through transistor 72. Accordingly, the current I 50 increases and the current I 52 decreases in response to the differential input signal. As the voltage at the base of transistor 50 decreases, the emitter voltage of transistor 50 at node 54 decreases accordingly. As the voltage at node 54 decreases, the voltage on the base of transistor 56 must decrease to maintain the V be of transistor 56 such that transistor 56 continues conducting current I 58 . The voltage at the base of transistor 52 is increasing as the voltage at the base of transistor 50 is decreasing. The emitter voltage of transistor 52 at node 64 increases accordingly. As the voltage at node 64 increases, the voltage on the base of transistor 62 must increase to maintain the V be of transistor 62 such that transistor 62 continues conducting current I 70 . With the base voltage of transistor 72 decreasing and the base voltage of transistor 74 increasing, transistor 72 conducts more current and transistor 74 conducts less current. The current I 50 decreases and the current I 52 increases in response to the differential input signal. Sinh amplifier 18 has a transconductance transfer function as shown in waveform 22 in FIG. 2 and given as: I DIFF2 = 2*I 58 * sinh (V IN /2V t ) where: I DIFF2 = I 50 - I 52 I 58 is equal to I 70 The currents I 58 and I 70 are adjustable to control the slope of waveform plot 22 and associated gain of amplifier 18. The currents I 50 and I 52 flow into summation nodes 44 and 46, respectively. Thus, the output current I OUT1 = I 36 + I 50 and the output current I OUT2 = I 38 + I 52 . The output current I OUT of amplification circuit 10 in FIG. 1 is given as I OUT = I OUT1 - I OUT2 , or equivalently: where: A is determined by I 40 B is determined by attenuator 12 C is determined by I 58 D is determined by attenuator 14 The parameters A, B, C, and D are adjustable to maximize the linear operating range of input signal V IN . In one example, the currents I 40 , I 58 , and I 70 are each set to values between 100 microamps to 1 milliamp. The parameters B is set to a value of 0.5 and the parameter D is set to a value of 0.9. By combining the operation of the tanh amplifier and the sinh amplifier and summing the result, the range of linear operation for the input signal increases. In summary, the present invention as set out in the appended claims provides a differential amplifier including a tanh amplifier and a sinh amplifier each receiving an input signal. The input signals to the tanh amplifier and sinh amplifier are independently attenuated. The transfer functions of the tanh amplifier and the sinh amplifier each have a linear region and a non-linear region. The output of the tanh amplifier and the sinh amplifier are summed so that the non-linear region of the tanh amplifier cancels with the non-linear region of the sinh amplifier. The overall transfer function of the differential amplifier is linear over a wide range of input signal amplitudes by the cancellation of the non-linear regions.

Claims: An amplification circuit having an input coupled for receiving an input signal and having an output for providing an output signal, wherein the amplification circuit includes a first amplifier (16) having a hyperbolic tangent transconductance transfer function and having an input coupled for receiving the input signal, a second amplifier (18) having a hyperbolic sine transconductance transfer function and having an input coupled for receiving the input signal, and a combining circuit (26) having first and second inputs coupled to the outputs of the first and second amplifiers respectively and having an output for providing the output signal of the amplification circuit, wherein the second amplifier comprises a first transistor (50) having a first conduction terminal coupled to a first summation node (44) and a control terminal coupled for receiving a first component of the input signal; a second transistor (52) having a first conduction terminal coupled to a second summation node (46) and a control terminal coupled for receiving a second component of the input signal; said first conduction terminals of the first and second transistors providing the output of the second amplifier; characterized in that the second amplifier further comprises: a third transistor (56) having a first conduction terminal coupled to a second conduction terminal of the first transistor, and a second conduction terminal coupled to a control terminal of the third transistor; a fourth transistor (72) having a first conduction terminal coupled to a second conduction terminal of the second transistor, a second conduction terminal coupled to a first power supply conductor, and a control terminal coupled to the control terminal of the third transistor; a first current source (58) having an output coupled to the second conduction terminal of the third transistor; a fifth transistor (62) having a first conduction terminal coupled to the second conduction terminal of the second transistor, and a second conduction terminal coupled to a control terminal of the fifth transistor; a sixth transistor (74) having a first conduction terminal coupled to the second conduction terminal of the first transistor, a second conduction terminal coupled to the first power supply conductor, and a control terminal coupled to the control terminal of the fifth transistor; and a second current source (70) having an output coupled to the second conduction terminal of the fifth transistor. The amplification circuit of claim 1 further including: a first attenuator having an input coupled for receiving the input signal and an output coupled to the input of the first amplifier; and a second attenuator having an input coupled for receiving the input signal and an output coupled to the input of the second amplifier. The amplification circuit of claim 1 wherein the combining circuit includes said first and second summation nodes at first and second outputs of the amplification circuit. The amplification circuit of claim 3 wherein the first amplifier includes: a seventh transistor (36) having a first conduction terminal coupled to the first summation node and a control terminal coupled for receiving said first component of the input signal; an eighth transistor (38) having a first conduction terminal coupled to the second summation node and a control terminal coupled for receiving said second component of the input signal; and a third current source (40) having an output coupled to the second conduction terminal of the seventh transistor and further coupled to the second conduction terminal of the eighth transistor.

Inventors: FINOL JESUS L, LOVELACE DAVID K, FINOL, JESUS L., LOVELACE, DAVID K.
Applicants: MOTOROLA INC, MOTOROLA, INC.
Application year: 1999
Main classification: H03F1
IPC codes: H03F1, H03F3