"Constant duty-cycle limiting of analog input signal swing in a class-D amplifier"

Abstract: A way of establishing a constant limit duty-cycle, substantially independent from fabrication process spread, temperature, etc., and to guarantee an optimal functioning of the final stage of the amplifier for all working conditions consists in detecting the equivalent values of the voltages to which the output signal of the amplifier switches (or pseudo supplies): VDD' and -VDD", respectively, and in making the limiting stage of the voltage swing of analog input signal utilize such pseudo supply values VDD' and -VDD" as respective reference values in limiting the voltage excursion of the analog signal VL output by the input limiting stage to a pre-defined fraction α<1 of such reference values, rather than using as a reference the real supply voltage values VDD and -VDD as commonly done.

Description: FIELD OF THE INVENTION The present invention relates to class-D amplifiers and in particular to integrated PWM audio amplifiers. BACKGROUND OF THE INVENTION The demands of reducing dissipation and optimizing efficiency has recently favored the development and utilization of PWM (Pulse Width Modulation) or PDM (Pulse Density Modulation) class-D amplifiers, even for typical analog applications, such as for example audio and electro-acoustic amplifiers. According to a common approach, the analog signal is converted into a constant frequency digital signal whose duty-cycle depends on the instantaneous value of the analog input signal, thus producing a PWM or alternatively a PDM signal whose average value is an amplified signal, substantially a replica of the analog input signal. This is normally done by means of a converter of an analog input signal into a digital signal (for example a PWM or a PDM signal) switching between the positive and negative supply voltages of the circuit and whose average value represents an amplified replica of the analog input signal. The reconstruction of the analog signal takes place in an output low pass filter. A functional scheme of such an amplifier is shown in Fig. 1. The waveform of the output signal Vop is a square wave whose amplitude is equal to the supply voltage and has a duty-cycle that, according to the diagram of Fig. 1, is given by D = T1/Tsw = (Tsw-T2)/Tsw which depends on the Vin input signal. The diagram of Fig.1 represents the case in which the output signal is positive and therefore the duty-cycle is greater than 50%. The average voltage Vo of the reconstructed signal on the load may be calculated as: Vo = (2*D-1)*VDD The average value Vo is obtained from the output voltage Vop of the amplifying stage G by the low pass filter LC; The gain G of the amplifier being given by: G = Vo/Vin Equation (1) shows that for reproducing a positive output voltage Vo that approximates the positive supply value VDD, it is necessary a duty-cycle D that approximates 1 and therefore a time T2 that tends to 0. However, an excessively small interval T2 may cause at least two problems in a class-D amplifier: because the output switchings of the amplifying stage have a finite rate, if ΔT is the switching time, when T2 becomes less than 2ΔT, the output waveform is strongly distorted, as illustrated in Fig.2, wherein a B type switching causes a strong output distortion and therefore of the audio signal; in amplifiers that use a final stage with a bootstrap capacitance, the functioning is correct until the discharge of the capacitance, which occurs during the time T1 when the output is given by +VDD, is balanced by the charge of the bootstrap capacitance which occurs during the time T2, when the output is low, at -VDD; if T2 tends to 0, the bootstrap capacitance does not recharge and therefore the functioning of the final stage may be compromised (re: US Patent 5,818,209). In order obviate to these problems, it is a common practice to limit the analog input signal Vin between two limiting thresholds commonly referred (dependent) to the actual voltages of the respective supply nodes (VDD and -VDD). Figure 3 shows the complete scheme of a circuit LIMITER that limits the excursion of the analog output voltage VL within a pre-established voltage fraction α<1 of the voltages of the two supply rails. The output signal VL of the circuit LIMITER, relative to an input sinusoid, is shown in Fig. 4. In correspondence of the maximum output voltage of the limiting stage, VLmax= αVDD, in terms of modulus, it is possible to establish through equation (1) the maximum duty-cycle Dlimit required by the final stage of the amplifier G, typically constituted by a half-bridge stage composed of two power devices, a high-side device switching the output to the positive supply VDD node and a low-side device switching the output to the negative supply node -VDD. If G is the amplifier gain, the average voltage of the reconstructed output signal Vo is given by: Vo = G*α*VDD thus, from equation (1) G*α*VDD = (2*Dlimit-1)*VDD and by simplifying: Dlimit = (1+G*α)*0.5 It would appear that by properly selecting the parameters, from equation (5), the limit duty-cycle (Dlimit) could be determined. In reality, equation (5) considers in first approximation as null the series resistance of the amplifier's final stage. By contrast, the delivery of current to the load occurs with a voltage drop on the series resistance of the low-side and high-side power devices. When the amplifier is delivering a positive current Io, the duty-cycle is greater than 50% and the output voltage Vop of the amplifying stage G has a characteristic as shown in Fig. 5. Indeed, VDD' is smaller than VDD by an amount equal to the voltage drop on the series resistance of the high-side power device of the output half-bridge. If Ron is the series resistance of the high-side power device of the final stage and Io is the average output current at a given load of the amplifier, the VDD' voltage is given by: VDD' = VDD-Ron*Io Similar considerations may also be made for a negative output current. The VDD" voltage is equal to the -VDD minus the voltage drop on the low-side device of the final stage. By considering equation (6), it is evident that the apparent supply voltage of the final stage should not be considered fixed to VDD and -VDD, but varying with the output current Io and given by VDD' and -VDD". The equation (1) used to determine the average output positive voltage becomes: Vo = (2*D-1)*VDD' In function of this new relation the limit duty-cycle (Dlimit) may be recalculated in correspondence of the maximum output voltage of the input limiting stage, using equation (7) instead of equation (1). With the same steps of the equations (3), (4), (5), the following equation is obtained: Dlimit = [1+G*α*(VDD/VDD')]*0.5 Since VDD' is smaller than VDD, the real limit duty-cycle considered by equation (8) is greater than the one considered by equation (5). Moreover, the VDD' depends on the output current and on the series resistance of the high-side power device of the output stage, which in turn depends on technological and manufacturing parameters, on the temperature, etc. Similar considerations may be made also for a negative output voltage -VDD" which is similarly limited by the voltage drop on the low-side power device of the output stage. Therefore, it is difficult to forecast with a sufficient precision the limit duty-cycle for any operating condition of the amplifier and difficult to guarantee an optimal functioning of the final stage under all conditions. PURPOSE AND SUMMARY OF THE INVENTION In view of these difficulties it has now been found and constitutes the object of the present invention a way of establishing a constant limit duty-cycle, substantially independent from fabrication process spread, temperature, etc., and to guarantee an optimal functioning of the final stage of the amplifier for all working conditions. Essentially, the method of the invention consists in detecting the equivalent values of the voltages to which the output signal of the amplifier switches (or pseudo supplies): VDD' and -VDD", respectively, and in making the limiting stage of the voltage swing of analog input signal utilize such pseudo supply values VDD' and -VDD" as respective reference values in limiting the voltage excursion of the analog signal VL output by the input limiting stage to a pre-defined fraction α<1 of such reference values, rather than using as a reference the real supply voltage values VDD and -VDD as commonly done. In this way, the role of the input limiter stage is to limit the maximum value of the positive voltage excursion to a αVDD' value and to limit the maximum value of the negative voltage excursion to -αVDD", that is, to threshold values that are not fixed but vary dynamically and independently from one another in function of the real working conditions of the amplifier. Therefore, the limit duty-cycle of the output Vop of the block that converts the analog signal, limited in amplitude, into a digital signal with an average value correspondent to the analog signal is definable in a precise and constant way and is substantially independent from process spread and temperature. This is implemented, according to an aspect of the invention, by realizing substantially a feedback loop constituted by a circuit, to the input of which is fed the output signal Vop of the amplifier, switching between the values VDD' and -VDD" in function of the amplifier working conditions and which divides it by a determined ratio a and produces through two distinct signal paths two output signals, the first being equivalent to αVDD' and the second to -αVDD". These two dynamically varying threshold values are fed to limiter circuit of the amplitude of the analog input signal of the amplifier, preforming a "clipping" of the analog input signal at thresholds so independently and dynamically generated. The invention is defined in claim 1 and in claim 2. BRIEF DESCRIPTION OF THE DRAWINGS The different aspects and advantages of the invention will become even more evident through the following description of an embodiment and by referring to the attached figures, in which: Figure 1 as already discussed is a scheme and a relative diagram of a class-D amplifier; Figure 2 shows the switching waveforms of the digital output signal; Figure 3 is a basic scheme of the amplifier of Figure 1, provided with a limiter stage of the analog input signal, according to a known technique; Figure 4 shows the effect of the input limiter stage; Figure 5 is a diagram of the waveform of the digital output signal of the amplifier, showing the voltage drop occurring in the final stage of the amplifier; Figure 6 is a basic scheme of a class-D amplifier with limitation of the amplitude of the analog input signal with a constant duty-cycle; Figure 7 shows a circuit suitable to dynamically generate limiting thresholds of the analog input signal, according to the present invention; Figure 8 shows the limiting circuit of the amplitude of the analog input signal employing the dynamically generated threshold values produced by the circuit of Fig. 7. DESCRIPTION OF AN EMBODIMENT OF THE INVENTION With reference to the basic scheme of Figure 6, the method of the invention consists in limiting the dynamic voltage excursion of the analog input signal Vin, using dynamic clipping thresholds αVDD' and -αVDD", independently generated, whose VDD' and -VDD" values correspond to the relative supply voltages VDD and -VDD decremented by the voltage drop that occurs on the series resistance of the respective power device of the half-bridge output stage of the class-D converting and amplifying circuit. Therefore, the two thresholds are generally different and depend on the value and on the direction of the average current Io delivered to the load. The scheme of Figure 6 considers the case of non-inverting amplifying stage with a gain G, as previously defined. The positive clipping threshold of the VL voltage output by the limiter is αVDD', while the negative clipping threshold will be -αVDD". If the Vin input is positive and such to have a VL voltage limited to αVDD', the limit duty-cycle Dlimit of the output voltage Vop may be determined as follows: VLmax = α*VDD' therefore, by the same steps (3), (4), (5) the same equation (5) for the limit duty-cycle is: Dlimit = (1+G*α)*0.5 which is constant, independently from the technological parameters of the manufacturing process or the temperature. A possible embodiment of a suitable circuit to generate the pair of dynamic reference thresholds used to limit the maximum excursion of the analog input signal is depicted in Fig. 7. The output of the amplifying stage G is coupled to the circuit input. The input signal Vop of the circuit is a square wave of varying duty-cycle and with a voltage "swing" between the positive switching voltage VDD' and the negative switching voltage VDD". Therefore, the digital signal applied to the Vop input already includes the voltage drops on the respective high-side and low-side power devices of the final power stage of the amplifier. The input voltage divider R1, R2 establishes the limiting factor given by: α = R2/(R1+R2) The circuit defines two signal propagation paths, one toward the output onto which is dynamically generated the desired positive voltage threshold Vth-up, and the other toward the output onto which is dynamically generated the desired negative voltage threshold Vth-down. Each signal path includes a comparator, respectively CMP 1 and CMP2, which compares the voltage of the intermediate node of the input divider with the ground potential GND, which is applied to inverting input of the comparator CMP1 of the upper branch and to noninverting input of the comparator CMP2 of the lower branch. The output of each comparator controls a pass-gate, respectively PG1 and PG2, which controls the charge and the discharge of a respective output capacitor, Cup and Cdown. The functioning is easily comprehended. When the digital signal Vop is high, its voltage level is at VDD'. The comparator CMP1 has a high output and therefore the pass-gate PG1 is closed. The Vth-up voltage on the output capacitance Cup is in a phase of acquisition of the voltage value αVDD'. During this phase, the other comparator CMP2 has a low output. The pass-gate PG2 is open and the Vth-down voltage is on a "hold" phase of the voltage value previously acquired. When the input digital signal Vop is low, its voltage value is at -αVDD". The comparator CMP1 has a low output and therefore the PG1 is open. The Vth-up voltage on the output capacitance Cup retains the value previously acquired at αVDD'. On the contrary, during this phase, the Vth-down voltage is in a phase of acquisition of the negative value -αVDD". Therefore, the circuit generates two thresholds, Vth-up and Vth-down, respectively, which track, independently from one another, αVDD' and -αVDD", respectively. The two dynamically varying and independent from one another thresholds are fed to a limiter circuit of the maximum amplitude of the analog input signal that performs a clipping at these dynamic threshold values: Vth-up and Vth-down. The limiter circuit may be realized in the form shown in Fig. 8. When the analog input signal Vin has a level between the two thresholds Vth-up and Vth-down, both comparators CMP3 and CMP4 have a low output and the pass-gate PG3 is closed while the other two pass-gates PG4 and PG5 are open. Therefore the output of the limiter stage VL is equal to the input Vin. Assuming that the input Vin becomes higher than the threshold Vth-up, the CMP3 output becomes high and therefore the pass-gate PG4 is closed, while the pass-gate PG3 opens. Therefore, the output VL coincides with the high threshold value Vth-up. By contrast, when Vin becomes lower than the low threshold Vth-down, VL is equal to the low threshold Vth-down. A clipping of the VL voltage to the respective instantaneous values of Vth-up and Vth-down is thus achieved.

Claims: A method of constant duty-cycle limiting in an class-D amplifier that entails limiting the maximum amplitude of an analog input signal (Vin), modulating the amplitude limited analog signal (VL) generating a digital output signal (Vop) switching between two voltages (VDD', -VDD"), each corresponding to the voltage (VDD, -VDD) of the respective supply rail of an output power stage of the amplifier less the voltage drop on a respective power device of the stage, with an average value representing an amplified replica of the amplitude limited analog input signal and regenerating an amplified analog signal (Vo) by a reconstructing low pass filter (L, C, RL), characterized in that it comprises feeding said digital signal (Vop) to the input of a circuit generating a pair of voltages of positive threshold (Vth-up) and of negative threshold (Vth-down), respectively, each corresponding to a pre-defined fraction (α) of the respective voltage (αVDD, -αVDD") which the digital signal switches to; limiting the maximum amplitude of the analog input signal to said two voltages of positive threshold (Vth-up) and of negative threshold (Vth-down). A system of constant duty-cycle limiting in an class-D amplifier comprising a circuit (LIMITER) limiting the maximum amplitude of an analog input signal (Vin), a modulating stage (G) outputting a digital signal (Vop) switching between two voltages (VDD', -VDD"), each corresponding to the voltage (VDD, -VDD) of the respective supply rail of an output power stage of the modulating stage less the voltage drop on a respective power device of the stage, with an average value representing an amplified replica of the amplitude limited analog input signal (VL), and a regenerating low pass filter (L, C, RL), characterized in that said limiting circuit (LIMITER) has a second and a third input through which are applied a positive threshold voltage (Vth-up) and a negative threshold voltage (Vth-down), respectively; a circuit generating said positive threshold (Vth-up) and said negative threshold (Vth-down), independently and dynamically as a pre-established fraction (α) of the respective switching voltage (VDD', -VDD") of the digital signal output by said modulating stage (G). The system of claim 2, characterized in that said threshold generating circuit is composed of an input voltage divider (R1, R2) coupled to the output node of said amplifying stage (G) and defining two propagation paths of the digital signal present on the intermediate node of said input divider toward two respective outputs onto which are generated said two threshold voltages (Vth-up, Vth-down); each path including a comparator (CMP1, CMP2) controlling a respective pass-gate (PG1, PG2) and a switched output capacitor (Cup, Cdown) electrically connected between the respective output and a common ground node of the circuit; the comparator (CMP 1) of the signal path toward the output onto which is generated said positive voltage threshold (Vth-up) has a noninverting input connected to the intermediate node of said input voltage divider and an inverting input node connected to ground. the comparator (CMP2) of the path toward the output onto which is generated said negative voltage threshold (Vth-down) has an inverting input connected to the intermediate node of said input voltage divider and a noninverting input node connected to ground.

Inventors: MASINI MARCO, TAVAZZANI CLAUDIO, MASINI, MARCO, TAVAZZANI, CLAUDIO
Applicants: ST MICROELECTRONICS SRL, STMICROELECTRONICS S.R.L.
Application year: 1999
Main classification: H03F3
IPC codes: H03F3, H03G11