ZERO DC CURRENT POWER-ON RESET CIRCUIT

Abstract: The present invention provides a power-on reset circuit (300) that consumes zero DC current including a transistor (P1), capacitor (C), a resistor (R) and an inverter (302).

Description: ZERO DC CURRENT POWER-ON RESET CIRCUIT FIELD OF THE INVENTION The present claimed invention relates to the field of power-on reset circuits. More particularly, the present claimed invention teaches power-on reset circuits that consume zero current in steady state and zero current methods for resetting circuits during power-on. BACKGROUND ART Integrated circuit (IC) chips are used and incorporated in virtually every segment of modern electronic and computer products. For example, modern products such as computers, telephones, electronic goods, etc. typically include one or more IC chips. These IC chips often include elements for storing states such as latches, flip-flops, static random access memory (SRAM), and the like. Often, users keep the products or systems that include these IC chips at power off mode when idle and power them up as needed. This arrangement saves energy and may prolong the life of the products. However, when an IC chip is powered up from a power off mode, the internal elements of the IC chip may not power up in their proper states. To address this problem, modern IC chips may include a power-on reset circuit to provide a signal that can be used to set or reset internal storage elements in the IC chips during the power up phase. The signal can also be used to disable a selected circuit. Prior Art Figure 1 illustrates a schematic block diagram of an IC chip 100 that uses a power-on reset circuit 102 to set a plurality of latches to a known state. The IC chip 100 includes the power-on reset circuit 102, which generates a power-on (POR) signal over line 103 during the power up phase of the IC chip 100. The latches 104, 106, 108, 110, and 112 (hereinafter 104 through 112) are arranged to receive and latch address signals A0 through An. The latched addresses are then transmitted to an address decoder 114, which determines and outputs address signals over lines 116. The address signals over lines 116 are fed into an analog multiplexer (AMUX) 118 as control signals. The AMUX 118 receives a plurality of inputs channels 120. The AMUX 118 is comprised of a plurality of switches and essentially determines which switches are enabled based on the input addresses over lines 116. Typically, only one switch in the AMUX 118 can be on at any one time. The AMUX 118 selects a channel from one of a plurality of channels 120 in response to the address signal over lines 116 and outputs the signal present at the selected channel at an output 122. In the IC chip configuration of Prior Art Figure 1, the POR circuit 102 generates a POR signal over line 103 during a power up phase. The POR signal over line 103 is fed into each of the latches 104 thorough 112 to set them to a known state such as all "1" or "0" signals. These initial states are then provided to the address decoder 114, which generates known address signals over lines 116. The known address signals then turns on only one switch in the AMUX 118, thereby ensuring proper functioning of the AMUX 118. Without a power-on reset circuit, the latches 104 through 112 may have random or unknown initial states when the IC chip is powered up. The unknown states may cause unknown data to be fed into the address decoder 114, resulting in generation of improper address signals. When different input voltages are applied to the input channels 120, more than one switch in the AMUX 118 may become operational due to the garbage address. The operation of more than one switch at one time results in an improper functioning of the AMUX 118. One drawback of conventional power-on reset circuits is consumption of current during the power-on steady state (as opposed to the transition period from power-off to power-on). Prior Art Figure 2 illustrates a conventional power-on reset circuit 200, which consumes a current Iref in the steady state. The power-on reset circuit 200 includes a transistor M3, which is coupled to a supply voltage rail Vcc at its source and a ground potential at its gate. The drain of the transistor M3 is coupled at a reference node 202 to a pair of transistors Ml and M2 connected in series. The transistors Ml and M2 are diode connected to provide a supply independent voltage reference at the reference node 202. Specifically, the diode connected transistors Ml and M2 set up a supply independent voltage at the reference node 202 equal to the sum of the threshold voltages of the transistors Ml and M2. With reference still to Prior Art Figure 2, the transistor M3 is a very weak p-type metal- oxide-semiconductor (PMOS) transistor with channel width to length ratio (i.e., W/L) being much less than 1. Accordingly, the transistor M3 feeds a current, Iref, to the reference node 202 to set up a reference voltage, Vref, at the reference node 202. The reference voltage, Vref, is equal to the sum of the threshold voltages of the transistors Ml and M2. - The power-on reset circuit 200 also includes a complementary MOS (CMOS) inverter coupled to the reference node 202. The CMOS inverter includes an n-type MOS (NMOS) transistor M4 and a PMOS transistor M5. The gates of the transistors M4 and M5 are coupled to each other and to the reference node 202. A first inverter II receives the output of the CMOS inverter as an input and outputs an inverted signal at a node 206. A second inverter 12 is coupled to the node 206 to receive the inverted signal as its input. The second inverter 12 inverts the inverted signal and feeds the inverted signal into a NAND gate 210. The power-on reset circuit 200 further includes a pair of PMOS transistors M6 and M7 coupled in series. Specifically, the source of the transistor M6 is coupled to the supply voltage rail Vcc and the gate is coupled to ground potential. The source of the transistor M7 is coupled to the drain of the transistor M6 and the gate of the transistor M7 is coupled to the node 206. The drain of the transistor is connected to the other input of the NAND gate 210 at a node 208. A capacitor Cl is also coupled to the node 208. Based on the output of the second inverter 12 and the signal at node 208, the NAND gate 210 generates a POR signal that can be used to reset components of IC chips. When Vcc is initially turned on, the transistor M3 feeds a small current Iref to the reference node 202. The Iref, in turn, sets up a reference voltage Vref, which is two threshold voltages above the ground potential assuming that the transistors Ml and M2 are matching transistors with one threshold voltage associated with each. The reference voltage Vref at the reference node 202 is substantially independent of the supply voltage Vcc. This is because the W/L ratio of the transistor M3 is much less than 1 while the W/L ratios of the transistors Ml and M2 are typically much larger than that of transistor M3. With continuing reference to Prior Art Figure 2, the supply voltage Vcc increases upon power up. When Vcc reaches one threshold voltage above Vref, the transistor M5 turns on and pulls the voltage at the node 204 high. In turn, the inverter II outputs a low voltage signal at the node 206. The low voltage signal at the node 206 turns on the transistor M7. The "on" transistor M7 then draws current to the node 208, thereby charging the capacitor Cl . The capacitor Cl functions as a time delay element to ensure that the output POR signal remains active for a sufficient duration to enable an external circuit to be set or reset to a known state when the supply voltage Vcc ramps up too quickly. The NAND gate 210 is coupled to receive its inputs from the output of the second inverter 12 and the node 208. The NAND gate 210 switches state when the voltage at the node 208 reaches the trip point of the NAND gate 210. Accordingly, the NAND gate 210 outputs a low POR signal which can be used to set other circuitry in an IC chip to a known state. Unfortunately as is apparent from the above description, the power-on reset circuit 200 consumes some current Iref at all stages of operation, both during start-up and steady-state. Consumption of current translates directly into undesirable power consumption and heat generation in an IC chip, and leads to shortening of battery life in portable equipment. Thus, what is needed is a circuit and method for generating a power-on signal while consuming zero DC current in the steady state. SUMMARY OF THE INVENTION Broadly speaking, the present invention fills these needs by providing a circuit that generates a power-on signal while consuming zero DC current. It should be appreciated that the present invention can be implemented in numerous ways, including as a process, an apparatus, a system, a device, or a method. Several inventive embodiments of the present invention are described below. In one embodiment, the present invention provides a power-on reset circuit that consumes zero DC current. The power-on reset circuit generates a power-on reset signal from a supply voltage that rises until reaching a final value. The power-on circuit includes a first transistor, a capacitor, a resistor, and an inverter. The first transistor has threshold turn-on voltage and is arranged to generate a reference voltage at a reference node from the supply voltage. The first transistor turns on when the supply voltage reaches the threshold voltage so that the reference voltage remains below the supply voltage by at least the threshold voltage. The capacitor is coupled to the first transistor at the reference node and is arranged to be charged when the supply voltage is greater than the threshold voltage of the first transistor. The resistor is coupled to the transistor for slowing down the charging of the capacitor when the supply voltage increases rapidly. The first inverter is coupled to the first transistor at the reference node to receive the reference voltage for generating an inverted output as the power-on reset signal. In another embodiment, the power-on reset circuit includes a switching means, a delay means, and an inverting means. The switching means generates a reference voltage from the supply voltage. The switching means turns on when the supply voltage reaches a predetermined voltage so that the reference voltage remains below the supply voltage by at least the predetermined voltage. The delay means slows down the rise of the reference voltage when the supply voltage increases rapidly. The inverting means inverts the reference voltage to generate an inverted output as the power-on reset signal. In yet another embodiment, the present invention provides a method for generating a power-on reset signal from a supply voltage that rises until reaching a final value. The method generates a reference voltage from the supply voltage. The reference voltage remains below the supply voltage by at least the predetermined voltage. When the supply voltage increases rapidly, the method decreases the rise of the reference voltage in compensation. The method inverts the reference voltage to generate an inverted output as the power-on reset signal. Advantageously, the power-on reset circuit and method of the present invention provides the benefit of substantially zero DC current while operating in the steady state. Operating at substantially zero DC current not only saves power and prolongs battery life, but also reduces heat, which continues to present a significant problem for high speed IC chips. Other aspects and advantages of the invention will become apparent from the following detailed description, taken in conjunction with the accompanying drawings, illustrating by way of example the principles of the invention. BRIEF DESCRIPTION OF THE DRAWINGS The accompanying drawings, which are incorporated in and form a part of this specification, illustrate embodiments of the invention and, together with the description, serve to explain the principles of the invention: Prior Art Figure 1 illustrates a schematic block diagram of an IC chip that uses a power- on reset circuit to set a plurality of latches to a known state. Prior Art Figure 2 illustrates a conventional power-on reset circuit, which consumes a current Iref in the steady state. Figure 3 A illustrates an exemplary power-on reset circuit that generates a power-on reset (POR) signal while consuming zero current in the steady state in accordance with one embodiment of the present invention. Figure 3B illustrates the power-on reset circuit with additional inverters, which are coupled to a first CMOS inverter in cascade. Figure 4 illustrates a graph of a supply voltage Vcc, a reference voltage Vref, and a POR signal voltage as a function of time for the exemplary power-on circuit depicted in Figures 3 A and 3B. DESCRIPTION OF THE PREFERRED EMBODIMENTS In the following detailed description of the present invention, a zero DC current power-on reset circuit and a method therefor, numerous specific details are set forth in order to provide a thorough understanding of the present invention. However, it will be obvious to one skilled in the art that the present invention may be practiced without these specific details. In other instances, well known methods, procedures, components, and circuits have not been described in detail so as not to unnecessarily obscure aspects of the present invention. Figure 3A illustrates a power-on reset circuit 300 that generates a power-on reset (POR) signal while consuming substantially zero current in the steady state in accordance with one embodiment of the present invention. The power-on reset circuit 300 includes transistors PI and P6, a resistor R, a capacitor C, and an inverter 302. In the preferred embodiment of the present invention, the transistors PI and P6 are MOSFET transistors. In the embodiment of Figure 3 A, the transistors PI and P6 are p-type MOSFET transistors. Each of the transistors PI and P6 has a source, a drain, and a gate. The source and gate of the transistor P6 are coupled to each other and to a supply voltage rail Vcc. The drain of the transistor P6 is coupled to the gate and drain of the transistor PI at a reference node 304. Hence, the transistor P6 forms a reverse biased diode. The drain of the transistor P6 is coupled to the gate and drain of the transistor PI at the reference node 304, which is associated with a reference voltage Vref. The transistor PI is thus diode connected and turns on when the supply voltage Vcc is greater than or equal to the threshold voltage, V τ , of the transistor PI. The source of transistor PI is coupled to the resistor R. The resistor R, in turn, is connected to the supply voltage rail, Vcc. As mentioned previously, the reference node 304 is connected to the gate and drain of the transistor PI and is capacitively coupled to ground potential through the capacitor C. Preferably, the capacitor is an MOSFET capacitor integrated into an IC chip along with the rest of the power-on reset circuit elements. . The inverter 302 is coupled to the reference node 304 to receive the reference voltage Vref as its input. The inverter 302 inverts the input Vref and outputs the inverted signal as the POR signal. In certain embodiments, the inverter 302 is implemented as a CMOS inverter including a PMOS transistor and an NMOS transistor. With reference still to Figure 3A, the supply voltage Vcc starts to increase from some initial state (e.g., zero volts) upon power-up. As Vcc ramps up from zero volts, the reference voltage Vref at the reference node 304 is initially at ground potential due to the capacitive coupling to ground potential through the capacitor C. The drain of the transistor P6 is coupled to the gate and the drain of the transistor PI at the reference node 304. The gate to source connection of the transistor P6 functions as a reverse biased diode so that when the supply voltage Vcc drops below the reference voltage Vref to within the threshold voltage V τ of the transistor P6, the transistor P6 turns on to provide a path to discharge the capacitor C. Since the transistor PI is diode connected, the reference voltage Vref remains at the ground potential until the supply voltage Vcc reaches the threshold voltage, V τ , of the transistor PI. When the gate to source voltage of the transistor PI reaches the threshold voltage V τ , the transistor PI turns on and the reference voltage Vref at the reference node 304 starts to rise. The diode connection of the transistor PI ensures that the difference between the reference voltage Vref and the supply voltage Vcc is greater than or equal to its threshold voltage V τ . The supply voltage Vcc continues to increase until it reaches the full Vcc voltage. Likewise, the reference voltage Vref increases and levels off at a constant voltage level below the Vcc voltage. The inverter 302 inverts the reference voltage Vref and outputs the inverted signal as a POR signal. Initially when the transistor PI is off, the POR signal tracks the ground potential of the reference voltage Vref. When the transistor PI turns on, the POR tracks the supply voltage Vcc. Upon reaching the trip point of the inverter 302, i.e., the point at which the inverter 302 changes output state in response to an input signal, the POR signal drops back to the ground potential. In the power-on circuit 300 of Figure 3 A, the capacitor C and the resistor R together perform time delay functions to provide insensitivity to changes in the supply voltage Vcc. Specifically, when the supply voltage Vcc increases very fast, the resistor R acts to slow down rise of the reference voltage Vref at the reference node 304 by slowing down the charging of the capacitor C. On the other hand, if the supply voltage Vcc increases slowly, the resistor R does not inhibit rise in the reference voltage Vref. In this case, the reference node voltage Vref closely follows the supply voltage Vcc at about one threshold voltage V r below Vcc. In the preferred embodiment, the inverter 302 is a CMOS inverter that draws substantially zero current in the steady state. The power-on reset circuit 300 of the present embodiment can include one or more inverters to generate a POR signal of either active low or high polarity. It should be appreciated that these inverters can be used as buffers to drive the POR signal into other components of an IC circuit. Figure 3B illustrates the power-on reset circuit 300 with additional inverters 306 and 308, which are coupled to the CMOS inverter 302 in cascade. The power-on reset circuit 300 implements the inverter 302 in Figure 3 as a first CMOS inverter 302 comprised of MOS transistors N2 and P2. Additionally, the power-on reset circuit 300 includes a pair of optional second and third CMOS inverters 306 and 308, respectively, coupled in cascade to the first CMOS inverter 302. The second optional CMOS inverter 306 includes MOS transistors N3 and P3, and is coupled to the first CMOS inverter 302 in series. The third optional CMOS inverter 308 includes MOS transistors N4 and P4, and is coupled to the second CMOS inverter 306 in cascade. Each of the CMOS inverters 302, 306, and 308 is coupled to supply voltage rail Vcc and ground potential. The power-on reset circuit 300 generates a POR signal at the output of the second CMOS inverter 308. With continuing reference to Figure 3B, in certain embodiments, the transistors PI, P2, P3, P4, and P6 are PMOS transistors and the transistors N2, N3, and N4 are NMOS transistors. The transistors PI and P2 are preferably designed as substantially high threshold devices and have substantially matching threshold voltages, V τ . In one embodiment, the threshold voltage for the transistors PI and P2 is about 1 volt. Additionally, the transistor N2 is also, preferably, a high threshold device with approximately 1 volt of threshold voltage. It should also be appreciated that the transistors PI, P2, P3, P4, P6, N2, N3, and N4 function as switches or switching devices and can be implemented as such. The device parameters are configured to draw substantially zero current through the transistor PI in the stead state while generating the POR signal. In one embodiment, the channel width-to-length (W/L) ratios of the PMOS transistors PI, P2, P3, P4, P6 are 5/10, 10/5, 20/5, 20/5, and 10/10, respectively, while the W/L ratios of the NMOS transistors N2, N3, and N4 are 5/40, 10/5, and 10/5, respectively. In addition, the capacitance value of the capacitor C is between 2 and 3 picofarads (pF) and the resistance value of the resistor R is about 500KΩ. In this configuration, the W/L ratio (e.g., 10/5) of the transistor P2 is much larger than the W/L ratio (e.g., 5/40) of the transistor N2. This disparity in the W/L ratios is designed to obtain the desired trip point for the inverter 302 formed by transistors P2 and N2. In the power-on circuit 300 configuration of Figure 3B, the second and third COMS inverters 306 and 308 coupled in cascade to the output of the first CMOS inverter 302 function as additional buffers to drive the original POR signal at the output of the first COMS inverter 302 into other components of an IC circuit. The second CMOS inverter 306 receives the original POR signal from the first COMS inverter and inverts the input signal. The second CMOS inverter 306 then outputs the inverted POR signal, which is then fed into the third CMOS inverter 308. The third COMS inverter 306 then inverts the received signal and outputs the twice inverted power-on signal as the power-on signal. Although the present embodiment illustrates three inverters, it should be borne in mind that the power-on circuit of the present invention can include any number of inverters suitable to generate a suitable output level and/or buffer drive. Figure 4 illustrates a graph 400 of one possible supply voltage Vcc and the resultant reference voltage Vref and the resultant POR signal voltage (shown as a hatched line) as a function of time for the power-on circuit 300 illustrated in Figures 3 A and 3B. Initially upon power up, the supply voltage Vcc starts to rise linearly in a ramp function. The reference voltage Vref and the POR signal voltage are initially at ground potential until the supply voltage Vcc reaches the threshold voltage V τ of the transistor PI . This is because the transistor PI is off during the time it takes the supply voltage to reach the threshold voltage V τ . When the supply voltage reaches the threshold voltage V τ , the transistor PI turns on. As the supply voltage Vcc continues to rise, the reference voltage Vref starts to increase and the capacitor C is charged. During this phase, the reference voltage Vref remains at one threshold voltage V τ below the supply voltage Vcc due to the diode connection of the transistor PI . After the supply voltage Vcc reaches the threshold voltage V τ , the power-on signal voltage almost immediately begins to track the supply voltage Vcc due to the inversion of the reference voltage Vref by the first inverter 302. The power-on signal voltage continues to track the supply voltage Vcc in this manner until the trip point of the first inverter 302 is reached. As the supply voltage Vcc, the reference voltage Vref, and the power-on signal voltage rise, the reference voltage Vref reaches a trip point 402 for the first inverter 302. At this trip point 402, the first inverter 302 changes its output signal and thus the power-on reset signal voltage. Accordingly, the POR signal voltage abruptly drops to the ground potential and remains at that voltage level. When the rise of the supply voltage Vcc is steep, the time delay elements, namely the resistor R and the capacitor C in the power-on circuit, counteract the fast " rise by slowing down the charging of the capacitor in the power-on circuit 300. On the other hand, when the rise of the supply voltage is not fast, the reference voltage Vref follows the supply voltage Vcc at one threshold voltage V τ below the supply voltage Vcc (i.e., Vcc-V τ ). In this manner, the power-on circuit 300 of the present invention substantially counteracts for variations in the rise of the supply voltage Vcc. Once the supply voltage Vcc has reached the full value of the supply voltage, the supply voltage Vcc levels off at a substantially constant level of the full Vcc value. The reference voltage Vref eventually reaches the Vcc voltage in the steady state, at which point the current flow stops and DC current is zero. The POR signal, on the other hand, maintains the ground potential previously reached at the trip point 402 of the first inverter 302. The power-on reset circuit of the present invention thus operates to provide a power on signal to set or reset circuitry in IC chips to known states. Advantageously, the power-on reset circuit and method of the present invention provides the benefit of substantially zero DC current while operating in the steady state. Operating at substantially zero DC current saves power and prolongs battery life while reducing heat, which continues to present a significant problem for high speed IC chips. While the present invention has been described in terms of several preferred embodiments, there are alterations, permutations, and equivalents which fall within the scope of this invention. It should also be noted that there are alternative ways of implementing both the method and apparatus of the present invention. It is therefore intended that the following appended claims be interpreted as including all such alterations, permutations, and equivalents as fall within the true spirit and scope of the present invention.

Claims: CLAIMS What is claimed is: 1. A power-on reset circuit for generating a power-on reset signal from a supply voltage that rises until reaching a final value, the circuit comprising: a first transistor having a threshold voltage and arranged to generate a reference voltage at a reference node from the supply voltage, wherein the first transistor turns on when the supply voltage reaches the threshold voltage so that the reference voltage remains below the supply voltage by at least the threshold voltage until the supply voltage reaches the final value; a capacitor coupled to the first transistor at the reference node, the capacitor being arranged to be charged when the supply voltage is greater than the threshold voltage of the first transistor; a resistor coupled to the transistor for slowing down the charging of the capacitor when the supply voltage increases rapidly; and a first inverter coupled to the first transistor at the reference node to receive the reference voltage for generating an inverted output as the power-on reset signal. 2. The power-on reset circuit as recited in claim 1 further comprising: a second transistor coupled to the first transistor and the capacitor at the reference node for discharging the capacitor when the supply voltage drops to within a predetermined voltage level below the reference voltage at the reference node. 3 The power-on reset circuit as recited in claim 1 further comprising: a diode coupled to the first transistor and the capacitor at the reference node for discharging the capacitor when the supply voltage drops to within a predetermined voltage level below the reference voltage at the reference node. 4. The power-on circuit as recited in claim 1 , wherein the first transistor is a diode connected transistor. 5. The power-on reset circuit as recited in claim 2, wherein the second transistor is a diode connected transistor. 6. The power-on reset circuit as recited in claim 5, wherein the first and second transistors are MOSFETs. 7. The power-on reset circuit as recited in claim 6, wherein the first transistor has a gate, a drain, and a source, wherein the gate and the drain of the first transistor are coupled to the reference node and the source of the first transistor is coupled to the resistor. 8. The power-on reset circuit as recited in claim 7, wherein the second transistor has a gate, a drain, and a source, wherein the gate and the source of the second transistor are coupled to the reference node and the drain of the second transistor is coupled to the supply voltage. 9. The power-on reset circuit as recited in claim 8, wherein the resistor is coupled to the supply voltage and the capacitor is coupled to a ground potential. 10. The power-on reset circuit as recited in claim 2, wherein the second transistor is a diode. 11. The power-on reset circuit as recited in claim 2, wherein the second transistor is reverse biased. 12. The power-on reset circuit as recited in claim 4, wherein the predetermined voltage level is the threshold voltage of the first transistor. 13. The power-on reset circuit as recited in claim 2, wherein the first inverter is a complementary MOS (CMOS) inverter. 14. The power-on reset circuit as recited in claim 13, wherein the first inverter comprises a p-type MOS transistor coupled in series with an n-type MOS transistor. 15. The power-on reset circuit as recited in claim 13 further comprising: a second inverter coupled to the first inverter in series to receive the power-on signal for inverting the power-on signal and outputting the inverted power-on signal as the power-on signal. 16. The power-on reset circuit as recited in claim 15 further comprising: a third inverter coupled to the second inverter in series to receive the inverted power-on signal for inverting the inverted power-on signal and outputting the twice inverted power-on signal as the power-on signal. 17. The power-on reset circuit as recited in claim 16, wherein the second and the third inverter are complementary MOS (CMOS) inverters. 18. The power-on reset circuit as recited in claim 17, wherein the each of the CMOS inverters of the second and third inverters includes a p-type MOS transistor coupled in series with an n-type MOS transistor. 19. The power-on reset circuit as recited in claim 16, wherein each of the first, second, and third inverters are coupled between a supply voltage potential and a ground potential. 20. The power-on reset circuit as recited in claim 16, wherein the first transistor and the transistors of the first inverter have matching threshold voltages. 21. The power-on reset circuit as recited in claim 16, wherein the first transistor and the transistors of the first inverter are high threshold devices. 22. The power-on reset circuit as recited in claim 16, wherein the first and the second transistors are p-type transistors. 23. The power-on reset circuit as recited in claim 22, wherein the first transistor and the transistors of the first inverter have a threshold voltage of about 1 volt. 24. The power-on reset circuit as recited in claim 16, wherein the channel width to length (W/L) ratio for the first transistor is about 5/10. 25. The power-on reset circuit as recited in claim 24, wherein the W/L ratios for the p-type and n-type MOS transistors are about 10/5 and 5/40, respectively. 26. The power-on reset circuit as recited in claim 1, wherein the circuit components of the of the power-on reset circuit are formed within a single integrated circuit device. 27. The power-on reset circuit as recited in claim 1, wherein the power-on reset circuit is formed within an integrated circuit device that is suitable for use within a cellular communications system. 28. The power-on reset circuit as recited in claim 1 , wherein the power-on reset circuit provides the power-on reset signal to memory units. 29. The power-on reset circuit for generating a power-on reset signal from a supply voltage that rises until reaching a final value, the circuit comprising: a first switching means for generating a reference voltage from the supply voltage, wherein the switching means turns on when the supply voltage reaches a predetermined voltage so that the reference voltage remains below the supply voltage by at least the predetermined voltage; a delay means for slowing down the rise of the reference voltage when the supply voltage increases rapidly; and a first inverting means for inverting the reference voltage to generate an inverted output as the power-on reset signal. 30. The power-on reset circuit as recited in claim 29, wherein the delay means comprises: a charging means for charging when the supply voltage is greater than the threshold voltage of the switching means; and a resistor means for slowing down the charging of the charging means when the supply voltage increases rapidly. 31. The power-on reset circuit as recited in claim 30 further comprising: a second switching means for discharging the charging means when the supply voltage drops to within the predetermined voltage level below the reference voltage. 32. The power-on reset circuit as recited in claim 31 further comprising: a second inverting means for inverting the power-on signal and for outputting the inverted signal as the power-on signal. 33. The power-on reset circuit as recited in claim 32 further comprising: a third inverting means for inverting the new power-on signal and outputting the twice inverted signal as the power-on signal. 34. The power-on reset circuit as recited in claim 31 , wherein the first switching means is a transistor. 35. The power-on reset circuit as recited in claim 31, wherein the charging means is a capacitor. 36. The power-on reset circuit as recited in claim 31 , wherein the resistor means is a resistor. 37. The power-on reset circuit as recited in claim 31 , wherein the first inverting means is a complementary MOS (CMOS) inverter. 38. A method for generating a power-on reset signal from a supply voltage that rises until reaching a final value, the method comprising: generating a reference voltage from the supply voltage, wherein the reference voltage remains below the supply voltage by at least the predetermined voltage; decreasing the rise of the reference voltage when the supply voltage increases rapidly; and inverting the reference voltage to generate an inverted output as the power-on reset signal. 39. The method as recited in claim 38, wherein the decreasing further comprises: charging a capacitor when the supply voltage is greater than the threshold voltage of the switching means; and slowing down the charging of the capacitor when the supply voltage increases rapidly. 40. The method as recited in claim 39 further comprising: discharging the capacitor when the supply voltage drops to within the predetermined voltage level below the reference voltage. 41. The method as recited in claim 39 further comprising: inverting the power-on signal; and outputting the inverted signal as the power-on signal. 42. The method as recited in claim 41 further comprising: inverting the power-on signal; and outputting the twice inverted signal as the power-on signal. AMENDED CLAIMS [received by the International Bureau on 18 August 1999 (18.08.99); original claims 1, 11, 12, 15, 16, 29, 32, 33 and 38 amended; remaining claims unchanged (όpages)] 1. A power-on reset circuit for generating a power-on reset signal from a supply voltage that rises until reaching a final value, the circuit comprising: a first transistor having a threshold voltage and arranged to generate a reference voltage at a reference node from the supply voltage, wherein the first transistor turns on when the supply voltage reaches the threshold voltage so that the reference voltage remains below the supply voltage by at least the threshold voltage until the supply voltage reaches the final value; a capacitor coupled to the first transistor at the reference node, the capacitor being arranged to be charged when the supply voltage is greater than the threshold voltage of the first transistor; a resistor coupled to the first transistor for slowing down the charging of the capacitor when the supply voltage increases rapidly; and a first inverter coupled to the first transistor at the reference node to receive the reference voltage for generating an inverted output as the power-on reset signal. 2. The power-on reset circuit as recited in claim 1 further comprising: a second transistor coupled to the first transistor and the capacitor at the reference node for discharging the capacitor when the supply voltage drops to within a predetermined voltage level below the reference voltage at the reference node. 3 The power-on reset circuit as recited in claim 1 further comprising: a diode coupled to the first transistor and the capacitor at the reference node for discharging the capacitor when the supply voltage drops to within a predetermined voltage level below the reference voltage at the reference node. 4. The power-on circuit as recited in claim 1 , wherein the first transistor is a diode connected transistor. 5. The power-on reset circuit as recited in claim 2, wherein the second transistor is a diode connected transistor. 6. The power-on reset circuit as recited in claim 5, wherein the first and second transistors are MOSFETs. 7. The power-on reset circuit as recited in claim 6, wherein the first transistor has a gate, a drain, and a source, wherein the gate and the drain of the first transistor are coupled to the reference node and the source of the first transistor is coupled to the resistor. 8. The power-on reset circuit as recited in claim 7, wherein the second transistor has a gate, a drain, and a source, wherein the gate and the source of the second transistor are coupled to the reference node and the drain of the second transistor is coupled to the supply voltage. 9. The power-on reset circuit as recited in claim 8, wherein the resistor is coupled to the supply voltage and the capacitor is coupled to a ground potential. 10. The power-on reset circuit as recited in claim 2, wherein the second transistor is a diode. 11. The power-on reset circuit as recited in claim 2, wherein the second transistor is reverse biased until the supply voltage drops below the reference voltage. 12. The power-on reset circuit as recited in claim 3, wherein the predetermined voltage level is the threshold voltage of the first transistor. 13. The power-on reset circuit as recited in claim 2, wherein the first inverter is a complementary MOS (CMOS) inverter. 14. The power-on reset circuit as recited in claim 13, wherein the first inverter comprises a p-type MOS transistor coupled in series with an n-type MOS transistor. 15. The power-on reset circuit as recited in claim 14 further comprising: a second inverter coupled to the first inverter in series to receive the inverted output and output a twice inverted output as the power-on reset signal. 16. The power-on reset circuit as recited in claim 15 further comprising: a third inverter coupled to the second inverter in series to receive the twice inverted output and output a three times inverted output as the power-on reset signal. 17. The power-on reset circuit as recited in claim 16, wherein the second and the third inverter are complementary MOS (CMOS) inverters. 18. The power-on reset circuit as recited in claim 17, wherein the each of the CMOS inverters of the second and third inverters includes a p-type MOS transistor coupled in series with an n-type MOS transistor. 19. The power-on reset circuit as recited in claim 16, wherein each of the first, second, and third inverters are coupled between a supply voltage potential and a ground potential. 20. The power-on reset circuit as recited in claim 16, wherein the first transistor and the transistors of the first inverter have matching threshold voltages. 21. The power-on reset circuit as recited in claim 16, wherein the first transistor and the transistors of the first inverter are high threshold devices. 22. The power-on reset circuit as recited in claim 16, wherein the first and the second transistors are p-type transistors. 23. The power-on reset circuit as recited in claim 22, wherein the first transistor and the transistors of the first inverter have a threshold voltage of about 1 volt. 24. The power-on reset circuit as recited in claim 16, wherein the channel width to length (W/L) ratio for the first transistor is about 5/10. 25. The power-on reset circuit as recited in claim 24, wherein the W/L ratios for the p-type and n-type MOS transistors are about 10/5 and 5/40, respectively. 26. The power-on reset circuit as recited in claim 1, wherein the circuit components of the of the power-on reset circuit are formed within a single integrated circuit device. 27. The power-on reset circuit as recited in claim 1 , wherein the power-on reset circuit is formed within an integrated circuit device that is suitable for use within a cellular communications system. 28. The power-on reset circuit as recited in claim 1, wherein the power-on reset circuit provides the power-on reset signal to memory units. 29. A power-on reset circuit for generating a power-on reset signal from a supply voltage that rises until reaching a final value, the circuit comprising: a first switching means for generating a reference voltage from the supply voltage, wherein the switching means turns on when the supply voltage reaches a predetermined voltage so that the reference voltage remains below the supply voltage by at least the predetermined voltage; a delay means for slowing down the rise of the reference voltage when the supply voltage increases rapidly; and a first inverting means for inverting the reference voltage to generate an inverted output as the power-on reset signal. 30. The power-on reset circuit as recited in claim 29, wherein the delay means comprises: a charging means for charging when the supply voltage is greater than the threshold voltage of the switching means; and a resistor means for slowing down the charging of the charging means when the supply voltage increases rapidly. 31. The power-on reset circuit as recited in claim 30 further comprising: a second switching means for discharging the charging means when the supply voltage drops to within the predetermined voltage level below the reference voltage. 32. The power-on reset circuit as recited in claim 31 further comprising: a second inverting means for inverting the inverted output of the first inverting means to generate a twice inverted output as the power-on reset signal. 33. The power-on reset circuit as recited in claim 32 further comprising: a third inverting means for inverting the twice inverted output of the second inverting means to generate a three times inverted output as the power-on reset signal. 34. The power-on reset circuit as recited in claim 31 , wherein the first switching means is a transistor. 35. The power-on reset circuit as recited in claim 31 , wherein the charging means is a 36. The power-on reset circuit as recited in claim 31 , wherein the resistor means is a resistor. 37. The power-on reset circuit as recited in claim 31, wherein the first inverting means is a complementary MOS (CMOS) inverter. 38. A method for generating a power-on reset signal from a supply voltage that rises until reaching a final value, the method comprising: generating a reference voltage from the supply voltage, wherein the reference voltage remains below the supply voltage by at least a predetermined voltage; decreasing the rise of the reference voltage when the supply voltage increases rapidly; and inverting the reference voltage to generate an inverted output as the power-on reset signal. 39. The method as recited in claim 38, wherein the decreasing further comprises: charging a capacitor when the supply voltage is greater than the threshold voltage of the switching means; and slowing down the charging of the capacitor when the supply voltage increases rapidly. 40. The method as recited in claim 39 further comprising: discharging the capacitor when the supply voltage drops to within the predetermined voltage level below the reference voltage. 41. The method as recited in claim 39 further comprising: inverting the power-on signal; and outputting the inverted signal as the power-on signal.

Inventors: SALMAN ZAID K, SHIEH SUI P, SALMAN, ZAID, K., SHIEH, SUI, P.
Applicants: MAXIM INTEGRATED PRODUCTS, MAXIM INTEGRATED PRODUCTS, INC.
Application year: 1999
Main classification: H03L7
IPC codes: H03K17