Complementary tuned mixer

Abstract: A mixer circuit for frequency conversion operates with low power supply voltage lower than 1 V. The circuit comprises a first pair (1) of N-channel MOS transistors and a second pair (2) of N-channel MOS transistors each receiving differential local frequency signal (LO(+), LO(-)), and a third pair (3) of P-channel MOS transistors receiving differential radio frequency signal (RF(+), RF(-)). Each of pair (1, 2, 3) of transistors is coupled in series with a parallel resonance circuit (4, 5, 6) which operates as a constant current source. A drain of each transistors (MP1, MP2) of the third pair (3) of transistors is connected to a junction of a first pair (1) and a second pair (2) of transistors and a parallel resonance circuit (4, 5). An output intermediate frequency signal (IF(+), IF(-)) which is difference between the local frequency and the radio frequency is obtained at the junction of drains of the first (1) and the second (2) pair of transistors and load resistors (RL1, RL2). No series connected transistor is inserted between a power source (VDD) and a ground, and each pairs (1, 2, 3) of transistors are inserted between the power source (VDD) and the ground essentially in parallel with one another.

Description: BACKGROUND OF THE INVENTION The present invention relates to a mixer circuit used for frequency conversion of carrier frequency in radio communication system. A mixer circuit is used for frequency conversion in a radio transceiver. A mixer circuit operates to multiply two analog signals for frequency conversion. A Gilbert cell type mixer circuit has been known for an integrated mixer circuit. Fig. 8 shows a prior Gilbert cell type mixer circuit which used MOSFET elements. The symbols MN1 and MN2 show N-channel MOS transistors constituting a first differential pair 1. A gate of those transistors accepts local frequency signals LO (LO+, LO-) in differential form. The symbols MN3 and MN4 are N-channel MOS transistors constituting a second pair 2, having a gate similarly accepting local frequency signals LO (LO+, LO-). The symbols MN5 and MN6 are N-channel MOS transistors constituting a third pair 3A. Each gate of those transistors accepts high frequency signal RF (RF+ and RF-) in differential form, respectively. The symbol MN7 is an N-channel MOS transistor which operates as a current source. The symbols RL1 and RL2 are a load resistor common to the first pair 1 and the second pair 2. In the Gilbert cell type mixer circuit in Fig. 8, the transistors MN5 and MN6 converts high frequency signal RF into differential current form, and each of the transistors MN1 through MN4 switches said current according to the local frequency signal LO, so that the product of the high frequency signal RF and the local frequency signal LO is obtained at one terminal of the loads RL1 and RL2 to provide intermediate frequency signal IF (IF+, IF-) in differential form. By the way, a wireless transceiver operates with a battery, and it is preferable that voltage of the battery is as low as possible in view of small size and light weight of a transceiver. However, the prior Gilbert cell type mixer circuit must have power supply voltage VDD at least 1.5-2.0 V, since the prior Gilbert cell type mixer circuit must have three stacks of transistors (MN1, MN5 and MN7), or (MN3, MN6 and MN7) et al. If we try to decrease power supply voltage, high frequency operation is difficult since drain junction capacitance of a transistor increases, therefore, no application to wireless communication is possible. As mentioned above, as the operation with low power supply voltage less than 1.5 V is impossible, a prior transceiver must have more than two series connected batteries each of which may be a primary battery (1.5 V) or a NiCd type secondary battery (1.2 V). Thus, small sized and/or light weight transceiver has been difficult because of the use of two series connected batteries. The document US-A-5 570 056 discloses an analog circuit for multiplying a first input signal with a second input signal. The document Razavi B. "A 1.5 V 900MHz Downconversion mixer" IEEE International Solid State Circuits Conference, US, IEEE INC. New York, vol.39, page 48-49 XP000685533 ISSN: 0193-6530 discloses another analog circuit for multiplying a first input signal with a second input signal using capacitors. SUMMARY OF THE INVENTION It is an object of the present invention, therefore, to provide a new and improved tuned mixer by overcoming the disadvantages and limitations of a prior tuned mixer. It is an object of the present invention to provide a tuned mixer which operates with power supply voltage lower than 1.0 V. The above and other objects are attained by a complementary tuned mixer circuit as defined in Claim 1. The transistors composing said first series circuit and said second series circuit have preferably opposite conductivity type to that of the transistors composing said differential amplifier. Said differential amplifier has differential transistor pair which receive the second multiply signal, and an impedance circuit which operates as a constant current source, each connected in series with said differential amplifier, between the first power supply terminal and the second power supply terminal. Preferably, said differential amplifier has a pair of capacitors in coupling lines between output lines of the differential amplifier and said series circuits to cut off D.C. current. When said capacitors are provided in said coupling lines, transistors in the first and the second series circuits may have the same conductivity type as that of transistors in the differential amplifier. Preferably, said impedance circuit is a parallel resonance circuit having an inductor and a capacitor, and resonating with said first multiply signal or said second multiply signal. As the first multiply signal frequency is in general close to the second multiply signal frequency, when the resonance circuit resonates with one of the multiply signal frequencies, it may have enough impedance to operate as a constant current source for both the multiply signals. When the value Q of the parallel resonance circuit is too high, a resistor is coupled with the resonance circuit in parallel to decrease the value Q. As an impedance circuit has high impedance for high frequency so that it operates as a constant current source, and low resistance for D.C. current so that high D.C. voltage is applied to transistors, it may not necessarily a parallel resonance circuit, but a mere inductor is enough. BRIEF DESCRIPTION OF THE DRAWINGS The foregoing and other objects, features, and attendant advantages of the invention will be well understood by means of the following description and accompanying drawings, wherein; Fig. 1 is a circuit diagram of a frequency mixer according to the present invention, Fig. 2 is an equivalent circuit of a parallel resonant circuit, and impedance characteristics of the same, Fig. 3 shows simulated waveforms of the apparatus of Fig. 1, Fig. 4 is a circuit diagram of another embodiment of a frequency mixer according to the present invention, Fig. 5 is a circuit diagram of still another embodiment of a frequency mixer according to the present invention, Fig. 6 is a circuit diagram of still another embodiment of a frequency mixer according to the present invention, Fig. 7 shows a differential amplifier used in each embodiments, and Fig. 8 is a circuit diagram of a prior frequency mixer. DESCRIPTION OF THE PREFERRED EMBODIMENTS (First embodiment) Fig. 1 is a circuit diagram of a frequency mixer according to the present invention. The same numerals are assigned in Fig. 1 for the same members as those in Fig. 8. In Fig. 1, a first differential pair 1 comprises a pair of transistors MN1 and MN2 which receive differential local frequency signals LO+ and LO- on each gate. A current supply terminal (source) of those transistors is coupled with a power source (ground) through a parallel resonance circuit 4 having an inductor L and a capacitor C. Similarly, a second differential pair 2 comprises a pair of transistors MN3 and MN4 which receive differential local frequency signals LO+ and LO- on each gate. A current supply terminal (source) of those transistors is coupled with a power source (ground) through a parallel resonance circuit 5 having an inductor L and a capacitor C. A third differential pair 3 comprises a pair of P-channel MOS transistors MP1 and MP2 which receive differential high frequency signals RF+ and RF- on each gate. A current supply terminal (source) of those transistors is coupled with a power source (VDD) through a parallel resonance circuit 6 having an inductor L and a capacitor C. Drains (outputs) of those transistors are connected to each current supply terminal (source) of the transistors of the first pair and the second pair, respectively. A load RL1 is connected to a drain of a non-inverted transistor MN1 (which receives one (+) of the differential local signals) of the first pair 1 and a drain of an inverted transistor MN4 (which receives one (-) of the differential local signals) of the second pair 2. A load RL2 is connected to a drain of an inverted transistor MN2 of the first pair 1 and a drain of a non-inverted transistor MN3 of the second pair 2. Each of the resonance circuits 4 through 6 are equivalent to the circuit of Fig. 2(a), which has a capacitor C, and a series circuit of an inductor L and a resistor Rs. The frequency-impedance characteristics of a parallel resonance circuit is shown in Fig. 2(b), which has the maximum impedance z 0 = L/CRs = RsQ 2 at the resonance frequency f 0 = 1/2π(LC) 1/2 , where Q is a value showing how sharp a resonance circuit is. It should be noted that a parallel resonance circuit has high impedance at resonance frequency f 0 , therefore, a parallel resonance circuit is equivalent to a current source for alternate (AC) signal. A parallel resonance circuit has small resistance for DC signal. That small resistance provides small voltage drop, which does not much affect to the operation of the present invention. As compared with a prior art of Fig. 8, the first differential pair 1, the second differential pair 2 and the third differential pair 3 are inserted essentially in parallel between the power supply terminal VDD and the ground. The signal transfer between the first pair 1 or the second pair 2, and the third pair 3 is carried out through resonance circuits 1 and 2 which operate as a constant current source. It should be noted that the total current in the transistors MN1, MN2 and MP3 is almost constant because of the presence of the parallel resonance circuit 4 which operates as a constant current source. Similarly, the total current in the transistors MN3, MN4 and MP2 is almost constant, and the total current in the transistors MP1 and MP2 is almost constant. For instance, when drain current of the transistor MP1 of the third pair 3 increases by the high frequency signal RF+, the current in the first differential pair 1 decreases, and therefore, the high frequency signal RF is transferred to the first pair 1. It should be appreciated that the total current in the first differential pair 1 (MN1 and MN2), and the transistor MP1 is constant because of the presence of the current source 4, the total current in the second differential pair 2 (MN3 and MN4) and the transistor MP2 is constant because of the presence of the current source 5. And, the total current in the transistors MP1 and MP2 is constant because of the presence of the current source 6. The voltage between a gate and a source of the third differential pair 3 is almost equal to the voltage between the power source voltage VDD and the high frequency signal (RF+, RF-), as the D.C. voltage drop in the parallel resonance circuit 6 is almost zero. That voltage determines bias current of the transistors. Similarly, the voltage between a gate and a source in the first differential pair 1 and the second differential pair 2 is determined by the voltage between the local frequency signal (LO+, LO-) and the ground. Therefore, bias voltage may be set arbitrarily and a circuit itself can operate with low power supply voltage. Fig. 3 shows simulated waveforms of the device of Fig. 1, in which a computer program HSPICE was used. In Fig. 3, the power supply voltage VDD is 1 V, the local frequency signal LO is 1.71 GHz, the radio frequency signal RF is 1.95 GHz, and an output intermediate frequency is 240 MHz. A lowpass filter is used to process the intermediate frequency so that the difference frequency component (240 MHz) is clarified. As described above, according to the present invention, no series connection of transistors between power supply terminals is necessary, and therefore, a frequency mixer can operate with low voltage less than 1 V. (Second embodiment) Fig. 4 shows a circuit diagram of a second embodiment of a frequency mixer according to the present invention. The feature of Fig. 4 as compared with the embodiment of Fig. 1 is that a N-channel MOS transistor in Fig. 1 is changed to a P-channel MOS transistor in Fig. 4, and a P-channel MOS transistor in Fig. 1 is changed to a N-channel MOS transistor in Fig. 4. The first differential pair 1 and the second differential pair 2 in Fig. 1 which receive differential local frequency signal are changed to the first differential pair 1A and the second differential pair 2A which have P-channel MOS transistors MP3 through MP6, and the third differential pair 3 in Fig. 1 is changed to the third differential pair 3A having N-channel MOS transistors MN5 and MN6. The relation of the power source VDD and the ground in view of the transistors is opposite to that of Fig. 1, and the parallel resonance circuits 4 through 6 are connected to a source of a respective differential pair of transistors, and the load resistors RL1 and RL2 are connected to a drain of a respective transistor. (Third embodiment) Fig. 5 is a circuit diagram of the third embodiment of a frequency mixer according to the present invention. The feature of the embodiment of Fig. 5 is that parallel resonance circuits 4A through 6A have a resistor Rp coupled with each of parallel resonance circuits 4-6 of Fig. 1, in parallel. When the value Q is too high in a parallel resonance circuit, the impedance of the parallel resonance circuit is sensitive in view of the frequency change. Therefore, the resistor Rp which satisfies z 0 = L/CRs>Rp is coupled with a parallel resonance circuit in parallel to decrease the value Q, so that the circuit may be designed easily. It should be note that no voltage drop for D.C. current occurs in the parallel resonance circuit of Fig. 5. (Fourth embodiment) Fig. 6 is a circuit diagram of the fourth embodiment of a frequency mixer according to the present invention. The feature of the embodiment of Fig. 6 is that parallel resonance circuits 4A through 6A have a resistor Rp coupled with each of parallel resonance circuits 4-6 of Fig. 4. The circuit of Fig. 6 has the advantage similar to that of Fig. 5. (Another embodiment) In the above embodiments, although an FET (Field Effect Transistor) is used, it is possible to use a bipolar transistor. In that case, a drain, a gate and a source of an FET corresponds to a collector, base and an emitter, respectively, and a P-channel MOS transistor is replaced by an NPN transistor, and a N-channel MOS transistor is replaced by a PNP transistor. It should be noted in the embodiments in Figs. 1, 4, 5 and 6 that the operation by the circuit P enclosed by the dotted line is equivalent with a differential amplifier Q in Fig. 7A, and the circuit P may be replaced by a differential amplifier. A differential amplifier Q receives, in the embodiment of Fig. 1, radio frequency signal RF+ and RF-, and provides differential outputs W1 and W2 to the transistor pairs (MN1, MN2) and (MN3, MN4). A differential amplifier Q is inserted between a power supply terminal VDD and ground. It should be noted that the ground line of the differential amplifier Q is provided by the impedance circuits 4 and 5 through the output lines W1 and W2 in the embodiments of Figs. 1 and 5, and by the ground line QE in the embodiments of Figs. 4 and 6. Further, the output lines W1 and W2 may have capacitors C1 and C2 respectively in series in each output lines as shown in Fig. 7B, so that DC current is prevented by the capacitors. In that case, inductors QL1, QL2 which are a load should be inserted between the power supply terminal VDD and the differential amplifier Q. When the capacitors C1 and C2 are inserted, the conductivity type of transistors composing a differential amplifier Q may the same as the conductivity type of transistors (MN1, MN2, MN3, MN4) which receive local frequency signal. The application of the structure of Fig. 7B to each of the embodiments of Figs. 1, 4, 5 and 6, and the selection of the conductivity type of transistors (P-channel, or N-channel) are obvious to those skilled in the art. (Effect of the invention) As described above in detail, the present invention uses a current source implemented by a parallel resonance circuit, instead of a current source implemented by a transistor in a prior art. Therefore, transistors are not connected in series between two power supply terminals. The circuit can operate with power supply voltage which is requested to operate one stage of a transistor, and therefore, the circuit can operate with low voltage around 1 V. Further, when a resistor is coupled with a parallel resonance circuit in parallel, the impedance of the parallel resonance circuit is less sensitive to frequency, and the circuit design is easy. From the foregoing, it will now be apparent that a new and improved frequency mixer has been found. It should be appreciated of course that the embodiments disclosed are merely illustrative and are not intended to limit the scope of the invention. Reference should be made to the appended claims, therefore, for indicating the scope of the invention.

Claims: A complementary mixer circuit comprising : a first series circuit having a first pair of differentially arranged transistors (1) receiving a first multiply signal in differential form (LO(+), LO(-)), and an impedance circuit (4); a second series circuit of the similar configuration to said first series circuit; and a differential amplifier (3) receiving a second multiply signal (RF(+), RF(-)) and providing an output signal (W 1 , W 2 ) in differential form; to a pair of output terminals; said first series circuit and said second series circuit being inserted between a first power terminal (VDD) and a second power terminal respectively through load resistors (RL1, RL2), said differential amplifier (3) being supplied by said first power terminal (VDD), and said output terminals are respectively coupled with the junction between the transistors (1) of said first series circuit and the impedance circuit (4) of said first series circuit and with the junction between the transistors (2) of said second series circuit and the impedance circuit (5) of said second series circuit, a product, in differential form (IF(+), IF(-)), of said first multiply signal (LO(+), LO(-)) and said second multiply signal (RF(+), RF(-)) being obtained at the junction between said load resistors (RL1, RL2) and said series circuits, characterized in that each of said impedance circuits (4, 5) operates as a constant current source and has high impedance at said first multiply signal (LO(+), LO(-)) and small resistance for DC signal. A complementary mixer circuit according to claim 1, wherein said differential amplifier comprises a series circuit of a pair of transistors (3) in differential form receiving said second multiply signal (RF(+), RF(-)) and an impedance circuit (6) which operates as a constant current source, inserted between said first power terminal (VDD) and said second power terminal. A complementary mixer circuit according to claim 1, wherein each output terminal of said differential amplifier is coupled via a respective capacitor (C1, C2), which prevents D.C. current, to the first and respectively second mentioned junctions in claim 1. A complementary mixer circuit according to claim 1, wherein said impedance circuit is a parallel resonance circuit having an inductor (L) and a capacitor (C), and resonate with said first multiply signal (LO(+), DO(-)) or said second multiply signal (RF(+), RF(-)). A complementary mixer circuit according to claim 1, wherein said impedance circuit is composed of an inductor (L). A complementary mixer circuit according to claim 4, wherein said parallel resonance circuit is provided with a resistor (Rp) coupled in parallel with said resonance circuit. A complementary mixer circuit according to claim 3, wherein transistors (1, 2) composing said first series circuit and said second series circuit are in different conductivity type from that of transistors (3) composing said differential amplifier. A complementary mixer circuit according to claim 2, wherein transistors (1, 2) composing said first series circuit and said second series circuit comprise N-channel MOS transistors, and transistors (3) composing said differential amplifier comprise P-channel MOS transistors. A complementary mixer circuit according to claim 2, wherein transistors (1A, 2A) composing said first series circuit and said second series circuit comprise P-channel MOS transistors, and transistors composing said differential amplifier (3A) comprise N-channel MOS transistors. A complementary mixer circuit according to claim 1, wherein each of said transistor pairs (1, 2) has two FET transistors, sources of each pair are coupled with an impedance circuit (4, 5) which is connected in series with the transistor pair (1, 2), and a drain of said FET transistors (1, 2) is coupled with a respective load circuit (RL1, RL2).

Inventors: HARADA MITSURU, TSUKAHARA TSUNEO, HARADA, MITSURU, TSUKAHARA, TSUNEO, Harada, Mitsuru, c/o Nippon Telegraph &amp; Tel. Corp., Tsukahara, Tsuneo, c/o Nippon Telegraph &amp; Tel Corp
Applicants: NIPPON TELEGRAPH & TELEPHONE, NIPPON TELEGRAPH AND TELEPHONE CORPORATION
Application year: 1999
Main classification: H03D7
IPC codes: H03D7