SYSTEM AND METHOD FOR EDGE TERMINATION OF PARALLEL CONDUCTIVE PLANES IN AN ELECTRICAL INTERCONNECTING APPARATUS

Abstract: A system and method are presented for stabilizing the electrical impedance of a structure (e.g., an electrical interconnecting apparatus) including a pair of parallel planar conductors separated by a dielectric layer. The structure may be, for example, a PCB, a component of a semiconductor device package, or formed upon a surface of an integrated circuit substrate. An electrical resistance connected between the planar conductors about a periphery of the structure serves to stabilize the electrical impedance of the structure, thereby reducing an amount of electromagnetic energy radiated from the structure. The electrical resistance may be multiple discrete electrical resistances dispersed about the periphery of the structure, and the structure need not be rectangular. For example, a portion of the periphery of the structure may define a curve. A general method for stabilizing the electrical impedance of the structure includes selecting a spacing distance. A grid is generated by superimposing two orthogonal sets of parallel lines upon one another, wherein the parallel lines within each set are separated by the spacing distance. The grid is dimensioned such that it completely covers the structure when overlayed upon the structure. The characteristic impedance of the structure may then be estimated using a physical dimension of the grid. The value of the electrical resistance may then be computed using the estimated characteristic impedance of the structure. The grid may also be used to determine the location of the discrete electrical resistances.

Description: TITLE: SYSTEM AND METHOD FOR EDGE TERMINATION OF PARALLEL CONDUCTIVE PLANES IN AN ELECTRICAL INTERCONNECTING APPARATUS BACKGROUND OF THE INVENTION 1 Field of the Invention This invention relates to electronic svstems, and more particularly to electπcal interconnecting apparatus having continuous planar conductors 2 Description of the Related Art Electronic systems typically employ several different types of electπcal interconnecting apparatus having planar layers of electπcally conductive mateπal (l e., planar conductors) separated by dielectric layers A portion of the conductive layers may be patterned to form electrically conductive signal lines or "traces" Conductive traces in different layers (i e , on different levels) are typically connected using contact structures formed m openings m the dielectric lavers ( I e vias) For example, integrated circuits tvpicallv have several layers of conductive traces which interconnect electronic devices formed upon and within a semiconductor substrate Each layer is separated from adjacent layers by dielectπc layers Withm a semiconductor device package, several layers of conductive traces separated by dielectπc layers may be used to electπcally connect bonding pads of an mtegrated circuit to terminals (e.g , pins or leads) of the device package Pnnted circuit boards also typically have several layers of conductive traces separated by dielectric layers The conductive traces are used to electπcally interconnect terminals of electronic devices mounted upon the PCB Signals m digital electronic systems typically carry information by alternating between two voltage levels (I e., a low voltage level and a high voltage level) A digital signal cannot transition instantaneously from the low voltage level to the high voltage level, or vice versa The finite amount of time during which a digital signal transitions from the low voltage level to the high voltage level is called the nse time of the signal Similarly, the finite amount of tune during wmch a digital signal transitions from the high voltage level to the low voltage level is called the fall time of the signal Digital electronic systems are continually being produced which operate at higher signal frequencies (I e , higher speeds) In order for the digital signals within such systems to remain stable for appreciable periods of time between transitions, the nse and fall times of the signals must decrease as signal frequencies increase This decrease in signal transition tunes (l e , nse and fall times) creates several problems within digital electronic systems, including signal degradation due to reflections, power supply "droop", ground "bounce", and mcreased electromagnetic emissions A signal driven upon (i.e , launched) from a source end of a conductive trace suffers degradation when a pomon of the signal reflected from a load end of the trace arnves at the source end after the transition is complete (i.e., after the nse time or fall tune of the signal) A portion of the signal is reflected back from the load end of the trace when the input impedance of the load does not match the charactenstic impedance of the trace When the length of a conductive trace is greater than the signal transition tune (i.e., the nse or fall tune) divided by about 20 tunes the delay per unit length along the trace, the effects of reflections upon signal uitegnty (i.e., transmission line effects) should be considered If necessary, steps should be taken to minimize the degradations of signals conveyed upon the trace due to reflections The act of altering impedances at the source or load ends of the trace in order to reduce signal reflections is referred to as "terminating" the trace For example, the input impedance of the load may be altered to match the characteπstic impedance of the trace m order to prevent signal reflection. As the transition tune (i.e , the rise or fall tune) of the signal decreases, so does the length of trace which must be terminated m order to reduce signal degradation. A digital signal alternating between the high and low voltage levels includes contπbutions from a fundamental smusoidal frequency (i.e., a first harmonic) and integer multiples of the first harmonic. As the nse and fall tunes of a digital signal decrease, the magnitudes of a greater number of the integer multiples of the first harmonic become significant. As a general rule, the frequency content of a digital signal extends to a frequency equal to the reciprocal of π times the transition time (i.e., nse or fall time) of the signal For example, a digital signal with a 1 nanosecond transition tune has a frequency content extending up to about 318 MHz All conductors have a certain amount of inductance. The voltage across the inductance of a conductor is duectly proportional to the rate of change of current through the conductor At the high frequencies present in conductors carrying digital signals havmg short transition tunes, a significant voltage drop occurs across a conductor having even a small mductance A power supply conductor connects one terminal of an electπcal power supply to a power supply terminal of a device, and a ground conductor connects a ground terminal of the power supply to a ground terminal of the device When the device generates a digital signal havmg short transition tunes, high frequency transient load currents flow m the power supply and ground conductors. Power supply droop is the term used to descnbe the decrease in voltage at the power supply terminal of the device due to the flow of transient load current through the inductance of the power supply conductor Similarly, ground bounce is the term used to descnbe the mcrease in voltage at the ground terminal of the device due to the flow of transient load current through the inductance of the ground conductor When the device generates several digital signals havmg short transition times simultaneously, the power supply droop and ground bounce effects are additive. Sufficient power supply droop and ground bounce can cause the device to fail to function coπectly Power supply droop is commonly reduced by arranging power supply conductors to form a crisscross network of intersecting power supply conductors (I e , a power supply gnd) Such a grid network has a lower inductance, hence power supply droop is reduced. A contmuous power supply plane may also be provided which has an even lower mductance than a grid network. Placmg a "bypass" capacitor near the power supply terminal of the device is also used to reduce power supply droop The bypass capacitor supplies a substantial amount of the transient load current, thereby reducing the amount of transient load current flowmg through the power supply conductor. Ground bounce is reduced by using a low mductance ground conductor grid network, or a contmuous ground plane havmg an even lower amount of inductance. Power supply and ground gnds or planes are commonly placed m close proximity to one another in order to further reduce the inductances of the grids or planes. Electromagnetic mterference (EMI) is the term used to descnbe unwanted interference energies either conducted as currents or radiated as electromagnetic fields. High frequency components present withm circuits producmg digital signals havmg short transition times may be coupled mto nearby electronic systems (e.g., radio and television circuits), disrupting proper operation of these systems The United States Federal Communication Commission has established upper limits for the amounts of EMI products for sale in the United States may generate Signal circuits form current loops which radiate magnetic fields m a differential mode Differential mode EMI is usually reduced by reducmg the areas proscnbed by the circuits and the magnitudes of the signal currents Impedances of power and ground conductors create voltage drops along the conductors, causing the conductors to radiate electnc fields m a common mode Common mode EMI is typically reduced by reducmg the impedances of the power and ground conductors Reducmg the impedances of the power and ground conductors thus reduces EMI as well as power supply droop and ground bounce Within the wide frequency range present withm electronic systems with digital signals having short transition times, the electncal impedance between any two parallel conductive planes (e.g , adjacent power and ground planes) may vary widely The parallel conductive planes may exhibit multiple electπcal resonances, resulting in alternating high and low impedance values Parallel conductive planes tend to radiate a significant amount of differential mode EMI at their boundaries (1 e , from their edges) The magnitude of differential mode EMI radiated from the edges of the parallel conductive planes vanes with frequency and is directly proportional to the electrical impedance between the planes Fig 1 is a perspective view of a pair of 10 m x 10 m square conductive planes separated by a fiberglass-epoxy composite dielectπc layer Each conductive plane is made of copper and is 0 0014 m thick The fiberglass-epoxy composite layer separatmg the planes has a dielectric constant of 4 0 and is 0 004 in thick Fig 2 is a graph of the magnitude of the simulated electrical impedance between the pair of rectangular conductive planes of Fig 1 (log 10 scale) versus the frequency of a voltage between the planes (log, 0 scale) The graph was created by modelmg each square mch of the pair of conductive planes as a matrix of transmission line segments The impedance value was computed by simulating the application of a 1 ampere constant current between the centers of the rectangular planes, varying the frequency of the current, and determining the magnitude of the steady state voltage between the centers of the rectangular planes As shown m Fig 2, the magnitude of the electrical impedance between the parallel conductive planes of Fig 1 varies widely at frequencies above about 20 MHz The parallel conductive planes exhibit multiple electncal resonances at frequencies between 100 MHz and 1 GHz, resultmg m alternating high and low impedance values The parallel conductive planes of Fig 1 would radiate substantial amounts of EMI at frequencies where the electncal impedance between the planes anywhere near their peripheries is high It would thus be desirable to have a system for stabilizing the electπcal impedance between parallel conductive planes Such a system would reduce power supply droop, ground bounce, and the amount of electromagnetic energy radiated from the edges of the planes Such impedance stabilization may also reduce the need for bypass capacitors SUMMARY OF THE INVENTION The problems outlmed above are m large part solved by a system and method for stabilizing the electncal impedance of an electncal interconnecting apparatus mcludmg a parr of parallel planar conductors separated by a dielectnc layer The electncal interconnecting apparatus may be, for example, a PCB, a semiconductor device package substrate, or an mtegrated circuit substrate The present method mcludes determining a characteristic impedance of the structure An electπcal resistance is then electπcally coupled between the planar conductors, wherem the electncal resistance has a value dependent upon the charactenstic impedance of the structure The electncal resistance may be a set of discrete electncal resistances (e g , resistors) dispersed between regions of the planar conductors near the penphenes, or a contmuous "stπpe" of electπcal resistance between the regions near penphenes When the electπcal resistance is a set of discrete electπcal resistances, the method may include selecting a value for each of the set of electncal resistances and electncally coupling each of the electncal resistances between the regions near the peripheries such that a lateral spacmg distance is mamtamed between the electπcal resistances When the structure is square, the charactenstic impedance of the entue structure may be determined and the spacmg distance between the electπcal resistances may be computed The charactenstic impedance of the structure may then be multiplied by the ratio of the length of the sides of the structure to the spacmg distance, resultmg m the value for each of the set of electncal resistances The charactenstic impedance "Zo" of a parr of square planar conductors in parallel and separated by a dielectnc layer may be approximated usmg where Zoo is the impedance of free space (120π ohms), h is the distance between the planar conductors, vv is the length of each of the sides of the composite structure, and ε r is the relative dielectπc constant of the dielectric layer The above equation for Zo is a low frequency approximation as it is derived usmg the low frequency (l e "static") capacitance between the planar conductors In the above equation, the charactenstic impedance of the planar conductors is thus directly proportional to the distance between the planar conductors and inversely proportional to the lengths of the sides of the composite structure and the square root of the relative dielectnc constant of the dielectnc layer The spacmg distance between the electncal resistances may be determined by the wavelength of the highest frequency in a frequency range of mterest For example, the interconnecting apparatus may include a signal layer havmg electncally conductive traces for conveymg signals The signals have an associated frequency range (l e , the frequency range of interest) As descnbed above, the frequency content of a digital signal may extend to a frequency equal to the reciprocal of π tunes the transition tune (l e , rise or fall tune) of the signal The spacmg distance between the electncal resistances is preferably made equal to a fraction of the wavelength of the highest frequency in the frequency range of mterest For example, the spacing distance between the electncal resistances may be less than or equal to one tenth of the wavelength of the highest frequency m the frequency range of mterest When the structure is rectangular but not square, the spacmg distance between the electncal resistances may first be determined The charactenstic impedance of a square portion of the structure havmg sides with lengths equal to the spacmg distance may then be computed The charactenstic impedance of the square portion of the structure is the value for each of the set of electncal resistances When the electncal resistance is contmuous between the regions of the planar conductors near the penphenes, and the structure is rectangular, the charactenstic impedance of the entire structure may be determined A resistive "stripe" along a given side of the structure between the regions near the penphenes should provide a resistance per unit length equal to the charactenstic impedance of the structure divided by the length of the side Accordmgly, the resistive stripe provides a total resistance along each side of the structure equal to the charactenstic impedance of the structure An electncal interconnecting apparatus m accordance with the present invention mcludes an electncal resistance electncally coupled between regions of the planar conductors near penphenes The electncal resistance has a value dependent upon a characteristic impedance of the planar conductors, and serves to stabilize the electncal impedance of the pau of parallel planar conductors The electπcal resistance may be a set of discrete electncal resistances (e g , resistors) dispersed between the outer regions Alternately, the electrical resistance may be a contmuous "stnpe" of electπcal resistance between the outer regions In one embodiment, the electπcal interconnecting apparatus mcludes multiple impedance networks dispersed about a region near a penphery of an upper surface of the electncal interconnecting apparatus The impedance networks are separated by a predetermined spacing distance A pair of vias is used to electπcally connect each impedance network between regions of the planar conductors near penphenes Each impedance network mcludes an electncal resistance (e g , a resistor) having a selected value dependent upon the characteristic impedance of the planar conductors Each impedance network may also include an electncal capacitance (e g , a capacitor) in senes with the electπcal resistance When the planar conductors are maintained at different direct current (d c ) potentials, the capacitance prevents a flow of d c cunent between the planar conductors through the impedance networks The spacmg distance between the impedance networks may be determined by the wavelength of the highest frequency m a frequency range of mterest as described above The electrical interconnecting apparatus may be, for example, substantially rectangular In this case, a subset of the impedance networks may reside withm a region near a penphery of an upper surface of one side of the electncal interconnecting apparatus The sum of the electπcal resistances of the subset of impedance networks may be made substantially equal to the characteristic impedance of the planar conductors Members of the subset may be connected together to form a chain of impedance networks Each impedance network may include an electrical capacitance C in senes with electπcal resistance R In this case, the value of C is preferably determined usmg the following equation C > 2π -R -f n where f res is the lowest resonant frequency of the structure includmg the planar conductors separated by the dielectric layer Thus the value of C is preferably inversely related to the value of R Resonant frequency f res may be determined experimentally or by computer simulation In Fig 2, fres ls me frequency where the impedance is minimum, approximately 100 MHz In an alternate embodunent of the electncal interconnecting apparatus, a senes combmation of resistance and capacitance formed between a parr of planar conductors is continuous about the regions near the penphenes of the planar conductors An electπcally resistive layer is positioned between the dielectric layer and one of the planar conductors such that the electncally resistive layer is m contact with the planar conductor The dielectnc layer mcludes an inner portion and an outer portion, wherem the outer portion is located between the regions near the penphenes of the planar conductors The dielectnc constant of the outer portion of the dielectπc layer is greater than the dielectnc constant of the inner portion of the dielectnc layer The portion of the electπcally resistive layer located between the outer portion of the dielectπc layer and the adjacent planar conductor provides an electncal resistance duectly proportional to the charactenstic impedance of the planar conductors The outer portion of the dielectnc layer provides an electncal capacitance m senes with the resistance The capacitance per unit length Q provided by the outer portion of the dielectnc layer is preferably dependent upon the resistance per unit length Rj provided by the resistive layer accordmg to the following equation c ; > 2π - R, - f, where f res is the lowest resonant frequency of the structure mcludmg the planar conductors separated by the dielectnc layer Thus the value of is preferably mversely related to the value of Rj The structure includmg a pau of parallel planar conductors separated by a dielectnc layer (e g , electrical interconnecting apparatus) need not be rectangular For example, a portion of a penphery of the structure may define a curve A general method for stabilizing the electncal impedance of the structure mcludes selecting spacmg distance 5 described above Spacmg distance s may, for example, be selected accordmg to S ≤ ' 10Λ wherein c is the speed of light, fm is a maximum frequency of a frequency range of interest, and ε r is the relative dielectnc constant of the dielectric layer A grid including two orthogonal sets of parallel lmes superimposed upon one another may then be generated The parallel lmes withm each set may be separated by spacmg distance s, and the grid may be dimensioned such that it completely covers the structure when overlayed upon the structure The charactenstic impedance of the structure may then be estimated as described above usmg at least one physical dimension of the gnd For example, the characteristic impedance Zo of the structure may be estimated usmg the equation where w is a dimension of the gnd The value of an electncal resistance coupled between the planar conductors may then be computed as descnbed above based upon the estimated charactenstic impedance of the structure The gnd may be generated by selectmg orthogonal first and second dimensions of the structure, preferably such that the product of the first and second dimensions of the structure is minimized Correspondmg first and second dimensions of the gnd may then be sized such that they are greater than or equal to the respective first and second dimensions of the structure As the parallel lmes of the gnd are separated by spacmg distance s, the first and second dimensions of the gnd are integer multiples of spacing distance s Results of computer simulations show that discrete electncal resistances coupled between portions of the penphenes of structures mcludmg pans of parallel planar conductors separated by dielectric layers are effective m stabilizing the electncal impedance of the structures Accordmgly, the electncal resistance may include multiple discrete electπcal resistances dispersed along at least a portion of a penphery of the structure When the gnd is square, the value of w m the impedance equation above may be the length of each side of the grid, and a nominal value of each of the discrete electncal resistances may be calculated as Zo (wls) Results of computer simulations show that values of the discrete electncal resistances may vary withm a range extending from about 0 1 tunes the nominal value to approximately 100 tunes the nominal value and still be effective in stabilizing the electπcal impedance of the structure Accordmgly, the value of each of the discrete electncal resistances may vary within a range extending from about 0 1 tunes the nominal value to approximately 100 times the nominal value When the grid is not square, the value of w in the impedance equation above mav be made equal to spacmg distance s, and the resultant estimated charactenstic impedance Zo may be used as the nominal value of each of the discrete electrical resistances Again the value of each of the discrete electπcal resistances may vary withm a range extending from about 0 1 times the nominal value to approximately 100 times the nommal value The couplmg may include overlaying the grid upon the structure, selecting a location for the electrical resistance at a pomt withm the grid where two orthogonal lines of the gnd intersect near the periphery of structure, and moving the location to an adjacent portion of the periphery Where multiple discrete electrical resistances are to be dispersed along the periphery, the moving may be accomplished such that distances between adjacent discrete electπcal resistances are made substantially equal BRIEF DESCRIPTION OF THE DRAWINGS Other objects and advantages of the invention will become apparent upon reading the following detailed descnption and upon reference to the accompanying drawings in which Fig 1 is a perspective view of a pair of 10 in x 10 m square conductive planes separated by a fiberglass-epoxy composite dielectric layer, Fig 2 is a graph of the magnitude of the simulated electncal impedance IZ| (log 10 scale) between the pair of rectangular conductive planes of Fig 1 versus the frequency of a voltage (log 10 scale) between the planes Fig 3 is a top plan view of one embodiment of an electncal interconnecting apparatus m accordance with the present invention, wherem the interconnecting apparatus mcludes multiple impedance networks dispersed withm a region near a penphery (l e , an outer edge) of an upper surface, Fig 4 is a cross sectional view of a portion the interconnecting apparatus of Fig 3, illustrating the connection of one of the impedance networks between parallel power and ground planes within the interconnecting apparatus, Fig 5 is a circuit diagram showmg an equivalent electncal network between the power and ground planes provided by the impedance network depicted m Fig 4, Fig 6 is a perspective view of a rectangular structure mcludmg a parr of planar electrical conductors separated by a dielectric layer, Fig 7 is a block diagram illustrating how the structure of Fig 6 is modeled as a two-dimensional network (l e , gnd) of ideal (l e , lossless) transmission line segments, Fig 8 is a perspective view of a structure mcludmg a pan of 10 m lO in square conductive planes separated by a fiberglass-epoxy composite dielectnc layer, wherem multiple impedance networks are dispersed withm a region near the penphery of the upper surface of the structure and connected between the planes, Fig 9 is a graph of the loganthm of the magnitude of the simulated electncal impedance |Zj (log 10 scale) between the pau of conductive planes of the structure of Fig 8 versus the frequency of a voltage (log 10 scale) between the planes, Fig 10 is a perspective view of a portion of the interconnect apparatus of Fig 3 wherem impedance networks are connected together to form a cham or "bar" of impedance networks, Fig 11 is a cross sectional view of a portion of the interconnecting apparatus of Fig 3 illustrating a second embodunent of the impedance networks, wherem each impedance network mcludes a capacitance, and wherem a resistance in series with the capacitance is the sum of the equivalent senes resistance (ESR) of the capacitance and the resistances of the vias connecting the impedance network between the power and ground planes, Fig 12 is a ctfcuit diagram showing an equivalent electrical network between the power and ground planes provided by the impedance network depicted m Fig 11 , Fig 13 is a cross sectional view of a portion the interconnecting apparatus of Fig 3 illustrating an alternate method of forming an electπcal resistance and capacitance m series between two conductive planes separated by a dielectπc layer, wherem a resistive layer and an outer portion of the dielectnc layer form a contmuous (I e , distnbuted) impedance network between regions of the conductive planes near peripheries, Fig 14 is a circuit diagram showmg an equivalent electrical network between the two conductive planes provided by the resistive layer and the outer portion of the dielectnc layer as depicted in Fig 13, Fig 15 is a cross sectional view of a portion the interconnecting apparatus of Fig 3 illustrating another alternate embodiment of the impedance networks, wherem each impedance network mcludes only an electrical resistance connected between two ground planes, Fig 16 is a cucuit diagram showmg an equivalent electncal network between the two ground planes provided by the impedance network depicted in Fig 15, Fig 17 is a perspective view of a structure mcludmg a parr of 8 in x 8 m. square conductive plates separated by a dielectnc layer, wherein multiple impedance networks are dispersed withm a region near the penphery of the structure and connected between the plates, Fig 18 is a graph of Mm |Z| values versus the ratio of the electncal resistance of each of the impedance networks in Fig 17 to a nominal resistance value (l e , the loganthm of a normalized resistance value of each impedance network, log 10 scale), wherem Fig 18 shows that the impedance networks havmg normalized resistance values rangmg from about 0 1 to approximately 100 are effective m stabilizmg the electrical impedance of the structure m Fig 17, Fig 19 is a top plan view of a rectangular gnd overlymg and covering an exemplary non-rectangular structure, wherem the structure includes two circular conductive plates arranged m parallel and separated by a dielectnc layer, and wherem the grid is used to estimate the charactenstic unpedance of the structure, Fig 20 is a perspective view of a structure mcludmg two cucular conductive plates arranged m parallel and separated by a dielectnc layer, Fig 21 is a graph of the magnitude of the measured electncal impedance between the pan of circular conductive plates of the structure of Fig 20 (logι 0 scale) versus the measurement frequency (log 10 scale) both with and without impedance networks connected between the plates about a penphery of the structure, wherem Fig 21 shows that the electπcal impedance of the structure of Fig 20 is stabilized significantly by the additions of the impedance networks, Fig 22 is a top plan view of a structure mcludmg a pair of 10 m x 10 m square conductive plates separated by a dielectnc layer, wherem multiple impedance networks are connected between the plates at 1 0 in spacmgs about a penphery of the structure, Fig 23 is a top plan view of the structure of Fig 22 wherein the impedance networks have been removed from one side of the square structure, Fig 24 is a top plan view of the structure of Fig 22 wherem the impedance networks have been removed from two sides of the square structure, Fig 25 is a top plan view of the structure of Fig 22 wherem the impedance networks have been removed from three sides of the square structure, Fig 26 is a graph of Mm |Z| values versus the number of sides of the structure of Fig 22 havmg unpedance networks connected between the plates, wherem Fig 26 shows that (l) placing impedance networks along only 1 side of the structure provides a minimal amount of impedance stabilization, and (n) placmg impedance networks along at least 2 sides of the structure provides a significant amount of unpedance stabilization, Fig 27 is a top plan view of a structure including a pau of 10 in x 10 in square conductive plates separated by a dielectnc layer wherem multiple impedance networks are connected between the plates at 1 0 in spacmgs about a penphery of the structure, and wherein the square structure has four corner regions (l e , "corners") wherem each "corner" includes an unpedance network located at a corner of the structure and two impedance networks on either side, Fig 28 is a top plan view of the structure of Fig 27 wherem the impedance networks have been removed from one "corner" of the square structure, Fig 29 is a top plan view of the structure of Fig 27 wherem the impedance networks have been removed from two "corners" of the structure, Fig 30 is a top plan view of the structure of Fig 27 wherem the impedance networks have been removed from three "corners" of the structure, Fig 31 is a top plan view of the structure of Fig 27 wherem the impedance networks have been removed from all four "corners" of the structure, Fig 32 is a graph of Mm |Z| values versus the number of "corners" of the structure of Fig 27 havmg unpedance networks connected between the plates, wherem Fig 32 shows that (l) removmg impedance networks from 1 to 3 "corners" of the structure does not have a negative impact on the unpedance stabilization provided by the impedance networks, and (ii) removing impedance networks from all 4 "corners" of the structure has only a slight negative impact on the impedance stabilization; Fig. 33 is a top plan view of a structure mcludmg a pau of 8 m. x 8 in. square conductive plates separated by a dielectnc layer, wherein multiple impedance networks are connected between the plates at 1.0 m spacmgs about a periphery of the structure; and Fig. 34 is a graph of Mm |Z| values versus the number of consecutive unpedance networks connected between the plates of the structure of Fig. 33, wherem Fig 34 shows that: (l) placing only 1 or 2 impedance networks along the penphery of the structure provides little impedance stabilization improvement over the untermmated state of the structure, (u) the impedance stabilization provided by impedance networks is positive and nearly lmear when between 3 and 8 unpedance networks are placed along the penphery of the structure, (in) additional impedance networks in excess of 8 further improve impedance stabilization until 14 impedance networks are placed along the penphery of the structure, and (iv) placing unpedance networks along the periphery of the structure in excess of 14 provides little or no improvement m impedance stabilization While the invention is susceptible to various modifications and alternative forms, specific embodiments thereof are shown by way of example m the drawings and will herem be descnbed m detail It should be understood, however, that the drawings and detailed description thereto are not mtended to limit the mvention to the particular form disclosed, but on the contrary, the intention is to cover all modifications, equivalents and alternatives falling withm the spmt and scope of the present invention as defined by the appended claims DETAILED DESCRIPTION OF THE INVENTION Fig 3 is a top plan view of one embodiment of an electπcal interconnecting apparatus 10 in accordance with the present mvention. Interconnecting apparatus 10 mcludes multiple layers of planar electrical conductors separated by dielectnc layers At least one of the planar electπcal conductors may be patterned to form signal lmes (i.e , interconnects or traces) Interconnecting apparatus 10 may be, for example, a PCB. a component of a semiconductor device package, or formed upon a surface of an integrated cucuit substrate Fig 4 is a cross sectional view of a portion interconnecting apparatus 10 In the embodiment of Fig. 4, interconnecting apparatus 10 mcludes four planar electrical conductors: a first signal plane 14, a ground plane 16, a power plane 18, and a second signal plane 20 During use of interconnecting apparatus 10, power plane 18 is connected to a power terminal of an electrical power supply, and ground plane 16 is connected to a ground terminal of the power supply Electronic devices connected between power plane 18 and ground plane 16 receive electncal power. Power plane 18 and ground plane 16 are contmuous across at least a portion of interconnecting apparatus 10 First signal plane 14 and second signal plane 20 are patterned to form electncally conductive traces as described above. Fust signal plane 14 and ground plane 16 are separated by a first dielectric layer 22 Ground plane 16 and power plane 18 are separated by a second dielectric layer 24. Power plane 18 and second signal plane 20 are separated by a thud dielectnc layer 26 In the embodiment of Fig. 3, interconnecting apparatus 10 mcludes multiple impedance networks 12 dispersed about a region near a penphery (i.e., an outer edge) of an upper surface of interconnecting apparatus 10. As will be descnbed m detail below, impedance networks 12 are separated by a selected spacing distance "s" Fig 4 is a cross sectional view of a portion interconnecting apparatus 10 through an unpedance network 12 In the embodiment of Figs 3 and 4, unpedance networks 12 are electncally connected between regions near penphenes of power plane 18 and ground plane 16 by a pan of vertical electncal conductors (l e , vias) Impedance networks 12 are used to stabilize the electπcal impedance between power plane 18 and ground plane 16 Fig 4 depicts one embodiment of unpedance network 12, wherem impedance network 12 includes an electncal resistance 28 connected m series with an electncal capacitance 30 Electrical resistance 28 may be, for example, a surface mount resistor Similarly, electπcal capacitance 30 may be, for example, a surface mount capacitor A first via 32 connects power plane 18 to electncal resistance 28, and a second via 34 connects ground plane 16 to electncal capacitance 30 Vias 32 and 34 may be, for example, plated-through holes formed using vanous well known techniques During use of interconnect apparatus 10, the power supply provides a direct current (d c ) electrical potential between power plane 18 and ground plane 16 Impedance networks 12 which ring the upper surface of interconnect apparatus 10 provide alternating cunent (a c ) termination of the structure mcludmg power plane 18 ground plane 16, and second dielectπc layer 24 separating power plane 18 and ground plane 16 Electncal switching occurring withm electronic devices connected between power plane 18 and ground plane 16 creates a c waveforms withm power plane 18 and ground plane 16 These a c waveforms "see" an unpedance value substantially equal to all of the electncal resistances 28 of unpedance networks 12 m parallel At the same time, electncal capacitances 30 prevent d c current from flowmg between power plane 18 and ground plane 16 through impedance networks 12 Fig 5 is a cucuit diagram showmg an equivalent electncal network 36 between power plane 18 and ground plane 16 provided by the impedance network 12 depicted m Fig 4 Electncal network 36 includes an electncal resistance 38, an electncal mductance 40, and an electπcal capacitance 42 The value of resistance 38 mcludes the value of resistance 28, the electrical resistances of vias 32 and 34, and the equivalent senes resistance (ESR) of capacitance 42 Inductance 40 mcludes the inductances of resistance 28 capacitance 30, via 32, and via 34 Capacitance 42 includes the value of capacitance 30 As descnbed above, impedance networks 12 are separated by a selected spacmg distance s Signals are conveyed withm interconnect apparatus 10 (e g , withm a signal layer) and have an associated range of frequencies (l e , a frequency range of mterest) Spacmg 5 oetween impedance networks 12 is preferably made equal to a fraction of the wavelength of the highest frequency in the frequency range of interest Spacing s may be, for example, less than or equal to one tenth of the wavelength of the highest frequency in the frequency range of mterest For example, signals conveyed withm interconnect apparatus 10 may have a transition time (I e , rise or fall tune) of 1 nanosecond In this case, the highest frequency m the frequency range of mterest, "fin", may be the reciprocal of π tunes the transition tune, or about 318 MHz The wavelength oϊfm is the velocity divided by the frequency If the dielectnc layer separatmg power plane 18 and ground plane 16 has a relative dielectnc constant of 4 7, the velocity is the speed of light "c" (about 3 0 x 10 8 m sec) divided by the square root of the relative dielectnc constant "ε r ", or approximately 1 38 x 10 s m/sec The wavelength of fin is the velocity (about 1 38 x 10 8 m/sec) divided by the frequency (approximately 318 MHz), or about 43 cm In this case, spacmg 5 may be less than or equal to about 4 3 cm (approximately 1 7 m ) In terms of a mathematical equation, 5 < - 10 . Fig 6 is a perspective view of a rectangular structure 44 mcludmg a pair of planar electπcal conductors separated by a dielectnc layer The planar conductors have dimensions "wl" and "w2", and the dielectric layer has a thickness or height "A" As shown m Fig 7, structure 44 is modeled as a two-dimensional network (l e , gnd) of ideal (I e , lossless) transmission line segments 46 Two sets of parallel lmes with equivalent spacmgs s are superimposed upon one another such that members of one set are perpendicular to members of the other set Transmission Ime segments 46 are mserted between the mtersections of these lmes, and transmission Ime segments 46 are connected at the mtersections It is noted that while lossless transmission Ime segments 46 are descnbed herem, "lossy" transmission line segments may be developed which account for resistive and skm losses m conductors and dielectnc losses is dielectric layers The characteristics of ideal transmission lmes are determined by two equations of two variables the mductance "Z," of the transmission Ime per unit length and the capacitance "C" of the transmission line per unit length A first equation defines a characteristic impedance "Z 0 " of the transmission line Z C The second equation defines the propagation delay "tprf" of the transmission line per unit length = -J LC Parameters for each transmission Ime segment 46 are determined on a "unit cell" basis The static (1 e , low frequency) capacitance of each square s-by-s unit cell "Cw" is given by < C„ = ε„ε r The propagation delay along an edge of the unit cell "φd u " is determined by s, the speed of light c, and the relative dielectric constant ε of the dielectric layer separating the planar conductors ' pd_u dε. The values of tpd u an d Cu are used to derive an approximate low frequency charactenstic impedance "Zo u" of each s-by-s square unit cell: where Zoo is the impedance of free space, 120π ohms. Each square s-by-s unit cell is represented by four transmission Ime segments 46, one along each side of the unit cell. Each transmission Ime segment 46 has a characteristic unpedance oϊ -Zoju. Transmission Ime segments 46 of adjacent unit cells are m parallel, resultmg in equivalent charactenstic impedances of 2 Zo_u Thus transmission Ime segments 46 along borders between adjacent unit cells have characteristic impedances of 2 Zo u, and transmission Ime segments 46 along outer edges of structure 44 have charactenstic impedances of 4-Zo_w All transmission Ime segments 46 have w u propagation delays When interconnect apparatus 10 is square, the values for electrical resistances 28 positioned along the edges of interconnect apparatus 10 may be selected by (l) computing the charactenstic impedance of the structure mcludmg the planar conductors, (n) determining spacing distance s, and (in) multiplying the characteristic unpedance of the structure by the ratio of the length of one side of the structure to spacmg distance s. For example, assume interconnect apparatus 10 mcludes a pau of 10 m x 10 m. square planar conductors separated by a dielectric layer havmg a thickness or height h of 0.004 in, and a relative dielectnc constant ε r of 4 7 Digital signals are conveyed havmg transition times of 1 nanosecond. As descnbed above, the highest frequency m the frequency range of interest fin may be the reciprocal of π times the transition tune, or 318 MHz Spacing s is thus preferably less than or equal to 1.7 m. In this case, select spacing s of 1 0 m. The characteristic impedance "Zo" of the structure mcludmg the planar conductors and the dielectnc layer is calculated usmg The ratio of the length of one side of the structure to spacing distance _s is 10, thus each electrical resistance 28 should have a value of about 0.070 Ω 10 = 0 70 Ω When interconnect apparatus 10 is rectangular but not square, the values for electncal resistances 28 positioned along the edges of structure 44 may be selected by: (l) determining spacmg distance s, and (n) computmg the charactenstic impedance of each s-by-s unit cell. For example, assume structure 44 has dimensions of 8 in. x 10 in., a dielectnc layer havmg a thickness or height h of 0.031 m. and a relative dielectnc constant ε r of 4.7, and digital signals with transition tunes of 1 nanosecond are conveyed As described above, the highest frequency in the frequency range of mterest fin may be the reciprocal of π times the transition time, or 318 MHz. Spacmg s is thus preferably less than or equal to 1 7 m. As before, select spacmg s of 1.0 m. Each square s-by-s unit cell has a charactenstic unpedance "Zo u" given by Each electπcal resistance 28 should have a value of about 5.39 Ω. The value for each electrical capacitance 30, denoted C, is preferably determined usmg the following equation: c > - 2π -R -f re where R is the value of electπcal resistance 28 and f res is the lowest resonant frequency of the structure mcludmg the planar conductors separated by the dielectric layer Resonant frequency J res may be determined expenmentally or by computer simulation. In Fig. 2, fres iS the frequency where the unpedance is mmunum. approximately 100 MHz. Fig. 8 is a perspective view of a structure 48 mcludmg a pau of 10 in x 10 in. square conductive planes separated by a fiberglass-epoxy composite dielectnc layer. Each conductive plane is made of copper and is 0.0014 m. thick The fiberglass-epoxy composite layer separatmg the planes has a dielectnc constant of 4 0 and has a thickness or height A of 0004 in Multiple impedance networks 12 are dispersed about a region near the penphery of the upper surface of structure 48 as shown in Fig 8 and separated by a spaced distance s of 1 0 m Each impedance network 12 included an electπcal resistance 28 m series with a capacitance 30 as described above Each capacitance 30 was selected to be 1 0 microfarad The charactenstic impedance "Zo" of the structure is calculated using The ratio of the length of one side of the structure to spacmg distance s is 10, thus each electncal resistance 28 should have a value of about 0 075 Ω • 10 = 0.75 Ω Each unpedance network 12 was represented by an equivalent electncal network 36 mcludmg an electncal resistance 38 havmg a value of 0.75 ohms, an electncal mductance 40 having a value of 0.2 nanohenπes, and an electncal capacitance 42 havmg a value of 1.0 microfarads. The value of resistance 38 is the sum of the resistance 28 and the electrical resistances of vias 32 and 34, mductance 40 is the electncal inductances of vias 32 and 34, and capacitance 42 is the selected value of capacitance 30. Fig. 9 is a graph of the magnitude of the simulated electncal unpedance |Z| between the pair of conductive planes of structure 48 of Fig. 8 (log, 0 scale) versus the frequency of a voltage between the planes (log,o scale) The unpedance value Z was computed by simulating the application of a 1 ampere constant current between the centers of the planes, varying the frequency of the current, and determining the magnitude of the steady state voltage between the centers of the rectangular planes As shown m Fig 9, the electπcal impedance between the parallel conductive planes of Fig 8 is nearly constant from 1 MHz to about 50 Mhz and mcreases almost monotonically at frequencies above 50 MHz The multiple electπcal resonances of the conductive planes of Fig 1 and evidenced at frequencies between 100 MHz and 1 GHz m Fig 2 have been damped resultmg in the stabilizing of the impedance between the pau of conductive planes As a result, the "edge terminated" parallel conductive planes of Fig 8 would radiate a substantially smaller amount of EMI than the "untermmated" conductive planes of Fig 1 Fig 10 is a perspective view of a portion of interconnect apparatus 10 wherem impedance networks 12 are connected together to form a cham or "bar" of impedance networks 12 Each impedance network 12 is a spaced distance s from adjacent unpedance networks 12 The bar of unpedance networks 12 may extend along the entire length of an edge of the upper surface of interconnect apparatus 10 A bar of impedance networks 12 may extend across each of the four edges of the upper surface of a rectangular interconnect apparatus 10 Fig 1 1 is a cross sectional view of a portion mterconnectmg apparatus 10 illustrating a second embodunent of impedance networks 12 In the embodunent of Fig 11, each unpedance network 12 mcludes a capacitance 50 A first via 52 connects power plane 18 to a first terminal of capacitance 50, and a second via 54 connects ground plane 16 to a second terminal of capacitance 50 Vias 52 and 54 may be, for example, plated- through holes formed usmg various well known techniques An electrical resistance substantially equal to the value of resistance 28 is incorporated in series with capacitance 50 For example, capacitance 50 may be selected such that it has an equivalent series resistance (ESR) substantially equal to the value of resistance 28 Alternately, vias 52 and 54 may be formed such that the sum of their resistances is substantially equal to the value of resistance 28 The resistances of vias 52 and 54 may be mcreased for example, by reducing their cross sectional areas or by forming them from a material having a higher resistivitv Fig 12 is a circuit diagram showmg an equivalent electrical network 56 between power plane 18 and ground plane 16 provided by the unpedance network 12 depicted m Fig 11 Electncal network 56 mcludes an electrical resistance 58, an electncal inductance 60, and an electncal capacitance 62 The value of resistance 58 mcludes the ESR of capacitance 62 and the electrical resistances of vias 52 and 54 Inductance 60 includes the inductances of capacitor 50, via 52, and via 54 Capacitance 62 includes the value of capacitance 50 Fig 13 is a cross sectional view of a portion of mterconnectmg apparatus 10 illustrating an alternate method of forming an electncal resistance and capacitance in senes between two conductive planes separated by a dielectric layer The conductive planes may be, for example, connected to different d c potentials as are a power plane and a ground plane In the embodiment of Fig 13, the multiple unpedance networks 12 of Figs 3-4 are replaced by a continuous (l e , distnbuted) unpedance network formed between regions of the conductive planes near penphenes In the embodunent of Fig 13, mterconnectmg apparatus 10 mcludes four electncally conductive planes a first signal plane 64, a ground plane 66, a power plane 68, and a second signal plane 70 A planar electncally resistive layer 72 is between ground plane 66 and power plane 68 and m contact with ground plane 66 Fust signal plane 64 and ground plane 66 are separated by a first dielectnc layer 74 Resistive layer 72 and power plane 68 are separated by a second dielectnc layer 76 Power plane 68 and second signal plane 70 are separated by a third dielectnc layer 78 A portion 80 around a region near the penphery of planar dielectric layer 76 has a higher relative dielectnc constant than the relative dielectnc constant of the remamder of dielectnc layer 76 Portion 80 of dielectnc layer 76 provides an electπcal capacitance between power plane 68 and resistive layer 72 Resistive layer 72 provides a resistance between dielectnc layer 76 and ground plane 66 The combmation of portion 80 of dielectnc layer 76 and resistive layer 72 between power plane 68 and ground plane 66 forms an electrical capacitance and an electπcal resistance in senes between power plane 68 and ground plane 66 The distnbuted impedance afforded by the series combmation of the electncal capacitance and an electπcal resistance is used to stabilize the electπcal impedance between power plane 68 and ground plane 66 Resistive layer 72 may include, for example, electrically conductive particulates (e g , silver, copper, or nickel) suspended m a non-conductive bmder (e g , epoxy resm, urethane, or polyester) The resistivity of the particulate-btnder combmation may be varied by changing the number of conductive particulates per unit volume of the particulate-bmder combination Increasmg the number of suspended conductive particulates per unit volume of the particulate-binder combination decreases the resistivity of the particulate-binder combmation Decreasmg the number of suspended conductive particulates per unit volume of the particulate-binder combmation increases the resistivity of the particulate-binder combmation Resistive layer 72 is formed such that the electncal resistance between portion 80 of dielectnc layer 76 and ground plane 66 along each edge of interconnect apparatus 10 is substantially equal to the charactenstic impedance between power plane 68 and ground plane 66 For example, assume a structure including a pair of 10 m x 10 m square planar conductors separated by a dielectπc layer having a relative dielectnc constant of 4 7 and a thickness or height h of 0 004 in The characteristic unpedance "Zo" of the structure is calculated as Accordmgly, the electncal resistance between portion 80 of dielectric layer 76 and ground plane 66 along each edge of the structure is substantially equal to 0 070 Ω It is noted that planar resistive layer 72 may alternately be positioned between second dielectπc layer 76 and power plane 68, and m contact with power plane 68 In yet another embodunent, a first and second resistive layers may be positioned between ground plane 66 and power plane 68 The first resistive layer may be located between second dielectnc layer 76 and ground plane 66, and in contact with ground plane 66 The second resistive may be located between second dielectπc layer 76 and power plane 68, and m contact with power plane 68 The dielectnc constant of portion 80 of dielectnc layer 76 may be increased by suspendmg particulates of a substance having a relatively high dielectnc constant (e g , titanium dioxide or banum titanate) withm a dielectnc bmder matenal (e g , epoxy resin, polytetrafluoroethylene, or polystyrene) The dielectnc constant of the particulate-binder combmation may be vaned by changmg the number of particulates per unit volume of the particulate-bmder combmation. Increasmg the number of suspended particulates per unit volume of the particulate-bmder combmation mcreases the dielectnc constant of the particulate-bmder combmation. Decreasmg the number of suspended particulates per unit volume of the particulate-bmder combmation decreases the dielectnc constant of the particulate-bmder combination Portion 80 of dielectnc layer 76 is preferably formed such that the capacitance per unit length provided by portion 80 between power plane 68 and ground plane 66 along each outer edge of rectangular interconnect apparatus 10 is given by c ; >. 2* • *, ■ /„ where is the lowest resonant frequency of the structure mcludmg power plane 68, ground plane 66, and dielectnc layer 76 Fig 14 is a cucuit diagram showmg an equivalent electπcal network 82 between power plane 68 and ground plane 66 provided by portion 80 of dielectric layer 76 and resistive layer 72 as depicted m Fig. 13 Electrical network 82 mcludes an electncal resistance 84 and an electncal capacitance 86 The value of resistance 84 mcludes the resistance of resistive layer 72 offered between portion 80 of dielectnc layer 76 and ground plane 66. Capacitance 86 includes the value of the capacitance offered by portion 80 of dielectric layer 76 The value and effects of any inductance m senes with resistance 84 and capacitance 86 are believed negligible m the embodiment of Fig. 13 Fig. 15 is a cross sectional view of a portion mterconnectmg apparatus 10 illustrating another alternate embodiment of impedance networks 12. In the embodiment of Fig 15, unpedance networks 12 are connected between a pau of planar conductors separated by at least one dielectnc layer and connected to the same d.c potential. The planar conductors may be, for example, two different ground planes. Each unpedance network 12 mcludes an electrical resistance 88 The value of resistance 88 is determmed m the same manner as descnbed above for resistance 28. In the embodunent of Fig 15, interconnecting apparatus 10 includes four electrically conductive planes: a first signal plane 90, a first ground plane 92, a second ground plane 94, and a second signal plane 96 A first via 98 connects second ground plane 94 to a first terminal of resistance 88. and a second via 100 connects first ground plane 92 to a second terminal of resistance 88 Vias 98 and 100 may be, for example, plated-through holes formed usmg vanous well known techniques Fig. 16 is a cucuit diagram showmg an equivalent electncal network 102 between first ground plane 92 and second ground plane 94 provided by the impedance network 12 depicted in Fig. 15. Electπcal network 102 mcludes an electncal resistance 104 and an electncal mductance 106. The value of resistance 104 is substantially the sum of resistance 88 and the electncal resistances of vias 98 and 100. Inductance 106 is substantially the electncal inductances of vias 98 and 100 Figs. 17 and 18 will now be used to illustrate the simulated effects of varying the resistance values of unpedance networks dispersed about the penphery of a rectangular structure, mcludmg two parallel conductive plates separated by a dielectnc layer, on the electncal unpedance of the structure. Fig. 17 is a perspective view of a structure 108 similar to structure 48 of Fig. 8. Structure 108 mcludes a pau of 8 m. x 8 m. square conductive plates separated by a dielectnc layer (e g , fiberglass-epoxy composite) Each conductive plate is made of copper and is 0 0014 m thick The dielectric layer separating the planes has a relative dielectnc constant of 4 7 and a thickness or height h of 0 002 m Multiple unpedance networks 110 are connected between the plates about a region near a periphery of structure 108 as shown in Fig 1 Adjacent impedance networks 110 are separated by a spaced distance s of 1 0 m For simplicity, each impedance network 110 mcluded only an electncal resistance The characteristic impedance "Zo" of the structure is calculated as descnbed above usmg The ratio of the length of the sides of the structure to spacmg distance is 8, thus a nominal value of the electncal resistance of each impedance network 110 was selected to be about 0 0435 Ω 8 = 0 348 Ω Structure 108 was modeled as a two-dimensional network (I e , grid) of transmission line segments as described above The gnd mcluded two orthogonal sets of parallel lmes with spacmgs 5 supenmposed upon one another The two orthogonal sets of parallel lmes mtersected at nodes, and transmission line segments were connected between the nodes along the parallel lmes Each square s-by-s unit cell mcluded four transmission line segments, one along each side of the unit cell Transrmssion Ime segments m parallel were replaced by a single transrmssion Ime segment having half the charactenstic impedance of the parallel segments As a result, transmission Ime segments along outer edges of structure 108 had charactenstic impedances twice those of transmission Ime segments between adjacent unit cells The resultmg grid had 81 nodes connected by transmission Ime segments The electrical impedances of the all 81 grid nodes of the structure 108 model were simulated over a frequency range from 10 MHz to 1 000 MHz (I e , 1 GHz) Between each set of simulations the value of the electncal resistance of each impedance network 110 was varied A normalized value the electrical resistance of each unpedance network 110 was calculated by dividing the actual resistance value by the nominal value The normalized value of the electrical resistance of each impedance network 110 was vaned over the range between 0 01 and 1,000 In order to judge the effect of varying the unpedance values of unpedance networks 110 upon the electπcal impedance of strucmre 108, a "Min" value of the magnitude of the unpedance of structure 108 (l e , Mm |Z|) was computed Fust, at each simulation frequency, the lowest value of the magnitudes of the impedances of the 81 grid nodes of the structure 108 model was determined Second, the lowest impedance magnitude value over the entue range of simulation frequencies (I e , Mm |Z|) was detemuned The "Mm" designation refers to the two-step minimum finding process The Mm |Z| values were detemuned for each different resistance value of unpedance networks 110 Fig 18 is a graph of the Mm |Z| values versus the normalized resistance value of each impedance network 110 (log 10 scale) Higher Mm |Z| values evidence the lack of senes resonance "dips" m electrical unpedance, thus higher Mm |Z| values are believed charactenstic of a more stable impedance of structure 108 Fig 18 shows that impedance networks 110 are effective m stabilizmg the impedance of structure 108 over a wide range of normalized resistance values Specifically, impedance networks 110 havmg normalized resistance values rangmg from about 0 1 to approximately 100 are effective m stabilizmg the unpedance of structure 108 While unpedance networks 110 havmg normalized resistance values of about 1 0 have the greatest stabilizmg effect, normalized resistance values rangmg from about 0 2 to approximately 10 are highly effective m stabilizmg the impedance of structure 108 A graph of "Max |Z|" values as a function of the normalized resistance of each unpedance network 110 (not shown) was also prepared The highest value of the magnitudes of the impedances of the 81 gnd nodes was determined at each simulation frequency, then the highest unpedance magnitude value over the entue range of simulation frequencies (l e , Max |Z|) was determined Lower Max |Z| values evidence the lack of parallel resonance "peaks" m electncal impedance, thus lower Max |Z| values are believed charactenstic of a more stable unpedance of strucmre 108 The Max |Z| graph also supported the above conclusions regardmg the ability of unpedance networks 110 to stabilize the impedance of structure 108 over a wide range of normalized resistance values A general method for determining electncal resistance values of, and locations for impedance networks to be dispersed along a penphery of a structure includes selectmg a spacmg distance s and forming a gnd usmg spacmg distance s Parallel lines of the grid are separated by spacmg distance s, and the gnd is sized such that it completely covers the strucmre when overlayed upon the structure Outer edges of the gnd may extend beyond the penphery of the structure (e g , in the case of a non-rectangular structure) The characteristic unpedance of the structure may then be estimated as descnbed above usmg at least one physical dimension of the grid The electncal resistance values of the unpedance networks may be computed as described above based upon the estimated charactenstic unpedance of the structure Fig 19 will now be used to illustrate the general method Fig 19 is a top plan view of a grid 112 overlayed upon and covering an exemplary non-rectangular structure 114 Structure 114 mcludes two circular conductive plates arranged m parallel and separated by a dielectnc layer The two circular conductive plates may, for example, have diameters of 10 m , and the dielectnc layer may have a thickness or height /; of 0 002 in and a relative dielectnc constant of 4 7 Signals conveyed withm structure 144 may have transition times of 1 nanosecond, leadmg to a highest frequency fin m a frequency range of mterest of about 318 MHz As descnbed above, spacmg distance s may be selected accordmg to s ≤ - ιo/ ra where c is the speed of light, fin is a maximum frequency of a frequency range of mterest, and ε r is the relative dielectnc constant of the dielectric layer A highest frequency fin of 318 MHz and a relative dielectnc constant of 4 7 leads to maximum spacmgs s of about 4 3 cm (approximately 1 7 in ) Spacmgs s may be selected to be, for example, 1 0 mch The gnd may then be generated usmg spacmg distance s The gnd includes two orthogonal sets of parallel lmes superimposed upon one another. The parallel lmes withm each set are separated by spacmg distance s, and the gnd is dimensioned such that it completely covers the structure when overlayed upon the structure The gnd may be generated by selecting orthogonal first and second dimensions of the structure. The first and second dimensions are preferably selected such that the product of the first and second dimensions is minimized Corresponding first and second dimensions of the grid may then be sized such that they are greater than or equal to the respective first and second dimensions of the structure As the parallel lmes of the grid are separated by spacmg distance s, the first and second dimensions of the grid are integer multiples of spacmg distance s In Fig. 19, dimensions wl and vv2 of gnd 112 may be selected to be 10 in., the same as the diameters of the conductive cucular plates of strucmre 114 As shown in Fig. 19, gnd 112 may be overlayed upon structure 114 such that it completely covers structure 114 It is noted that other values of spacmgs s may require that dimensions wl and w2 of gnd 112 exceed the conespondmg dimensions of structure 114 m order to allow gnd 112 to completely cover structure 114 when overlayed upon strucmre 114. In general, it is desirable that the dimensions of grid 112 be the smallest possible which allow grid 112 to completely cover structure 114 when overlayed upon structure 114 In this case, the product of the orthogonal dimensions wl and w2 of grid 112 will be minimized The characteristic impedance Zo of structure 114 may be estimated as described above usmg the equation- As grid 112 is square, w is made equal to dimension wl (or w2) of gnd 112 (i.e., 10 m.). The resulting estimated charactenstic impedance Zo of structure 114 is The ratio of vv to spacmg distance s is 10, thus a nominal value of the electπcal resistance of each impedance network may be computed as Zo ■ (wls) = 0.0348 Ω 10 = 0 348 Ω It is noted that when the grid is not square, the value of w in the equation for characteristic impedance Zo above may be made equal to spacmg distance s, and the resultant estimated charactenstic unpedance Zo may be used as the nominal value of the electncal resistance of each unpedance network. The locations of the unpedance networks to be dispersed about the penphery of structure 114 may be detemuned as shown m Fig. 19 Nodes nearest the periphery of structure 114, designated by "•" symbols m Fig 19, are first selected as potential locations of the unpedance networks. Potential locations not falling along the penphery of structure 114 are moved to an adjacent portion of the penphery of structure 114 The resultmg locations of the impedance networks are designated by the "x" symbols m Fig. 19. The potential locations are preferably moved to adjacent portions of the penphery such that the distances between a given location and its nearest neighbors are substantially equal. In Fig. 19, this is accomplished by movmg the potential locations along lmes of gnd 122 to adjacent portions of the penphery of structure 114 For example, a potential location at node 116 is moved along Ime 118 of grid 122 to location 120 along the penphery of structure 114 The above example results m 28 impedance networks havmg resistance values of 0 348 Ω and dispersed about the penphery of structure 144 as shown m Fig 19 The impedance networks are separated by an average distance of about 1 22 in Agam, exemplary structure 114 in Fig 19 is non-rectangular It is noted that the general method descnbed above may be used for determining electncal resistance values of, and locations for, unpedance networks to be dispersed along a penphery of any stmcture mcludmg a pan of parallel planar conductors separated by a dielectnc layer, whether the planar conductors be rectangular or non-rectangular Figs 20 and 21 will now be used to illustrate how tolerant the edge termination method is to resistance values and placements of unpedance networks about the penphery of a strucmre Fig 20 is a perspective view of strucmre 122 mcludmg two circular conductive plates arranged m parallel and separated by a dielectric layer The two cucular conductive plates have diameters of 10 m , and the dielectnc layer has a thickness or height h of 0 002 m and a relative dielectric constant of 4 7 Rather than the 28 impedance networks havmg resistance values of 0 348 Ω, 31 impedance networks havmg resistance values of 1 0 Ω were placed at about 1 0 in intervals around the penphery of structure 122 This change represents about an 18 percent decrease in average spacing and a 187 percent increase m electrical resistance (I e , a normalized resistance value of 2 87) Electrical impedance measurements were made (l) between the plates at a location along the penphery of stmcture 122 at a location correspondmg to an impedance network, and (u) both with and without unpedance networks 124 Fig 21 is a graph of the magnitude of the measured unpedance |Z| between the pan of circular conductive plates of structure 122 (log, 0 scale) versus the measurement frequency (log 10 scale) both with and without impedance networks 124 As shown m Fig 21, the electπcal impedance of the "untermmated" stmcture 122 without impedance networks 124 vanes greatly at frequencies above about 50 MHz The parallel conductive plates exhibit multiple electrical resonances at frequencies between about 300 MHz and 1 GHz, resultmg in alternating high and low impedance values On the other hand, the electrical impedance of the "edge termmated structure 122 with unpedance networks 124 rises monotonically from 10 MHz to about 500 Mhz, and the multiple electncal resonances present without impedance networks 124 between about 300 MHz and 1 GHz are damped considerably The impedance of structure 122 is thus stabilized significantly by the additions of unpedance networks 124 It is believed the edge termmated structure 122 with unpedance networks 124 would radiate a substantially smaller amount of EMI than the untermmated structure 122 without impedance networks 124 Figs 22-26 will now be used to show how the simulated effects of eliminating unpedance networks along one or more sides of a rectangular structure impacts the beneficial impedance-stabilizing effects of edge termination Fig 22 is a top plan view of a stmcture 126 mcludmg a pan of 10 m x 10 m square conductive plates separated by a dielectric layer Each conductive plate or sheet is made of copper and 0 0014 m thick The dielectnc layer separating the planes has a relative dielectnc constant of 4 7 and a thickness or height h of 0 002 in Multiple unpedance networks 128 are dispersed about a region near the periphery of structure 126 as shown in Fig 22 The selected spacmgs s were 1 0 m The electncal resistances of each unpedance network 128 was computed as descnbed above, resultmg m a resistance value of 0 348 Ω Figs 23-25 show structure 126 with impedance networks 128 removed from one, two, and three sides respectively. In Figs. 23-25, impedance networks 128 removed from stmcture 126 are marked with an "x" symbol. Structure 126 was modeled as a two-dimensional network (i.e., gnd) of transmission line segments as descnbed above. The gnd mcluded two orthogonal sets of parallel lmes with spacmgs s superimposed upon one another. The orthogonal sets of parallel lmes intersected at nodes, and transmission line segments connected nodes along the parallel lmes. The resultmg gnd had 121 nodes connected by transmission line segments The impedances of all the 121 gnd nodes of the structure 126 model were simulated over a frequency range from 10 MHz to 1,000 MHz (i.e., 1 GHz) A first set of simulations measured the impedance of structure 126 with all impedance networks 128 mtact (i.e., along all four sides of structure 126 as shown m Fig. 22) Between each successive set of simulations, impedance networks 128 were removed from a different side of structure 126 as shown m Figs 23-25 A "Mm" value of the magnitudes of the impedances of the nodes of stmcture 126 (l e., Mm |Z|) was computed as descnbed above and used to judge the effects of eliminating unpedance networks along one or more sides of strucmre 126 on the beneficial impedance-stabilizing effects of edge termination First, at each simulation frequency, the lowest value of the magnitudes of the impedances of the 121 grid nodes of the structure 126 model was determined Second, the lowest impedance magnitude value over the entire range of simulation frequencies (l e., Mm |Z|) was determined Fig. 26 is a graph of the Mm |Z| values versus the number of sides of stmcture 126 having unpedance networks 128 (i.e., the number of "edge termmated" sides of stmcture 126) As descnbed above, higher Mm |Z| values evidence the lack of senes resonance "dips" in electncal unpedance, thus higher Mm |ZI values are believed charactenstic of a more stable electncal unpedance of strucmre 126. Fig 26 shows that placmg impedance networks 128 along 1 side of structure 126 provides a minimal amount of impedance stabilization, while placmg impedance networks 128 along at least 2 sides of structure 126 provides a significant amount of impedance stabilization. Figs. 27-32 will now be used to show the simulated effects of eliminating unpedance networks along one or more comers of rectangular stmcture 126 on the beneficial impedance-stabilizing effects of edge termination Fig. 27 is a top plan view of stmcture 126 having multiple unpedance networks 128 dispersed about a region near the periphery of the upper surface as described above Rectangular stmcture 126 has four comer regions or "comers", wherem each "comer" mcludes an impedance network 128 located at a comer of stmcture 126 and two unpedance networks 128 on either side. Figs 28-31 show stmcture 126 with impedance networks 128 removed from one, two, three, and four "comers" respectively In Figs 28-31, impedance networks 128 removed from strucmre 126 are marked with an "x" symbol Strucmre 126 was modeled as a two-dimensional grid with 1.0 m. spacmgs s and 121 nodes connected by transmission Ime segments as descnbed above The impedances of the all 121 grid nodes of the structure 126 model were simulated over a frequency range from 10 MHz to 1,000 MHz (l e., 1 GHz) A first set of simulations measured the unpedance of stmcture 126 with all impedance networks 128 intact (I e., m all four comers of structure 126 as shown in Fig. 27) Between each successive set of simulations, unpedance networks 128 were removed from a different "comer" of stmcture 126 as shown m Figs 28-31. A "Mm" value of the magnitudes of the impedances of the nodes of stmcture 126 (i.e., Mm |Z|) was computed as descnbed above and used to judge the effects of eliminating unpedance networks from "comers" of stmcture 126 on the beneficial impedance-stabilizing effects of edge termmation Fig 32 is a graph of the Mm |Z| values versus the number of "comers" of structure 126 having unpedance networks 128 (I e , the number of edge termmated "comers" of stmcture 126) Fig 32 shows that removmg impedance networks 128 from 1 to 3 "comers" of stmcture 126 does not have a negative impact on the unpedance stabilization provided by impedance networks 128, while removing impedance networks 128 from all 4 "comers" of stmcture 126 has only a slight negative impact on the impedance stabilization Figs 33-34 will now be used to show the simulated effects of eliminating unpedance networks along the penphery of a rectangular structure on the beneficial impedance-stabilizing effects of edge termination Fig 33 is a top plan view of a structure 130 including a pau of 8 in x 8 in square conductive plates separated by a dielectnc layer Each conductive plate or sheet is made of copper and 0 0014 m thick The dielectnc layer separatmg the planes has a relative dielectnc constant of 4 7 and a thickness or height h of 0 002 m The selected spacmgs s were 1 0 m A total of 32 impedance networks 132 are dispersed about a region near the penphery of the upper surface of structure 130 and numbered consecutively from one comer of structure 130 as mdicated m Fig 33 A nominal electrical resistance of each impedance network 132 was computed as descnbed above resultmg m a value of 0 348 Ω Structure 130 was modeled as a two-dimensional grid with 1 0 in spacmgs s and 81 nodes connected by transmission Ime segments as described above The impedances of the all 81 gnd nodes of the strucmre 130 model were "measured" via simulation over a frequency range from 10 MHz to 1,000 MHz (l e , 1 GHz) A first set of simulations measured the impedances of the nodes of structure 130 with all 32 impedance networks 132 mtact and havmg resistance values equal to the calculated nominal value A second set of simulations measured the impedances of the nodes of structure 130 with 31 unpedance networks 132 mtact and the impedance network 132 numbered "1" in Fig 33 removed Prior to the second set of simulations, the resistance values of the 31 remammg unpedance networks 132 were "adjusted" to the calculated nominal value times the fraction (31/32) A thud set of simulations measured the impedances of the nodes of structure 130 with 30 impedance networks 132 intact and unpedance networks 132 numbered "2" and "1" in Fig 33 removed The resistance values of the remammg impedance networks 132 were "adjusted" to the calculated nominal value times the fraction (30/32) pnor to the thud set of simulations Impedance networks 132 were removed from structure 130, the resistance values of the remaining impedance networks 132 were adjusted, and node impedances were measured via sunulation until all 32 impedance networks 132 were removed from structure 130 A "Mm" value of the magnitudes of the impedances of the nodes of strucmre 130 (l e , Mm |Z|) was computed as descnbed above and used to judge the effects of eliminating unpedance networks m succession along the periphery of strucmre 130 on the beneficial impedance-stabilizing effects of edge termmation First, at each simulation frequency, the lowest value of the magnitudes of the impedances of the 81 gnd nodes of the structure 130 model was determined Second, the lowest unpedance magnitude value over the entue range of sunulation frequencies (I e , Min |Z|) was determined Fig 34 is a graph of the Mm |Z| values versus the number of unpedance networks 132 intact (l e , the number of "edge terminations") Agam, as unpedance networks 132 were removed from stmcture 130, the resistance values of the remammg unpedance networks 132 were adjusted as descnbed above Fig 34 shows that placmg only 1 or 2 unpedance networks 132 along the penphery of stmcture 130 provides little unpedance stabilization improvement over the untermmated state of structure 130 The unpedance stabilization provided by unpedance networks 132 is positive and nearly lmear when between 3 and 8 impedance networks 132 are placed along the penphery of stmcture 130 Additional unpedance networks m excess of 8 further improve unpedance stabilization until 14 unpedance networks 132 are placed along the penphery of stmcture 130 Fig 34 implies that placmg impedance networks 132 along the penphery of stmcture 130 m excess of 14 provides little or no improvement m unpedance stabilization Numerous vanations and modifications will become apparent to those skilled in the art once the above disclosure is fully appreciated It is mtended that the following claims be interpreted to embrace all such vanations and modifications

Claims: WHAT IS CLAIMED IS: 1. A method for stabilizmg the electrical impedance of a substantially rectangular structure mcludmg a pau of parallel planar conductors separated by a dielectπc layer, wherem the unpedance stabilization reduces an amount of electromagnetic energy radiated from the structure, the method compnsmg: determining a charactenstic impedance Zo of the structure; and electncally couplmg a plurality of electncal resistances between the planar conductors along a side of the structure, wherem each of the electrical resistances has a value greater than and dependent upon the charactenstic unpedance of the stmcture. 2. The method as recited m claim 1, wherein the electncal resistances are discrete electncal resistances dispersed along an outer edge of the side of the structure 3. The method as recited m claim 1 , wherem the strucmre is square and has four sides of equal length w , and wherein the charactenstic unpedance Zo of the structure is given by and wherem Zoo is the impedance of free space, h is the distance between the planar conductors, and ε r is the relative dielectric constant of the dielectnc layer 4 The method as recited m claim 1, wherem n electncal resistances are coupled between the planar conductors along the side of the stmcture, and where n ≥ 2, and wherein each of the n electπcal resistances has a value substantially equal to n Zo 5. A method for stabilizmg the electncal impedance of a substantially rectangular structure mcludmg a pau of parallel planar conductors separated by a dielectric layer, wherem the impedance stabilization reduces an amount of electromagnetic energy radiated from the strucmre, the method compnsmg: selecting a value for each of n electπcal resistances, wherem n ≥ 2, and wherem the value of each of the n electncal resistances is greater than a charactenstic impedance of the strucmre; and electncally couplmg the n electncal resistances between the planar conductors along an outer edge of a side of the stmcture, wherem the couplmg is performed such that a lateral spacing distance is maintained between the electncal resistances. 6. The method as recited m claim 5, wherem the structure is square and has four sides of equal length, and wherem the selecting comprises determining the charactenstic impedance of the stmcture; computing the spacmg distance between the electncal resistances, and multiplying the charactenstic impedance of the structure by the ratio of the length of the sides of the structure to the spacmg distance. 7. The method as recited in claim 5, wherem the selecting comprises determining the spacing distance between the electncal resistances, and computmg a characteristic impedance of a square portion of the stmcture havmg four sides, wherem the length of each side is equal to the spacmg distance 8. An electncal mterconnectmg apparatus, compnsmg: a pau of parallel planar electncal conductors separated by a dielectric layer, wherem each planar electncal conductor is substantially rectangular and has four sides, and wherein each planar electncal conductor has an outer region substantially near a periphery; and a plurality of impedance net orks electπcally connected between the outer regions of the planar conductors, wherem each impedance network includes an electncal resistor, and wherem n of the unpedance networks reside along one side of the electrical mterconnectmg apparatus, and wherem n ≥ 2, and wherein the electrical resistor of each of the n impedance networks has a value greater than a charactenstic unpedance of the planar conductors. 9. The electπcal mterconnectmg apparatus as recited m claim 8, wherein each unpedance network is located upon an upper surface of the electπcal mterconnectmg apparatus, and wherem a pan of vias is used to connect each unpedance network between the outer regions of the planar conductors. 10. The electncal mterconnectmg apparatus as recited m claim 8, wherein the plurality of unpedance networks are separated by a predetermined spacmg distance. 11. The electncal mterconnectmg apparatus as recited m claim 10, wherem signals are conveyed withm the electncal mterconnectmg apparatus, and wherem the signals have an associated frequency range, and wherem the spacmg distance between the impedance networks is equal to a fraction of the wavelength of the highest frequency m the frequency range 12 The electπcal mterconnectmg apparams as recited m claun 11, wherem the electncal mterconnectmg apparatus further compnses a signal layer, and wherein the signal layer mcludes traces for conveymg the signals 13 The electncal mterconnectmg apparatus as recited in claun 11, wherem the spacmg distance between the unpedance networks is less than or equal to one tenth of the wavelength of the highest frequency in the frequency range 14 The electncal mterconnectmg apparams as recited in claim 8, wherem the n impedance networks are connected together to form a cham of unpedance networks 15 The electrical interconnecting apparatus as recited in claim 8, wherem each unpedance network further compnses an electrical capacitor in senes with the electπcal resistor 16 The electπcal interconnecting apparams as recited in claun 8, wherem the electπcal mterconnectmg apparams is a printed cucuit board 17 The electπcal mterconnectmg apparatus as recited in claun 8, wherein the dielectric layer is a fϊberglass- epoxy composite 18 The electπcal mterconnectmg apparatus as recited m claun 8, wherem each of the planar conductors is contmuous over at least a portion of the electπcal mterconnectmg apparatus 19 The electπcal mterconnectmg apparatus as recited m claun 8, wherein a non-zero direct current electncal potential is maintained between the pau of planar conductors during use 20 The electrical mterconnectmg apparams as recited m claim 8, a duect current electπcal potential of 0 volts is mamtamed between the pair of planar conductors during use 21 An electπcal mterconnectmg apparams, compnsmg a pau of parallel planar electπcal conductors separated by a dielectnc layer, wherem each planar electπcal conductor is substantially rectangular and has four sides, and wherein each planar electπcal conductor has an outer region substantially near a penphery, and a plurality of unpedance networks electncally connected between the outer regions of the planar conductors, wherem each unpedance network mcludes an electncal resistance m senes with an electπcal capacitance, and wherem n of the unpedance networks reside along one side of the electncal mterconnectmg apparams, and wherem n ≥ 2, and wherem the electncal resistance of each of the n impedance networks has a value greater than a charactenstic unpedance of the planar conductors 22 An electπcal mterconnectmg apparams, compnsmg a pan of parallel planar electncal conductors separated by a dielectnc layer, wherem each planar electπcal conductor is substantially rectangular and has four sides, and wherein each planar electrical conductor has an outer region substantially near a penphery, and a continuous electncal resistance electrically coupled between the outer regions of the planar conductors, wherein a portion of the contmuous electncal resistance exists between the planar conductors along an outer edge of one side of the structure, and wherem the portion of the continuous electncal resistance offers an electπcal resistance substantially equal to a characteristic unpedance of the planar conductors 23 The electrical mterconnectmg apparatus as recited m claim 22, wherem the electtical resistance compnses a planar electrically resistive layer 24 The electrical mterconnectmg apparams as recited m claim 23, wherem the electrically resistive layer is positioned between the dielectric layer and one of the planar conductors, and wherein the electtically resistive layer is m contact with the one of the planar conductors 25 The electncal interconnecting apparatus as recited m claim 24, wherem the dielectric layer includes an umer portion and an outer portion, and wherem the outer portion is located between regions of the planar conductors near penphenes, and wherein the dielectnc constant of the outer portion of the dielectnc layer is greater than the dielectπc constant of the inner portion of the dielectric layer 26 The electπcal interconnecting apparatus as recited in claun 25, wherem the outer portion of the dielectnc layer provides an electπcal capacitance near a penphery of the dielectnc layer, and wherem the electncal capacitance has a value inversely related to a value of the electncal resistance 27 A method for stabilizmg the electrical unpedance of a substantially rectangular structure mcludmg a pair of parallel planar conductors separated by a dielectric layer, wherem the unpedance stabilization reduces an amount of electromagnetic energy radiated from the stmcture, the method compnsmg determining a characteristic impedance Zo of the stmcture, and forming a contmuous electπcal resistance between the planar conductors along an outer edge of a side of the structure, wherem the contmuous electπcal resistance offers an electπcal resistance substantially equal to Zo 28 The method as recited in claun 27, further compnsmg forrning a continuous electncal capacitance between the planar conductors along the outer edge of the side of the stmcture, wherem the continuous electncal capacitance is m senes with the contmuous electncal resistance, and wherem the contmuous electncal capacitance offers an electπcal capacitance dependent upon a resonant frequency the stmcmre 29 A method for stabilizmg the electncal impedance of a stmcture mcludmg a pau of parallel planar conductors separated by a dielectric layer and thereby reducmg an amount of electromagnetic energy radiated from the structure, the method compnsmg selecting a spacmg distance dependent upon a relative dielectπc constant of the dielectric layer, generatmg a gnd compnsmg two orthogonal sets of parallel lmes, wherem the parallel lmes of each set are separated by the spacmg distance, and wherem the gnd has physical dimensions greater than or equal to corresponding dimensions of the structure such that the gnd completely covers the stmcmre when overlayed upon the stmcmre, estimating a characteristic impedance of the stmcmre dependent upon at least one physical dimension of the gnd, and electrically couplmg an electncal resistance between the planar conductors, wherem the electrical resistance has a value dependent upon the charactenstic impedance of the stmcmre 30 The method as recited m claim 29, wherem the generatmg comprises selectmg orthogonal first and second dimensions of the stmcmre 31 The method as recited m claim 30, wherem the gnd has orthogonal first and second dimensions, wherem the first dimension of the gnd is greater than or equal to the first dimension of the stmcmre, and wherem the second dimension of the gnd is greater than or equal to the second dimension of the strucmre 32 The method as recited m claun 30, wherem the selectmg is accomplished such that the product of the first and second dimensions of the stmcture are minimized 33 The method as recited m claim 31 , wherem the first and second dimensions of the gnd are integer multiples of the spacmg distance 34 The method as recited m claim 29, wherem the spacmg distance is further dependent upon a maximum frequency withm a frequency range of mterest 35 The method as recited m claim 29, wherein the selectmg is accomplished such that the spacing distance s is given by C s ≤ W ε r wherem c is the speed of light, fin is a maximum frequency within a frequency range of interest, and ε r is the relative dielectnc constant of the dielectπc layer 36 The method as recited m claim 29, wherem the estimating of the charactenstic unpedance Zo of the structure is earned out usmg wherem Zoo is the impedance of free space, h is the thickness of dielectric layer, vv is a dimension of the grid, and ε r is the relative dielectnc constant of the dielectnc layer 37 The method as recited m claim 36, wherem the electπcal resistance compnses a plurality of discrete electπcal resistances dispersed along at least a pomon of a penphery of the stmcmre 38 The method as recited m claun 37, wherem when the gnd is square, v is set equal to the length of each side of the grid and a nommal value of each of the discrete electncal resistances is computed as Zo (wls) where s is the spacmg distance 39 The method as recited m claim 38, wherem the value of each of the discrete electncal resistances vanes withm a range extendmg from about 0 1 tunes the nommal value to approximately 100 tunes the nominal value 40 The method as recited m claun 37, wherem when the gnd is not square, w is set equal to the spacmg distance and a nommal value of each of the discrete electncal resistances is set equal to the calculated value of Zo 41 The method as recited m claun 40, wherem the value of each of the discrete electπcal resistances vanes withm a range extendmg from about 0 1 tunes the nommal value to approximately 100 tunes the nommal value 42 The method as recited m claun 29, wherem the couplmg comprises overlaying the gnd upon the stmcmre, selectmg a location for the electncal resistance at a pomt withm the grid where two orthogonal lmes of the gnd mtersect near a periphery of stmcmre, and movmg the location to an adjacent portion of the penphery 43 The method as recited in claim 42, wherem the electπcal resistance comprises a plurality of discrete electncal resistances dispersed along a penphery of the stmcture, and wherem the movmg is accomplished such that distances between adjacent discrete electrical resistances are substantially equal 44 The method as recited m claun 29, wherem the couplmg compnses couplmg the electncal resistance between the planar conductors along at least a portion of a penphery of the structure 45 The method as recited m claim 29, wherem a portion of a penphery of the stmcmre defines a curve 46 The method as recited m claun 29, wherem the stmcture is substantially rectangular and has four sides, and wherem the couplmg compnses couplmg the plurality of electncal resistances between the planar conductors along at least a portion of one side of the structure 47 An electncal mterconnectmg apparatus, compnsmg a pau of parallel planar electrical conductors separated by a dielectπc layer, wherem each planar electrical conductor has an outer region substantially near a periphery, and wherem a pomon of the penphery of at least one of the pau of parallel planar electrical conductors defines a curve, and a plurality of unpedance networks electrically connected between the outer regions of the planar conductors, wherem each unpedance network mcludes an electrical resistor 48 The electπcal mterconnectmg apparatus as recited m claun 47, wherein each of the plurality of unpedance networks compnses an electrical resistance 49 The electncal mterconnectmg apparatus as recited m claun 47, wherem signals are conveyed withm the electncal mterconnectmg apparams, and wherem the signals have an associated frequency range, and wherem a maximum distance between adjacent unpedance networks is less than a wavelength of a maximum frequency with the frequency range

Inventors: NOVAK ISTVAN, YIP WAI-YEUNG, NOVAK, ISTVAN, YIP, WAI-YEUNG
Applicants: SUN MICROSYSTEMS INC, SUN MICROSYSTEMS, INC.
Application year: 1999
Main classification: H03H7
IPC codes: H01P1, H03H7, H05K1