FERROELECTRIC THIN FILMS OF REDUCED TETRAGONALITY

Abstract: A ferroelectric material, especially as incorporated into a crystallographically oriented epitaxial ferroelectric cell, of Pb1-xLaxZryTi1-yO3 or Pb1-xNbxZryTi1-yO3 having a moderately high La or Nb content such that the unit cell is less tetragonal, that is, more nearly cubic, so as to reduce stress effects. A most preferred value of the c/a constant is about 1.01. Exemplary compositional ranges for x are 6 to 20 % for La and 3 to 15 % for Nb, when y is 20 %. The reduced polarizabilities voltages are consistent with integrated ferrroelectric memories operating at 3.0V and lower.

Description: Ferroelectric Thin Films of Reduced Tetragonality FIELD OF THE INVENTION The invention relates generally to perovskite materials. In particular, the invention relates ferroelectric materials usable in ferroelectric memory cells. BACKGROUND ART Ferroelectric random access memories (FRAMs) offer the possibility of a non-volatile memory to replace silicon ones since FRAMs do not require energy to retain their electrically impressed polarization state. The schematized general structure of an FRAM 10 is illustrated in FIG. 1 and includes two capacitor plates 12, 14 between which is placed a body 16 of ferroelectric material. Not only does the ferroelectric material 16 have a dielectric constant substantially in excess of unity, but also under the proper conditions the ferroelectric is bistable. Once the capacitor plates 12, 14 have poled the ferroelectric into either the upwardly or downwardly directed polarization state, the ferroelectric body 16 remains in that state even after the poling voltage is removed. That is, a charge (or voltage) remains on the cell 10 without any power being currently applied. Sometime later, the charge can be measured. Thereby, the FRAM 10 forms a non-volatile memory. Conventionally, the FRAM has included a polycrystalline ferroelectric material sandwiched between two metallic electrodes in a capacitor structure. Such a design however has suffered from reliability and aging problems. More recently, Ramesh and coworkers have been developing crystallographically oriented ferroelectric cells using metal oxide electrodes. Dhote et al. have disclosed a platinum-based lower electrode in U.S. Patent Application, Serial No. 08/578,499, filed December 26, 1995, also published as PCT Publication 97/23886 on July 3, 1997. An exemplary structure of Dhote et al. for a ferroelectric random access memory (FRAM) 20, similar to a silicon dynamic RAM, is illustrated in cross section in FIG. 2. It is understood that this FRAM structure is replicated many times to form a large FRAM integrated circuit and that other support circuitry needs to be formed in the same chip. The overall FRAM structure, with a few exceptions, is known and has been disclosed by Ramesh in the previously cited U.S. patents and applications. Kinney provides a good overview of FRAM integrated circuits in "Signal magnitudes in high density ferroelectric memories," Integrated Ferroelectrics, vol. 4, 1994, pp. 131-144. The FRAM 20 is formed on a (OOl)-oriented crystalline silicon substrate 22 so that other silicon circuitry can easily be incorporated. A metal-oxide-semiconductor (MOS) transistor is formed by diffusing or implanting dopants of conductivity type opposite to that of the substrate 22 into source and drain wells 24, 26. The intervening gate region is overlaid with a gate structure 28 including a lower gate oxide and an upper metal gate line, e.g., aluminum, to control the gate. A first inter-level dielectric layer 30, for example of silicon dioxide, is deposited over the substrate 22 and the transistor structure. A contact hole 32 is photolithographically etched through the first inter-level dielectric layer 30 over the source well 24, and polysilicon is filled therein to form a polysilicon contact plug to the transistor source 24. A metal source line 34 is photolithographically delineated on top of the first inter-level dielectric layer 30 and electrically contacts the polysilicon plug 32. A second inter-level dielectric layer 36 is then deposited over the first inter-level dielectric layer 30. Another contact hole 38 is etched through both the first and second inter- level dielectric layers 30, 36 over the area of drain well 26, and polysilicon is filled therein to form a contact to the transistor drain 26. The processing up to this point is very standard in silicon technology. A lift-off mask is then deposited and defined to have an aperture over the drain contact hole 38 but of a larger area for the desired size of capacitor, although in commercial manufacture a masked dry plasma etch would typically be performed. Over the mask and into the aperture are deposited a sequence of layers. A polysilicon layer 40 provides good electrical contact to the polysilicon plug 38. A TiN layer 42 and a platinum layer 44 form conductive barrier layers between the polysilicon and the oxidizing metal-oxide contacts. Polysilicon is semiconductive, but, if its surface is oxidized into SiO 2 , a stable, insulating layer is formed that prevents electrical contact. Over the platinum layer 44 is deposited a layer 46 of a conductive metal oxide, preferably a perovskite, such as lanthanum strontium cobalt oxide (LSCO), although other metal oxides may be used, especially layered perovskites. This material has a composition nominally given by Lao 5 Sr 05 CoO 3 , although compositions of approximately La,_ x Sr x CoO 3 are possible with 0.15>x>0.85. It is now well known that LSCO forms an acceptable electrical contact, and it further promotes highly oriented growth of perovskite ferroelectric materials. The photomask is then lifted off leaving the lower stack of layers 40, 42, 44, 46 shown in FIG. 2. Another photomask is then defined allowing the conformal deposition of a Z-shaped field-oxide layer 48, which covers the sides of the previously defined lower stack, has a rim extending over the edge of the upper surface of the lower stack, and has a foot extending outwardly from the bottom of the lower stack, but leaves a central aperture for the after deposited upper ferroelectric stack. The field-oxide layer 48 electrically insulates the after deposited ferroelectric from the side portions of the lower electrode. In the past, the field-oxide layer 48 has been formed of SiO 2 or TiO 2 , but neither of these materials are ideal. Perovskite ferroelectrics when deposited over these materials tend to form in a mixture of perovskite and pyrochlore phases, which then differentially etch, resulting in unreliable etching. A better material for the field oxide layer 48 is bismuth titanate (approximately of the stoichiometric composition Bi 4 Ti 3 O 12 ), which is a perovskite and can be grown by the same growth process as the other perovskite layers. Ramesh in U.S. Patent 5,248,564 discloses that Bi 4 Ti 3 O 12 is a powerful templating layer for promoting the growth of crystallographically oriented perovskites over unoriented substrates so a Bi 4 Ti 3 O 12 field oxide layer 48 assures good quality ferroelectrics are grown over it. Other perovskite materials may be substituted for the bismuth titanate as long as they are not highly conducting and they display a low dielectric constant, e.g., not be a ferroelectric. For most effective templating, the perovskite forms of the Bi 4 Ti 3 O 12 should have a layered structure, that is, have a c-axis lattice that is at least twice those of the a- and b-axes. After the formation of the field oxide 48, another photomask is deposited and defined that includes an aperture around the lower stack 40, 42, 44, 46 but the outer periphery of its bottom overlies the feet 49 of the field-oxide layer 48. A ferroelectric layer 50 is then deposited under conditions favoring crystallographically oriented growth. Preferably, the ferroelectric layer 50 comprises lead lanthanum zirconium titanate (PLZT) or lead niobium zirconium titanate (PNZT). The deposition of the perovskite ferroelectric layer over LSCO or other similar perovskite conductive electrodes allows the ferroelectric to be deposited at a relatively low temperature but still manifest favorable crystallinity. Over the ferroelectric layer 50 is deposited an upper conductive metal-oxide layer 52, preferably symmetrically formed with the lower conductive metal-oxide layer 44, of a perovskite, such as LSCO. An upper platinum layer 54 is deposited over the upper conductive metal-oxide layer 52. This layer 54 is not considered to involve critical technology, and its platinum composition was selected only as an interim solution. It is anticipated that the composition will be changed to TiW or other metallizations common in silicon technology. After the upper platinum layer 54 is deposited, the photomask is lifted off leaving the structure of the upper stack illustrated in FIG. 2. A third inter-level dielectric layer 56 is deposited and etched to cover the ferroelectric stack. This layer 56 is intended more as a passivation layer than as an inter-level dielectric. The upper electrode 54 is then electrically contacted by etching a via 60 through the third inter-level dielectric layer 56 overlying the ferroelectric stack, filling the via 60 with Ti/W, and delineating a metal capacitor line 62 of Al that electrically contacts the Ti/W plug 60. Dhote et al. found that depositing the lower platinum layer 44 at a relatively high temperature, in the neighborhood of 500-550°C, allows the deposition of the ferroelectric stack (the ferroelectric and the two sandwiching metal-oxide layers) at a higher thermal budget, which is defined as the integral of the temperature (measured in °C) and the time the sample is at that temperature. Since the three layers, that is, the PNZT layer 50, the upper LSCO electrode 52, and the upper Pt layer 54, are typically deposited in a single chamber at a single temperature, the thermal budget becomes the product of the deposition temperature and the total deposition time. PNZT is a well known ferroelectric material. Dhote et al. give particular examples of the composition of PNZT as Pb 004 Nb 0 18 Zr 078 TiO 3 and PbNb 004 Zr 028 Ti 068 O 3 , that is, PNZT which is on one hand lead-poor or on the other hand lead-rich and zirconium-rich. A problem which needs to be addressed in ferroelectric memories of any sort is their fatigue behavior. It is generally observed that the ferroelectric or polarization properties of a ferroelectric cell degrade over a large number of read-write cycles. The polycrystalline cells suffer greatly from fatigue while the crystallographically oriented cells exhibit much greater resistance to fatigue. Nonetheless, fatigue is still believed to be problem with crystallographically oriented cells. To be able to quantize fatigue and other operating characteristics in ferroelectric cells, it is necessary to understand the polarization characteristics of a ferroelectric cell. A ferroelectric hysteresis loop 64 is illustrated in FIG. 3. The horizontal axis represents the voltage across the cell. The vertical axis represents the polarization of the material, whether immediately impressed or residual (remanent), that is, without a voltage being applied. The polarization is proportionately related to the time integral of the charge flowing into or from the cell. The hysteresis curve is highly non-linear. For this discussion, it is assumed that the characteristics are symmetric although this is not usually true in practice. The illustrated hysteresis curve implies that the hysteresis curve approaches a maximum polarization P sat as the applied voltage asymptotically approaches a saturation voltage V sat . However, the poling is usually performed along the voltage direction only to V max , which yields a P max of only about 90% of P sat . The difference in the polarization between poling to ±V max is indicated by P*, that is P*=2P max for a symmetric hysteresis curve. When the cell has been pulsed to V max , with an accompanying polarization of P max , but thereafter the voltage is reduced to V=0, the polarization is nonetheless maintained at a residual polarization P r . If the cell had been poled negatively, the polarization is retained a negative residual polarization, which for a symmetric hysteresis curve equal -P r . Assuming that the reading is performed by positive poling with an applied voltage of V max , the measured charge upon poling corresponds to either a non-switched polarization P Λ or a switched polarization P*. The reading circuitry must be able to distinguish the difference between them, which is the pulsed polarization ΔP = P* - P A . For a symmetric hysteresis curve, the pulsed polarization ΔP is equal to 2P r . Generally, it is felt that for superior performance the hysteresis curve should be as rectangular as possible. That is, the coercive voltage V c should be maximized for a given V max . This feeling is based upon the facts that the remanent polarization P r should be made as large as possible and that the remanent polarization increases with the coercive voltage. However, we believe that there are some countervailing considerations. Another consideration is that if ferroelectric memories are to be commercialized, they must be compatible with other silicon integrated circuits used in, for example, personal computers, computer work stations, and other computer controlled applications. For many years, digital silicon integrated circuits, whether logic or memory, were powered by a DC voltage V cc of 5VDC. However, in recent years, advanced integrated circuits have been designed to be powered by lesser voltages, 3.0VDC, 2.3VDC and 1.8NDC for example. The decreased voltages both reduce the problems associated with thermal dissipation in extremely dense integrated circuits and also provide extended battery operation for portable computers. An example of the critical reading circuitry associated with a ferroelectric cell 10 is illustrated in the circuit diagram of FIG. 4. This embodiment follows the description by Kinney et al. Other equivalent circuitry is possible. Associated with each ferroelectric cell 10 is a read transistor 66, corresponding to the MOS transistor 23 in FIG. 2. A word line 68 controls the read transistors 66 of a column of memory cells 10, but in a direction orthogonal to the work line 68. The read transistor 66 selectively connects the ferroelectric cell 10 to a bit line 70, which is similarly connected to row of memory cells 10. That is, the word lines 68 and bit lines 70 run in perpendicular directions over a rectangular array of memory cells 10. Because of hysteretic effects in the ferroelectric material, it is necessary to provide during the read process selective biasing of the other electrode of the ferroelectric cell 10 through a plate line 72, which runs in parallel to the word line 68. During the read process, the ferroelectric cell 10 is temporarily connected to the bit line 70 and the charge stored on the cell 10, whether in the positive or negative state, is shared with a larger parasitic capacitance 74 associated with the bit line 70, thereby generating two possible voltages on the bit line 70. A sense amplifier 76 then compares this voltage to a reference voltage resulting from a charge stored on a reference capacitor 78 and input to the sense amplifier 76 on line 79. The sense amplifier 76 outputs a digital signal OUT representing the charge state of the ferroelectric memory cell 10. Typically, the reference capacitor 78 is the parasitic capacitance associated with the complementary bit line -BL 79 not used in the current read cycle. The sense amplifier 76 is most often implemented as a cross-coupled bistable latch circuit that latches in one of two states depending upon which of the voltages on its two inputs lines 70, 79 is the highest. Hence, it is desirable to set the voltage on the reference capacitor 78 or associated bit line 79 at a voltage intermediate the complementary voltages induced on the active bit line 70 by the complementary states of the ferroelectric cell 10. All the above described operations are controlled, pre-charged, and discharged by a logic circuitry 80 having two power supply inputs at ground and at the DC power supply voltage V cc . As a result, barring the use of complex voltage multiplying circuitry, all operations within the memory circuit are limited to a maximum voltage swing of V cc . However, many designs for ferroelectric memories have been based on the power supply voltage V cc being 5VDC. As a general but loose rule, for a ferroelectric capacitor memory cell, the applied poling voltage V max is limited to no more than approximately half of the power supply voltage V cc . The reading of a ferroelectric cell is typically done by dividing the charge stored on the ferroelectric capacitor with a larger capacitance associated with the bit line. On account of this voltage drop and other voltage losses across various capacitors in the reading and writing circuitry, it is common that V max or V sat is five time the coercive voltage V c . In any case, low values of the coercive voltage V c are reflected in low values of the saturation voltage V sat . Assuming a power supply voltage V cc of 1.8VDC, it is desired that the coercive voltage V c be 0.5 to 0.6VDC, with everything being switched by 0.9VDC. Generally, if the coercive voltage V c is low, the saturation voltage V sat is also low. Theoretically, it is possible in view of the reduced voltage operating range to simply reduce the thickness of the ferroelectric layer in the ferroelectric cell since the ferroelectric effects are dependent upon the applied electric field, that is, the applied potential divided by the thickness of the ferroelectric layer. Thereby V c and V max would scale downward with the ferroelectric thickness. However, present day ferroelectric materials are imperfect electrical insulators, and an unacceptably high electrical conductivity will prevent the ferroelectric cell from operating in a realistic system. The problem is-linear, that is, not ohmic, for example by electronic quantum hopping. As a result, a small increase in local effective electric field may result in a very large increase in electrical current. These effects result in the commonly accepted limitation that the ferroelectric layer have a minimum thickness of 0.23μm or at least no less than 0.15μm. At lesser thicknesses, the leakage current across the ferroelectric becomes excessive. As a result of the minimum thickness, the voltage applied across the ferroelectric layer must exceed a minimum value producing adequate capacitive charge storage. The physical operation of a ferroelectric cell is believed to follow the mechanism illustrated in FIG. 5 for a simple ferroelectric material such as PZT ( PbZrTiO 3 ), PLZT (PbLaZrTiO 3 , and other well known materials. These first three materials are best characterized as alloys of the compounds PbZrO 3 , PbTiO 3 , LaZrO 3 , and LaNbO 3 , in the case of PLZT. Similar characterizations should be made for PNZT (PbNbZrTiO 3 ). A unit cell for these materials is generally tetragonal, that is, a rectangular cell having three perpendicular unit vectors, one having a value c and the other two having the same value a. For most ferroelectric materials, c is greater than a. The ratio c/a will be defined to be the tetragonality factor of the ferroelectric material. The unit cell includes eight rare-earth atoms 82 of lead (Pb), lanthanum (La), or niobium (Nb) at its corners, six oxygen (O) atoms 84 in the middle of the six rectangular faces, and one cation atom of titanium (Ti), zirconium (Zr), etc. located generally at the center of the tetragonal cell. However, below the Curie temperature, the low- energy cation position is located either above or below the cell center at one of the offset positions 86a, 86b. The displacement of the cation from the cell center provides the bistable ferroelectric behavior. Which of the two offset positions 86a, 86b the cation assumes determines the polarization state of the cell. It is desired to take advantage of the known characteristics, advantages, and disadvantages of ferroelectric memory cells to produce a design for cells particularly advantageous for low-voltage operation. SUMMARY OF THE INVENTION The invention can be summarized as a ferroelectric capacitor cell having a crystallographically oriented ferroelectric layer formed on a metal-oxide electrode layer. The ferroelectric material is chosen to have a composition that has a low tetragonality factor, that is, a low c/a ratio for a tetragonal perovskite. In particular, the tetragonality factor may indicate a composition of a complex ferroelectric alloy that provides less than optimal ferroelectric characteristics. Nonetheless, a ferroelectric cell is likely to manifest better fatigue characteristics because of the less stress of the lower tetragonality factor, and the better characteristics may not be polable with voltage levels used in densely integrated memories. The effect has been demonstrated for lead lanthanum zirconium titanate (PLZT) and lead niobium zirconium titanate (PNZT). BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a schematic representation of a ferroelectric memory cell. FIG. 2 is a cross-sectional view of a ferroelectric memory cell to which the invention can be applied. FIG. 3 is a graph illustrating the important ferroelectric parameters of a ferroelectric cell. FIG. 4 is a electrical schematic diagram illustrating the read/write circuitry associated with a ferroelectric memory cell. FIG. 5 is a schematic orthographic illustration of the crystalline structure of ferroelectric materials such as PZT, PLZT and other perovskites. FIG. 6 is graph of hysteresis curves for two compositions of lead lanthanum zircotitanate. FIG. 7 is a graph of hysteresis curves for different poling voltages for a PLZT composition of the invention. FIG. 8 is a graph of hysteresis curves for three compositions of lead niobium zircotitanate. FIG. 9 is a graph of the switched polarization as a function of poling voltage for cells composed of PNZT with three values of niobium content. FIG. 10 is a graph of coercive voltage as a function of poling voltage for the three PNZT cells. FIG. 11 is a graph of bipolar switched polarization as a function of fatigue cycles for the three PNZT cells. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT My conclusion based partially upon some of the considerations presented in the background section is that, for advanced ferroelectric integrated circuits, the coercive voltage V c and the maximum operating voltage V max should be no more than acceptably high values, contrary to the prior art which believed the coercive voltage should be as high as possible. The present invention attempts to take advantage of the countervailing considerations between large tetragonality promoting good ferroelectric behavior but poor fatigue characteristics and excessively high operating voltage and small tetragonality exhibiting poor ferroelectric characteristics but good fatigue characteristics and low operating voltages. The c/a factor of the ferroelectric material, illustrated in FIG. 5, has major implications for the ferroelectric behavior and fatigue characteristics. A small c/a ratio means the unit cell is closer to a cubic symmetry while a larger ratio results in greater tetragonality of the cell. Generally, the larger the c/a ratio, the greater is the polarizability of the material, as manifested by large values of the maximum polarization P max and of the remanent polarization P r . It would also appear that a large c/a ratio produces a more rectangular hysteresis loop 70, thus contributing to a large coercive voltage V c . However, as explained before, a large coercive voltage N c may not always be desirable. It also appears that a large c/a ratio contributes to fatigue characteristics and may as a result further reduce the squareness of the hysteresis. These perovskite materials are almost always grown above the Curie temperature so that the material as grown has a cubic lattice structure with a single lattice dimension of a '. In the crystallographically oriented materials needed for advanced ferroelectric integrated circuits, the cubic material as grown is to some degree epitaxially oriented to the underlying templating layer of, for example, LSCO. As the material is cooled to below the Curie temperature, the material converts to the tetragonal structure of FIG. 5. Ignoring thermal expansion effects at temperatures remote from the transition, as the material is cooled across the phase transition, the lattice constant decreases in two dimensions from a 'to a while in the other dimension the lattice constant increases from a 'Xo c. Nonetheless, the newly tetragonal material remains atomically anchored to the substrate that does not undergo such a transition. As a result, the transition impresses a great amount of stress in the ferroelectric material, particularly near the interface with the templating layer, and the stress is larger for larger c/a ratios. Such high levels of stress are expected to drive several mechanisms contributing to fatigue and imprint in crystallographically oriented ferroelectrics. It is noted that in polycrystalline ferroelectrics typical in the prior art, there is no atomic templating, and the tetragonal crystallites can accommodate a much higher lattice mismatch on the crystallite faces. Thus, particularly for crystallographically oriented tetragonal perovskites, a large c/a ratio implies a great amount of induced stress which may seriously increase fatigue. It is also believed that a large c/a ratio leads to slower switching of the ferroelectric polarization. A second effect is that there are three possible orientations for the tetragonal structure as the material is cooled from the growth temperature to below the Curie temperature. The structure of FIG. 5 is based upon the generally preferred orientation that the c-axis is perpendicular to the plane of the templating layer. This is referred to as a c-domain. However, on a local scale, it is also possible that one or the other of the two α-axes is perpendicular to the templating layer with the c-axis lying in the plane. These orientations are α-domains. The existence of both a- and c-orientations produce 90° domain walls between the two differentially oriented regions. Uniform c-domains are preferred, and generally the -domains will anneal to the orientation of the neighboring c-domains and form larger domains. However, if there is large value of c/a, any annealing at lower temperature includes a significant distortion from the existing crystal structure and the transition, while favorable, is difficult to activate. That is, the multiple orientations may be metastable. Song et al. have explained this effect in "Activation field of ferroelectric (Pb,La)(Zr,Ti)O 3 capacitors," Applied Physics Letters, vol. 71, no. 15, October 1997, pp. 2211-2213. Furthermore, the operation of ferroelectric cells ultimately depends upon the switching of polarization domains. It is well known that ferroelectrics containing multiple domains with 90° domain walls between them require higher fields to switch compared to those with only 180° domain walls. Hence, it is desirable to suppress the multiple orientations arising from c-domains in the predominantly c-axis oriented ferroelectric material. Based upon these considerations, we now believe that ferroelectric integrated circuits which need to be operated at lower voltages should include a ferroelectric material of lower tetragonality, that is, a reduced c/a ratio though one having a value above unity. The c/a ratio may be described as a tetragonality factor for materials having the same or nearly the same a- axis lattice vectors in two directions. Although the polarization effects may be degraded by a lower c/a ratio, they may still be quite adequate. At the same time, the fatigue characteristics are improved because of the reduced strain. Further, it is believed that the material is easier to anneal into a purely c-axis oriented material. Yet further, the ferroelectric cells of lower tetragonality are expect to be more easily switched. That is, the switching speed is increased. I believe, based on experiments presented below, that a c/a ratio of about 1.01 is most preferred, and beneficial results are obtained with values of the tetragonality factor extending down to 1.005. One favored class of ferroelectric material is PLZT, that is Pb,. x La x Zr y Ti,. y . A more compact designation is, for example, 7/65/35 where x=l%, y=65%, and i-y=35%. The designation thus amounts to x/y/l-y. Generally, a large value of x decreases ferroelectric effects but favors crystalline quality because of the decreased tetragonality. PLZT with high values of x around 65% are used for electrooptical devices, but at these values of x, the material is non-tetragonal. I believe that for reduced voltage operation, PLZT should have a La content x of between 6 and 12%. One of the examples presented by Ramesh in U.S. Patent 5,270,298 includes a ferroelectric cell structure with PLZT having a composition of x=10%, y=20%, that is, 10/20/80. Note that the cited application uses different definitions for x and y. Two prototype capacitor structures were fabricated according the method of the cited patent. One composition was (0/20/80) and the other was (10/20/80), that x equals alternatively 0% and 10%. The crystallographic parameters for thin films of these materials are given in TABLE 1. Yang et al. reports similar results in "Low voltage performance of Pb(Zr, Ti)O 3 capacitors through donor doping," Applied Physics Letters, vol. 71, no. 25, December 1997, pp. 3578- 3580. x (%) c (nm) a (nm) c/a 0 0.411 0.395 1.034 3 0.410 0.396 1.030 10 0.4025 0.396 1.016 TABLE 1 Pulsed hysteresis curves were measured for the two samples. The results are shown in FIG. 6. The PZT sample (x=0) in loop 90 shows a very square characteristic, while the PLZT sample with x=10% in loop 92 shows a less square behavior. Later measurements of the hysteresis curve for the x=0.3 PLZT capacitors show results intermediate the graphs of FIG. 6. The x=0.1 PLZT sample was tested for a number of pulsed poling voltages. The hysteresis loops are shown in FIG. 7: loop 94 for 5V poling; loop 96 for 2.3V poling; and loop 98 for 2V poling. For the x=0.1 PLZT sample, the saturation polarization is about 35μC/cm 2 at 5V, and the coercive voltages V c are all about 0.6V. The x=0.1 PLZT capacitors were tested for fatigue at both room temperature and at 100°C. Both the fatiguing and test pulses were at 2V. The samples showed essentially no fatigue out to 10 11 cycles. Other tests with =0.03 PLZT capacitors showed better initial polarizability, but fatigue above 10 9 cycles degrade the polarizability to below that for the As suggested previously, it is believed that the higher-lanthanum ferroelectrics will switch with lower energies than the more highly polarized lower-lanthanum ferroelectrics because of the lesser occurrence of -axis domains. In an operational cell, this benefit is believed to extend to switching with shorter pulse widths, an effect that becomes important with ferroelectric memories which should switch at substantially less than a lμm when incorporated into computer systems, for example, using pulse widths of 100ns. Experimental results are not available for a direct comparison between similarly fabricated cells with ferroelectrics of differing tetragonality. However, pulse-width measures show that PLZT capacitors may have somewhat less switchable polarization at longer pulse widths than do PZT capacitors, presumably because PLZT has a lower tetragonality factor than does PZT. However, as the pulse width decreases towards 100ns, the switchable polarization of PZT substantially falls while PLZT suffers a lesser decrease. Thus, it is expected that the higher- lanthanum PLZT will operate better with very short pulse widths. These results for PLZT show that superior results are obtained with a tetragonality factor c/a of 1.016 rather than 1.030. I believe that a tetragonality factor of 1.01 should provide even better results for low voltage operation of the ferroelectric cell, and a tetragonality factor of even 1.005 would be beneficial. Another ferroelectric material of great interest is PNZT, that is, Pb 1 . x Nb x Zr y Ti 1 . y O 3 . We observe that this material behaves similarly to PLZT, although less dramatically in the polarization effects, but the fatigue and timing effects are substantial. A series of prototype test capacitor structures were fabricated using the now conventional pulsed ablation deposition (PLD) technique. A (lOO)-oriented silicon substrate was covered first with a TiN barrier layer. The TiN-covered substrate was then covered in a PLD process with a platinum contact layer. The ferroelectric layers were then grown by PLD in an oxygen environment at 600°C. The ferroelectric stack consisted of a lower contact template layer of LSCO, a PNZT ferroelectric layer, and a top contact layer of LSCO. The crystallographic parameters for thin films of Pb ! . x Nb x Zr 02 Ti 08 O 3 , that is, (x/80/20) PNZT, are given in TABLE 2. are given in TABLE 2. x (%) c (nm) a (nm) c/a 0 0.4103 0.3968 1.034 6 0.4088 0.3975 1.0284 10 0.4083 0.3991 1.0233 TABLE 2 Hysteresis curves for capacitor structures for the three compositions were measured with a poling voltage of 4.5V, as shown in FIG. 8. Loop 100 shows the hysteresis curve for x=0, that is, PZT; loop 102, for x=6%; and loop 104, for x=10%. The polarization properties decrease somewhat for x=6% and substantially more for =10%. Nonetheless the niobium- rich sample exhibit good hysteretic characteristics. Similar hysteretic characteristics were obtained using a barrier layer of (Ti 09 Al 0 ,)N with a varying niobium content. Close analysis of these curves show interesting results as the maximum applied voltages are reduced and as the devices are fatigued. In FIG. 9 are illustrated curves for the switched polarization ΔP=P*-P Λ as a function of the maximum applied voltage V max . Curve 110 gives the switch polarization for a Nb content of x=0%; curve 112, for The Nb-free sample, that is, of PZT, exhibits the largest switched polarization at the highest switching voltage of 5 V. The sample with x=6% is somewhat reduced, and the highest content of niobium exhibits the least switched polarization. At 4V, the difference is even larger. However, as the maximum voltages are reduced below 3V, the situation changes. At 2N, the results are the same for 6% and 10%. In FIG. 10 are shown the coercive voltages V c as a function of maximum applied voltage V max for the same three values of Νb content. Curve 120 gives the value for x=0; curve 122, for The low values of V c correspond to low values of V sat and to better low-voltage properties. The fatigue results are even more interesting. The memory cells were fatigued with bipolar pulses of ±3V at 1MHz. Their bipolar switched polarizations ±P were measured at various times during the fatigue cycling, and the results are shown in FIG. 11. Curves 130 gives the switched polarizations for With no fatigue, the cells with lower Νb content showed somewhat better switched polarization than the cell with x=10%. However, after extended fatiguing, the cells with x=0 began to severely degrade, and those with Νb content of 6% and higher showed better overall results. Thus, it is seen that the La or Νb content should be raised to levels above those normally recommended for commercially viable ferroelectric memory cells. For PLZT, the lanthanum fraction x should be at least 3% and preferably more than 6% up to 12% when the Zr fraction is approximately 20%. I believe that 15% is the maximum preferred La fraction if reasonable polarizabilities are to be achieved. The highest value of the La content is limited by the PLZT forming in a non-ferroelectric phase. The Zr fraction can be increased to 50%, for which the La fraction is much less, preferably around 2%. For PΝZT, I believe the same numbers apply to the Zr and Νb fractions. Expressed in terms of the tetragonality factor c/a, for PΝZT it should be reduced to below 1.029 and preferably below 1.025. Beneficial results are expected with the PNZT tetragonality factor having a value in a range extending down to 1.020. The memory cell presented in FIG. 1 is presented only to explain the exact structure used in the examples. Other structures of crystallographically oriented ferroelectrics may be used. Particularly preferred are those not requiring any platinum, such as the one incorporating an intermetallic barrier, disclosed by Dhote et al. in U.S. Patent Application 08/582,545, filed January 3, 1996 and by Dhote et al. in U.S. Patent Application 08/871,059, filed June 19, 1997. The former corresponds to PCT Publication WO 97/25745. Though the invention has been described with respect to particular compositions of PLZT and PNZT, it is not limited thereto. Rare-earth elements other than lanthanum and niobium may be used in fractions that reduce the tetragonality relative to a fraction that produces higher polarization effects. The invention thus provides a ferroelectric cell that trades off unneeded polarization for needed stress reduction, resulting in less fatigue and higher switching speeds.

Claims: What is claimed is: 1. A ferroelectric memory cell, comprising: a metal oxide first electrode; a ferroelectric layer formed on said first electrode, having a perovskite crystal structure, and comprising Pb, Zr, Ti, O and at least one additional rare-earth element; a second electrode formed on said ferroelectric layer; and circuitry connected to said two electrodes for powering, controlling, and reading a charge stored on said ferroelectric layer and having a maximum DC power supply voltage of no more than 3V, wherein said ferroelectric layer comprises a sufficient fraction of said at least one rare earth element to allow operation of said circuitry at said maximum DC power supply voltage. 2. The memory cell of Claim 1, wherein said at least one rare-earth element comprises La. 3. The memory cell of Claim 1, wherein said at least one rare-earth element comprises Nb. 4. The memory cell of Claim 1, wherein a fraction x of the rare-element compared to a fraction 1-x of Pb is equal to or greater than 3%. 5. The memory cell of Claim 4, wherein said fraction x is equal to or greater than 6%. 6. The memory cell of Claim 6, wherein said fraction x is no more than 30%. 7. A ferroelectric cell, comprising: a first electrode comprising a metal oxide; a ferroelectric layer formed on said first electrode, having a perovskite crystal structure, and comprising Pb^Nb χ Zr y Ti^ y O ; ,, where x is equal to or greater than 3%; and a second electrode formed over said ferroelectric layer. 8. The memory cell of Claim 5, wherein y is between 15% and 30%. 9. The memory cell of claim 2, wherein y is approximately 20%. 10. The memory cell of Claim 9, wherein x is equal to or greater than 6%. 11. The memory cell of Claim 10, wherein x is no greater than 15% 12. A ferroelectric cell, comprising: a first electrode comprising a metal oxide; a ferroelectric layer formed on said first electrode and comprising a first amount of a first rare-earth element, a second amount of a second rare-element, at least one cation element, and oxygen and forming a first perovskite crystal structure with a first tetragonality factor; a second electrode formed over said ferroelectric layer; wherein said first and second amounts are chosen to have values such that said first tetragonality factor is less than a second tetragonality factor produced if said ferroelectric layer were formed into a second perovskite crystal structure without any of said first rare- earth element a first polarization characteristic of said first perovskite crystal structure being less than a corresponding second polarization characteristics of at least one of said second. 13. The ferroelectric cell of Claim 12, wherein said first and second amounts are chosen to have values such that said first tetragonality factor is less than a third tetragonality factor produced if said ferroelectric layer were formed into a third perovskite crystal structure without any of said second rare-earth element, said first polarization characteristic of said first perovskite crystal structure being less than a corresponding third polarization characteristic of said third perovskite crystal structure. 14. The ferroelectric cell of Claim 12, further comprising circuitry connected to said two electrodes for powering, controlling, and reading a charge stored on said ferroelectric layer and having a maximum DC power supply voltage of no more than 3V. 15. The ferroelectric cell of Claim 12, wherein said ferroelectric layer comprises Pb, La, Zr, Ti, and O. 16. The ferroelectric cell of Claim 12, wherein said ferroelectric layer comprises Pb, Nb, Zr, Ti, and O.

Inventors: RAMESH RAMAMOORTHY, RAMESH, RAMAMOORTHY
Applicants: TELCORDIA TECH INC, UNIV MARYLAND, TELCORDIA TECHNOLOGIES, INC., UNIVERSITY OF MARYLAND
Application year: 1999
Main classification: H01L29
IPC codes: G11C11, H01L21, H01L27, H01L29