CONVERTER CIRCUIT AND VARIABLE GAIN AMPLIFIER WITH TEMPERATURE COMPENSATION

Abstract: A voltage converting multiplier circuit converts a single ended input voltage Vgain into a differential output voltage VOUT, and includes a differential input cell (120) and a differential output cell (130), each biased by a respective control current (140, 150). A control circuit includes an input device (R10) having a resistance Rin coupled to an input terminal (110), and a differential amplifier (A2) which controls the differential input cell to maintain a voltage at one end of the input device (R10) equal to a reference voltage VREF, so as to convert the input voltage into an input current dI equal to (VREF-VIN)/R1. A current mirror (160) ensures that the input current is splitted by the branches (123, 124) of the differential input cell (120), which current splitting is mirrored to the differential output cell (130). An output device (R14, R15) (having a resistance ROUT in each branch (134, 133) of the differential output cell (130) converts the differential output current to the differential output voltage VOUT, where VOUT = Vin(Rout/Rin)(Icout/Icin) where Icout and Icin are the control currents applied to the differential input and output cells, respectively. A temperature compensated voltage is achieved where Icin is a constant current and Icout is a temperature compensated current. A temperature compensated variable gain amplifier including the converter circuit is also disclosed.

Description: Converter circuit and variable gain amplifier with temperature compensation. BACKGROUND OF THE INVENTION 1. Field of the Invention The invention concerns converter circuits which convert a single ended voltage to a differential output. More particularly, the invention concerns reducing circuit complexity 5 and size of such a converter circuit while providing temperature compensation. The invention also concerns a variable gain amplifier ("VGA") with such a converter circuit. 2. Description of the Prior Art Many communication applications require some sort of variable gain that is a 10 exponentially proportional to an input control voltage. Since on a dB scale the gain curve becomes a straight line, this is commonly referred to as "linear-in-dB". An example of where a linear-in-dB variable gain is required is in transceivers for cellular phones. A VGA is used in the automatic gain control loop of the transmitter to regulate the power of the signal transmitted from the cellular phone. A VGA is also used in the receiver to 15 regulate the signal power for the intermediate-frequency (LF) and signal dividing stages of the receiver despite a varying input power of the received RF signal. Most VGA circuits accomplish this desired linear-in-dB behavior by, one way or another, exploiting the exponential characteristic of a bipolar transistor. A well-known technique relies on the fact that the ratio of the collector currents of a bipolar differential pair 20 is exponentially dependant on the differential input voltage. Figure 1 shows a differential pair of bipolar transistors Ql and Q2 with common emitters biased by a tail current Itail from current source 5 and their bases controlled by a differential input voltage vin+, vin- at differential inputs 1,2. The relation between the collector currents iout+ and iout- at the outputs 3, 4 and the input voltages vin+ and vin- can be described as where q is the charge of an electron, k is Boltzmann's constant and T represents the absolute temperature. The fact that it is the ratio of the collector currents that exhibits the linear-in-dB behavior enables the bipolar differential pair to be used for a wide range of variable gain circuits that rely on current ratios to set their gain. A classic and widely-used example of such a circuit is the translinear Gilbert multiplier cell known, inter alia, from, B. Gilbert, "Analog IC Design, the Current Mode Approach", Chapter 2, Peter Peregrinus Ltd (U.K. 1990). Equation 1 clearly shows the exponential characteristic of the circuit. It also reveals another important aspect. The presence of the absolute temperature T, in the denominator of the right hand side argument, indicates that the collector current ratio is not only a function of the differential input voltage, but also of the operating temperature. This temperature effect can be quite significant, as circuits are commonly required to operate over a temperature range between about 230°K and 380°K. The mathematical solution to the temperature sensitivity of Eq. 1 is relatively simple: multiplying the differential input voltage with a factor that is proportional to the absolute temperature cancels out the absolute temperature T in the denominator. In other words, if where c is an arbitrary constant, then by multiplying the differential input voltage with f(T), Eq. 1 becomes lou t - l(V, - - Vm-) m _ cq(V^ -V m T _ cq(V^ -V,„ kT kT The right hand term of Eq. 3, apart from the constants, relies on the input voltage alone and has become independent of the temperature. A known way to realize the temperature cancellation principle of Eq. 3 in a physical circuit is shown in Figs. 2(a), 2(b). Figure 2(b) represents a Gilbert multiplier that multiplies an incoming control signal by a factor that equals the ratio of the two currents Iconst and Iptat. If the current "Iconst" is constant over temperature and "Iptat" is proportional to the absolute temperature T (PTAT), this ratio becomes the desired linear function of the temperature: f(T) = 2 = cT 1 const Unfortunately, the known multiplier of Fig. 2(b) only accepts a differential current (10+dl, 10-dl) at its input 12, 13, whereas the required control input for most variable gain amplifiers is single-ended voltage. This disparity accounts for the added circuitry shown in Fig. 2(a), which is a schematic of a traditional voltage-to-current convertor with single-ended input and differential output. The circuit of Fig. 2(a) is known from: Gurkanwal Singh Sahota, Charles James Persico, "High Dynamic Range Variable-Gain Amplifier for CDMA Wireless Applications", proceeding ISSCC (U.S.A. 1997). To understand the operation of the circuit of Fig. 2(a), assume that the amplifier Al has sufficient gain to keep the voltage at its positive input equal to the reference voltage V ref at its negative input. In that case, the voltage at the right hand terminal of the input resistor Rl becomes V ref . Since the other terminal of the resistor Rl is connected to the input terminal 9 which receives the gain control voltage V ga j n , there will be a voltage drop of V ref -V gain across the resistor Rl, which causes a current dl to be taken away from the circuit. This current dl is supplied by the transistor Q3, together with the constant bias current 10. The total current at the collector of the transistor Q3 is therefore 10 + dl. In case the voltage at the positive input of the amplifier Al inadvertently deviates from the assumed voltage V re f, the feedback loop formed by the transistors Ql, Q2 and Q3 will adjust the collector current of the transistor Q3 until the voltage at the positive input of the amplifier Al is corrected to V re r. Due to the parallel connections of the base and emitter terminals of the transistors Q3 and Q4, the collector current of the transistor Q4 will track that of the transistor Q3. Thus, a current of 10 + dl will flow out of the first output terminal 10 of the voltage-to-current converter. The transistor Q5 also copies the collector current of the transistor Q3. In this case, however, the current 10 + dl is directed through the current mirror formed by the transistors Q6/Q7, and then subtracted from a constant bias current 210. The result at the second output terminal 11 is a current that equals I0-dI. The total differential output current of the circuit in Fig. 2(a) is ((10+dI - (10-dI)), or 2dl, which can be used to directly drive the Gilbert multiplier of Fig. 2(b). Looking more closely at the voltage-to-current converter of Fig. 2(a), several drawbacks become apparent, most of them related to the accuracy of the circuit. First, the voltages at the collectors of the transistors Q2, Q3, Q4 and Q5 are all different, leading to small but significant differences in the collector currents of the respective transistors. This causes an error in the overall gain setting of the variable gain amplifier. In the same way, integrated circuit process related random mismatches between any of the devices Q2-Q5 will adversely affect the accuracy. A second drawback stems from the fact that the current coming out of the transistor Q5 is first mirrored by the transistors Q6 and Q7, while the current from the transistor Q4 is directly flowing to the output terminal 10 without first being mirrored by a current mirror. Not only will any random mismatch between the transistors Q6 and Q7 deteriorate the overall performance, but also here, the collector voltages of the two current mirror transistors Q6, Q7 are not identical, adding to the total error. A final, more general, drawback involves the complexity of the circuit. Combining the two schematics of Fig.2(a) and Fig.2(b) typically yields a block that consumes a considerable part of the total die area of a VGA. SUMMARY OF THE INVENTION Generally speaking, according to one aspect of the invention, a voltage converting multiplier circuit includes a multiplier circuit comprising a differential input cell and a differential output cell coupled in a pair wise configuration. Each differential cell includes an inverting input, a non-inverting input, an inverting output and a non-inverting output, and a control current terminal. An input terminal receives an input voltage V gaιn and a control circuit receives a reference voltage V re f, converts the input voltage to an input current dl proportional to the difference between the reference voltage V re f and the input voltage V m , equally divides the input current and applies the divided input current to the inverting and non- inverting outputs of the differential input cell such that the inverting and non-inverting outputs of the differential output cell output a differential output current I ou t proportional to dl (I cout /I cm ), where I cout is a control current applied to the control current terminal of the differential output cell and I c in is a control current applied to the control current terminal of the differential input cell. Instead of first converting a single ended input voltage to a differential output current to be applied to the input cell of a multiplier circuit as in the known configuration of Fig. 2, the circuit according to the invention controls an input cell of a multiplier circuit to convert a single ended input voltage to an input current, which input current is split to provide a differential current in the first cell which is mirrored to the output cell. This technique allows for reducing component count as well as improving circuit accuracy as compared to the known circuit. According to another aspect of the invention, the control circuit includes an input device having resistance R, n coupled to the input terminal, and a differential amplifier which controls the differential input cell to maintain a voltage at one end of the input device equal to a reference voltage VR EF . SO as to convert the input voltage into the input current dl equal to (V REF - V, N )/R in . According to another aspect of the invention, the control circuit includes a current mirror having an input which together with an inverting output of the differential input cell supplies the input current dl. Each of the current mirror input and the inverting output of the differential cell supply part, and preferably half, of the input current dl. Since the current mirror only mirrors part of the input current dl, any errors due to process variations in manufacturing the current mirror transistors is significantly reduced as compared to the known circuit in which the current mirror mirrors the entire input current. According to yet another aspect of the invention, a pair of output devices each coupled to a respective one of the inverting and non-inverting outputs of said differential output cell convert the differential output current to a differential output voltage. Each of the pair of output devices has a resistance R oUt , the differential output voltage being at least substantially equal to (I cout I c i n )(R out Ri n )(V re rV in ). According to still another aspect of the invention, error is further reduced as compared to the known circuit by equalizing the collector voltages of the bipolar transistors forming the current mirror. This is accomplished in a simple manner with a second differential amplifier according to an embodiment. According to yet another aspect of the invention, temperature compensation is achieved by biasing the differential input cell with a constant current and the differential output cell with a temperature compensated current. According to another aspect of the invention, a common mode control circuit controls the common mode current of the differential amplifier. According to still another aspect of the invention, a VGA includes such a voltage converting multiplier converter circuit, thus providing a simplified VGA which receives a single ended gain control voltage and outputs a temperature compensated current having a linear-in-dB relationship with the gain control voltage. These and other object, features and advantages of the invention will become apparent with reference to the following detailed description and the drawings. BRIEF DESCRIPTION OF THE DRAWINGS Figure 1 shows a differential pair of bipolar transistors (prior art); Figures 2(a) and 2(b) together illustrate the building blocks of a prior art temperature compensating voltage converter circuit. Figure 2(b) is a circuit diagram of a prior art Gilbert cell multiplier and Figure 2(a) is a circuit diagram of a prior art voltage-to-current converter for driving the Gilbert cell of Figure 2(b; Figure 3 is a circuit diagram of temperature compensating voltage converter circuit according to one embodiment of the invention; and Figure 4 is a circuit diagram of a temperature compensating voltage converter circuit according to a second embodiment of the invention. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Figure 3 shows an improved voltage converting multiplier circuit 100 according to one embodiment of the invention which converts a single-ended, gain control input voltage V ga i n to a temperature compensated, differential output voltage V outp , V outm . This differential output voltage, when used to drive the inputs 1, 2 of the differential pair (transistors Ql, Q2) of Figure 1, provides a collector current ratio of the differential pair Ql, Q2 which is exponentially proportional to the gain control voltage V gaιn ("linear-in-dB"), and independent of temperature. Circuit 100 includes a multiplier cell having a differential input cell 120 including differential input transistors Q19, Q20 and a differential output cell 130 including differential output transistors Q21, Q22. Each differential cell includes, respectively, an inverting input 121, 131 and a non-inverting input 122, 132, an inverting output 123, 133, and a non-inverting output 124, 134. The outputs of the differential cells are formed by the respective collectors of the transistors Q19-Q22 while the inputs are formed by the respective bases of the transistors Q19-Q22. The differential cells 120, 130 are coupled in pairwise configuration, with the inverting inputs 121, 131 (or alternatively the bases of the transistors Q19, Q22) coupled together and the non-inverting inputs 122, 132 (or alternatively the bases of the transistors Q20, Q21) coupled together. The emitters of the transistors Q19, Q20 are commonly coupled at a control current terminal 125 of the differential input cell while the emitters of the output transistors Q21, Q22 are commonly coupled at a control current terminal 135 of the differential output cell. Input terminal 110 receives a single ended input voltage V gaιn . A control circuit includes an input resistor R10 having a resistance R ιn , a differential amplifier A2 and a current mirror 160. Current mirror 160 includes bipolar transistors Q16, Q17 having their emitters coupled to a first supply terminal Vcc and their bases coupled to each other. The base of transistor Q17 is also connected to its collector. The differential amplifier A2 includes an inverting and a non-inverting input and an inverting and non-inverting output. The non- inverting input is coupled to receive a reference voltage V re f. The inverting input of the amplifier A2 is coupled to one end of the input resistor Rl 0, the other end of which is coupled to the input terminal 110. The non-inverting output of amplifier A2 is coupled to the non- inverting input 122 (the base of transistor Q20) and the inverting output is coupled to the inverting input 121 (the base of transistor Q19). The collectors of the current mirror transistors Q16, Q17 are coupled to respective outputs 123, 124 of the differential input cell. Current source 140 biases the emitters of the transistors Q19, Q20 with a first bias current I cιn via the current control terminal 125 while the current source 150 biases the emitters of the output transistors Q21, Q22 with a second bias current I c0Ut via the current control terminal 135 of the differential output cell. The circuit 100 also includes a pair of resistors R14, R15, each coupled between V cc and a respective output 134, 135 of output cell 130. The circuit of Figure 3 operates as follows. The differential amplifier A2 nulls the difference between the voltages at its inverting and non-inverting inputs. This means that the input resistor R10 will see a voltage V ref at its end (right side in Fig. 3) connected to the inverting input of amplifier A2. When a gain control voltage V ga j„ is applied at the input terminal 110, a current dl will flow out of the circuit, dl being equal to (Vref- Vgain)/Rj n . The differential input pair Q19, Q20 is biased at a constant current ^, provided by current source 140, and is driven by the output of amplifier A2. The current dl is split and directly forced onto the input differential pair Q19, Q20. Half of the current (dI/2) flowing out through input terminal 110 is supplied by the input transistor Q 19, and the other half is supplied by the other input transistor Q20, through the current mirror 160 formed by the transistors Q16 and Q17. The current difference in the two branches of the differential input cell, i.e. the difference in collector currents of the input pair Q19 and Q20 is therefore dl, due to the flow of current dI/2 in opposite directions in transistors Q19, Q20. The current gain of the circuit 100 is set by the ratio of the tail currents I cm and l out , so the difference in collector currents dl 0ut of the differential output pair Q21 and Q22 equals Substituting the above expression for dl yields This current difference dlout between the collector currents of the output transistors Q21, Q22 generates a differential output voltage V 0U tp, V ou tm at the output terminals 171, 172 across the resistors R14 and R15. Selecting resistors R14, R15 equal to each other with a resistance R oUt , the differential output voltage Vd 0 the output terminals V ou tp, V ou tm becomes V do ~ V outp ' V outm ~ R4.5 dlout gain ' Vref) A temperature compensated output is achieved when the current source 140 provides a constant current I coπst and the current source 150 provides a temperature compensation current I pta t- Current sources suitable for the constant current source 140 and the temperature compensating source 150 are well known in the art. Substituting for I cout + I cιn> equation 6 becomes V = 77 - 77 - IP"" R<"" (τr . V ) V do ' outp V outm y gain ¥ refj I const In this expression, it is the ratio I ta t Ico ns t that accounts for the desired temperature compensation. Since the input current dl is directly forced onto the input transistors Q19 and Q20 of Fig. 3, the number of error mechanisms as compared to the prior art circuit in Fig. 2(a) is greatly reduced. Additionally, by providing the differential amplifier A2 within the multiplier circuit, the two separate functions of voltage-to-current conversion and current multiplication are merged into one circuit. This greatly improves accuracy and reduces die size (as evident from the reduced component count) as compared to the known configuration of Figs. 2(a), 2(b). While the circuit of Figure 3 is not completely error free, the possible error is reduced as compared to the prior art circuit of Fig. 2. The main source of error arises from any random mismatch occurring during production of the transistors Q16, Q17 of the current mirror 160 and the fact that the collector voltages of these transistors are not equal. The effect of these errors is halved, however, as compared to the prior art circuit of Fig. 2(a), since the current through the current mirror 160 accounts for only half the current difference dl of the input transistors Q19, Q20. The splitting of the current dl is controlled by the current mirror ratio of the current mirror 160. It should be noted that ideally the current dl should be split equally, as any other proportioning only reduces accuracy of the circuit. Figure 4 shows a second embodiment of the invention which further reduces the error of the circuit of Figure 3. Circuit elements corresponding to those of Figure 3 bear the same reference numerals. The circuit of Fig. 4 equalizes the collector voltages of the transistors Q16 and Q17. This is accomplished by replacing the direct base-collector diode connection of the transistor Q17 of Figure 3 by a differential amplifier 280 that fixes the collector voltage of the transistor Ql 7 to the reference voltage V re f, which is the same voltage as found on the collector of the transistor Q16. The differential amplifier 280 for the current mirror 160 is implemented by the bipolar transistors Q14 and Q15 and the current source 181. Transistor Q15 has its base coupled to the collector of the transistor Q17 and its collector coupled to the supply Vcc. Transistor Q14 has its base coupled to receive the reference voltage V ref and its collector coupled to the bases of the transistors Q16 and Q17. The emitters of transistors Q14, Q15 are commonly coupled to and biased by the current source 181 which provides a biasing current 12. Transistor Q14, Q15 and Q17 form a feedback loop which maintains the same voltage at the base of Q15 and the collector of Q 17, as is known in the art. Figure 4 also provides a detailed schematic for the amplifier A2 of Fig. 3. It consists of the transistors Q12 and Q13 that form a differential pair, and a current source 190 which provides a biasing current II for this differential pair. Transistor Q18 establishes the common mode level of the amplifier 130, as is also known in the art. Thus it will be understood that the converter circuits of Figs. 3 and 4 convert a single ended input voltage into a differential signal. The output signal is the differential collector currents of the transistors Q21, Q22. This differential output current provides a voltage drop across the resistors R14, R15 which provides a differential output voltage. This output signal is temperature compensated when the control currents for the input and output cells are I const and I pta t. Coupling the converter circuit of either Figs. 3 or 4 to drive the differential pair of Fig. 1 provides a compact, accurate VGA with a single ended input which produces a temperature compensated differential output current having collector current ratio which is linear-in-db. Such a VGA is useful in numerous applications, and particularly in automatic gain control circuits for radio transceivers, such as in cellular phones. Although preferred embodiments of the present invention have been shown and described, it will be appreciated by those skilled in the art that changes may be made in these embodiments without departing from the principles and spirit of the invention, the scope of which is defined in the claims. For example, those of ordinary skill in the art will appreciate that the current mirror transistors may be Field Effect Transistors (FET's) instead of the bipolar transistors shown. Additionally, while bipolar transistors are shown for the multiplier cell transistors Q19-Q22 because of their exponential gain characteristics, those of ordinary skill in the art will appreciate that for some applications, FET's may be substituted which operate in their sub-threshold region, since in this region FET's also exhibit an exponential gain characteristic. The many features and advantages of the invention are apparent from the detailed specification and it is intended by the appended claims to cover all such features and advantages which fall within the true spirit and scope of the invention. Since numerous modifications and changes will readily occur to those skilled in the art, it is not desired to limit the invention to the exact construction and operation illustrated and described, and accordingly all suitable modifications and equivalents may be resorted to, falling within the scope of the invention.

Claims: CLAIMS: 1) A voltage converting multiplier circuit for converting a single ended voltage to a differential output signal, comprising: an input terminal (110) which receives an input voltage Vg a , n ; a multiplier circuit comprising a differential input cell (120) and a differential output cell (130), each differential cell including an inverting input (121, 131), a non-inverting input (122, 132), an inverting output and a non-inverting output (124, 134), and a control current terminal (125, 135), the inputs of said differential input cell being coupled to respective ones of the inputs of said differential output cell; and a control circuit (A2, R10, 160) coupled to said input terminal and said multiplier circuit and which receives a reference voltage V ref , converts the input voltage to an input current dl proportional to the difference between the reference voltage V ref and the input voltage V ga i n , divides the input current and applies the divided input current to the inverting and non-inverting outputs of said differential input cell such that the inverting and non- inverting outputs of said differential output cell output a differential output current dl 0ut proportional to dl (Lout/Icm), where I cout is a control current applied to said control current terminal of said differential output cell and I c j n is a control current applied to said control current terminal of said differential input cell. 2) A voltage converting multiplier circuit according to claim 1 , further comprising a pair of output devices (R14, R15) each coupled to a respective one of the inverting and non- inverting outputs of said differential output cell to convert the differential output current to a differential output voltage. 3) A voltage converting multiplier circuit according to claim 1 , wherein said control circuit includes an input device (R10) having a resistance Ri n coupled to said input terminal such that said input current dl equals (V re f -V in )/Ri n . 4) A voltage converting multiplier circuit according to claim 3, wherein each of said pair of output resistances (R14, R15) has a resistance Rout, the differential output voltage being equal to (Icou t Ic ι n)(Rou t Rm)(Vref-V ιn ). 5) A voltage converting multiplier circuit according to claim 1, wherein said control circuit includes an input device (RIO) having a resistance, said input device having a first end coupled to said input terminal and a second end, and a differential amplifier (A2) having an inverting input coupled to said second end of said input device, an inverting input which receives the reference voltage, an inverting output coupled to the inverting input of said input differential cell and a non-inverting output coupled to said non-inverting input of said differential input cell, said differential amplifier controlling the input differential cell to maintain a voltage at said second end of said input device equal to V ref . 6) A voltage converting multiplier circuit according to claim 5, further comprising a circuit (Ql 8) which controls the common mode current of said differential amplifier. 7) A voltage converting multiplier circuit according to claim 1 , wherein said control circuit includes a current mirror (160) having an input which together with said inverting output of said input differential cell supplies said input current dl, each of the current mirror input and said inverting output of said differential cell supplying approximately half of said input current dl, and said current mirror having an output coupled to the non-inverting output of said differential input cell and supplying a current of approximately dI/2 thereto. 8) A voltage converting multiplier circuit according to claim 7, wherein said current mirror includes a pair of bipolar transistors (Q16, Q17) each having a collector coupled to a respective one of said inverting and non-inverting outputs of said differential input cell, and further comprising a differential amplifier (280) which equalizes the collector voltages of said current mirror to the reference voltage V re f. 9) A voltage converting multiplier circuit according to claim 1 , wherein each of said differential input cell and said differential output cell comprises a pair of differentially coupled bipolar transistors (Q19, Q20; Q21; Q22), one transistor of each pair of bipolar transistors having a base comprising said inverting input and a collector comprising said inverting output, and the other transistor of each pair of bipolar transistors having a base comprising said non-inverting input and a collector comprising said non-inverting output, and each transistor of a respective said pair of bipolar transistors having an emitter commonly coupled to the respective said control current terminal.

Inventors: ESCHAUZIER RUDOLPHE G, SEREMETA DORIN, ESCHAUZIER, RUDOLPHE, G., SEREMETA, DORIN
Applicants: KONINKL PHILIPS ELECTRONICS NV, PHILIPS SVENSKA AB, KONINKLIJKE PHILIPS ELECTRONICS N.V., PHILIPS AB
Application year: 1999
Main classification: H02M7
IPC codes: G05F3, H03F1, H03F3, H03G3