SEMICONDUCTOR STRUCTURE AND PROCEDURE FOR MINIMISING NON-IDEALITIES

Abstract: The invention relates to a semiconductor structure and a method for minimising non-idealities in a semiconductor structure, in which a drain, a source, a floating gate (102) and at least one input (108) capacitively connected to the floating gate (102) are disposed on a substrate (105) so as to form a nu -MOSFET transistor. According to the invention, a conductive layer insulated from the floating gate (102) and at least partially superimposed on the gate (102) is formed in the semiconductor structure and the conductive layer is connected to a constant potential.

Description: SEMICONDUCTOR STRUCTURE AND PROCEDURE FOR MINIMISING NONIDEALITIES The present invention relates to microelectronics. In particular, the invention concerns a semi- conductor structure and a method for minimising non- idealities in semiconductors. BACKGROUND OF THE INVENTION In prior art, a semiconductor structure is known in which one or more inputs are cpacitively connected to the gate of a MOSFET transistor (Metal Oxide Semiconductor Field Effect Transistor) . In the present publication, components thus formed are referred to with the designation v-MOSFET. These components can be connected together to form more complex assemblies. Fig. 1 presents the circuit diagram and a cross- sectional view of a possible implementation. The basic idea of the v-MOSFET transistor is that the input voltages are summed at the gate of the transistor in accordance with capacitive weighting coefficients. The voltage summed at the gate is given by the equation where φ F is the voltage at the floating gate, Ci is the weighting coefficient (capacitance) of input i and Vi is the voltage at input i. By using different combinations of weighting coefficients and inputs, it is possible to implement many functions, such as electric neurons or A/D and D/A converters. In the v-MOSFET structures presented, a problem is that there are variations and non-idealities in the semiconductor manufacturing process. In addition to the designed inputs, the capacitive coupling be- tween the gate and the substrate causes distortion of the summing. In the manufacturing process of semiconductor circuits, certain parameters change from one process run to the next, e.g. when there are variations in the alignment of manufacturing masks or in layer thickness. The properties of complex components, such as transistors, are determined by the combined effect of several parameters. Thus, for instance, the threshold voltage of a transistor may vary by as much as ten per cent. Fig. 2 illustrates simulation of the effects of process variations on the threshold voltage of a transistor. In the design of complex v-MOSFET structures, it would be desirable to be able to increase the num- ber of inputs to provide as many inputs as possible. Process variations can be reduced by developing the process itself or by lowering the tolerances permitted in the process, but this leads to increased manufacturing costs. It would also preclude the use of known advantageous manufacturing processes. The object of the present invention is to eliminate or at least to significantly reduce the problems described above. A further object of the invention is to disclose a new type of semiconductor structure and a method by which non-idealities due to variations in the IC process as well as internal non- idealities in semiconductors can be minimised by electric means. BRIEF DESCRIPTION OF THE INVENTION The invention concerns a method for minimising non-idealities in a semiconductor structure in which a drain, a source, a floating gate and at least one input are disposed on a substrate, the input being capacitively connected to the floating gate. Said semiconductor structure is preferably a v-MOSFET transistor. According to the invention, a conductive layer insulated from the floating gate and at least partially superimposed on the gate is formed in the semiconductor structure. The conductive layer is connected to a constant potential suitably selected, allowing non-idealities of the semiconductor structure to be minimised. In a preferred embodiment of the invention, an eliminating grid at least partially covering the floating gate is formed from the conductive layer. In this case, the constant potential can be used to eliminate the parasitic substrate capacitance of the floating gate. In a preferred embodiment of the invention, a control grid of the same material with the input is formed from the conductive layer. The control grid is capacitively connected to the floating gate, in a manner corresponding to the input connection. The control grid is preferably formed in the same layer with the input . In a preferred embodiment of the invention, a basin located at least partially under the floating gate is formed from the conductive layer. In a preferred embodiment of the invention, the conductive layer according to the above-described methods is divided into at least two sections so that the potentials of different sections can be controlled independently of each other. The sections can be controlled digitally. The proportions of the sections can also be distributed with a binary weighting. Moreover, the invention concerns a semiconductor structure comprising a substrate with a drain, source, floating gate and at least one input disposed on it, the input being capacitively connected to the floating gate. According to the invention, the semi- conductor structure comprises a conductive layer insulated from the floating gate and at least partially superimposed on the gate. In addition, the conductive layer is connected to a constant potential. A semiconductor structure according to the invention comprises an eliminating grid formed from the semiconductor structure and at least partially extending over the floating gate. A semiconductor structure according to the invention comprises a control grid formed from the conductive layer and made of the same material with the input, said control grid being capacitively connected to the floating gate. The control grid is preferably formed in the same layer with the input. A semiconductor structure according to the invention comprises a basin formed from the conductive layer and disposed at least partially under the floating gate. In certain embodiments, the semiconductor structures described above are implemented by dividing the conductive layer into at least two sections, al- lowing the potentials in different sections to be controlled independently of each other. In a preferred case, different sections are provided with digital control. The proportions of the sections can also be distributed with a binary weighting. The semiconductor structure of the invention can be applied in various implementations, such as A/D converters, digital logic gates, neural network connections, D/A converters or comparators, in which the offset can be electrically corrected. LIST OF ILLUSTRATIONS In the following, the invention will be described by the aid of a few examples of its embodiments with reference to the attached drawing, in which Fig. la presents an example of a circuit diagram for a v-MOSFET transistor; Fig. lb presents a sectional side view of a v-MOSFET transistor provided with an eliminating grid; Fig. lc presents a sectional top view of a v- MOSFET transistor provided with an eliminating grid; Fig. 2 presents the DC transfer function of a simulated inverter with different transistor parameters; Fig. 3a presents an example representing the simulated potential of the floating gate of a v-MOSFET transistor as a function of the voltage of the eliminating grid; Fig. 3b presents the circuit used in the simulation; Fig. 4a presents the DC transfer function of a simulated inverter when the states of the control grids are varied; Fig. 4b presents the circuit used in the simulation; Fig. 5a presents a sectional side view of an- other v-MOSFET structure comprising control grids; Fig. 5b presents a sectional top view of a v- MOSFET structure comprising control grids; Fig. 6 presents a diagram representing a circuit for generating control grid voltages; Fig. 7a presents a sectional side view of a v-MOSFET structure comprising a conductive layer below the floating gate; Fig. 7b presents a sectional top view of a v- MOSFET comprising a conductive layer below the float- ing gate; Fig. 8a presents the DC transfer function of a simulated inverter when the states of the control grids are varied; and Fig. 8b presents the circuit used in the simulation. DETAILED DESCRIPTION OF THE INVENTION Fig. lb shows a side view and Fig. lc a top view of a semiconductor structure according to the invention, presented by way of example. It is to be noted that the dimensions shown in the figures are only one example of an implementation according to the present invention. The semiconductor structure is implemented on a substrate 105. The substrate usually consists of single-crystal silicon. The v-MOSFET transistor comprises an active region 104 and a floating gate 102, which has been formed from a second polysilicon layer. Polysilicon can also be replaced with some other conductive material applicable. The transistor may be an enhancement-type or a depletion-type transistor. Gate insulation 103 is provided between the active region 104 and the gate 102. The floating gate 102 is controlled by control grids 108, which have been formed from the lower polysilicon layer and insulated from the upper polysilicon layer by using e.g. nitride in the manufacturing process. The control grids 108 are insulated from the substrate 105 by a dielectric layer 106 of field oxide. Between the polysilicon layers and the metal layer formed on top of them there is a pro- tecting dielectric layer 101 of silicon dioxide. Elimination of parasitic substrate capacitance can be implemented by processing e.g. a metallic conductor layer onto the floating gate 102 and forming an eliminating grid 107 from this layer. The eliminat- ing grid 107 can also be disposed below the floating gate 102. The eliminating grid is insulated from the floating gate by an insulating layer 101. According to the invention, a constant potential is applied to the eliminating grid 107. Fig. 3 illustrates a simulation arrangement in which the voltage of the eliminating grid 107 is varied while at the same time applying a constant voltage, e.g. V DD /2, to the main inputs 108. It can be seen from the figure that, with this structure, when the control voltage is ,10 V, the floating gate voltage V (FG) equals V DD /2, in other words, the effect of para- sitic substrate capacitance has been completely eliminated. Due to other non-idealities in the semiconductor, it is not necessarily appropriate trying to achieve complete compensation of substrate capacitance by this method. In some non-critical applications, sufficient compensation can be accomplished by connecting the eliminating grid 107 to the operating voltage. In v-MOSFET circuits, the non-idealities de- scribed in the preamble can also be cancelled by using a circuit as illustrated in Fig. 4. A cross-section of the structure implemented in this case is presented in Fig. 5. In addition to the main inputs 108, the structure comprises control grids 109 formed in the lower polysilicon layer. The order of the polysilicon layers relative to each other is of no importance as regards the invention; the essential point is that capacitive coupling is provided between the control grids 109 and the floating gate 102. In conjunction with the same structure, an eliminating grid 107 can also be used. Control voltages, which may be digital voltages, are applied to the control grids 109. For the control grids 109, it is possible to select weighting coefficients [ ] capacitances with e.g. binary weighting Ci oc 2 i_1 (i = 1, 2,..., n) . In this case, by using n control grids 109, n 2 different base levels are obtained, regardless of the voltages at the main inputs 108. Fig. 4a illustrates a simulation arrangement with three control grids 109 to which all possible states are connected in turn while a ramp voltage is applied to the main inputs 108. The number of control grids 109 required and their total capacitance are de- termined by the desired control accuracy and the technology used. In the example simulation, the ratio between the total coupling capacitance of the inputs 108 and the sum of the capacitances of the control grids 109 is 10/1. The smallest voltage change occurring at the floating gate 102 is obtained from the equation: where the superscript c means control grid, n is the number of main inputs, C c χ is the lowest capaci- tance of the control grids and m is the number of control grids. The largest voltage change is obtained from the equation: Φ "Femax = In the above equations, substrate capacitance and the effect of a possible eliminating grid 107 are omitted. This solution provides the advantage of allowing the use of digital control. A digital control signal can be generated within the microcircuit e.g. using a circuit as shown in Fig. 6. Using an accurate comparator and logic, a signal for controlling the control grids 109 is defined that will bring the output of the v-MOSFET circuit as close to the desired level as possible. With a control sequence generated, several v-MOSFET circuits can be controlled as the variations in process parameters between different parts of the same microcircuit are small. Thus, using this method, regulation of microcircuits containing many functions of similar nature, such as neural net- work circuits, can be implemented with a relatively small increase in surface area. As the price of micro- circuits is directly proportional to area, consider- able advantages are achieved for a small increase in price. In an embodiment, corresponding digital control is implemented for an eliminating grid 107, in which case the eliminating grid 107 processed onto the floating gate 102 is divided into several sections, in which the control is implemented. Non-idealities in v-MOSFET circuits can also be compensated by forming a conductive layer, e.g. an n-type basin 110 connected to a constant potential, below the floating gate 102. Fig. 7a - b present a schematic view of a possible structure. Connected to the basin 110 via a contact 111 is a piece of conductor metal 112 to apply a constant potential to the ba- sin 110. In this case, the potential of the floating gate 102 will be where φ F is the floating gate voltage, C x is the weighting coefficient (capacitance) of input i, and V x is the voltage at input i. In the above equation, the potential of the conductor below the floating gate 102 and the weighting coefficient have the subscript 0. In typical IC technology, the capacitance ratio of an (actual) capacitor to be processed is typically 5 - 20. When an analogue control voltage (V a ) having a magnitude such that V ss < V a < V DD is used, the effects of process variations on MOSFET transistors can be almost completely eliminated. Fig. 8a presents a simulation diagram with typical transis- tor parameters, with a constant voltage, e.g. V DD /2, applied to the main inputs and a ramp voltage applied to the controlling n-basin 110. In another simulation arrangement, the transistor parameters have been changed while keeping the same input voltages. From Fig. 8a it can be seen that, regardless of the transistor parameters, a control voltage is found that allows the desired output voltage to be achieved. It is possible to implement digital control as described above for the lower basin 110 as well. In this case, the basin below the floating gate 102 is divided into several sections and a separate control potential is applied to each section. The invention is not restricted to the exam- pies of its embodiments described above, but many variations are possible within the scope of the inventive idea defined in the claims

Claims: CLAIMS 1. Method for minimising non-idealities in a semiconductor structure, in which a drain a source a floating gate (102) ; and at least one input (108) are disposed on a substrate (105) , said input being capacitively connected to said floating gate (102) , characteri sed in that a conductive layer is formed in the semiconductor structure, which layer is insulated from the floating gate (102) and at least partially superimposed on the gate (102) ; and the conductive layer is connected to a constant potential. 2. Method as defined in claim 1, characterised in that an eliminating grid (107) extending at least partially over the floating gate is formed from the conductive layer. 3. Method as defined in claim 1, characterised in that a control grid (109) of the same material with the input (108) is formed from the conductive layer; and the control grid (109) is capacitively connected to the floating gate (102) . 4. Method as defined in claim 3, characterised in that the control grid (109) is formed in the same layer with the input (108) . 5. Method as defined in claim 1, characterised in that a basin (110) disposed at least partially under the floating gate (102) is formed from the conductive layer. 6. Method as defined in any one of the pre- ceding claims 1 - 5, characterised in that the conductive layer is divided into at least two sec- tions so that the potentials of different sections can be controlled independently of each other. 7. Method as ^ defined in claim 6, characterised in that the sections are controlled digitally. 8. Method as defined in claim 6 or 7, characterised in that the proportions of the sections are distributed with a binary weighting. 9. Semiconductor structure having a substrate (105) on which are arranged: a drain; a source; a floating gate (102); and at least one input (108) capacitively connected to the floating gate (102) , characteri sed in that a conductive layer insulated from the floating gate (102) and at least partially superimposed on the gate (102) has been formed in the semiconductor; and the conductive layer is connected to a constant potential . 10. Semiconductor structure as defined in claim 9, characterised in that it comprises an eliminating grid (107) formed from the conductive layer and at least partially extending over the floating gate (102) . 11. Semiconductor structure as defined in claim 9, characterised in that it comprises a control grid (109) formed from the conductive layer, said control grid being made of the same material with the input (108) and capacitively connected to the floating gate (102) . 12. Semiconductor structure as defined in claim 11, characteri sed in that the control grid (109) is formed in the same layer with the input (108) . 13. Semiconductor structure as defined in claim 9, characterised in that it comprises a basin (106) formed from the conductive layer and disposed at least partially below the floating gate (102) . 14. Semiconductor structure as defined in any one of the preceding claims 9 - 13, characterised in that the conductive layer is divided into at least two sections so that the potentials of different sections can be controlled independently of each other. 15. Semiconductor structure as defined in claim 14, characterised in that the sections are provided with digital control. 16. Semiconductor structure as defined in claim 14 or 15, characterised in that the proportions of the sections are distributed with a binary weighting. 17. Semiconductor structure as defined in any one of claims 9 - 16, characterised in that the semiconductor structure is comprised in an A/D converter. 18. Semiconductor structure as defined in any one of claims 9 - 17, characterised in that the semiconductor structure is comprised in a digital logic gate. 19. Semiconductor structure as defined in any one of claims 9 - 18, characterised in that the semiconductor structure is comprised in a neural network circuit. 20. Semiconductor structure as defined in any one of claims 9 - 19, characterised in that the semiconductor structure is comprised in a D/A converter. 21. Semiconductor structure as defined in any one of claims 9 - 20, characterised in that the semiconductor structure is comprised in a comparator.

Inventors: RANTALA ARTO, RANTALA, ARTO
Applicants: RANTALA ARTO, VALTION TEKNILLINEN, RANTALA, ARTO, VALTION TEKNILLINEN TUTKIMUSKESKUS VTT
Application year: 1999
Main classification: H01L29
IPC codes: G11C27, H01L27, H01L29