PROCESSOR BRIDGE WITH DISSIMILAR DATA ACCESS

Abstract: A bridge for a multi-processor system includes bus interfaces for connection to an I/O bus of a first processing set, an I/O bus of a second processing set and a device bus. A bridge control mechanism is operable to compare address and data phases of I/O accesses by the first and second processing sets. A direct memory access mechanism is operable to initiate a direct memory access operation to read from a corresponding location in each processor set into a respective dissimilar data register associated with each processing set. The bridge control mechanism is operable during the direct memory access operation to disregard differences in the data phase for the dissimilar data write access. As a result it is possible to transfer dissimilar data from the processors into the bridge in a combined (lockstep comparison) mode. In a subsequent phase the bridge control mechanism responds to a read destination address supplied in common by the first and second processing sets for a dissimilar data read access to supply data read from a determined one of the dissimilar data registers to the first and second processing sets. In this manner the data from one processing set can be copied to the other processing set while in a combined mode.

Description: TITLE: PROCESSOR BRIDGE WITH DISSIMILAR DATA ACCESS BACKGROUND OF THE INVENTION This invention relates to a multi-processor computer system including first and second processing sets (each of which may compπse one or more processors) which communicate with an I/O device bus The application finds particular application to fault tolerant computer systems where two or more piocessor sets need to communicate with an I O device bus in lockstep with provision for identifying lockstep enors in order to identify faulty operation of the system as a whole It has been proposed to identify lockstep errors by comparing I/O operations output by the processing sets This is a reliable method as long as the outputs from the processor sets are deterministic, that is as long as long as the outputs from the processing sets are going to be identical when the processors are operating correctly This will normally be the case when the processors are operating synchronously under the control of a common clock However, it can be that some events may not be wholly deterministic An example of this is where the individual piocessmg sets each mclude a real time clock which are not synchronized If the real time clocks are sampled by the respective processmg sets, then a different sample may be generated m the respective processmg sets For example, if the sample is taken at just the time at which the clocks are mcremented, one processing set may take the sample just before the mcrement and the other may take the sample just after the mcrement Where these different values are output by the processing sets and are evaluated by a comparator check for lockstep operation, this would be determined as a lockstep error A further problem is that such values may be operated on by the individual processing sets which could lead to further divergence of the processmg sets These problems have had the effect of limiting the design of lockstep systems to avoid the danger of potentially non-deterministic events Accordingly, an aim of the invention is to overcome or at least mitigate these pioblems SUMMARY OF THE INVENTION Particular and preferred aspects of the invention are set out m the accompanymg independent and dependent claims Combinations of features from the dependent claims may be combined with features of the independent claims as appropπate and not merely as explicitly set out m the claims In accordance with one aspect of the invention, there is provided a bridge for a multi-processor system 1 he bi idge mcludes a bus interfaces for connection to an I O bus of a first processing set, an I/O bus of a second piocessmg set and a device bus A bridge control mechanism is operable to compare address and data phases of I/O accesses by the first and second processing sets A direct memory access mechanism is operable to initiate a direct memory access operation to read from a corresponding location m each processing set mto a respective dissimilar data register associated with each processing set The bridge control mechanism is operable duπng the direct memory access operation to disregard differences in the data for the dissunilar data direct memory access As a result it is possible to transfer dissimilar data from the processors into the bridge in a combined (lockstep comparison) mode An example of such data is non-deterministic data (for example relating to a real time clock) In a subsequent phase, the processing sets can then read m common a selected one of the dissimilar data registers, whereby it is possible to transfer the dissimilar data from one processor to the other without causing a lockstep error to be detected The bridge control mechanism can be operable to disregard the data and the associated data parity for the DMA access It should be noted that the bus interfaces referenced above need not be separate components of the budge, but may be incorporated in other components of the bridge, and may mdeed be simply connections for the lines of the buses concerned A direct memory access control register can hold an addresses of the processing set location to be read by the DMA access and the size of the read to carry this out This can form one of a set of control and status registeis in the bridge The bridge control mechanism c?n compnse a comparator connected to the first and second processor bus interfaces, the comparator bemg configured to be operable to detect differences between signals on the I/O buses of the first and second processmg sets as indicative of a lockstep error m a combmed mode The bridge contiol mechanism can be operable to block the output of the comparator during direct memory access Alternatively, or in addition, the bridge control mechanism can be operable to inhibit the operation of the comparator In a subsequent phase, the bndge control mechanism can be configured to be operable to respond to a lead destination address supplied in common by the first and second processing sets for a dissimilar data read access to supply data read from a determined one of the dissimilar data registers to the first and second piocessmg sets In this manner the data from one processmg set can be copied to the other processing set while in a combined mode The read destmation address supplied in common by the first and second processmg sets can determine the dissimilar data register from which data is read The dissimilar data registers can be configured as hardware registers m the bridge Alternatively, they can be configured in random access memory in the bridge The bridge can include at least one further processor bus interface for connection to an I/O bus of a fuither processmg set In accordance with another aspect of the invention, there is provided a computer system comprising a first piocessmg set havmg an I/O bus, a second processing set havmg an I/O bus, a device bus and a bridge as desuibed above Each processmg set comprises at least one processor, memory and a processing set I/O bus onti oiler In accordance with a further aspect of the invention there is provided a method of operating a computer system as described above, the method compπsing comparing address and data phases of I/O accesses from the first and second processmg sets for detei mining lockstep operation of the processmg sets, initiating a direct memory access operation to read from a corresponding location in each processor set into the associated dissimilar data register, and dining the direct memory access operation disregarding differences in the data phase for the dissimilar data write access BRIEF DESCRIPTION OF THE DRAWINGS Exemplary embodiments of the present mvention will be descπbed hereinafter, by way of example only, with reterence to the accompanymg drawmgs in which like reference signs relate to like elements and m which Figure 1 is a schematic overview of a fault tolerant computer system incorporating an embodiment of the Figure 2 is a schematic overview of a specific implementation of a system based on that of Figure 1 , Figure 3 is a schematic representation of one implementation of a processmg set, Figure 4 is a schematic representation of another example of a processmg set, Figure 5 is a schematic representation of a further processmg set, Figure 6 is a schematic block diagram of an embodiment of a bndge for the system of Figure 1 , Figure 7 is a schematic block diagram of storage for the bridge of Figure 6, Figure 8 is a schematic block diagram of control logic of the bndge of Figure 6, Figure 9 is a schematic representation of a routmg matrix of the bndge of Figure 6, Figure 10 is an example implementation of the bndge of Figure 6, Figure 11 is a state diagram illustrating operational states of the bndge of Figure 6, Figure 12 is a flow diagram illustrating stages m the operation of the bndge of Figure 6, Figure 13 is a detail of a stage of operation from Figure 12, Figure 14 illustrates the posting of I/O cycles m the system of Figure 1, Figure 15 illustrates the data stored m a posted wnte buffer, Figure 16 is a schemattc representation of a slot response register, Figure 17 illustrates a dissimilar data direct memory access mechanism, Figure 18 illustrates a modification to Figure 17, Figure 19 illustrates a dissimilar data read stage, Figure 20 illustrates an alternative dissimilar data read stage, Figure 21 is a flow diagram summansing the operation of a dissimilar data direct memory access mechanism, Figure 22 is a schematic block diagram explammg arbitration within the system of Figure 1 , Figure 23 is a state diagram illustrating the operation of a device bus arbiter, Figure 24 is a state diagram illustrating the operation of a bndge arbiter, Figure 25 is a timing diagram for PCI signals, Figure 26 is a schematic diagram illustrating the operation of the bndge of Figure 6 for direct memory access, Figure 27 is a flow diagram illustrating a direct memory access method in the bndge of Figure 6, and Figure 28 is a flow diagram of a re-integration process mcludmg the monitoring of a dirty RAM DESCRIPTION OF THE PREFERRED EMBODIMENTS Figure 1 is a schematic overview of a fault tolerant computing system 10 comprising a plurality of CPLsets (processmg sets) 14 and 16 and a bridge 12 As shown in Figure 1, there are two processmg sets 14 and 16, although in other embodiments there may be three or more processing sets The bridge 12 forms an inteiface between the processmg sets and I/O devices such as devices 28, 29, 30, 31 and 32 In this document, the term "processing set" is used to denote a group of one or more processors, possibly including memory, which output and receive common outputs and inputs It should be noted that the alternative term mentioned above, "CPUset", could be used mstead, and that these terms could be used mterchangeably throughout this document Also, it should be noted that the term "bridge" is used to denote any device, apparatus or anangement suitable for interconnecting two or more buses of the same or different types The first processing set 14 is connected to the bridge 12 via a first processmg set I/O bus (PA bus) 24, in the present instance a Penpheral Component Interconnect (PCI) bus The second processmg set 16 is connected to the bridge 12 via a second processing set I/O bus (PB bus) 26 of the same type as the PA bus 24 (l e here a PCI bus) The I O devices are connected to the bridge 12 via a device I/O bus (D bus) 22, m the piesent instance also a PCI bus Although, m the particular example descnbed, the buses 22, 24 and 26 are all PCI buses, this is merely by w ay of example, and in other embodiments other bus protocols may be used and the D-bus 22 may have a ditteient protocol from that of the PA bus and the PB bus (P buses) 24 and 26 The processmg sets 14 and 16 and the bndge 12 are operable in synchronism under the control of a common clock 20, which is connected thereto by clock signal lmes 21 Some of the devices mcludmg an Ethernet (E-NET) interface 28 and a Small Computer System Inteiface (SCSI) mterface 29 are permanently connected to the device bus 22, but other I/O devices such as I/O devices 30, 31 and 32 can be hot insertable into individual switched slots 33, 34 and 35 Dynamic field effect tiansistor (FET) switchmg can be provided for the slots 33, 34 and 35 to enable hot msertability of the devices such as devices 30, 31 and 32 The provision of the FETs enables an increase in the length of the D bus 22 as only those devices which are active are switched on, reducing the effective total bus length It will be appieciated that the number of I/O devices which may be connected to the D bus 22, and the number of slots piovided for them, can be adjusted accordmg to a particular implementation m accordance with specific design lequirements Figure 2 is a schematic overview of a particular implementation of a fault tolerant computer employing a budge structure of the type illustrated in Figure 1 In Figure 2, the fault tolerant computer system includes a pluia ty (here four) of bndges 12 on first and second I/O motherboards (MB 40 and MB 42) order to increase the number of I/O devices which may be connected and also to improve reliability and redundancy Thus, in the embodiment shown m Figure 2, two processmg sets 14 and 16 are each provided on a respective processing set boaid 44 and 46, with the processing set boards 44 and 46 'bridging' the I/O motherboards MB 40 and MB 42 A first, master clock source 20A is mounted on the first motherboard 40 and a second, slave clock source 20B is mounted on the second motherboard 42 Clock signals are supplied to the processing set boards 44 and 46 via respective connections (not shown in Figure 2) First and second bridges 12 1 and 12 2 are mounted on the first I/O motherboard 40 The first bridge 12 1 is connected to the processing sets 14 and 16 by P buses 24 1 and 26 1, respectively Similarly, the second budge 12 2 is connected to the processing sets 14 and 16 by P buses 24 2 and 26 2, respectively The bridge 12 1 is connected to an I/O databus (D bus) 22 1 and the bridge 12 2 is connected to an I/O databus (D bus) 22 2 Third and fourth bridges 12 3 and 12 4 are mounted on the second I/O motherboard 42 The bridge 12 3 is connected to the processing sets 14 and 16 by P buses 24 3 and 26 3, respectively Similarly, the bridge 4 is ι.onnected to the processmg sets 14 and 16 by P buses 24 4 and 26 4, respectively The bridge 12 3 is connected to an I/O databus (D bus) 22 3 and the bridge 12 4 is connected to an I/O databus (D bus) 22 4 It can be seen that the anangement shown in Figure 2 can enable a large number of I/O devices to be connected to the two processing sets 14 and 16 via the D buses 22 1, 22 2, 22 3 and 22 4 for either increasing the lange of I/O devices available, or providing a higher degree of redundancy, or both Figure 3 is a schematic overview of one possible configuration of a processing set, such as the piocessmg set 14 of Figure 1 The processmg set 16 could have the same configuration In Figure 3, a plurality of piocessors (here four) 52 are connected by one or more buses 54 to a processing set bus controller 50 As shown in Figure 3, one or more processing set output buses 24 are connected to the processing set bus controller 50, each processing set output bus 24 being connected to a respective bndge 12 For example, in the anangement of Figure 1, only one processing set I/O bus (P bus) 24 would be provided, whereas in the arrangement of Figure 2, four such processing set I/O buses (P buses) 24 would be provided In the processing bet 14 shown m Figure 3, individual processors operate using the common memory 56, and receive inputs and piovide outputs on the common P bus(es) 24 Figure 4 is an alternative configuration of a processmg set, such as the processing set 14 of Figure 1 Here a plurality of processor/memory groups 61 are connected to a common internal bus 64 Each piocessor/memory group 61 includes one or more processors 62 and associated memory 66 connected to a internal group bus 63 An mterface 65 connects the internal group bus 63 to the common internal bus 64 Accordingly, in the anangement shown in Figure 4, individual processing groups, with each of the processors 62 and associated memory 66 are connected via a common internal bus 64 to a processing set bus controller 60 The mtei faces 65 enable a processor 62 of one processing group to operate not only on the data m its local memoiy 66, but also m the memory of another processing group 61 withm the processmg set 14 The piocessmg set bus controller 60 provides a common interface between the common internal bus 64 and the piocessmg set I O bus(es) (P bus(es)) 24 connected to the bndge(s) 12 It should be noted that although only two piocessmg groups 61 are shown in Figure 4, it will be appreciated that such a structure is not limited to this numbei of processing groups Figure 5 illustrates an alternative configuration of a processing set, such as the processing set 14 of i iguie 1 Here a simple processing set includes a single processor 72 and associated memory 76 connected via a common bus 74 to a processmg set bus controller 70 The processing set bus controller 70 provides an inteiface between the internal bus 74 and the processmg set I/O bus(es) (P bus(es)) 24 for connection to the bndge(s) 12 Accordmgly, it will be appreciated from Figures 3, 4 and 5 that the processmg set may have many ditteient forms and that the particular choice of a particular processmg set structure can be made on the basis of the processing requirement of a particular application and the degree of redundancy required In the following descπption, it is assumed that the processing sets 14 and 16 referred to have a structure as shown in Figure 3, although it will be appreciated that another form of processing set could be provided The bndge(s) 12 are operable in a number of operating modes These modes of operation will be described in more detail later. However, to assist in a general understandmg of the structure of the bridge, the two operating modes will be briefly summarized here. In a first, combined mode, a bndge 12 is operable to mute addiesses and data between the processing sets 14 and 16 (via the PA and PB buses 24 and 26, respectively) and the devices (via the D bus 22). In this combined mode, I O cycles generated by the processing sets 14 and 16 are compared to ensure that both processmg sets are operating correctly Companson failures force the bridge 12 mto an error limiting mode (EState) m which device I/O is prevented and diagnostic information is collected. In the second, split mode, the bridge 12 routes and arbitrates addresses and data from one ot the processmg sets 14 and 16 onto the D bus 22 and/or onto the other one of the processing sets 16 and 14 respectively In this mode of operation, the processmg sets 14 and 16 are not synchronized and no I/O co paiisons are made. DMA operations are also permitted m both modes. As mentioned above, the different modes of operation, mcludmg the combmed and split modes, will be descnbed m more detail later However, there now follows a descnption of the basic structure of an example of the bndge 12 Figure 6 is a schematic functional overview of the bndge 12 of Figure 1 First and second processing set I/O bus interfaces, PA bus mterface 84 and PB bus interface 86, are connected to the PA and PB buses 24 and 26, respectively. A device I/O bus mterface, D bus mterface 82, is connected to the D bus 22 It should be noted that the PA, PB and D bus mterfaces need not be configured as separate elements but could be mcorpoiated in other elements of the bndge. Accordmgly, withm the context of this document, where a leferences is made to a bus mterface, this does not require the presence of a specific separate component, but rather the capability of the bridge to connect to the bus concerned, for example by means of physical or logical budge connections for the lmes of the buses concerned Routing (heremafter termed a routing matrix) 80 is connected via a first internal path 94 to the PA bus liiteitace 84 and via a second internal path 96 to the PB bus interface 86 The routing matrix 80 is further connected via a third internal path 92 to the D bus interface 82. The routmg matπx 80 is thereby able to provide I/O bus transaction routmg in both directions between the PA and PB bus interfaces 84 and 86 It is also able to piovide routing in both directions between one or both of the PA and PB bus mterfaces and the D bus interface 82 The routing matrix 80 is connected via a further internal path 100 to storage control logic 90. The storage control logic 90 controls access to bndge registers 110 and to a random access memory (SRAM) 126. The loutmg matrix 80 is therefore also operable to provide routmg m both directions between the PA, PB and D bus mtei faces 84, 86 and 82 and the storage control logic 90 The routing matnx 80 is controlled by bridge control logic 88 over control paths 98 and 99. The bridge control logic 88 is responsive to control signals, data and addresses on internal paths 93, 95 and 97, and also to clock signals on the clock lme(s) 21. In the embodiment of the invention, each of the P buses (PA bus 24 and PB bus 26) operates under a PCI piotocol The processmg set bus controllers 50 (see Figure 3) also operate under the PCI protocol Accoidingly, the PA and PB bus interfaces 84 and 86 each provide all the functionality required for a compatible interface providing both master and slave operation for data transferred to and from the D bus 22 or internal memories and registers of the bridge in the storage subsystem 90 The bus interfaces 84 and 86 can piovide diagnostic information to internal bridge status registers m the storage subsystem 90 on transition of the budge to an error state (EState) or on detection of an I/O error The device bus interface 82 performs all the functionality required for a PCI compliant master and slave interface for transferring data to and from one of the PA and PB buses 84 and 86. The D bus 82 is operable during direct memory access (DMA) transfers to provide diagnostic information to internal status registers in the storage subsystem 90 of the bridge on transition to an EState or on detection of an I/O error. Figure 7 illustrates in more detail the bridge registers 110 and the SRAM 124. The storage control logic 1 10 is connected via a path (e.g. a bus) 112 to a number of register components 114, 116, 118, 120. The storage control logic is also connected via a path (e.g. a bus) 128 to the SRAM 126 in which a posted write buffer component 122 and a dirty RAM component 124 are mapped. Although a particular configuration of the components 114, 116, 118, 120, 122 and 124 is shown in Figure 7, these components may be configured in oiher ways, with other components defined as regions of a common memory. As shown in Figure 7, the posted write buffer 122 and the dirty RAM 124 are mapped to different regions of the SRAM memory 126, whereas the registers 114, 116, 118 and 120 are configured as separate from the SRAM memory. Control and status registers (CSRs) 114 form internal registers which allow the control of various operating modes of the bridge, allow the capture of diagnostic information for an EState and for I O enors, and control processing set access to PCI slots and devices connected to the D bus 22. These registers are set by signals from the routing matrix 80. Dissimilar data registers (DDRs) 116 provide locations for containing dissimilar data for different processing sets to enable non-deterministic data events to be handled. These registers are set by signals from the PA and PB buses. A DMA engine in the bridge enables dissimilar data to be read from a common location in the processing sets to the DDRs 116, while disabling a comparator for comparing the I/O cycles on the PA and PB buses.. At least one DDR is provided each processing set. A selected one of the DDRs can then be read in-sync by the processing sets 14 and 16. The DDRs thus provide a mechanism enabling a location to be reflected from one processing set (14/16) to another (16/14). Slot response registers (SRRs) 118 determine ownership of device slots on the D bus 22 and to allow DMA to be routed to the appropriate processing set(s). These registers are linked to address decode logic. Disconnect registers 120 are used for the storage of data phases of an I O cycle which is aborted and data is trapped in the bridge. The disconnect registers 120 receive all data queued in the bridge when a target device disconnects a transaction, or as the EState is detected. These registers are connected to the routing matrix 80. The routing matrix can queue up to three data words and byte enables. Provided the initial addresses are voted as being equal, address target controllers derive addresses which increment as data is exchanged between the bridge and the destination (or target). Where a writer (for example a processor I/O write, or a DVMA (D bus to P bus access)) is writing data to a target, this data can be caught in the bridge when an error occurs. Accordingly, this data is stored in the disconnect registers 120 when an error occurs. These disconnect registers can then be accessed on recovery from an EState to recover the data associated with the write or read cycle which was in progress when the EState was initiated. Although shown separately, the DDRs 116, the SRRs 118 and the disconnect registers may form an integral part of the CSRs 114. EState and error CSRs 114 provided for the capture of a failing read or write cycle on the P buses 24 and 26 with an indication of the failing datum Following a move to an EState, all of the writes initiated to the P buses aie logged in the posted write buffer 122 These may be other writes that have been posted in the piocessmg set bus controllers 50, or which may be initiated by software before an EState interrupt causes the piocessors to stop carrying out writes to the P buses 24 and 26 A dirty RAM 124 is used to mdicate which pages of the mam memory 56 of the processing sets 14 and 16 hav e been modified by direct memory access (DMA) transactions from one or more devices on the D bus 22 Each page (e g each 8K page) is marked by a single bit in the dirty RAM 124 which is set when a DMA write occuis and can be cleared by a read and clear cycle initiated on the dirty RAM 124 by a processor 52 of a pi ocessmg set 14 and 16 The dirty RAM 124 and the posted write buffer 118 may both be mapped into the memory 124 in the budge 12 This memory space can be accessed during normal read and write cycles for testing purposes Figure 8 is a schematic functional overview of the bridge control logic 88 shown in Figure 6 All of the devices connected to the D bus 22 are addressed geographically Accordingly, the bridge cames out decodmg necessary to enable the isolating FETs for each slot before an access to those slots is initiated The address decodmg performed by the address decode logic 136 and 138 essentially permits four basic access types - an out-of-sync access (I e not m the combined mode) by one processing set (e g processmg set 14 of Figuie 1) to the other processmg set (e g processing set 16 of Figure 1), in which case the access is routed from the PA bus interface 84 to the PB bus interface 86, - an access by one of the processing sets 14 and 16 in the split mode, or both processing sets 14 and 16 in the combined mode to an I/O device on the D bus 22, in which case the access is routed via the D bus inteiface 82, a DMA access by a device on the D bus 22 to one or both of the processmg sets 14 and 16, which w ould be directed to both processing sets 14 and 16 in the combined mode, or to the relevant processing set 14 oi 16 it out-of-sync, and if in a split mode to a processing set 14 or 16 which owns a slot in which the device is located, and - a PCI configuration access to devices in I O slots As mentioned above, geographic addressing is employed Thus, for example, slot 0 on motherboard A has the same address when referred to by processmg set 14 or by processing set 16 Geographic addressing is used m combmation with the PCI slot FET switchmg During a onf iguiation access mentioned above, separate device select signals are provided for devices which are not I E 1 isolated A single device select signal can be provided for the switched PCI slots as the FET signals can be used to enable a correct card Separate FET switch lines are provided to each slot for separately switching the FETs for the slots The SRRs 118, which could be incorporated m the CSR registers 114, are associated with the address decode functions The SRRs 118 serve m a number of different roles which will be descnbed in more detail latei However, some of the roles are summanzed here In a combmed mode, each slot may be disabled so that writes are simply acknowledged without any tiansaction occurring on the device bus 22, whereby the data is lost Reads will return meaningless data, once again without causmg a transaction on the device board. In the split mode, each slot can be in one of three states. The states are: - Not owned; - Owned by processing set A 14; - Owned by processing set B 16. A slot that is not owned by a processing set 14 or 16 making an access (this includes not owned or unowned slots) cannot be accessed. Accordingly, such an access is aborted. When a processmg set 14 or 16 is powered off, all slots owned by it move to the un-owned state. A piocessmg set 14 or 16 can only claim an un-owned slot, it cannot wrest ownership away from another piocessmg set This can only be done by powenng off the other processmg set, or by getting the other piocessmg set to relinquish ownership. The ownership bits are assessable and settable while m the combmed mode, but have no effect until a split state is entered. This allows the configuration of a split system to be determined while still in the combined mode. Each PCI device is allocated an area of the processmg set address map. The top bits of the address are determined by the PCI slot. Where a device carries out DMA, the bndge is able to check that the device is using the conect address because a D bus arbiter informs the bridge which device is using the bus at a particular time If a device access is a processing set address which is not valid for it, then the device access will be ignoied It should be noted that an address presented by a device will be a virtual address which would be tianslated by an I/O memory management unit m the processing set bus controller 50 to an actual memory addiess The addresses output by the address decoders are passed via the initiator and target controllers 138 and 140 to the routing matnx 80 via the lmes 98 under control of a bridge controller 132 and an arbiter 134 An arbiter 134 is operable in various different modes to arbitrate for use of the bridge on a first-come- fnst-seiv ed basis usmg conventional PCI bus signals on the P and D buses. In a combined mode, the arbiter 134 is operable to arbitrate between the in-sync processing sets 14 and 16 and any initiators on the device bus 22 for use of the bridge 12 Possible scenarios are - processing set access to the device bus 22; - processing set access to internal registers in the bridge 12, - Device access to the processing set memory 56. In split mode, both processing sets 14 and 16 must arbitrate the use of the bridge and thus access to the device bus 22 and internal bridge registers (e.g CSR registers 114). The bridge 12 must also contend with lmtiatois on the device bus 22 for use of that device bus 22. Each slot on the device bus has an arbitration enable bit associated with it. These arbitration enable bits aie cleared after reset and must be set to allow a slot to request a bus. When a device on the device bus 22 is suspected of providmg an I/O error, the arbitration enable bit for that device is automatically reset by the A PCI bus interface in the processing set bus controller(s) 50 expects to be the master bus controller toi the P bus concerned, that is it contams the PCI bus arbiter for the PA or PB bus to which it is connected The budge 12 cannot directly control access to the PA and PB buses 24 and 26 The bridge 12 competes for access to the PA or PB bus with the processing set on the bus concerned under the control of the bus controller "IO on the bus concerned Also shown in Figure 8 is a comparator 130 and a bndge controller 132 The comparator 130 is opeiable to compare I/O cycles from the processing sets 14 and 16 to determine any out-of-sync events On deteimimng an out-of-sync event, the comparator 130 is operable to cause the bridge controller 132 to activate an EState tor analysis of the out-of-sync event and possible recovery therefrom Tigure 9 is a schematic functional overview of the routing matnx 80 The routing matrix 80 comprises a multiplexer 143 which is responsive to initiator control signals 98 tiom the initiator controller 138 of Figure 8 to select one of the PA bus path 94 , PB bus path 96, D bus path 92 an internal bus path 100 or a dissimilar data direct memory access path 93 as the current input to the routing Separate output buffers 144, 145, 146 and 147 are provided for output to each of the paths 94, 96, 92 and 100 with those buffers being selectively enabled by signals 99 from the target controller 140 of Figure 8 Betw een the multiplexer and the buffers 144-147 signals are held m a buffer 149 In the present embodiment thiee cycles of data for an I/O cycle will be held in the pipeline represented by the multiplexer 143, the buffer 149 and the buffers 144 In Figures 6 to 9 a functional descnption of elements of the bridge has been given Figure 10 is a si- hematic representation of a physical configuration of the bridge in which the bridge control logic 88, the stoiagc control logic 90 and the bridge registers 110 are implemented m a first field programmable gate array (1 PGA) 89 the routing matnx 80 is implemented in further FPGAs 80 1 and 80 2 and the SRAM 126 is implemented as one or more separate SRAMs addressed by a address control lines 127 The bus interfaces 82, 84 and 86 shown in Figure 6 are not separate elements, but are integrated in the FPGAs 80 1, 80 2 and 89 Two 1 PG <\s 80 1 and 80 2 are used for the upper 32 bits 32-63 of a 64 bit PCI bus and the lower 32 bits 0-31 of the 64 bit PCI bus It will be appreciated that a single FPGA could be employed for the routing matrix 80 where the necessary logic can be accommodated within the device Indeed, where a FPGA of sufficient capacity is available the bridge control logic, storage control logic and the bridge registers could be incorporated in the same 1 PGA as the routmg matrix Indeed many other configurations may be envisaged, and indeed technology othei than FPGAs, for example one or more Application Specific Integrated Circuits (ASICs) may be employed As shown in Figure 10, the FPGAs 89, 80 1 and 80 2 and the SRAM 126 are connected via internal bus paths 85 and path control lines 87 Figure 11 is a transition diagram illustrating in more detail the various operating modes of the bridge T e budge operation can be divided into three basic modes, namely an error state (EState) mode 150, a split state mode 156 and a combined state mode 158 The EState mode 150 can be further divided mto 2 states After initial resetting on powermg up the bridge, or following an out-of sync event, the bridge is in this initial EState 152 In this state, all writes are stored m the posted write buffer 120 and reads from the internal budge legisters (e g , the CSR registers 116) are allowed, and all other reads are treated as errors (I e they are aborted) In this state, the individual processmg sets 14 and 16 perform evaluations for determining a restart time Each processmg set 14 and 16 will determine its own restart timer timing The timer setting depends on a ' blame" factor for the transition to the EState A processing set which determines that it is likely to have caused the eiror sets a long time for the timer A processing set which thinks it unlikely to have caused the error sets a short time for the timer The first processing set 14 and 16 which times out, becomes a primary processing set Accoidingly, when this is determined, the bridge moves (153) to the primary EState 154 When either processmg set 14/16 has become the primary processmg set, the bridge is then operating in the pnmary EState 154 This state allows the pnmary processmg set to write to bridge registers (specifically the SRRs 118) Other writes are no longer stored in the posted write buffer, but are simply lost Device bus leads aie still aborted m the pnmary EState 154 Once the EState condition is removed, the bridge then moves (155) to the split state 156 In the split state 156 access to the device bus 22 is controlled by the SRR registers 118 while access to the bridge storage is simply arbitrated The primary status of the processing sets 14 and 16 is ignored Transition to a combmed operation is achieved by means of a sync_reset (157) After issue of the sync_reset operation, the bridge is then opeiable in the combined state 158, whereby all read and write accesses on the D bus 22 and the PA and PB buses 24 and 26 are allowed All such accesses on the PA and PB buses 24 and 26 are compared m the compaiator 130 Detection of a mismatch between any read and write cycles (with an exception of specific dissimilai data I/O cycles) cause a transition 151 to the EState 150 The various states descnbed are controlled by the budge controller 132 The role of the comparator 130 is to monitor and compare I/O operations on the PA and PB buses in the combined state 151 and, m response to a mismatched signal, to notify the bridge controller 132, whereby the budge controller 132 causes the transition 152 to the error state 150 The 1 0 operations can include all I/O operations initiated by the processing sets, as well as DMA transfers m respect of DMA initiated by a device on Table 1 below summarizes the various access operations which are allowed in each of the operational states TABLE 1 D Bus - Read D Bus- Write E State Master Abort Stored in Post Write Buffer Piimaiv EState Master Abort Lost Split Controlled by SRR bits Controlled by SRR bits and arbitrated and arbitrated Combined Allowed and compared Allowed and compared As described above, after an initial reset, the system is m the initial EState 152 In this state, neither piocessmg sets 14 or 16 can access the D bus 22 or the P bus 26 or 24 of the other processing set 16 or 14 The internal budge registers 116 of the bridge are accessible, but are read only A system running m the combined mode 158 transitions to the EState 150 where there is a comparison failuie detected in this bndge, or alternatively a comparison failure is detected m another bridge in a multi- bndge system as shown, for example, in Figure 2 Also, transitions to an EState 150 can occur in other situations, for example m the case of a software controlled event forming part of a self test operation On movmg to the EState 150, an interrupt is signaled to all or a subset of the processors of the piocessmg sets via an interrupt lme 95 Following this, all I/O cycles generated on a P bus 24 or 26 result m leads being returned with an exception and writes being recorded in the posted wnte buffer The operation of the comparator 130 will now be descnbed m more detail The comparator is connected to paths 94, 95, 96 and 97 for comparing address, data and selected control signals from the PA and PB bus interfaces 84 and 86 A failed comparison of in-sync accesses to device I/O bus 22 devices causes a move from the combmed state 158 to the EState 150 For processing set I O read cycles, the address, command, address parity, byte enables and parity error paiameteis are compared. If the companson fails durmg the address phase, the bridge asserts a retry to the processing set bus controlleis 50, which prevents data leavmg the I/O bus controllers 50 No activity occurs in this case on the dev ice I/O bus 22. On the processor(s) retrying, no enor is returned If the companson fails during a data phase (only control signals and byte enables are checked), the budge signals a target-abort to the processmg set bus controllers 50 An error is returned to the processors In the case of processmg set I/O bus write cycles, the address, command, panty, byte enables and data paiameteis are compared. If the companson fails during the address phase, the bridge asserts a retry to the processing set bus controlleis 50, which results in the processing set bus controllers 50 retrying the cycle again The posted write buttei 122 is then active. No activity occurs on the device I/O bus 22. If the companson fails during the data phase of a write operation, no data is passed to the D bus 22 The tailing data and any other transfer attributes from both processing sets 14 and 16 are stored in the disconnect registers 122, and any subsequent posted write cycles are recorded m the posted write buffer 118 In the case of direct virtual memory access (DVMA) reads, the data control and parity are checked for each datum If the data does not match, the bridge 12 terminates the transfer on the P bus. In the case of DVMA wntes, control and parity error signals are checked for correctness. Other signals in addition to those specifically mentioned above can be compared to give an indication of diveigence of the processing sets Examples of these are bus grants and various specific signals during piocessmg set transfers and during DMA transfers Errors fall roughly into two types, those which are made visible to the software by the processing set bus contioller 50 and those which are not made visible by the processing set bus controller 50 and hence need to be made visible by an interrupt from the bridge 12. Accordingly, the bridge is operable to capture errors reported in connection with processing set read and write cycles, and DMA reads and wntes. Clock control for the bridge is performed by the bridge controller 132 in response to the clock signals tiom the clock line 21 Individual control lines from the controller 132 to the various elements of the bridge are not shown in Figures 6 to 10 Figure 12 is a flow diagram illustrating a possible sequence of operatmg stages where lockstep errors aie detected during a combmed mode of operation Stage SI represents the combined mode of operation where lockstep enor checking is performed by the comparator 130 shown m Figure 8 In Stage S2, a lockstep error is assumed to have been detected by the comparator 130 In Stage S3, the current state is saved in the CSR registers 114 and posted writes are saved in the posted wnte buffer 122 and/or m the disconnect registers 120 Figure 13 illustrates Stage S3 in more detail Accordmgly, m Stage S31, the bndge controller 132 detects hether the lockstep error notified by the comparator 130 has occurred durmg a data phase in which it is possible to pass data to the device bus 22 In this case, in Stage S32, the bus cycle is termmated Then, in Stage S33 the data phases are stored m the disconnect registers 120 and control then passes to Stage S35 where an evaluation is made as to whether a further I/O cycle needs to be stored Alternatively, if at Stage S31, it is deteimmed that the lockstep error did not occur during a data phase, the address and data phases for any posted w rite I O cycles are stored in the posted write buffer 122 At Stage S34, if there are any further posted write I/O opeiations pending, these are also stored in the posted wnte buffer 122 Stage S3 is performed at the initiation of the initial error state 152 shown in Figure 11 In this state, the fust and second processing sets arbitrate for access to the bridge Accordmgly, in Stage S31-S35, the posted w rite addiess and data phases for each of the processing sets 14 and 16 are stored m separate portions of the posted wnte buffer 122, and/or m the single set of disconnect registers as descnbed above Figure 14 illustrates the source of the posted wnte I O cycles which need to be stored in the posted w nte butter 122 During normal operation of the processing sets 14 and 16, output buffers 162 in the individual piocessois contain I/O cycles which have been posted for transfer via the processmg set bus controllers 50 to the budge 12 and eventually to the device bus 22 Similarly, buffers 160 in the processing set controllers 50 also contain posted I/O cycles for transfer over the buses 24 and 26 to the bridge 12 and eventually to the device bus 22 Accordingly, it can be seen that when an error state occurs, I/O write cycles may already have been posted by the processors 52, either m their own buffers 162, or already transferred to the buffers 160 of the piocessmg set bus controllers 50 It is the I/O write cycles m the buffers 162 and 160 which gradually piopauatc through and need to be stored in the posted write buffer 122 As shown m Figure 15, a write cycle 164 posted to the posted write buffer 122 can comprise an addiess field 165 mcludmg an address and an address type, and between one and 16 data fields 166 including a byte enable field and the data itself The data is written mto the posted write buffer 122 in the EState unless the initiating processmg set has been designated as a primary CPU set At that time, non-pnmary wntes in an EState still go to the posted write buffei even after one of the CPU sets has become a primary processing set An address pointer in the CSR legisteis 1 14 points to the next available posted wnte buffer address, and also provides an overflow bit which is set when the bridge attempts to write past of the top of the posted write buffer for any one of the processing sets 14 and 16 Indeed, m the present implementation, only the first 16 K of data is recorded m each buffer Attempts to write beyond the top of the posted write buffer are ignored The value of the posted write buffer pointei can be cleared at reset, or by software using a write under the control of a primary processing set Returning to Figure 12, after saving the status and posted wntes, at Stage S4 the individual processing .ts independently seek to evaluate the error state and to determine whether one of the processing sets is faulty I his deteimination is made by the individual processors m an error state m which they individually read status horn the control state and EState registers 114 Dunng this error mode, the arbiter 134 arbitrates for access to the bridge 12 In Stage S5, one of the processmg sets 14 and 16 establishes itself as the primary processing set This is detei mined by each of the processmg sets identifying a time factor based on the estimated degree of R e sponsibility for the error, whereby the first processing set to time out becomes the primary processing set In Stage S" the status is recovered for that processing set and is copied to the other processing set The primary piocessmg is able to access the posted write buffer 122 and the disconnect registers 120 In Stage S6, the bndge is operable m a split mode If it is possible to re-establish an equivalent status for the first and second processing sets, then a reset is issued at Stage S7 to put the processing sets m the combined mode at Stage SI However, it may not be possible to re-establish an equivalent state until a faulty piocessmg set is replaced Accordmgly the system will stay in the Split mode of Stage S6 in order to contmued operation based on a smgle processmg set After replacmg the faulty processing set the system could then establish an equivalent state and move via Stage S7 to Stage SI \s described above, the comparator 130 is operable in the combined mode to compare the I/O operations output by the first and second processing sets 14 and 16 This is fine as long as all of the I/O operations of the first and second processmg sets 14 and 16 are fully synchronized and deterministic Any deviation from this will be interpreted by the comparator 130 as a loss of lockstep This is m pnnciple correct as even a minor deviation from identical outputs, if not trapped by the comparator 130, could lead to the piocessmg sets divergmg further from each other as the individual processing sets act on the deviating outputs Howes ei a strict application of this puts significant constraints on the design of the individual processing sets An example of this is that it would not be possible to have independent tune of day clocks in the individual piocessmg sets operatmg under their own clocks This is because it is impossible to obtain two crystals which aie 100% identical in operation Even small differences m the phase of the clocks could be critical as to hethei the same sample is taken at any one time, for example either side of a clock transition for the respective piocessmg sets Accordingly, a solution to this problem employs the dissimilar data registers (DDR) 116 mentioned ear ei The solution is to employ a DMA engme m the bridge to cause data to be read from a location in the piocessmg sets 14 and 16 into respective DDRs 116 in the bridge while disabling the companson of the data phases of the read operations Then the processing sets 14 and 16 can read a selected one of the DDRs, w hereby each of the processing sets is able to act on the same data Figure 17 is a schematic representation of aspects of the bridge of Figures 6 to 10 It will be noted that details of the bridge not shown m Figure 6 to 8 are shown m Figure 17, whereas other details of the bridge shown in Figures 6 to 8 are not shown in Figure 17, for reasons of clarity The DDRs 116 are provided in the bridge registers 110 of Figure 7, but could be provided elsewhere in the bridge in other embodiments One DDR 116 is provided for each processmg set In the example of the multi-piocessor system of Figure 1 where two processing sets 14 and 16 are provided, two DDRs 116A and 1 16B aie provided, one for each of the first and second processing sets 14 and 16, respectively A DMA engme 133 is provided in the bridge controller 132, although m other embodiments this could be provided elsewhere m the bndge 12 The DMA engme 133 provides a state machme responsive to data 135 stored in the CSRs 124 This data delmes a start tune for a DMA dissimilar data operation, the processor set address from which to read the data, how much data to be transferred and any bits m a data word to be transferred which are void The DMA engine is responsive to this data to initiate a DMA operation which emulates a device bus DMA operation, sending identical DMA requests (DMA1) to the first and second processmg sets 14 and 16 via the PA bus interface 84 and the PB bus interface 86 The DMA engme also disables the comparator 130 by means of a disable signal 137 so that differences between the dissimilar data returned in response to the DMA operation does not cause the comparator to signal a lockstep error The DMA engme could be operable completely to disable the comparator, or could be operable to disable the detection of differences m the data and/or data parity only of the accessed data. The DMA engme further enables gates 115A and 115B connected to the paths 94 and 96, respectively, to enable the dissimilar data returned in response to the DMA operation to be stored in the first and second DDRs 1 16A and 116B, respectively At the end of the data phase the comparator 130 is once again enabled to detect any differences between I O address and/or data phases as indicative of a lockstep error Following the transfer of the dissimilar data from the processing sets to the first and second DDRs 1 16A and 116B, the processing sets are then operable to read the data from a selected one of the DDRs 116A and 116B Tigure 18 illustrates an alternative arrangement where the disable signal 137 is negated and is used to control a gate 131 at the output of the comparator 130 When the disable signal is active the output of the compaiator is disabled, whereas when the disable signal is inactive the output of the comparator is enabled Figure 19 illustrates the reading of the first DDR 116A in a subsequent dissimilar data read stage As illustrated in Figure 19, each of the processing sets 14 and 16 outputs the same predetermined address DDR-RA w hich is separately interpreted by the respective first and second decoding sections 136A and 136B as addressing the same DDR, namely the first DDR 116A As a result, the content of the first DDR 116A is read by both of the processing sets 14 and 16, thereby enablmg those processmg sets to receive the same data This enables the two processmg sets 14 and 16 to achieve deterministic behavior, even if the source of the data wiitten into the DDRs 116 by the processing sets 14 and 16 was n t deterministic As an alternative, the processmg sets could each read the data from the second DDR 116B Figure 20 illustrates the reading of the second DDR 116B in a dissimilar data read stage following the dissimilar data write stage of Figure 15 As illustrated m Figure 20, each of the processmg sets 14 and 16 outputs the same pi edetei mined address DDR-RB which is separately interpreted by the respective first and second decoding sections 136A and 136B as addressing the same DDR, namely the second DDR 116B As a result, the content of the second DDR 116B is read by both of the processing sets 14 and 16, thereby enabling those processing sets to leceive the same data As with the dissimilar data read stage of Figure 16, this enables the two piocessmg sets 14 and 16 to achieve deterministic behavior, even if the source of the data wntten into the DDRs 1 16 by the processing sets 14 and 16 was not deterministic The selection of which of the first and second DDRs 116A and 116B to be read can be determined m any appiopnate manner by the software operatmg on the processing modules This could be done on the basis of a simple selection of one or the other DDRs, or on a statistical basis or randomly or m any other manner as long as the same choice of DDR is made by both or all of the processing sets Figure 21 is a flow diagram summarizing the various stages of operation of the DDR mechanism described above In stage S10, a DMA operation is initiated by the DMA engine 133 In stage SI 1, the comparator 130 is disabled In stage SI 2, the data received from the processing sets 14 and 16 in response to the DMA operation is stored in the fust and second DDRs 116A and 116B, respectively, via the gates 115A and 115B, respectively In stage S13, a DDR read address is received from the first and second processmg sets and is decoded by the decode sections 130A and 130B, respectively If the received address DDR-RA is for the first DDR 116A, then in stage S14 the content of that DDR 1 16A is lead by both of the processmg sets 14 and 16 Alternatively, 116A if the received address DDR-RB is for the second DDR 116B, then in stage SI 5 the content of that DDR 116B is read by both of the processing sets 14 and 16 Figuie 22 is a schematic representation of the arbitration performed on the respective buses 22, 24 and 26, and the arbitration for the bridge itself Each of the processmg set bus controllers 50 m the respective processing sets 14 and 16 includes a conventional PCI master bus arbiter 180 for providing arbitration to the respective buses 24 and 26 Each of the master aibiters 180 is responsive to request signals from the associated processing set bus controller 50 and the bi idge 12 on respective request (REQ) lines 181 and 182 The master arbiters 180 allocate access to the bus on a first-come-first-served basis, issuing a grant (GNT) signal to the winning party on an appropriate grants line 183 oι 184 \ conventional PCI bus arbiter 185 provides arbitration on the D bus 22 The D bus arbiter 185 can be configuicd as part of the D bus mterface 82 of Figure 6 or could be separate therefrom As with the P bus master aibiters 180, the D bus arbiter is responsive to request signals from the contending devices, including the budge and the devices 30, 31, etc. connected to the device bus 22 Respective request lines 186, 187, 188, etc for each of the entities competing for access to the D bus 22 are provided for the request signals (REQ) The D bus ai biter 185 allocates access to the D bus on a first-come-first-served basis, issumg a grant (GNT) signal to the winning entity via respective grant lines 189, 190, 192, etc Figure 23 is a state diagram summarising the operation of the D bus arbiter 185 In a particular embodiment up to six request signals may be produced by respective D bus devices and one by the bndge itself On a tiansition into the GRANT state, these are sorted by a pnoπty encoder and a request signal (REQ#) with the highest piioπty is registered as the winner and gets a grant (GNT#) signal Each winner which is selected modifies the priorities m a priority encoder so that given the same REQ# signals on the next move to grant A different device has the highest pnoπty, hence each device has a "fair" chance of accessing DEVs The bridge REQ# has a higher weighting than D bus devices and will, under very busy conditions, get the bus for every second device It a device requesting the bus fails to perform a transaction withm 16 cycles it may lose GNT# via the BACKOFF state BACKOFF is required as, under PCI rules, a device may access the bus one cycle after GNT# is removed Devices may only be granted access to D bus if the bridge is not in the not in the EState A new GNT# is produced at the tunes when the bus is idle In the GRANT and BUSY states, the FETs are enabled and an accessing device is known and forwaided to the D bus address decode logic for checking against a DMA address provided by the device Turning now to the bridge arbiter 134, this allows access to the bndge for the first device which asserts the PCI FRAME# signal indicating an address phase Figure 24 is a state diagram summarising the operation of the bridge arbiter 134 As with the D bus arbiter, a priority encoder can be provided to resolve access attempts which collide In this case "a collision" the loser/losers are retned which forces them to give up the bus Under PCI rules letned ices must try repeatedly to access the bndge and this can be expected to happen To prevent devices which are very quick with their retry attempt from hoggmg the bridge, retried interfaces are remembered and assigned a higher priority These remembered retries are pπontised m the same w ay as address phases However as a precaution this mechanism is timed out so as not to get stuck waiting for a taulty oi dead device The algonthm employed prevents a device which hasn't yet been retried, but which would be a higher pnonty retry than a device currently waiting for, from being retried at the first attempt In combined operations a PA or PB bus input selects which P bus mterface will win a bridge access Both aie informed they won Allowed selection enables latent fault checkmg during normal operation EState pi events the D bus from winning The bridge arbiter 134 is responsive to standard PCI signals provided on standard PCI control lines 22, 24 and 25 to control access to the bridge 12 Figure 25 illustrates signals associated with an I/O operation cycle on the PCI bus A PCI frame signal (FRAME#) is initially asserted At the same time, address (A) signals will be available on the DATA BUS and the appiopπate command (write/read) signals (C) will be available on the command bus (CMD BUS) Shortly after the fiame signal being asserted low, the initiator ready signal (IRDY#) will also be asserted low When the device lesponds, a device selected signal (DEVSEL#) will be asserted low When a target ready signal is asserted low (TRDY#), data transfer (D) can occur on the data bus The bridge is operable to allocate access to the bridge resources and thereby to negotiate allocation of a taiget bus in response to the FRAME# being asserted low for the initiator bus concerned Accordmgly, the budge aibiter 134 is operable to allocate access to the bridge resources and/or to a target bus on a first-come- tust-seived basis in response to the FRAME# being asserted low As well as the simple first-come-first-served basis, the aibiters may be additionally provided with a mechanism for logging the arbitration requests, and can imply a conflict resolution based on the request and allocation history where two requests are received at an identical time Alternatively, a simple priority can be allocated to the various requesters, whereby, m the case of identically timed requests, a particular requester always wins the allocation process. Each of the slots on the device bus 22 has a slot response register (SRR) 118, as well as other devices connected to the bus, such as a SCSI interface. Each of the SRRs 118 contams bits defining the ownership of the slots, oi the devices connected to the slots on the dnect memory access bus. In this embodiment, and for leasons to be elaborated below, each SRR 118 compnses a four bit register However, it will be appreciated that a laiger register will be required to determine ownership between more than two processmg sets. For example, if three processmg sets are provided, then a five bit register will be requned for each slot. Figure 16 illustrates schematically one such four bit register 600 As shown in Figure 16, a first bit 602 is identified as SRR[0], a second bit 604 is identified as SRR[1], a third bit 606 is identified as SRR[2] and a fourth bit 608 is identified as SRR[3]. Bit SRR[0] is a bit which is set when writes for valid transactions are to be suppressed. Bit SRR[1] is set when the device slot is owned by the first processmg set 14. This defines the access loute between the first processmg set 14 and the device slot When this bit is set, the first processing set 14 can always be master of a device slot 22, while the ability for the device slot to be master depends on whether bit Bit SRR[2] is set when the device slot is owned by the second processmg set 16 This defines the access loute between the second processing set 16 and the device slot. When this bit is set, the second piocessmg set 16 can always be master of the device slot or bus 22, while the ability for the device slot to be master depends on whether bit SRR[3] is set Bit SRR[3] is an arbitration bit which gives the device slot the ability to become master of the device bus 22, but only if it is owned by one of the processing sets 14 and 16, that is if one of the SRR [1] and SRR[2] When the fake bit (SRR[0]) of an SRR 118 is set, writes to the device for that slot are ignored and do not appear on the device bus 22 Reads return indeterminate data without causmg a transaction on the device bus 22 In the event of an I/O error the fake bit SRR[0] of the SRR 188 corresponding to the device which caused the eiror is set by the hardware configuration of the bridge to disable further access to the device slot concerned An interrupt may also be generated by the bridge to inform the software which originated the access leading to the I/O error that the error has occurred. The fake bit has an effect whether the system is m the split oi the combined mode of operation. The ownership bits only have effect, however, in the split system mode of operation. In this mode, each slot can be in three states: Not-owned; Owned by processmg set 14; and Owned by processmg set 16 This is determined by the two SRR bits SRR[1] and SRR[2], with SRR[1] being set when the slot is owned by piocessmg set 14 and SRR[2] being set when the slot is owned by processing set B If the slot is unowned then neither bit is set (both bits set is an illegal condition and is prevented by the hardware). A slot which is not owned by the processing set makmg the access (this includes un-owned slots) cannot be accessed and results in an abort A processmg set can only claim an un-owned slot, it cannot wrest ownership away from another processing set This can only be done by powermg-off the other processing set When a piocessmg set is powered off, all slots owned by it move to the un-owned state Whilst it is not possible lor a processing set to wrest ownership from another processing set, it is possible for a processing set to give owneiship to another processmg set The owned bits can be altered when in the combmed mode of operation state but they have no effect until the split mode is entered Table 2 below summanzes the access rights as determined by an SRR 118 Tiom Table 2, it can be seen that when the 4-bit SRR for a given device is set to 1100, for example, then the slot is owned by processmg set B (l e SRR[2] is logic high) and processmg set A may not read from or write to the device (l e SRR[1] is logic low), although it may read from or write to the bridge "FAKE_AT" is set logic low (I e SRR[0] is logic low) indicating that access to the device bus is allowed as there are no faults on the bus As "ARB_EN" is set logic high (l e SRR[3] is logic high), the device with which the register is associated can become master of the D bus This example demonstrates the operation of the register when the bus and associated devices are operating correctly TABLE 2 SRR PA BUS PB BUS Device Interface [3[2][1 ][0] 0000 xOOλ Read/Write bndge SRR Read/Write bridge SRR Access denied 0010 Read/Write bridge Read/Write bridge Access Denied because Owned D Slot No access to D Slot arbitration bit is off 0100 Read/Write bridge Read/write bridge Access Denied because No access to D Slot Access to D Slot arbitration bit is off 1010 Read/Write bndge, Read/Write Bridge Access to CPU B Denied Owned D Slot No access to D Slot Access to CPU A OK 1 100 Read/Write bndge, Read/Write bridge Access to CPU A Denied No access to D Slot Access to D Slot Access to CPU B OK 0011 Read/Write bndge, Read/Write bridge Access Denied because Bridge discard writes No access to D Slot Arbitration bit is off 0101 Read/Wnte bndge, Read/Write bridge Access Denied because No access to D slot Bridge discards writes Arbitration bit is off 101 1 Read/Write bndge, Read/Write bridge Access to CPU B Denied Bridge discard writes No access to D Slot Access to CPU A OK 1101 Read/Write bndge, Read/Write bridge Access to CPU B Denied No access to D slot Bridge discards writes Access to CPU A OK In an alternative example, where the SRR for the device is set to 0101, the setting of SRR[2] logic high indicates that the device is owned by processing set B However, as the device is malfunctioning, SRR[3] is set logic low and the device is not allowed access to the processing set SRR[0] is set high so that any writes to the device aie ignored and reads therefrom return indeterminate data In this way, the malfunctioning device is etfectπ elv isolated from the processing set, and provides indeterminate data to satisfy any device drivers, for example that might be lookmg for a response from the device Figure 26 illustrates the operation of the bridge 12 for direct memory access by a device such as one of the devices 28, 29, 30, 31 and 32 to the memory 56 of the processing sets 14 and 16 When the D bus arbiter 185 receives a direct memory access (DMA) request 193 from a device (e g , device 30 in slot 33) on the device bus the D bus arbiter determines whether to allocate the bus to that slot As a result of this grantmg procedure, the D-bus arbiter knows the slot which has made the DMA request 193 The DMA request is supplied to the address decoder 142 in the bridge, where the addresses associated with the request are decoded The address decodei is responsive to the D bus grant signal 194 for the slot concerned to identify the slot which has been gianted access to the D bus for the DMA request The address decode logic 142 holds or has access to a geographic address map 196, which identifies the relationship between the processor address space and the slots as a result of the geographic address employed This geographic address map 196 could be held as a table m the bndge memory 126, along with the posted write buffer 122 and the dirty RAM 124 Alternatively, it could be held as a table m a separate memory element possibly forming part of the address decoder 142 itself The map 182 could be configured m a form othei than a table The address decode logic 142 is configured to verify the correctness of the DMA addresses supplied by the de\ ice 30 In one embodiment of the invention, this is achieved by comparing four significant address bits ot the addiess supplied by the device 30 with the corresponding four address bits of the address held in the geographic addressing map 196 for the slot identified by the D bus grant signal for the DMA request In this example, four address bits are sufficient to determine whether the address supplied is within the correct address lange In this specific example, 32 bit PCI bus addresses are used, with bits 31 and 30 always being set to 1, bit 29 being allocated to identify which of two bridges on a motherboard is being addressed (see Figure 2) and bits 28 to 26 identifying a PCI device Bits 25-0 define an offset from the base address for the address range for each slot Accordingly, by comparing bits 29-26, it is possible to identify whether the address(es) supplied tall(s) within the appropriate address range for the slot concerned It will be appreciated that in other embodiments a different number of bits may need to be compared to make this determination depending upon the allocation of the addresses The address decode logic 142 could be arranged to use the bus grant signal 184 for the slot concerned to identity a table entry for the slot concerned and then to compare the address m that entry with the address(es) leceived with the DMA request as descnbed above Alternatively, the address decode logic 142 could be aπanged to use the address(es) received with the DMA address to address a relational geographic address map and to determine a slot number therefrom, which could be compared to the slot for which the bus grant signal 1 4 is intended and thereby to determine whether the addresses fall withm the address range appropnate for the slot concerned Either way, the address decode logic 142 is arranged to permit DMA to proceed if the DMA addresses fall within the expected address space for the slot concerned. Otherwise, the address decoder is arranged to ignore the slots and the physical addresses. The address decode logic 142 is further operable to control the routmg of the DMA request to the appropnate processing set(s) 14/16. If the bridge is m the combined mode, the DMA access will automatically be allocated to all of the in-sync processing sets 14/16. The address decode logic 142 will be aware that the budge is in the combined mode as it is under the control of the bridge controller 132 (see Figure 8). However, where the bridge is m the split mode, a decision will need to be made as to which, if any, of the processing sets the DMA lequest is to be sent. When the system is in split mode, the access will be directed to a processing set 14 or 16 which owns the slot concerned. If the slot is un-owned, then the bndge does not respond to the DMA request. In the split mode, the address decode logic 142 is operable to determine the ownership of the device originating the DMA lequest by accessing the SRR 118 for the slot concerned The appropnate slot can be identified by the D bus giant signal. The address decode logic 142 is operable to control the target controller 140 (see Figure 8) to pass the DM \ lequest to the appropriate processing set(s) 14/16 based on the ownership bits SRR[1] and SRR[2] If bit SRR[1] is set, the first processing set 14 is the owner and the DMA request is passed to the first processing set If bit SRR[2] is set, the second processing set 16 is the owner and the DMA request is passed to the second piocessmg set If neither of the bit SRR[1] and SRR[2] is set, then the DMA request is ignored by the address decodei and is not passed to either of the processing sets 14 and 16. Figure 27 is a flow diagram summarizing the DMA verification process as illustrated with reference to Figure 24 In stage S20, the D-bus arbiter 160 arbitrates for access to the D bus 22. In stage S21, the address decoder 142 verifies the DMA addresses supplied with the DMA request by accessing the geographic address map. In stage S22, the address decoder ignores the DMA access where the address falls outside the expected i nge foi the slot concerned Alternatively, as represented by stage S23, the actions of the address decoder are dependent upon w hethei the bridge is m the combined or the split mode If the bridge is m the combmed mode, then in stage S24 the address decoder controls the target controllei 140 (see Figure 8) to cause the routing matnx 80 (see Figure 6) to pass the DMA request to both piocessmg sets 14 and 16. If the bridge is in the split mode, the address decoder is operative to verify the ownership of the slot concerned by reference to the SRR 118 for that slot in stage S25. If the slot is allocated to the first processing set 14 (i.e. the SRR[1] bit is set), then m stage S26 the address decoder 142 controls the target controller 140 (see Figure 8) to cause the routing matrix 80 (see Figure 6) to pass the DMA request to first processing set 14 If the slot is allocated to the second processing set 16 (i.e. the SRR[2] bit is set), then in stage S27 the address decoder 142 controls the target controller 140 (see Figure 8) to cause the routing matrix 80 (see Figure 6) to pass the DMA request to the second processing set 16. If the slot is unallocated (1 e neither the SRR[1] bit nor the SRR[2] bit is set), then m step SI 8 the address decoder 142 ignores or discards the DMA request and the DMA request is not passed to the processing sets 14 and 16 A DMA, or direct vector memory access (DVMA), request sent to one or more of the processing sets causes the necessary memory operations (read or wnte as appropnate) to be effected on the processing set memory There now follows a descnption of an example of a mechanism for enablmg automatic recovery from M EState (see Figure 11) The automatic recovery process includes reintegrahon of the state of the processmg sets to a common status in oider to attempt a restart m lockstep To achieve this, the processmg set which asserts itself as the pnmary piocessmg set as descnbed above copies its complete state to the other processmg set This mvolves ensuring that the content of the memory of both processors is the same before trying a restart in lockstep mode However, a problem with the copymg of the content of the memory from one processmg set to the other is that dui ing this copymg process a device connected to the D bus 22 might attempt to make a direct memory access ( DMA) lequest for access to the memory of the pnmary processmg set If DMA is enabled, then a wnte made to an aiea of memory which has already been copied would result m the memory state of the two processors at the end ot the copy not being the same In principle, it would be possible to inhibit DMA for the whole of the copy piocess However, this would be undesirable, bearing m mind that it is desirable to minimise the time that the system or the resources of the system are unavailable As an alternative, it would be possible to retry the whole copy opeiation when a DMA operation has occurred dunng the penod of the copy However, it is likely that tuithei DMA operations would be performed dunng the copy retry, and accordmgly this is not a good option eithei Accoidingly, m the present system, a dirty RAM 124 is provided m the bndge As descnbed earlier the duty RAM 124 is configured as part of the bndge SRAM memory 126 The dirty RAM 124 compnses a bit map havmg a duty indicator, for example a dirty bit, for each block, oi page of memory The bit for a page of memory is set when a wnte access to the area of memory concerned is made In an embodiment of the invention one bit is provided for every 8K page of mam processmg set memory The bit for a page of processmg set memory is set automatically by the address decoder 142 when this decodes a DMA lequest for that page of memory for either of the processmg sets 14 or 16 from a device connected to the D bus 22 The dirty RAM can be reset, or cleared when it is read by a processmg set, for example by means of read and cleai instructions at the beginnmg of a copy pass, so that it can start to record pages which are dirtied smce a given time The du y RAM 124 can be read word by word If a large word size is chosen for readmg the dirty RAM 124, this will optimise the readmg and resetting of the dirty RAM 124 Accoidingly, at the end of the copy pass the bits m the dirty RAM 124 will mdicate those pages of piocessmg set memory which have been changed (or dirtied) by DMA wntes dunng the penod of the copy A fuithei copy pass can then be performed for only those pages of memory which have been dirtied This will take less time that a full copy of the memory Accordmgly, there are typically less pages marked as dirty at the end of the next copy pass and, as a result, the copy passes can become shorter and shorter As some time it is necessary to decide to inhibit DMA wntes for a short penod for a final, short, copy pass, at the end of which the memones of the two processmg sets will be the same and the pnmary processmg set can issue a reset operation to restart the combined mode. The duty RAM 124 is set and cleared in both the combined and split modes This means that in split mode the dirty RAM 124 may be cleared by either processing set. The dirty RAM 124 address is decoded from bits 13 to 28 of the PCI address presented by the D bus device Enoneous accesses which present illegal combmations of the address bits 29 to 31 are mapped into the duty RAM 124 and a bit is dirtied on a write, even though the bridge will not pass these transactions to the piocessmg sets When readmg the dirty RAM 124, the bridge defines the whole area from 0x00008000 to OxOOOOffff as dirty RAM and will clear the contents of any location in this range on a read. As an alternative to providing a single dirty RAM 124 which is cleared on being read, another alternative would be to provide two duty RAMs which are used m a toggle mode, with one being written to w hile another is read. Figure 28 is a flow diagram summansing the operation of the dirty RAM 124 In stage S41, the pnmary processmg set reads the dirty RAM 124 which has the effect of resetting the duty RAM 124. In stage S42, the pnmary processor (e g processmg set 14) copies the whole of its memory 56 to the memory 56 of the other processmg set (e.g processmg set 16) In stage S43, the pnmary processmg set reads the duty RAM 124 which has the effect of resetting the duty RAM 124 In stage S44, the pnmary processor determines whether less than a predetermined number of bits have been wi men m the dirty RAM 124. If more than the predetermined number of bits have been set, then the processor m stage S45 copies those pages of its memory 56 which have been dirtied, as mdicated by the dirty bits read from the duty RAM 124 in stage S43 to the memory 56 of the other processmg set Control then passes back to stage S43 If. m stage S44, it is determined less than the predetermined number of bits have been written in the dirty RAM 124, then m Stage S45 the pnmary processor causes the bndge to inhibit DMA requests from the devices connected to the D bus 22. This could, for example, be achieved by clearing the arbitration enable bit for each of the device slots, thereby denymg access of the DMA devices to the D bus 22. Alternatively, the address decoder 142 could be configured to ignore DMA requests under mstructions from the pnmary processor. Dunng the penod in which DMA accesses are prevented, the pnmary processor then makes a final copy pass from its memory to the memory 56 of the other processor for those memory pages corresponding to the bits set m the duty RAM 124. In stage S47 the primary processor can issue a reset operation for initiating a combmed mode In stage S48, DMA accesses are once more permitted. It will be appreciated that although particular embodiments of the invention have been descnbed, many modifications/additions and/or substitutions may be made withm the spint and scope of the present mvention as defined in the appended claims. For example, although m the specific descnpnon two processmg sets are provided, it will be appreciated that the specifically descnbed features may be modified to provide for three or more piocessmg sets

Claims: WHAT IS CLAIMED: 1. A bridge for a multi-processor system, the bridge comprising a first processor bus interface for connection to an I/O bus of a first processing set, a second processor bus interface for connection to an I/O bus of a second processing set, a device bus interface for connection to a device bus, a bridge control mechanism configured to be operable to compare address and data phases of I/O accesses by the first and second processing sets, at least one dissimilar data register associated with each processing set, and a direct memory access mechanism operable to initiate a direct memory access operation to read from a corresponding location in each processing set into the associated dissimilar data register, the bridge control mechanism being configured to be operable during the direct memory access operation to disregard differences in the data for the dissimilar data direct memory access. 2. The bridge of claim 1, comprising a direct memory access control register for holding an addresses of the location to be read and the size of the read to carry this out. 3. The bridge of claim 1, wherein the bridge control mechanism comprises a comparator connected to the first and second processor bus interfaces, the comparator being configured to be operable to detect differences between signals on the I/O buses of the first and second processing sets as indicative of a lockstep error. 4. The bridge of claim 3, wherein the bridge control mechanism is operable to block the output of the comparator. 5. The bridge of claim 3, wherein the bridge control mechanism is operable to inhibit the operation of the comparator. 6. The bridge of claim 3, wherein the bridge control mechanism is configured to be operable to respond to a read destination address supplied in common by the first and second processing sets for a dissimilar data read access to supply data read from a determined one of the dissimilar data registers to the first and second processing sets. 7. The bridge of claim 6, wherein the read destination address supplied in common by the first and second processing sets determines the dissimilar data register from which data is read. 8. The bridge of claim 6, comprising an address decode mechanism responsive to a read destination address supplied in common by the first and second processing sets for a dissimilar data read access to modify the destination address such that the address decoder derives an address for one of the first and second dissimilar data registers from the common read destination address. 9 The bridge of claim 1, wherein the dissimilar data registers are configured m random access memory in the budge 10 The bridge of claim 1, wherein the dissimilar data registers are configured as hardware registers in the bndge 1 1 The bridge of claim 1, compnsing at least one further processor bus mterface for connection to an I O bus of a further processmg set 12 A computer system compnsmg a first processing set having an I/O bus, a second processing set having an I/O bus, a device bus and a bridge, the bndge being connected to the I/O bus of the first processing set, the I O bus of the second processing set and a device bus and compnsing a bridge control mechanism configured to be operable to compare address and data phases of I/O accesses by the first and second processmg sets, at least one dissimilar data register associated with each processing set, and a dnect memory access mechanism operable to initiate a direct memory access operation to read from a coirespondmg location m each processor set mto the associated dissimilar data register, the bridge control mechanism being configured to be operable dunng the direct memory access operation to disregard differences in the data for the dissimilar data dnect memory access 13 The system of claim 12, wherein each processing set compnses at least one processor, memory and a piocessmg set I/O bus controller connected to the processing set I/O bus 14 The system of claim 12, further comprising at least one further processmg set l -> The system of claim 12, wherem the monitor comprises a direct memory access control register for holding an address of the location to be read and the size of the read to carry this out 16 The system of claim 12, wherem the bridge control mechanism comprises a comparator connected to the fust and second processor bus interfaces, the comparator being configured to be operable to detect ditfeiences between signals on the I/O buses of the first and second processmg sets as indicative of a lockstep enoi 17 The system of claim 16, wherem the bridge control mechanism is operable to block the output of the compaiator 18 The system of claim 16, wherem the bndge control mechanism is operable to inhibit the operation of the compaiator 19 The system of claim 16, wherem the bridge control mechanism is configured to be operable to respond to a read destmation address supplied m common by the first and second processmg sets for a dissimilar data lead access to supply data read from a determined one of the dissimilar data registers to the first and second piocessmg sets 20 The system of claim 19, wherem the read destmation address supplied in common by the first and second piocessmg sets determines the dissimilar data register from which data is read 21 The system of claim 19, compnsmg an address decode mechanism responsive to a read destination address supplied m common by the first and second processmg sets for a dissimilar data read access to modify the destmation address such that the address decoder denves an address for one of the first and second dissimilar data registers from the common read destmation address 22 The system of claim 12, wherein the dissimilar data registers are configured m random access memory in the bndge 23 The system of claim 12, wherem the dissimilar data registers are configured as hardware registers in the bndge 24 The system of claim 12, compnsmg at least one further processor bus interface for connection to an I OO bbuuss ooff aa ffuurrtthheerr p prroocceessssiinngg sseett 23 A method of operatmg a multi-processor system compnsing a first processmg set having a first I/O bus, a second processing set havmg a second I/O bus, a device bus and a bndge, the bridge interconnecting the tust piocessmg set I/O bus, the second processing set I/O bus and the device bus, the bndge including at least one dissimilar data register associated with each processmg set, and a direct memory access mechanism, the method comprising comparing address and data phases of I/O accesses from the first and second processmg sets for determining lockstep operation of the processmg sets, initiating a direct memory access operation to read from a corresponding location m each processing set into the associated dissimilar data register, and during the dnect memory access operation disregardmg differences in the data phase for the dissimilar data dnect memory access 26 The method of claim 25, compnsing subsequently detecting a read destination address supplied m common by the first and second processing sets for a dissimilar data read access to supply data read from a determined one of the dissimilar data registers to the first and second processmg sets 27. The method of claim 26, wherein the read destination address supplied in common by the first and second processing sets determines the dissimilar data register from which data is read.

Inventors: GARNETT PAUL J, OYELAKIN FEMI A, ROWLINSON STEPHEN, GARNETT, PAUL, J., OYELAKIN, FEMI, A., ROWLINSON, STEPHEN
Applicants: SUN MICROSYSTEMS INC, SUN MICROSYSTEMS, INC.
Application year: 1999
Main classification: G06F11
IPC codes: G06F11, G06F13