Filtering for transmission using quadrature modulation

Abstract: A system for digital communications includes a transmitter and a receiver, which comprise, respectively, a quadrature modulator and a quadrature demodulator. The transmitter also includes a non-recursive low pass filter, which has the same frequency characteristic as the output of the modulator, whereas the receiver includes a non-recursive low pass filter with the same frequency characteristic as the output of the demodulator. The filters are realised as transversal filters, and in each case are split into in-phase and quadrature parts, in which the in-phase part uses the coefficients of odd oder, and the quadrature part the coefficients of even order.

Description: BACKGROUND OF THE INVENTION The present invention relates to a system for transmitting two types of signal by orthogonal modulation, or more in particular to a digital signal transmission system comprising an orthogonal modulation transmission unit and an orthogonal demodulation receiving unit having a digital configuration. In recent years, a signal transmission system of orthogonal modulation type such as QPSK or QAM scheme has been employed for improving the transmission rate in the digital radio communication for mobile units and terrestrial communication. The orthogonal modulation scheme is for transmitting two types of signals by orthogonal modulation using two types of mutually orthogonal carriers expressed as cos(2π x f'c x t) and sin(2π x f'c x t) where t is the time and f'c the carrier frequency. The conventional digital signal transmission system of orthogonal modulation type has employed an orthogonal modulator/demodulator circuit mainly using a mixer of analog configuration for the apparent reason of its low cost and small circuit size. The conventional signal transmission system using this orthogonal modulator/demodulator circuit of analog type will be explained with reference to Figs. 19 and 20. First, Fig. 19 shows an example of a conventional transmission circuit of orthogonal modulation type. The information code input from an input terminal 1 is converted into two types of baseband digital signals Id(n), Qd(n) by a transmission signal processing circuit 2 and then applied to an orthogonal modulator 3, where n is an integer not less than 1 indicating the order of the clock signal pulses. The signals Id(n), Qd(n) input to the orthogonal modulator 3 are converted into analog signals by D/A converters 4i, 4q, respectively. Then, the transmission bandwidth of signals is limited to a predetermined value B by LPFs (low-pass filters) 5i, 5q of analog configuration. The signals I(t), Q(t) output from the LPFs 5i, 5q are input to a mixer 6 where they are orthogonally modulated in analog fashion by the operation according to equation (1) below. D(t) = I(t) x cos(2π x fc x t) + Q(t) x sin(2π x fc x t) The signal D(t) thus orthogonally modulated is input to a BPF (bandpass filter) 7 where the unrequited component generated in the mixer 6 is removed. The output signal of the BPF 7 is supplied to an up converter 8 where it is converted to a carrier signal of a still higher frequency f'c. The high-frequency transmission signal is transmitted from an antenna 9. Fig. 20 shows an example of a conventional receiving circuit of orthogonal demodulation type. The signal received by an antenna 10 is restored to the original orthogonal modulation signal D(t) by a down converter 11. The orthogonal modulation signal D(t) supplied to an orthogonal demodulator 13 is input to a mixer 14 and converted into a signal of a carrier frequency fc. The mixer 14 processes the signal D(t) in two ways by equations (2) and (3) shown below, and orthogonally demodulates the two types of signals I(t), Q(t) in analog fashion using the orthogonality of the trigonometric function. I(t) = D(t) x cos(2π x fc x t) Q(t) = D(t) x sin(2π x fc x t) The two signals I(t), Q(t) orthogonally demodulated in this way have the unrequited components thereof removed by the analog LPFs 15i, 15q, respectively. The signals I(t), Q(t) are converted into digital signals Id(n), Qd(n) by the A/D converters 16i, 16q, respectively, and supplied to a receiving signal processing circuit 17. The receiving signal processing circuit 17 demodulates the two digital input signals Id(n), Iq(n), and outputs the resulting information code from an output terminal 18. In the conventional analog modulation system described above, the two types of carrier signal used for orthogonal modulation and demodulation, i.e. the two carrier signals expressed by "cos" and "sin" in Figs. 19 and 20, if insufficient in orthogonality (accuracy of π/2 in phase difference), develop inter-code interference between the two types of components and increases the error rate of the demodulated code, resulting in a deteriorated communication quality. In view of this, in the prior art, a mixer of analog configuration regulated to high accuracy is used so that the orthogonal (phase difference) error between the two reference carrier waves assumes a sufficiently small value of 1 degree or less. The conventional system described above fails to take digitization into consideration and poses the problem of difficulty of improving the performance thereof. Specifically, in recent years, schemes such as 64QAM or OFDM with a large number of points more than the conventional BPSK and QPSK schemes have come to be employed. These schemes require a still higher accuracy of orthogonality. The analog technique, however, has its own limit of improving the orthogonality accuracy and therefore is difficult to improve the performance of the transmission system. SUMMARY OF THE INVENTION In view of this, the inventors have studied a digital orthogonal modulator and a digital orthogonal demodulator in which orthogonal modulation and orthogonal demodulation are performed by digital signal processing in order to secure a sufficiently high accuracy required for orthogonality. An example will be explained with reference to Figs. 21 and 22. First, the digital orthogonal modulator of Fig. 21 is a digital version of the orthogonal modulator 3 of analog configuration shown in Fig. 19. In similar fashion, the digital orthogonal demodulator of Fig. 22 is a digital version of the orthogonal demodulator 13 of analog configuration shown in Fig. 20. The circuits other than the orthogonal modulator and the orthogonal demodulator are the same as those of Figs. 19 and 20. Therefore, the configuration and operation of the orthogonal modulator and the orthogonal demodulator will be mainly described below. First, typical signal waveforms of the first digital signal Id(n) and the second digital signal Qd(n) of a sampling frequency fd supplied from the transmission signal processing circuit 2 are illustrated in Figs. 23(a), (b). In Figs. 23 (a), (b), the solid curve represents the signal waveform of the I signal before sampling; and the dashed curve represents the signal waveform of the Q signal before sampling. The corresponding sampling signals are also indicated by solid and dashed arrows, respectively. Of all the signals applied to the digital orthogonal modulator shown in Fig. 21, the first digital signal Id(n) is converted to a signal I'd4(m) of a quadruple sampling frequency 4 x fd by a first quadruple sampling converter 19i in such a manner that three zeros are inserted between the nth sampling value Id(n) and the (n+1)th sampling value Id(n+1) as shown in Fig. 23(c), where m is an integer representing the order of the clock signal for the quadruple sampling operation. The signal I'd4(m) thus converted, as shown typically in Fig. 24, contains the unrequited harmonic components 20. In Fig. 24, the hatched portions show the bands of the required signal information components. The digital LPF 21i, like the conventional LPF 5i shown in Fig. 19, limits the signal I'd4(m) to the bandwidth B while at the same time removing the unrequited harmonic components 20. As a result, the signal waveform of the output signal Id4(m) of the digital LPF 21i assumes a sampling waveform with zeros filled between the signals as shown in Fig. 23(e). This is also the case with the second signal Qd(n). As shown in Fig. 23(d), the second signal Qd(n) is converted into a signal Q'd4(m) of a quadruple frequency 4 x fd by a second quadruple sample converter 19q, limited to the bandwidth B by a digital LPF 21q, and as shown in Fig. 23(f), converted into the signal Qd4(m) with zeros filled therebetween. Assume that the carrier frequency fc of the orthogonal modulation signal is set to fd in this way. Equation (1) indicated above as an operation formula for orthogonal modulation can be expressed as Dd4(m) = Id4(m) x cos(2π x m/4) + Qd4(m) x sin(2π x m/4) In equation (4), the term on the right side containing "cos" assumes values 1 and -1 alternately when m is an even number including zero, and assumes zero when m is an odd number. The term on the right side containing "sin", on the other hand, assumes the values of 1 and -1 alternately when m is an odd number and assumes zero when m is an even number including zero. Therefore, equation (4) can be expressed sequentially in accordance with m, as follows. m = 0 → Dd4(0) = Id4(0) m = 1 → Dd4(1) = Qd4(1) m = 2 → Dd4(2) = -Id4(2) m = 3 → Dd4(3) = -Qd4(3) m = 4 → Dd4(4) = Id4(4) m = 5 → Dd4(5) = Qd4(5) . . . . . . Actually, therefore, the orthogonal modulation can be carried out and the orthogonal modulation signal Dd4(m) as shown by the signal waveform of Fig. 23(g) can be produced by sequentially switching the signals Id4(m), Qd4(m) and signals of opposite polarities -Id4(m), -Q4d(m) without executing the multiplication of equation (4). The digital orthogonal modulator of Fig. 21 uses a digital orthogonal modulation circuit 22 operating according to this method. As shown in Fig. 21, two polarity inverting circuits 22i, 22q and a cyclic switch 22s operating at a frequency fc (= 4 x fd) are used. The signals Id4(m) and Qd4(m) are converted into polarity inverted signals -Id4(m) and -Qd4(m), respectively, by the polarity inverting circuits 22i and 22q. The signals Id4(m), Qd4(m), -Id4(m), -Qd4(m) are extracted selectively sequentially by the clock signal of frequency fc through the switch 22s, thereby producing an orthogonal modulation signal Dd4(m) shown in the waveform diagram of Fig. 23(g). The orthogonal modulation signal Dd4(m) output from the digital orthogonal modulation circuit 22 is then converted into an analog signal by a D/A converter 24. The analog orthogonal modulation signal D(t) with the unrequited harmonic components thereof removed by the BPF 25 is output from the digital orthogonal modulator. In this process, the two digital LPFs 21i, 21q are required to have the same characteristic. It is common practice, therefore, to employ digital LPFs having a nonrecursive (FIR: finite impulse response) type circuit configuration and the same tap coefficient, as shown in Fig. 25. The digital LPF shown in Fig. 25 includes a shift register 26, memories 27-1, 27-2,..., 27-H, multiplier circuits 28-1, 28-2,...., 28-H and a Σ (summing) circuit 29. The shift register 26 includes multiple stages of concatenated memory cells for sequentially transferring and storing input serial signals I'd4(p+1), I'd4(p+2),...., I'd4(p+H), stage by stage, in response to each clock pulse of frequency 4 x fd. The memories 27-1, 27-2,...., 27-H function to store H tap coefficients C 1 , C 2 ,...., CH required for limiting the bandwidth to B. In the above description, p is an arbitrary integer. The shift register 26 executes the operation of equation (5) below for each clock pulse using the tap coefficient values stored in the memories 27-1, 27-2 and so forth, and sequentially outputs the calculated values Id4(p). Id4(p) = C 1 x I'd4(p+1) + C 2 x I'd4(p+2) + C 3 x I'd4(p+3) + ... + ... + C H x I'd4(p+H) In the process, the H multiplier circuits 28-1, 28-2,..., 28-H multiply the tap coefficients C 1 ,...., C H by the signals values I'd4(p+1),..., I'd4(p+H). Further, the Σ circuit 29 includes a plurality of adder circuits and outputs the total sum of the values C 1 x I'd4(p+1) to C H x I'd4(p+H) multiplied in the multiplier circuits 28-1 to 28-H. In this way, the multiplier circuits 28-1 to 28-H function as a digital LPF. Now, the digital orthogonal demodulator of Fig. 22 will be explained. This demodulator carries out orthogonal demodulation by processing the signals in substantially reverse way to the digital orthogonal modulator of Fig. 21. In Fig. 22, the orthogonal modulation signal D(t) output from a down converter 11 (Fig. 20) has the unrequited frequency components thereof removed by the BPF 30. The signal D(t) is sampled at the sampling frequency of 4 x fd by the A/D converter 31 and thus converted into a digital orthogonal modulation signal Dd4(m). The orthogonal modulation signal Dd4(m) thus sampled has a signal waveform as shown in Fig. 26(a) which is identical to that of Fig. 23(g). Assume that the carrier frequency fc of the orthogonal modulation signal is set to fd. Equations (2) and (3) shown as operation formulae for orthogonal demodulation are expressed as equations (6) and (7), respectively. Id4(m) = Dd4(m) x cos(2π x m/4) Qd4(m) = Dd4(m) x sin(2π x m/4) Then, as in equation (4) for the digital orthogonal modulator shown in Fig. 21, the orthogonal demodulation can be performed with a simple circuit configuration. Specifically, equation (6) including "cos" assumes values of 1 and -1 alternately when m is an even number including zero, and assumes zero when m is an odd number. Equation (7) including "sin", on the other hand, assumes values of 1 and -1 alternately when m is an odd number and zero when m is an even number including zero. First, equation (6) assumes the following values sequentially according to m. m = 0 → Dd4(0) = Id4(0) m = 1 → Dd4(1) = 0 m = 2 → Dd4(2) = -Id4(2) m = 3 → Dd4(3) = 0 Then, equation (7) assumes the following values also sequentially according to m. m = 0 → Dd4(0) = 0 m = 1 → Dd4(1) = Qd4(1) m = 2 → Dd4(2) = 0 m = 3 → Dd4(3) = -Qd4(3) m = 4 → Dd4(4)) = 0 In this case, too, the orthogonal demodulation can be accomplished by sequentially switching and independently extracting the signals Id4(m), Qd4(m) and polarity-inverted signals -Id4(m), -Qd4(m) without directly executing the multiplication of equations (6) and (7). Thus, the orthogonal demodulation signals Id4(m) and Qd4(m) are obtained as shown in Figs. 26(b), (c). Fig. 22 shows a digital orthogonal demodulator using a digital orthogonal demodulation circuit 32 operating according to the above-mentioned method. As shown in Fig. 22, this digital orthogonal demodulator includes two polarity inverting circuits 32i, 32q and cyclic switches 32si, 32sq operating at the frequency of fc (= 4 x fd). The signal Dd4(m) from the A/D converter 31 is output as a polarity-inverted signal -Dd4(m) by the polarity inverting circuits 32i, 22q. These signals are sequentially alternated between 0 (35i, 35q) and Dd4(m), -Dd4 (m) for each clock of the frequency fc and selectively output, thereby producing the orthogonal demodulation signals Id4(m), Qd4(m) as shown in Figs. 26(b), (c). In this way, the signal Id4(m) output from the digital orthogonal demodulation circuit 32, as shown in Fig. 26(b), assumes a waveform containing a 0 value for each sampling signal. This portion of 0 value is interpolated by the digital LPF 33i as shown in Fig. 26(d). The signal of Fig. 26(d) is sampled at the sampling frequency fd by the 1/4 sampling converter 34i thereby to output the signal Id(n) orthogonally demodulated as shown in Fig. 26(f). In similar fashion, the signal Qd4(m) output from the digital orthogonal demodulation circuit 32, as shown in Fig. 26(c), assumes a waveform containing a 0 value for each sampling signal. The signal Qd4(m) has the 0 value portion interpolated by the digital LPF 33q as shown in Fig. 26(e). The signal of Fig. 26(e) is then resampled by the 1/4 sample converter 34q thereby to output the signal Qd(n) orthogonally demodulated as shown in Fig. 26(g). As shown in Fig. 25, a nonrecursive (FIR type) circuit having the same coefficient values as the digital orthogonal modulator described with reference to Fig. 21 is used as the digital LPFs 33i and 33q. The nonrecursive digital filter used in this case requires a considerable number of adder circuits and multiplier circuits. The multiplier circuits, which assumes a considerable circuit size, are desirably as few as possible. In the cases of Figs. 21 and 22 which use a nonrecursive digital LPF of Fig. 25, however, many multiplier circuits are required leading to an extremely large circuit size. An increased size of the multiplier circuits is indicative of an increased number of taps of the digital filter. In other words, as many taps as multiplier circuits are required. In forming a digital. filter on a integrated circuit, an increased number of multiplier circuits and an increased number of taps bring about an increased space of the integrated circuit, resulting in an increased manufacturing cost of the filter. The steeper the frequency cutoff characteristic required of the LPF, the more taps (multiplier circuits) are required. In the case of an orthogonal frequency division multiplexing (OFDM) modulation constituting one of the orthogonal modulation schemes, for example, the occupied bandwidth is fully utilized. For the transmission signal not to leak to adjacent other frequency bands, therefore, a digital LPF of at least about 50 taps is required. Since 50 or more taps are required for the digital LPF, the transmission system requires twice as many multiplier circuits, or about 100 multiplier circuits. This is because two LPFs are used for each tap. The nonrecursive digital LPF in the receiving system also requires as many multiplier circuits. Thus, a total of about 200 multiplier circuits are required for the transmission system and the receiving system combined. As long as the information transmission rate remains low, the use of the multiplier circuits by time division can reduce the number of the multiplier circuits actually required to be formed on the filter circuit. With the increase in the transmission rate, however, the parallel operation of all the multiplier circuits is required due to the limited operating speed of each multiplier circuit. It will be necessary, for example, to form as many as 200 multiplier circuits. A simple digitization, therefore, constitutes a stumbling block to a higher transmission rate due to the increased circuit size of the multiplier circuits. The article by G.R.SAPHIRO :"FIR switched-capacitor modulators for discrete QAM" in Proceedings of the International Symposium on Circuits and Systems, Kyoto, June 5-7,1985, pages 1629 - 1632, describes M-ary QAM modulators using a single switched-capacitor FIR structure. The modulators provide shaping of both passbands and stop bands. The published European Patent Application No EP 693 844 A2 (NIPPON TELEGRAPH AND TELEPHONE CORP.) describes a digitized quadrature modulator for receiving I- channel input digital signal and Q-channel input digital signal, and for quadrature modulating the I-channel and Q-channel digital signals by a digital signal processing. The modulator has a digital filter for shaping the spectrum of the I-channel and the Q-channel input digital signals to provide I-channel and Q-channel output signals, complementers for taking the complement of the I-channel and Q-channel output signals to provide I-channel and Q-channel complement signals, and a multiplexer for multiplexing the I-channel and Q-channel output signals from the digital filter and the I-channel and Q-channel complement signals from the complementers to provide a quadrature modulated output signal. The article by X.H.WANG : "Digital IF modulator and demodulator design for transmission over band-limited channels", 3 rd International Conference on Signal Processing, Bejing, China, 14-18 Oct. 1996, pages 1242 - 1245, describes a digital IF quadrature modulator/demodulator used in a hybrid digital and analog 16 QAM transmitter and receiver architecture for upstream transmission over CATV networks. In the implementation of the interpolation filter, each I and Q signal N-tap filter is broken down into four N/4 tap subfilters with a clock speed equal to the symbol rate. The output of the I and Q baseband filter is obtained by sampling each filter in time sequence. By merging the digital mixing with the I and Q channel interpolation filter, the overall digital modulation can be performed by implementing only the odd coefficients of the low pass filter in the I channel and the even coefficients in the Q channel. The object of the invention is to realize an improved orthogonal modulator/demodulator with a non-recursive digital filter so that a digital signal communication system is obtained in which the requirement for a high transmission rate can be met without increasing the circuit size of the digital orthogonal modulator/demodulator. This object is met by the digital signal transmission system described in the independent claims. A further embodiment of the invention is described in the dependent claim. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a block diagram showing an example of a digital orthogonal modulator according to a first embodiment of the invention. Fig. 2 is a signal waveform diagram for explaining the operation of the digital orthogonal modulator according to the first embodiment. Fig. 3 is a model diagram for explaining the operating principle of one of the digital LPFs according to the first embodiment. Fig. 4 is another model diagram for explaining the operating principle of the other digital LPF according to the first embodiment. Fig. 5 is a signal waveform diagram for explaining the operation of the digital orthogonal modulator according to the first embodiment. Fig. 6 is a block diagram showing an example of one of the digital LPFs according to the first embodiment. Fig. 7 is a block diagram showing an example of the other digital LPF according to the first embodiment. Fig. 8 is a block diagram showing an example of the digital orthogonal demodulator according to a second embodiment of the invention. Fig. 9 is a signal waveform diagram for explaining the operation of the digital orthogonal demodulator according to the second embodiment. Fig. 10 is a model diagram for explaining the operating principle of the digital LPF according to the second embodiment. Fig. 11 is another model diagram for explaining the operating principle of the digital LPF according to the second embodiment Fig. 12 is a block diagram showing an example of one of the digital LPFs according to the second embodiment. Fig. 13 is a block diagram showing an example of the other digital LPF according to the second embodiment. Fig. 14 is a signal waveform diagram for explaining the operation of the digital orthogonal demodulator according to the second embodiment. Fig. 15A is a model diagram for explaining the operating principle of the digital LPF according to a third embodiment of the invention. Figs. 15B and 15C are block diagrams showing an example of the digital LPF according to the third embodiment of the invention. Fig. 16A is a model diagram for explaining the operating principle of the digital LPF according to a fourth embodiment of the invention. Figs. 16B is a block diagram showing an example of the digital LPF according to the fourth embodiment of the invention. Fig. 17 is a block diagram for explaining the operating principle of the digital LPF according to a fifth embodiment of the invention. Fig. 18 is a block diagram showing an example of the configuration of the digital LPF according to the fifth embodiment of the invention. Fig. 19 is a block diagram showing an example of the transmission circuit including a digital orthogonal modulator according to the prior art. Fig. 20 is a block diagram showing an example of the receiving circuit including a digital orthogonal demodulator according to the prior art. Fig. 21 is a block diagram showing an example of the orthogonal modulator having a digital configuration. Fig. 22 is a block diagram showing an example of the orthogonal demodulator having a digital configuration. Fig. 23 is a signal waveform diagram for explaining the operation of the orthogonal modulator having a digital configuration. Fig. 24 is a model diagram for explaining the unrequited harmonic components generated by the digital orthogonal modulation. Fig. 25 is a block diagram showing an example of the digital LPF used for the digital orthogonal demodulator. Fig. 26 is a signal waveform diagram for explaining the operation of the orthogonal demodulator having a digital configuration. Fig. 27A is a graph showing the ideal frequency characteristic of the digital LPF. Fig. 27B shows an example of the impulse response curve of the digital LPF. DESCRIPTION OF THE PREFERRED EMBODIMENTS A digital signal transmission system according to the present invention will be explained below in detail with reference to the embodiments shown in the accompanying drawings. First, reference is made to a digital orthogonal modulator according to a first embodiment of the invention. To assure full understanding of the operating principle of the invention, an explanation will be given with reference to the digital orthogonal modulator shown in Fig. 21. As already described, the orthogonal modulation process shown by equation (4) can be realized with a simple switch circuit. Specifically, in the patterns shown in Figs. 2(a), (b) of the signals Id4(m), Qd4(m) output from the digital LPFs 21i, 21q of Fig. 21, the sample values indicated by thick arrows and values with the polarity inverted are alternately selected and output to perform the orthogonal modulation process. Figs. 2(a), (b), (c) are the same as the waveform diagrams of Figs. 23(e), (f), (g), respectively. It should be noted here that the sampling values indicated by thin arrows in the pattern of Figs. 2(a), (b) are not used at all for the orthogonal modulation process. It follows therefore that in the digital LPFs 21i, 21q shown in Fig. 21, only the values at the sampling points indicated by thick arrows in Figs. 2(a), (b) are calculated and output. First, when calculating the value at a sampling point indicated by a thick arrow, or the value Id4(0) in Fig. 2(a), for example, the internal state of the shift register 26 in the digital LPF 21i is as shown in Fig. 3(a). In Fig. 3, the memories of the shift register 26 for storing the values other than zero inserted by the quadruple sample converter 19i are shadowed. In similar manner, when determining the value at another sampling point indicated by thick arrow, or the value Id4(2), for example, the internal state of the shift register 26 is as shown in Fig. 3(b). Specifically, whatever signal is input to the shift register 26, the states of Figs. 3(a), (b) are alternated. Then, the tap coefficients C 2 , C 4 , C 6 ,... C EVEN and so forth are multiplied by zero inserted in any of signal calculations. Actually, therefore, the multiplication between the signal value and the tap coefficient is not required. Thus, the multiplication between only the tap coefficients C 1 , C 3 , C 5 ,... C ODD and so forth and the values on the shift register is required. The same can be said of the signal Qd4(m) shown in Fig. 2(b). In the case of the signal Qd4(m), however, the positions of the sampling points indicated by thick arrows are displaced by one sampling point from those for the signal Id4(m). Therefore, when calculating the values at the sampling points indicated by thick arrows of Fig. 2(b), or the values of Qd4(1) and Qd4(3), for example, the internal state of the shift register 26 in the digital LPF 21q is as shown in Figs. 4(a), (b). Thus, in the case of the signal Qd4(m), only the tap coefficients C 2 , C 4 , C 6 and so forth are multiplied, as in the case of the tap coefficients C 1 , C 3 , C 5 and so forth for the signal Id4(m). In both calculations, the tap coefficients are not actually required to be multiplied with the signal value, since only zero inserted is multiplied. This indicates the possibility of reducing the number of multipliers. Fig. 1 shows a digital orthogonal modulator according to the first embodiment of the invention configured based on the aforementioned recognition. The quadruple sample converters 19i, 19q in the digital orthogonal modulator of Fig. 21 are replaced by double sample converters 19'i, 19'q, the digital LPFs 21i, 21q are replaced by digital LPFs 21'i, 21'q, and the digital orthogonal modulation circuit 22 is replaced by a digital orthogonal modulation circuit 22'. The configuration of the remaining component parts remains the same as in Fig. 21. The double sample converters 19'i, 19'q are supplied with signals Id(n), Qd(n), respectively, of the sampling frequency fd, as shown in Figs. 5(a), (b). The zero is inserted between the nth sampling value and the (n+1)th sampling value so that the signals Id(n), Qd(n) are converted into signals I'd2(k), Q'd2(k) having a double sampling frequency 2 x fd. The signal waveforms of the signals I'd2(k), Q'd2(k) thus converted are shown in Figs. 5(c), (d), respectively. Of these signals, first, the signal I'd2(k) is input to the digital LPF 21'i, and the operation of equation (8) below is executed for each clock pulse of the sampling frequency 2 x fd. Id2(p) = C 1 x I'd2(p+1) + C 3 x I'd2(p+2) + C 5 x I'd2(p+3) + ...... + C H x I'd2(p+R+1) where R is an arbitrary integer, and the number H of terms may be either an even or odd number. In this case, however, H is set to an odd number 2 x R + 1. Thus, the configuration of the digital LPF 21'i is as shown in Fig. 6. The signal Q'd2(k), on the other hand, is input to the digital LPF 21'q, and the operation of equation (9) below is executed for each clock pulse of the sampling frequency 2 x fd. Qd2(p) = C 2 x Q'd2(p+1) + C 4 x Q'd2(p+2) + C 6 x Q'd2(p+3) + ...... + C (H-1) x Q'd2(p+R) Thus, the configuration of the digital LPF 21'q is as shown in Fig. 7. As a result, the signals Id2(k), Qd2(k) output from the digital LPFs 21'i, 21'q, respectively, assume a waveform as shown in Figs. 5(e), (f) or a sampling waveform with zeros inserted. As clear from equations (8) and (9), each equation uses every other tap coefficient extracted from the series of coefficients C 1 , C 2 ,.....,C H in equation (5). As a result, the number of multiplications is about one half that for equation (5). Thus, according to this embodiment, the number of multiplier circuits of the digital LPFs 21'i, 21'q, as seen from Figs. 6 and 7, is about one half that for the digital LPFs 21i, 21q of Fig. 21, respectively. In this way, the circuit size is remarkably reduced. Equations (8) and (9) use different series of coefficients. Combining the coefficient series of equation (8) and the coefficient series of equation (9), therefore, can obtain the same coefficient series as equation (5). The two sets of coefficients give a series of values on a smooth impulse response curve, such as shown in Fig. 27B. Thus, the same performance is exhibited as in the case of Fig. 21 without any adverse effect which otherwise might be caused by the reduction in the number of multiplier circuits. According to this embodiment, H is an odd number, and one of the digital LPF 21'i and the digital LPF 21'q has one more tap than the other. In this case, the number of the tap coefficients C 2 , C 4 and so forth required for determining the signal Qd2(k) in Fig. 5(f) is one tap more or less than the number of tap coefficients C 1 , C 3 and so forth required for determining the signal Id2(k) of Fig. 5(e). For this reason, the signal waveform of Fig. 5(f) is displaced one clock pulse of the clock of the quadruple sampling frequency 4 x fd forward of the signals indicated by thick arrows in Fig. 2(b). In the digital orthogonal modulation circuit 22' according to this embodiment, therefore, as shown in Fig. 1, a delay circuit 22'D of one clock pulse is inserted. This delay circuit 22'D adjusts (delays) the timing of the signal Qd2(k) as shown in Fig. 5(g). Thus, once the orthogonal modulation is carried out by the digital orthogonal modulation circuit 22', as shown in Fig. 5(h), the orthogonal modulation signal Dd4(m) having the same waveform as the one shown in Fig. 23(g) can be produced. The orthogonal modulation signal Dd4(m) output from the digital orthogonal modulation circuit 22' is converted into an analog signal by a D/A converter 24. The orthogonal modulation signal which is now an analog signal is band-limited by a BPF 25, and output from the digital orthogonal modulator as an orthogonal modulation signal D(t). The orthogonal modulation signal D(t) is supplied to an up converter 8 (Fig. 19). According to the first embodiment shown in Fig. 1, as clear from Figs. 6 and 7, the number of taps of the digital LPFs 21'i, 21'q is reduced to one half that of the digital LPFs 21i, 21q used in the circuit of Fig. 21. In this embodiment, in spite of the fact that the circuit size of the digital LPF is remarkably reduced, the characteristic of the orthogonal modulation signal Dd4(m) output remains the same as the characteristic of the orthogonal modulation signal Dd4(m) for the circuit of Fig. 21. In the process, the sampling frequency of the signal input to the digital LPFs 21'i, 21'q is one half that for the circuit of Fig. 21. Therefore, the clock frequency of the drive pulse can also be reduced to one half. On the other hand, the multiplier circuit requires repeating a large number of addition operations for obtaining the multiplication result. By this reason, it is practically very difficult to make a high speed digital filter circuit in the orthogonal modulator. However, according to the embodiment of the present invention, the multiplier circuit can be operated in relatively low speed with a low frequency clock signal, and then digital filter can be easily realized in the orthogonal modulator. Thus, in the digital orthogonal modulator according to the first embodiment which has the same function and performance as the circuit of Fig. 21, the required number of taps of the digital LPF can be reduced by about one half, and therefore the circuit size of the transmission circuit can be remarkably reduced. At the same time, the operating speed of the multiplier circuits can be reduced to one half, and therefore the multiplier circuits can be easily fabricated. Consequently, it is possible to produce a digital signal transmission system which is inexpensive and easy to manufacture. In the first embodiment, an explanation was made about the case in which the number H of taps of the digital LPF is an odd number 2 x R + 1. The first embodiment, however, can be executed also when the number of taps is an even number H = 2 x R. In the latter case, the two digital LPFs 21'i, 21'q have the same number of taps without posing any problem. Now, the digital orthogonal demodulator on the receiving side according to the second embodiment of the invention will be explained. In this case, too, to assure full understanding of the operating principle of the invention, the digital orthogonal demodulator shown in Fig. 22 will be explained first. As described above, the signals Id4(m), Qd4(m) output from the digital LPFs 33i, 33q of the demodulator shown in Fig. 22 are supplied to the 1/4 sample converters 34i, 34q, respectively, where the sampling values indicated by thick arrows in Figs. 9(c), (d) are sequentially selected and output as orthogonal demodulation signals Id(n), Qd(n). Figs. 9(a) to 9(f) show the same waveforms as Figs. 26(b) to 26(g), respectively. First, as in the foregoing case, it should be noted that the sampling values indicated by thin arrows in the waveform diagram of Figs. 9(c), (d) are not used at all. Thus, in the digital LPFs 33i, 33q, only the values at the sampling points indicated by thick arrows in Figs. 9(c), (d) are actually calculated and output. When calculating the value at a sampling point indicated by thick arrow, or the value of Qd4(0), for example, in Figs. 9(c), (d), the internal state of the shift register 26 in the digital LPF 33q is as shown in Fig. 10. In this case, too, as in the case of Fig. 3, the memories storing the values other than zero inserted are shadowed. The tap coefficients C 1 , C 3 , C 5 , and so forth are multiplied by zero inserted, and therefore need not actually be multiplied by the signal value. In other words, the insertion of zero values in the digital orthogonal demodulation circuit 32 is not required, but only the tap coefficients C 2 , C 4 , C 6 and so forth can be multiplied. This is also the case with the signal Id4(m) of Fig. 9(c). In the case of the signal Id4(m), however, the positions of the sampling points assuming a value other than zero are displaced in timing by one sampling point from those for the signal Qd4(m). Therefore, when calculating the value at a sampling point indicated by thick arrow in Fig. 9(c), or the value Id4(0), for example, the shift register 26 in the digital LPF 33i assumes the internal state as shown in Fig. 11. Thus, in processing the signal Id4(m), the tap coefficients C 1 , C 3 , C 5 and so forth not used for processing the signal Qd4(m) are used. For the tap coefficients C 2 , C 4 , C 6 and so forth used for processing the signal Qd4(m), however, zero is multiplied, and therefore, the multiplication of the signal value and the tap coefficients is not actually required. In the case of the signal Id4(m) in Fig. 9(c), the values at the sampling points indicated by thick arrows already exist in the signal of Fig. 9(a), and the LPF for interpolating the values at the positions of zero value appears to be unnecessary. After orthogonal demodulation, however, the frequency characteristics of the signal Id(n) and the signal Qd(n) are required to be identical to each other. For this purpose, the digital LPF 33i having the same characteristic as the digital LPF 33q is used to secure the same frequency characteristic of the two types of signals. The second embodiment of the present invention is configured based on the foregoing recognition. Now, a circuit configuration of the digital orthogonal demodulator according to this embodiment will be explained with reference to Fig. 8. The digital orthogonal demodulator shown in Fig. 8 includes a digital orthogonal demodulation circuit 32' in place of the digital orthogonal demodulation circuit 32 in the digital orthogonal demodulator of Fig. 22, digital LPFs 33'i, 33'q in place of the digital LPFs 33i, 33q, and 1/2 sample converters 34'i, 34'q in place of the 1/4 sample converters 34i, 34q. The configuration of the other component parts is basically the same as that of the corresponding ones in Fig. 22. The signal Dd4(m) of Fig. 14(a) output from the A/D converter 31 is separated into two routes before being input to the digital orthogonal demodulation circuit 32'. In one of the routes, the signal is delayed by one clock of the sampling frequency 4 x fd in a delay circuit 32'D and output as a delay signal shown in Fig. 14(b). The signal not delayed shown in Fig. 14(a), the delayed signal of Fig. 14(b), and the signals of the inverted polarities thereof, i.e. a total of four types of signals are sequentially sampled by switches 32'si, 32'sq operating at the frequency 2 x fd, and thus converted into the signal Id2(k) shown in Fig. 14(c) and the signal Qd2(k) shown in Fig. 14(d), respectively. In the diagrams, characters S/H designate a sample-and-hold circuit. Then, first among these signals, the signal Id2(k) is input to the digital LPF 33'i, in which it is processed for each clock pulse of the sampling frequency 2 x fd according to equation (10) below and assumes the signal I'd2(k) shown in Fig. 14(e). I'd2(p) = C 1 x Id2(p+1) + C 3 x Id2(p+2) + C 5 x Id2(p+3) + ...... + C H x Id2(p+R+1) In equation (10), the number H of terms may be either odd or even. In this case, however, an odd number H = 2•R + 1 is employed, and therefore the digital LPF 33'i assumes the configuration shown in Fig. 12. The signal Qd2(k), on the other hand, is input to the digital LPF 33'q and, by being processed for each clock pulse at the sampling frequency 2 x fd according to equation (11) below, converted into the signal Q'd2(k) shown in Fig. 14(f). Q'd2(p) = C 2 x Qd2(p+1) + C 4 x Qd2(p+2) + C 6 x Qd2(p+3) + ...... + C (H-1) x Qd2(p+R) Thus, the digital LPF 33'q assumes the configuration shown in Fig. 13. In both of these arithmetic operations, as clear from equations (10) and (11), every other tap coefficient is extracted from a series of the coefficients C 1 , C 2 ,....,C H of equation (5). According to this embodiment, therefore, the number of multiplications is about one half smaller than that for equation (5). Also, in equations (10) and (11), different series of coefficients are used from each other. When the series of coefficients of equation (10) is combined with that of equation (11), therefore, the same series of coefficients is obtained as that of equation (5). When H is an odd number as in this embodiment, one of the digital LPF 33'i and the digital LPF 33'q has one more tap than the other. The signal I'd2(k) and the signal Q'd2(k) output from the digital LPFs 33'i, 33'q, respectively, are sampled at the frequency 2 x fd in 1/2 sample circuits 34'i, 34'q, respectively. The resulting orthogonal demodulation signals Id(n), Iq(n) of a still lower sampling frequency fd produced by the 1/2 sample circuits are converted into analog signals and supplied to a receiving signal processing circuit 17 (Fig. 20). In the process, the orthogonal demodulation signals Id(n), Iq(n) assume the signal waveforms shown in Figs. 14(g), (h), respectively. Also according to this embodiment, an explanation was made about the case in which the number H of taps of the digital LPF is an odd number given by 2•R + 1. Nevertheless, the embodiment can be executed with an even number of taps, i.e. H = 2 x R. In such a case, the number of taps is the same for the two digital LPFs 33'i, 33'q, which poses no problem. According to the second embodiment of Fig. 8, as seen from Figs. 12 and 13, the number of taps of the digital LPFs 33'i, 33'q can be reduced to one half that for the digital LPFs 33i, 33q used in the circuit of Fig. 22. In spite of this, the characteristic and hence the performance of the output orthogonal demodulation signals Id(n), Qd(n) remains exactly the same as that of the signal output from the circuit of Fig. 22. In addition, the sampling frequency of the signal input to the digital LPF is reduced to one half, and therefore the clock frequency of the drive pulse can also be reduced by one half. Consequently, in the digital orthogonal demodulator according to the second embodiment having the same function and the same performance as the circuit of Fig. 22, the required number of taps of the digital LPF can be reduced remarkably, and therefore the circuit size of the transmission is also reduced. Further, the multiplier circuit not good at the high-speed operation can be reduced to about one half in operating speed. As a result, a digital signal transmission system easy to manufacture and inexpensive can be readily produced. Now, third to fifth embodiments of the invention will be explained. The embodiments described below represent a method of further reducing the number of multiplier circuits required for the digital LPFs 21'i, 21'q, 33'i, 33'q in the embodiments of Figs. 1 and 8. The configuration of the component parts other than the digital LPF remains the same as that of the above-mentioned embodiments. Therefore, the configuration of the digital LPFs will be mainly explained below. First, the third embodiment will be described. Before entering the detailed explanation, the concept of the digital LPF used in the third embodiment will be explained. In this case, a filter having the characteristic expressed by equation (5) having the series of coefficients symmetric about the center coefficient is designed. Specifically, the filter is designed to hold the relations C 1 =C H , C 2 = C H-1 , C 3 = C H-2 ,....C n = C H-(n-1) among the coefficients. In the case where the number H of terms is odd and 2•R + 1, however, only the coefficient C R+1 has no corresponding coefficient. In equation (8), on the other hand, every other coefficient C 1 , C 3 , C 5 ,...., C H is extracted from the coefficients C 1 , C 2 , C 3 , C 4 , C 5 and so forth of equation (5). Therefore, the same relations of C 1 = C H , C 3 = C H-2 and so forth are maintained also among the coefficients extracted. Thus, a filter having symmetric coefficients can be produced. In similar manner, the coefficients extracted according to equation (9) can produce a filter having symmetric coefficients. Such a filter having symmetric coefficients can be illustrated as shown in Fig. 15A. In the filter having symmetric coefficients as shown in Fig. 15A, the shift registers included in the digital LPF are arranged not simply forwardly but reversed from an intermediate point as shown in Fig. 15B or Fig. 15C. Further, adder circuits 31-1 to 31-4 are inserted for adding the signal values returned and the signal values newly input, and the resulting sum is multiplied by a common coefficient in the multiplier circuits 28-1 to 28-9. In this way, too, the digital LPF can be configured. The third embodiment of the invention, therefore, uses a digital LPF having the circuit configuration as shown in Figs. 15B and 15C. When the number H of taps is odd, the number of taps of one of the two series of tap coefficients is also odd, and therefore a circuit configuration as shown in Fig. 15B is obtained. For the other series having an even number of taps, on the other hand, as shown in Fig. 15C, the circuit configuration is such that the coefficients are reversed from midway. In the digital LPF having a circuit configuration shown in Figs. 15B and 15C, therefore, the number of multiplier circuits can be further reduced by one half from that for the digital LPFs shown in Figs. 6, 7, 12, 13. As a result, as compared with the digital LPF used in the circuits of Figs. 21, 22, the total number of multiplier circuits can be reduced to one fourth. According to the embodiment shown in Figs. 15B, 15C, the adder circuits 31-1 and so forth are required. Since the adder circuit has a considerably simpler circuit configuration than the multiplier circuit, however, the increase in the circuit size by the adder circuits poses no substantial problem. According to the third embodiment using the digital LPF having the circuit configuration shown in Figs. 15B, 15C, therefore, there is provided a transmission system having a further reduced circuit size while having the same function and performance as the circuits of Figs. 21, 22. Now, a fourth embodiment of the invention will be explained. The concept of the digital LPF according to the fourth embodiment is to reduce the number of multiplier circuits taking advantage of the fact that the signals input to the digital LPF, i.e. the signals shown in Figs. 5(c), (d) still contain sampling points of zero value. Fig. 16A shows a typical state of the shift register in the digital LPF when the signal of Fig. 5(c) is input thereto. As described above, in Fig. 16A, the memories other than shadowed simply store zero regardless of whatever signals are input, and therefore are not actually required to carry out the multiplication. According as the signal is transferred in the shift register 26, one series of coefficients C 1 , C 5 , C 9 and so forth and the other series of coefficients C 3 , C 7 , C 11 , and so forth are alternately multiplied by the signal values of the memories shadowed. In the digital LPF according to the fourth embodiment, therefore, as shown in Fig. 16B, every other memory of the shift register 26 is removed. Further, one series of tap coefficients and the other series of tap coefficients are switched by switches 42-1 to 42-5. Thus, the switches 42-1 and so forth are operated in synchronism with the signal shift in the shift register 26. At the same time, the process of inserting zero values in the input signal is eliminated, so that the signals Id(n), Qd(n) are input directly to the LPF. Specifically, the double sample converters 19'i, 19'q of Fig. 1 are eliminated. Each time a new signal value is input and the signal is shifted by one memory in the shift register 26, the switches 42-1 and so forth are operated while suspending the shifting, thereby multiplying the signals of the memories by the two series of coefficients. This switching operation exhibits substantially the same function as the double sampling. According to the fourth embodiment, therefore, the number of multiplier circuits of the digital LPF can be further reduced by one half that of the digital LPF of the first embodiment. In other words, according to the fourth embodiment, while maintaining the same function and performance as the circuit of Fig. 21, the number of multiplier circuits of the digital LPF can be reduced as remarkably as to one fourth, so that the circuit size of the digital signal transmission system can be correspondingly reduced. Now, a fifth embodiment of the invention will be explained. In the fifth embodiment, among the digital LPFs of the third embodiment, the number of the multiplier circuits of digital LPF having an odd number of taps in total can be further reduced by one half. This is equivalent to an application of the configuration of the circuit of Fig. 16B according to the fourth embodiment to the concept of the circuit shown in Figs. 15B, 15C according to the third embodiment. First, when the signal of Fig. 5(c) is applied to the circuit of Fig. 15B, the shift register 26 assumes the state shown in Fig. 17(a). After that, when the next signal is applied and the signal of the shift register shifts by one stage, the state changes to the one shown in Fig. 17(b). From Figs. 17(a), (b), the following fact is known. Specifically, the coefficients multiplied by the values other than zero stored in the shift register are seen to alternate between the two series of coefficients each time the shift register shifts. Like in Fig. 16B according to the fourth embodiment, therefore, as shown in Fig. 18, switches 43-1, 43-2 are inserted, while at the same time inserting no zero value in the input signal so that the signal is input continuously. In other words, the double sample converters 19'i, 19'q are eliminated. Each time the next signal is input, the switches 43-1, etc. are operated while suspending the shifting, so that the two series of coefficients are multiplied respectively. According to the fifth embodiment, therefore, the number of multiplier circuits required for the digital LPF can be further reduced by one half as compared with the digital LPF having an odd number of taps in the third embodiment. Specifically, while maintaining the same function and the same performance as the circuit of Fig. 21, the number of multiplier circuits required for one of the two digital LPFs can be reduced as remarkably as to one eighth. In the fifth embodiment, the number of multiplier circuits can be reduced only for one of the two digital LPFs. The circuit size of the multiplier circuits is so large that the simple reduction in the number of multiplier circuits of one of the digital LPFs can lead to a considerable reduction in the circuit size of the whole system. For the filter having the characteristic given by equation (5), if designed to have an even number H (= 2 x R) of terms and to have symmetric coefficients, the number of multiplier circuits cannot be reduced unlike in the third embodiment. This is by reason of the fact that the relations between the coefficients are given as C 1 = C H , C 2 = C H-1 ,C 3 = C H-2 ,....C R = C R+1 , and therefore the first series of coefficients composed of every other one coefficient is given as C 1 , C 3 ,..., C H-1 , while the second series of coefficients as C 2 , C 4 ,...,C H . One of the two series of the coefficients fails to be symmetric, and therefore this embodiment fails to produce the same effect as the third embodiment. Even in such a case, however, if the order of the second series of coefficients is reversed, the resulting series of coefficients C H ,....,C 4 , C 2 is equal to that of the first series of coefficients. In this case, therefore, the circuit size can be reduced by sharing the coefficient memories. A method of determining the values of the tap coefficient series C 1 , C 2 , C 3 ,..., C H in each of the embodiments described above will be explained below with reference to Figs. 27A, 27B. Fig. 27A shows a target frequency characteristic of the digital LPF. The cut-off area of the frequency characteristic of an actual LPF probably has a more gentle slope than shown. Given such a target frequency characteristic, an impulse response characteristic curve is determined as obtained when an impulse is input to a filter of this characteristic. The inverse Fourier transformation of the target frequency characteristic produces the impulse response characteristic curve shown in Fig. 27B. About the peak point of the impulse response curve, the series of H numerical values are sampled symmetrically at intervals of the clock period dt of the digital signal. In the case shown in Fig. 27B, H = 9, and therefore the series of numerical values C 1 , C 2 , C 3 , C 4 ,...C 9 are obtained. This series C 1 , C 2 , C 3 , C 4 ,...C H is divided into the even numbered series C 2 , C 4 , C 6 ,...C 2R and the odd numbered series C 1 , C 3 ,...C 2R+1 . The even numbered series C 2 , C 4 , C 6 ,...C 2R constitute the tap coefficient series for one of the digital LPFs, and the odd numbered series C 1 , C 3 ,...C 2R+1 constitute the tap coefficient series for the other LPF. The circuit size and the power consumption of the digital orthogonal modulation circuit and the digital orthogonal demodulation circuit are determined substantially by the number of multiplier circuits. In the case where each LPF in the circuit of Fig. 21 requires 50 taps, for example, one LPF requires 50 multiplier circuits. Thus, the two LPFs for I and Q signals require a total of 100 multiplier circuits which are required to be operated at the clock frequency of 80 MHz for quadruple samples. According to the first embodiment of the invention described above, in contrast, the number of taps for each LPF can be reduced to about 25 or about one half. Therefore, the number of multiplier circuits required for the two LPF multiplier circuits of I and Q signals is only 50 or about one half that required by the prior art. The circuit space can thus be reduced to about one half that of the prior art. Specifically, the circuit of Fig. 21, which has hitherto required two IC chips, uses only one IC chip. Also, the processing speed can be reduced from the clock frequency of 80 MHz for the quadruple samples in the circuit of Fig. 21 to the clock frequency of 40 MHz of double samples for the first embodiment of the invention. The resulting power consumption is one half smaller, which combined with the fact that the number of multiplier circuits is one half less, results in the decrease in power consumption to as small as one fourth. In similar fashion, according to the third embodiment described above, the number of multiplier circuits can be reduced to about 25 or one fourth, and therefore the circuit space can be reduced to one fourth of that required for the prior art, and the power consumption to one eighth of that required for the prior art. It will thus be understood from the foregoing description that according to this invention, the circuit size of the digital orthogonal modulator/demodulator can be remarkably reduced, with the result that the circuit size of both the transmitter and the receiver can be remarkably reduced, thereby sufficiently reducing the size and cost of the digital signal transmission system. Also, according to this invention, the operating speed can be reduced to one half, and therefore, in spite of the fact that the multiplier circuits not good at high-speed operation are employed, a transmission system easy to manufacture and low in cost is provided.

Claims: A digital signal transmission system using an orthogonal modulation method, comprising: first and second non-recursive digital low-pass filter circuits (21'i, 21'q) for passing only a predetermined frequency band component of the output signal of a first digital signal (Id(n)) and a second digital signal (Qd(n)) sampled at a first sampling rate and having phases orthogonal to each other; first and second polarity inverting circuits (22i, 22q) for inverting the polarity of the outputs of said first and second digital low-pass filter circuits; and a switching circuit (22s) for selectively and alternately outputting the outputs of said first and second digital low-pass filer circuits and the outputs of said first and second polarity inverting circuits; wherein each of said first and second non-recursive digital low-pass filters includes a shift register (26) having a row of a plurality of interconnected memory cells supplied with the output of selected one of said first and second digital signals, a plurality of memories (27-1 to 27-9) for storing the tap coefficients corresponding to the cells of said shift register, and a plurality of multipliers (28-1 to 28-9) for multiplying the digital signal of each cell of said shift register with said tap coefficient corresponding to each of said cells; characterized in that assuming that the tap coefficients arranged sequentially on a predetermined impulse response curve for said low-pass filter are expressed as C 1 , C 2 , C 3 , .... C H , the tap coefficients of the cell row for one of said first and second digital filters are arranged as C 1 , C 3 , C 5 , ...., C ODD and the tap coefficients of the cell row for the other digital filter are arranged as C 2 , C 4 ; C 6 , ..., C EVEN , where H is an arbitrary positive integer not less than 2; and wherein two different tap coefficients adjacent to each cell of said shift register are set in one of said first and second digital low-pass filters; said digital signal transmission system further comprising a plurality of switches (42-1, 42-2, ...) for alternately selecting and applying said two tap coefficients to said multipliers. A digital signal transmission system according to claim 1, assuming the tap coefficients arranged sequentially on a predetennined impulse response curve for said low-pass filters are expressed as C 1 , C 2 , C 3 , ..., C H , the tap coefficients are set in such relations that C 1 = C H , C 2 = C H-1 , C 3 = C H-2...., C n = C H-(n-1) , the tap coefficients of the cell row of one of said first and second digital filters are arranged as C 1 , C 3 , C 5 , ..., C 2R+1 , and the tap coefficients of the cell row of the other digital filter are arranged as C 2 , C 4 , C 6 , ..., C 2R , where H is an arbitrary positive integer not less than 2, n is an arbitrary positive integer not less than 1 and R is an arbitrary positive integer; wherein each of said first and second digital filters further includes a plurality of adders (51-1, 51-2) for adding the value of the n-th cell and the value of the (H-(n-1)))th cell, and said multipliers multiply the outputs of said adders by said tap coefficients, respectively. A digital signal receiving system for orthogonally demodulating an orthogonally modulated signal, comprising: a delay circuit (32'D) for producing a second digital signal delayed by a predetermined time behind a first digital signal (Dd4(m)) of an orthogonally modulated first sampling rate (4fd); the first and second polarity inverting circuits (32i, 32q) for inverting the polarity of each of said first and second digital signals; a first switching circuit (32'sq) for producing said first digital signal and the output signal of said first polarity inverting circuit alternately; a second switching circuit (32'si) for producing said second digital signal and the output signal of said second polarity inverting circuit alternately; first and second non-recursive digital low-pass filter circuits (33'i, 33'q) for passing only a predetermined frequency band component of the output signals of said first and second switching circuits; and first and second sampling rate converters (34'i, 34'q) for converting the output signals of said first and second non-recursive digital low-pass filter circuits into a signal sampled at the rate one half of said first sampling rate and outputting two digital signals (Id(n), Qd(n)) sampled at the rate of one half and having mutually orthogonal phases, characterized by that each of said first and second non-recursive digital low-pass filters includes a shift register (26) having a row of a plurality of interconnected memory cells supplied with the outputs of said switching circuits, a plurality of memories (27-1 to 27H) for storing the tap coefficients corresponding to the cells of said shift register, respectively, and a plurality of multipliers (28-1 to 28-H) for multiplying the digital signal of each cell and assuming that the tap coefficients arranged sequentially on a predetermined impulse response curve for said low-pass filters are expressed as C 1 , C 2 , C 3 , ..., C H , the tap coefficients of the cell row for one of said first and second digital filters are arranged as C 1 , C 3 , C 5 , ..., C ODD and the tap coefficients of the cell row of the other digital filter are arranged as C 2 , C 4 , C 6 , ..., C EVEN , where H is an arbitrary positive integer not less than 2; and wherein two different tap coefficients adjacent to each cell of said shift register are set in one of said first and second digital low-pass filters; said digital signal transmission system further comprising a plurality of switches (42-1, 42-2, ...) for alternately selecting and applying said two tap coefficients to said multipliers.

Inventors: AKIYAMA TOSHIYUKI, MIYASHITA ATSUSHI, TSUKAMOTO NOBUO, AKIYAMA, TOSHIYUKI, MIYASHITA, ATSUSHI, TSUKAMOTO, NOBUO
Applicants: HITACHI ELECTRONICS, HITACHI DENSHI KABUSHIKI KAISHA
Application year: 1999
Main classification: H04L25
IPC codes: H04L27, H04L25