Semiconductor integrated circuit

Abstract: A cut-off state of a carrier signal or a carrier signal outside an effective range of a frequency is detected by a carrier detector, and a signal switching circuit inputs a clock 2 from an external device into a phase comparator in place of the carrier signal, with which a locked state is maintained in a PLL comprising the phase comparator, a charge pump, a loop filter, a voltage control oscillator, and a 1/N divider, so that a high-speed locking operation is realized to another appropriate carrier signal.

Description: FIELD OF THE INVENTION The present invention relates to a semiconductor integrated circuit for receiving a specified signal such as a carrier signal and a feedback signal outputted from a voltage control oscillator for outputting a synchronous signal based on the specified signal, comparing the phase of the specified signal to the phase of the feedback signal and outputting a comparison signal indicating a result of comparison to the voltage control oscillator, and more specifically to a semiconductor integrated circuit for forming a PLL (Phase-Locked Loop) to perform a locking operation. 'INTEGRATABLE LOSS-OF-OSCSILLATOR CIRCUIT FOR USE WITH STANDBY SPARING IN CONJUNCTION WITH PHASE-LOCKED LOOP BUFFERING OF SYSTEM OSCILLATOR' IBM TECHNICAL DISCLOSURE BULLETING; US,IBM CORP. NEW YORK, vol. 35, no. 4A, 1 September 1992 (1992-09-01), pages 406-409, XP000314814 ISSN: 0018-8689 disdoses an integrated circuit according to the upper dause of claim 1. BACKGROUND OF THE INVENTION Fig. 1 is a block diagram showing schematic configuration of a PLL circuit based on the conventional technology. In Fig. 1, the conventional type of PLL circuit comprises a phase comparator 102, a charge pump 103, a loop filter 104, a voltage control oscillator 105, and a 1/N divider 106. Herein, especially a PLL circuit for receiving a carrier signal indicating an FM input signal as an input signal and obtaining a synchronous signal to this carrier signal is described. In Fig. 1, the phase comparator 102 compares a timing of the rising point of the received carrier signal to that of an oscillation signal received from the voltage control oscillator 105 through the 1/N divider 106 (an oscillation signal received from the voltage control oscillator 105 through the 1/N divider 106 is referred to as an internal oscillation signal hereinafter), and when an rising of the internal oscillation signal is delayed as compared to the carrier signal, namely when the frequency of the internal oscillation signal is lower than the frequency of the carrier signal inputs a signal UP as a low level into the gate of a P channel type of MOS transistor 112 in the charge pump 103 during that period. On the other hand, when the rising of the internal oscillation signal is leading the carrier signal, namely when a frequency of the internal oscillation signal is higher than the frequency of the carrier signal inputs a signal DOWN as a high level into the gate of a N channel type of MOS transistor 113 in the charge pump 103 during that period. The charge pump 103 is configured so that a current source 111, the P channel type of MOS transistor 112, the N channel type of MOS transistor 113, and a current source 114 are serially connected to each other between a power unit and the ground, and a node (node N) of the MOS transistor 112 and MOS transistor 113 is connected to the voltage control oscillator 105 through the loop filter 104. When a signal UP indicating a low level is inputted into the gate of the MOS transistor 112 the MOS transistor 112 is turned ON and a positive charge is supplied from the current source 111 to the node N. Namely, a positive charge is supplied to the loop filter 104 that is provided in the next stage. The amplitude of this positive charge is obtained by integrating the current values for the current source 111 over a period of time for which the signal UP keeps on indicating the low level. On the other hand, when a signal DOWN indicating a high level is inputted into the gate of the MOS transistor 113, the MOS transistor 113 is turned on and a negative charge is supplied from the current source 114 to the node N. Namely, a negative charge is supplied to the loop filter 104 provided in the next stage. The amplitude of this negative charge is obtained by integrating the current values for the current source 114 over a period of time for which the signal DOWN keeps on indicating the high level. The loop filter 104 is configured so that a resistor 115 and a capacitor 116 are serially connected to each other between a node N and the ground and it accumulates the charge supplied from the charge pump 103 in the capacitor 116 through the resistor 115 and generates a control voltage for controlling the voltage control oscillator 105 provided in the next stage. The voltage control oscillator 105 is an oscillator for outputting a signal with a frequency decided according to a control voltage, and can obtain this oscillation signal as a synchronous signal. Further, this oscillation signal is inputted into the 1/N divider 106. The 1/N divider 106 subjects the oscillation signal from the voltage control oscillator 105 to 1/N-division so that the frequency of the oscillation signal from the voltage control oscillator 105 coincides with the frequency of the carrier signal, and outputs the subjected signal as an internal oscillation signal as described above. This internal oscillation signal is inputted again into the phase comparator 102, which effects formation of a negative feedback loop for receiving an output signal as an input signal again. Thus, the PLL circuit increases the frequency of the internal oscillation signal by feeding a positive voltage corresponding to the phase difference to the voltage control oscillator 105 as a control signal when the phase of the internal oscillation signal is delayed with respect to the carrier signal. Namely, a higher frequency can make the phase lead. When the phase of the internal oscillation signal leads the carrier signal the frequency of the internal oscillation signal is lowered by feeding a negative voltage corresponding to the phase difference to the voltage control oscillator 105 as a control signal. Namely, a lower frequency can make the phase delayed. By the action of negative feedback described above, the frequency of the internal oscillation signal coincides with the carrier signal in its frequency as well as phase thereof, therefore, a synchronous signal that accurately indicates the frequency of the carrier signal can be outputted. The state where the frequency of this carrier signal coincides with that of the internal oscillation signal is termed as a locked state, and the period of time required to reach this locked state is termed as lock-up time. In the PLL circuit shown in Fig. 1, operations of the charge pump 103 as well as the loop filter 104 can equivalently be realized by a digital circuit and there has been distributed a digital PLL obtained by changing the configuration including those components described above, phase comparator 102, voltage control oscillator 105, and 1/N divider 106 to a digital format. The digital PLL, especially a PLL-IC obtained by forming the digital PLL to an IC is applied in a digital system such as an FSK modem demodulator for demodulating an A/D converted carrier signal and a frequency synthesizer for a transceiver. However, in the conventional type of PLL circuit, a locked stage is unlocked when a carrier signal is not inputted because of its being shut off due to an external factor or the like or when a carrier signal outside an effective range of a frequency is inputted, and when an appropriate carrier signal is again inputted a sequential operation for reaching the locked state again (described a locking operation hereinafter) is required to be performed. As described above, a long time is required for the lock-up operation, therefore, a synchronous signal can not speedily be obtained. US-A-5 410 572 discloses an other phase locked loop circuit for generating an output signal from a reference signal at a frequency equal to a multipte of the frequency of said reference signal. SUMMARY OF THE INVENTION The present invention was made to solve the problems described above, and it is an object of the present invention to perform a high-speed locking operation and realize a high-speed and stable feedback loop operation when an appropriate carrier signal is inputted again after entry of a carrier signal is cut off or a carrier signal outside an effective range of a frequency is inputted. In order to solve the above problems and achieve the object, in the present invention, a semiconductor integrated circuit for comparing a phase of a specified signal (such as a carrier signal) to that of an internal oscillation signal (a feedback signal) outputted from a voltage control oscillator by a phase comparing unit, and receiving a synchronous signal in synchronism to a carrier signal by inputting a result of the comparison in this phase comparing unit, namely a comparison signal indicating a phase difference between the specified signal and internal oscillation signal to be supplied back to the voltage control oscillator; the semiconductor integrated circuit comprises an oscillating state detector for detecting an oscillating state of the specified signal; and a signal switch for switching the specified signal or the comparison signal outputted from the phase comparing unit to a signal for maintaining the internal oscillation signal having been outputted up to the time just before switching from the voltage control oscillator according to the oscillating state detected by the oscillating state detector, namely to a control signal inputted into the voltage control oscillator to make the oscillator keep on outputting the internal oscillation signal. With the above invention, an oscillating state of the specified signal is detected by the carrier detector, and the specified signal or the comparison signal is switched to a signal for maintaining oscillation and output of an internal oscillation signal outputted from the voltage control oscillator according to the detected oscillating state, so that, for example, when the specified signal is not detected or when a signal outside a specified range of a frequency is inputted, the internal oscillation signal is not cut off by inputting a signal for making the voltage control oscillator keep on outputting an internal oscillation signal having been outputted up to the time just before switching from the voltage control oscillator therein, therefore, when a normal specified signal is inputted again, a locking operation can be speeded up as compared to the case where a feedback loop operation is started from the state in which the internal oscillation signal is not outputted from the voltage control oscillator, namely from the state in which there is no feedback signal. According to one feature of the present invention, a semiconductor integrated circuit for comparing a phase of a specified signal to that of an internal oscillation signal outputted from a voltage control oscillator by a phase comparing unit, and receiving a synchronous signal in synchronism to a specified signal by inputting a result of the comparison in this phase comparing unit, namely a comparison signal indicating a phase difference between the specified signal and internal oscillation signal to be supplied back to the voltage control oscillator; the semiconductor integrated circuit comprises an oscillating state detector for detecting an oscillating state of the specified signal; and a signal switch for switching entry to the phase comparing unit from the specified signal to a previously-prepared signal (clock 2) with a specified frequency according to the oscillating state detected by the oscillating state detector. With the above invention, an oscillating state of the specified signal is detected by the oscillating state detector, and the specified signal is switched to the clock 2 to be inputted into the phase comparing unit according to the detected oscillating state, so that, for example, even when a specified signal is not detected or when a signal outside a specified range of a frequency is inputted, the locked state is not unlocked, therefore, a lock-up time required when an effective signal is detected again can be reduced, which allows a high-speed and stable feedback loop operation to be realized. According to one feature of the present invention, a semiconductor integrated circuit for comparing a phase of a specified signal to that of an internal oscillation signal outputted from a voltage control oscillator by a phase comparing unit, and receiving a synchronous signal in synchronism to a specified signal by inputting a result of the comparison in this phase comparing unit, namely a comparison signal indicating a phase difference between the specified signal and internal oscillation signal to be supplied back to the voltage control oscillator; the semiconductor integrated circuit comprises an oscillating state detector for detecting an oscillating state of the specified signal; and a signal switch for switching the comparison signal outputted from the phase comparing unit to a signal generated depending on a constant voltage source or a constant current source according to the oscillating state detected by the oscillating state detector. With the above invention, an oscillating state of the specified signal is detected and the comparison signal is switched to a signal generated depending on the constant voltage source for supplying a specified voltage or the constant current source for supplying a specified charge according to the detected oscillating state, so that, for example, even when a specified signal is not detected or when a signal outside a specified range of a frequency is inputted, the locked state is not unlocked, therefore, a lock-up time required when an effective signal is detected again can be reduced, which allows a high-speed and stable feedback loop operation to be realized. According to one feature of the present invention, a semiconductor integrated circuit for comparing a phase of a specified signal to that of an internal oscillation signal outputted from a voltage control oscillator by a phase comparing unit, and receiving a synchronous signal in synchronism to a specified signal by inputting a result of the comparison in this phase comparing unit, namely a comparison signal indicating a phase difference between the specified signal and internal oscillation signal to be supplied back to the voltage control oscillator; the semiconductor integrated circuit comprises a holding unit for holding therein the comparison signal outputted from the phase comparing unit; an oscillating state detector for detecting an oscillating state of the specified signal; and a signal switch for switching the comparison signal to a voltage held in the holding unit according to the oscillating state detected by the oscillating state detector. With the above invention, the comparison signal outputted from the phase comparing unit is held in the holding unit, and the signal switch switches entry to a loop filter or the voltage control oscillator from the comparison signal to a voltage held in the holding unit according to the oscillating state of the specified signal detected by the oscillating state detector, so that, for example, even when a specified signal is not detected or when a signal outside a specified range of a frequency is inputted, the locked state is not unlocked, and a feedback signal according to the comparison signal in the previous locked state is inputted, therefore, a lock-up time required when an effective signal is detected again can further be reduced, which allows a high-speed and stable feedback loop operation to be realized. According to one feature of the present invention, a semiconductor integrated circuit in addition has a oscillating state detector which checks presence of the specified signal and/or a frequency of the specified signal, and outputs, when it is determined that the specified signal is not being inputted or that a frequency of the specified signal is outside a prespecified range, a detection signal indicating that an oscillating state of the specified signal does not satisfy prespecified requirements; and a signal switch which switches the specified signal or the comparison signal outputted from the phase comparing unit to a signal for maintaining an internal oscillation signal according to this detection signal. According to one feature of the present invention, a semiconductor integrated circuit in addition has a oscillating state detector comprising a counter for counting a pulse number of the specified signal during a specified period of time according to an external clock (clock 1) or a number of external clocks during a specified period of time according to the specified signal, and a condition comparing unit for comparing a pulse number or a pulse number of the clock 1 counted by the counter to a comparison object value indicating the prespecified range for a frequency of the specified signal and outputting a condition comparison signal, and also the specified detector outputs the detection signal according to the condition comparison signal. According to one feature of the present invention, a semiconductor integrated circuit in addition has a voltage control oscillator internally provided therein as one of the components to form a PLL (Phase-Locked Loop). With the above invention, the voltage control oscillator is internally provided therein, and a function as the PLL circuit for controlling the voltage control oscillator is effected by a control voltage generated according to the comparison signal outputted from the phase comparing unit, so that an external circuit for functioning as the PLL circuit is reduced, which allows an operation of the PLL by one chip and minimization of the PLL circuit to be achieved. Other objects and features of this invention will become apparent from the following description with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a block diagram showing schematic configuration of the PLL circuit based on the conventional technology. Fig. 2 is a block diagram showing schematic configuration of the semiconductor integrated circuit according to Embodiment 1 of the present invention. Fig. 3 is a block diagram showing internal configuration of the carrier detector in the semiconductor integrated circuit according to Embodiment 1. Fig. 4 is an explanatory view showing circuit configuration of the comparator in the semiconductor integrated circuit according to Embodiment 1. Fig. 5 is a truth table showing a relation among (A1, A0), (B1, B0), and each output signal in the terminals OS, OE, and OG in the semiconductor integrated circuit according to Embodiment 1. Fig. 6 is a time chart for explaining the operation of the carrier detector in the semiconductor integrated circuit according to Embodiment 1. Fig. 7 is a block diagram showing schematic configuration of another carrier detector in the semiconductor integrated circuit according to Embodiment 1. Fig. 8 is a time chart for explaining an operation of another carrier detector in the semiconductor integrated circuit according to Embodiment 1, and Fig. 9 is a block diagram showing another schematic configuration of the semiconductor integrated circuit according to Embodiment 1. DESCRIPTION OF THE PREFERRED EMBODIMENTS Detailed description is made for a preferred embodiment of the operational amplifier according to the present invention. It should be noted that this invention is not limited by these embodiment. Detailed description is made hereinafter for the preferred embodiments of the semiconductor integrated circuit according to the present invention with reference to the related drawings. It should be noted that, the present invention is not limited by these embodiments. Fig. 2 is a block diagram showing schematic configuration of a semiconductor integrated circuit according to Embodiment 1. In Fig. 2, the semiconductor integrated circuit according to Embodiment 1 comprises a signal switching circuit 10, a carrier detector 11, a phase comparator 12, a charge pump 13, a loop filter 14, a voltage control oscillator 15, and a 1/N divider 16. Herein, especially a case where the signal switching circuit 10, carrier detector 11, phase comparator 12, charge pump 13, loop filter 14, voltage control oscillator 15, and 1/N divider 16 are configured by a digital circuit is described, and this semiconductor integrated circuit functions as a PLL circuit for obtaining a synchronous signal to the carrier signal by inputting therein signals (carrier signal) for converting a carrier of, for instance, an FSK signal to square waves due to A/D conversion as an input signal. In Fig. 2, the signal switching circuit 10 is a circuit comprising a switch enabling switching of connection with a common contact 10a to either of a switching contact 10b or a switching contact 10c. In the signal switching circuit 10, the common contact 10a is connected to a terminal of the phase comparator 12 to which an input signal is inputted, the switching contact 10b connected to an external oscillator not shown receives the clock 2 and the switching contact 10c receives a carrier signal. The clock 2 is a clock signal that oscillates at a frequency equivalent to that of the carrier signal. As described above, the signal switching circuit 10 can select either of the clock 2 or the carrier signal as a signal to be inputted into the phase comparator 12. For example, when a detection signal outputted from the carrier detector 11 indicates a high level the common contact 10a is connected to the switching contact 10c in which the carrier signal is inputted, and when a detection signal outputted from the carrier detector 11 indicates a low level the common contact 10a is connected to the switching contact 10b in which the clock 2 is inputted. The phase comparator 12 comprises an EX-OR circuit or a R-S type of flip-flop circuit, and compares a timing of the rising point of a signal outputted from the signal switching circuit 10 (described a selected input signal hereinafter) to that of an oscillation signal (described an internal oscillation signal hereinafter) as a feedback signal to the voltage control oscillator 15 inputted through the 1/N divider 16, and when the rising of the internal oscillation signal is delayed with respect to the selected input signal, namely when a frequency of the selected input signal is lower than that of the internal oscillation signal, a signal UP at a low level is inputted into the charge pump 13 for that period of time. On the other hand, when the rising of the internal oscillation signal is leading with respect to the selected input signal, namely when a frequency of the selected input signal is higher than that of the internal oscillation signal, a signal DOWN at a high level is inputted into the charge pump 13 for that period of time. The charge pump 13 is a circuit for feeding a current for driving the loop filter 14 provided in the next stage, it feeds a positive current to the loop filter 14 provided in the next stage when the signal UP indicating a low level is received from the phase comparator 12, and feeds a negative current to the loop filter 14 provided in the next stage when the signal DOWN indicating a high level is received therefrom. The loop filter 14 is a low-pass filter which removes unnecessary higher harmonics and noise and also generates a positive or negative control voltage for controlling the voltage control oscillator 15 provided in the next stage according to the current supplied from the charge pump 13. The voltage control oscillator 15 is an oscillator for outputting a signal with a frequency decided according to the control voltage outputted from the charge pump 13, it can obtain this oscillation signal as a synchronous signal. Further, this oscillation signal is inputted into the 1/N divider 16. The 1/N divider 16 subjects the oscillation signal from the voltage control oscillator 15 to 1/N-division so that the frequency of the oscillation signal from the voltage control oscillator 15 coincides with the frequency of the selected input signal, and outputs the subjected signal as an internal oscillation signal. A negative feedback loop for receiving an output signal as an input signal is formed by inputting again this internal oscillation signal in the phase comparator 12. As described above, the semiconductor integrated circuit according to Embodiment 1 increases the frequency of the internal oscillation signal by feeding a positive voltage corresponding to the phase difference to the voltage control oscillator 15 as a control signal when the phase of an internal oscillation signal is delayed with respect to a selected input signal. Namely, a higher frequency can make the phase lead. On the other and, when the phase of the internal oscillation signal leads the selected input signal, the frequency of the internal oscillation signal is lowered by feeding a negative voltage corresponding to the difference to the voltage control oscillator 15 as a control signal. Namely a lower frequency can make the phase delayed. The locked state that the internal oscillation signal is coincident with the selected input signal in its frequency as well as phase thereof is effected by the action of the negative feedback as described above, which allows a synchronous signal accurately indicating a frequency of the selected input signal to be outputted. Next, description is made for the carrier detector 11. The carrier detector 11 is a circuit for receiving a carrier signal and a clock 1 generated in an external oscillator not shown in the figure, detecting whether the carrier signal is cut off or whether a carrier signal outside an effective range of a frequency is inputted, and outputting a detection signal, for example, as a low-level signal. Fig. 3 is a block diagram showing internal configuration of the carrier detector 11. In Fig. 3, the carrier detector 11 comprises a pulse generator 21, a counter 22, a register 23, comparators 24 and 25, a AND gate 26, a D flip-flop 27, and an inverter 28. The pulse generator 21 is a circuit for receiving a clock 1 and outputting a pulse with a smaller pulse width than that of the clock 1 on rising of the clock 1. The pulse generator 21 is realized by a device such as an one-shot multi-vibrator. The counter 22 is a circuit for receiving a carrier signal and counting a pulse number (Dn) of this carrier signal. The counter 22 is reset by the entry of a pulse outputted from the pulse generator 21. The register 23 is a circuit for receiving a clock 1, obtaining and storing theirin a value (Dn') indicating a counted result by the counter 22 on rising of the clock 1. The comparator 24 compares the value (Dn') stored in the register 23 to an upper limit of a recognizable frequency range as a normal carrier signal, namely a value (DH) indicating an effective highest frequency, and outputs a high-level signal as a result of comparison (a condition comparison signal) when Dn' is smaller than DH. On the other hand, the comparator 25 compares the value (Dn') stored in the register 23 to a lower limit of a recognizable frequency range as a normal carrier signal, namely a value (DL) indicating an effective lowest frequency, and outputs a high-level signal as a result of comparison (a condition comparison signal) when Dn' is larger than DL. The AND gate 26 receives the results of comparison outputted from the comparator 24 and comparator 25 respectively and inputs an output signal into a D terminal of the D flip-flop 27 provided in the next stage. Also the inverter 28 inputs a signal obtained by inverting the pulse outputted from the pulse generator 21 into a clock terminal of the D flip-flop 27. The D flip-flop 27 stores therein an output signal from the AND gate 26 when the signal outputted from the inverter 28 rises, and outputs the stored signal as a detection signal. Next, description is made for circuit configuration of the comparator 24. Fig. 4 is an explanatory view showing circuit configuration of the comparator 24. It should be noted that the comparator 24 shown in Fig. 4 is a circuit used when a result of comparison of entry value (Dn') expressed in 2 bits (A1, A0) with a value (DH) expressed in 2 bits (B1, B0) is outputted as an example. The comparator 24 can perform comparison even if Dn' and DH are values each expressed in 2 bits or more by being configured the same as the circuit shown in Fig. 4. In Fig. 4, the comparator 24 comprises two EXOR gates L11 and L12, four inverters L13 to L16, one AND gate L17, six OR gates L18 to L23, and two 3-entry AND gates L24 and L25, and of the gates, the OR gates L19, L20, L22, and L23 are 3-entry OR gates respectively. The comparator shown in Fig. 4 has three terminals OS, OE, and OG each for outputting a comparison result, and when it is determined that the value (Dn') expressed by (A1, A0) is larger than a value (DH) expressed by (B1, B0) as a result of comparison, a high-level signal is outputted to an output terminal OG, a high-level signal is outputted to an output terminal OS when it is determined that Dn' is smaller than DH, and a high-level signal is outputted to an output terminal OE when it is determined that Dn' is equal to DH. This comparator 24 processes a signal outputted especially from the terminal OS as a detection signal. In Fig. 4, the bit A0 is inputted into one of input terminals of the EXOR gate L11, input terminal of the inverter L13, one of input terminals of the OR gate L18, and into a first input terminal of the OR gate L19 respectively, while the bit A1 is inputted into one of input terminals of the EXOR gate L12, input terminal of the inverter L15, the second input terminal of the OR gate L19, and into a first input terminal of the OR gate L20 respectively. The bit B0 is inputted into the other input terminal of the EXOR gate L11, input terminal of the inverter L14, one of input terminals of the OR gate L21, and into the first input terminal of the OR gate L23 respectively, while the bit B1 is inputted into the other input terminal of the EXOR gate L12, input terminal of the inverter L16, the first input terminal of the OR gate L22, and into the second input terminal of the OR gate L23 respectively. Output from the EXOR gate L11 is inputted into one of input terminals of the AND gate L17, and output from the EXOR gate L12 is inputted into the other input terminal of the AND gate L17. Output terminal of the AND gate L17 is connected to the terminal OE. Output from the inverter L13 is inputted into the other input terminal of the OR gate L21 as well as in the second input terminal of the OR gate L22, while output from the inverter L14 is inputted into the other input terminal of the OR gate L18 as well as in the second input terminal of the OR gate L20 respectively. Output from the inverter L15 is inputted into the third input terminal of the OR gate L22 as well as in the third input terminal of the OR gate L23, while output from the inverter L16 is inputted into the third input terminal of the OR gate L19 as well as into the third input terminal of the OR gate L20 respectively. Each output from the OR gates L18 to L20 is inputted into the NAND gate L24, and each output from the OR gates L21 to L23 is inputted into the NAND gate L25. An output terminal of the NAND gate L24 is connected to the terminal OG and an output terminal of the NAND gate L25 is connected to the terminal OS. Next, description is made for an operation of the comparator 24. Fig. 5 is a truth table showing a relation between (A1, A0) indicating Dn', (B1, B0) indicating DH, and each output signal in the terminals OS, OE, and OG. It should be noted that, as a signal outputted from the terminal OS, a case where the terminal OS outputs a high-level signal and a case where it outputs a low-level signal are considered herein. As a combination of (A1, A0) with (B1, B0) when (A1, A0) indicating Dn' is smaller than (B1, B0) indicating DH, namely when the terminal OS outputs a high-level signal, there are six types of combinations such as {(A1, A0), (B1, B0)} = {(0, 0), (0, 1)}, {(0, 0), (1, 0)}, {(0, 1), (1, 0)}, {(0, 0), (1, 1)}, {(0, 1), (1, 1)}, and {(1, 0), (1, 1)}. Description is made for an operation of the comparator 24 in the case of {(A1, A0), (B1, B0)} = {(0, 0), (0, 1)} out of the above combinations, with reference to the circuit configuration shown in Fig. 4. At first, as values are equal such as (A0, B0) = (1, 0), the output from the EXOR gate L11 indicates a low level, namely logic "0". As values are equal such as (A1, B1) = (0, 1), the output from the EXOR gate L12 also indicates a low level, namely logic "0". Thus, the output from the AND gate L17 indicates logic "0", so that a low-level signal is outputted to the terminal OE. The outputs from the inverters L13 to L16 indicate logic "0", "1", "1", and "0" respectively. Accordingly, the logic "1", "1" is inputted into the OR gate L18, which outputs the logic "1", the logic "1", "0", "0" is inputted into the OR gate L19, which outputs the logic "1", and the logic "0", "1", "0" is inputted into the OR gate L20, which outputs the logic "1". Therefore, the output from the NAND gate L24 indicates the logic "0", and a low-level signal is outputted to the terminal OG. The same processing is subjected to each of the remaining five combinations of (A1, A0) with (B1, B0), and a low-level signal is outputted to the terminal OG. The logic "0", "0" is inputted into the OR gate L21, which outputs the logic "0", the logic "0", "1", "1" is inputted into the OR gate L22, which outputs the logic "1", and the logic "1", "0", "1" is inputted in the OR gate L23, which outputs the logic "1". Therefore, the output from the NAND gate L25 indicates the logic "1", and a high-level signal is outputted to the terminal OS. Namely, it is indicated that the value (Dn') expressed by (A1, A0) is smaller than the value (DH) expressed by (B1, B0). Other than the six combination of (A1, A0) with (B1, B0), namely when the value (Dn') expressed by (A1, A0) is larger than the value (DH) expressed by (B1, B0), a low-level signal is outputted to the output terminal OS. The comparator 25 has the same configuration and operation as those of the comparator 24 described above. It should be noted that, the comparator 25 outputs a high-level detection signal when Dn' is larger than DL in therefore, a terminal to which the detection signal is outputted should be the terminal OG. Next, description is made for an operation of the carrier detector 11. Fig. 6 is a time chart for explaining the operation of the carrier detector 11. In the time chart of Fig. 6, the reference signs a to i correspond to the positions a to i shown in Fig. 3, and show status of the signals on these positions respectively. In Fig. 6, at first, a pulse T21 is outputted from the pulse generator 21 with the rising T11 of a clock 1. Also, the register 23 obtains an output signal T31 indicating a value (Dn-1) as a result of counting in the counter 22 and stores the signal therein with the rising T11 of the clock 1. The counter 22 is reset by the pulse T21 outputted from the pulse generator 21, and new counting of clocks according to a carrier signal is started. A signal T41 indicating a value (Dn-1') stored in the register 23 is inputted into the comparators 24, 25, and it is determined whether the signal is within an effective range of a frequency or not. When it is determined that (Dn-1') is less than the value (DH) indicating the highest frequency, the comparator 24 outputs a signal T51 indicating a high level, on the other hand, when it is determined that (Dn-1') is greater than the value (DL) indicating the lowest frequency, the comparator 25 outputs a signal T61 indicating a high level. Therefore, the AND gate 26 receives two signals each indicating a high level and outputs a signal T71 indicating a high level. Herein, the pulse T21 outputted from the pulse generator 21 is inverted in the inverter 28 and inputted into a clock terminal of the D flip-flop 27, so that the D flip-flop 27 receives the signal T71 indicating a high level outputted from the AND gate 26 after a period of time equal to a pulse width of the pulse T21 and stores the signal therein. This stored signal is outputted as a detection signal T81 indicating a high level. Then, a pulse T22 is again outputted from the pulse generator 21 with the rising T12 of the clock 1. Also, the register 23 obtains an output signal T32 indicating a value (Dn) as a result of counting in the counter 22 with the rising T12 of the clock 1 and stores the signal therein. A signal T42 indicating a value (Dn') stored in the register 23 is inputted into the comparators 24, 25, and it is determined whether the signal is within an effective range of a frequency or not when it is determined that (Dn-1') is less than the value (DH) indicating the highest frequency in the comparator 24 as well as (Dn-1') is greater than the value (DL) indicating the lowest frequency in the comparator 25, both the comparators 24 and 25 output signals T51 and T61 each indicating a high level. Therefore, the AND gate 26 receives two signals each indicating a high level and outputs the signal T71 indicating a high level. Herein, as described above, the D flip-flop 27 receives the signal T71 indicating a high level outputted from the AND gate 26 after a period of time equal to a pulse width of the pulse T22, stores the signal therein, and outputs this stored signal indicating a high level as the detection signal T81. Then, when a carrier signal to be counted with the pulse T22 as a trigger is cut off with the pulse T2 which is the last one, namely in a state where a result of counting keeps on showing "1" in the counter after the rising T12 of the clock 1 and on, and further when the clock 1 shows a new rising T13, a pulse T23 is outputted from the pulse oscillator 21, "1" is stored in the register 23, and a signal T43 indicating this "1" is also inputted into the comparator 24 as well as in the comparator 25. The comparator 24 outputs a signal T51 indicating a high level because the value "1" inputted therein is less than the value DH indicating the highest frequency, but the comparator 25 outputs a signal T62 indicating a low level because the value "1" inputted therein is less than the value DL indicating the lowest frequency. In response to this output a signal T72 indicating a low level is also outputted from the AND gate 26. Then, the signal T72 indicating a low level outputted from the AND gate 26 is inputted and stored in the D flip-flop 27, after a period of time equal to a pulse width of the pulse T22 as described above, and a signal T82 indicating the stored low-level signal is outputted as a detection signal. Herein, the comparator 24 and comparator 25 are asynchronously operated, therefore, hazard HZ1 and HZ2 may occur at the time of transition from the high level to the low level of the signals in each output from the comparators as well as in the output from the AND gate 26 following the outputs. The D flip-flop 27 operates in synchronism with a clock signal according to a pulse outputted from the pulse oscillator 21, therefore, occurrence of hazard in the signal to be outputted is prevented. The time chart shown in Fig. 6 shows a case where a carrier signal is cut off, and if a frequency of the carrier signal is less than the value indicating the lowest frequency inputted into the comparator 25, the same operation is effected. Also even if the frequency of the carrier signal is more than the value indicating the highest frequency inputted into the comparator 24, a signal outputted from the comparator 24 indicates a low level and the AND gate 26 also outputs a signal indicating a low level, therefore the operation is resultantly the same as that described above. As described above, a detection signal outputted from the carrier detector 11 as explained above shows a low level when no carrier signal is inputted or when a carrier signal outside an effective range of a frequency is inputted. The signal switching circuit 10 connects, after receiving this low-level detection signal, the common contact 10a to the switching contact 10b to which a clock 2 is supplied, and selects the clock 2 as an input signal to be inputted into the phase comparator 12. The phase comparator 12 keeps, in order to maintain the locked state to the inputted clock 2, the locked state even when no carrier signal is inputted or a carrier signal outside an effective range of a frequency is inputted, and when an effective carrier signal is detected again in the carrier detector 11, namely when a high-level signal is inputted into the signal switching circuit 10 as a detection signal, the carrier signal is inputted into the phase comparator 12, and a synchronous signal can speedily be received by hardly generating a lock-up time. Next, description is made for another example of the carrier detector 11. Fig. 7 is a block diagram showing schematic configuration of another carrier detector 11. The carrier detector 11 shown in Fig. 7 is different from the carrier detector 11 shown in Fig. 3 in points that a clock 1 is inputted into the counter 22, a carrier signal is inputted into the pulse generator 21, and that a signal indicating an overflow in the counter 22 is inputted into a reset terminal (R) of the D flip-flop 27. However, oscillation frequency of the clock 1 is required to be sufficiently higher than that of the carrier signal. It should be noted that, the same reference numerals are assigned to sections common to those in Fig. 3, and description thereof is omitted herein. Fig. 8 is a time chart for explaining an operation of the carrier detector 11 shown in Fig. 7. In the time chart of Fig. 8, the reference signs a to j correspond to positions a to j shown in Fig. 7, and show states of signals in the positions respectively. In Fig. 8, at first, a pulse T21 is outputted from the pulse generator 21 with the rising T1 of a carrier signal. Also, the register 23 obtains an output signal T31 indicating a value (Dn-1) as a result of counting in the counter 22 and stores the signal therein with the rising T1 of the carrier signal. The counter 22 is reset by the pulse T21 outputted from the pulse generator 21 and new counting of the clock 1 is started. A signal T51 indicating a value (Dn-1') stored in the register 23 is inputted into the comparators 24 and 25, and it is determined whether the signal is within an effective range of a frequency or not. When it is determined that Dn-1' is less than the value (DH) indicating the highest frequency the comparator 24 outputs a signal T61 indicating a high level, on the other hand, when it is determined that Dn-1' is greater than the value (DL) indicating the lowest frequency the comparator 25 outputs a signal T71 indicating a high level. Therefore, the AND gate 26 receives two signals each indicating a high level, and outputs a signal T81 indicating a high level. Herein, the pulse T21 outputted from the pulse generator 21 is inverted in the inverter 28, and inputted into a clock terminal of the D flip-flop 27, so that the D flip-flop 27 receives the signal T71 indicating a high level outputted from the AND gate 26 after a period of time equal to a pulse width of the pulse T21 and stores the signal therein. This stored signal is outputted as a detection signal T91 indicating a high level. Then, a pulse T22 is again outputted from the pulse generator 21 with the rising T2 of the carrier signal. Also, the register 23 obtains an output signal T32 indicating a value (Dn) as a result of counting in the counter 22 with the rising T2 of this carrier and stores the signal therein. A signal T52 indicating a value (Dn') stored in the register 23 is inputted into the comparators 24 and 25, and it is determined whether the signal is within an effective range of a frequency or not. When it is determined that Dn-1' is less than the value (DH) indicating the highest frequency in the comparator 24 and that Dn-1' is greater than the value (DL) indicating the lowest frequency in the comparator 25, both the comparators 24 and 25 output signals T61 and T71 each indicating a high level. Therefore, the AND gate 26 receives two signals each indicating a high level, and outputs the signal T81 indicating a high level. Herein, as described above, the D flip-flop 27 receives the signal indicating a high level outputted from the AND gate 26 after a period of time equal to a pulse width of the pulse T22, stores the signal therein, and outputs this stored signal indicating a high level as the detection signal T91. Then, when a carrier signal is cut off with the pulse T22 indicating the rising T2 which is the last one, namely in a state where counting of the clock 1 is continued after the rising T2 of the carrier signal and on, a pulse from the pulse oscillator 21 according to the carrier signal is not outputted, hence the counter 22 will not be reset. In this state, as a pulse outputted from the pulse oscillator 21 is not inputted into the D flip-flop 27 as a clock input, hence the D flip-flop 27 maintains the high-level signal stored therein last time, hence a cut-off of the carrier signal can not be detected. However, the counting by the counter 22 results in an inevitable overflow, and then the counter 22 outputs an overflow signal (OVF) T41 indicating a high level, and the D flip-flop 27 receives this overflow signal T41 in the reset terminal thereof, so that the data (a high-level signal in this case) stored on the rising of the overflow signal T41 can be reset to a low level. With this feature, a detection signal T92 indicating a low level is outputted from the D flip-flop 27, which allows a cut-off of the carrier signal to be detected. Although the time chart shown in Fig. 8 shows especially the case where a carrier signal is cut off, the case where a frequency of a carrier signal is outside an effective range can be detected by the comparator 24 or the comparator 25. It should be noted that, the clock 1 is an object for counting by the counter 22, a pulse number of the clock 1 during the first transitional period of the pulse for the carrier signal is a result of counting by the counter 22 to be stored in the register 23. Namely, higher is the frequency of a carrier signal narrower is the rising interval of a pulse of a carrier signal, and smaller is the pulse number of the clock 1 to be counted during this interval. The lower is the frequency of a carrier signal, the wider is the rising interval of a pulse of a carrier signal, and larger is the pulse number of the clock 1 to be counted during this interval. Accordingly, the comparator 24 outputs a low-level signal when a counted result stored in the register 23 is smaller than the value indicating the highest frequency, namely than the pulse number (DH) of the clock 1 between pulses of the carrier signal with the highest frequency. On the other hand, the comparator 25 outputs a low-level signal when a counted result stored in the register 23 is larger than the value indicating the lowest frequency, namely than the pulse number (DH) of the clock 1 between pulses of the carrier signal with the lowest frequency. With those low-level signals, the AND gate 26 also outputs a signal indicating a low-level, therefore, the operation thereof results in the same as the operation in the carrier detector 11 shown in Fig. 3 as described above. With Embodiment 1 described above, when no carrier signal is inputted or when a carrier signal outside an effective range of a frequency is inputted by the carrier detector 11, a detection signal indicating a low level is outputted, and the signal switching circuit 10 inputs a clock 2 having a frequency equivalent to the normal carrier signal into the phase comparator 12 by receiving this detection signal indicating a low level, and inputs the carrier signal into the phase comparator 23 when the detection signal indicates a high level, so that, even when no carrier signal is inputted or when a carrier signal outside an effective range of a frequency is inputted, the locked state is not unlocked, and a lock-up time required when an effective carrier signal is detected again can be reduced, which allows high-speed as well as stable phase locking to be achieve. Fig. 9 is a block diagram showing another schematic configuration of the semiconductor integrated circuit according to Embodiment 1. Fig. 13 shows a state where a semiconductor integrated circuit 50 is obtained by integrating the configuration comprising the signal switching circuit 10, carrier detector 11, phase comparator 12, charge pump 13, and 1/N divider 16 into one chip, and where the loop filter 14 and voltage control oscillator 15 are connected to the semiconductor integrated circuit 50 as external circuits, while the configuration other than that described above is the same as the configuration shown in Fig. 2. As described above, the design can be changed as required depending on whether the configuration other than the configuration comprising the signal switching circuit 10, carrier detector 11, phase comparator 12, and charge pump 13 such as configuration with the loop filter 14 included in the semiconductor integrated circuit 50 and configuration with the 1/N divider 16 provided as an external circuit is to be included in the semiconductor integrated circuit according to the present invention for integrating into one chip or not. The semiconductor integrated circuit according to Embodiment 1 can function as a PLL circuit applied in radio equipment such as a portable telephone, an automobile telephone, and a cordless telephone; tuning to a frequency, a detector, data reproduction, and clock reproduction in a modem for wire or wireless modem; or a frequency synthesizer and a motor speed controller or the like, and the phase comparator 12 can be selected as a mixer type of phase comparator, a digital system of phase comparator, or a phase frequency comparator for designing as required; the loop filter 14 as an active loop filter; and the voltage control oscillator 15 as an emitter-linked multi-vibrator, a voltage control oscillator with configuration of CMOS, or a voltage control oscillator using an operation amplifier each according to any of those object devices. As described above, with the present invention, even when a specified signal is not detected or when an input signal outside a specified range of a frequency is inputted, a signal for maintaining oscillation and output of a synchronous signal (internal oscillation signal) is replaced and can be inputted into a voltage control oscillator, and when an effective signal is inputted again, a high-speed locking operation can be preformed and a synchronous signal can speedily be obtained as compared to the case where a feedback loop operation is started from the state in which an internal oscillation signal is not outputted from the voltage control oscillator, namely from the state in which there is no feedback signal therein. This application is based on Japanese patent application No. HEI 10-345970 filed in the Japanese Patent Office on December 4, 1998, the entire contents of which are hereby incorporated by reference. Although the invention has been described with respect to a specific embodiment for a complete and clear disclosure, the appended claims are not to be thus limited but are to be construed as embodying all modifications and alternative constructions that may occur to one skilled in the art which fairly fall within the basic teaching herein set forth.

Claims: A semiconductor integrated circuit comprising: a voltage control oscillator (15) for outputting a synchronous signal based on a specified signal; a phase comparing unit (12) for receiving the specified signal and a feedback signal outputted from said voltage control oscillator (15), comparing the phase of the specified signal to that of the feedback signal, and outputting a comparison signal indicating a result of comparison to said voltage control oscillator (15): a charge pump (13) for receiving the comparison signal from the phase comparing unit (12), the charge pump (13) outputting positive or negative charges according to a level of the comparison signal, and an oscillating state detector (11) for detecting an oscillating state of the specified signal, characterized in that the oscillating state detector (11) has a first input terminal for inputting the specified signal and a second input terminal for inputting a first clock signal, and detects the oscillating state based on a comparison of the specified signal and the first clock signal, the semiconductor integrated circuit further comprises a signal switch (10) having a first input terminal (10b) for inputting a second clock signal, a second input terminal (10c) for inputting the specified signal, and an output terminal (10a) connected to the phase comparing unit for switching the specified signal to a the second clock signal for maintaining oscillation of the voltage control oscillator and output of the synchronous signal from said voltage ontrol oscillator (15) according to the oscillating state detected by said oscillating state detector (11), and that the phase comparing unit (12), the charge pump (13), and voltage control oscillator (15) are commonly used for the specified signal and the second clock signal. A semiconductor integrated circuit according to claim 1, wherein said oscillating state detector checks the presence of the specified signal and/or a frequency of the specified signal and when the specified signal is not inputted or when the frequency of the specified signal is out of a prespecified range outputs a detection signal indicating that an oscillating state of the specified signal does not satisfy the prespecified requirements; and said signal switch switches the specified signal according to the detection signal outputted from said oscillating detector. A semiconductor integrated circuit according to the claim 2, wherein said oscillating state detector comprises: a counter for counting a pulse number of the specified signal during a specified period of time according to an external clock or a number of external clocks during a specified period of time according to the specified signal; and a condition comparing unit for comparing a pulse number or an external clock number counted by said counter to a comparison object value indicating the prespecified range for a frequency of the prespecified signal and outputting a condition comparison signal; wherein said oscillating state detector outputs the detection signal according to the condition comparison signal. A semiconductor integrated circuit according to the claim 1, wherein said voltage control oscillator is internally provided therein to form a PLL (Phase-Locked Loop).

Inventors: GOTOH KUNIHIKO, SEGAWA YUJI, GOTOH, KUNIHIKO, SEGAWA, YUJI, Gotoh, Kunihiko, c/o Fujitsu Limited, Segawa, Yuji, c/o Fujitsu limited
Applicants: FUJITSU LTD, FUJITSU LIMITED
Application year: 1999
Main classification: H03L7
IPC codes: H03L7