A SYNCHRONOUS FLYBACK CONVERTER

Abstract: In a continuous mode flyback converter having a synchronous switch (Q2) the drive pulse to the switch (Q2) on the secondary side is generated by an inverting buffer circuit being fed from the output voltage terminal. By using such an arrangement several advantages are obtained. Hence, the pulse generating circuit arrangement generates a drive signal to the synchronous switch which is independent of the input voltage and the drive losses can thereby be minimized.

Description: A SYNCHRONOUS FLYBACK CONVERTER TECHNICAL FIELD The present invention relates to a DC-DC converter circuit, and in particular to a synchronous flyback converter circuit for operation in a continuous mode. BACKGROUND OF THE INVENTION AND PRIOR ART In DC-DC power supply of different kinds of electrical devices, power rectifiers are utilized in order to output a correct rectified output voltage. Typically a diode would be employed on the secondary side in order to obtain the rectified output voltage . One way of obtaining a suitable rectifier circuit is to use flyback topology. In a flyback topology a primary side stores magnetic energy in a magnetisable core or the like during a charging interval . The energy is then fed to a secondary side during the so called flyback interval . The main advantage of a power rectifier circuit having a flyback topology compared to other rectifier circuits is its simple construction, which makes it cheap to manufacture. Furthermore, flyback converters can be divided into two different kinds: - continuous mode flyback converters, and - discontinuous mode flyback converters . In a continuous mode flyback converter the magnetic energy never drops to zero so that energy is continuously flowing either in or out of the core of the transformer, whereas in a discontinuous mode, intervals when energy is neither flowing in nor out of the core of the transformer occurs. A conventional flyback converter comprises, on the primary side, a primary winding of a transformer and a switch, and on the secondary side a secondary winding of the transformer connected to a diode and an output capacitor over which a load can be connected. Such a converter has a large voltage drop over the diode. Thus, in the case when the output voltage over the output capacitor is low, the voltage drop over the diode becomes a significant part of the overall voltage, which makes the power converter inefficient for such low voltage applications. In order to solve this problem a FET transistor, which has a much lower voltage drop can be used on the secondary side . Such an arrangement will reduce the losses on the secondary side . The FET transistor can for example be directly connected to an auxiliary winding arranged in series with the secondary winding of the transformer. A converter designed according to these principles is for example described in the co-pending Swedish patent application No. 9801595-1. However, in such driving structures, where an auxiliary winding is used, the gate amplitude of the FET on the secondary side will depend on the input voltage, i.e. the voltage applied to the primary side. This will cause excessive drive losses, since the drive amplitude must be designed for the lowest input voltage in such a case. This is particularly a problem in applications where a large input voltage range is desired. Furthermore, other DC-DC converters according to the state of the art are described in WO 98/04028 and in WO 95/02918. Also, in the US patent No. 5,719,755 a DC-DC converter is described. SUMMARY It is an object of the present invention to overcome the problems as outlined above and to provide a continuous mode flyback converter which has a simple construction, and yet being efficient compared to the converters according to the prior art, and which particularly well suited for a large input voltage range . This object and others are obtained by the power converters as set out in the appended claims . Thus, a drive pulse is generated by an inverting buffer circuit, which is fed from the output voltage. By using such a pulse generating circuit, the drive signal to the synchronous switch becomes independent of the input voltage and the drive losses can thereby be minimized. BRIEF DESCRIPTION OF THE DRAWINGS The present invention will now be described in more detail by way of non-limiting examples and with reference to the accompanying drawings, in which: - Fig. 1 is a circuit diagram of a continuous mode DC-DC converter . - Figs. 2a - 2c are timing diagrams. DESCRIPTION OF PREFERRED EMBODIMENTS In Fig. 1 a DC-DC converter is shown. The power converter comprises, on the primary side, a primary winding 101 and a switch 103. The primary winding is supplied with power from a DC voltage source 105. The switch can for example be an n-channel MOSFET transistor Ql as shown in the figure. The drain terminal of the transistor Ql is connected to a first terminal of the primary winding 101 and the source is connected to the low voltage input terminal of the voltage source 105. The switch is controlled by a control device (not shown) connected to the gate of the transistor Ql, and is arranged to switch the transistor Ql on and off at desired times . The control device can for example collect control data from the output terminals of the secondary side of the converter. The DC-voltage source 105 can in turn be connected to an AC- voltage supply (not shown) via a rectifying circuit. The primary side feeds a secondary side with energy via a transformer M2. The secondary side comprises a secondary winding 109 having an opposite winding direction than the winding on the primary side. A first terminal 111 of the winding 109 is connected to a first terminal 113 of a resistor Rl, the emitter 115 of a PNP transistor Q3 , and to a first terminal 117 of an output capacitor CO . The second terminal 119 of the resistor Rl is connected to a first terminal 121 of a resistor R2 , the second terminal 123 of which is connected to the second terminal 125 of the winding 109. The base 127 of the transistor Q3 is connected to a point 129 between the second terminal 119 of the resistor Rl and the first terminal 121 of the resistor R2. The collector 131 of the transistor Q3 is connected to the collector 133 of a NPN transistor Q4. The base 135 of the transistor Q4 is in a preferred embodiment connected to the second terminal 125 of the winding 109 via a resistor R3 and a capacitor Cl connected in series. The emitter 137 of the transistor Q4 is connected to the second terminal 139 of the capacitor CO and to the source 141 of a FET transistor Q2. The gate 143 of the transistor Q2 is connected to a point 145 between the collector terminals of the transistors Q3 and Q4. The drain of the transistor Q2 is connected to the second terminal 125 of the winding 109. A load ZL can be connected between the terminals of the output capacitor CO. In operation, during the on-time of Ql, i.e. when the control device makes the MOSFET transistor conducting, energy is stored in the core of the transformer M2. Due to the winding direction a positive voltage will appear at the drain terminal of the transistor Q2. The transistor Q4 will at the same time be conducting and the transistor Q2 will therefore be switched off. When the transistor Ql is turned off by the control device, the polarity in the windings of the transformer M2 are reversed due to the energy stored in the core of the transformer M2. The reversed polarities will cause a negative voltage to appear at the drain terminal of the transistor Q2. Via the voltage divider provided by the resistors Rl and R2 , the reversed polarity on the secondary side will cause the transistor Q3 to conduct . When the transistor Q3 starts to conduct the gate terminal 143 of the transistor Q2 goes high and the transistor Q2 starts to conduct . The capacitor Cl and the resistor R3 are provided so that the turn off and turn on times for the transistor Q3 will be low. In Figs 2a - 2c, the timing of the circuit shown in Fig 1 is illustrated. Thus, in Fig. 2c the voltage appearing at the gate of the transistor Ql is shown. In Fig. 2b, the voltage appearing between the terminals of the secondary winding of the transformer M2 at the corresponding time is shown. In Fig. 2c the voltage appearing between the gate and source terminals of the transistor Q2 at the corresponding time is shown. Thus, by providing an arrangement where a drive pulse to the FET transistor on the secondary side is generated by an inverting buffer circuit being fed from the output voltage terminal several advantages are obtained. Hence, the pulse generating circuit arrangement generates a drive signal to the synchronous switch which is independent of the input voltage and the drive losses can thereby be minimized. Furthermore, no auxiliary winding on the secondary side is required as in the co-pending Swedish patent application No. 9801595-1, which can be an advantage in some applications. The invention is not limited to the implementation described in conjunction with Figs. 1, 2a, 2b and 2c, but can easily be modified without deviating from the scope of the appended claims .

Claims: CLAIMS 1. A continuous mode flyback converter having a primary and a secondary side, the secondary side comprising a synchronous switch (Q2), having an arrangement operating in response to the output voltage of the converter arranged to control the synchronous switch, characterized in that the arrangement for controlling the switch comprises a PNP transistor (Q3) , the emitter of which is connected to a first output terminal (117) of the converter and an NPN transistor (Q4) , the emitter of which is connected to a second output terminal (139) of the converter and the collector of the transistor (Q4) being connected to a control input terminal (143) of the switch (Q2) . 2. A converter according to claim 1, characterized in that base terminal (127) of the transistor (Q3) is fed from the terminals of the secondary side via a voltage divider circuit (Rl, R2) . 3. A converter according to claim 2, characterized in that the voltage divider circuit comprises two resistors (Rl and R2) connected in series . 4. A converter according to any of claims 1 - 3, characterized in that base terminal (135) of the transistor (Q4) is fed from a terminal (125) of the secondary side. 5. A converter according to claim 4 , characterized in that the that the base terminal (135) of the transistor (Q4) is connected to the terminal (125) of the secondary side via a circuit comprising a resistor (R3) and a capacitor (Cl) connected in series . 6. A converter according to any of claims 1 - 5, characterized in that switch (Q2) is a FET transistor, in particular a MOSFET transistor.

Inventors: HEDENSKOG BO, SVAERDSJOE CLAES, HEDENSKOG, BO, SVAERDSJOE, CLAES
Applicants: ERICSSON TELEFON AB L M, HEDENSKOG BO, SVAERDSJOE CLAES, HEDENSKOG, BO, SVAERDSJOE, CLAES, TELEFONAKTIEBOLAGET LM ERICSSON (PUBL)
Application year: 1999
Main classification: H02M3
IPC codes: H02M3, H02M7